SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1997
6/97
The MC74LVX245 is an advanced high speed CMOS octal bus
transceiver.
It is intended for two–way asynchronous communication between data
buses. The direction of data transmission is determined by the level of the
T/R
input. The output enable pin (OE) can be used to disable the device,
so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static discharge.
• High Speed: t
PD
= 4.7ns (Typ) at VCC = 3.3V
• Low Power Dissipation: I
CC
= 4µA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: V
OLP
= 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
APPLICATION NOTES
1. Do not force a signal on an I/O pin when it is an active output, damage may
occur.
2. All floating (high impedence) input or I/O pins must be fixed by means of
pull up or pull down resistors or bus terminator ICs.
3. A parasitic diode is formed between the bus and VCC terminals. Therefore,
the LVX245 cannot be used to interface 5V to 3V systems directly.
Figure 1. 20–Lead Pinout (Top View)
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
OE
B0 B1 B2 B3 B4 B5 B6 B7
T/R
A0 A1 A2 A3 A4 A5 A6 A7 GND
LVX
LOW–VOLTAGE CMOS
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
PIN NAMES
Function
Output Enable Input
Transmit/Receive Input
Side A 3–State Inputs or 3–State
Outputs
Side B 3–State Inputs or 3–State
Outputs
Pins
OE
T/R
A0–A7
B0–B7