MOTOROLA MC10E155, MC100E155 Technical data
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 3
Motorola, Inc. 1996
5/95
The MC10E/100E155 contains six 2:1 multiplexers followed by
transparent latches with single-ended outputs. When both Latch Enables
(LEN1, LEN2) are LOW, the latch is transparent, and output data is
controlled by the multiplexer select control, SEL. A logic HIGH on either
LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR)
overrides all other controls to set the Q outputs LOW.
• 850ps Max. LEN to Output
• 825ps Max. D to Output
• Single-Ended Outputs
• Asynchronous Master Reset
• Dual Latch-Enables
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
D5a
D5b
LEN1
LEN2
V
EE
MR
SEL
D0a
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
5
Q
4
V
CC
Q
3
Q
2
V
CCO
Q
1
D0b D1a D2a V
CCOQ0
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
PIN NAMES
Pin Function
D0a – D
04
Input Data a
D0b – D4b Input Data b
SEL Data Select Input
LEN1, LEN2 Latch Enables
MR Master Reset
Q0– Q
4
Outputs
TRUTH TABLE
SEL Data
H
L
a
b
6-BIT 2:1
MUX-LATCH
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
SEL
LEN1
LEN2
MR
Q
0
Q
1
Q
2
Q
3
Q
4
D
Q
EN
R
D
Q
EN
R
D
Q
EN
R
D
Q
EN
R
D
Q
EN
R
D5a
D5b
Q
5
D
Q
EN
R
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
V
NCD3aD3bD4aD4b
CCO
D1b D2b
MC10E155 MC100E155
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 85 102 85 102 85 102
100E 85 102 85 102 98 117
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
t
PLH
Propagation Delay to Output ps
t
PHL
D 325 500 700 325 500 700 325 500 700
SEL 475 675 925 475 675 925 475 675 925
LEN 350 500 750 350 500 750 350 500 750
MR 450 600 850 450 600 850 450 600 850
t
s
Setup Time ps
D 300 100 300 100 300 100
SEL 500 250 500 250 500 250
t
h
Hold TIme ps
D 300 –100 300 –100 300 –100
SEL 0 – 250 0 – 250 0 – 250
t
RR
Reset Recovery Time 800 650 800 650 800 650 ps
t
PW
Minimum Pulse Width ps
MR 400 400 400
t
SKEW
Within-Device Skew 75 75 75 ps 1
t
r
Rise/Fall Times ps
t
f
20 - 80% 300 450 800 300 450 800 300 450 800
1. Within-device skew is defined as identical transitions on similar paths through a device.
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