MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The 7560 group is the 8-bit microcomputer based on the 740 family core technology.
The 7560 group has the LCD drive control circuit, an 8-channel A- D/D-A converter, UART and PWM as additional functions.
The various microcomputers in the 7560 group include variations of internal memory size and packaging. For details, refer to the section on part numbering.
For details on availability of microcomputers in the 7560 Group, refer the section on group expansion.
FEATURES |
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• Basic machine-language instructions ....................................... |
71 |
• The minimum instruction execution time ............................ |
0.5 s |
(at 8 MHz oscillation frequency) |
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• Memory size |
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ROM ................................................................ |
32 K to 60 K bytes |
RAM ............................................................... |
1024 to 2560 bytes |
• Programmable input/output ports ............................................. |
55 |
• Software pull-up resistors .................................................... |
Built-in |
• Output ports ................................................................................. |
8 |
• Input ports .................................................................................... |
1 |
•Interrupts .................................................. |
17 sources, 16 vectors |
(includes key input interrupt) |
• Timers ........................................................... |
8-bit 3, 16-bit 2 |
• Serial I/O1 ..................... |
8-bit 1 (UART or Clock-synchronous) |
• Serial I/O2 .................................... |
8-bit 1 (Clock-synchronous) |
• PWM output .................................................................... |
8-bit 1 |
• A-D converter .................................................. |
8-bit 8 channels |
• D-A converter .................................................. |
8-bit 2 channels |
• LCD drive control circuit |
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Bias ................................................................................... |
1/2, 1/3 |
Duty ............................................................................ |
1/2, 1/3, 1/4 |
Common output .......................................................................... |
4 |
Segment output ......................................................................... |
40 |
•2 Clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
• Watchdog timer ............................................................. |
14-bit 1 |
• Power source voltage ................................................ |
2.2 to 5.5 V |
• Power dissipation |
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In high-speed mode ........................................................... |
40 mW |
(at 8 MHz oscillation frequency, at 5 V power source voltage) |
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In low-speed mode .............................................................. |
60 W |
(at 32 kHz oscillation frequency, at 3 V power source voltage) |
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• Operating temperature range ................................... |
– 20 to 85°C |
Camera, household appliances, consumer electronics, etc.
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SEG10 |
SEG11 |
SEG12 |
SEG13 |
SEG14 |
SEG15 |
SEG16 |
SEG17 |
P30/SEG18 |
P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 |
P10/SEG34 |
P11/SEG35 P12/SEG36 P13/SEG37 |
P14/SEG38 |
P15/SEG39 |
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80 |
79 |
78 |
77 |
76 |
75 |
74 |
73 |
72 |
71 |
70 |
69 |
68 |
67 |
66 |
65 |
64 |
63 |
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62 |
61 |
60 |
59 |
58 57 |
56 |
55 |
54 |
53 |
52 |
51 |
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SEG9 |
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81 |
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50 |
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P16 |
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SEG8 |
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82 |
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49 |
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P17 |
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SEG7 |
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83 |
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48 |
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P20 |
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SEG6 |
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84 |
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47 |
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P21 |
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SEG5 |
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85 |
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46 |
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P22 |
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SEG4 |
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86 |
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45 |
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P23 |
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SEG3 |
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87 |
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44 |
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P24 |
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SEG2 |
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88 |
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43 |
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P25 |
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SEG1 |
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89 |
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M37560MF-XXXFP |
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42 |
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P26 |
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VCC |
91 |
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40 |
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VSS |
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SEG0 |
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90 |
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41 |
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P27 |
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VREF |
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92 |
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39 |
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XOUT |
||||||
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|
||||||||||||
AVSS |
|
|
93 |
|
|
|
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|
38 |
|
|
|
XIN |
|||||||
COM3 |
|
|
|
|
94 |
|
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|
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37 |
|
|
|
XCOUT |
|||||
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|
||||||||
COM2 |
|
|
|
|
95 |
|
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36 |
|
|
|
XCIN |
|||||
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|
||||||||
COM1 |
|
|
|
|
96 |
|
|
|
|
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|
35 |
|
|
|
|
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|
|||
|
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|
|
|
|
|
|
|
|
RESET |
||||||
COM0 |
|
|
|
97 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
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|
|
|
|
|
|
|
34 |
|
|
|
|
P70/INT0 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
|||||||||||
VL3 |
|
|
|
98 |
|
|
|
|
|
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|
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|
|
|
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|
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|
33 |
|
|
|
|
P71 |
|||||
|
|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
VL2 |
|
|
99 |
|
|
|
|
|
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|
|
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|
32 |
|
|
|
|
P72 |
||||||
|
|
|
|
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|
|
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|
|
|
|
|
||||||||||||
C2 |
|
|
100 |
|
|
|
|
|
|
|
|
|
|
|
|
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|
31 |
|
|
|
|
P73 |
||||||
|
|
|
|
|
|
|
|
|
1 |
|
2 |
|
3 |
|
4 |
|
5 |
|
6 |
|
7 |
|
8 |
|
9 |
|
|
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
|
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
|
|
|
|
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|
|
||||||||||||||||||||||||||||||||||
|
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|||||||
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|
P60/SIN2/AN0 P57/ADT/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 |
|
P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/φ /TOUT P42/INT2 |
P41/INT1 |
|
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|
||||||||||||||||||||||||||||||||||||||||||
|
|
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|
|
C1 |
VL1 |
P67/AN7 |
P66/AN6 |
P65/AN5 |
P64/AN4 |
P63/SCLK22/AN3 |
P62/SCLK21/AN2 |
P61/SOUT2/AN1 |
|
P40 P77 P76 |
P75 |
P74 |
|
|
|
|
|
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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|
Package type : 100P6S-A
Fig. 1 Pin configuration of M37560MF-XXXFP
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
|
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SEG13 |
|
SEG14 |
|
SEG15 |
|
SEG16 |
|
SEG17 |
|
P30/SEG18 |
|
P31/SEG19 |
|
P32/SEG20 |
|
P33/SEG21 |
|
P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 |
|
P10/SEG34 P11/SEG35 P12/SEG36 |
|
P13/SEG37 |
|
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||||||||||||||||||||||||||||||||||||||||||||
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|
75 |
74 |
73 |
72 |
71 |
70 |
69 |
68 |
67 |
66 |
65 |
64 |
63 |
62 |
61 |
60 |
|
|
|
59 |
58 |
57 |
56 |
55 |
54 |
53 |
52 |
51 |
|
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|
|
|||||||||||||||||||||||||||||||||||||||
SEG12 |
|
|
76 |
|
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|
50 |
|
|
|
|
P14/SEG38 |
|||||||||
|
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||||||||||||||
SEG11 |
|
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|
||||||
|
|
77 |
|
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49 |
|
|
|
|
P15/SEG39 |
||||||||||
SEG10 |
|
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P16 |
||||||||
|
|
78 |
|
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48 |
|
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|
|||||||||||
SEG9 |
|
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P17 |
||||||||
|
|
79 |
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
47 |
|
|
|
|
|||||||||||
SEG8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P20 |
||||||||
|
|
80 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
46 |
|
|
|
|
|||||||||||
SEG7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P21 |
||||||||
|
|
81 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
45 |
|
|
|
|
|||||||||||
SEG6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P22 |
||||||||
|
|
82 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
44 |
|
|
|
|
|||||||||||
SEG5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P23 |
||||||||
|
|
83 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
43 |
|
|
|
|
|||||||||||
SEG4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P24 |
||||||||
|
|
84 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
42 |
|
|
|
|
|||||||||||
SEG3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P25 |
||||||||
|
|
85 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
41 |
|
|
|
|
|||||||||||
SEG2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P26 |
||||||||
|
|
86 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
40 |
|
|
|
|
|||||||||||
SEG1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P27 |
||||||||
|
|
87 |
|
|
|
|
|
|
|
|
|
M37560MF-XXXGP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
39 |
|
|
|
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
XOUT |
||||||||||||||||||||||||||||||||||||||||||||||
VCC |
|
|
89 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
37 |
|
|
|
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||
SEG0 |
|
|
88 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
38 |
|
|
|
|
VSS |
|||||||||
VREF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
XIN |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
90 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
36 |
|
|
|
|
||||||||||
AVSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
XCOUT |
||||||||
|
|
|
91 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
35 |
|
|
|
|
||||||||||
COM3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
XCIN |
||||||||
|
|
|
92 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
34 |
|
|
|
|
||||||||||
COM2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
93 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
33 |
|
|
|
|
RESET |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
COM1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P70/INT0 |
||||||||
|
|
|
94 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
32 |
|
|
|
|
||||||||||
COM0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P71 |
||||||
|
|
|
|
|
95 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
31 |
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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VL3 |
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P72 |
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96 |
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30 |
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P73 |
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VL2 |
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97 |
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29 |
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C2 |
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P74 |
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98 |
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28 |
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C1 |
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P75 |
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99 |
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27 |
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P76 |
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VL1 |
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100 |
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26 |
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1 |
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2 |
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3 |
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4 |
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5 |
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7 |
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8 |
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9 |
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10 |
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11 |
12 |
13 |
14 |
15 |
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16 |
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17 |
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18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
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P67/AN7 |
P66/AN6 |
P65/AN5 |
P64/AN4 |
P63/SCLK22/AN3 |
P62/SCLK21/AN2 |
P61/SOUT2/AN1 |
P60/SIN2/AN0 |
P57/ADT/DA2 |
P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 |
|
P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/φ /TOUT |
P42/INT2 P41/INT1 P40 |
P77 |
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Package type : 100P6Q-A
Fig. 2 Pin configuration of M37560MF-XXXGP
2
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)
( 5 V ) ( 0 V )
Reset input
Clock |
output |
Clock |
input |
VSS
VCC
RESET
XOUT
XIN
VL1 |
C1 |
C2 |
VL2 |
VL3 |
2 |
1 |
100 |
99 |
98 |
40
Data bus
91
35
38 39 |
Clockgenerating circuit |
COM0 |
COM1 |
COM2 |
COM3 |
SEG0 |
SEG1 |
SEG2 |
SEG3 |
SEG4 |
SEG5 |
SEG6 |
SEG7 |
SEG8 |
SEG9 |
SEG10 |
SEG11 |
SEG12 |
SEG13 |
SEG14 |
SEG15 |
SEG16 |
SEG17 |
|
|
97 |
96 |
95 |
94 |
90 |
89 |
88 |
87 |
86 |
85 |
84 |
83 |
82 |
81 |
80 |
79 |
78 |
77 |
76 |
75 |
74 |
73 |
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64 |
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P0(8) |
59 60 61 62 63 |
I/OportP0 |
LCD |
drivecontrol |
circuit |
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56 57 58 |
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5455 |
P1 |
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D-A1 |
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P1(8) |
49 50 51 52 53 |
I/Oport |
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yeKtupiney(K-noekawpu)tpurrenti |
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48 |
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LCDdisplay RAM (20bytes) |
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D-A2 |
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P2(8) |
41 42 43 44 45 46 47 |
I/OportP2 |
φ XCOUT
XCIN
(16) |
(16) |
Timer2(8) |
Timer3(8) |
TimerX |
TimerY |
1(8) |
|
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Timer |
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Reset |
|
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XCOUT Sub- |
clock output |
hdog |
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XCIN Sub- |
clock input |
Watc |
timer |
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laeRemittropnoitcnuf |
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72 |
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71 |
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70 |
TOUT |
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P3(8) |
|
66 67 68 69 |
SI/O1(8) |
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φ |
|
65 |
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26 |
||
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2TNI,1TNI |
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25 |
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24 |
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P4(8) |
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22 23 |
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21 |
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20 |
PWM(8) |
|
CNTR,CNTR01 |
|
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19 |
DA2 |
DA1 |
P5(8) |
|
14 15 16 17 18 |
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13 |
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12 |
(8) |
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11 |
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9392 |
|
converter |
|
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TDA |
|
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A-D |
|
SI/O2(8) |
|
|
10 |
|
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P6(8) |
|
6 7 8 9 |
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5 |
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4 |
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3 |
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0TNI |
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34 |
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33 |
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P7(8) |
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32 |
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29 30 31 |
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28 |
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27 |
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COUT |
|
37 |
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X |
CIN |
36 |
|
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X |
|
I/O port P4 Output port P3
|
I/OportP5 |
|
|
REF AVSS |
|
|
V |
|
|
I/OportP6 |
|
|
I/OportP7 |
|
XCOUT |
Sub-clock |
output |
XCIN |
Sub-clock |
input |
Fig. 3 Functional block diagram
3
|
|
|
|
|
MITSUBISHI MICROCOMPUTERS |
||
|
|
|
|
|
|
7560 Group |
|
|
|
|
|
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
|||
|
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|
|
PIN DESCRIPTION |
|
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|
||||
Table 1 Pin description (1) |
|
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||||
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Pin |
Name |
Function |
|
|
||
|
Function except a port function |
||||||
|
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||
|
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|
|
VCC, VSS |
Power source |
•Apply voltage of 2.2 V to 5.5 V to VCC, and 0 V to VSS. |
|
|
|||
|
|
|
|
|
|
|
|
VREF |
Analog refer- |
•Reference voltage input pin for A-D converter. |
|
|
|||
|
|
|
ence voltage |
|
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|
|
|
|
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|
|
|
|
|
AVSS |
Analog power |
•GND input pin for A-D converter. |
|
|
|||
|
|
|
source |
•Connect to VSS. |
|
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|
|
|
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||
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|
|
Reset input |
•Reset input pin for active “L”. |
|
|
|
RESET |
|
|
|||||
XIN |
Clock input |
•Input and output pins for the main clock generating circuit. |
|||||
|
|
|
|
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set |
|||
|
|
|
|
the oscillation frequency. |
|
|
|
XOUT |
Clock output |
|
|
||||
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. A |
|||||||
|
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|
||||
|
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|
|
feedback resistor is built-in. |
|
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|
|
VL1–VL3 |
LCD power |
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage. |
|
|
|||
|
|
|
source |
•Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.) |
|||
|
|
|
|
||||
|
|
|
|
|
|
||
C1, C2 |
Charge-pump |
•External capacitor pins for a voltage multiplier (3 times) of LCD contorl. |
|||||
|
|
|
capacitor pin |
|
|
|
|
|
|
|
|
|
|
|
|
COM0–COM3 |
Common output |
•LCD common output pins. |
|
|
|||
|
|
|
|
•COM2 and COM3 are not used at 1/2 duty ratio. |
|
|
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|
|
•COM3 is not used at 1/3 duty ratio. |
|
|
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|
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|
|
SEG0–SEG17 |
Segment output |
•LCD segment output pins. |
|
|
|||
|
|
|
|
|
|
|
|
P00/SEG26– |
I/O port P0 |
•8-bit I/O port. |
|
•LCD segment output pins |
|||
P07/SEG33 |
|
•CMOS compatible input level. |
|
|
|||
|
|
|
|
|
|
||
|
|
|
|
•CMOS 3-state output structure. |
|
|
|
|
|
|
|
•Pull-up control is enabled. |
|
|
|
|
|
|
|
•I/O direction register allows each 8-bit pin to be pro- |
|
|
|
|
|
|
|
grammed as either input or output. |
|
|
|
P10/SEG34– |
I/O port P1 |
•6-bit I/O port with same function as port P0. |
|
|
|||
P15/SEG39 |
|
•CMOS compatible input level. |
|
|
|||
|
|
|
|
|
|
||
|
|
|
|
•CMOS 3-state output structure. |
|
|
|
|
|
|
|
•Pull-up control is enabled. |
|
|
|
|
|
|
|
•I/O direction register allows each 6-bit pin to be pro- |
|
|
|
|
|
|
|
grammed as either input or output. |
|
|
|
|
|
|
|
|
|
|
|
P16, P17 |
|
•2-bit I/O port. |
|
|
|||
|
|
|
|
•CMOS compatible input level. |
|
|
|
|
|
|
|
•CMOS 3-state output structure. |
|
|
|
|
|
|
|
•I/O direction register allows each pin to be individually programmred as either input or output. |
|||
|
|
|
|
•Pull-up control is enabled. |
|
|
|
P20 – P27 |
I/O port P2 |
•8-bit I/O port with same function as P16 and P17. |
|
•Key input (key-on wake-up) interrupt |
|||
|
|
|
|
•CMOS compatible input level. |
|
input pins |
|
|
|
|
|
|
|
||
|
|
|
|
•CMOS 3-state output structure. |
|
|
|
|
|
|
|
•Pull-up control is enabled. |
|
|
|
P30/SEG18 – |
Output port P3 |
•8-bit output port with same function as port P0. |
|
•LCD segment output pins |
|||
P37/SEG25 |
|
•CMOS 3-state output structure. |
|
|
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•Port output control is enabled. |
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4
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MITSUBISHI MICROCOMPUTERS |
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7560 Group |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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Table 2 Pin description (2) |
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Pin |
Name |
Function |
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Function except a port function |
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P40 |
I/O port P4 |
•1-bit I/O port with same function as P16 and P17. |
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•CMOS compatible input level. |
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•N-channel open-drain output structure. |
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P41/INT1, |
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•7-bit I/O port with same function as P16 and P17. |
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•Interrupt input pins |
P42/INT2 |
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•CMOS compatible input level. |
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•CMOS 3-state output structure. |
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P43/φ /TOUT |
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•φ clock output pin |
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•Pull-up control is enabled. |
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•Timer 2 output pin |
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P44/RXD, |
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•Serial I/O1 I/O pins |
P45/TXD, |
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P46/SCLK1, |
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P47/SRDY1 |
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P50/PWM0, |
I/O port P5 |
•8-bit I/O port with same function as P16 and P17. |
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•PWM function pins |
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P51/PWM1 |
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•CMOS compatible input level. |
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•CMOS 3-state output structure. |
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P52/RTP0, |
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•Real time port function pins |
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P53/RTP1 |
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•Pull-up control is enabled. |
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P54/CNTR0, |
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•Timer X, Y function pins |
P55/CNTR1 |
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P56/DA1, |
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•D-A conversion output pins |
P57/ADT/DA2 |
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P60/AN0/SIN2, |
I/O port P6 |
•8-bit I/O port with same function as P16 and P17. |
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•A-D conversion input pins |
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P61/AN1/SOUT2, |
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•CMOS compatible input level. |
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•Serial I/O2 I/O pins |
P62/AN2/SCLK21, |
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•CMOS 3-state output structure. |
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P63/AN3/SCLK22 |
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•Pull-up control is enabled. |
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P64/AN4– |
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•A-D conversion input pins |
P67/AN7 |
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P70/INT0 |
Input port P7 |
•1-bit input port. |
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•Interrupt input pin |
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P71–P77 |
I/O port P7 |
•7-bit I/O port with same function as P16 and P17. |
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•CMOS compatible input level. |
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•N-channel open-drain output structure. |
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XCOUT |
Sub-clock output |
•Sub-clock generating circuit I/O pins. |
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XCIN |
Sub-clock input |
(Connect a resonator. External clock cannot be used.) |
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5
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Product |
M37560 M F – XXX FP |
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Package type |
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FP : 100P6S-A package |
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GP : 100P6Q-A package |
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ROM number |
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ROM/PROM size |
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1 |
: 4096 bytes |
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2 |
: 8192 bytes |
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3 |
: 12288 bytes |
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4 |
: 16384 bytes |
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5 |
: 20480 bytes |
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6 |
: 24576 bytes |
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7 |
: 28672 bytes |
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8 |
: 32768 bytes |
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9 |
: 36864 bytes |
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A : 40960 bytes |
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B : 45056 bytes |
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C : 49152 bytes |
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D : 53248 bytes |
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E : 57344 bytes |
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F : 61440 bytes |
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The first 128 bytes and the last 2 bytes of ROM |
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are reserved areas ; they cannot be used. |
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Memory type |
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M : Mask ROM version |
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Fig. 4 Part numbering |
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6
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION |
Packages |
Mitsubishi plans to expand the 7560 group as follows.
100P6Q-A |
.................................. 0.5 mm-pitch plastic molded QFP |
100P6S-A ................................ |
0.65 mm-pitch plastic molded QFP |
Memory Type
Support for mask ROM version.
Memory Size
ROM size ........................................................... |
32 K to 60 K bytes |
RAM size .......................................................... |
1024 to 2560 bytes |
Memory Expansion Plan
ROM size (bytes) |
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Under development |
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60K |
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M37560MF |
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56K |
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52K |
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48K |
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44K |
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40K |
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36K |
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Under development |
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32K |
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M37560M8 |
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28K |
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24K |
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20K |
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16K |
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12K |
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8K |
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4K |
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192 |
256 |
512 |
768 |
1024 |
1280 |
1536 |
1792 |
2048 |
2304 |
2560 |
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RAM size (bytes) |
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Fig. 5 Memory expansion plan
Currently products are listed below.
Table 3. List of products |
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As of Mar. 2001 |
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Product |
ROM size (bytes) |
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RAM size (bytes) |
Package |
Remarks |
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ROM size for User in ( |
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M37560M8-XXXFP |
32768 |
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1024 |
100P6S-A |
Mask ROM version |
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M37560M8-XXXGP |
(32638) |
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100P6Q-A |
Mask ROM version |
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M37560MF-XXXFP |
61440 |
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2560 |
100P6S-A |
Mask ROM version |
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M37560MF-XXXGP |
(61310) |
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100P6Q-A |
Mask ROM version |
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7
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 7560 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7.
Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
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b7 |
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b0 |
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A |
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Accumulator |
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b7 |
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b0 |
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X |
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Index register X |
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b7 |
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b0 |
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Y |
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Index register Y |
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Stack pointer |
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b15 |
b7 |
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PCH |
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PCL |
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Program counter |
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b7 |
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b0 |
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N |
V |
T |
B |
D |
I |
Z |
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Processor status register (PS) |
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Carry flag |
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Zero flag |
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Interrupt disable flag |
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Decimal mode flag |
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Break flag |
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Index X mode flag |
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Overflow flag |
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Negative flag |
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Fig. 6 740 Family CPU register structure |
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8
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request
(Note)
Execute JSR
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M (S) |
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(PCH) |
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Push return address |
(S) |
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(S) – 1 |
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on stack |
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M (S) |
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(PCL) |
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(S) |
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(S)– 1 |
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Subroutine
Execute RTS
(S) (S) + 1
POP return
address from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
M(S) (PCH)
(S)(S) – 1
M (S) (PCL)
(S) (S) – 1
M (S)(PS)
(S) (S) – 1
Interrupt
Service Routine
Execute RTI
Push return address on stack
Push contents of processor status register on stack
I Flag is set from “0” to “1” Fetch the jump vector
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(S) |
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(S) + 1 |
POP contents of |
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processor status |
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(PS) |
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M (S) |
register from stack |
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(S) |
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(S) + 1 |
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(PCL) |
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M (S) |
POP return |
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address |
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(S) |
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(S) + 1 |
from stack |
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(PCH) |
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M (S) |
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Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
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Push instruction to stack |
Pop instruction from stack |
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Accumulator |
PHA |
PLA |
Processor status register |
PHP |
PLP |
9
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MITSUBISHI MICROCOMPUTERS |
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7560 Group |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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[Processor status register (PS)] |
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• Bit 4: Break flag (B) |
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The processor status register is an 8-bit register consisting of 5 |
The B flag is used to indicate that the current interrupt was gen- |
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flags which indicate the status of the processor after an arithmetic |
erated by the BRK instruction. The BRK flag in the processor |
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operation and 3 flags which decide MCU operation. Branch opera- |
status register is always “0”. When the BRK instruction is used to |
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tions can be performed by testing the Carry (C) flag , Zero (Z) flag, |
generate an interrupt, the processor status register is pushed |
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Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, |
onto the stack with the break flag set to “1”. |
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V, N flags are not valid. |
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• Bit 5: Index X mode flag (T) |
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When the T flag is “0”, arithmetic operations are performed be- |
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• Bit 0: Carry flag (C) |
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tween accumulator and memory. When the T flag is “1”, direct |
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The C flag contains a carry or borrow generated by the arith- |
arithmetic operations and direct data transfers are enabled be- |
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metic logic unit (ALU) immediately after an arithmetic operation. |
tween memory locations. |
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It can also be changed by a shift or rotate instruction. |
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• Bit 6: Overflow flag (V) |
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• Bit 1: Zero flag (Z) |
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The V flag is used during the addition or subtraction of one byte |
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The Z flag is set if the result of an immediate arithmetic operation |
of signed data. It is set if the result exceeds +127 to -128. When |
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or a data transfer is “0”, and cleared if the result is anything other |
the BIT instruction is executed, bit 6 of the memory location op- |
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than “0”. |
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erated on by the BIT instruction is stored in the overflow flag. |
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• Bit 2: Interrupt disable flag (I) |
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• Bit 7: Negative flag (N) |
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The I flag disables all interrupts except for the interrupt gener- |
The N flag is set if the result of an arithmetic operation or data |
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ated by the BRK instruction. |
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transfer is negative. When the BIT instruction is executed, bit 7 |
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Interrupts are disabled when the I flag is “1”. |
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of the memory location operated on by the BIT instruction is |
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• Bit 3: Decimal mode flag (D) |
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stored in the negative flag. |
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The D flag determines whether additions and subtractions are |
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executed in binary or decimal. Binary arithmetic is executed |
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when this flag is “0”; decimal arithmetic is executed when it is |
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“1”. |
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Decimal correction is automatic in decimal mode. Only the ADC |
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and SBC instructions can be used for decimal aritmetic. |
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Table 5 Set and clear instructions of each bit of processor status register |
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C flag |
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Z flag |
I flag |
D flag |
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B flag |
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T flag |
V flag |
N flag |
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Set instruction |
SEC |
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– |
SEI |
SED |
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SET |
– |
– |
Clear instruction |
CLC |
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CLI |
CLD |
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– |
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CLT |
CLV |
– |
10
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7 |
b0 |
CPU mode register
(CPUM (CM) : address 003B16)
Processor mode bits
b1 b0 |
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0 |
0 |
: Single-chip mode |
0 |
1 |
: |
1 |
0 |
: Not available |
1 |
1 |
: |
Stack page selection bit |
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0 |
: 0 page |
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1 |
: 1 page |
Not used (returns “1” when read) (Do not write “0” to this bit)
Port XC switch bit
0 : Oscillation stop
1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode)
Fig. 8 Structure of CPU mode register
11
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
RAM area |
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RAM size |
Address |
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(bytes) |
XXXX16 |
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000016 |
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SFR area |
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192 |
00FF16 |
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256 |
013F16 |
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004016 |
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Zero page |
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LCD display RAM area |
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384 |
01BF16 |
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005416 |
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512 |
023F16 |
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010016 |
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640 |
02BF16 |
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RAM |
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768 |
033F16 |
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896 |
03BF16 |
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XXXX16 |
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1024 |
043F16 |
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1536 |
063F16 |
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Reserved area |
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2048 |
083F16 |
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2560 |
0A3F16 |
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044016 |
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ROM area |
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Not used (Note) |
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ROM size |
Address |
Address |
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YYYY16 |
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(bytes) |
YYYY16 |
ZZZZ16 |
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Reserved ROM area |
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(128 bytes) |
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4096 |
F00016 |
F08016 |
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8192 |
E00016 |
E08016 |
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ZZZZ16 |
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12288 |
D00016 |
D08016 |
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16384 |
C00016 |
C08016 |
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20480 |
B00016 |
B08016 |
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24576 |
A00016 |
A08016 |
ROM |
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28672 |
900016 |
908016 |
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FF0016 |
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32768 |
800016 |
808016 |
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36864 |
700016 |
708016 |
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FFDC16 |
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40960 |
600016 |
608016 |
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Interrupt vector area |
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Special page |
45056 |
500016 |
508016 |
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49152 |
400016 |
408016 |
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FFFE16 |
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53248 |
300016 |
308016 |
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Reserved ROM area |
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FFFF16 |
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57344 |
200016 |
208016 |
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61440 |
100016 |
108016 |
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Note: When RAM area exceeds 1024 bytes, the areas shown the table are used.
Fig. 9 Memory map diagram
12
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MITSUBISHI MICROCOMPUTERS |
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7560 Group |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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000016 |
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002016 |
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Port P0 (P0) |
Timer X (low) (TXL) |
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000116 |
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002116 |
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Port P0 direction register (P0D) |
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Timer X (high) (TXH) |
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000216 |
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002216 |
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Port P1 (P1) |
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Timer Y (low) (TYL) |
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000316 |
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002316 |
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Port P1 direction register (P1D) |
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Timer Y (high) (TYH) |
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000416 |
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002416 |
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Port P2 (P2) |
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Timer 1 (T1) |
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000516 |
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002516 |
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Port P2 direction register (P2D) |
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Timer 2 (T2) |
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000616 |
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002616 |
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Port P3 (P3) |
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Timer 3 (T3) |
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000716 |
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002716 |
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Port P3 output control register (P3C) |
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Timer X mode register (TXM) |
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000816 |
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002816 |
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Port P4 (P4) |
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Timer Y mode register (TYM) |
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000916 |
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002916 |
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Port P4 direction register (P4D) |
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Timer 123 mode register (T123M) |
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000A16 |
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002A16 |
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Port P5 (P5) |
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TOUT/φ output control register (CKOUT) |
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000B16 |
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002B16 |
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Port P5 direction register (P5D) |
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PWM control register (PWMCON) |
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000C16 |
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002C16 |
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Port P6 (P6) |
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PWM prescaler (PREPWM) |
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000D16 |
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002D16 |
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Port P6 direction register (P6D) |
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PWM register (PWM) |
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000E16 |
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002E16 |
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Port P7 (P7) |
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Reserved area |
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000F16 |
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002F16 |
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Port P7 direction register (P7D) |
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Reserved area |
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001016 |
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003016 |
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Reserved area |
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001116 |
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003116 |
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Reserved area |
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001216 |
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003216 |
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D-A1 conversion register (DA1) |
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001316 |
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003316 |
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D-A2 conversion register (DA2) |
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001416 |
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003416 |
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Reserved area |
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A-D control register (ADCON) |
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001516 |
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003516 |
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Key input control register (KIC) |
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A-D conversion register (AD) |
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001616 |
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003616 |
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PULL register A (PULLA) |
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D-A control register (DACON) |
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001716 |
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003716 |
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PULL register B (PULLB) |
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Watchdog timer control register (WDTCON) |
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001816 |
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003816 |
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Transmit/Receive buffer register(TB/RB) |
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Segment output enable register (SEG) |
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001916 |
Serial I/O1 status register (SIO1STS) |
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003916 |
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LCD mode register (LM) |
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001A16 |
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003A16 |
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Serial I/O1 control register (SIO1CON) |
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Interrupt edge selection register (INTEDGE) |
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001B16 |
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003B16 |
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UART control register (UARTCON) |
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CPU mode register (CPUM) |
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001C16 |
Baud rate generator (BRG) |
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003C16 |
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Interrupt request register 1(IREQ1) |
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001D16 |
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003D16 |
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Serial I/O2 control register (SIO2CON) |
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Interrupt request register 2(IREQ2) |
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001E16 |
Reserved area |
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003E16 |
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Interrupt control register 1(ICON1) |
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001F16 |
Serial I/O2 register (SIO2) |
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003F16 |
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Interrupt control register 2(ICON2) |
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Fig. 10 Memory map of special function register (SFR)
13
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Direction Registers
The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direction registers which determine the input/output direction of each individual pin. (Ports P00–P07 are shared with bit 0 of the port P0 direction register, and ports P10–P15 shared with bit 0 of the port
P1 direction register.) Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
Port P3 Output Control Register
Bit 0 of the port P3 output control register (address 000716) enables control of the output of ports P30–P37.
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to “0” (the port output function is invalid) and pulled up.
Pull-up Control
b7 |
b0 |
PULL register A
(PULLA : address 001616)
P00, P01 pull-up
P02, P03 pull-up
P04–P07 pull-up
P10–P13 pull-up
P14, P15 pull-up
P16, P17 pull-up
P20–P23 pull-up
P24–P27 pull-up
b7 |
b0 |
PULL register B
(PULLB : address 001716)
P41–P43 pull-up
P44–P47 pull-up
P50–P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
Note: The contents of PULL register A and PULL register B do not affect ports programmed as the output port.
Fig. 11 Structure of PULL register A and PULL register B
By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports P0 to P2, P4 to P6 can control pullup with a program.
However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports.
The PULL register A setting is invalid for pins set to segment output with the segment output enable register.
14
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 List of I/O port function (1)
Pin |
Name |
Input/Output |
I/O Format |
Non-Port Function |
Related SFRs |
Diagram No. |
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P00/SEG26– |
Port P0 |
Input/output, |
CMOS compatible |
LCD segment output |
PULL register A |
(1) |
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P07/SEG33 |
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byte unit |
input level |
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Segment output enable |
(2) |
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CMOS 3-state output |
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register |
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P10/SEG34– |
Port P1 |
Input/output, |
CMOS compatible |
LCD segment output |
PULL register A |
(1) |
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P15/SEG39 |
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6-bit unit |
input level |
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Segment output enable |
(2) |
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CMOS 3-state output |
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register |
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P16 , P17 |
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Input/output, |
CMOS compatible |
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PULL register A |
(4) |
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individual bits |
input level |
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CMOS 3-state output |
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P20–P27 |
Port P2 |
Input/output, |
CMOS compatible |
Key input (key-on |
PULL register A |
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individual bits |
input level |
wake-up) interrupt |
Interrupt control register2 |
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CMOS 3-state output |
input |
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Key input control register |
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P30/SEG18– |
Port P3 |
Output |
CMOS 3-state output |
LCD segment output |
Segment output enable |
(3) |
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P37/SEG25 |
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register |
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P3 output enable register |
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P40 |
Port P4 |
Input/output, |
CMOS compatible |
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(13) |
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individual bits |
input level |
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N-channel open-drain |
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output |
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P41/INT1, |
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CMOS compatible |
External interrupt input |
Interrupt edge selection |
(4) |
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P42/INT2 |
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input level |
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register |
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P43/φ /TOUT |
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CMOS 3-state output |
Timer output |
PULL register B |
(12) |
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φ output |
Timer 123 mode register |
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TOUT/φ output control |
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register |
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P44/RXD, |
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Serial I/O1 function I/O |
PULL register B |
(5) |
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P45/TXD, |
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Serial I/O1 control register |
(6) |
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P46/SCLK1, |
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Serial I/O1 status register |
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(7) |
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P47/SRDY1 |
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UART control register |
(8) |
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P50/PWM0, |
Port P5 |
Input/output, |
CMOS compatible |
PWM output |
PULL register B |
(10) |
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P51/PWM1 |
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individual bits |
input level |
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PWM control register |
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CMOS 3-state output |
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P52/RTP0, |
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Real time port |
PULL register B |
(9) |
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P53/RTP1 |
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function output |
Timer X mode register |
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P54/CNTR0 |
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Timer X function I/O |
PULL register B |
(11) |
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Timer X mode register |
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P55/CNTR1 |
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Timer Y function input |
PULL register B |
(14) |
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Timer Y mode register |
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P56/DA1 |
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DA1 output |
PULL register B |
(15) |
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D-A control register |
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P57/ADT/ |
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DA2 output |
PULL register B |
(15) |
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DA2 |
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A-D trigger input |
D-A control register |
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A-D control register |
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15
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 List of I/O port function (2)
Pin |
Name |
Input/Output |
I/O Format |
Non-Port Function |
Related SFRS |
Diagram No. |
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P60/SIN2/AN0 |
Port P6 |
Input/ |
CMOS compatible input |
A-D conversion input |
PULL register B |
(17) |
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output, |
level |
Serial I/O2 function I/O |
A-D control register |
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individual |
CMOS 3-state output |
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Serial I/O2 control |
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P61/SOUT2/ |
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(18) |
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bits |
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register |
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AN1 |
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P62/SCLK21/ |
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(19) |
AN2 |
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P63/SCLK22 / |
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(20) |
AN3 |
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P64/AN4– |
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A-D conversion input |
A-D control register |
(16) |
P67/AN7 |
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PULL register B |
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P70/INT0 |
Port P7 |
Input |
CMOS compatible input |
External interrupt input |
Interrupt edge |
(23) |
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level |
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selection register |
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P71–P77 |
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Input/ |
CMOS compatible input |
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(13) |
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output, |
level |
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individual |
N-channel open-drain |
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bits |
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output |
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COM0–COM3 |
Common |
Output |
LCD common output |
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LCD mode register |
(21) |
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SEG0–SEG17 |
Segment |
Output |
LCD segment output |
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(22) |
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Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections.
2:Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow VCC to VSS through the input-stage gate.
16
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P01–P07, P11–P15 |
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Pull-up |
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LCD drive timing |
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VL2/VL3/VCC |
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Segment data |
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Segment/Port |
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Interface logic level |
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Segment |
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Data bus |
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Port latch |
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shift circuit |
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Port |
direction register |
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VL1/VSS |
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Port |
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Port/Segment |
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Port direction register |
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(2) Ports P00, P10
Pull-up
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LCD drive timing |
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VL2/VL3/VCC |
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Direction register |
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Segment/Port |
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Segment data |
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Interface logic level |
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Data bus |
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Port latch |
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shift circuit |
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VL1/VSS |
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Port/Segment |
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Port direction register |
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(3) Port P3 |
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Pull-up |
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LCD drive timing |
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VL2/VL3/VCC |
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Segment data |
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Segment/Port |
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Interface logic level |
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Segment |
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Data bus |
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Port latch |
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shift circuit |
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VL1/VSS |
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Port/Segment |
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Output control |
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(4) Ports P16,P17,P2,P41,P42 |
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(5) Port P44 |
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Direction register
Data bus |
Port latch |
Pull-up control |
Pull-up control |
Serial I/O1 enable bit |
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Reception enable bit |
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Direction |
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register |
Data bus |
Port latch |
Key-on wake up interrupt input |
Serial I/O1 input |
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INT1, INT2 interrupt input |
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Except P16, P17 |
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Fig. 12 Port block diagram (1)
17
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Port P45 |
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(7) Port P46 |
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Serial I/O1 synchronization |
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Pull-up control |
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clock selection bit |
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Pull-up control |
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P45/TxD P-channel output disable bit |
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Serial I/O1 enable bit |
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Serial I/O1 enable bit |
Serial I/O1 mode selection bit |
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Transmission enable bit |
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Serial I/O1 enable bit |
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Direction |
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Direction |
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register |
register |
Data bus |
Port latch |
Data bus |
Port latch |
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Serial I/O1 output |
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Serial I/O1 clock output |
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Serial I/O1 clock input |
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(8) Port P47 |
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(9) Ports P52,P53 |
Pull-up control |
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Pull-up control |
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Serial I/O1 mode selection bit |
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Serial I/O1 enable bit |
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SRDY1 output enable bit |
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Direction |
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Direction |
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register |
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register |
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Data bus |
Port latch |
Data bus |
Port latch |
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Real time control bit |
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Serial I/O1 ready output |
Real time port data |
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(10) Ports P50,P51 |
(11) Port P54 |
Pull-up control |
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Pull-up control |
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Direction |
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register |
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Direction |
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register |
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Data bus |
Port latch |
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Data bus |
Port latch |
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Pulse output mode |
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Timer output |
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PWM function enable bit |
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CNTR0 interrupt input |
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PWM output |
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Fig. 13 Port block diagram (2)
18
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(12) Port P43 |
Pull-up control |
(13) Ports P40,P71–P77 |
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Direction |
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Direction |
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register |
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register |
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Data bus |
Port latch |
Data bus |
Port latch |
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TOUT/φ output control |
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Timer output |
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TOUT/φ selection bit |
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φ |
output |
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(14) Port P55 |
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(15) Ports P56,P57 |
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Pull-up control |
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Pull-up control |
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Direction |
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Direction |
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register |
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register |
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Data bus |
Port latch |
Data bus |
Port latch |
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CNTR1 interrupt input |
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A-D trigger input |
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Except P56 |
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D-A converter output |
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D-A1,D-A2 output enable bit |
(16) Ports P64–P67 |
(17) Port P60 |
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Pull-up control |
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Pull-up control |
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Direction |
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Direction |
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register |
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register |
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Data bus |
Port latch |
Data bus |
Port latch |
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A-D conversion input |
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Serial I/O2 input |
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Analog input pin selection bit |
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A-D conversion input |
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Analog input pin selection bit |
Fig. 14 Port block diagram (3)
19
MITSUBISHI MICROCOMPUTERS
7560 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(18) Port P61
P61/SOUT2 P-channel output disable bit |
Pull-up control |
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Serial I/O2 transmit end signal |
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Synchronous clock selection bit |
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Serial I/O2 port selection bit |
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Direction |
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register |
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Data bus |
Port latch |
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(19) Port P62
Synchronous clock selection bit
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Pull-up control |
Serial I/O2 port selection bit |
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Synchronous clock output pin |
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selection bit |
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Direction |
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register |
Data bus |
Port latch |
Serial I/O2 output |
Serial I/O2 clock output |
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A-D conversion input |
Serial I/O2 clock input |
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Analog input pin selection bit |
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A-D conversion input |
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Analog input pin selection bit |
(20) Port P63
Pull-up control
Synchronous clock selection bit Serial I/O2 port selection bit
Synchronous clock output pin selection bit Direction register
Data bus Port latch
Serial I/O2 clock output
A-D conversion input
Analog input pin selection bit
(21)COM0–COM3
VL3
The gate input signal of each transistor is controlled by the LCD
duty ratio and the bias value.
VL2
VL1
VSS
(22)SEG0–SEG17
VL2/VL3
The voltage applied to the sources of P-
channel and N-channel transistors is the controlled voltage by the bias value.
VL1/VSS
(23) Port P70
Direction
register
Data bus Port latch
INT0 input
Fig. 15 Port block diagram (4)
20