1.5–2.5 GHz Upconverter/
Downconverter
Technical Data
HPMX-5001
•2.7 V Single Supply Voltage
•Low Power Consumption (60Ê mA in Transmit Mode, 39 mA in Receive Mode Typical)
•2 dBm Typical Transmit Power at 1900 MHz
•Half-Frequency VCO with Frequency Doubler
•32/33 Dual-Modulus Prescaler
•Flexible Chip Biasing, Including Standby Mode
•TQFP-32 Surface Mount Package
•Operation to 2.5 GHz
•Use with Companion HPMX-5002 IF chip
•DECT, UPCS and ISM Band Handsets and Basestations
H
-5001 HPMX
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ZZZ XXXX
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HPMX-5001 |
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YYWW |
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XXXX |
ZZZ |
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8 |
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17 |
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9 |
16 |
RX IF OUT |
POWER DOWN |
CONTROL |
RX RF IN |
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X2 |
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EXT. |
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VCO |
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TANK |
TX RF OUT |
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32/33 |
RATIO |
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SELECT |
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TX IF IN |
PRESCALER |
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OUT |
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5965-9105E |
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7-90 |
The HPMX-5001 Upconverter/ Downconverter provides RF system designers with all of the necessary features to perform an RF-to-IF downconversion for a receive path, as well as an IF-to- RF upconversion for transmit mode.
Designed to meet the unique needs of portable applications, the HPMX-5001 combines the qualities of flexible chip biasing, low power consumption, and true 2.7 V minimum supply voltage operation to provide superior performance and battery life. By incorporating the active elements of the VCO on-chip, as well as a 32/33 dual-modulus prescaler, overall system component count and costs are decreased. The 32-TQFP package insures that this high level of integration occupies a small amount of printed circuit board space.
The HPMX-5001 can be used in either dual-conversion systems (with the HPMX-5002 IF Demodulator/Modulator) or single-conversion systems. The HPMX-5001 is manufactured
using Hewlett-Packard’s HP-25 |
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Silicon Bipolar Process with |
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25Ê GHz f and 30 GHz f . |
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T |
Max |
HPMX-5001 Absolute Maximum Ratings[1]
Parameter |
Min. |
Max. |
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VCC Supply Voltage |
-0.2V |
8 V |
Voltage at Any Pin[4] |
-0.2V |
V + 0.2 V |
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CC |
Power Dissipation[2,3] |
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600mW |
RF Input Power |
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15 dBm |
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Junction Temperature |
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+150°C |
Storage Temperature |
-55°C |
+125°C |
Thermal Resistance[2]:
θjc = 100°C/W
Notes:
1.Operation of this device in excess of any of these parameters may cause permanent damage.
2.TCASE = 25°C.
3.Derate at 10 mW/°C for TCASE > 90°C.
4.Except CMOS logic inputs – see Summary Characterization Information table.
Unless otherwise noted, all parameters are guaranteed under the following conditions: VCC = 3.0 V. Test results are based upon use of networks shown in test board schematic diagram (see Figure 28). Typical values are for VCC = 3.0 V, TA = 25°C.
Symbol |
Parameters and Test Conditions |
Units |
Min. |
Typ. |
Max. |
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GC |
Receive Conversion Gain[1] |
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dB |
12 |
14 |
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Pout |
Transmitter Power Output |
Input[2] |
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2:1 output VSWR |
dBm |
0 |
2 |
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ICC |
Device Supply Current |
Transmit Mode |
mA |
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64 |
80 |
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Receive Mode |
mA |
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43 |
54 |
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Synth Mode |
mA |
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15 |
19 |
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Standby Mode (with DIVMC Set High) |
μA |
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1 |
50 |
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V |
DIV Single-Ended Swing[3] |
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V |
0.7 |
1 |
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DIV |
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PP |
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Notes:
1.50 Ω RF source, 100 MHz < IF < 300 MHz, 1.89 GHz RF. There is a 750 Ω resistor on chip between RXIF and RXIFB (pins 3 and 4). A matching network from 750 Ω to 50 Ω is used for this measurement. Insertion loss of the matching network is included in the net
conversion gain figure. See Figure 28.
2.Signal injected into P3 in Figure 28 is -12.5 dBm.
3.DIV output AC coupled into a 2 kΩ || 10 pF load. See test board schematic diagram, Figure 28.
7-91
Typical values measured on test board shown in Figure 28 at VCC = 3.0 V, TA = 25°C, RXIF = 110.592 MHz, TXRF = 1.89 GHz, unless otherwise noted.
Symbol |
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Parameters and Test Conditions |
Units |
Typical |
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VIH |
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CMOS Input High Voltage (Can Be Pulled |
V |
³ VCC-0.8 |
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up as High as V + 7 V)[1] |
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CC |
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VIL |
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CMOS Input Low Voltage |
V |
£ VCC-1.9 |
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IIH |
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CMOS Input High Current |
mA |
<10 |
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IIL |
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CMOS Input Low Current |
mA |
>-300 |
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ts |
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DIVMC Setup Time[2,8] |
ns |
4 |
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th |
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DIVMC Hold Time[2,8] |
ns |
0 |
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tpd |
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DIV Propagation Delay[2,8] |
ns |
<7 |
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Mode Switching Time[3] |
ms |
<1 |
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Receive Mode |
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1.89GHz |
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2.45GHz |
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Gc |
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Receive Conversion Gain[9] |
dB |
14 |
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13.5 |
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NF |
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Noise Figure[4] |
dB |
10 |
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10 |
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IIP3 |
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Input Third Order Intercept Point |
dBm |
-8 |
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-9 |
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IP1dB |
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Input 1 dB Gain Compression Point |
dBm |
-18 |
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-18 |
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LO Leakage (2 x fVCO) at IF Port |
dBm |
-57 |
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— |
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VSWRin |
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Input VSWR[5] |
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1.3:1 |
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1.3:1 |
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Transmit Mode[6] |
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PIM3 |
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Power Output Level for >35 dB IM3 Suppression[10] |
dBm |
— |
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-5 |
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OP1dB |
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Output 1 dB Gain Compression Point |
dBm |
0 |
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0 |
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VSWRout |
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Output VSWR |
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1.8:1 |
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1.8:1 |
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LO Suppression (2 x fVCO) |
dBc |
25 |
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30 |
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F3dBIF |
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IF 3 dB Bandwidth |
MHz |
500 |
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500 |
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Transmitter C/N @ 2 x fVCO + 4 MHz[11] |
dBc/Hz |
+137 |
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+134 |
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Synth Mode |
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1LO Frequency Range[7] |
MHz |
750-1200 |
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Notes:
1.All CMOS logic inputs are internally pulled up to logic high level.
2.See Figure 2 for detailed timing diagram.
3.Between any two different biasing modes. This switching time does not include PLL lock-up time.
4.Single sideband noise figure.
5.In modes other than receive, the VSWR may be as high as 10:1.
6.Single-ended 50 Ω RF load, 300 Ω series IF terminations (600 Ω differential), 100 MHz < IF < 300 MHz, 1.89 GHz RF.
7.The LO is followed by a frequency doubler which raises the LO range to 1500-2400 MHz.
8.DIV output AC coupled into a 2 kΩ || 10 pF load. See test diagram, Figure 28.
9.50 Ω RF source, 110 MHz < IF < 300 MHz, 1.89 GHz or 2.45 GHz RF. There is a 750 Ω resistor on chip between RXIF and RXIFB (pins 3 and 4). A matching network from 750 Ω to 50ÊΩ is used for this measurement. Insertion loss of the matching network is
included in the net conversion gain figure.
10.PIM3 is the maximum SSB output power for at least 35 dB IM3 spur suppression.
11.Measured at saturated output power for 1.89 GHz. Measured at -5 dBm SSB output power for 2.45Ê GHz.
7-92
Table 1 - HPMX-5001 Pin Description
No. |
Mnemonic |
I/O Type |
Description |
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1 |
TXCTRL |
CMOS I/P |
Controls biasing of transmit mixer, amplifiers, and doubler |
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3 |
RXIFB |
Analog O/P |
Inverted single-ended downconverted receiver output, |
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normally tied to VCC (internal 750 Ω resistor connects to RXIF) |
4 |
RXIF |
Analog O/P |
Single-ended downconverted receiver output, drives SAW |
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filter (internal 750 Ω resistor connects to RXIFB) |
5 |
TXIF |
Analog I/P |
Transmit non-inverting IF input |
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6 |
TXIFB |
Analog I/P |
Transmit inverting IF input |
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7 |
LNAREF |
Analog DC I/P |
Reference input for receive input amplifier |
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8 |
RXRF |
Analog I/P |
Receive RF input |
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10 |
TXRXVCC |
DC Supply |
Supply voltage for transmit path, receive front-end and mixer |
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11,15 |
TXRXGND |
Ground |
Ground for transmit path, receive front-end and mixer |
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12 |
TXRFB |
Analog O/P |
Inverting output of transmit path (see test diagram for |
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matching network) |
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14 |
TXRF |
Analog O/P |
Non-inverting output of transmit path (see test diagram for |
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matching network) |
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16 |
DBLVCC |
DC Supply |
Supply voltage for LO frequency doubler |
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17 |
DBLGND |
Ground |
Ground for LO frequency doubler |
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20 |
VCOTNKS |
Analog I/P |
Sense line from external tank circuit to on-chip VCO amplifier |
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21 |
VCOTNKF |
Analog O/P |
Force line from on-chip VCO amplifier to external tank circuit |
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22 |
VCOVCC |
DC Supply |
Supply voltage for on-chip VCO amplifier |
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23 |
VCOGND |
Ground |
Ground for on-chip VCO amplifier |
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26 |
DIVVCC |
DC Supply |
Supply voltage for 32/33 dual-modulus prescaler |
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27 |
DIVGND |
Ground |
Ground for 32/33 dual-modulus prescaler |
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28 |
DIV |
Analog O/P |
Output from 32/33 dual-modulus prescaler |
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30 |
DIVMC |
CMOS I/P |
Modulus control signal for 32/33 dual-modulus prescaler |
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31 |
LOCTRL |
CMOS I/P |
Controls biasing for VCO and 32/33 dual modulus prescaler |
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32 |
RXCTRL |
CMOS I/P |
Controls biasing for receive mixer, amplifiers, and doubler |
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2,9,13, |
VSUB |
Ground |
Substrate bias voltage |
18,19,24, |
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25,29 |
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Table 2 - HPMX-5001 Mode Control
(CMOS Logic Levels - all pins internally pulled up to high level)
Mode |
TXCTRL |
RXCTRL |
LOCTRL |
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Transmit |
0 |
1 |
0 |
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Receive |
1 |
0 |
0 |
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Synth |
1 |
1 |
0 |
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Standby |
1 |
1 |
1 |
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7-93
31 |
32 |
1 |
2 |
16 |
17 |
18 |
19 |
32 |
33 |
1 |
2 |
VCO |
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DIV |
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DIVMC |
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DIVIDE BY 33 (DIVMC = 0) |
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31 |
33 |
1 |
2 |
16 |
17 |
18 |
19 |
32 |
1 |
2 |
3 |
VCO |
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DIV |
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tpd |
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DIVMC |
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ts |
th |
DIVIDE BY 32 (DIVMC = 1) |
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Figure 2. HPMX-5001 Prescaler Timing Diagram.
FRONT-END RF FILTER
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CERAMIC |
TX IF INPUT |
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TX |
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TX PA |
FILTER |
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T/R |
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X2 |
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RX LNA |
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32/33 |
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CERAMIC |
HPMX-5001 |
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IMAGE |
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FILTER |
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RX IF FILTER |
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RX IF OUTPUT |
LO1 REFERENCE OSCILLATOR
TANK
˜ 30 MHz
SYNTHESIZER
Figure 3. HPMX-5001 Block Diagram/Typical Application.
7-94