Features
•Utilizes the AVR® Enhanced RISC Architecture
•121 Powerful Instructions - Most Single Clock Cycle Execution
•128K bytes of In-System Reprogrammable Flash ATmega103/L
64K bytes of In-System Reprogrammable Flash ATmega603/L
–SPI Interface for In-System Programming
–Endurance: 1,000 Write/Erase Cycles
•4K bytes EEPROM ATmega103/L
2K bytes of EEPROM ATmega603/L
–Endurance: 100,000 Write/Erase Cycles
•4K bytes Internal SRAM
•32 x 8 General Purpose Working Registers + Peripheral Control Registers
•32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
•Programmable Serial UART + SPI Serial Interface
•VCC Supply
–2.7 - 3.6V ATmega603L/ATmega103L
–4.0 - 5.5V ATmega603/ATmega103
•Fully Static Operation
–0 - 6 MHz ATmega603/ATmega103
–0 - 4 MHz ATmega603L/ATmega103L
•Up to 6 MIPS Throughput at 6 MHz
•RTC with Separate Oscillator
•Two 8-Bit Timer/Counters with Separate Prescaler and PWM
•One 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-Bit PWM
•Programmable Watchdog Timer with On-Chip Oscillator
•On-Chip Analog Comparator
•8-Channel, 10-Bit ADC
•Low Power Idle, Power Save and Power Down Modes
•Software Selectable Clock Frequency
•Programming Lock for Software Security
Pin Configuration
TQFP
8-Bit |
Microcontroller |
with 64K/128K |
Bytes In-System |
Programmable |
Flash |
ATmega603 |
ATmega603L |
ATmega103 |
ATmega103L |
Preliminary |
Rev. 0945BS–09/98 |
Note: This is a summary document. For the complete 92
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page document, please visit our web site at |
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www.atmel.com or e-mail at literature@atmel.com and request literature #0945B.
Block Diagram
Figure 1. The ATmega603/103 Block Diagram
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PF0 - PF7 |
PA0 - PA7 |
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PC0 - PC7 |
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VCC |
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GND |
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PORTF BUFFERS |
PORTA DRIVER/BUFFERS |
PORTC DRIVERS |
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AVCC |
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ANALOG MUX |
ADC |
DATA REGISTER |
DATA DIR. |
DATA REGISTER |
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PORTA |
REG. PORTA |
PORTC |
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8-BIT DATA BUS |
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AGND |
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XTAL1 |
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AREF |
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INTERNAL |
OSCILLATOR |
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OSCILLATOR |
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XTAL1 |
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PROGRAM |
STACK |
WATCHDOG |
OSCILLATOR |
TOSC2 |
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COUNTER |
POINTER |
TIMER |
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PROGRAM |
SRAM |
MCU CONTROL |
TIMING AND |
TOSC1 |
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FLASH |
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REGISTER |
CONTROL |
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RESET |
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INSTRUCTION |
GENERAL |
TIMER/ |
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ALE |
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REGISTER |
COUNTERS |
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PURPOSE |
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WR |
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REGISTERS |
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RD |
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INSTRUCTION |
X |
INTERRUPT |
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Y |
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DECODER |
Z |
UNIT |
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CONTROL |
ALU |
EEPROM |
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LINES |
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STATUS |
PROGRAMMING |
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PEN |
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REGISTER |
LOGIC |
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SPI |
UART |
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ANALOG COMPARATOR |
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DATA REGISTER |
DATA DIR. |
DATA REGISTER |
DATA DIR. |
DATA REGISTER |
DATA DIR. |
+ |
- |
PORTE |
REG. PORTE |
PORTB |
REG. PORTB |
PORTD |
REG. PORTD |
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VCC |
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PORTE DRIVER/BUFFERS |
PORTB DRIVER/BUFFERS |
PORTD DRIVER/BUFFERS |
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GND |
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PE0 - PE7 |
PB0 - PB7 |
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PD0 - PD7 |
Description
The ATmega603/103 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega603/103 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture
is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega603/103 provides the following features: 64K/128K bytes of In-system Programmable Flash, 2K/4K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 8 Input lines, 8 Output lines, 32 general purpose working registers, 4 flexible timer/counters with compare modes and PWM, UART, programmable Watchdog Timer with internal oscillator, an SPI serial port and three software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power
2 ATmega603(L) and ATmega103(L)
ATmega603(L) and ATmega103(L)
Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high-density non-volatile memory technology. The on-chip ISP Flash allows the program memory to be reprogrammed in-system through a serial interface or by a conventional nonvolatile memory programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega603/103 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega603/103 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Port A serves as Multiplexed Address/Data bus when using external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O pins with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
Port C (PC7..PC0)
Port C is an 8-bit Output port. The Port C output buffers can sink 20 mA.
Port C also serves as Address output when using external SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated.
Comparison Between ATmega 603 and
ATmega 103
The ATmega603 has 64K bytes of In-System Programmable Flash, 2K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega603 does not have the ELPM instruction.
The ATmega103 has 128K bytes of In-System Programmable Flash, 4K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega103 has the ELPM instruction, necessary to reach the upper half of the Flash memory for constant table lookup.
Table 1 summarizes the different memory sizes for the two devices.
Table 1. Memory Size Summary
Part |
Flash |
EEPROM |
SRAM |
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ATmega603 |
64K bytes |
2K bytes |
4K bytes |
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ATmega103 |
128K bytes |
4K bytes |
4K bytes |
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Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
Port D also serves the functions of various special features.
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated.
Port E also serves the functions of various special features.
Port F (PF7..PF0)
Port F is an 8-bit Input port. Port F also serves as the analog inputs for the ADC.
RESET
input. A low on this pin for two machine cycles while the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
TOSC1
Input to the inverting Timer/Counter oscillator amplifier
TOSC2
Output from the inverting Timer/Counter oscillator amplifier
WR
External SRAM Write Strobe.
RD
External SRAM Read Strobe.
ALE
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-order address (8 bits) into an address latch during the
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