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iMac 27 A1419
Schematics
117 pgs2.63 Mb2
Schematics Rev 8.0.0
123 pgs2.41 Mb0

Apple iMac 27 A1419 Schematics Rev 8.0.0

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DRAWING
DRAWING
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2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PROPRIETARY PROPERTY OF APPLE INC.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
DESCRIPTION OF REVISION
CK APPD
2 1
1245678
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NOTICE OF PROPRIETARY PROPERTY:
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THE INFORMATION CONTAINED HEREIN IS THE
C
A
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SHEET
Apple Inc.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING TITLE
D
SIZE
REVISION
DRAWING NUMBER
BRANCH
REV ECN
7
B
3
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
IV ALL RIGHTS RESERVED
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
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TABLE_TABLEOFCONTENTS_ITEM
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D8 MLB ULTIMATE
1 OF 123
2012-08-28
ENGINEERING RELEASED
1 OF 144
8.0.0
051-9505
8
0001607319
prefsb
LAST_MODIFIED=Mon Aug 27 13:33:38 2012
ABBREV=DRAWING
TITLE=K72
LAST_MODIFIED=Mon Aug 27 13:33:38 2012
N/A
1
MASTER
1
Table of Contents
Date
Sync
Contents
Page
(.csa)
Page
(.csa)
Date
Contents
Sync
63
AUDIO: Speaker ID
68
D8_MLB
08/27/2012
SCH,D8,MLB ULTIMATE
64
PM Regulator Enables
69
D8_MLB
08/27/2012
65
PM Power Good
70
D8_MLB
08/27/2012
66
VReg CPU Core/AXG Cntl
71
D8_MLB
08/27/2012
67
VReg CPU Core Phases
72
D8_MLB
08/27/2012
68
VReg CPU AXG Phases
73
D8_MLB
08/27/2012
69
VReg CPU 1.05V S0
74
D8_MLB
08/27/2012
70
VReg CPU VccSA S0
75
D8_MLB
08/27/2012
71
VReg 3.3V S5/5V S4
76
D8_MLB
08/27/2012
72
VReg VDDQ and 1.8V S0
77
D8_MLB
08/27/2012
73
VREG 3.42V G3HOT
78
D8_MLB
08/27/2012
74
FET-Controlled S0 and S4
79
D8_MLB
08/27/2012
75
Internal DP MUXing
92
D8_MLB
08/27/2012
76
TBT DDC Crossbar
93
D8_MLB
08/27/2012
77
Thunderbolt Connector A
94
D8_MLB
08/27/2012
78
Internal DP Support
95
D8_MLB
08/27/2012
79
Thunderbolt Connector B
96
D8_MLB
08/27/2012
80
Backlight Controller MCU
97
D8_MLB
08/27/2012
81
Backlight LED Driver
98
D8_MLB
08/27/2012
82
Backlight Controller
99
D8_MLB
08/27/2012
83
KEPLER PCI-E
100
D8_YAN
04/09/2012
84
KEPLER FRAME BUFFER A/B
101
D8_YAN
04/09/2012
85
KEPLER FRAME BUFFER C/D
102
D8_YAN
04/09/2012
86
GDDR5 Frame Buffer A
103
D8_YAN
04/09/2012
87
GDDR5 Frame Buffer B
104
D8_YAN
04/09/2012
88
GDDR5 FRAME BUFFER C
105
D8_YAN
04/09/2012
89
GDDR5 FRAME BUFFER D
106
D8_YAN
04/09/2012
90
KEPLER EDP/DP/GPIO
107
D8_YAN
04/09/2012
91
KEPLER GPIO/STRAPPING
108
D8_YAN
07/27/2012
92
KEPLER MISC
109
D8_YAN
04/09/2012
93
KEPLER CORE POWER
111
D8_YAN
04/09/2012
94
KEPLER FBVDD/Q POWER
112
D8_YAN
04/09/2012
95
KEPLER PEX PWR/GNDS
113
D8_YAN
04/09/2012
96
VReg GPU Core Phases
114
D8_MLB
08/27/2012
97
VReg GPU Core Phases
115
D8_MLB
08/27/2012
98
VREG GPU CORE PHASE 4
116
D8_MLB
08/27/2012
99
GPU VDDQ AND 1V05 GPU/PCH/TBT VREGS
117
D8_MLB
08/27/2012
100
D8 RULE DEFINITIONS
120
D8_MLB
08/27/2012
101
DDR3 Constraints
121
D8_MLB
08/27/2012
102
CPU PCIe Constraints
122
D8_MLB
02/06/2012
103
CPU MISC/DMI/FDI/XDP Constraints
123
D8_MLB
08/27/2012
104
SATA/FDI/XDP Constraints
124
D8_MLB
08/27/2012
105
PCH and BR Constraints
125
D8_MLB
08/27/2012
106
USB/Camera Constraints
126
D8_MLB
08/27/2012
107
SMBus/Sensor Constraints
127
D8_MLB
08/27/2012
108
VReg Constraints
128
D8_MLB
08/27/2012
109
CPU VReg Constraints
129
D8_MLB
08/27/2012
110
Platform VReg Constraints
130
D8_MLB
08/27/2012
111
TBT/DP Constraints
131
D8_MLB
08/27/2012
112
GDDR5/GPU Constraints
132
D8_MLB
01/11/2012
113
GDDR5 FB C/D CONSTRAINTS
133
D8_MLB
12/20/2011
114
BLC Constraints
134
D8_MLB
08/27/2012
115
GPU VREG CONSTRAINTS
135
D8_MLB
08/27/2012
116
ETHERNET/SD CONSTRAINTS
136
D8_MLB
08/27/2012
117
AUTO-CONSTRAINTS 1
138
D8_MARK
06/20/2012
118
AUTO-CONSTRAINTS 2
139
D8_MARK
06/20/2012
119
AUTO-CONSTRAINTS 3
140
D8_MARK
06/20/2012
120
AUTO-CONSTRAINTS 4
141
D8_MARK
06/20/2012
121
AUTO-CONSTRAINTS 5
142
D8_MARK
06/20/2012
122
AUTO-CONSTRAINTS 6
143
D8_MARK
06/20/2012
123
AUTO-CONSTRAINTS 7
144
D8_MARK
06/20/2012
08/23/2011
2
K70_MLB
2
System Block Diagram
08/27/2012
3
D8_MLB
3
Power Block Diagram
06/15/2012
4
D8_MLB_ULTIMATE
4
BOM Configuration
08/27/2012
5
D8_MLB
5
DEBUG LEDS
08/27/2012
6
D8_MLB
6
Power Connectors/Aliases
08/27/2012
7
D8_MLB
7
Holes/PD parts
08/27/2012
8
D8_MLB
8
Unused Signal Aliases
08/27/2012
9
D8_MLB
9
Signal Aliases
08/27/2012
10
D8_MLB
10
CPU DMI/PEG/FDI/RSVD
08/27/2012
11
D8_MLB
11
CPU CLOCK/MISC/JTAG
08/27/2012
12
D8_MLB
12
CPU DDR3 INTERFACES
08/27/2012
13
D8_MLB
13
CPU POWER
08/27/2012
14
D8_MLB
14
CPU GROUNDS
08/27/2012
15
D8_MLB
15
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
08/27/2012
16
D8_MLB
16
CPU NON-GFX DECOUPLING
08/27/2012
17
D8_MLB
17
GFX DECOUPLING & PCH PWR ALIAS
08/27/2012
18
D8_MLB
18
PCH SATA/PCIE/CLK/LPC/SPI
08/27/2012
19
D8_MLB
19
PCH DMI/FDI/GRAPHICS
08/27/2012
20
D8_MLB
20
PCH PCI/USB
08/27/2012
21
D8_MLB
21 PCH MISC
08/27/2012
22
D8_MLB
22
PCH POWER
08/27/2012
23
D8_MLB
23
PCH GROUNDS
08/27/2012
24
D8_MLB
24
PCH DECOUPLING
08/27/2012
25
D8_MLB
25
CPU and PCH XDP
08/27/2012
26
D8_MLB
26
CHIPSET SUPPORT
08/27/2012
27
D8_MLB
27
USB 2.0 HUB (BT/SMC)
08/27/2012
28
D8_MLB
28
CPU Memory S3 Support
08/27/2012
29
D8_MLB
29
DDR3 SO-DIMM Connector A Slot0
08/27/2012
30
D8_MLB
30
DDR3 SO-DIMM Connector A Slot1
08/27/2012
31
D8_MLB
31
DDR3 SO-DIMM CONNECTOR B SLOT0
08/27/2012
32
D8_MLB
32
DDR3 SO-DIMM CONNECTOR B SLOT1
08/27/2012
33
D8_MLB
33
DDR3 ALIASES AND BITSWAPS
08/27/2012
34
D8_MLB
34
DDR3/FRAMEBUF VREF MARGINING
08/27/2012
35
D8_MLB
35
AIRPORT/BT
08/27/2012
36
D8_MLB
36
Thunderbolt Host (1 of 2)
08/27/2012
37
D8_MLB
37
Thunderbolt Host (2 of 2)
08/27/2012
38
D8_MLB
38
Thunderbolt Power Support
08/27/2012
39
D8_MLB
39
ETHERNET PHY (CAESAR IV+)
08/27/2012
40
D8_MLB
40
Ethernet Support & Connector
08/27/2012
41
D8_MLB
41
SD READER CONNECTOR
08/27/2012
42
D8_MLB
42
Camera Controller
08/27/2012
43
D8_MLB
43
Camera Controller Support
08/27/2012
45
D8_MLB
44
SATA Connectors
08/27/2012
46
D8_MLB
45
EXTERNAL USB PORTS A & B
08/27/2012
47
D8_MLB
46
EXTERNAL USB PORTS C & D
08/27/2012
49
D8_MLB
47 SMC
08/27/2012
50
D8_MLB
48
SMC Support
08/27/2012
51
D8_MLB
49
SPI and Debug Connector
08/27/2012
52
D8_MLB
50
SMBus Connections
08/27/2012
53
D8_MLB
51
I and V Sense 1
08/27/2012
54
D8_MLB
52
HDD/SSD Temp Sense
08/27/2012
55
D8_MLB
53
Temperature Sensors
08/27/2012
56
D8_MLB
54
System Fan
08/27/2012
59
D8_MLB
55
I and V Sense 2
08/27/2012
61
D8_MLB
56
AUDIO: CODEC/REGULATORS
08/27/2012
62
D8_MLB
57
AUDIO: HEADPHONE AMP
08/27/2012
63
D8_MLB
58
AUDIO: LEFT SPKR AMP
08/27/2012
64
D8_MLB
59
AUDIO: RIGHT SPKR AMP
08/27/2012
65
D8_MLB
60
AUDIO: Jack, Mikey, CHS Switch
08/27/2012
66
D8_MLB
61
Audio: Spkr/Mic Conn.
08/27/2012
67
D8_MLB
62
AUDIO: Detects/Grounding
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
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8 7 6 5 4 3
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A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PATH: KISMET > K70/72 > BLOCK DIAGRAMS > K72 BLOCK DIAGRAM
System Block diagram can be found on Kismet
System Block Diagram
prefsb
051-9505
8.0.0
2 OF 144 2 OF 123
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Regulator
U7600
PP3V42_G3H
IW0R
Fan
TBT IO
Speaker amps
GPU
LCD
PPVCCSA_S0
PP1V05_S0_CPU
PPVCORE_S0_CPU
PPVAXG_S0
PPFBVDDQ_S0_GPU
PPVCORE_S0_GPU
GPU (Core)
GPU (FB)
CPU (AXG)
CPU
CPU (Core)
CPU (VccIO)
PP1V05_TBTCIO
PP1V05_TBTLC
P1V05_S0_PCH
P1V05_S0
TBT Router
TBT Router
GPU (IOVDD, PLLVDD)
PCH (VCC, VccIO)
PP12V_S0_HDD
HDD (12V)
PH0R
PGTR
=
=
PH02+PH05
=
PCTR
SMC, RTC, MojoMux
PP12V_G3H
en
Regulator
VD2R
PR1R
IR1R
RegS0
Vin
UB700
en
S0
1V05
SD Card, DP Mux, DP X-bar
VD2R
PG0F
VD2R
IG0F
PC0S
Regulator
S0
FBVDDQ
GPU
3.3V
PCH, PwrCtl
Regulator
U7801
Reg
Vin
G3H G3H
3V42
VccIO
S0S0 Reg
Vin en
Regulator
U7400
Bootrom, PCH, SMC, XDP,
Audio, LCD TCON, SnsCtl, VRD, PCH
PP5V_S0
VRegCtl, SnsCtl
Audio, PCH
PP5V_S0_HDD
HDD (5V)
PP5V_S4
CAM, USB Ports, VRegCtl
PH05
IH05
VH05
SSD
PP3V3_S0_SSD
PH1R
IW1R
V3V3
PP3V3_S0
VG0C
VC0C
USB Hub, SMC, TBT I/O
PP3V3_S4_ENET
PP3V3_S4
WIFI
PP3V3_S4_AP
PW0R
V3V3
SD Card, USB Mux, VRD, PwrCtl
PP3V3_TBTLC
TBT Router
Ethernet
IC0S
S4RegS4
en 5V
S0LDOS0
en
VTT
VTT
LDO S3
S3Reg
en
S3
Regulator
U7700
Vin
VDDQ
IM0R
VM0R
PM0R
PPDDRVTT_S0
DIMM (VTT)
DIMM VREF Margining CA
IC0M
VC0M
PC0M
PPDDRVTT_S3
PP1V5_S0
PPVDDQ_S3_DDR
PP1V5_S0_CPU_MEM
CPU (Mem)
Audio
DIMM (1V5)
Vin
PH02
IH02
VD2R
UB750
Regulator
Loads
IN1R
VN1R
PN1R
en
S0 Reg
GPU
S0
UB400
Vin en
S0Reg
IG0C
PG0C
U7100
Vin
S0
Regulator
AXG
VC0G IC0G
PC0G
S0Reg
Core
IC0C
PC0C
en
Reg
VccSA
S0
VD2R
VD2R
IC0I
PC0I
Regulator
U7500
Vin
PPHV_SW_TBTAPWR
PPHV_SW_TBTBPWR
TBT Port A
TBT Port B
PD2R
ID2R
Supply Module
PP5V_S0
en
Vin
S0
U7750
Regulator
Reg S0
1.8V
PP1V8_S0_REG
CPU PLL
en
PP12V_S5
S5Reg
Vin
PP5V_S5
PP12V_S0_BLC
S5 LDO5VS5
PP12V_ACDC
12V
G3H
AC/DC
Reg
ALS, CAM, BT
en
PP3V3_S5
S0
PP12V_S0
S0Reg
PC0I
+
PC0S
+
)
PC0MPC0G
+
PC0C
(
+
5.7 (GK104/GK107_BLENDED_CONSTANT)
+
PG0F
+
PG0C
1.176 *
1.176 *
High-side Component Total Power Keys
Power Block Diagram
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
prefsb
051-9505
8.0.0
3 OF 144 3 OF 123
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
D8 SCHEMATIC / PCB #’S
BOM Variants
ASICs
Programmable Parts
ALTERNATE:335S0812
ALTERNATE:335S0854
CPU SOCKET
CPU SOCKET ALTERNATES
VRAM Module Parts
D8 ALTERNATES
Bar Code Labels / EEEE #’s
CPUs
BOM Groups
SYNC_MASTER=D8_MLB_ULTIMATE
BOM Configuration
SYNC_DATE=06/15/2012
1
CRITICAL
EEEE:F652
LABEL,MLB,2D
EEEE_F652
825-7896
CRITICAL
1
EEEE_F4TY
LABEL,MLB,2D
EEEE:F4TY
825-7896
EEEE_F4MW EEEE:F4MW
825-7896
LABEL,MLB,2D
1
CRITICAL
1
CRITICAL
EEEE_F64W EEEE:F64W
825-7896
LABEL,MLB,2D
1
CRITICAL
EEEE_F0V5 EEEE:F0V5
825-7896
LABEL,MLB,2D
CRITICAL
1
EEEE_DYW3 EEEE:DYW3
825-7896
LABEL,MLB,2D
102S0879
0.010 OHM,1%,1206
ALL
102S0880
138S0803 138S0804
ALL
2.2UF CAPS SOFT
128S0365
ALL
128S0368
150UF CAPS BLK
376S1081
ALL
P/NCH DUAL FET
376S0975
341S3645
CIVROM
U3990
341S3644
CRITICALPCB1 D8820-3299
PCBF,MLB,D8,ULTIMATE
1
4
333S0619
CRITICAL
UA300,UA350,UA400,UA450
IC,SGRAM,GDDR5,32MX32,1.5GHZ,G-DIE,HF
FB:1G_SAMSUNG
UA500,UA550,UA600,UA650
IC,SGRAM,GDDR5,32MX32,1.5GHZ,G-DIE,HF
CRITICAL
4
333S0619
FB:1G_SAMSUNG
IC,SGRAM,GDDR5,64MX32,D-DIE
CRITICAL
333S0631
4
UA500,UA550,UA600,UA650
FB:2G_SAMSUNG
CRITICAL
4
UA300,UA350,UA400,UA450
IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE
333S0620
FB:1G_HYNIX
333S0620
4
IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE
CRITICAL
FB:1G_HYNIX
UA500,UA550,UA600,UA650
CRITICAL
333S0631
4
FB:2G_SAMSUNG
IC,SGRAM,GDDR5,64MX32,D-DIE
UA300,UA350,UA400,UA450
UA300,UA350,UA400,UA450
333S0630
FB:2G_HYNIX
4
IC,GDDR5,64MX32,A-DIE
CRITICAL
4
FB:2G_HYNIX
CRITICAL
IC,GDDR5,64MX32,A-DIE
333S0630
UA500,UA550,UA600,UA650
SCH,MLB,D8,ULTIMATE
SCH1 D8
1
CRITICAL051-9505
ALL
157S0058
Enet Magnetics
157S0084
ALL
377S0126
USB diodes
377S0147
511S0073
ALL
FOXCONN SOCKET
511S0072
ALL
511S0073
TYCO SOCKET
511S0071
CRITICAL
1
511S0073
U1000
SOCKET.MOLEX,LGA1155,CPU-LF
PCBA,MLB,ULTIMATE,3.4G,GTX,SAM,2GB,D8
639-3662
D8_COMMON,D8,CPU:4C_3P4GHZ,GPU:104GTX,FB:2G_SAMSUNG,EEEE:F0V5
IC, GPU, NV GK104 7-4-PS-A2
GPU:104GT
CRITICAL
UA000
337S4333
1
337S4333
GPU:104GT2
1
UA000
CRITICAL
IC, GPU, NV GK104 7-4-PS-A2
PCBA,MLB,ULTIMATE,3.2G,GTX,SAM,2GB,D8
639-3950
D8_COMMON,D8,CPU:4C_3P2GHZ,GPU:104GTX,FB:2G_SAMSUNG,EEEE:F49R
1
338S1113
U3600
IC,TBT,CR-4C,B1,PRQ,288 FCBGA,12X12MM
CRITICAL
1
337S4277
U1800
IC,PANTHER POINT,C1,SLJC7,PRQ,BD82Z77
CRITICAL
U3900
CRITICAL
1
343S0616
IC,BCM57766A1,ENET&SD,8X8
IC, GPU, NV GK104 8-4-PS-A2,
337S4332 CRITICAL
1
UA000
GPU:104GTX
337S3978
CRITICAL
BLCMCU:BLANK
U9700
IC,BLC MCU LPC2132FBD64/01, LQFP64
1
1
U9700
BLCMCU:PROG
CRITICAL
341S3674
IC,BLC,MCU, PRPOGRAMMED, V0204, D8
1
U3990
335S0862
CRITICAL
CIVROM:BLANK
IC,SERIAL FLASH,2MBIT, 2.7V, REF F
U3990
CRITICAL1CIVROM:PROG
341S3645
IC,ENET 1MBIT, SPI,ROM, V1.13 D8
CAMROM:BLANK
CRITICAL
1
U4202
335S0852
IC,FLASH,SPI,1MBIT,3V3
CRITICAL
U4202
1
CAMROM:PROG
341S3675
IC,CAMERA FLASH,V7228,D7/D8
335S0807
U5110
1
BOOTROM:BLANK
CRITICAL
IC,64 MBIT SPI SERIAL FLASH
SMC:PROGCRITICAL
1
U4900
341S3394
IC,PROGRMD,SMC,A3,V2.2A32,D8
IC,SMC,LX4FS1AH5BBCIGA3
338S1098
1
U4900
SMC:BLANK
CRITICAL
CRITICAL
BOOTROM:PROG
U5110
341S3673
1
IC,PROGRMD,EFI ROM,V00FC,D7/D8
335S0865
CRITICAL
TBTROM:BLANK
IC,EEPROM,SERIAL,8KB,MLP8
1
U3690
1
U3690
IC,EEPROM,CR,V14.1 (B1),D8
341S3672
CRITICAL
TBTROM:PROG
PCBA,MLB,DEV,D8.ULTIMATE
DEVELOPMENT,D8_DEVEL
085-4435
PCBA,MLB,ULTIMATE,3.4G,GT,HYN,1GB,D8
D8_COMMON,D8,CPU:4C_3P4GHZ,GPU:104GT,FB:1G_HYNIX,EEEE:F64V
639-4086
PCBA,MLB,ULTIMATE,3.2G,GT,HYN,1GB,D8
D8_COMMON,D8,CPU:4C_3P2GHZ,GPU:104GT,FB:1G_HYNIX,EEEE:F651
639-4090
CRITICAL
1
EEEE:F49PEEEE_F49P
825-7896
LABEL,MLB,2D
1
EEEE:F49R
CRITICAL825-7896
EEEE_F49R
LABEL,MLB,2D
639-3560
PCBA,MLB,ULTIMATE,3.4G,GT,SAM,1GB,D8
D8_COMMON,D8,CPU:4C_3P4GHZ,GPU:104GT,FB:1G_SAMSUNG,EEEE:DYW3
PCBA,MLB,ULTIMATE,3.2G,GT,SAM,1GB,D8
639-3949
D8_COMMON,D8,CPU:4C_3P2GHZ,GPU:104GT,FB:1G_SAMSUNG,EEEE:F49P
639-4087
PCBA,MLB,ULTIMATE,3.4G,GTX,HYN,2GB,D8
D8_COMMON,D8,CPU:4C_3P4GHZ,GPU:104GTX,FB:2G_HYNIX,EEEE:F64W
PCBA,MLB,ULTIMATE,3.2G,GTX,HYN,2GB,D8
D8_COMMON,D8,CPU:4C_3P2GHZ,GPU:104GTX,FB:2G_HYNIX,EEEE:F652
639-4091
CPU
CPU:4C_3P4GHZ
1
337S4247
IVB,SR0PK,PRQ,E1,3.4,77W,4+2,1.15,8M,LG
CRITICAL
CPU:4C_3P2GHZ
1
337S4356
CPU
IVB,SR0T8,PRQ,N1,3.2,77W,4+1,1.1,6M,LGA
CRITICAL
D8_PRODUCTION
VREFMRGN:N,PRODUCTION
D8_DEVEL
XDP_CONN,LPCPLUS,VREFMRGN:EXT,DEVEL_AUDIO,TEMPSNSDEV
D8_PROGPARTS
SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG,BLCMCU:PROG
D8_COMMON1
XDP,RSMRST:GATE,SPEAKERID,VREF:CPU,TBTHV:P12V
D8_COMMON
COMMON,ALTERNATE,D8_COMMON1,D8_PROGPARTS,D8_PRODUCTION
1
EEEE_F651
825-7896 CRITICAL
LABEL,MLB,2D
EEEE:F651
CRITICAL
EEEE_F64V
825-7896
LABEL,MLB,2D
EEEE:F64V
1
prefsb
051-9505
8.0.0
4 OF 144 4 OF 123
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
G
D
S
IN
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
IN
G
D
S
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEM 1V5_S3 LED
LED GND ISOLATION SWITCH
ALL_SYS_PWRGD LED
S5 LED
CPU 1V05_S0 LED
S4 (SLEEP) LED
GPU FBVDD LED
CPU VCORE LED
BLC_EN LED
CPU AXG LED
PCH/GPU 1V05 LED
GPU_GOOD LED VIDEO_ON LED
GPU VCORE LED
SLP_S3 LED
APN: 705S0137
64 69
120
MF-LF
DEVELOPMENT
R507
402
1K
1/16W
5%
DEVELOPMENT
LED507
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
2N7002DW-X-G
SOT-363
64 99
120
DEVELOPMENT
R502
1K
1/16W
5% MF-LF
402
DEVELOPMENT
LED502
GREEN-3.6MCD
2.0X1.25MM-SM
R512
1K
402
5% MF-LF
1/16W
PLACE_SIDE=BOTTOM
2.0X1.25MM-SM
SILK_PART=3
GREEN-3.6MCD
LED512
SOT-363
2N7002DW-X-G
MF-LF
R511
402
5%
1K
1/16W
2.0X1.25MM-SM
GREEN-3.6MCD
PLACE_SIDE=BOTTOM
LED511
SILK_PART=2
21
103
2N7002DW-X-G
SOT-363
47 65
117
R501
1/16W
5%
1K
402
MF-LF
GREEN-3.6MCD
PLACE_SIDE=BOTTOM
LED501
SILK_PART=1
2.0X1.25MM-SM
402
MF-LF
1K
R513
1/16W
5%
PLACE_SIDE=BOTTOM
SILK_PART=4
LED513
2.0X1.25MM-SM
GREEN-3.6MCD
2N7002DW-X-G
SOT-363
DEVELOPMENT
R514
402
1K
5% MF-LF
1/16W
DEVELOPMENT
LED514
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
2N7002DW-X-G
SOT-363
80
78
111
DEVELOPMENT
KMT221GLHS
SW500
SM
DEVELOPMENT
MF-LF 402
R505
5%
1K
1/16W
DEVELOPMENT
LED505
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
2N7002DW-X-G
SOT-363
64 96
115
DEVELOPMENT
1K
R506
5% 1/16W MF-LF 402
DEVELOPMENT
LED506
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
2N7002DW-X-G
SOT-363
64 99
120
DEVELOPMENT
R503
MF-LF
1/16W
1K
5%
402
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
LED503
DEVELOPMENT
2N7002DW-X-G
SOT-363
64 72
120
DEVELOPMENT
R504
402
1K
5% MF-LF
1/16W
2.0X1.25MM-SM
DEVELOPMENT
LED504
GREEN-3.6MCD
DEVELOPMENT
SOT-363
2N7002DW-X-G
15 19 28 40 47 48 64
120
DEVELOPMENT
R510
402
1/16W MF-LF
1K
5%
DEVELOPMENT
LED510
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
2.0X1.25MM-SM
LED509
GREEN-3.6MCD
DEVELOPMENT
R509
MF-LF
1/16W
5%
1K
402
DEVELOPMENT
2N7002DW-X-G
SOT-363
25 65 66
120
DEVELOPMENT
2N7002DW-X-G
SOT-363
DEVELOPMENT
R508
402
1K
5% MF-LF
1/16W
2.0X1.25MM-SM
DEVELOPMENT
LED508
GREEN-3.6MCD
66
121
SOT-363
DEVELOPMENT
2N7002DW-X-G
SYNC_DATE=08/27/2012
DEBUG LEDS
SYNC_MASTER=D8_MLB
ALL_SYS_PWRGD
PM_LED_A_PGOOD_REG_GPUCORE_S0
=PP3V3_S5_LED
GPU_GOOD
PM_LED_K_ALL_SYS_PWRGD
PM_LED_K_GPU_GOOD
=PP3V3_S4_LED =PP3V3_S0_LED =PP3V3_S0_LED
PM_LED_A_VIDEO_ON
VIDEO_ON_L
NO_TEST=TRUE
NC_Q513_1
NO_TEST=TRUE
NC_Q513_6
NC_Q513_2 NO_TEST=TRUE
PM_PGOOD_REG_P1V05_S0
=PP3V3_S0_LED
PM_PGOOD_REG_VDDQ_S3
=PP3V3_S5_LED
PM_LED_A_PGOOD_REG_VDDQ_S3
PM_LED_K_PGOOD_REG_VDDQ_S3
LED_GND
PM_LED_K_PGOOD_REG_P1V05
LED_GND
PM_LED_A_PGOOD_REG_P1V05
PM_PGOOD_REG_CPU_P1V05_S0
LED_GND
PM_SLP_S3_L
=PP3V3_S0_LED
PM_LED_K_PGOOD_CPU_P1V05_S0
LED_GND
PM_LED_K_SLP_S3
PM_LED_A_SLP_S3
REG_CPUAXG_PGOOD
LED_GND
PM_PGOOD_REG_GPUCORE_S0
PM_LED_A_CPUAXG_PGOOD
PM_LED_K_CPUAXG_PGOOD
=PP3V3_S0_LED
LED_GND
PM_LED_K_PGOOD_REG_GPUCORE_S0
=PP3V3_S5_LED
PM_PGOOD_REG_CPUCORE_S0
PM_PGOOD_REG_FBVDDQ_S0
BLC_GOOD
LED_GND
=PP3V3_S0_LED
LED_GND
PM_LED_K_BLC_GOOD
PM_LED_A_BLC_GOOD
PM_LED_K_PGOOD_CPUCORE_S0
PM_LED_A_PGOOD_CPUCORE_S0
=PP3V3_S0_LED
LED_GND
PM_LED_K_PGOOD_REG_FBVDDQ_S0
=PP3V3_S5_LED
PM_LED_A_PGOOD_REG_FBVDDQ_S0
LED_GND
=PP3V3_S4_LED
PM_LED_A_S4
PM_LED_A_PGOOD_CPU_P1V05_S0
PM_LED_A_GPU_GOOD
PM_LED_A_ALL_SYS_PWRGD
PM_LED_A_S5
=PP3V3_S5_LED
MIN_LINE_WIDTH=0.3 MM
LED_GND
MIN_NECK_WIDTH=0.2 MM
prefsb
051-9505
8.0.0
5 OF 144 5 OF 123
1
2
K
A
6
2
1
1
2
K
A
1
2
K
A
3
5
4
1
2
K
A
6
2
1
1
2
K
A
1
2
K
A
6
2
1
1
2
K
A
3
5
4
1 3
2 4
5
1
2
K
A
6
2
1
1
2
K
A
3
5
4
1
2
K
A
6
2
1
1
2
K
A
3
5
4
1
2
K
A
K
A
1
2
3
5
4
6
2
1
1
2
K
A
3
5
4
5 6
120
5 6 5 6 5 6
120
5 6
5 6
5
5 5
5 6
5
120
120
5
120
120
5 6
5
5 6
5
5 6
5
120
120
5 6
5
5 6
5
5 6
120
120 120
120
5 6
5
OUT OUT
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FILTER ADDED TO BURSTMODE_EN_L TO PASS SURGE RDAR://11059712
MLB to AC-DC Supplemental Signal Connector
MLB to AC-DC Connector
S5 Rails
On when in S5
G3 Rails
518-0389
518S0863
Always on: Keeps the PCH RTC alive
THIS IS 1.5V RAIL
THIS IS 1.5V RAIL
THIS IS 1.5V RAIL
S3 Rails
Enabled when system is in run or sleep
GPU Rails (S0)
Enabled when system is in run
Ground/Common
S0 Rails
Enabled when system is in run
Enabled when Thunderbolt cable is plugged in
Thunderbolt Rails (S0)
G3H Rails
On with AC/DC plugged in
Enabled when system has AC and is in run or sleep
S4 Rails
C603
1000PF
NP0-C0G 402
5% 25V
EMC J600.5:10MM
NP0-C0G
1000PF
C602
5% 25V
402
EMC J600.5:10MMJ600.4:10MM
10UF
25V X5R 805
10%
C601
53
122
SILK_PART=PWRSIG
M-RT-SM
504050-0791
J601
5%
10K
MF-LF
1/16W
402
R603
PLACE_NEAR=J601.3:30MM
53
122
1K
MF-LF
402
1/16W
PLACE_NEAR=J601.1:3MM
R606
5%
PLACE_NEAR=J601.1:3MM
D600
402
6.8V-100PF
48
121
5%
1/16W
R604
402
1K
PLACE_NEAR=J601.3:3MM
MF-LF
16V
0.01UF
0402
X7R-CERM
20%
C604
PLACE_NEAR=R604.2:3MM
D601
6.8V-100PF
402
PLACE_NEAR=J601.1:4MM
48 71
117
MF-LF
1K
1/16W
402
5%
R600
PLACE_NEAR=J601.7:3MM
402
6.8V-100PF
D602
PLACE_NEAR=J601.7:3MM
J600
M-RT-TH-1
CRITICAL
43045-1201
0402
0.1UF
C600
10% 16V X7R-CERM
PLACE_NEAR=R606.1:3MM
C605
10%
0.1UF
X7R-CERM 0402
16V
PLACE_NEAR=R600.1:3MM
SYNC_DATE=08/27/2012
Power Connectors/Aliases
SYNC_MASTER=D8_MLB
MAKE_BASE=TRUE
PP1V8_S0
=PP1V8_S0_PCH_VCC_VRM =PP1V8_S0_PCH_CLK
PP1V8_S0_REG
=PP1V8_S0_CPU_PLL =PP1V8_S0_PCH =PP1V8_S0_PCH_VCC_DFTERM
=PP1V5_S0_DP
PP1V5_S0_CPU_MEM_SNS =PP1V5_S0_CPU_MEM
=PP12V_S0_FAN
=PP12V_S0_HDD_PWR
=PP12V_S0_REG_CPU_P1V05_PWR
SMC_ACDC_ID
MAKE_BASE=TRUE
PP12V_S0
=PP12V_S0_PWRCTL
=PP12V_S0_REG_P1V05_PWR
=PP12V_S0_REG_CPU_VCCSA_PWR
=PP5V_S0_VRD
PP5V_S0
MAKE_BASE=TRUE
=PP12V_S0_REG_CPUCORE
=PP12V_S0_LCD
=PP12V_S0_REG_GPUCORE
=PP12V_S0_FBVDDQ_PWR
PP12V_S0_FET =PP12V_S0_AUDIO_SPKRAMP
PP5V_S4_REG =PP5V_S4_REG_VDDQ_S3
=PP3V3_S0_VRD
TSNS_ACDC_N TSNS_ACDC_P
PWR_BTN_R
PP3V3_G3
MAKE_BASE=TRUE
PP12V_G3H
MAKE_BASE=TRUE
PP3V42_G3H
MAKE_BASE=TRUE
SMC_ACDC_ID_R
SMC_ACDC_ID_R
=PP3V3_G3H_LPCPLUS
=PPVIN_G3H_SMCVREF
PP3V42_G3H_REG =PP3V3_G3H_BT
=PP12V_G3H_FET_P12V_S5
=PP3V3_G3_PCH
MAKE_BASE=TRUE
PP12V_ACDC
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC_GPIO
=PP3V3_S0_PCH_VCC_ADAC
=PP3V3_S0_PCH_STRAPS
PP12V_S5_FET
=PP3V3_TBT_CLK
PPVCCSA_S0_REG
PPCPUAXG_S0_REG
PPCPUCORE_S0_REG
=PP3V3_S0_SMBUS_TCON
PP3V3_S0_SSD_SNS
=PP3V3_S0_TBTPWRCTL
=PP3V3_S0_SMC
=PP3V3_S0_SMBUS_SMC
=PP5V_S0_HDD_PWR
=PP3V3_S0_DP =PP3V3_S0_ENET =PP3V3_S0_FAN =PP3V3_S0_GPU =PP3V3_S0_INTDPMUX =PP3V3_S0_LED
=PP3V3_S0_MEM_A_SPD
=PP3V3_S0_PCH
=PP3V3_S0_PCH_VCC
PP5V_S0_HDD_SNS =PP5V_S0_HDD
=PP3V3_S0_GPU_IFPX_PLLVDD
PP3V3_S0_FET
=PP1V05_S0_GPU_IFPEF_IOVDD =PP1V05_S0_GPU_PEX_PLLVDD
=PP1V05_S0_GPU_PEX_IOVDD
=PP1V05_S0_GPU_IFPCD_IOVDD
=PP1V05_S0_PCH_PWR =PP1V05_S0_P1V05TBTFET
PP1V05_S0_REG
=PPVCCIO_S0_CPU =PPVCCIO_S0_SMC =PPVCCIO_S0_XDP
PP1V05_S0_CPU_REG
=PPVAXG_S0_CPU
=PPVCORE_S0_CPU
=PPVCCSA_S0_CPU
PPDDRVREF_DQ_MEM_B =PPDDRVREF_DQ_MEM_B
PPDDRVREF_CA_MEM_B
=PP3V3_TBTLC_RTR
PP12V_S0_REG_CPU_P1V05_SNS
=PP1V05_S0_PCH_VCCIO_DMI
=PPDDRVREF_CA_MEM_B
PP5V_S0_FET
=PP12V_S0_REG_P1V05
=PP12V_S0_REG_VCCSA
=PPDDRVTT_S0_MEM_A =PPDDRVTT_S0_MEM_B
=PP1V5_S0_CPU_MEM_PWR
=PPVCORE_S0_GPU
=PP1V05_S0_PCH_VCCIO_USB
PPDDRVREF_DQ_MEM_A
=PP3V3_S0_MEM_B_SPD
=PP3V3_S0_AUDIO =PP3V3_S0_AUDIO_DIG
PP12V_S0_REG_CPU_VCCSA_SNS
=PP5V_S0_REG_P1V05
PP12V_S0_REG_P1V05_SNS
=PPDDRVREF_CA_MEM_A
PP1V05_S0_PCH_SNS =PP1V05_S0_PCH
=PPDDRVREF_DQ_MEM_A
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP1V05_S0_PCH_VCC_ADPLL
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCCLKDMI
=PP1V05_S0_PCH_VCC_SSC =PP1V05_S0_PCH_V_PROC_IO
=PP1V35_S0_GPU_FBVDDQ
PPGPUCORE_S0_REG
=PP3V3_S0_PCH_PM
=PP3V3_S0_P3V3TBTFET
PP1V5R1V35_S0_GPU_REG
=PP5V_S0_REG_FBVDDQ
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCC_ASW
PP1V5_S0_FET =PP1V5_S0_AUD_DIG
=PP3V3_S0_GPU_MISC =PP3V3_S0_GPU_VDD33
PP12V_S0_FBVDDQ_SNS
=PP3V3_S0_PCH_VCC_PCI
=PP3V3_S0_SDCARD
=PP3V3_S0_RSTBUF
=PP3V3_S0_SSD_PWR
=PPDDRVTT_S0_CLAMP
=PP12V_S0_REG_FBVDDQ
=PP12V_S0_BLC
=PP12V_S0_HDD
PP12V_S0_BLC_FET
PPDDRVTT_S0_LDO
PP12V_S0_HDD_SNS
=PP12V_S0_REG_CPU_P1V05
=PP3V3_S0_PWRCTL
=PP3V3_S0_PCH_VCC_HVCMOS
=PP3V3_S0_LED_SATA
MAKE_BASE=TRUE
PP5V_S0_HDD
PPDDRVTT_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPDDRVREF_DQ_MEM_A_S3
MAKE_BASE=TRUE
PP1V5_S0
MAKE_BASE=TRUE
PPVCORE_S0_GPU
MAKE_BASE=TRUE
PP12V_S0_FBVDDQ
MAKE_BASE=TRUE
PP1V05_TBTLC
PPFBVDDQ_S0_GPU
MAKE_BASE=TRUE
PP12V_S0_CPU_P1V05
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP12V_S0_VCCSA
PPDDRVREF_CA_MEM_A_S3
MAKE_BASE=TRUE
PP3V3_S0_SSD
MAKE_BASE=TRUE
PP12V_S0_BLC
MAKE_BASE=TRUE
PP12V_S0_HDD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPDDRVREF_CA_MEM_B_S3
PPVAXG_S0
MAKE_BASE=TRUE
PPVCCSA_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPVCORE_S0_CPU
MAKE_BASE=TRUE
PP1V05_S0_CPU
MAKE_BASE=TRUE
PP1V05_S0_PCH
MAKE_BASE=TRUE
PPDDRVREF_DQ_MEM_B_S3
MAKE_BASE=TRUE
PP1V05_S0
MAKE_BASE=TRUE
PP1V5_S0_CPU_MEM
MAKE_BASE=TRUE
PP12V_S0_P1V05
MAKE_BASE=TRUE
PP3V3_TBTLC
=PP3V3_TBT_PCH_GPIO
=PP3V3_S0_SENSE =PP3V3_S0_SMBUS
=PP3V3_TBTLC_FET
=PP1V05_TBTCIO_RTR
=PP1V05_TBTLC_RTR
=PP1V05_TBTLC_FET
=PP3V3_S0_BLC
=PP1V05_TBTCIO_FET
MAKE_BASE=TRUE
PP1V05_TBTCIO
MAKE_BASE=TRUE
PPVDDQ_S3
MAKE_BASE=TRUE
PPVDDQ_S3_DDR
PPDDRVTT_S3
MAKE_BASE=TRUE
=PP5V_S4_MEMRESET
PP3V3_S4_FET =PP3V3_S4_ALS =PP3V3_S4_AP_PWR
=PP3V3_S4_ENET =PP3V3_S4_LED =PP3V3_S4_MEMRESET
=PP3V3_S4_PWRCTL
=PP3V3_S4_PM
=PP3V3_S4_SENSE
=PP3V3_S4_SMBUS_SMC =PP3V3_S4_SMC
=PP3V3_S4_TBT
PP3V3_S4_AP_SNS =PP3V3_S4_AP
PP3V3_S4_ENET_FET
=PP3V3_S4_ENET_SYSCLK
=PP3V3_S4_ENET_FET
=PP3V3_S4_ENET_CLK
PPVDDQ_S3_REG
=PPVDDQ_S3_FET_VDDQ_S0
=PPVDDQ_S3_DDR_PWR
=PPVDDQ_S3_LDO_DDRVTT
PPVDDQ_S3_DDR_SNS =PPVDDQ_S3_DDR_VREF =PPVDDQ_S3_MEM_A =PPVDDQ_S3_MEM_B =PPVDDQ_S3_MEMRESET
PPDDRVTT_S3_LDO =PPDDRVTT_S3_VREFCA
PP3V3_G3_RTC =PP3V3_G3_PCH_RTC
=PP12V_G3H_PWR
PP12V_G3H_SNS =PP12V_G3H_P3V42
=PP12V_S5_REG_P3V3P5V_S5 =PP12V_S5_REG_VDDQ_S3
=PP5V_S0_REG_CPU_P1V05
=PP5V_S0_REG_CPUCORE
=PP5V_S0_LPCPLUS
=PP5V_S0_ISENSE
=PP5V_S0_PCH
=PP5V_S0_REG_P1V8 =PP5V_S0_REG_VCCSA
=PP5V_S0_AUDIO =PP5V_S0_BLC
BURSTMODE_EN_R_L
PPDDRVREF_CA_MEM_A
=PP3V3_S0_SSD
=PP3V3_S0_VRD
MAKE_BASE=TRUE
PP3V3_S0
PP5V_S4
MAKE_BASE=TRUE
PP12V_G3H_ACDC
PP3V3_S4_ENET
MAKE_BASE=TRUE
=PP3V3_S4_CAMERA
=PP5V_S4_USB
=PP5V_S4_FET_P5V_S0
=PP5V_S4_CAMERA
MAKE_BASE=TRUE
PP3V3_S4_AP
PP12V_G3H_ACDC
=PP12V_S5_PWRCTL =PPHV_SW_TBTAPWRSW
PP3V3_S5
MAKE_BASE=TRUE
=PP5V_S5_PWRCTL
PP5V_S5_LDO
=PP5V_S5_PCH
PP3V3_S5_REG =PP3V3_S5_FET_P3V3_S0 =PP3V3_S5_FET_P3V3_S4 =PP3V3_S5_SMC =PP3V3_S5_LED
=PP3V3_S5_PCH_STRAPS
=PP3V3_S5_PCH
=PP3V3_S5_PCH_VCCSUS_HDA
=PP3V3_S5_PCH_VCC_DSW
=PP3V3_S5_PCH_VCCSUS_USB
=PP3V3_S5_PWRCTL =PP3V3_S5_ROM
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S5_VRD =PP3V3_S5_XDP =PP3V3_S5_SMC_USBMUX
=PP3V3_S5_SDCARD
=PP3V3_S5_SENSE
=PPHV_SW_TBTBPWRSW =PP12V_S5_SNS
MAKE_BASE=TRUE
PP12V_S5
=PP3V3_G3H_SMC_USBMUX
=PP3V3_G3H_SMC
PP5V_S5
MAKE_BASE=TRUE
=PP3V3_G3H_RTC_D
=PP12V_G3H_FET_P12V_S0
PP12V_G3H_ACDC
PWR_BTN
BURSTMODE_EN_L
=PP3V3_S4_SMBUS
=PP3V3_S4_USB_HUB
=PP3V3_S4_TBTAPWRSW =PP3V3_S4_TBTBPWRSW
=PP3V3_S4_VREFMRGN =PP3V3_S4_AUDIO_DIG
PP3V3_S4
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GND
prefsb
051-9505
8.0.0
6 OF 144 6 OF 123
2
1
2
1
2
1
8
9
4
2 3
5 6 7
1
1
2
1 2
1
2
1 2
2
1
1
2
1 2
1
2
1 2 3 4 5 6
12
7 8
10 11
9
2
1
2
1
110
24
26
72
13 16
19
22 24
75
51
11 13 16
54
51
55
48
122
110
65
55
55
72 96
110
67
78
96
51
74
58 59
71
72
6
66 69 70 72 96 99
121
110
110
110
6
122
6
122
49
48
73
35
74
18 19
110
15 19 20 38
22 24
17
15
74
26
70
17 68
67 68
50
51
38
48 51 91
50
51
76 78
39
54
83 91 92 95 96
75
5
29 30
18 21 24
22 24
51
52
90
74
90
83 95
83
90
51
38
99
10 11 13 16 28 66
48
25
69
13 17 51 66
13 16 51 66
13 16
34
31 32
34
15 36 37 38 50
55
22 24
31 32
74
99
70
29 30
31 32
51
51 93
22 24
34
31 32
42 56 58 59 62
60
55
99
55
29 30
51
18 29 30
22 24
22 24
17
18 22 24
18 19 22 24
22 24
22 24
22 24
84 85 86 87 88 89
94
97 98
26
38
99
115
99
22 24
22 24
74
56
92
91
51
22 24
41
26
51
28
99
82
52
74
72
51
69
28 74
22 24
15 44
110
110
110
110
115
110
38
108
110
110
110
110
110
110
110
110
109
108
109
108
108
110
108
110
110
110
15
51 52 53 55
50
38
37
37
38
80
38
108
110
110
110
28
74
42
55
40
5
28
65 72 74
28
51
50
48 36 37 38 77 79
55
15 35
40
26
39 40
26
72
74
51
72
51
34
29 30
31 32
28
72
34
26
121
22
51
51
73
71
72
69
66
49
51
24
72
70
56 63
82
34
44
6
66 69 70 72 96 99
110
110
6
110
42 43
45 46
74
42
110
6
64 65 74
77
110
71
71
24
71
74
74
48
5
15
19 24 26
22 24
22 24
22 24
64 65
49
22 24
71
25
45 46
41
51
79
51
110
45
47 48 50
110
26
74
6
50
27
48 77
48 79
34
60
110
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU HEATSINK MOUNTING FEATURES
(998-5013. PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT)
998-4640 (PLATED HOLES, 10MM DIA, 12MM PAD)
HEATPIPE MTG HOLES
WIRELESS CARD MTG HOLES
998-4938 (PLATED HOLES, 1.9MM INNER DIAMETER, 4.3MM PAD)
APN: 860-1461
860-1487 (PCB STANDOFF)
SSD STANDOFF
Rear Cover
Rear Cover
998-5014 (PLATED HOLES, 4MM DRILL, 8.5MM TOP, 8MM BOT)
4MM PLATED HOLES (998-4158)
CPU Heatsink
OMIT
8P5R5-NSP
ZH0700 ZH0701
OMIT
8P5R5-NSP
OMIT
8P5R5-NSP
ZH0702 ZH0703
OMIT
8P5R5-NSP
CRITICAL
NUT0713
STDOFF-4.5OD2.2ID-5.6H-SM
CRITICAL
STDOFF-7.14OD16.45H-TH-1.5-5.2
ZH0715
ZH0718
CRITICAL
STDOFF-7.14OD16.45H-TH-1.5-5.2
5P5R1P9-4P3B-NSP
CRITICAL
ZH0722ZH0721
5P5R1P9-4P3B-NSP
CRITICAL
ZH0726
10R12
ZH0725
CRITICAL
6P0R3P2-NSP
ZH0724
6P0R3P2-NSP
CRITICAL
ZH0723
CRITICAL
6P0R3P2-NSP
CRITICAL
8P5R4P0-8P0B-NSP
ZH0717
CRITICAL
8P5R4P0-8P0B-NSP
ZH0716
ZH0714
8P5R4P0-8P0B-NSP
CRITICAL
ZH0713
8P5R4P0-8P0B-NSP
CRITICAL
6P0R3P2-NSP
ZH0720
CRITICAL
SYNC_DATE=08/27/2012
Holes/PD parts
SYNC_MASTER=D8_MLB
prefsb
051-9505
8.0.0
7 OF 144 7 OF 123
1 1 1 1
1
1
1
11
1
11
1
11
1
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1
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH Clocks
PCH PCIe
PCH USB
CPU Memory
PCH PCI
PCH Unused Display
PCH Test Points
PCH SATA
PCH and CPU FDI
PCH Miscellaneous
CPU Reserved
PCH Reserved
SYNC_MASTER=D8_MLB
Unused Signal Aliases
SYNC_DATE=08/27/2012
TP_MEM_A_DQS_P<8>
TP_MEM_A_DQ_CB<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DMI_MIDBUS_CLK100NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE2_R2D_CNX
TP_PCIE2_R2D_CN TP_PCIE2_R2D_CP
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
TP_PCH_PWM3
TP_PCH_SST
TP_PCH_RESERVE_0
NC_DP_IG_C_AUXNX
NO_TEST=TRUE
MAKE_BASE=TRUE
DP_IG_C_MLP<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE5NX
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE6P
DMI_MIDBUS_CLK100M_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DMI_MIDBUS_CLK100PX
DMI_MIDBUS_CLK100M_P
TP_PCIE_CLK100M_PE0N
TP_PCIE2_D2RP
NC_PE_TNX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
DP_IG_D_CTRL_DATA
DP_IG_D_HPD
TP_PCIE1_D2RN
TP_PCIE1_R2D_CN
TP_MEM_B_DQ_CB<7..0>
CPU_CFG<15..12>
TP_CPU_RSVD<46..19>
TP_CPU_RSVD<16..1>
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_D_D2RN
TP_SATA_E_D2RN
TP_SATA_F_R2D_CN
TP_MEM_A_DQS_N<8>
TP_PCH_PWM0
TP_HDA_SDIN2
PCH_FDI_FSYNC<1..0>
PCH_FDI_LSYNC<1..0>
PCH_FDI_INT
PCH_FDI_RX_N<7..0>
PCH_FDI_RX_P<7..0>
TP_CPU_FDI_TX_N<7..0>
TP_CPU_FDI_TX_P<7..0>
TP_SDVO_STALLP
TP_SDVO_INTN
TP_CPU_FDI_FSYNC<1..0>
TP_CPU_FDI_LSYNC<1..0>
TP_CPU_FDI_INT
TP_PCH_CL_DATA1
TP_PCH_CL_CLK1
TP_HDA_SDIN3
TP_PCH_RESERVE_8
TP_PCH_L_VDD_EN
TP_PCH_L_BKLTEN
TP_PCH_RESERVE_27
TP_PCH_RESERVE_25
DP_IG_C_MLN<3..0>
DP_IG_B_DDC_DATA
DP_IG_C_AUX_N
TP_SDVO_INTP
TP_PCH_CL_RST1
TP_PCH_PWM2
TP_PCH_PWM1
TP_PCH_RESERVE_20
TP_PCH_RESERVE_23
TP_PCH_RESERVE_7
TP_PCH_RESERVE_19
TP_PCH_RESERVE_21
TP_PCH_RESERVE_28
TP_PCH_RESERVE_24
TP_PCH_RESERVE_17
TP_PCH_RESERVE_18
TP_PCH_RESERVE_15
TP_PCH_RESERVE_16
TP_PCH_RESERVE_14
TP_PCH_RESERVE_13
TP_PCH_RESERVE_12
TP_PCH_RESERVE_10
TP_PCH_RESERVE_11
TP_PCH_RESERVE_9
TP_PCH_RESERVE_5
TP_PCH_RESERVE_6
TP_PCH_RESERVE_3
TP_PCH_RESERVE_4
TP_SDVO_TVCLKINP
DP_IG_C_AUX_P
DP_IG_C_CTRL_CLK
TP_PCH_L_BKLTCTL
TP_SDVO_STALLN
DP_IG_D_MLP<3..0>
TP_SDVO_TVCLKINN
DP_IG_D_AUXN
DP_IG_D_AUXP
DP_IG_D_MLN<3..0>
TP_SATA_F_D2RP
TP_CRT_IG_DDC_DATA
TP_CRT_IG_VSYNC
TP_CRT_IG_BLUE
TP_CRT_IG_RED
TP_CRT_IG_GREEN
TP_SATA_E_R2D_CP
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_PCH_TP20
TP_PCH_TP19
TP_PCH_TP18
TP_PCH_TP17
TP_PCH_TP16
TP_PCH_TP15
TP_PCH_TP13
TP_PCH_TP14
TP_PCH_TP12
TP_PCH_TP11
TP_PCH_TP10
TP_PCH_TP9
TP_PCH_TP8
TP_PCH_TP7
TP_PCH_TP6
TP_PCH_TP5
TP_PCH_TP4
TP_PCH_TP3
TP_SATA_D_D2RP
TP_PCH_TP2
TP_SATA_C_R2D_CP
TP_SATA_E_D2RP
DP_IG_C_HPD
DP_IG_D_CTRL_CLK
DP_IG_C_CTRL_DATA
TP_LPC_DREQ0_L
TP_PCH_INIT3V3_L
TP_HDA_SDIN1
TP_CRT_IG_HSYNC
TP_SATA_F_R2D_CP
TP_PCH_RESERVE_22
TP_PCH_RESERVE_26
TP_SATA_E_R2D_CN
TP_PCH_TP1
TP_SATA_F_D2RN
DP_IG_B_DDC_CLK
TP_PCI_AD<31..0>
TP_PCI_C_BE_L<3..0>
TP_PCI_PAR
TP_PCI_RESET_L
TP_PCH_PCI_GNT0_L
TP_PCH_RESERVE_2
TP_PCH_RESERVE_1
DP_IG_B_AUX_P
DP_IG_B_MLN<3..0>
DP_IG_B_MLP<3..0>TP_MEM_B_DQS_N<8>
TP_MEM_B_DQS_P<8>
DP_IG_B_HPD
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE7P
TP_PE_TX_N<3..0>
TP_PE_RX_N<3..0>
TP_PE_TX_P<3..0>
TP_PE_RX_P<3..0>
USB_PCH_4_P
USB_PCH_6_N
USB_PCH_6_P
USB_PCH_11_P
USB_PCH_12_P
USB_PCH_12_N
USB_PCH_13_P
USB_PCH_13_N
TP_PCH_CLKOUT_DPP
TP_PCIE_CLK100M_PE7N
TP_PCIE2_D2RN
TP_PCIE1_D2RP
TP_CRT_IG_DDC_CLK
TP_PCIE1_R2D_CP
DP_IG_B_AUX_N
NO_TEST=TRUE
NC_PCIE2_R2D_PNX
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE1_D2RNX
NO_TEST=TRUE
NC_MEM_B_DQSNX<8>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_RSVD<46..19>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_6
MAKE_BASE=TRUE
NC_SATA_C_R2D_CNX
NO_TEST=TRUE
NC_SATA_D_R2D_CNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_PWM0
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_HDA_SDIN3
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_INT
NC_SDVO_TVCLKINNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_FDI_FSYNC<1..0>
MAKE_BASE=TRUE
NC_DP_IG_D_AUXPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_FDI_LSYNC<1..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_FDI_FSYNC<1..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_FDI_RPX<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_FDI_RNX<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_FDI_TPX<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_L_BKLTEN
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_L_VDD_EN
NC_PCI_CLK33M_OUT2
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_CL_CLK1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_L_BKLTCTL
NO_TEST=TRUE
NC_PCI_CLK33M_OUT3
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_CL_RST1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_CL_DATA1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_SST
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_PWM3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_PWM2
NO_TEST=TRUE
NC_PCH_PWM1
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_AUXNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_MLPX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_LSYNC<1..0>
MAKE_BASE=TRUE
NC_CPU_FDI_INT
NO_TEST=TRUE
NC_CPU_FDI_TNX<7..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_17
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_18
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_14
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_13
MAKE_BASE=TRUE
NC_PCH_RESERVE_12
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_10
NC_PCH_RESERVE_11
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_9
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_8
MAKE_BASE=TRUE
NC_PCH_RESERVE_7
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_5
MAKE_BASE=TRUE
NC_PCH_RESERVE_3
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_4
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_0
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_1
NC_SDVO_STALLNX
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_HPD
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_HPD
NC_DP_IG_D_MLNX<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_CTRL_DATA
NC_DP_IG_C_MLPX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_MLNX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_F_D2RPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_F_D2RNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_F_R2D_CPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_CTRL_CLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_MLPX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_MLNX<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_DDC_CLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
NC_CRT_IG_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_RED
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_GREEN
NC_SATA_E_D2RNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_E_R2D_CPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_D_R2D_CPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_C_D2RNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_C_D2RPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP19
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP18
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP17
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP16
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP15
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP13
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP14
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP12
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP11
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP10
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP9
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP8
MAKE_BASE=TRUE
NC_PCH_TP7
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP6
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP5
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP4
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_TP1
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_TP2
MAKE_BASE=TRUE
NC_PCH_TP3
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_DDC_DATA
NC_DP_IG_C_AUXPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_HPD
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_AUXPX
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_AD<31..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCI_PAR
MAKE_BASE=TRUE
NC_PCI_C_BE_L<3..0>
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCI_RESET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_GNT0_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LPC_DREQ0_L
NC_PCH_INIT3V3_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_HDA_SDIN1
MAKE_BASE=TRUE
NC_HDA_SDIN2
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_RSVD<16..1>
NC_DP_IG_D_CTRL_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_STALLPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SDVO_INTNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_DQ_CB<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MEM_B_DQ_CB<7..0>
NC_SDVO_TVCLKINPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_INTPX
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_27
NO_TEST=TRUE
NC_PCH_RESERVE_16
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_15
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_E_D2RPX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_F_R2D_CNX
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_19
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_20
MAKE_BASE=TRUE
NC_PCH_RESERVE_21
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_22
MAKE_BASE=TRUE
NC_SATA_E_R2D_CNX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_23
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_24
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_25
NO_TEST=TRUE
NC_PCH_RESERVE_26
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_28
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP20
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_CTRL_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_MEM_A_DQSNX<8>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MEM_A_DQSPX<8>
NC_DP_IG_B_AUXNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_C_R2D_CPX
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_CPU_CFG<15..12>
MAKE_BASE=TRUE
NC_MEM_B_DQSPX<8>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE4PX
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE4NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE5PX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6NX
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6PX
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7PX
NC_PCIE_CLK100M_PE7NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_RNX<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_TPX<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_RPX<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_4NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_4PX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_5PX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_5NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_6NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_6PX
NC_USB_PCH_11PX
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_11NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_12PX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_12NX
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_13PX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_13NX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_CLKOUT_DPNX
NC_PCIE2_D2RNX
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE2_D2RPX
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE1_D2RPX
NC_PCIE1_R2D_CNX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE1_R2D_CPX
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE5P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_CLKOUT_DPPX
TP_PCH_CLKOUT_DPN
USB_PCH_4_N
USB_PCH_5_N
USB_PCH_5_P
USB_PCH_11_N
MAKE_BASE=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO66_CLKOUTFLEX2
NO_TEST=TRUE
NC_PCH_GPIO67_CLKOUTFLEX3
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCH_GPIO67_CLKOUTFLEX3
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO64_CLKOUTFLEX0
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_PCH_GPIO64_CLKOUTFLEX0
PCH_CLK25M_XTALOUT
MAKE_BASE=TRUE
NC_PCH_CLK25M_XTALOUT
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE0PX
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE0NX
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE0P
prefsb
051-9505
8.0.0
8 OF 144 8 OF 123
12
12
18
18
20
20
21
21
19
19
18
21
18
18
18
18
19
19
18
18
12
10
10
10
18
18
18
18
18
12
21
18
19
19
19
19
19
10
10
19
19
10
10
10
18
18
18
19
18
18
19
19
19
19
19
19
18
21
21
19
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21
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18
21 18
18
19
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18
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18
21
18
19
20
20
20
20
20
19
19
19
19
19 12
12
19
21
21
10
10
10
10
20
20
20
20
20
20
20
20
18
21
18
18
19
18
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20
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18
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ALIASES (BLANK)
Signal Aliases
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
prefsb
051-9505
8.0.0
9 OF 144 9 OF 123
IN IN IN IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN IN IN IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT
OUT
OUT OUT OUT OUT OUT
OUT OUT OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DMI_TX_1*
PE_TX_3*
PE_TX_3
PE_TX_2*
PE_TX_2
PE_TX_1*
PE_TX_1
PE_TX_0*
PE_TX_0
PE_RX_3*
PE_RX_3
PE_RX_2*
PE_RX_2
PE_RX_1*
PE_RX_1
PE_RX_0*
PE_RX_0
PEG_TX_15*
PEG_TX_15
PEG_TX_14*
PEG_TX_14
PEG_TX_13*
PEG_TX_13
PEG_TX_12*
PEG_TX_12
PEG_TX_11*
PEG_TX_11
PEG_TX_10*
PEG_TX_10
PEG_TX_9*
PEG_TX_9
PEG_TX_8*
PEG_TX_8
PEG_TX_7*
PEG_TX_7
PEG_TX_6
PEG_TX_5*
PEG_TX_5
PEG_TX_4*
PEG_TX_4
PEG_TX_3*
PEG_TX_3
PEG_TX_2*
PEG_TX_2
PEG_TX_1*
PEG_TX_1
PEG_TX_0*
PEG_TX_0
PEG_RX_15*
PEG_RX_15
PEG_RX_13*
PEG_RX_12
PEG_RX_11*
PEG_RX_11
PEG_RX_10
PEG_RX_9
PEG_RX_8
PEG_RX_7
PEG_RX_6
PEG_RX_5
PEG_RX_4*
PEG_RX_4
PEG_RX_3*
PEG_RX_3
PEG_RX_2
PEG_RX_1*
PEG_RX_0
FDI_TX_7*
FDI_TX_7
FDI_TX_6*
FDI_TX_6
FDI_TX_5*
FDI_TX_5
FDI_TX_4*
FDI_TX_4
FDI_TX_3*
FDI_TX_3
FDI_TX_2*
FDI_TX_2
FDI_TX_1*
FDI_TX_1
FDI_TX_0*
FDI_TX_0
FDI_LSYNC_1
FDI_LSYNC_0
FDI_FSYNC_1
FDI_FSYNC_0
DMI_TX_3*
DMI_TX_3
DMI_TX_2*
DMI_TX_2
DMI_TX_1
DMI_TX_0*
DMI_TX_0
DMI_RX_3*
DMI_RX_3
DMI_RX_2*
DMI_RX_2
DMI_RX_1
DMI_RX_0*
FDI_COMPIO FDI_ICOMPO
FDI_INT
PEG_COMPI
PEG_ICOMPO
PEG_RX_1
PEG_RX_14*
PEG_RX_12*
PEG_RX_6*
PEG_RX_13 PEG_RX_14
PEG_RCOMPO
PEG_RX_10*
PEG_RX_9*
PEG_RX_8*
PEG_RX_7*
PEG_RX_2*
PEG_RX_0*
PEG_RX_5*
PEG_TX_6*
DMI_RX_0
DMI_RX_1*
SYM 1 OF 10
FLEXIBLE DISPLAY INTERFACE
PCI EXPRESS -- GRAPHICS
DMI
PCI EXPRESS
RSVD_NCTF_AV1 RSVD_NCTF_AW2 RSVD_NCTF_AY3
RSVD_NCTF_B39
NCTF_AW38
NCTF_AU40
NCTF_D1
NCTF_C2
NCTF_A38
CFG_8
RSVD_J34
RSVD_J33
RSVD_J31
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7
CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17
RSVD_K9 RSVD_K31 RSVD_K34 RSVD_L9 RSVD_L31 RSVD_L33 RSVD_L34 RSVD_M34 RSVD_N33 RSVD_N34
RSVD_P35 RSVD_P37 RSVD_P39 RSVD_R34 RSVD_R36 RSVD_R38 RSVD_R40 RSVD_AB6
RSVD_AB7 RSVD_AD34 RSVD_AD35 RSVD_AD37
RSVD_AE6
RSVD_AF4
RSVD_AG4 RSVD_AJ11 RSVD_AJ29 RSVD_AJ30 RSVD_AJ31 RSVD_AN20 RSVD_AP20 RSVD_AT11 RSVD_AT14 RSVD_AU10 RSVD_AV34 RSVD_AW34 RSVD_AY10
RSVD_J9
RSVD_H8
RSVD_H7
RSVD_C38
RSVD_D38
RSVD_C39
SYM 5 OF 10
RESERVED
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(Available for Workstation only)
CFG [6:5] PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = 1 X8, 2 X4
CFG [3] PCIE STATIC X4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [1:0] RESERVED CONFIGURATION LANE
( IVY BRIDGE EDS #473717 TABLE 6-5 )
CFG [17:7] RESERVED CONFIGURATION LANE
CFG [4] RESERVED CONFIGURATION LANE
INTEL SUGGESTS TO KEEP THESE TPS
ThermDA
ThermDC
(Unused)
ROUTE B5 TO R1010.1 AS A SEPERATE 12 MIL TRACE.
SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1
CFG [2] PCIE STATIC X16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
19
103
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
1/16W
R1010
PLACE_NEAR=U1000.B4:12.7MM
1%
MF-LF
402
25
103
25
103
8
8
8
8
25
103
25
103
25
103
25
103
25
103
15 25
103
15 25
103
25
103
15 25
103
15 25
103
25
103
25
103
U1000
OMIT_TABLE
IVY-BRIDGE
BGA-SKT-K70
U1000
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
R1011
0
5%
402
1/16W MF-LF
PLACE_NEAR=U1000.AE2:6.3MM
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
CPU DMI/PEG/FDI/RSVD
CPU_FDI_COMPIO
TP_PE_TX_P<3>
TP_PE_TX_P<2>
TP_CPU_FDI_TX_N<2>
PEG_D2R_C_P<5>
CPU_PEG_COMP
PEG_D2R_C_N<1> PEG_D2R_C_N<2> PEG_D2R_C_N<3>
=PPVCCIO_S0_CPU
PEG_D2R_C_P<3>
PEG_D2R_C_N<12>
PEG_D2R_C_N<11>
PEG_D2R_C_N<5>
CPU_CFG<7>
TP_PE_RX_P<1>
TP_CPU_FDI_TX_P<7>
TP_CPU_FDI_TX_P<2>
TP_PE_RX_N<0>
TP_PE_RX_N<3>
TP_PE_RX_P<2>
PEG_R2D_P<14>
TP_CPU_FDI_TX_P<4>
PEG_D2R_C_P<14>
TP_PE_TX_P<0>
DMI_S2N_N<3>
DMI_S2N_N<0>
PEG_R2D_P<11>
PEG_R2D_P<13>
PEG_R2D_P<7>
PEG_D2R_C_N<15>
PEG_D2R_C_P<0>
DMI_S2N_P<2>
DMI_N2S_P<2>
PEG_D2R_C_N<8>
CPU_CFG<15>
PEG_D2R_C_N<4>
CPU_CFG<0>
CPU_CFG<3>
TP_CPU_RSVD<16>
PEG_D2R_C_N<14>
PEG_D2R_C_P<2>
PEG_D2R_C_N<6>
DMI_S2N_P<1>
TP_CPU_FDI_TX_N<6>
PEG_R2D_P<0>
DMI_N2S_N<0>
TP_CPU_FDI_TX_N<3>
TP_CPU_RSVD<30>
DMI_N2S_N<2>
PEG_D2R_C_N<13>
TP_CPU_FDI_FSYNC<1>
TP_PE_RX_P<0>
TP_PE_TX_N<0>
DMI_N2S_P<1>
DMI_N2S_N<1>
PEG_R2D_P<3>
PEG_R2D_P<2>
PEG_R2D_P<1>
DMI_N2S_P<3>
PEG_R2D_N<0>
PEG_D2R_C_P<7>
PEG_D2R_C_P<15>
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<14>
DMI_S2N_N<1>
DMI_S2N_P<3>
TP_CPU_FDI_LSYNC<0>
TP_CPU_FDI_TX_P<5>
PEG_R2D_P<12>
PEG_R2D_N<10>
TP_CPU_FDI_TX_P<0>
TP_PE_TX_N<2>
CPU_CFG<12>
CPU_CFG<9>
CPU_CFG<6>
TP_CPU_RSVD<8>
PEG_D2R_C_P<11>
PEG_R2D_P<5>
PEG_R2D_P<8>
PEG_R2D_N<14>
TP_PE_TX_P<1>
TP_CPU_RSVD<2> TP_CPU_RSVD<3>
TP_CPU_RSVD<1>
TP_CPU_RSVD<4>
TP_CPU_RSVD<46>
TP_CPU_RSVD<40>
TP_CPU_RSVD<39>
TP_CPU_RSVD<38>
TP_CPU_RSVD<37>
TP_CPU_RSVD<35>
TP_CPU_RSVD<34>
TP_CPU_RSVD<33>
TP_CPU_RSVD<32>
TP_CPU_RSVD<31>
TP_CPU_RSVD<28>
TP_CPU_RSVD<27>
TP_CPU_RSVD<25>
TP_CPU_RSVD<24>
TP_CPU_RSVD<23>
TP_CPU_RSVD<22>
TP_CPU_RSVD<21>
TP_CPU_RSVD<20>
CPU_CFG<11>
CPU_CFG<10>
CPU_CFG<4>
TP_CPU_RSVD<7>
TP_CPU_RSVD<9>
TP_CPU_NCTF<1> TP_CPU_NCTF<2>
TP_CPU_NCTF<4>
CPU_CFG<13>
CPU_CFG<8>
TP_CPU_RSVD<15>
TP_CPU_RSVD<14>
TP_CPU_RSVD<13>
TP_CPU_RSVD<12>
TP_CPU_RSVD<10>
TP_CPU_RSVD<5> TP_CPU_RSVD<6>
TP_CPU_RSVD<26>
TP_PE_TX_N<1>
TP_CPU_FDI_TX_P<1>
DMI_S2N_P<0>
TP_CPU_RSVD<36>
TP_CPU_RSVD<43>
TP_CPU_NCTF<3>
TP_CPU_NCTF<5>
TP_CPU_RSVD<29>
PEG_R2D_P<10>
PEG_R2D_P<9>
TP_CPU_RSVD<19>
TP_CPU_RSVD<45>
TP_CPU_RSVD_NCTF<4>
TP_CPU_RSVD_NCTF<3>
TP_CPU_RSVD_NCTF<2>
TP_CPU_RSVD_NCTF<1>
TP_CPU_RSVD<44>
TP_CPU_RSVD<42>
TP_CPU_RSVD<41>
CPU_CFG<2>
CPU_CFG<1>
DMI_N2S_N<3>
TP_CPU_FDI_TX_P<3>
TP_CPU_FDI_TX_N<4>
PEG_R2D_N<1>
TP_PE_RX_P<3>
TP_CPU_FDI_INT
TP_CPU_FDI_TX_N<0> TP_CPU_FDI_TX_N<1>
PEG_D2R_C_N<9> PEG_D2R_C_N<10>
PEG_R2D_N<2>
PEG_R2D_N<15>
PEG_R2D_P<6>
TP_CPU_FDI_LSYNC<1>
TP_CPU_FDI_FSYNC<0>
TP_CPU_FDI_TX_P<6>
PEG_D2R_C_P<12>
PEG_R2D_N<5>
TP_CPU_RSVD<11>
PEG_D2R_C_N<7>
TP_CPU_FDI_TX_N<5>
PEG_D2R_C_P<4>
PEG_D2R_C_P<1>
PEG_R2D_N<4>
PEG_R2D_P<4>
TP_PE_TX_N<3>
PEG_R2D_P<15>
PEG_R2D_N<13>
PEG_R2D_N<8>
PEG_R2D_N<6>
DMI_N2S_P<0>
PEG_R2D_N<12>
PEG_R2D_N<11>
PEG_R2D_N<9>
PEG_D2R_C_P<6>
PEG_D2R_C_P<9>
PEG_D2R_C_P<8>
DMI_S2N_N<2>
PEG_R2D_N<3>
PEG_R2D_N<7>
TP_CPU_FDI_TX_N<7>
PEG_D2R_C_P<10>
PEG_D2R_C_P<13>
NO_TEST=TRUE
NC_SNS_CPU_THERMDP
NO_TEST=TRUE
NC_SNS_CPU_THERMDN
CPU_CFG<5>
PEG_D2R_C_N<0>
TP_PE_RX_N<2>
TP_PE_RX_N<1>
prefsb
051-9505
8.0.0
10 OF 144 10 OF 123
1 2
W8
U6
U5
R5
R6
T8
T7
P7
P8
U1
U2
T3
T4
R1
R2
P4
P3
N6
N5
L5
L6
M7
M8
J6
J5
K8
K7
G6
G5
G9
G10
F7
F8
E5
E6
D3
D7
D8
J13
J14
F11
F12
G13
G14
E13
E14
C14
C13
N2
N1
L2
K3
J2
J1
H3
G2
F4
E2
A5
C6
B7
B8
E9
E10
C10
D11
B11
AG1
AG2
AF2
AF3
AE8
AE7
AD6
AD7
AD3
AD4
AD1
AD2
AC3
AC2
AC7
AC8
AE4
AC4
AE5
AC5
AA8
AA7
Y7
Y6
W7
V6
V7
AA5
AA4
Y4
Y3
V3
W4
AE2 AE1
AG3
B4 B5
D12
M4
K4
A6
L1 M3
C4
H4
G1
F3
E1
C9
B12
C5
C3
W5
V4
AV1 AW2 AY3 B39
AW38
AU40
D1
C2
A38
J38
J34
J33
J31
H36 J36 J37 K36 L36 N35 L37 M36
L35 M38 N36 N38 N39 N37 N40 G37 G36
K9 K31 K34
L9 L31 L33 L34 M34 N33 N34
P35 P37 P39 R34 R36 R38 R40 AB6 AB7 AD34 AD35 AD37 AE6 AF4 AG4 AJ11 AJ29 AJ30 AJ31 AN20 AP20 AT11 AT14 AU10 AV34 AW34 AY10
J9
H8
H7
C38
D38
C39
1
2
103
8
8
8
102
6
11 13 16 28 66
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BI BI BI BI BI
IN
IN
OUT OUT
OUT
IN IN
OUT
OUT
BI
BI
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SM_VREF
SM_DRAMRST*
SM_DRAMPWROK
PM_SYNC
PREQ*
TMS
TRST*
TDI TDO
DBR*
BPM[0]* BPM[1]* BPM[2]* BPM[3]* BPM[4]* BPM[5]* BPM[6]* BPM[7]*
TCK
PRDY*
BCLK_ITP
BCLK_0
BCLK_ITP*
BCLK_0*
UNCOREPWRGOOD
SKTOCC*
RESET*
THERMTRIP*
CATERR*
PECI
PROCHOT*
PROC_SEL
SYM 2 OF 10
CLOCKS
THERMAL
DDR3 MISC
PWR MGMT
JTAG & BPM
OUT
IN
OUT
IN IN
IN
OUT
IN
IN IN
IN
IN
OUT
OUT
BI BI BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BASED ON INTEL MOBILE SOLUTION
FROM PCH
25
103
25
103
25
103
25
103
25
103
1K
MF-LF 402
5% 1/16W
R1111
19 28
103
21 25 28
103
34
110
34
110
28
103
15
103
15
103
19
103
48
103
47 48 66
103
21 47 48
103
MF-LF
PLACE_NEAR=U1000.F36:50mm
75
402
5%
1/16W
R1124
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
MF-LF 402
1K
1% 1/16W
R1141
1K
MF-LF 402
1% 1/16W
R1140
0402
C1140
0.1UF
16V X7R-CERM
10%
48
103
402
1/16W
0
5%
MF-LF
R1102
51
MF-LF
402
5%
1/16W
R1101
25
103
25
103
25
103
25
103
25
103
25
103
25
103
200
MF-LF
402
1%
1/16W
R1120
1/16W
1%
402
MF-LF
130
R1121
18
103
18
103
19
103
43
MF-LF
5%
1/16W
402
R1125
26
103
64
103
25
103
25
103
25
103
25
103
CPU CLOCK/MISC/JTAG
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
CPU_DDR_VREF
=PP1V5_S0_CPU_MEM
DMI_CLK100M_CPU_N
ITPCPU_CLK100M_N DMI_CLK100M_CPU_P
ITPCPU_CLK100M_P
XDP_CPU_PRDY_L
XDP_CPU_TCK
XDP_BPM_L<7>
XDP_BPM_L<6>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
XDP_DBRESET_L
XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TRST_L
XDP_CPU_TMS
XDP_CPU_PREQ_L
=PP1V5_S0_CPU_MEM
=PPVCCIO_S0_CPU
PM_MEM_PWRGD_R
CPU_DDR_VREF
PM_MEM_PWRGD
CPU_RESET_L
CPU_DIMM_VREF_DAC_A
CPU_DIMM_VREF_DAC_B
CPU_MEM_RESET_L
PLT_RESET_LS1V05_L
PM_SYNC CPU_PWRGD
CPU_THRMTRIP_L
CPU_PECI
CPU_CATERR_L
CPU_PROC_SEL
CPU_SKTOCC_L
CPU_PROCHOT_R_L
=PPVCCIO_S0_CPU
CPU_PROCHOT_L
prefsb
051-9505
8.0.0
11 OF 144 11 OF 123
1
2
1
2
AH4
AH1
AJ22
AW18
AJ19
E38
K40
L38 J39
L40 L39
E39
H40 H38 G38 G40 G39 F38 E40 F40
M40
K38
C40
W2
D40
W1
J40
AJ33
F36
G35
E37
J35
H34
K32
1
2
1
2
2
1
12
1
2
1
2
12
12
11
110
6
11 13 16
6
11 13 16
6
10 11 13 16 28 66
103
11
110
103
103
6
10 11 13 16 28 66
BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
OUT
OUT OUT
OUT
OUT OUT
OUT OUT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT OUT
OUT
OUT OUT
OUT OUT
BI BI BI BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT OUT
OUT
OUT
OUT OUT
SA_DQ_32 SA_DQ_33
SA_DQS_8*
SA_BS_2
SA_CAS*
SA_BS_1
SA_BS_0
SA_DQ_63
SA_DQ_62
SA_DQ_61
SA_DQ_60
SA_DQ_9
SA_CK_1
SA_ODT_2
SA_ODT_1
SA_ODT_0
SA_RAS* SA_WE*
SA_CK_0
SA_CK_0*
SA_CK_1*
SA_CK_2
SA_CK_2*
SA_CK_3
SA_CK_3*
SA_CKE_0
SA_CKE_1
SA_CKE_2
SA_CKE_3
SA_CS_0* SA_CS_1* SA_CS_2* SA_CS_3*
SA_DQ_0 SA_DQ_1
SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19
SA_DQ_2
SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29
SA_DQ_3
SA_DQ_30 SA_DQ_31
SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39
SA_DQ_4
SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49
SA_DQ_5
SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59
SA_DQ_6 SA_DQ_7 SA_DQ_8
SA_DQS_0
SA_DQS_0*
SA_DQS_1
SA_DQS_1*
SA_DQS_2
SA_DQS_2*
SA_DQS_3
SA_DQS_3*
SA_DQS_4
SA_DQS_4*
SA_DQS_5
SA_DQS_5*
SA_DQS_6
SA_DQS_6*
SA_DQS_7
SA_DQS_7*
SA_DQS_8
SA_ECC_CB_0 SA_ECC_CB_1 SA_ECC_CB_2 SA_ECC_CB_3 SA_ECC_CB_4 SA_ECC_CB_5 SA_ECC_CB_6 SA_ECC_CB_7
SA_MA_0 SA_MA_1
SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15
SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9
SA_ODT_3
SYM 3 OF 10
DDR SYSTEM MEMORY A
SB_CK_1*
SB_DQS_3*
SB_DQ_33
SB_DQS_4
SB_DQS_2
SB_DQS_8*
SB_CKE_3
SB_CS_0* SB_CS_1* SB_CS_2* SB_CS_3*
SB_CAS* SB_RAS* SB_WE*
SB_BS_0 SB_BS_1 SB_BS_2
SB_CK_0
SB_CK_0*
SB_CK_1
SB_CK_2
SB_CK_2*
SB_CK_3
SB_CK_3*
SB_CKE_0
SB_CKE_1
SB_CKE_2
SB_DQ_0 SB_DQ_1
SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19
SB_DQ_2
SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29
SB_DQ_3
SB_DQ_30 SB_DQ_31 SB_DQ_32
SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39
SB_DQ_4
SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49
SB_DQ_5
SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59
SB_DQ_6
SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_DQ_7 SB_DQ_8 SB_DQ_9
SB_DQS_0
SB_DQS_0*
SB_DQS_1
SB_DQS_1* SB_DQS_2*
SB_DQS_3
SB_DQS_4*
SB_DQS_5
SB_DQS_5*
SB_DQS_6
SB_DQS_6*
SB_DQS_7
SB_DQS_7*
SB_DQS_8
SB_ECC_CB_0 SB_ECC_CB_1 SB_ECC_CB_2 SB_ECC_CB_3 SB_ECC_CB_4 SB_ECC_CB_5 SB_ECC_CB_6 SB_ECC_CB_7
SB_MA_0 SB_MA_1
SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15
SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9
SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3
SYM 4 OF 10
DDR SYSTEM MEMORY B
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29 30
101
29
101
29
101
29
101
29
101
29
101
29
101
29
101
29
101
29
101
29
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31
101
31
101
31
101
31
101
31
101
31
101
31
101
31
101
31
101
31
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
33
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
31 32
101
30
101
30
101
30
101
30
101
30
101
30
101
30
101
30
101
30
101
30
101
32
101
32
101
32
101
32
101
32
101
32
101
32
101
32
101
32
101
32
101
29 30
101
31 32
101
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
CPU DDR3 INTERFACES
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
MEM_B_DQ<53>
MEM_A_CLK_P<0>
MEM_A_DQ<8>
MEM_A_DQ<6>
MEM_A_DQS_P<3>
MEM_A_DQ<11> MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_A_DQ<9>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<10>
MEM_A_ODT<3>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<1>
MEM_A_A<0>
TP_MEM_A_DQ_CB<7>
TP_MEM_A_DQ_CB<6>
TP_MEM_A_DQ_CB<5>
TP_MEM_A_DQ_CB<4>
TP_MEM_A_DQ_CB<3>
TP_MEM_A_DQ_CB<2>
TP_MEM_A_DQ_CB<1>
TP_MEM_A_DQ_CB<0>
TP_MEM_A_DQS_P<8>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQ<7>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_CS_L<3>
MEM_A_CS_L<2>
MEM_A_CS_L<0>
MEM_A_CKE<0>
MEM_A_CLK_P<3>
MEM_A_CLK_N<0>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_ODT<0> MEM_A_ODT<1>
MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>
MEM_A_BA<0> MEM_A_BA<1>
MEM_A_CAS_L
MEM_A_BA<2>
TP_MEM_A_DQS_N<8>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_B_ODT<3>
MEM_B_ODT<2>
MEM_B_ODT<1>
MEM_B_ODT<0>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<1>
MEM_B_A<0>
TP_MEM_B_DQ_CB<7>
TP_MEM_B_DQ_CB<6>
TP_MEM_B_DQ_CB<5>
TP_MEM_B_DQ_CB<4>
TP_MEM_B_DQ_CB<3>
TP_MEM_B_DQ_CB<2>
TP_MEM_B_DQ_CB<1>
TP_MEM_B_DQ_CB<0>
TP_MEM_B_DQS_P<8>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<6>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<5>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<4>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<3>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<2>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_CKE<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_CAS_L
TP_MEM_B_DQS_N<8>
MEM_B_DQS_P<2>
MEM_B_DQS_P<4>
MEM_B_DQ<33>
MEM_B_DQS_N<3>
MEM_B_CLK_N<1>
MEM_B_DQ<60>
MEM_B_DQS_N<1>
MEM_A_DQ<19>
MEM_A_DQ<26>
MEM_B_CLK_P<2>
MEM_A_CLK_N<2>
MEM_A_CLK_P<2>
MEM_A_CKE<3>
MEM_A_CLK_N<3>
MEM_A_CKE<2>
MEM_A_CLK_P<1> MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<2>
MEM_B_DQ<20>
MEM_B_CS_L<3>
MEM_B_CS_L<2>
MEM_B_CS_L<1>
MEM_B_CKE<2>
MEM_B_CLK_N<3>
MEM_B_CKE<3>
MEM_B_CS_L<0>
MEM_B_CLK_P<1>
MEM_B_CKE<1>
MEM_B_CLK_N<2>
MEM_B_CLK_P<3>
prefsb
051-9505
8.0.0
12 OF 144 12 OF 123
AU35 AW37
AV12
AV20
AV30
AW28
AY29
AE40
AE39
AG38
AG39
AN4
AU24
AU30
AU32
AV31
AU28 AW29
AY25 AW25
AU25
AW27 AY27
AV26 AW26
AV19
AT19
AU18
AV18
AU29 AV32 AW30 AU33
AJ3 AJ4
AR3 AR4 AN2 AN3 AR2 AR1 AV2 AW3 AV5 AW5
AL3
AU2 AU3 AU5 AY5 AY7 AU7 AV9 AU9 AV7 AW7
AL4
AW9 AY9
AU39 AU36 AW35 AY36 AU38 AU37
AJ2
AR40 AR37 AN38 AN37 AR39 AR38 AN39 AN40 AL40 AL37
AJ1
AJ38 AJ37 AL39 AL38 AJ39 AJ40 AG40 AG37 AE38 AE37
AL2 AL1 AN1
AK3
AK2
AP3
AP2
AW4
AV4
AV8
AW8
AV37
AV36
AP38
AP39
AK38
AK39
AF38
AF39
AV13
AU12 AU14 AW13 AY13 AU13 AU11 AY12 AW12
AV27 AY24
AV28 AU21 AT21 AW32 AU20 AT20
AW24 AW23 AV23 AT24 AT23 AU22 AV22 AT22
AW33
AK20
AN12
AR29
AN29
AR8
AN15
AV15
AN25 AN26 AL25 AT26
AK25 AP24 AR25
AP23 AM24 AW17
AL21 AL22
AL20
AL23 AM22
AP21 AN21
AU16
AY15
AW15
AG7
AG8
AM10 AL10
AL6
AM6
AL9
AM9
AP7
AR7 AP10 AR10
AJ9
AP6
AR6
AP9
AR9 AM12 AM13 AR13 AP13 AL12 AL13
AJ8
AR12 AP12 AR28
AL28 AL29 AP28 AP29 AM28 AM29
AG5
AP32 AP31 AP35 AP34 AR32 AR31 AR35 AR34 AM32 AM31
AG6
AL35 AL32 AM34 AL31 AM35 AL34 AH35 AH34 AE34 AE35
AJ6
AJ35 AJ34 AF33 AF35
AJ7
AL7
AM7
AH7
AH6
AM8
AL8 AP8
AN13
AN28
AP33
AR33
AL33
AM33
AG35
AG34
AN16
AL16 AM16 AP16 AR16 AL15 AM15 AR15 AP15
AK24 AM20
AN23 AU17 AT18 AR26 AY16 AV16
AM19 AK18 AP19 AP18 AM18 AL18 AN18 AY17
AL26 AP26 AM26 AK26
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
VCCIO_31
VCCIO_44
VCCIO_SEL
VCCIO_45
VCCIO_30
VSSAXG_SENSE
VCCAXG_SENSE
VSSIO_SENSE
VCCIO_SENSE
VCC_024
VCC_038
VCCIO_42
VCCIO_29
VCCIO_28
VCCIO_09
VCC_001 VCC_002 VCC_003 VCC_004
VCCIO_27
VCC_012
VCC_015
VCC_005 VCC_006 VCC_007 VCC_008 VCC_009 VCC_010 VCC_011
VCC_013 VCC_014
VCC_016 VCC_017 VCC_018
VCC_020 VCC_021 VCC_022 VCC_023
VCC_025 VCC_026 VCC_027 VCC_028 VCC_029 VCC_030 VCC_031 VCC_032 VCC_033 VCC_034 VCC_035 VCC_036 VCC_037
VCC_039 VCC_040 VCC_041 VCC_042 VCC_043 VCC_044 VCC_045 VCC_046 VCC_047 VCC_048 VCC_049 VCC_050 VCC_051 VCC_052
VCC_057 VCC_058 VCC_059 VCC_060 VCC_061 VCC_062 VCC_063 VCC_064 VCC_065 VCC_066 VCC_067 VCC_068 VCC_069 VCC_070
VCCIO_02
VCCIO_01
VCCIO_20
VCCIO_26
VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36
VCCIO_40
VCCIO_43
VCCIO_04 VCCIO_05 VCCIO_06 VCCIO_07 VCCIO_08
VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14
VCCIO_16
VCCIO_19
VCCSA_SENSE
VIDALERT*
VIDSCLK
VIDSOUT
VSS_SENSE
VCCIO_41
VCC_SENSE
VCC_056
VCC_055
VCC_054
VCC_053
VCCIO_03
VCC_019
VCCIO_15
VCCIO_17 VCCIO_18
VCCIO_22 VCCIO_21 VCCIO_23 VCCIO_24 VCCIO_25
VCCIO_32
VCCIO_37 VCCIO_38 VCCIO_39
VCCSA_VID
SYM 6 OF 10
CPU VIDS
POWER
IO POWER
CPU CORE SUPPLY
SENSE LINES
VCCAXG_44
VCCAXG_43
VCCAXG_02 VCCAXG_03
VDDQ10
VCCPLL1
VCCPLL0
VDDQ22
VDDQ21
VDDQ20
VDDQ19
VDDQ16
VDDQ14
VDDQ13
VDDQ12
VDDQ11
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VDDQ0
VCCAXG_16
VCCAXG_15
VCCAXG_14
VCCAXG_13
VCCAXG_12
VCCAXG_11
VCCAXG_10
VCCAXG_09
VCCAXG_07
VCCAXG_06
VCCAXG_05
VCCAXG_04
VCCAXG_42
VCCAXG_41
VCCAXG_40
VCCAXG_39
VCCAXG_38
VCCAXG_37
VCCAXG_36
VCCAXG_35
VCCAXG_34
VCCAXG_33
VCCAXG_32
VCCAXG_31
VCCAXG_30
VCCAXG_29
VCCAXG_28
VCCAXG_27
VCCAXG_26
VCCAXG_25
VCCAXG_24
VCCAXG_22
VCCAXG_21
VCCAXG_19
VCCAXG_18
VCCAXG_17
VCCAXG_23
VCCAXG_20
VDDQ15
VDDQ17 VDDQ18
VDDQ5
VCCAXG_01
VCCAXG_08
SYM 7 OF 10
1.8V
POWER
DDR3-1.5V RAILS
GRAPHICS
VCC_092
VSS_NCTF2 VSS_NCTF3
VCC_097
VCC_091
VCC_090
VCC_089
VCC_088
VCC_087
VCC_083
VCC_112
VCC_117
VCC_113 VCC_114 VCC_115 VCC_116
VCC_118 VCC_119 VCC_120 VCC_121 VCC_122 VCC_123 VCC_124 VCC_125
VCC_128 VCC_129 VCC_130
VCC_131 VCC_132 VCC_133 VCC_134 VCC_135 VCC_136 VCC_137 VCC_138 VCC_139 VCC_140 VCC_141 VCC_142 VCC_143 VCC_144 VCC_145 VCC_146 VCC_147 VCC_148 VCC_149 VCC_150 VCC_151 VCC_152 VCC_153
VCC_156 VCC_157 VCC_158 VCC_159 VCC_160
VCCSA0 VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6
VCCSA8 VCCSA9
VSS_NCTF1
VCC_073
VCC_072
VCC_071
VCC_155
VCC_154
VCC_084
VCC_093
VSS_NCTF0
VCC_100 VCC_101
VCC_104
VCC_106
VCC_105
VCC_096
VCC_095
VCC_094
VCC_086
VCC_085
VCCSA7
VCCSA10
VCC_107
VCC_082
VCC_077
VCC_074
VCC_076
VCC_161
VCC_126 VCC_127
VCC_111
VCC_098 VCC_099
VCC_075
VCC_081
VCC_103
VCC_102
VCC_078 VCC_079 VCC_080
VCC_108 VCC_109 VCC_110
SYM 10 OF 10
CPU CORE SUPPLY
VCCSA
CPU CORE SUPPLY
POWER
NCTF
OUT
OUT OUT
OUT OUT
OUT OUT
OUT
IN
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
U1000
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
70
108
66
109
66
109
69
108
69
108
66
109
66
109
0
1/16W
MF-LF
5%
402
R1311
402
1/16W
1%
MF-LF
R1310
5%
0
MF-LF
1/16W
402
R1312
402
75
1% 1/16W
R1300
MF-LF
PLACE_NEAR=U1000.A37:10mm
MF-LF
1/16W
1%
110
R1302
402
PLACE_NEAR=U1000.B37:10mm
66
109
66
109
66
109
CPU POWER
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
CPU_VIDSOUT
CPU_VIDALERT_R_L
=PPVCORE_S0_CPU
=PPVAXG_S0_CPU
=PP1V8_S0_CPU_PLL
=PP1V5_S0_CPU_MEM
CPU_VIDSCLK
CPU_VIDSOUT_R
=PPVCCIO_S0_CPU
CPU_VIDSCLK_R
CPU_VIDALERT_L
SNS_CPU_VCORE_N
SNS_CPU_VCCSA
SNS_CPU_VAXG_P
=PPVCCSA_S0_CPU
=PPVCORE_S0_CPU
=PPVCCIO_S0_CPU
SNS_CPU_VCORE_P
SNS_CPU_VAXG_N
SNS_CPU_VCCIO_N
SNS_CPU_VCCIO_P
NC_CPU_VCCIO_VID NO_TEST=TRUE
NO_TEST=TRUE
NC_CPU_VCCSA_VID
prefsb
051-9505
8.0.0
13 OF 144 13 OF 123
L3
V8
P33
W3
J8
M32
L32
AB3
AB4
C18
D14
U4
J7
J4
AJ26
A12 A13 A14 A15
J3
B16
B25
A16 A18 A24 A25 A27 A28 B15
B18 B24
B27 B28 B30
B33 B34 C15 C16
C19 C21 C22 C24 C25 C27 C28 C30 C31 C33 C34 C36 D13
D15 D16 D18 D19 D21 D22 D24 D25 D27 D28 D30 D31 D33 D34
E18 E19 E21 E22 E24 E25 E27 E28 E30 E31 E33 E34 E35 F15
A7
A11
B9
G4
L7 M13 N3 N4
R7
U7
AB8 AF8 AG33 AJ16 AJ17
AJ28 AJ32 AK15 AK17 AK19
AK23
AK30
T2
A37
C37
B37
B36
U3
A36
E16
E15
D36
D35
AA3
B31
AK21
AK27 AK29
D6 D10 E3 E4 G3
L4
N7 R3 R4
P34
Y38
Y37
AB34 AB35
AU19
AK12
AK11
AY28
AY26
AY23
AW31
AV25
AV21
AU31
AU27
AU23
AR24
AR23
AR22
AR21
AJ24
AJ23
AJ20
AJ14
AJ13
AC40
AC39
AC38
AC37
AC36
AC35
AC34
AC33
AB39
AB38
AB37
AB36
Y36
Y35
Y34
Y33
W38
W37
W36
W35
W34
W33
U40
U39
U38
U37
U36
U35
U34
U33
T40
T38
T37
T35
T34
T33
T39
T36
AV24
AV29 AV33
AR20
AB33
AB40
G25
AV39 AY37
G32
G24
G22
G21
G19
G18
F33
H31
J18
H32 J12 J15 J16
J19 J21 J22 J24 J25 J27 J28 J30
K18 K19 K21
K22 K24 K25 K27 K28 K30 L13 L14 L15 L16 L18 L19 L21 L22 L24 L25 L27 L28 L30 M14 M15 M16 M18
M22 M24 M25 M27 M28
H10 H11 H12 J10 K10 K11 L11
M10 M11
B3
F19
F18
F16
M21
M19
F34
G27
A4
H14 H15
H19
H22
H21
G31
G30
G28
G16
G15
L12
M12
H24
F32
F25
F21
F24
M30
K15 K16
H30
G33 H13
F22
F31
H18
H16
F27 F28 F30
H25 H27 H28
1 2
1 2
1 2
1
2
1
2
109
6
13 16 51 66
6
17 51 66
6
16
6
11 16
109
6
10 11 13 16 28 66
109
6
16
6
13 16 51 66
6
10 11 13 16 28 66
VSS_180
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_165
VSS_164
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_156
VSS_155
VSS_154
VSS_153
VSS_152
VSS_151
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_144
VSS_143
VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_125
VSS_124
VSS_123
VSS_122
VSS_121
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
VSS_110
VSS_109
VSS_108
VSS_107
VSS_106
VSS_105
VSS_104
VSS_103
VSS_102
VSS_101
VSS_100
VSS_099
VSS_098
VSS_097
VSS_096
VSS_095
VSS_094
VSS_093
VSS_092
VSS_091
VSS_090
VSS_089
VSS_088
VSS_087
VSS_086
VSS_085
VSS_084
VSS_083
VSS_082
VSS_081
VSS_080
VSS_079
VSS_078
VSS_077
VSS_076
VSS_075
VSS_074
VSS_073
VSS_072
VSS_071
VSS_070
VSS_069
VSS_068
VSS_067
VSS_066
VSS_065
VSS_064
VSS_063
VSS_062
VSS_061
VSS_060
VSS_059
VSS_058
VSS_057
VSS_056
VSS_055
VSS_054
VSS_053
VSS_052
VSS_051
VSS_050
VSS_049
VSS_048
VSS_047
VSS_046
VSS_045
VSS_044
VSS_043
VSS_042
VSS_041
VSS_040
VSS_039
VSS_038
VSS_037
VSS_036
VSS_035
VSS_034
VSS_033
VSS_032
VSS_031
VSS_030
VSS_029
VSS_028
VSS_027
VSS_026
VSS_025
VSS_024
VSS_023
VSS_020
VSS_019
VSS_001 VSS_002 VSS_003 VSS_004 VSS_005
VSS_012
VSS_006 VSS_007 VSS_008 VSS_009 VSS_010 VSS_011
VSS_013 VSS_014 VSS_015
VSS_021 VSS_022
VSS_016 VSS_017 VSS_018
SYM 8 OF 10
VSS
VSS_360
VSS_359
VSS_358
VSS_357
VSS_356
VSS_355
VSS_354
VSS_353
VSS_352
VSS_351
VSS_350
VSS_349
VSS_348
VSS_347
VSS_346
VSS_345
VSS_344
VSS_343
VSS_342
VSS_341
VSS_340
VSS_339
VSS_338
VSS_337
VSS_336
VSS_335
VSS_334
VSS_333
VSS_332
VSS_331
VSS_330
VSS_329
VSS_328
VSS_327
VSS_326
VSS_325
VSS_324
VSS_323
VSS_322
VSS_321
VSS_320
VSS_319
VSS_318
VSS_317
VSS_316
VSS_315
VSS_314
VSS_313
VSS_312
VSS_311
VSS_310
VSS_309
VSS_308
VSS_307
VSS_306
VSS_305
VSS_304
VSS_303
VSS_302
VSS_301
VSS_300
VSS_299
VSS_298
VSS_297
VSS_296
VSS_295
VSS_294
VSS_293
VSS_292
VSS_291
VSS_290
VSS_289
VSS_288
VSS_287
VSS_286
VSS_285
VSS_284
VSS_283
VSS_282
VSS_281
VSS_280
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
VSS_274
VSS_273
VSS_272
VSS_271
VSS_270
VSS_269
VSS_268
VSS_267
VSS_266
VSS_265
VSS_264
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_196
VSS_195
VSS_194
VSS_200
VSS_199
VSS_198
VSS_197
VSS_188
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_182
VSS_187
VSS_186
VSS_181
VSS_185
VSS_184
VSS_183
SYM 9 OF 10
VSS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
U1000
CPU GROUNDS
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
prefsb
051-9505
8.0.0
14 OF 144 14 OF 123
AV10
AU8
AU6
AU4
AU34
AU26
AU15
AU1
AT9
AT8
AT7
AT6
AT5
AT40
AT4
AT39
AT38
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
AT3
AT29
AT28
AT27
AT25
AT2
AT17
AT16
AT15
AT13
AT12
AT10
AT1
AR5
AR36
AR30
AR27
AR19
AR18
AR17
AR14
AR11
AP5
AP40
AP4
AP37
AP36
AP30
AP27
AP25
AP22
AP17
AP14
AP11
AP1
AN9
AN8
AN7
AN6
AN5
AN36
AN35
AN34
AN33
AN32
AN31
AN30
AN27
AN24
AN22
AN19
AN17
AN14
AN11
AN10
AM5
AM40
AM4
AM39
AM38
AM37
AM36
AM30
AM3
AM27
AM25
AM23
AM21
AM2
AM17
AM14
AM11
AM1
AL5
AL36
AL30
AL27
AL24
AL19
AL17
AL14
AL11
AK9
AK8
AK7
AK6
AK5
AK40
AK4
AK37
AK36
AK35
AK34
AK33
AK32
AK31
AK28
AK22
AK16
AK14
AK13
AK10
AK1
AJ5
AJ36
AJ27
AJ25
AJ21
AJ18
AJ15
AJ12
AH8
AH5
AH40
AH39
AH38
AH37
AH36
AH33
AH3
AH2
AG36
AF7
AF6
AF5
AF40
AF37
AF36
AF34
AF1
AE36
AE33
AE3
AD40
AD39
A17 A23 A26 A29 A35
AA6
AA33 AA34 AA35 AA36 AA37 AA38
AB5 AC1 AC6
AD5 AD8
AD33 AD36 AD38
Y8
Y5
W6
V5
V40
V39
V38
V37
V36
V35
V34
V33
V2
V1
U8
T6
T5
T1
R8
R39
R37
R35
R33
P6
P5
P40
P38
P36
P2
P1
N8
M9
M6
M5
M39
M37
M35
M33
M29
M26
M23
M20
M2
M17
M1
L8
L29
L26
L23
L20
L17
L10
K6
K5
K39
K37
K35
K33
K29
K26
K23
K20
K2
K17
K14
K13
K12
K1
J32
J29
J26
J23
J20
J17
J11
H9
H6
H5
H39
H37
H35
H33
H29
H26
H23
H20
H2
H17
H1
G8
G7
G34
G29
G26
G23
G20
G17
G12
G11
F9
F6
F5
F39
F37
F35
F29
F26
F23
F20
F2
F17
F14
F13
F10
F1
E8
E7
E36
E32
E29
E26
E23
E20
E17
E12
E11
D9
D5
D4
D39
D37
D32
D29
D26
D23
D20
D2
D17
C8
C7
C35
C32
C29
C26
C23
C20
C17
C12
C11
B6
B38
B35
B32
B29
B26
B23
B17
B14
B13
B10
AY18
AY14
AY11
AY8
AY6
AY4
AY35
AW10
AW6
AW36
AW16
AW14
AW11
AV14
AV6
AV38
AV11
AV35
AV3
AV17
OUT
S
G
D
IN
D
G S
D
GS
OUT
D
GS
D
S G
D
S G
B
Y
A
OUT
IN
D
GS
OUT
D
GS
OUT
B
Y
A
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DP_AUXIO_EN GLITCHES ON S0/S3 TRANSITIONS RDAR://11085566
D8: ISOLATION FET TO PREVENT TBT 3V3_TBTLC LEAKAGE RDAR://10885566
D7/D7I: CHECK CACTUSRIDGE POWER SEQUENCING & LEAKAGE RDAR://10739300
AP CLKREQ# ISOLATION
ISOLATION FET TO PREVENT LEAKAGE ON AP_PWR_EN AND AP_CLKREQ_L RDAR://11068662
UNUSED clock terminations for FCIM MODE
DP_AUXCH_ISOL IS ACTIVE LOW!
Inverts PCH GPIO DP_AUXCH_ISOL to drive DP_AUXIO_EN for external DP
DP_AUXIO_EN Inversion
TBT CLKREQ# ISOLATION
CFG[5:6] = Sel PCIe Cfg CFG[3]=Direct/Rev for X4 CFG[2]= Direct/Rev for x16
11 = 1x16 (default) 1 = DIR 1 = DIR 10 = 2x8 0 = REV 0 = REV
IVB PCIe Straps configuration:
00 = 1x8,2x4
TBT JTAG_TCK ISOLATION
AP PWR_EN ISOLATION
R1501
5%
MF-LF
402
10K
1/16W
R1502
1/16W5%MF-LF
402
10K
402
1/16W
R1504
5%
MF-LF
10K
1/16W
10K
MF-LF5%402
R1509
1/16W
5%
402
MF-LF
10K
R1510
1/16W
R1511
MF-LF
10K
402
5%
10K
5%
MF-LF1/16W
R1528
402
PLACE_NEAR=U1000.N35:20MM
1/16W
R1512
NOSTUFF
5%
1K
MF-LF
402
PLACE_NEAR=U1000.L37:20MM
1/16W MF-LF1K402
5%
NOSTUFF
R1513
1/16W
R1523
NOSTUFF
MF-LF
5%
1K
402
PLACE_NEAR=U1000.K36:20MM
R1522
MF-LF
402
1K
5%
1/16W
PLACE_NEAR=U1000.J37:20MM
MF-LF
402
R1531
1/16W
10K
5%
402
MF-LF
R1534
1/16W
5%
10K
MF-LF
402
R1533
1/16W
5%
10K
402
MF-LF1/16W
5%
10K
R1530
5%
R1555
MF-LF
402
10K
1/16W
402
MF-LF1/16W
R1542
10K
5%
R1505
MF-LF
10K
5%
1/16W
402
MF-LF
10K
1/16W
R1556
5%
402
402
MF-LF
R1557
5%
10K
1/16W
R1558
402
MF-LF
5%
10K
1/16W
R1517
402
1/16W
10K
MF-LF
5%
5%
402
1/16W MF-LF
10K
R1520
402
R1519
10K
5%
MF-LF1/16W
1/16W5%MF-LF
402
R1518
10K
R1516
5%
MF-LF
10K
402
1/16W
1/16W
1K
5%
402
MF-LF
R1537
402
MF-LF
5%
1K
1/16W
R1536
R1514
402
MF-LF1/16W
5%
1K
MF-LF
402
5%
1/16W
R1529
5%
MF-LF
10K
R1538
1/16W
402
402
1/16W MF-LF
10K
R1540
5%
10K
5%
402
1/16W
R1539
MF-LF
1/16W
402
MF-LF
5%
10K
R1541
1/16W MF-LF
402
R1508
5%
10K
100K
MF-LF
402
1/16W
R1535
5%
MF-LF
402
R1563
1/16W
5%
10K
402
R1532
MF-LF1/16W
5%
20K
18
105
PLACE_NEAR=R1805.1:3MM
1/16W MF-LF
402
5%
330
R1552
NTR1P02L
Q1500
SOT23-3-HF
47
122
R1570
100K
402
MF-LF1/16W
5%
R1571
MF-LF1/16W
100K
402
5%
R1551
MF-LF
402
1/16W
5%
10K
PLACE_NEAR=U1800.P33:5mm
402
MF-LF
R1548
1/16W
5%
10K
10K
R1549
402
MF-LF1/16W
5%
R1550
1/16W
10K
MF-LF
402
5%
PLACE_NEAR=U1800.R33:5mm
402
MF-LF
R1547
1/16W
10K
5%
PLACE_NEAR=U1800.AF55:6MM
5%
1/16W MF-LF
R1546
402
10K
R1545
MF-LF
PLACE_NEAR=U1800.AG56:5mm
402
10K
5%
1/16W
R1544
PLACE_NEAR=U1800.BD38:5mm
402
MF-LF1/16W
5%
10K
PLACE_NEAR=U1800.BF38:5mm
402
R1543
MF-LF1/16W
5%
10K
R1564
MF-LF
4.7K
1/16W
402
5%
R1590
10K
402
5% MF-LF
1/16W
SSM3K15AMFVAPE
VESM
Q1509
CRITICAL
1/16W
402
R1591
MF-LF
5%
10K
R1592
10K
402
1/16W
5% MF-LF
SSM3K15FV
Q1510
SOD-VESM-HF
15 21
122
MF-LF
10K
402
1/16W
5%
NOSTUFF
R1565
10K
R1526
1/16W5%MF-LF
402
1/16W
R1527
MF-LF
10K
402
5%
402
1/16W
5%
10K
MF-LF
R1594
SSM3K15FV
SOD-VESM-HF
Q1530
Q1540
SSM6N15AFE
CRITICAL
SOT563
402
5%
10K
R1561
MF-LF
1/16W
R1562
10K
5% 1/16W MF-LF 402
SOT563
SSM6N15AFE
Q1540
CRITICAL
402
5%
10K
MF-LF
1/16W
R1595
1/16W
10K
402
MF-LF
5%
R1596
1/16W
5% MF-LF
402
10K
R1597
0
NOSTUFF
5%
1/16W MF-LF
R1598
402
NOSTUFF
5%
402
MF-LF
R1599
1/16W
0
R1500
MF-LF1/16W
5%
NOSTUFF
0
402
R1593
402
MF-LF
1/16W
5%
10K
74LVC1G08GW
SOT353
U1500
21
103
1/16W 402
R1521
MF-LF
10K
5%
R1584
402
MF-LF
0
NOSTUFF
5%
1/16W
D1521
BAT54XV2T1
SOD-523
36
10K
R1583
402
5% 1/16W MF-LF
402
NOSTUFF
R1585
0
1/16W5%MF-LF
R1586
10K
402
MF-LF
5% 1/16W
10K
402
1/16W
5%
R1587
MF-LF
SOD-VESM-HF
SSM3K15FV
Q1550
15 21
117
10K
402
1/16W
5% MF-LF
R1588
SSM3K15FV
SOD-VESM-HF
Q1560
15 20
103
74LVC1G08GW
U1501
SOT353
77 79
117
10% X7R-CERM
0.1UF
0402
16V
C1500
U1500.5:3MM
10%
C1501
X7R-CERM
16V 0402
0.1UF
U1501.5:3MM
2.0K
1/16W MF-LF
402
1%
R1524
1/16W MF-LF
402
1%
2.0K
R1525
5%
0
R1554
NOSTUFF
1/16W
402
MF-LF
R1553
402
MF-LF
0
NOSTUFF
1/16W
5%
SYNC_DATE=08/27/2012
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
SYNC_MASTER=D8_MLB
PCH_BLC_MCU_RESET_R
PCH_BLC_EXT_BOOT_R
=PP3V3_TBT_PCH_GPIO
PCH_CAM_EXT_BOOT_L
PCH_CAM_RESET
PCH_GPIO6
USB_EXTA_OC_L
=PP3V3_S4_AP
TBT_PWR_EN
TBT_PWR_EN_R
JTAG_TBT_TCK_ISOL
JTAG_TBT_TCK
=PP3V3_TBT_PCH_GPIO
TBT_CIO_PLUG_EVENT_ISOL
TBT_CIO_PLUG_EVENT
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH_STRAPS
PCH_GPIO1
DP_AUXCH_ISOL
SSD_CLKREQ_L
ENET_CLKREQ_L
TBT_PCH_CLKREQ_L
=PP3V3_TBT_PCH_GPIO
CPU_CFG<2>
CPU_CFG<6>
USB_EXTD_OC_EHCI_L
PCH_SATALED_L
=PP3V3_S0_LED_SATA
PCH_SMBALERT_L
USB_EXTC_OC_L
=PP3V3_S5_PCH_STRAPS
PCH_SPKR
SATARDRVR_EN
PEG_CLKREQ_L
SMC_RUNTIME_SCI_L
=PP3V3_S0_PCH_STRAPS
PCH_GPIO48
PM_SLP_S4_L
PM_SLP_S5_L
ENET_LOW_PWR_PCH
PCH_GPIO22
ENET_MEDIA_SENSE
WOL_EN
PCH_GPIO29
PCH_CLK14P3M_REFCLK
PCH_CLK100M_DMIN
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_GPIO
JTAG_TBT_TDO_ISOL
JTAG_TBT_TMS_ISOL
=PP3V3_TBT_PCH_GPIO
JTAG_TBT_TDO
JTAG_TBT_TMS
JTAG_TBT_TDI_ISOL
TBT_PCH_CLKREQ_L
TBT_CLKREQ_L
HDA_SYNC
ITPXDP_CLK100M_N ITPCPU_CLK100M_N
ITPXDP_CLK100M_P ITPCPU_CLK100M_P
TBT_PWR_REQ_L
BT_PWR_RST_L
AP_PWR_EN_ISO
AP_PWR_EN
USB_EXTB_OC_EHCI_L
=PP3V3_S4_AP
=PP3V3_S5_PCH_STRAPS
SMC_WAKE_SCI_L
PCH_SUSWARN_L
PCH_GPIO72
PM_PWRBTN_L
TBT_SW_RESET_R_L
AP_CLKREQ_L
AP_PWR_EN
AP_CLKREQ_L
TBT_GO2SX_BIDIR
=PP3V3_S0_PCH_STRAPS
=PP3V3_S5_PCH_STRAPS
AP_CLKREQ_L_ISO
SPI_DESCRIPTOR_OVERRIDE_L
DP_AUXCH_ISOL
PM_PCH_PWROK
DP_AUXIO_EN
SPI_DESCRIPTOR_OVERRIDE_R
=PP3V3_S0_PCH_STRAPS
PM_SLP_S3_L
PCH_CLKIN_GND0
PCH_CLK100M_SATAP
PCH_CLK96M_DOTP
PCH_CLK96M_DOTN
PCH_CLK100M_SATAN
HDA_SDOUT_R
SDCONN_STATE_CHANGE
USB_EXTD_OC_L
=PP3V3_TBT_PCH_GPIO
=PP3V3_TBTLC_RTR
PCH_CLK100M_DMIP
PCH_CLKIN_GND1
CPU_CFG<5>
CPU_CFG<3>
USB_EXTB_OC_L
JTAG_TBT_TDI
=PP3V3_S0_PCH_GPIO
DP_AUXCH_ISOL_EN
=PP3V3_S0_PCH_GPIO
prefsb
051-9505
8.0.0
15 OF 144 15 OF 123
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
3
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1
2
3
1 2
1
2
1
2
3
1 2
1 2
1 2
1
2
1
2
3
3
4
5
1
2
1
2
6
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1
2
4
3
1
2
5
1
2
1 2
A K
1
2
1 2
1
2
1
2
1
2
3
1
2
1
2
3
4
3
1
2
5
2
1
2
1
1 2
1 2
1 2
1 2
21
120
21
120
6
15
21
21
120
21
20 45
103
6
15 35
26 36
122
36
103
21
103
6
15
6
15 19 20 38
6
15
21
15 18
103
18
122
18 40
118
15 21
122
6
15
10 25
103
10 25
103
20
103
18 44
6
44
18
120
20 46
103
6
15
18
18
103
18 83
120
21 47
122
6
15
21
19 47 64
120
19 47 64
120
21 26
103
21
18 39
116
21 40
123
19
18
18
6
15 19 20 38
6
15 19 20 38
6
15 19 20 38
36
119
36
119
6
15
21
119
18
119
36
119
38
122
18 56
105
18 25
103
11
103
18 25
103
11
103
20 36
122
20 35
117
35
117
15 20
103
20
103
6
15 35
6
15
21 47
122
19
120
19
19 25 47
120
21
15 21
117
21 36
6
15
6
15
35
117
15 18
103
19 26 35 43 65 80
120
105
6
15
5
19 28 40 47 48 64
120
18
18
18
18
18
20 41
103
20 46
103
6
15
6
36 37 38 50
18
18
10 25
103
10 25
103
20 45
103
21
119
6
15 19 20 38
103
6
15 19 20 38
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLL (CPU VCCSFR) DECOUPLING
Memory (CPU VCCDDR) DECOUPLING
PLACEMENT_NOTE (C1660-C1665):
PLACEMENT_NOTE (C1650-C1657):
CPU VCCIO DECOUPLING
8X 22UF 0805, 6X 10UF 0805
10x 10UF and 10x 1UF CAPACITORS
BULK CAPS ON VTT REG PAGE 77
INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders
PLACEMENT_NOTE (C1600-C1613):
Bulk decoupling is on VCCSA reg page 75
2x 10uF 0603. INTEL RECOMMENDATION 2X 10uF 0805
CPU VCCSA DECOUPLING
BULK CAPS ON CPU VREG PAGE 74
BULK CAPS ON CPU VREG PAGE 72
2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 1x 10uF 0805
CPU VCORE DECOUPLING
14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)
REPLACED WITH 603 PER RDAR://10700439
C1693
1UF
X5R 402
10% 10V
C1692
2.2UF
X5R 402
10%
6.3V
4.7UF
10%
6.3V X5R-CERM 603
C1691
C1629
Place inside socket cavity
X5R 603
20% 10V
C1628
Place inside socket cavity
X5R 603
20% 10V
C1627
Place inside socket cavity
X5R 603
20% 10V
C1626
Place inside socket cavity
X5R 603
20% 10V
C1624
Place inside socket cavity
X5R 603
20% 10V
C1623
Place inside socket cavity
X5R 603
20% 10V
C1622
Place inside socket cavity
X5R 603
20% 10V
C1621
Place inside socket cavity
X5R 603
20% 10V
C1620
Place inside socket cavity
X5R 603
20% 10V
C1630
Place inside socket cavity
1UF
X5R 402
10% 16V
C1625
Place inside socket cavity
X5R 603
20% 10V
402
C1631
Place inside socket cavity
1UF
X5R
10% 16V
1UF
402
C1632
Place inside socket cavity
X5R
10% 16V
1UF
10% X5R
402
C1633
Place inside socket cavity
16V
C1634
Place inside socket cavity
1UF
X5R 402
10% 16V
C1635
Place inside socket cavity
1UF
X5R 402
10% 16V
C1636
Place inside socket cavity
1UF
X5R 402
10% 16V
C1637
Place inside socket cavity
1UF
X5R 402
10% 16V
C1638
Place inside socket cavity
1UF
X5R 402
10% 16V
C1639
Place inside socket cavity
1UF
X5R 402
10% 16V
2V POLY CASE-D2-SM
20%
C1670
CRITICAL
330UF-0.0045OHM
C1695
20%
603
X5R
6.3V
C1682
6.3V
1UF
20% X5R
0201
C1683
1UF
X5R
20%
6.3V 0201
C1684
1UF
X5R 0201
20%
6.3V
C1685
1UF
X5R 0201
20%
6.3V
C1686
X5R 0201
20%
6.3V
1UF
C1687
20% 2V POLY
NOSTUFF
330UF-0.0045OHM
CASE-D2-SM
CRITICAL
C1667
20% X5R
603
6.3V
20%
6.3V 603
X5R
C1666
C1600
X5R-CERM2
6.3V
20%
0603
X5R-CERM2
6.3V
20%
0603
C1601
6.3V
20%
C1602
0603
X5R-CERM2
C1603
X5R-CERM2
6.3V
20%
0603
C1604
X5R-CERM2
6.3V
20%
0603
20%
6.3V X5R-CERM2 0603
C1605
X5R-CERM2
6.3V
20%
C1606
0603
X5R-CERM2
6.3V
20%
0603
C1607
X5R-CERM2
6.3V
20%
0603
C1608
X5R-CERM2
6.3V
20%
0603
C1609
C1610
0603
20%
6.3V X5R-CERM2
0603
20%
6.3V X5R-CERM2
C1611
0603
20% X5R-CERM2
6.3V
C1612 C1613
0603
20%
6.3V X5R-CERM2
0603
C1650
X5R-CERM2
6.3V
20%
22UF 22UF
20%
6.3V X5R-CERM2
C1651
0603
20% X5R-CERM2
C1652
0603
6.3V X5R-CERM2
6.3V
20%
0603
C1653
20%
6.3V
C1654
0603
X5R-CERM2
20%
6.3V X5R-CERM2
C1655
0603
20%
6.3V X5R-CERM2
C1656
0603
20%
6.3V X5R-CERM2
C1657
0603
C1676
0603
20%
6.3V X5R-CERM2 X5R-CERM2
6.3V
20%
0603
C1677
6.3V
20%
0603
C1678
X5R-CERM2 X5R-CERM2
6.3V
20%
0603
C1679
0603
X5R-CERM2
6.3V
20%
C1680 C1681
0603
20%
6.3V X5R-CERM2
X5R-CERM2
20%
0603
C1690
6.3V
C1696
0805
20%
6.3V X5R
C1697
0805
6.3V
20% X5R
C1665
6.3V
20% 603
X5R
Place at edge of socket.
C1664
6.3V
20% 603
X5R
Place at edge of socket.Place at edge of socket.
X5R 603
20%
C1663
6.3V
20%
Place at edge of socket.
6.3V
603
X5R
C1662
Place at edge of socket.
603
20%
6.3V X5R
C1661
X5R 603
20%
6.3V
Place at edge of socket.
C1660
C1694
1UF
X5R 402
10% 10V
SYNC_DATE=08/27/2012
CPU NON-GFX DECOUPLING
SYNC_MASTER=D8_MLB
=PPVCORE_S0_CPU
=PP1V8_S0_CPU_PLL
=PPVCCIO_S0_CPU
=PPVCCSA_S0_CPU
=PP1V5_S0_CPU_MEM
=PPVCORE_S0_CPU
prefsb
051-9505
8.0.0
16 OF 144 16 OF 123
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
13 16
51 66
6
13
6
10 11 13
28 66
6
13
6
11 13
6
13 16 51 66
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACEMENT_NOTE (C1704-C1709):
AXG BULK CAPS
INTEL RECOMMENDATION 4X22UF 0805,3X 4.7UF
VAXG DECOUPLING
1/16W
5%
402
MF-LF
0
R1730
0
MF-LF
402
5%
1/16W
R1740
6.3V
10%
603
X5R-CERM
Place inside socket cavity
4.7UF
C1710
6.3V
10%
603
Place inside socket cavity
X5R-CERM
4.7UF
C1711
4.7UF
6.3V X5R-CERM 603
10%
Place inside socket cavity
C1712
5% 1/16W MF-LF
0
402
R1720
10V
10UF
20% X5R
C1795
603
X5R
20%
10UF
10V
C1794
603
330UF-0.006OHM
2V
20% POLY
C1793
CRITICAL
CASE-D2-SM
CRITICAL
POLY
20%
330UF-0.006OHM
C1792
2V CASE-D2-SM
CRITICAL
330UF-0.006OHM
POLY
2V
20%
C1791
CASE-D2-SM
330UF-0.006OHM
20% POLY
CASE-D2-SM
C1790
2V
CRITICALCRITICAL
2V
20% POLY
C1789
330UF-0.006OHM
CASE-D2-SM
CRITICAL
2V
20% POLY
C1788
CASE-D2-SM
330UF-0.006OHM
20%
6.3V X5R-CERM2
C1704
0603
20%
6.3V X5R-CERM2
C1705
0603
20%
6.3V X5R-CERM2
C1706
0603
20%
6.3V X5R-CERM2
C1707
0603
20%
6.3V X5R-CERM2
C1708
0603
20%
6.3V X5R-CERM2
C1709
0603
PLACE C1731 AT BALL U1800.AB1
C1731
10%
402
CERM
6.3V
1UF
PLACE C1741 AT BALL U1800.AC2
C1741
402
CERM
6.3V
10%
1UF
SYNC_MASTER=D8_MLB
GFX DECOUPLING & PCH PWR ALIAS
SYNC_DATE=08/27/2012
=PP1V05_S0_PCH_VCC_ADPLL
=PP3V3_S0_PCH_VCC_ADAC
PPCPUAXG_S0_REG
=PPVAXG_S0_CPU
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
PP1V05_S0_PCH_VCCADPLLB_F
MAKE_BASE=TRUE
PP1V05_S0_PCH_VCCADPLLA_F
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
MAKE_BASE=TRUE
PP3V3_S0_PCH_VCCA_DAC_F
prefsb
051-9505
8.0.0
17 OF 144 17 OF 123
1 2
1 2
2
1
2
1
2
1
1 2
2
1
2
11
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
6
6
68
6
13 51 66
22
120
22
120
22
121
IN
IN
OUT
OUT
OUT
IN
BI
IN
IN OUT OUT
IN
IN OUT OUT
IN IN
IN IN
IN IN
OUT
OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
IN
OUT OUT
OUT
OUT
OUT
OUT
IN
IN
IN IN
IN IN
IN
IN
IN
OUT
OUT
BI
OUT
BI
IN
IN OUT OUT
OUT OUT
IN
OUT
BI
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT OUT
BI
BI
BI
BI
OUT
SATA3COMPI
SATA3RCOMP0
SATA3RBIAS
SATA3RXP
HDA_SYNC
INTRUDER*
LDRQ1*/GPIO23
SATA1TXN
SATA3RXN
SATA1RXN
SATA1TXP
SATA0RXN
SERIRQ
FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
FWH4/LFRAME*
SATA1RXP
SATA2TXN SATA2TXP
SATA3TXN SATA3TXP
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
SATA5RXN
SATA5TXN SATA5TXP
SATAICOMPO SATAICOMPI
SATALED*
SATA0GP/GPIO21 SATA1GP/GPIO19
L_BKLTCTL
HDA_RST*
SPKR
HDA_SDIN1
HDA_SDIN3
HDA_SDIN2
HDA_SDO
GPIO33 GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CS0*
SPI_MOSI
SPI_MISO
RTCX1 RTCX2
SATA0TXP
SATA0TXN
SATA2RXN SATA2RXP
SATA5RXP
SATA0RXP
LDRQ0*
L_BKLTEN L_VDD_EN
FWH0/LAD0
INTVRMEN
SPI_CS1*
HDA_SDIN0
SRTCRST*
SPI_CLK
RTCRST*
HDA_BCLK
(1 OF 10)
LPC
RTC
IHDA
SATA
JTAG
SPI
CLKIN_DMI_P
PETN2
CLKOUT_PEG_A_N
CL_RST1*
CLKIN_DMI_N
PERP3
CLKOUT_PEG_B_N
CLKIN_DOT_96P
CL_DATA1
CL_CLK1
CLKIN_GND1_P
CLKIN_GND1_N
CLKIN_GND0_P
CLKOUT_ITPXDP_N
CLKOUTFLEX3/GPIO67
CLKOUTFLEX2/GPIO66
CLKOUTFLEX1/GPIO65
CLKOUTFLEX0/GPIO64
XCLK_RCOMP
XTAL25_OUT
XTAL25_IN
CLKIN_PCILOOPBACK
REFCLK14IN
CLKIN_SATA_P
CLKIN_DOT_96N
CLKOUT_DP_N CLKOUT_DP_P
CLKOUT_DMI_P
CLKOUT_DMI_N
CLKOUT_PEG_A_P
SMBCLK
SMBALERT*/GPIO11
SML1DATA/GPIO75
SML1CLK/GPIO58
SML1ALERT*/PCHHOT*/GPIO74
SML0DATA
SML0ALERT*/GPIO60
SML0CLK
SMBDATA
PERN3
PETP2
CLKOUT_PCIE5P
PCIECLKRQ5*/GPIO44
CLKOUT_PCIE4P
CLKOUT_PCIE5N
CLKOUT_PCIE3P
CLKOUT_PCIE4N
CLKOUT_PCIE3N
PCIECLKRQ2*/GPIO20/SMI*
CLKOUT_PCIE2P
CLKOUT_PCIE2N
CLKOUT_PCIE1N CLKOUT_PCIE1P
CLKOUT_PCIE0N CLKOUT_PCIE0P
PETP8
PERP8 PETN8
PETP7
PERN8
PETN7
PERP7
PERN7
PETN6 PETP6
PERP5
PETP4
PERN5
PETN4
PERP4
PETP3
PERN4
PETN3
PERP2
CLKIN_SATA_N
CLKIN_GND0_N
CLKOUT_ITPXDP_P
CLKOUT_PEG_B_P
PETN5 PETP5
PERN6 PERP6
PERP1
PERN1
PETN1 PETP1
PERN2
FLEX
CLOCK
PCI-E*
PEG
FROM CLK BUFFER
SMBUS
(2 0F 10)
OUT
OUT
OUT OUT OUT OUT
OUT OUT
OUT OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DOES THIS NEED LENGTH MATCH???
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
PLACE THIS RESISTOR PACK CLOSE TO PCH (MIN 500MIL)
26
105
56
105
49
105
49
105
49
105
49
105
47 49
119
44
104
44
104
44
104
44
104
44
104
44
104
44
104
44
104
8
8
8
8
39
102
39
102
8
8
8
8
39
102
39
102
8
8
35
102
35
102
36
102
36
102
15 83
120
11
103
11
103
83
102
83
102
8
8
15
15
15
15
15
15
15
26
105
26
105
26
105
50
122
50
122
50
121
50
121
35
102
35
102
35
102
35
102
1/16W
402
1%
MF-LF
37.4
PLACE_NEAR=U1800.AJ53:2mm
R1830
10K
1/16W
5%
402
MF-LF
R1820
39
102
39
102
90.9
1%
402
MF-LF
PLACE_NEAR=U1800.AL2:2mm
1/16W
R1890
18
120
50
122
50
122
8
8
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
36
102
402
1%
MF-LF
750
1/16W
PLACE_NEAR=U1800.AC52:2mm
R1832
PLACE_NEAR=U1800.AE52:2mm
MF-LF 402
1/16W
1%
49.9
R1831
8
8
1/16W
33
MF-LF
402
5%
R1860
47 49
105
47 49
105
MF-LF
402
5%
33
1/16W
R1861
47 49
105
1/16W
33
402
MF-LF
5%
R1862
47 49
105
MF-LF
402
5%
33
1/16W
R1863
47 49 105
FCBGA
OMIT_TABLE
PANTHER-POINT
U1800
OMIT_TABLE
FCBGA
PANTHER-POINT
U1800
1/16W
402
5%
33
MF-LF
R1864
402
5% 1/16W
20K
R1803
MF-LF
1/16W
R1802
20K
MF-LF
5%
402
10%
402
10V X5R
1UF
C1803
X5R 402
10% 10V
1UF
C1802
5%
402
MF-LF
1/16W
1M
R1801
390K
1/16W
5%
MF-LF
R1800
402
45
46
56
105
56
105
15 56
105
56
105
5%
SM-LF
1/16W
33
R1805
NOSTUFF
R1851
0
MF-LF
1/16W
402
5%
R1852
0
5%
402
1/16W MF-LF
15
103
15
103
1/20W
201
MF5%
0
SIGNAL_MODEL=EMPTY
R1841
MF
201
5%01/20W
SIGNAL_MODEL=EMPTY
R1842
8
8
SYNC_DATE=08/27/2012
PCH SATA/PCIE/CLK/LPC/SPI
SYNC_MASTER=D8_MLB
DMI_MIDBUS_CLK100M_N
ITPXDP_CLK100M_N
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO64_CLKOUTFLEX0
PCH_CLKIN_GND1
TP_PCH_GPIO67_CLKOUTFLEX3
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_CL_CLK1
TP_PCH_CL_DATA1
PCH_CLK100M_SATAP
TP_PCIE2_R2D_CP
TP_PCIE1_D2RN TP_PCIE1_D2RP TP_PCIE1_R2D_CN TP_PCIE1_R2D_CP
TP_PCIE2_R2D_CN
TP_PCIE2_D2RN TP_PCIE2_D2RP
TP_PCIE_CLK100M_PE0N TP_PCIE_CLK100M_PE0P
PCIE_AP_D2R_P
PCIE_CLK100M_AP_N
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN
XDP_PCH_TDI
TP_SATA_C_R2D_CP
TP_SATA_C_D2RP
TP_SATA_C_D2RN
SATA_SSD_R2D_N SATA_SSD_R2D_P
TP_SATA_C_R2D_CN
PCIE_CLK100M_TBT_N
PEG_CLKREQ_L
PCIE_TBT_R2D_C_P<3>
PCIE_ENET_D2R_P
HDA_RST_R_L
HDA_SDIN0
TP_HDA_SDIN3
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_D2R_P<2>
PCIE_TBT_D2R_N<2>
TP_PCH_CLKOUT_DPN
DMI_CLK100M_CPU_N
XDP_PCH_TMS
HDA_SYNC_R
PCH_SPKR
TP_HDA_SDIN2
ENET_MEDIA_SENSE
TP_PCH_CLKOUT_DPP
XDP_PCH_TCK
HDA_SDOUT_R
PCH_CLK14P3M_REFCLK
=PP1V05_S0_PCH
SML_PCH_0_CLK
DMI_CLK100M_CPU_P
PCH_CLK100M_DMIN
DP_AUXCH_ISOL
DP_AUXCH_ISOL_R SATARDRVR_EN_R
TP_SATA_F_R2D_CN
TP_SATA_F_D2RP
TP_PCH_L_VDD_EN
LPC_AD<1>
SPI_MOSI_R
PCH_SATA3COMP
HDA_BIT_CLK_R
HDA_SDOUT_R
SATA_SSD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_P
PCH_INTRUDER_L
TP_PCH_CL_RST1
PCH_CLK96M_DOTN
SML_PCH_1_DATA
TP_SATA_F_D2RN
TP_PCH_L_BKLTEN
TP_PCH_L_BKLTCTL
=PP3V3_G3_PCH
PCIE_TBT_D2R_P<0>
PCIE_TBT_R2D_C_P<1>
PCH_CLK96M_DOTP
PCH_CLK100M_SATAN
HDA_SYNC_R
HDA_SYNC HDA_RST_L
PCH_CLK100M_DMIP
PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P
TP_LPC_DREQ0_L TBT_PWR_EN_PCH
LPC_SERIRQ
SATA_SSD_D2R_N
PCH_CLK32K_RTCX1
SSD_CLKREQ_L
ENET_CLKREQ_L
TP_HDA_SDIN1
HDA_RST_R_L
HDA_BIT_CLK
HDA_SDOUT
SATA_HDD_R2D_C_P
SATA_HDD_D2R_N
=PP3V3_S0_PCH
PCH_CLK32K_RTCX2
LPC_FRAME_L
LFRAME_L
LPC_AD<2>
LPC_R_AD<2>
LPC_AD<0>
LPC_R_AD<0> LPC_R_AD<1>
LPC_AD<3>
LPC_R_AD<3>
SPI_MISO
HDA_BIT_CLK_R
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTVRMEN
JTAG_TBT_TMS
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
PCH_SATA3RBIAS
PCH_SATAICOMP
PCIE_TBT_D2R_N<0>
PCIE_CLK100M_TBT_P
USB_EXTB_SEL_XHCI
SML_PCH_0_DATA
USB_EXTD_SEL_XHCI
SML_PCH_1_CLK
PCH_CLK33M_PCIIN
PCH_CLK25M_XTALOUT
PCH_CLKIN_GND0
=PP1V05_S0_PCH_VCCIO_PCIE
SPI_CS0_R_L
PEG_CLK100M_P
PCIE_ENET_R2D_C_P
ITPXDP_CLK100M_P
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_D2R_P<1>
PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>
PCIE_CLK100M_AP_P
PCIE_TBT_R2D_C_N<3>
PCIE_TBT_D2R_P<3>
PCIE_TBT_D2R_N<3>
SMBUS_PCH_DATA
SMBUS_PCH_CLK
PCH_SMBALERT_L
PCIE_ENET_D2R_N
PCIE_ENET_R2D_C_N
SATARDRVR_EN
PCH_CLK25M_XTALIN
TP_SATA_D_D2RP
TP_SATA_E_R2D_CP
TP_SATA_F_R2D_CP
PCH_SATALED_L
=PP1V05_S0_PCH_VCCIO_SATA
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLKREQ5_GPIO44_L
PCIE_AP_D2R_N
PCIE_TBT_D2R_N<1>
PCIE_TBT_R2D_C_N<1>
PEG_CLK100M_N
DMI_MIDBUS_CLK100M_P
TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N
PCH_INTVRMEN
PCH_INTRUDER_L
PCH_SRTCRST_L
RTC_RESET_L
NC_SPI_CS1_L
NO_TEST=TRUE
SPI_CLK_R
PCH_XCLK_RCOMP
XDP_PCH_TDO
PCIE_CLKREQ5_GPIO44_L
prefsb
051-9505
8.0.0
18 OF 144 18 OF 123
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1 2
AE54 AE52 AC52
AN44
BP23
BM38 BA20
AG49
AN46
AA53
AG47
AC56
AV52
BJ17 BJ20 BG20
BG17
AA56
AL56 AL53
AN56 AM55
AN49 AN50 AT50 AT49
AT46
AV50 AV49
AJ53 AJ55
BF57
BC54 AY52
AG12
BC22
BE56
BF22
BJ22
BK22
BT23
BC25 BA25
BA43
BC50
BC52
BF47
AT57
AU53
AT55
BR39 BN39
AE44
AE46
AL50 AL49
AT44
AB55
BK17
AG18 AG17
BK15
BN41
AR56
BD22
BN37
AR54
BT41
BU22
R33
C22
AG8
BF49
P33
J17
AE12
BF38
BF50
BA50
P27
R27
V52
R52
BA2
AW5
BA5
AT9
AL2
AJ5
AJ3
BD15
AN8
AG56
BD38
N56 M55
R31
P31
AG9
BT47
BN49
BK46
BJ46
BR46
BM50
BU49
BT51
BR49
H17
A22
AG2
BL54
Y8
AF3
AB8
Y9
AB9
AV43
AB14
AB12
AA5
W5
AE6 AC6
D13
J10 B13
F13
H10
F15
H12
J12
A16 B15
M15
E17
N15
F18
M17
B21
P17
E21
R20
AF55
W53
N52
AE11
B17 C16
J15 L15
L20
J20
F25 F23
P20
1 2
1
2
1
2
2
1
2
1
121
2
1 2 3 4
8 7 6 5
1 2
1 2
1 2 1 2
15 25
103
8
8
15
8
8
8
8
8
8
8
8
25
103
8
8
8
8
18
105
8
25
103
18
105
15
8
15 39
116
25
103
15 18
105
6
8
8
8
104
18
105
15 18
105
18
8
8
8
8
6
19
18
105
8
26
122
15
122
15 40
118
8
18
105
6
21 24
105
105
105
105
105
18
105
18 26 48
121
18
120
18
15
119
8
8
104
104
8
15
6
19 22 24
15 25
103
15
120
8
8
8
15 44
6
22 24
18
18
18
120
18 26 48
121
105
25
103
18
120
IN
OUT
OUT OUT
OUT OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
INIT3_3V*
GPIO32
DMI2TXP
PWRBTN*
RSMRST*
SYS_RESET*
DMI3RXN
DMI2RXN
DMI2RXP DMI3RXP
DMI_ZCOMP
SUSACK*
SLP_SUS*
DSWVRMEN
DF_TVS
SLP_LAN*/GPIO29
PMSYNCH
SLP_A*
SLP_S3*
SLP_S4*
SUSCLK/GPIO62
SUS_STAT*/GPIO61
FDI_LSYNC0
FDI_FSYNC1
FDI_INT
FDI_RXP7
FDI_RXP6
FDI_RXP5
FDI_RXP4
FDI_RXP3
FDI_RXP1
FDI_RXN7
FDI_RXN6
FDI_RXN5
FDI_RXN4
FDI_RXN3
FDI_RXN2
FDI_RXN1
FDI_RXN0
RI*
SUSWARN*/GPIO30
PWROK
SYS_PWROK
DMI_IRCOMP
DMI2RBIAS
DMI1TXN
DMI0TXN
DMI1RXP
DMI0RXP
FDI_RXP0
FDI_LSYNC1
DMI0RXN
FDI_RXP2
DMI1RXN
FDI_FSYNC0
APWROK
DMI2TXN DMI3TXN
DMI0TXP DMI1TXP
GPIO31 GPIO72
DMI3TXP
SLP_S5*/GPIO63
WAKE*
DPWROK
DRAMPWROK
DMI
FDI
(3 OF 10)
SYSTEM POWER
MANAGEMENT
DDPB_AUXN DDPB_AUXP
DDPB_0P DDPB_1N DDPB_1P
DDPB_3N DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_HPD
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N
DDPD_3P
CRT_BLUE CRT_GREEN CRT_RED
CRT_DDC_CLK CRT_DDC_DATA
CRT_HSYNC CRT_VSYNC
DAC_IREF CRT_IRTN
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_INTN SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_HPD
DDPB_0N
DDPB_2N DDPB_2P
DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_AUXN DDPD_AUXP
DDPD_2P DDPD_3N
RESERVED
(4 OF 10)
CRT
DIGITAL DISPLAY INTERFACE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACE CLOSE TO U1800 PIN
SHORT THESE TWO PINS VERY NEAR THE PINS PLACE THE RESISTOR VERY CLOSE TO COMMON POINT
KEEPING TP, IF NEED TO USE IT LATER
10
103
8
8
8
8
8
49.9
MF-LF
402
1%
1/16W
R1900
PLACE_NEAR=U1800.E31:5MM
19 35 40 120
48
105
15 47 64
120
15 47 64
120
5
15 28 40 47 48 64
120
11 28
103
65
120
15 25 47
120
65
120
15 26 35 43 65 80
120
48 65
120
25 26 47
120
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
10
103
5% 1/16W MF-LF
402
10K
R1905
11
103
26 47 49
119
402
1/16W
1%
1K
MF-LF
R1925
MF-LF
1/16W
5%
1K
402
R1951
PLACE_NEAR=U1800.AT3:3mm
5%
10K
1/16W MF-LF
402
R1909
390K
5%
402
1/16W
MF-LF
R1915
MF-LF 402
1/16W
1%
750
R1920
PLACE_NEAR=U1800.A32:5MM
5%
2.2K
402
MF-LF
1/16W
R1981
4.7K
5% 1/16W MF-LF
402
R1980
OMIT_TABLE
PANTHER-POINT
FCBGA
U1800
OMIT_TABLE
PANTHER-POINT
FCBGA
U1800
5%
10K
402
MF-LF
1/16W
R1999
1/16W
5%
402
MF-LF
10K
R1998
PCH DMI/FDI/GRAPHICS
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
PCH_RI_L
PCH_DMI2RBIAS
CPU_PROC_SEL
MAKE_BASE=TRUE
PCIE_WAKE_L
PM_RSMRST_PCH_L
PCH_SUSWARN_L
PCH_GPIO31_ACPRESENT
PCH_DF_TVS
PM_SLP_S4_L
PCH_GPIO29
PCH_DSWVRMEN
PCH_FDI_FSYNC<0>
DMI_N2S_N<2>
PCH_GPIO32
LPC_PWRDWN_L
PCIE_WAKE_L
PCH_FDI_LSYNC<1>
DP_IG_D_CTRL_DATA
TP_PCH_RESERVE_6
TP_PCH_RESERVE_14
DP_IG_D_CTRL_CLK
TP_PCH_RESERVE_11
TP_PCH_RESERVE_10
TP_PCH_RESERVE_9
DP_IG_B_MLN<2>
=PP3V3_G3_PCH
TP_PM_SLP_A_L
DP_IG_C_MLP<3>
DP_IG_B_MLP<3>
PCH_DSWVRMEN
PCH_DF_TVS
TP_PCH_SUSACK_L
=PP3V3_S5_PCH
DMI_S2N_P<0>
PM_PCH_APWROK
=PP1V05_S0_PCH_VCCIO_PCIE
PM_PCH_PWROK
PM_MEM_PWRGD
PM_SYSRST_L
DMI_S2N_P<3>
PM_SLP_S5_L
DMI_S2N_N<3>
DMI_S2N_N<2>
DMI_N2S_N<1>
DMI_N2S_N<0>
DMI_N2S_P<0> DMI_N2S_P<1>
DMI_S2N_N<1>
PCH_FDI_RX_N<0>
PM_SLP_S3_L
TP_PCH_SLP_SUS_L
DMI_N2S_P<3>
DMI_N2S_N<3>
DMI_S2N_P<2>
=PP1V8_S0_PCH
DP_IG_D_MLN<3>
DP_IG_D_MLP<2>
DP_IG_D_AUXP
DP_IG_D_AUXN
DP_IG_C_MLN<3>
DP_IG_C_MLP<2>
DP_IG_C_MLN<2>
DP_IG_C_MLP<1>
DP_IG_C_MLN<1>
DP_IG_C_MLP<0>
DP_IG_B_MLP<2>
DP_IG_B_MLN<0>
DP_IG_B_DDC_DATA
DP_IG_B_DDC_CLK
TP_SDVO_INTP
TP_SDVO_INTN
TP_SDVO_STALLP
TP_SDVO_STALLN
TP_SDVO_TVCLKINP
TP_SDVO_TVCLKINN
DP_IG_D_MLP<3>
DP_IG_D_MLN<2>
DP_IG_D_MLP<1>
DP_IG_D_MLN<1>
DP_IG_D_MLP<0>
DP_IG_D_MLN<0>
DP_IG_D_HPD
DP_IG_C_MLN<0>
DP_IG_C_HPD
DP_IG_C_AUX_P
DP_IG_C_AUX_N
DP_IG_C_CTRL_DATA
DP_IG_C_CTRL_CLK
DP_IG_B_MLP<1>
DP_IG_B_AUX_P
DP_IG_B_MLP<0>
DP_IG_B_MLN<3>
DP_IG_B_MLN<1>
PM_PCH_SYS_PWROK
PCH_DMI_COMP
DMI_S2N_P<1>
DP_IG_B_HPD
DP_IG_B_AUX_N
DMI_N2S_P<2>
DMI_S2N_N<0>
TP_PCH_RESERVE_7
TP_PCH_RESERVE_5
TP_PCH_RESERVE_4
TP_PCH_RESERVE_3
TP_PCH_RESERVE_1 TP_PCH_RESERVE_2
TP_PCH_RESERVE_8
TP_PCH_RESERVE_12
TP_PCH_RESERVE_15 TP_PCH_RESERVE_16 TP_PCH_RESERVE_17
TP_PCH_RESERVE_0
TP_PCH_RESERVE_13
TP_PCH_RESERVE_20 TP_PCH_RESERVE_21
TP_PCH_RESERVE_19
TP_PCH_RESERVE_18
TP_PCH_RESERVE_26
TP_PCH_RESERVE_28
TP_PCH_RESERVE_27
TP_CRT_IG_BLUE TP_CRT_IG_GREEN
TP_CRT_IG_DDC_CLK
TP_CRT_IG_HSYNC TP_CRT_IG_VSYNC
=PP3V3_S0_PCH_GPIO
PCH_FDI_RX_N<1>
PM_SYNC
PCH_GPIO72
PM_PWRBTN_L
PM_CLK32K_SUSCLK_R
PCH_DAC_IREF
=PP3V3_S5_PCH
=TBT_WAKE_L
PCH_FDI_RX_N<5>
PCH_FDI_RX_N<4>
PCH_FDI_RX_N<3>
PCH_FDI_RX_N<2>
PCH_FDI_RX_N<6> PCH_FDI_RX_N<7>
PCH_FDI_RX_P<6>
PCH_FDI_INT
PCH_FDI_FSYNC<1>
PCH_FDI_LSYNC<0>
PCH_FDI_RX_P<7>
PCH_FDI_RX_P<2>
PCH_FDI_RX_P<0> PCH_FDI_RX_P<1>
PCH_FDI_RX_P<3>
TP_PCH_RESERVE_22 TP_PCH_RESERVE_23 TP_PCH_RESERVE_24 TP_PCH_RESERVE_25
PCH_FDI_RX_P<4> PCH_FDI_RX_P<5>
TP_PCH_INIT3V3_L
TP_CRT_IG_DDC_DATA
TP_CRT_IG_RED
prefsb
051-9505
8.0.0
19 OF 144 19 OF 123
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
12
BN56
BC56
J38
BT43
BK38
BE52
E37
B37
C36 F38
E31
BP45
BD43
BR42
R47
BH49
F55
BC41
BM53
BN52
BA47
BN54
E49
C52
H46
P43
H43
C49
A46
D47
F43
M43
J43
B47
B45
C46
H41
F45
C42
BJ48
BU46
BJ38
BJ53
B31
A32
P38
J36
B35
B33
B43
D51
D33
J41
A36
B51
BC46
H38 M41
H36 R38
BG43 AV46
P41
BH50
BC44
BT37
BG46
Y50
R9 R8
R14 M12 M11
M3 L5
AL12 AL14
U12 U14 N2
J3
AL9 AL8
M1
B5 D5 D7 C6 C9
E11
U43 M49 M50 R50
U44 U46 U50 R44
U49 AB44 AB49
E52
H52
F53
J55
L56
K46
AB50
L53
Y44
G56 AB46
K49
K50
M48
AM1
AN2
AN6
AW3
AW1
AR4
AR2
AT3
AM6
U9 U8
U5 W3
T3 U2
AL15 AL17
T1
R12
K8 H8
L2 G4 G2 F5 F3 E2 E4
R6 N6
B7 B11
Y41
H50
J57
1
2
1
2
120
103
11
103
19 35 40
120
15
120
19
15
19
120
8
8
8
8
8
8
8
8
6
18
8
8
19
120
19
6
19 24 26
6
18 22 24
8
6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
103
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
6
15 20 38
8
15
6
19 24 26
36
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BI
BI
BI
BI
BI BI
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
USB3TN1
USB3TP1
USB3RN1
USB3RN2
USB3RP2
CLKOUT_PCI0 CLKOUT_PCI1
USBP13P
AD0 AD1 AD2 AD3
AD18
USBP8P
USBP8N
USBP7P
AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17
AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28
PIRQD*
REQ0*
REQ2*/GPIO52 REQ3*/GPIO54
GNT0*
GNT3*/GPIO55
PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5
PCIRST*
SERR* PERR*
IRDY* PAR DEVSEL* FRAME*
PLOCK*
STOP* TRDY*
PME*
PLTRST*
USBP0N USBP0P
USBP1N USBP1P
USBP2N USBP2P
USBP3N USBP3P
USBP4N USBP4P
USBP5N USBP5P
USBP6N USBP6P
USBP7N
USBP9N USBP9P
USBP10N
USBP11N USBP11P
USBP12N
USBP13N
USBRBIAS*
REQ1*/GPIO50
AD29 AD30 AD31
USBP12P
USBP10P
C/BE3*
C/BE0* C/BE1* C/BE2*
PIRQA*
GNT2*/GPIO53
GNT1*/GPIO51
PIRQC*
PIRQB*
USBRBIAS
USB3RP1
CLKOUT_PCI4
CLKOUT_PCI3
CLKOUT_PCI2
USB3TN2
USB3TP2
USB3RP3
USB3RN3
USB3TP3
USB3TN3
USB3RN4
USB3RP4
USB3TP4
USB3TN4
OC0*/GPIO59
OC2*/GPIO41
OC1*/GPIO40
OC3*/GPIO42 OC4*/GPIO43
OC5*/GPIO9
OC7*/GPIO14
OC6*/GPIO10
USB
(5 OF 10)
PCI
IN
IN
IN IN
OUT
IN IN IN IN
OUT
IN IN
IN
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI BI
OUT
OUT
OUT
OUT
BI BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
UNUSED
UNUSED
CAMERA
INTERNAL HUB (BT,SMC12)
EHCI - EXT D
UNUSED
EHCI - EXT B
UNUSED
UNUSED
UNUSED
EXT D
EXT C
EXT B
EXT A
TIE TRACES TOGETHER CLOSE TO PINS
PLACE THE RESISTOR CLOSE TO COMMON POINT
45
106
45
106
8
8
45
106
45
106
45
106
45
106
45
106
45
106
45
106
45
106
45
106
45
106
46
106
46
106
46
106
46
106
46
106
46
106
46
106
U1800
FCBGA
PANTHER-POINT
OMIT_TABLE
46
106
R2019
NOSTUFF
402
MF-LF
1/16W
5%
10K
60
62
15 36
122
15 35
117
15 45
103
15 45
103
15 46
103
15 46
103
15
103
15
103
15
103
15 41
103
R2001
0
MF5%
1/20W
201
SIGNAL_MODEL=EMPTY
R2002
MF5%
1/20W
201
0
SIGNAL_MODEL=EMPTY
201
SIGNAL_MODEL=EMPTY
0
MF5%
1/20W
R2003
R2007
SIGNAL_MODEL=EMPTY
201
MF
0
5%
1/20W
R2004
SIGNAL_MODEL=EMPTY
0
MF5%
1/20W
201 201
MF
0
5%
1/20W
R2005
SIGNAL_MODEL=EMPTY
MF
0
5%
1/20W
201
R2006
SIGNAL_MODEL=EMPTY
R2008
201
0
1/20W
MF5%
SIGNAL_MODEL=EMPTY
45
106
45
106
46
106
46
106
46
106
8
46
106
8
8
8
8
8
42
42
46
106
46
106
8
8
R2070
PLACE_NEAR=U1800.BM25:2mm
1%
402
MF-LF
1/16W
R2010
1/16W
5% 402
MF-LF
10K
R2011
10K
5% 402
MF-LF1/16W
R2012
5%
10K
1/16W
402
MF-LF
R2013
10K
1/16W5%MF-LF
402
R2015
402
1/16W5%MF-LF
10K
R2016
5% 402
1/16W MF-LF
10K
R2017
1/16W
5% 402
MF-LF
10K
R2020
MF-LF
402
1/16W
10K
5%
R2021
402
MF-LF1/16W
10K
5%
R2022
MF-LF
402
1/16W
5%
10K
26
120
26
105
26
105
26
105
R2023
MF-LF
402
1/16W
5%
10K
R2024
MF-LF1/16W
5%
10K
402
R2026
10K
5% 402
MF-LF1/16W
R2025
5%
MF-LF
10K
1/16W
402
R2027
MF-LF
10K
5%
1/16W
402
27
106
27
106
8
8
R2030
402
10K
1/16W5%MF-LF
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
PCH PCI/USB
AP_PWR_EN
USB_EXTB_OC_EHCI_L
USB_EXTC_OC_L
PCI_PERR_L
PCI_INTB_L PCI_INTC_L PCI_INTD_L
PCI_REQ0_L
USB_EXTB_OC_R_L
USB_EXTA_OC_L
SDCONN_STATE_CHANGE
USB3_EXTC_RX_F_N
USB_PCH_13_P
USB3_EXTA_TX_N
USB3_EXTD_TX_P
USB3_EXTD_TX_N
USB_EXTA_OC_R_L
USB_EXTC_OC_R_L USB_EXTD_OC_R_L USB_EXTB_OC_EHCI_R_L
AP_PWR_EN_R
USB_EXTD_OC_EHCI_L
USB3_EXTD_RX_F_P
USB3_EXTD_RX_F_N
TP_PCI_CLK33M_OUT2
PCI_DEVSEL_L
USB3_EXTB_TX_P
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3>
PCI_INTA_L
PCH_USB_RBIAS
TP_PCI_AD<29>
SDCONN_STATE_CHANGE_R
USB_EXTD_OC_EHCI_R_L
USB_EXTB_OC_L
TP_PCI_PME_L
USB3_EXTA_TX_P
PCH_CLK33M_PCIOUT
PCI_FRAME_L
TP_PCI_PAR
TP_PCI_AD<30> TP_PCI_AD<31>
TP_PCI_C_BE_L<1>
PCI_PLOCK_L
TP_PCI_AD<11> TP_PCI_AD<12> TP_PCI_AD<13>
USB_PCH_9_N
USB_PCH_12_N
TP_PCI_AD<2>
TP_PCI_AD<0>
TP_PCI_AD<3> TP_PCI_AD<4>
TP_PCI_RESET_L
AUD_IP_PERIPHERAL_DET
TP_PCH_PCI_GNT0_L
AUD_I2C_INT_L
LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R
TBT_PWR_REQ_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
BLC_GPIO
TP_PCI_AD<6>
BT_PWR_RST_L
TP_PCH_STRP_ESI_L
TP_PCH_STRP_BBS1
JTAG_GMUX_TMS
TP_PCI_AD<28>
TP_PCI_CLK33M_OUT3
USB_PCH_11_N
USB3_EXTC_TX_P
PLT_RESET_L
USB3_EXTA_RX_F_P
USB_PCH_10_P
USB_PCH_12_P
USB_PCH_13_N
USB_PCH_11_P
USB_PCH_10_N
USB_PCH_9_P
USB_PCH_7_N
USB_PCH_6_P
USB_PCH_6_N
USB_PCH_5_P
USB_PCH_5_N
USB_PCH_4_P
USB_PCH_4_N
USB_PCH_3_P
USB_PCH_3_N
USB_PCH_2_P
USB_PCH_2_N
USB_PCH_1_P
USB_PCH_1_N
USB_PCH_0_P
USB_PCH_0_N
TP_PCI_AD<27>
TP_PCI_AD<26>
TP_PCI_AD<25>
TP_PCI_AD<24>
TP_PCI_AD<23>
TP_PCI_AD<22>
TP_PCI_AD<21>
TP_PCI_AD<20>
TP_PCI_AD<19>
TP_PCI_AD<17>
TP_PCI_AD<16>
TP_PCI_AD<15>
TP_PCI_AD<14>
TP_PCI_AD<10>
TP_PCI_AD<9>
TP_PCI_AD<8>
TP_PCI_AD<7>
TP_PCI_AD<5>
USB_PCH_7_P
USB_PCH_8_N USB_PCH_8_P
TP_PCI_AD<18>
TP_PCI_AD<1>
USB3_EXTB_RX_F_P
USB3_EXTB_RX_F_N
USB3_EXTA_RX_F_N
PCH_STRP_TOPBLK_SWP_L
PCI_SERR_L
USB3_EXTC_TX_N
USB3_EXTC_RX_F_P
USB3_EXTB_TX_N
=PP3V3_S0_PCH_GPIO
BLC_I2C_MUX_SEL
USB_EXTD_OC_L
prefsb
051-9505
8.0.0
20 OF 144 20 OF 123
C29
E29
H31
J27
L27
AT11 AN14
BK27
BF15 BF17
BT7
BT13
BC6
BR29
BN27
BD31
BG12 BN11 BJ12
BU9
BR12
BJ3 BR9
BJ10
BM8 BF3 BN2 BE4 BE6
BG15
BT11 BA14
BL2 BC4 BL4 BC2
BM13
BA9 BF9 BA8
BP5
BG5
BK8
AV11
BA15
BE2
BN9 AV9
BT15
BR4
AV14
BR6 BM3
BF11
BH8 BH9
BC11
BA17
BC12
BC8
AV15
BK48
BF36 BD36
BC33 BA33
BM33 BM35
BT33 BU32
BR32 BT31
BN29 BM30
BK33 BJ33
BF31
BR26 BT27
BK25
BJ31 BK31
BF27
BJ27
BP25
BT5
BF8 AV17 BK12
BD27
BJ25
BP13
BN4
BP7
BG2
BK10
BU12
AV8
BM15
BJ5
BM25
J31
AT14
AT17
AT12
F28
E27
L25
J25
B27
C26
L22
J22
D25
B25
BM43
BG41
BD41
BK43 BP43 BJ41
BM45
BT45
1
2
1 2 1 2 1 2
1 2
1 2 1 2 1 2
1 2
1
2
1 2 1 2 1 2 1 2
1 2 1 2 1 2
1 2 1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
8
8
8
8
106
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
119
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
120
6
15 19 38
OUT
IN
OUT
IN
NCTF
RSVD
GPIO
MISC
CPU
NCTF
(6 OF 10)
VSS_NCTF
SDATAOUT0/GPIO39
SLOAD/GPIO38
SATA4GP/GPIO16
PCIECLKRQ6*/GPIO45
TACH4/GPIO68
A20GATE
BMBUSY*/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N CLKOUT_PCIE7P
GPIO27
GPIO28
GPIO35/NMI*
GPIO57
GPIO8
NC_5
PCIECLKRQ7*/GPIO46
PECI
PROCPWRGD
PWM0 PWM1 PWM2 PWM3
RCIN*
SATA3GP/GPIO37
SATA5GP_GPIO49
SCLOCK/GPIO22
SDATAOUT1/GPIO48
SST
STP_PCI*/GPIO34
TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
THRMTRIP*
TP1
TP10
TP11
TP12
TP13
TP14
TP16
TP17
TP18
TP19
TP2
TP20
TP3
TP4
TP5
TP6
TP7
TP8
TP9
NC_1 NC_2 NC_3 NC_4
VSSADAC
GPIO15
LAN_PHY_PWR_CTRL/GPIO12
GPIO24/PROC_MISSING
SATA2GP/GPIO36
TP15
BI
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
NC
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
RDAR://11363991 D7/D7I/D8/J35/J36: RENAME GPU/TBT MUX SELECT TO DP_TBT_SEL
Place this near the T point
X
11 25 28
103
48
120
R2155
402
10K
MF-LF
1/16W
5%
R2150
5%
10K
1/16W MF-LF
402
28 34
103
R2190
402
1/16W MF-LF
100K
5%
49
119
R2170
MF-LF1/16W
402
5%
0
NOSTUFF
R2140
MF-LF
402
5%
1/16W
0
U1800
OMIT_TABLE
PANTHER-POINT
FCBGA
11 47 48
103
5
103
15 47
122
38
122
26
103
62 75
103
15
103
15
119
15
117
15
122
15 26
103
49
105
MF
1/20W
SIGNAL_MODEL=EMPTY
R2106
201
0
5%
R2101
0
MF
1/20W
5%
201
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
0
1/20W
MF5%
201
R2104
MF
SIGNAL_MODEL=EMPTY
201
5%
0
R2107
1/20W
R2108
1/20W
MF
201
5%
0
SIGNAL_MODEL=EMPTY
R2103
SIGNAL_MODEL=EMPTY
MF
201
1/20W
5%
0
R2109
SIGNAL_MODEL=EMPTY
201
0
5%
1/20W
MF
SIGNAL_MODEL=EMPTY
MF
1/20W
0
201
5%
R2105
R2110
33
201
MF
1/20W
5%
R2111
MF
201
33
1/20W
5%
43
106
43
120
1/20W
R2113
201
33
5% MF
80
120
80
120
5%331/20W
201
MF
R2112
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
PCH MISC
TP_PCH_TP20
JTAG_TBT_TCK_R
TBT_PCH_CLKREQ_L
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
ISOLATE_CPU_MEM_R_L
JTAG_TBT_TDI
AUD_IPHS_SWITCH_EN_PCH
CPU_PWRGD
CPU_PECI
=PP3V3_S0_PCH
JTAG_TBT_TCK
=PP3V3_S0_PCH
TBT_CIO_PLUG_EVENT
DP_TBT_SEL
PCH_CAM_RESET_R
ENET_LOW_PWR_PCH
JTAG_TBT_TDO
AUD_IPHS_SWITCH_EN_PCH_R
AP_CLKREQ_L
PCH_A20GATE
TBT_CIO_PLUG_EVENT_R TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N TP_PCIE_CLK100M_PE7P
HDD_PWR_EN
PCH_PECI
PCH_PROCPWRGD
TP_PCH_PWM0 TP_PCH_PWM1 TP_PCH_PWM2 TP_PCH_PWM3
PCH_RCIN_L
ENET_LOW_PWR_PCH_R
PCH_GPIO22
TP_PCH_SST
TBT_SW_RESET_R_L
LPCPLUS_GPIO
PCH_GPIO1
PCH_GPIO6
SMC_RUNTIME_SCI_L
PM_THRMTRIP_L
TP_PCH_TP1
TP_PCH_TP10
TP_PCH_TP11
TP_PCH_TP12
TP_PCH_TP13
TP_PCH_TP14
TP_PCH_TP16
TP_PCH_TP17
TP_PCH_TP18
TP_PCH_TP19
TP_PCH_TP2
TP_PCH_TP3
TP_PCH_TP4
TP_PCH_TP5
TP_PCH_TP6
TP_PCH_TP7
TP_PCH_TP8
TP_PCH_TP9
XDP_PIN03
WOL_EN
TP_PCH_TP15
PCH_CAM_RESET
SPIROM_USE_MLB
PCH_GPIO48
PCH_CAM_EXT_BOOT_L
PCH_BLC_MCU_RESET
PCH_BLC_EXT_BOOT_R
PCH_BLC_EXT_BOOT
ISOLATE_CPU_MEM_L
GPU_GOOD
GPU_GOOD_R
DP_TBT_SEL_R
TBT_SW_RESET_L
PCH_CAM_EXT_BOOT_R_L
PCH_BLC_MCU_RESET_R
prefsb
051-9505
8.0.0
21 OF 144 21 OF 123
1
2
1
2
1
2
1 2
1 2
A6
A4
BF55
BE54
AU56
AV44
BU16
BM57
B2
BB57
AW55
AB3 AA2
AE2 AF1
BJ43
BJ55
BJ57
BT53
BP51
AY20
BP55
H48
D53
BN21 BT21 BM20 BN19
BG56
BG53
BA56
BA53
AW53
BC43
BL56
BT17
BR19
BA22
BR16
BM18
BN17
BP15
E56
P22
BM46
BA27
BC49
AE49
AE41
AE50
BA36
AY36
Y14
L31
Y12
L33
M38
L36
Y18
Y17
AB18
AB17
A54 A52 F57 D57
BU54
BU6
BM1
BP1
BU4
BU52
AU2
BM55
BK50
BT2
BP57
BP53
BB55
AE43
F1
D1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
8
25
103
15 36
15 47
122
25
103
15
119
6
18 21 24
6
18 21 24
15
103
25
103
25
103
8
8
8
8
52
118
120
8
8
8
8
120
25
103
15
8
15
15
15
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
25
103
15 40
123
8
15
120
15
15
15
120
25
103
25
103
VCCAPLLEXP
VCCCLKDMI
VCCAPLLDMI2
VCCIO
VCCADAC
VCCVRM1
VCCIO
VCC3_3_0
VCCVRM0
VCCASW
VCCCORE
VCC3_3
VCCAFDIPLL
VCCDMI
(7 OF 10)
VCCIO_DMI/CLK
VCC CORE
CRTDMI
FDI
VCCASW
VCCIO_PCIE
HVCMOS
V_PROC_IO_NCTF
VCCRTC
V5REF_SUS
VCCADPLLB
VCCSPI
VCCIO
V5REF
VCCAPLLSATA
VCC3_3
DCPSUSBYP
VCCACLK
DCPRTC
VCCADPLLA
DCPSST
V_PROC_IO
VCCDFTERM0 VCCDFTERM1
VCCDIFFCLKN
VCCDSW3_3
VCCIO
VCCVRM3
VCCSUSHDA
VCCVRM2
DCPRTC_NCTF
VCCSUS3_3
VCCSSC
VCC3_3
DCPSUS
SATA
PCI/GPIO/LPC
PCI/GPIO/LPC
(10 OF 10)
USB
CPURTC
HDA
CLOCK AND MISCELLANEOUS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH output, for decoupling only
Max and Idle = 1mA
20mA Max, 10mA Idle
(VCCIO[1-31] total)
3.456A Max, 426mA Idle
PCH output, for decoupling only
57 mA Max, 30mA Idle
1.44 A Max, 474mA Idle
55mA Max, 5mA Idle
20mA Max, 1mA Idle
3mA Max, 1mA Idle
200 mA Max, 2mA Idle
(VCCSUS3_3 - 11 TOTAL)
Need to check layout decoupling
409 mA Max, 42mA Idle
Max and Idle = 1 MA
40mA Max, 10mA Idle
40mA Max, 5mA Idle
Max and Idle = 1mA
97mA Max, 15mA Idle
(VCCVRM 4 total)
159mA Max, 114mA Idle
105mA Max, 90mA Idle
10 mA Max, 1mA Idle
1.61A Max, 433mA Idle
(VCC3_3[1-9] total)
Max and Idle = 1mA
10V CERM
20%
402
0.1UF
C2210
PLACE_NEAR=U1800.BR54:4MM
10%
201
X5R
6.3V
0.1UF
PLACE_NEAR=U1800.BA46:2mm
C2222
20% 10V CERM 402
C2232
PLACE_NEAR=U1800.BU42:2mm
0.1UF
1UF
6.3V
10%
PLACE_NEAR=U1800.BU42:2mm
402
CERM
C2231
PANTHER-POINT
FCBGA
OMIT_TABLE
U1800
PANTHER-POINT
FCBGA
OMIT_TABLE
U1800
PCH POWER
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
=PP3V3_G3_PCH_RTC
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=3.3V
PPVOUT_S0_PCH_DCPSST
=PP5V_S5_PCH_V5REFSUS
=PP5V_S0_PCH_V5REF
TP_PP1V05_S0_PCH_VCCAPLL_SATA
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S5_PCH_VCCSUS_USB
TP_PP1V05_S0_PCH_FDIPLL
=PP3V3_S0_PCH_VCC_PCI
=PP1V05_S0_PCH_VCC_ASW
=PP3V3_S0_PCH_VCC_HVCMOS
=PP1V05_S0_PCH_VCC_CORE
PP1V05_S0_PCH_VCCADPLLB_F
PP1V8_S0_PCH_VCCVRM_F
TP_PP1V05_S0_PCH_VCCAPLL_EXP
TP_DCPSUS_0
=PP1V05_S0_PCH_VCC_SSC
PP1V8_S0_PCH_VCCVRM_F
=PP3V3_S5_PCH_VCC_DSW
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP1V8_S0_PCH_VCC_DFTERM
PP1V05_S0_PCH_VCCADPLLA_F
=PP3V3_S5_PCH_VCC_SPI
PP1V8_S0_PCH_VCCVRM_F
PP3V3_S0_PCH_VCCA_DAC_FTP_PPVOUT_PCH_DCPSUSBYP
=PP1V05_S0_PCH_VCC_DMI
=PP3V3_S0_PCH_VCC
TP_DCPSUS_2
=PP3V3_S0_PCH_VCC_GPIO
=PP1V05_S0_PCH_VCCIO_DMI
PP1V8_S0_PCH_VCCVRM_F
=PP1V05_S0_PCH_VCCCLKDMI
TP_PP1V05_S0_PCH_VCCAPLLDMI2
=PP1V05_S0_PCH_VCCIO_PCIE
=PP3V3_S5_PCH_VCCSUS_HDA
TP_DCPSUS_1
=PP1V05_S0_PCH_V_PROC_IO
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PPVOUT_G3_PCH_DCPRTC
=PP1V05_S0_PCH_VCCIO_USB
TP_PP1V05_S0_PCH_VCC_A_CLK
prefsb
051-9505
8.0.0
22 OF 144 22 OF 123
2
1
2
1
2
1
2
1
AG26 AG28 AJ24
AN34
AL34
AJ28
AJ26
B53
AJ20
A19
AN32
AC32
Y26
V33
AA36
Y20 Y22 Y24
Y28 V22 V25 V27 F20
AT1
R56
B41
Y30 Y32
Y34
Y36
V36 V31 F30
AF57
AJ1
AU32 AV36 AU34 AG24
AL24 AL28 AN22 AN24 AN26 AN28 AR24 AR26 AR28 AR30 AR36 AR38 AU30 AU36
AC24 AC26 AC28 AC30
AE24 AE28 AE30 AE32 AE34 AE36
AJ32 AJ34 AJ36 AL32
AR32 AR34
BC17 BD17 BD20
C54
E41
AG32 AG34
AA34
B56
BU42
BT25
AC2
AN52
AG40 AG38 AG41 BA38 AN40 AN41
BF1
U56
AV20
AU20
A12
AN38
AV41
AL5
BR54
AB1
BA46
AT41
AU22
D55
T55 T57
AE15 AE17 AG15
AV40
AY25 AY27 AV24 AV26
AV30 AV32 AY31 AY33 BJ36 BK36 BM36 AT40 AU38 BT35
AJ38 AE40
AL40
R2
AV28
R54
BT56
U31
AC20 AE20
AL38
AA32
A39
6
24
24
6
18 24
6
24
6
24
6
24
6
24
6
24
17
120
22 24
120
6
24
22 24
120
6
24
6
24
6
24
17
120
6
24
22 24
120
17
121
6
24
6
24
6
24
6
24
22 24
120
6
24
6
18 19 24
6
24
6
24
6
24
VSS
VSS
(8 OF 10)
VSS
VSS
(9 OF 10)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FCBGA
PANTHER-POINT
OMIT_TABLE
U1800
FCBGA
PANTHER-POINT
OMIT_TABLE
U1800
PCH GROUNDS
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
prefsb
051-9505
8.0.0
23 OF 144 23 OF 123
AE56 BR36
AB15
AB43
AA28
AN11
AM57
AM52
AM3
AL47
AL46
AL41
AL36
AL30
AL26
AL22
AL20
AL18
AL11
AJ22 AJ30
AK6
AK52
AJ57
AG5 AG50 AG53 AH52
AH6
AG30 AG36 AG43 AG44 AG46
AF6 AG11 AG14 AG20 AG22
AF52
AE4 AE47
AE8
AE9
AE38
AE14 AE18 AE22 AE26
AC54
AC34 AC36
AC4
AC22
AB47 AB52 AB57
AB6
AB11
AA38
AB40 AB41
AA30
AA26
AA24
AA22
AA20
A9
A49
A42
A26
BG33 BG36
BG31
BF25 BF33 BF41 BF43 BF46 BF52 BF6 BG22 BG25 BG27
BC27 BC31 BC36 BC38 BC47 BC9 BD25 BD33 BF12 BF20
BA41 BA44 BA49 BB1 BB3 BB52 BB6 BC14 BC15 BC20
BA31
AV47 AV6 AW57 AY38 AY6 B23 BA11 BA12
AV34
AT52 AT6 AT8 AU24 AU26 AU28 AU5 AV12 AV18 AV22
AN54 AN9 AR20 AR22 AR52 AR6 AT15 AT18 AT43 AT47
AN12 AN15 AN17 AN18 AN20 AN30 AN36 AN4 AN43 AN47
AC38
AV38
A29
AY22
C12
J46 J48 J5 J53 K52 K6 K9 L12 L17 L38 L41 L43 M20 M22 M25 M27 M31 M33 M36 M46 M52 M57 M6 M8 M9 N4 N54 R11 R15 R17 R22 R4 R41 R43 R46 R49
T6 U11 U15 U17 U20 U22 U25 U27 U33 U36 U38 U41 U47 U53 V20 V38 V6 W1 W55 W57 Y11 Y15 Y38 Y40 Y43 Y46 Y47 Y49 Y52 Y6 AL43 AL44 R36 P36 R25 P25
BH52
BH6
BJ1 BJ15 BK20 BK41 BK52
BK6 BM10 BM12 BM16 BM22 BM23 BM26 BM28 BM32 BM40 BM42 BM48
BN47
BN6
BP3 BP33 BP35 BR22 BR52 BU19 BU26 BU29 BU36 BU39
C19
C32
C39
C4 D15 D23
D3 D35 D43 D45 E19 E39 E54
E6
E9 F10 F12 F16 F22 F26 F32 F33 F35 F36 F40 F42 F46 F48 F50
F8 G54 H15 H20 H22 H25 H27 H33
H6
J1 J33
T52
BN31
BM5
BG38
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1 mA S0-S5
PLACEMENT_NOTE:
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PLACEMENT_NOTE:
<1 MA
PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)
<1 MA S0-S5
PLACEMENT_NOTEs:
(PCH PCI 3.3V PWR)
PCH VCC3_3 BYPASS
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PLACEMENT_NOTEs:
PLACEMENT_NOTEs:
1 mA
(PCH DMI 1.05V PWR)
PCH VCCIO BYPASS
INTEL PDG: 1X 0.1UF
INTEL PDG: 1X 0.1UF
PLACEMENT_NOTE:
INTEL PDG: 2X 1UF
PLACEMENT_NOTES:
PCH VCCIO BYPASS (PCH USB 1.05V PWR)
PLACEMENT_NOTEs:
(PCH HD Audio 3.3V/1.5V PWR)
PLACEMENT_NOTE:
INTEL PDG: 1X 0.1UF
PLACEMENT_NOTEs:
INTEL PDG: 4X 1UF AND 2X 10UF
FOR PCH_VCC_DIFFCLK AND PCH_VCC_CORE
(PCH 1.05V CORE PWR)
PLACEMENT_NOTEs:
PCH VCCCORE BYPASS
PCH VCCSUS3_3 BYPASS
PLACEMENT_NOTEs:
(PCH Reference for 5V Tolerance on PCI)
INTEL PDG: 1X 1UF
INTEL PDG: 2X 0.1UF AND 1X 2.2UF
PLACEMENT_NOTEs:
PCH VCCSUSHDA BYPASS
(PCH SUSPEND USB 3.3V PWR)
PLACEMENT_NOTE:
INTEL PDG: 2X 0.1UF AND 1X 4.7UF
PLACEMENT_NOTEs (all 3):
PLACEMENT_NOTEs:
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PCH V5REF Filter & Follower
PLACE C2439 AT BALL BF1
C2439
X5R
10% 10V
402
1UF
1
2
R2405
MF-LF
1/16W
402
5%
100
PLACE C2438 AT BALL BT25
C2438
10V
0.1UF
CERM
402
20%
D2400
BAT54DW-X-G
SOT-363
R2404
1
2
10
1/16W MF-LF
5%
402
D2400
SOT-363
BAT54DW-X-G
402
5%
1/16W
0
R2400
MF-LF
10V CERM
20%
402
0.1UF
C2440
PLACE C2440 AT BALL T55
PLACE C2441 AT BALL AV28
C2441
10V 402
CERM
20%
0.1UF
C2450
6.3V
10%
402
CERM
1UF
PLACE C2450 AT BALL AV26
C2419
CERM
6.3V
1UF
10%
402
PLACE C2419 AT BALL B41
10%
6.3V
1UF
CERM 402
PLACE C2422 AT BALL AU20
C2422
C2449
6.3V
10%
1UF
402
CERM
PLACE C2449 AT BALL AY27
X5R 402
20%
6.3V
4.7UF
C2416
PLACE C2416 AT BALL D55
C2485
402
0.1UF
25V
10% X5R
PLACE C2485 AT BALL AL38
805-1
6.3V
20%
CERM
C2410
10UF
PLACE C2410 AT BALL Y20
C2463
CERM
6.3V
10%
1UF
402
PLACE C2463 AT BALL V25
10UF
C2480
805-1
20%
CERM
6.3V
PLACE C2480 AT BALL AC20
10%
1UF
C2475
6.3V CERM 402
PLACE C2475 AT BALL AE20
C2437
805-1
6.3V
20%
CERM
10UF
PLACE C2437 AT BALL AE15
C2435
402
6.3V
10%
1UF
CERM
PLACE C2435 AT BALL AE17
C2434
10% CERM
402
6.3V
1UF
PLACE C2434 AT BALL AE15
C2471
CERM
6.3V
20%
10UF
805-1
PLACE C2471 AT BALL AA34
1UF
C2469
402
6.3V CERM
10%
PLACE C2469 AT BALL V36
CERM
6.3V
10%
402
1UF
C2414
PLACE C2414 AT BALL Y26
805
10UF
CERM
6.3V
20%
C2401
PLACE C2401 AT BALL V22
1UF
C2487
6.3V CERM 402
10%
PLACE C2487 AT BALL E41
C2452
10%
402
6.3V CERM
1UF
PLACE C2452 AT BALL AG38
10%
402
6.3V CERM
1UF
C2453
PLACE C2453 AT BALL AJ38
PLACE C2412 AT BALL AT40
10%
6.3V X5R 402
C2412
2.2UF
C2499
0.1UF
10V
CERM
20%
402
PLACE C2499 AT BALL AV40
PLACE C2442 AT BALL AN52
6.3V
C2442
402
1UF
10% CERM
20%
6.3V CERM
805-1
PLACE C2445 AT BALL R2
10UF
C2445
CERM
10%
1UF
402
6.3V
PLACE C2443 AT BALL AJ1
C2443
PLACE C2436 AT BALL R54
1UF
10%
C2436
6.3V CERM 402
C2486
25V
402
10%
0.1UF
PLACE C2486 AT BALL AU22
X5R
C2444
1UF
CERM
6.3V
402
10%
PLACE C2444 AT BALL BA38
C2446
10%
6.3V CERM 402
1UF
PLACE C2446 AT BALL AY25
10UF
PLACE C2472 AT BALL V31
C2472
6.3V CERM
20%
805-1
C2470
CERM
6.3V
PLACE C2470 AT BALL Y32
10%
402
1UF
C2473
20%
PLACE C2473 AT BALL F30
805-1
10UF
6.3V CERM
C2425
CERM
PLACE C2425 AT BALL BD20
1UF
6.3V
402
10%
C2427
1UF
CERM
PLACE C2427 AT BALL BD17
6.3V
402
10%
PLACE C2461 AT BALL AR32
6.3V
10UF
20%
CERM
805-1
C2461
20%
805-1
CERM
10UF
6.3V
PLACE C2460 AT BALL AJ34
C2460
402
6.3V
1UF
10% CERM
C2482
PLACE C2482 AT BALL AC24
C2481
CERM
10%
1UF
402
6.3V
PLACE C2481 AT BALL AC32 PLACE C2483 AT BALL AL34
402
10%
1UF
6.3V
C2483
CERM
C2407
10%
1UF
6.3V CERM 402
PLACE C2407 AT BALL Y28
6.3V
C2415
805-1
CERM
20%
10UF
PLACE C2415 AT BALL F20
CERM
6.3V
1UF
10%
PLACE C2429 AT BALL Y24
C2429
402
C2428
805-1
20%
CERM
6.3V
10UF
PLACE C2428 AT BALL AJ24
C2420
805-1
10UF
CERM
20%
6.3V
PLACE C2420 AT BALL AU32
805-1
10UF
20%
6.3V CERM
C2418
PLACE C2418 AT BALL AN22
C2498
402
1UF
10%
6.3V CERM
PLACE C2498 AT BALL AR24
402
CERM
10%
6.3V
1UF
C2496
PLACE C2496 AT BALL AR36
10%
1UF
402
CERM
PLACE C2456 AT BALL AG28
C2456
6.3V
10%
6.3V CERM 402
1UF
C2426
PLACE C2426 AT BALL AU30
PLACE C2411 AT BALL AJ20
1UF
402
16V X5R
10%
C2411
402
C2455
PLACE C2412 AT BALL AV30
6.3V X5R
10%
2.2UF
0402
X7R-CERM
16V
10%
0.1UF
C2490
0402
X7R-CERM
16V
10%
0.1UF
C2413
0402
X7R-CERM
16V
10%
0.1UF
C2484
0.1UF
10% 16V X7R-CERM 0402
C2430
0402
16V
10%
0.1UF
X7R-CERM
C2417
0402
X7R-CERM
16V
10%
0.1UF
C2421
10%
0.1UF
16V X7R-CERM 0402
C2423
10% 16V X7R-CERM 0402
0.1UF
C2424
0.1UF
16V 0402
10% X7R-CERM
C2447
PCH DECOUPLING
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
PP1V8_S0_PCH_VCCVRM_F
VOLTAGE=1.8V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
PP5V_S5_PCH_V5REFSUS
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.3MM VOLTAGE=5V
=PP3V3_S0_PCH_VCC_HVCMOS
=PP3V3_S0_PCH_VCC
=PP1V05_S0_PCH_V_PROC_IO
=PP3V3_S0_PCH_VCC_PCI
=PP3V3_S5_PCH_VCCSUS_USB
=PP5V_S0_PCH
=PP5V_S0_PCH_V5REF
=PP1V05_S0_PCH_VCC_ASW
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP1V05_S0_PCH_VCCIO_USB
=PP3V3_S5_PCH_VCCSUS_HDA
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S5_PCH_VCC_DSW
=PP1V05_S0_PCH_VCC_DMI
=PP3V3_S0_PCH
=PP1V05_S0_PCH_VCC_SSC
=PP3V3_S5_PCH =PP5V_S5_PCH
=PP1V8_S0_PCH_VCC_VRM
=PP1V8_S0_PCH_VCC_DFTERM
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S0_PCH_VCC_GPIO
=PP1V05_S0_PCH_VCCCLKDMI
=PP5V_S5_PCH_V5REFSUS
PP5V_S0_PCH_V5REF
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM
prefsb
051-9505
8.0.0
24 OF 144 24 OF 123
2
1
2
1
6
1
5
3
4
2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
22
120
121
6
22
6
22
6
22
6
22
6
22
6
22
6
22
6
22
6
22
6
18 19 22
6
22
6
22
6
22
6
18 22
6
22
6
22
6
18 21
6
22
6
19 26
6
6
6
22
6
22
6
22
6
22
22
121
BI
IN
IN IN
IN IN
IN IN
NC
IN
BI
OUT
IN IN
IN
IN
IN
IN
IN IN
IN
IN
IN IN
IN
IN OUT OUT OUT
OUT
IN
IN
IN IN IN IN
OUT
OUT
OUT
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN
IN
OUT OUT
IN IN
IN IN
NC
BI IN
OUT
IN IN
IN IN
OUT
IN
NC NC
NC NC
NC NC
NC
NC
NC
NC
NC
OUT
OUT
OUT OUT
OUT
OUT
IN OUT OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
- Unused GPIOs 0 & 15 not isolated.
be replaced with aliases. Otherwise these R’s must
and path to non-XDP signal destination.
Pull-up to 3.3V on csa 26 (PCH Support)
1K series resistor on csa 26 (PCH Support)
Connects to PCH XDP Conn
- For isolated GPIOs:
- MXM_GOOD not isolated as only LED is affected.
needs to split between route from PCH to J2550
- ’Output’ PCH/XDP signals require pulls.
PCH Signals
oc7#/gpio14
xdp_present#
obsdata_c1
sata2gp/gpio36 sata3gp/gpio37
gpio15
PCH Micro2-XDP
1K series resistor on csa 26 (PCH Support)
obsdata_b0
obsdata_c2 obsdata_c3
obsen_d1
obsen_c0
obsdata_c2
obsen_d0
obsdata_c1
obsdata_a2
trstn
itpclk/hook4
obsen_a1
obsdata_d3
itpclk#/hook5
reset#/hook6
obsdata_c3
obsen_d1
tms
tdi
tdo
dbr#/hook7
vcc_obs_cd
obsen_c0
obsen_d0
obsdata_c0
obsen_c1
itpclk/hook4
tdo
tdi tms
obsdata_a2 obsdata_a3
obsen_b0
vcc_obs_ab
pwrgd/hook0
scl
sda
hook3
hook1
obsdata_b2
obsen_b1
hook2
obsdata_b0
tck0
tck1
scl
sda
vcc_obs_ab hook2 hook3
hook1
pwrgd/hook0
obsdata_b3
obsdata_b2
obsdata_b1
obsdata_a1
obsdata_a0
obsdata_a0
obsen_a1
obsen_a0
obsdata_b1
obsdata_b3
CPU Micro2-XDP
obsdata_a1
PCH/XDP Signal Isolation Notes:
events while using PCH XDP.
obsdata_d0 obsdata_d1
obsdata_d2
obsdata_c0
obsen_c1
obsen_a0
XDP Signals
- ’Output’ non-XDP signals require pulls.
If PCH XDP not implemented, all of R2524-R2537 can
connect to appropriate non-XDP signals on PCB.
obsen_b1
obsen_b0
oc3#/gpio42
oc2#/gpio41
oc0#/gpio59
oc6#/gpio10
oc5#/gpio9
sata1gp/gpio19
sata0gp/gpio21
gpio0
gpio35
sata5gp/gpio49
sata4gp/gpio16
mgpio7/gpio28
xdp_present#
trstn
dbr#/hook7
itpclk#/hook5
obsdata_d2
obsdata_d1
obsdata_d0
oc4#/gpio43
oc1#/gpio40
obsdata_a3
obsdata_d3
vcc_obs_cd reset#/hook6
be stuffed even in production so that PCH pins
R2524-R2537 should be placed where signal path
- USB OC#’s not isolated, avoid USB port overcurrent
tck0
tck1
998-2516
998-2516
11
103
11
103
11
103
11
103
11
103
11
103
10
103
10
103
25 50
25 50
11 25
103
10
103
10
103
10
103
10 25
103
10 15
103
10 15
103
10
103
10
103
10 15
103
10
103
10 15
103
10
103
26
103
11 25
103
11 25
103
11 25
103
11 25
103
402
MF-LF
5%
1/16W
XDP
R2506
0
SW2600.2:350MM
19 26 47
120
1/16W
XDP
5%
R2505
0
MF-LF
402
R1553.1:5MM
MF-LF
R2504
5%
402
1/16W
XDP
0
R1554.1:5MM
15 18
103
15 18
103
11
103
11
103
11
103
11
103
1K
MF-LF
402
5%
1/16W
R2500
XDP
U1000.J40:25MM
5%
XDP
1/16W
402
R2501
0
U4900.D10:350MM
MF-LF
R2502
XDP
402
1/16W
5%
1K
U1000.H36:25MM
MF-LF
J2500.47:10MM
R2503
0
MF-LF
402
1/16W
XDP
5%
5
65 66
120
10 25
103
15 19 25 47
120
11 21 28
103
R2510
XDP
5% MF-LF
51
1/16W 402
J2500.52:10MM
R2511
XDP
51
5% 1/16W
402
U1000.L40:10MM
MF-LF
R2512
XDP
51
5% 1/16W MF-LF 402
U1000.L38:10MM
R2513
XDP
51
5% 1/16W MF-LF 402
U1000.J39:10MM
R2514
XDP
51
5% 1/16W MF-LF 402
U1000.M40:10MM
25
103
25
103
25
103
25
103
25
103
25
103
25
103
25
103
25
103
25
103
26
103
18 25
103
18 25
103
18 25
103
25
103
25
103
25
103
25
103
25 50
25 50
18 25
103
25
103
25
103
25
103
25
103
15 19 25 47
120
R2550
1K
5%
1/16W
MF-LF
402
XDP
J2550.30:10MM
6
25
R2562
XDP
MF-LF
1/16W
200
U1800.BC50:10MM
5%
402
R2561
XDP
U1800.BC52:10MM
200
402
1/16W
5% MF-LF
R2566
XDP
U1800.BA43:10MM
MF-LF
1/16W 402
5%
51
402
R2560
1/16W
200
5% MF-LF
XDP
J2500.52:121MM
20
103
20
103
20
103
20
103
20
103
20
103
20
103
20
103
21
103
21
103
21
103
18
103
18
103
21
103
21
103
21
103
21
103
J2500
DF40RC-60DP-0.4V
XDP_CONN
M-ST-SM
CRITICAL
J2550
M-ST-SM
XDP_CONN
DF40RC-60DP-0.4V
CRITICAL
1/16W MF-LF
5%
0
402
R2567
NOSTUFF
R2565
XDP
U1800.BA43:10MM
100
5%
402
MF-LF
1/16W
R2564
XDP
U1800.BA43:10MM
100
MF-LF 402
5% 1/16W
5%
402
MF-LF
1/16W
100
XDP
R2563
J2500.52:121MM
33
1/16W
MF-LF
402
5%
R2520 R2521
1/16W
33
MF-LF
402
5%
R2522
1/16W
402
33
MF-LF
5%
R2523
33
5%
1/16W
402
MF-LF
33
MF-LF
4025%1/16W
R2524 R2525
33
MF-LF
402
1/16W
5%
R2526
33
MF-LF
1/16W
5%
402
R2527
402
33
MF-LF
1/16W
5%
R2537
5%
33
MF-LF
1/16W
402
5%
R2528
MF-LF
402331/16W
R2529
5%
1/16W
MF-LF
402
33
R2530
1/16W
5%
402
MF-LF
33
R2533
402
MF-LF335%
1/16W
R2534
1/16W
5%
33
MF-LF
402
R2535
1/16W
33
5%
MF-LF
402
R2536
402
33
5%
1/16W
MF-LF
21
103
R2531
5%
1/16W
402
33
MF-LF
R2532
33
5%
1/16W
MF-LF
402
11 25
103
11 25
103
5%
402
MF-LF
1/16W
0
R2551
XDP
U4900.D10:117MM
16V
10%
0.1UF
C2500
X7R-CERM
XDP
0402
XDP
C2501
0.1UF
0402
10% 16V X7R-CERM
XDP
0.1UF
0402
10% 16V X7R-CERM
C2551
16V
10% X7R-CERM
XDP
0402
0.1UF
C2550
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
CPU and PCH XDP
=PP3V3_S5_XDP
=PPVCCIO_S0_XDP
=SMBUS_XDP_SCL
XDP_CPU_PWRGD XDP_CPU_PWRBTN_L
XDP_CPU_TMS
=PP3V3_S5_XDP
XDP_CPU_TDI
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM MAX_NECK_LENGTH=3MM
PP3V3_S5_XDP_R
VOLTAGE=3.3V
ISOLATE_CPU_MEM_R_L
XDP_PIN03
XDP_DA3_USB_EXTD_OC_L
USB_EXTD_OC_R_L USB_EXTB_OC_EHCI_R_L USB_EXTD_OC_EHCI_R_L
USB_EXTA_OC_R_L USB_EXTB_OC_R_L USB_EXTC_OC_R_L
PM_PWRBTN_L
=PP3V3_S5_XDP
XDP_PCH_PWRGD
CPU_CFG<2>
CPU_CFG<7>
XDP_FC0_PCH_GPIO15 XDP_FC1_TBT_CIO_PLUG_EVENT
XDP_DD3_ENET_LOW_PWR_PCH
XDP_DB2_AP_PWR_EN
CPU_CFG<3>
CPU_CFG<8> CPU_CFG<9>
XDP_CPU_TDO
XDP_DBRESET_L
XDP_PCH_TCK
XDP_DA1_USB_EXTB_OC_L
XDP_FC0_PCH_GPIO15
GPU_GOOD_R
DP_TBT_SEL_R
XDP_DB3_SDCONN_STATE_CHANGE
XDP_DB1_USB_EXTD_OC_EHCI_L
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DA0_USB_EXTA_OC_L
XDP_DA2_USB_EXTC_OC_L
XDP_DA1_USB_EXTB_OC_L
SDCONN_STATE_CHANGE_R
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_CPU_PLTRST_L
XDP_DA0_USB_EXTA_OC_L
XDP_DD3_ENET_LOW_PWR_PCH
XDP_DC1_GPU_GOOD
XDP_PCH_PLTRST_L
XDP_PCH_TMS
XDP_DB1_USB_EXTD_OC_EHCI_L
=SMBUS_XDP_SDA
XDP_PCH_TCK
XDP_DB2_AP_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE
CPU_CFG<1>
CPU_CFG<17>
CPU_CFG<0>
XDP_BPM_L<0> XDP_BPM_L<1>
XDP_BPM_L<2>
CPU_CFG<4>
XDP_CPU_PRDY_L
CPU_CFG<10> CPU_CFG<11>
=SMBUS_XDP_SDA
XDP_CPU_TCK
XDP_BPM_L<3>
XDP_CPU_PREQ_L
=PPVCCIO_S0_XDP
ITPXDP_CLK100M_P
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI XDP_CPU_TMS XDP_CPU_TCK
XDP_CPU_CFG<0>
PM_SYSRST_L
CPU_CFG<16>
XDP_DD2_AUD_IPHS_SWITCH_EN_PCH
XDP_DD1_JTAG_TBT_TCK
XDP_DD0_DP_TBT_SEL
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DD1_JTAG_TBT_TCK
TBT_CIO_PLUG_EVENT_R
XDP_FC1_TBT_CIO_PLUG_EVENT
XDP_PCH_TDI
XDP_DC3_SATARDRVR_EN
XDP_DC2_DP_AUXCH_ISOL
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_PCH_TDI
XDP_PCH_TDO
XDP_DC2_DP_AUXCH_ISOL
XDP_DC1_GPU_GOOD
XDP_DA3_USB_EXTD_OC_L
AUD_IPHS_SWITCH_EN_PCH_R ENET_LOW_PWR_PCH_R
PM_PGOOD_REG_CPUCORE_S0
XDP_BPM_L<7>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_PCH_TDO
=SMBUS_XDP_SCL
XDP_PCH_PWRBTN_L
AP_PWR_EN_R
XDP_DD0_DP_TBT_SEL
XDP_DA2_USB_EXTC_OC_L
XDP_BPM_L<6>
CPU_CFG<0>
XDP_PCH_TMS
XDP_DD2_AUD_IPHS_SWITCH_EN_PCH
XDP_DC3_SATARDRVR_EN
ITPXDP_CLK100M_N
CPU_CFG<6>
CPU_CFG<5>
SATARDRVR_EN_R
CPU_PWRGD
JTAG_TBT_TCK_R
XDP_VR_READY
XDP_CPU_TRST_L
XDP_DBRESET_L
XDP_CPU_CLK100M_N
XDP_CPU_CLK100M_P
DP_AUXCH_ISOL_R
PM_PWRBTN_L
prefsb
051-9505
8.0.0
25 OF 144 25 OF 123
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1
2
1
2
53
51
43
41
35
29
23
19
17
15
11
7
5
9
3
2
13
10 12 14 16
8
1
21
27
33
37 39
45 47 49
57
55
59
6
20 22 24 26
32
30
38
42 44
48
46
50 52 54
58
56
60
28
40
18
4
34 36
25
31
61
62
6364
53
51
43
41
35
29
23
19
17
15
11
7
5
9
3
2
13
10 12 14 16
8
1
21
27
33
37 39
45 47 49
57
55
59
6
20 22 24 26
32
30
38
42 44
48
46
50 52 54
58
56
60
28
40
18
4
34 36
25
31
61
62
6364
1 2
1
2
1
2
1
2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2
1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2
1 2
2
1
2
1
2
1
2
1
6
25
6
25
103
103
6
25
121
103
25
103
25
103
18 25
103
25
103
25
103
25
103
25
103
25
103
25
103
6
25
11 25
103
11 25
103
11 25
103
11 25
103
11 25
103
103
25
103
25
103
25
103
18 25
103
18 25
103
25
103
25
103
25
103
103
25
103
25
103
18 25
103
25
103
25
103
103
103
103
OUT
NCNC
OUT
OUT
IN
OUT
IN
IN
NCNC
OUT
OUT
IN
OUT
IN
OUT
OUT
NC
OUT
OUT
OUT
OUT
NC
NC
OUT
GND
VDD
25MHZ_A
VDDIO_B
VDDIO_A
VDDIO_C
25MHZ_B 25MHZ_C
THRM
XIN
XOUT
PAD
NC
OUT
OUT
OUT
OUT
OUT
Y
A
B
08
OUT
Y
A
B
08
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
PCH RTC Crystal
Reset Button
OPEN-DRAIN BUFFER
System 25MHz Clock Generator
PCH 25MHZ CLOCK
From GreenClk @ 1.8V
To PCH @ 1.1V
Ethernet XTAL Power SB XTAL Power TBT XTAL Power
Unbuffered
Platform Reset Connections
Buffered
ENET > S0 > TBT, so ENET is used here.
VDD must be powered if any VDDIO is.
GreenClk 25MHz Power
VTT VOLTAGE DIVIDER AND PU ON CPU PAGE
Clock series termination
511-0054
RDAR://11218892 TESTPOINT TO RESET RTC FOR APPLE CARE
GPIO Isolation to prevent glitches on critical core well GPIOs
Coin-Cell Holder
RTC Power Sources
NOTE: 30 PPM crystal required
19 25 47
120
R2602
1/16W
5%
MF-LF
2
402
1K
1
D2600
SOT-363
BAT54DW-X-G
R2681
1/16W
5%
402
MF-LF
33
33
402
5%
1/16W
R2690
MF-LF
49
117
83 91
118
18
105
18
105
20
120
R2626
402
1/16W
5%
33
MF-LF
PLACE_NEAR=U1800.AN14:10mm
R2625
1/16W
5%
33
402
MF-LF
PLACE_NEAR=U1800.AT11:10mm
20
105
49
105
47
105
20
105
18
105
MF-LF
5%
1/16W
402
33
PLACE_NEAR=U1800.AT14:10mm
R2627
20
105
402
CERM
10V
0.1UF
C2680
20%
R2680
402
1/16W
100K
5%
MF-LF
BB10201-C1403-7H
SM
J2600
R2611
5%
1/16W
10M
402
MF-LF
U2680
SOT23-5-HF
MC74VHC1G08
C2690
402
CERM
10V
20%
0.1UF
5%
1/16W
R2610
0
MF-LF
402
25
103
1/16W
5%
R2699
MF-LF
XDP
1K
402
35
117
R2688
33
MF-LF
402
5%
1/16W
R2655
33
MF-LF
402
5%
1/16W
74LVC1G07
U2690
SC70
402
1K
5%
MF-LF
1/16W
R2698
XDP
25
103
41
118
R2692
33
1/16W
5%
MF-LF
402
18
105
36
105
C2620
0.1UF
402
20%
10V
CERM
C2622
10V
0.1UF
20%
CERM
402
CERM
10V
20%
402
0.1UF
C2624
402
R2605
1/16W MF-LF
5%
0
1/16W
R2606
1M
402
MF-LF
5%
NO STUFF
39
105
R2628
33
5%
402
1/16W MF-LF
PLACE_NEAR=U2600.4:10MM
C2602
402
1UF
10%
6.3V
CERM
SLG3NB146V
TDFN
CRITICAL
U2600
Y2610
SM-HF
32.768K-12.5PF
CRITICAL
NOSTUFF
R2696
1/16W 402
MF-LF
5%
0
SILK_PART=SYS RESET
47
122
402
MF-LF
1/16W
5%
33
VREFMRGN:EXT
R2694
28 34
119
11
103
38
15 36
122
10V
402
CERM
0.1UF
20%
C2650
PLACE_NEAR=U2650.8:2MM
SOT833
CRITICAL
4
8
U2650
74LVC2G08GT
60
402
0.1UF
CERM
10V
20%
C2660
PLACE_NEAR=U2660.5:2MM
U2650
CRITICAL
4
8
74LVC2G08GT
SOT833
MC74VHC1G08
SOT23-5-HF
U2660
39 41
118
R2697
4.7K
1/16W
5%
402
MF-LF
R2672
1%
140
MF-LF 402
1/16W
R2671
40.2
1/16W MF-LF
402
1%
DEVELOPMENT
SILK_PART=SYS RESET
SM
NTC020AA1JB260T
SW2600
33
402
5%
MF-LF
1/16W
R2691
C0G-CERM
0402
50V
5%
12PF
C2605
C2606
12PF
5%
50V
C0G-CERM
0402
PLACE_NEAR=Y2610.3:7MM
C2610
0402
C0G-CERM
50V
5%
12PF
12PF
PLACE_NEAR=Y2610.1:2MM
0402
C0G-CERM
50V
5%
C2611
SMT-PAD
OMIT
1.97X2.02MM-NSP
TP2601
OMIT
SM-PAD
1.4-SQ-NSP
TP2603
1.97X2.02MM-NSP
TP2600
OMIT
SMT-PAD
SM-PAD
OMIT
1.4-SQ-NSP
TP2602
Y2605
25.000MHZ-20PPM-12PF-85C
3.2X2.5MM-SM
CRITICAL
SYNC_MASTER=D8_MLB
CHIPSET SUPPORT
SYNC_DATE=08/27/2012
=PP3V3_S5_PCH
AUD_IPHS_SWITCH_EN
LPC_CLK33M_LPCPLUS
LPC_CLK33M_LPCPLUS_R
SYSCLK_CLK25M_X2
PCH_CLK32K_RTCX1
PM_PCH_PWROK
SYSCLK_CLK25M_X1
=PP3V3_G3H_RTC_D
PPVBATT_G3_RTC_R
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
PP3V3_G3_RTC
RTC_RESET_L
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm
PPVBATT_G3_RTC
VOLTAGE=3.3V
PCH_CLK33M_PCIOUT
ENET_LOW_PWR
MAKE_BASE=TRUE
PLT_RESET_L
MAKE_BASE=TRUE
TBT_PLT_RST_L
SMC_LRESET_L
MAKE_BASE=TRUE
=PP3V3_S0_RSTBUF
PLT_RST_BUF_L
=TBT_RESET_L
AP_RESET_L
ENET_SD_RESET_L
=PP3V3_S5_PCH
LPC_PWRDWN_L
LPC_CLK33M_SMC_R
=PP1V8_S0_PCH_CLK =PP3V3_TBT_CLK
SYSCLK_CLK25M_X2_R
GPU_RESET_L
DEBUG_RESET_L
LPC_CLK33M_SMC
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_TBT
AUD_IPHS_SWITCH_EN_PCH
PM_PCH_PWROK
ENET_LOW_PWR_PCH
PCH_CLK25M_XTALIN
TBT_PWR_EN
=PP3V3_S5_PCH
TBT_PWR_EN_PCH
SYSCLK_CLK25M_SB
XDP_PCH_PLTRST_L
=PP3V3_S4_ENET_SYSCLK
SYSCLK_CLK25M_SB
PCH_CLK33M_PCIIN
=PP3V3_S0_RSTBUF
=PP3V3_S0_PCH_PM
=PP3V3_S4_ENET_CLK
SYSCLK_CLK25M_ENET_R
CPU_RESET_L
PM_SYSRST_L
PCH_CLK32K_RTCX2
PCH_CLK32K_RTCX2_R
XDP_CPU_PLTRST_L
PCA9557D_RESET_L
prefsb
051-9505
8.0.0
26 OF 144 26 OF 123
3
6
2
4
1
5
1 2
1 2
1 2
1 2
1 2
2
1
1
2
1
2
1
2
5
1
2
3
4
2
1
1 2
1 2
1 2
1 2
4
1 3
2
5
1 2
1 2
2
1
2
1
2
1
1 2
1
2
1 2
2
1
9
2
5
367
4 8
11
1
10
41
1
2
1 2
2
1
7
2
1
2
1
3
6
5
5
1
2
3
4
1
2
1
2
1 2
132
4
1 2
1 2
1 2
1 2
1 2
1
1
1
1
42
1 3
6
19 24 26
105
15 19 26 35 43 65 80
120
105
6
121
6
121
18 48
121
121
6
26
120
6
19 24 26
19 47 49
119
6
6
105
26
105
21
103
15 19 26 35 43 65 80
120
15 21
103
6
19 24 26
18
122
26
105
6
26
105
6
26
6
6
26
105
105
BI BI
BI
BI
NC NC
NC NC
TEST1
USBDM_DN1
USBDP_DN1
VBUS_DET
USBDP_DN2 USBDM_DN2
SUSP_IND/NON_REM0
VDD33
NC
XTALOUT
XTALIN/CLKIN
TEST
RESET*
HS_IND
NON_REM1
PLLFILT
CRFILT
VDD33
VDD33
VDD33
USBDM_UP
USBDP_UP
PRTPWR1 PRTPWR2
OCS1* OCS2*
RBIAS
VDD33
EPAD
IN
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
NON_REM 0 and 1 are used to indicate whether the downstream ports are removable or captive
NON_REM[1:0] = 1x ---> ports 1 and 2 are non-removable
via array to GND
NON_REM[1:0] = 01 ---> port 1 is non-removable
ePad needs a minimum of 3x3
NON_REM[1:0] = 00 ---> ports 1 and 2 are removable
155S0220
338S1076
50mV P-P spec @ 100k-1MHz
MF
R2707
12K
1/16W 402
1%
PLACE_NEAR=U2700.26:2MM
20
106
20
106
35
106
35
106
MF-LF 402
5% 1/16W
R2705
1/16W
5% MF-LF
402
R2708
R2703
402
1/16W MF-LF
10K
5%
X5R-CERM
10%
4.7UF
603
6.3V
C2705
402
16V X5R
C2708
10%
1UF
R2706
1/16W
1M
5% MF-LF
402
MF
1/20W
5%
201
R2711
MF-LF
5%
R2704
402
1/16W
U2700
CRITICAL
QFN
USB2412-DZK
1/16W
R2709
402
5%
0
MF-LF
35 64 74
120
201
MF
R2710
1/20W
5%
FERR-120-OHM-1.5A
L2700
0402
5%
C0G-CERM
0402
C2701
50V
C2702
5%
C0G-CERM
50V
0402
1/16W
R2712
402
1K
5%
MF-LF
CERM
16V
C2712
402
0.01UF
10%
24.000M-50PPM-16PF
5X3.2X1.5-SM
Y2700
CRITICAL
C2709
0402
0.1UF
10% 16V X7R-CERM
C2710
0402
0.1UF
10% 16V X7R-CERM
C2711
0402
0.1UF
10% 16V X7R-CERM
X7R-CERM
16V 0402
0.1UF
10%
C2703 C2704
X7R-CERM
16V 0402
0.1UF
10%
0402
0.1UF
10% 16V X7R-CERM
C2707 C2706
X7R-CERM
16V
10%
0.1UF
0402
USB 2.0 HUB (BT/SMC)
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
MIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V
PP3V3_S4_USB_HUB_VDD
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.25MM
PP1V2_USB_HUB_PLLFILT
VOLTAGE=1.2V
MAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3MM
VOLTAGE=1.2V
PP1V2_USB_HUB_CRFILT
MIN_LINE_WIDTH=0.4MM
USB_HUB_XTAL2_R
USB_HUB_XTAL1
PM_PGOOD_P3V3_S4_FET
USB_HUB_RESET_L
USB_HUB_NON_REM1
USB_HUB_XTAL2
USB_HUB_NON_REM0
USB_PCH_7_P
USB_HUB_RBIAS
USB_HUB_2N
USB_BT_P
=PP3V3_S4_USB_HUB
=PP3V3_S4_USB_HUB
USB_PCH_7_N
USB_BT_N
=PP3V3_S4_USB_HUB
=PP3V3_S4_USB_HUB
USB_HUB_HS_IND
USB_HUB_VBUS_DET
USB_HUB_2P
prefsb
051-9505
8.0.0
27 OF 144 27 OF 123
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2
1
2
1
2
1
2
2
1
2
1
1
2
1
2
1
2
15
28
1
18
3 2
19
14
5
23
24
6
17
16
13
25
92027
10
21
22
7
11
8
12
26
4
29
1 2
1
2
21
1 2
1 2
1 2
2
1
2 1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
121
120
120
106
106
106
106
106
106
106
106
6
27
6
27
6
27
6
27
106
106
106
OUT
IN
G
D
S
OUT
D
SG
D
SG
D
SG
D
SG
NC
NC
IN
D
S
G
G
D
S
G
D
S
OUT
IN
IN
A Y
NC NC
VCC
GND
NCNC
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEMVTT_EN = CPU_PWRGD * PM_SLP_S3_L (VTT is enabled when PCH tells CPU to enable VCCORE)
MEMVTT Clamp actively holds MEMVTT rail low until MEMVTT is enabled.
Clamping MEMVTT will keep the MEM_CKE low until CPU actively controls it.
CPU does not drive MEM_CKE until VCCORE activated but CPU 1V5 (VDDQ) leaks into it.
MEMVTT_EN Generator
Enables MEMVTT when PCH drives CPU PWRGD.
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L (Block CPU from driving MEM_RESET_L in S3)
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
The circuits below handle MEMVTT power during S0->S3->S0 transitions, as well
WHEN LOW: MEM_RESET_L IS ISOLATED.
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1 1
0 (*)
X
X
CPU_MEM_RESET_L
MEMVTT_EN
1
1
0
1
1
1
1 1
0
1
0
1
1
1
1 1
1
1
1
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PM_SLP_S3_L
ISOLATE_CPU_MEM_L
Rails will power-up as if from S3, but MEM_RESET_L now needs to be asserted in S0. Software
S0
to
S0
to
NOTE: On a S5->S0 transition, ISOLATE_CPU_MEM_L will default low.
must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
Ensures CKE signals are held low in S3 and in S0 before CPU PWRGD
75mA max load @ 0.75V 60mW max power
MEMVTT Clamp
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
With optional delay from 1V5 S0 PGOOD
1V5 S0 "PGOOD" for CPU
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behaviour of signals. WHEN HIGH: MEM_RESET_L NOT ISOLATED.
MEM_RESET_L Generator
rdar://11117167
S3
PLT_RESET_L equivalent
Open-drain buffer
CPU_PWRGD
CPU_MEM_RESET_L
CPU_MEM_RESET_L
1
MEM_RESET_L
0
Vih = 0.65 * Vcc = 0.65 * 1.05 = 0.68V
R2802
10K
402
1/16W
5%
MF-LF
28 64
119
28 64
119
R2851
1/16W
5%
402
MF-LF
R2850
5%
603
10
1/10W MF-LF
10K
5%
R2820
1/16W
402
MF-LF
DMB53D0UV
SOT-563
Q2820
CRITICAL
R2822
1/16W 402
5% MF-LF
10K
CRITICAL
Q2820
DMB53D0UV
SOT-563
11 19
103
R2810
1/16W
10K
5%
402
MF-LF
SSM6N15AFE
SOT563
CRITICAL
Q2810
SOT563
SSM6N15AFE
Q2850
CRITICAL
SOT563
SSM6N15AFE
CRITICAL
Q2850
CRITICAL
SSM6N15AFE
SOT563
Q2810
U2820
SC70
74LVC1G07
64 74
120
20K
1/16W
5%
MF-LF 402
R2985
0.0022UF
CERM
10%
402
C2899
50V
SOT23-HF1
2N7002
Q2899
R2897
20K
MF-LF
402
1/16W
5%
SOT-363
2N7002DW-X-G
Q2898
MF-LF 402
1/16W
5%
20K
R2898
20K
MF-LF
402
5%
1/16W
R2899
2N7002DW-X-G
SOT-363
Q2898
29 30 31 32
101
21 34
103
11
103
0.01UF
20%
0402
16V X7R-CERM
C2821
CERM
50V
C2820
NOSTUFF
0402
20%
0.001UF
NOSTUFF
0402
20%
0.001UF
C2851
CERM
50V
CRITICAL
SOT891
U2830
74AUP1G07GF
20% 16V X7R-CERM 0402
0.01UF
C2830
R2831
0
1/16W MF-LF
5%
402
R2832
NOSTUFF
5%
MF-LF
1/16W
0
402
5%
10K
402
MF-LF
1/16W
R2830
5
15 19 40 47 48 64
120
26 34
119
11 21 25
103
R2833
402
5%
0
1/16W MF-LF
0402
X7R-CERM
NOSTUFF
C2831
16V
0.01UF
20%
SYNC_MASTER=D8_MLB
CPU Memory S3 Support
SYNC_DATE=08/27/2012
PM_PGOOD_REG_ALL_P1V05_S0_R =PPVCCIO_S0_CPU
CPU_PWRGD
MEMVTT_EN
PCA9557D_RESET_L
CPU_PWRGD_3V3_R
PM_SLP_S3_L
=PPDDRVTT_S0_CLAMP
ISOLATE_CPU_MEM_5V
ISOLATE_CPU_MEM_L
CPU_MEM_RESET_L
MEM_RESET_L
=PP5V_S4_MEMRESET
=PPVDDQ_S3_MEMRESET
=PP3V3_S4_MEMRESET
=PP3V3_S4_PM
PM_MEM_PWRGD_L
PM_MEM_PWRGD
PM_PGOOD_FET_VDDQ_S0
MEMVTT_EN
PGOOD_P1V5_S0_DLY
=PP3V3_S0_PWRCTL
VTTCLAMP_EN
=PP3V3_S0_PWRCTL
=PP3V3_S4_MEMRESET
VTTCLAMP_L
MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.25mm
CPU_PWRGD_1V05_R
ISOLATE_CPU_MEM_5V_L
CPU_PWRGD_3V3
MEMVTT_EN_L
prefsb
051-9505
8.0.0
28 OF 144 28 OF 123
1
2
1
2
1
2
1
2
4
5
3
1
2
6
2
1
1
2
3
4
5
6
1
2
3
4
5
6
1
2
4
1 3
2
5
1
2
2
1
1
32
1
2
3
5
4
1
2
1
2
6
2
1
2
1
2
1
2
1
2
4
1
5
63
2
1
12
12
1
2
12
2
1
64
120
6
10 11 13 16 66
117
6
119
6 6 6
28
6
120
120
6
28 74
123
6
28 74
6
28
123
119
117
119
BI BIBI
BI
IN
BI BI
BI BI
BI BI
BI
IN
BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI
BI
BI
BI
BI BI
BI
BI
IN IN
IN
IN
IN
IN
IN IN
IN IN
IN
IN
IN
IN
BI BI
BI BI
BI
IN
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
OUT
BI IN
IN
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
NC
NC
NC
BI
DQ0
VREFDQ VSS_1
VSS_3 DM0
VSS_12 DQ16
VSS_14
DQ18
VSS_21
VSS_24
DQ27
EVENT*
DQS7*
DQS6*
DQS5*
DQS4*
S1*
CAS*
S0*WE*
RAS*
CK1*CK0*
DQS3*
DQS2*
RESET*
DQS1*
DQS0*
DQ31
VDD_0 NC_0 BA2 VDD_2 A12/BC* A9
A8
VSS_50
VTT_0
VDDSPD SA1
SA0
DQ59
VSS_48 DQ58
DM7
VSS_47
DQ57
DQ56
VSS_45
DQ50 DQ51
DQ49 VSS_40
DQS6 VSS_43
DQ48
VSS_36 DQ42 DQ43 VSS_38
DM5
DQ40
VSS_35
VSS_33
DQ41
DQ35
VSS_28
DQS4 VSS_31 DQ34
DQ32
TEST
VDD_16
VSS_26
DQ33
VDD_10
VDD_6
A1 VDD_8 CK0
VDD_4
A5
CKE0
VSS_22
DM3
DQ26
VSS_19
DQ19
DQ25
DQ24
VSS_17
DQS2
DQ17
DQ10 DQ11
VSS_10
DQS1
VSS_8
DQ9
DQ8
VSS_6
DQ3
DQ2
SCL
SDA
VSS_49
DQ62 DQ63
VSS_51
DQS7
VTT_1
DM6
DQ53
VSS_41
VSS_42
DQ60 DQ61
VSS_46
DQ52
DQ45
VSS_34
VSS_39
DQS5
VSS_37
DQ46
DQ44
DQ47
VSS_32
DM4
VDD_17 VREFCA VSS_27
DQ36 DQ37
VSS_29
VSS_30
DQ38 DQ39
BA1
VDD_11
VDD_13
ODT0
VDD_15
ODT1 NC_1
CK1
A0
A2
A6 A4
A11
A7
VDD_7
VDD_5
VDD_9
VDD_3
A14
A15
CKE1
VDD_1
VSS_25
DQ30
DQS3
VSS_23
DM2
DQ29
VSS_20
DQ28
DQ23
VSS_18
VSS_16
DQ22
VSS_15
DQ21
DM1
DQ13
VSS_9
VSS_11
DQ14 DQ15
VSS_13
DQ20
DQ12
VSS_7
VSS_4
DQ1
DQ7
DQ6
DQ4 DQ5
DQS0
VSS_5
VSS_2
VSS_0
VSS_44
DQ55
DQ54
A3
A10_AP BA0 VDD_12
VDD_14 A13
KEY
SYM 1 OF 2
SYM 2 OF 2
MTG HOLE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
P/N: 516S1030
Power aliases required by this page:
- =PPDDRVTT_S0_MEM_A
- =I2C_SODIMMA_SDA
BOM options provided by this page:
- =PPVDDQ_S3_MEM_A
- =PP1V5_S0_MEM_A
(NONE)
Page Notes
- =I2C_SODIMMA_SCL
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
30 33
30 33
402
0.1UF
20%
C2931
CERM
10V
6.3V
C2930
2.2UF
402-LF
20% CERM
30 33
30 33
12
101
30 33
30 33
30 33
30 33
30 33
30 33
30 33
28 30 31 32
101
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12
101
12
101
12 30
101
12 30
101
12
101
12
101
30 33
30 33
30 33
30 33
30 33
12
101
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
C2936
0.1UF
CERM 402
20% 10V
2.2UF
CERM 402-LF
20%
C2935
6.3V
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 31 32 47 48
119
30 50
30 50
12
101
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12
101
12
101
12 30
101
12 30
101
12 30
101
12 30
101
12 30
101
12
101
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
30 33
1/16W 402
MF-LF
R2941
5%
10K
MF-LF 402
5% 1/16W
R2940
10K
2.2UF
C2940
402-LF
CERM
6.3V
20%
X5R 603
20%
6.3V
C2900
20%
X5R 603
6.3V
C2901
402
10V
20% CERM
0.1UF
C2910
CERM
10V
20% 402
0.1UF
C2911
0.1UF
CERM 402
20% 10V
C2912
10V
20% 402
CERM
0.1UF
C2913
0.1UF
402
CERM
C2914
20% 10V
0.1UF
CERM 402
20% 10V
C2915
0.1UF
CERM 402
10V
C2916
20%
10V
20% 402
0.1UF
C2917
CERM
0.1UF
CERM 402
20% 10V
C2918
0.1UF
CERM 402
20% 10V
C2919 C2920
0.1UF
CERM 402
20% 10V
0.1UF
CERM
10V
20% 402
C2921
0.1UF
CERM 402
20% 10V
C2922
10V
0.1UF
CERM 402
20%
C2923
C2953
10V
10%
402
X5R
1UF1UF
X5R 402
10% 10V
C2952
10V
10%
402
X5R
1UF
C2951
1UF
X5R 402
10% 10V
C2950
30 33
SODIMM-P0.60-D8
J2900
F-ANG-SM-2
SODIMM-P0.60-D8
J2900
F-ANG-SM-2
SYNC_DATE=08/27/2012
DDR3 SO-DIMM Connector A Slot0
SYNC_MASTER=D8_MLB
=MEM_A_DQ<4>
MEM_A_CKE<0>
=PPVDDQ_S3_MEM_A
MEM_A_WE_L
=MEM_A_DQ<0>
=PPDDRVREF_DQ_MEM_A
=MEM_A_DQ<16>
=MEM_A_DQ<18>
=MEM_A_DQ<27>
MEM_EVENT_L
=MEM_A_DQS_N<7>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<4>
MEM_A_CS_L<1>
MEM_A_CAS_L
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_CLK_N<1>MEM_A_CLK_N<0>
=MEM_A_DQS_N<3>
=MEM_A_DQS_N<2>
=MEM_A_DQS_N<0>
=MEM_A_DQ<31>
MEM_A_BA<2>
MEM_A_A<12> MEM_A_A<9>
MEM_A_A<8>
=PPDDRVTT_S0_MEM_A
=PP3V3_S0_MEM_A_SPD MEM_DIMM0_SA<1>
MEM_DIMM0_SA<0>
=MEM_A_DQ<59>
=MEM_A_DQ<58>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
=MEM_A_DQ<50> =MEM_A_DQ<51>
=MEM_A_DQ<49>
=MEM_A_DQS_P<6>
=MEM_A_DQ<48>
=MEM_A_DQ<42> =MEM_A_DQ<43>
=MEM_A_DQ<40> =MEM_A_DQ<41>
=MEM_A_DQ<35>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<32> =MEM_A_DQ<33>
MEM_A_A<1>
MEM_A_CLK_P<0>
MEM_A_A<5>
=MEM_A_DQ<26>
=MEM_A_DQ<19>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQS_P<2>
=MEM_A_DQ<17>
=MEM_A_DQ<10> =MEM_A_DQ<11>
=MEM_A_DQS_P<1>
=MEM_A_DQ<8>
=I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA
=MEM_A_DQ<62> =MEM_A_DQ<63>
=MEM_A_DQS_P<7>
=PPDDRVTT_S0_MEM_A
=MEM_A_DQ<53>
=MEM_A_DQ<60> =MEM_A_DQ<61>
=MEM_A_DQ<52>
=MEM_A_DQ<45>
=MEM_A_DQS_P<5>
=MEM_A_DQ<46>
=MEM_A_DQ<44>
=MEM_A_DQ<47>
=PPVDDQ_S3_MEM_A
=PPDDRVREF_CA_MEM_A
=MEM_A_DQ<36> =MEM_A_DQ<37>
=MEM_A_DQ<38> =MEM_A_DQ<39>
MEM_A_BA<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_CLK_P<1>
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<6> MEM_A_A<4>
MEM_A_A<11> MEM_A_A<7>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_CKE<1>
=MEM_A_DQ<30>
=MEM_A_DQS_P<3>
=MEM_A_DQ<29>
=MEM_A_DQ<28>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<13>
=MEM_A_DQ<14>
=MEM_A_DQ<20>
=MEM_A_DQ<12>
=MEM_A_DQ<1>
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQ<5>
=MEM_A_DQS_P<0>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
MEM_A_A<3>
MEM_A_A<10> MEM_A_BA<0>
MEM_A_A<13>
MEM_DIMM0_SA<0> =PP3V3_S0_MEM_A_SPD
MEM_DIMM0_SA<1>
MEM_RESET_L
=MEM_A_DQ<15>
=MEM_A_DQS_N<1>
=MEM_A_DQ<9>
=MEM_A_DQ<2> =MEM_A_DQ<3>
prefsb
051-9505
8.0.0
29 OF 144 29 OF 123
2
1
2
1
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
5
1 3
9
11
37 39
43
51
61
71
69
198
186
169
152
135
121
115
114113
110
104103
62
45
30
27
10
70
75 77 79 81 83 85
89
195
203
199 201
197
193
189 191
187
185
183
181
179
175 177
165 167
171 173
163
155 157 159 161
153
147
151
145
149
143
133
137 139 141
129
125
123
127
131
105
93
97 99
101
87
91
73
65
63
67
55
53
59
57
49
47
41
33 35
31
29
25
23
21
19
17
15
202
200
190 192 194 196
188
204
170
166 168
172
180 182 184
164
148 150
162
154 156 158
146
160
144
136
124 126 128 130 132 134
138 140 142
108
106
112
116 118 120 122
102
98
96
90 92
84 86
94
88
100
82
80
78
74 76
72
68
64 66
46
58 60
56
52 54
48 50
44
42
28
24 26
32 34 36 38 40
22
20
13
7
18
16
4 6
12 14
8
2
178
176
174
95
107 109 111
117 119
205 206 207 208 209
6
29 30
6
30
6
29 30
6
29 30
29
29
6
29 30
6
29 30
6
30
29
6
29 30
29
BI BIBI
BI
IN
BI BI
BI BI
BI BI
BI
IN
BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI
BI
BI
BI
BI BI
BI
BI
IN IN
IN
IN
IN
IN
IN IN
IN IN
IN
IN
IN
IN
BI BI
BI BI
BI
IN
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
OUT
BI IN
IN
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
NC
NC
NC
BI
DQ0
VREFDQ VSS_1
VSS_3 DM0
VSS_12 DQ16
VSS_14
DQ18
VSS_21
VSS_24
DQ27
EVENT*
DQS7*
DQS6*
DQS5*
DQS4*
S1*
CAS*
S0*WE*
RAS*
CK1*CK0*
DQS3*
DQS2*
RESET*
DQS1*
DQS0*
DQ31
VDD_0 NC_0 BA2 VDD_2 A12/BC* A9
A8
VSS_50
VTT_0
VDDSPD SA1
SA0
DQ59
VSS_48 DQ58
DM7
VSS_47
DQ57
DQ56
VSS_45
DQ50 DQ51
DQ49 VSS_40
DQS6 VSS_43
DQ48
VSS_36 DQ42 DQ43 VSS_38
DM5
DQ40
VSS_35
VSS_33
DQ41
DQ35
VSS_28
DQS4 VSS_31 DQ34
DQ32
TEST
VDD_16
VSS_26
DQ33
VDD_10
VDD_6
A1 VDD_8 CK0
VDD_4
A5
CKE0
VSS_22
DM3
DQ26
VSS_19
DQ19
DQ25
DQ24
VSS_17
DQS2
DQ17
DQ10 DQ11
VSS_10
DQS1
VSS_8
DQ9
DQ8
VSS_6
DQ3
DQ2
SCL
SDA
VSS_49
DQ62 DQ63
VSS_51
DQS7
VTT_1
DM6
DQ53
VSS_41
VSS_42
DQ60 DQ61
VSS_46
DQ52
DQ45
VSS_34
VSS_39
DQS5
VSS_37
DQ46
DQ44
DQ47
VSS_32
DM4
VDD_17 VREFCA VSS_27
DQ36 DQ37
VSS_29
VSS_30
DQ38 DQ39
BA1
VDD_11
VDD_13
ODT0
VDD_15
ODT1 NC_1
CK1
A0
A2
A6 A4
A11
A7
VDD_7
VDD_5
VDD_9
VDD_3
A14
A15
CKE1
VDD_1
VSS_25
DQ30
DQS3
VSS_23
DM2
DQ29
VSS_20
DQ28
DQ23
VSS_18
VSS_16
DQ22
VSS_15
DQ21
DM1
DQ13
VSS_9
VSS_11
DQ14 DQ15
VSS_13
DQ20
DQ12
VSS_7
VSS_4
DQ1
DQ7
DQ6
DQ4 DQ5
DQS0
VSS_5
VSS_2
VSS_0
VSS_44
DQ55
DQ54
A3
A10_AP BA0 VDD_12
VDD_14 A13
KEY
SYM 1 OF 2
SYM 2 OF 2
MTG HOLE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
- =I2C_SODIMMA_SDA
- =PPDDRVTT_S0_MEM_A
Page Notes
- =PP1V5_S0_MEM_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
- =I2C_SODIMMA_SCL
BOM options provided by this page:
(NONE)
Signal aliases required by this page:
- =PPVDDQ_S3_MEM_A
Power aliases required by this page:
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
P/N: 516S1030
29 33
29 33
0.1UF
10V
20%
C3031
CERM 402
C3030
6.3V
20%
402-LF
2.2UF
CERM
29 33
29 33
12
101
29 33
29 33
29 33
29 33
29 33
29 33
29 33
28 29 31 32
101
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12
101
12
101
12 29
101
12 29
101
12
101
12
101
29 33
29 33
29 33
29 33
29 33
12
101
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
10V
20% 402
CERM
0.1UF
C3036
6.3V
20%
2.2UF
C3035
CERM 402-LF
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 31 32 47 48
119
29 50
29 50
12
101
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12
101
12
101
12 29
101
12 29
101
12 29
101
12 29
101
12 29
101
12
101
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
29 33
1/16W
5%
402
MF-LF
10K
R3041
402
5% MF-LF
10K
R3040
1/16W
2.2UF
CERM 402-LF
20%
6.3V
C3040
X5R 603
20%
6.3V
C3000
X5R 603
20%
6.3V
C3001
10V
20% 402
CERM
0.1UF
C3010
10V
20% 402
CERM
0.1UF
C3011
10V
20% 402
CERM
0.1UF
C3012
10V
20% 402
CERM
0.1UF
C3013
10V
20% 402
CERM
0.1UF
C3014
10V
20% 402
CERM
0.1UF
C3015
CERM 402
20% 10V
0.1UF
C3016
402
CERM
10V
20%
0.1UF
C3017
0.1UF
20% 10V
402
CERM
C3018
402
20%
C3019
10V CERM
0.1UF 0.1UF
20% 10V CERM 402
C3020
0.1UF
CERM 402
20% 10V
C3021
0.1UF
CERM 402
20% 10V
C3022
CERM 402
20% 10V
C3023
0.1UF
402
X5R
1UF
10% 10V
C3053
1UF
X5R 402
10% 10V
C3052
402
X5R
10% 10V
C3051
1UF
10V X5R
10%
1UF
C3050
402
29 33
SODIMM-P0.60-D8
J3000
F-ANG-SM-2
SODIMM-P0.60-D8
J3000
F-ANG-SM-2
SYNC_MASTER=D8_MLB
DDR3 SO-DIMM Connector A Slot1
SYNC_DATE=08/27/2012
=PP3V3_S0_MEM_A_SPD
=PP3V3_S0_MEM_A_SPD
MEM_DIMM1_SA<0> MEM_DIMM1_SA<1>
MEM_A_A<13>
MEM_A_BA<0>
MEM_A_A<10>
MEM_A_A<3>
=MEM_A_DQ<54> =MEM_A_DQ<55>
=MEM_A_DQS_P<0>
=MEM_A_DQ<5>
=MEM_A_DQ<4>
=MEM_A_DQ<6> =MEM_A_DQ<7>
=MEM_A_DQ<1>
=MEM_A_DQ<12>
=MEM_A_DQ<20>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<21>
=MEM_A_DQ<22> =MEM_A_DQ<23>
=MEM_A_DQ<28> =MEM_A_DQ<29>
=MEM_A_DQS_P<3>
=MEM_A_DQ<30>
MEM_A_CKE<3>
MEM_A_A<15> MEM_A_A<14>
MEM_A_A<7>
MEM_A_A<11>
MEM_A_A<4>
MEM_A_A<6>
MEM_A_A<2> MEM_A_A<0>
MEM_A_CLK_P<3>
MEM_A_ODT<3>
MEM_A_ODT<2>
MEM_A_BA<1>
=MEM_A_DQ<39>
=MEM_A_DQ<38>
=MEM_A_DQ<37>
=MEM_A_DQ<36>
=PPDDRVREF_CA_MEM_A
=PPVDDQ_S3_MEM_A
=MEM_A_DQ<47>
=MEM_A_DQ<44>
=MEM_A_DQ<46>
=MEM_A_DQS_P<5>
=MEM_A_DQ<45>
=MEM_A_DQ<52>
=MEM_A_DQ<61>
=MEM_A_DQ<60>
=MEM_A_DQ<53>
=PPDDRVTT_S0_MEM_A
=MEM_A_DQS_P<7>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=I2C_SODIMMA_SDA =I2C_SODIMMA_SCL
=MEM_A_DQ<2> =MEM_A_DQ<3>
=MEM_A_DQ<8> =MEM_A_DQ<9>
=MEM_A_DQS_P<1>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<17>
=MEM_A_DQS_P<2>
=MEM_A_DQ<24> =MEM_A_DQ<25>
=MEM_A_DQ<19>
=MEM_A_DQ<26>
MEM_A_CKE<2>
MEM_A_A<5>
MEM_A_CLK_P<2>
MEM_A_A<1>
=MEM_A_DQ<33>
=MEM_A_DQ<32>
=MEM_A_DQ<34>
=MEM_A_DQS_P<4>
=MEM_A_DQ<35>
=MEM_A_DQ<41>
=MEM_A_DQ<40>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<48>
=MEM_A_DQS_P<6>
=MEM_A_DQ<49>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<56> =MEM_A_DQ<57>
=MEM_A_DQ<58> =MEM_A_DQ<59>
MEM_DIMM1_SA<0>
MEM_DIMM1_SA<1>
=PP3V3_S0_MEM_A_SPD
=PPDDRVTT_S0_MEM_A
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<12>
MEM_A_BA<2>
=PPVDDQ_S3_MEM_A
=MEM_A_DQ<31>
=MEM_A_DQS_N<0>
=MEM_A_DQS_N<1>
MEM_RESET_L
=MEM_A_DQS_N<2>
=MEM_A_DQS_N<3>
MEM_A_CLK_N<2> MEM_A_CLK_N<3>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_CS_L<2>
MEM_A_CAS_L
MEM_A_CS_L<3>
=MEM_A_DQS_N<4>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<7>
MEM_EVENT_L
=MEM_A_DQ<27>
=MEM_A_DQ<18>
=MEM_A_DQ<16>
=PPDDRVREF_DQ_MEM_A
=MEM_A_DQ<0>
prefsb
051-9505
8.0.0
30 OF 144 30 OF 123
2
1
2
1
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
5
1 3
9
11
37 39
43
51
61
71
69
198
186
169
152
135
121
115
114113
110
104103
62
45
30
27
10
70
75 77 79 81 83 85
89
195
203
199 201
197
193
189 191
187
185
183
181
179
175 177
165 167
171 173
163
155 157 159 161
153
147
151
145
149
143
133
137 139 141
129
125
123
127
131
105
93
97 99
101
87
91
73
65
63
67
55
53
59
57
49
47
41
33 35
31
29
25
23
21
19
17
15
202
200
190 192 194 196
188
204
170
166 168
172
180 182 184
164
148 150
162
154 156 158
146
160
144
136
124 126 128 130 132 134
138 140 142
108
106
112
116 118 120 122
102
98
96
90 92
84 86
94
88
100
82
80
78
74 76
72
68
64 66
46
58 60
56
52 54
48 50
44
42
28
24 26
32 34 36 38 40
22
20
13
7
18
16
4 6
12 14
8
2
178
176
174
95
107 109 111
117 119
205 206 207 208 209
6
29 30
6
29 30
30
30
6
29
6
29 30
6
29 30
30
30
6
29 30
6
29 30
6
29 30
6
29
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN
IN
NC
BI
BI
BI
BI
BI BI
BI
IN
BI
BI
BI
BI BI
BI BI
BI
IN
BI
BI BI
BI
BI
IN
IN
IN IN
IN
IN IN
IN IN
IN IN
IN
BI
NC
DQ0
VREFDQ VSS_1
VSS_3 DM0
VSS_12 DQ16
VSS_14
DQ18
VSS_21
VSS_24
DQ27
EVENT*
DQS7*
DQS6*
DQS5*
DQS4*
S1*
CAS*
S0*WE*
RAS*
CK1*CK0*
DQS3*
DQS2*
RESET*
DQS1*
DQS0*
DQ31
VDD_0 NC_0 BA2 VDD_2 A12/BC* A9
A8
VSS_50
VTT_0
VDDSPD SA1
SA0
DQ59
VSS_48 DQ58
DM7
VSS_47
DQ57
DQ56
VSS_45
DQ50 DQ51
DQ49 VSS_40
DQS6 VSS_43
DQ48
VSS_36 DQ42 DQ43 VSS_38
DM5
DQ40
VSS_35
VSS_33
DQ41
DQ35
VSS_28
DQS4 VSS_31 DQ34
DQ32
TEST
VDD_16
VSS_26
DQ33
VDD_10
VDD_6
A1 VDD_8 CK0
VDD_4
A5
CKE0
VSS_22
DM3
DQ26
VSS_19
DQ19
DQ25
DQ24
VSS_17
DQS2
DQ17
DQ10 DQ11
VSS_10
DQS1
VSS_8
DQ9
DQ8
VSS_6
DQ3
DQ2
SCL
SDA
VSS_49
DQ62 DQ63
VSS_51
DQS7
VTT_1
DM6
DQ53
VSS_41
VSS_42
DQ60 DQ61
VSS_46
DQ52
DQ45
VSS_34
VSS_39
DQS5
VSS_37
DQ46
DQ44
DQ47
VSS_32
DM4
VDD_17 VREFCA VSS_27
DQ36 DQ37
VSS_29
VSS_30
DQ38 DQ39
BA1
VDD_11
VDD_13
ODT0
VDD_15
ODT1 NC_1
CK1
A0
A2
A6 A4
A11
A7
VDD_7
VDD_5
VDD_9
VDD_3
A14
A15
CKE1
VDD_1
VSS_25
DQ30
DQS3
VSS_23
DM2
DQ29
VSS_20
DQ28
DQ23
VSS_18
VSS_16
DQ22
VSS_15
DQ21
DM1
DQ13
VSS_9
VSS_11
DQ14 DQ15
VSS_13
DQ20
DQ12
VSS_7
VSS_4
DQ1
DQ7
DQ6
DQ4 DQ5
DQS0
VSS_5
VSS_2
VSS_0
VSS_44
DQ55
DQ54
A3
A10_AP BA0 VDD_12
VDD_14 A13
KEY
SYM 1 OF 2
SYM 2 OF 2
MTG HOLE
NC
BI
BI BI
BI BI
BI BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
OUT
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI BI
BI BI
BI BI
BI BI
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
- =PPVDDQ_S3_MEM_B
- =PPDDRVTT_S0_MEM_B
- =PP1V5_S0_MEM_B
Signal aliases required by this page:
BOM options provided by this page:
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
(NONE)
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
Power aliases required by this page:
Page Notes
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
P/N: 516S1030
1UF
10%
402
10V X5R
C3153
32 50
12
101
12 32
101
12 32
101
12 32
101
12 32
101
12 32
101
12 32
101
12 32
101
12
101
12
101
12 32
101
32 33
32 33
32 33
32 33
32 33
32 33
32 33
0.1UF
CERM
20%
402
10V
C3131
12 32
101
32 33
32 33
32 33
32 33
32 33
32 33
32 33
C3130
2.2UF
402-LF
6.3V CERM
20%
32 33
12
101
32 33
32 33
32 33
32 33
32 33
12
101
12 32
101
12 32
101
12 32
101
12
101
C3117
20%
402
10V CERM
0.1UF
12 32
101
12 32
101
12 32
101
12 32
101
12
101
12
101
0.1UF
CERM 402
20% 10V
C3123
10V 402
CERM
0.1UF
C3116
20%
12
101
20% CERM
0.1UF
C3115
402
10V
0.1UF
10V
20%
402
C3114
CERM
0.1UF
20%
402
CERM
C3113
10V
0.1UF
CERM 402
20% 10V
C3122
20% 402
CERM
0.1UF
10V
C3121
20% 10V
402
CERM
C3120
0.1UF
20%
0.1UF
CERM 402
10V
C3119
0.1UF
CERM 402
20%
C3112
10V
0.1UF
10V
20%
402
CERM
C3111
20%
0.1UF
CERM 402
10V
C3110
32 33
10V
20% 402
CERM
0.1UF
C3118
6.3V
20% 603
X5R
C3101
6.3V
20% 603
X5R
C3100
J3100
F-ANG-SM-2
SODIMM-P0.60-D8
SODIMM-P0.60-D8
J3100
F-ANG-SM-2
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
CERM
0.1UF
10V 402
20%
C3136
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
6.3V
20% 402-LF
CERM
2.2UF
C3135
29 30 32 47 48
119
12 32
101
12 32
101
12 32
101
12 32
101
12 32
101
12
101
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
402
10% X5R
10V
1UF
C3152
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
1UF
10V
10%
402
X5R
C3151
32 33
402
10K
MF-LF
5% 1/16W
R3141
10K
MF-LF 402
5% 1/16W
R3140
2.2UF
CERM 402-LF
20%
6.3V
C3140
32 33
32 33
32 33
32 33
10V
10%
402
X5R
1UF
C3150
32 33
32 33
32 33
32 33
32 33
28 29 30 32
101
32 33
32 33
32 50
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
12 32
101
SYNC_MASTER=D8_MLB
DDR3 SO-DIMM CONNECTOR B SLOT0
SYNC_DATE=08/27/2012
=MEM_B_DQ<6>
=PP3V3_S0_MEM_B_SPD
=PP3V3_S0_MEM_B_SPD
MEM_DIMM2_SA<0>
MEM_DIMM2_SA<1>
MEM_B_A<13>
MEM_B_BA<0>
MEM_B_A<10>
MEM_B_A<3>
=MEM_B_DQ<54> =MEM_B_DQ<55>
=MEM_B_DQS_P<0>
=MEM_B_DQ<5>
=MEM_B_DQ<4>
=MEM_B_DQ<7>
=MEM_B_DQ<1>
=MEM_B_DQ<12> =MEM_B_DQ<13>
=MEM_B_DQ<22> =MEM_B_DQ<23>
=MEM_B_DQ<28> =MEM_B_DQ<29>
=MEM_B_DQS_P<3>
=MEM_B_DQ<30>
MEM_B_CKE<1>
MEM_B_A<15> MEM_B_A<14>
MEM_B_A<7>
MEM_B_A<11>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<2> MEM_B_A<0>
MEM_B_CLK_P<1>
MEM_B_ODT<1>
MEM_B_ODT<0>
MEM_B_BA<1>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DQ<37>
=MEM_B_DQ<36>
=PPDDRVREF_CA_MEM_B
=PPVDDQ_S3_MEM_B
=MEM_B_DQ<47>
=MEM_B_DQ<44>
=MEM_B_DQ<46>
=MEM_B_DQS_P<5>
=MEM_B_DQ<45>
=MEM_B_DQ<52>
=MEM_B_DQ<61>
=MEM_B_DQ<60>
=MEM_B_DQ<53>
=PPDDRVTT_S0_MEM_B
=MEM_B_DQS_P<7>
=MEM_B_DQ<63>
=MEM_B_DQ<62>
=I2C_SODIMMB_SDA =I2C_SODIMMB_SCL
=MEM_B_DQ<2> =MEM_B_DQ<3>
=MEM_B_DQ<8> =MEM_B_DQ<9>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQ<17>
=MEM_B_DQS_P<2>
=MEM_B_DQ<24> =MEM_B_DQ<25>
=MEM_B_DQ<19>
=MEM_B_DQ<26>
MEM_B_CKE<0>
MEM_B_A<5>
MEM_B_CLK_P<0>
MEM_B_A<1>
=MEM_B_DQ<33>
=MEM_B_DQ<32>
=MEM_B_DQ<34>
=MEM_B_DQS_P<4>
=MEM_B_DQ<35>
=MEM_B_DQ<41>
=MEM_B_DQ<40>
=MEM_B_DQ<43>
=MEM_B_DQ<42>
=MEM_B_DQ<48>
=MEM_B_DQS_P<6>
=MEM_B_DQ<49>
=MEM_B_DQ<51>
=MEM_B_DQ<50>
=MEM_B_DQ<56> =MEM_B_DQ<57>
=MEM_B_DQ<58> =MEM_B_DQ<59>
MEM_DIMM2_SA<0>
MEM_DIMM2_SA<1>
=PP3V3_S0_MEM_B_SPD
=PPDDRVTT_S0_MEM_B
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<12>
MEM_B_BA<2>
=PPVDDQ_S3_MEM_B
=MEM_B_DQ<31>
=MEM_B_DQS_N<0>
=MEM_B_DQS_N<1>
MEM_RESET_L
=MEM_B_DQS_N<2>
=MEM_B_DQS_N<3>
MEM_B_CLK_N<0> MEM_B_CLK_N<1>
MEM_B_RAS_L
MEM_B_WE_L
MEM_B_CS_L<0>
MEM_B_CAS_L
MEM_B_CS_L<1>
=MEM_B_DQS_N<4>
=MEM_B_DQS_N<5>
=MEM_B_DQS_N<6>
=MEM_B_DQS_N<7>
MEM_EVENT_L
=MEM_B_DQ<27>
=MEM_B_DQ<18>
=MEM_B_DQ<16>
=PPDDRVREF_DQ_MEM_B
=MEM_B_DQ<0>
=MEM_B_DQ<20>
=MEM_B_DQ<14> =MEM_B_DQ<15>
=MEM_B_DQ<21>
=MEM_B_DQS_P<1>
prefsb
051-9505
8.0.0
31 OF 144 31 OF 123
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
5
1 3
9
11
37 39
43
51
61
71
69
198
186
169
152
135
121
115
114113
110
104103
62
45
30
27
10
70
75 77 79 81 83 85
89
195
203
199 201
197
193
189 191
187
185
183
181
179
175 177
165 167
171 173
163
155 157 159 161
153
147
151
145
149
143
133
137 139 141
129
125
123
127
131
105
93
97 99
101
87
91
73
65
63
67
55
53
59
57
49
47
41
33 35
31
29
25
23
21
19
17
15
202
200
190 192 194 196
188
204
170
166 168
172
180 182 184
164
148 150
162
154 156 158
146
160
144
136
124 126 128 130 132 134
138 140 142
108
106
112
116 118 120 122
102
98
96
90 92
84 86
94
88
100
82
80
78
74 76
72
68
64 66
46
58 60
56
52 54
48 50
44
42
28
24 26
32 34 36 38 40
22
20
13
7
18
16
4 6
12 14
8
2
178
176
174
95
107 109 111
117 119
205 206 207 208 209
2
1
2
1
2
1
2
1
1
2
1
2
2
1
2
1
6
31 32
6
31 32
31
31
6
32
6
31 32
6
31 32
31
31
6
31 32
6
31 32
6
31 32
6
32
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN
IN
NC
BI
BI
BI
BI
BI BI
BI
IN
BI
BI
BI
BI BI
BI BI
BI
IN
BI
BI BI
BI
BI
IN
IN
IN IN
IN
IN IN
IN IN
IN IN
IN
BI
NC
DQ0
VREFDQ VSS_1
VSS_3 DM0
VSS_12 DQ16
VSS_14
DQ18
VSS_21
VSS_24
DQ27
EVENT*
DQS7*
DQS6*
DQS5*
DQS4*
S1*
CAS*
S0*WE*
RAS*
CK1*CK0*
DQS3*
DQS2*
RESET*
DQS1*
DQS0*
DQ31
VDD_0 NC_0 BA2 VDD_2 A12/BC* A9
A8
VSS_50
VTT_0
VDDSPD SA1
SA0
DQ59
VSS_48 DQ58
DM7
VSS_47
DQ57
DQ56
VSS_45
DQ50 DQ51
DQ49 VSS_40
DQS6 VSS_43
DQ48
VSS_36 DQ42 DQ43 VSS_38
DM5
DQ40
VSS_35
VSS_33
DQ41
DQ35
VSS_28
DQS4 VSS_31 DQ34
DQ32
TEST
VDD_16
VSS_26
DQ33
VDD_10
VDD_6
A1 VDD_8 CK0
VDD_4
A5
CKE0
VSS_22
DM3
DQ26
VSS_19
DQ19
DQ25
DQ24
VSS_17
DQS2
DQ17
DQ10 DQ11
VSS_10
DQS1
VSS_8
DQ9
DQ8
VSS_6
DQ3
DQ2
SCL
SDA
VSS_49
DQ62 DQ63
VSS_51
DQS7
VTT_1
DM6
DQ53
VSS_41
VSS_42
DQ60 DQ61
VSS_46
DQ52
DQ45
VSS_34
VSS_39
DQS5
VSS_37
DQ46
DQ44
DQ47
VSS_32
DM4
VDD_17 VREFCA VSS_27
DQ36 DQ37
VSS_29
VSS_30
DQ38 DQ39
BA1
VDD_11
VDD_13
ODT0
VDD_15
ODT1 NC_1
CK1
A0
A2
A6 A4
A11
A7
VDD_7
VDD_5
VDD_9
VDD_3
A14
A15
CKE1
VDD_1
VSS_25
DQ30
DQS3
VSS_23
DM2
DQ29
VSS_20
DQ28
DQ23
VSS_18
VSS_16
DQ22
VSS_15
DQ21
DM1
DQ13
VSS_9
VSS_11
DQ14 DQ15
VSS_13
DQ20
DQ12
VSS_7
VSS_4
DQ1
DQ7
DQ6
DQ4 DQ5
DQS0
VSS_5
VSS_2
VSS_0
VSS_44
DQ55
DQ54
A3
A10_AP BA0 VDD_12
VDD_14 A13
KEY
SYM 1 OF 2
SYM 2 OF 2
MTG HOLE
NC
BI
BI BI
BI BI
BI BI
BI
BI
BI
BI
BI BI
BI BI
BI
BI
BI
BI
OUT
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI BI
BI BI
BI BI
BI BI
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
P/N: 516S1030
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
- =PPDDRVTT_S0_MEM_B
- =PPVDDQ_S3_MEM_B
- =I2C_SODIMMA_SCL
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
- =I2C_SODIMMA_SDA
BOM options provided by this page:
(NONE)
- =PP1V5_S0_MEM_B
Power aliases required by this page:
Signal aliases required by this page:
Page Notes
1UF
X5R 402
10% 10V
C3253
31 50
12
101
12 31
101
12 31
101
12 31
101
12 31
101
12 31
101
12 31
101
12 31
101
12
101
12
101
12 31
101
31 33
31 33
31 33
31 33
31 33
31 33
31 33
0.1UF
C3231
20% 10V CERM 402
12 31
101
31 33
31 33
31 33
31 33
31 33
31 33
31 33
C3230
2.2UF
20% CERM
402-LF
6.3V
31 33
12
101
31 33
31 33
31 33
31 33
31 33
12
101
12 31
101
12 31
101
12 31
101
12
101
0.1UF
CERM 402
20% 10V
C3217
12 31
101
12 31
101
12 31
101
12 31
101
12
101
12
101
C3223
0.1UF
CERM 402
20% 10V
0.1UF
CERM 402
20% 10V
C3216
12
101
0.1UF
CERM 402
20% 10V
C3215
0.1UF
CERM 402
20% 10V
C3214
0.1UF
CERM 402
20% 10V
C3213
0.1UF
CERM 402
20% 10V
C3222
402
20% 10V CERM
0.1UF
C3221
0.1UF
CERM 402
10V
20%
C3220
0.1UF
CERM 402
20% 10V
C3219
10V
20%
402
CERM
0.1UF
C3212
10V
20%
402
CERM
0.1UF
C3211
10V
20%
402
CERM
C3210
0.1UF
31 33
10V
20% 402
CERM
0.1UF
C3218
X5R 603
20%
6.3V
C3201
6.3V
20% 603
X5R
C3200
F-ANG-SM-2
J3200
SODIMM-P0.60-D8
J3200
F-ANG-SM-2
SODIMM-P0.60-D8
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
CERM 402
20% 10V
0.1UF
C3236
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
2.2UF
CERM 402-LF
20%
6.3V
C3235
29 30 31 47 48
119
12 31
101
12 31
101
12 31
101
12 31
101
12 31
101
12
101
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
1UF
X5R 402
10% 10V
C3252
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
1UF
X5R 402
10% 10V
C3251
31 33
1/16W
5%
402
MF-LF
R3241
10K
1/16W
5%
402
MF-LF
10K
R3240
CERM 402-LF
20%
6.3V
2.2UF
C3240
31 33
31 33
31 33
31 33
X5R 402
10% 10V
1UF
C3250
31 33
31 33
31 33
31 33
31 33
28 29 30 31
101
31 33
31 33
31 50
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
31 33
12 31
101
SYNC_MASTER=D8_MLB
DDR3 SO-DIMM CONNECTOR B SLOT1
SYNC_DATE=08/27/2012
MEM_B_A<4>
MEM_B_A<2>
MEM_B_CKE<3>
=MEM_B_DQ<13>
=MEM_B_DQ<0>
=PPDDRVREF_DQ_MEM_B
=MEM_B_DQ<18>
=MEM_B_DQ<27>
MEM_EVENT_L
=MEM_B_DQS_N<7>
=MEM_B_DQS_N<6>
=MEM_B_DQS_N<5>
=MEM_B_DQS_N<4>
MEM_B_CS_L<3>
MEM_B_CAS_L
MEM_B_CS_L<2>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_CLK_N<3>MEM_B_CLK_N<2>
=MEM_B_DQS_N<3>
=MEM_B_DQS_N<2>
MEM_RESET_L
=MEM_B_DQS_N<1>
=MEM_B_DQS_N<0>
=MEM_B_DQ<31>
=PPVDDQ_S3_MEM_B
MEM_B_BA<2>
MEM_B_A<12> MEM_B_A<9>
MEM_B_A<8>
=PPDDRVTT_S0_MEM_B
=PP3V3_S0_MEM_B_SPD MEM_DIMM3_SA<1>
MEM_DIMM3_SA<0>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<56>
=MEM_B_DQ<50> =MEM_B_DQ<51>
=MEM_B_DQ<49>
=MEM_B_DQS_P<6>
=MEM_B_DQ<48>
=MEM_B_DQ<42> =MEM_B_DQ<43>
=MEM_B_DQ<40> =MEM_B_DQ<41>
=MEM_B_DQ<35>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<32> =MEM_B_DQ<33>
MEM_B_A<1>
MEM_B_CLK_P<2>
MEM_B_A<5>
MEM_B_CKE<2>
=MEM_B_DQ<26>
=MEM_B_DQ<19>
=MEM_B_DQ<25>
=MEM_B_DQ<24>
=MEM_B_DQS_P<2>
=MEM_B_DQ<17>
=MEM_B_DQ<10> =MEM_B_DQ<11>
=MEM_B_DQS_P<1>
=MEM_B_DQ<9>
=MEM_B_DQ<8>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
=MEM_B_DQ<62> =MEM_B_DQ<63>
=MEM_B_DQS_P<7>
=PPDDRVTT_S0_MEM_B
=MEM_B_DQ<53>
=MEM_B_DQ<60> =MEM_B_DQ<61>
=MEM_B_DQ<52>
=MEM_B_DQ<45>
=MEM_B_DQS_P<5>
=MEM_B_DQ<46>
=MEM_B_DQ<44>
=MEM_B_DQ<47>
=PPVDDQ_S3_MEM_B
=PPDDRVREF_CA_MEM_B
=MEM_B_DQ<36> =MEM_B_DQ<37>
=MEM_B_DQ<38> =MEM_B_DQ<39>
MEM_B_BA<1>
MEM_B_ODT<2>
MEM_B_ODT<3>
MEM_B_CLK_P<3>
MEM_B_A<0>
MEM_B_A<6>
MEM_B_A<11> MEM_B_A<7>
MEM_B_A<14>
MEM_B_A<15>
=MEM_B_DQ<30>
=MEM_B_DQS_P<3>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DQ<21>
=MEM_B_DQ<14> =MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DQ<12>
=MEM_B_DQ<1>
=MEM_B_DQ<7>
=MEM_B_DQ<5>
=MEM_B_DQS_P<0>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
MEM_B_A<3>
MEM_B_A<10> MEM_B_BA<0>
MEM_B_A<13>
MEM_DIMM3_SA<0> =PP3V3_S0_MEM_B_SPD
MEM_DIMM3_SA<1>
=PP3V3_S0_MEM_B_SPD
=MEM_B_DQ<6>
=MEM_B_DQ<16>
=MEM_B_DQ<4>
prefsb
051-9505
8.0.0
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Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SYNC_MASTER=D8_MLB
DDR3 ALIASES AND BITSWAPS
SYNC_DATE=08/27/2012
MEM_A_DQS_N<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<52>
MAKE_BASE=TRUE
MEM_B_DQ<58>
MAKE_BASE=TRUE
MEM_B_DQ<59>
MAKE_BASE=TRUE
MEM_B_DQS_N<7>
MAKE_BASE=TRUE
MEM_B_DQS_N<6>
MAKE_BASE=TRUE
MEM_B_DQ<40>
MEM_B_DQ<34>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<37>
MEM_B_DQ<13>
MAKE_BASE=TRUE
MEM_B_DQ<14>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<0>
MEM_B_DQS_N<2>
MAKE_BASE=TRUE
MEM_A_DQ<51>
MAKE_BASE=TRUE
MEM_A_DQ<52>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<40>
MAKE_BASE=TRUE
MEM_A_DQ<43>
MEM_A_DQ<44>
MAKE_BASE=TRUE
MEM_A_DQ<45>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<46>
MEM_A_DQ<47>
MAKE_BASE=TRUE
MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MEM_A_DQS_N<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<32>
MEM_A_DQ<33>
MAKE_BASE=TRUE
MEM_B_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<33>
MEM_B_DQ<35>
MAKE_BASE=TRUE
MEM_B_DQS_N<5>
MAKE_BASE=TRUE
MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<3>
MAKE_BASE=TRUE
MEM_A_DQ<26> MEM_A_DQ<25>
MAKE_BASE=TRUE
MEM_A_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<30>
MEM_A_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<54>
MEM_A_DQ<12>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<55>
MEM_A_DQ<10>
MAKE_BASE=TRUE
MEM_A_DQ<14>
MAKE_BASE=TRUE
MEM_A_DQ<21>
MAKE_BASE=TRUE
MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<22>
MAKE_BASE=TRUE
MEM_A_DQ<28>
MAKE_BASE=TRUE
MEM_A_DQ<39>
MEM_A_DQ<29>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<38>
MAKE_BASE=TRUE
MEM_A_DQ<36>
MEM_A_DQ<27>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<63>
MAKE_BASE=TRUE
MEM_B_DQ<61>
MAKE_BASE=TRUE
MEM_B_DQ<60>
MAKE_BASE=TRUE
MEM_B_DQ<57>
MAKE_BASE=TRUE
MEM_B_DQ<53>
MAKE_BASE=TRUE
MEM_A_DQ<34>
MEM_A_DQ<35>
MAKE_BASE=TRUE
MEM_A_DQ<37>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<56>
MAKE_BASE=TRUE
MEM_B_DQ<42>
MAKE_BASE=TRUE
MEM_A_DQS_N<0>
MAKE_BASE=TRUE
MEM_B_DQS_P<7>
MEM_A_DQS_P<4>
MAKE_BASE=TRUE
MEM_A_DQS_P<6>
MAKE_BASE=TRUE
MEM_B_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<18>
MAKE_BASE=TRUE
MEM_A_DQS_P<0>
MEM_A_DQ<23>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<2>
MEM_A_DQ<15>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<31>
MAKE_BASE=TRUE
MEM_A_DQ<9>
MAKE_BASE=TRUE
MEM_A_DQ<7>
MAKE_BASE=TRUE
MEM_A_DQ<6>
MAKE_BASE=TRUE
MEM_A_DQ<5>
MAKE_BASE=TRUE
MEM_A_DQ<4>
MAKE_BASE=TRUE
MEM_A_DQ<3>
MAKE_BASE=TRUE
MEM_A_DQ<2>
MAKE_BASE=TRUE
MEM_A_DQ<1>
MAKE_BASE=TRUE
MEM_A_DQ<0>
MEM_A_DQS_N<1>
MAKE_BASE=TRUE
MEM_A_DQS_P<1>
MAKE_BASE=TRUE
MEM_A_DQS_N<4>
MAKE_BASE=TRUE
MEM_B_DQ<47>
MAKE_BASE=TRUE
MEM_B_DQ<41>
MAKE_BASE=TRUE
MEM_B_DQS_P<6>
MAKE_BASE=TRUE
MEM_B_DQ<50>
MAKE_BASE=TRUE
MEM_B_DQ<51>
MAKE_BASE=TRUE
MEM_B_DQ<43>
MAKE_BASE=TRUE
MEM_B_DQ<44>
MAKE_BASE=TRUE
MEM_B_DQ<45>
MAKE_BASE=TRUE
MEM_B_DQ<46>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<36>
MEM_B_DQ<49>
MAKE_BASE=TRUE
MEM_B_DQ<24>
MAKE_BASE=TRUE
MEM_B_DQ<29>
MAKE_BASE=TRUE
MEM_B_DQ<23>
MAKE_BASE=TRUE
MEM_B_DQ<17>
MAKE_BASE=TRUE
MEM_B_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<16>
MAKE_BASE=TRUE
MEM_B_DQ<20>
MEM_B_DQS_N<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<22> MEM_B_DQ<21>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<9> MEM_B_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<25>
MEM_B_DQS_P<1>
MAKE_BASE=TRUE
MEM_B_DQS_N<1>
MAKE_BASE=TRUE
MEM_B_DQ<5>
MAKE_BASE=TRUE
MEM_B_DQ<4>
MAKE_BASE=TRUE MAKE_BASE=TRUE
MEM_B_DQ<3> MEM_B_DQ<2>
MAKE_BASE=TRUE
MEM_B_DQ<1>
MAKE_BASE=TRUE
MEM_B_DQ<15>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<12>
MAKE_BASE=TRUE
MEM_B_DQ<11>
MEM_B_DQ<26>
MAKE_BASE=TRUE
MEM_B_DQ<27>
MAKE_BASE=TRUE
MEM_B_DQ<28>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<31>
MEM_B_DQ<6>
MAKE_BASE=TRUE
MEM_B_DQS_P<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<0>
MEM_B_DQ<7>
MAKE_BASE=TRUE
MEM_A_DQ<17>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<30>
MAKE_BASE=TRUE
MEM_A_DQ<13>
MAKE_BASE=TRUE
MEM_B_DQ<18>
MAKE_BASE=TRUE
MEM_B_DQS_P<2>
MEM_B_DQ<10>
MAKE_BASE=TRUE
MEM_B_DQ<19>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<20>
MAKE_BASE=TRUE
MEM_A_DQ<19>
MEM_A_DQ<11>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_P<2>
MEM_B_DQS_N<4>
MAKE_BASE=TRUE MAKE_BASE=TRUE
MEM_B_DQS_P<4>
MAKE_BASE=TRUE
MEM_B_DQ<39> MEM_B_DQ<38>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<41>
MEM_A_DQ<42>
MAKE_BASE=TRUE
MEM_A_DQ<61>
MAKE_BASE=TRUE
MEM_A_DQ<63>
MAKE_BASE=TRUE
MEM_A_DQ<56>
MAKE_BASE=TRUE
MEM_A_DQ<57>
MAKE_BASE=TRUE
MEM_A_DQ<58>
MAKE_BASE=TRUE
MEM_A_DQ<59>
MAKE_BASE=TRUE
MEM_A_DQ<60>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MEM_A_DQS_N<7>
MAKE_BASE=TRUE
MEM_A_DQ<48>
MAKE_BASE=TRUE
MEM_A_DQ<49>
MEM_A_DQ<50>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<53>
MEM_B_DQ<55>
MAKE_BASE=TRUE
MEM_B_DQ<54>
MAKE_BASE=TRUE
MEM_B_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<62>
MAKE_BASE=TRUE
MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<58>
=MEM_B_DQ<48>
=MEM_B_DQS_N<7>
=MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQ<59> =MEM_B_DQ<62>
=MEM_B_DQS_P<1>
=MEM_A_DQ<8>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DQS_P<2>
=MEM_A_DQ<22>
=MEM_A_DQS_N<3>
=MEM_A_DQ<32>
=MEM_A_DQS_P<1>
=MEM_A_DQ<44>
=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQ<14>
=MEM_A_DQ<54>
=MEM_A_DQ<57> =MEM_A_DQ<56>
=MEM_A_DQ<2>
=MEM_A_DQ<63> =MEM_A_DQ<59>
=MEM_A_DQ<0>
=MEM_A_DQS_P<0>
=MEM_A_DQS_N<0>
=MEM_A_DQ<28>
=MEM_A_DQ<42>
=MEM_A_DQ<37> =MEM_A_DQ<35> =MEM_A_DQ<34>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<33>
=MEM_A_DQ<60>
=MEM_A_DQ<17> =MEM_A_DQ<16>
=MEM_A_DQ<15>
=MEM_B_DQ<56> =MEM_B_DQ<57>
=MEM_B_DQ<39> =MEM_B_DQ<38> =MEM_B_DQ<37> =MEM_B_DQ<36> =MEM_B_DQ<35> =MEM_B_DQ<34> =MEM_B_DQ<33> =MEM_B_DQ<32>
=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>
=MEM_B_DQ<47> =MEM_B_DQ<46> =MEM_B_DQ<45> =MEM_B_DQ<44> =MEM_B_DQ<43> =MEM_B_DQ<42> =MEM_B_DQ<41> =MEM_B_DQ<40>
=MEM_B_DQS_N<6>
=MEM_B_DQ<49>
=MEM_B_DQ<58>
=MEM_B_DQ<50>
=MEM_B_DQ<15>
=MEM_B_DQ<12>
=MEM_B_DQ<0>
=MEM_B_DQ<1>
=MEM_B_DQ<2>
=MEM_B_DQ<7>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<6>
=MEM_B_DQ<3>
=MEM_B_DQ<9>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<30>
=MEM_B_DQ<31>
=MEM_B_DQS_P<3>
=MEM_B_DQS_N<3>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DQ<18>
=MEM_B_DQ<22>
=MEM_B_DQS_N<2>
=MEM_B_DQ<25>
=MEM_B_DQ<27>
=MEM_B_DQS_N<4> =MEM_B_DQS_P<4>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<0>
=MEM_B_DQS_N<0>
=MEM_B_DQ<26>
=MEM_B_DQ<24>
=MEM_A_DQ<7> =MEM_A_DQ<6> =MEM_A_DQ<4> =MEM_A_DQ<1> =MEM_A_DQ<3>
=MEM_A_DQ<9>
=MEM_A_DQ<19>
=MEM_A_DQS_P<4>
=MEM_A_DQS_N<4>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<26>
=MEM_A_DQ<27>
=MEM_A_DQ<30>
=MEM_A_DQ<31>
=MEM_A_DQS_P<3>
=MEM_B_DQ<14> =MEM_B_DQ<8>
=MEM_B_DQ<63>
=MEM_B_DQS_P<7>
=MEM_B_DQS_P<6>
=MEM_B_DQ<51>
=MEM_B_DQ<55> =MEM_B_DQ<54> =MEM_B_DQ<52> =MEM_B_DQ<53>
=MEM_B_DQ<19>
=MEM_B_DQ<23>
=MEM_B_DQS_P<2>
=MEM_B_DQ<13>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_A_DQS_N<2>
=MEM_A_DQ<41> =MEM_A_DQ<40>
=MEM_A_DQS_P<6>
=MEM_A_DQS_N<1>
=MEM_A_DQ<5>
=MEM_A_DQ<23>
=MEM_A_DQ<21> =MEM_A_DQ<20> =MEM_A_DQ<18>
=MEM_A_DQ<29>
=MEM_A_DQ<36>
=MEM_A_DQS_N<5> =MEM_A_DQS_P<5>
=MEM_A_DQ<45>
=MEM_A_DQ<43>
=MEM_A_DQ<53>
=MEM_A_DQ<49>
=MEM_A_DQ<51>
=MEM_A_DQS_N<6>
=MEM_A_DQ<55>
=MEM_A_DQ<52>
=MEM_A_DQ<50>
=MEM_A_DQ<48>
=MEM_A_DQS_P<7>
=MEM_A_DQ<62>
=MEM_A_DQS_N<7>
prefsb
051-9505
8.0.0
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V-
V+
V-
V+
IN
D
S G
D
S G
NC NC
NC NC
NC
NC
RESET*
A0 A1 A2
SCL SDA
P0 P1 P2
P5 P6 P7
P3 P4
THRM
VCC
GND
PAD
NC
NC
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTA
SCL
SDA
A0
A1
GND
IN
BI
TABLE_5_ITEM
CRITICAL
BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Addr=0x98(WR)/0x99(RD)
NOTE: CPU DAC output step sizes:
VRef DQ
Driven by CPU
DAC Channel: PCA9557D Pin:
DAC range: VRef current: DAC step size:
Margined target:
MEM A VREF CA
0.75V (DAC: 0x3A)
7.69mV / step @ output
0.300V - 1.200V (+/- 450mV)
+3.4mA - -3.4mA (- = sourced)
MEM B VREF CA
MEM VREG
8.59mV / step @ output
+61uA - -61uA (- = sourced)
1.5V (DAC: 0x3A)
1.000V - 2.000V (+/- 500mV)
0.000V - 3.000V (0x00 - 0x74)
GPU Frame Buffer (1.8V, 70% VRef)
1.056V - 1.442V (+/- 180mV)
+6.0mA - -5.0mA (- = sourced)
0.000V - 3.300V (0x00 - 0xFF)
1.267V (DAC: 0x8B)
1.51mV / step @ output
0.000V - 1.501V (0x00 - 0x74)
C C D D 3 4 5 6
soft-resets and sleep/wake cycles.
a DAC output, cannot enable
NOTE: MEMVREG and FRAMEBUF share
RST* on ’platform reset’ so that system watchdog will disable margining.
Addr=0x30(WR)/0x31(RD)
(OD)
NOTE: Margining will be disabled across all
both at the same time!
Nominal value
DDR3 (1.5V) 7.70mV per step
VREFMRGN:EXT
402
CERM
10V
20%
0.1UF
C3402
MAX4253
CRITICAL
B1
U3402
B4
UCSP
U3402
MAX4253
CRITICAL
UCSP
B4
B1
VREFMRGN:EXT
R3418
SHORT
NONE
NONE NONE
OMIT
402
SHORT
NONE NONE
R3419
402
NONE
OMIT
26 28
119
PLACE_NEAR=R3421.2:2MM
MF-LF
1/16W 402
1K
1%
R3422
PLACE_NEAR=R3441.2:4MM
R3442
1/16W MF-LF
1K
402
1%
1K
MF-LF
R3421
402
PLACE_NEAR=Q3420.6:64MM
1/16W
1%
1K
1%
402
MF-LF
1/16W
R3441
PLACE_NEAR=Q3420.3:70MM
1/16W
R3403
1%
200
402
MF-LF
VREFMRGN:EXT
R3404
VREFMRGN:EXT
MF-LF
1/16W
402
133
1%
R3406
402
1%
133
1/16W MF-LF
VREFMRGN:EXT
1%
1/16W
R3405
200
402
MF-LF
VREFMRGN:EXT
SOT563
SSM6N15AFE
Q3420
CRITICAL
Q3420
SOT563
CRITICAL
SSM6N15AFE
NOSTUFF
0
R3480
1/16W
402
5%
MF-LF
1/16W MF-LF
402
R3481
0
5%
16V
10%
0.1UF
C3440
0402
X7R-CERM
PLACE_NEAR=Q3420.3:70MM
C3441
16V
10%
0.1UF
0402
X7R-CERM
C3420
X7R-CERM 0402
0.1UF
10% 16V
C3421
X7R-CERM 0402
0.1UF
10% 16V
1/16W
100K
5%
402
MF-LF
R3402
VREFMRGN:EXT
402
1
2
1/16W
5%
100K
R3401
VREFMRGN:EXT
MF-LF
VREFMRGN:EXT
U3401
PCA9557
QFN
CRITICAL
50
50
CRITICAL
VREFMRGN:EXT
U3400
MSOP
DAC5574
50
50
VREFMRGN:EXT
CERM
10V
0.1UF
C3401
20%
402
C3400
2.2UF
VREFMRGN:EXT
20%
402-LF
CERM
6.3V
VREFMRGN:EXT
0.1UF
CERM
C3403
10V
20%
402
SYNC_DATE=08/27/2012
DDR3/FRAMEBUF VREF MARGINING
SYNC_MASTER=D8_MLB
VREFMRGN:N
RES,MTL FLM,0,5%,402,SM,LF
R3403,R3405
2
116S0004
CPU_DIMM_VREF_DAC_A
PLACE_NEAR=Q3420.6:2mm
PPDDRVREF_DQ_MEM_A
=PPVDDQ_S3_DDR_VREF
PPDDRVREF_DQ_MEM_B
=PPVDDQ_S3_DDR_VREF
MIN_LINE_WIDTH=0.3 mm
PP3V3_S4_VREFMRGN_CTRL
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
PP3V3_S4_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
VREFMRGN_SODIMMS_CA_MEM_B_R
=PP3V3_S4_VREFMRGN
=I2C_VREFDACS_SCL
PCA9557D_RESET_L
=I2C_PCA9557D_SCL
=PPDDRVTT_S3_VREFCA
PPDDRVREF_CA_MEM_A
ISOLATE_CPU_MEM_L
ISOLATE_CPU_MEM_L
CPU_DIMM_VREF_DAC_B
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SDA
VREFMRGN_CA_SODIMMA_BUF
VREFMRGN_SODIMMS_CA_MEM_A
VREFMRGN_CA_SODIMMB_EN
=PP3V3_S4_VREFMRGN
VREFMRGN_CA_SODIMMB_BUF
PPDDRVREF_CA_MEM_B
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_SODIMMS_CA_MEM_B
prefsb
051-9505
8.0.0
34 OF 144 34 OF 123
2
1
C4
C1
C3
C2
A4
A1
A3
A2
1 2
1 2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1 2
6
1
2
3
4
5
1 2
1
2
2
1
2
1
2
1
2
1
1
2
15
3 4 5
1 2
6 7 9
12 13 14
16
10 11
17
8
8
3
5
4
2
16
7
9
10
2
1
2
1
2
1
11
110
6
6
34
6
6
34
110
110
6
34
6
6
21 28 34
103
21 28 34
103
11
110
123
6
34
6
123
IN
IN
OUT
OUT
OUT OUT
OUT
IN IN
IN
IN
BI
D
GS
VDD
GND
DM
DP
OE*
S
DP_1
DM_1
DM_2
DP_2
BI
BI
IN
D
GS
OUT
NC
D
S
G
G
S
D
P-CH
N-CH
IN
VINONVOUT
GND
VINONVOUT
GND
IN
OUT
EN
MR*
GND
THRM
IN
VDD
SENSE
RESET*
+
-
PAD
(OD)
DLY
VREF
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SUPERVISOR & CLKREG # ISOLATION
DELAY = 130 MS +/- 20%
514S0335
AIRPORT
BLUETOOTH
WI-FI POWER CONSUMPTION: RDAR://10174119
26
117
15 35
117
15
117
CERM
10V
20%
0.1uF
C3530
402
1%
402
1/16W MF-LF
R3531
1%
MF-LF
1/16W 402
R3532
R3530
402
1% 1/16W MF-LF
35
117
20%
C3508
X5R 603
6.3V
18
102
18
102
J3500
SSD-K99
F-RT-SM1
CRITICAL
35
117
18
102
18
102
X5R
6.3V
201
0.1UF
C3505
10%
X5R
0.1UF
6.3V
201
10%
C3506
18
102
18
102
47 48
117
6.3V
C3504
20% X5R
603
R3570
5%
10K
402
1/16W MF-LF
CRITICAL
SSM3K15FV
Q3570
SOD-VESM-HF
U3501
USB3740
CRITICAL
DFN
SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO
27
106
27
106
27 64 74
120
SSM3K15FV
CRITICAL
SOD-VESM-HF
Q3501
47 48
122
MF
201
1%
15K
1/20W
R3599
C3531
CERM 402
20% 10V
0.1uF
1/16W
10K
5%
MF-LF
402
R3542
SOT563
DMC2400UV
Q3543
15 20
117
1/16W 402
5% MF-LF
10K
R3543
TPS22924B
CRITICAL
U3503
CSP
CRITICAL
U3502
CSP
TPS22924B
15 35
117
SLG4AP041V
U3530
TDFN
0603
FERR-220-OHM-2.5A
CRITICAL
L3502
CRITICAL
L3501
0603
FERR-220-OHM-2.5A
0402
C3502
0.1UF
10% 16V X7R-CERM
C3503
0402
0.1UF
10% 16V X7R-CERM
10% 16V
0.1UF
C3507
0402
X7R-CERM
AIRPORT/BT
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
PP3V3_G3H_BT_FLT
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PP3V3_S4_AP_FLT
NET_PHYSICAL_TYPE=POWER_PHY
PCIE_AP_R2D_C_P
PCIE_AP_D2R_P
PP3V3_G3H_BT_FET
VOLTAGE=3.3V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM
BT_PWR_EN
PP3V3_S4_AP_FET
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 mm
BT_PWR_RST_L
PM_PCH_PWROK
P3V3AP_VMON
AP_RESET_CONN_L
AP_CLKREQ_Q_L
PCIE_WAKE_L
AP_WAKE_L
SMC_PME_S4_WAKE_L
USB_ACT_DET
USB_BT_MUX_N
=PP3V3_S4_AP_FET
USB_BT_P
USB_BT_MUX_N
AP_RESET_CONN_L
AP_WAKE_L
AP_CLKREQ_Q_L
USB_BT_MUX_P
PM_PGOOD_P3V3_S4_FET
USB_BT_N
=PP3V3_G3H_BT
SMC_S4_WAKESRC_EN
BT_PWR_RST_L_Q
BT_PWR_RST_L_Q
PCIE_AP_R2D_C_N
AP_EVENT_L
PCIE_AP_R2D_N
PCIE_CLK100M_AP_N
PCIE_AP_D2R_N
PCIE_AP_R2D_P
PCIE_CLK100M_AP_P
USB_BT_MUX_P
=PP3V3_S4_AP_FET
=PP3V3_G3H_BT
AP_CLKREQ_L_ISO
AP_PWR_EN_ISO
AP_RESET_L
=PP3V3_S4_AP
=PP3V3_S4_AP_FET
=PP3V3_S4_AP
AP_PWR_EN_ISO
prefsb
051-9505
8.0.0
35 OF 144 35 OF 123
2
1
1
2
1
2
1
2
2
1
18
21
19 20
10 11 12
13
16
15
14
17
9
1 2 3 4 5 6 7 8
1 2
1 2
2
1
1
2
1
2
3
58
9
10
3
4
2
1
7
6
1
2
3
1
2
2
1
1
2
6
1
2
5
4
3
1
2
A2 B2
C2
B1
A1
C1
A2 B2
C2
B1
A1
C1
8
6
3
5
9
7
1
2
4
21
21
2
1
2
1
2
1
121
121
121
117
121
15 19 26 43 65 80
120
119
35
117
35
117
19 40
120
35
117
35
106
35 48
35
106
35
117
35
106
6
35
47 48
122
35
117
35 117
102
102
35
106
6
35
6
15 35
35 48
6
15 35
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT OUT
IN
IN
IN
OUT
IN IN
OUT
OUT
OUT
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
OUT IN
OUT
IN
IN
OUT OUT
OUT OUT
BI BI
IN
IN IN IN OUT
OUT OUT
BI BI
IN
OUT OUT OUT
OUT OUT OUT
OUT
OUT
PETN_3
PETN_2
PETP_2
PETP_1 PETN_1
PETP_0 PETN_0
MONOBS_N
MONDC0 MONDC1
PERN_3
PERP_3
PERN_2
PERP_2
PERN_1
PERP_1
PERP_0 PERN_0
MONOBS_P
TMU_CLK_IN
TMU_CLK_OUT
DPSRC_3_P
DPSRC_2_P
DPSRC_3_N
DPSRC_1_P
DPSRC_2_N
DPSRC_1_N
DPSRC_0_P
DPSRC_AUX_P
DPSRC_0_N
DPSRC_HPD_OD
DPSRC_AUX_N
GPIO_2/GO2SX
GPIO_15
GPIO_9/OK2GO2SX_OD*
GPIO_14
GPIO_8/EN_CIO_PWR_OD*
GPIO_7/CIO_SCL_OD
GPIO_6/CIO_SDA_OD
GPIO_5/CIO_PLUG_EVENT
GPIO_4/WAKE_N_OD
GPIO_3
PB_CIO3_TX_N/DP_SRC_2_N
PB_CONFIG2/CIO_2_LSOE
PB_CIO2_RX_N
PB_CONFIG1/CIO_2_LSEO
PB_CIO2_RX_P
PB_CIO2_TX_P/DP_SRC_0_P PB_CIO2_TX_N/DP_SRC_0_N
PB_CIO3_TX_P/DP_SRC_2_P
PB_DPSRC_3_N
PB_DPSRC_1_N
PB_DPSRC_1_P
PB_LSRX/CIO_3_LSOE
PB_CIO3_RX_N
PB_LSTX/CIO_3_LSEO
PB_CIO3_RX_P
PB_DPSRC_3_P
GPIO_11/PB_CIO_SEL/BYP1
GPIO_13/PB_DP_PWRDN/BYP2
GPIO_1/PB_HV_EN/BYP0
PB_DPSRC_HPD
PB_AUX_N
PB_AUX_P
THERMDA
EE_DI EE_DO EE_CS_N
TDI
EE_CLK
TDO
DPSNK0_2_P
DPSNK0_3_N
DPSNK0_1_P
DPSNK0_2_N
DPSNK0_0_P
DPSNK0_1_N
DPSNK0_AUX_P
DPSNK0_0_N
DPSNK0_HPD
DPSNK0_AUX_N
DPSNK1_3_N
DPSNK1_3_P
DPSNK1_2_N
DPSNK1_2_P
DPSNK1_1_N
DPSNK1_1_P
DPSNK1_0_N
DPSNK1_0_P
DPSNK1_AUX_N
DPSNK1_AUX_P
DPSNK1_HPD
PA_CIO0_TX_N/DP_SRC_0_N
PA_CIO0_TX_P/DP_SRC_0_P
PA_CIO0_RX_N
PA_CIO0_RX_P
PA_CONFIG2/CIO_0_LSOE
PA_CONFIG1/CIO_0_LSEO
PA_CIO1_TX_N/DP_SRC_2_N
PA_CIO1_TX_P/DP_SRC_2_P
PA_CIO1_RX_N
PA_CIO1_RX_P
PA_LSRX/CIO_1_LSOE
PA_LSTX/CIO_1_LSEO
PA_DPSRC_1_N
PA_DPSRC_1_P
PA_DPSRC_3_N
PA_DPSRC_3_P
PA_AUX_P
PA_DPSRC_HPD
PA_AUX_N
GPIO_10/PA_CIO_SEL/BYP1
GPIO_0/PA_HV_EN/BYP0
GPIO_12/PA_DP_PWRDN/BYP2
PETP_3
RSENSE
REFCLK_100_IN_P REFCLK_100_IN_N
XTAL_25_IN
XTAL_25_OUT
TMS TCK
TEST_EN TEST_PWR_GOOD
DPSNK0_3_P
PWR_ON_POC_RSTN
PERST_N
NC
RBIAS
PCIE_RST_0_N PCIE_RST_1_N
PCIE_RST_3_N
PCIE_RST_2_N
PCIE_CLKREQ_OD_N
EN_LC_PWR
PCIE RESET
PCIE GEN2
MISC
(SYM 1 OF 2)
CLOCKS
JTAG/TEST PORT
RECEIVE
TRANSMIT
EEPROM
SINK PORT 0SINK PORT 1
SOURCE PORT 0
PORT3 PORT2
PORT0PORT1
DISPLAYPORT
PORTS
OUT
NC
IN
IN IN
OUT
IN
BI
IN
D
C
Q
S*
W*
HOLD*
PAD
VSS
THM
VCC
IN
OUT
OUT
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
NOTE: The following pins require testpoints:
5 - PCIE_RST_1_N
2 - GPIO_2
SNK0 AC Coupling
SNK1 AC Coupling
R3681 for CYA, allows separation of GPIO_2/GPIO_9 if necessary.
(FORCE_PWR)
(TBT_EN_CIO_PWR_L)
(TBT_SPI_MISO)
(TBT_SPI_CLK)
(TBT_SPI_CS_L)
Use AA8 GND ball for THERM_DN
(TBT_SPI_MOSI)
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
8 - GPIO_15 9 - GPIO_11 10 - GPIO_14 11 - GPIO_0 12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX
1 - GPIO_1
0 - GPIO_13
4 - GPIO_5
6 - PCIE_RST_2_N
Divides 3.3V to 1.8V
Stuff one of R3861/2.
DEBUG: For monitoring current/voltage
7 - PCIE_RST_3_N
3 - GPIO_3
Not used in host mode.
DEBUG: For monitoring clock
MF-LF
5%
1/16W
402
3.3K
R3690
90
111
90
111
402
MF-LF
1/16W
5%
0
R3625
MF-LF 402
1/16W
5%
100K
R3632
77
111
77
111
77
111
77
111
77
111
77
111
77
111
77
111
77
111
77
111
79
111
79
111
79
111
79
111
79
111
79
111
79
111
79
111
79
111
79
111
5% 1/16W MF-LF
402
100K
R3630
R3631
1/16W
402
100K
MF-LF
5%
77
111
77
111
1/16W 402
0
5%
MF-LF
R3629
1/16W MF-LF 402
5%
3.3K
R3693
0201
0.1UF
10% 16V
C3629
90
111
90
111
90
111
90
111
90
111
90
111
90
111
90
111
90
111
90
111
0201
0.1UF
16V10%
C3628
0201
0.1UF
10% 16V
C3627
0201
0.1UF
16V10%
C3626
0201
0.1UF
10% 16V
C3625
0201
0.1UF
16V10%
C3624
0201
0.1UF
10% 16V
C3623
0201
0.1UF
16V10%
C3622
201
1/20W MF
1K
1%
R3655
0201
10% X5R-CERM
0.1UF
16V
C3621
0201
0.1UF
10% 16V
C3620
0201
0.1UF
10% 16V
C3630
0201
0.1UF
10% 16V
C3631
0201
0.1UF
10% 16V
C3632
0201
0.1UF
10% 16V
C3633
0201
0.1UF
10% 16V
C3634
0201
0.1UF
10% 16V
C3635
0201
0.1UF
10% 16V
C3636
0201
0.1UF
10% 16V
C3637
0201
0.1UF
10% 16V
C3638
0201
0.1UF
10% 16V
C3639
90
111
90
111
90
111
90
111
90
111
90
111
90
111
90
111
6.3V
1UF
10%
CERM
402
C3690
90
111
90
111
77
111
77
111
79
111
79
111
38
79
111
79
111
79
111
79
111
79
111
79
111
79
117
15
119
15
119
15
103
15
119
77
111
77
111
77
111
77
111
77
117
36 77
122
77
36 77
36 79
122
79
36 79
38
122
19
FCBGA
OMIT_TABLE
CRITICAL
CACTUSRIDGE4C
U3600
38
26
105
1/16W MF-LF 402
10K
5%
R3698
402
806
1%
MF-LF
1/16W
R3695
MF-LF
1/16W
5%
402
1K
R3696
402
MF-LF
NO STUFF
1/16W
5%
10K
R3699
18
102
18
102
38
122
50
111
50
111
38
122
CRITICAL
MLP
M95256-RMC6XG
OMIT_TABLE
U3690
402
5% 1/16W MF-LF
100K
R3697
NONE
402
NONE
NOSTUFF
NONE
R3615
OMIT
402
MF-LF
1/16W
5%
10K
R3688
MF-LF 402
1/16W
5%
10K
R3687
5%
MF-LF 402
1/16W
10K
R3686
1/16W MF-LF
402
5%
10K
R3685
MF-LF 402
1/16W
5%
10K
R3680
NO STUFF
MF-LF 402
1/16W
5%
10K
R3682
15 26
122
36 76
122
10%
402
0.1UF
16V X5R
C3610
NO STUFF
MF-LF
402
1/16W
5%
47K
R3610
15
15 20
122
MF-LF
402
1/16W
5%
10K
R3683
MF-LF
0
5% 1/16W
402
R3681
15 21 36
0.1UF
16V10%
C3601
0201
0201
16V10%
0.1UF
C3600
0.1UF
16V
C3602
0201
10%
0201
0.1UF
16V10%
C3603
3.3K
5%
402
1/16W MF-LF
R3692
16V10%
C3604
0201
0.1UF
0201
0.1UF
10% 16V
C3605
0201
0.1UF
16V10%
C3606
0201
0.1UF
C3607
16V10%
16V
0201
10%
C3640
0.1UF
0201
0.1UF
C3641
10% 16V
0201
0.1UF
16V10%
C3642
1/16W
5% MF-LF
402
3.3K
R3691
0201
0.1UF
16V10%
C3643
0201
10%
0.1UF
C3645
16V
0201
16V10%
C3644
0.1UF
0201
0.1UF
10% 16V
C3646
10%
0.1UF
16V
0201
C3647
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
18
102
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
Thunderbolt Host (1 of 2)
TBT_A_D2R_P<0>
DP_TBTSNK0_ML_P<3>
DP_TBTSNK0_ML_C_N<2>
TP_DP_TBTSRC_ML_CN<1>
TP_DP_TBTSRC_ML_CP<0> TP_DP_TBTSRC_ML_CN<0>
TP_DP_TBTSRC_AUXCH_CN
DP_TBTSRC_HPD
TBT_GO2SX_BIDIR
DP_TBTSNK0_ML_N<0>
DP_TBTSNK1_ML_P<3>
TBT_CIO_PLUG_EVENT_ISOL
TBT_PWR_EN
TP_DP_TBTSRC_ML_CP<1>
TP_DP_TBTSRC_ML_CP<3>
SYSCLK_CLK25M_TBT_R
TP_TBT_MONDC0
TBT_MONOBSN
PCIE_TBT_R2D_N<0>
TBT_SPI_CLK
=TBT_WAKE_L
TP_DP_TBTSRC_AUXCH_CP
JTAG_TBT_TDI_ISOL
JTAG_TBT_TCK_ISOL
TBT_SPI_MOSI
JTAG_TBT_TMS_ISOL
DP_TBTSNK0_ML_N<3>
DP_TBTSNK0_ML_P<2> DP_TBTSNK0_ML_N<2>
TP_TBT_PCIE_RESET0_L TP_TBT_PCIE_RESET1_L TP_TBT_PCIE_RESET2_L
PCIE_TBT_R2D_N<3>
PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_P<1>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_R2D_N<1>
PCIE_TBT_R2D_P<0>
PCIE_TBT_R2D_C_P<0>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_R2D_P<3>
PCIE_TBT_D2R_P<3>
PCIE_TBT_D2R_C_P<3>
PCIE_TBT_D2R_C_N<3>
PCIE_TBT_D2R_C_N<2>
PCIE_TBT_D2R_N<2>
PCIE_TBT_D2R_C_P<1>
PCIE_TBT_D2R_C_N<1>
PCIE_TBT_D2R_C_P<0>
PCIE_TBT_D2R_N<0>
TBT_PWR_ON_POC_RST_L
PCIE_TBT_R2D_N<2>
PCIE_TBT_D2R_C_P<2>
TBT_PCIE_RESET_L
TBT_EN_LC_PWR
=TBT_CLKREQ_L
TBT_TMU_CLK_IN
TBT_TMU_CLK_OUT
SYSCLK_CLK25M_TBT
TBT_SPI_CS_L
DP_TBTSNK0_AUXCH_N
TP_DP_TBTSRC_ML_CN<3>
TBT_GPIO_9
TBT_DDC_XBAR_EN_L
=PP3V3_TBTLC_RTR
TBT_B_D2R_P<0>
DP_TBTPB_HPD
DP_TBTSNK0_ML_P<3>
TBT_SPI_MISO
=PP3V3_S4_TBT
=PP3V3_TBTLC_RTR
TBT_GPIO_14
=PP3V3_S4_TBT
DP_TBTSNK1_ML_N<0>
TBT_B_R2D_C_P<0>
TBT_A_HV_EN TBT_A_CIO_SEL TBT_A_DP_PWRDN
TBTROM_HOLD_L
TBTROM_WP_L
TP_TBT_MONDC1
TBT_A_CONFIG1_BUF
TP_TBT_PCIE_RESET3_L
PCIE_TBT_R2D_C_P<3>
DP_TBTSNK0_HPD
DP_TBTSNK1_ML_N<2>
DP_TBTSNK1_ML_P<2>
DP_TBTSNK0_ML_N<3>
DP_TBTSNK1_ML_N<0>
DP_TBTSNK1_ML_C_N<1>
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_ML_C_P<1>
DP_TBTSNK0_ML_C_N<1>
DP_TBTSNK1_ML_P<0>
I2C_TBTRTR_SCL
TP_TBT_XTAL25OUT
PCIE_TBT_R2D_C_N<3>
DP_TBTSNK1_AUXCH_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK1_ML_C_N<2>
TBT_B_LSRX
TBT_B_LSTX
DP_TBTPB_ML_C_N<3>
DP_TBTPB_AUXCH_C_P
TBT_A_D2R_N<0>
DP_TBTPA_ML_C_N<1>
DP_TBTSNK1_ML_N<1>
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_ML_N<1>
TBT_RSENSE
DP_TBTSNK1_AUXCH_N
DP_TBTSNK1_ML_P<0>
DP_TBTSNK1_ML_P<1>
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_ML_N<1>
DP_TBTSNK0_ML_P<0>
DP_TBTSNK0_ML_P<1>
TP_TBT_THERM_DP
TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>
TBT_A_CONFIG2_RC
TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>
TBT_A_D2R_P<1> TBT_A_D2R_N<1>
TBT_A_LSTX TBT_A_LSRX
DP_TBTPA_ML_C_P<1>
DP_TBTPA_ML_C_P<3>
DP_TBTSNK1_HPD
PCIE_TBT_D2R_P<1>
PCIE_TBT_D2R_P<2>
PCIE_TBT_D2R_N<3>
TP_DP_TBTSRC_ML_CN<2>
TP_DP_TBTSRC_ML_CP<2>
TBT_B_R2D_C_N<0>
TBT_B_D2R_N<0>
TBT_B_CONFIG2_RC
TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1>
TBT_B_D2R_P<1> TBT_B_D2R_N<1>
DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>
DP_TBTPB_ML_C_P<3>
DP_TBTPB_AUXCH_C_N
TBT_B_HV_EN TBT_B_CIO_SEL TBT_B_DP_PWRDN
DP_TBTSNK0_ML_C_P<0>
DP_TBTSNK0_ML_C_N<0>
DP_TBTSNK0_ML_C_P<2>
DP_TBTSNK0_ML_C_P<3>
DP_TBTSNK0_ML_C_N<3>
DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK1_ML_C_N<0>
DP_TBTSNK1_ML_C_P<1>
DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK1_ML_C_N<3>
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK0_ML_N<1>
DP_TBTSNK0_ML_N<0>
DP_TBTSNK0_ML_P<0>
DP_TBTSNK0_ML_N<2>
DP_TBTSNK0_ML_P<2>
DP_TBTSNK1_ML_P<1>
DP_TBTSNK1_ML_P<2>
DP_TBTSNK1_ML_P<3>
DP_TBTSNK1_ML_N<3>
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_ML_N<2>
TBT_B_CONFIG1_BUF
DP_TBTPA_HPD
DP_TBTPA_AUXCH_C_P
DP_TBTPA_ML_C_N<3>
DP_TBTPA_AUXCH_C_N
=PP3V3_TBTLC_RTR
PCIE_TBT_R2D_C_N<2>
PCIE_CLK100M_TBT_N
TBT_DDC_XBAR_EN_L
TBT_GPIO_9
I2C_TBTRTR_SDA
TBT_B_DP_PWRDN
TBT_A_DP_PWRDN
TBT_A_HV_EN TBT_B_HV_EN
TBT_GPIO_14
PCIE_CLK100M_TBT_P
TBT_PWR_REQ_L
DP_TBTSNK0_ML_P<1>
DP_TBTSNK1_ML_N<3>
TBT_GO2SX_BIDIR
PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_C_N<0>
PCIE_TBT_D2R_N<1>
TBT_RBIAS
TBT_MONOBSP
PCIE_TBT_R2D_C_N<0>
TBT_TEST_EN TBT_TEST_PWR_GOOD
JTAG_TBT_TDO_ISOL
TBT_EN_CIO_PWR_L
MAKE_BASE=TRUE
prefsb
051-9505
8.0.0
36 OF 144
36 OF 123
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
AD19
AD15
AD13
AD9
AD11
AD5
AD7
W16
AD23
AC24
AB19
AA18
AA16
AB15
AB13
AA12
AB9
AA10
W18
Y3
AA4
A14
A12
B15
A10
B13
B11
A8
C2
B9
V3
D3
Y1
V5
M5
T3
P3
AC2
AB1
AA2
J4
W2
U24
H5
N22
P1
R22
R24
N24
W24
B23
B21
A20
G6
U22
L6
W22
A22
L2 L4
M1
K3
E2
D1
Y7
R4
P5
AD3
V1
W4
R2
E16
D13
E18
D15
E20
D17
A6
D19
U6
B5
D5
E6
D7
E8
D9
E10
D11
E12
B3
A4
T5
E24
G24
E22
G22
G4
K1
J24
L24
J22
L22
J6
N2
B17
A16
B19
A18
F3
H1
F1
M3
G2
H3
AD17
U20
AB21 AD21
AA24
AB23
AB3
AA6
N4
AB5
E14
J2
R6
U4
W20
N6 T1
U2
Y5
W6
K5
1
2
1 2
121
2
94
5
6
2
1
3
7
8
1
2
1
2
121
2
121
2
1
2
1
2
2
1
1
2
1
2
1
2
1 2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
1 2
1 2
36
111
75
75
75
75
75
111
36
111
36
111
75
75
105
102
111
75
111
36
111
36
111
36
111
102
102
102
102
102
102
102
102
102
102
102
102
102 102
111
36
111
75
36
36 76
122
6
15 36 37 38 50
36
111
111
6
36 37 38 77 79
6
15 36 37 38 50
36
6
36 37 38 77 79
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
75
75
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
6
15 36 37 38 50
36
36 79
36 77
36 77
122
36 79
122
36
36
111
36
111
15 21 36
102
VSSPE VSSPE
VSSPE VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE VSSPE
VSSPE VSSPE VSSPE
VSSPE VSSPE
VSS VSS
VSS VSS
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VSS VSS
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VCC1P0_DPAUX
VCC1P0_DPAUX
VCC3P3_POC
VSSPE
VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE
VCC1P0 VCC1P0
VCC3P3_DP VCC3P3_DP
VCC3P3_DP
VCC3P3_CIO
VCC3P3_CIO
VCC3P3_CIO
VCC3P3
VCC3P3
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0 VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC3P3
VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE
VSSPE
VSSPE
VSSPE VSSPE VSSPE VSSPE
VSSPE
VSSPE
VSSPE VSSPE VSSPE
VSSPE
VSSPE
VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE
VSSPE
VSSPE
VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE
VSSPE
VSSPE
VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE
VSSPE
VSSPE
VCC3P3_DP
VCC3P3_DPAUX
(SYM 2 OF 2)
VCCGND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
EDP current / power consumption figures from CR DG v0.57, IBL doc #472455.
EDP: 1000 mA
250 mW (Dual Port)
??? mW (Single Port)
???? mW (Single-Port) 2700 mW (Dual-Port) EDP: 3000 mA
250 mW (Dual-Port) EDP: 240 mA
??? mW (Single-Port)
EDP: 10 mA
20%
0201
X5R
1UF
6.3V
C3745
20%
0201
X5R
1UF
6.3V
C3716
0402-1
CERM-X5R
10UF
20%
6.3V
C3705
20%
0201
X5R
1UF
6.3V
C3773
20%
0201
X5R
1UF
6.3V
C3774
20%
0201
X5R
6.3V
1UF
C3717
20%
0201
X5R
6.3V
1UF
C3713
0402-1
CERM-X5R
20%
6.3V
10UF
C3700
0402-1
CERM-X5R
10UF
6.3V
20%
C3701
20%
0201
X5R
1UF
6.3V
C3714
20%
0201
X5R
6.3V
1UF
C3715
OMIT_TABLE
CACTUSRIDGE4C
FCBGA
CRITICAL
U3600
0402-1
CERM-X5R
6.3V
10UF
20%
C3760
20%
0201
X5R
1UF
6.3V
C3772
20%
0201
X5R
6.3V
1UF
C3771
20%
0201
X5R
6.3V
1UF
C3710
20%
0201
X5R
6.3V
1UF
C3770
20%
0201
X5R
1UF
6.3V
C3790
20%
0201
X5R
1UF
6.3V
C3711
20%
0201
X5R
1UF
6.3V
C3712
20%
0201
X5R
6.3V
1UF
C3744
20%
0201
X5R
6.3V
1UF
C3743
20%
0201
X5R
6.3V
1UF
C3742
20%
0201
X5R
1UF
6.3V
C3741
20%
0201
X5R
6.3V
1UF
C3740
Thunderbolt Host (2 of 2)
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
=PP3V3_S4_TBT
=PP1V05_TBTCIO_RTR
=PP1V05_TBTLC_RTR
=PP3V3_TBTLC_RTR
prefsb
051-9505
8.0.0
37 OF 144 37 OF 123
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
212
1
2
1
C18
C20
C14
C16
C12
C10
B7
B1
AC8
AC6
AC4
AC22
AC18 AC20
AC16
AC14
AC12
AB7
AB17
AC10
AA8
AB11
AA14 AA20
AA22
A2
A24
U8
V9
U12
U16
T9
T13
T17
R8
R16
R12
P9
P17
P13
N16
N8
M9
N12
M17
L8
M13
L16
L12
K13
AD1
K9
H9
G8
K7
Y9
G10
G12
G14 G16
H19
G18
K19
M19 P19
T19
V15 V19
W12
W14
K11 K15
H13 H15
H11
R18
N18
L18
P7
M7
W10
V11
U10
T11
R14
R10
P15
N14
P11
N10
M15
M11
L14
L10
W8
T15
V7
U14
K17
J8
J16
J14
J12
J10
T7
C22 C24
C4
C6 C8
D21
E4
D23
F11 F13
F15
F17
F21
F19
F23 F5
F7
G20
F9
H21 H23
J18
J20 K21
K23
L20
M23
M21
N20
P21
P23 R20
T21
T23 U18
V17
V13
V21
V23 Y11
Y13
Y15 Y17
Y19
Y23
Y21
H17
H7
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
36 38 77 79
6
6
6
15 36 38 50
GND
VOUT
ON
VIN
OUT
IN
IN
RESET*
OUT
EN
MR*
GND
THRM
IN
VDD
SENSE
+
-
PAD
(OD)
0.7V
DLY
VOUT
GND
ON
VIN
GND
VOUT
ON
VIN
SENSE
THRM
RESET*
CT
GND
MR*
VDD
PAD
OUT
IN
D
SG
IN
D
S G
OUT
D
GS
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM options provided by this page:
- =TBT_CLKREQ_L
Signal aliases required by this page:
- =PP1V05_TBT_FET (1.05V FET Output)
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)
- =PP3V3_S0_TBTPWRCTL
- =PP3V3_TBT_FET (3.3V FET Output)
- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)
DLY = 60 ms +/- 20%
1.05V TBT "CIO" Switch
Delay = 27.3ms
TPS3808G25
(IPU)
Max Current = 4A (85C)
Vt = 2.33V +/- 2%
Pull-up: R3610
@ 1.05V
R(on)
Type
Part
Load Switch
11.5 mOhm Max
8 mOhm Typ
U3820
TPS22920
- =PPVIN_SW_TBTBST (8-13V Boost Input)
TBTBST:Y - Stuffs 15V boost circuitry.
- =PP15V_TBT_REG (15V Boost Output)
Power aliases required by this page:
- =TBT_RESET_L
Page Notes
Intel investigating whether RC is sufficient.
TBT "POC" Power-up Reset
Supervisor & CLKREQ# Isolation
Platform(PCIe) Reset
TPS22924C
18.5 mOhm Typ
Load Switch
U3810
25.8 mOhm Max
3.3V TBT "LC" Switch
Part
R(on) @ 2.5V
Type
Max Current = 2A (85C)
20.3 mOhm Typ
28.6 mOhm Max
Load Switch
TPS22924C
U3815
@ 1.0V
R(on)
Part
Type
Max Current = 2A (85C)
1.05V TBT "LC" Switch
Pull-up provided by SB page.
U3810
TPS22924
CSP
CRITICAL
36
402
10%
0.1UF
X5R
25V
C3800
26
36
C3810
6.3V CERM
10%
1UF
402
402
CERM
6.3V
10%
C3815
1UF
CRITICAL
SLG4AP016V
TDFN
U3800
R3807
1/16W
5%
100K
MF-LF 402
1UF
402
CERM
6.3V
10%
C3816
NOSTUFF
R3816
1/16W MF-LF
402
0
5%
TPS22920
CRITICAL
CSP
U3820
TPS22924
CRITICAL
CSP
U3815
1UF
10%
6.3V CERM
402
C3820
TPS3808
QFN
CRITICAL
U3830
402
25V X5R
10%
0.1UF
C3830
36
122
0402
10% 25V
0.0047UF
CERM
C3831
21
122
SSM6N37FEAPE
SOT563
Q3825
36
122
100K
MF-LF
1/16W
402
5%
R3820
SOT563
SSM6N37FEAPE
Q3825
5%
402
1/16W MF-LF
100K
R3830
15
122
SSM3K15AMFVAPE
VESM
Q3840
36
122
1/16W
R3840
10K
402
5%
MF-LF
C3825
330PF
50V
10%
X7R-CERM
0402
47 48 65
122
402
C3811
10%
6.3V CERM
1UF
MF-LF
1/16W
R3811
36.5K
1%
402
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
Thunderbolt Power Support
=PP1V05_S0_P1V05TBTFET
=TBT_RESET_L
=PP3V3_S0_P3V3TBTFET
TBT_EN_LC_RC1V05
=PP1V05_TBTLC_FET
=TBT_CLKREQ_L
TBT_EN_LC_RC3V3
=PP3V3_TBTLC_FET
MAKE_BASE=TRUE
TBT_CLKREQ_ISOL_L
TBT_CLKREQ_L
=PP3V3_S0_TBTPWRCTL
TBT_EN_LC_PWR
SMC_DELAYED_PWRGD
=PP3V3_S0_PCH_GPIO
TBTPOCRST_MR_L
=PP3V3_TBTLC_RTR
=PP3V3_TBTLC_RTR
=PP3V3_S4_TBT
=PP1V05_S0_P1V05TBTFET
TBT_PWR_ON_POC_RST_L
TBTPOCRST_CT
TBT_EN_CIO_PWR
TBT_EN_CIO_PWR_L
TBT_PCIE_RESET_L
PP1V05_TBTLC
TBT_SW_RESET_L
=PP1V05_TBTCIO_FET
TBT_EN_LC_ISOL
38 OF 123
38 OF 144
8.0.0
051-9505
prefsb
C1
A1
B1
C2
B2
A2
2
1
2
1
2
1
4
8
6
3
5
9
7
1
2
1
2
2
1
1 2
A1
D1
D2
A2
B2 C2
B1 C1
C1
A1 B1
C2
B2
A2
2
1
2
7
6
3
5
4
1
2
1
2
1
6
1
2
1
2
3
4
5
1
2
1
2
3
1
2
2
1
2
1
1 2
6
38
6
6
6
122
6
6
15 19 20
6
15 36 37 38 50
6
15 36 37 38 50
6
36 37 77 79
6
38
122
6
108
6
122
IN
IN
OUT
IN
OUT
OUT
IN
IN
BI
BI BI
BI BI BI BI BI
BI
BI BI
OUT
IN
IN
IN
OUT
VDDC
SR_LX
PCIE_PLLVDDL
SR_VFB
SR_VDDP
SR_VDD
SCLK SI/LINKLED*
CS*
SO
SPD100LED*/SERIAL_DO TRAFFICLED*/SERIAL_DI
TRD0_P
TRD1_P
TRD0_N
TRD1_N
TRD2_N
TRD2_P
TRD3_N
TRD3_P
GPIO_1/CR_BUS_PWR
GPIO_0
RE*/GPIO_2
VMAIN_PRSNT
PCIE_TXD_N PCIE_TXD_P
PCIE_RXD_N
PCIE_RXD_P
PCIE_REFCLK_N
PCIE_REFCLK_P
PERST*
CLKREQ*
WAKE*
LOW_PWR
SD_DETECT/WE*
CR_CMD/CLE
CR_CLK/RY_BY*
CR_DATA0 CR_DATA1
CR_DATA3
CR_DATA2
CR_DATA4 CR_DATA5 CR_DATA6
CE*/MS_INS*
CR_DATA7
CR_LED/ALE
XD_DETECT
THRM_PAD
XTALI XTALO
RDAC
GPHY_PLLVDDL
AVDDH
VDDO
XTALVDDH
BIASVDDH
AVDDL
SMD_DATA
SMB_CLK
CR_WP*/XD_WP*
OUT
IN
IN
OUT
IN
OUT
BI
BI BI
IN
BI
BI
BI
BI BI
NC
RESET*
CS*
SCK
SO
WP*
SI
GND
VCC
IN
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
VDD for Card Reader I/O
Special Star routing needed on these pins. Decoupling on Pg 37.
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
(IPx-ENET)
(IPU-ENET)
Connect only to U3900 pin 20.
No MS (Memory Stick) Insert feature needed. Control signal to light LED or control SD bus power.
ENET supports both active-levels for WP.
(OD)
IF ENET SWITCHING REGULATOR IS USED, THIS PIN SHOULD HAVE A 1K PD TO GND
(IPD-ENET)
(IPU)
SD_DETECT can only be used active low due to errata.
281mA (1000base-T max power, Caesar IV)
(OD)
(OD)
(IPU-ENET)
(OD)
o
PHY Non-Volatile Memory
NOTE: Pull-down on SO plus internal pull-ups on
=ENET_WAKE_L to PCIE_WAKE_L.
info as well as code for Bonjour proxy.
(Required ROM size 1 Mbit)
Avoids need for EFI to program at startup.
is powered-down in S3/S5. Standard
Must isolate from PCIe WAKE# if PHY
WAKE#
If PHY is always powered then alias
Resistor
Limiting
396mA (1000base-T, Caesar II)
(IPD)
N-channel FET isolation suggested.
(See note)
(IPD-ENETM)
Current
(IPD)
(IPD)
Internal 1.2V Switching Regulator pins.
ROM contains MAC address, PCIe config
other 3 SPI pins configures ENET for the
ROM is used then the straps must change. NOTE: ENETM requires SI pull-down instead of SO.
Atmel AT45DB011D (1Mbit) ROM. If a different
NOTE: "IPx" == Programmable pull-up/down
(IPU-ENET)
the card reader on-chip I/O.
LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
(NO IPU OR IPD-ENET)
(IPU-ENET)
(IPU-ENET)
ENET_SR_DISABLE
ENET_CR Signals
BCM requests SD CR[0:7], CMD, CLK termination.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
20%
C3935
603
X5R
6.3V
C3925
402
20%
6.3V X5R-CERM1
4.7UF
SM
L3925
CRITICAL
FERR-600-OHM-0.5A
C3920
20%
6.3V X5R-CERM1
4.7UF
402
5% MF-LF
402
1K
1/16W
R3942
18
102
18
102
40
26 41
118
402
1% 1/16W
R3965
MF-LF
1.24K
18
102
18
102
18
102
18
102
40
116
40
116
40
116
40
116
40
116
40
116
40
116
40
116
1/16W
5%
R3941
MF-LF 402
1/16W MF-LF
5%
402
R3940
41
116
41
116
41
116
41
116
41
116
NOSTUFF
402
5% 1/16W
R3990
MF-LF
41
116
41
116
15 18
116
1/16W
5%
402
MF-LF
R3910
OMIT_TABLE
BCM57765
QFN-8X8
U3900
40
39
116
39
116
39
116
39
116
41
118
39
116
39
116
39
116
39
116
41
116
41
116
41
116
41
116
41
116
1/16W
402
MF-LF
R3981
5%
1K
U3990
OMIT_TABLE
AT45DB011D
SOIC-8S1
41
118
26
105
33
1/20W
MF5% 201
PLACE_NEAR=U3900.26:5MM
R3961
0.1UF
10% 16V
X5R-CERM
0201
C3905
X5R-CERM
0.1UF
C3910
0201
10% 16V
X5R-CERM
10% 16V
0201
C3911
0.1UF
10% X5R-CERM
0201
16V
C3916
0.1UF
C3921
16V
10%
0.1UF
0201
X5R-CERM
0201
X5R-CERM
0.1UF
10% 16V
C3926
0201
C3931
0.1UF
10% 16V
X5R-CERM
X5R-CERM
0201
16V
10%
0.1UF
C3936
16V
10%
0201
X5R-CERM
0.1UF
C3950
10%
X5R-CERM
16V
0201
C3951
0.1UF
X5R-CERM
0.1UF
16V
10%
0201
C3955
16V
X5R-CERM
0201
10%
0.1UF
C3956
0201
10% 16V
0.1UF
C3990
X5R-CERM
R3979
33
1/20W
MF5% 201
PLACE_NEAR=U3900.21:5MM
R3971
33
MF5%
1/20W
201
PLACE_NEAR=U3900.25:5MM
R3972
33
1/20W
MF 2015%
PLACE_NEAR=U3900.24:5MM
R3973
33
MF 201
1/20W
5%
PLACE_NEAR=U3900.23:5MM
R3974
33
MF5%
1/20W
201
PLACE_NEAR=U3900.22:5MM
5% MF
1/20W
201
33
R3975
PLACE_NEAR=U3900.52:5MM
201
33
MF
1/20W
R3976
5%
PLACE_NEAR=U3900.53:5MM
R3977
MF
1/20W
33
2015%
PLACE_NEAR=U3900.54:5MM
MF
33
5% 201
1/20W
PLACE_NEAR=U3900.55:5MM
R3978
0402
L3900
CRITICAL
FERR-600-OHM-300MA-0.85OHM
FERR-600-OHM-300MA-0.85OHM
L3905
CRITICAL
0402
CRITICAL
0402
L3910
FERR-600-OHM-300MA-0.85OHM
0402
L3920
CRITICAL
FERR-600-OHM-300MA-0.85OHM
L3930
CRITICAL
0402
FERR-600-OHM-300MA-0.85OHM
16V
0.1UF
C3996
10%
0201
X5R-CERM X5R-CERM
10%
0201
C3997
0.1UF
16V
X5R-CERM
C3998
0201
0.1UF
16V
10%
16V
10%
0.1UF
0201
X5R-CERM
C3999
MF-LF
5%
R3901
0
1/16W
402
6.3V
20%
402
4.7UF
X5R-CERM1
C3979
0201
6.3V
10% X5R-CERM
1.0UF
C3912
X5R-CERM
6.3V
1.0UF
10%
C3913
0201
40
118
0201
16V
X5R-CERM
0.1UF
10%
C3900
4.7UF
6.3V
20% X5R-CERM1
402
C3930
6.3V
20%
402
4.7UF
X5R-CERM1
C3915
5%
402
MF-LF
1/16W
R3997
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
ETHERNET PHY (CAESAR IV+)
PCIE_ENET_D2R_C_P
PCIE_ENET_R2D_N
PCIE_CLK100M_ENET_N ENET_RESET_L ENET_CLKREQ_L_Q
ENET_MOSI
ENET_MISO
ENETCONN_MDI_N<0>
ENETCONN_MDI_P<2>
ENETCONN_MDI_P<1>
=PP3V3R1V8_CR_IOPWR_OUT
ENET_CR_DATA<4>
=ENET_WAKE_L
ENET_LOW_PWR
SDCONN_DATA<7>
PCIE_ENET_D2R_P
=PP3V3_S0_ENET
PCIE_ENET_D2R_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
ENET_SR_VFB
ENET_CS_L
PCIE_ENET_D2R_C_N
ENET_SR_LX
ENET_CR_PWREN
PCIE_ENET_R2D_P
ENET_VMAIN_PRSNT
ENET_CR_DATA<3>
ENET_SR_DISABLE
ENET_CR_DATA<7>
ENETCONN_MDI_P<3>
ENETCONN_MDI_N<1>
=PP3V3_S4_ENET_FET
ENET_CS_L
ENET_SCLK
ENET_MISO
ENET_SCLK
SMB_ENET_SDA
SMB_ENET_SCL
PCIE_CLK100M_ENET_P
=PP3V3_S4_ENET_FET
ENET_MOSI
PP3V3_S4_ENET_FET_AVDDH
MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
PP1V2_S4_ENET_PHY_GPHYPLL
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 MM
NO_TEST=TRUE
NC_ENET_CE_L_MS_INS_L
SDCONN_WP
SDCONN_CLK
SDCONN_CMD
SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6>
ENET_CR_DATA<1>
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP3V3_S4_ENET_FET_BIASVDDH
PP1V2_S4_ENET_PHY_AVDDL
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.2V
PP1V2_S4_ENET_PHY_PCIEPLL
ENETCONN_MDI_N<3>
VOLTAGE=3.3V
PP3V3_S4_ENET_FET_SRVDD
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm
PP3V3_S4_ENET_FET_XTALVDDH
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
ENET_SD_DETECT_L
=PP3V3R1V8_CR_IOPWR_OUT
=PP1V2_S4_ENET_PHY
ENETCONN_MDI_N<2>
SYSCLK_CLK25M_ENET
TP_ENET_CR_3V3_EN_L ENET_TRAFFICLED_L
ENET_RDAC
ENET_CR_DATA<6>
ENET_CR_DATA<5>
ENET_CR_DATA<2>
ENET_CR_DATA<0>
ENET_SD_CLK
ENET_SD_CMD
ENET_MEDIA_SENSE
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PP3V3R1V8_ENET_LR_OUT_REG
TP_ENET_CR_1V8_EN
ENETCONN_MDI_P<0>
39 OF 144
prefsb
051-9505
8.0.0
39 OF 123
2
1
2
1
21
2
1
1
2
1
2
121
2
1
2
1
2
62
35
16
29
51
45
13
15
14
66 64
63
65
2
67
40
44
41
43
47
46
49
50
8
5
9
58
27 28
34
33
30
31
11
12
3
4
1
26
21
25 24
22
23
52 53 54
59
55
60
68
69
18 19
38
61
36
32
48
42
20567
17
37
39
10
6
57
1 2
7
6
3
4
2
8
5
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
1 2
1 2
1 2
2
1
1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
21
21
21
21
21
2
1
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
1
2
102
102
39 40
116
6
40
102
40
118
102
116
118
116
6
39 40
6
39 40
121
120
116
121
120
120
121
121
39 40
40
116
116
116
116
116
116
116
120
BI
BI
BI
BI BI
BI
G
DS
IN
G
D
S
G
D
S
IN
D
GS
NBC
BI
BI
D
GS
OUT
BI
TX
RX
TX
RX
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
ENET_MDI_TRAN2+
ENET_MDI_TRAN1+
ENET_MDI_TRAN3-
SHIELD
ENET_MDI_TRAN0-
ENET_MDI_TRAN0+
ENET_MDI_TRAN2-
ENET_MDI_TRAN1-
ENET_MDI_TRAN3+
ENET_MDI
PINS
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CAESAR IV 1.2V INT.VR CMPTS
157S0058
SILKSCREEN:ENET ACT
CAESAR IV WAKE# ISOLATION
"ENET" = "S0" || ("S&& "WOL_EN")
CAESAR IV ACTIVITY LED
Power decoupling
3.3V ENET FET
ENET Enable Generation
Feedback loop
40
116
40
116
40
116
40
116
40
116
40
116
CRITICAL
Q4020
NTR4101P
SOT-23-HF
0.033UF
C4020
402
X5R
16V
10%
1/16W
5%
MF-LF
402
100K
R4021
MF-LF
402
R4020
1/16W
5%
10K
15 21
123
SOT-363
CRITICAL
2N7002DW-X-G
Q4021
2N7002DW-X-G
SOT-363
Q4021
5
15 19 28 47 48 64
120
X5R-CERM1 402
C4010
6.3V
20%
4.7UF
1/16W
10K
R4070
402
5% MF-LF
CRITICAL
SOD-VESM-HF
SSM3K15FV
Q4070
DEVELOPMENT
330
5% 1/16W MF-LF 402
R4050
LED4050
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
PCAA031B-SM
4.7UH-0.8A
CRITICAL
L4010
C4012
6.3V
X5R 603
20%
40
116
40
116
R4003
MF-LF
5%
75
402
1/16W
R4002
1/16W
75
MF-LF
5%
402
R4001
1/16W MF-LF 402
5%
7575
R4000
MF-LF
1/16W
5%
402
NOSTUFF
C4000
10% 2KV CERM
1000PF
1206
402
10V
20% CERM
0.1UF
C4004C4003
10V CERM
20%
402
0.1UF
CERM
0.1UF
20%
402
10V
C4002C4001
CERM
10V
20%
0.1UF
402
16V
C4014
0.1UF
0201
10% X5R-CERM
C4015
16V 0201
X5R-CERM
10%
0.1UF
X5R-CERM 0201
C4016
16V
10%
0.1UF 0.1UF
10% 16V
C4017
X5R-CERM 0201
C4018
0.1UF
10% 0201
16V X5R-CERM
0201
C4019
16V
0.1UF
10% X5R-CERM
1/16W
R4071
10K
402
5% MF-LF
CRITICAL
Q4071
SSM3K15FV
SOD-VESM-HF
15 18
118
40
116
T4000
SM
LFE8904CF
LFE8904CF
SM
T4010
39
116
39
116
40
116
40
116
40
116
40
116
40
116
40
116
39
116
39
116
39
116
39
116
39
116
39
116
X5R-CERM 0201
10% 16V
0.1UF
C4024
X5R-CERM
10% 0201
C4023
0.1UF
16V
C4022
402
X5R-CERM1
4.7UF
20%
6.3V
C4021
0.01UF
10% 50V
X7R-CERM
0402
CRITICAL
J4000
RCPT-RJ45-D8
F-ANG-TH
40
116
6.3V
20% X5R-CERM1
402
4.7UF
C4025
NOSTUFF
C4011
0.1UF
10% 16V X7R-CERM 0402
SYNC_DATE=08/27/2012
Ethernet Support & Connector
SYNC_MASTER=D8_MLB
=PP3V3_S4_ENET_FET
ENETCONN_MDI_N<1>
=PP3V3R1V8_CR_IOPWR_OUT
ENETCONN_MDI_T_P<0>
ESD_HOT=TRUE
ENETCONN_MDI_T_N<1>
ESD_HOT=TRUE
ENETCONN_MDI_T_P<2>
ESD_HOT=TRUE
ESD_HOT=TRUE
ENETCONN_MDI_T_N<0>
ENETCONN_MDI_T_P<1>
ESD_HOT=TRUE
ENETCONN_MDI_T_N<2>
ESD_HOT=TRUE
ENETCONN_MDI_T_P<3>
ESD_HOT=TRUE
ENETCONN_MDI_T_N<3>
ESD_HOT=TRUE
ENETCONN_MDI_T_N<0>
ENETCONN_MDI_N<2>
ENETCONN_MCT0
ENET_PWR_EN_L_R
PP3V3_S4_ENET_FET
=PP3V3_S4_ENET
ENETCONN_MDI_T_P<0>
=PP1V2_S4_ENET_PHY
ENET_PWR_EN_L
ENETCONN_MDI_P<1>
ENETCONN_MDI_T_P<3>
ENET_TRAFFICLED_L
=PP3V3_S4_ENET_FET
PM_SLP_S3_L
WOL_EN
ENET_CLKREQ_L
PCIE_WAKE_L
=ENET_WAKE_L
ENET_CLKREQ_L_Q
=PP3V3_S4_ENET_FET
ENETCONN_MDI_P<0>
ENETCONN_MDI_N<3>
ENETCONN_MDI_P<3>
ENETCONN_MCT2
ENETCONN_MDI_T_N<1>
ENETCONN_MDI_T_P<1>
ENETCONN_MDI_T_P<2>
ENETCONN_MDI_T_N<2>
ENET_ACT
=PP3V3_S4_ENET_FET
ENETCONN_MCT3
ENET_SR_VFB
ENETCONN_MDI_T_N<3>
ENETCONN_MCT1
MIN_NECK_WIDTH=0.2 mm
ENETCONN_MCT_BS
MIN_LINE_WIDTH=0.4 MM
DIDT=TRUE
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MM
ENET_SR_LX
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6MM
ENET_WAKE_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP1V2_ENET_INTREG
MAKE_BASE=TRUE
VOLTAGE=1.2V
PP1V2_ENET_INTREG
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
ENETCONN_MDI_P<2>
ENETCONN_MDI_N<0>
ENETCONN_TCT
prefsb
051-9505
8.0.0
40 OF 144 40 OF 123
32
1
2
1
1 2
1
2
6
2
1
3
5
4
2
1
1
2
1
2
3
1
2
K
A
21
2
1
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
3
10
6
5
7
8
9
11
12
4
3
2
1
10
6
5
7
8
9
11
12
4
3
2
1
2
1
2
1
2
1
12
4 3
8
9
2 1
10 11 12 13 14
5
6
7
2
1
2
1
6
39 40
39
116
118
6 6
39
118
39
6
39 40
19 35
120
39
39
118
6
39 40
116
118
6
39 40
116
39
116
39
118
118
40
120
40
120
118
OUT
OUT
OUT
IN
IN
LOW_PWR
GND
THRM
VDD
RST_OUT*
DET_OUT
DET_CHNGD*
DET_LVL
DET_IN
RST_IN*
DET_CH_EN*
DLY
RST
LOGIC
XOR
(IPU)
XOR
(OD)
(OD)
PAD
THRML
OUT
GND
FAULT*
ILIM
EN
IN
PAD
BI BI BI BI
OUT
IN
OUT
BI
BI
BI
BI
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
CRD_DETECT_SWITCH
SHLD_PIN
SHLD_PIN
SHLD_PIN
DAT6
DAT5
DAT7
DAT2
DAT1
DAT0
DAT4
VSS
CMD
CLK
VDD
VSS
CD/DAT3
WRITE_PROTECT_SWITCH
SHLD_PIN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
512-0038
DLY block is 20ms nominal
regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#
FROM SD CONN ->
SD CARD 3.3V OVERCURRENT PROTECTION
-> TO ENET CHIP
-> TO PCH GPIO
When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms
SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.
39
118
5%
0
MF-LF
1/16W
402
R4114
15 20
103
39
116
1UF
10% 10V X5R
402-1
C4110
26 39
118
R4110
10K
NOSTUFF
5%
402
MF-LF
1/16W
R4111
0
1/16W MF-LF
402
5%
26
118
NOSTUFF
402
1/16W MF-LF
0
5%
R4112
TDFN
SLG4AP026V
U4111
CRITICAL
TPS2553
U4100
SON
6.3V
20%
603
X5R
C4102
1/16W MF-LF 402
R4100
47K
5%
5%
MF-LF
1/16W
R4101
402
0
R4108
402
5%
1/16WMF-LF
1/16W
402
5%
MF-LF
0
R4116
0
5%
MF-LF
R4109
402
1/16W
0
MF-LF
5%
402
1/16W
R4117
39
116
39
116
39
116
39
116
39
116
50V 402
CERM
5%
C4170
NOSTUFF
5%
402
0
1/16WMF-LF
R4107
5%
R4105
0
402
MF-LF 1/16W
MF-LF
0
R4104
5%
1/16W
402
0
402
MF-LF5%1/16W
R4106
5%
0
R4103
1/16W
402
MF-LF
39
116
39
116
39
116
39
116
39
116
39
116
201
10K
5% 1/20W MF
R4115
0603
C4100
X5R
20%
6.3V
0402
C4101
16V X7R-CERM
0.1UF
10%
0402
16V X7R-CERM
0.1UF
10%
C4103
5%
CERM
50V
C4171
NOSTUFF
0402
47NH-1.3OHM
L4102
0402
SD-CARD-D8
J4100
F-ANG-TH1
R4113
402
13K
1% 1/16W MF-LF
R4118
13K
1% 1/16W MF-LF 402
SYNC_MASTER=D8_MLB
SD READER CONNECTOR
SYNC_DATE=08/27/2012
=PP3V3_S0_SW_SD_PWR
SDCONN_DETECT
ESD_HOT=TRUE
SDCONN_DATA_R<6>
SDCONN_DATA_R<5>
ESD_HOT=TRUE
SDCONN_DATA_R<7>
ESD_HOT=TRUE
SDCONN_DATA_R<2>
ESD_HOT=TRUE
SDCONN_DATA_R<1>
ESD_HOT=TRUE
SDCONN_DATA_R<0>
ESD_HOT=TRUE
SDCONN_DATA_R<4>
ESD_HOT=TRUE
SDCONN_CMD_R
ESD_HOT=TRUE
SDCONN_CLK_R
ESD_HOT=TRUE
SDCONN_WP
SDCONN_CMD
SDCONN_DATA<3>
SDCONN_DATA<6>
SDCONN_CLK
SDCONN_DATA<0>
SDCONN_DATA<4>
SDCONN_DATA<7>
SDCONN_DATA<2>
SDCONN_DATA<1>
SLG_ENET_RESET_R_L
=PP3V3_S0_SDCARD
ENET_SD_RESET_L
SDCONN_DATA<5>
ENET_LOW_PWR
=PP3V3_S0_SW_SD_PWR
=PP3V3_S0_SDCARD
ENET_SD_DETECT_L
SDCONN_STATE_CHANGE
SDCONN_DETECT
=PP3V3_S5_SDCARD
SD_DETECT_LVL
SLG_ENET_RESET_L
ENET_CR_PWREN
ENET_RESET_L
ESD_HOT=TRUE
SDCONN_DATA_R<3>
SDCONN_ILIM
SDCONN_OC_L
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S0_SW_SD_PWR
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm
SDCONN_ILIM_R
prefsb
051-9505
8.0.0
41 OF 144 41 OF 123
1 2
2
1
1
2
1 2
1 2
2
5
11
10
4
8
9
1
7
3
6
715
3
2
4
6
2
1
1
2
1
2
1 2
1 2
1 2
1 2
2
1
1 2
1 2
1 2
1 2
1 2
1
2
2
1
2
1
2
1
2
1
21
27
26
25
24
22
21
20
23
14
19
18
17
12
11
13
9
8
7
10
6
2
5
4
3
1
15
16
1
2
1
2
41
41
121
116
116
116
116
116
116
116
116
116
121
6
41
41
6
41
41
121
6
121
121
39
118
116
121
121
121
NC
NC
HOLD*
SCLK
WP*
CS*
VCC
THRM
GND
SO/SIO1
SI/SIO0
PAD
OVDD2
OVDD1
USB_VDDA0
MAVSS
DVSS6
DVSS4
USB_VSSA0
GPIO0 GPIO1 GPIO3 GPIO9
MRXDATAINP
MRXCLKINP MRXCLKINN
CLKIN
MRXDATAINN
SF_DOUT
SF_DIN
CS_PWDB
SF_CLK
MIPI_RESISTOR
USB_VSDL0
OVSS2
CS_SCK
USB_PADM
USB_PADP
LED_FIXED
CS_SDA
SF_CS*
VSSA_PLL
DVDD4
DVDD6
VDDA_PLL
CS_CLK
CS_RSTB
TEST
USB_VRES
RST*
UART1_RX UART1_TX
THRM
SF_WP*
OVSS1
DVSS3
USB_VDDL0
CLKOUT
NC
MAVDD33
DVDD3
PAD
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPIO3 CAN BE CONFIGED AS GENERAL
USB CAMERA CONTROLLER
SERIAL FLASH
STITCH THERMAL PAD TO INNER GROUND
335S0852
UART1_TX IS STRAP FOR SELECTION
SPI CLOCK DURING POWER-ON. ’1’ = POSITIVE EDGE ’0’ = NEGATIVE EDGE
518S0856
USE 100 OHMS AND 150PF FOR 10MHZ FILTER
(SMIA_DATA_P)
(SMIA_CLK_P)
(SMIA_CLK_N)
CAMERA/ALS/DMIC CONNECTOR
(SMIA_DATA_N)
OF POS/NEG EDGE SAMPLING OF
197S0478
CRYSTAL
’1’= EXT FW
GPIO AFTER POWER ON
’0’= INT FW
GPIO3: EXT/IN FIRMWARE BOOT SEL
337S4151
201
10%
6.3V
0.1UF
C4218
X5R
20% X5R
6.3V
1.0UF
C4216
0201-MUR
6.3V 0201-MUR
C4221
1.0UF
X5R
20%
201
24K
1% MF
1/20W
R4204
PLACE_NEAR=U4200.33:5mm
R4216
201
1% MF
1/20W
47
1% 1/20W
201
MF
R4213
PLACE_NEAR=U4200.24:5mm
1.0UF
X5R
20%
6.3V
C4222
0201-MUR
XW4202
SHORT-0201
XW4203
SHORT-0201
6.3V
C4223
201
0.1UF
10% X5R
6.3V
10% X5R
201
0.1UF
C4226
PLACE_NEAR=U4200.24:5mm
X5R
6.3V
10%
0.1UF
201
C4219
C4215
6.3V
10%
0.1UF
201
X5R
0.1UF
X5R
10%
201
6.3V
C4224
0.1UF
10% X5R
C4217
201
6.3V
C4214
201
10% X5R
6.3V
0.1UF
0.1UF
10%
6.3V 201
X5R
C4213
1%
R4218
1/20W MF
1K
201 201
1K
MF
1/20W
1%
R4219
20455-020E-32
J4200
F-RT-SM
CRITICAL
L4200
0402
FERR-1000-OHM
R4260
0
0
R4264
R4214
1/20W
1M
1% MF
201
R4215
47
1%
1/20W
201
MF
X5R
10%
C4228
6.3V
0.1UF
201
R4211
MF 1%
10K
1/20W
201
R4210
1/20W MF
1%
201
10K
0402
FERR-600-OHM-300MA-0.85OHM
L4220
X5R
10%
6.3V 201
C4220
0.1UF
L4210
0402
FERR-1000-OHM
1/20W
R4220
10
201
5% MF
C4262
1UF
X5R
16V
10%
402
FERR-1000-OHM
0402
L4202
10%
402
16V X5R
1UF
C4264
L4204
0402
FERR-1000-OHM
0402
FERR-1000-OHM
L4206
10% 16V X5R 402
1UF
C4266
5% MF
1/20W
0
R4267
201
5% 50V CERM
150PF
C4267
402
NOSTUFF
0
1/20W
MF
5%
201
R4268
5% 50V CERM 402
NOSTUFF
150PF
C4268
MX25L1006EZUI-10G
USON
1MBIT-104MHZ
CRITICAL
OMIT_TABLE
U4202
R4206
1/20W
1% MF
201
10K
201
1/20W
1%
R4203
33
PLACE_NEAR=U4200.6:5mm
MF
1/20W
201
1%
33
MF
R4205
PLACE_NEAR=U4200.5:5mm
1/20W
1%
33
R4209
201
MF
PLACE_NEAR=U4202.2:5mm
MF 201
1/20W
1%
10K
R4207 R4208
4.7K
5% MF
201
1/20W
10% 16V X5R
1UF
C4265
402
18PF
5%
25V
0201
C4227
NP0-C0G-CERM
C4225
25V
0201
18PF
NP0-C0G-CERM
5%
R4250
201
100
1% MF
1/20W
NOSTUFF
NOSTUFF
1%
201
MF
100
1/20W
R4255
12.000MHZ-30PPM-10PF-85C
3.2X2.5MM-SM
Y4200
CRITICAL
VC0359
FQFN
CRITICAL
U4200
SYNC_DATE=08/27/2012
Camera Controller
SYNC_MASTER=D8_MLB
PP3V3_S4_CAMFILT
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
PP1V2_S4_CAMERA
=PP3V3_S4_CAMERA
PP1V8_S4_CAMERA
PP1V2_S4_CAMERA
PP1V2_S4_CAMFILT
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.2V
I2C_CAMSENSOR_SCL
USB_PCH_8_P
USB_CAMERA_N
MAKE_BASE=TRUE
CAM_AGND
TP_CAM_GPIO1
CAM_EXT_BOOT
SMIA_DATA_P
SMIA_CLK_P SMIA_CLK_N
CAM_XTAL_INSMIA_DATA_N
CAM_SF_DOUT
CAM_SF_DIN
TP_CS_PWD_L
CAM_SF_CLK
MIPI_RESISTOR
MAKE_BASE=TRUE
USB_CAMERA_P
TP_CAM_LED_PWM
I2C_CAMSENSOR_SDA
CAM_SF_CS_L
CAM_PLLGND
TP_ISM_CLK TP_ISM_RST_L
CAM_TEST
CAM_USB_VRES
CAM_PROC_RESET_L
CAM_RX CAM_TX
CAM_SF_WP_L
CAM_XTAL_OUT
CAM_XTAL_IN
CAM_XTAL_OUT_R
SMIA_DATA_N
SMIA_DATA_P
=PP3V3_S4_ALS
=SMB_ALS_SCL
PP1V8_S4_CAMERA
=PP5V_S4_CAMERA
=SMB_ALS_SDA
AUD_DMIC_CLK
AUD_DMIC_SDA1
PP3V3_S4_ALS_F
AUD_DMIC_SDA1_CONN
AUD_DMIC_CLK_CONN
PP1V8_S4_CAMERA_F
SMB_ALS_F_SDA
I2C_CAMSENSOR_SDA I2C_CAMSENSOR_SCL
MIN_NECK_WIDTH=0.15MM
PP3V3_DMIC_CONN
MIN_LINE_WIDTH=0.4MM
VOLTAGE=3.3V
SMB_ALS_F_SCL
PP5V_S4_CAMERA_F
PP3V3_S4_ALS_F
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
PP1V8_S4_CAMERA_F
MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.8V
PP5V_S4_CAMERA_F
MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=5V
SMIA_CLK_P
SMIA_CLK_N
SMB_ALS_F_SCL
SMB_ALS_F_SDA
GND_AUDIO_DMIC
CAM_PLLGND
CAM_AGND
USB_PCH_8_N
=PP3V3_S4_CAMERA
CAM_SF_DOUT
CAM_SF_DIN_R
CAM_SF_DIN
CAM_SF_DOUT_R
CAM_SF_CLK
CAM_XTAL_OUT
VOLTAGE=1.2V
PP1V2_S4_F_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
=PP3V3_S0_AUDIO
=PP3V3_S4_CAMERA
CAM_SF_WP_L CAM_SF_HOLD_L
CAM_SF_CLK_R
CAM_SF_CS_L
CAM_AGND
prefsb
051-9505
8.0.0
42 OF 144 42 OF 123
2
1
2
1
2
1
1
2
1
2
1
2
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
9
10
6
3 4 5
2
1
21 22
12 13
20
8
7
11
14
19
18
17
16
15
23 24
21
1 2
1 2
1
2
1 2
2
1
1
2
1
2
21
2
1
21
1 2
2
1
21
2
1
21
21
2
1
1 2
2
1
1 2
2
1
7
6
3
1
8
9
4
2
5
1
2
1 2 12
1 2
1
2
1
2
2
1
1 2
1 2
1
2
1
2
42
1 3
40
7
23
31
443522
48 47 46 12
28
30 29
927
4
5
37
6
33
18
39
41
21
20
17
42
3
25
34
43
26
38 36
11
24
1
14 13
49
2
8
15
19
10
45
32
16
42 43
6
42 43
42 43
42 43
42
106
20
106
42
106
43
117
42
106
42
106
42
106
42
106
42
106
42
106
42
106
42
106
106
106
42
106
42
106
42
106
106
43
117
42
106
42
106
42
106
106
42
106
42
106
6
50
42 43
6
50
56
56
42
121
42
42
106
42
106
42
106
121
42
106
42
42
121
42
42
42
106
42
106
42
106
42
106
56
42
106
42
106
20
6
42 43
42
106
106
42
106
106
42
106
42
106
6
56 58 59 62
6
42 43
42
106
106
106
42
106
42
106
NC
NC
EN
NC
NC
VO
VIN
GND
NC
NC
EN
NC
NC
VO
VIN
GND
D
G S
Y
A
B
08
Y
A
B
08
D
G S
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Camera Processor Reset
Camera Processor ExtBoot Cntl
PP1V2_S4_CAMERA VregPP1V8_S4_CAMERA Vreg
C4300
10%
201
X5R
6.3V
0.1UF
C4314
4.7UF
6.3V
20% X5R-CERM1
402
C4310
1UF
16V X5R
10%
402
DFN
CRITICAL
ISL9021AIRUCZ-T
U4310
C4324
6.3V X5R-CERM1
4.7UF
20%
402
U4320
CRITICAL
DFN
ISL9021AIRUWZ-T
C4320
402
X5R
16V
1UF
10%
R4300
5%
201
1/20W MF
51K
C4301
10V X5R-CERM
20%
2.2UF
402
Q4300
CRITICAL
VESM
SSM3K15AMFVAPE
8
4
U4300
74LVC2G08
SOT902
CRITICAL
8
4
U4300
SOT902
74LVC2G08
CRITICAL
Q4302
VESM
CRITICAL
SSM3K15AMFVAPE
R4302
5%
10K
201
MF
1/20W
C4312
0402
X5R-CERM
1UF
10% 10V
R4310
4.7K
MF
5%
201
1/20W
R4320
4.7K
201
5% 1/20W MF
C4322
10% 10V X5R-CERM 0402
1UF
Q4310
SOT-363-LF
MMDT3904-X-G
Q4310
SOT-363-LF
MMDT3904-X-G
R4306
MF 201
10K
1/20W
5%
R4304
1K
5% 1/20W MF 201
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
Camera Controller Support
PM_PCH_PWROK
=PP3V3_S4_CAMERA
PCH_CAM_RESET_R
PM_PCH_PWROK
=PP3V3_S4_CAMERA
PP1V2_S4_CAMERA
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MMMIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
PP1V8_S4_CAMERA
VOLTAGE=1.8V
P1V2_S4_EN
CAM_EXT_BOOT
CAM_EXT_BOOT_L
=PP3V3_S4_CAMERA
PP1V8_S4_CAMERA
CAM_P1V2_RST_HOLDOFF_L
CAM_PROC_RESET
CAM_P1V2_RST_HOLDOFF
PP1V2_S4_CAMERA
P1V8_S4_EN
=PP3V3_S4_CAMERA
=PP3V3_S4_CAMERA
PCH_CAM_EXT_BOOT_R_L
CAM_PROC_RESET_L
prefsb
051-9505
8.0.0
43 OF 144 43 OF 123
2
1
2
1
2
1
3
5
2
6
1
4
2
1
3
5
2
6
1
4
2
1
1
2
2
1
1
2
3
5
2
3
1
6
7
1
2
3
1
2
2
1
1
2
1
2
2
1
1
6
2
4
3
5
1
2
1
2
15 19
26
35
43
65
80
120
6
42 43
21
120
15 19 26 35 43 65 80
120
6
42 43
42 43 42 43
119
42
117
106
6
42 43
42 43
106
117
106
42 43
119
6
42 43
6
42 43
21 106
42
117
IN
OUT OUT
IN IN
IN IN
OUT OUT
OUT
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
D8:CONSIDER CHANGING SMC_OOB2_RX/TX_L PULL-UP TO 100K (FROM 10K) RDAR://10817697
155S0397 20mOHM
518S0865
HDD POWER
GUMSTICK2
HDD DATA
518S0251
AC CAP O S12 SIDE
AC CAP O S12 SIDE
AC CAP O S12 SIDE
514S0411
POR USE
AC CAP O S12 SIDE
CLK_REQ RESET_L
SATA Activity LED
FERR-70-OHM-4A
PLACE_NEAR=J4500.1:3MM
0603
L4500
CRITICAL
10V
0.1UF
402
C4501
CERM
20%
C4500
10V 402
CERM
0.1UF
20%
48
122
18
104
18
104
18
104
18
104
FERR-220-OHM
0402
L4530
M-ST-SM
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
J4520
EP00-081-91
CRITICAL
SILK_PART=HDD
10% 402
X7R25V
0.01UF
C4521
GND_VOID=TRUE
0.01UF
GND_VOID=TRUE
C4522
402
25V
10%
X7R
10% 402
25V X7R
GND_VOID=TRUE
C4523
0.01UF
X7R25V 40210%
GND_VOID=TRUE
0.01UF
C4524
18
104
18
104
18
104
18
104
52
122
C4532
20% X5R
603
10V
10UF10UF
10% 25V X5R
C4531
1206-1
48
122
SILK_PART=GS2 SSD
SSD-K70
F-RT-SM1
CRITICAL
J4500
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
M-ST-SM-1
SILK_PART=PWR
CRITICAL
J4530
78047-0773
5% MF-LF
R4521
402
1/16W
MF-LF 402
R4522
1/16W
5%
R4599
603
DEVELOPMENT
5%
MF-LF
1/10W
330
SILK_PART=SATA
D4599
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
SATA Connectors
SATA_SSD_R2D_N
NO_TEST=TRUE
=PP3V3_S0_SSD
SMC_OOB2_RX_L SMC_OOB2_TX_L
PP3V3_S0_SSD_FLT
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm
SATALED_L
MAKE_BASE=TRUE
SATA_HDD_D2R_P
NO_TEST=TRUE
NO_TEST=TRUE
SATA_HDD_R2D_N
SATA_HDD_R2D_C_N
NO_TEST=TRUE
NO_TEST=TRUE
SATA_HDD_R2D_P
NO_TEST=TRUE
SATA_HDD_D2R_N
NO_TEST=TRUE
SATA_HDD_D2R_C_N
NO_TEST=TRUE
SATA_HDD_D2R_C_P
SATA_SSD_R2D_P
NO_TEST=TRUE
SATA_SSD_D2R_N
NO_TEST=TRUE
SATA_SSD_D2R_P
NO_TEST=TRUE
PCH_SATALED_L
=PP3V3_S0_LED_SATA
SATALED_R_L
=PP3V3_S0_SSD
SMC_OOB1_RX_FILT
SATA_HDD_R2D_C_P
NO_TEST=TRUE
VOLTAGE=12V
MIN_NECK_WIDTH=0.4mm
MIN_LINE_WIDTH=0.6mm
PP12V_S0_HDD_FET
PP5V_S0_HDD_FET
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V
SMC_OOB1_RX_CN
prefsb
051-9505
8.0.0
45 OF 144 44 OF 123
21
2
1
2
1
21
1 2 3
5
4
6 7
1 2
1 2
1 2
1 2
2
1
2
1
2
24
26
25
31
27 28
18
1
7
6
3 4
8
23
22
20
5
10 11
9
13
12
15 16
14
17
21
19
29 30
32 33 34 35
37 38
40
39
36
7
6
5
4
3
2
1
1
2
1
2
12
K
A
6
44
121
121
104
104
104
104
15 18
6
15
6
44
52
120
52
121
122
GND
THRM
OUT2
OUT1
ILIM
IN_0 IN_1
EN2
FAULT1* FAULT2*
EN1
PAD
BI
L2
L1
L2
L1
SYM_VER-1
IN
SYM_VER-1
BI
BI
BI
L2
L1
L2
L1
OUT
OUT
IN
IN
BI
VDD
GND
DM
DP
OE*
S
DP_1
DM_1
DM_2
DP_2
BI
IN
IN
VDD
GND
DM
DP
OE*
S
DP_1
DM_1
DM_2
DP_2
IN
STDA_SSTX+
STDA_SSTX-
STDA_SSRX+
GND
D­D+
GND_DRAIN
VBUS
STDA_SSRX-
SHIELD
STDA_SSTX+
STDA_SSTX-
STDA_SSRX+
GND
D­D+
GND_DRAIN
VBUS
STDA_SSRX-
SHIELD
NC
NC
GND
VBUS
IO
IO
NC
NC
GND
VBUS
IO
IO
OUT
IN
IN
OUT
OUT
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
377S0126
155S0367
377S0126
377S0104
353S3052
44 mOHM
=> 2.19A MIN
2x ILIM resistors rdar://11104691
3ms Rise Time
EHCI
=> 2.63A MAX
23.2K (1%)
514-0840
514-0839
BLM18S121: 25 mOHM
USB/SMC DEBUG MUX
SEL: 0 MOJO SEL: 1 USB
155S0430
155S0367
155S0721
377S0104
155S0430
353S3603
BLM18S121: 25 mOHM
155S0721
377S0104377S0104
377S0104
353S3603
155S0721
377S0104 377S0104
EXT PORT B
155S0721
377S0104
EXT PORT A
PCH GPIO60
XHCI
U4600
TPS2561DR
SON
CRITICAL
20
106
80OHM-25%-100MA
L4603
GND_VOID=TRUE
CRITICAL
0504
L4604
0504
GND_VOID=TRUE
CRITICAL
80OHM-25%-100MA
CRITICAL
L4602
DLP0NS
120-OHM-90MA
6.3V
GND_VOID=TRUE
C4608
10% 201
0.1UF
X5R
GND_VOID=TRUE
C4609
201
6.3V
0.1UF
X5R 10%
CERM
0.1UF
402
C4606
20% 10V
CERM
20%
0.1UF
C4607
402
10V
46 64
120
L4611
0603
FERR-120-OHM-3A
L4612
DLP0NS
120-OHM-90MA
CRITICAL
402
10V
C4617
20% CERM
0.1UF
MF-LF
R4615
5%
1/16W
402
10K
CERM
10V
20%
0.1UF
402
C4616
20
106
20
106
20
106
CRITICAL
L4613
0504
GND_VOID=TRUE
80OHM-25%-100MA
GND_VOID=TRUE
0504
80OHM-25%-100MA
L4614
CRITICAL
20
106
20
106
10%
0.1UF
201
6.3V
X5R
GND_VOID=TRUE
C4618
GND_VOID=TRUE
6.3V
0.1UF
X5R 10%
C4619
201
20
106
20
106
402
C4601
0.1UF
10V
20% CERM
PLACE_NEAR=U4600.2:2MM
TANT
6.3V
20%
CASE-D2E
330UF-25MOHM
C4602
C4613
10V
20%
603
X5R
NOSTUFF
20%
603
10V X5R
C4603
NOSTUFF
MF-LF
402
5%
0
1/16W
R4604
20
106
DFN
U4610
USB3740
CRITICAL
SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO
20
106
47 48
119
47
U4630
USB3740
DFN
CRITICAL
18
ESD0P2RF-02LS
CRITICAL
TSSLP-2-1
D4604 D4605
TSSLP-2-1
CRITICAL
ESD0P2RF-02LS
CRITICAL
D4602
TSSLP-2-1
ESD0P2RF-02LS
CRITICAL
ESD0P2RF-02LS
TSSLP-2-1
D4603
CRITICAL
TSSLP-2-1
ESD0P2RF-02LS
D4613
CRITICAL
D4612
ESD0P2RF-02LS
TSSLP-2-1
D4615
TSSLP-2-1
ESD0P2RF-02LS
CRITICAL
ESD0P2RF-02LS
D4614
CRITICAL
TSSLP-2-1
USB-NO1-T86-D8
F-ANG-TH
J4600
CRITICAL
CRITICAL
J4610
F-ANG-TH
USB-NO2-T86-D8
X7R-CERM
16V
0.01UF
20%
0402
C4605
0402
20%
0.01UF
16V X7R-CERM
C4615
R4603
11.5K
1/16W MF-LF
PLACE_NEAR=R4602.2:2MM
1%
402
SLP1210N6
D4601
RCLAMP0582N
NOSTUFF
CRITICAL
D4611
CRITICAL
NOSTUFF
RCLAMP0582N
SLP1210N6
15 20
103
20
106
20
106
20
106
20
106
0603
L4601
FERR-120-OHM-3A
MF-LF
402
5%
10K
R4605
1/16W
PLACE_NEAR=U4600.7:2MM
11.5K
R4602
MF-LF
1%
1/16W
402
47 48
119
15 20
103
SYNC_DATE=08/27/2012
EXTERNAL USB PORTS A & B
SYNC_MASTER=D8_MLB
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
PP5V_S4_EXTB
MIN_LINE_WIDTH=0.6MM
USB_EXTAB_ILIM
USB_EXTAB_ILIM_R
USB_EXTB_OC_L
USB_PCH_1_P
USB_PCH_9_P
USB_DEBUGPRT_EN_L
USB3_EXTB_TX_F_P
NO_TEST=TRUE
USB3_EXTA_RX_F_P
NO_TEST=TRUE
USB3_EXTA_RX_P
NO_TEST=TRUE
NO_TEST=TRUE
USB3_EXTA_TX_F_N
NO_TEST=TRUE
USB2_EXTA_MUXED_N
USB3_EXTB_RX_N
NO_TEST=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V
PP3V3_G3H_SMC_USBMUX_R
USB3_EXTB_RX_F_P
NO_TEST=TRUE
USB3_EXTA_TX_P
NO_TEST=TRUE
USB3_EXTA_TX_N
NO_TEST=TRUE
NO_TEST=TRUE
USB3_EXTA_RX_F_N
NO_TEST=TRUE
USB3_EXTB_TX_N
USB3_EXTB_TX_P
NO_TEST=TRUE
USB3_EXTB_RX_F_N
NO_TEST=TRUE
NO_TEST=TRUE
USB3_EXTB_TX_C_N
USB2_EXTB_MUXED_P
NO_TEST=TRUE
NO_TEST=TRUE
USB3_EXTB_RX_P
NO_TEST=TRUE
USB3_EXTB_TX_F_N
USB2_EXTB_MUXED_N
NO_TEST=TRUE
USB_PCH_0_N
MOJO_TX_L
MOJO_RX_L
=PP3V3_G3H_SMC_USBMUX
USB_PCH_1_N
USB_EXTB_SEL_XHCI
USB_PCH_0_P
USB3_EXTA_TX_F_P
NO_TEST=TRUE
USB3_EXTA_RX_N
NO_TEST=TRUE
=PP3V3_S5_SMC_USBMUX
PM_EN_USB_PWR
=PP5V_S4_USB
USB_EXTA_OC_L
USB_PCH_9_N
PP5V_S4_EXTA
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V MIN_NECK_WIDTH=0.2MM
NO_TEST=TRUE
USB3_EXTA_TX_C_P
NO_TEST=TRUE
USB3_EXTA_TX_C_N
NO_TEST=TRUE
USB3_EXTB_TX_C_P
USB2_EXTB_MUXED_F_P
NO_TEST=TRUE
USB2_EXTB_MUXED_F_N
NO_TEST=TRUE
PP5V_S4_EXTB_F
VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
USB2_EXTA_MUXED_P
NO_TEST=TRUE
PP5V_S4_EXTA_F
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
NO_TEST=TRUE
USB2_EXTA_MUXED_F_P
USB2_EXTA_MUXED_F_N
NO_TEST=TRUE
prefsb
051-9505
8.0.0
46 OF 144 45 OF 123
1
11
8
9
7
2 3
5
10
6
4
4
3
2
1
4
3
2
1
4 3
1 2
1 2
1 2
2
1
2
1
21
4 3
1 2
2
1
1
2
2
1
4
3
2
1
4
3
2
1
1 2
1 2
2
11
2
2
1
2
1
1 2
58
9
10
3
4
2
1
7
6
58
9
10
3
4
2
1
7
6
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
9
8
6
4
14 15 16
2 3
11 12 13
17
21
7
1
5
22
10
18 19 20
9
8
6
4
14 15 16
2 3
11 12 13
17
21
7
1
5
22
10
18 19 20
2
1
2
1
1
2
32
1
6
5
4
32
1
6
5
4
21
1
2
1
2
121
106
106
106
106
106
121
106
106
106
106
106
6
106
106
6
46
6
46
121
106
106
106
106
106
121
106
121
106
106
GND
THRM
OUT2
OUT1
ILIM
IN_0 IN_1
EN2
FAULT1* FAULT2*
EN1
PAD
L2
L1
L2
L1
SYM_VER-1
IN
SYM_VER-1
BI
BI
BI
L2
L1
L2
L1
OUT
OUT
IN
IN
BI
VDD
GND
DM
DP
OE*
S
DP_1
DM_1
DM_2
DP_2
IN
BI
BI
STDA_SSTX+
STDA_SSTX-
STDA_SSRX+
GND
D­D+
GND_DRAIN
VBUS
STDA_SSRX-
SHIELD
STDA_SSTX+
STDA_SSTX-
STDA_SSRX+
GND
D­D+
GND_DRAIN
VBUS
STDA_SSRX-
SHIELD
NC
NC
GND
VBUS
IO
IO
NC
NC
GND
VBUS
IO
IO
OUT
IN
IN
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
2x ILIM resistors rdar://11104691
23.2K (1%)
PCH GPIO74
353S3052
XHCI
EHCI
=> 2.19A MIN => 2.63A MAX
BLM18S121: 25 mOHM
BLM18S121: 25 mOHM
377S0104
155S0367
155S0721
155S0721
377S0104 377S0104
44 mOHM
155S0430
155S0367
353S3603
155S0721
155S0721
377S0104
377S0104377S0104
3ms Rise Time
155S0430
EXT PORT D
377S0104377S0104
EXT PORT C
514-0842
514-0841
377S0126
377S0126
CRITICAL
SON
U4700
TPS2561DR
CRITICAL
L4703
0504
GND_VOID=TRUE
80OHM-25%-100MA
80OHM-25%-100MA
CRITICAL
0504
GND_VOID=TRUE
L4704
CRITICAL
DLP0NS
120-OHM-90MA
L4702
GND_VOID=TRUE
6.3V
0.1UF
C4708
10%
X5R
201
10%
6.3V
C4709
GND_VOID=TRUE
201
0.1UF
X5R
20% 10V CERM
0.1UF
C4707
402
45 64
120
FERR-120-OHM-3A
L4711
0603
L4712
CRITICAL
120-OHM-90MA
DLP0NS
402
CERM
20%
0.1UF
10V
C4717
10K
MF-LF
402
1/16W
5%
R4715
402
20% CERM
C4716
0.1UF
10V
20
106
20
106
20
106
80OHM-25%-100MA
GND_VOID=TRUE
0504
L4713
CRITICAL
GND_VOID=TRUE
CRITICAL
L4714
80OHM-25%-100MA
0504
20
106
20
106
GND_VOID=TRUE
C4718
X5R
6.3V 201
0.1UF
10%
C4719
10%
X5R
0.1UF
201
6.3V
GND_VOID=TRUE
20
106
20
106
PLACE_NEAR=U4700.2:2MM
CERM 402
0.1UF
20%
C4701
10V
330UF-25MOHM
C4702
20%
6.3V
CASE-D2E
TANT
20%
X5R 603
NOSTUFF
C4713
10V
NOSTUFF
603
X5R
20%
10V
C4703
20
106
USB3740
CRITICAL
DFN
U4730
18
TSSLP-2-1
CRITICAL
ESD0P2RF-02LS
D4704
CRITICAL
TSSLP-2-1
D4705
ESD0P2RF-02LS
CRITICAL
TSSLP-2-1
ESD0P2RF-02LS
D4702
TSSLP-2-1
D4703
CRITICAL
ESD0P2RF-02LS
ESD0P2RF-02LS
D4713
TSSLP-2-1
CRITICAL
D4712
ESD0P2RF-02LS
TSSLP-2-1
CRITICAL
D4715
CRITICAL
TSSLP-2-1
ESD0P2RF-02LS
D4714
TSSLP-2-1
ESD0P2RF-02LS
CRITICAL
20
106
20
106
USB-NO3-T86-D8
J4700
CRITICAL
F-ANG-TH
F-ANG-TH
USB-NO4-T86-D8
J4710
CRITICAL
C4705
20%
0.01UF
16V 0402
X7R-CERM
20%
0.01UF
16V 0402
X7R-CERM
C4715
R4702
PLACE_NEAR=U4700.7:2MM
11.5K
1/16W
1%
402
MF-LF
PLACE_NEAR=R4702.2:2MM
R4703
402
11.5K
1%
MF-LF
1/16W
CRITICAL
SLP1210N6
RCLAMP0582N
NOSTUFF
D4711
D4701
CRITICAL
SLP1210N6
RCLAMP0582N
15 20
103
20
106
20
106
20
106
20
106
FERR-120-OHM-3A
0603
L4701
15 20
103
SYNC_MASTER=D8_MLB
EXTERNAL USB PORTS C & D
SYNC_DATE=08/27/2012
NO_TEST=TRUE
USB2_EXTD_MUXED_F_N
NO_TEST=TRUE
USB2_EXTD_MUXED_F_P
PP5V_S4_EXTD_F
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V MIN_LINE_WIDTH=0.6MM
NO_TEST=TRUE
USB2_EXTC_F_N
NO_TEST=TRUE
USB2_EXTC_F_P
PP5V_S4_EXTC_F
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V MIN_NECK_WIDTH=0.2MMMIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
PP5V_S4_EXTC
NO_TEST=TRUE
USB3_EXTC_TX_F_N USB3_EXTC_TX_F_P
NO_TEST=TRUE
NO_TEST=TRUE
USB3_EXTC_TX_N
NO_TEST=TRUE
USB3_EXTC_TX_C_N
USB3_EXTD_TX_C_P
NO_TEST=TRUE
NO_TEST=TRUE
USB3_EXTC_RX_N
NO_TEST=TRUE
USB3_EXTD_TX_F_P
USB3_EXTC_RX_P
NO_TEST=TRUE
USB3_EXTD_TX_N
NO_TEST=TRUE
USB3_EXTD_TX_P
NO_TEST=TRUE
USB3_EXTD_RX_F_P
NO_TEST=TRUE
USB3_EXTD_RX_F_N
NO_TEST=TRUE
USB3_EXTD_TX_C_N
NO_TEST=TRUE
USB3_EXTC_TX_C_P
NO_TEST=TRUE
USB3_EXTC_RX_F_N
NO_TEST=TRUE
NO_TEST=TRUE
USB3_EXTC_RX_F_P
USB3_EXTC_TX_P
NO_TEST=TRUE
USB3_EXTD_RX_N
NO_TEST=TRUE
USB3_EXTD_RX_P
NO_TEST=TRUE
USB3_EXTD_TX_F_N
NO_TEST=TRUE
NO_TEST=TRUE
USB2_EXTD_MUXED_P
NO_TEST=TRUE
USB2_EXTD_MUXED_N
USB_PCH_10_N
USB_PCH_10_P
USB_PCH_3_N
USB_PCH_3_P
USB_EXTD_SEL_XHCI
PM_EN_USB_PWR
USB_EXTC_OC_L
USB_EXTD_OC_L
=PP3V3_S5_SMC_USBMUX
USB_PCH_2_P USB_PCH_2_N
USB_EXTCD_ILIM_R
USB_EXTCD_ILIM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V MIN_LINE_WIDTH=0.6MM
PP5V_S4_EXTD
=PP5V_S4_USB
prefsb
051-9505
8.0.0
47 OF 144 46 OF 123
1
11
8
9
7
2 3
5
10
6
4
4
3
2
1
4
3
2
1
4 3
1 2
1 2
1 2
2
1
21
4 3
1 2
2
1
1
2
2
1
4
3
2
1
4
3
2
1
1 2
1 2
2
11
2
2
1
2
1
58
9
10
3
4
2
1
7
6
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
9
8
6
4
14 15 16
2 3
11 12 13
17
21
7
1
5
22
10
18 19 20
9
8
6
4
14 15 16
2 3
11 12 13
17
21
7
1
5
22
10
18 19 20
2
1
2
1
1
2
1
2
32
1
6
5
4
32
1
6
5
4
21
106
106
121
106
106
121 121
106
106
106
106
106
106
106
106
106
106
106
106
106
106
6
45
121
6
45
LPC0AD3 LPC0CLK LPC0FRAME*
LPC0AD1 LPC0AD2
AIN08
AIN07 LPC0CLKRUN* LPC0PD*
AIN13
AIN14
PM7/FAN0TACH0
PM6/FAN0PWM0
AIN04
C1-
I2C2SDA
AIN05
AIN09
AIN11
AIN21
AIN23
PK7/FAN0TACH1
AIN15
AIN06
AIN10
AIN20
AIN22
T1CCP1/PJ1
PK5
LPC0AD0
AIN12
PECI0RX PECI0TX
PK6/FAN0PWM1
LPC0RESET*
PQ0/IRQ124
PP6/IRQ122
PN3/FAN0TACH2
I2C0SDA
AIN01
AIN00
PQ1/IRQ125
I2C0SCL
U1TX/PB1
USB0DP
USB0DM
AIN03
AIN02
T0CCP1/PB7
T0CCP0/PB6
PQ2/IRQ126
U1RX/B0
LPC0SCI*
AIN17
AIN16
PN2/FAN0PWM2
WT4CCP1/PH7
AIN18
AIN19
WT4CCP0/PH6
WT3CCP1/PH5
WT5CCP1/PM3
LPC0SERIRQ
PH3/FAN0TACH5
WT3CCP0/PH4
PH2/FAN0PWM5
PP3/IRQ119 PP4/IRQ120
C0-
WT2CCP0/PH0 WT2CCP1/PH1
PQ5/IRQ129
PP7/IRQ123
WT0CCP0/PG4
I2C3SDA
SSI1FSS/PF3
PC5/C1+
U0RX
SSI0RX/PA4
PP5/IRQ121
PQ7/IRQ131
WT0CCP1/PG5
I2C3SCL
SSI1CLK/PF2
PN4/FAN0PWM3
PP1/IRQ117
U0TX
SSI0CLK/PA2 SSI0FSS/PA3
I2C1SCL
PP2/IRQ118
PQ6/IRQ130
I2C4SDA
SSI1RX/PF0
PN7/FAN0TACH4
PP0/IRQ116
SSI0TX/PA5
I2C1SDA
I2C5SDA
PQ3/IRQ127 PQ4/IRQ128
I2C4SCL
I2C2SCL
SSI1TX/PF1
PN6/FAN0PWM4
PN5/FAN0TACH3
I2C5SCL
T3CCP0/PJ4/C2+
T3CCP1/PJ5/C2-
PF4 PF5
T1CCP0/PJ0
T2CCP0/PJ2 T2CCP1/PJ3
C0+
(1 OF 2)
VDDC
VREFA-
SWO/TDO
TDI
RST*
HIB*
WAKE*
XOSC0
VREFA+
VDDA
GNDA
PK4/RTCCLK
GND
NC
OSC0
XOSC1
SWCLK/TCK SWDIO/TMS
OSC1
VBAT
VDD
(2 OF 2)
IN
IN
BI BI BI BI
IN IN IN
BI
OUT IN OUT
BI BI BI BI BI BI BI BI BI BI BI BI
IN IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT OUT OUT OUT
OUT
IN
OUT
OUT OUT OUT
IN
OUT
IN
IN
OUT
OUT OUT OUT
NC
OUT
IN OUT
IN OUT
BI BI
OUT IN
IN
OUT
OUT
IN
OUT
IN IN
IN
IN IN IN IN IN IN IN
IN OUT
OUT
BI
OUT OUT IN IN OUT
IN
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
IN IN
IN
IN
IN
IN
IN
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
proj
arch
arch arch
od
od
od
proj proj
arch
proj
proj
proj
arch
arch
arch
arch
arch
od
od
analog
analog
od
arch
od
od
analog
arch
int
arch
arch
arch
arch
od
arch arch
arch arch arch
arch arch
arch
arch
arch
arch
arch
proj
proj
proj
arch
arch
arch
arch
proj proj
od
proj
int
analog
arch
arch
proj
proj
proj
proj proj
arch arch
arch
analog
analog
proj
analog
int
int
int
int
arch
arch
arch
od
od
od
arch
arch
od
analog
arch
proj
proj
analog
analog
proj
analog
analog
analog
proj
proj
analog
proj
analog
proj
analog analog
analog
analog
analog
proj
analog
analog
proj
analog
arch
pwm
proj
proj
arch
arch
arch
arch
arch
od
od
arch
arch
arch
arch
proj
od
proj
proj
proj
int
int
int
int
arch
proj
int
int
int
int
arch
arch
arch
arch
proj
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating,
proj
arch
proj
arch
arch
proj
analog
proj
analog
od
analog
analog
arch
int
proj
arch
proj
arch
arch
analog
those designated as inputs require pull-ups.
(OD)
proj
arch
arch arch arch
arch
arch
arch
proj
analog
arch
U4900
OMIT_TABLE
BGA
LM4FSXAH5BB
U4900
BGA
OMIT_TABLE
LM4FSXAH5BB
XW4900
SM
PLACE_NEAR=U4900.A1:4MM
48 49
122
48
105
R4902
1M
MF
1/20W
5%
201
18 49
105
18 49
105
18 49
105
18 49
105
26
105
18 49
105
26
122
18 49
119
48 49
120
19 26 49
119
15 21
122
50
121
50
121
50
121
50
121
50
121
50
121
50
121
50
121
48 50
121
48 50
121
48 50
121
48 50
121
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48 74
122
48 65
120
38 48 65
122
48
122
45 48
119
45 48
119
48
48
105
48
105
48
105
48
105
45
48 91
122
5
65
117
48
122
15 19 25
120
19 25 26
120
29 30 31 32 48
119
15 21
122
11 21 48
103
48
122
48 49
122
48 49
122
48
48
54
54
48
48
48
54
122
54
122
48
122
35 48
122
48
48
48
48
118
5
15 19 28 40 48 64
120
15 19 64
120
15 19 64
120
48
122
48
35 48
122
48
35 48
117
48
48
48
48
48
48
48
118
91
122
65
121
15
122
L4901
30-OHM-1.7A
0402
11 48 66
103
52
122
48
48
122
48
65
C4917
X5R
6.3V
10%
201
0.1UF
C4913
6.3V
10%
201
0.1UF
X5R
C4914
X5R
10%
201
0.1UF
6.3V
C4915
0.1UF
201
10%
6.3V X5R
C4916
X5R
6.3V
10%
201
0.1UF
C4903
0.1UF
X5R
6.3V
10%
201
C4904
X5R
6.3V
10%
201
0.1UF
C4905
X5R
6.3V
10%
201
0.1UF
C4906
X5R
10%
0.1UF
201
6.3V
C4909
X5R
6.3V
10%
201
0.1UF
C4908
201
X5R
6.3V
10%
0.1UF
C4907
0.1UF
6.3V X5R 201
10%
C4901
0.1UF
201
10%
6.3V X5R
48
48
48
117
48
122
48
122
48
48
C4921
0.01UF
10% 10V X5R-CERM 0201
PLACE_NEAR=U4900.D2:4mm
C4920
6.3V X5R
20%
0201
1UF
PLACE_NEAR=U4900.D1:4mm
C4910
402
CERM
6.3V
10%
1UF
C4911
402
CERM
6.3V
10%
1UF
C4912
402
CERM
6.3V
10%
1UF
20%
0603-1
X5R-CERM
C4902
1UF
10V
SMC
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
LPC_AD<1>
LPC_AD<0>
LPC_FRAME_L
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1 MM
MIN_LINE_WIDTH=0.25 MM
PP3V3_G3H_SMC_VDDA
SMC_ADC5
SMC_PP5
SMC_TCK
SMC_TDO
CPU_PROCHOT_L
SMBUS_SMC_3_SCL
SMC_TDI
SMBUS_SMC_5_G3H_SCL
SMC_ADC16
SMC_ADC18
SMC_ADC23
SMC_CPU_CATERR_L
MOJO_RX_L
SMC_PROCHOT
SMC_DELAYED_PWRGD
SMC_PP6
SMC_RX_L SMC_TX_L
SMC_FAN_1_CTL
SMC_ADC7
SMC_ADC9
SMC_ADC12
SMC_ADC19
SMC_GFX_THROTTLE_L
SMC_RESET_L
SMC_TMS
SMC_S4_WAKESRC_EN
SMC_WAKE_L
SMC_XTAL
NC_SMC_XOSC1 NO_TEST=TRUE
SMC_EXTAL
AP_EVENT_L
SMC_CLK32K
NC_SMC_HIB_L NO_TEST=TRUE
SPI_SMC_MOSI
MOJO_TX_L
SMC_ADC0
SMC_ADC21 SMC_ADC22
CPU_THRMTRIP_3V3
SMC_PM_G2_EN
SMC_PN7
SMC_DP_HPD_L
ENET_ASF_GPIO
SMC_BC_ACOK G3_POWERON_L
SMC_PJ3
SMC_BATLOW_L
SMC_PJ2
SMC_OOB1_RX_L
LPC_SERIRQ PM_CLKRUN_L LPC_PWRDWN_L
SMC_PME_S4_WAKE_L
SMBUS_SMC_5_G3H_SDA
USB_SMC_N
PM_SLP_S4_L
SMC_PP7
SMC_ADC11
SMC_ADC8
PM_SLP_S3_L
USB_SMC_P
SMBUS_SMC_1_S0_SDA
LPC_AD<2>
SMC_LRESET_L
SMC_RUNTIME_SCI_L
SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_0_S0_SCL
SMC_PN6
SMBUS_SMC_0_S0_SDA
SMC_WAKE_SCI_L
SMC_VCCIO_CPU_DIV2
SMC_ADC10
SMC_ADC6
SMC_ADC15
SMC_ADC20
SMBUS_SMC_2_S4_SCL
SMS_INT_L
PM_SLP_S5_L SMC_ONOFF_L
SMC_FAN_0_TACH
SMC_SYS_LED
PM_PWRBTN_L
SMC_THRMTRIP
ALL_SYS_PWRGD
SMC_GFX_OVERTEMP
PM_DSW_PWRGD
SPI_DESCRIPTOR_OVERRIDE_L
SMC_ADC17
SMC_S5_PWRGD_VIN
SMC_PM_PCH_SYS_PWROK
SMC_PP0
CPU_PECI
SMC_OOB1_TX_L
SMC_PH7
MEM_EVENT_L
PM_SYSRST_L
USB_DEBUGPRT_EN_L
S5_PWRGD
SPI_SMC_CS_L
SPI_SMC_CLK
SPI_SMC_MISO
SMC_PME_S4_DARK_L
SMC_PH2
SMC_PN2
SMBUS_SMC_3_SDA SMBUS_SMC_4_ASF_SCL
SMC_PECI_L
SMC_PH3
SMC_PN5
SMC_PN4
SMC_PN3
SMC_FAN_1_TACH
SMC_FAN_0_CTL
SMBUS_SMC_2_S4_SDA
SMBUS_SMC_1_S0_SCL
LPC_AD<3> LPC_CLK33M_SMC
SMC_ADC2
SMC_ADC14
SMC_ADC13
SMC_ADC1
SMC_ADC3 SMC_ADC4
PP1V2_G3H_SMC_VDDC
MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.2V
MIN_LINE_WIDTH=0.25 MM
GND_SMC_AVSS
PP3V3_G3H_AVREF_SMC
=PP3V3_G3H_SMC
prefsb
051-9505
8.0.0
49 OF 144 47 OF 123
D11 H12 D12
A13 C12
B5
A4 G11 F13
C2
B1
L13
H11
B3
L2
M8
A3
A5
A6
A7
A8
A12
B2
B4
B6
B7
B8
B9
B12
B13
C1
C4 C6
C11
C13
D4
D8
D10
D13
E1
E2
E4
E10
E11
E12
E13
F1
F2
F3
F4
F5
F11
F12
G1
G2
G3
G4
H1
H2
H3
H4
H10
H13
J2
J3
J4
J12
J13
K2
K3
K4
K5
K6
K7
K8
K10
L1
L3
L4
L5
L6
L7
L8
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M9
M11
M13
N1
N2
N3
N5
N6
N7
N8
N9
N11
N12
N4
D5
C5
L9
K9
C9
A9
C8
K1
K13
J1
J9
J7
F10
D1
C7
A11 B10
G10
M12
N13
M10
D2
D3
C3
B11
A1
A2
E3
E5 F9
G12
H5 H9 J5
E6 E8
D9
J10
E9
N10
J8
C10 A10
G13
K12
D7
K11
J11
D6
J6
12
1
2
21
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
48 49 122
48 49 122
48 49 122
48 49 122
122
48
122
48
122
120
48 51 55
118
48
121
6
48 50
D
SG
IN
OUT
NC
NC
IN
OUT
REFOUT
MR1*
THRM
GND
RESET*
DELAY
MR2*
VIN
V+
SN0903048
PAD
OUT
NC NC
OUT
IN
BI
IN
BI
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
IN
D
SG
IN
D
SG
IN
IN
BI
IN
OUT
IN
D
G S
D
G S
D
G S
OUT
OUT
IN
IN
D
SG
D
SG
VDD
GND
DM
DP
OE*
S
DP_1
DM_1
DM_2
DP_2
IN
IN
D
SG
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
RDAR://10107203
Note: Previously SMC_NMI. Matt card pulls low.
Note: IPU are pulled to VIN rail
Remove USB hookup from SMC (not needed)
SMC Crystal
SMC 32KHz Clock
(ipu)
(ipu)
SMC Supervisor and AVREF Supply
rdar://11180279 SMC_RESET_L workaround
Level-shifter that allows SMC to drive PROCHOT
SMC samples on power on to enter recovery flasher mode.
Arch Pull Up/Down
PCH and CPU PM signals to SMC
AC/DC from oscillating in and out.
PECI Support
radar://11033060
Serial/JTAG Interface Pull-ups
If power high (i.e. charging iPad)
SMC to monitor 12V G3H power in S3
Pull-down needed for SMC SSI signals
TP for access if ZPB re-instated
case when SMC is initializing in S5, and chip is not yet configured.
rdar://10506970
rdar://10196882
SMC SPI Support
ADC Channel Aliases
Enable S4 Wake Sources
Power Button
Unused Project-specific
To absorb current from discharging RTC Reset Cap
enable BURSTMODE to avoid the
SMC Controlled RTC Reset
To let SMC log if a CATERR or SYS_PWROK abruptly occurs
Note:
Level-shifter that allows unidir SMC to drive bidir PECI
RDAR://11158919 D8:DETERMINE VALUE AND STUFF SERIES R FOR SPI BUS
Project-specific Aliases
197S0472
RDAR://10350663 SMC CRYSTAL SELECTION
PLACEMENT_NOTE: Place this circuit near the Tee point to minimize reflections
PROCHOT Support
Platform Thermal Control
Allow either GFX_OVERTEMP, SMC-driven THRMTRIP or
For a debug ability to communicate to BLC MCU through SMC
Connect BLC Serial through Mojo Mux
CPU-driven THRMTRIP to drive PCH PM_THRMTRIP
SEE
(RADAR://PROBLEM/11724870)
THIS CIRCUIT WILL NOT WORK
SECOND STAGE FET WILL NOT FIX THIS S0 COLLAPSES BEFORE SIGNAL REACHES 3.3 SOLUTION WILL REQUIRE LATCHING OF TT
Note:
Comparator VCCIO Reference
AC/DC Burst Mode Enable
and ACDC_BURST_EN_L could be floating.
Open-drain stage on S4 to account
Q5024
SOT563
CRITICAL
SSM6N15AFE
45 47 48
119
45 47 48
119
16V
10%
0.01UF
0402
X7R-CERM
C5060
R5059
NOSTUFF
0
1/16W MF-LF
5%
402
R5058
NOSTUFF
MF-LF
0
1/16W
5%
402
10K
MF
1/20W
201
5%
R5026
80
122
80
122
CRITICAL
Y5065
12.000MHZ-50PPM-8PF-100OHM
5X3.2X1.2-SM
MMDT3904-X-G
CRITICAL
Q5027
SOT-363-LF
SOT-363-LF
Q5027
MMDT3904-X-G
CRITICAL
0.01UF
X5R-CERM
C5040
0201
10V
10%
PLACE_NEAR=U4900.K1:4MM
0402
0.1UF
10% 16V X7R-CERM
C5031
U5000
DFN
CRITICAL
VREF-3.3V-VDET-3.0V
402
C5000
10%
0.47UF
CERM-X5R
6.3V
0603-1
X5R-CERM
10V
1UF
C5005
20%
47 49
122
MF-LF 402
5% 1/16W
100K
R5005
47
122
R5065
402
0
5%
MF-LF
1/16W
47
122
11 47 66
103
R5078
MF
1/20W
201
5%
100K
R5035
0
5%
1/16W
402
MF-LF
47
122
R5036
NONE NONE
NONE
OMIT
NOSTUFF
402
5% MF-LF
1/16W
330
402
R5037
11 21 47
103
PLACE_NEAR=U4900.K1:6MM
R5030
10K
1/16W
402
1%
MF-LF
10K
402
1% 1/16W MF-LF
R5031
PLACE_NEAR=U4900.K1:5MM
47
R5085
2015%MF
1/20W
10K
47
105
49
105
49
105
47
105
49
105
47
105
49
105
47
105
R5075
10K
1/20W
201
MF
5%
R5080
5% MF
201
1/20W
10K
47
105
PLACE_NEAR=U1800.BA47:6MM
5%
402
MF-LF
22
R5060
1/16W
19
105
R5020
5%
201
MF
1/20W
10K
R5077
1/20W
MF5%201
100K
6
77 77
R5079
100K
1/20W
2015%MF
MF
5%
10K
1/20W
201
R5090
100K
5% MF
201
1/20W
R5091
R5095
1/20W
5%
201
10K
MF 5%
1/20W
10K
MF
201
R5096 R5097
MF5%201
1/20W
10K
R5098
MF
10K
1/20W
201
5%
R5093
100K
2015%MF
1/20W
R5092
5%
10K
201
MF
1/20W
R5087
100K
201
5%
1/20W
MF
R5076
MF
1/20W
201
5%
10K
79
R5048
0
5%
1/20W
MF
201
19 65
120
47
122
47
122
0
5% MF
1/20W
201
R5049
11
103
SSM6N15AFE
Q5023
CRITICAL
SOT563
47 91
122
SSM6N15AFE
CRITICAL
SOT563
Q5023
49
122
47
122
5%
1K
MF
1/20W
R5025
201
21
120
R5040
10K
1/20W
MF
201
5%
48
117
201
1/20W
10K
MF
5%
R5041
6
71
117
R5038
43
402
1/16W MF-LF
5%
51
201
MF
5%
1/20W
R5023
MF
201
R5027
3.3K
5%
1/20W
11
103
201
R5028
1/20W
3.3K
MF
5%
SSM3K15AMFVAPE
VESM
CRITICAL
Q5035
CRITICAL
Q5025
SSM3K15AMFVAPE
VESM
VESM
SSM3K15AMFVAPE
CRITICAL
Q5099
18 26
121
5%
1/16W
R5099
402
MF-LF
10K
C5099
NOSTUFF
1.0UF
6.3V 0402
X5R-CERM
20%
MF-LF
5%
R5094
1/16W
330
402
MF
1/20W
201
5%
10K
R5024
R5070
10K
5%
1/20W
201
MF
R5071
10K
5%
1/20W
MF
201
402
1/16W
5%
1M
MF-LF
R5066
NOSTUFF
R5084
100K
5%
MF-LF
1/16W
402
R5086
100K
5%
1/16W
402
MF-LF
47
117
R5017
100K
5%
1/16W
402
MF-LF
R5081
10K
201
5%
1/20W
MF
6
79
S5000
NTC020AA1JB260T
SM
SILK_PART=PWR BTN
NTC020AA1JB260T
SILK_PART=PWR BTN
S5020
SM
6
121
R5072
1/20W
201
10K
NOSTUFF
MF
5%
5%
C5065
50V 0402
C0G-CERM
C5066
50V 0402
C0G-CERM
5%
16V 0402
10% X7R-CERM
0.01UF
C5001
X7R-CERM
0.01UF
C5006
16V
10%
0402
SSM6N15AFE
Q5040
SOT563
SOT563
Q5040
SSM6N15AFE
R5050
402
MF-LF
1/16W
1%
R5051
402
MF-LF
1/16W
15
1%
R5052
1%
15
1/16W MF-LF
402
R5053
402
MF-LF
1/16W
15
1%
R5009
47
5% 1/16W MF-LF
402
C5009
4.7UF
10% X5R-CERM
25V 0603
U5060
CRITICAL
USB3740
DFN
48 80
117
48 80
117
SOT563
CRITICAL
SSM6N15AFE
Q5024
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
SMC Support
SMC_VCCIO_CPU_DIV2
BURSTMODE_EN_L
ACDC_BURST_EN
=PP3V3_S4_SMC
SMC_TO_BLC_TX_L
BLC_EXT_BOOT
SMBUS_SMC_4_ASF_SCL
MAKE_BASE=TRUE
SMCISNS_P3V3S0_SSD
MAKE_BASE=TRUE
SMCISNS_P12VS0_CPU_P1V05
SMCISNS_P12VS0_CPU_VCCSA
MAKE_BASE=TRUE
SMBUS_SMC_5_G3H_SDA SMC_OOB1_TX_L
SMC_GFX_OVERTEMP
SMC_ADC20
PM_THRMTRIP_L
NC_SMB_OOB1_TX_L
NO_TEST=TRUE
MAKE_BASE=TRUE
SMC_PN3
SMC_ADC23
=PPVCCIO_S0_SMC
SMC_XTAL_R
SPI_SMC_MISO
SMC_PH3
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_SMC_N
NC_SMC_PN3
NO_TEST=TRUE
MAKE_BASE=TRUE
SMC_PN6
NC_SMC_PP6
NO_TEST=TRUE
MAKE_BASE=TRUE
SMC_ONOFF_L
MAKE_BASE=TRUE
SMC_PECI_L_R
SMC_PECI_L
SMC_RX_L
SMC_TCK
MOJO_RX_L
SMC_TMS
SMC_BLC_MUX_TX_L SMC_BLC_MUX_RX_L
BLC_EXT_BOOT
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMBUS_SMC_5_G3H_SCL
TP_SMC_PH7
MAKE_BASE=TRUE
GND_SMC_AVSS
SMC_CPU_PECI
=PPVCCIO_S0_SMC
SMC_PN2
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SMC_PN6
=PP3V3_G3H_SMC
SMC_ADC4
MAKE_BASE=TRUE
SMCISNS_P1V5S0_CPU_MEM
MAKE_BASE=TRUE
SMCVSNS_PVDDQS3_DDR
MAKE_BASE=TRUE
SMCISNS_P5VS0_HDD
SMC_ADC19
=PP3V3_S4_TBTBPWRSW
=PP3V3_S4_TBTAPWRSW
=TBTBPWRSW_EN
=TBTAPWRSW_EN
=PP3V3_G3H_SMC
SMC_ADC18
=PP3V3_G3H_SMC
SPI_MLB_CS_LSPI_SMC_CS_L
SPI_MLB_CLKSPI_SMC_CLK
SPI_MLB_MOSISPI_SMC_MOSI
SPI_MLB_MISO
ACDC_BURST_EN_L
MAKE_BASE=TRUE
NC_SMC_DP_HPD_L
NO_TEST=TRUE
SMC_PP5 SMC_PP6 SMC_PP7
MAKE_BASE=TRUE
SMCVSNS_P1V05S0_PCH
SMC_PN5
NC_USB_SMC_P
MAKE_BASE=TRUE
NO_TEST=TRUE
=PP3V3_S5_SMC
SMC_ADC21
MAKE_BASE=TRUE
SMCVSNS_P3V3S0
SMCISNS_P3V3S4_AP
MAKE_BASE=TRUE
SMCISNS_P1V05S0_PCH
MAKE_BASE=TRUE
SMC_PN7
SMBUS_SMC_5_G3H_SCL
SMC_PH7
USB_SMC_P
SMC_PJ3
SMC_ASSERT_RTCRST
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_BLC_FAULT
SMS_INT_L
AP_EVENT_L
ENET_ASF_GPIO
SMC_BC_ACOK
=PP3V3_S4_AP_FET
MAKE_BASE=TRUE
SMCISNS_P12VS0_FBVDDQ
MAKE_BASE=TRUE
SMCVSNS_CPUCORE
=PP3V3_G3H_SMC
RTC_RESET_L
RTC_RESET_L_R
SMC_ADC6
SMC_ADC2
SMC_ADC5
SMC_ADC8
SMC_ADC13
SMC_ADC16
SMC_ADC1
SMC_ADC3
SMC_ADC7
SMC_ADC9 SMC_ADC10 SMC_ADC11 SMC_ADC12
G3_POWERON_L SMC_BATLOW_L
SMC_DELAYED_PWRGD PM_DSW_PWRGD
SMC_TX_L
SMC_TDI
MOJO_TX_L
SMC_PME_S4_WAKE_L
SMC_SYS_LED
SMC_S4_WAKESRC_EN
SMC_ADC15
MEM_EVENT_L PM_CLKRUN_L
=PP3V3_S0_SMC
SMC_BLC_FAULT
SMC_XTAL
SMCISNS_P12VS0_P1V05
MAKE_BASE=TRUE
SMC_OOB2_RX_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ACDC_BURST_EN_L
SMCVSNS_P1V5S0_CPU_MEM
MAKE_BASE=TRUE
SMCISNS_GPUCORE
MAKE_BASE=TRUE
SMC_OOB2_TX_L
MAKE_BASE=TRUE
BDV_BKL_PWM
MAKE_BASE=TRUE
SMCISNS_P12VS0_HDD
MAKE_BASE=TRUE
SMC_ACDC_ID
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMCVSNS_P5VS0_HDD
SMCISNS_PVDDQS3_DDR
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMCVSNS_CPUAXG
SMCISNS_CPUCORE
MAKE_BASE=TRUE
SMCISNS_CPUAXG
MAKE_BASE=TRUE
SMC_PJ2 SMC_PP0
MAKE_BASE=TRUE
SMCVSNS_GPUCORE
SMCVSNS_P12VG3H
MAKE_BASE=TRUE
SMC_ADC0
SMC_PN4
SMCISNS_P12VG3H
MAKE_BASE=TRUE
SMC_PM_G2_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMC_PN2
USB_SMC_N
SMC_PH2
SMC_TDO
PM_SLP_S3_L
SMC_RESET_L
CPU_PROCHOT_L
SMC_PROCHOT
CPU_PECI
=PP3V3_S0_SMC
MOJO_RX_L
SMC_PM_PCH_SYS_PWROK
SMC_CPU_CATERR_L
PM_PCH_SYS_PWROK
CPU_CATERR_L
MIN_LINE_WIDTH=0.4MM
PP3V3_G3H_AVREF_SMC
MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V
=PPVIN_G3H_SMCVREF
VOLTAGE=3.42V
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.4MM
PP3V42_G3H_SMC_SPVSR
SMC_MANUAL_RST_L
GND_SMC_AVSS
MIN_NECK_WIDTH=0.1MM VOLTAGE=0V
MIN_LINE_WIDTH=0.4MM
PWR_BTN
SMC_ASSERT_RTCRST
SMC_CLK32K
PM_CLK32K_SUSCLK_R
NO_TEST=TRUE
NC_SMC_PN7
MAKE_BASE=TRUE
NC_SMC_PP5
NO_TEST=TRUE
MAKE_BASE=TRUE
SMC_ADC17
CPU_THRMTRIP_L
SMC_ADC14
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SMC_PP7
SMC_EXTAL
SMBUS_SMC_4_ASF_SDA
NC_SMBUS_SMC_4_ASF_SDA
MAKE_BASE=TRUE
NO_TEST=TRUE
SMC_ADC22
SMC_TO_BLC_RX_L
SMC_ROMBOOT
SMC_THRMTRIP
NC_SMC_PME_S4_DARK_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SMBUS_SMC_4_ASF_SCL
NO_TEST=TRUE
MAKE_BASE=TRUE
=PPVCCIO_S0_SMC
MOJO_TX_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMBUS_SMC_5_G3H_SDA
SMC_PME_S4_DARK_L
SMC_DP_HPD_L
CPU_THRMTRIP_R_L
=PP3V3_S0_SMC
CPU_THRMTRIP_3V3
prefsb
051-9505
8.0.0
50 OF 144 48 OF 123
6
1
2
2
1
12
12
1
2
21
4
3
5
1
6
2
2
1
2
1
8
6
9
2
5
4
7
3
1
2
1
2
1
1
2
12
1 2
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
12
1
2
1 2
1 2
1 2 1 2
1 2 1 2 1 2 1 2
1 2
1 2
1 2
1 2
12
12
6
1
2
3
4
5
12
1
2
1
2
12
1
2
12
1
2
1
2
3
1
2
3
1
2
3
1
2
2
1
1 2
1
2
1 2
1 2
1
2
1 2
1 2
1 2
1 2
132
4
132
4
1 2
2
1
2
1
2
1
2
1
3
4
5
6
1
2
12
12
12
12
1 2
2
1
58
9
10
3
4
2
1
7
6
3
4
5
117
6
122
47 50
121
51
122
55
122
55
122
47 50
121
47
122
47
47
47
6
48
122
47
47
122
47 49
122
47 49
122
45 47 48
119
47 49
122
47 48 51 55
118
122
6
48
47
6
47 48 50
47
51
122
51
122
51
122
47
6
47 48 50
47
6
47 48 50
47
47
47
51
122
47
6
47
51
122
55
122
51
122
47
47 50 121
47
47
47
48
122
48
47
35 47
117
47
118
47
35
51
122
51
122
6
47 48 50
121
47
47
47
47
47
47
47
47
47
47
47
47
47
47
118
47
38 47 65
122
47 65
120
47 49
122
47 49
122
45 47 48
119
35 47
122
47
35 47
122
47
29 30 31 32 47
119
47 49
120
6
48 51 91
48
47
122
55
122
44
122
48
117
51
122
51
122
44
122
75
111
51
122
6
122
51
122
51
122
51
122
51
122
51
122
47
47
51
122
51
122
47
47
51
122
47 74
122
47
47
47 49
122
5
15 19 28 40 47 64
120
6
48 51 91
47
121
6
122
47 48 51 55
118
48
122
47
47
47
122
47 50 121
47
122
6
48
47
47
122
117
6
48 51 91
IN
OUT
IN
OUT
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
IN
IN
OUT
IN
IN
OUT
WP*
SI
HOLD*
VSS
SCK
CE*
VDD
SO
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
BI BI BI IN
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
998-4235
LPC+SPI Connector
MATT CONNECTOR
RDAR://11158919 D8:DETERMINE VALUE AND STUFF SERIES R FOR SPI BUS
SPI BootROM
RDAR://11364047 D8: CHANGE R5112 TO 100K FOR SPIROM_USE_MLB
RDAR://11379703 D8: MOVE MATT CARD POWER TO G3H
SPI Series Termination
47 48
122
47 48
122
26
117
21
119
18 47
105
26
105
47 48
122
47 48
122
48
122
47 48
122
47 48
122
47 48
122
19 26 47
119
18 47
119
49
105
49
105
47 48
120
49
105
48 49
105
48 49
105
1UF
10%
402
CERM
6.3V
C5110
64MBIT
OMIT_TABLE
SOIC
CRITICAL
SST25VF064C
U5110
MF-LF
1/16W
402
3.3K
5%
R5111
48 49
105
48 49
105
R5123
1/16W
PLACE_NEAR=J5100.11:5mm
5%
24
402
MF-LF
18
105
18
105
48 49
105
48 49
105
48 49
105
48 49
105
R5121
PLACE_NEAR=U1800.AR54:7MM
1/16W
15
MF-LF
402
5%
PLACE_NEAR=U1800.AU53:6MM
15
1/16W
5%
MF-LF
402
R5122
21 49
105
18
105
15
R5120
PLACE_NEAR=U1800.AT57:5mm
1/16W
402
MF-LF
5%
18
105
CRITICAL
LPCPLUS
M-ST-SM
DF40C-30DP-0.4V
J5100
18 47
105
18 47
105
18 47
105
49
105
21 49
105
18 47
105
PLACE_NEAR=J5100.12:5mm
1/16W MF-LF
5%
402
43
R5125
402
MF-LF
1/16W
PLACE_NEAR=J5100.14:5mm
5%
43
R5126
402
PLACE_NEAR=R5126.2:5mm
R5127
43
1/16W MF-LF
5%
43
MF-LF
PLACE_NEAR=R5125.2:5mm
402
5%
1/16W
R5128
PLACE_NEAR=U5110.2:5MM
R5130
402
1/16W MF-LF
5%
24
1%
PLACE_NEAR=R5124.2:5mm
54.9
R5129
402
MF-LF
1/16W
PLACE_NEAR=J5100.11:5mm
MF-LF
R5124
1% 1/16W
402
5% 1/16W
R5112
100K
MF-LF 402
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
SPI and Debug Connector
SPI_MLB_MISO
SPI_CS0_R_L
SPI_CLK_R
SPI_MOSI_R
SPI_MOSI
SPI_CS0_L
SPI_CLK
SPI_MISO
=PP3V3_G3H_LPCPLUS =PP5V_S0_LPCPLUS
LPC_CLK33M_LPCPLUS LPC_AD<0>
LPC_AD<2>
=PP3V3_S5_ROM
SPIROM_USE_MLB
SPI_MLB_MOSI
SPI_MLB_CLK
SPI_MLB_CS_L
SPI_ALT_MISO
SPI_ALT_CLK
SPI_ALT_MOSI
SPI_WP_L
LPC_SERIRQ
SMC_TCK
LPC_FRAME_L SPIROM_USE_MLB
SPI_ALT_MOSI
LPC_AD<3>
LPC_AD<1>
SMC_TX_L
DEBUG_RESET_L SMC_TDO
LPCPLUS_GPIO
TP_SMC_TRST_L TP_SMC_MD1
SPI_ALT_MISO
PM_CLKRUN_L SPI_ALT_CLK SPI_ALT_CS_L
LPC_PWRDWN_L SMC_TDI
SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TMS
SPI_MLB_MISO
SPI_MLB_CLK
SPI_MLB_CS_L
SPI_MLB_MOSI
SPI_ALT_CS_L
prefsb
051-9505
8.0.0
51 OF 144 49 OF 123
2
1
4
7
8
5
1 3
2
6
1
2
1
2
1 2
1 2
1 2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
3
1
5
9
7
15
11 13
17 19 21 23 25 27 29
31
32
33
34
1
2
1
2
1 2
1 2
1 2
1 2
1
2
1
2
105
105
105
6
6
6
49
105
49
105
49
105
49
105
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SMC (SMBus 3)
J2900 & J3000
radar://11669665
0x73 Read
TBT I2C will not be used in D8 0-ohm not stuffed and pullups stuffed
EMC1414-1:
I2C can be used as alternative to JTAG
Thunderbolt Router
U3600
addresses in 0b11111XXX are "reserved"
0xFF Write 0xFE Read
U6551
Mikey
UJ6500
U3401
Vref Control
0x76 Write 0x77 Read
U9700
0x30 Write 0x31 Read
U1800
PCH (SMBus)
U3400
VRef DACs
Memory Channel B
Memory Channel A
J3100 & J3200
0x99 Read
0xA0 Write
0xA2 Write
DIMM 0: 0xA1 Read
DIMM 2: 0xA3 Read
0xA4 Write
0xA6 Write 0xA7 Read
DIMM 1: 0xA5 Read
DIMM 3:
0x98 Write
Backlight Controller
PCH (SMLink 0)
U1800
PCH SMLink 0 is unused
0x6E Write 0x6F Read
SMC SMBus 4 is unused (reserved for ethernet LOM)
SMC (SMBus 5)
Temp Sensors "T2"
SMC SMBus 3 is reserved for SMC/PCH multi-master experiment
0x53 Read
D8 TCon has 2.2K pullup
K62 TCon has 4.7K pullup
Ambient Light Sensor
GK107:U8000 / GK104:UA000
0x6F Read
0x6E Write
J4200
Display TCon master
J9500 U9700
Backlight Controller
U4900
LCD remote IR temp
0x88 Write
0x93 Read
SMC SMBus 5 is unused
0x8A Write 0x8B Read
U5550
PCH PECI sensor data
PCH (SMLink 1)
U1800
J9500
0x98 Write
U5500
0x99 Read
U5500U4900
0x89 Read
GPU die temp
U4900
U4900
U4900
U5550
TMP421: 0x9F Read
0x1A Write 0x1B Read
0x9E Write
Panel/Vendor ID:
0x52 Write
SMC (SMBus 2)
U4900
0x9F Read
U5590
0x9E Write
SMC (SMBus 4)
0x92 Write
EMC1428-7:
Temp Sensors "T1"
SMC (SMBus 0)
SMC (SMBus 1)
0x95 Read
0x94 Write
J2500 & J2550
radar://11710650
XDP disconnected from I2C bus to reduce load
XDP
Display TCon slave
0x72 Write
China Headset
2.2K
1/16W
R5261
5%
402
MF-LF
R5260
2.2K
402
MF-LF
1/16W
5%
R5271
MF-LF 402
8.2K
5% 1/16W
8.2K
402
1/16W MF-LF
5%
R5270
2.2K
5%
402
1/16W MF-LF
R5201R5200
2.2K
5%
MF-LF
402
1/16W
2.2K
402
1/16W
5% MF-LF
R5211
2.2K
R5210
1/16W
5%
MF-LF
402
402
5% 1/16W MF-LF
R5221
2.2K
402
MF-LF
1/16W
5%
2.2K
R5220
R5241
NOSTUFF
1/16W
402
5%
MF-LF
4.7K
1/16W
R5240
NOSTUFF
402
4.7K
5%
MF-LF
2.2K
MF-LF
R5281
5%
402
1/16W
MF-LF
2.2K
402
5%
1/16W
R5280
5%
MF-LF
R5231
NOSTUFF
4.7K
402
1/16W
NOSTUFF
R5230
4.7K
402
1/16W MF-LF
5%
NOSTUFF
4.7K
R5251
5%
402
1/16W MF-LF
R5250
NOSTUFF
5%
4.7K
402
MF-LF
1/16W
5%
0
1/16W MF-LF
402
R5264
NOSTUFF NOSTUFF
1/16W
5%
0
402
MF-LF
R5265
0
402
5%
R5203
1/16W MF-LF
5%
R5202
0
1/16W MF-LF
402
402
1/16W
5%
0
MF-LF
R5262
402
1/16W
5%
MF-LF
0
R5263
R5282
1/16W
0
MF-LF
5%
402
0
MF-LF5%1/16W
R5283
402
NOSTUFF
R5233
1/16W
0
MF-LF
402
5%
NOSTUFF
R5232
402
MF-LF5%1/16W
0
NOSTUFF
5%
0
R5266
MF-LF
402
1/16W
NOSTUFF
0
R5267
MF-LF5%1/16W
402
3.3K
R5269
1/16W
5%
402
MF-LF
3.3K
1/16W
R5268
5%
MF-LF
402
R5275
2.2K
1/16W
5%
402
MF-LF
NOSTUFF
NOSTUFF
2.2K
402
MF-LF
1/16W
5%
R5274
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
SMBus Connections
=I2C_CHS_SCL
=I2C_CHS_SDA
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
SMBUS_PCH_CLK
=SMBUS_XDP_SCL
=SMBUS_XDP_SDA
SMBUS_PCH_CLK_R
MAKE_BASE=TRUE
SMBUS_PCH_DATA_R
MAKE_BASE=TRUE
=PP3V3_S0_SMBUS
=PP3V3_S0_SMBUS
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_2_S4_SDA
SMBUS_SMC_2_S4_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SCL
=SMB_SNS2_SCL
=PP3V3_S0_SMBUS_SMC
=SMB_SNS3_SCL
GPU_SMB_DAT_R
=PP3V3_S4_SMBUS_SMC
=SMB_ALS_SDA
=SMB_ALS_SCL
=SMB_SNS1_SCL
GPU_SMB_CLK_R
=PP3V3_S0_SMBUS_SMC
=PP3V3_S0_SMBUS_SMC
=I2C_TCON_SLA_SDA
=I2C_TCON_SLA_SCL
=SMB_SNS2_SDA
=SMB_SNS3_SDA
SML_PCH_1_DATA
SML_PCH_1_CLK
=PP3V3_S0_SMBUS_TCON
I2C_TCON_MAS_SCL SMB_TCON_BLC_SCL
SMB_TCON_BLC_SDA
=PP3V3_S0_SMBUS_SMC
I2C_TCON_MAS_SDA
SMBUS_SMC_3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_4_ASF_SCL
=PP3V3_G3H_SMC
SMBUS_SMC_5_G3H_SDA
SMBUS_SMC_5_G3H_SCL
=SMB_SNS1_SDA
SML_PCH_0_CLK
=PP3V3_S4_SMBUS
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SDA
=I2C_PCA9557D_SCL
SMB_PCH_BLC_SCL
SMB_PCH_BLC_SDA
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
=PP3V3_TBTLC_RTR
I2C_TBTRTR_SCL
I2C_TBTRTR_SDA
SML_PCH_0_DATA
prefsb
051-9505
8.0.0
52 OF 144 50 OF 123
121
2
121
2
121
2
121
2
121
2
121
2
121
2
121
2
121
2
121
2
121
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
121
2
121
2
60
60
18 121
18 121
25
25
121
121
6
50
6
50
47
121
47
121
47
121
47
121
47
121
47
121
53
6
50
53
91 112
6
42
42
53
91 112
6
50
6
50
78
78
53
53
18 122
18 122
6
78 118
80 114
80 114
6
50
78 118
47
121
47
121
47 48 121
47 48 121
6
47 48
47 48 121
47 48 121
53
18 122
6
29 30
29 30
31 32
31 32
34
34
34
34
80 114
80 114
60
60
6
15 36 37 38
36
111
36
111
18 122
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V+
REFIN+
IN-
OUT
GND
OUT
OUT
OUT
V+
REFIN+
IN-
OUT
GND
OUT
OUT
V+
REFIN+
IN-
OUT
GND
OUT
OUT
OUT
V+
REFIN+
IN-
OUT
GND
V+
REFIN+
IN-
OUT
GND
GND
IN+ IN-
OUT
GND
IN+ IN-
OUT
OUT
OUT
IN
OUT
IN-
IN+ REF
V+
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ADC 0/1 12V G3H (ID2R/VD2R)
AC/DC CURRENT SENSOR TO 100V/V: RDAR://10645440
CPU VDD (DDR3) lowside sense
GK104:
ADC12/13 CPUAXG IMON S0 (VC0G/IC0G)
PEAK: 35.0 A
OpAmp Gain = 3.1 V/V
ADC 4/5 CPU DDR3 S0 (IC0M/VC0M)
SCALE:141 A
PEAK: 4.75 A SCALE:6.60 A
SCALE:141 A
ADC 6/7 SODIMM DDR3 S3 (IM0R/VM0R)
TDP: 10.0 A
SCALE:41.4 A
AC/DC lowside sense (System total)
Gain: 500 V/V
ADC20/21 SSD 3.3V S0 (IH1R/VR3R)
ADC 16/17 PCH 1.05V S0 (IN1R/VN1R)
OpAmp Gain = 3.1 V/V
(radar://problem/1056794)
SCALE:8.25 A
PEAK: 2.0 A
PEAK: 1.2 A
Gain: 200 V/V
353S2073
GK107:
353S2216
PEAK: 5.93 A TDP: 4.45 A
353S3597
SCALE:3.3 A
TDP: 0.5 A
TDP: 1.25 A
Gain: 200 V/VGain: 500 V/V
353S2073 Gain: 200 V/V
PEAK: 3.0A
TDP: 63 A
DIMM 1.5V lowside sense
353S2216
PCH Vcc 1.05V lowside sense
SCALE:3.3 A
TDP: 25.0 A
PEAK: 11.3 A
NOTE, MUST KEEP 5V OUT BELOW 3.3V
VMAX = 0.9V @ 120 A
PEAK: 120 A TDP: 95 A
PEAK: 30 A TDP: 24 A
HIGHSIDE SENSE FOR HDD 12V
353S2073
Current sense of SSD 3.3V FET
Voltage sense of 3.3V S0
SCALE:3.3 A
TDP: 0.8 A
GPU Core
PEAK: 112 A
TDP: 2.1 A
CPU VCCore
353S2073 Gain: 200 V/V
Gain: 200 V/V
VMax = 0.9V @ 35A
VR IMON SCALE TENTATIVE
SCALE:13.2 A
GAIN: 100 V/V
353S2208
OpAmp Gain = 3.1 V/V
Highside sense for HDD 5V
CPU VCCAXG
SCALE:142 A
ADC 10/11 CPUCORE IMON S0 (VC0C/IC0C)
TDP: 1.76 A
PEAK: 2.35 A
GPU FB highside sense
ADC 2/3 GPUCORE IMON S0 (IG0C/VG0C)
SCALE:33 A
TDP: 25 A
VMax = 0.9V @ 120A
SCALE:3.30 A
ADC 9 FBVDDQ 12V S0 (IG0F)
ADC14/15 HDD 5V S0 (VH05/IH05)
ADC18 HDD 12V S0 (IH02/VH02)
48
122
U4900.E2:10mm
0.1UF
CERM
10V
C5302
20%
402
48
122
C5303
6.3V X5R
0.22UF
402
20%
U4900.E1:10mm
1/16W
1%
MF-LF
R5301
402
U4900.E2:10mm
10K
6
MF-LF
1%
402
1/16W
R5303
4.53K
U4900.E1:10mm
20%
402
X5R
0.22UF
6.3V
C5300
R5302
MF-LF
3.32K
1/16W
1%
402
U4900.E2:10mm
U5325
OPA348 SC70-5
CRITICAL
R5327
1/16W
1%
21K
MF-LF
402
402
1%
MF-LF
1/16W
10K
R5325
5%
MF-LF
1/16W
R5329
U4900.A6:10mm
5.1K
402
MF-LF
10K
1/16W
402
1%
R5326
48
122
66
109
48
122
20% X5R
402
6.3V
C5328
0.22UF
U4900.B6:10mm
402
4.53K
1%
1/16W
R5328
U4900.B6:10mm
MF-LF
48
122
48
122
402
6.3V
U4900.C1:10mm
0.22UF
X5R
20%
C5333
4.53K
1/16W
1%
MF-LF
402
R5333
U4900.C1:10mm
402
R5334
5.1K
5% 1/16W MF-LF
U4900.C2:10mm
402
MF-LF
1/16W
1%
R5332
21K
10K
402
1/16W
1%
MF-LF
R5330
SC70-5
CRITICAL
OPA348
U5330
R5331
MF-LF
10K
1/16W
1%
402
66
109
48
122
48
122
U4900.B3:10mm
R5312
4.53K
1/16W
1%
MF-LF
402
6.3V
402
X5R
20%
U4900.B3:10mm
C5312
0.22UF
1/16W
U4900.A3:10mm
1%
MF-LF
R5313
4.53K
402
U4900.A3:10mm
X5R
6.3V
402
0.22UF
C5313
20%
0.22UF
402
20% X5R
6.3V
C5310
48
122
48
122
U4900.B1:10MM
0.22UF
20%
402
X5R
6.3V
C5337
U4900.B1:10MM
6.65K
1/16W 402
MF-LF
1%
R5337
U4900.B2:10MM
1%
402
1/16W MF-LF
4.53K
R5338
U4900.B1:10MM
1%
MF-LF
402
1/16W
R5336
4.53K
6
U4900.B2:10MM
20%
0.22UF
6.3V
402
X5R
C5338
6
R5310
1%
MF-1
1W
0.001
0612
48
122
U4900.B4:10MM
C5317
0.22UF
402
X5R
20%
6.3V
U4900.B4:10MM
R5317
1/16W
1%
MF-LF
402
4.53K
6
48
122
6.3V X5R 402
20%
U4900.A4:10MM
0.22UF
C5318
U4900.A4:10MM
R5318
4.53K
MF-LF
1%
402
1/16W
0.22UF
6.3V
20% X5R
402
C5315
R5315
0.0005
MF
0612
1W
1%
48 122
1%
R5323
U4900.A5:10MM
1/16W
402
MF-LF
4.53K
6
6.3V
20%
C5320
0.22UF
402
X5R
20%
6.3V X5R
C5323
0.22UF
402
U4900.A5:10MM
U5320
SC70
INA210
48
122
U4900.G2:10MM
X5R
C5342
0.22UF
20%
6.3V 402
R5342
U4900.G2:10MM
1/16W
1%
MF-LF
402
4.53K
6
48
122
20%
6.3V
402
X5R
C5343
0.22UF
U4900.G1:10MM
U4900.G1:10MM
MF-LF
1/16W
402
1%
4.53K
R5343
20%
6.3V
402
X5R
C5340
0.22UF
R5340
1W
MF-1
1%
0.002
0612
INA210
SC70
U5340
48
122
U4900.H1:10MM
C5348
X5R 402
6.3V
0.22UF
20%
R5348
4.53K
MF-LF
402
1%
U4900.H1:10MM
1/16W
6
20% X5R
402
6.3V
C5345
0.22UF
SC70
U5345
INA210
48
122
1%
MF-LF
402
1/16W
4.53K
R5351
U4900.B7:10MM
48
122
C5352
U4900.B7:10MM
X5R 402
20%
0.22UF
6.3V
U4900.A7:10MM
C5353
20%
0.22UF
6.3V
402
X5R
1%
402
MF-LF
1/16W
4.53K
R5353
U4900.A7:10MM
6
0.002
MF
1%
R5350
0612
1W
INA211
SC70
U5310
INA211
SC70
U5315
WCSP-4
U5350
INA216A4YFFX
WCSP-4
U5335
INA216A4YFFX
R5316
0
1/16W
5%
MF-LF
402
NOSTUFF
5%
0
R5319
1/16W MF-LF
402
402
1%
R5308
1/16W
U4900.F2:10mm
MF-LF
4.53K
48
122
48
122
402
20%
C5308
6.3V X5R
U4900.F2:10mm
0.22UF
1/16W
5.1K
5%
402
MF-LF
R5309
U4900.F1:10mm
CRITICAL
SC70-5
OPA348
U5305
1/16W MF-LF
1%
402
10K
R5305
21K
R5307
MF-LF
1%
402
1/16W
1%
402
1/16W
10K
MF-LF
R5306
96
115
INA214
U5300
SC70
U4900.F1:10mm
0402
X5R-CERM
6.3V
10%
0.22UF
C5309
U4900.A6:10MM
C5329
0.22UF
10%
6.3V X5R-CERM 0402
0402
X5R-CERM
6.3V
10%
C5334
U4900.C2:10MM
0.22UF
20%
0.01UF
0402
C5305
X7R-CERM
16V
C5325
20%
0.01UF
X7R-CERM
16V 0402
0402
C5330
16V X7R-CERM
0.01UF
20%
0612-2
R5320
1% 1W MF
0.005
0612-2
1% 1W MF
0.005
R5335
0612-2
1% 1W MF
0.005
R5345
MF-1
1W
1%
0612
0.001
R5300
I and V Sense 1
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
ISNSA_P12VS0_HDD_N
ISNSA_P12VS0_HDD_P
PP12V_S0_HDD_SNS
=PP12V_S0_HDD_PWR
ISNSA_P1V05S0_PCH_P
ISNSA_P12VS0_FBVDDQ_P
ISNSA_P5VS0_HDD_N
ISNSA_P5VS0_HDD_P
PP5V_S0_HDD_SNS
=PP5V_S0_HDD_PWR
ISNSA_P12VS0_FBVDDQ_N
PP12V_S0_FBVDDQ_SNS
=PP12V_S0_FBVDDQ_PWR
=PP12V_S5_SNS
SMCVSNS_P12VG3H
=PP5V_S0_ISENSE
=PP5V_S0_ISENSE
=PP5V_S0_ISENSE
ISNS_GPUCORE_FB
GND_SMC_AVSS
ISNS_CPUCORE_FB
GND_SMC_AVSS
ISNS_CPUAXG_FB
=PPVCORE_S0_GPU
=PP3V3_S5_SENSE
ISNS_P12VG3H_R
PPVDDQ_S3_DDR_SNS
SMCVSNS_P1V5S0_CPU_MEM
=PP3V3_S0_SENSE
ISNS_P12VS0_FBVDDQ_R
=PP3V3_S0_SMC
ISNS_P12VS0_HDD_R
GND_SMC_AVSS
ISNS_P3V3S0_SSD_R
ISNSA_P3V3S0_SSD_N
GND_SMC_AVSS
GND_SMC_AVSS
=PP3V3_S0_SSD_PWR
ISNSA_P3V3S0_SSD_P
GND_SMC_AVSS
SMCVSNS_GPUCORE
=PP3V3_S4_SENSE
ISNSA_PVDDQS3_DDR_N
ISNS_PVDDQS3_DDR_R
SMCVSNS_PVDDQS3_DDR
=PP3V3_S0_SENSE
SMCISNS_P12VS0_FBVDDQ
SMCVSNS_P1V05S0_PCH
SMCISNS_P1V05S0_PCH
SMCISNS_PVDDQS3_DDR
SMCISNS_P1V5S0_CPU_MEM
GND_SMC_AVSS
VR_GPU_IMON
ISNSA_P1V5S0_CPU_MEM_N
ISNSA_P1V05S0_PCH_N
=PP1V05_S0_PCH_PWR
ISNS_CPUCORE_N
ISNSA_P1V5S0_CPU_MEM_P
ISNS_GPUCORE_P ISNS_CPUCORE_P
REG_CPUCORE_IMON
PP1V05_S0_PCH_SNS
GND_SMC_AVSS
GND_SMC_AVSS
GND_SMC_AVSS
SMCISNS_P12VS0_HDD
SMCVSNS_P3V3S0
=PP3V3_S0_SENSE
ISNS_CPUAXG_P
SMCISNS_P5VS0_HDD
ISNS_P5VS0_HDD_R
=PPVDDQ_S3_DDR_PWR
GND_SMC_AVSS
=PP3V3_S0_SENSE
ISNS_P1V05S0_PCH_R
=PP3V3_S0_SENSE
GND_SMC_AVSS
GND_SMC_AVSS
SMCISNS_P3V3S0_SSD
GND_SMC_AVSS
GND_SMC_AVSS
=PP1V5_S0_CPU_MEM_PWR
GND_SMC_AVSS
PP3V3_S0_SSD_SNS
SMCISNS_P12VG3H
GND_SMC_AVSS
REG_CPUAXG_IMON
ISNS_CPUAXG_N
GND_SMC_AVSS
ISNSA_PVDDQS3_DDR_P
ISNS_P1V5S0_CPU_MEM_R
GND_SMC_AVSS
SMCVSNS_P5VS0_HDD
SMCVSNS_CPUCORE=PPVCORE_S0_CPU
PP1V5_S0_CPU_MEM_SNS
ISNS_GPUCORE_N
=PPVAXG_S0_CPU
SMCISNS_GPUCORE
SMCVSNS_CPUAXG
SMCISNS_CPUCORE
SMCISNS_CPUAXG
GND_SMC_AVSS
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP3V3_PVDDQS3_ISNS
=PP12V_G3H_PWR
PP12V_G3H_SNS
ISNSA_P12VG3H_P
ISNSA_P12VG3H_N
prefsb
051-9505
8.0.0
53 OF 144 51 OF 123
2
1
2
1
1 2
1 2
2
1
1
2
4
1
3
5
2
1 2
1 2
1 2
1
2
2
1
1 2
2
1
1 2
1 2
1 2
1 2
4
1
3
5
2
1
2
1 2
2
1
1 2
2
1
2
1
2
1
1
2
1 2
1 2
2
1
43
21
2
1
1 2
2
1
1 2
2
1
43
21
1 2
2
1
2
1
2
3
14
5
6
2
1
1 2
2
1
1 2
2
1
43
21
2
3
14
5
6
2
1
1 2
2
1
2
3
14
5
6
1 2
2
1
2
1
1 2
43
21
2
3
14
5
6
2
3
14
5
6
B2
B1
A1
A2
B2
B1
A1
A2
1 2
1 2
1 2
2
1
1 2
4
1
3
5
2
1 2
1 2
1
2
6
5
4 1
3
2
2
1
2
1
2
1
2
1
2
1
2
1
43
21
43
21
43
21
43
21
118
118
6
119 118
119
119
6
118
6 6
6
51
6
51
6
51
119
47 48 51 55
118
119
47 48 51 55 118
119
6
93
6
119
6
51 52
53 55
119
6
48 91
119
47 48 51 55 118
119
119
47 48 51 55
118
47 48 51 55
118
6
119
47 48 51 55
118
6
119
119
6
51 52
53 55
47 48 51 55
118
119
119
6
119
119
119 119
47 48 51 55 118
47 48 51 55
118
47 48 51 55
118
6
51 52
53 55
119
119
6
47 48 51 55
118
6
51 52
53 55
119
6
51 52
53 55
47 48 51 55
118
47 48 51 55
118
47 48 51 55
118
47 48 51 55 118
6
47 48 51 55
118
47 48 51 55
118
119
47 48 51 55
118
119
119
47 48 51 55 118
6
13 16 66
119
6
13
17 66
47 48 51 55 118
6
118
118
G
D
S
OUT
NC
VCC+
GND
IN
D
SG
D
SG
GND
VDD
D
SON
CAP
IN
OUT
OUT
NC
THRM
GND
PG
ON
NC
D1
D2
G
VCC
PAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(max 2.8A,ave 0.6A)
HDD Out-of-Band Temp Sensing
353S3672
REMOVE R5413 AND SHORT R5412 AFTER HDD_PWR_EN WORKS
(PULL UP TO 3V3_S5 INSIDE PCH)
for Test Only
4AMP,
Input: 2.4V to 5.5V
12mOhm
376S0910
HDD 12V_S0 FET
(max 0.7A,ave 0.3A)
353S3098
4nF = 2.3V/ms Ramp Rate
Drive asleep: HDD drives HDD_OOB_TEMP low
Drive active: Valid signal protocol
Notes:
From drive:
0.0V to 0.3V
1.2V to 2.0V
Low: High:
Node is at 1.5V
R5413 is no stuff
HDD 5V_S0 FET
Drive disconnected: Pulled high
Trip is 1.0V
Temperature read from SATA power connecter pin 11
603
0.1UF
CERM
20% 16V
C5420
CRITICAL
Q5410
IRFH3702TRPBF
PQFN
44
121
R5412
0
5%
1/16W
MF-LF
402
LMV331
U5400
CRITICAL
SC70-5
R5400
MF-LF
1/16W
1%
402
R5401
MF-LF
1/16W
1%
402
21
118
R5413
NOSTUFF
1/16W MF-LF
1%
402
Q5420
SSM6N15AFE
SOT563
CRITICAL
402
MF-LF 1/16W
5%
10K
R5421
CRITICAL
SOT563
SSM6N15AFE
Q5420
SLG5AP304V
U5420
TDFN
CRITICAL
10% CERM
25V 0402
C5421
0.0047UF
0402
X7R-CERM
16V
10%
0.1UF
C5400
0402
X7R-CERM
10%
0.1UF
C5401
16V
R5403
402
3.3K
1/16W MF-LF
5%
R5402
180K
1/16W MF-LF
5%
402
R5404
402
MF-LF
1/16W
5%
150K
MF-LF
1/16W
5%
1K
R5405
402
44
122
47
122
44
120
C5410
1UF
X5R
10%
603
16V
U5410
SLG5AP026
TDFN
CRITICAL
MF-LF
1/10W
5%
100
603
R5410
HDD/SSD Temp Sense
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
=PP3V3_S0_SENSE
HDD_OOB_1V00_REF
SMC_OOB1_RX_L
=PP5V_S0_HDD
HDD_PWR_EN_R
HDD_PWR_EN_L
SMC_OOB1_RX_FILT
SMC_OOB1_RX_R
PP12V_S0_HDD_FET
FET_HDD_SLGSW
HDD_12V_S0_GATE
=PP12V_S0_HDD
HDD_PWR_EN
=PP3V3_S0_SENSE
PP5V_S0_HDD_FET
HDD_PWR_EN_R
HDD5V_RAMP_CAP
prefsb
051-9505
8.0.0
54 OF 144 52 OF 123
2
1
5
1
4
1 2
5
4
2
3
1
1
2
1
2
1
2
6
1
2
1
2
3
4
5
8 1
3
52
7
2
1
2
1
2
1
1 2
1
2
1
2
1
2
2
1
9
4
8
2
3
5
6
7
1
1 2
6
51 52 53 55
118
6
52
118
118 122
118
118
6
6
51 52 53 55
IN IN
IN
BI
NC
ALERT*
THERM*/ADDR
DP1
SMCLK
SMDATA
VDD
DN1
DP2/DN3
DN2/DP3
GND
AGNDDGND
SCL
SDA
ADR0 ADR1
DRDY*
V+
IN
BI
BI
IN
VDD
DP6/DN7 DN6/DP7
DN4/DP5
DP2/DN3 DN2/DP3
DP4/DN5
DN1
DP1
THRM_PAD
GND
NC
TRIP/SET
SMDATA
SMCLK
SYS_SHND*
ALERT*
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
Temperature Sensor T1 EMC1414: Near PSU Conn
Make sure these caps are OK with U5500 Vendor!
NOTE - Follow TI layout guide(SBOU108.pdf) for this part!!!
Temperature Sensor T3: LCD Remote Sensor(Dev4Now)
I2C Address (TMP006):
SNS T2: TEMP SENSOR IC
MLB Prox 2 (Tm1p)
EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93
AC/DC
Via connector to diode inside PSU
Temperature Sensor T2 EMC1428: Near GPU VR
will be used as MLB sensor.
AC/DC (Tp2p)
LCD Skim (TL2p)
CPU Prox (TC0p)
BLC Proximity
0x8A (Write) 0x8B (Read)
I2C Address (EMC1414-1):
0x98 (Write) 0x99 (Read)
Internal sensor of the EMC 1414
Note:
518S0698
Skin
Skin Temp (TS0p)
MLB Prox 1 (Tm0p)
CPU Proximity
Ambient
GPU Proximity
Set trip point to 125 C.
SO-DIMM Proximity 1
SO-DIMM Proximity 2
SO-DIMM Proximity 3
SO-DIMM Proximity 4
Ambient (TA0p)
GPU Prox (TG0p)
SoDIMM Prox 1 (TM0p)
SoDIMM Prox 3 (TM2p)
BLC PROX (Tb0p)
SoDIMM Prox 2 (TM1p)
SoDIMM Prox 4 (TM3p)
Q5550.3:2MM
C5550
+/-0.25PF
2.2PF
402
C0G-CERM
50V
1UF
X5R
10V
10%
402-1
C5500
L5510.2:2MM
10% 50V CERM
0.0022UF
402
C5510
J601.3:21MM
L5510
FERR-220-OHM
0402
FERR-220-OHM
0402
L5511
J601.4:20MM
6
122
6
122
Q5570.3:2MM
2.2PF
C0G-CERM
SIGNAL_MODEL=EMPTY
+/-0.25PF 50V
402
C5570
C0G-CERM
+/-0.25PF
C5505
2.2PF
Q5505.3:2MM
402
50V
SIGNAL_MODEL=EMPTY
1/16W
R5500
402
MF-LF
5%
10K
50
50
Q5550
DFN1006H4-3
BC846BLP
PLACEMENT_NOTE=Place Q5550 near GPU and GDDR5
TEMPSNSDEV
L5500.2:2MM
0.0022UF
C5501
SIGNAL_MODEL=EMPTY
CERM 402
50V
10%
TEMPSNSDEV
J5500.1:15MM
0402
FERR-220-OHM
L5500
TEMPSNSDEV
J5500.2:15MM
0402
FERR-220-OHM
L5501
TEMPSNSDEV
SILK_PART=SkinTemp
CRITICAL
53780-8602
M-RT-SM
J5500
2.2PF
Q5560.3:2MM
C5560
50V C0G-CERM
+/-0.25PF
402
BC846BLP
DFN1006H4-3
Q5560
PLACEMENT_NOTE=Place Q5560 near BLC VR
Q5570
BC846BLP
DFN1006H4-3
PLACEMENT_NOTE=Place Q5570 near SO-DIMM connectors (top left)
Q5505
PLACEMENT_NOTE=PLACE Q5505 NEAR CPU
DFN1006H4-3
BC846BLP
U5500
PLACEMENT_NOTE=PLACE U5500 NEAR PSU CONNECTOR
EMC1414-1-AIZL
MSOP
J601.4:30MM
TEMPSNSDEV
TMP0006AIYZER
WCSP
U5590
50
50
TEMPSNSDEV
10K
R5590
MF-LF 402
1/16W
5%
402
CERM
50V
5%
47PF
NOSTUFF
C5503
U5500.5:2MM
47PF
402
U5500.4:2MM
NOSTUFF
5%
CERM
50V
C5502
1/16W MF-LF
20K
5%
402
R5552
5%
10K
MF-LF
1/16W
R5551
402
50
50
1%
6.81K
402
1/16W MF-LF
R5550
X5R
402-1
10V
1UF
10%
C5559
PLACEMENT_NOTE=PLACE U5550 NEAR GPU VR TO GET GPU VR PROX TEMP
EMC1428-7
U5550
CRITICAL
QFN
OMIT
XW5505
SM
SM
OMIT
XW5504
SM
OMIT
XW5503
OMIT
XW5502
SM
SM
XW5501
OMIT
OMIT
SM
XW5500
2.2PF
C5555
50V C0G-CERM 402
+/-0.25PF
Q5555.3:2MM
DFN1006H4-3
BC846BLP
Q5555
PLACEMENT_NOTE=Place Q5555 near bottom of board
Q5575.3:2MM
SIGNAL_MODEL=EMPTY
2.2PF
50V C0G-CERM
+/-0.25PF
402
C5575
PLACEMENT_NOTE=Place Q5575 near SO-DIMM connectors (top right)
Q5575
BC846BLP
DFN1006H4-3
SIGNAL_MODEL=EMPTY
Q5580.3:2MM
C0G-CERM 402
50V
+/-0.25PF
2.2PF
C5580
Q5580
BC846BLP
DFN1006H4-3
PLACEMENT_NOTE=Place Q5580 near SO-DIMM connectors (bottom left)
C5585
SIGNAL_MODEL=EMPTY
Q5585.3:2MM
50V
2.2PF
C0G-CERM
+/-0.25PF
402
PLACEMENT_NOTE=Place Q5585 near SO-DIMM connectors (bottom right)
Q5585
BC846BLP
DFN1006H4-3
X7R-CERM
0.01UF
C5590
TEMPSNSDEV
0402
16V
10%
SIGNAL_MODEL=EMPTY
0.0022UF
C5552
CERM
50V
10%
402
U5550.15:10MM
C5554
SIGNAL_MODEL=EMPTY
10% 50V
CERM
0.0022UF
402
U5550.10:10MM
U5550.10:5MM
SIGNAL_MODEL=EMPTY
C5556
0.0022UF
CERM
50V
10%
402
ALL
Alternate Temp Diode
372S0185372S0186
SYNC_MASTER=D8_MLB
Temperature Sensors
SYNC_DATE=08/27/2012
TSNS_2_2_N
TSNS_2_5_P
TSNS_2_5_N
TSNS_2_7_P
TSNS_2_7_N
TSNS_2_7_N
TSNS_2_7_P
TSNS_2_6_P
TSNS_2_5_N
TSNS_2_5_P
TSNS_2_4_P
TSNS_2_4_N
TSNS_2_3_P
TSNS_2_3_N
TSNS_2_2_P
TSNS_2_1_P
TSNS_2_1_N
TSNS_1_2_N
MAKE_BASE=TRUE
TSNS_1_2_P
TSNS_1_3_P
=SMB_SNS2_SDA
TSNS_2_ALERT_L
TSNS_1_ALERT_L =SMB_SNS1_SDA
TSNS_1_1_N
TSNS_1_1_P
TSNS_3_DRDY_L
TSNS_SKIN_P
TSNS_1_1_P
=SMB_SNS3_SDA
TSNS_1_1_N
TSNS_1_3_N
TSNS_1_3_P
TSNS_ACDC_N
TSNS_1_3_N
=SMB_SNS1_SCL
TSNS_2_ADDR
=SMB_SNS2_SCL
TSNS_2_TRIPSET
TSNS_ACDC_P
TSNS_1_2_N
TSNS_1_2_P
MAKE_BASE=TRUE
TSNS_2_3_N TSNS_2_3_P
=PP3V3_S0_SENSE
TSNS_2_4_P
TSNS_2_6_N
TSNS_2_4_N
TSNS_2_2_N
TSNS_2_2_P
TSNS_2_1_N
TSNS_2_1_P
TSNS_SKIN_N
TSNS_2_6_N
=PP3V3_S0_SENSE
=SMB_SNS3_SCL
=PP3V3_S0_SENSE
TSNS_2_6_P
prefsb
051-9505
8.0.0
55 OF 144 53 OF 123
2
1
2
1
2
1
21
21
2
1
2
1
1
2
3
2
1
2
1
21
21
4
2
1
3
2
1
3
2
1
3
2
1
3
2
1
8
72
10
9
1
3
4
5
6
A2
A1
B3
C3 C1
B1
C2
A3
1
2
2
1
2
1
1
2
1
2
1
2
2
1
16
15 14
9
3 4
10
2
1
17
8
13
5
11
12
6
7
2
1
2
1
2
1
2
1
2
1
2
1
2
1
3
2
1
2
1
3
2
1
2
1
3
2
1
2
1
3
2
1
2
1
1 2
1 2
1 2
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
53
122
6
51 52 53 55
53
122
53
122
53
122
53
122
53
122
53
122
53
122
122
53
122
6
51 52 53 55
6
51 52 53 55
53
122
IN
IN
OUT
OUT
D
GS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
12V DC
Otherwise, this is simply a pass-FET.
FET input.
there is a pull-up, going to a Hi-Z
See RADAR: 10565825- D7: Need scematic and PCB file of fan(All Vendors).
when Q5610 is on.
Note:
It is assumed there is a pull-up to
The circuit for the PWM input to
level-shifter to protect the SMC.
This resembles an open-drain if
at common and the SMC sinks current
definition, the drain of Q5610 is
present on the SMC pin! Then by
the fan acts as a non-inverting
turns on, there would be 5V/12V
when the SMC PWM goes low and Q5610
5V/12V inside the fan, otherwise
Tach GND
518S0730
SMC Fan 0 (System)
SMC Fan 1 (Unused)
0603
220-OHM-1.4A
CRITICAL
L5600
0402
X7R-CERM
20% 16V
0.01UF
C5601
16V 1206-1
CERM
20%
4.7UF
C5600
47
122
M-RT-SM
53780-8604
CRITICAL
J5600
47
47
FERR-220-OHM
0402
L5620
CRITICAL
FERR-220-OHM
0402
CRITICAL
L5610
0402
100PF
5% 50V CERM
C5610
47K
402
5% 1/16W MF-LF
R5626
R5625
402
47K
1/16W MF-LF
5%
47
122
402
5% MF-LF
1/16W
10K
R5610
VESM
SSM3K15AMFVAPE
CRITICAL
Q5610
0201
X7R-CERM
16V
U4900.L13:5MM
1000PF
C5690
10%
C5620
100PF
CERM
50V
5%
0402
SYNC_MASTER=D8_MLB
System Fan
SYNC_DATE=08/27/2012
SMC_FAN_0_TACH FAN_0_TACH_FET
PP12V_S0_FAN_0_FILT
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V
FAN_0_PWM_FET
=PP12V_S0_FAN
SMC_FAN_1_CTL
NC_SMC_FAN_1_TACH
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
NO_TEST=TRUE
SMC_FAN_1_TACH
=PP3V3_S0_FAN
SMC_FAN_0_CTL
=PP3V3_S0_FAN
MIN_LINE_WIDTH=0.5MM
FAN_0_PWM_FILT
MIN_NECK_WIDTH=0.25MM
FAN_0_TACH_FILT
prefsb
051-9505
8.0.0
56 OF 144 54 OF 123
21
2
1
2
1
5
1 2
4
6
3
21
21
2
1
1
2
1 2
1
2
1
2
3
2
1
2
1
118
120
118
6
6
54
6
54
118
118
OUTOUT
V+
REFIN+
IN-
OUT
GND
OUT
V+
REFIN+
IN-
OUT
GND
OUT
OUT
OUT
V+
REFIN+
IN-
OUT
GND
OUT
OUT
V+
REFIN+
IN-
OUT
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
ADC23 CPU VCCIO 12V S0 (IC0I)
SCALE:3.30 A
PEAK: 0.83 A
TDP: 0.15 A
TDP: 0.83 A
353S2073 Gain: 200 V/V
Gain: 200 V/V
353S2073 Gain: 200 V/V
TDP: 0.15 A
SCALE:1.65 A
PEAK: 0.46 A
ADC8 PCH/GPU/TBT 1V05 12V S0 (IR1R)
Gain: 200 V/V
353S2073
353S2073
ADC19 AP 3.3V S4 (IW0R)
SCALE:1.65 A
PEAK: 1.0 A
PEAK: 0.86 A
Current sense of AP 3.3V FET
ADC22 CPU VCCSA 12V S0 (IC0S)
SCALE:1.65 A
TDP: 0.4 A
48
122
U4900.H2:10MM
C5904
0.22UF
X5R 402
6.3V
20%
OMIT_TABLE
R5904
U4900.H2:10MM
DEVELOPMENT
402
1/16W
4.53K
MF-LF
1%
6
DEVELOPMENT
C5900
X5R 402
6.3V
20%
0.22UF
SC70
U5900
DEVELOPMENT
INA210
48
122
X5R 402
6.3V
0.22UF
20%
C5914
U4900.A8:10MM
4.53K
1/16W MF-LF
402
1%
R5914
U4900.A8:10MM
402
0.22UF
6.3V
20% X5R
C5910
INA210
U5910
SC70
6
48
122
X5R 402
6.3V
0.22UF
20%
C5909
U4900.B8:10MM
R5909
U4900.B8:10MM
4.53K
1/16W MF-LF
402
1%
6
402
X5R
6.3V
C5905
0.22UF
20%
SC70
INA210
U5905
48
122
402
1%
MF-LF
4.53K
R5919
1/16W
U4900.A5:10MM
6
6.3V
20%
0.22UF
X5R 402
C5919
U4900.A5:10MM
6.3V
20%
402
X5R
0.22UF
C5915
INA210
SC70
U5915
1206-1
MF
1/2W
0.010
1%
R5915
R5900
MF
1/2W
1%
1206-1
0.010
1206-1
MF
1/2W
0.010
1%
R5905
R5910
0612-2
MF
1W
1%
0.005
132S0080
1
CAP,0.22UF,402
C5904
DEVELOPMENT
1
RES,0,OHM,402
116S0004
C5904
PRODUCTION
SYNC_DATE=08/27/2012
I and V Sense 2
SYNC_MASTER=D8_MLB
PP12V_S0_REG_CPU_VCCSA_SNS
ISNS_P3V3S4_AP_R
GND_SMC_AVSS
SMCISNS_P3V3S4_AP
PP3V3_S4_AP_SNS
=PP3V3_S0_SENSE
ISNSA_P3V3S4_AP_N
ISNSA_P12VS0_CPU_VCCSA_N
ISNSA_P12VS0_CPU_VCCSA_P
=PP12V_S0_REG_CPU_VCCSA_PWR
ISNSA_P3V3S4_AP_P
=PP3V3_S4_AP_PWR
ISNSA_P12VS0_P1V05_N
ISNSA_P12VS0_P1V05_P
PP12V_S0_REG_P1V05_SNS
=PP12V_S0_REG_P1V05_PWR
=PP3V3_S0_SENSE
ISNS_P12VS0_P1V05_R
ISNS_P12VS0_CPU_P1V05_R
GND_SMC_AVSS
SMCISNS_P12VS0_P1V05
SMCISNS_P12VS0_CPU_VCCSA
=PP3V3_S0_SENSE
GND_SMC_AVSS
SMCISNS_P12VS0_CPU_P1V05
GND_SMC_AVSS
=PP3V3_S0_SENSE
ISNS_P12VS0_CPU_VCCSA_R
=PP12V_S0_REG_CPU_P1V05_PWR
PP12V_S0_REG_CPU_P1V05_SNS
ISNSA_P12VS0_CPU_P1V05_P
ISNSA_P12VS0_CPU_P1V05_N
prefsb
051-9505
8.0.0
59 OF 144 55 OF 123
2
1
1 2
2
1
2
3
14
5
6
2
1
1 2
2
1
2
3
14
5
6
2
1
1 2
2
1
2
3
14
5
6
1 2
2
1
2
1
2
3
14
5
6
43
21
43
21
43
21
43
21
119
47 48 51 55
118
6
51 52
53 55
119
118
118
6
119
6
119
119
6
6
51 52
53 55
119
119
47 48 51 55
118
6
51 52
53 55
47 48 51 55
118
47 48 51 55
118
6
51 52
53 55
119
6
118
118
OUT
OUT
/SPDIF_OUT2
VL_HD
SENSE_A
GPIO1/DMIC_SDA2
GPIO0/DMIC_SDA1
VHP_FILT+
GPIO2
RESET*
LINEOUT_L1-
VBIAS_DAC
FLYP
VA_REF
VD
GPIO3
VHP_FILT-
LINEOUT_R1-
LINEOUT_R1+
LINEOUT_R2-
SPDIF_OUT
LINEIN_C-
FLYC FLYN
SPDIF_IN
LINEOUT_L1+
THRM_PAD
VA_HP
HPOUT_R
HPREF
VCOM
AGND
VA
LINEIN_R+
LINEIN_L+
MICIN_L+ MICIN_L-
MICBIAS
SYNC
DGND
DMIC_SCL
HPOUT_L
SDI SDO
VL_IF
BITCLK
MICIN_R-
MICIN_R+
VREF+_ADC
LINEOUT_L2+ LINEOUT_L2­LINEOUT_R2+
OUT
OUT
IN
OUT
NC NC
OUT
G
D
S
P-CHN
D
S
G
N-CHN
G
D
S
P-CHN
NC NC
D
S
G
N-CHN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
NR/FB
NC
IN
EN
GND
IN
OUT
OUT
OUT
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TWEETERS
NC
NC
NC
DMICS 1 & 2
HP AMP CNTRL
MAC SPKR AMP CNTRL
NC
SE FSINPUT= 1.22VRMS
PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5
WIN SPKR AMP CNTRL
DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC
NC NC
WOOFERS
HP AMP/LINE OUT
RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT
DAC2/3 FSOUTPUTSE= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC1 FSOUTPUT= 1.34VRMS
DIFF FSINPUT= 2.45VRMS
NC
NC
NC
PLACE C6200 AS CLOSE TO PIN 9 AS POSSIBLE
4.5V POWER SUPPLY FOR CODEC
VD MUST BE LESS THAN OR EQUAL TO VL_HD
APPLE P/N 353S2592
AUDIO CODEC
APPLE P/N 353S2456
60
105
56 58
QFN
CRITICAL
CS4206B
U6101
X5R-1
4V
402
4.7UF
20%
C6101
57
42
1/16W MF-LF
402
5%
22
R6104
56 58
42
SOD-523
BAT54XV2T1
D6100
SM
XW6110
MF-LF
1/16W 402
0
5%
DEVEL_AUDIO
R6171
20%
0402-1
X5R-CERM
10V
CRITICAL
C6107
SM
XW6100
42
SOT563
CRITICAL
DMC2400UV
DEVEL_AUDIO
Q6170
0
402
MF-LF
1/16W
5%
DEVEL_AUDIO
R6170
CRITICAL
DMC2400UV
SOT563
DEVEL_AUDIO
Q6170
DEVEL_AUDIO
DMC2400UV
CRITICAL
SOT563
Q6171
DEVEL_AUDIO
5% 1/16W MF-LF 402
0
R6172
DEVEL_AUDIO
5%
0
402
1/16W MF-LF
R6173
22
402
1/16W
5%
MF-LF
R6102
DMC2400UV
DEVEL_AUDIO
SOT563
CRITICAL
Q6171
16V
X7R-CERM
0402
0.1UF
10%
C6123
X5R 0402
10% 10V
0.47UF
C6100
10%
0402
X5R
10V
0.47UF
C6102
22
1/16W
402
MF-LF
5%
R6101
0402
X5R
10V
10%
0.47UF
C6106
0402
X5R
0.47UF
10V
10%
C6115
10V X5R 0402
0.47UF
10%
C6104
1/16W MF-LF
1%
402
R6103
2.2UF
CERM
20%
6.3V 402-LF
C6111
18
105
6.3V CERM
20%
402-LF
2.2UF
C6112
56 60 62
121
402
MF-LF
2.67K
1% 1/16W
R6100
CERM 402-LF
2.2UF
6.3V
20%
C6109
402-LF
2.2UF
CERM
6.3V
20%
C6110
16V
20%
CASE-B2-SM
POLY-TANT
C6108
20V
10% TANT
CASE-P3-HF
CRITICAL
1UF
C6113
18
105
CRITICAL
20% 16V POLY-TANT CASE-B2-SM
C6114
60 63
60 63
78
111
59 63
59 63
58 63
58 63
57 59 63
57 59 63
57 58 63
POLY-TANT
16V
20%
CASE-B2-SM
C6103
18
105
402-1
10V X5R
10%
1UF
C6105
57 58 63
402
MF-LF
0
1/16W
5%
R6105
15 18
105
56 60 62
121
6
42 56 58 59 62
56 57
121
6
42 56 58 59 62
6
63
18
105
402
5%
1/16W
0
MF-LF
R6120
SM
XW6111
1UF
10% 10V X5R
402-1
C6122
CRITICAL
SON
TPS71745
VR6101
0402
FERR-220-OHM
L6110
0402
FERR-220-OHM
L6111
10V
10%
1UF
402-1
X5R
C6124
62 63
56 57
121
56 60 62
121
58
AUDIO: CODEC/REGULATORS
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
C6113
127S0111127S0134
THAILAND ALTERNATE
NC_AUD_MIC_INN_R
NO_TEST=TRUE
NC_AUD_MIC_INP_R
NO_TEST=TRUE
AUD_LO2_R_N
AUD_LO2_R_P
AUD_LO1_L_N
TP_AUD_HP_L
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.1MM
GND_AUDIO_CODEC
PP4V5_AUDIO_ANALOG
PP5V_AUDIO_HPAMP
=PP3V3_S0_AUDIO
GND_AUDIO_CODEC
AUD_CODEC_MICBIAS
NC_AUD_LI_P_L
NO_TEST=TRUE
AUD_MIC_INL_P
NC_AUD_LI_P_R
NO_TEST=TRUE
AUD_LO2_L_N
AUD_LO2_L_P
AUD_LO1_R_N
=PP1V5_S0_AUD_DIG
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.1MM
TP_AUD_HP_R
MIN_NECK_WIDTH=0.1MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM
PP5V_AUDIO_HPAMP
AUD_GPIO_3
GND_AUDIO_CODEC
AUD_DMIC_SDA1 TP_AUD_GPIO_1 AUD_GPIO_2
HDA_BIT_CLK
DP_INT_SPDIF_AUDIO
AUD_SPDIF_CHIP
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
CS4206_VREF_ADC
AUD_MIC_INL_N
NC_AUD_LI_COM
NO_TEST=TRUE
AUD_LO1_R_P
MIN_LINE_WIDTH=0.2MM
CS4206_HPREF
MIN_NECK_WIDTH=0.1MM
HDA_SYNC
AUD_SPDIF_OUT
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG
MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
4V5_NR
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
GND_AUDIO_CODEC
MIN_NECK_WIDTH=0.2MM
PP4V5_AUDIO_ANALOG
AUD_SENSE_A
CS4206_FLYN
AUD_CODEC_MICBIAS
HDA_SDOUT HDA_RST_L
AUD_SDI_RHDA_SDIN0
AUD_LO1_L_P
=PP3V3_S0_AUDIO
CS4206_FN
CS4206_FP
VBIAS_DAC
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
GND_AUDIO_HPAMP
AUD_DMIC_CLK
CS4206_FLYP CS4206_FLYC
GND_AUDIO_DMIC
MIN_LINE_WIDTH=0.20MM VOLTAGE=0V
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.40MM
4V5_REG_IN
4V5_REG_EN
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
CS4206_VCOM
CS4206_DMIC_SCL
Q6171_P_S
Q6171_P_G
Q6171_N_G
Q6171_N_S
Q6170_N_S
Q6170_N_G
Q6170_P_G
Q6170_P_S
=PP5V_S0_AUDIO
prefsb
051-9505
8.0.0
61 OF 144 56 OF 123
3
13
12
2
44
14
11
34
29
45
24
9
15
41
37
36
33
48
22
43 42
47
35
49
46
40
39
28
26
25
23
21
18 17
16
10
7
4
38
8 5
1
6
20
19
27
31 30 32
2
1
1 2
A K
2
1
1
2
2
1
2
1
3 4
5
1
2
1
2
6
3 4
5
1
2
1
2
1 2
1
2
6
2
1
2
1
2
1
1 2
2
1
2
1
2
1
1
2
212
1
1
2
212
1
1
2
1
2
1
2
1
2
2
1
1
2
1 2
2
1
2
1
1
3
5
2
6
4
21
21
2
1
56 60 62 63
56 60 62 63
6
56 60 62 63
56 60 62 63
105
56 60 62 63
105
57
117
PGND
SGND
PVSS
THM_PAD
PVDD
SVDD
BIAS
OUTL
OUTR
C1P C1N
SVDD2 INL­INL+
INR-
INR+
SHDN*
IN
IN
IN
IN
IN IN
IN IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
G
D
S
IN
IN
OUT
G
D
S
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
NCNC
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
10V
10%
1UF
X5R
402-1
C6252
X5R
1UF
10% 10V
402-1
C6256
TQFN
MAX97220AETE
CRITICAL
U6250
56 59 63
56 59 63
56 58 63
56 58 63
57 63
57 63
57 63
57 63
57 63
57 63
57 60
57 63
57 63
57 60
57 60
57 60
402-1
10% 10V
1UF
X5R
C6253
C6261
TANT
20%
6.3V
CRITICAL
CASE-A
CRITICAL
6.3V TANT
20%
CASE-A
C6263
20%
6.3V TANT
CASE-A
CRITICAL
C6273
CRITICAL
C6271
TANT
6.3V
20%
CASE-A
402
1/16W
5%
33
MF-LF
R6252
33
402
MF-LF
1/16W
5%
R6251
20%
0402-1
X5R-CERM
10V
C6251
NOSTUFF CRITICAL
SOT23
MMBFJ201
Q6251
0402
FERR-220-OHM
L6250
1/16W
MF-LF
402
5%
R6250
56
57
57
402
MF-LF
1/16W
5%
R6253
1/16W
402
MF-LF
5%
R6254
NOSTUFF CRITICAL
SOT23
MMBFJ201
Q6250
NOSTUFF
1/16W MF-LF
0
402
5%
R6255
NOSTUFF
0
5%
402
MF-LF
1/16W
R6256
402
1%
19.6K
SIGNAL_MODEL=EMPTY
MF-LF
1/16W
R6272
SIGNAL_MODEL=EMPTY
402
1/16W MF-LF
1%
19.6K
R6274
SIGNAL_MODEL=EMPTY
402
R6264
1%
MF-LF
1/16W
19.6K
MF-LF
19.6K
1%
1/16W
402
SIGNAL_MODEL=EMPTY
R6262
0402
CERM
50V
5%
100PF
SIGNAL_MODEL=EMPTY
C6274
0402
100PF
SIGNAL_MODEL=EMPTY
5% CERM
50V
C6264
5%
50V CERM 0402
100PF
SIGNAL_MODEL=EMPTY
C6262
SIGNAL_MODEL=EMPTY
100PF
0402
CERM
50V
5%
C6272
16V
X7R-CERM
0402
0.1UF
10%
C6250
10%
0.1UF
0402
X7R-CERM
16V
C6257
16V X7R-CERM 0402
0.1UF
10%
C6258
402
R6261
MF-LF
1/16W
26.1K
1%
402
26.1K
1/16W MF-LF
1%
R6263
MF-LF
402
R6273
1/16W
1%
26.1K
402
R6271
1%
26.1K
1/16W MF-LF
20% X5R-CERM
25V
2.2UF
0402-1
C6254
X5R-CERM
25V
20%
2.2UF
0402-1
C6255
AUDIO: HEADPHONE AMP
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
C6271
127S0120127S0135
THAILAND ALTERNATE
127S0135
C6261
127S0120
THAILAND ALTERNATE
127S0120127S0135
C6263
THAILAND ALTERNATE
127S0120127S0135
C6273
THAILAND ALTERNATE
MAX97220_C1N
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
MAX97220_C1P
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
GND_AUDIO_HPAMP
MIN_LINE_WIDTH=0.5MM
MAX97220_PVSS
MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
MIN_LINE_WIDTH=0.4MM
MAX97220_BIAS
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
MAX97220_OUTL
MIN_LINE_WIDTH=0.4MM
AUD_LO1_L_C_P
AUD_LO1_L_C_N
MAX97220_INL_N
MAX97220_INL_P
AUD_LO1_R_C_N
MAX97220_INR_N
AUD_LO1_R_C_P
MAX97220_INR_P
MAX97220_PVSS
MAX97220_INR_N
MAX97220_INL_N
MAX97220_INR_P
MAX97220_SHDN_LAUD_GPIO_2
AUD_LO1_R_N
AUD_LO1_L_P
AUD_LO1_L_N
GND_AUDIO_HPAMP
HPOUT_JFET_G
PP5V_AUDIO_HPAMP
AUD_HP_PORT_REF
MAX97220_OUTR
MAX97220_INL_P
MAX97220_SHDN_L
MAX97220_OUTL_ZOBEL MAX97220_OUTR_ZOBEL
MIN_LINE_WIDTH=0.4MM
MAX97220_OUTR
MIN_NECK_WIDTH=0.2MM
GND_AUDIO_HPAMP
PP5V_AUDIO_HPAMP
MAX97220_OUTL
AUD_LO1_R_P
prefsb
051-9505
8.0.0
62 OF 144 57 OF 123
2
1
2
1
365
17
1
13
11
12
10
2 4
9
14 15
8
7
16
2
1
1 2
1 2
1 2
1 2
1
2
1
2
2
1
1
2
3
21
1
2
121
2
1
2
3
1 2
1 2
1 2
1
2
1
2
1 2
2
1
2
1
1 2
1 2
2
1
2
1
2
1
1 2
1 2
1 2
1 2
2
1
2
1
56 57
57
63
63
63
63
57
56 57
56 57
121
60
56 57
56 57
121
IN
IN
IN
OUT
OUT
OUT
OUT
REGEN
VREG/AVDD
PGND
THRM_PAD
PVDD
THERM
NC
AGND
EDGEINL-
INR+
GAIN
INL+
BOOTL-
INR-
MONO
OUTR-
OUTL+
BOOTR+
OUTL-
SDNR*
OUTR+
BOOTR-
BOOTL+
TEST
SDNL*
OUT OUT OUT
IN
IN
OUT
OUT
NC NC
OUT
OUT
IN
IN
SYM_VER-2
SYM_VER-2
IN
IN
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FC_HPF, WOOFERS = ~4 HZ (1.0 UF)
ONLY WOOFERS ON UNDER WINDOWS
INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS
MAKE LAYOUT MORE LOGICAL
OUTPUT POLARITY FLIP TO
FC_HPF, TWEETERS = ~847 HZ (4700 PF)
SPEAKER AMP GAIN = +9 DB
EDGE RATE
NC
SHOULD BE TIED TO GND
SPEAKER AMP RIN = 40K NOMINAL
APPLE P/N 353S3163
LEFT CH SPEAKER AMP
PINS 14 & 15 ARE TEST PINS AND
WOOFERS & TWEETERS ON UNDER MAC OS
AUD_RAMP_MONO NET: LOW = STEREO OPERATION
HIGH = MONO OPERATION
+9 DB NOSTUFF 0 OHM
+18 DB 47 KOHM NOSTUFF
+12 DB NOSTUFF 47 KOHM
GAIN R6306 R6307
+15 DB NOSTUFF NOSTUFF +24 DB 0 OHM NOSTUFF
OFF NOSTUFF 0 OHM
ON 0 OHM NOSTUFF
CONTROL R6304 R6305
NPO-C0G-CERM
5%
50V
0805
4700PF
C6311
1UF
0402
X5R
25V
10%
C6308
1UF
0402
X5R
25V
10%
C6309
2.2UF
402
X5R-CERM
10V
20%
C6317
58
6
59
805
25V X5R
10%
C6300
10%
805
25V X5R
C6301
0.22UF
603
20% 25V X5R
C6316
58
603
X5R
20%
0.22UF
25V
C6315
0.22UF
20%
603
25V X5R
C6314
20%
603
25V
0.22UF
X5R
C6313
CRITICAL
5%
1000PF
402
25V
SIGNAL_MODEL=EMPTY
NP0-C0G
C6319
NP0-C0G
402
25V
SIGNAL_MODEL=EMPTY
1000PF
5%
CRITICAL
C6320
NP0-C0G
25V
5%
402
SIGNAL_MODEL=EMPTY
CRITICAL
1000PF
C6321
SIGNAL_MODEL=EMPTY
CRITICAL
1000PF
5%
25V
NP0-C0G
402
C6322
X5R
25V 402
10%
0.1UF
C6302
1UF
603-1
10% X5R
25V
C6303
402
25V
0.1UF
X5R
10%
C6304
61 63
61 63
61 63
61 63
X5R
1UF
603-1
10% 25V
C6305
CRITICAL
LFCSP
SSM3302
U6300
NOSTUFF
MF-LF
1/16W 402
0
5%
R6305
MF-LF
5%
402
0
1/16W
R6304
58
1/16W 402
0
5% MF-LF
R6303
58
1/16W
NOSTUFF
MF-LF
5%
0
402
R6306
58
56
1/16W
5%
402
MF-LF
0
R6308
56
402
5% 1/16W MF-LF
R6309
50V
100PF
402
CERM
5%
NOSTUFF
C6318
58 59
1/16W
402
MF-LF
5%
R6301
5%
NOSTUFF
402
100PF
50V CERM
C6312
58 59
CRITICAL
SIGNAL_MODEL=EMPTY
NP0-C0G
1000PF
402
25V
5%
C6323
SIGNAL_MODEL=EMPTY CRITICAL
NP0-C0G 402
25V
5%
1000PF
C6324
58
58
58
58
FERR-1000-OHM
0402
L6308
SIGNAL_MODEL=EMPTY
DLY5ATN111SQ2
110-OHM-3A
CRITICAL
L6305
DLY5ATN111SQ2
110-OHM-3A
SIGNAL_MODEL=EMPTY
CRITICAL
L6307
56 57 63
56 57 63
56 63
FERR-1000-OHM
0402
L6303
0402
FERR-1000-OHM
L6302
FERR-1000-OHM
0402
L6301
56 63
FERR-1000-OHM
0402
L6300
58 59
58
58 59
220UF
SM-CASE-C1-HF
CRITICAL
ELEC
16V
20%
C6306
SM-CASE-C1-HF
ELEC
220UF
16V
20%
CRITICAL
C6307
47K
5% 1/16W MF-LF 402
R6307
5%
50V
NPO-C0G-CERM
0805
4700PF
C6310
SYNC_MASTER=D8_MLB
AUDIO: LEFT SPKR AMP
SYNC_DATE=08/27/2012
AUD_LAMP_LINC_N
AUD_LAMP_LINC_P
=PP3V3_S0_AUDIO
AUD_LAMP_AVDD
AUD_LAMP_GAIN
AUD_LAMP_OUTNR
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
AUD_LAMP_OUTNL
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
AUD_LAMP_OUTPL
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
AUD_LAMP_BOOTRN
AUD_LAMP_OUTPR
AUD_LAMP_OUTNR
AUD_SPKR_LWFR_OUT_P
AUD_SPKR_LWFR_OUT_N
AUD_SPKR_LTWT_OUT_N
AUD_SPKR_LTWT_OUT_P
AUD_SPKRAMP_WIN_SHDN_L
AUD_LAMP_MONO
AUD_SPKRAMP_MAC_SHDN_L
AUD_LO2_L_N
AUD_LO1_L_P
AUD_LO1_L_N
AUD_LO2_L_P
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
AUD_LAMP_BOOTLP
MIN_NECK_WIDTH=0.15MM
AUD_LAMP_BOOTLN
MIN_LINE_WIDTH=0.20MM
AUD_LAMP_AVDD
MIN_NECK_WIDTH=0.15MM VOLTAGE=5V
MIN_LINE_WIDTH=0.20MM
TP_AUD_LAMP_THERM
AUD_LAMP_EDGE
AUD_LAMP_EDGE
AUD_SPKRAMP_WIN_SHDN_L
AUD_GPIO_3
AUD_LAMP_MONO
AUD_CODEC_MICBIAS
AUD_SPKRAMP_MAC_SHDN_L
AUD_LAMP_GAIN
MIN_NECK_WIDTH=0.15MM
AUD_LAMP_BOOTRP
MIN_LINE_WIDTH=0.20MM
AUD_LAMP_OUTPR
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
AUD_LAMP_LIN_P
AUD_LAMP_LIN_N
AUD_LAMP_RINC_P
AUD_LAMP_RIN_N
AUD_LAMP_RINC_N
AUD_LAMP_RIN_P
=PP12V_S0_AUDIO_SPKRAMP
prefsb
051-9505
8.0.0
63 OF 144 58 OF 123
1 2
1 2
1 2
2
1
2
1
2
1
1 2
1 2
1 2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
394038
33
23
8
31
41
37
35
34
32
24
17
13
7
10
36
12
20
21
11
6
19
3
16
27
2
30
5
22
28
26
4
29
25
1
18
15
14
9
1
2
1
2
1
2
1
2
1 2
1
2
2
1
1
2
2
1
2
1
2
1
21
4 3
1 2
4 3
1 2
21
21
21
21
1
2
1
2
1
2
1 2
63
63
6
42 56 59 62
58
58
63
63
63
63 63
63
IN
IN
IN
REGEN
VREG/AVDD
PGND
THRM_PAD
PVDD
THERM
NC
AGND
EDGEINL-
INR+
GAIN
INL+
BOOTL-
INR-
MONO
OUTR-
OUTL+
BOOTR+
OUTL-
SDNR*
OUTR+
BOOTR-
BOOTL+
TEST
SDNL*
IN
IN
IN
OUT OUT OUT
IN
IN
NC NC
IN
OUT
IN
OUT
SYM_VER-2
SYM_VER-2
IN
IN
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GAIN R6406 R6407
+24 DB 0 OHM NOSTUFF
+15 DB NOSTUFF NOSTUFF
+12 DB NOSTUFF 47 KOHM +18 DB 47 KOHM NOSTUFF
+9 DB NOSTUFF 0 OHM
NC
RIGHT CH SPEAKER AMP
APPLE P/N 353S3163
SPEAKER AMP GAIN = +9 DB SPEAKER AMP RIN = 40K NOMINAL FC_HPF, TWEETERS = ~847 HZ (4700 PF)
EDGE RATE ON 0 OHM NOSTUFF
OFF NOSTUFF 0 OHM
LOW = STEREO OPERATION
PINS 14 & 15 ARE TEST PINS AND SHOULD BE TIED TO GND
CONTROL R6404 R6405
OUTPUT POLARITY FLIP TO MAKE LAYOUT MORE LOGICAL
HIGH = MONO OPERATION
AUD_RAMP_MONO NET:
ONLY WOOFERS ON UNDER WINDOWS
INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS
FC_HPF, WOOFERS = ~4 HZ (1.0 UF)
WOOFERS & TWEETERS ON UNDER MAC OS
6
58
CRITICAL
SIGNAL_MODEL=EMPTY
402
1000PF
5% 25V NP0-C0G
C6421
CRITICAL
25V NP0-C0G 402
1000PF
5%
SIGNAL_MODEL=EMPTY
C6419
CRITICAL
NP0-C0G
5%
402
25V
SIGNAL_MODEL=EMPTY
1000PF
C6420
1000PF
5%
25V
NP0-C0G
402
CRITICAL
SIGNAL_MODEL=EMPTY
C6422
603
20%
0.22UF
25V X5R
C6415
56 57 63
56 63
20% 25V
0.22UF
X5R 603
C6416
X5R
20% 25V
603
0.22UF
C6413
X5R
0.22UF
25V
20%
603
C6414
CRITICAL
SSM3302
LFCSP
U6400
59
20% 10V
X5R-CERM
402
2.2UF
C6417
58
58
25V 805
10% X5R
C6401
1/16W
0
402
MF-LF
5%
R6404
5%
0
402
1/16W MF-LF
NOSTUFF
R6405
59 59
MF-LF
5%
0
402
1/16W
R6403
59
0
5% MF-LF
402
NOSTUFF
1/16W
R6406
59
10% X5R
25V 805
C6400
59
SIGNAL_MODEL=EMPTY CRITICAL
402
5% 25V NP0-C0G
1000PF
C6423
5% 25V NP0-C0G
CRITICAL
1000PF
402
SIGNAL_MODEL=EMPTY
C6424
20%
470UF
SM
POLY
16V
CRITICAL
C6406
59
59
59
59
SIGNAL_MODEL=EMPTY
CRITICAL
110-OHM-3A
DLY5ATN111SQ2
L6405
DLY5ATN111SQ2
CRITICAL
SIGNAL_MODEL=EMPTY
110-OHM-3A
L6407
5% 1/16W MF-LF 402
47K
R6407
0805
50V
5%
4700PF
NPO-C0G-CERM
C6410
5%
50V
NPO-C0G-CERM
0805
4700PF
C6411
X5R
10% 25V
0402
1UF
C6408
10% 25V X5R
0402
1UF
C6409
FERR-1000-OHM
0402
L6400
0.1UF
10% X5R
402
25V
C6404
0402
FERR-1000-OHM
L6401
FERR-1000-OHM
0402
L6402
0402
FERR-1000-OHM
L6403
X5R 402
25V
10%
0.1UF
C6402
603-1
25V X5R
10%
1UF
C6403
25V
10%
603-1
X5R
1UF
C6405
56 63
56 57 63
61 63
61 63
61 63
61 63
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
AUDIO: RIGHT SPKR AMP
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
AUD_RAMP_OUTPL
AUD_RAMP_RINC_N
AUD_RAMP_RIN_N
AUD_RAMP_RINC_P
AUD_RAMP_RIN_P
AUD_RAMP_LIN_P
AUD_RAMP_GAIN
AUD_RAMP_LINC_N
AUD_RAMP_LIN_N
AUD_RAMP_LINC_P
AUD_LO2_R_P
AUD_RAMP_MONO
=PP12V_S0_AUDIO_SPKRAMP
AUD_LO2_R_N
AUD_RAMP_AVDD
AUD_RAMP_MONOAUD_RAMP_EDGE
TP_AUD_RAMP_THERM
AUD_RAMP_EDGE
AUD_SPKRAMP_WIN_SHDN_L
AUD_SPKRAMP_MAC_SHDN_L
AUD_LO1_R_N
AUD_LO1_R_P
=PP3V3_S0_AUDIO
AUD_SPKR_RWFR_OUT_N
AUD_RAMP_OUTPR
AUD_SPKR_RWFR_OUT_P
AUD_RAMP_OUTNR
AUD_SPKR_RTWT_OUT_N
AUD_SPKR_RTWT_OUT_P
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
AUD_RAMP_BOOTLN
MIN_NECK_WIDTH=0.25MM
AUD_RAMP_OUTPR
MIN_LINE_WIDTH=0.6MM
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
AUD_RAMP_OUTNR
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
AUD_RAMP_BOOTLP
MIN_NECK_WIDTH=0.15MM
AUD_RAMP_BOOTRN
MIN_LINE_WIDTH=0.20MM
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
AUD_RAMP_BOOTRP
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM VOLTAGE=5V
AUD_RAMP_AVDD
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
AUD_RAMP_OUTNL
AUD_RAMP_GAIN
prefsb
051-9505
8.0.0
64 OF 144 59 OF 123
2
1
2
1
2
1
2
1
1 2
1 2
1 2
1 2
394038
33
23
8
31
41
37
35
34
32
24
17
13
7
10
36
12
20
21
11
6
19
3
16
27
2
30
5
22
28
26
4
29
25
1
18
15
14
9
2
1
2
1
1
2
1
2
1
2
1
2
2
1
2
1
2
1
1
2
4 3
1 2
4 3
1 2
1
2
1 2
1 2
1 2
1 2
21
2
1
21
21
21
2
1
2
1
2
1
63 63
63 63
63
63 63
63
59
6
42 56 58 62
59
OUT
OUT
IN
BI
OUT
IN
IN
CS
HDET
ENABLE
INT*
SDA
SCL
AGND
MICBIAS
DETECT
BYPASS
AVDD
DGND
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
NOISE ISSUE SEEN ON EARLY HEADSETS (SEE RADAR <RDAR://PROBLEM/6210118>)
R/C6750 FILTER TO ADDRESS OUT-OF-BAND
MIKEY RECEIVER CKT
WRITE: 0X72 READ: 0X73
APN 353S3231
I2C PULLUPS ON SOUTHBRIDGE PAGE
ON: INPUT LOOKS LIKE 1M PULL-UP TO 3V
HDET FUNCTION:
OFF: INPUT LOOKS LIKE 1M PULL-DOWN TO GND
APPLE P/N 518S0687
I2C ADDRESSES
MIKEY U6551 READ 0111 0011 0X73 MIKEY U6551 WRITE 0111 0010 0X72
INTENTIONALLY
OPPOSIDE
POLARITY
56 63
56 63
50
50
20
26
62
R6561
402
47K
MF-LF
5%
1/16W
NOSTUFF
U6551
MQFN-RSV
CRITICAL
CD3285A0
5%
MF
1/20W
201
R6556
R6550
1/16W MF-LF
5%
402
R6554
1K
5%
402
MF-LF
SIGNAL_MODEL=EMPTY
1/16W
C6556
402
25V
10% X7R
0.01UF
C6555
CRITICAL
20%
X5R-CERM
10V
0402
4.7UF
60
60 63
60 63
FERR-1000-OHM
L6505
0402
56 60 62 63
62
0402
FERR-1000-OHM
L6501
L6500
FERR-1000-OHM
0402
62
60 63
L6510
0402
FERR-1000-OHM
62
0
R6551
MF-LF
5%
1/16W
402
402
R6553
1K
5%
SIGNAL_MODEL=EMPTY
MF-LF
1/16W
NOSTUFF
J6500
54722-0224
F-ST-SM
SIGNAL_MODEL=EMPTY
CRITICAL
FERR-120-OHM-2.0A
0402
L6507
56 105
0402
L6502
FERR-1000-OHM
0402
FERR-120-OHM-2.0A
L6509
CRITICAL
57
50
NOSTUFF
FERR-120-OHM-2.0A
L6504
0402
CRITICAL
FERR-120-OHM-2.0A
CRITICAL
0402
L6503
50
57
57
60
60 63
R6506
5%
402
1/16W MF-LF
0
R6562
201
MF
1/20W
10K
5%
R6555
201
MF
1/20W
5%
FERR-120-OHM-2.0A
CRITICAL
0402
L6508
C6552
10% 16V
X7R-CERM
0402
0.1UF
X7R-CERM
C6553
10% 16V
0402
0.1UF
C6560
16V X7R-CERM 0402
0.1UF
10%
C6558
5%
0402-1
CERM
50V
CRITICAL
C6550
10%
0.0082UF
X7R-CERM
25V
CRITICAL
0402
ESDALC5-1BM2
SOD882
DZ6500
SOD882
ESDALC5-1BM2
DZ6501
SOD882
ESDALC5-1BM2
DZ6502
ESDALC5-1BM2
DZ6503
SOD882 SOD882
ESDALC5-1BM2
DZ6504
SOD882
ESDALC5-1BM2
DZ6505
0402
FERR-120-OHM-2.0A
L6511
CRITICAL
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
AUDIO: Jack, Mikey, CHS Switch
=PP3V3_S4_AUDIO_DIG
AUD_J1_MIC_N
AUD_J1_TIPDET1_R
AUD_J1_HP_OUTR
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM
GND_AUDIO_CODEC
=I2C_MIKEY_SDA
AUD_TIPDET1_R
MAX97220_OUTR
AUD_HP_PORT_REF
MAX97220_OUTL
AUD_SPDIF_OUT
=I2C_CHS_SCL
GND_AUDIO_CODEC
AUD_TIPDET2_R
MIN_LINE_WIDTH=0.25MM
HS_MIC_BIAS
MIN_NECK_WIDTH=0.20MM
=I2C_MIKEY_SCL
AUD_PORTD_DET_L
PP4V5_AUDIO_ANALOG
AUD_HS_MIC_N
AUD_MIC_INL_N
AUD_MIC_INL_P
HS_HDET
=PP3V3_S0_AUDIO_DIG
HS_SW_DET
HS_RX_BP
AUD_HS_MIC_RC_N
AUD_IPHS_SWITCH_EN
=I2C_CHS_SDA
AUD_TYPEDET_R
HS_MIC_BIAS
=PP3V3_S0_AUDIO_DIG
AUD_HS_MIC_P
AUD_HS_MIC_N
AUD_J1_TYPEDET_R
AUD_HS_MIC_RC_P
AUD_HS_MIC_P
GND_AUDIO_CODEC
AUD_I2C_INT_L
AUD_J1_MIC_P
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.25MM
AUD_J1_MIC_BIAS
AUD_J1_TIPDET2_R
AUD_J1_GND_ANALOG
MIN_LINE_WIDTH=0.50MM VOLTAGE=0V
MIN_NECK_WIDTH=0.20MM
AUD_J1_HP_PORT_REF
AUD_J1_HP_OUTL
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM
AUD_J1_PP3V3_S0
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM
prefsb
051-9505
8.0.0
65 OF 144 60 OF 123
1 2
16
13
1
4
2
3
678
12
10
11
9
15
14
5
1
2
1 2
1
2
2
1
2
1
21
21
21
21
1 2
1
2
1 3
7
5
9 11 13 15
19
17
21
2 4 6 8
14
10 12
18
16
20 22
21
21
21
21
21
1 2
1
2
1
2
21
1 2
1 2
2
1
2
1
2
1
1 2
1 2
1 2
1 2
1 2
1 2
21
6
63
56 60 62 63
56 62
121
6
60
63
6
60
63
56 60 62 63
63
OUT
IN
IN
OUT
IN IN
IN IN
IN IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
APPLE P/N 518S0862
SPEAKER CABLE CONNECTORS
TWEETER (FR)
WOOFER (BR)WOOFER (BL)
TWEETER (FL)
63
58 63
58 63
63
59 63
59 63
59 63
59 63
58 63
58 63
CRITICAL
M-RT-SM
504050-0691
J6603
CRITICAL
M-RT-SM
504050-0691
J6602
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
Audio: Spkr/Mic Conn.
AUD_SPKR_LTWT_OUT_N
AUD_SPKR_LTWT_OUT_P
AUD_SPKR_VENDOR_ID_L
AUD_SPKR_LWFR_OUT_N
AUD_SPKR_LWFR_OUT_P
AUD_SPKR_RTWT_OUT_N
AUD_SPKR_RTWT_OUT_P
AUD_SPKR_VENDOR_ID_R
AUD_SPKR_RWFR_OUT_N
AUD_SPKR_RWFR_OUT_P
prefsb
051-9505
8.0.0
66 OF 144 61 OF 123
1 2
4
3
5 6
8
7
1 2
4
3
5 6
8
7
OUT
IN
NC
IN
OUT
IN
OUT
IN
IN
OUT
D
SG
D
SG
D
SG
D
SG
D
S
G
N-CHN
G
D
S
P-CHN
IN
D
SG
D
SG
D
SG
D
S
G
D
S
G
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
APN:376S1032
IPHS HS Detect Debounce CKT
LI Insert Detect
(DETECT A)
NC
AUDIO CONNECTOR DETECT STATES
NC
PLACE C6700 CLOSE TO Q6700 PIN 4
PORT D DETECT (HEADPHONES)
NOTHING SPDIF HEADPHONE
PORT B DETECT(SPDIF DELEGATE)
AUD_OUTJACK_INSERT 0 1 1
AUD_TYPEDET_R 1 1 0
AUD_TIPDET*_R 0 1 1
AUD_SENSE_A 1 20K/2.67K RDIV 5.11K/2.67K RDIV
TBT/DP Audio Enable
20
R6745
0
MF-LF
402
1/16W
5%
C6741
X5R 402
16V
0.1UF
10%
NOSTUFF
56 62 63
R6744
5%
MF-LF
1/16W
402
L6743
FERR-1000-OHM
0402
60
56 62 63
R6792
47K
5%
402
MF-LF
1/16W
C6791
CERM
20%
0.1UF
402
10V
R6796
MF-LF 402
20.0K
1/16W
1%
R6730
10K
1/16W MF-LF
5%
402
FERR-1000-OHM
0402
L6732
21 75
103
60
R6795
5.11K
1/16W 402
MF-LF
1%
R6731
1%
39.2K
MF-LF 402
1/16W
R6742
47K
5% 1/16W MF-LF
402
R6791
1/16W
5%
MF-LF
402
60
R6741
47K
5% 1/16W MF-LF
402
62
62
Q6797
SSM6N15AFE
SOT563
Q6796
SSM6N15AFE
SOT563
Q6741
SSM6N15AFE
SOT563
Q6741
SSM6N15AFE
SOT563
Q6700
DMC2400UV
SOT563
Q6700
SOT563
DMC2400UV
60
R6701
5% 1/16W MF-LF
402
R6702
402
MF-LF
1/16W
5%
R6703
5% 1/16W MF-LF 402
Q6797
SSM6N15AFE
SOT563
R6743
MF-LF
402
1/16W
5%
47K
Q6796
SOT563
SSM6N15AFE
Q6800
SOT563
SSM6N15AFE
Q6740
NTZD3152P
SOT-563-HF
Q6740
NTZD3152P
SOT-563-HF
C6700
10%
0.1UF
0402
X7R-CERM
16V
AUDIO: Detects/Grounding
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
DP_TBT_SEL
AUD_LI_TIPDET
AUD_SENSE_A
AUD_TYPEDET_OD_INV
AUD_OUTJACK_INSERT
GND_AUDIO_CODEC
AUD_TYPEDET_OD
PP4V5_AUDIO_ANALOG
PP4V5_AUDIO_ANALOG
AUD_PORTD_DET_L
AUD_OUTJACK_INSERT_L
AUD_TIPDET1_R
AUD_TIPDET2_R
AUD_TIPDET_INV
AUD_PORTA_DET_L
GND_AUDIO_CODEC
AUD_PORTB_DET_L
AUD_J1_DET_RC
AUD_TYPEDET_R
GND_AUDIO_CODEC
=PP3V3_S0_AUDIO
AUD_IP_PERIPHERAL_DET
AUD_SENSE_A
AUD_IP_PERPH_DET_DB
AUD_J1_DET_RC
AUD_IP_PERPH_DET_R
GND_AUDIO_CODEC
prefsb
051-9505
8.0.0
67 OF 144 62 OF 123
1 2
2
1
1
2
21
1 2
2
1
1
2
1
2
21
1
2
1
2
1
2
1
2
1
2
3
4
5
3
4
5
3
4
5
6
1
2
1
2
6
34
5
1
2
1
2
1
2
6
1
2
1
2
6
1
2
3
4
5
1
6
2
4
3
5
2
1
56 60 62 63
56 60 62
121
56 60 62
121
56 60 62 63
56 60 62 63
6
42 56 58 59
56 60 62 63
OUT
IN IN
D
SG
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PHYSICAL_RULE_SET
AREA_TYPE
NET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
CIRCUIT THEORY OF OPERATION AVAILABLE IN <RDAR://PROBLEM/9776522>
PORT C DETECT(SPEAKER MISMATCH)
CODEC OUTPUT SIGNAL PATHS
FUNCTION
PRIMARY SPKRS (WFR) SECONDARY SPKRS (TWT)
PIN COMPLEX
0X0E (14,LEFT & RIGHT)
0x10 (16)
PIN COMPLEX
0X0A (DET D)GPIO_2
MAC SHDN
0X03 (3)
DET ASSIGNMENT
0X09 (DET A)
DET ASSIGNMENT
PANTHER POINT GPIO 3 (PERIPH DET)
0X0D (DET B)
0X0D (13,V22,B,LEFT)
CONVERTER
ENABLE/CONTROL
0X0C (DET C)
PANTHER POINT GPIO 5 (RCVR INT)
N/A
ENABLE/CONTROL
N/A
N/A
DET ASSIGNMENT
CONVERTER
0X0B (11)
WIN SHDN
0X12 (18,LEFT)
0X06 (6)
N/A
MICBIAS
0X0A (10,D)
PIN COMPLEX
PANTHER POINT GPIO 16
GPIO_2
N/A
MICBIAS
N/A N/A
0X05 (5) 0X06 (6)
0x0F (15)
0X0A (10,V24)
0X03 (3)
GPIO_3
0X04 (4)
CODEC INPUT SIGNAL PATHS
0X08 (8)
0X03 (3)0X03 (3)
SPDIF OUT
HP/LINE OUT
MULTIPLE SPKR VENDORS
FUNCTION
N/A
ELECTRICAL_CONSTRAINT_SET
SPACING
NET_TYPE
PHYSICAL
N/A
FUNCTION
INTERNAL MIC ARRAY
SPDIF IN
N/A
CONVERTER
EXTERNAL MIC
OTHER DETECT
0X07 (7)
N/A
0X04 (4)
VOLUME/MUTE
N/A
NC
I203
I204
I205
I206
I207
I208
I209
I210
I211
I212
I215
I216
I217 I218
I219
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229
I230
I236
I237
I238
I239
I240 I241
I242 I243
I244
I245
I246
I247
I254
I255
I263
I264
R6812
SPEAKERID
402
MF-LF
1/16W
1%
R6813
MF-LF
1/16W 402
1%
SPEAKERID
R6810
1/16W
SPEAKERID
1%
402
MF-LF
R6811
1%
1/16W MF-LF
SPEAKERID
402
R6816
1/16W
SPEAKERID
MF-LF
402
1%
56 62
U6800
SPEAKERID
SC70-5
CRITICAL
MAX9119EXK-T
61 61
L6802
FERR-1000-OHM
0402
SPEAKERID
R6820
SPEAKERID
5%
1/16W
33
MF-LF
402
R6894
1%
1/16W
10K
402
MF-LF
SPEAKERID
C6811
SPEAKERID
16V X7R-CERM 805
2.2UF
10%
R6815
SPEAKERID
75K
1% 1/16W MF-LF
402
R6817
SPEAKERID
MF-LF
1/16W
402
37.4K
1%
R6814
SPEAKERID
1% 1/16W MF-LF
402
I324 I325
I326
I327 I328
I329
Q6800
SSM6N15AFE
SOT563
C6810
10%
0.1UF
0402
X7R-CERM
16V
SPEAKERID
SPKROUTDIFF
0.2 MM
0.6 MM
0.25 MM
0.2 MM
10 MM
Y
*
0.1 MM 0.1 MM
0.1 MM
10 MM
0.1 MM
*
Y
AUDIODIFF
SPKROUTDIFF
*
SPKROUTDIFF
AUDIO
0.1 MM
*
? ?
*
SPKROUT
0.2 MM
AUDIODIFF
*
AUDIODIFF
AUDIO: Speaker ID
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
AUD_PORTC_DET_L
GND_AUDIO_CODEC
AUD_SPKR_VENDOR_ID_L
MAX9119_NEG
=PP5V_S0_AUDIO
SPKR_MATCH_DRV_R
AUD_SENSE_A
SPKR_MATCH_DRV
AUD_MIC_INL_P
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUD_HS_MIC_RC_N
AUDIO
AUDIO_DIFFPAIR
AUDIODIFF
AUD_HS_MIC_N
AUDIO
AUDIO_DIFFPAIR
AUDIODIFF
AUDIODIFF
AUD_HS_MIC_P
AUDIO_DIFFPAIR
AUDIO
AUD_HS_MIC_RC_P
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUD_J1_MIC_P
AUDIO
AUDIO_DIFFPAIR
AUDIODIFF
AUD_J1_MIC_N
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
AUD_MIC_INL_N
AUDIO
AUDIO_DIFFPAIR
AUDIODIFF
SPKROUT_DIFFPAIR
SPKROUTDIFF
SPKROUT
AUD_SPKR_LWFR_OUT_N
SPKROUT_DIFFPAIR
SPKROUTDIFF
SPKROUT
AUD_SPKR_RTWT_OUT_N
SPKROUTDIFF
AUD_SPKR_LTWT_OUT_P
SPKROUT
SPKROUT_DIFFPAIR
SPKROUTDIFF
SPKROUT
SPKROUT_DIFFPAIR
AUD_SPKR_LTWT_OUT_N
SPKROUT_DIFFPAIR
SPKROUTDIFF
SPKROUT
AUD_SPKR_LWFR_OUT_P
SPKROUT_DIFFPAIR
SPKROUTDIFF
AUD_SPKR_RTWT_OUT_P
SPKROUT
SPKROUTDIFF
AUD_SPKR_RWFR_OUT_N
SPKROUT
SPKROUT_DIFFPAIR
AUD_SPKR_RWFR_OUT_P
SPKROUTDIFF
SPKROUT
SPKROUT_DIFFPAIR
MAX97220_INR_P
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
MAX97220_INL_P
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUDIODIFF
AUD_LAMP_LIN_N
AUDIO
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
AUD_LAMP_RIN_P
AUDIO_DIFFPAIR
AUD_LAMP_RINC_N
AUDIO
AUDIODIFF
AUD_LAMP_RINC_P
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUD_LAMP_LINC_P
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUD_RAMP_RIN_N
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_RAMP_RIN_P
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUD_RAMP_LIN_N
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_RAMP_LIN_P
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_RAMP_RINC_N
AUDIODIFF
AUDIO
MAX97220_INR_N
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
AUD_RAMP_LINC_P
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_RAMP_LINC_N
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIODIFF
AUD_LAMP_RIN_N
AUDIO
AUD_LO2_R_N
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
AUD_LO2_R_P
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_LO2_L_N
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUD_LO2_L_P
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_LO1_R_C_N
AUDIO_DIFFPAIR
AUDIO
AUDIODIFF
AUD_LO1_L_N
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUD_LO1_L_P
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUD_LO1_R_C_P
AUDIO_DIFFPAIR
AUDIO
AUDIODIFF
AUD_LO1_R_N
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_LO1_R_P
AUDIO_DIFFPAIR
AUDIO
AUDIODIFF
AUD_LO1_L_C_N
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUD_LO1_L_C_P
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
AUD_RAMP_RINC_P
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIODIFF
AUD_LAMP_LIN_P
AUDIO
AUDIODIFF
AUD_LAMP_LINC_N
AUDIO
AUDIO_DIFFPAIR
MAX97220_INL_N
AUDIODIFF
AUDIO
AUDIO_DIFFPAIR
=PP5V_S0_AUDIO
MAX9119_POS
MAX9119_OUT
=PP5V_S0_AUDIO
AUD_SPKR_VENDOR_ID_R
prefsb
051-9505
8.0.0
68 OF 144 63 OF 123
1
2
1
2
1
2
1
2
1 2
3
1
2
4
5
21
1 2
1
2
2
1
1
2
1 2
1
2
6
1
2
2
1
56 60 62
6
56 63
56 60
60
60
60
60
60
60
56 60
58 61
59 61
58 61
58 61
58 61
59 61
59 61
59 61
57
57
58
58
58
58
58
59
59
59
59
59
57
59
59
58
56 59
56 59
56 58
56 58
57
56 57 58
56 57 58
57
56 57 59
56 57 59
57
57
59
58
58
57
6
56 63
6
56 63
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
D
G S
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
08
Y1
Y2
GND
B2
VCC
A1 B1 A2
IN
IN
IN
IN
OUT
IN
IN
08
08
08
08
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
RADR://11753451 ADD PP3V3_S4 TO PWR SEQUENCE
GPU Sequencing
S3 1V5 Reg (S0/S3) Enable
S0 Platform Parallel Sequence Enable
Parallel Enable PGOOD combinator
S0 5V and TBT Enable
S4 3V3 Enable
S4 USB Enable
CPU/PCH Sequencing
CPUCORE
S5 3V3 Soft Enable
S0 12V Enable
0.0
Rail definitions
PCH/GPU/TBT 1V05
8. All rails must be powered off within 10 ms from first rail powering off
7. The ramp time for any rail must be more than 40 uS
5. PEX_VDD (our GPU_1V05) after FBVDDQ
4. FBVDDQ (our GPU_VDDQ) after NVVDD
2. IFPA/B_IOVDD (1.8 V) with or after 3V3_S0 (unused in our implementation)
2. SMC guarantees timing on PCH DPWROK and PWROK
1. No hard specification on platform rails
Notes on sequencing requirements
3. CPU VDDQ must ramp before MEMVTT and vice versa on power down. It has no relationship to any other rails.
VccSA, VDDQ, VccA (1.8 V), VccIO (VccSA, VccA, and VccIO must ramp within 50 ms of each other)
S4 5V Enable
6. IFPC/D/E/F_IOVDD (1.05V) wit or after PEX_VDD
1. VDD33 (our 3V3_S0)
3. NVVDD (our GPUCORE) after IFPA/B_IOVDD
Intel:
NVIDIA GFX:
CPU 1V05
GPU FBVDDQ
3V3
tau (RC delay, ms):
if there is no processor.
Note:
Note:
Halt power sequencing at S5
stuff R6903 to circumvent
0.0
1V8
1V5
Expected 3.9V +/- 0.4V EN signal
or short gate to source.
VCCSA
MEMVTT
GPUCORE
All processor non-Core and non-Graphics (5 V, 3.3 V, 1.8 V 1.5 V, PCH Core/PLL/VRM)
Platform: Uncore:
68K
5%
R6990
MF-LF 402
1/16W
PLACE_NEAR=U7600.12:15MM
R6991
402
5%
33K
MF-LF
1/16W
PLACE_NEAR=U7600.12:15MM
71 74
120
64 74
120
C6910
10%
0.47UF
6.3V
NOSTUFF
CERM-X5R 402
NOSTUFF
0.47UF
CERM-X5R
C6911
6.3V
10%
402
MF-LF
R6902
5%
33K
402
1/16W
NOSTUFF
C6901
0.47UF
402
10%
CERM-X5R
6.3V
65 74
120
15 19 47
120
72
120
0
5%
MF-LF
1/16W
402
R6920
64 71
120
45 46
120
C6920
402
NOSTUFF
0.47UF
CERM-X5R
6.3V
10%
R6910
5%
402
1/16W
33
MF-LF
NOSTUFF
MF-LF
33
402
1/16W
5%
R6911
71
120
96
115
74
120
5
72
120
5
15 19 28 40 47 48 120
66
120
0
5%
MF-LF
1/16W
402
R6937
65 70
120
5%
R6930
402
MF-LF
1/16W
33
74
120
15 19 47
120
11
103
R6901
5%
402
10K
MF-LF
1/16W
100K
402
1/16W MF-LF
5%
R6900
77 79
R6940
0
MF-LF
402
5%
1/16W
64 74
120
72
120
1/16W
0
R6932
402
MF-LF
5%
64 74
120
74
120
1/16W
402
0
5%
R6933
MF-LF
72
120
99
120
R6934
0
MF-LF
1/16W
402
5%
64
120
70
120
R6936
1/16W MF-LF
5%
0
402
64 65
120
PLACE_SIDE=BOTTOM
Q6900
VESM
SSM3K15AMFVAPE
99
120
1/16W MF-LF
5%
0
R6941
402
5
96 115
74
120
1/16W MF-LF
5%
0
402
R6931
74
120
72
120
28
119
R6903
1/16W
5%
10K
MF-LF
402
NOSTUFF
R6929
MF-LF
5%
33
402
1/16W
69
120
R6935
0
1/16W
5%
402
MF-LF
64 74
120
R6919
0
5%
MF-LF
1/16W
402
64 71
120
NOSTUFF
10%
402
CERM-X5R
0.47UF
6.3V
C6919
U6921
8
4
SOT833
74LVC2G08GT
5
99
120
28 74
120
5
99
120
5
69
120
NOSTUFF
402
0.47UF
6.3V
10% CERM-X5R
C6934
C6935
0.47UF
402
CERM-X5R
NOSTUFF
10%
6.3V
R6922
5%
1/16W
0
MF-LF
402
28
120
R6923
5%
0
MF-LF
1/16W
402
27 35 74
120
64 71
120
NOSTUFF
402
R6921
MF-LF
0
5%
1/16W
74LVC08
7
14
TSSOP-HF
U6900
PLACE_SIDE=BOTTOM
74LVC08
7
14
TSSOP-HF
U6900
PLACE_SIDE=BOTTOM
14
7
U6900
TSSOP-HF
74LVC08
PLACE_SIDE=BOTTOM
74LVC08
7
14
TSSOP-HF
U6900
PLACE_SIDE=BOTTOM
0.1UF
C6900
0402
10% 16V X7R-CERM
0402
C6921
X7R-CERM
16V
10%
0.1UF
PM Regulator Enables
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
=PP3V3_S5_PWRCTL
=PP3V3_S5_PWRCTL
PM_PGOOD_P3V3_S4_FET
PM_EN_REG_GPUCORE_S0
PM_EN_FET_P5V_S0
TBT_S0_EN
MAKE_BASE=TRUE
PM_EN_LDO_DDRVTT_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PM_EN_FET_VDDQ_S0
PM_EN_REG_CPU_P1V05_S0
PM_PGOOD_FBVDDQ_VDDQ_S0
PM_PGOOD_FET_P3V3_S0
=TBT_S0_EN
PM_PGOOD_REG_ALL_P1V05_S0
PM_EN_REG_P3V3_S5
PM_PGOOD_REG_P5V_S4
PM_EN_USB_PWR
CPU_SKTOCC_L
PM_EN_FET_P3V3_S4
PM_EN_REG_FBVDDQ_S0
=PP3V3_S5_PWRCTL
PM_PGOOD_REG_P1V8_S0
PM_EN_REG_VCCSA_S0
PM_EN_REG_CPUCORE_S0
PM_PGOOD_REG_VCCSA_S0
PM_PGOOD_REG_GPUCORE_S0
PM_PGOOD_FET_P3V3_S0
PM_EN_FET_P3V3_S0
PM_PGOOD_REG_FBVDDQ_S0 PM_PGOOD_FET_VDDQ_S0
MEMVTT_EN
PM_PGOOD_FET_P5V_S0
PM_PGOOD_REG_P1V05_S0 PM_PGOOD_REG_CPU_P1V05_S0
PM_EN_REG_P1V05_S0
=PP12V_S5_PWRCTL
PM_EN_FET_P3V3_S4
PM_PGOOD_REG_P5V_S4
PM_SLP_S5_L
CPU_SKTOCC
PM_EN_S4
PM_SLP_S4_L
=PP3V3_S5_PWRCTL
PM_EN_REG_VDDQ_S3
PM_SLP_S3_L
PM_PGOOD_REG_VDDQ_S3
PM_EN_FET_P12V_S0
=PP3V3_S5_PWRCTL
PU_U6900
PGOOD_P12V_S0
=PP3V3_S5_PWRCTL
PM_EN_S0
PM_PGOOD_REG_ALL_P1V05_S0
PM_PGOOD_FBVDDQ_VDDQ_S0
PM_PGOOD_REG_ALL_P1V05_S0_R
PM_EN_REG_P1V8_S0
PM_PGOOD_P5VRP3V3_S4
PM_PGOOD_REG_P5V_S4
PM_EN_REG_P5V_S4
prefsb
051-9505
8.0.0
69 OF 144 64 OF 123
1
2
1
2
2
1
2
1
1
2
2
1
1 2
2
1
1
2
1
2
1 2
1 2
1
2
1
2
1 2
1 2
1 2
1 2
1 2
1
2
3
1 2
1 2
1
2
1 2
1 2
1 2
2
1
3
71 2 5 6
2
1
2
1
1 2
1 2
1 2
8
9
10
3
2
1
11
12
13
6
5
4
2
1
2
1
6
64 65
6
64 65
122
6
64 65
6
65 74
117
120
6
64 65
6
64 65
121
6
64 65
120
64 65
120
64
120
IN
IN
OUT
OUT
IN
IN
IN
OUT
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
G
D
S
G
D
S
V-
V+
08
08
08
08
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
R7020 determination: rdar://10961528
Platform Power Good
RSMRST# is asserted when power good from regulator is de-asserted in the
The SMC guarantees proper assertion and de-assertion of RSMRST# for
Power off or loss of AC:
Asserted at least 10 ms after all suspend well power is valid
First
Second
Need AND Gate to deassert PM_PCH_PWROK to PCH when unexpected power loss happensradar://11043352
To PCH
To PCH
Third
SMC_S5_PWRGD_VIN input is above comparator input level of 1.5 V.
to allow PCH to switch suspend well to battery without excessive loading
The iMac K70K72 designs does not support Deep Sx modes so both DPWROK and
normal operation via PM_DSW_PWRGD.
event AC is lost. Power good de-assertion should happen quickly enough
Secondary method:
To PCH
From SMC
Note:
Requirements:
Power on:
normal operation.
Primary method:
RSMRST# signals are shorted together
Intel Doc# 29517 Maho Bay PDG, Section 22.13 Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8
Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V
SMC asserts RSMRST# (PM_DSW_PWRGD) when SMC_S5_PWRGD_VIN input drops from
SMC de-asserts RSMRST# (PM_DSW_PWRGD) when S5_PWRGD input is asserted and
To SMC
To SMC
From SMC
To PCH
to meet Intel spec.
To PCH
1.8 V to 1.5 V (as implemented) when 12 V S5 rail drops to 10 V.
Resume Reset
The SMC guarantees proper assertion and de-assertion of RSMRST# for
(9V/9.58V; 580MV HYSTERESIS)
PCH Power Goods
PGOOD COMPARATORS FOR PP12V_S0
To SMC, for 99ms delay
Derive SMC ALL_SYS_PWRGD
The end of the power sequence for S0 rails except CPU CORE.
5
25 66
120
38 47 48
122
402
1/16W
0
MF-LF
5%
R7021
R7020
402
1/16W
5%
MF-LF
110
R7023
NOSTUFF
402
5% 1/16W MF-LF
0
402
NOSTUFF
MF-LF
5%
1/16W
0
R7022
19 48
120
47
121
65 71
120
47 48 65
120
65 71
120
47
402
68K
5% 1/16W MF-LF
R7030
33K
1/16W
5% MF-LF
402
R7031
19 65
120
47 48 65
120
1/16W
0
402
5%
MF-LF
RSMRST:SMC
R7032
5
47 65
117
19 65
120
RSMRST:GATE
5%
0
402
1/16W MF-LF
R7035
64
120
64 70
120
15 19 26 35 43 80
120
R7024
402
1K
1/16W MF-LF
5%
19
120
R7086
10K
MF-LF
5%
402
1/16W
2N7002DW-X-G
Q7080
SOT-363
MF-LF
5% 1/16W
10K
402
R7084
SOT-363
Q7080
2N7002DW-X-G
R7083
49.9K
1/16W MF-LF
402
1%
C7080
CERM
0.1UF
20% 16V
603
1/16W
100K
MF-LF
1%
402
R7081
R7082
1/16W
402
MF-LF
1%
SOT23-5-HF
CRITICAL
U7080
LM397
0
1/16W
5%
MF-LF
402
R7087
402
MF-LF
1/16W
1%
33.2K
R7080
TSSOP-HF
14
7
PLACE_SIDE=BOTTOM
U7000
74LVC08
U7000
74LVC08
7
14
TSSOP-HF
PLACE_SIDE=BOTTOM
U7000
74LVC08
PLACE_SIDE=BOTTOM
7
14
TSSOP-HF
PLACE_SIDE=BOTTOM
TSSOP-HF
14
7
U7000
74LVC08
0402
C7000
0.1UF
16V X7R-CERM
10%
X7R-CERM
16V
C7021
0402
10%
0.1UF
PM Power Good
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
PM_PCH_PWROK
=PP3V3_S5_PWRCTL
9V_COMP_REF
12V_COMP_REF
=PP3V3_S5_PWRCTL
=PP3V3_S4_PWRCTL
=PP12V_S5_PWRCTL
PGOOD_P12V_S0
PGOOD_P12V_S0_R
PM_PCH_SYS_PWROK
PGOOD_12V_S0_G1
=PP12V_S5_PWRCTL
=PP12V_S0_PWRCTL
SMC_S5_PWRGD_VIN
PM_RSMRST_PCH_L
=PP12V_S5_PWRCTL
PM_RSMRST_PCH_L
S5_PWRGD
PM_DSW_PWRGD
MAKE_BASE=TRUE
PM_PGOOD_REG_P3V3_S5
PM_PCH_APWROK
PGOOD_12V_S0_G2
PM_DSW_PWRGD
PM_PGOOD_REG_P3V3_S5
PM_RSMRST_PCH_L_R
=PP3V3_S5_PWRCTL
PM_PGOOD_REG_ALL_P1V05_S0
PM_PGOOD_REG_VCCSA_S0
ALL_SYS_PWRGD
PM_PGOOD_REG_CPUCORE_S0
SYS_PWROK_R
=PP3V3_S5_PWRCTL
ALL_SYS_PWRGD
PM_PCH_PWROK_APWROK
=PP3V3_S5_PWRCTL
SMC_DELAYED_PWRGD
prefsb
051-9505
8.0.0
70 OF 144 65 OF 123
1 2
1 2
1
2
1 2
1
2
1
2
1 2
1 2
1 2
1
2
3
5
4
1
2
6
2
1
1
2
2
1
1
2
1 2
1
2
3
4
5
1 2
1
2
6
5
4
11
12
13
8
9
10
3
2
1
2
1
2
1
6
64 65
6
64 65
6
72 74
6
64 65 74
64 74
120
6
64 65 74
6
6
64 65 74
120
6
64 65
122
6
64 65
5
47 65
117
6
64
65
VR_RDYS
IMONS
FS_DRP
VCC
ISEN1+
PWM1
ISEN1-
PWM2 ISEN2+ ISEN2-
PWM3
ISEN3-
ISEN3+
TMS
ISEN4-
ISEN4+
PWM4
FSS_DRPS
EN_VTT
RSET
VSENS
RAMP_ADJ
FBS
RGNDS
VR_RDY
COMPS
SVCLK
SVDATA
SVALERT*
VSEN
FB
RGND
PSICOMP
COMP
IMON
VR_HOT* TM
THRM
ISENS-
ISENS+
PWMS
HFCOMPS/DVCS
EN_PWR
ADDR_IMAXS_TMAX
NPSI_DE_IMAX
BT_FDVID_TCOMP
BTS_DES_TCOMPS
SICI
HFCOMP
PAD
IN
IN
OUT
IN
BI
OUT
OUT
OUT
OUT
IN IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
To Core VSense
To Core HF comp
Max peak current:
AXG voltage sense input
AXG sense from CPU
12.7 A (BUDGET)
CPU AXG S0 Regulator
30.0 A (BUDGET) 290 kHz
OC trip point:
Max avg current:
To sense amps
OC trip point:
To AXG HF comp
(core comp out)
63 A (BUDGET) 110 A (BUDGET)
Straps 1
Switching freq:
(pu 1)
(core hf comp)
(straps 1)
(axg hf comp)
(core fb in)
(pgood)
(pu 2)
(pu 2)
(pu 2)
(pu 2)
(axg fb in)
(pgood)
290 kHz
To XDP
(pu 2)
(straps 2)
(straps 2)
(axg imon out)
(straps 1)
(straps 1)
Straps 2
(core vsen in)
Max avg current: Max peak current:
Switching freq:
To Core feedback
? A (nom)/? A (min)
Pull-ups 2
To Core PSI comp
(vr hot out)
(core imon out)
VRHot to ProcHot
CHANGES TO THE CPU CONTROLLER D8 VR_HOT RDAR://11093493
(pu 1)
(pu 1)
(core psi comp)
To AXG VSense
? A (nom)/? A (min)
(axg vsen in)
Pull-ups 1
Core sense from CPU
(straps 1)
(axg comp out)
Core temp measurement
AXG temp measurement
(straps 2)
To AXG feedback
AXG compensation and feedback
Core voltage sense input
Power goods
Core compensation and feedback
To AXG voltage sense
CPU Core S0 Regulator
AXG IMON output
Core IMON output
To Core voltage sense
To sense amps
ISL6364
QFN
U7100
68
109
13
109
402
5%
R7175
0
1/16W MF-LF
R7170
1/16W
0
5%
MF-LF
402
SM
XW7172
L7330.2:51MM
OMIT
5%
R7172
1/16W MF-LF
1K
402
1/16W
5%
MF-LF
10
402
R7176
SIGNAL_MODEL=EMPTY
5%
1/16W
10
402
SIGNAL_MODEL=EMPTY
R7171
MF-LF
5%
1K
402
1/16W MF-LF
R7177
249
402
1/16W
1% MF-LF
R7163
1% MF-LF
402
301
1/16W
R7162
R7165
10
1/16W MF-LF
402
1%
U7100.49:9MM
XW7100
SM
OMIT
6.8K
0603
RT7190
1K
402
MF-LF
5%
R7190
1/16W
1/16W MF-LF
402
5%
1K
R7192
RT7192
6.8K
0603
2.2
805
1/8W
5% MF-LF
R7100
R7102
201
1/20W MF
255K
1%
R7103
MF
1/20W 201
953K
1%
13 66
109
13 66
109
13 66
109
1/16W
5%
0
402
MF-LF
R7109
255K
1/20W 201
MF
1%
R7104
2.74K
402
R7195
MF-LF
1/16W
1%
402
R7196
MF-LF
1% 1/16W
6.65K
1% MF-LF
402
R7119
1/16W
110
1%
402
MF-LF
1/16W
90.9
R7118
NOSTUFF
R7117
1/16W 402
1%
54.9
MF-LF
0
1/16W MF-LF
402
5%
R7193
11 47 48
103
51 66
109
51 66
109
402
MF-LF
5%
1K
1/16W
R7198
402
5% 1/16W MF-LF
10K
R7199
5
25 65
120
R7125
1/16W
MF-LF
5%
0
402
402
1/16W
5%
R7126
MF-LF
0
5%
0
R7127
1/16W
MF-LF
402
1/16W
R7128
5%
0
MF-LF
402
68
109
68
109
5%
0
1/16W
MF-LF
R7129
402
68 109
R7101
1% MF
1/20W
953K
201
R7105
1% 1/20W
16.5K
MF 201
1/20W
1% MF
R7106
26.1K
201
MF
R7114
402
1.18M
1% 1/16W
C7161
39PF
5%
0402
50V CERM
C7131
5% 50V
82PF
0402
CERM
C7133
390PF
X7R-CERM
50V
10%
0402 0402
390PF
50V
10% X7R-CERM
C7136
C7135
0402
X7R-CERM
16V
20%
0.01UF
0.0012UF
C7130
0402
50V CERM
10%
0402
50V CERM
10%
0.0012UF
C7141 C7146
CERM
10% 50V
0402
0.0012UF
0402
50V CERM
10%
0.0012UF
C7171
0.0012UF
0402
10% 50V CERM
C7176
1%
R7116
1/16W MF-LF 402
14.0K
NOSTUFF
0.01UF
20% X7R-CERM
16V
C7165
0402
NOSTUFF
0402
0.0012UF
C7148
50V CERM
10%
0.0012UF
NOSTUFF
0402
50V CERM
10%
C7178
0.0033UF
C7134
10% 50V
X7R-CERM
0402
1/16W
1% MF-LF
402
R7160
11.8K
MF-LF
3.09K
R7166
402
1/16W
1%
MF
R7107
201
24.3K
1/20W
1%
MF
1%
R7108
17.4K
201
1/20W
16V
10%
C7117
0.1UF
0402
X7R-CERM
16V
10%
0.1UF
C7150
X7R-CERM 0402
C7190
X7R-CERM 0402
0.1UF
10% 16V
16V
10%
0.1UF
0402
X7R-CERM
C7192
C7195
X7R-CERM 0402
0.1UF
16V
10%
68 109
10UF
C7100
0805
10% 25V X6S
1%
2.43K
1/16W MF-LF 402
R7131
402
MF-LF
1/16W
2.43K
1%
R7161
10% 50V X7R-CERM 0402
0.0018UF
C7160
1%
MF-LF
1/16W
15.4K
R7181
402
402
1/16W
13.7K
MF-LF
1%
R7151
1% 1/16W MF-LF
402
R7136
215K
67 109
67 109
67 109
R7120
0
NOSTUFF
1/16W 402
MF-LF
5%
67
109
402
5%
R7121
1/16W MF-LF
0
NOSTUFF
0
R7122
1/16W
5%
NOSTUFF
MF-LF 402 402
R7123
1/16W
5%
NOSTUFF
MF-LF0MF-LF
NOSTUFF
R7124
402
1/16W
5%
0
64
120
67
109
NOSTUFF
1/20W
5%
R7112
201
MF
0
1/20W
NOSTUFF
R7110
201
MF
5%
0
R7111
105K
201
1/20W MF
1%
R7113
201
1/20W MF
1%
124K
67
109
R7115
NOSTUFF
201
1/20W MF
10K
5%
402
10% 16V
C7180
0.082UF
CERM-X7R
1%
90.9
R7180
1/16W MF-LF
402
NOSTUFF
1/16W
100K
MF-LF
402
5%
R7182
NOSTUFF
100K
5%
402
MF-LF
1/16W
R7152
1/16W
5%
402
MF-LF
0
R7150
67
109
100K
1/16W 402
MF-LF
5%
R7197
67
109
4.99K
1/16W
1%
402
MF-LF
R7130
MF-LF
249
1% 1/16W
402
R7133
402
1%
499
R7132
MF-LF
1/16W
1%
100
402
MF-LF
1/16W
R7134
1%
402
1/16W MF-LF
10
R7135
67
109
MF-LF
402
5%
0
R7140
1/16W
SIGNAL_MODEL=EMPTY
1/16W
10
MF-LF
5%
402
R7141
1K
402
R7142
MF-LF
1/16W
5%
R7230.2:71MM
XW7142
OMIT
SM
13
109
68
109
SIGNAL_MODEL=EMPTY
MF-LF
1/16W
5%
10
R7146
402
R7145
402
MF-LF
1/16W
0
5%
13
109
R7147
MF-LF
1/16W
1K
5%
402
OMIT
XW7147
SM
XW7142.2:2MM
OMIT
SM
XW7177
XW7172.2:5MM
13
109
SYNC_MASTER=D8_MLB
VReg CPU Core/AXG Cntl
SYNC_DATE=08/27/2012
AGND_CPU
CPUCORE_IMON_R
REG_VCC_U7100
REG_VCC_U7100
SNS_AXG_XW_N
AGND_CPU
REG_CPUAXG_VSEN
AGND_CPU
CPUAXG_IMON_R
=PPVAXG_S0_CPU
CPUAXG_COMP_RC
REG_CPUAXG_COMP
CPUAXG_FB_R_2
REG_CPUAXG_FB
CPUAXG_FB_R_1
CPUCORE_FB_R_1
=PPVCCIO_S0_CPU
REG_VCC_U7100REG_VCC_U7100
AGND_CPU
REG_CPUAXG_TM
REG_CPUCORE_TM
AGND_CPU
REG_CPUAXG_RGND
REG_CPUAXG_PGOOD
REG_CPUCORE_SW_FREQ
REG_CPUCORE_IMON
CPU_VIDALERT_L
REG_VCC_U7100
REG_CPUAXG_VSEN
REG_VCC_U7100
REG_PWM_CPUAXG_R
REG_PWM_CPUCORE_2_R
REG_CPUCORE_NPSI
CPUCORE_FB_R_2
AGND_CPU
CPU_VIDSOUT
CPU_VIDSCLK
REG_CPUCORE_FB
REG_CPUCORE_VSEN
CPU_VIDALERT_L
REG_CPUAXG_TCOMP REG_CPUCORE_SUTH
REG_CPUCORE_FDVID
AGND_CPU
PP12V_S0_CPUCORE_FLT
CPUCORE_EN_PWR_R
CPUAXG_FB_RC
REG_CPUAXG_HFCOMP
CPUCORE_PSICOMP_RC
REG_ISENAXG_PR
REG_PWM_CPUCORE_3_R
REG_PWM_CPUCORE_1_R
REG_PWM_CPUAXG
REG_PWM_CPUCORE_4_R
REG_CPUAXG_IMON
REG_ISENCORE_2_NR
REG_ISENCORE_3_P
REG_ISENCORE_4_P
REG_CPUCORE_RGND
REG_CPUCORE_VSEN
AGND_CPU
REG_CPUAXG_IMON
AGND_CPU
AGND_CPU
SNS_AXG_R_N
SNS_CORE_R_N
CPUCORE_COMP_RC
REG_CPUCORE_RGND
REG_CPUCORE_SW_FREQ REG_CPUCORE_RAMPADJ
REG_CPUCORE_RAMPADJ
REG_CPUAXG_SW_FREQ
REG_ISENCORE_4_NR
REG_ISENCORE_3_NR
REG_ISENCORE_2_P
CPU_VIDSOUT
CPU_VIDSCLK
REG_CPUCORE_SUTH
REG_CPUAXG_TCOMP
REG_CPUCORE_PGOOD
REG_CPUAXG_COMP
REG_CPUAXG_FB
REG_CPUCORE_IAUTO
REG_CPUCORE_PSICOMP
REG_CPUAXG_TM
REG_CPUAXG_VSEN
REG_CPUAXG_SW_FREQ
SNS_CPU_VCORE_N
SNS_AXG_XW_P
REG_ISENCORE_1_NR
REG_PWM_CPUCORE_3
REG_PWM_CPUCORE_4
REG_CPUCORE_PGOOD
=PP3V3_S0_VRD
REG_CPUAXG_PGOOD
=PP3V3_S0_VRD
SNS_CORE_XW_N
SNS_CORE_R_P
REG_CPUCORE_VRHOT_L
REG_ISENCORE_1_P
SNS_AXG_R_P
SNS_CPU_VAXG_N
REG_CPUAXG_RGND
REG_CPUAXG_HFCOMP
REG_CPUCORE_TM
REG_CPUCORE_IMON
REG_CPUCORE_HFCOMP
REG_CPUCORE_FDVID
PP12V_S0_CPUCORE_FLT
AGND_CPU
REG_CPUCORE_NPSI
REG_VCC_U7100
REG_PWM_CPUCORE_2
REG_ISENAXG_NR
REG_PWM_CPUCORE_1
CPU_PROCHOT_L
AGND_CPU
=PP5V_S0_REG_CPUCORE
SNS_CORE_XW_P
CPUCORE_FB_RC
REG_CPUCORE_PSICOMP
PM_PGOOD_REG_CPUCORE_S0
MAKE_BASE=TRUE
SNS_CPU_VCORE_P
REG_CPUCORE_COMP
REG_CPUCORE_VRHOT_L
REG_CPUCORE_RSET
REG_CPUCORE_EN_PWR
PM_EN_REG_CPUCORE_S0
REG_CPUCORE_COMP
REG_VCC_U7100
REG_CPUCORE_FB
SNS_CPU_VAXG_P
=PPVCORE_S0_CPU
AGND_CPU
AGND_CPU
REG_CPUCORE_HFCOMP
REG_CPUCORE_VSEN
prefsb
051-9505
8.0.0
71 OF 144 66 OF 123
17
14
34
35
46
38
45
36 42 41
39
47
48
23
43
44
37
22
40
33
20
2
19 21
13
18
12
10
11
4
7
3
6
8
9
15 31
49
25
24
26
16
1
27
28
29
30
32
5
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1
2
1
2
1 2
1 2
2
1
1
2
1
2
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1 2
1 2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
1 2
1
2
1 2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
2
1
1
2
1
2
1 2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2 1 2
1 21 2
1 21 2
1 21 2
1 2
66 67 68
109
109
66
109
66
109
109
66 67 68
109
66
109
66 67 68
109
109
6
13 17
51
109
66
109
109
66
109
109 109
6
10 11 13 16 28
66
109
66
109
66 67 68
109
66
109
66
109
66 67 68
109
66
109
5
66
121
66 109
13 66
109
66
109
66
109
66
109
109
109
66
109
109
66 67 68
109
13 66
109
13 66
109
66
109
66 109
66
109
66
109
66
109
66 67 68
109
66 67 68
109
109
109
66
109
109
109
109
109
51 66 109
66
109
66
109
66 67 68
109
66 67 68
109
66 67 68
109
109
109
109
66
109
66
109
66
109
66 109
66 109
66
109
66
109
66
121
66 109
66
109
109
66 109
66
109
66
109
66
109
109
66
121
6
66 69 70 72 96 99
5
66
121
6
66 69 70 72 96 99
109
109
66
121
109
66
109
66
109
66
109
51 66
109
66 109
66
109
66 67 68
109
66 67 68
109
66
109
66
109
66 67 68
109
6
109
109
66
109
66 109
66
121
109
109
66
109
66
109
66
109
6
13 16
51
66 67 68
109
66 67 68
109
66
109
66
109
OUT
OUT
OUT
OUT
OUT
OUT
OUT
S
D
G
S
D
G
S
D
G
NC
NC
IN
NC
NC
IN
NC
NCNC
NCNC
NCNC
D
G
S
D
G
S
D
G
S
BOOT
UGATE
PHASE
NC NC
GND
LGATE
VCC
PVCC
THRML
PWM
PAD
BOOT
UGATE
PHASE
NC NC
GND
LGATE
VCC
PVCC
THRML
PWM
PAD
GDSEL
LGATE
VCC
PWM
BOOT
UGATE
GND
THRML
PHASE
LVCC
UVCC
PAD
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CPU Output Decoupling
CPU Phase 2
CPU Phase 3
CPU Phase 1
Filtered 12V Rail
66
109
NOSTUFF
R7237
2.2
5% 1/8W MF-LF 805
SIGNAL_MODEL=EMPTY
R7241
1.02K
1/16W
1%
402
MF-LF
66
109
66
109
6
67 68
603
5% 1/10W
10
MF-LF
R7267
0
MF-LF
R7256
5%
1/10W
603
NOSTUFF
R7257
2.2
5% 1/8W MF-LF 805
MF-LF
1/16W
1%
402
R7261
1.02K
SIGNAL_MODEL=EMPTY
66
109
66
109
6
67 68
Q7210
DIRECTFET-SA
IRF6802SDTRPBF
CRITICAL
Q7210
CRITICAL
IRF6802SDTRPBF
DIRECTFET-SA
Q7250
IRF6802SDTRPBF
DIRECTFET-SA
CRITICAL
603
MF-LF
1/10W
5%
0
R7216
66
109
66
109
CRITICAL
0.0005
R7230
MF
0612
1W
1%
CRITICAL
MF
1W
1%
0.0005
0612
R7250
DIRECTFET-MX
CRITICAL
Q7211
IRF6893MTRPBF
Q7231
IRF6893MTRPBF
DIRECTFET-MX
CRITICAL
IRF6893MTRPBF
CRITICAL
Q7251
DIRECTFET-MX
ISL6612
U7230
CRITICAL
QFN1
ISL6612
U7250
CRITICAL
QFN1
SIGNAL_MODEL=EMPTY
C7221
220PF
10% X7R-CERM
50V 0402
SIGNAL_MODEL=EMPTY
0402
50V X7R-CERM
220PF
10%
C7241
SIGNAL_MODEL=EMPTY
0402
50V
10%
220PF
X7R-CERM
C7261
X7R-CERM
50V
NOSTUFF
0402
C7217
0.001UF
10%
0.001UF
0402
NOSTUFF
50V X7R-CERM
10%
C7237
10% X7R-CERM
50V 0402
0.001UF
C7257
NOSTUFF
270UF-0.006OHM
CRITICAL
C7280
CASE-D2
20% 2V TANT TANT
2V
20%
CASE-D2
C7281
CRITICAL
270UF-0.006OHM
TANT
2V
20%
CASE-D2
CRITICAL
270UF-0.006OHM
C7282
TANT
2V
20%
CASE-D2
C7283
270UF-0.006OHM
CRITICAL
TANT
2V
20%
CASE-D2
C7284
270UF-0.006OHM
CRITICAL
20%
CASE-D2
2V TANT
CRITICAL
C7285
270UF-0.006OHM
0.1UF
0402
10% 16V X7R-CERM
C7240
X7R-CERM
10%
0.1UF
C7220
0402
16V
C7260
X7R-CERM
16V
10%
0402
0.1UF
0603
0.22UF
10% 25V X7R
C7236
0603
0.22UF
10% 25V X7R
C7256
X7R
16V
10%
0603
1.0UF
C7225
1.0UF
0603
10% 16V X7R
C7226
10% X7R
16V 0603
1.0UF
C7227
1.0UF
0603
10% 16V X7R
C7245
1.0UF
0603
10% 16V X7R
C7247
C7265
X7R
10%
1.0UF
16V 0603 0603
10% 16V X7R
1.0UF
C7267
1UF
X6S-CERM
25V
10%
0402
EMC
C7214
25V
10%
1UF
EMC
C7215
X6S-CERM 0402
EMC
1UF
0402
10% 25V X6S-CERM
C7235
EMC
1UF
0402
10% 25V X6S-CERM
C7234
X6S-CERM
25V
10%
0402
1UF
EMC
C7255
0402
X6S-CERM
25V
10%
1UF
EMC
C7254
X6S-CERM
16V
20%
0603
10UF
C7212
CRITICAL
16V 0603
C7213
20%
10UF
X6S-CERM
10UF
0603
20% 16V X6S-CERM
C7233
10UF
20%
C7232
0603
X6S-CERM
16V
X6S-CERM
16V
20%
0603
10UF
C7253C7251
16V
20%
0603
10UF
X6S-CERM
X7R
25V
10%
0603
0.22UF
C7216
TH1
180UF
20% 16V
CRITICAL
POLY
C7291
C7292
TH1
180UF
20% 16V POLY
CRITICAL
180UF
20% 16V POLY
C7293
CRITICAL
TH1
POLY
C7294
20% 16V
180UF
CRITICAL
TH1
C7295
16V POLY
CRITICAL
20%
180UF
TH1
SDP110808M-TH
CRITICAL
L7210
0.24UH-30A-0.35MOHM
L7230
0.24UH-30A-0.35MOHM
CRITICAL
SDP110808M-TH
CRITICAL
L7250
0.24UH-30A-0.35MOHM
SDP110808M-TH
0.36UH-30A-0.6MOHM
L7200
CRITICAL
SDP110808MR36MF-TH
805
NOSTUFF
R7217
5%
2.2
MF-LF
1/8W
CRITICAL
ISL6622
U7210
DFN
66
109
CRITICAL
0.0005
MF
1W
1%
0612
R7210
SIGNAL_MODEL=EMPTY
R7221
1.02K
1% 1/16W MF-LF
402
66
109
6
67 68
R7247
10
5% MF-LF
603
1/10W
603
0
5% 1/10W MF-LF
R7236
SYNC_MASTER=D8_MLB
SYNC_DATE=08/27/2012
VReg CPU Core Phases
=PP12V_S0_REG_CPUCORE
PP12V_S0_CPUCORE_FLT
PPCPUCORE_S0_SENSE_1
REG_PHASE_CPUCORE_1
PPCPUCORE_S0_SENSE_2
REG_PHASE_CPUCORE_2
PPCPUCORE_S0_SENSE_3
REG_LGATE_CPUCORE_2
REG_BOOT_CPUCORE_1_RC
REG_UGATE_CPUCORE_1
PP12V_S0_CPUCORE_FLT
PP12V_S0_CPUCORE_FLT
REG_PWM_CPUCORE_3
PP12V_S0_CPUCORE_FLT
REG_SNUBBER_CPUCORE_1
REG_LGATE_CPUCORE_3
REG_LVCC_U7250
REG_LVCC_U7230
REG_LVCC_U7210
REG_BOOT_CPUCORE_3_RC
REG_BOOT_CPUCORE_2_RC
REG_ISENCORE_1_N
REG_UGATE_CPUCORE_2
PPCPUCORE_S0_REG
REG_BOOT_CPUCORE_1
REG_ISENCORE_3_N
REG_PWM_CPUCORE_1
REG_LGATE_CPUCORE_1
REG_PWM_CPUCORE_2
REG_BOOT_CPUCORE_2
REG_BOOT_CPUCORE_3
REG_ISENCORE_1_NR
REG_ISENCORE_2_NR
REG_ISENCORE_3_NR
REG_SNUBBER_CPUCORE_2
REG_SNUBBER_CPUCORE_3
AGND_CPU
AGND_CPU
AGND_CPU
REG_ISENCORE_3_P
PPCPUCORE_S0_REG
REG_UGATE_CPUCORE_3
PPCPUCORE_S0_REG
PPCPUCORE_S0_REG
REG_ISENCORE_1_P
REG_ISENCORE_2_P
REG_ISENCORE_2_N
PP12V_S0_CPUCORE_FLT
REG_PHASE_CPUCORE_3
prefsb
051-9505
8.0.0
72 OF 144 67 OF 123
1
2
1 2
1
2
1
2
1
2
1 2
3 7
2
8
4 5
1
6
3 7
2
8
1
2
4 3
2 1
4 3
2 1
5
3 4
71 2 6
5
3 4
71 2 6
5
3 4
71 2 6
2
1
10
3 8
5
6
7
9
11
4
2
1
10
3 8
5
6
7
9
11
4
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
21
21
21
21
1
2
3
6
9
4
2
1
5
11
10
7
8
43
21
1 2
1
2
1
2
6
66 67 68
109
109
109
109
109
109
109
109
109
66 67 68
109
66 67 68
109
66 67 68
109
109
109
109
109
109
109
109
109
109
109
109
109
109
109
109
109
66 67 68
109
66 67 68
109
66 67 68
109
109
6
67 68
109
66 67 68
109
109
GDSEL
LGATE
VCC
PWM
BOOT
UGATE
GND
THRML
PHASE
LVCC
UVCC
PAD
IN
OUT
NC
S
D
G
OUT
OUT
OUT
NC
IN
NC
NCNC
D
G
S
D
S
G
S
G
D
BOOT
UGATE
PHASE
NC NC
GND
LGATE
VCC
PVCC
THRML
PWM
PAD
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CPU Phase 4
AXG Phase
10
603
1/10W
R7347
5% MF-LF
NOSTUFF
603
MF-LF
5%
0
1/10W
R7336
CRITICAL
DFN
ISL6622
U7330
66
109
66
109
Q7250
CRITICAL
DIRECTFET-SA
IRF6802SDTRPBF
2.2
R7317
1/8W MF-LF 805
5%
NOSTUFF
1/10W
5% MF-LF
603
0
R7316
6
67
66
109
66
109
402
1% 1/16W MF-LF
1.02K
R7321
SIGNAL_MODEL=EMPTY
R7327
603
MF-LF
1/10W
5%
10
66
109
CRITICAL
R7310
0.0005
0612
1W MF
1%
CRITICAL
IRF6893MTRPBF
DIRECTFET-MX
Q7311
CRITICAL
DIRECTFET_S3C
Q7331
649135PBF
649136PBF
S1
CRITICAL
Q7330
QFN1
ISL6612
U7310
CRITICAL
SIGNAL_MODEL=EMPTY
0402
50V X7R-CERM
220PF
10%
C7321
0402
10% 50V X7R-CERM
220PF
C7341
SIGNAL_MODEL=EMPTY
R7342
301
1/16W
1%
402
MF-LF
C7337
X7R-CERM
0.001UF
NOSTUFF
0402
50V
10%
NOSTUFF
C7317
50V
0.001UF
X7R-CERM 0402
10%
X7R-CERM
C7340
0402
16V
10%
0.1UF
0.1UF
C7320
0402
10% 16V X7R-CERM
C7316
0603
0.22UF
10% 25V X7R
X7R
10%
0603
25V
0.22UF
C7336
16V
C7325
0603
1.0UF
10% X7R
C7327
X7R 0603
1.0UF
10% 16V
1.0UF
C7345
16V
10% X7R
0603
X7R
16V
10%
0603
C7346
1.0UF
C7347
0603
10% 16V X7R
1.0UF
EMC
X6S-CERM
25V
10%
0402
C7314
1UF
X6S-CERM
25V
10%
0402
1UF
EMC
C7315
C7335
25V
10%
0402
1UF
EMC
X6S-CERM
EMC
1UF
0402
10% 25V X6S-CERM
C7334
C7312
10UF
0603
X6S-CERM
16V
20%
X6S-CERM
16V
20%
0603
10UF
C7313
10UF
0603
20% 16V X6S-CERM
C7333
10UF
0603
20% 16V X6S-CERM
C7332
CRITICAL
20% POLY
16V
180UF
TH1
C7396
CRITICAL
C7397
180UF
POLY TH1
20% 16V
CRITICAL
180UF
C7398
TH1
20% 16V POLY
CRITICAL
POLY
16V
20%
180UF
TH1
C7399
0.24UH-30A-0.35MOHM
SDP110808M-TH
CRITICAL
L7310
SDP110808M-TH
CRITICAL
0.24UH-30A-0.35MOHM
L7330
SIGNAL_MODEL=EMPTY
C7342
0402
120PF
5% 50V C0G-CERM
6
17
66
109
402
R7341
1.02K
1% 1/16W MF-LF
SIGNAL_MODEL=EMPTY
0.0005
1W
CRITICAL
MF
0612
1%
R7330
2.2
NOSTUFF
1/8W 805
MF-LF
5%
R7337
SYNC_MASTER=D8_MLB
VReg CPU AXG Phases
SYNC_DATE=08/27/2012
REG_LGATE_CPUCORE_4
PP12V_S0_CPUCORE_FLT
REG_UGATE_CPUCORE_4
REG_LVCC_U7310
REG_ISENAXG_N
AGND_CPU
AGND_CPU
REG_ISENCORE_4_NR
REG_SNUBBER_CPUAXG
REG_PWM_CPUCORE_4
REG_PWM_CPUAXG
REG_UGATE_CPUAXG
REG_BOOT_CPUCORE_4
REG_BOOT_CPUCORE_4_RC
REG_BOOT_CPUAXG_RC
REG_LVCC_U7330
REG_ISENCORE_4_P
REG_BOOT_CPUAXG
PPCPUCORE_S0_REG
REG_LGATE_CPUAXG
PP12V_S0_CPUCORE_FLT
PP12V_S0_CPUCORE_FLT
REG_ISENCORE_4_N
REG_SNUBBER_CPUCORE_4
REG_PHASE_CPUAXG
PPCPUAXG_S0_SENSE
REG_PHASE_CPUCORE_4
PPCPUCORE_S0_SENSE_4
REG_ISENAXG_NR
PPCPUAXG_S0_REG
REG_ISENAXG_PR
AGND_CPU
REG_ISENAXG_P
prefsb
051-9505
8.0.0
73 OF 144 68 OF 123
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1
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8
4 5
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1
2
1 2
1
2
4 3
2 1
5
3 4
71 2 6
128
356
7
4
3
4
2
1
5 6
2
1
10
3 8
5
6
7
9
11
4
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
21
21
2
1
1 2
43
21
1
2
109
66 67 68
109
109
109
109
66 67 68
109
66 67 68
109
109
109
109
109
109
109
109
109
66 67 68
109
66 67 68
109
109
109
109
109
109
109
66 67 68
109
109
OUT
PHASE
BOOT
UGATE
LGATE
PHASE
RTN
FSEL
PGOOD
OCSET
VO
SREF
VCC
PVCC
GND
PGND
EN
FB
IN
OUT
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Vout = 0.5 * (1 + Ra / Rb)
(reg_phase_vccsas0)
Regulator requires
prevent noise in the audio frequencies
<Rb>
<Ra>
a minimum load to
Max avg current:
500 kHz
8.10 A (BUDGET)
8.50 A (BUDGET) ? A (min)/? A (max)
<Rb>
<Ra>
Max peak current: OC trip point: Switching freq:
Note:
To regulator:
CPU VccIO (1.05V) S0 Regulator
6
NP0-C0G
5%
402
EMC
25V
1000PF
C7481
Q7410.2:30MM
5% NP0-C0G
EMC
402
25V
C7480
1000PF
Q7410.2:30MM
R7417
2.2
MF-LF
5% 1/10W
603
NOSTUFF
C7422
6.3V
20%
10UF
603
X5R
Q7410
POWER56
FDMS3602S
CRITICAL
R7401
805
1/8W MF-LF
5%
2.2
805
1/8W
MF-LF
5%
10
R7400
10%
1UF
X5R
16V 402
C7400
U7400
ISL95870
UTQFN
CRITICAL
5% 1/16W MF-LF
402
R7460
0
U1000.T2:8MM
SM
SIGNAL_MODEL=EMPTY
XW7435
MF-LF
SIGNAL_MODEL=EMPTY
1% 1/16W
402
3.01K
R7435
SIGNAL_MODEL=EMPTY
1%
3.01K
MF-LF
R7430
1/16W
402
64
120
R7436
2.74K
1% 1/16W MF-LF 402
R7431
1%
MF-LF
1/16W
402
2.74K
SM
XW7400
U7400.3:5MM
5
64
120
I44
R7480
20K
1/16W
5%
402
MF-LF
XW7535.2:8MM
SIGNAL_MODEL=EMPTY
XW7430
SM
13
108
13
108
25V X5R-CERM
20%
0603
C7411
C7421
330UF-0.009OHM
20%
CASE-D2-HF
2V POLY
CRITICAL
20% X5R-CERM
0603
25V
C7412
R7416
1/10W
5%
MF-LF
603
0
1.0UH-20%-15A-0.0065OHM
L7410
PIC0605H-SM
10V X5R-CERM
C7401
20%
402
2.2UF
10K
1/16W
1%
MF-LF
R7450
402
402
10K
L7410.2:3MM
MF-LF
1/16W
1%
R7451
5% 50V
0402
10PF
C0G-CERM
C7435
C7430
C0G-CERM 0402
50V
5%
10PF
CRITICAL
C7420
330UF-0.009OHM
2V POLY
20%
CASE-D2-HF
10% 16V
0402
X7R-CERM
0.047UF
C7440
10%
0.1UF
X7R-CERM
16V
C7416
0402
C7417
NOSTUFF
0402
50V X7R-CERM
10%
0.001UF
TH1
180UF
C7410
20% 16V POLY
CRITICAL
R7450.2:3MM
0402
X7R-CERM
16V
20%
0.022UF
C7450
MF-LF
R7418
603
200
5% 1/10W
C7418
NP0-C0G
5%
25V 402
1000PF
SYNC_DATE=08/27/2012
VReg CPU 1.05V S0
SYNC_MASTER=D8_MLB
SNS_CPU_VCCIO_P
SNS_CPU_VCCIO_N
SNS_CPU_P1V05S0_XW_N
REG_CPU_P1V05S0_RTN
PP1V05_S0_CPU_REG
REG_CPU_P1V05S0_OCSET
REG_CPU_PHASE_P1V05S0
REG_CPU_BOOT_P1V05S0
REG_CPU_UGATE_P1V05S0
REG_CPU_P1V05S0_VO
REG_CPU_P1V05S0_SREF
REG_CPU_P1V05S0_FB
REG_CPU_P1V05S0_OCSET
REG_CPU_P1V05S0_PGOOD
SNS_CPU_P1V05S0_XW_P
=PP3V3_S0_VRD
REG_CPU_P1V05S0_PGOOD
REG_CPU_LGATE_P1V05S0
=PP5V_S0_REG_CPU_P1V05
REG_PVCC_U7400
REG_CPU_P1V05S0_VO
PM_EN_REG_CPU_P1V05_S0
REG_CPU_P1V05S0_FSEL
REG_CPU_BOOT_P1V05S0_RC
REG_CPU_SNUBBER_P1V05S0
PM_PGOOD_REG_CPU_P1V05_S0
MAKE_BASE=TRUE
AGND_CPU_P1V05S0
REG_VCC_U7400
=PP12V_S0_REG_CPU_P1V05
prefsb
051-9505
8.0.0
74 OF 144 69 OF 123
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1
2
1
1
2
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1
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1
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2
1
12
11
15
10
2
5
9
7
8
4
13
14
1
16
3
6
1
2
2
1
121
2
1
2
1
2
2
1
1
2
2
1
2
1
1
2
2
1
1
2
21
2
1
1
2
1
2
212
1
1
2
2
1
2
1
2
1
1
2
1 2
1
2
2
1
108
108
69
108
108
108
108
69
108
108
108
69
108
69
121
108
6
66 70 72 96 99
69
121
108
6
108
69
108
108
108
108
108
108
6
OUT
PHASE
OUT
IN
BOOT
UGATE
LGATE
PHASE
RTN
FSEL
PGOOD
OCSET
VO
SREF
VCC
PVCC
GND
PGND
EN
FB
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
<Ra>
<Rb>
Vout = 0.5 * (1 + Ra / Rb)
30 A (BUDGET) ? A (min)/? A (max) 500 kHz
Note:
a minimum load to prevent noise in the audio frequencies
<Rb>
Regulator requires
To regulator:
OC trip point:
Max avg current:
Switching freq:
Max peak current:
<Ra>
(reg_phase_vccsas0)
CPU VccSA (0.925V) S0 Regulator
12.07 A (BUDGET)
5%
1000PF
NP0-C0G
25V 402
C7518
6
2.2
MF-LF
5% 1/10W
603
R7517
NOSTUFF
0
R7516
603
MF-LF
1/10W
5%
10%
2.2UF
X5R
16V 603
C7501
FDMS3602S
POWER56
Q7510
CRITICAL
1/8W
R7501
805
5% MF-LF
2.2
6.3V
20%
10UF
X5R
C7522
603
805
1/8W
MF-LF
5%
R7500
10
10%
1UF
X5R
16V 402
C7500
330UF-0.009OHM
20% 2V POLY
CRITICAL
C7521
CASE-D2-HF
64 65
120
20K
1/16W
5%
402
MF-LF
R7580
XW7535
U1000.T2:4MM
SIGNAL_MODEL=EMPTY
SM
XW7535.2:4MM
SIGNAL_MODEL=EMPTY
XW7530
SM
13
108
MF-LF
1/16W
1%
402
12.1K
R7551
L7510.2:3MM
12.1K
1%
MF-LF
1/16W
402
L7510.1:3MM
R7550
CRITICAL
ISL95870
UTQFN
U7500
64
120
2.32K
SIGNAL_MODEL=EMPTY
402
1% 1/16W MF-LF
R7535
2.32K
1%
402
1/16W MF-LF
R7530
SIGNAL_MODEL=EMPTY
2.74K
1% 1/16W MF-LF 402
R7536
402
0
5% 1/16W MF-LF
R7560
402
MF-LF
1/16W
1%
2.74K
R7531
330UF-0.009OHM
CRITICAL
2V POLY
20%
CASE-D2-HF
C7520
U7500.3:39MM
XW7500
SM
Q7510.2:3MM
C7580
402
X5R
25V
10%
EMC
1UF
C7581
Q7510.2:3MM
10%
1UF
EMC
402
25V X5R
PIC0605H-SM
L7510
1.0UH-20%-15A-0.0065OHM
10PF
0402
50V C0G-CERM
5%
C7535
10PF
5% 50V
0402
C0G-CERM
C7530
0402
0.047UF
C7540
16V X7R-CERM
10%
0402
C7516
16V X7R-CERM
0.1UF
10%
10% X7R-CERM
50V 0402
NOSTUFF
0.001UF
C7517
0603
10% 50V
X7R-CERM
C7550
R7550.2:3MM
0.012UF
POLY
16V
20%
180UF
C7510
TH1
CRITICAL
603
200
5% MF-LF
1/10W
R7518
SYNC_DATE=08/27/2012
VReg CPU VccSA S0
SYNC_MASTER=D8_MLB
REG_VCCSAS0_FB
REG_VCCSAS0_VO
AGND_VCCSAS0
=PP12V_S0_REG_VCCSA
REG_SNUBBER_VCCSAS0
PM_EN_REG_VCCSA_S0
SNS_VCCSAS0_XW_P
=PP5V_S0_REG_VCCSA
REG_VCC_U7500
SNS_CPU_VCCSA
REG_VCCSAS0_PGOOD
=PP3V3_S0_VRD
REG_VCCSAS0_FSEL
REG_VCCSAS0_PGOOD
REG_UGATE_VCCSAS0
REG_VCCSAS0_OCSET
REG_LGATE_VCCSAS0
REG_PVCC_U7500
REG_VCCSAS0_SREF
REG_BOOT_VCCSAS0_RC
REG_VCCSAS0_RTN
REG_VCCSAS0_VO
REG_PHASE_VCCSAS0
PPVCCSA_S0_REG
REG_VCCSAS0_OCSET
PM_PGOOD_REG_VCCSA_S0
MAKE_BASE=TRUE
REG_BOOT_VCCSAS0
SNS_VCCSAS0_XW_N
prefsb
051-9505
8.0.0
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2
2
1
1
2
2
1
1
2
1
2
212
1
1
2
1
2
12
11
15
10
2
5
9
7
8
4
13
14
1
16
3
6
121
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
21
212
1
2
1
2
1
2
1
1 2
1
2
1
2
108
70
108
108
6
108
108
6
108
70
121
6
66 69 72 96 99
108
70
121
108
70
108
108
108
108
108
108
70
108
108
70
108
108
108
PGOOD2
FCCM
VIN
FB1
FSET1
EN2
FSET2
BOOT2
THRM
PGND
EN1
FB2
VOUT2VOUT1
ISEN2ISEN1
OCSET1
OCSET2
LGATE1
LGATE2
PHASE2
BOOT1
UGATE1
LDO5
PGOOD1
VCC1
VCC2
UGATE2
PHASE1
PAD
OUT
IN
OUT
OUT
OUTOUT
IN
PHASE
S
G
G
S
D
D
N-CH
P-CH
IN
G
D
S
G
D
S
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(reg_phase_p3v3s5)
Vout = 0.6 * (1 + Ra / Rb)
between PWM and ultrasonic DCM
(reg_p5vs4_isen)
(reg_p5vs4_ocset)
(reg_phase_p5vs4)
? A (design)/ 6.9 A (budget)
10 A (design)/ 6.08 A (budget)
6 A (design)/ 4.85 A (budget) ? A (nom)/? A (min)
Max avg current:
Max peak current:
OC trip point:
Max peak current:
5V S4 Regulator
? A (nom)/? A (min)
(reg_p5vs4_vout)
<Rb>
<Ra>
(reg_p3v3s4_ocset)
<Ra>
Switching freq:
<Rb>
BURSTMODE_EN_L
Vreg Mode
1
0 PWM
DCM
modes based on load requirements
This circuit toggles the Vreg
Switching freq:
350 kHz
OC trip point:
Vout = 0.6 * (1 + Ra / Rb)
(reg_p3v3s4_vout)
3.3V S5 Regulator
350 kHz
Max avg current:
? A (design)/ 6.6 A (budget)
(reg_p3v3s4_isen)
U7600
ISL62383CRTZ
QFN
CRITICAL
5%
0
603
R7656
1/10W MF-LF
X5R
25V
10%
402
C7656
0.1UF
0.499
1% MF
603
R7657
1/10W
NOSTUFF
MF-LF
1/16W
1%
402
9.76K
R7658
27.0NF
X5R
10V
10%
402
C7658
9.76K
1/16W
1%
402
MF-LF
R7659
XW7650
L7650.2:1MM
SM
OMIT
75K
402
1% 1/16W MF-LF
R7670
1%
402
MF-LF
1/16W
10K
R7671
R7672
1%
402
976
1/16W MF-LF
402
1000PF
5% 25V NP0-C0G
C7672
1% 1/16W MF-LF 402
16.5K
R7673
1%
16.5K
MF-LF 402
1/16W
R7633
1/16W MF-LF
45.3K
402
1%
R7630
1000PF
NP0-C0G
402
5%
25V
C7632
R7632
976
1/16W MF-LF
402
1%
R7631
402
0.5%
10.0K
1/16W
MF
L7610.1:6MM
XW7610
SM
OMIT
CRITICAL
L7610
PAB0705AR-SM
2.2UH-10A-12.5MOHM
X7R-CERM
10%
0.01UF
16V
0402
C7618
R7618
15.8K
402
1%
MF-LF
1/16W
R7619
15.8K
1/16W MF-LF 402
1%
MF-LF
0
5% 1/10W
603
R7616
10% X5R
25V 402
0.1UF
C7616
X5R
16V
10%
1UF
402
C7600
1UF
16V 402
10% X5R
C7602
16V
1UF
402
10% X5R
C7603
805
MF-LF
1/8W
5%
2.2
R7602
6
4.7UF
6.3V 603
20% CERM
C7601
5%
1
805
1/8W MF-LF
R7603
64
120
L7610.1:6MM
C7640
1000PF
NP0-C0G
5%
25V 402
EMC
NOSTUFF
0.499
MF
1/10W
1%
603
R7617
64
120
20K
1/16W
R7680
402
5% MF-LF
R7640
20K
MF-LF
1/16W
5%
402
65
120
6 6
64 74
120
1000PF
L7650.2:4MM
C7680
EMC
402
5% NP0-C0G
25V
603
X5R
6.3V
10UF
C7622
20%
CRITICAL
Q7610
FDMS3602S
POWER56
X5R 603
6.3V
10UF
20%
C7662
CASE-D3L-SM
330UF
POLY-TANT
6.3V
20%
CRITICAL
C7660
2.2UH+/-20%-0.0069OHM-16A
CRITICAL
PIC1005H-SM
L7650
L7610.1:6MM
C7641
EMC
25V
NP0-C0G
1000PF
5%
402
NP0-C0G
L7650.2:4MM
C7681
1000PF
5% 25V
402
EMC
CRITICAL
20%
6.3V POLY-TANT
330UF
CASE-D3L-SM
C7661
Q7650.5:3MM
402
EMC
1UF
10% 25V X5R
C7682
Q7650.5:3MM
C7683
25V
1UF
402
EMC
10% X5R
Q7610.2:3MM
X5R
25V
10%
1UF
EMC
402
C7643
Q7610.2:3MM
EMC
C7642
1UF
25V X5R
10%
402
Q7600
SOT563
NOSTUFF
SSM6L36FE
6
48
117
NOSTUFF
402
MF-LF
10K
5%
1/16W
R7601
402
5%
MF-LF
1/16W
1K
R7600
NOSTUFF
MLP3.3X3.3
CRITICAL
FDMC0223S
Q7655
FDMC0225
MLP3.3X3.3
CRITICAL
Q7650
8X9-TH2
CRITICAL
C7610
270UF
20% 16V
ELEC
270UF
C7650
ELEC
16V
20%
CRITICAL
8X9-TH2 8X9-TH2
CRITICAL
270UF
20% 16V ELEC
C7651
0402
10% 16V X7R-CERM
0.01UF
C7633
X7R-CERM 0402
C7673
16V
10%
0.01UF
0402
NOSTUFF
C7617
50V X7R-CERM
0.001UF
10%
50V
C7657
0.001UF
NOSTUFF
0402
X7R-CERM
10%
0.001UF
NOSTUFF
0402
50V X7R-CERM
10%
C7675
CRITICAL
C7621
150UF
20%
6.3V POLY CASE-B6S-SM
C7620
150UF
CRITICAL
6.3V POLY CASE-B6S-SM
20%
SYNC_DATE=08/27/2012
VReg 3.3V S5/5V S4
SYNC_MASTER=D8_MLB
PP5V_S4_REG
REG_SNUBBER_P5VS4
PM_EN_REG_P3V3_S5
PM_EN_REG_P5V_S4
=PP12V_S5_REG_P3V3P5V_S5
REG_PHASE_P5VS4
REG_BOOT_P3V3S5
REG_P3V3S5_VOUT
REG_P3V3S5_OCSET
REG_PHASE_P3V3S5
REG_P3V3S5_ISEN
REG_U7600_FCCM
REG_P5VS4_VOUT
REG_P5VS4_ISEN
REG_UGATE_P3V3S5
REG_BOOT_P3V3S5_RC
REG_P5VS4_FB
REG_P3V3S5_FB
BURSTMODE_EN
BURSTMODE_EN
PP5V_S5_LDO
REG_P5VS4_FSET
REG_P3V3S5_FSET
REG_VIN_U7600
REG_UGATE_P5VS4
REG_BOOT_P5VS4_RC
REG_U7600_FCCM_R
REG_P3V3S5_VOUT_R
BURSTMODE_EN_L
=PP5V_S5_PWRCTL
REG_LGATE_P3V3S5
REG_P3V3S5_PGOOD
REG_P5VS4_PGOOD
=PP3V3_S5_VRD
=PP3V3_S5_VRD
REG_P3V3S5_PGOOD
REG_U7600_FCCM
REG_P5VS4_PGOOD
REG_P5VS4_VOUT_R
=PP5V_S5_PWRCTL
REG_BOOT_P5VS4
REG_VCC2_U7600
REG_LGATE_P5VS4
REG_VCC1_U7600
REG_P5VS4_OCSET
MAKE_BASE=TRUE
PM_PGOOD_REG_P3V3_S5
PM_PGOOD_REG_P5V_S4
MAKE_BASE=TRUE
REG_SNUBBER_P3V3S5
PP3V3_S5_REG
051-9505
8.0.0
prefsb 76 OF 144 71 OF 123
1
3
17
8
6
24
2
21
29
19
12
28
279
26
10
11 25
16 20
23
15
14
18
7
5
4
22
13
1
2
2
1
1
2
1 2
1 2
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
2
1
21
1 2
1 2
1
2
1
2
2
1
2
1
2
1
2
1
1
2
2
1
1
2
2
1
1
2
1
2
1
2
2
1
2
1
6
1
345
7
2
2
11
2
21
2
1
2
1
1
2
2
1
2
1
2
1
2
1
4
5
2
1
3
6
1
2
12
5
1 2 3
4
5
1 2 3
4
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
1
2
1
2
110
6
110
110
110
110
110
110
71
110
110
110
110
110 110
71
117
71
117
110 110
110
110
110
110
6
71
110
71
121
71
121
6
71
6
71
71 121
71
71
121
110
6
71
110
110
110
110
110
110
V5IN
REFIN
S5
VREF
S3
MODE TRIP
SW
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
VTTREF
DRVH
VBST
VLDOIN
THRM
VTT
GND
PGND
PADGND
IN IN
OUT
OUT
OUT
NC NC
IN
OUT
LX
VDD
VIN
THRM_PAD
PGND
SGND
EN
PG
SYNCH
LX
VFB
NC
NC
VSW
PGND
TGR
TG
BG
VIN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
VDDQ (1.5V) S3 Regulator
9.0 A (BUDGET) ? A (nom)/? A (min)
Need copper around Q7710
<Ra>
1.8V S0 Regulator
Max avg current: OC trip point:
to sink heat
<Rb>
Vout = 1.8 * (Ra / (Ra + Rb))
10mA (max)
<Rb>
PU: PWM
Vout = 0.8 * (1 + Ra / Rb)
<Ra>
400 kHz
PD: PFM (SKIP mode)
Critical:
? kHz
Switching freq:
Max peak current:
? A (nom)/? A (min)
1.7 A (BUDGET)
11.3 A (BUDGET)
0.6 A (BUDGET)
Switching freq:
OC trip point:
Max peak current:
Max avg current:
TPS51916
U7700
QFN
CRITICAL
5% 25V
NOSTUFF
C7717
402
1000PF
NP0-C0G
1/10W 603
0.499
1%
NOSTUFF
R7717
MF
402
X5R
25V
10%
0.1UF
C7716
5%
MF-LF
0
1/10W
603
R7716
SM
XW7710
OMIT
L7710.2:1MM
C7725
6.3V 603
22UF
20%
CRITICAL
X5R-CERM-1
C7725.1:3MM
XW7725
SM
OMIT
CRITICAL
C7726
20%
603
6.3V
22UF
X5R-CERM-1
OMIT
SM
XW7700
U7700.21:4MM
402
16V
10%
0.22UF
CERM
C7727
R7731
1/16W
1%
49.9K
402
MF-LF
10K
1%
402
R7730
1/16W MF-LF
64
120
64
120
C7721
330UF-0.009OHM
CASE-D2-HF
POLY
2V
20%
CRITICAL
C7720
CRITICAL
20%
330UF-0.009OHM
2V POLY CASE-D2-HF
C7701
603
20%
10UF
X5R
6.3V
X5R
C7700
603
2.2UF
16V
10%
R7700
805
1/8W
MF-LF
5%
2.2
5
64
120
20K
5%
402
MF-LF
1/16W
R7740
6
1.0UH-7A
L7750
PIMB053T-SM
CRITICAL
C7758
402
CERM
50V
47PF
5%
R7758
59.0K
1/16W MF-LF 402
1%
R7759
47.0K
MF-LF
1/16W
1%
402
C7760
603
22UF
X5R-CERM-1
20%
6.3V
R7770
100K
402
5% 1/16W MF-LF
R7771
402
5% 1/16W MF-LF
100K
NOSTUFF
6.3V
20%
10UF
C7722
603
X5R
C7761
20%
6.3V X5R-CERM-1
22UF
603
6
64
120
64
120
10UF
X5R
6.3V 603
20%
C7750
6.3V X5R 603
C7751
10UF
20%
QFN
CRITICAL
U7750
ISL8014A
CSD58872Q5D
Q7710
CRITICAL
SON5X6
X5R
EMC
402
10%
1UF
25V
C7742
Q7710.1:3MM
EMC
402
X5R
10% 25V
Q7710.1:3MM
C7743
1UF
6
X5R
C7723
603
6.3V
20%
10UF
R7735
402
1K
1% MF-LF
1/16W
1UF
U7750.1:3MM
402
EMC
25V X5R
10%
C7753
U7750.1:3MM
C7752
EMC
25V 402
1UF
10% X5R
R7780
10K
1/16W
1%
402
MF-LF
0.01UF
C7731
0402
50V X7R-CERM
10%
10% 16V
0.1UF
0402
X7R-CERM
C7730
TH1
20%
CRITICAL
C7710
POLY
16V
180UF 180UF
20% POLY
TH1
C7711
CRITICAL
16V
603
R7711
1/10W
0
MF-LF
5%
1UF
402
10% X5R
25V
C7745
Q7710.1:3MM
25V 402
1UF
10% X5R
C7744
Q7710.1:5MM
1/16W MF-LF 402
44.2K
1%
R7736
SDP1182-SM
CRITICAL
L7710
1.0UH-27A-1.05MOHM
SYNC_MASTER=D8_MLB
VReg VDDQ and 1.8V S0
SYNC_DATE=08/27/2012
PPVDDQ_S3_REG
REG_PHASE_VDDQS3_L
=PP12V_S5_REG_VDDQ_S3
PP1V8_S0_REG
REG_P1V8S0_VFB
PPDDRVTT_S0_LDO
REG_SNUBBER_VDDQS3
REG_UGATE_VDDQS3_R
REG_UGATE_VDDQS3
=PP3V3_S0_VRD
REG_P1V8S0_PGOOD
=PP5V_S4_REG_VDDQ_S3
REG_VDDQS3_PGOOD
PM_EN_REG_VDDQ_S3
REG_BOOT_VDDQS3
PPDDRVTT_S3_LDO
PM_EN_LDO_DDRVTT_S0
LDO_DDRVTTS0_SNS
REG_VDDQS3_PGOOD
REG_PHASE_VDDQS3
=PPVDDQ_S3_LDO_DDRVTT
REG_BOOT_VDDQS3_RC
=PP5V_S0_VRD
REG_P1V8S0_SYNCH
PM_EN_REG_P1V8_S0
REG_P1V8S0_PGOOD
=PP3V3_S4_PWRCTL
PM_PGOOD_REG_P1V8_S0
MAKE_BASE=TRUE
PM_PGOOD_REG_VDDQ_S3 MAKE_BASE=TRUE
REG_VDDQS3_VDDQSNS
REG_VDDQS3_VREF
REG_VDDQS3_TRIP
REG_VDDQS3_MODE
REG_VDDQS3_REFIN
=PP5V_S0_REG_P1V8
AGND_VDDQS3
REG_PHASE_P1V8S0
REG_V5IN_U7700
REG_LGATE_VDDQS3
prefsb
051-9505
8.0.0
77 OF 144 72 OF 123
12
8
16
6
17
19 18
13
11 20 9 3 1
5
14
15
2
21
4
7
10
2
1
1
2
2
11
2
1 2
2
1
1 2
2
1
2
1
2
1
1
2
1
2
1
2
1
2
2
1
2
1
1
2
1
2
21
2
1 1
2
1
2
2
1
1
2
1
2
2
1
2
1
2
1
2
1
15
13
3
1
17
12
11
10
9
5
7
4
14
8
16 6
2
6
9
4
3
5
8
7
1
2
1
2
1
2
1
1
2
2
1
2
1
1
2
2
1
2
1
1
2
1
2
1
2
2
1
2
1
1
2
21
110
6
110
110
110
110
6
66 69 70 96 99
72
121
6
72
121
110
6
110
72
121
110
6
110
6
96
110
72
121
6
65 74
110
110
110
110
110
6
110
110
110
110
SW
BOOST
VIN
BIAS
SHDN*
GND
NC
FB
PAD
THRM
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
OC trip point:
Vout = 1.25V * (1 + Ra / Rb)
Vout = 3.425 250mA max output (Switcher limit)
? A (nom)/? A (min)
0.10 A (BUDGET)
0.04 A (BUDGET)
? kHz
<Ra>
<Rb>
Switching freq:
Max peak current:
3.425V "G3Hot" Regulator
Max avg current:
D8:CONTROLLER CHANGE FOR 3.42V SMC SUPPLY RDAR://11003901
D7/D7I: IMPLEMENT A CLEANER DISABLE FOR PP3V42_G3H REGULATOR RDAR://11132734
FF0%
1/10W
0603
0.00
R7865
5%
CERM
50V
C7864
0402
U7801
DFN
LT3470AED
R7861
402
MF-LF
1/16W
1%
1%
49.9K
1/16W MF-LF 402
R7862
0603
X5R-CERM1
6.3V
20%
C7865
402
MF-LF
1/16W
1%
R7863
402
1% 1/16W MF-LF
R7864
CDPH4D19FHF-SM
L7861
C7861
X5R-CERM
25V
20%
0603
NP0-C0G 402
5% 25V
C7862
NOSTUFF
1000PF
10% 16V
402
CERM
0.22UF
C7863
10%
402
25V
1UF
C7802
X5RX5R
10% 25V
C7807
402
1UF
C7806
X5R-CERM 0603
20%
25V
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
VREG 3.42V G3HOT
P3V42G3H_SHDN_L
PP12V_G3H_P3V42
=PP12V_G3H_P3V42
P3V42G3H_FB
PP3V42_G3H_REG
P3V42G3H_BOOST
P3V42G3H_SW
prefsb
051-9505
8.0.0
78 OF 144 73 OF 123
1 2
2
1
4
3
6
2
8
5
7
1
9
1
2
1
2
2
11
2
1
2
21
2
1
2
1
2
12
1
2
1
2
1
110
110
6
110
6
119
110
OUT
NC
OUT
IN
THRM
GND
PG
ON
NC
D1
D2
G
VCC
PAD
OUT
NC
IN
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
OUT
NC
IN
G
D
S
G
D
S
IN
IN
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
G
D
S
IN
OUT
NC
NC
NC
OUT
NC
THRM
GND
PG
ON
NC
D1
D2
G
VCC
PAD
IN
IN
D
S
G
D
S
G
D
S
G
ON
NC
S
VCC
D
PG
G
GND
THRM
PAD
DGS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
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D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
376S1125
RADAR://11420274 NEW MOSFET Q7950 TO AVOID 50A 100US PULSE ON 12V S0.
Max peak current:
Max avg current:
6 A (BUDGET) 6 A (BUDGET) SOFT START ON BLC
BLC12V BYPASS STUFFING OPTION
5V S0 FET
RADAR://10865139 U7970 ENSURES S5_PWRGD ISN’T ASSERTED AFTER HARD SHUTDOWN.
VDDQ (1.5V) S0 FET
Max avg current:
9.0 A (BUDGET)
20.4 A (BUDGET)
Input: 2.4V to 5.5V
Max peak current:
Max avg current:
12V S0 FET
Max peak current:
Max avg current:
2.7 A (BUDGET)
NOSTUFF
NOSTUFF
NO BYPASS
STUFF
R7986:
R7911:
STUFF
BYPASS
Input: 2.4V to 5.5V
3.3V S0 FET (4.8A PK / 3.5A AVG)
Max peak current:
12V S5 FET
Max avg current: 7.533 A (BUDGET)
3.3V S4 FET (2.7A PK / 2.0A AVG)
12V S0 BLC FET
24.1 A (BUDGET)
Max peak current:
9.733 A (BUDGET)
11.3 A (BUDGET)
3.9 A (BUDGET)
6
R7930
402
1/16W
5%
10K
MF-LF
28 64
120
64
120
SLG5AP026
CRITICAL
TDFN
U7950
R7950
5%
1/10W
603
MF-LF
100
C7950
1UF
10% X5R
603
16V
MF-LF 402
1/16W
100K
5%
R7951
6
64 74
120
DFN
CRITICAL
SLG5AP004
U7930
6
16V X5R
10%
603
1UF
C7970
100
R7970
MF-LF
5%
1/10W
603
5%
402
100K
R7971
MF-LF
1/16W
47 48
122
Q7940
PQFN
IRFH3702TRPBF
CRITICAL
IRFH3702TRPBF
Q7900
PQFN
CRITICAL
402
MF-LF
1/16W
5%
10K
R7900
64
120
64
120
SLG5AP004
U7940
CRITICAL
DFN
DFN
CRITICAL
SLG5AP004
U7900
SLG5AP004
DFN
U7920
CRITICAL
IRFH3702TRPBF
PQFN
CRITICAL
Q7920
64
120
6
6
5% MF-LF
402
1/16W
R7982
10K
R7980
603
100
MF-LF
1/10W
5%
1UF
603
X5R
10% 16V
C7980
CRITICAL
TDFN
SLG5AP026
U7980
64 74
120
78
111
1/16W
10K
402
MF-LF
5%
R7910
1/16W
402
MF-LF
R7911
10K
NOSTUFF
5%
CRITICAL
DIRECTFET_S3C
649135PBF
Q7970
Q7930
CRITICAL
DIRECTFET_S3C
649135PBF
CRITICAL
649135PBF
DIRECTFET_S3C
Q7980
R7983
200K
1% 1/16W MF-LF 402
402
5%
0
MF-LF
1/16W
R7974
MF-LF
47.0K
R7952
1% 1/16W
402
5%
R7940
22K
402
MF-LF
1/16W
R7920
402
MF-LF
1/16W
22K
5%
SLG5AP022-200030V
CRITICAL
TDFN
U7970
402
R7953
5% MF-LF
0
1/16W
402
0
5% 1/16W MF-LF
R7987
NOSTUFF
5% MF-LF
402
R7973
1/16W
0
10% 50V X7R 0402
C7973
0.022UF
Q7950
IRF6717MTR1PBF
DIRECTFET-MX
CRITICAL
C7953
0.022UF
0805
X7R-CERM
50V
10%
402
NOSTUFF
R7989
MF-LF
1/16W
5%
0
C7900
0402
0.1UF
10% 16V X7R-CERM
C7940
0402
0.1UF
16V
10% X7R-CERM
C7921
0402
0.1UF
10% 16V X7R-CERM
0402
16V X7R-CERM
10%
0.1UF
C7930
SYNC_DATE=08/27/2012
FET-Controlled S0 and S4
SYNC_MASTER=D8_MLB
=PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
PP1V5_S0_FET
PP3V3_S0_FET
PM_EN_FET_P12V_S0_R
=PP5V_S4_FET_P5V_S0
PM_PGOOD_FET_P12V_S0_BLC
PGOOD_P12V_S0
PP3V3_S4_FET
FET_EN_P12V_S0_R
PGOOD_P12V_S0
PP12V_S5_FET
FET_EN_P12V_S0
VIDEO_ON
=PP12V_G3H_FET_P12V_S0
PM_EN_REG_P3V3_S5
PM_PGOOD_P3V3_S4_FET
PM_PGOOD_FET_P3V3_S0
PM_EN_FET_VDDQ_S0
=PP3V3_S4_PWRCTL
PM_EN_FET_P3V3_S4
PM_PGOOD_FET_P5V_S0
=PP3V3_S4_PWRCTL
P3V3_S3_EN_G
=PPVDDQ_S3_FET_VDDQ_S0
FET_VCC_U7980
FET_EN_P12V_S0_BLC_R
PM_EN_FET_P12V_S0
P3V3_S0_EN_G
=PP3V3_S0_PWRCTL
PM_EN_FET_P12V_S0
PM_EN_FET_P5V_S0
PP5V_S0_FET
P5V_S0_EN_G
=PP3V3_S0_PWRCTL
FET_EN_VDDQ_S0
PM_PGOOD_FET_VDDQ_S0
SMC_PM_G2_EN
=PP3V3_S0_PWRCTL
FET_EN_P12V_S5
FET_VCC_U7970
FET_EN_P12V_S5_R
PM_PGOOD_FET_P12V_S5
FET_VCC_U7950
=PP3V3_S5_FET_P3V3_S4
PP12V_S0_BLC_FET
FET_EN_P12V_S0_BLC
=PP12V_G3H_FET_P12V_S5
=PP12V_G3H_FET_P12V_S0
=PP3V3_S5_FET_P3V3_S0
PM_EN_FET_P3V3_S0
=PP3V3_S4_PWRCTL
PP12V_S0_FET
PM_PGOOD_FET_P12V_S0
prefsb
051-9505
8.0.0
79 OF 144 74 OF 123
1
2
9
4
8
2
3
5
6
7
1
1 2
2
1
1
2
7
8
9
4
3
5
1
6
2
2
1
1 2
1
2
5
1
4
5
1
4
1
2
7
8
9
4
3
5
1
6
2
7
8
9
4
3
5
1
6
2
7
8
9
4
3
5
1
6
2
5
1
4
1
2
1 2
2
1
9
4
8
2
3
5
6
7
1
1 2
1 2
1
2
8
3
5
6
7
4
1
2
8
3
5
6
7
4
1
2
8
3
5
6
7
4
1
2
1 2
1
2
1
2
1
2
2
3
6
1
5
8
7
4
9
1
2
1 2
1
2
2
1
5
3 4
71 2 6
2
1
1 2
2
1
2
1
2
1
2
1
6
64 65 74
6
64 65 74
6
64 65 74
6
64 65 74
6
120
6
82
120
64 65 74
120
6
118
64 65 74
120
118
6
74
64 71
120
27 35 64
120
64
120
6
65 72 74
64
120
6
65 72 74
119
6
118
118
119
6
28 74
119
6
28 74
118
6
28 74
118
118
118
120
118
6
118
6
6
74
6
6
65 72 74
120
S
GND
OUTPUT
MUX
SELECTOR
I1
I0
Y
VCC
IN IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN IN
IN IN
IN IN
IN IN
OUT OUT
OUT OUT
OUT OUT
OUT OUT
NC NC
BI
BI
BI
IN IN
IN IN
IN IN
IN IN
NC NC
BI
BI
OUT
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
DIN1_1-
DIN1_1+
VDD
VDD
GND
GND
GND
GND
DIN1_0-
DIN1_3-
DOUT_0+
DOUT_1-
DAUX1-
DIN2_0+ DIN2_0-
DAUX2+
DIN2_3-
DIN2_3+
DIN2_2-
DIN2_2+
HPDIN
AUX+
DIN2_1-
DDC_AUX_SEL
DIN2_1+
DOUT_3-
DOUT_3+
DOUT_2-
DOUT_2+
DDC_DAT1
DDC_CLK1
DOUT_1+
DIN1_2+
GPU_SEL
HPD_2
DDC_CLK2
DAUX2-
DDC_DAT2
DIN1_3+
DAUX1+
DIN1_2-
HPD_1
XSD*
DIN1_0+
GND
GND
AUX-
DOUT_0-
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PD is on the LR page
TP to DP aliases
74LVC1G157
SOT487
BKLT_PWM
U9220
48
111
91
111
21 62 75
103
MF-LF
47
402
5%
1/16W
R9222
BKLT_PWM
0402
FERR-220-OHM
BKLT_PWM
L9201
80
111
R9266
1/20W
MF
201
5%
470K
R9267
201
MF
1/20W
5%
470K
R9265
201
MF
1/20W
5%
470K
R9264
201
MF
1/20W
5%
470K
R9263
201
MF
1/20W
5%
470K
201
MF
470K
5%
1/20W
R9262
R9261
MF
201
1/20W
5%
470K
1/20W
5%
MF
201
470K
R9260
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
R9290
MF-LF
1/16W
0
402
5%
C9290
X5R
10%
1UF
402
16V
201
C9268
10%
0.1UF
X5R
6.3V X5R
0.1UF
201
6.3V
10%
C9269
90
117
90
111
90
111
90
111
90
111
90
111
90
111
90
111
90
111
78
111
78
111
78
111
78
111
78
111
78
111
78
111
78
111
C9208
6.3V
10%
X5R
0.1UF
201
C9209
201
0.1UF
6.3V
10%
X5R
78
111
90
111
90
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
C9211
X5R
10%
6.3V
0.1UF
201
X5R
10%
6.3V
0.1UF
201
C9210
75
111
75
111
R9200
201
5% 1/20W MF
36
111
R9201
5%
10K
1/20W MF 201
21 62 75
103
78
111
78
117
MF
5%
201
1/20W
R9202
5% 1/20W MF 201
R9203
201
10K
5%
1/20W
MF
R9204
36
36
36
36
36
36
36
36
36
36
201
5% 1/20W MF
R9211
201
MF
1/20W
5%
R9210
201
5% 1/20W MF
R9213
201
MF
5%
R9212
1/20W
0.15UF
10%
6.3V
C9200
0201 X5R
10%
X5R
6.3V
C9201
0201
0.15UF
10%
X5R
6.3V
C9202
0201
0.15UF
0.15UF
10%
X5R
6.3V
C9203
0201
0.15UF
10%
6.3V
C9204
X5R
0201
0.15UF
X5R
6.3V
C9205
0201
10%
10%
X5R
6.3V
C9206
0201
0.15UF
X5R
0201
0.15UF
10%
6.3V
C9207
C9250
0.22UF
20%
6.3V
X5R
0201
0201
C9251
X5R
6.3V
20%
0.22UF
0.22UF
20%
6.3V
X5R
C9252
0201
0.22UF
20%
6.3V
X5R
C9253
0201
0201
C9254
X5R
6.3V
20%
0.22UF
0.22UF
20%
6.3V
X5R
C9255
0201
0201
C9256
X5R
6.3V
20%
0.22UF
0201
C9257
X5R
6.3V
20%
0.22UF
U9200
CBTL06142EEE
CRITICAL
TFBGA
10% 16V
0402
X7R-CERM
C9291
0.1UF
X5R
10% 16V
0.1uF
BKLT_PWM
C9270
402
SYNC_MASTER=D8_MLB
Internal DP MUXing
SYNC_DATE=08/27/2012
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.5V
PP1V5_S0_DP_BIAS
=PP1V5_S0_DP
DP_TBTSRC_ML_C_P<0>
DP_TBTSRC_ML_C_N<1>
DP_TBTSRC_ML_C_N<3>
DP_INTPNL_AUX_N
DP_INTPNL_AUX_P
DP_TBTSRC_ML_C_N<0>
DP_TBTSRC_ML_C_P<1>
DP_TBTSRC_ML_C_P<2>
TP_DP_TBTSRC_ML_CN<2>
DP_INT_EG_AUX_C_P
DP_TBTSRC_ML_C_P<0>
DP_TBTSRC_ML_C_N<1>
DP_INTPNL_HPD
DP_INTPNL_ML_C_N<1>
DP_INT_EG_ML_N<1>
DP_INT_EG_ML_P<1>
=PP3V3_S0_INTDPMUX
DP_INT_EG_ML_N<0>
DP_INT_EG_ML_N<3>
DP_INTPNL_ML_C_P<0>
DP_INT_EG_AUX_C_N
DP_TBTSRC_ML_C_N<0>
DP_TBTSRC_AUX_C_P
DP_TBTSRC_ML_C_N<3>
DP_TBTSRC_ML_C_P<3>
DP_TBTSRC_ML_C_N<2>
DP_TBTSRC_ML_C_P<2>
DP_TBTSRC_ML_C_P<1>
DP_INTPNL_ML_C_N<3>
DP_INTPNL_ML_C_P<3>
DP_INTPNL_ML_C_N<2>
DP_INTPNL_ML_C_P<2>
DP_INTPNL_ML_C_P<1>
DP_INT_EG_ML_P<2>
DP_TBT_SEL
DP_TBTSRC_HPD
DP_INT_EG_ML_P<3>
DP_INT_EG_ML_N<2>
DP_INT_EG_HPD
DP_INT_EG_ML_P<0>
DP_INTPNL_ML_C_N<0>
GPU_LCD_BKLT_PWM
=PP3V3_S0_INTDPMUX
TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_ML_CP<2>
TP_DP_TBTSRC_ML_CP<1>
TP_DP_TBTSRC_ML_CN<0>
TP_DP_TBTSRC_ML_CP<0>
LCD_BL_FILT
LCD_BKLT_PWM
LCD_BL_PWM
DP_TBT_SEL
BDV_BKL_PWM
TP_DP_TBTSRC_ML_CN<1>
TP_DP_TBTSRC_ML_CP<3>
DP_INT_EG_AUX_N
DP_INT_EG_AUX_P
DP_TBTSRC_AUXCH_P
DP_TBTSRC_AUXCH_N
=PP1V5_S0_DP
=PP1V5_S0_DP
TP_DP_TBTSRC_AUXCH_CN
TP_DP_TBTSRC_ML_CN<3>
DP_INTPNL_ML_P<1> DP_INTPNL_ML_N<1>
DP_INTPNL_ML_P<2> DP_INTPNL_ML_N<2>
DP_INTPNL_ML_P<3> DP_INTPNL_ML_N<3>
DP_INTPNL_ML_N<0>
DP_TBTSRC_ML_P<0>
DP_TBTSRC_ML_P<1>
DP_TBTSRC_ML_N<1>
DP_TBTSRC_ML_N<0>
DP_TBTSRC_ML_N<2>
DP_TBTSRC_ML_C_N<2>
DP_TBTSRC_ML_P<3>
DP_TBTSRC_ML_C_P<3>
DP_TBTSRC_ML_N<3>
DP_TBTSRC_ML_P<2>
DP_INTPNL_ML_P<0>
=PP3V3_S0_INTDPMUX
MAKE_BASE=TRUE
DP_TBTSRC_AUXCH_N
MAKE_BASE=TRUE
DP_TBTSRC_ML_P<3>
DP_TBTSRC_ML_N<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_TBTSRC_ML_P<1>
MAKE_BASE=TRUE
DP_TBTSRC_ML_N<1>
DP_TBTSRC_ML_N<2>
MAKE_BASE=TRUE
DP_TBTSRC_AUXCH_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_TBTSRC_ML_N<3>
MAKE_BASE=TRUE
DP_TBTSRC_ML_P<0>
MAKE_BASE=TRUE
DP_TBTSRC_ML_P<2>
=PP3V3_S0_INTDPMUX
DP_TBTSRC_AUX_C_N
DP_GPU_MUX_EN
prefsb
051-9505
8.0.0
92 OF 144 75 OF 123
1 3
4
6
2 5
12
21
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
12
2
1
2
1
2
1
1 2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
1
2
121
2
121
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
A5
B5
J4
A2
H4G8C8
B3
A4
A9
B2
D1
J9
B8 B9
H6
F9
F8
E9
E8
J1
H2
D9
C2
D8
F1
F2
E1
E2
J8
H8
D2
B6
A1
H3
H5
J6
J5
A8
H9
A6
J2
B7
B4
H7
G2
H1
B1
2
1
2
1
6
75
75
111
75
111
75
111
75
111
75
111
75
111
111
111
6
75
111
111
111
111
111
111
111
111
111
6
75
111
6
75
6
75
75
111
75
111
6
75
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
6
75
111
117
IN
OUT
IN
BI
BI
IN
BI
VCC
OUTA1+ OUTA1-
OUTA0+ OUTA0-
SAO
OUTB1+ OUTB1-
OUTB0-
OUTB0+
SBO
ENA
INA-
INA+
ENB
SAI
INB-
INB+
SBI
GND
THRM
PAD
OUT BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Dual-Port Host DDC Crossbar
92
111
79
117
36
122
79
117
92
111
91
111
91
111
C9300
20%
CERM
10V
0.1UF
402
U9300
TS3DS10224
QFN
CRITICAL
77
117
77
117
TBT DDC Crossbar
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
=PP3V3_S0_DP
DP_TBTPA_DDC_DATA
DP_TBTPB_DDC_DATA
DP_TBTPB_DDC_CLK
DP_TBTPA_DDC_CLK
DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA
DP_TBTSNK0_DDC_DATA
DP_TBTSNK0_DDC_CLK
TBT_DDC_XBAR_EN_L
prefsb
051-9505
8.0.0
93 OF 144 76 OF 123
2
1
13
20 19
18 17
15
6 7
9
8
11
16
2
1
10
14
4
3
12
5
21
6
78
IN IN
OUT
IN IN
ISET_S3
V3P3OUT
ISET_S0
EN
S0
HV_EN
RSVD
GND
THRM
OUT
VHV
ISET_V3P3
RSVD
V3P3
PAD
IN
IN
IN
DPMLO+ DPMLO-
VDD
DP-
DP+
DDC_CLK
AUX+
AUX-
AUXIO_EN
AUXIO­AUXIO+
THMPAD
GND
BIASIN
BIASOUT
DDC_DAT
CA_DETOUT
CA_DET
DP_PD
LSTX LSRX
HPDOUT
HPD
OUT
BI
IN
IN
IN
IN
IN
OUT
OUT OUT
OUT
OUT
IN IN
BI BI
IN IN
OUT
ML_LANE1N
CONFIG1
SHLD
GND4
DP_PWR
CONFIG2
AUX_CHN
HPD
AUX_CHP
GND2
ML_LANE3N
GND1
ML_LANE3P
ML_LANE0N
ML_LANE1P
GND3
GND0
ML_LANE0P
SHLD
RETURN
ML_LANE2N
ML_LANE2P
PORT A
NC
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Two Rs in series required by CD3210
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
IV3P3 1100mA 1030mA 1200mA
Nominal Min Max
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
(0-18.9V)
NOTE: Polarity Swapped for layout!
For 12V systems:
for single-fault protection(S0,S3 only)
(Both D’s)
TBT: Terminated
18.9V Max
470k R’s for ESD protection on AC-coupled signals.
(0-18.9V)
TBT: TX_1
TBT: RX_1 Bias Sink
Low: 0 - 0.8V
High: 2.0 - 5.0V
to 100K (DPv1.1a).
Sink HPD range:
greater than or equal
DP Source must pull
(Both C’s)
DP Dir
TBT: LSX_R2P/P2R (P/N)
TBT: LSX_A_R2P/P2R (P/N)
(Both C’s)
DP Dir
down HPD input with
3.3V/HV Power MUX
wake from Thunderbolt devices.
V3P3 must be S4 to support
12V: See below
TBT: TX_0
TBT Dir
(Both C’s)
NOTE: Polarity Swapped for layout!
(Both C’s)
Nominal Min Max IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
NOTE: Polarity Swapped for layout!
TBT Dir
Thunderbolt Connector A
514-0831
36
111
36
111
C9402
10%
0.01UF
0201
25V
12
R9401
MF
1/20W
201
5%
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
5%
1K
MF
201
1/20W
R9494 R9495
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
1K
5%
MF
1/20W
201
R9441
5%
100K
MF
1/20W
201
0603
GND_VOID=TRUE
650NH-5%-0.430MA-0.52OHM
CRITICAL
SIGNAL_MODEL=EMPTY
L9498
L9499
650NH-5%-0.430MA-0.52OHM
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
0603
CRITICAL
C9481
402
CERM
20%
0.1UF
10V
C9480
CRITICAL
603
6.3V
X5R-CERM-1
20%
22UF
C9487
CASE-B2-SM
20%
6.3V
CRITICAL
POLY-TANT
100UF
R9452
1M
5% MF
1/20W
201
R9451
5%
1M
MF
1/20W
201
GND_VOID=TRUE
R9498
2.2K
5%
MF
1/20W
201
GND_VOID=TRUE
R9499
2.2K
5%
MF
1/20W
201
L9400
0603
FERR-120-OHM-3A
36
111
C9410
0.1UF
X7R
50V
10%
603-1
D9499
CRITICAL
BAR90-02LRH
GND_VOID=TRUE
BAR90-02LRH
D9498
CRITICAL
GND_VOID=TRUE
R9470
1/20W
470K
MF 201
GND_VOID=TRUE
5%
R9471
201
1/20W MF
GND_VOID=TRUE
470K
5%
GND_VOID=TRUE
C9471
0201
X5R
6.3V
20%
0.22UF
C9470
0201
GND_VOID=TRUE
6.3V
0.22UF
20% X5R
36
111
36
111
GND_VOID=TRUE
C9472
0201
0.22UF
20% X5R
6.3V
C9473
0201
20% X5R
6.3V
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
R9473
201
1/20W MF
5%
470K
R9472
470K
GND_VOID=TRUE
201
1/20W MF
5%
C9405
25V
X5R-CERM
10%
0201
0.01UF
C9406
0.01UF
X5R-CERM
10%
0201
25V
U9410
QFN
CRITICAL
CD3210A0RGP
36
122
48
64 79
R9410
402
1%
22.6K
MF-LF
1/16W
TBTHV:P15V
R9411
22.6K
MF-LF
TBTHV:P15V
1/16W
402
1%
MF-LF
R9412
36.5K
402
1% 1/16W
0.1UF
50V
603-1
10%
X7R
C9411
U9420
CRITICAL
CBTL05023
HVQFN
R9429
5%
100K
MF
1/20W
201
R9428
5%
100K
MF
1/20W
201
C9420
0.1UF
10%
6.3V X5R 201
C9421
0.1UF
10%
6.3V X5R 201
36
117
76
117
76
117
15 79
117
36
36
36
111
R9426
1/20W
MF
1M
5%
201
R9427
201
1/20W MF
5%
10K
C9425
10%
0.1UF
6.3V X5R 201
36
111
36
111
36
111
36
111
36
111
C9432
6.3V
X5R
0201
20%
0.22UF
C9433
0201
X5R
20%
6.3V
0.22UF
36
111
36
111
C9430
10%
0.1UF
6.3V
X5R 201
C9431
0.1UF
10%
6.3V
X5R 201
36
111
36
111
C9478
0201
X5R
6.3V
0.22UF
20%
C9479
0201
0.22UF
6.3V
20% X5R
36
111
36
111
R9479
201
470K
5%MF1/20W
R9478
470K
5%MF1/20W
201
C9415
0603
25V
4.7UF
10%
R9413
TBTHV:P15V
1%
402
MF-LF
1/16W
22.6K
R9414
TBTHV:P15V
22.6K
MF-LF 402
1/16W
1%
CRITICAL
SOT891
U9460
74AUP1T97
36
111
C9460
16V X5R-CERM 0201
10%
0.1UF
65
F-ANG-TH
DUAL-MDP-D8
CRITICAL
J9400
GND_VOID=TRUE
201
4V
20%
CERM-X5R-1
0.47UF
C9474
GND_VOID=TRUE
201
CERM-X5R-1
4V
20%
0.47UF
C9475
GND_VOID=TRUE
0.47UF
20%
4V
CERM-X5R-1
201
C9476
GND_VOID=TRUE
0.47UF
20% 201
C9477
CERM-X5R-1
4V
50V
0402
30PF
5%
C9498
C0G-NP0
0402
C0G-NP0
50V
5%
30PF
C9499
0201
X7R-CERM
C9494
330PF
10% 16V
C9495
330PF
10% 16V X7R-CERM 0201
0402
C9400
0.01UF
10% 50V X7R-CERM
X7R-CERM 0402
0.01UF
50V
10%
C9401
SYNC_MASTER=D8_MLB
Thunderbolt Connector A
SYNC_DATE=08/27/2012
R9410,R9413
TBTHV:P12V
2
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
114S0338
2
R9411,R9414
114S0338
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
TBTHV:P12V
DP_TBTPA_ML_P<3>
TBT_A_R2D_P<1> TBT_A_R2D_N<1>
MIN_LINE_WIDTH=0.38 MM VOLTAGE=12V
MIN_NECK_WIDTH=0.20 MM
PP3V3RHV_SW_TBTAPWR
TBT_A_LSRX_UNBUF
DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>
TBT_A_D2R_N<0> TBT_A_D2R_P<0>
TBT_A_D2R_C_P<1>
TBT_A_D2R_N<1> TBT_A_D2R_P<1>
TBT_A_BIAS
TBT_A_D2R_C_N<0>
DP_A_LSX_ML_N<1>
TBT_A_D2R1_AUXDDC_N
TBT_A_D2R1_AUXDDC_P
TBT_A_R2D_N<0>
DP_A_LSX_ML_P<1>
TBT_A_R2D_P<0>
DP_TBTPA_ML_N<1>
=PP3V3_S4_TBT
TBT_A_CIO_SEL
DP_A_AUXCH_DDC_N
DP_TBTPA_ML_C_P<1>
TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>
TBT_A_CONFIG1_BUF
DP_TBTPA_DDC_DATA
DP_A_LSX_ML_N<1>
DP_A_LSX_ML_P<1>
DP_TBTPA_ML_P<1>
TBT_A_R2D_C_P<1>
TBT_A_R2D_C_N<1>
TBT_A_HPD
DP_TBTPA_DDC_CLK
TBT_A_CONFIG1_RC
DP_A_AUXCH_DDC_P
DP_AUXIO_EN
TBT_A_LSTX
=PPHV_SW_TBTAPWRSW
TBTAPWRSW_ISET_S0_R
TBT_A_DP_PWRDN
DP_TBTPA_HPD
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_N DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_C_P
=TBTAPWRSW_EN
=PP3V3_S4_TBTAPWRSW
TBT_A_HV_EN
=TBT_S0_EN
TBTAPWRSW_ISET_S3_R
TBTAPWRSW_ISET_S0
TBTAPWRSW_ISET_S3
TBTAPWRSW_ISET_V3P3
TBT_A_LSRX
DP_TBTPA_ML_C_N<1>
=PP3V3_S4_TBT
TBT_A_D2R_C_P<0>
TBT_A_HPD
DP_A_AUXCH_DDC_N
DP_A_AUXCH_DDC_P
TBT_A_D2R_C_N<1>
TBT_A_CONFIG2_RC
TBT_A_CONFIG1_RC
DP_TBTPA_ML_N<3>
TBT_A_BIAS
VOLTAGE=3.3V
TBTACONN_1_C
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V
MIN_LINE_WIDTH=0.38 MM
TBTACONN_7_C
VOLTAGE=18.9V
MIN_NECK_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
PPHV_SW_TBTAPWR
VOLTAGE=12V
MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V
MIN_LINE_WIDTH=0.38 MM
TBTACONN_20_RC
prefsb
051-9505
8.0.0
94 OF 144 77 OF 123
2
1
1 2
121
2
1
2
2 1
2 1
2
1
2
11
2
121
2
121
2
21
2
1
A K
A K
1
2
1
2
1 2
1 2
1 2
1 2
1
2
1
2
1 2
1 2
9
18
10
5
17
11
16
123
4
13
21
12
14
7
6
8
15
20
19
121
2
1
2
2
1
19
20
15
3
10
11
5
8
7
2
23
22
25
21
9
1
24
4
16 18
6
14
13
12 17
1
2
1
2
2
1
2
1
1
2
1
2
2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
121
2
6
3
4
2
1
5
2
1
11
4
515049
47
464544
43
14
20
6
18
2
16
8
12
42
7
10
5
9
13
1 3
48
41
52
19
17
15
1 2
1 2
1 2
1 2
212
1
212
1
2
1
2
1
111
111
111
121
111
77
122
111
77
111
111
111
111
77
111
111
111
6
36 37 38 77 79
77
111
77
111
77
111
111
77
77
122
77
111
6
111
111
6
48
6
36 37 38 77 79
111
77
77
111
77
111
111
77
122
111
77
122
121
OUT
IN
NC
OUT
BI
IN BI
OUT OUT
BI BI
IN IN
IN IN
IN IN
IN IN
OUT OUT
OUT
OUT
OUT
NC
NC
GND
Y1 Y2
A
NC
VCC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
On a H->L transition of A, Y2 follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video Y1 is simply an inverted version of A, with no delay
The delay applies only on a L->H transition on A. This guarantees video is valid before the backlight is enabled.
Backlight Control
ipd
U9500 OUTPUT Y2 IS A NON-INVERTED, DELAYED VERSION OF INPUT A
K6X BACKLIGHT CONTROL SUPPORT
guarantee backlight is only on when Panel has valid video
TO DIAGS LED
used by diag LED
155S0367
Display TCon Master
To BLC
518S0852
Display TCon Slave
INTERNAL DP (STRAIGHT)
518S0778
402
NOSTUFF
20% 10V CERM
0.1UF
C9506
78 80 81
117
74 78
111
NOSTUFF
R9501
5%
0
402
1/16W MF-LF
C9520
10UF
10% 16V
0805
X5R-CERM
50
118
50
118
50
50
56
111
75
117
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
74 78
111
80
117
20525-140E-01
CRITICAL
J9500
F-RT-SM
M-RT-SM
DEVELOPMENT
J9520
53780-8606
CRITICAL
DEVELOPMENT
C9530
X5R-CERM
10UF
16V
10%
0805
DEVELOPMENT
SM
FERR-250-OHM
L9520
R9502
1/16W
402
MF-LF
5%
0
NOSTUFF
CERM
C9501
0402
50V
20%
0.001UF
DEVELOPMENT
C9531
0402
CERM
50V
20%
0.001UF
0603
L9500
FERR-120-OHM-3A
78 80 81
117
47
5%
1/16W
402
MF-LF
R9504
U9502
5
SOT886
74AUP2G14GM
2
SOT23
D9501
BAT54XG
20% 10V
0.1UF
CERM 402
C9502
U9501
SOT886
74AUP2G14GM
2
5
402
NOSTUFF
R9506
1/16W MF-LF
5%
0
5
78
111
R9505
1/16W
402
MF-LF
5%
0
5
78
111
CERM 402
10V
20%
0.1UF
C9504
C9503
10UF
X5R-CERM 0805
16V
10%
MF-LF
R9503
1%
1/16W
402
20.0K
U9501
74AUP2G14GM
5
2
SOT886
SOT886
2
5
U9502
74AUP2G14GM
NOSTUFF
CRITICAL
SC70
SN1105002
U9500
SYNC_MASTER=D8_MLB
Internal DP Support
SYNC_DATE=08/27/2012
VIDEO_ON
VIDEO_ON_L
BLC_EN
LCD_BKL_ON_DLY
DP_INTPNL_ML_N<2>
VIDEO_ON
I2C_TCON_MAS_SCL
=PP12V_S0_LCD PP12V_LCD_EXT
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V
DP_INTPNL_ML_N<3>
DP_INTPNL_AUX_N
=I2C_TCON_SLA_SDA
DP_INTPNL_HPD
I2C_TCON_MAS_SDA
BLC_VSYNC
DP_INTPNL_AUX_P
DP_INT_SPDIF_AUDIO
=I2C_TCON_SLA_SCL
=PP12V_S0_LCD
PP12V_LCD
VOLTAGE=12V MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.4 mm
DP_INTPNL_ML_P<3>
DP_INTPNL_ML_P<2>
DP_INTPNL_ML_N<1>
DP_INTPNL_ML_P<1>
DP_INTPNL_ML_N<0>
DP_INTPNL_ML_P<0>
VIDEO_ON_L
=PP3V3_S0_DP
VIDEO_ON_L_DLY
=PP3V3_S0_DP
=PP3V3_S0_DP
VIDEO_ON_K6X_L
BLC_EN
=PP3V3_S0_DP
BLC_EN_DELAY
VIDEO_ON
VIDEO_ON_D8_L
prefsb
051-9505
8.0.0
95 OF 144 78 OF 123
2
1
1 2
2
1
42
51
50
49
48
52
47
46
45
44
43
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
21 22 23
25
24
16
18
17
19 20
15
11 12 13 14
8 9
10
7
6
1 2
5
3 4
41
1 2
4
3
5 6
8
7
2
1
21
1 2
2
1
2
1
21
1 2
3 4
1 3
2
1
1 6
1 2
1 2
2
1
2
1
1 2
3 4
1 6
2
5 4
3
6
1
74 78
111
6
78
120
6
78
120
6
76 78
6
76 78
6
76 78
6
76 78
117
IN IN
OUT
IN IN
ISET_S3
V3P3OUT
ISET_S0
EN
S0
HV_EN
RSVD
GND
THRM
OUT
VHV
ISET_V3P3
RSVD
V3P3
PAD
IN
IN
IN
DPMLO+ DPMLO-
VDD
DP-
DP+
DDC_CLK
AUX+
AUX-
AUXIO_EN
AUXIO­AUXIO+
THMPAD
GND
BIASIN
BIASOUT
DDC_DAT
CA_DETOUT
CA_DET
DP_PD
LSTX LSRX
HPDOUT
HPD
OUT
BI
IN
IN
IN
IN
IN
OUT
OUT OUT
OUT
OUT
IN IN
BI BI
IN IN
OUT
GND1
ML_LANE0N
ML_LANE1P
AUX_CHN
AUX_CHP
CONFIG1 CONFIG2
DP_PWR
GND2
HPD
ML_LANE3N
ML_LANE3P
SHLD
SHLD
GND4
ML_LANE0P
GND0
RETURN
ML_LANE2N
ML_LANE2P
GND3
ML_LANE1N
PORT B
NC
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(Both C’s)
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
Nominal Min Max
NOTE: Polarity Swapped for Layout!
NOTE: Polarity Swapped for Layout!
(Both C’s)
3.3V/HV Power MUX
TBT Dir
TBT: LSX_R2P/P2R (P/N)
Two Rs in series required by CD3210
High: 2.0 - 5.0V Low: 0 - 0.8V
470k R’s for ESD protection on AC-coupled signals.
(Both C’s)
TBT: RX_1 Bias Sink
(0-18.9V)
(0-18.9V)
TBT Dir
(Both C’s)
TBT: LSX_A_R2P/P2R (P/N)
TBT: TX_1
DP Dir
greater than or equal
Sink HPD range:
to 100K (DPv1.1a).
(Both D’s)
TBT: Terminated
TBT: TX_0
DP Dir
DP Source must pull down HPD input with
IV3P3 1100mA 1030mA 1200mA
V3P3 must be S4 to support wake from Thunderbolt devices.
below
18.9V Max
12V: See
for single-fault protection(S0,S3 only)
Nominal Min Max
Thunderbolt Connector B
For 12V systems:
NOTE: Polarity Swapped for Layout!
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
514-0831
36
111
36
111
25V
0.01UF
10%
0201
C9602
R9601
12
5%
MF
201
1/20W
5%
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
1/20W
201
R9694
1K
MF
5%
1K
GND_VOID=TRUE
MF
1/20W
201
R9695
SIGNAL_MODEL=EMPTY
201
1/20W MF
5%
100K
R9641
0603
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
CRITICAL
650NH-5%-0.430MA-0.52OHM
L9698
CRITICAL
SIGNAL_MODEL=EMPTY
650NH-5%-0.430MA-0.52OHM
0603
GND_VOID=TRUE
L9699
20% 10V CERM 402
0.1UF
C9681
CRITICAL
20%
603
22UF
X5R-CERM-1
6.3V
C9680
CRITICAL
6.3V
20%
POLY-TANT
CASE-B2-SM
100UF
C9687
5%
1M
MF
1/20W
201
R9652
1M
5% MF
1/20W
201
R9651
GND_VOID=TRUE
5%
2.2K
MF
1/20W
201
R9698
GND_VOID=TRUE
5%
2.2K
MF
1/20W
201
R9699
FERR-120-OHM-3A
0603
L9600
36
111
10% 50V X7R 603-1
0.1UF
C9610
GND_VOID=TRUE
CRITICAL
BAR90-02LRH
D9699
GND_VOID=TRUE
CRITICAL
BAR90-02LRH
D9698
201
1/20W MF
470K
5%
GND_VOID=TRUE
R9670
GND_VOID=TRUE
201
1/20W MF
5%
470K
R9671
0201
GND_VOID=TRUE
X5R
6.3V
20%
0.22UF
C9671
0.22UF
0201
GND_VOID=TRUE
6.3V
20% X5R
C9670
36
111
36
111
0201
0.22UF
20% X5R
6.3V
GND_VOID=TRUE
C9672
0201
0.22UF
20% X5R
6.3V
GND_VOID=TRUE
C9673
1/20W
201
MF
470K
5%
GND_VOID=TRUE
R9673
GND_VOID=TRUE
201
1/20W MF
5%
470K
R9672
25V
10%
X5R-CERM
0.01UF
0201
C9605
25V
10%
X5R-CERM
0.01UF
0201
C9606
QFN
CRITICAL
CD3210A0RGP
U9610
36
122
48
64 77
22.6K
TBTHV:P15V
1/16W MF-LF
402
1%
R9610
22.6K
1%
MF-LF 402
1/16W
TBTHV:P15V
R9611
1%
36.5K
1/16W
R9612
402
MF-LF
603-1
50V
0.1UF
X7R
10%
C9611
HVQFN
CBTL05023
CRITICAL
U9620
100K
5% MF
1/20W
201
R9629
100K
5%
MF
1/20W
201
R9628
6.3V
0.1UF
X5R 201
10%
C9620
0.1UF
6.3V X5R 201
10%
C9621
36
117
76
117
76
117
15 77
117
36
36
36
111
5%
1M
MF
1/20W
201
R9626
5%
10K
MF
1/20W 201
R9627
0.1UF
6.3V X5R 201
10%
C9625
36
111
36
111
36
111
36
111
36
111
C9632
0201
0.22UF
6.3V
20% X5R
0201
0.22UF
6.3V
20% X5R
C9633
36
111
36
111
0.1UF
6.3V
X5R 201
10%
C9630
0.1UF
6.3V
X5R 201
10%
C9631
36
111
36
111
C9678
0201
X5R
20%
6.3V
0.22UF
0201
0.22UF
20%
6.3V
X5R
C9679
36
111
36
111
5%
470K
MF
1/20W
201
R9679
5%
470K
MF
1/20W
201
R9678
22.6K
1%
402
MF-LF
1/16W
TBTHV:P15V
R9613
22.6K
1/16W 402
MF-LF
1%
TBTHV:P15V
R9614
10% 25V
4.7UF
0603
C9615
CRITICAL
SOT891
74AUP1T97
U9660
16V X5R-CERM 0201
10%
0.1UF
C9660
36
111
65
F-ANG-TH
J9400
CRITICAL
DUAL-MDP-D8
GND_VOID=TRUE
0.47UF
20%
4V
CERM-X5R-1
201
C9676
GND_VOID=TRUE
201
CERM-X5R-1
4V
20%
0.47UF
C9677
GND_VOID=TRUE
0.47UF
20%
4V
CERM-X5R-1
201
C9674
GND_VOID=TRUE
0.47UF
20%
4V
CERM-X5R-1
201
C9675
C9698
C0G-NP0
5%
30PF
0402
50V
0402
C0G-NP0
50V
5%
30PF
C9699
C9695
330PF
10% 16V X7R-CERM 0201
C9694
0201
X7R-CERM
330PF
10% 16V
0402
X7R-CERM
C9600
50V
10%
0.01UF
0402
0.01UF
C9601
10% 50V X7R-CERM
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
Thunderbolt Connector B
TBTHV:P12V
2
R9611,R9614
114S0338
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
TBTHV:P12V
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
114S0338
2
R9610,R9613
TBT_B_R2D_P<0> TBT_B_R2D_N<0>
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V
TBTBCONN_7_C
PP3V3RHV_SW_TBTBPWR
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=12V
TBT_B_D2R_C_N<0>
TBT_B_HPD
TBT_B_D2R_C_P<0>
DP_B_LSX_ML_N<1>
MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V
MIN_LINE_WIDTH=0.38 MM
TBTBCONN_1_C
TBT_B_D2R1_AUXDDC_P
DP_TBTPB_ML_N<3>
DP_TBTPB_ML_P<3>
DP_TBTPB_ML_C_P<3>
TBT_B_R2D_N<1>
TBT_B_R2D_P<1>
VOLTAGE=3.3V
TBT_B_BIAS
MIN_LINE_WIDTH=0.38 MM
VOLTAGE=18V
TBTBCONN_20_RC
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=12V
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
PPHV_SW_TBTBPWR
DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N
TBT_B_D2R_C_P<1>
DP_TBTPB_ML_C_N<1>
TBT_B_LSRX_UNBUF
DP_TBTPB_ML_C_P<1>
TBTBPWRSW_ISET_V3P3
=PP3V3_S4_TBT
DP_TBTPB_AUXCH_P
DP_TBTPB_ML_N<1>
DP_AUXIO_EN
TBT_B_LSRX
=PP3V3_S4_TBT
TBTBPWRSW_ISET_S0_R
=PP3V3_S4_TBTBPWRSW
=PPHV_SW_TBTBPWRSW
=TBT_S0_EN
TBTBPWRSW_ISET_S3_R
TBT_B_HV_EN
TBTBPWRSW_ISET_S0
TBTBPWRSW_ISET_S3
=TBTBPWRSW_EN
TBT_B_R2D_C_P<1>
TBT_B_R2D_C_P<0> TBT_B_R2D_C_N<0>
DP_TBTPB_ML_P<1>
TBT_B_LSTX
DP_TBTPB_AUXCH_N
DP_TBTPB_ML_C_N<3>
TBT_B_R2D_C_N<1>
DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
DP_B_AUXCH_DDC_N DP_B_AUXCH_DDC_P
DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>
DP_TBTPB_DDC_CLK
DP_TBTPB_DDC_DATA
TBT_B_CONFIG1_BUF
TBT_B_HPD
TBT_B_DP_PWRDN
DP_TBTPB_HPD
TBT_B_CONFIG1_RC
TBT_B_CIO_SEL
TBT_B_BIAS
TBT_B_D2R1_AUXDDC_N
DP_B_LSX_ML_P<1>
TBT_B_D2R_N<1> TBT_B_D2R_P<1>
TBT_B_D2R_C_N<1>
TBT_B_D2R_N<0> TBT_B_D2R_P<0>
TBT_B_CONFIG2_RC
TBT_B_CONFIG1_RC
prefsb
051-9505
8.0.0
96 OF 144 79 OF 123
2
1
1 2
121
2
1
2
2 1
2 1
2
1
2
11
2
121
2
121
2
21
2
1
A K
A K
1
2
1
2
1 2
1 2
1 2
1 2
1
2
1
2
1 2
1 2
9
18
10
5
17
11
16
123
4
13
21
12 14
7
6
8
15
20
19
121
2
1
2
2
1
19
20
15
3
10
11
5
8
7
2
23
22
25
21
9
1
24
4
16 18
6
14
13
12 17
1
2
1
2
2
1
2
1
1
2
1
2
2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
121
2
2
1
6
3
4
2
1
5
2
1
27
25
29
38
36
24 26
40
28
22
32
30
53
54
565758
5960616263
64
55
34
23
21
39
37
35
33
31
1 2
1 2
1 2
1 2
212
1
212
1
2
1
2
1
111
111
121
111
79
111
79
111
111
111
111
111
111
79
122
121
79
111
79
111
111
6
36 37 38 77 79
111
111
6
36 37 38 77 79
6
48
6
111
111
79
111
79
111
79
111
79
111
79
79
122
79
122
111
79
111
111
79
122
NC NC
OUT
B
Y
A
IN
NC
G
D
S
NC
NC
NC
B
Y
A
NC
G
S
D
NC
NC
NC NC
S
D
G
NC
THRM_PAD
VDD
GND
COMP
DIS/EN*
BP
GDRV
ISNS
RC
SS
FB
NC
D
G S
Y
A
B
08
D
G S
Y
A
B
08
IN
GND
OUT
GND
OUT
IN
NC
NC
NC
NC
P1.26/RTCK
P1.27/TDO
P0.3/SDA0/MAT0.0/EINT1 P0.4/SCK0/CAP0.1/AD0.6
P0.10/CAP1.0
P0.9/RXD1/PWM6/EINT3
P0.8/TXD1/PWM4
P0.29/AD0.2/CAP0.3/MAT0.3
VDD
VDDA VREF
P0.23
P0.27/AD0.0/CAP0.1/MAT0.1
P0.30/AD0.3/EINT3/CAP0.0
P0.0/TXD0/PWM1 P0.1/RXD0/PWM3/EINT0 P0.2/SCL0/CAP0.0
P0.5/MISO0/MAT0.1/AD0.7 P0.6/MOSI0/CAP0.2 P0.7/SSEL0/PWM2/EINT2
P0.11/CAP1.1/SCL1 P0.12/MAT1.0 P0.13/MAT1.1 P0.14/EINT1/SDA1 P0.15/EINT2 P0.16/EINT0/MAT0.2/CAP0.2 P0.17/CAP1.2/SCK1/MAT1.2 P0.18/CAP1.3/MISO1/MAT1.3 P0.19/MAT1.2/MOSI1/CAP1.2 P0.20/MAT1.3/SSEL1/EINT3 P0.21/PWM5/CAP1.3 P0.22/CAP0.0/MAT0.0
P0.25/AD0.4/AOUT P0.26/AD0.5
P0.28/AD0.1/CAP0.2/MAT0.2
P0.31
P1.16/TRACEPKT0 P1.17/TRACEPKT1 P1.18/TRACEPKT2 P1.19/TRACEPKT3 P1.20/TRACESYNC P1.21/PIPESTAT0 P1.22/PIPESTAT1 P1.23/PIPESTAT2
P1.24/TRACECLK
P1.25/EXTIN0
P1.28/TDI P1.29/TCK P1.30/TMS
P1.31/TRST*
RESET*
RTCX1 RTCX2
VBAT
VSS
VSSA
XTAL1 XTAL2
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
APN 998-3605
(WAS BLC_BLON)
14V BLC PRE-REGULATOR
(IPU)
BLC_EN IS DRIVEN BY TCON (CSA95)
353S3748
(WAS BLC_GPIO)
BLC MCU
D8:SUOPERTEX GPIOS FOR BLC ISP RDAR://10987156
D8 PROTO 2 BLC ADDING 3.3V VOLTAGE REFERENCE RDAR://11280328
MCU ISP PROG AND TEST CONNECTOR
402
5%
0
1/16W MF-LF
R9716
MF-LF
1/16W
5%
10M
402
R9717
NOSTUFF
R9718
4.7K
5%
1/16W
MF-LF
402
NOSTUFF
R9719
4.7K
402
MF-LF
1/16W
5%
R9715
10K
402
MF-LF
5%
1/16W
402
MF-LF
1/16W
5%
10K
R9705
100K
MF-LF
R9707
402
1/16W
5%
402
MF-LF
1/16W
5%
R9706
1K
R9702
402
1K
5%
1/16W MF-LF
D9700
BAS316DG
SOD323-SM
402
MF-LF
1/16W
5%
100K
R9703
X5R 402
10%
1UF
C9705
16V
R9720
NOSTUFF
4.7K
5% 1/16W MF-LF
402
NOSTUFF
R9721
4.7K
5% 1/16W MF-LF 402
NOSTUFF
1/16W
R9726
MF-LF
0
5%
402
1/16W
5%
1K
R9728
402
MF-LF
10K
R9727
5%
402
1/16W MF-LF
F-RT-SM
CF20151D0R0-NH
DEVELOPMENT
J9700
603
50V
5%
1000PF
C9701
C0G-CERM
603
C0G-CERM
50V
5%
1000PF
C9702
603
C0G-CERM
50V
5%
1000PF
C9703
C0G-CERM
50V 603
5%
C9725
1000PF
1000PF
5%
603
50V C0G-CERM
C9709
82
117
U9780
SOT353
74LVC1G08GW
80
117
1%
R9780
100K
1/10W MF-LF 603
0603
NOSTUFF
L9702
1KOHM-25%-0.6A
C9735
603
X5R
16V
10%
2.2UF
1KOHM-25%-0.6A
0603
L9704
402
MF-LF
1/16W
5%
R9722
0
50V
1000PF
C9722
5%
603
C0G-CERM
10K
R9724
1/10W
1% MF-LF
603
Q9700
SOT23-3
BSH111DG
1/10W
1%
603
MF-LF
R9725
10K
NOSTUFF
M-ST-TH
HB3902U-L
J9701
10UF
C9748
35V X5R
10%
1210
D9740
SS12P4S
TO277A
PRE_BOOST:Y
Q9740
PRE_BOOST:Y
CSD16412Q5A
MLP5X6-LFPAK-Q5A
MF-LF 603
1/10W
R9750
1%
49.9K
PRE_BOOST:Y
PIMB136T-SM
L9740
NOSTUFF
12UH-7A-0.02OHM
10
805
MF-LF
R9744
1/8W
1%
NOSTUFF
0.010
1%
2010
1W MF
R9749
PRE_BOOST:Y
603
1.0K
R9748
1% 1/10W MF-LF
PRE_BOOST:Y
0805
X7R
50V
10%
C9744
1.0UF
PRE_BOOST:Y
5%
MF-LF
1/10W
603
R9743
330K
PRE_BOOST:Y
C9743
10%
0805
X7R
1.0UF
50V
PRE_BOOST:Y
50V
270PF
603
5% CERM
C9742
PRE_BOOST:Y
X7R
10% 50V
C9746
0.1UF
603-1
PRE_BOOST:Y
C9741
0.1UF
603-1
50V
10%
X7R
PRE_BOOST:Y
1.10K
MF-LF
1/8W
1%
805
R9745
PRE_BOOST:Y
603
MF-LF
R9742
1/10W
1%
10K
PRE_BOOST:Y
10%
CERM
603
50V
1500PF
C9740
PRE_BOOST:Y
0.001
1% 1W
R9752
2512
MF-LF
74LVC1G08GW
SOT353
U9790
Q9701
SOT23-HF1
2N7002
10K
402
5% 1/16W MF-LF
R9790
MF-LF
402
10K
R9791
1/16W
5%
10K
R9793
402
MF-LF
5% 1/16W
1/16W MF-LF
5%
402
10K
R9792
2.2UF 10% 25V
603
C9771
X5R-CERM
4.7UF
C9770
0603
25V
10% X5R-CERM
1/10W
5%
0
MF-LF 603
R9740
PRE_BOOST:Y
603
1/10W MF-LF
5%
R9741
22K
PRE_BOOST:Y
Q9741
FDMS6681Z
POWER56
NOSTUFF
PRE_BOOST:Y
1%
MF-LF
30.1
1/10W
R9747
603
5%
1/16W MF-LF
402
0
R9797
U9740
TPS40210
MSOP
PRE_BOOST:Y
402
1/16W
5% MF-LF
R9781
X7R-CERM
390PF
C9745
0402
50V
10%
PRE_BOOST:Y
C9747
0.068UF
10% 50V X7R-CERM 0603
PRE_BOOST:Y
49.9K
603
1% 1/10W
R9751
MF-LF
PRE_BOOST:Y
SSM3K15AMFVAPE
VESM
CRITICAL
Q9711
U9710
74LVC2G08
CRITICAL
SOT902
4
8
C9710
0.1UF
10%
201
X5R
6.3V
CRITICAL
VESM
Q9710
SSM3K15AMFVAPE
U9710
CRITICAL
SOT902
74LVC2G08
4
8
5%
MF-LF
1/16W
402
0
R9712
MF-LF
1/16W
5%
402
0
R9713
NOSTUFF
5%
100K
R9711
MF-LF 402
1/16W
NOSTUFF
MF-LF
R9710
402
1/16W
5%
100K
5%
R9730
402
0
1/16W MF-LF
5%
1/16W
R9731
0
MF-LF
402
18PF
5% 50V
C9706
0402
C0G-CERM
18PF
0402
5% 50V C0G-CERM
C9707
10X10.8-SM
C9749
470UF
20% 25V ELEC
DPAK
U9770
L78M08ABDT
0603
L9703
1KOHM-25%-0.6A
402
MF-LF
NOSTUFF
10K
R9732
5% 1/16W
10K
MF-LF
R9733
1/16W
5%
402
U9720
REF3333
SOT23-3
C9720
2.2UF
603
16V X5R
10%
4.7UF
C9721
603
6.3V
10% X5R-CERM
1206
MF
1/4W
R9701
0.1%
0.100
603
5% CERM
1000PF
C9733
25V
603
C9734
16V
10% X5R
2.2UF
Y9705
3.2X2.5MM-SM
12.000MHZ-30PPM-10PF-85C
CRITICAL
X7R-CERM
16V
10%
0.1UF
C9791
0402
0.1UF
10% 16V X7R-CERM
C9792
0402
C9704
0402
16V
10%
0.1UF
X7R-CERM
0.1UF
X7R-CERM
10% 16V
0402
C9708
0402
16V X7R-CERM
0.1UF
10%
C9790
LQFP
OMIT_TABLE
LPC2132FBD64
U9700
SYNC_DATE=08/27/2012
Backlight Controller MCU
SYNC_MASTER=D8_MLB
BLC_MCU_RXD0 BLC_MCU_B_SDA_CONN
LCD_BKLT_PWM
BOOST_BYPASS
PP12V_S0_BLC_VINP
BOOST_FET_DRAIN
BLC_P3V3_REF
BOOST_FB
BOOST_ISNS_R
BLC_MCU_XTAL_IN
BLC_MCU_XTAL_OUT
BLC_MCU_RESET_L
TP_BLC_MCU_TP_2
SMB_PCH_BLC_SCL
PP5V_S0_BLC_R
BLC_P3V3S
LED_DRIVER_OVP3P
LCD_BKLT_PWM
BLC_P3V3S
BLC_EXT_BOOT_L
=PP3V3_S0_BLC
BLC_P3V3S
BLC_P3V3_REF
BLC_P3V3S
BLC_MCU_PWM5_R
PP5V_S0_BLC_R
BLC_P_ON
BOOST_GDRV
BLC_P3V3S
SMB_PCH_BLC_SDA
BLC_MCU_RXD0
PCH_BLC_MCU_RESET
BLC_UVLO
BLC_VSYNC
SMB_PCH_BLC_SDA
PM_PCH_PWROK
PCH_BLC_EXT_BOOT
BLC_MCU_UVLO
BLC_P3V3S
PP12V_S0_BLC_VIN2
PP8V_BLC
BLC_EN_R
TP_PCH_GPIO6_TACH2
BLC_MCU_RESET_L
BLC_MCU_TRST
BLC_MCU_TRST
BLC_P3V3S
BOOST_ISNS
BOOST_VDD
FLAG_V
BLC_ENA
BLC_MCU_TMS
BLC_MCU_RTCK
BLC_PWM_3_R
BLC_MCU_TCK
BOOST_COMP_C
BLC_BST
BOOST_COMP
PRE_REG_OUT_R
BOOST_GDRV_R
BLC_EN
BLC_PWM_2_R
BLC_MCU_TDI
BOOST_RC
BLC_BL
BLC_ENA
BLC_ENA1
FLAG_V
SMB_TCON_BLC_SDA
BLC_MCU_TXD0
=PP3V3_S0_BLC
BLC_EN
BLC_MCU_TDI
BLC_MCU_RTCK BLC_MCU_TDO
BLC_MCU_TCK
BLC_MCU_TXD0
BLC_PWM_1_R
BLC_GOOD
BLC_MCU_TDO
BLC_MCU_RXD0
SMB_TCON_BLC_SCL
BLC_MCU_XTAL_OUT_R
PP5V_S0_BLC_R
BLC_MCU_BV
BLC_MCU_FLAG_V
PRE_REG_OUT
SMC_BLC_MUX_TX_L
SMC_BLC_MUX_RX_L
BLC_MCU_RESET
BLC_MCU_RESET_L
BLC_VSYNC
STRCLK_R1
BLC_P3V3A
PP3V3_S0_BLC_R
PRE_REG_OUT
BLC_MCU_RESET_R_L
BLC_EXT_BOOT
BLC_MCU_TXD0
PM_PCH_PWROK
BLC_VSYNC_R
BLC_DIM_MCU
BLC_MCU_PWM5
LED_DRIVER_OVP2P
LED_DRIVER_OVP1P
SMB_PCH_BLC_SDA
BLC_MCU_TMS
BOOST_EN_L
BOOST_EN_L
BLC_BST_R
BOOST_EN_GATE
BLC_P3V3S
BLC_P3V3S
BLC_P3V3S
BLC_P3V3A
BLC_P3V3S
BOOST_BYPASS_GATE
BOOST_SS
BOOST_BP
prefsb
051-9505
8.0.0
97 OF 144 80 OF 123
1
2
1 2
1
2
1
2
1 2
1
2
1
2
1 2
1 2
A K
1
2
2
1
1
2
1
2
1 2
1 2
1
2
1 2 3 4 5 6 7 8 9 10
12
11
13 14 15
17
16
2
1
2
1
2
1
2
1
2
1
4
3
1
2
5
1
2
21
2
1
21
1 2
2
11
2
3
2
1
1 2
2
1
2
1
1
3
2
5
1 2 3
4
1
2
21
1 2
1
2
1 2
2
1
1 2
2
1
2
1
2
1
1 2
1
2
1 2
1 2
1 2
4
3
1
2
5
3
2
1
1
2
1 2
1
2
1
2
2
1
2
1
1
2
1 2
3 2 1
5
4
1 2
1 2
11
10
6
4
3
9
8
7
1
2
5
1
2
2
1
2
1
1
2
1
2
3
1
6
7
2
1
1
2
3
5
2
3
1 2
1 2
1
2
1
2
1 2
1 2
2
1
2
1
1
2
1
2
3
21
121
2
3
21
2
1
2
1
1 2
2
1
2
1
42
1 3
2
1
2
1
2
1
2
1
2
1
24 64
26 27
35
34
33
14
234351
7
63
58
11
15
19 21 22
29 30 31
37 38 39 41 45 46 47 53 54 55
1 2
9
10
13
17
16 12 8 4 48 44 40 36 32 28
60 56 52 20
57
3 5
49
6
1825425059
62 61
80
117
117
75 80
111
82
117
82
114
114
80 82
114
114
114
114
114
80
117
50
114
80 81 82
114
80 82
114
81
119
75 80
111
80 82
114
117
6
80
80 82
114
80 82
114
80 82
114
117
80 81 82
114
81 82
117
114
80 82
114
50 80
114
80
117
21
120
82
117
78 80
117
50 80
114
15 19 26 35 43 65 80
120
21
120
117
80 82
114
81 82
114
81
114
117
80
117
80
117
80
117
80 82
114
114
114
80 81 82
118
80
117
80
117
80
117
81
114
80
117
114
82 117
114
114
78 80 81
117
81
114
80
117
117
82
117
80 81 82
118
50
114
80
117
6
80
78 80 81
117
80
117
80
117
80
117
80
117
80
117
81
114
5
80
117
80
117
50
114
114
80 81 82
114
82
117
117
80 81
114
48
122
48
122
117
80
117
78 80
117
81
114
80
114
80 81
114
117
48
117
80
117
15 19 26 35 43 65 80
120
117
117
117
81
119
81
119
50 80
114
80
117
80
117
80
117
117
80 82
114
80 82
114
80 82
114
80
80 82
114
117
117
117
OUT
IN
IN
IN IN IN
OUT
OUT
IN
G
D
S
OUT
OUT
G
D
S
IN
OUT
OUT
OUT
OUT
G
D
S
IN
S
G
D
S
G
D
S
G
D
VDD3
VIN
VDD1
VDD2
VDD
GATE1
CS1
FDBK1
OVP1
FLT1
CS2
GATE2
OVP2
GATE3
FLT2
FDBK2
FDBK3
FLT3
CS3
OVP3
GND1
GND
GND2
GND3
THRM
PWMD2
PWMD1
PWMD3
IREF3
IREF2
IREF1
CLK
EN
COMP1
COMP3
COMP2
SKIP
VIN_SNS
FLG
SC
NC
PAD
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MF-LF
1% 1/8W
100K
R9820
805
10% X7R
100V
C9824
1000PF
603
81 82
114
80
114
10%
1000PF
C9825
NOSTUFF
603
100V X7R
82
114
MF-LF
603
1/10W
2.0K
1%
R9803
R9804
2.0K
1/10W MF-LF1%603
1%
603
1/10W MF-LF
R9801
2.0K
CERM
5% 50V
402
C9829
150PF
NOSTUFF
82
114
82
114
82
114
D9800
BAS316DG
SOD323-SM
80
119
81 82
119
78 80
117
NOSTUFF
603
MF-LF
1/10W
5%
R9834
0
RJK1211DNS
Q9821
HWSON-8
MF-LF
NOSTUFF
1/10W
634K
603
1%
R9824
R9806
603
MF-LF
0.1%
24.9K
1/16W
NOSTUFF
R9826
MF 2512
4.7
1W
1%
603
5%
MF-LF
1/10W
R9825
220
SD9820
SS5P10-M3
TO277A
SHORT-1206
XW9800
81 82
119
80
119
TO277A
SS5P10-M3
SD9860
R9808
1M
603
MF-LF
1/10W
1%
100V 603
C9864
X7R
10%
1000PF
1/8W 805
1% MF-LF
100K
R9860
4.7
1W
R9866
NOSTUFF
2512
MF
1%
402
5% CERM
C9869
150PF
NOSTUFF
50V
603
R9865
5%
MF-LF
1/10W
220
MF-LF
5%
0
1/10W
603
R9863
HWSON-8
Q9861
RJK1211DNS
1/10W
NOSTUFF
MF-LF
1%
603
634K
R9864
82
114
MF-LF
1/8W
805
5%
22
R8667
LED_FLT_R_3
603
X7R
C9865
1000PF
10%
NOSTUFF
100V
1/10W MF-LF
603
R9869
1%
1.0K
NOSTUFF
603
MF-LF
1/10W
5%
R9874
0
82
114
82 114
81 82
119
80
119
TO277A
SD9840
SS5P10-M3
1/10W
R9805
1.0K MF-LF
603
1%
X7R
10%
C9844
603
1000PF
100V
805
1% MF-LF
1/8W
100K
R9840
1% MF
1W 2512
4.7
R9846
NOSTUFF
CERM 402
50V
5%
150PF
NOSTUFF
C9849
603
10% 100V
NOSTUFF
C9845
1000PF
X7R
603
MF-LF
5%
220
1/10W
R9845
1/10W5%603
MF-LF
0
R9843
Q9841
RJK1211DNS
HWSON-8
603
MF-LF
1%
1/10W
R9844
634K
NOSTUFF
82
114
MF-LF
805
LED_FLT_R_2
1/8W
5%
R8647
22
603
MF-LF
R9849
1.0K
1/10W
1%
0
R9854
5% MF-LF
603
1/10W
NOSTUFF
16V X5R-X7R
C9808
603-2
10%
1UF
PLACE_NEAR=U9800.9:3MM
IRF6645PBF
DIRECTFET-SJ
Q9820
DIRECTFET-SJ
Q9840
IRF6645PBF
IRF6645PBF
Q9860
DIRECTFET-SJ
0.00
R9891
1/10W
0% FF
0603
0.00
R9892
FF
0%
0603
1/10W
R9893
0.00
1/10W
0% FF
0603
NOSTUFF
POWERDI-123
D9820
DFLS1100
DFLS1100
POWERDI-123
D9840
NOSTUFF
DFLS1100
D9860
NOSTUFF
POWERDI-123
0603
X7R-CERM
C9880
NOSTUFF
10%
2.7NF
25V
U9800
HV9989K6-G
QFN
1/10W
R9881
0.00
FF
0%
0603
CRITICAL
X7R 603
100V
1000PF
10%
C9833
C9832
1000PF
603
X7R
100V
10%
CRITICALCRITICAL
X7R
10%
603
100V
1000PF
C9859
100V 603
C9822
CRITICAL
10% X7R
1000PF
603
X7R
10% 100V
1000PF
C9821
CRITICAL
X7R
100V
10%
1000PF
C9820
CRITICAL
603
25V 0603
10% X7R
1UF
C9812
X7R 0603
25V
10%
1UF
C9813
R9829
1%
603
MF-LF
1/10W
1.0K
C9802
0.47UF
50V CERM-X5R 0603
10%
L9820
IHLP6767GZ-SM
33UH-20%-10A-0.0351OHM
OMIT_TABLE
L9840
33UH-20%-10A-0.0351OHM
IHLP6767GZ-SM
OMIT_TABLE
L9860
IHLP6767GZ-SM
33UH-20%-10A-0.0351OHM
OMIT_TABLE
603
MF-LF
1/10W
5%
0
R9835
0
MF-LF
603
R9855
1/10W
5%
0
R9875
MF-LF
603
5%
1/10W
R9847
MF-LF
603
5%
0
NOSTUFF
1/10W
1% 2W MF 2512-LF
R9828
0.03
R9848
0.03
2512-LF
MF
2W
1%
R9868
0.03
MF
2W
1%
2512-LF
10% X7R-CERM
100V
C9830
1000PF
0603
100V X7R-CERM
1000PF
0603
10%
C9850
100V
C9870
0603
X7R-CERM
10%
1000PF
C9851
100PF
C0G-CERM 0603
5% 100V
100PF
100V C0G-CERM
5%
0603
C9871
100PF
100V C0G-CERM
5%
0603
C9831
NOSTUFF
C0G-CERM5%0603
100V
C9881
100PF
0603
100PF
5%
C0G-CERM
100V
C9882
NOSTUFF
C0G-CERM 0603
C9883
100PF
5%
100V
NOSTUFF
R9880
603
5% MF-LF
120K
1/10W
MF-LF
1/8W
5%
805
LED_FLT_R_1
R9827
22
1/16W
R9897
402
1%
MF-LF
0.0022UF
PLACE_NEAR=U9800.15:3MM
10%
C9806
0603-1
CERM
50V
SHORT-1206
XW9803
1% 1/10W
603
2.94K
MF-LF
R9822
1% 1/10W MF-LF 603
R9821
845
603
MF-LF
1%
R9842
1/10W
2.94K
845
603
MF-LF
1/10W
1%
R9841
R9862
2.94K
603
MF-LF
1/10W
1%
R9861
845
603
MF-LF
1/10W
1%
C9873
10UF
25V
10% X5R
1206-1
10% 25V X5R 1206-1
C9872
10UF
10UF
1206-1
25V
10% X5R
C9874
10UF
C9875
X5R
25V 1206-1
10%
10% X5R
25V 1206-1
10UF
C9877
1206-1
25V X5R
10%
10UF
C9876
MF-LF
1/16W
5%
402
R9896
1
R9830
6.2
1/10W FF 0603
0.1% 1/10W
0.1%
R9833
51
FF 0603
R9831
6.2
1/10W
0.1%
0603
FF
R9832
6.2
1/10W
0.1%
0603
FF
51
0.1% 1/10W FF 0603
R9853
0.1% 1/10W FF
6.2
0603
R9852
0.1% 1/10W FF
6.2
0603
R9851
0.1% 1/10W FF
6.2
0603
R9850
FF
1/10W
0.1%
0603
51
R9873
0603
6.2
FF
1/10W
0.1%
R9872
FF 0603
R9870
0.1% 1/10W
6.2
0603
6.2
FF
1/10W
0.1%
R9871
50V
603
CERM
5%
100PF
C9891
PLACE_NEAR=U9800.12:3MM
50V 603
100PF
C9890
5% CERM
PLACE_NEAR=U9800.4:4MM
603
100PF
5% 50V CERM
PLACE_NEAR=U9800.27:3MM
C9892
MF-LF
603
1/10W
0
R9823
5%
C9823
20% 100V
10X12.5-TH
ELEC
20% ELEC
100V 10X12.5-TH
C9843
ELEC
20% 100V
10X12.5-TH
C9863
603
MF-LF
1% 1/10W
143K
R9814
PLACE_NEAR=U9800.4:7MM
1%
603
1/10W MF-LF
143K
R9815
PLACE_NEAR=U9800.12:6MM
143K
1%
603
MF-LF
1/10W
R9816
PLACE_NEAR=U9800.27:5MM
50V
5%
1000PF
C9816
C0G-CERM
PLACE_NEAR=R9815.2:25MM
603
1000PF
C9815
50V
5%
603
C0G-CERM
PLACE_NEAR=R9815.2:2MM
1000PF
C9814
603
50V
5%
PLACE_NEAR=R9814.2:2MM
C0G-CERM
R9898
402
6.98K
1% MF-LF
1/16W
2.2UF
C9826
CRITICAL
10% 100V X7R-CERM 1210-2
2.2UF
C9827
CRITICAL
10% 100V X7R-CERM 1210-2
2.2UF
C9828
10% X7R-CERM
100V
CRITICAL
1210-2
X7R-CERM
100V
10%
CRITICAL
2.2UF
C9840
1210-2
X7R-CERM
10%
CRITICAL
C9841
2.2UF
100V 1210-2
CRITICAL
C9842
2.2UF
10% 100V X7R-CERM 1210-2
X7R-CERM
100V
10%
CRITICAL
2.2UF
C9853
1210-2
X7R-CERM
100V
10%
CRITICAL
2.2UF
C9854
1210-2
X7R-CERM
100V
10%
CRITICAL
2.2UF
C9855
1210-2
X7R-CERM
100V
10%
CRITICAL
C9856
2.2UF
1210-2
2.2UF
C9857
CRITICAL
10% 100V X7R-CERM 1210-2
X7R-CERM
100V
10%
CRITICAL
C9858
2.2UF
1210-2
1%
0603
PLACE_NEAR=U9800.4:5MM
1/10W MF-LF
2.0M
R9817
1%
MF-LF 0603
PLACE_NEAR=U9800.12:4MM
1/10W
2.0M
R9812
R9818
0603
MF-LF
1/10W
1%
2.0M
PLACE_NEAR=U9800.27:3MM
C9809
16V
10%
1UF
603-2
X5R-X7R
PLACE_NEAR=U9800.1:4MM
X5R-X7R
16V
10%
603-2
C9810
1UF
PLACE_NEAR=U9800.33:3MM
C9811
1UF
16V X5R-X7R 603-2
10%
PLACE_NEAR=U9800.30:3MM
XW9801
SHORT-1206
SHORT-1206
XW9802
SYNC_MASTER=D8_MLB
Backlight LED Driver
SYNC_DATE=08/27/2012
3
IND,PWR,33UH,20%,10A,35.5MOHM
L9820,L9840,L9860
CRITICAL152S1668
PRE_REG_OUT
BLC_VOUT1
PRE_REG_OUT
BLC_SNUB_3
LED_DRVR_CS_RC_3
LED_DRVR_DRAIN_3
LED_DRVR_DRAIN_1
BLC_GND_1
BLC_VOUT1
BLC_GND_1
BLC_VOUT1
BLC_GND_1
BLC_GND_3
LED_DRIVER_OVP3
BLC_VOUT3
LED_DRIVER_OVP3P
LED_DRIVER_OVP2_OUT
BLC_GND_2
BLC_VIN_SNS
PP5V_S0_BLC_R
LED_DRIVER_GATE3
BLC_GND_2
IS2_BLC
LED_DRVR_CS_C1
LED_DRIVER_GATE3
BLC_GND_2
BLC_GND_3
BLC_GND_1
BLC_VOUT2
BLC_SNUB_2
BLC_SKIP
LED_DRIVER_REF3
LED_DRIVER_REF1
LED_DRIVER_OVP1_OUT
LED_DRIVER_GATE2
BLC_GND_1
LED_DRIVER_FDBK3
BLC_PWM_3
BLC_GND_3
LED_DRIVER_FDBK3
LED_DRIVER_FDBK_R_3
LED_DRIVER_OVP3
BLC_GND_2
LED_DRIVER_FDBK_R_2
BLC_GND_1
LED_DRIVER_FDBK_R_1
PRE_REG_OUT
LED_DRIVER_OVP2
LED_DRIVER_GATE3_R
LED_DRIVER_OVP1
BLC_GND_1
LED_DRIVER_GATE2_R
PP12V_S0_BLC_VIN2
SPTX_VIN
LED_DRIVER_FDBK1
LED_DRIVER_REF2
BLC_GND_1
LED_DRIVER_OVP2P
LED_DRIVER_OVP2
LED_DRIVER_OVP1P
LED_DRVR_CS_RC_1
LED_DRIVER_CS2
LED_DRIVER_FDBK2
LED_DRIVER_CS1
LED_DRVR_CS_C3
LED_DRVR_DRAIN_2
IS3_BLC
BLC_GND_3
U9800_PIN20
FLAG_V
BLC_VIN_SNS
LED_DRIVER_OVP1
LED_DRIVER_FLT1
BLC_VIN2
BLC_SNUB_1
LED_DRIVER_FDBK2
LED_DRIVER_FLT3
LED_DRIVER_OVP2_OUT
LED_DRIVER_CS2
LED_DRIVER_FLT2
BLC_VIN2
LED_DRIVER_GATE2
BLC_VIN2
LED_DRIVER_FLT3
IS1_BLC
AGND_BLC
LED_DRIVER_OVP3_OUT
BLC_PWM_2_R
BLC_PWM_1_R
BLC_P_ON
BLC_PWM_3_R
PP8V_BLC
BLC_EN
AGND_BLC
BLC_GND_1
LED_DRIVER_OVP3_OUT
LED_DRIVER_CS3
LED_DRIVER_FLT2
LED_DRIVER_GATE1
BLC_PWM_1
LED_DRIVER_CS3
BLC_GND_3
BLC_PWM_2
LED_DRIVER_EN
BCOMP3
U9800_SC
BCOMP1
BLC_GND_3
BLC_GND_2
BLC_VIN2
LED_DRIVER_GATE1_R
LED_DRVR_CS_RC_2
BCOMP2
AGND_BLC
LED_DRVR_CLK
STRCLK_R1
BLC_GND_2
BLC_GND_3
AGND_BLC
BLC_GND_3
LED_DRIVER_COMP2
LED_DRIVER_COMP1
LED_DRIVER_COMP3
BLC_GND_1 BLC_GND_2
LED_DRVR_CS_C2
BLC_GND_2
81 OF 123
8.0.0
051-9505
prefsb
98 OF 144
1
2
2
1
2
1
1 2
1 2
1 2
2
1
AK
1
2
5
1 2 3
4
1 2
1 2
1
2
1 2
1
3
2
1 2
1
3
2
1
2
2
1
1
2
1
2
2
1
1 2
1 2
5
1 2 3
4
1 2
1 2
2
1
1 2
1
2
1
3
2
1 2
2
1
1
2
1
2
2
1
2
1
1 2
1 2
5
1 2 3
4
1 2
1 2
1 2
1
2
2
1
6 71 2
43
5
6 71 2
43
5
6 71 2
43
5
1 2
1 2
1 2
A K
A K
A K
2
1
30
8
1339
40
3
5
7
2
37
35
14
31
36
38
26
29
28
24
391134
32
41
18
17
19
25
13
6
23
10
4
27
12
15
21
22
16
20
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2
1
21
21
21
1 2
1 2
1 2
1 2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
1 2
1 2
1 2
1
2
1 2
1
2
2
1
1 2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
1 2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
1 2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
2
1
2
1
2
1
1 2
1 2
114
80 81
114
80 81
114
114
114
114
81 82
114
81 82
114
81 82
114
81 82
114
81 82
114
81
119
81 82
114
81
117
80 82
114
81
114
81 82
114
114
81
114
81 82
114
81 82
114
81 82
114
117
119
81
114
81 82
114
81
114
82
114
81 82
114
81
114
114
81 82
119
81 82
114
114
81 82
114
114
80 81
114
81 82
119
114
81 82
114
114
80 82
114
114
114
81 82
114
114
81
114
81
114
114
114
81 82
114
80 82 118
81
117
81 82
119
114
81 82 114
81
114
81
114
81
119
81
114
81
114
81 82
114
81
114
81 82
114
81
114
81 82
114
81
119
80
114
80
114
80 82
117
80
114
80
114
81 82
114
81 82
114
81
119
81
114
81
114
114
82
114
81
114
81 82
114
82
114
82
119
114 114
81 82
114
81 82
114
81 82
114
114
114
114
81 82
114
114
81 82
114
81 82
114
81 82
114
81 82
114
114
114
114
81 82
114
81 82
114
81 82
114
OUT
OUT
OUT
G
S
D
G
S
D
G
S
D
G
S
D
B
Y
A
IN
B
Y
A
S
D
G
NC
1IN+ 1IN-
2IN+ 2IN-
3IN+
4IN-
3IN-
4IN+
1OUT
2OUT
GND
VCC
3OUT
4OUT
1IN+ 1IN-
2IN+ 2IN-
3IN+
4IN-
3IN-
4IN+
1OUT
2OUT
GND
VCC
3OUT
4OUT
SYM_VER-1
SYM_VER-1
SYM_VER-1
D
S
G
IN
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
UVLO VIN2 BLC_BL
2.0V @10V = "0" (SHUTDOWN)
2.5V @12V = "1"
Backlight Connector
518S0862
NOSTUFF STUFF NOSTUFF STUFF
NO BYPASS NOSTUFF
R9999:
R9976:
UVP PROTECTION
PWM <= 50% -> TURN ON BOOST PWM > 50% -> TURN OFF BOOST
NOSTUFF
BYPASS STUFF
R9995:
R9998:
STUFF NOSTUFF
R9994:
STUFF
OVP PROTECTION
Output Current Adjustment
BLC12V BYPASS STUFFING OPTION
IN-RUSH CURRENT LIMITER
81
114
81
114
81
114
Q9940
2N7002
SOT23-HF1
1/10W MF-LF
R9940
603
0
5%
Q9951
SOT23-3
BSH111DG
Q9953
SOT23-3
BSH111DG
SOT23-3
BSH111DG
Q9952
R9955
1/10W MF-LF
1%
603
499K
X7R
C9955
603-1
50V
0.1UF
10%
603
MF-LF
1/10W
0
5%
R9951
603
MF-LF
1/10W
R9952
0
5%
5%
0
603
MF-LF
1/10W
R9953
1206
C9973
CERM
4.7UF
20% 25V
1206
20%
4.7UF
25V CERM
C9972
R9980
10K
1/10W
5%
MF-LF
603
BAS316DG
SOD323-SM
D9900
1/10W MF-LF
603
R9981
5%
1.0K
5%
1.0M
R9979
1/10W MF-LF
603
MF-LF 603
1/10W
R9974
5%
10K
R9970
10K
603
5% MF-LF
1/10W
5%
100K
1/10W MF-LF
603
R9972
SOT23-HF1
2N7002
Q9926
1% 1/10W MF-LF 603
R9967
1M
R9968
0603
2.0M
1% MF-LF
1/10W
R9966
1/10W MF-LF
5%
0
603
D9901
BAS316DG
SOD323-SM
1% 1/10W MF-LF 603
R9964
10%
603
X5R
16V
1UF
C9964
603
1% 1/10W
R9962
10K
MF-LF
R9963
0603
MF-LF
1/10W
1%
R9961
1/10W MF-LF 603
0
5%
C9962
1UF
10% 16V X5R 603
X7R
10% 50V
603-1
0.1UF
C9963
SOD323-SM
BAS316DG
D9902
38.3K
1%
R9914
1/10W MF-LF 603
603
MF-LF
1/10W
5%
R9934
10
X7R
C9912
10% 50V
0.1UF
603-1
10% X7R
50V
C9913
0.1UF
603-1
R9912
1/10W MF-LF 603
1%
603
R9913
1% 1/10W MF-LF
34.8K
R9936
MF-LF
603
1/10W
10
5%
C9911
0.1UF
10% 50V
603-1
X7R
1/10W
1%
603
MF-LF
R9910
R9911
43K
0603
MF-LF
1/10W
1%
0.1UF
X7R
10%
C9910
603-1
50V
SOT23-HF1
2N7002
Q9924
MF-LF
R9918
5%
603
10K
1/10W
Q9925
2N7002
SOT23-HF1
R9938
603
1/10W
5%
10
MF-LF
R9969
1/10W
5%
1.5M
603
MF-LF
50V
10% X7R
C9914
0.1UF
603-1
X5R-CERM 0402
0.1UF
50V
NOSTUFF
10%
C9970
C9931
10%
603
16V X5R
1UF
10% X5R
16V 603
C9934
1UF
16V
C9936
X5R
10%
1UF
603
100V
10%
603
1000PF
CRITICAL
X7R
C9949C9948
10%
603
X7R
CRITICAL
1000PF
100V
10% 100V X7R 603
1000PF
CRITICAL
C9947
X7R
CRITICAL
10%
C9946
603
1000PF
100V
1000PF
C9945
603
100V
CRITICAL
10% X7R
X5R 603
1UF
10% 16V
C9938
CRITICAL
C9944
1000PF
603
X7R
10% 100V
100V
1000PF
X7R
CRITICAL
603
10%
C9990
603
CRITICAL
X7R
100V
10%
C9969
1000PF
C9935
X7R
50V 603-1
0.1UF
10%
1000PF
C9968
CRITICAL
603
X7R
100V
10%
603
X7R
100V
C9967
10%
1000PF
CRITICALCRITICAL
C9966
1000PF
10% 100V X7R 603
1000PF
X7R
10%
603
100V
CRITICAL
C9965
10%
603-1
X7R
50V
C9937
0.1UF
10K
5%
603
1/10W MF-LF
R9919
74LVC1G08GW
U9960
SOT353
74
120
X7R
10%
C9939
50V
0.1UF
603-1
U9970
SOT353
74LVC1G08GW
10K
1/10W
R9915
MF-LF 603
1%
NOSTUFF
1/16W MF-LF
R9996
402
0
5%
5%
402
1/16W
0
MF-LF
R9995
402
MF-LF
R9994
1K
5% 1/16W
NOSTUFF
1/16W
5%
R9971
1K
MF-LF
402
X7R
50V
0.1UF
10%
603-1
C9997
POWER56
Q9970
FDMS6681Z
R9977
215
25121% 1W
MF-LF
25121W
MF-LF
215
1%
R9997
F9900
1206
10AMP-63V
5%
1/16W
MF-LF
402
0
BLC12V_BYPASS:Y
R9999
220-OHM-1.4A
L9921
0603
BLC12V_BYPASS:Y
5%
0
402
1/16W
R9998
MF-LF
LM324DEX
U9950
SOI
SOI
U9920
LM324DEX
ELEC
35V
20%
6.3X8-SM-HF
C9974
100UF
NOSTUFF
L9920
DLW5BT-SM-HF
250-OHM-5A
DLW5BT-SM-HF
250-OHM-5A
L9922
NOSTUFF
L9923
220-OHM-1.4A
0603
DLW5BT-SM-HF
NOSTUFF
L9924
250-OHM-5A
S0T23-3-HF
Q9971
BSS84
603
C9998
1000PF
25V CERM
5%
603
CERM
C9999
1000PF
5% 25V
NOSTUFF
C9971
0.068UF
0603
X7R-CERM
50V
10%
220-OHM-1.4A
0603
L9925
BSH111DG
SOT23-3
Q9973
BSH111DG
SOT23-3
Q9972
Q9941
BSH111DG
SOT23-3
BSH111DG
SOT23-3
Q9974
100K
402
5% 1/16W MF-LF
R9927
71.5K
R9917
603
MF-LF
1/10W
1%
R9965
603
MF-LF
1/10W
56K
5%
0
R9928
MF-LF
1/10W
603
5%
0
1/8W
MF-LF
805
5%
R9920
1W
0.005
R9976
1%
MF
2512
10%
NOSTUFF
C9942
1UF
603-1
X5R
25V
R9932
FF
1/10W
0.1%
603
3.57K 3.57K
603
0.1% 1/10W FF
R9933
1/16W
0.5%
603
MF-LF
R9954
20K
R9916
603
1% 1/10W MF-LF
42.2K
R9921
1/8W5%0MF-LF
805
0.1%
MF-LF
1/16W
603
R9931
10.0K
NOSTUFF
C9975
CERM
16V
5%
603
0.047UF
1/10W
1%
603
MF-LF
499K
R9942
R9943
1/10W
1%
MF-LF
603
100K
1% MF-LF
1/10W 603
R9941
100K
805
5%
1/8W
0
MF-LF
R9922
MF-LF
1/10W
1%
10K
R9978
603
R9975
MF-LF
1/10W
10K
603
1%
504050-0691
M-RT-SM
J9920
C9920
10%
2.2UF
X7R-CERM
100V 1210-2
CRITICAL
1210-2
10%
2.2UF
C9921
X7R-CERM
100V
CRITICAL
1210-2
10%
2.2UF
C9923
X7R-CERM
100V
CRITICAL
1210-2
CRITICAL
10%
2.2UF
C9993
X7R-CERM
100V
R9923
805
MF-LF
1/8W5%
0
1210-2
10%
2.2UF
C9925
X7R-CERM
100V
CRITICAL
1210-2
C9926
2.2UF
10%
CRITICAL
100V X7R-CERM
1210-2
2.2UF
10%
C9927
X7R-CERM
100V
CRITICAL
1210-2
10%
2.2UF
C9928
X7R-CERM
100V
CRITICAL
1210-2
CRITICAL
10%
2.2UF
C9929
X7R-CERM
100V
1210-2
C9960
2.2UF
10% X7R-CERM
100V
CRITICAL
1210-2
2.2UF
C9961
10%
CRITICAL
100V X7R-CERM
1210-2
CRITICAL
C9992
2.2UF
10% 100V X7R-CERM
1210-2
C9991
CRITICAL
2.2UF
10% 100V X7R-CERM
5%
0
MF-LF
805
1/8W
R9924
1210-2
C9941
X7R-CERM
100V
10%
2.2UF
CRITICAL
1210-2
C9940
X7R-CERM
100V
10%
2.2UF
CRITICAL
1210-2
CRITICAL
C9989
X7R-CERM
100V
10%
2.2UF
1210-2
C9987
2.2UF
10% X7R-CERM
100V
CRITICAL
1210-2
X7R-CERM
C9986
CRITICAL
2.2UF
10% 100V
1210-2
X7R-CERM
C9985
100V
10%
2.2UF
CRITICAL
1210-2
C9984
X7R-CERM
100V
10%
2.2UF
CRITICAL
1210-2
100V
10%
2.2UF
C9983
CRITICAL
X7R-CERM
1210-2
2.2UF
C9982
X7R-CERM
100V
10%
CRITICAL
1210-2
X7R-CERM
2.2UF
CRITICAL
10% 100V
C9981
1/8W
MF-LF
0
R9925
5%
805
C9980
X7R-CERM
100V
10%
1210-2
2.2UF
CRITICAL
0402
10% 16V X7R-CERM
C9995
0.1UF
C9951
0.1UF
X7R-CERM
16V
10%
0402
X7R-CERM
16V
10%
0402
C9996
0.1UF
81
114
81
114
81
114
81 82
114
81
114
81 82
114
SYNC_MASTER=D8_MLB
Backlight Controller
SYNC_DATE=08/27/2012
IS2_BLC_F
BLC_VOUT1
IS1_BLC
BLC_LED_P_1
BLC_LED_N_2
BLC_LED_P_2
BLC_LED_N_3
PP12V_S0_BLC_VIN2
BLC_P_ON_D_R
FLAG_V_L
PP5V_S0_BLC_R
BLC_UVLO
LED_DRIVER_EN_L_R
LED_DRIVER_EN_L
AGND_BLC
BLC_P3V3S
BLC_P_ON_D
BLC_LED_P_3
PP5V_S0_BLC_R
OVP_OUT1
BLC_P3V3S
BLC_VINP_GATE
BLC_P_ON_DRAIN
PP12V_S0_BLC_VINP
UVP_REF
BLC_P3V3_REF
BLC_MCU_BV_D
BLC_MCU_BV
IS1_BLC_F
LED_DRIVER_REF1
LED_DRIVER_REF2
BLC_P3V3_REF
BLC_MCU_AOUT_R
OVP_OUT3_R
AGND_BLC
BLC_PWM_3
OVP_OUT3 AGND_BLC
BLC_P3V3_REF
=PP12V_S0_BLC
BLC_VIN2_GATE
BLC_VIN2_SRC
BLC_ON_DRAIN
AGND_BLC
LED_DRIVER_OVP1
BLC_VOUT3
=PP5V_S0_BLC
IS3_BLC_F
UVP_IN_4
PP5V_S0_BLC_R
BLC_BL_GATE
PP12V_S0_BLC_VINP
PP12V_S0_BLC_VIN2
BLC_GND_3
BLC_P_ON_R
LED_DRIVER_REF3
BLC_P3V3S
IS2_BLC
BLC_VOUT2
BLC_BST
BLC_P_ON_GATE
BLC_MCU_BV_R
LED_DRIVER_OVP2
LED_DRIVER_OVP3
BLC_PWM_2
OVP_OUT2_R
OVP_OUT2
BLC_P_ON
OVP_OUT1_R
BLC_GND_2
BLC_GND_1
BOOST_BYPASS
BLC_BYPASS_GATE
BLC_BL
BLC_ENA1
BLC_BL
BLC_ON_R
BLC_ENA1
BLC_P_ON
FLAG_V
BLC_P3V3S
BLC_ON
PP12V_S0_BLC_F
OCA_FET_DRAIN
PM_PGOOD_FET_P12V_S0_BLC
LED_DRIVER_EN
BLC_VIN2
AGND_BLC
BLC_PWM_1
BLC_P_ON_BYPASS
IS3_BLC
BLC_LED_N_1
UVP_IN_3
BLC_VOUT3
OVP_OREF
AGND_BLC
BLC_GND_2
BLC_GND_3
BLC_GND_3
UVP_IN_1 UVP_IN_1_REF
UVP_IN_2
BLC_MCU_BV
BLC_GND_2
BLC_VOUT2
BLC_VOUT3
BLC_VOUT2
prefsb
051-9505
8.0.0
99 OF 144 82 OF 123
3
2
1
1
2
3
2
1
3
2
1
3
2
1
1
2
2
1
1 2
1 2
1 2
2
1
2
1
1 2
AK
1 2
1
2
1
2
1
2
1
2
3
2
1
1
2
1
2
1
2
A K
1
2
2
1
1
2
1
2
1
2
2
1
2
1
K A
1
2
1 2
2
1
2
1
1
2
1
2
1 2
2
1
1
2
1
2
2
1
3
2
1
1
2
3
2
1
1 2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
4
3
1
2
5
2
1
4
3
1
2
5
1
2
1 2
1
2
1
2
1 2
2
1
3 2 1
5
4
1 2
1 2
21
1
2
21
1
2
3 2
5 6
10
13
9
12
1
7
11 4
8
14
3 2
5 6
10
13
9
12
1
7
11 4
8
14
1
2
4
32
1
4
32
1 21
4
32
1
3
2
1
2
1
2
1
2
1
21
3
2
1
3
2
1
3
2
1
3
2
1
1
2
1
2
1
2
1 2
1 2
1 2
2
1
1
2
1
2
1
2
1
2
1 2
1 2
2
1
1
2
1 2
1
2
1 2
1
2
1
2
1 2
4
3
5 6
8
7
2
1
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
114
114
114
114
80 81 82
114
117
80 81 82
114
80
117
119
119
81 82
114
80 82
114
117
114
80 81 82
114
119
80 82
114
117
117
80 82
114
122
80 82
114
117
80 82
117
114
80 82
114
117
119
81 82 114
81
114
119
81 82 114
80 82
114
6
117
117
117
81 82
114
81
119
6
122
80 81 82
114
117
80 82
114
80 81 82
114
81 82
114
117
80 82
114
80
117
117
117
81
119
81 119
81
114
119 119
80 81 82
117
119
81 82
114
81
114
80
117
117
80 82
117
80 82
117
80 82 117
117
80 82
117
80 81 82
117
80 81
118
80 82
114
117
114
119
81 119
81
114
81 82
114
81
114
117
114
122
81 82
114
119
81 82
114
81 82
114
81 82
114
81 82
114
122
122
122
80 82
117
81 82
114
81 82
114
81 82
114
81 82
114
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PCI_EXPRESS
SYM 1 OF 14
PEX_TX13
PEX_RX12
PEX_TX12*
PEX_RX4 PEX_RX4*
PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ
PEX_TX14 PEX_TX14*
PEX_RX14 PEX_RX14*
PEX_TX15 PEX_TX15*
PEX_RX15 PEX_RX15*
PEX_TX12
PEX_RX12*
PEX_TX13*
PEX_RX13 PEX_RX13*
PEX_TX10 PEX_TX10*
PEX_RX10 PEX_RX10*
PEX_TX11 PEX_TX11*
PEX_RX11 PEX_RX11*
PEX_RX9*
PEX_TX8*
PEX_RX8*
PEX_TX9*
PEX_RX9
PEX_TX9
PEX_TX8
PEX_RX8
PEX_RX7*
PEX_RX5*
PEX_TX6*
PEX_RX6*
PEX_TX7*
PEX_TX7
PEX_RX7
PEX_TX6
PEX_RX6
PEX_RX3*
PEX_TX5*
PEX_TX4*
PEX_TX5
PEX_RX5
PEX_TX4
PEX_RX3
TESTMODE
PEX_PLLVDD
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT*
PEX_SVDD_3V3
PEX_IOVDDQ
PEX_PLL_HVDD
PEX_IOVDDQ
PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD PEX_IOVDD
PEX_IOVDD
PEX_WAKE*
PEX_RST*
PEX_CLKREQ*
PEX_REFCLK*
PEX_REFCLK
PEX_TX0*
PEX_TX0
PEX_RX0*
PEX_RX0
PEX_TX1*
PEX_TX1
PEX_RX1*
PEX_RX1
PEX_TX2 PEX_TX2*
PEX_RX2
PEX_TX3
PEX_RX2*
PEX_TX3*
PEX_TERMP
PEX_IOVDD
PEX_IOVDD
NC
IN
OUT
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
UNDER GPU
Signal aliases required by this page:
(NONE)
(NONE)
BOM options provided by this page:
Page Notes
Power aliases required by this page:
- =PP1V05_S0_GPU_PEX_IOVDD
- =PP3V3_SO_GPU
- =PP1V05_S0_GPU_PEX_PLLVDD
GPU PEX_PLLVDD 150MA
PLACE NEAR GPU
ESR = 0.31OHM
PLACE NEAR GPU
UNDER GPU
NEAR GPU
GPU PEX_IOVDD/Q 3300MA
NEAR GPU
GPU PLL_HVDD/PEX_SVVD 210MA
PLACE UNDER GPU
Place near GPU
ALL LANES ARE REVERSED AND LANES 10,8,7,6,5,3,2,1 ARE POLARITY SWAPPED
ALL LANES ARE REVERSED AND LANES 15,14,13,11,10,8,7,6,5,2,0 ARE POLARITY SWAPPED
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
X5R 0201
0.22UF
20% 6.3V
GND_VOID=TRUE
CA020
10
102
20%
GND_VOID=TRUE
CA021
0.22UF
0201X5R6.3V
CA022
0.22UF
20% 0201X5R6.3V
GND_VOID=TRUE
CA023
20%
0.22UF
0201X5R6.3V
GND_VOID=TRUE
GND_VOID=TRUE
20%
0.22UF
X5R6.3V
CA024
0201
6.3V
GND_VOID=TRUE
CA025
20%
0.22UF
0201X5R
6.3V
0.22UF
GND_VOID=TRUE
20% X5R
CA026
0201
20%
0.22UF
X5R6.3V
CA027
0201
GND_VOID=TRUE
20%
0.22UF
0201X5R6.3V
GND_VOID=TRUE
CA028
020120%
0.22UF
X5R6.3V
GND_VOID=TRUE
CA029
6.3V 020120%
0.22UF
X5R
GND_VOID=TRUE
CA030
10
102
0.22UF
6.3V20% 0201X5R
GND_VOID=TRUE
CA031
020120%
0.22UF
X5R6.3V
GND_VOID=TRUE
CA032
20% 0201
0.22UF
X5R6.3V
GND_VOID=TRUE
CA033
0.22UF
GND_VOID=TRUE
20% X5R6.3V
CA034
0201
GND_VOID=TRUE
0.22UF
20% 0201X5R6.3V
CA035
6.3V X5R
0.22UF
20% 0201
GND_VOID=TRUE
CA056
20% 6.3V X5R
0.22UF
0201
CA057
GND_VOID=TRUE
6.3V
0.22UF
X5R 020120%
CA058
GND_VOID=TRUE
CA059
GND_VOID=TRUE
0.22UF
6.3V X5R 020120%
X5R
CA060
6.3V 0201
0.22UF
20%
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
6.3V 020120% X5R
CA061
CA063
0.22UF
GND_VOID=TRUE
X5R 02016.3V20%
20% X5R
GND_VOID=TRUE
6.3V 0201
0.22UF
CA064
GND_VOID=TRUE
X5R 020120%
CA065
6.3V
0.22UF
CA066
6.3V X5R 0201
GND_VOID=TRUE
20%
0.22UF
X5R 020120%
CA068
GND_VOID=TRUE
0.22UF
6.3V
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
CA069
20%
CA070
6.3V X5R
0.22UF
GND_VOID=TRUE
020120%
GND_VOID=TRUE
6.3V 0201
0.22UF
CA062
X5R20%
6.3V X5R 020120%
0.22UF
GND_VOID=TRUE
CA067
CA055
6.3V X5R20% 0201
GND_VOID=TRUE
0.22UF
CA039
0.22UF
6.3V X5R 020120%
GND_VOID=TRUE
CA036
0.22UF
GND_VOID=TRUE
6.3V X5R 020120%
CA037
0.22UF
GND_VOID=TRUE
6.3V X5R 020120%
GND_VOID=TRUE
0.22UF
6.3V X5R 020120%
CA038
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA040
CA041
6.3V X5R 020120%
GND_VOID=TRUE
0.22UF
10
102
10
102
10
102
10
102
10
102
10
102
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA043
GND_VOID=TRUE
6.3V X5R 020120%
CA042
0.22UF
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA045
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA044
6.3V
GND_VOID=TRUE
X5R 0201
0.22UF
20%
CA046
6.3V
GND_VOID=TRUE
X5R 0201
0.22UF
20%
CA048
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA047
0201
GND_VOID=TRUE
X5R
0.22UF
6.3V20%
CA050
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA049
X5R6.3V 0201
0.22UF
20%
GND_VOID=TRUE
CA051
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA071
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA073
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA072
6.3V
GND_VOID=TRUE
X5R 0201
0.22UF
20%
CA076
GND_VOID=TRUE
6.3V X5R 020120%
0.22UF
CA075
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA074
0.22UF
X5R
GND_VOID=TRUE
6.3V 020120%
CA078
X5R6.3V
GND_VOID=TRUE
0201
0.22UF
20%
CA077
6.3V X5R 020120%
0.22UF
GND_VOID=TRUE
CA080
6.3V X5R 0201
0.22UF
20%
GND_VOID=TRUE
CA079
GND_VOID=TRUE
0201
0.22UF
20% 6.3V X5R
CA082
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA081
GND_VOID=TRUE
6.3V 0201
0.22UF
20% X5R
CA083
GND_VOID=TRUE
6.3V X5R 020120%
0.22UF
CA085
6.3V X5R 020120%
GND_VOID=TRUE
0.22UF
CA084
GND_VOID=TRUE
6.3V X5R 0201
0.22UF
20%
CA086
GK104
UA000
OMIT_TABLE
BGA
GPU
26 91
118
15 18
120
18
102
18
102
NOSTUFF
RA002
200
MF 2011%1/20W
RA005
201
1%
2.49K
1/20W
MF
PLACE_NEAR=UA000.BJ38:5MM
0201
X6S
6.3V
CA089
0.1UF
10%
PLACE_NEAR=UA000.AW26:3.8MM
X6S
6.3V
CA095
0.1UF
10%
0201
PLACE_NEAR=UA000.AW32:3.8MM
0201
CA094
10%
0.1UF
6.3V X6S
PLACE_NEAR=UA000.AW30:3.8MM
10
102
10
102
0402
X6S
10UF
20% 4V
CA007
0402
X6S
CA006
10UF
20% 4V
X6S-CERM
4V
20%
CA005
22UF
0603
X6S-CERM 0603
22UF
20% 4V
CA004
0402
X6S
4V
20%
10UF
CA014
10UF
20% 4V
CA013
X6S 0402
X6S-CERM
CA011
22UF
20% 4V
0603
X6S-CERM
CA012
20%
22UF
4V
0603
10
102
RA006
MF-LF
1/16W
5%
10K
402
10
102
1UF
CA001
0402
X7R
6.3V
10%
PLACE_NEAR=UA000.AW33:3.8MM
1UF
CA002
0402
X7R
6.3V
10%
PLACE_NEAR=UA000.AY32:3.8MM
1UF
CA008
0402
X7R
6.3V
10%
PLACE_NEAR=UA000.AY24:3.8MM
1UF
CA009
0402
X7R
6.3V
10%
PLACE_NEAR=UA000.AY26:3.8MM
CA088
0402
X7R
6.3V
10%
1UF
PLACE_NEAR=UA000.AW26:20MM
4.7UF
0402
X6S
6.3V
20%
CA003
PLACE_NEAR=UA000.AY33:20MM
CA010
20%
6.3V X6S 0402
4.7UF
PLACE_NEAR=UA000.AY26:20MM
CA092
4.7UF
6.3V
20%
0402
X6S
PLACE_NEAR=UA000.AW30:20MM
0402
X6S
6.3V
20%
4.7UF
CA093
PLACE_NEAR=UA000.AW32:20MM
10
102
CA087
20%
6.3V X6S 0402
4.7UF
PLACE_NEAR=UA000.AW26:20MM
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
10
102
SYNC_DATE=04/09/2012
SYNC_MASTER=D8_YAN
KEPLER PCI-E
PEG_D2R_C_P<5>
PEG_D2R_C_N<6>
PEG_D2R_C_N<7>
PEG_D2R_C_N<5>
PEG_R2D_C_P<0>
PEG_R2D_C_N<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<4>
PEG_R2D_C_P<2>
PEG_R2D_N<8>
=PP1V05_S0_GPU_PEX_PLLVDD
=PP3V3_S0_GPU
=PP1V05_S0_GPU_PEX_IOVDD
PEG_R2D_C_P<2>
PEG_D2R_N<13>
PEG_R2D_N<9>
PEG_D2R_C_N<0>
PEX_TSTCLK_O_NG
PEG_D2R_P<2>
PEG_R2D_N<14>
PEG_R2D_P<15>
PEG_R2D_N<1>
PEG_R2D_C_N<6>
PEG_D2R_N<7>
PEG_D2R_C_P<0>
PEG_D2R_C_N<2>
PEG_D2R_C_P<3>
PEG_D2R_P<1>
PEG_D2R_N<1>
PEG_CLKREQ_L
PEG_D2R_P<1>
PEG_D2R_P<9>
PEG_R2D_C_P<9>
PEX_TSTCLK_O_PL
PEG_CLK100M_P PEG_CLK100M_N
PEG_D2R_N<0>
PEG_R2D_C_P<10>
PEG_D2R_P<10>
PEG_D2R_C_P<4>
PEG_D2R_P<10>
PEG_D2R_P<13> PEG_D2R_N<13>
PEG_R2D_N<15>
PEG_D2R_P<7>
PEG_R2D_C_P<7>
PEG_D2R_P<8> PEG_D2R_N<8>
PEG_R2D_C_N<8>
PEG_D2R_C_N<3>
PEG_D2R_N<4>
PEG_D2R_N<7>
PEG_D2R_P<14>
PEG_R2D_C_N<13>
PEG_R2D_C_P<8>
PEG_R2D_C_N<8>
PEG_R2D_C_P<9>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_N<11>
PEG_R2D_C_P<12>
PEG_R2D_C_N<12>
PEG_R2D_C_P<13>
PEG_R2D_C_N<13>
PEG_R2D_C_P<15>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_D2R_C_P<8>
PEG_D2R_C_N<8>
PEG_D2R_P<7>
PEG_D2R_C_N<9>
PEG_D2R_P<6>
PEG_D2R_C_P<9>
PEG_D2R_N<6>
PEG_D2R_C_P<10>
PEG_D2R_C_N<10>
PEG_D2R_P<5>
PEG_R2D_P<1>
PEG_R2D_P<0>
PEG_R2D_N<0>
PEG_D2R_C_P<11>
PEG_D2R_P<4>
PEG_D2R_C_P<12>
PEG_D2R_P<3>
PEG_D2R_C_P<13>
PEG_D2R_N<2>
PEG_D2R_C_N<12>
PEG_D2R_C_P<14>
PEG_D2R_C_N<13>
PEG_D2R_C_N<14>
PEG_D2R_C_P<15>
PEG_D2R_C_N<15>
PEG_D2R_P<0>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_D2R_C_N<1>
PEG_D2R_P<9>
PEG_D2R_P<8>
PEG_D2R_C_N<4>
PEG_R2D_C_P<6>
PEG_D2R_N<3>
PEG_R2D_C_N<6>
PEG_R2D_C_P<14>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_P<3>
PEG_D2R_N<2>
PEG_R2D_C_N<1>
PEG_R2D_C_P<0>
PEG_R2D_C_N<0>
GPU_TESTMODE
PEG_R2D_C_P<3>
PEG_D2R_P<5>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_R2D_C_P<6>
PEG_D2R_P<6>
PEG_D2R_N<6>
PEG_R2D_C_N<5>
PEG_R2D_C_N<7>
PEG_R2D_C_P<8>
PEG_D2R_N<9>
PEG_R2D_C_N<9>
PEG_R2D_C_N<11>
PEG_R2D_C_P<11>
PEG_D2R_N<11>
PEG_D2R_P<11>
PEG_R2D_C_N<10>
PEG_D2R_N<10>
PEG_R2D_C_P<13>
PEG_R2D_C_N<12>
PEG_D2R_P<12>
PEG_R2D_C_N<15>
PEG_R2D_C_P<15>
PEG_D2R_N<15>
PEG_D2R_P<15>
PEG_R2D_C_N<14>
PEG_R2D_C_P<14>
PEG_D2R_N<14>
PEG_D2R_N<12>
PEG_R2D_C_P<12>
PEG_D2R_N<5>
PEG_R2D_C_N<2>
PEG_D2R_P<0>
PEG_R2D_C_P<1>
PEG_D2R_N<0>
PEG_D2R_N<10>
PEG_D2R_N<1>
PEG_D2R_C_N<11>
PEG_R2D_C_P<7>
PEG_R2D_C_N<7>
PEG_D2R_C_P<1>
PEG_D2R_C_P<2>
PEG_D2R_P<11>
PEG_D2R_C_P<7>
PEG_D2R_N<11>
PEG_D2R_C_P<6>
PEG_D2R_P<2>
PEG_D2R_P<13>
PEG_R2D_C_P<4> PEG_R2D_C_N<4>
PEG_R2D_C_P<5>
PEG_R2D_C_N<3>
PEG_D2R_N<3>
PEG_R2D_P<12>
PEG_R2D_C_N<5>
PEG_R2D_N<7>
PEG_R2D_P<7>
PEG_R2D_N<6>
PEG_R2D_P<6>
PEG_R2D_N<5>
PEG_R2D_P<5>
PEG_R2D_P<4>
PEG_R2D_N<4>
PEG_R2D_N<3>
PEG_R2D_P<3>
PEG_R2D_N<2>
PEG_R2D_P<2>
PEG_R2D_P<10>
GPU_RESET_L
GPU_PEX_TERMP
PEG_R2D_P<13>
PEG_R2D_C_P<3>
PEG_R2D_C_P<5>
PEG_D2R_P<4>
PEG_R2D_C_N<2>
PEG_R2D_C_N<1>
PEG_R2D_P<14>
PEG_R2D_N<13>
PEG_R2D_N<12>
PEG_R2D_P<11>
PEG_R2D_N<11>
PEG_R2D_N<10>
PEG_R2D_P<9>
PEG_D2R_P<12>
PEG_D2R_N<12>
PEG_D2R_P<14>
PEG_D2R_N<14>
PEG_R2D_P<8>
PEG_D2R_P<15>
PEG_D2R_N<15>
prefsb
051-9505
8.0.0
100 OF 144
83 OF 123
21
21
21
21
21
21
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21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
BE34
BH33
BD33
BG26 BH26
AY24 AY26 AY27 AY29 AY30 BA24
BD35 BC35
BJ35 BJ36
BC36 BD36
BH36 BG36
BC33
BG33
BE35
BG35 BH35
BE31 BE32
BG32 BH32
BD32 BC32
BJ32 BJ33
BG30
BC29
BJ30
BD30
BH30
BC30
BD29
BJ29
BH29
BJ27
BD27
BG27
BE29
BE28
BG29
BC27
BH27
BG24
BC26
BE25
BD26
BJ26
BE26
BH24
BA23
AW26
BH38 BG38
AW32
BB30
AW30
BB27
BA26 BA27 BA29 BA30 BA32 BB24
BA35
BA33
AW33 AY32
AY35
BJ21
BE20
BB20
BC20
BD20
BD21
BC21
BG21
BH21
BE23
BE22
BH23
BG23
BD23 BC23
BJ23
BC24
BJ24
BD24
BJ38
BB33
AY33
1 2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
83
102
83
102
83
102
83
102
83
102
6
95
6
91 92 95 96
6
83
102
83
102
112
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
112
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
112
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
112
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
83
102
IN
D
GS
OUT
FBA
SYM 2 OF 14
FB_REFPLL_DLL_AVDD0 FB_REFPLL_DLL_AVDD1
FBA_DQS_RN7
FBA_DQS_RN6
FBA_DQS_RN5
FBA_DQS_RN4
FBA_DQS_RN3
FBA_DQS_RN1 FBA_DQS_RN2
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_WP6
FBA_DQS_WP5
FBA_DQS_WP4
FBA_DQS_WP2 FBA_DQS_WP3
FBA_DQS_WP0 FBA_DQS_WP1
FBA_DQM6 FBA_DQM7
FBA_DQM5
FBA_DQM3 FBA_DQM4
FBA_DQM2
FBA_DQM1
FBA_DQM0
FBA_D63
FBA_D62
FBA_D61
FBA_D60
FBA_D59
FBA_D58
FBA_D57
FBA_D56
FBA_D55
FBA_D54
FBA_D52 FBA_D53
FBA_D51
FBA_D49 FBA_D50
FBA_D48
FBA_D47
FBA_D46
FBA_D44 FBA_D45
FBA_D43
FBA_D42
FBA_D41
FBA_D39 FBA_D40
FBA_D37 FBA_D38
FBA_D36
FBA_D35
FBA_D34
FBA_D31 FBA_D32 FBA_D33
FBA_D30
FBA_D29
FBA_D26
FBA_D28
FBA_D27
FBA_D24 FBA_D25
FBA_D21
FBA_D23
FBA_D22
FBA_D19 FBA_D20
FBA_D18
FBA_D16 FBA_D17
FBA_D14 FBA_D15
FBA_D13
FBA_D12
FBA_D11
FBA_D10
FBA_D8 FBA_D9
FBA_D7
FBA_D6
FBA_D5
FBA_PLL_AVDD
FBA_WCKB67*
FBA_WCKB67
FBA_WCKB45*
FBA_WCK67*
FBA_WCK67
FBA_WCKB45
FBA_WCK45*
FBA_WCK45
FBA_WCKB23*
FBA_WCKB23
FBA_WCKB01*
FBA_WCK23*
FBA_WCK23
FBA_WCK01*
FBA_WCKB01
FBA_WCK01
FBA_CLK1*
FBA_CLK1
FBA_CLK0*
FBA_CLK0
FBA_DEBUG0 FBA_DEBUG1
FBA_CMD33
FBA_CMD32
FBA_CMD31
FBA_CMD29 FBA_CMD30
FBA_CMD28
FBA_CMD24
FBA_CMD21
FBA_CMD23
FBA_CMD20
FBA_CMD18
FBA_CMD16 FBA_CMD17
FBA_CMD14
FBA_CMD13
FBA_CMD15
FBA_CMD11 FBA_CMD12
FBA_CMD10
FBA_D3 FBA_D4
FBA_D1
FBA_CMD9
FBA_CMD8
FBA_CMD6
FBA_CMD5
FBA_CMD3 FBA_CMD4
FBA_CMD1 FBA_CMD2
FBA_CMD0
FBA_CMD27
FBA_CMD26
FBA_CMD25
FBA_CMD22
FBA_CMD19
FBA_D2
FBA_D0
FBA_CMD7
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI BI BI BI BI BI BI
IN IN IN IN IN IN IN IN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
NC NC
OUT OUT
OUT OUT
OUT OUT
OUT OUT
NC
NC
NC
NC
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
NC
NC
NC NC
NC
NC
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
SYM 3 OF 14
FBB
FBB_D6
FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18
FBB_CMD21
FBB_D3
FBB_D2
FBB_D1
FBB_D0
FBB_CMD0
FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8
FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13
FBB_CMD19 FBB_CMD20
FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29
FBB_CMD33
FBB_D4 FBB_D5
FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63
FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7
FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7
FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7
FBB_WCK01
FBB_WCK01*
FBB_WCK23
FBB_WCK45
FBB_WCK45*
FBB_WCK67
FBB_WCK67*
FBB_WCKB01*
FBB_WCKB45
FBB_WCKB45*
FBB_WCKB67
FBB_WCKB67*
FBB_CMD2
FBB_CMD1
FBB_PLL_AVDD
FBB_WCKB23*
FBB_WCKB23
FBB_WCK23*
FBB_WCKB01
FBB_DEBUG1
FBB_CLK1*
FBB_CLK1
FBB_CLK0*
FBB_CLK0
FBB_DEBUG0
FBB_CMD32
FBB_CMD30 FBB_CMD31
BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI
IN
IN
IN IN IN IN IN IN
OUT OUT
OUT OUT
NC
NC
NC
NC
OUT
OUT
OUT
OUT
NC NC
NC NC
NC NC NC NC NC NC NC NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
D
GS
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEM VREFB SWITCH
MEM VREFA SWITCH
- =PP1V35_S0_GPU_FVDDQ
(NONE)
BOM options provided by this page:
- PP1V05_S0_GPU_PLLVDD_FLT
- PP3V3_S0_GPU_FB_PLL_AVDD_FLT
Page Notes
(NONE)
Signal aliases required by this page:
Power aliases required by this page:
1/20W
10K
1%
MF 201
RA155
201
MF
1/20W
1%
10K
RA157
10K
MF
1% 1/20W
RA154
201
1/20W MF
10K
1%
RA156
201
84 85 91 118
QA101
SSM3K15AMFVAPE
CRITICAL
VESM
UA000
BGA
GPU
GK104
OMIT_TABLE
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
10%
6.3V X6S 0201
0.1UF
CA116
PLACE_NEAR=UA000.L21:30MM
86
112
84 86
112
84 86
112
86
112
86
112
86
112
86
113
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
84 86
112
84 86
112
86
112
86
112
86
112
86
113
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
86
112
X6S
CA107
0.1UF
10%
6.3V
0201
PLACE_NEAR=UA000.AJ39:3.8MM
1/20W
RA107
NOSTUFF
MF
1%
60.4
201
RA106
1/20W MF
1%
60.4
NOSTUFF
201
87
112
84 87
112
84 87
112
87
112
87
112
87
112
87
113
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
84 87
112
84 87
112
87
112
87
112
87
112
87
113
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
RA109
MF
1/20W
1%
60.4
NOSTUFF
201
RA108
MF
60.4
NOSTUFF
201
1% 1/20W
87
112
87
112
87
112
87
112
0.1UF
10%
CA111
6.3V X6S 0201
PLACE_NEAR=UA000.L36:3.8MM
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
GK104
GPU
BGA
UA000
OMIT_TABLE
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
87
112
86
112
86
112
86
112
86
112
87
112
87
112
87
112
87
112
10%
0.1UF
6.3V X6S 0201
CA117
PLACE_NEAR=UA000.AC39:30MM
84 85 91 118
SSM3K15AMFVAPE
VESM
QA100
CRITICAL
86
118
10K
RA151
1% 1/20W MF 201
201
RA153
10K
1% 1/20W MF
RA150
MF
1/20W
1%
10K
201
201
MF
RA152
10K
1/20W
1%
KEPLER FRAME BUFFER A/B
SYNC_DATE=04/09/2012
SYNC_MASTER=D8_YAN
FB_A1_RESET_L
FB_B1_WCLK_P<1>
FB_B1_DQ<11>
FB_B1_DQ<10>
FB_B1_DQ<3>
FB_B0_WCLK_P<0>
PP3V3_S0_GPU_FB_PLL_AVDD_FLT
FB_A1_WCLK_N<0>
FB_A1_WCLK_P<0>
FB_B1_EDC<1>
FB_A1_A<2> FB_A1_A<3>
FB_A1_CS_L
FB_B1_A<2>
FB_B0_A<12>
FB_A1_DQ<8>
FB_A1_CKE_L
FB_A0_CKE_L
FB_A1_A<0>
FB_SW_LEG_A
FB_A1_DQ<30>
FB_A1_EDC<1>
FB_A0_EDC<3> FB_A1_EDC<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<3>
FB_A1_EDC<3>
FB_B1_DQ<22>
FB_B0_WCLK_N<0>
FB_A0_EDC<0>
FB_A0_WCLK_N<0>
FB_A0_WCLK_P<0>
FB_A0_DQ<18>
FB_A0_DQ<12>
FB_A1_CLK_P
FB_A1_CLK_N
FB_A0_DQ<30>
FB_A0_DQ<22>
FB_A0_A<3>
FB_A1_CAS_L
FB_A1_DQ<22>
FB_A1_DBI_L<3>
FB_B0_DQ<24>
FB_B0_DQ<23>
FB_B1_A<0>
FB_A0_WE_L
FB_A0_A<7>
FB_A0_RESET_L
FB_B0_WE_L
FB_A0_A<12>
FB_A0_ABI_L FB_A0_A<6>
FB_A0_A<5>
FB_A0_A<4>
FB_A1_A<7>
FB_A0_DQ<16>
FB_A1_ABI_L
FB_A0_DQ<11>
FB_A0_DQ<10>
FB_A0_DQ<9>
FB_A0_CAS_L
FB_B1_DQ<28>
FB_B1_DQ<20>
FB_B0_WCLK_P<1>
FB_B1_DQ<31>
FB_A0_WCLK_P<1>
FB_A1_WCLK_N<1>
FB_A1_WCLK_P<1>
FB_A0_WCLK_N<1>
FB_B1_DQ<26>
FB_B1_DQ<17>
GPU_FBA_DEBUG0
FB_B1_A<3>
FB_B1_CS_L
FB_B0_EDC<3>
FB_A0_DQ<27>
FB_A0_DQ<28>
FB_A1_DQ<5>
FB_B1_DQ<1>
FB_B0_DQ<29>
FB_B1_DQ<6>
FB_A0_DQ<29>
FB_A1_DBI_L<2>
FB_A1_DBI_L<0>
FB_A0_DBI_L<2>
FB_A0_DBI_L<1>
FB_A0_DBI_L<0>
FB_A1_DQ<31>
FB_A1_DQ<28>
FB_A1_DQ<27>
FB_A1_DQ<26>
FB_A1_DQ<24>
FB_A1_DQ<20>
FB_A0_DQ<20>
FB_A0_DQ<19>
FB_A0_DQ<23>
FB_A0_DQ<21>
FB_A1_DQ<1>
FB_A1_DQ<0>
FB_A0_DQ<31>
FB_A1_DQ<3>
FB_A1_DQ<6>
FB_A1_DQ<7>
FB_A1_DQ<9>
FB_A1_DQ<10>
FB_A1_DQ<11>
FB_A1_DQ<13>
FB_A1_DQ<14> FB_A1_DQ<15>
FB_A1_DQ<18>
FB_A1_DQ<17>
FB_A1_DQ<19>
FB_A0_DQ<0>
FB_A0_DQ<1>
FB_A0_DQ<4> FB_A0_DQ<5>
FB_A0_DQ<6>
FB_A0_DQ<7>
FB_A0_CKE_L
FB_A0_CS_L
FB_A1_A<6>
=PP1V35_S0_GPU_FBVDDQ
GPU_FBB_DEBUG0
FB_B1_CLK_P
FB_B1_CLK_N
FB_B0_CKE_L
FB_B0_RESET_L
FB_B1_EDC<3>
FB_B0_EDC<1>
FB_B0_EDC<0>
FB_B1_DBI_L<2>
FB_B0_DBI_L<3>
FB_B0_DBI_L<2>
FB_B0_DBI_L<1>
FB_B0_DBI_L<0>
FB_B1_DQ<30>
FB_B1_DQ<29>
FB_B1_DQ<25>
FB_B1_DQ<24>
FB_B1_DQ<23>
FB_B1_DQ<21>
FB_B1_DQ<19>
FB_B1_DQ<18>
FB_B1_DQ<16>
FB_B1_DQ<15>
FB_B1_DQ<14>
FB_B1_DQ<13>
FB_B1_DQ<12>
FB_B1_DQ<9>
FB_B1_DQ<8>
FB_B1_DQ<7>
FB_B1_DQ<5>
FB_B1_DQ<4>
FB_B1_DQ<0>
FB_B0_DQ<31>
FB_B0_DQ<30>
FB_B0_DQ<28>
FB_B0_DQ<27>
FB_B0_DQ<26>
FB_B0_DQ<25>
FB_B0_DQ<22>
FB_B0_DQ<18>
FB_B0_DQ<17>
FB_B0_DQ<16>
FB_B0_DQ<8>
FB_B0_DQ<7>
FB_B1_A<4>
FB_B1_A<5>
FB_B1_WE_L
FB_B1_A<7>
FB_B1_A<6>
FB_B1_ABI_L
FB_B1_A<12>
FB_B1_RAS_L
FB_B0_A<2>
FB_B0_A<4>
FB_B0_A<0>
FB_B0_CAS_L
FB_B0_DQ<2>
FB_B1_RESET_L
FB_B1_CKE_L
FB_B1_CAS_L
FB_B0_DQ<6>
FB_A0_DQ<26>
FB_A1_DQ<21>
FB_A1_DQ<23>
FB_A1_DQ<25>
FB_A1_DQ<29>
FB_B0_DQ<13>
FB_B1_A<1>
FB_A0_DQ<2> FB_A0_DQ<3>
FB_B0_DQ<5>
FB_B0_DQ<0>
FB_B0_DQ<1>
FB_B0_DQ<3>
FB_B0_DQ<4>
FB_A0_DQ<15>
FB_A0_RESET_L
FB_B0_ABI_L
FB_B0_A<1>
FB_B0_RAS_LFB_A0_RAS_L
FB_A0_A<1> FB_A0_A<0>
FB_B0_DQ<15>
FB_A0_DQ<13> FB_A0_DQ<14>
FB_B0_DQ<19>
FB_B0_A<3>
FB_B0_DQ<11>
FB_A1_DQ<4>
FB_A1_DQ<12>
FB_A1_A<12>
FB_A0_DBI_L<3>
FB_B1_DBI_L<0>
FB_B1_WCLK_P<0>
FB_B0_EDC<2>
FB_B1_EDC<0>
FB_B1_DQ<27>
FB_A1_DBI_L<1>
FB_A0_CLK_N
FB_A1_DQ<16>
FB_A0_CLK_P
FB_A1_EDC<2> FB_B1_EDC<2>
PP3V3_S0_GPU_FB_PLL_AVDD_FLT
FB_A1_DQ<2>
=PP1V35_S0_GPU_FBVDDQ
FB_A1_WE_L FB_A1_A<5>
FB_A1_A<4>
GPU_FBB_DEBUG1
FB_A0_DQ<8>
FB_A0_DQ<25>
FB_A0_DQ<24>
GPU_FBA_DEBUG1
FB_B0_CLK_P
FB_B0_CLK_N
FB_B0_DQ<20>
FB_B1_DQ<2>
FB_B0_DQ<21>
=PP1V35_S0_GPU_FBVDDQ
FB_B1_RESET_L
=PP1V35_S0_GPU_FBVDDQ
FB_B1_CKE_LFB_B0_CKE_L
GPU_ALT_VREF
GPU_ALT_VREF
FB_SW_LEG_B
FB_B0_WCLK_N<1>
FB_A0_EDC<2>
FB_A0_EDC<1>
FB_B0_RESET_L
FB_B1_WCLK_N<1>
FB_B0_DQ<10>
FB_B0_DQ<9>
FB_A0_A<2>
=PP1V35_S0_GPU_FBVDDQ
FB_B0_A<5>
FB_B0_A<6>
FB_B0_DQ<12>
FB_B0_DQ<14>
FB_A1_RAS_L
FB_A1_A<1>
FB_B0_CS_L
FB_B0_A<7>
FB_A0_DQ<17>
=PP1V35_S0_GPU_FBVDDQ
FB_A1_RESET_L
FB_A1_CKE_L
FB_B1_WCLK_N<0>
PP1V05_S0_GPU_PLLVDD_FLT
prefsb
051-9505
8.0.0
101 OF 144
84 OF 123
1
2
1
2
1
2
1
2
1
2
3
AC39
L21
AK46
AJ41
AN44
AV46
AC43
Y44
AF43
AK47
U46
AJ42
AN43
AV47
AF42 AC44
U45 Y43
AG42 AM46
AR45
AA41 AV45
AG44
AC45
U40
AM43
AK44
AM44
AM45
AK49
AK48
AK43
AK45
AK41
AK42
AJ40 AK40
AJ43
AG43 AG41
AG40
AN42
AN41
AT45 AR44
AR48
AR49
AN45
AW46 AR46
AW48 BA47
AW47
AT47
AT49
AA40 AT48 AT46
AA42
AA43
AD42
AA44
AC42
AD44 AD43
AF45
AD45
AD46
AG45 AF44
AG46
AJ46 AG47
Y45 Y48
Y49
Y46
AA47
AA45
AA46 AC46
U42
U41
U44
AJ39
AN46
AN47
AR42
AM41
AM42
AR43
AT43
AT44
AC40
AC41
Y41
AD40
AD41
V45
Y42
V46
AJ45
AJ44
AF40
AF41
Y47 AR47
AF46
AF49
AG49
AJ48 AG48
AJ49
AM47
AV49
AN49
AV48
BA49
BB49 BA48
AF47
AD47
AF48
AD49 AD48
AC47
V42 U43
V41
AC49
AC48
AA49
V47
V48 V49
U48 U49
U47
AJ47
AM48
AM49
AN48
AW49
V44
V43
AA48
2
1
2
1
1
2
1
2
1
2
1
2
2
1
J29
B36 B38 D49 C48 B46
C44
F30
E30
G30
D30 C29
A30 B30 B32 A32 C32 A33 B33 B35 A35 C35 A36
A46 A45
A44 B44 C42 B42 A42 A41 B41 C39
C38
G29 F29
H29 C33 E33 F33 D33 C30 K33 E32 D32 H39 G39 F39 D41 F38 G38 D38 E38 F36 K35 E36 D36 G35 F35 D35 E35 M44 P42 M43 P43 R45 R46 R43 R44 M47 P44 M46 M45 P47 P49 P45 P46 F46 E47 D47 D48 F48 H46 H47 H48 L45 L44 J46 H49 L47 J49 L48 L49
E29 G33 H38 C36 P41 P48 F47 L46
H30 J33 E39 H35 R41 M49 E49 J48
J30 H33 D39 J35 R42 M48 F49 J47
F32 G32
G36
M42 M41
H45 H44
J32
L42 L43
J45 J44
A29
B29
L36
J36
K36
H36
H32
C41
D42
E42
F41
E41
D29
A38
B39 A39
2
1
1
2
3
1
2
1
2
1
2
1
2
84 86
112
84 85 95
84 86
112
84 86
112
84 86
112
6
84 85 86 87 88 89 94
84 85 95
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89
94
84 87
112
6
84 85
86 87
88 89 94
84 87
112
84 87 112
84 87
112
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
91 95
SYM 4 OF 14
FBC
FBC_CMD27
FBC_DQS_RN6 FBC_DQS_RN7
FBC_DQS_RN4 FBC_DQS_RN5
FBC_DQS_RN3
FBC_DQS_RN1 FBC_DQS_RN2
FBC_DQS_RN0
FBC_DQS_WP7
FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6
FBC_DQS_WP2 FBC_DQS_WP3
FBC_DQS_WP0 FBC_DQS_WP1
FBC_DQM5 FBC_DQM6 FBC_DQM7
FBC_DQM3 FBC_DQM4
FBC_DQM0 FBC_DQM1 FBC_DQM2
FBC_D62 FBC_D63
FBC_D59 FBC_D60 FBC_D61
FBC_D57 FBC_D58
FBC_D54 FBC_D55 FBC_D56
FBC_D52 FBC_D53
FBC_D49 FBC_D50 FBC_D51
FBC_D47 FBC_D48
FBC_D44 FBC_D45 FBC_D46
FBC_D42 FBC_D43
FBC_D41
FBC_D39 FBC_D40
FBC_D36 FBC_D37 FBC_D38
FBC_D34 FBC_D35
FBC_D31 FBC_D32 FBC_D33
FBC_D29 FBC_D30
FBC_D26 FBC_D27 FBC_D28
FBC_D24
FBC_D21 FBC_D22 FBC_D23
FBC_D19 FBC_D20
FBC_D18
FBC_D16 FBC_D17
FBC_D13 FBC_D14 FBC_D15
FBC_D11 FBC_D12
FBC_D8 FBC_D9 FBC_D10
FBC_D7
FBC_WCK45
FBC_WCKB01*
FBC_WCKB01
FBC_CLK0*
FBC_CMD31
FBC_CMD29 FBC_CMD30
FBC_CMD26
FBC_CMD28
FBC_CMD24 FBC_CMD25
FBC_CMD21 FBC_CMD22 FBC_CMD23
FBC_CMD19 FBC_CMD20
FBC_CMD16 FBC_CMD17
FBC_CMD13 FBC_CMD14 FBC_CMD15
FBC_CMD11 FBC_CMD12
FBC_CMD8 FBC_CMD9
FBC_CMD10
FBC_CMD7
FBC_D6
FBC_D3 FBC_D4 FBC_D5
FBC_D1 FBC_D2
FBC_D0
FBC_CMD6
FBC_CMD4
FBC_CMD3
FBC_CMD5
FBC_CMD1 FBC_CMD2
FBC_CMD0
FBC_PLL_AVDD
FBC_CMD18
FBC_WCKB67*
FBC_WCKB67
FBC_WCK67*
FBC_WCK67
FBC_WCKB45*
FBC_WCKB45
FBC_WCK45*
FBC_WCK23
FBC_WCKB23*
FBC_WCKB23
FBC_WCK23*
FBC_WCK01*
FBC_WCK01
FBC_DEBUG1
FBC_DEBUG0
FBC_CMD32 FBC_CMD33
FBC_CLK0
FBC_CLK1
FBC_CLK1*
FBC_D25
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI BI BI BI BI BI BI
IN IN IN IN IN IN IN IN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
NC NC
OUT OUT
OUT OUT
OUT OUT
NC
NC
NC
NC
SYM 5 OF 14
FBD
FBD_CMD9
FBD_DQS_RN6 FBD_DQS_RN7
FBD_DQS_RN4 FBD_DQS_RN5
FBD_DQS_RN3
FBD_DQS_RN1 FBD_DQS_RN2
FBD_DQS_RN0
FBD_DQS_WP7
FBD_DQS_WP4 FBD_DQS_WP5 FBD_DQS_WP6
FBD_DQS_WP2 FBD_DQS_WP3
FBD_DQS_WP0 FBD_DQS_WP1
FBD_DQM7
FBD_DQM6
FBD_DQM5
FBD_DQM4
FBD_DQM3
FBD_DQM2
FBD_DQM1
FBD_DQM0
FBD_D62 FBD_D63
FBD_D60
FBD_D59
FBD_D61
FBD_D57 FBD_D58
FBD_D55
FBD_D54
FBD_D56
FBD_D52 FBD_D53
FBD_D51
FBD_D50
FBD_D49
FBD_D48
FBD_D47
FBD_D46
FBD_D45
FBD_D44
FBD_D43
FBD_D42
FBD_D41
FBD_D39 FBD_D40
FBD_D38
FBD_D36 FBD_D37
FBD_D34 FBD_D35
FBD_D32
FBD_D31
FBD_D33
FBD_D29 FBD_D30
FBD_D27
FBD_D26
FBD_D28
FBD_D24 FBD_D25
FBD_D22
FBD_D21
FBD_D23
FBD_D19 FBD_D20
FBD_D18
FBD_D16 FBD_D17
FBD_D14
FBD_D13
FBD_D15
FBD_D11 FBD_D12
FBD_D10
FBD_D9
FBD_D8
FBD_D7
FBD_D6
FBD_D5
FBD_D4
FBD_D3
FBD_D2
FBD_D1
FBD_D0
FBD_CMD8
FBD_CMD7
FBD_CMD6
FBD_CMD5
FBD_CMD4
FBD_CMD3
FBD_CMD1 FBD_CMD2
FBD_CMD0
FBD_CLK1*
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD26
FBD_CMD32
FBD_DEBUG1
FBD_PLL_AVDD
FBD_WCK01 FBD_WCK01*
FBD_WCK23 FBD_WCK23*
FBD_WCK45 FBD_WCK45*
FBD_WCK67 FBD_WCK67*
FBD_WCKB01
FBD_WCKB01*
FBD_WCKB23
FBD_WCKB23*
FBD_WCKB45
FBD_WCKB45*
FBD_WCKB67
FBD_WCKB67*
FBD_CLK1
FBD_CLK0*
FBD_CLK0
FBD_DEBUG0
FBD_CMD33
FBD_CMD31
FBD_CMD30
FBD_CMD29
FBD_CMD28
FBD_CMD27
FBD_CMD25
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
OUT OUT
OUT OUT
NC NC
NC
NC
NC
NC
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI
IN IN IN IN IN IN IN IN
OUT OUT
OUT OUT
OUT OUT
NC
NC
NC
NC
OUT OUT
OUT OUT
NC NC
NC NC
OUT OUT
NC
NC
NC NC NC NC NC NC
NC
NC
NC
NC
NC
NC
NC NC
IN
D
GS
OUT
IN
D
GS
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEM VREFD SWITCH
MEM VREFC SWITCH
(NONE)
Page Notes
(NONE)
Signal aliases required by this page:
Power aliases required by this page:
BOM options provided by this page:
- =PP1V35_S0_GPU_FBVDDQ
- PP3V3_S0_GPU_FB_PLL_AVDD_FLT
201
1/20W
10K
1%
MF
RA255
201
MF
1% 1/20W
10K
RA257
201
10K
MF
1% 1/20W
RA254
201
1/20W MF
10K
1%
RA256
UA000
OMIT_TABLE
BGA
GPU
GK104
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
85 88
113
85 88
112
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
85 88
113
85 88
112
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
88
113
PLACE_NEAR=UA000.L26:3.8MM
0201
CA216
10%
0.1UF
6.3V X6S
RA207
NOSTUFF
60.4
1% 1/20W MF 201
RA206
NOSTUFF
60.4
1% 1/20W MF 201
GK104
BGA
UA000
OMIT_TABLE
GPU
89
113
85 89
113
85 89
112
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
85 89
113
85 89
112
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
RA209
NOSTUFF
60.4
1% 1/20W MF 201
RA208
NOSTUFF
60.4
1% 1/20W MF 201
89
113
89
113
PLACE_NEAR=UA000.AA11:3.8MM
CA207
0201
10%
0.1UF
6.3V X6S
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
89
113
88
113
88
113
88
113
88
113
88
113
88
113
89
113
89
113
89
113
89
113
89
113
89
113
84 85 91 118
QA201
SSM3K15AMFVAPE
CRITICAL
VESM
89
118
84 85 91 118
MF
1/20W
1%
10K
201
RA251
QA200
SSM3K15AMFVAPE
VESM
CRITICAL
RA253
1%
MF
10K
1/20W
201
RA250
10K
1% 1/20W MF 201
MF
10K
1% 1/20W
RA252
201
KEPLER FRAME BUFFER C/D
SYNC_MASTER=D8_YAN
SYNC_DATE=04/09/2012
PP3V3_S0_GPU_FB_PLL_AVDD_FLT
FB_C1_DQ<30>
FB_C0_DQ<14>
FB_C0_DQ<0>
PP3V3_S0_GPU_FB_PLL_AVDD_FLT
FB_D1_EDC<3>
FB_D1_EDC<1>
FB_C1_EDC<3>
FB_C0_DBI_L<0>
FB_C1_DQ<0>
FB_C0_DQ<25>
FB_C0_DQ<11>
FB_C0_DQ<5>
FB_C0_A<7>
FB_C1_ABI_L
FB_C1_A<6> FB_C1_A<7>
FB_C0_CKE_L
FB_C1_CAS_L
FB_C1_RESET_L
FB_C1_A<1>
FB_C1_A<0>
FB_C1_A<2> FB_C1_A<3>
FB_D1_DQ<3>
GPU_FBD_DEBUG1
GPU_FBD_DEBUG0
FB_D1_DBI_L<0>
FB_C1_WCLK_N<1>
FB_C1_WCLK_P<1>
FB_D1_DQ<8>
FB_C1_CLK_N
FB_C0_WCLK_N<1>
FB_C1_DBI_L<0>
FB_C1_EDC<0>
FB_C1_EDC<1>
FB_C1_DQ<21>
FB_C1_DQ<24>
FB_C1_DQ<28>
FB_C0_DBI_L<2>
FB_C1_DBI_L<1> FB_C1_DBI_L<2>
FB_C1_DBI_L<3>
FB_D1_DQ<19>
FB_D0_DQ<21>
FB_D0_DQ<23> FB_D0_DQ<24>
FB_D0_DQ<25>
FB_D1_DQ<2>
GPU_FBC_DEBUG1
FB_C1_DQ<4>
FB_C0_EDC<0> FB_C0_EDC<1>
FB_D1_DQ<11>
FB_C1_CKE_L
=PP1V35_S0_GPU_FBVDDQ
FB_C0_A<4>
FB_C0_CAS_L
FB_C0_RAS_L
FB_C0_A<1>
FB_C0_A<6>
FB_D1_DQ<29>
FB_D1_WCLK_N<0>
FB_D1_WCLK_P<0>
FB_D1_WCLK_P<1>
FB_D0_DBI_L<0>
FB_D1_DQ<28>
FB_D1_DQ<30>
FB_D1_DQ<31>
FB_D1_DQ<24>
FB_D0_WCLK_N<0>
FB_D0_WCLK_P<0>
FB_C1_WCLK_P<0>
FB_C0_WCLK_P<1>
FB_C0_WCLK_P<0>
FB_D0_DQ<16>
FB_D0_DQ<13>
FB_D1_A<1>
FB_D0_DQ<22>
FB_C0_A<3>
FB_D0_A<6>
FB_D0_ABI_L
FB_D0_A<7> FB_D0_WE_L
FB_D0_DQ<8>
FB_D0_DQ<9>
FB_D0_DQ<5>
FB_C0_DQ<3>
FB_C0_DQ<8>
FB_D0_DQ<10>
FB_D0_A<5>
FB_D1_A<6>
FB_D0_A<12>
FB_D0_A<0>
FB_D0_A<1>
FB_D0_RAS_L
FB_D0_RESET_L
FB_D0_CKE_L
FB_D0_CAS_L
FB_D0_DQ<18>
FB_D0_DQ<17>
FB_D0_DQ<3>
FB_D0_DQ<2>
FB_D0_DQ<1>
FB_C0_DQ<1>
FB_C0_RESET_L
FB_D0_DQ<0>
FB_D0_DQ<7>
FB_D0_DQ<6>
FB_D0_DQ<4>
FB_C1_RESET_L
FB_C0_RESET_L
FB_C1_CLK_P
FB_C0_CLK_P
GPU_FBC_DEBUG0
FB_C0_WCLK_N<0>
FB_C0_DQ<2>
FB_C0_DQ<4>
FB_C0_DQ<6>
FB_C0_CLK_N
FB_C0_DQ<7>
FB_C0_DQ<10>
FB_C0_DQ<9>
FB_C0_DQ<12>
FB_C0_DQ<15>
FB_C0_DQ<17>
FB_C0_DQ<16>
FB_C0_DQ<18>
FB_C0_DQ<20>
FB_C0_DQ<19>
FB_C0_DQ<23>
FB_C0_DQ<21>
FB_C0_DQ<24>
FB_C0_DQ<28>
FB_C0_DQ<27>
FB_C0_DQ<26>
FB_C0_DQ<30>
FB_C0_DQ<29>
FB_C0_DQ<31>
FB_C1_DQ<3>
FB_C1_DQ<2>
FB_C1_DQ<6>
FB_C1_DQ<8>
FB_C1_DQ<7>
FB_C1_DQ<9>
FB_C1_DQ<11>
FB_C1_DQ<14>
FB_C1_DQ<13>
FB_C1_DQ<12>
FB_C1_DQ<16>
FB_C1_DQ<15>
FB_C1_DQ<17>
FB_C1_DQ<20>
FB_C1_DQ<23>
FB_C1_DQ<22>
FB_C1_DQ<26>
FB_C1_DQ<25>
FB_C1_DQ<29>
FB_C1_DQ<27>
FB_C0_DBI_L<1>
FB_C0_DBI_L<3>
FB_C0_EDC<2>
FB_D1_A<7>
FB_D1_A<5>
FB_D1_A<2>
FB_D1_A<3>
FB_D1_CS_L
FB_D1_CLK_P
FB_D1_A<0>
FB_D1_RAS_L
FB_D1_RESET_L
FB_D1_CKE_L
FB_D1_CAS_L
FB_D0_CS_L
FB_D0_A<3>
FB_D0_A<2>
FB_D0_A<4>
FB_D0_DQ<11>
FB_D0_DQ<14>
FB_D0_DQ<19>
FB_D0_DQ<26> FB_D0_DQ<27>
FB_D0_DQ<30>
FB_D0_DQ<29>
FB_D0_DQ<31> FB_D1_DQ<0>
FB_D1_DQ<5>
FB_D1_DQ<4>
FB_D1_DQ<6>
FB_D1_DQ<7>
FB_D1_DQ<9>
FB_D1_DQ<10>
FB_D1_DQ<12>
FB_D1_DQ<13> FB_D1_DQ<14>
FB_D1_DQ<15>
FB_D1_DQ<16> FB_D1_DQ<17>
FB_D1_DQ<18>
FB_D1_DQ<21>
FB_D1_DQ<20>
FB_D1_DQ<22>
FB_D1_DQ<23>
FB_D1_DQ<26>
FB_D1_DQ<25>
FB_D1_DQ<27>
FB_D0_DBI_L<1> FB_D0_DBI_L<2>
FB_D1_DBI_L<1>
FB_D1_DBI_L<2> FB_D1_DBI_L<3>
FB_D0_EDC<1>
FB_D0_EDC<0>
FB_D0_EDC<3>
FB_D0_EDC<2>
FB_D1_EDC<2>
FB_D1_EDC<0>
FB_C1_DQ<19>
FB_C1_DQ<18>
FB_C0_EDC<3>
FB_C0_CKE_L
FB_C0_A<0>
FB_C0_ABI_L
FB_C0_A<12>
=PP1V35_S0_GPU_FBVDDQ
FB_C0_A<2>
FB_C1_CS_L
FB_C1_EDC<2>
FB_C1_DQ<5>
=PP1V35_S0_GPU_FBVDDQ
FB_D1_DQ<1>
=PP1V35_S0_GPU_FBVDDQ
FB_C1_DQ<31>
FB_C1_WCLK_N<0>
FB_D0_DBI_L<3>
FB_D1_WCLK_N<1>
FB_D0_DQ<12>
FB_C1_A<4>
FB_D0_DQ<20>
FB_C0_DQ<13>
FB_D0_DQ<15>
=PP1V35_S0_GPU_FBVDDQ
FB_D1_RESET_L
=PP1V35_S0_GPU_FBVDDQ
FB_D0_RESET_L
FB_D1_CKE_LFB_D0_CKE_L
GPU_ALT_VREF
FB_SW_LEG_D
GPU_ALT_VREF
FB_SW_LEG_C
FB_D0_WCLK_N<1>
FB_D0_WCLK_P<1>
FB_D0_CLK_N
FB_D0_CLK_P
FB_C0_DQ<22>
FB_D1_A<12>
FB_D1_ABI_L
FB_D1_CLK_N
FB_C1_DQ<10>
FB_C1_RAS_L
FB_C1_CKE_L
FB_C0_CS_L
FB_C0_A<5>
FB_C0_WE_L
FB_D0_DQ<28>
FB_C1_WE_L
FB_C1_A<12>
FB_C1_A<5>
FB_D1_WE_L
FB_D1_A<4>
FB_C1_DQ<1>
prefsb
051-9505
8.0.0
102 OF 144
85 OF 123
1
2
1
2
1
2
1
2
A20
G18 F21
D27 G24
D14
G11 J15
C6
G21
E27 F24 H18
H15 C14
D6
F11
E21 F17 J23
D12 K27
E6 E9
H17
H23 K23
H21 F23 G23
H20 F20
D20 E20 G20
F18 E18
C17 D17 E17
D24 D15
A24 B24 E24
D23 C23
D21
H27 E23
G27 F27 J27
F26 H26
G14 G26 J26
F12 G12
A14 B14 E12
E14
K14 H14 J14
G15 K15
J17
K17 G17
F9
J11
E8
A9
H11
B9
E11
D9
C4
D26
G9
H9
E15
B18
C20 C18
C21
B20
B21 A21
B26 A23 B23
C26 A26
C27 B27
B15 B17 A17
C15 A15
C12 A12 B12
A11
D5
C8 C5 B5
D8 B8
A8
B11
A6
A5
B6
A4 B4
B3
L26
A27
K21
J21
K20
J20
J24
H24
E26
H12
D11
C11
J12
G8
F8
C24
C9
D18 A18
F15
J18 K18
F14
2
1
1
2
1
2
AA1
R9 P4
F3 L6
AA6
AD6
V7
AG4
P3
F4 L7 R8
V8
AA7
AG5 AD7
M4
U8
J5
E3
AA8
U6
AA5
AG10
M7 P7
M5
P1
M6
P6 P2
P9
P8
P5
R10 P10
R7
U9
U7
U10
L8
L9
H5
J6
J1
J2
L5
D3 J4
E4
F5 E2
H1 H3
H2
AC10
H4
AC6 AC8
AC9
Y8
AC7
Y6 Y7
Y4
V5
Y5
U5 V6
U4
R4 U3
AD5
AD2
AD1
AC3 AD4
AC4
AA4
AC5
AG8
AG9
AG6
AG7
AF8
AF6
AF9
AF7
AA2
AC2
AC1
AF2
AF1
AF3
AG2 AG1
AG3
R5
AA3 Y1 Y2 Y3 V3 V2 C2 D1 D2 E1 F2 F1 L2 L1 M3
M2
V1
J3
AA11
AF4 AF5
Y9 Y10
H6 H7
M8 M9
AD8 AD9
AA9 AA10
J8 J7
L3 L4
R6
V10
V9
AD3
V4
U1
U2
R2
R1
R3
M1
1
2
1
2
2
1
1
2
3
1
2
1
2
3
1
2
1
2
1
2
84 85 95
84 85 95
85 88
113
85 88
113
6
84 85 86 87 88 89 94
85 88
112
85 88
112
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
85 89
112
6
84 85
86 87
88 89
94
85 89
112
85 89
113
85 89 113
IN
IN
A11/A6
SEN
WCK01*
WCK01
EDC3
EDC0
A10/A0
DQ0
DQ13
DQ12
DQ24
CK
A9/A1
BA1/A5 BA2/A4
CAS*
CK*
CKE*
CS*
DQ9
DQ11
DQ14
DQ16
DQ19
DQ23
DQ25 DQ26 DQ27
DQ31
EDC1 EDC2
MF
RAS*
WCK23 WCK23*
WE*
ZQ
BA0/A2
DQ28 DQ29
DQ22
DQ21
DQ17
DQ15
DQ10
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DBI3*
DBI0*
DBI2*
DBI1*
BA3/A3
A8/A7
ABI*
RESET*
DQ18
DQ20
NC
A12/RFU/NC
DQ30
NC
(MF=1)
(1 OF 2)
MF SEN
CAS*
A11/A6
BA1/A5
DQ29
WCK01*
WCK23 WCK23*
RESET*
EDC1 EDC2
NC
DQ28
A10/A0
CKE*
BA0/A2
DQ3 DQ4 DQ5 DQ6
DQ8
DQ9 DQ10 DQ11
BA3/A3
BA2/A4
WE*
DBI2*
A9/A1
A8/A7
CK*
DQ30
ABI*
CK
CS*
DBI1*
DBI3*
DQ0
DQ1
DQ2
DQ7
DQ12
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ25 DQ26
EDC0
EDC3
RAS*
DQ13
DQ15
DQ27
DBI0*
DQ14
DQ31
DQ24
WCK01
ZQ
A12/RFU/NC
NC
(1 OF 2)
(MF=0)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
IN
IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
NC
NC
BI BI BI BI
IN IN IN IN
IN
IN
IN
IN
IN
IN
IN IN
IN IN
IN IN
IN IN IN IN
IN
IN
BI BI BI BI
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI BI
BI
BI
IN
IN
IN IN
BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
IN
IN
IN
IN
IN
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(NONE)
Power aliases required by this page:
Page Notes
MIRRORED
NORMAL
- =PP1V35_S0_GPU_FBVDD
BOM options provided by this page:
Signal aliases required by this page:
CK TERMINATION - A0
CK TERMINATION - A1
PLACE CLOSE TO UA300
10UF
603-3
6.3V
20% X5R
CA300 CA301
20%
6.3V X5R
10UF
603-3
6.3V
20%
402
X5R
4.7UF
CA303
6.3V
20%
402
X5R
CA304
4.7UF
CA350
20%
6.3V
10UF
X5R 603-3
CA351
20%
6.3V
10UF
X5R 603-3
6.3V
20%
402
X5R
CA353
4.7UF
20%
402
X5R
4.7UF
CA354
6.3V
RA303
1%
201
MF
1K
1/20W
PLACE_NEAR=UA300.J10:8.4MM
1K
1/20W
1%
MF
201
RA304
MF
201
1%
1/20W
120
RA300
PLACE_NEAR=UA300.J13:8.4MM
RA353
MF
1/20W
1%
201
1K
PLACE_NEAR=UA350.J10:8.4MM
120
RA350
MF
201
1%
1/20W
PLACE_NEAR=UA350.J13:8.4MM
RA301
1/20W
1%
MF
40.2
201
PLACE_NEAR=UA300.J12:20MM
201
MF
40.2
1%
1/20W
RA351
PLACE_NEAR=UA350.J12:20MM
1/20W
1%
MF
40.2
RA302
201
PLACE_NEAR=UA300.J11:20MM
1/20W
1%
201
RA352
MF
40.2
PLACE_NEAR=UA350.J11:20MM
RA334
1/20W
931
MF 201
1%
PLACE_NEAR=UA300.J14:8.4MM
1/20W 201
1%
549
RA330
MF
PLACE_NEAR=UA300.J14:8.4MM
1.33K
RA331
MF 201
1% 1/20W
PLACE_NEAR=UA300.J14:8.4MM
84 86 118
549
RA332
MF 201
1% 1/20W
PLACE_NEAR=UA300.U10:8.4MM
84 86 118
RA335
MF 201
1% 1/20W
931
PLACE_NEAR=UA300.U10:8.4MM
1%
RA333
1.33K
MF
1/20W
201
PLACE_NEAR=UA300.U10:8.4MM
6.3V
20%
0201
X5R
1UF
CA356
20%
CA357
1UF
X5R
6.3V 0201
6.3V
20% X5R
0201
CA358
1UF
6.3V
20%
1UF
X5R
CA359
0201
6.3V
20%
0201
X5R
1UF
CA360
6.3V
20%
0201
X5R
1UF
CA361
20%
0201
X5R
CA362
1UF
6.3V 6.3V
20%
0201
1UF
CA363
X5R
6.3V
20%
0201
X5R
1UF
CA364
6.3V
20%
0201
X5R
1UF
CA365
6.3V
20%
0201
X5R
1UF
CA306
X5R 0201
6.3V
20%
1UF
CA307
6.3V
20% X5R
1UF
CA308
0201
CA309
6.3V
20% X5R
1UF
0201
6.3V
20%
0201
X5R
CA310
1UF
6.3V
20%
0201
X5R
1UF
CA311
6.3V
20%
0201
X5R
1UF
CA312
6.3V
20%
0201
X5R
1UF
CA313
6.3V
20%
0201
X5R
1UF
CA314
6.3V
20%
0201
X5R
1UF
CA315
1K
RA354
MF
201
1%
1/20W
32MX32-1.5GHZ-MFH
K4G10325FG-HC03
BGA
OMIT_TABLE
UA300
OMIT_TABLE
32MX32-1.5GHZ-MFL
K4G10325FG-HC03
UA350
BGA
K4G10325FG-HC03
BGA
UA350
32MX32-1.5GHZ-MFL
OMIT_TABLE
32MX32-1.5GHZ-MFH
K4G10325FG-HC03
BGA
OMIT_TABLE
UA300
84 86
118
RA338
1%
201
MF
931
1/20W
PLACE_NEAR=UA350.J14:8.4MM
RA336
MF
549
1%
201
1/20W
PLACE_NEAR=UA350.J14:8.4MM
RA337
1/20W
1%
1.33K
MF 201
PLACE_NEAR=UA350.J14:8.4MM
84 86
118
RA341
MF 201
1%
931
1/20W
PLACE_NEAR=UA350.U10:8.4MM
549
MF 201
1% 1/20W
RA339
PLACE_NEAR=UA350.U10:8.4MM
RA340
1%
1.33K
MF
1/20W
201
PLACE_NEAR=UA350.U10:8.4MM
CA390
0.01UF
10% 10V X5R-CERM 0201
CA391
0201
X5R-CERM
10V
10%
0.01UF
CA331
820PF
10% 50V CERM 0402
PLACE_NEAR=UA300.J14:8.4MM
0402
CERM
50V
10%
820PF
CA340
PLACE_NEAR=UA300.A10:8.4MM
0402
CERM
50V
10%
820PF
CA333
PLACE_NEAR=UA300.U10:8.4MM
820PF
10% 50V CERM 0402
CA341
PLACE_NEAR=UA350.A10:8.4MM
820PF
10% 50V CERM 0402
CA383
PLACE_NEAR=UA350.U10:8.4MM
0402
CERM
50V
10%
820PF
CA381
PLACE_NEAR=UA350.J14:8.4MM
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
113
84
112
84 86
112
84 86
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
6.3V
10%
201
X5R
CA316
0.1UF
6.3V 201
X5R
0.1UF
CA317
10%
CA318
10%
201
X5R
0.1UF
6.3V 6.3V
10%
201
X5R
0.1UF
CA319
6.3V
10%
201
X5R
0.1UF
CA320
6.3V
10%
201
X5R
0.1UF
CA321
6.3V
10%
201
X5R
0.1UF
CA322
0.1UF
6.3V
10%
201
X5R
CA323 CA324
201
X5R
6.3V
10%
0.1UF
6.3V
10%
201
X5R
0.1UF
CA325
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84 86
112
84 86
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
6.3V
10% X5R
0.1UF
CA367
201
6.3V
10%
201
X5R
0.1UF
CA366
0.1UF
10%
201
X5R
CA371
6.3V
6.3V
10%
201
X5R
0.1UF
CA375
10%
6.3V 201
X5R
0.1UF
CA370
6.3V
201
X5R
0.1UF
CA374
10%
6.3V
10%
201
0.1UF
CA369
X5R
CA373
6.3V
10% X5R
0.1UF
201
6.3V
10%
201
X5R
0.1UF
CA368
6.3V
10%
201
X5R
0.1UF
CA372
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
113
84
112
84
112
84
112
84
112
SYNC_DATE=04/09/2012
GDDR5 Frame Buffer A
SYNC_MASTER=D8_YAN
FB_A1_ZQ
=PP1V35_S0_GPU_FBVDDQ
FB_A0_DQ<26>
FB_A0_DQ<30>
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_A0_VREFC
FB_A0_A<12>
FB_SW_LEG_A
FB_A0_VREFD
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_SW_LEG_A
=PP1V35_S0_GPU_FBVDDQ
FB_A0_EDC<2>
FB_A1_CLK_N
FB_A0_CK_MID
FB_A0_CLK_N
=PP1V35_S0_GPU_FBVDDQ
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_A1_VREFD
FB_A1_VREFC
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm
=PP1V35_S0_GPU_FBVDDQ
FB_A0_ZQ
FB_A0_A<7>
=PP1V35_S0_GPU_FBVDDQ
FB_A1_CK_MID
FB_A0_MF FB_A0_SEN
FB_A0_DQ<11>
FB_A0_DQ<25>
FB_A0_DQ<27>
FB_A1_A<3>
FB_A1_DQ<8>
FB_A0_WCLK_N<1>
FB_A0_DQ<28>
FB_A0_DQ<31>
FB_A0_DQ<24>
FB_A0_CLK_N
FB_A0_CLK_P
FB_A0_CKE_L
FB_A0_A<0>
FB_A1_DQ<30>
FB_A1_A<12>
FB_A0_DQ<29>
FB_A0_EDC<3>
FB_A0_WCLK_P<1>
FB_A0_WCLK_N<0>
FB_A0_RAS_L
FB_A0_DQ<12>
FB_A1_CLK_P
FB_A0_WCLK_P<0>
FB_A0_ABI_L
FB_A0_DQ<15>
FB_A0_CAS_L
FB_A0_A<5>
FB_A0_CS_L FB_A0_WE_L
FB_A0_A<1>
FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<19>
FB_A0_DQ<21>
FB_A0_EDC<1>
FB_A1_MF
FB_A0_A<6>
FB_A0_A<4>
FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<0> FB_A0_DBI_L<3>
FB_A0_VREFC
FB_A0_A<3>
FB_A1_SEN
FB_A0_DQ<10>
FB_A0_DQ<9>
FB_A1_VREFD
FB_A1_VREFC
FB_A1_CAS_L
FB_A1_A<6>
FB_A1_A<5>
FB_A1_DQ<29>
FB_A1_WCLK_N<0>
FB_A1_WCLK_P<1> FB_A1_WCLK_N<1>
FB_A1_RESET_L
FB_A1_EDC<1> FB_A1_EDC<2>
FB_A1_DQ<28>
FB_A1_A<0>
FB_A1_CKE_L
FB_A1_A<2>
FB_A1_DQ<3> FB_A1_DQ<4> FB_A1_DQ<5> FB_A1_DQ<6>
FB_A1_DQ<9> FB_A1_DQ<10> FB_A1_DQ<11>
FB_A1_A<4>
FB_A1_WE_L
FB_A1_DBI_L<2>
FB_A1_A<1>
FB_A1_A<7>
FB_A1_CLK_N
FB_A1_CLK_P
FB_A1_CS_L
FB_A1_DBI_L<1>
FB_A1_DBI_L<3>
FB_A1_DQ<0> FB_A1_DQ<1> FB_A1_DQ<2>
FB_A1_DQ<7>
FB_A1_DQ<12>
FB_A1_DQ<16>
FB_A1_DQ<19> FB_A1_DQ<20> FB_A1_DQ<21> FB_A1_DQ<22> FB_A1_DQ<23>
FB_A1_DQ<25> FB_A1_DQ<26>
FB_A1_EDC<0>
FB_A1_EDC<3>
FB_A1_RAS_L
FB_A1_DQ<13>
FB_A1_DQ<15>
FB_A1_DQ<27>
FB_A1_DBI_L<0>
FB_A1_DQ<14>
FB_A1_DQ<31>
FB_A1_DQ<24>
FB_A1_WCLK_P<0>
FB_A0_EDC<0>
FB_A0_DQ<0>
FB_A0_DQ<13> FB_A0_DQ<14>
FB_A0_DQ<16>
FB_A0_DQ<23>
FB_A0_A<2>
FB_A0_DQ<22>
FB_A0_DQ<8>
FB_A0_DQ<7>
FB_A0_DQ<6>
FB_A0_DQ<5>
FB_A0_DQ<4>
FB_A0_DQ<3>
FB_A0_DQ<2>
FB_A0_DQ<1>
FB_A0_DQ<20>
FB_A0_VREFD
FB_A0_RESET_L
=PP1V35_S0_GPU_FBVDDQ
=PP1V35_S0_GPU_FBVDDQ
FB_SW_LEG_A
FB_SW_LEG_A
FB_A1_ABI_L
FB_A1_DQ<18>
FB_A1_DQ<17>
FB_A0_CLK_P
prefsb
051-9505
8.0.0
103 OF 144
86 OF 123
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
H5
J10
P5
P4
C2
R2
K4
U4
N13
N11
A4
J12
K5
H10 H11
G3
J11
J3
L12
U13
T13
M11
A11
B13
F13
A2 B4 B2
F2
R13 C13
J1
L3
D4 D5
G12
J13
K11
E4 E2
F11
E13
A13
M13
T11
U11
M2
M4
N2
N4
T2
T4
U2
D2
P2
D13
P13
K10
H4
J4
J2
B11
E11
A5 J5
F4
U5
J1
J10
L3
K5
K10
N2
D5
P4 P5
J2
C13 R13
U5
N4
H4
J3
H11
B2 E4 E2 F4
A11 A13 B11 B13
H10
K11
L12
P13
H5
K4
J11
M4
J4
J12
G12
D13
P2
A4 A2 B4
F2
E11
U11 U13 T11 T13 N11 N13 M11 M13
U2 T4
C2
R2
G3
E13
F13
T2
D2
F11
M2
U4
D4
J13
J5
A5
U14
U12
U3
U1
R14
R12
R11
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
K2
H13
H2
F10
F5
E1
C14
C11
C4
C3
C1
A14
A1
T10
T5
P10
L10
L5
K14
K1
H14
H1
G10
G5
D10
B10
B5
U10
A10
J14
T14
T12
T3
T1
P14
P12
P3
P1
N10
N5
M14
M12
M3
M1
L13
L2
K12
K3
H12
H3
G13
G2
F14
F12
F3
F1
E10
E5
D14
D12
D3
D1
R10
R5
P11
L14
L11
L4
L1
G14
G11
G4
G1
D11
C10
C5
B1
B3 B12 B14
A12
A3
E12 E14
E3
C12
C12
C11
C4
C3
C1
A14
U14
U12
U3
U1
R14
R12
R11
A12
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
A3
K2
H13
H2
F10
E14
E12
E3
E1
C14
A1
K14
K1
H14
H1
G10
G5
D10
B10
T10
T5
P10
L10
L5
B5
U10
A10
J14
E5
D14
D12
D3
D1
B14
T14
T12
T3
T1
P14
P12
P3
B12
P1
N10
M14
F14
F12
F3
F1
E10
B1
L4
L1
G14
G11
G4
G1
D11
C10
R10
R5
P11
L14
L11
N5
M12
M3
M1
L13
L2
K12
B3
K3
H12
H3
G13
G2
F5
C5
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
84 85 86 87 88 89 94
86
118
86
118
6
84
85 86
87 88
89 94
84 86
112
112
84 86
112
6
84 85 86 87 88 89 94
86
118
86
118
6
84 85 86 87 88 89 94
6
84
85 86
87
88 89 94
84 86
112
86
118
86
118
86
118
86
118
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
84 86 112
IN
BI
IN
IN
A11/A6
SEN
WCK01*
WCK01
EDC3
EDC0
A10/A0
DQ0
DQ13
DQ12
DQ24
CK
A9/A1
BA1/A5 BA2/A4
CAS*
CK*
CKE*
CS*
DQ9
DQ11
DQ14
DQ16
DQ19
DQ23
DQ25 DQ26 DQ27
DQ31
EDC1 EDC2
MF
RAS*
WCK23 WCK23*
WE*
ZQ
BA0/A2
DQ28 DQ29
DQ22
DQ21
DQ17
DQ15
DQ10
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DBI3*
DBI0*
DBI2*
DBI1*
BA3/A3
A8/A7
ABI*
RESET*
DQ18
DQ20
NC
A12/RFU/NC
DQ30
NC
(MF=1)
(1 OF 2)
MF SEN
CAS*
A11/A6
BA1/A5
DQ29
WCK01*
WCK23 WCK23*
RESET*
EDC1 EDC2
NC
DQ28
A10/A0
CKE*
BA0/A2
DQ3 DQ4 DQ5 DQ6
DQ8
DQ9 DQ10 DQ11
BA3/A3
BA2/A4
WE*
DBI2*
A9/A1
A8/A7
CK*
DQ30
ABI*
CK
CS*
DBI1*
DBI3*
DQ0
DQ1
DQ2
DQ7
DQ12
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ25 DQ26
EDC0
EDC3
RAS*
DQ13
DQ15
DQ27
DBI0*
DQ14
DQ31
DQ24
WCK01
ZQ
A12/RFU/NC
NC
(1 OF 2)
(MF=0)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
IN
IN
BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
NC
NC
BI BI BI BI
IN IN IN IN
IN
IN
IN
IN
IN
IN
IN IN
IN IN
IN IN
IN IN IN IN
IN
IN
BI BI BI BI
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI BI
BI
BI
IN
IN
IN IN
BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
IN
IN IN
IN
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CK TERMINATION - B1
Power aliases required by this page:
BOM options provided by this page:
(NONE)
MIRRORED
NORMAL
Page Notes
Signal aliases required by this page:
(NONE)
- =PP1V35_S0_GPU_FBVDD
CK TERMINATION - B0
PLACE CLOSE TO UA400
PLACE CLOSE TO UA450
84
112
84
112
6.3V
20% X5R
CA400
10UF
603-3
20% X5R
603-3
6.3V
CA401
10UF
CA404
4.7UF
X5R 402
20%
6.3V6.3V X5R 402
20%
4.7UF
CA403
CA450
X5R
20%
6.3V
10UF
603-3
6.3V
20% X5R
CA451
10UF
603-3
CA453
4.7UF
X5R 402
20%
6.3V
CA454
4.7UF
X5R 402
20%
6.3V
201
1% MF
1/20W
RA404
1K
MF
201
1%
1/20W
1K
RA403
PLACE_NEAR=UA400.J10:8.4MM
RA453
MF
201
1%
1/20W
1K
PLACE_NEAR=UA450.J10:8.4MM
201
1% MF
1/20W
RA450
120
PLACE_NEAR=UA450.J13:8.4MM
MF
RA402
40.2
201
1%
1/20W
PLACE_NEAR=UA400.J11:20MM
201
1%
40.2
RA401
MF
1/20W
PLACE_NEAR=UA400.J12:20MM
1%
40.2
RA452
1/20W
MF
201
PLACE_NEAR=UA450.J11:20MM
40.2
MF
201
1/20W
1%
RA451
PLACE_NEAR=UA450.J12:20MM
1.33K
1/20W
1%
201
MF
RA431
PLACE_NEAR=UA400.J14:8.4MM
84 87 118
1/20W
931
1%
201
MF
RA434
PLACE_NEAR=UA400.J14:8.4MM
201
MF
1/20W
1%
549
RA430
PLACE_NEAR=UA400.J14:8.4MM
201
1/20W
1%
MF
1.33K
RA433
PLACE_NEAR=UA400.U10:8.4MM
201
RA435
1/20W
1% MF
931
PLACE_NEAR=UA400.U10:8.4MM
1/20W
1%
201
MF
549
RA432
PLACE_NEAR=UA400.U10:8.4MM
84 87 118
CA406
X5R 0201
20%
6.3V
1UF
CA407
1UF
X5R 0201
20%
6.3V
CA408
1UF
X5R 0201
20%
6.3V
CA409
1UF
X5R 0201
20%
6.3V
CA410
1UF
X5R 0201
20%
6.3V
CA411
1UF
X5R 0201
20%
6.3V
CA412
1UF
X5R 0201
20%
6.3V
0201
CA413
1UF
X5R
20%
6.3V
CA414
1UF
X5R 0201
20%
6.3V
CA415
1UF
X5R 0201
20%
6.3V
CA456
1UF
X5R 0201
20%
6.3V X5R 0201
20%
6.3V
1UF
CA457
1UF
X5R 0201
20%
6.3V
CA458 CA459
X5R 0201
20%
6.3V
1UF
CA460
X5R 0201
6.3V
1UF
20%
CA461
1UF
0201
20%
6.3V X5R
1UF
X5R
20%
6.3V
CA462
0201
CA463
20%
6.3V
1UF
X5R 0201
1UF
X5R 0201
20%
6.3V
CA464
1UF
X5R 0201
6.3V
20%
CA465
RA454
MF
201
1%
1/20W
1K
32MX32-1.5GHZ-MFH
K4G10325FG-HC03
OMIT_TABLE
BGA
UA400
K4G10325FG-HC03
32MX32-1.5GHZ-MFL
BGA
OMIT_TABLE
UA450
OMIT_TABLE
UA450
K4G10325FG-HC03
BGA
32MX32-1.5GHZ-MFL
OMIT_TABLE
BGA
K4G10325FG-HC03
32MX32-1.5GHZ-MFH
UA400
84 87
118
931
1% 1/20W
201
RA438
MF
PLACE_NEAR=UA450.J14:8.4MM
RA436
549
1% 1/20W MF 201
PLACE_NEAR=UA450.J14:8.4MM
1.33K
RA437
MF 201
1% 1/20W
PLACE_NEAR=UA450.J14:8.4MM
84 87
118
RA441
931
MF
1% 1/20W
201
PLACE_NEAR=UA450.U10:8.4MM
RA439
549
MF 201
1% 1/20W
PLACE_NEAR=UA450.U10:8.4MM
RA440
1.33K
MF
1% 1/20W
201
PLACE_NEAR=UA450.U10:8.4MM
0201
X5R-CERM
10V
10%
0.01UF
CA490
0201
X5R-CERM
10V
10%
0.01UF
CA491
0402
CERM
50V
10%
820PF
CA431
PLACE_NEAR=UA400.J14:8.4MM
10% 50V CERM 0402
820PF
CA440
PLACE_NEAR=UA400.A10:30MM
820PF
10% 50V CERM 0402
CA433
PLACE_NEAR=UA400.U10:30MM
0402
CERM
50V
10%
820PF
CA441
PLACE_NEAR=UA450.A10:8.4MM
0402
CERM
50V
10%
820PF
CA483
PLACE_NEAR=UA450.U10:8.4MM
820PF
10% 50V CERM 0402
CA481
PLACE_NEAR=UA450.J14:8.4MM
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
113
84
112
84 87
112
84 87
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
1/20W
1%
201
MF
120
RA400
PLACE_NEAR=UA400.J13:8.4MM
84
112
84
112
84
112
84
112
84
112
CA416
0.1UF
X5R 201
10%
6.3V X5R
CA417
201
10%
0.1UF
6.3V
CA418
0.1UF
X5R 201
10%
6.3V
CA419
0.1UF
X5R 201
10%
6.3V
CA420
0.1UF
X5R 201
10%
6.3V
201
10%
CA421
0.1UF
X5R
6.3V
6.3V
CA422
0.1UF
X5R 201
10%
0.1UF
X5R 201
6.3V
CA423
10%
CA424
0.1UF
X5R 201
10%
6.3V 6.3V
CA425
0.1UF
X5R 201
10%
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84 87
112
84 87
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
CA467
201
0.1UF
X5R
10%
6.3V
0.1UF
X5R 201
10%
6.3V
CA466
CA471
0.1UF
10%
6.3V X5R 201
CA475
0.1UF
X5R 201
10%
6.3V
CA470
0.1UF
X5R 201
10%
6.3V
CA474
X5R 201
10%
6.3V
0.1UF
CA469
0.1UF
X5R 201
10%
6.3V
CA473
0.1UF
X5R
10%
6.3V
201
CA468
6.3V
0.1UF
X5R 201
10%
0.1UF
X5R 201
10%
6.3V
CA472
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
112
84
113
84
112
84
112
84
112
SYNC_MASTER=D8_YAN
SYNC_DATE=04/09/2012
GDDR5 Frame Buffer B
FB_B0_VREFD
=PP1V35_S0_GPU_FBVDDQ
=PP1V35_S0_GPU_FBVDDQ
FB_B1_WCLK_N<1>
FB_B1_WCLK_P<1>
FB_B1_WCLK_P<0>
FB_B1_EDC<3>
FB_B1_EDC<1>
FB_B1_WE_L
FB_B1_CS_L
FB_B1_CLK_N
MIN_NECK_WIDTH=0.1 mm
FB_B0_VREFC
MIN_LINE_WIDTH=0.25 MM
=PP1V35_S0_GPU_FBVDDQ
=PP1V35_S0_GPU_FBVDDQ
MIN_NECK_WIDTH=0.1 mm MIN_LINE_WIDTH=0.25 MM
FB_B1_VREFC
FB_B1_VREFD
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_SW_LEG_B
FB_B0_MF FB_B0_SEN FB_B0_RESET_L
FB_B0_DQ<15>
FB_B0_DQ<11>
FB_B0_DQ<9>
FB_B1_SEN
FB_B1_ZQ
FB_B0_DQ<24>
FB_B0_CS_L
FB_B0_A<6>
FB_B0_EDC<0> FB_B0_EDC<1>
FB_B0_CLK_N
FB_B0_DQ<19>
FB_B0_DQ<18>
FB_B1_MF
FB_B0_DQ<4>
FB_B0_DQ<3>
FB_B0_DQ<10>
FB_B1_RAS_L
FB_B0_A<4>
FB_B0_DBI_L<2>
FB_B0_A<0>
FB_B0_A<2> FB_B0_A<5>
FB_B0_A<3>
FB_B0_WCLK_N<1>
FB_B1_DQ<26>
FB_B0_CLK_P
FB_B0_DQ<28>
FB_B0_DQ<20>
FB_B0_DQ<14>
FB_B0_DQ<2>
FB_B1_VREFD
FB_B1_VREFC
FB_B1_CAS_L
FB_B1_A<6>
FB_B1_A<5>
FB_B1_WCLK_N<0>
FB_B1_RESET_L
FB_B1_EDC<2>
FB_B1_A<0>
FB_B1_CKE_L
FB_B1_A<2>
FB_B1_DQ<3> FB_B1_DQ<4> FB_B1_DQ<5> FB_B1_DQ<6>
FB_B1_DQ<8> FB_B1_DQ<9> FB_B1_DQ<10> FB_B1_DQ<11>
FB_B1_A<3>
FB_B1_A<4>
FB_B1_DBI_L<2>
FB_B1_A<1>
FB_B1_A<7>
FB_B1_DQ<30>
FB_B1_ABI_L
FB_B1_CLK_P
FB_B1_DBI_L<1>
FB_B1_DBI_L<3>
FB_B1_DQ<0> FB_B1_DQ<1> FB_B1_DQ<2>
FB_B1_DQ<7>
FB_B1_DQ<12>
FB_B1_DQ<16> FB_B1_DQ<17> FB_B1_DQ<18> FB_B1_DQ<19> FB_B1_DQ<20> FB_B1_DQ<21> FB_B1_DQ<22> FB_B1_DQ<23>
FB_B1_EDC<0>
FB_B1_DQ<13>
FB_B1_DQ<15>
FB_B1_DQ<27>
FB_B1_DBI_L<0>
FB_B1_DQ<14>
FB_B1_DQ<24>
FB_B0_WCLK_N<0>
FB_B0_WCLK_P<0>
FB_B0_EDC<3>
FB_B0_DQ<0>
FB_B0_DQ<13>
FB_B0_DQ<12>
FB_B0_A<1>
FB_B0_CAS_L
FB_B0_CLK_N
FB_B0_CKE_L
FB_B0_RAS_L
FB_B0_WCLK_P<1>
FB_B0_WE_L
FB_B0_DQ<29>
FB_B0_DQ<22>
FB_B0_DQ<21>
FB_B0_DQ<17>
FB_B0_DQ<8>
FB_B0_DQ<7>
FB_B0_DQ<6>
FB_B0_DQ<5>
FB_B0_DQ<1>
FB_B0_DBI_L<3>
FB_B0_DBI_L<0>
FB_B0_DBI_L<1>
FB_B0_A<12>
FB_B0_DQ<30>
FB_B1_CLK_N
FB_B0_CLK_P
=PP1V35_S0_GPU_FBVDDQ
FB_B0_ZQ
FB_B0_EDC<2>
FB_B0_DQ<23>
FB_B0_DQ<25> FB_B0_DQ<26> FB_B0_DQ<27>
FB_B0_DQ<31>
FB_B0_VREFD
FB_B0_VREFC
=PP1V35_S0_GPU_FBVDDQ
FB_SW_LEG_B
FB_SW_LEG_B
FB_B1_A<12>
=PP1V35_S0_GPU_FBVDDQ
FB_B1_DQ<31>
FB_B1_DQ<29>
FB_B1_DQ<28>
FB_B1_DQ<25>
FB_SW_LEG_B
FB_B1_CLK_P
FB_B0_DQ<16>
FB_B0_ABI_L
FB_B0_A<7>
FB_B0_CK_MID
FB_B1_CK_MID
prefsb
051-9505
8.0.0
104 OF 144
87 OF 123
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1 21 2
1 21 2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
H5
J10
P5
P4
C2
R2
K4
U4
N13
N11
A4
J12
K5
H10 H11
G3
J11
J3
L12
U13
T13
M11
A11
B13
F13
A2 B4 B2
F2
R13 C13
J1
L3
D4 D5
G12
J13
K11
E4 E2
F11
E13
A13
M13
T11
U11
M2
M4
N2
N4
T2
T4
U2
D2
P2
D13
P13
K10
H4
J4
J2
B11
E11
A5 J5
F4
U5
J1
J10
L3
K5
K10
N2
D5
P4 P5
J2
C13 R13
U5
N4
H4
J3
H11
B2 E4 E2 F4
A11 A13 B11 B13
H10
K11
L12
P13
H5
K4
J11
M4
J4
J12
G12
D13
P2
A4 A2 B4
F2
E11
U11 U13 T11 T13 N11 N13 M11 M13
U2 T4
C2
R2
G3
E13
F13
T2
D2
F11
M2
U4
D4
J13
J5
A5
U14
U12
U3
U1
R14
R12
R11
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
K2
H13
H2
F10
F5
E1
C14
C11
C4
C3
C1
A14
A1
T10
T5
P10
L10
L5
K14
K1
H14
H1
G10
G5
D10
B10
B5
U10
A10
J14
T14
T12
T3
T1
P14
P12
P3
P1
N10
N5
M14
M12
M3
M1
L13
L2
K12
K3
H12
H3
G13
G2
F14
F12
F3
F1
E10
E5
D14
D12
D3
D1
R10
R5
P11
L14
L11
L4
L1
G14
G11
G4
G1
D11
C10
C5
B1
B3 B12 B14
A12
A3
E12 E14
E3
C12
C12
C11
C4
C3
C1
A14
U14
U12
U3
U1
R14
R12
R11
A12
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
A3
K2
H13
H2
F10
E14
E12
E3
E1
C14
A1
K14
K1
H14
H1
G10
G5
D10
B10
T10
T5
P10
L10
L5
B5
U10
A10
J14
E5
D14
D12
D3
D1
B14
T14
T12
T3
T1
P14
P12
P3
B12
P1
N10
M14
F14
F12
F3
F1
E10
B1
L4
L1
G14
G11
G4
G1
D11
C10
R10
R5
P11
L14
L11
N5
M12
M3
M1
L13
L2
K12
B3
K3
H12
H3
G13
G2
F5
C5
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
87
118
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
87
118
6
84 85 86 87 88 89 94
6
84
85 86
87 88
89 94
87
118
87
118
84 87
112
87
118
87
118
84 87
112
84 87 112
6
84 85
86 87 88
89 94
87
118
87
118
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
84 87 112
112
IN
BI
IN
IN
MF SEN
CAS*
A11/A6
BA1/A5
DQ29
WCK01*
WCK23 WCK23*
RESET*
EDC1 EDC2
NC
DQ28
A10/A0
CKE*
BA0/A2
DQ3 DQ4 DQ5 DQ6
DQ8
DQ9 DQ10 DQ11
BA3/A3
BA2/A4
WE*
DBI2*
A9/A1
A8/A7
CK*
DQ30
ABI*
CK
CS*
DBI1*
DBI3*
DQ0
DQ1
DQ2
DQ7
DQ12
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ25 DQ26
EDC0
EDC3
RAS*
DQ13
DQ15
DQ27
DBI0*
DQ14
DQ31
DQ24
WCK01
ZQ
A12/RFU/NC
NC
(1 OF 2)
(MF=0)
A11/A6
SEN
WCK01*
WCK01
EDC3
EDC0
A10/A0
DQ0
DQ13
DQ12
DQ24
CK
A9/A1
BA1/A5 BA2/A4
CAS*
CK*
CKE*
CS*
DQ9
DQ11
DQ14
DQ16
DQ19
DQ23
DQ25 DQ26 DQ27
DQ31
EDC1 EDC2
MF
RAS*
WCK23 WCK23*
WE*
ZQ
BA0/A2
DQ28 DQ29
DQ22
DQ21
DQ17
DQ15
DQ10
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DBI3*
DBI0*
DBI2*
DBI1*
BA3/A3
A8/A7
ABI*
RESET*
DQ18
DQ20
NC
A12/RFU/NC
DQ30
NC
(MF=1)
(1 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
IN
IN
BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
NC
NC
BI BI BI BI
IN IN IN IN
IN
IN
IN
IN
IN
IN
IN IN
IN IN
IN IN
IN IN IN IN
IN
IN
BI BI BI BI
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI BI
BI
BI
IN
IN
IN IN
BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
IN
IN IN
IN
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CK TERMINATION - C0
Signal aliases required by this page:
(NONE)
CK TERMINATION - C1
- =PP1V35_S0_GPU_FBVDD
Power aliases required by this page:
BOM options provided by this page:
NORMAL
MIRRORED
Page Notes
(NONE)
PLACE CLOSE TO UA500
85
113
85
113
6.3V 603-3
10UF
20% X5R
CA500 CA501
10UF
603-3
X5R
6.3V
20%
CA504
4.7UF
X5R 402
20%
6.3V
CA503
4.7UF
20%
6.3V X5R 402
603-3
10UF
6.3V
20% X5R
CA550
603-3
10UF
6.3V
20% X5R
CA551
CA553
4.7UF
X5R 402
20%
6.3V
CA554
4.7UF
X5R 402
20%
6.3V
RA504
MF
201
1%
1/20W
1K 1K
1/20W
1% MF
201
RA503
PLACE_NEAR=UA500.J10:8.4MM
1%
1K
1/20W
201
MF
RA553
PLACE_NEAR=UA550.J10:8.4MM
120
RA550
1/20W
MF
1%
201
PLACE_NEAR=UA550.J13:8.4MM
201
RA502
40.2
MF
1%
1/20W
PLACE_NEAR=UA500.J11:20MM
RA501
40.2
201
MF
1%
1/20W
PLACE_NEAR=UA500.J12:20MM
201
MF
1/20W
1%
40.2
RA552
PLACE_NEAR=UA550.J11:20MM
RA551
40.2
MF
201
1/20W
1%
PLACE_NEAR=UA550.J12:20MM
1.33K
1%
201
MF
RA531
1/20W
PLACE_NEAR=UA500.J14:8.4MM
85 88 118
1/20W
931
RA534
1%
MF 201
PLACE_NEAR=UA500.J14:8.4MM
1/20W
1%
201
549
MF
RA530
PLACE_NEAR=UA500.J14:8.4MM
1%
201
MF
1.33K
RA533
1/20W
PLACE_NEAR=UA500.U10:8.4MM
1/20W
201
MF
931
RA535
1%
PLACE_NEAR=UA500.U10:8.4MM
201
MF
RA532
549
1/20W
1%
PLACE_NEAR=UA500.U10:8.4MM
85 88 118
CA506
1UF
X5R 0201
20%
6.3V
CA507
1UF
X5R 0201
20%
6.3V
1UF
CA508
X5R 0201
6.3V
20%
CA509
1UF
X5R 0201
20%
6.3V
CA510
1UF
X5R 0201
20%
6.3V
CA511
1UF
X5R 0201
20%
6.3V
CA512
1UF
X5R 0201
20%
6.3V
CA513
1UF
X5R 0201
20%
6.3V
CA514
1UF
X5R 0201
20%
6.3V
CA515
1UF
X5R 0201
20%
6.3V
CA556
X5R 0201
20%
6.3V
1UF
CA557
1UF
X5R 0201
20%
6.3V
CA558
1UF
X5R 0201
20%
6.3V
CA559
1UF
X5R 0201
20%
6.3V
CA560
1UF
X5R 0201
20%
6.3V
CA561
1UF
X5R 0201
20%
6.3V
CA562
1UF
X5R
20%
6.3V
0201
20%
6.3V
1UF
X5R 0201
CA563
CA564
1UF
X5R 0201
20%
6.3V
CA565
1UF
X5R 0201
20%
6.3V
1K
RA554
MF
201
1%
1/20W
K4G10325FG-HC03
32MX32-1.5GHZ-MFL
BGA
OMIT_TABLE
UA550
OMIT_TABLE
K4G10325FG-HC03
32MX32-1.5GHZ-MFH
BGA
UA500
BGA
32MX32-1.5GHZ-MFL
K4G10325FG-HC03
OMIT_TABLE
UA550
BGA
OMIT_TABLE
K4G10325FG-HC03
32MX32-1.5GHZ-MFH
UA500
85 88
118
PLACE_NEAR=UA550.J14:8.4MM
201
MF
1%
931
1/20W
RA538
PLACE_NEAR=UA550.J14:8.4MM
201
RA536
1/20W
1%
549
MF
PLACE_NEAR=UA550.J14:8.4MM
1/20W MF 201
1%
1.33K
RA537
85 88
118
1%
931
MF 201
1/20W
RA541
PLACE_NEAR=UA550.U10:8.4MM
549
1% 1/20W MF 201
RA539
PLACE_NEAR=UA550.U10:8.4MM
1/20W
1.33K
MF 201
1%
RA540
PLACE_NEAR=UA550.U10:8.4MM
0201
X5R-CERM
10V
10%
0.01UF
CA590
0201
X5R-CERM
10V
10%
0.01UF
CA591
0402
CERM
50V
10%
820PF
CA531
PLACE_NEAR=UA500.J14:8.4MM
0402
CERM
50V
10%
820PF
CA540
PLACE_NEAR=UA500.A10:30MM
820PF
10% 50V CERM 0402
CA533
PLACE_NEAR=UA500.U10:30MM
0402
CERM
50V
10%
820PF
CA541
PLACE_NEAR=UA550.A10:8.4MM
0402
CERM
50V
10%
820PF
CA583
PLACE_NEAR=UA550.U10:8.4MM
PLACE_NEAR=UA550.J14:8.4MM
CA581
820PF
10% 50V CERM 0402
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85 88
113
85 88
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
112
120
RA500
MF
1%
1/20W
201
PLACE_NEAR=UA500.J13:8.4MM
85
113
85
113
85
113
85
113
85
113
CA516
0.1UF
X5R 201
10%
6.3V
CA517
0.1UF
X5R 201
10%
6.3V
CA518
0.1UF
X5R 201
10%
6.3V
CA519
0.1UF
10%
6.3V X5R 201
CA520
0.1UF
201
10%
6.3V X5R
0.1UF
X5R 201
10%
6.3V
CA521
CA522
0.1UF
X5R 201
10%
6.3V
CA523
0.1UF
X5R 201
10%
6.3V
CA524
0.1UF
X5R 201
10%
6.3V
CA525
0.1UF
X5R 201
10%
6.3V
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85 88
113
85 88
113
85
112
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
201
0.1UF
X5R
10%
6.3V
CA567
0.1UF
X5R 201
10%
6.3V
CA566
0.1UF
CA571
X5R 201
10%
6.3V
CA575
0.1UF
X5R 201
10%
6.3V
10%
0.1UF
CA570
X5R 201
6.3V
CA574
X5R 201
10%
6.3V
0.1UF
6.3V
CA569
0.1UF
X5R 201
10%
CA573
0.1UF
X5R 201
10%
6.3V
CA568
6.3V
0.1UF
X5R 201
10%
CA572
0.1UF
X5R 201
10%
6.3V
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
SYNC_DATE=04/09/2012
SYNC_MASTER=D8_YAN
GDDR5 FRAME BUFFER C
=PP1V35_S0_GPU_FBVDDQ
FB_C0_VREFD
=PP1V35_S0_GPU_FBVDDQ
FB_C1_VREFC
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
=PP1V35_S0_GPU_FBVDDQ
FB_C1_A<12>
FB_C1_DQ<31>
FB_C0_ABI_L
FB_C1_CK_MID
=PP1V35_S0_GPU_FBVDDQ
=PP1V35_S0_GPU_FBVDDQ
FB_SW_LEG_C
FB_SW_LEG_C
=PP1V35_S0_GPU_FBVDDQ
FB_C1_CLK_N
FB_C0_CLK_N
FB_C0_DQ<18>
FB_C0_RESET_L
FB_C0_A<7>
FB_C0_DBI_L<0> FB_C0_DBI_L<3>
FB_C0_DQ<4> FB_C0_DQ<5> FB_C0_DQ<6> FB_C0_DQ<7> FB_C0_DQ<8>
FB_C0_DQ<17>
FB_C0_DQ<21>
FB_C0_WE_L
FB_C0_WCLK_P<1>
FB_C0_RAS_L
FB_C0_EDC<2>
FB_C0_EDC<1>
FB_C0_DQ<16>
FB_C0_DQ<9>
FB_C0_CS_L
FB_C0_CAS_L
FB_C0_A<4>
FB_C0_EDC<0>
FB_C0_WCLK_N<0>
FB_C0_A<6>
FB_C0_DQ<22>
FB_C1_WCLK_P<0>
FB_C1_DQ<24>
FB_C1_DQ<14>
FB_C1_DBI_L<0>
FB_C1_DQ<27>
FB_C1_DQ<15>
FB_C1_DQ<13>
FB_C1_RAS_L
FB_C1_EDC<3>
FB_C1_EDC<0>
FB_C1_DQ<26>
FB_C1_DQ<25>
FB_C1_DQ<23>
FB_C1_DQ<22>
FB_C1_DQ<21>
FB_C1_DQ<20>
FB_C1_DQ<19>
FB_C1_DQ<18>
FB_C1_DQ<17>
FB_C1_DQ<16>
FB_C1_DQ<12>
FB_C1_DQ<7>
FB_C1_DQ<2>
FB_C1_DQ<1>
FB_C1_DQ<0>
FB_C1_DBI_L<3>
FB_C1_DBI_L<1>
FB_C1_CS_L
FB_C1_CLK_P
FB_C1_ABI_L
FB_C1_DQ<30>
FB_C1_CLK_N
FB_C1_A<7>
FB_C1_DBI_L<2>
FB_C1_WE_L
FB_C1_A<4> FB_C1_A<3>
FB_C1_DQ<11>
FB_C1_DQ<10>
FB_C1_DQ<9>
FB_C1_DQ<8>
FB_C1_DQ<6>
FB_C1_DQ<5>
FB_C1_DQ<4>
FB_C1_DQ<3>
FB_C1_A<2>
FB_C1_CKE_L
FB_C1_A<0>
FB_C1_DQ<28>
FB_C1_EDC<2>
FB_C1_EDC<1>
FB_C1_RESET_L
FB_C1_WCLK_N<1>
FB_C1_WCLK_P<1>
FB_C1_WCLK_N<0>
FB_C1_DQ<29>
FB_C1_A<5>
FB_C1_A<6>
FB_C1_CAS_L
FB_C0_VREFC FB_C0_VREFD
FB_C1_VREFC FB_C1_VREFD
FB_C0_WCLK_P<0>
FB_C0_DQ<2>
FB_C0_A<3>
FB_C0_DQ<25>
FB_C0_DQ<24>
FB_C0_DQ<29>
FB_C0_A<12>
FB_C0_DBI_L<2>
FB_C0_DBI_L<1>
FB_C0_A<2> FB_C0_A<5>
FB_C0_DQ<0> FB_C0_DQ<1>
FB_C1_MF
FB_C0_DQ<10> FB_C0_DQ<11> FB_C0_DQ<12>
FB_C0_DQ<3>
FB_C0_EDC<3>
FB_C0_DQ<23>
FB_C0_DQ<20>
FB_C0_DQ<19>
FB_C0_A<0>
FB_C0_CLK_N
FB_C0_DQ<26>
FB_C0_DQ<31>
FB_C0_CKE_L
FB_C0_DQ<13> FB_C0_DQ<14> FB_C0_DQ<15>
FB_C0_SEN
FB_C0_MF
FB_C0_A<1>
FB_C0_CLK_P
FB_C1_ZQ
FB_C1_SEN
FB_C1_CLK_P
FB_SW_LEG_C
FB_C1_VREFD
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm
FB_C0_CLK_P
FB_C0_ZQ
FB_C0_CK_MID
FB_C0_WCLK_N<1>
FB_C0_DQ<30>
FB_C0_DQ<28>
FB_C0_DQ<27>
FB_C1_A<1>
=PP1V35_S0_GPU_FBVDDQ
FB_SW_LEG_C
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_C0_VREFC
prefsb
051-9505
8.0.0
105 OF 144
88 OF 123
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1 21 2
1 21 2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
J1
J10
L3
K5
K10
N2
D5
P4 P5
J2
C13 R13
U5
N4
H4
J3
H11
B2 E4 E2 F4
A11 A13 B11 B13
H10
K11
L12
P13
H5
K4
J11
M4
J4
J12
G12
D13
P2
A4 A2 B4
F2
E11
U11 U13 T11 T13 N11 N13 M11 M13
U2 T4
C2
R2
G3
E13
F13
T2
D2
F11
M2
U4
D4
J13
J5
A5
H5
J10
P5
P4
C2
R2
K4
U4
N13
N11
A4
J12
K5
H10 H11
G3
J11
J3
L12
U13
T13
M11
A11
B13
F13
A2 B4 B2
F2
R13 C13
J1
L3
D4 D5
G12
J13
K11
E4 E2
F11
E13
A13
M13
T11
U11
M2
M4
N2
N4
T2
T4
U2
D2
P2
D13
P13
K10
H4
J4
J2
B11
E11
A5 J5
F4
U5
U14
U12
U3
U1
R14
R12
R11
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
K2
H13
H2
F10
F5
E1
C14
C11
C4
C3
C1
A14
A1
T10
T5
P10
L10
L5
K14
K1
H14
H1
G10
G5
D10
B10
B5
U10
A10
J14
T14
T12
T3
T1
P14
P12
P3
P1
N10
N5
M14
M12
M3
M1
L13
L2
K12
K3
H12
H3
G13
G2
F14
F12
F3
F1
E10
E5
D14
D12
D3
D1
R10
R5
P11
L14
L11
L4
L1
G14
G11
G4
G1
D11
C10
C5
B1
B3 B12 B14
A12
A3
E12 E14
E3
C12
C12
C11
C4
C3
C1
A14
U14
U12
U3
U1
R14
R12
R11
A12
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
A3
K2
H13
H2
F10
E14
E12
E3
E1
C14
A1
K14
K1
H14
H1
G10
G5
D10
B10
T10
T5
P10
L10
L5
B5
U10
A10
J14
E5
D14
D12
D3
D1
B14
T14
T12
T3
T1
P14
P12
P3
B12
P1
N10
M14
F14
F12
F3
F1
E10
B1
L4
L1
G14
G11
G4
G1
D11
C10
R10
R5
P11
L14
L11
N5
M12
M3
M1
L13
L2
K12
B3
K3
H12
H3
G13
G2
F5
C5
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
84 85 86 87 88 89 94
88
118
6
84
85 86
87 88
89 94
88
118
6
84 85 86 87 88 89 94
112
6 84
85
86 87 88 89 94
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
85 88
113
85 88
113
88
118
88
118
88
118
88
118
85 88
113
88
118
85 88 113
112
6
84 85 86 87 88 89 94
88
118
IN
BI
IN
IN
MF SEN
CAS*
A11/A6
BA1/A5
DQ29
WCK01*
WCK23 WCK23*
RESET*
EDC1 EDC2
NC
DQ28
A10/A0
CKE*
BA0/A2
DQ3 DQ4 DQ5 DQ6
DQ8
DQ9 DQ10 DQ11
BA3/A3
BA2/A4
WE*
DBI2*
A9/A1
A8/A7
CK*
DQ30
ABI*
CK
CS*
DBI1*
DBI3*
DQ0
DQ1
DQ2
DQ7
DQ12
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ25 DQ26
EDC0
EDC3
RAS*
DQ13
DQ15
DQ27
DBI0*
DQ14
DQ31
DQ24
WCK01
ZQ
A12/RFU/NC
NC
(1 OF 2)
(MF=0)
A11/A6
SEN
WCK01*
WCK01
EDC3
EDC0
A10/A0
DQ0
DQ13
DQ12
DQ24
CK
A9/A1
BA1/A5 BA2/A4
CAS*
CK*
CKE*
CS*
DQ9
DQ11
DQ14
DQ16
DQ19
DQ23
DQ25 DQ26 DQ27
DQ31
EDC1 EDC2
MF
RAS*
WCK23 WCK23*
WE*
ZQ
BA0/A2
DQ28 DQ29
DQ22
DQ21
DQ17
DQ15
DQ10
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DBI3*
DBI0*
DBI2*
DBI1*
BA3/A3
A8/A7
ABI*
RESET*
DQ18
DQ20
NC
A12/RFU/NC
DQ30
NC
(MF=1)
(1 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
IN
IN
BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
NC
NC
BI BI BI BI
IN IN IN IN
IN
IN
IN
IN
IN
IN
IN IN
IN IN
IN IN
IN IN IN IN
IN
IN
BI BI BI BI
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI BI
BI
BI
IN
IN
IN IN
BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
IN
IN IN
IN
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CK TERMINATION - D0
Power aliases required by this page:
- =PP1V35_S0_GPU_FBVDD
BOM options provided by this page:
NORMAL
MIRRORED
(NONE)
(NONE)
PLACE CLOSE TO UA600
Signal aliases required by this page:
Page Notes
CK TERMINATION - D1
85
113
85
113
6.3V
20% X5R
10UF
CA600
603-3
6.3V
CA601
X5R
20%
10UF
603-3
CA604
6.3V
20% X5R
4.7UF
402
20% X5R
4.7UF
6.3V
CA603
402
10UF
CA650
X5R
20%
6.3V 603-3
CA651
X5R
20%
6.3V
10UF
603-3
6.3V
20% X5R
4.7UF
402
CA653
X5R
6.3V
20%
4.7UF
CA654
402
1/20W
1%
MF
201
1K
RA604
1/20W
RA603
1% MF
201
PLACE_NEAR=UA600.J10:8.4MM
1K
1/20W
1%
MF
RA653
201
1K
PLACE_NEAR=UA650.J10:8.4MM
1%
MF
1/20W
201
120
RA650
PLACE_NEAR=UA650.J13:8.4MM
201
MF
1/20W
1%
40.2
RA602
PLACE_NEAR=UA600.J11:20MM
1/20W
1%
MF
40.2
RA601
201
PLACE_NEAR=UA600.J12:20MM
1%
40.2
MF
1/20W
RA652
201
PLACE_NEAR=UA650.J11:20MM
MF
1%
1/20W
RA651
201
40.2
PLACE_NEAR=UA650.J12:20MM
201
RA631
MF
1% 1/20W
1.33K
PLACE_NEAR=UA600.J14:8.4MM
85 89 118
201
RA634
MF
1% 1/20W
931
PLACE_NEAR=UA600.J14:8.4MM
1%
201
RA630
MF
549
1/20W
PLACE_NEAR=UA600.J14:8.4MM
201
MF
1% 1/20W
1.33K
RA633
PLACE_NEAR=UA600.U10:30MM
201
931
MF
1% 1/20W
PLACE_NEAR=UA600.U10:8.4MM
RA635
201
549
1%
RA632
1/20W MF
PLACE_NEAR=UA600.U10:8.4MM
85 89 118
6.3V
20% X5R
1UF
CA606
0201
1UF
6.3V
20% X5R
CA607
0201
6.3V
20% X5R
1UF
CA608
0201
6.3V
20% X5R
1UF
CA609
0201
6.3V
20% X5R
1UF
CA610
0201
6.3V
20% X5R
1UF
CA611
0201
6.3V
20%
1UF
CA612
X5R 0201
6.3V
20% X5R
1UF
CA613
0201
6.3V
20% X5R
1UF
CA614
0201
6.3V
20% X5R
1UF
0201
CA615
20%
6.3V X5R
1UF
CA656
0201
6.3V
20% X5R
1UF
CA657
0201
X5R
6.3V
20%
1UF
CA658
0201
20%
1UF
6.3V X5R
CA659
0201
20% X5R
1UF
6.3V
CA660
0201
6.3V
20% X5R
1UF
CA661
0201
6.3V
20% X5R
1UF
CA662
0201
X5R
1UF
6.3V
20%
CA663
0201
6.3V
20% X5R
1UF
CA664
0201
20%
6.3V X5R
1UF
CA665
0201
RA654
1%
1/20W
MF
201
1K
UA650
BGA
OMIT_TABLE
32MX32-1.5GHZ-MFL
K4G10325FG-HC03
32MX32-1.5GHZ-MFH
K4G10325FG-HC03
BGA
OMIT_TABLE
UA600
K4G10325FG-HC03
UA650
32MX32-1.5GHZ-MFL
BGA
OMIT_TABLE
UA600
OMIT_TABLE
BGA
K4G10325FG-HC03
32MX32-1.5GHZ-MFH
85 89
118
931
1/20W
1% MF
201
RA638
PLACE_NEAR=UA650.J14:8.4MM
1/20W
549
MF 201
1%
RA636
PLACE_NEAR=UA650.J14:8.4MM
1.33K
1/20W
1%
MF 201
RA637
PLACE_NEAR=UA650.J14:8.4MM
85 89
118
1/20W
1%
MF
931
201
RA641
PLACE_NEAR=UA650.U10:8.4MM
RA639
1% MF
549
201
1/20W
PLACE_NEAR=UA650.U10:8.4MM
1/20W
1% MF
1.33K
201
RA640
PLACE_NEAR=UA650.U10:8.4MM
CA690
0.01UF
10% 10V X5R-CERM 0201
CA691
0.01UF
10% 10V X5R-CERM 0201
0402
CERM
50V
10%
820PF
CA631
PLACE_NEAR=UA600.J14:8.4MM
0402
CERM
50V
10%
820PF
PLACE_NEAR=UA600.A10:30MM
CA640
0402
CERM
10%
820PF
CA633
PLACE_NEAR=UA600.U10:30MM
50V
0402
CERM
50V
10%
820PF
CA641
PLACE_NEAR=UA650.A10:8.4MM
0402
CERM
50V
10%
820PF
CA683
PLACE_NEAR=UA650.U10:8.4MM
820PF
10% 50V CERM 0402
CA681
PLACE_NEAR=UA650.J14:8.4MM
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85 89
113
85 89
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
112
PLACE_NEAR=UA600.J1:30MM
120
RA600
201
MF
1%
1/20W
85
113
85
113
85
113
85
113
85
113
6.3V
10% X5R
0.1UF
201
CA616
6.3V
10% X5R
0.1UF
CA617
201
6.3V
10% X5R
0.1UF
CA618
201
0.1UF
6.3V
10% X5R
CA619
201
6.3V
10% X5R
201
CA620
0.1UF
6.3V
10% X5R
0.1UF
CA621
201
6.3V
10% X5R
0.1UF
CA622
201
6.3V
10% X5R
0.1UF
CA623
201
6.3V
10% X5R
0.1UF
CA624
201
6.3V
10% X5R
0.1UF
CA625
201
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85 89
113
85 89
113
85
112
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
6.3V
10% X5R
0.1UF
CA667
201
6.3V
10% X5R
0.1UF
CA666
201
6.3V
10% X5R
CA671
0.1UF
201
6.3V
10% X5R
0.1UF
CA675
201
6.3V
10%
0.1UF
X5R
CA670
201
0.1UF
6.3V
10% X5R
CA674
201
6.3V
10% X5R
0.1UF
CA669
201
6.3V
10% X5R
0.1UF
CA673
201
201
CA668
10% X5R
0.1UF
6.3V
6.3V
10% X5R
0.1UF
CA672
201
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
85
113
SYNC_MASTER=D8_YAN
SYNC_DATE=04/09/2012
GDDR5 FRAME BUFFER D
FB_D0_VREFD
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_D1_CLK_N
FB_D0_ZQ
=PP1V35_S0_GPU_FBVDDQ
FB_SW_LEG_D
FB_D1_VREFC
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_D0_CKE_L
FB_D0_CLK_N
FB_D0_DQ<9> FB_D0_DQ<10>
FB_D0_DQ<15>
FB_D0_RESET_L
FB_D1_CLK_P
=PP1V35_S0_GPU_FBVDDQ
FB_SW_LEG_D
FB_D0_A<5>
FB_D0_A<0>
FB_D0_DQ<26>
=PP1V35_S0_GPU_FBVDDQ
FB_SW_LEG_D
=PP1V35_S0_GPU_FBVDDQ
FB_D0_A<7>
FB_D0_EDC<3>
FB_D0_EDC<1>
FB_D0_MF
FB_D0_RAS_L
FB_D0_WE_L
FB_D0_WCLK_N<1>
FB_D0_ABI_L
FB_D0_WCLK_P<1>
FB_D0_DQ<11>
FB_D0_DQ<8>
FB_D0_DQ<14>
FB_D0_DQ<13>
FB_D0_DQ<22>
FB_D0_DQ<21>
FB_D0_DQ<17>
FB_D0_EDC<2>
FB_D0_DQ<0>
FB_D0_DQ<12>
FB_D0_CS_L
FB_D0_CAS_L
FB_D0_DBI_L<0> FB_D0_DBI_L<3>
FB_D0_DQ<3>
FB_D0_DQ<16>
FB_D0_A<12>
FB_D0_DQ<20>
FB_D0_DQ<18>
FB_D0_DBI_L<2>
FB_D0_DQ<1> FB_D0_DQ<2>
FB_D0_DQ<4> FB_D0_DQ<5> FB_D0_DQ<6> FB_D0_DQ<7>
FB_D0_DQ<29>
FB_D0_A<2>
FB_D0_DQ<31>
FB_D0_DQ<19>
FB_D0_A<4>
FB_D0_A<1>
FB_D0_CLK_P
FB_D0_DQ<24> FB_D0_WCLK_P<0> FB_D0_WCLK_N<0>
FB_D0_A<6>
FB_D1_WCLK_P<0>
FB_D1_DQ<31>
FB_D1_DQ<14>
FB_D1_DBI_L<0>
FB_D1_DQ<27>
FB_D1_DQ<15>
FB_D1_DQ<13>
FB_D1_RAS_L
FB_D1_DQ<26>
FB_D1_DQ<25>
FB_D1_DQ<23>
FB_D1_DQ<22>
FB_D1_DQ<21>
FB_D1_DQ<20>
FB_D1_DQ<19>
FB_D1_DQ<18>
FB_D1_DQ<17>
FB_D1_DQ<16>
FB_D1_DQ<7>
FB_D1_DQ<2>
FB_D1_DQ<1>
FB_D1_DQ<0>
FB_D1_DBI_L<3>
FB_D1_DBI_L<1>
FB_D1_CS_L
FB_D1_CLK_P
FB_D1_ABI_L
FB_D1_DQ<30>
FB_D1_A<7> FB_D1_A<1>
FB_D1_DBI_L<2>
FB_D1_WE_L
FB_D1_A<4> FB_D1_A<3>
FB_D1_DQ<11>
FB_D1_DQ<10>
FB_D1_DQ<9>
FB_D1_DQ<8>
FB_D1_DQ<6>
FB_D1_DQ<5>
FB_D1_DQ<4>
FB_D1_DQ<3>
FB_D1_A<2>
FB_D1_CKE_L
FB_D1_A<0>
FB_D1_DQ<28>
FB_D1_EDC<2>
FB_D1_WCLK_N<1>
FB_D1_WCLK_P<1>
FB_D1_WCLK_N<0>
FB_D1_DQ<29>
FB_D1_A<5>
FB_D1_A<6>
FB_D1_CAS_L
FB_D0_VREFC FB_D0_VREFD
FB_D1_VREFC FB_D1_VREFD
FB_D0_EDC<0>
FB_D0_DQ<25>
FB_D0_DQ<30>
FB_D0_DQ<28>
FB_D0_DQ<23>
FB_D1_DQ<12>
FB_D0_DQ<27>
FB_D0_DBI_L<1>
FB_D1_CLK_N
FB_D1_RESET_L
FB_D1_EDC<1>
FB_D1_EDC<0>
FB_D1_SEN
FB_SW_LEG_D
FB_D0_CLK_N
FB_D0_A<3>
FB_D1_CK_MID
=PP1V35_S0_GPU_FBVDDQ
FB_D0_SEN
FB_D0_CLK_P
FB_D0_CK_MID
=PP1V35_S0_GPU_FBVDDQ
=PP1V35_S0_GPU_FBVDDQ
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_D0_VREFC
FB_D1_EDC<3>
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.25 MM
FB_D1_VREFD
FB_D1_A<12>
FB_D1_DQ<24>
FB_D1_MF
FB_D1_ZQ
prefsb
051-9505
8.0.0
106 OF 144
89 OF 123
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1 21 2
1 21 2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
J1
J10
L3
K5
K10
N2
D5
P4 P5
J2
C13 R13
U5
N4
H4
J3
H11
B2 E4 E2 F4
A11 A13 B11 B13
H10
K11
L12
P13
H5
K4
J11
M4
J4
J12
G12
D13
P2
A4 A2 B4
F2
E11
U11 U13 T11 T13 N11 N13 M11 M13
U2 T4
C2
R2
G3
E13
F13
T2
D2
F11
M2
U4
D4
J13
J5
A5
H5
J10
P5
P4
C2
R2
K4
U4
N13
N11
A4
J12
K5
H10 H11
G3
J11
J3
L12
U13
T13
M11
A11
B13
F13
A2 B4 B2
F2
R13 C13
J1
L3
D4 D5
G12
J13
K11
E4 E2
F11
E13
A13
M13
T11
U11
M2
M4
N2
N4
T2
T4
U2
D2
P2
D13
P13
K10
H4
J4
J2
B11
E11
A5 J5
F4
U5
U14
U12
U3
U1
R14
R12
R11
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
K2
H13
H2
F10
F5
E1
C14
C11
C4
C3
C1
A14
A1
T10
T5
P10
L10
L5
K14
K1
H14
H1
G10
G5
D10
B10
B5
U10
A10
J14
T14
T12
T3
T1
P14
P12
P3
P1
N10
N5
M14
M12
M3
M1
L13
L2
K12
K3
H12
H3
G13
G2
F14
F12
F3
F1
E10
E5
D14
D12
D3
D1
R10
R5
P11
L14
L11
L4
L1
G14
G11
G4
G1
D11
C10
C5
B1
B3 B12 B14
A12
A3
E12 E14
E3
C12
C12
C11
C4
C3
C1
A14
U14
U12
U3
U1
R14
R12
R11
A12
R4
R3
R1
N14
N12
N3
N1
M10
M5
K13
A3
K2
H13
H2
F10
E14
E12
E3
E1
C14
A1
K14
K1
H14
H1
G10
G5
D10
B10
T10
T5
P10
L10
L5
B5
U10
A10
J14
E5
D14
D12
D3
D1
B14
T14
T12
T3
T1
P14
P12
P3
B12
P1
N10
M14
F14
F12
F3
F1
E10
B1
L4
L1
G14
G11
G4
G1
D11
C10
R10
R5
P11
L14
L11
N5
M12
M3
M1
L13
L2
K12
B3
K3
H12
H3
G13
G2
F5
C5
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
89
118
85 89
113
6
84
85 86
87 88
89 94
89
118
85 89 113
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
89
118
89
118
89
118
89
118
85 89
113
112
6 84
85
86 87 88 89 94
85 89 113
112
6
84 85 86 87 88 89 94
6
84 85 86 87 88 89 94
89
118
89
118
IFPE_IOVDD
IFPD_L2
IFPD_L2*
IFPA_IOVDD
IFPB_TXC
IFPA_TXD2
IFPA_TXD3*
IFPA_TXD3
IFPA_TXD2*
IFPA_TXD1
IFPA_TXD1*
IFPA_TXD0
IFPB_TXD4*
IFPB_TXD4
IFPB_TXC*
IFPD_AUX_I2CX_SDA*
IFPEF_PLLVDD
IFPEF_RSET
IFPD_IOVDD IFPD_IOVDD
GPIO17
GPIO16
IFPF_IOVDD IFPF_IOVDD
IFPE_IOVDD
IFPF_L0
IFPF_L1
IFPF_L0*
IFPF_L2
IFPF_L1*
IFPF_L2*
IFPF_L3
IFPF_AUX_I2CZ_SCL
IFPF_L3*
GPIO18
IFPF_AUX_I2CZ_SDA*
IFPE_L0
IFPE_L0*
IFPE_L1*
IFPE_L1
IFPE_L2*
IFPE_L2
IFPE_L3*
IFPE_L3
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA*
IFPD_L0
IFPD_L0*
IFPD_L3
IFPD_AUX_I2CX_SCL
IFPC_L2*
IFPC_L3
IFPC_L3*
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA*
GPIO14
IFPB_TXD7
IFPB_TXD7*
IFPA_TXD0*
IFPA_TXC
IFPA_TXC*
IFPB_TXD6*
IFPB_TXD6
IFPC_L0
IFPC_L0*
IFPC_L1
IFPC_L1*
IFPC_L2
IFPB_TXD5
IFPB_TXD5*
IFPAB_RSET
IFPD_RSET
IFPC_IOVDD IFPC_IOVDD
IFPD_PLLVDD
GPIO15
IFPD_L3*
IFPD_L1
IFPD_L1*
IFPA_IOVDD
IFPB_IOVDD IFPB_IOVDD
IFPC_RSET
IFPAB_PLLVDD
IFPC_PLLVDD
IFPAB
IFPD
IFPC
SYM 6 OF 14
IFPEF
NC
NC
NC
NC NC
NC NC
NC NC
NC NC
NC
NC
NC
NC
NC
NC
NC NC
NC NC
NC NC
NC
NC
NC
NC
NC
NC NC
OUT OUT
OUT OUT
OUT OUT
OUT OUT
BI BI
OUT OUT
OUT OUT
OUT OUT
OUT OUT
BI BI
OUT OUT
OUT OUT
OUT OUT
OUT OUT
NC
NC
BI BI
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Place under GPU
ESR = 0.05OHM
Place under GPU
DISABLE PHYS A, B & C FOR D8
PD FOR AUX CHANNELS (FOR NVIDIA)
PD FOR RSET
IFPX PLLVDD
Place near GPU
Place near GPU
IFP EF IOVDD
PLACE BELOW GPU NEAR DISPLAY SECTION
Place near GPU
Place under GPU
IFP CD IOVDD
ESR = 0.05OHM
RA713
MF
100K
201
1% 1/20W
RA714
201
MF
1%
100K
1/20W
RA717
1% 1/20W MF 201
100K
RA718
MF
1% 1/20W
201
100K
PLACE_NEAR=UA000.BE12:5MM
RA706
1K
201
1/20W
1%
MF
PLACE_NEAR=UA000.BF11:5MM
1/20W
201
RA707
1%
MF
1K
FERR-220-OHM-2A
CRITICAL
0603
LA706
PLACE_NEAR=UA000.BC8:20MM
PLACE_NEAR=UA000.BA14:20MM
CRITICAL
LA705
0603
FERR-220-OHM-2A
CA758
10%
0.1UF
6.3V X6S 0201
PLACE_NEAR=UA000.BA15:3.8MM
10%
0.1UF
0201
X6S
6.3V
CA757
PLACE_NEAR=UA000.BA14:3.8MM
MF
1/20W
RA703
10K
1%
201
1% 1/20W
201
MF
10K
RA719
0.1UF
10%
CA732
6.3V X6S 0201
PLACE_NEAR=UA000.BC9:5MM
CA731
0.1UF
10%
6.3V X6S 0201
CA712
0.1UF
X6S 0201
10%
6.3V
PLACE_NEAR=UA000.BB9:3.8MM
BGA
OMIT_TABLE
CRITICAL
GK104
GPU
UA000
75
111
75
111
75
111
75
111
75
111
75
111
75
111
75
111
90
90
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
90
90
36
111
36
111
36
111
36
111
36
111
36
111
36
111
36
111
RA716
1/20W
1%
201
100K
MF
RA715
1/20W
100K
1%
MF 201
75 90
111
75 90
111
0402
20%
6.3V
X6S
4.7UF
CA719
PLACE_NEAR=UA000.BB11:20MM
0402
CA725
4.7UF
20%
X6S
6.3V
PLACE_NEAR=UA000.BA14:20MM
0402
4.7UF
20%
X6S
6.3V
CA733
PLACE_NEAR=UA000.BC8:20MM
4.7UF
X6S
6.3V
CA734
0402
20%
PLACE_NEAR=UA000.BD8:20MM
0402
10%
6.3V X7R
1UF
CA756
PLACE_NEAR=UA000.BA14:20MM
0402
CA715
X7R
10%
6.3V
1UF
PLACE_NEAR=UA000.BB9:20MM
CA735
1.0UF
20% 4V X6S
0201
PLACE_NEAR=UA000.BD8:20MM
1.0UF
20% 4V X6S
0201
CA736
PLACE_NEAR=UA000.BD9:20MM
201
1/20W
1%
RA701
MF
10K
1% 1/20W
10K
201
MF
RA702
10K
RA704
1/20W
1%
MF 201
LA704
330-OHM-1.2A
CRITICAL
0603
CA718
10%
0.1UF
6.3V X6S 0201
PLACE_NEAR=UA000.BB11:3.8MM
PLACE_NEAR=UA000.BD8:5MM
CA738
6.3V
10%
0.1UF
X6S 0201
PLACE_NEAR=UA000.BC8:5MM
CA737
0.1UF
10%
0201
X6S
6.3V
SYNC_MASTER=D8_YAN
SYNC_DATE=04/09/2012
KEPLER EDP/DP/GPIO
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2mm
PP1V05_GPU_IFPEF_IOVDD_FLT
VOLTAGE=1.05V
PP1V05_GPU_IFPD_IOVDD_FLT
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 MM
VOLTAGE=3.3V
PP3V3_GPU_IFPX_PLLVDD_FLT
=PP1V05_S0_GPU_IFPCD_IOVDD
DP_TBTSNK0_EG_AUXCH_P
=PP3V3_S0_GPU_IFPX_PLLVDD
GPU_IFPB_IOVDD
DP_TBTSNK1_EG_AUXCH_N
MAKE_BASE=TRUE
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_P
MAKE_BASE=TRUE
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK0_AUXCH_C_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_TBTSNK0_AUXCH_C_P
DP_INT_EG_ML_P<2>
DP_INT_EG_ML_N<2>
DP_INT_EG_HPD
DP_TBTSNK1_HPD
DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK1_ML_C_P<1>
DP_TBTSNK1_ML_C_N<0>
DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_ML_C_N<1>
DP_TBTSNK1_ML_C_N<2>
DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_ML_C_N<3>
DP_TBTSNK0_HPD
DP_TBTSNK1_EG_AUXCH_N
DP_TBTSNK0_ML_C_P<0>
DP_TBTSNK0_ML_C_N<0>
DP_TBTSNK0_ML_C_N<1> DP_TBTSNK0_ML_C_P<1>
DP_TBTSNK0_ML_C_N<2>
DP_TBTSNK0_ML_C_P<2>
DP_TBTSNK0_ML_C_N<3> DP_TBTSNK0_ML_C_P<3>
DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
DP_INT_EG_ML_P<0>
DP_INT_EG_ML_P<1>
DP_INT_EG_ML_N<1>
GPU_IFPC_PLLVDD
DP_TBTSNK0_EG_AUXCH_N
DP_INT_EG_AUX_N
DP_TBTSNK1_EG_AUXCH_N
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
DP_INT_EG_AUX_P
DP_INT_EG_AUX_P
DP_INT_EG_ML_N<0>
DP_INT_EG_AUX_N
DP_INT_EG_ML_N<3> DP_INT_EG_ML_P<3>
GPU_IFPA_IOVDD
=PP1V05_S0_GPU_IFPEF_IOVDD
GPU_IFPC_IOVDD
GPU_IFPAB_PLLVDD
PLACE_NEAR=UA000.BD9:3.8MM
PP3V3_GPU_IFPX_PLLVDD_FLT
IFPD_RSET
PP3V3_GPU_IFPX_PLLVDD_FLT
IFPEF_RSET
DP_TBTSNK0_EG_AUXCH_P
prefsb
051-9505
8.0.0
107 OF 144
90 OF 123
1
2
1
2
1
2
1
2
1
2
1
2
21
21
2
1
2
1
1
2
1
2
2
1
2
1
2
1
BD8
BH11
BG11
BA17
BH18
BF17
BC17 BD17
BE17
BD15
BC15
BH14
BJ14 BJ15
BG18
BF4
BB9
BF11
BA14 BA15
AW6
AW2
BC9 BD9
BC8
BF9
BJ9
BE9
BH8
BJ8
BG8
BJ6
BJ4
BH6
AW3
BH4
BE8
BF8
BG6 BF6
BE6 BD6
BE5 BD5
BG3
BH3
BG12
BH12
BG9
BG4
BC12
BD11
BE11
BG2
BF2
AW5
BJ17
BJ18
BG14
BC18
BD18
BG17 BH17
BC14
BD14
BF14
BE14
BD12
BG15
BH15
BE18
BE12
BA11 BA12
BB11
AV6
BH9
BJ12
BJ11
BB17
BA18 BB18
BB14
BB15
BB12
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
21
2
1
2
1
2
1
90
6
90
6
118
90 36
111
36
111
90
36
111
36
111
75
117
36
111
36
111
118
90
75 90
111
90
90
90
75 90
111
118
6
118
118
90
118
90
118
90
MULTI_STRAP_REF0_GND
STRAP3 STRAP4
STRAP1 STRAP2
STRAP0
XTAL_SSIN XTAL_IN
LXS_PLLVDD
GPCPLL_AVDD
GPCPLL_AVDD
VID_PLLVDD
SP_PLLVDD
CEC
PGOOD
BUFRST*
ROM_SCLK
ROM_SO
ROM_SI
XTAL_OUT
ROM_CS*
GPIO24
XTAL_OUTBUFF
GPIO22 GPIO23
GPIO21
GPIO20
GPIO19
GPIO12 GPIO13
GPIO7
GPIO9
GPIO0
I2CB_SDA
I2CC_SDA
I2CB_SCL
I2CC_SCL
I2CS_SDA
I2CS_SCL
GPIO2 GPIO3
GPIO1
GPIO6
GPIO8
GPIO5
GPIO4
GPIO10 GPIO11
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TRST*
THERMDN THERMDP
MISC_1
MISC_2
XTAL/PLL
SYM 7 OF 14
NC
NC
NC NC
GND
THRM
VCC
CS*
WP*
SI
SCLK
SO
HOLD*
PAD
BI
OUT
OUT
NC
08
NC
D
G S
IN
OUT
BI
OUT
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
OUT
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU JTAG
GPU overtemp masking
GP
GP
GPIOs
GPU VBIOS ROM
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
Native Func
GP
GP
ISOLATION R’S FOR GPU INT TEMP SENSE.
GP
197S0464
GPU XTAL 27 MHZ
CONFIG STRAPS - MLS
USE 1% RESISTOR FOR ACCURACY
CKPLUS_WAIVE=PDIFPR_BADTERM CKPLUS_WAIVE=NDIFPR_BADTERM
GK104
UA000
BGA
GPU
1%
10K
RA818
1/20W
MF
201
1%
1/20W
MF
10K
RA821
201
RA817
10K
201
1/20W
5%
MF
GPU_ROM:YES
10%
CA804
6.3V
201
X5R
0.1UF
1/20W
5%
RA824
GPU_ROM:YES
0
MF
201
PLACE_NEAR=UA000.BA3:9.5MM
RA827
33
5%
GPU_ROM:YES
201
1/20W
MF
PLACE_NEAR=UA000.BA2:30MM
GPU_ROM:YES
RA826
5% MF
33
201
1/20W
GPU_ROM:YES
1/20W
MF
5%
201
10K
RA823
NOSTUFF
RA828
MF
5%
0
1/20W
201
NOSTUFF
MX25L1005CMI-12G
USON
CRITICAL
1MBIT
UA802
PLACE_NEAR=UA000.BA5:8MM
MF
RA822
33
201
5%
1/20W
GPU_ROM:YES
PLACE_NEAR=UA802.2:8MM
RA825
5%
33
1/20W
MF
GPU_ROM:YES
201
47
122
91 99
118
RA832
201
MF5%01/20W
10K
RA830
201
MF
1/20W
5%
RA829
5%
1/20W
201
MF
10K
NOSTUFF
RA836
10K
5%
1/20W
MF
201201
MF
1/20W
5%
10K
RA835
47 48
122
UA801
74LVC1G08
SOT891
RA820
10K
201
MF
1/20W
5%
VESM
QA801
SSM3K15AMFVAPE
26 83
118
10%
201
X5R
6.3V
0.1UF
CA801
1/20W MF 201
1%
15K
RA802
MF
20K
1%
201
RA804
1/20W
OMIT_TABLE
RA805
1/20W
201
MF
1%
10K
RA807
45.3K
1/20W
1%
201
MF
1%
15K
1/20W
201
MF
RA812
OMIT_TABLE
MF
RA813
10K
1/20W
1%
201
0
1/20W
MF5%
RA837
201
96
115
76
111
76
111
1/20W
NOSTUFF
2.2K
RA840
201
1%
MF
NOSTUFF
RA841
2.2K
1%
MF 201
1/20W
MF
RA842
1%
2.2K
1/20W
201
MF
1%
201
RA843
1/20W
2.2K
1/20W05% MF
201
RA844
0
RA845
5%
1/20WMF201
50
112
50
112
RA850
0
5% MF
201
1/20W
1/20W0201
5%
RA851
MF
1/20W
5% MF
RA852
0
201
1/20W
RA853
0
5% MF
201
0
RA854
MF5%
1/20W
201
1/20W
RA855
0
MF5%
201
96
115
96
115
96
115
96
115
96
115
96
115
RA856
10K
5%
1/20W
MF
201
84 85 91
118
GPU_ROM:YES
RA859
MF
1/20W
201
5%
10K
RA871
MF
201
10K
1/20W
1%
NOSTUFF
96
115
RA860
0
201
5%
1/20W
MF
PLACE_NEAR=UA000.BB7:5MM
201
RA819
MF
1/20W
1%
40.2K
201
1/20W
5%
MF
RA861
10K
MF
5% 1/20W
201
10K
RA862
5% 1/16W MF-LF 402
180
RA863
RA864
270
1%
201
MF
1/20W
RA801
201
MF
1/20W
4.99K 1%
NOSTUFF NOSTUFF
1/20W
1%
4.99K
MF 201
RA803 RA809
NOSTUFF
201
1/20W MF
1%
4.99K
MF
1%
4.99K
1/20W
201
NOSTUFF
RA811
NOSTUFF
201
MF
RA815
4.99K
1/20W
1%
RA806
1%
4.99K
201
NOSTUFF
MF
1/20W
201
NOSTUFF
4.99K 1%
RA808
1/20W MF MF
1/20W
RA814
1%
4.99K
NOSTUFF
201201
1/20W
4.99K 1%
MF
RA810
45.3K
1/20W
1%
201
MF
RA816
PLACE_NEAR=YA801.1:2MM
NP0-C0G-CERM
18PF
5%
CA802
0201
25V
0201
5%
18PF
NP0-C0G-CERM
25V
CA803
PLACE_NEAR=YA801.3:2MM
201
MF1%1/20W
100K
RA846
201
MF1%1/20W
100K
RA847
RA865
NOSTUFF
10K
201
1/20W
5%
MF
27MHZ-30PPM-18PF-60OHM
2.50X2.00MM-SM
YA801
CRITICAL
KEPLER GPIO/STRAPPING
SYNC_DATE=07/27/2012
SYNC_MASTER=D8_YAN
FB:1G_SAMSUNG
1
RES,MF,20KOHM,1,1/20W,0201
RA804
118S0175
RES,MF,15KOHM,1,1/20W,0201
118S0105
1
FB:1G_HYNIX
RA804
RES,MF,20KOHM,1,1/20W,0201
1 RA812
118S0175
GPU:104GTX
RES,MF,45.3KOHM,1,1/20W,0201
1 RA804
FB:2G_SAMSUNG
118S0385
RA8041
118S0315
FB:2G_HYNIX
RES,MF,34.8KOHM,1,1/20W,0201
RA812
118S0105
1
RES,MF,15KOHM,1,1/20W,0201
GPU:104GT
RA812
118S0105
1
RES,MF,15KOHM,1,1/20W,0201
GPU:104GT2
=PP3V3_S0_GPU
GPU_ROM_SO
MAKE_BASE=TRUE
GPU_LCD_BKLT_PWM
GPU_GPIO_7
GPU_GPIO_6
GPU_SSC_SMB_DAT
DP_TBTSNK1_DDC_DATA
GPU_SMB_DAT
GPU_RESET_L
GPU_OSC_27M_XTAL_P GPU_OSC_27M_XTAL_N
REG_GPUCORE_VID6
FBVDD_ALTVO
GPU_SMB_CLK_R
GPU_GPIO_1
GPU_GPIO_4
GPU_GPIO_12
GPU_GPIO_8
GPU_GPIO_5
GPU_GPIO_13
GPU_GPIO_19
GPU_BUFRSTN
GPU_MLS_STRAP2
GPU_MLS_STRAP1
GPU_JTAG_TDO
GPU_JTAG_TRST_L
GPU_JTAG_TDI
GPU_JTAG_TCK
=PP3V3_S0_GPU
=PP3V3_S0_GPU
DP_TBTSNK1_DDC_CLK
GPU_VCORE_VID4
SMC_GFX_OVERTEMP_R_L
GPU_VCORE_VID6
GPU_SMB_CLK
GPU_SSC_SMB_CLK
GPU_GPIO_3
GPU_GPIO_9
GPU_GPIO_21
GPU_ROM_SI
GPU_ROM_SO
MAKE_BASE=TRUE
GPU_VCORE_VID0
GPU_GPIO_22
GPU_MLS_STRAP3
GPU_MLS_STRAP3
GPU_MLS_STRAP4
GPU_ROM_SI
GPU_ROM_SCLK
=PP3V3_S0_SMC
SMC_GFX_OVERTEMP_Q
GPU_SMB_DAT_R
GPU_VCORE_VID5
GPU_VCORE_VID3
SMC_GFX_THROTTLE_R_L
GPU_PSI_L_R
SMC_GFX_OVERTEMP
SMC_GFX_OVERTEMP_R_L
=PP3V3_S0_GPU
REG_GPUCORE_VID5
REG_GPUCORE_VID3
REG_GPUCORE_VID4
REG_GPUCORE_VID1
REG_GPUCORE_VID2
GPU_PSI_L
GPU_ALT_VREF
=PP3V3_S0_GPU
MULTI_STRAP_REF
GPU_XTAL_OUTBUFF
GPU_ROM_SO_R
GPU_ROM_HOLD_L
FBVDD_ALTVO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO23_RESERVED
NO_TEST=TRUE
NC_SWAP_RDY
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO20_RESERVERD
GPU_VCORE_VID6
MAKE_BASE=TRUE
NC_EG_BKLT_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_HDMI_EG_HPD
MAKE_BASE=TRUE
NO_TEST=TRUE
GPU_ROM_SI_R
GPU_GPIO_24
GPU_GPIO_23
GPU_XTAL_SSIN
PP1V05_S0_GPU_SP_PLLVDD_FLT
PP1V05_S0_GPU_PLLVDD_FLT
GPU_MLS_STRAP0
GPU_VCORE_VID2
GPU_GPIO_11
GPU_GPIO_20
GPU_VCORE_VID1
GPU_VCORE_VID0
SMC_GFX_THROTTLE_L
REG_GPUCORE_VID7
GPU_VCORE_VID1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GPU_VCORE_VID2
MAKE_BASE=TRUE
GPU_VCORE_VID3
MAKE_BASE=TRUE
GPU_VCORE_VID4
MAKE_BASE=TRUE
GPU_VCORE_VID5
GPU_PSI_L_R
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_GFX_OVERTEMP_R_L
MAKE_BASE=TRUE
SMC_GFX_THROTTLE_R_L
MAKE_BASE=TRUE
GPU_ALT_VREF
GPU_GPIO_2
GPU_GPIO_0
MAKE_BASE=TRUE
NC_EG_LCD_PWR_EN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_RASTER_SYNC
NO_TEST=TRUE
GPU_GPIO_10
GPU_MLS_STRAP4
GPU_MLS_STRAP2
GPU_MLS_STRAP1
GPU_MLS_STRAP0
GPU_JTAG_TMS
GPU_ROM_CS_L
GPU_ROM_CS_L_R
=PP3V3_S0_GPU_VDD33
GPU_ROM_SCLK_R
GPU_ROM_WP_L
GPU_ROM_SCLK
prefsb
051-9505
8.0.0
108 OF 144
91 OF 123
BB7
BA8 BB6
AW8 BA7
BA6
BB3 BB2
AT11
AD11
Y39
AW28
AW27
AV8
AV9
AW9
BA2
BA4
BA5
BA1
BA3
AT2
BB1
AR9 AV3
AT3
AV5
AT8
AV4 AT5
AT10
AW7
AT9
BB4
BD1
BB5
BD2
BE3
BF3
AV1 AW4
AT7
AT1
AV7
AT4
AW1
AT6 AV2
BJ20
BH20
BG20
BF20
BF21
BE1 BF1
1 2 1 2
1
2
2
1
1
2
1 2
1 2
1
2
1
2
49
8
1
3
5
6
2
7
1 2
1 2
1 2
1
2
1
2
1
2
1
2
3
6
2
1
4
5
1
2
1
2
3
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1
2
1
2
1 2 1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1
2
1 2
1 2
1 2
121
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
1 2
1 2
1
2
42
1 3
6
83 91 92 95 96
91
118
75
111
112
112 112
118
91
118
91
118
118
118
118
112
6
83 91 92 95 96
6
83 91 92 95 96
91
115
91
122
91
115
112
91 118
91
118
91
115
91
118
91
118
91
118
91
118
91
112
6
48 51
122
91
115
91
115
91
122
91
115
91
122
6
83 91 92 95 96
6
83 91 92 95 96
118
118
91 99
118
91
115
118
95
84 95
91
118
91
115
91
115
91
115
91
115
91
115
91
115
91
115
91
115
91
115
91
122
91
122
84 85 91
118
91
118
91
118
91
118
91
118
118
118
118
6
112
118
91
112
SPARE SPARE
MIOB_CLKOUT
MIOB_CLKIN
MIOA_CAL_PU_GND
DACA_RSET
DACA_VREF
I2CA_SDA
VDD3V3
MIOA_VSYNC
MIOA_DE
MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4
MIOA_D8
MIOA_D5
MIOA_D11
MIOA_CTL3
MIOA_D7
MIOA_D9
DACA_BLUE
MIOA_D0
MIOB_VSYNC
MIOB_HSYNC
3V3MISC
VDD3V3
MIOB_D10
MIOB_D8
MIOB_D6
MIOB_D4
MIOB_D3
MIOB_D2
MIOA_CLKIN
MIOA_CAL_PD_VDDQ
VDD3V3
VDD3V3
MIOA_VREF
DACA_VDD I2CA_SCL
DACA_HSYNC DACA_VSYNC
DACA_GREEN
DACA_RED
MIOA_D6
MIOA_D10
MIOA_HSYNC
MIOA_CLKOUT
MIOA_CLKOUT*
MIOB_CLKOUT*
MIOB_DE
MIOB_CTL3
MIOB_D11
MIOB_D9
MIOB_D7
MIOB_D5
MIOB_D1
MIOB_D0 VDD3V3 VDD3V3
VDD3V3
VDD3V3
3V3AUX_NC
3V3MISC
MIOB_VREF
MIOB_CAL_PU_GND
MIOB_CAL_PD_VDDQ
NC NC NC
SPARE
SPARE
SPARE
SPARE SPARE SPARE SPARE
DACA
SYM 8 OF 14
NC/3V3
MIOB
MIOA
OUT
BI
NC
NC
NC NC
NC NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
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Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
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THE POSESSOR AGREES TO THE FOLLOWING:
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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACE UNDER GPU
PLACE UNDER GPU
D8 GK104: DO I2CA AND I2CB PINS REQUIRE EXTERNAL PULLUPS? CA_DET RDAR://11010937
PLACE NEAR GPU
GK104
UA000
BGA
GPU
76
111
76
111
NOSTUFF
RA901
2.2K
1/20W
201
MF
1% 1%
2.2K
MF 201
RA902
NOSTUFF
1/20W
RA903
201
5% MF
1/20W
10K
6.3V X6S 0201
10%
0.1UF
CA903
PLACE_NEAR=UA000.AW15:3.8MM
CA904
0.1UF
X6S
10%
6.3V
0201
PLACE_NEAR=UA000.AY15:3.8MM
6.3V X6S 0201
10%
0.1UF
CA905
NOSTUFF
PLACE_NEAR=UA000.AW15:3.8MM
CA906
6.3V
10%
0.1UF
X6S 0201
NOSTUFF
PLACE_NEAR=UA000.AY15:3.8MM
0402
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6.3V X7R
1UF
CA902
PLACE_NEAR=UA000.AW15:21.6MM
CA908
1UF
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6.3V
10%
0402
PLACE_NEAR=UA000.AY17:3.8MM
CA907
1UF
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10%
0402
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NOSTUFF
CA909
1UF
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10%
0402
PLACE_NEAR=UA000.AY17:3.8MM
4.7UF
6.3V
CA901
0402
X6S
20%
PLACE_NEAR=UA000.AW15:21.6MM
201
RA905
100K
1% 1/20W MF
201
RA906
100K
1% 1/20W MF
KEPLER MISC
SYNC_MASTER=D8_YAN
SYNC_DATE=04/09/2012
=PP3V3_S0_GPU
DP_TBTSNK0_DDC_CLK
=PP3V3_S0_GPU
=PP3V3_S0_GPU
GPU_DACA_VDD33
=PP3V3_S0_GPU
=PP3V3_S0_GPU_MISC
DP_TBTSNK0_DDC_DATA
prefsb
051-9505
8.0.0
109 OF 144
92 OF 123
AM10 AN10
AN3
AM5
AJ8
AY20
AW20
BD3
AJ10
AK8 AM4
AJ2 AJ6 AJ5 AK4
AM3
AJ4
AK6
AK5
AK3
AK7
AW21
AJ7
AN7
AM7
AW17
AW15
AN6
AN1
AR7
AN5
AN9
AM9
AJ3
AJ9
AK11
AJ11
AM1
AW18
BD4
BA20 AY18
BA21
AY21
AK9
AM2
AJ1
AK1 AK2
AN2
AR3
AR8
AR2
AR6
AN4
AN8
AM6
AM8 AN11 AR11
AM11
AY15
AW14
AY17
AR1
AR4
AR5
BE15 BF12 BF18
AK10
AY14
AR10
BC11 BF15
BG5 BJ5
1
2
1
2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
6
83 91 92 95 96
6
83 91 92 95 96
6
83 91 92 95 96
6
83 91 92 95 96
6
GND_SENSE
VDD_SENSE
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD
VDD
VDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD
VDD VDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD
VDD
VDD
VDD
VDD
VDD_1/2
SYM 9 OF 14
VDD
VDD
VDD VDD VDD VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD VDD VDD
SYM 10 OF 14
VDD_2/2
OUT OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACE UNDER GPU
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PLACE UNDER GPU
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- =PPVCORE_S0_GPU
Signal aliases required by this page:
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PLACE NEAR GPU W/ 35MM FROM GPU CENTER
UA000
BGA
GK104
GPU
GPU
GK104
BGA
UA000
PLACE_NEAR=UA000.AT40:42MM
CRITICAL
CB167
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2V
20%
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CASE-D2-SM
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20%
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CB168
CRITICAL
CASE-D2-SM
POLY
330UF-0.006OHM
2V
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20%
PLACE_NEAR=UA000.AT40:35MM
CRITICAL
CASE-D2-SM
20%
330UF-0.006OHM
2V POLY
CB166
PLACE_NEAR=UA000.AT40:35MM
96
115
96
115
5%
100
MF 201
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1/20W
RB102
RB101
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CB105
0402
6.3V X6S
20%
4.7UF
CB101
4.7UF
20%
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6.3V
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6.3V X6S 0402
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4.7UF
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6.3V
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CB139CB138
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CB137
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20%
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6.3V
0402
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20%
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CB136CB135
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6.3V X6S
20%
4.7UF
CB134
4.7UF
20%
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6.3V
0402
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20%
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6.3V
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20%
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6.3V
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4.7UF
20%
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6.3V
0402
CB130
4.7UF
20%
X6S
6.3V
0402
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4.7UF
0402
6.3V X6S
20%
CB128
0402
6.3V X6S
20%
4.7UF
CB127
0402
6.3V X6S
20%
4.7UF
CB126
0402
6.3V X6S
20%
4.7UF
6.3V
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20%
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CB124
6.3V X6S
20%
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0402
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CB122
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CB173
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CB174
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CB175
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CB176
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CB177
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CB178
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CB179
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CB180
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20% 4V X6S-CERM 0603
CB181
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CB141
1.0UF
20% 4V X6S
CB142
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1.0UF
20% 4V X6S
CB143
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20% 4V X6S
CB144
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1.0UF
20% 4V X6S
CB145
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20% 4V X6S
CB146
0201
1.0UF
20% 4V X6S
CB147
0201
1.0UF
20% 4V X6S
CB148
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1.0UF
20% 4V X6S
CB149
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1.0UF
20% 4V X6S
CB150
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20% 4V X6S
CB151
0201
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20% 4V X6S
CB152
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CB153
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CB154
0201
1.0UF
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CB155
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CB156
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1.0UF
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CB157
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CB158
0201
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CB159
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CB160
0201
1.0UF
20% 4V X6S
CB161
10UF
20% 4V X6S 0402
10UF
20% 4V X6S 0402
CB162
10UF
20% 4V X6S 0402
CB163
10UF
20% 4V X6S 0402
CB164
SYNC_MASTER=D8_YAN
KEPLER CORE POWER
SYNC_DATE=04/09/2012
=PPVCORE_S0_GPU
MIN_LINE_WIDTH=0.41 MM MIN_NECK_WIDTH=0.10 MM VOLTAGE=1.0V
VSNS_GPU_VDD
=PPVCORE_S0_GPU
MIN_LINE_WIDTH=0.41MM MIN_NECK_WIDTH=0.10 MM VOLTAGE=0V
VSNS_GPU_VSS
prefsb
051-9505
8.0.0
111 OF 144
93 OF 123
AW23
AY23
AH31 AJ14 AJ16 AJ18 AJ20 AJ22 AJ24 AJ26 AJ28 AJ30 AJ32 AK15 AK17 AK19 AK21
AK25 AK27 AK29 AK31 AL14 AL16 AL18 AL20 AL22 AL24 AL26 AL28 AL30 AL32 AM15 AM17 AM19 AM21 AM23 AM25 AM27 AM29 AM31 AM32 AN39 AP39 AR39 AR40 AR41 AT39 AT40 AT41 AU39 AU41 AU42 AV41 AV42 AV43 AV44 AW35 AW36 AW37 AW41 AW42 AW43 AW44 AW45 AY36 AY42 AY45 BA36 BA37 BA38 Y31
AD19
AB15
AC32
AB19 AB21 AB23 AB25 AB27 AB29 AB31 AC14 AC16 AC18 AC20 AC22 AC24
AC28
AD15 AD17
AD23 AD25 AD27 AD29 AD31 AE14 AE16 AE18 AE20 AE22 AE24 AE26 AE28 AE30 AE32 AF15 AF17 AF19 AF21 AF23 AF25 AF27 AF29 AF31 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AG28 AG30 AG32 AH15 AH17 AH19 AH21 AH23 AH25 AH27 AH29
AA14 AA16 AA18 AA20 AA22 AA24 AA26 AA28 AA30 AA32
AB17
AK23
AC26
AC30
AD21
BJ48
R16
U14 U16 U18 U20
Y29
Y27
Y25
Y23
Y21
Y19
Y17
Y15
W32
W30
W28
W26
W24
W22
W20
W18
W16
W14
V31
V29
V27
V25
V23
V21
V19
V17
V15
U32
U30
U28
U26
U24
U22
T31
T29
T27
T25
T23
T21
T19
T17
T15
R32
R30
R28
R26
R24
R22
R20
R18
R14
P31
P29
P27
P25
P23
P21
P19
P17
P15
BJ47
BJ46
BJ45
BJ44
BJ42
BJ41
BJ39
BH49
BH48
BH47
BH46
BH45
BH44
BH43
BH42
BH41
BH40
BH39
BG49
BG48
BG47
BG46
BG45
BG44
BG42
BG41
BG39
BF49
BF48
BF47
BF46
BF45
BF44
BF43
BF42
BF41
BF40
BF39
BF38
BE49
BE48
BE47
BE46
BE45
BE44
BE43
BE42
BE41
BE40
BE39
BE38
BD49
BD48
BD47
BD46
BD45
BD39
BD38
BC46
BC45
BC42
BC41
BB47
BB46
BB45
BB44
BB43
BB42
BB41
BB40
BB39
BB38
BB37
BA46
BA45
BA44
BA43
BA42
BA39
BC39
BC38
BD41 BD42 BD44
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
6
51 93
6
51 93
FBVDDQ
SYM 11 OF 14
FBVDDQ FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ FBVDDQ
FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ FBVDDQ FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ
FBVDDQ_SENSE
FB_CLAMP
FB_VREF
FB_CALTERM_GND
FB_CAL_PU_GND
FB_CAL_PD_VDDQ
PROBE_FB_GND
PROBE_FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU FBVDD/Q DECOUPLING I(EDP PEAK)=26A
PLACE UNDER GPU
PLACE UNDER GPU
Page Notes
Power aliases required by this page:
BOM options provided by this page:
Signal aliases required by this page:
(NONE)
(NONE)
- =PP1V35_GPU_FBVDDQ
PLACE UNDER GPU
PLACE UNDER GPU
UA000
BGA
GK104
GPU
MF 201
1/20W
1%
RB205
PLACE_NEAR=UA000.R48:5MM
PLACE_NEAR=UA000.R47:5.5MM
RB204
1% 1/20W MF 201
PLACE_NEAR=UA000.P40:3.8MM
RB202
1% 1/20W
201
MF
201
MF
1/20W
1%
RB206
NOSTUFF
RB207
10K
MF 201
5% 1/20W
RB209
1% 1/20W MF 201
1.33K
NOSTUFF
PLACE_NEAR=UA000.R39:7MM
PLACE_NEAR=UA000.R39:8MM
NOSTUFF
CB252
0.1UF
10% 16V
402
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1%
NOSTUFF
RB208
201
MF
1/20W
1.33K
PLACE_NEAR=UA000.R39:8MM
NOSTUFF
1/20W
1%
201
RB201
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PLACE_NEAR=UA000.R49:3.8MM
RB203
1/20W
MF
201
5%
0
CB201
0.1UF
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10%
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6.3V
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10%
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10%
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4.7UF
CB221 CB229
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4.7UF
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20%
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6.3V
20%
4.7UF
CB227
4.7UF
20%
6.3V X6S 0402
CB228
NOSTUFF
0402
X6S
6.3V
20%
4.7UF
CB230
NOSTUFF
0402
X6S
6.3V
20%
4.7UF
CB231
NOSTUFF
0402
X6S
6.3V
20%
4.7UF
CB232
NOSTUFF
0402
X6S
6.3V
20%
4.7UF
CB233
NOSTUFF
0402
X6S
6.3V
20%
4.7UF
CB234
NOSTUFF
0402
X6S
6.3V
20%
4.7UF
CB235
4.7UF
20%
6.3V X6S 0402
CB236
NOSTUFF
1UF
CB211
10%
6.3V X7R 0402
CB212
1UF
10%
6.3V X7R 0402
CB213
1UF
10%
6.3V
X7R 0402
CB214
1UF
10%
6.3V X7R 0402
CB215
1UF
10%
6.3V X7R 0402
CB216
1UF
10%
6.3V X7R 0402
CB217
1UF
10%
6.3V X7R 0402
CB218
1UF
10%
6.3V X7R 0402
CB240
22UF
20%
4V
X6S-CERM 0603
CB241
22UF
20%
4V
X6S-CERM 0603
CB242
22UF
20%
4V
X6S-CERM 0603
CB243
22UF
20%
4V
X6S-CERM 0603 0603
X6S-CERM
4V
20%
22UF
NOSTUFF
CB244 CB245
0603
X6S-CERM
4V
20%
22UF
NOSTUFF
SM
SIGNAL_MODEL=EMPTY
XWB201
XWB200
SM
SIGNAL_MODEL=EMPTY
99
115
99
115
0402
X6S
4V
20%
10UF
CB246
0402
X6S
4V
20%
10UF
CB247
0402
X6S
4V
20%
10UF
CB248
0402
X6S
4V
20%
10UF
CB249
0402
X6S
4V
20%
10UF
NOSTUFF
CB250
NOSTUFF
0402
X6S
4V
20%
10UF
CB251
SYNC_MASTER=D8_YAN
SYNC_DATE=04/09/2012
KEPLER FBVDD/Q POWER
FB_VREF_GPU
=PP1V35_S0_GPU_FBVDDQ
VSNS_FBVDDQ
FB_CAL_PU_GND
FB_CAL_PD_VDDQ
VSNS_FBVDDQ_N
VSNS_FBVDDQ_P
FB_CAL_TERM_GND
=PP1V35_S0_GPU_FBVDDQ
FB_PROBE_GND
FBVDDQ_SENSE_R FB_CLAMP
FB_PROBE_VDDQ
prefsb
051-9505
8.0.0
112 OF 144
94 OF 123
B47 C45
D45
J42
J39
J38
H43
H42
H41
G42
G41
F45
F44
F42
E45
E44
D46
D44
C47
C46
AN40
AM40
AM39
AK39
AG39
AF39
AF11
AD39
AD10
AC11
AA39
J43 K24 K26 K29 K30 K32 L14 L15
L24
L23
L27 L29 L30
L33
L32
L35 L41 P11 P39 R11 R40 U11 U39 V11 V39 V40 Y11 Y40
R49 BB48 R39
R47
R48
P40
AF10
AG11
L20
L18
L17
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
1
2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
12
1 2
2
1
2
1
2
1
2
1
2
1
2
1
118
6
84 85 86 87 88 89 94
115
112
112
112
6
84 85 86 87 88 89 94
115
SYM 12 OF 14
GND
GND
GND
GND
GND
GND GND GND GND GND GND GND
GND
GND GND GND
GND
GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GND
GND
GND
GND
GND
GND
GND GND
GND GND GND
GND GND
GND
GND
GND
GND GND
GND GND GND
GND GND
GND
GND GND
GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND GND
GND
GND
GND GND GND GND
GND
GND
GND
GND GND GND
GND GND GND GND GND
GND
GND
GND GND GND
GND GND
GND
GND
GND
GND GND GND GND GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
GND GND
GND GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SYM 13 OF 14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND_F
GND_H
GND GND
GND
GND GND
GND GND GND
GND GND
GND GND GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
GND
GND
GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
GND
GND
GND GND GND
GND
GND
GND
GND
GND
GND
GND GND GND GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND
GND
SYM 14 OF 14
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU GPU_FB_PLL_AVDD 120MA X 4 = 480MA
Place near GPU
- =PP1V05_GPU_PEX_PLLVDD
- =PP1V05_GPU_PEX_IOVDD
- =PP3V3_GPU_VDD33
Power aliases required by this page:
(NONE)
(NONE)
Page Notes
Signal aliases required by this page:
BOM options provided by this page:
ESR = 0.01OHM
Place under GPU
Place near GPU
Place under GPU
ESR = 0.05OHM
Place near GPU
ESR = 0.01OHM
GPU SP_PLLVDD/VID_PLLVDD 47MA+41MA
GPU GPC_PLLAVDD/LXS_PLLVDD/FB_DLL_AVDD 52MA+39MA+50MA
RDAR://11427653 D8: REPLACE 138S0682 WITH 138S0802
0603
FERR-220-OHM-2A
LB301
CRITICAL
GPU
GK104
BGA
UA000
BGA
GPU
GK104
UA000
GK104
BGA
GPU
UA000
0603
CRITICAL
LB304
30-OHM-25%-5A-0.01-OHM
30-OHM-25%-5A-0.01-OHM
CRITICAL
0603
LB305
0201
10%
6.3V X6S
CB330
0.1UF
PLACE_NEAR=UA000.AW27:3.8MM
0201
0.1UF
10%
6.3V X6S
CB331
PLACE_NEAR=UA000.AW27:3.8MM
0.1UF
10%
6.3V X6S 0201
CB353
PLACE_NEAR=UA000.Y39:3.8MM
PLACE_NEAR=UA000.AD11:3.8MM
CB354
0.1UF
10%
6.3V X6S 0201
PLACE_NEAR=UA000.AT11:3.8MM
CB355
0.1UF
10%
6.3V X6S 0201
PLACE_NEAR=LB301.1:3.8MM
0201
X6S
10%
0.1UF
6.3V
CB323
PLACE_NEAR=LB304.1:3.8MM
CB350
0.1UF
10%
6.3V X6S 0201
PLACE_NEAR=LB305.1:3.8MM
CB360
0201
X6S
6.3V
10%
0.1UF
4.7UF
0402
X6S
CB325
20%
6.3V
PLACE_NEAR=UA000.AW27:21.6MM
CB326
20% 4V
X6S
1.0UF
PLACE_NEAR=UA000.AW27:21.6MM
0201
X6S
4V
20%
1.0UF
0201
CB352
PLACE_NEAR=UA000.AT11:21.6MM
1UF
10%
6.3V
PLACE_NEAR=UA000.L36:21.6MM
X7R 0402
CB362
PLACE_NEAR=UA000.AJ39:29MM
CB361
22UF
20%
6.3V X5R 0603
CB324
20UF
20%
4V
0402
X5R-CERM
X5R-CERM
4V
20%
0402
CB351
20UF
KEPLER PEX PWR/GNDS
SYNC_MASTER=D8_YAN
SYNC_DATE=04/09/2012
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 MM
PP1V05_S0_GPU_SP_PLLVDD_FLT
=PP1V05_S0_GPU_PEX_PLLVDD
VOLTAGE=1.05V
PP1V05_S0_GPU_PLLVDD_FLT
MIN_LINE_WIDTH=0.41MM MIN_NECK_WIDTH=0.2MM
PP3V3_S0_GPU_FB_PLL_AVDD_FLT
MIN_LINE_WIDTH=0.41MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V
=PP1V05_S0_GPU_PEX_PLLVDD
=PP3V3_S0_GPU
prefsb
051-9505
8.0.0
113 OF 144
95 OF 123
21
AH2
AF30
AF26
AF32
AG17 AG19 AG21 AG23 AG25 AG27 AG29
AH18
AH20 AH22 AH24
AH28
AH26
AH30 AH32 AH39 AH4 AH41 AH42 AH45 AH46 AH48 AH5 AH8 AH9 AJ15 AJ17
AJ21
AJ19
AJ23
AM20
AM18
AM16
AL9 AM14
AL48 AL5 AL8
AL45 AL46
AL41
AL4
AL42
AL31 AL39
AL25 AL27 AL29
AL21 AL23
AL2
AL17 AL19
AK32 AL11 AL15
AK30
AK28
AK26
AK24
AK22
AK20
AK18
AK16
AK14
AJ31
AJ29
AJ27
AJ25
AF20 AF22
AF18
AE8
AF14 AF16
AE9
AE5
AE42 AE45 AE46 AE48
AE41
AE29
AE27
AE31 AE39
AE4
AE19
AE2 AE21 AE23 AE25
AD32
AD30
AE11 AE15 AE17
AD20 AD22
AD26
AD24
AD28
AC29 AC31 AD14 AD16 AD18
AC19
AC23
AC21
AC25 AC27
AB5
AC15
AB9
AB8
AC17
AB48
AB41
AB45 AB46
AB42
AB4
AB28
AB32
AB30
AB39
AB26
AB2
AB18
AB20 AB22 AB24
AB11 AB14
AA29 AA31
AB16
AA27
AA23 AA25
AA21
AA19
AA17
AA15
A48
A47
A3
A2
AH16
AH14
AH11
AG31
AG15
AF28
AF24
E19
E16
E13
E10
D7
D43
D40
D4
D37
D34
D31
D28
D25
D22
D19
D16
D13
D10
C49
C3
C1
BJ3
BJ2
BH7
BH5
BH37
BH34
BH31
BH28
BH25
BH22
BH2
BH19
BH16
BH13
BH10
BH1
BG1
BF7
BF5
BF37
BF36
BF35
BF34
BF33
BF32
BF31
BF30
BF29
BF28
BF27
BF26
BF25
BF24
BF23
BF22
BF16
BE33
BE30
BE27
BE24
BE21
BE2
BE19
BE16
BE13
BE10
BC5
BC48
BC4
BC2
BB8
BB36
BB35
BB34
BB32
BB31
BB29
BB28
BB26
BB25
BB23
BB22
BB19
BB16
BB13
BB10
BA34
BA31
BA28
BA25
BA22
BA19
BA16
BA13
B7
B49
B48
B45
B43
B40
B37
B34
B31
B28
B25
B22
B2
B19
B16
B13
B10
B1
AY8
AY5
AY48
AY46
AY4
AY2
AW34
AW31
AW29
AW25
AW22
AW19
AW16
AW13
AU9
AU8
AU5
AU48
AU46
AU45
AU4
AU2
AU11
AT42
AP9
AP5
AP48
AP46
AP45
AP42
AP41
AP4
AP2
AP11
AM30
AM28
AM26
AM24
AM22
BF19
BF13
BF10
BE7
BE4
BE37
BE36
AP8
E34
BB21
AW24
Y30 Y32
Y28
Y24 Y26
Y18 Y20 Y22
Y14 Y16
W5 W8 W9
W46 W48
W45
W42
W41
W39
W31
W4
W29
W27
W23
W21
W25
W2
W19
W17
W15
W11
V32
V30
V28
V26
V24
T39
T42
T41
T4
T46
T45
T8
T5
T48
U15
T9
U21
U19
U17
U25
U23
U27 U29 U31
V16
V14
V18 V20 V22
T32
T30
T28
T26
T24
T22
T20
T2
T18
T11 T14 T16
R31
R29
R23 R25 R27
R21
R19
R17
R15
P20
L22
E22 E25 E28 E31
E37 E40 E43 E46 E48
E5 E7 F6 G2
G4 G45 G46 G48
G5 H10 H13 H16 H19 H22 H25 H28 H31 H34 H37 H40
H8 J13 J16 J19 J22 J25 J28 J31 J34 J37
K2
K4 K42 K45 K46 K48
K5
K8 L13 L16 L19
L25 L28 L31 L34 L37 N11
N2 N39
N4 N41 N42 N45 N46 N48
N5
N8
N9 P14 P16 P18
P22 P24 P26 P28 P30 P32
21
21
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
91
6
83 95
84 91
84 85
6
83 95
6
83 91 92 96
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
OUT
IN
IN
OUT
IN
IN
OUT
IN
IN
COMP
ISEN1-
VDIFF VSEN RGND
EN_PWR
DAC
REF
TM
PWM4
PWM3
FS
SS
VID1
VID6
VID2 VID3 VID4 VID5
VID7
VR_RDY
VID0
VCC
OFS
PSI*
TCOMP
FB
PWM2
ISEN1+
ISEN2+ ISEN2-
ISEN3+ ISEN3-
ISEN4+
VR_HOT
THRM
EN_VTT
ISEN4-
IMON
PWM1
H_CPURST_N
PAD
SYM_VER_2
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DEFAULT: 0.9000V STEP: 12.5MV
LAYOUT: PLACE RTB401 NEAR HOT SPOT.
LOCAL 5V
GPU CORE REG 1.1V/???A O/P= PPGPUCORE_S0_REG
AVG = ???A
PEAK = ???A
VOUT = VCORE
GPU VCORE
VR_HOT goes HIGH when VTM/VCC < 28% and LOW when VTM/VCC > 33%.
152-0110
IMAX = 10.5A
1.25 mOhm loadline
GPU CORE INPUT Filtering
NEED TO FIGURE OUT SEQUENCING FOR ENABLE
XWB401
SM
OMIT
RB415
1/16W
1%
402
MF-LF
49.9K49.9K
402
RB414
1/16W
1%
MF-LF
5%
402
MF-LF
RB412
1/16W
6
72 96
5
64
115
51
115
VR_GPU_IMON
CB403
CERM
50V
10%
0.0022UF
402
0.0022UF
CB402
402
10% CERM
50V
SIGNAL_MODEL=EMPTY
10%
CB401
50V 402
CERM
0.0022UF
NOSTUFF
RB409
MF-LF
1/16W 402
1%
NOSTUFF
NOSTUFF
RB407
1% 1/16W MF-LF 402
21K
NOSTUFF
402
RB405
1%
MF-LF
1/16W
20.0K
MF-LF
1.02K
402
1%
1/16W
RB400
5%
402
MF-LF
0
1/16W
RB406
97
115
97
115
97
115
97
115
97
115
97
115
97
115
97
115
97
115
91
115
MF-LF
0
402
5%
RB445
1/16W
RB404
402
MF-LF
1/16W
5%
0
NOSTUFF
RB498
0
5%
402
MF-LF
1/16W
0.1UF
CB480
CERM
10V 402
20%
C0G 402
1%
50V
NOSTUFF
CB430
50V
1%
C0G 402
NOSTUFF
CB440
NOSTUFF
C0G
50V
1%
402
CB450
0
402
MF-LF
5%
1/16W
RB450
RB440
1/16W
402
MF-LF
5%
0
5%
MF-LF
0
1/16W
402
RB432
5%
RB442
1/16W
0
MF-LF
402
1/16W
0
MF-LF
5%
402
RB452
1/16W
1%
402
MF-LF
RB449
1/16W
1M
RB446
5%
NOSTUFF
402
MF-LF
OMIT
XWB420
SM
XWB430
SM
OMIT
RTB401
0603
115
RB433
1%
1/16W
402
MF-LF
1.02K
402
1% 1/16W MF-LF
1.02K
RB443
1/16W
402
MF-LF
1%
RB453
1.02K
0402
10K
RB411
MF-LF
0.1%
1/16W
1% 1/16W MF-LF 402
75K
RB408
1%
MF-LF
1/16W
1K
402
RB402
CB404
50V
5%
CERM
402
402
MF-LF
1/16W
1%
RB403
287
CB441
402
5% CERM
50V
150PF
402
50V CERM
150PF
5%
CB451
50V CERM
150PF
5%
402
CB431
1%
402
MF-LF
10K
1/16W
RB417
RB438
0
MF-LF
402
1/16W
5%
98
115
98
115
402
0
1/16W
5%
MF-LF
RB420
402
1/16W
1%
1.02K
RB421
MF-LF
402
5% 50V CERM
150PF
CB461
1% 50V C0G
402
NOSTUFF
CB460
RB434
0
MF-LF
402
5%
1/16W
98
115
93
115
93
115
402
1K
1% 1/16W MF-LF
RB475
402
1%
1K
RB474
MF-LF
1/16W
RB476
1% 1/16W MF-LF 402
1K
NOSTUFF
402
RB495
1K
MF-LF
1%
NOSTUFF
1/16W
402
MF-LF
RB497
1K
1% 1/16W
RB480
402
1/16W
1K
1%
NOSTUFF
MF-LF
1/16W
1K
402
1% MF-LF
RB483
402
1K
RB470
1/16W
1% MF-LF
402
1K
1%
RB471
MF-LF
1/16W
NOSTUFF
402
RB496
1K
1/16W MF-LF
1%
402
1K
1% 1/16W MF-LF
NOSTUFF
RB472
402
1K
1% MF-LF
1/16W
RB473
402
1% MF-LF
1/16W
1K
NOSTUFF
RB481
402
MF-LF
1% 1/16W
NOSTUFF
RB482
1K
402
1% MF-LF
1K
1/16W
RB485
0.1%
10K
1/16W MF-LF
0402
RB499
0
5%
402
1/16W
RB484
MF-LF
RB478
402
MF-LF
1/16W
1%
1K
NOSTUFF
CRITICAL
QFN
ISL6334D
UB400
CB433
C0G-CERM 0402
25V
220PF
5%
CB443
5%
220PF
C0G-CERM
25V 0402
CB453
0402
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5%
0402
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5% C0G-CERM
25V
CB463
10%
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X7R-CERM
16V
CB409
NOSTUFF
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0
RB444
402
MF-LF
NOSTUFF
MF-LF
RB455
5%
402
1/16W
0
NOSTUFF
1/16W
RB448
5%
402
MF-LF
0
NOSTUFF
RB447
5%
402
MF-LF
0
1/16W
1%
1/16W
402
RB431
MF-LF
178
RB441
1%
178
1/16W MF-LF
402
402
MF-LF
1/16W
178
1%
RB451
RB439
178
MF-LF
1%
1/16W
402
402
2.15K
RB410
MF-LF
1/16W
1%
402
RB416
MF-LF
1/16W
0
5%
X7R-CERM
0.0033UF
0402
50V
10%
CB410
1%
8.06K
MF-LF
402
RB401
1/16W
0.0047UF
CB405
402
25V
CERM
10%
1/16W
1%
RB477
402
MF-LF
X7R-CERM
50V
10%
0402
CB406
0.001UF
X7R-CERM
16V
10%
0.1UF
CB432
0402
CB442
X7R-CERM
16V
10%
0.1UF
0402
CB452
X7R-CERM
16V
10%
0.1UF
0402
0402
0.1UF
10% 16V X7R-CERM
CB462
X5R-X7R-CERM
16V
10%
0.022UF
CB412
0402
CB407
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10V
10%
1UF
0402
0.36UH-30A-0.6MOHM
SDP110808MR36MF-TH
LB400
CRITICAL
MF-LF
805
RB418
2.2
5%
1/8W
1/16W
0
RB479
5%
MF-LF
402
SYNC_DATE=08/27/2012
VReg GPU Core Phases
SYNC_MASTER=D8_MLB
REG_GPUCORE_VID6
REG_GPUCORE_VID1
PP12V_S0_GPUCORE_FLT
=PP12V_S0_REG_GPUCORE
VR_GPU_ISNS4_R_N
VR_GPU_ISNS3_R_N
REG_PWM_GPUCORE_4
VR_GPU_EN_VTT
REG_GPUCORE_VID2
VR_GPU_PWM3_R
VR_GPU_ISNS2_R_N
VR_GPU_IMON_R
VR_GPU_COMP_RC
VR_GPU_FB
PP5V_S0_GPU_VCORE_VCC
VOLTAGE=5V
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM
VR_GPU_PWM4_R
VR_GPU_PWM1_R
AGND_GPU
VR_GPU_ISNS1_R_N
VR_GPU_PWM2_R
VR_GPU_COMP_R
=PP3V3_S0_GPU
REG_GPUCORE_VID3
=PP3V3_S0_GPU
PM_PGOOD_REG_GPUCORE_S0
VR_GPU_DAC
VR_GPU_IOUT_PD
VR_GPU_ISNS4_R_P
VR_GPU_ISNS2_R_P
VR_GPU_ISNS1_R_P
REG_ISEN_GCORE_1_N
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_1
REG_ISEN_GCORE_3_N
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_3
MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.3MM MIN_LINE_WIDTH=0.6MM
VOLTAGE=0V
AGND_GPU
REG_ISEN_GCORE_4_N
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_4
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_3
REG_ISEN_GCORE_3_P
REG_ISEN_GCORE_2_N
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_2
VSNS_GPU_VSS
VR_GPU_COMP
AGND_GPU
VSNS_GPU_VDD
=PP5V_S0_VRD
PM_EN_REG_GPUCORE_S0
PM_EN_REG_GPUCORE_S0_R
REG_PWM_GPUCORE_3
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_4
REG_ISEN_GCORE_4_P
=PP3V3_S0_VRD
PP5V_S0_GPU_VCORE_VCC
AGND_GPU
=PP5V_S0_VRD
VR_GPU_VDIFF
VR_VDF_R1
VR_GPU_OFS
VR_GPU_FS
PP5V_S0_GPU_VCORE_VCC
VR_GPU_TCOMP
VOLTAGE=1.1V
VR_GPU_VSEN
VR_VDF_R2
VR_GPU_FB_R
VOLTAGE=0V
VR_GPU_RGND
VR_GPU_ISNS3_R_P
REG_PWM_GPUCORE_1
REG_PWM_GPUCORE_2
VR_GPU_ISNS1_RR_2
VR_GPU_ISNS2_RR_2
VR_GPU_ISNS3_RR_2
VR_GPU_ISNS4_RR_2
AGND_GPU
REG_ISEN_GCORE_2_P
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_2
REG_GPUCORE_VID5
GPU_PSI_L
VR_GPU_FAN
REG_GPUCORE_VID4
REG_GPUCORE_VID0
VR_GPU_VRDHOT
REG_GPUCORE_VID7
REG_ISEN_GCORE_1_P
DIFFERENTIAL_PAIR=REG_ISEN_GCORE_1
VR_GPU_REF
VR_GPU_SS
VR_GPU_TM
96 OF 123
114 OF 144
8.0.0
051-9505
prefsb
NET_PHYSICAL_TYPE=SNS_DIFF_PHY
NET_PHYSICAL_TYPE=SNS_DIFF_PHY
1 2
121
2
1
2
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
12
12
12
12
12
1 2
1
2
1 2
1 2
2
1
1 2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
2
1
2
1
2
1
1
2
12
12
1 2
2
1
2
1
12
1
2
1
2
1
2
1
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1
2
1
2
1
2
1
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1
2
1
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1
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1
2
1
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1
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1
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1
2
1
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11
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31
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40
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8
18
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38
41
33
24
10
26
37
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1
2
1
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1
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1
2
1
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1
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1
2
1 2
1 2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
1
2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
21
12
1 2
91
115
91
115
97 98
115
6
115
115
115
91
115
115
115
115
115
96
115
115
115
96
115
115
115
115
6
83 91 92 95 96
91
115
6
83 91 92 95 96
115
115
115
115
96
115
115
96
115
64
115
120
6
66 69 70 72 99
96
115
96
115
6
72 96
115
115
115
96
115
115
115
115
115
115
115
115
115
115
96
115
91
115
91
115
115
91
115
115
115
115
115
OUT
OUT
OUT
OUT
NC
NC
IN
NC
OUT
OUT
OUT
S
G
D
S
G
D
S
G
D
D
G
S
D
G
S
D
G
S
NCNC
NCNC
NCNC
NC
NC
NC
NC
NC
NC
BOOT
UGATE
PHASE
NC NC
GND
LGATE
VCC
PVCC
THRML
PWM
PAD
IN
NC
GDSEL
LGATE
VCC
PWM
BOOT
UGATE
GND
THRML
PHASE
LVCC
UVCC
PAD
GDSEL
LGATE
VCC
PWM
BOOT
UGATE
GND
THRML
PHASE
LVCC
UVCC
PAD
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU Output Decoupling
GPU Phase 3
GPU Phase 1
GPU Phase 2
96
115
NOSTUFF
805
5% 1/8W
2.2
RB537
MF-LF
96
115
96
115
6
97 98
0
5%
603
MF-LF
1/10W
RB516
96
115
6
97 98
96
115
96
115
0612
0.0005
MF
1W
1%
RB550
CRITICAL
NOSTUFF
RB557
2.2
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1/8W
5%
805
0
5%
603
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NOSTUFF
RB567
5% 1/10W
10
603
MF-LF
CRITICAL
RB510
1W
0.0005
0612
1% MF
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SQ
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CRITICAL
QB512
SQ
IRF6811STRPBF
CRITICAL
QB514
SQ
IRF6811STRPBF
CRITICAL
CRITICAL
IRF6893MTRPBF
QB511
DIRECTFET-MX
DIRECTFET-MX
CRITICAL
IRF6893MTRPBF
QB531
IRF6893MTRPBF
CRITICAL
DIRECTFET-MX
QB551
0.0005
MF
1W
0612
1%
RB530
CRITICAL
ISL6612
QFN1
CRITICAL
UB530
10% X7R-CERM
50V 0402
NOSTUFF
CB517
0.001UF
0.001UF
0402
50V X7R-CERM
10%
CB537
NOSTUFF
0.001UF
CB557
NOSTUFF
0402
50V X7R-CERM
10%
96
115
603
10
5%
RB527
MF-LF
1/10W
NOSTUFF
UB550
DFN
ISL6622
CRITICAL
RB531
1/10W
603
MF-LF
0
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0
1/10W MF-LF
RB528
603
5%
1/10W
603
RB529
MF-LF
0
0603
CB516
0.22UF
10% 25V X7R
CB536
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25V
10%
0.22UF
0603
CB556
0603
0.22UF
25V X7R
10%
1.0UF
CB525
0603
10% 16V X7R
0603
10% 16V X7R
1.0UF
CB526
CB527
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10%
0603
1.0UF
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CB545
X7R
16V
10%
0603
1.0UF
CB547
0603
16V X7R
10%
1.0UF
CB565
0603
X7R
16V
10%
1.0UF
X7R
16V
10%
0603
1.0UF
CB566
0603
1.0UF
10% 16V X7R
CB567
CB512
0805
10% 25V X6S
CRITICAL
10UF
CRITICAL
CB513
10UF
0805
10% 25V X6S
CB533
X6S
25V
10%
0805
10UF
CRITICAL
CB532
25V
10%
0805
10UF
CRITICAL
X6S
CB553
CRITICAL
10UF
0805
10% 25V X6S
CB552
CRITICAL
0805
10% 25V X6S
10UF
CB515
X6S-CERM
25V
10%
0402
1UF
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CB514
X6S-CERM
25V
10%
0402
1UF
EMC
EMC
1UF
0402
10% 25V X6S-CERM
CB535
EMC
1UF
0402
10% 25V X6S-CERM
CB534
X6S-CERM
25V
10%
0402
1UF
EMC
CB555CB554
EMC
1UF
0402
10% 25V X6S-CERM
TH1
CB510
16V
20%
180UF
POLY
CRITICAL
TH1
CB511
16V
20%
180UF
POLY
CRITICAL
TH1
16V
20%
180UF
POLY
CB530
CRITICAL
TH1
CB531
16V
20%
180UF
POLY
CRITICAL
TH1
CB595
16V
20%
180UF
POLY
CRITICAL
SDP110808M-TH
CRITICAL
LB510
0.24UH-30A-0.35MOHM
SDP110808M-TH
CRITICAL
0.24UH-30A-0.35MOHM
LB530
CRITICAL
0.24UH-30A-0.35MOHM
SDP110808M-TH
LB550
CB580
CASE-D2-SM
20% 2V POLY
330UF-0.006OHM
CRITICAL
RB517
NOSTUFF
MF-LF
1/8W 805
2.2
5%
330UF-0.006OHM
20% 2V POLY CASE-D2-SM
CRITICAL
CB581
CASE-D2-SM
20% 2V POLY
330UF-0.006OHM
CRITICAL
CB582
CRITICAL
CB585
CASE-D2-SM
20% 2V POLY
330UF-0.006OHM
CRITICAL
CB584
330UF-0.006OHM
20% POLY
CASE-D2-SM
2V
CASE-D2-SM
20% 2V POLY
330UF-0.006OHM
CRITICAL
CB583
DFN
CRITICAL
UB510
ISL6622
96
115
96
115
6
97 98
1/10W 603
MF-LF
10
5%
RB547
5%
1/10W
RB536
MF-LF
0
603
SYNC_MASTER=D8_MLB
VReg GPU Core Phases
SYNC_DATE=08/27/2012
PP12V_S0_GPUCORE_FLT
PPGPUCORE_S0_SENSE_1
REG_PHASE_GPUCORE_1
PPGPUCORE_S0_SENSE_2
REG_PHASE_GPUCORE_2
PPGPUCORE_S0_SENSE_3
REG_PHASE_GPUCORE_3
REG_SNUBBER_GPUCORE_2
REG_LGATE_GPUCORE_2
REG_ISEN_GCORE_2_N
PPGPUCORE_S0_REG
PP12V_S0_GPUCORE_FLT
REG_LVCC_UB550
REG_UGATE_GPUCORE_3
REG_UVCC_UB550
REG_LVCC_UB530
PP12V_S0_GPUCORE_FLT
REG_LVCC_UB510
PP12V_S0_GPUCORE_FLT
REG_UVCC_UB510
PPGPUCORE_S0_REG
REG_LGATE_GPUCORE_3
REG_PWM_GPUCORE_3
REG_BOOT_GPUCORE_1
REG_UGATE_GPUCORE_1
REG_BOOT_GPUCORE_2
REG_PWM_GPUCORE_2
REG_SNUBBER_GPUCORE_3
REG_SNUBBER_GPUCORE_1
REG_ISEN_GCORE_3_P
REG_ISEN_GCORE_1_P
REG_ISEN_GCORE_1_N
PPGPUCORE_S0_REG
PPGPUCORE_S0_REG
REG_ISEN_GCORE_3_N
REG_PWM_GPUCORE_1
REG_ISEN_GCORE_2_P
REG_UGATE_GPUCORE_2
REG_LGATE_GPUCORE_1
REG_BOOT_GPUCORE_1_RC
REG_BOOT_GPUCORE_2_RC
REG_BOOT_GPUCORE_3_RC
REG_BOOT_GPUCORE_3
REG_VCC_UB550
prefsb
051-9505
8.0.0
115 OF 144
97 OF 123
1
2
1
2
4 3
2 1
1
2
1
2
1
2
43
21
3
4
2
1
5 6
3
4
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1
5 6
3
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5
3 4
71 2 6
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71 2 6
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1
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3
6
9
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2
1
5
11
10
7
8
1 2
1 2
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
21
21
21
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
6
9
4
2
1
5
11
10
7
8
1
2
1
2
96 97 98
115
115
115
115
115
115
115
115
115
96 97 98
115
115
115
115
115
96 97 98
115
115
96 97 98
115
115
6
97 98
115
115
115
115
115
115
115
115
115
115
115
115
115
OUT
OUT
OUT
NC
IN
NC
S
G
D
D
G
S
NCNC
NC
NC
BOOT
UGATE
PHASE
NC NC
GND
LGATE
VCC
PVCC
THRML
PWM
PAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU PHASE 4
RB667
603
10
5% MF-LF
1/10W
RB656
MF-LF
603
0
5%
1/10W
805
MF-LF
2.2
RB657
1/8W
5%
NOSTUFF
96
115
96
115
6
97
96
115
RB650
0.0005
MF
1W
1%
0612
CRITICAL
QB650
CRITICAL
IRF6811STRPBF
SQ
QB651
CRITICAL
DIRECTFET-MX
IRF6893MTRPBF
UB650
ISL6612
CRITICAL
QFN1
10%
CB657
0.001UF
0402
NOSTUFF
50V X7R-CERM
CB656
0603
0.22UF
10% 25V X7R
1.0UF
CB665
0603
10% 16V X7R
CB667
X7R
16V
10%
0603
1.0UF
CRITICAL
10UF
CB652
0805
10% 25V X6S
CB653
CRITICAL
10UF
0805
10% 25V X6S
EMC
CB655
X6S-CERM
25V
10%
0402
1UF
X6S-CERM
25V
10%
0402
1UF
EMC
CB654
TH1
CB650
16V
20%
180UF
POLY
CRITICAL
SDP110808M-TH
CRITICAL
LB650
0.24UH-30A-0.35MOHM
SYNC_MASTER=D8_MLB
VREG GPU CORE PHASE 4
SYNC_DATE=08/27/2012
PPGPUCORE_S0_SENSE_4
REG_PHASE_GPUCORE_4
PP12V_S0_GPUCORE_FLT
PPGPUCORE_S0_REG
REG_LVCC_UB650
PP12V_S0_GPUCORE_FLT
REG_SNUBBER_GPUCORE_4
REG_ISEN_GCORE_4_N
REG_ISEN_GCORE_4_P
REG_PWM_GPUCORE_4
REG_BOOT_GPUCORE_4
REG_LGATE_GPUCORE_4
REG_UGATE_GPUCORE_4
REG_BOOT_GPUCORE_4_RC
prefsb
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3 8
5
6
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2
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2
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2
11
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21
115
115
96 97 98
115
115
96 97 98
115
115
115
115
115
115
OUT
OUT
FB
EN
PVCC
VCC
SREF
VO
OCSET
PGOOD
FSEL
RTN
PHASE
LGATE
UGATE
BOOT
PGND
GND
SET0
SET1
VID0
VID1
IN
IN
IN
VSW
PGND
TGR
TG
BG
VIN
BOOT
UGATE
LGATE
PHASE
RTN
FSEL
PGOOD
OCSET
VO
SREF
VCC
PVCC
GND
PGND
EN
FB
IN
IN
OUT
IN
NCNC
D
S
G
S
G
D
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
GPU/PCH/TBT 1V05 SUPPLY
<Ra><Ra>
Vout = 0.5V * (1 + Ra / Rb)
audio frequencies
prevent noise in the
Note:
<Rb>
SENSING LOCATION TBD
<Ra> <Ra>
GPIO_16 VID 1
GPU VDDQ SUPPLY
??? A MAX OUTPUT
0
VOUT = 1.5V / 1.35V
0 1
1.35 V
1.5 V
0
GPU VDDQ
F = ??? KHZ
VID 0
5.3A MAX OUTPUT
F = 500 KHZ
<Rb>
VOUT = 1.05V
Vout = 0.5 * (1 + Ra / Rb)
<Rb>
a minimum load to
Regulator requires
To regulator:
<Rb>
6
115
CB717
20%
6.3V 603
X5R
10UF
5
64 99
120
CASE-D2-HF
330UF-0.009OHM
CB716
20% 2V POLY
CRITICAL
CB715
POLY
20%
330UF-0.009OHM
CASE-D2-HF
2V
CRITICAL
330UF-0.009OHM
CB714
2V POLY
20%
CASE-D2-HF
CRITICAL
25V
10UF
CRITICAL
CB708
0603
20% X5R-CERM
5%
25V 402
NP0-C0G
1000PF
CB713
RB713
402
MF-LF
1/16W
5%
20K
CB707
20%
10UF
25V 0603
CRITICAL
X5R-CERM
1UF
X5R
10% 25V
402
CB710
EMC QB710.2:5MMQB710.2:5MM
CB709
1UF
10%
402
EMC
25V X5R
2.2
603
RB709
5% 1/10W MF-LF
NOSTUFF
CRITICAL
ISL95870AH
UTQFN
UB750
XWB771
SM
SIGNAL_MODEL=EMPTY
SM
XWB770
SIGNAL_MODEL=EMPTY
5%
2.2
805
1/8W
RB706
MF-LF
603
2.2UF
10% 16V X5R
CB704
5%
1/8W
805
RB705
MF-LF
10
CB703
X5R
10% 16V
1UF
402
94
115
UB750.3:1MM
SM
XWB773
64
120
RB774
MF-LF
402
1/16W
1%
301K
RB777
402
5%
0
MF-LF
1/16W
91
118
NOSTUFF
5% 1/16W MF-LF 402
0
RB776
402
MF-LF
RB775
1/16W
1%
150K
27K
1% MF
RB778
1/16W
402
RB771
402
SIGNAL_MODEL=EMPTY
1% 1/16W MF-LF
2.32K2.32K
402
1%
SIGNAL_MODEL=EMPTY
1/16W MF-LF
RB770
NOSTUFF
402
2.74K
1/16W
RB773
1% MF-LFMF-LF
2.74K
1%
1/16W
402
RB772
NOSTUFF
X5R
10V
20%
603
CB734
CRITICAL
MF 201
1/20W
RB718
5%
0
NOSTUFF
CB745
603
X5R
20%
6.3V
X5R
603
CB744
20%
6.3V
POLY
2V
330UF-0.009OHM
CB743
CRITICAL
20%
CASE-D2-HF
10% 25V
1UF
X5R 402
CB738
EMC QB720.1:6MM
330UF-0.009OHM
CASE-D2-HF
20%
2V
POLY
CB742
CRITICAL
5%
CB741
1000PF
NP0-C0G
402
25V
XWB706
SM
EMC
10% 25V X5R 402
1UF
CB737
QB720.1:7MM
SM
XWB705
NP0-C0G
25V 402
5%
CB739
1000PF
NOSTUFF
SON5X6
QB720
CSD58872Q5D
402
MF-LF
RB722
5%
1/16W
10K
CB733
2.2UF
603
X5R
16V
10%
CRITICAL
UB700
ISL95870
UTQFN
XWB704
SM
64
120
6
99
5
64 99
120
XWB710
SM
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
XWB711
SM
805
3.3
MF-LF
1/8W
5%
RB719
5%
603
1/10W MF-LF
1
RB723
NOSTUFF
RB712
1/16W MF-LF 402
200
5%
5%
MF-LF
200
1/16W
RB740
402
94
115
DIRECTFET_S3C
649135PBF
QB711
CRITICAL
QB710
CRITICAL
S1
649136PBF
C0G-CERM
CB731
10PF
0402
50V
5%
50V
10PF
5%
0402
C0G-CERM
CB730
C0G-CERM
10PF
0402
50V
5%
CB785
10PF
5% 50V
0402
C0G-CERM
CB770
0.047UF
10% X7R-CERM
CB732
0402
16V
10% X7R-CERM
CB705
0402
16V
0.1UF
X7R-CERM
CB711
NOSTUFF
0402
0.001UF
50V
10%
0.22UF
402
16V
10%
CB740
CERM
0.033UF
CB790
16V X5R
10%
402
RB707
603
MF-LF
1/10W
0
5%
CERM-X7R
0.33UF
RB710.2:3MM
CB712
603
16V
10%
SDP1182M-TH
0.68UH-20%-32A-0.00066OHM
LB710
CRITICAL
1/16W
1% MF-LF
402
2.8K
LB710.2:25MM
RB711
2.8K
402
RB710
MF-LF
1/16W
1%
1%
11.3K
1/16W MF-LF 402
RB714
RB716
402
1/16W
11.3K
1% MF-LF
1%
402
10.2K
1/16W
RB715
MF-LF
RB717
402
1/16W
10.2K
1% MF-LF
TH1
CB702
16V
20%
180UF
POLY
CRITICAL CRITICAL
POLY
180UF
20% 16V
CB706
TH1
CRITICAL
POLY
180UF
20% 16V
CB720
TH1
16V
20%
180UF
POLY TH1
CB736
CRITICAL
TH1
16V
20% POLY
180UF
CRITICAL
CB750
5%
0
1/8W
MF-LF
805
RB721
RB720
402
MF-LF
1/16W
0
5%
402
MF-LF
RB724
1/16W
3.83K
1%
RB725
402
MF-LF
1/16W
3.83K
1%
CB735
0402
0.1UF
10% 16V X7R-CERM
CRITICAL
LB720
1.0UH-27A-1.05MOHM
SDP1182-SM
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
GPU VDDQ AND 1V05 GPU/PCH/TBT VREGS
REG_P1V05S0_VO_R
P1V05_OCSET_R
REG_P1V05S0_OCSET
REG_P1V05S0_VO
REG_BOOT_P1V05S0
REG_LGATE_P1V05S0
REG_SNUBBER_P1V05S0
=PP12V_S0_REG_FBVDDQ
FBVDD_ALTVO
REG_BOOT_FBVDDQ_RC
REG_BOOT_FBVDDQ
REG_FBVDDQ_OCSET
REG_FBVDDQ_VO
REG_SNUBBER_FBVDDQ
REG_LGATE_FBVDDQ
REG_FBVDDQ_VO
REG_UGATE_FBVDDQ
REG_VCC_UB750
REG_PVCC_UB750
SNS_FBVDDQ_XW_P
PP1V05_S0_REG
PM_PGOOD_REG_FBVDDQ_S0
=PP5V_S0_REG_P1V05
REG_VCC_UB700
=PP3V3_S0_VRD
=PP3V3_S0_VRD
=PP5V_S0_REG_FBVDDQ
PM_PGOOD_REG_P1V05_S0
REG_FBVDDQ_OCSET
PM_EN_REG_FBVDDQ_S0
PM_PGOOD_REG_P1V05_S0
REG_P1V05S0_OCSET
REG_FBVDDQ_SET1
REG_P1V05S0_SREF
REG_P1V05S0_FSEL
PM_PGOOD_REG_FBVDDQ_S0
MAKE_BASE=TRUE
REG_FBVDDQ_SET0
REG_FBVDDQ_SET1_R
REG_FBVDDQ_SREF
SNS_FBVDDQ_XW_N
PM_EN_REG_P1V05_S0
SNS_P1V05_IOVDD_XW_PSNS_P1V05_IOVDD_XW_N
REG_P1V05S0_FB
REG_P1V05S0_RTN
REG_PHASE_FBVDDQ
P1V05_AGND
VSNS_FBVDDQ_P
VSNS_FBVDDQ_N
REG_FBVDDQ_FB
AGND_FBVDDQ
REG_FBVDDQ_RTN
REG_FBVDDQ_FSEL
PP1V5R1V35_S0_GPU_REG
REG_UGATE_P1V05S0_R
=PP12V_S0_REG_P1V05
REG_UGATE_P1V05S0
REG_PHASE_P1V05S0
REG_BOOT_P1V05S0_RC
REG_P1V05S0_VO
REG_PHASE_P1V05S0_L
PP1V05_S0_REG
VOLTAGE=0V
prefsb
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10
15
20
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5
212
1
1
2
2
1
1
2
2
1
12
1
2
1 2
1
2
1
2
1
2
121
2
121
2
2
1
1
2
2
1
2
1
1
2
2
1
1
2
2
1
2
1
2
1
2
1
2
1
6
9
4
3
5
8
7
1
1
2
2
1
12
11
15
10
2
5
9
7
8
4
13
14
1
16
3
6
1 2
2
1
2
1
1
2
1
2
1
2
1
2
128
356
7
4
3
4
2
1
5 6
2
1
2
1
2
1
2
1
2
1
2
1
2
1
12
2
1
1
2
1 2
21
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
12
1
2
1
2
1
2
2
1
21
108
108
99
108
99
108
108
108
108
6
115
115
99
115
99
115
115
115
99
115
115
115
115
115
5
64 99
120
6
108
6
66 69 70 72 96 99
6
66 69 70 72 96 99
6
99
115
5
64
99
120
99 108
121
108
108
121
121
121
115
109 109
108
108
115
108
115
115
115
108
6
108
108
108
99
108
108
6
99
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_BOARD_INFO
VERSION
ALLEGRO
(MIL or MM)
BOARD UNITS
BOARD LAYERS
BOARD AREAS
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
BGA Area Constraints
D8 BOARD SPECIFIC PHYSICAL AND SPACING CONSTRAINTS
Fixed and Dielectric
General Physical Rule Definitions
General Spacing Definitions
Default
Board Stack-up
Top
Signal
0.5 oz (Cu plated)
FINISHED BOARD THICKNESS: 1.94 MM
Plane
1 oz
Core
0.5 oz
Signal
Prepreg
Plane
Core
Core
Plane
1 oz
Plane
Prepreg
Signal
Signal
1 oz
0.076 MM
0.076 MM
Core 0.101 MM
Core
Plane
1 oz
1 oz
Plane
0.071 MM
Prepreg
0.071 MM
Prepreg
0.5 oz (Cu plated)
Signal
Btm
Prepreg
0.115 MM
0.5 oz
0.101 MM
0.5 oz
0.115 MM
0.380 MM
0.5 oz
0.380 MM
1 oz
Prepreg
Signal
2
3
4
6
7
8
9
10
11
5
0.076 MM
Compensation Physical Rule Definition
Power and Common
GENERIC
BGA
NOTE: line width based on 12 mil recommendation
NOTE: neck width based on 4 mil recommendation
=STANDARD =STANDARD
0.085 MM
Y*
0.115 MM
=STANDARD45_OHM_SE
=STANDARD
0.090 MM
50_OHM_SE
=STANDARDY*
0.085 MM
=STANDARD
=STANDARD
ISL5,ISL855_OHM_SE
Y
=STANDARD
=STANDARD
0.080 MM 0.080 MM
0.130 MM
0.1 MM
0.085 MM
Y*
68_OHM_DIFF
0.171 MM
=STANDARD
0.1 MMY
TOP,BOTTOM
68_OHM_DIFF
0.185 MM
=STANDARD
0.085 MM
0.150 MM
0.085 MM
ISL5,ISL845_OHM_SE
=STANDARDY =STANDARD
=STANDARD
0.126 MM =STANDARD45_OHM_SE
=STANDARD
0.135 MM
TOP,BOTTOM
0.085 MM
Y =STANDARD
=STANDARD =STANDARD
0.105 MM
50_OHM_SE
Y
0.085 MM
=STANDARD
TOP,BOTTOM
Y
55_OHM_SE
=STANDARD* =STANDARD
=STANDARD
0.075 MM 0.075 MM
PM_ISO
*PM *
GND
DEFAULT
PM *
SYNC_DATE=08/27/2012
SYNC_MASTER=D8_MLB
D8 RULE DEFINITIONS
1:1_SPACING
0.1 MM
?
*
BGA
**
BGA_P1MM
0.190 MM
0.085 MM
=STANDARD
Y
0.136 MM
80_OHM_DIFF
* 0.1 MM
80_OHM_DIFF
0.085 MM
=STANDARD
Y
0.141 MM
0.185 MM
0.1 MM
TOP,BOTTOM
0.121 MM
=STANDARD
85_OHM_DIFF
* Y
0.085 MM
0.1 MM
0.190 MM
TOP,BOTTOM
Y
0.085 MM
=STANDARD
0.090 MM
0.230 MM
100_OHM_DIFF
0.1 MM
100_OHM_DIFF
*
0.085 MM
=STANDARD
Y
0.086 MM
0.200 MM
0.1 MM
0.200 MM
=STANDARD
*
90_OHM_DIFF
0.085 MM
Y 0.1 MM
0.109 MM
0.155 MM
Y
42_OHM_SE
=STANDARD
0.085 MM
=STANDARD
=STANDARD
TOP,BOTTOM
10 MM
DEFAULT
0 MM0 MM
* Y
=50_OHM_SE
0.1 MM
ISL5,ISL8
0.165 MM 0.085 MM
39_OHM_SE =STANDARD
Y =STANDARD =STANDARD
COMP_SE
*
0.105 MM
3 MM
=STANDARD =STANDARD
0.305 MM
Y
DEFAULT
?
0.1 MM
*
?
1X_DIELECTRIC
*
0.076 MM
?
0.071 MM
1X_DIELECTRIC
TOP,BOTTOM
TOP,BOTTOM
34_OHM_SE
=STANDARD
0.220 MM 0.085 MM
=STANDARDY
=STANDARD
34_OHM_SE
=STANDARD
0.205 MM 0.085 MM
=STANDARD
Y
ISL5,ISL8
=STANDARD
TOP,BOTTOM
Y
0.175 MM
=STANDARD =STANDARD
=STANDARD39_OHM_SE
0.085 MM
=STANDARD
0.085 MM0.150 MM
39_OHM_SE
Y =STANDARD =STANDARD*
0.100 MM 0.085 MM
Y
50_OHM_SE
=STANDARD =STANDARD
ISL5,ISL8 =STANDARD
0.1 MM
90_OHM_DIFF
0.200 MM
=STANDARD
0.085 MM
TOP,BOTTOM
Y
0.111 MM
TOP,BOTTOM
Y
85_OHM_DIFF
=STANDARD
0.085 MM0.125 MM
0.190 MM
0.1 MM
=STANDARD
34_OHM_SE
0.185 MM 0.085 MM
=STANDARD
=STANDARDY*
=STANDARD
0.130 MM
42_OHM_SE
=STANDARDY
0.085 MM
=STANDARD
*
0.145 MM
=STANDARDY
0.085 MM
=STANDARD
=STANDARDISL5,ISL842_OHM_SE
=STANDARD
TOP,BOTTOM
55_OHM_SE
=STANDARD
0.085 MM
Y
=STANDARD
0.085 MM
?
1X_DIELECTRIC
ISL3,ISL10
0.101 MM
*
?
=DEFAULTSTANDARD
=DEFAULT
STANDARD =DEFAULT
Y*
=DEFAULT
=DEFAULT
10 MM
NO_TYPE,BGA,BGA_TBT
MM
16.2
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
?
*
PM_ISO
=1:1_SPACING
?
*
GENERIC_ISO
=1:1_SPACING
PWR_P2MM
1100
*
=2:1_SPACING
GND_P2MM
1000
*
=2:1_SPACING
8000
*
GND_ISO
=STANDARD
=STANDARD
?
*
BGA_P1MM
prefsb
051-9505
8.0.0
120 OF 144 100 OF 123
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