Apple A1311 Schematics

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

DRAWING

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

3

B

7

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BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

K60 MLB

1 OF 98

051-8115

11.1.0

1 OF 110

2011-02-08

Contents

Sync

Date

(.csa)

Page

49

01/06/2011

K60_MARK

52

SMBUS CONNECTIONSTable of Contents

1

1

K60

05/21/2009

ABBREV=DRAWING

TITLE=K22

LAST_MODIFIED=Tue Feb 8 14:39:56 2011

LAST_MODIFIED=Tue Feb 8 14:39:56 2011

Page

(.csa)

Contents

Date

Sync

50

01/06/2011

K62

53

CPU/PCH/GPU POWER SENSE

51

01/06/2011

K62

54

HDD OOB SENSE

52

01/06/2011

K60_MARK

55

TEMP SENSORS

53

01/06/2011

K62

56

HD AND OD FAN

54

01/06/2011

K60_JERRY

57

CPU FAN

55

01/06/2011

K62

61

SPI ROM

56

01/06/2011

K60_DAVID

62

AUDIO: CODEC/REGULATOR

57

01/06/2011

K60_DAVID

63

AUDIO: FILTER/BUFFER

58

01/06/2011

K60_DAVID

64

AUDIO: SPEAKER AMP_1

59

01/06/2011

K60_DAVID

65

AUDIO: SPEAKER AMP

60

01/06/2011

K60_DAVID

66

Audio: MLB to I/O Conn.

61

11/24/2010

K60_DAVID

67

AUDIO: Detects/Grounding

62

01/06/2011

K60_DAVID

68

AUDIO: Mikey

63

01/06/2011

K62

69

POWER SEQUENCING ENABLES

64

01/06/2011

K62

70

POWER SEQUENCING PGOOD

65

N/A

K60_AARON

71

VREG: PPVCORE_S0_CPU

66

01/06/2011

K62

72

VREG: CPU CORE - PHASES 1-3

67

N/A

K60_AARON

73

VREG:AXG PHASE/CORE - CAPS

68

01/06/2011

K62

74

1V05 REGULATOR

69

11/15/2010

K62

75

CPU VCCSA REGULATOR

70

01/06/2011

K62

77

5V_S3 / 3V3_S5 VREGS

71

01/06/2011

K62

78

1.5V / 1.8V VREGS

72

01/06/2011

K62

79

3.42 G3HOT SUPPLY

73

01/06/2011

K62

80

S3+S0 FETS

74

01/06/2011

K60_JERRY

81

12V_S0 & 12V_S5 switch

75

01/06/2011

K62

84

MXM PCIe, DP & Power

76

N/A

K60_MASTER

85

MXM I/O

77

01/06/2011

K62

86

MXM PCIE CAPS

78

07/18/2010

K60_AARON

87

DP ALIAS AND CONTROL

79

01/06/2011

K62

88

GREEN CLOCK

80

01/06/2011

K62

89

T29 POWER

81

01/06/2011

K62

90

Display: Int DP Connector

82

11/14/2010

K62

91

2V9/3V3/12V POWER SWITCH

83

01/06/2011

K62

92

Internal DP MUXing

84

11/14/2010

K62

93

DisplayPort/T29 A MUXing

85

01/06/2011

K62

94

DisplayPort/T29 A Connector

86

01/06/2011

K62

97

T29 Host (1 of 2)

87

01/06/2011

K62

98

T29 Host (2 of 2)

88

01/06/2011

K62

100

K60/K62 RULE DEFINITIONS

89

01/06/2011

K60_ROSITA

101

Memory Constraints

90

01/06/2011

K62

102

PCIE/DMI/FDI/SATA CONSTRAINTS

91

01/06/2011

K62

103

IBEX PEAK CONSTRAINTS

92

01/06/2011

K62

104

USB/ENET/SD/FW/AUD CONSTRAINTS

93

01/06/2011

K62

105

GRAPHICS CONSTRAINTS

94

01/06/2011

K62

106

SMC Constraints

95

01/06/2011

K62

107

POWER CONSTRAINTS

96

01/06/2011

K62

108

T29 CONSTRAINTS

97

01/06/2011

K62

109

PM RESETS ENABLES PGOOD CONST

98

01/06/2011

K62

110

K60/K62 ICT/FCT

System Block Diagram

2

2

K60_SIJI

01/06/2011

Power Block Diagram

3

3

K60_JERRY

01/06/2011

BOM Configuration

4

4

K60_AARON

N/A

DEBUG LEDS

5

5

K62

01/06/2011

Power Conn / Alias

6

6

K60_MARK

12/30/2010

Holes

7

7

K74_MASTER

N/A

UNUSED SIGNAL ALIAS

8

8

K62

01/06/2011

Signal Aliases

9

9

K62

01/06/2011

CPU DMI/PEG/FDI/RSVD

10

10

K62

01/06/2011

CPU CLOCK/MISC/JTAG

11

11

K62

01/06/2011

CPU DDR3 INTERFACES

12

12

K62

01/06/2011

CPU POWER

13

13

K62

01/06/2011

CPU GROUNDS

14

14

K62

01/06/2011

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

15

15

K62

01/06/2011

CPU NON-GFX DECOUPLING

16

16

K62

01/06/2011

GFX DECOUPLING & PCH PWR ALIAS

17

17

K62

01/06/2011

PCH SATA/PCIE/CLK/LPC/SPI

18

18

K62

01/06/2011

PCH DMI/FDI/GRAPHICS

19

19

K62

01/06/2011

PCH PCI/FLASHCACHE/USB

20

20

K62

01/06/2011

PCH MISC

21

21

K62

01/06/2011

PCH POWER

22

22

K62

01/06/2011

PCH GROUNDS

23

23

K62

01/06/2011

PCH DECOUPLING

24

24

K62

01/06/2011

CPU & PCH XDP

25

25

K62

01/06/2011

CLOCK (CK505)

26

26

K62

01/06/2011

CHIPSET SUPPORT

28

27

K62

01/06/2011

DDR3 VREF MARGINING

29

28

K62

01/06/2011

MEMORY CAPS

30

29

K62

01/06/2011

DDR3 SO-DIMM 0 & 2

31

30

K62

01/06/2011

DDR3 SO-DIMM 1 & 3

32

31

K62

01/06/2011

DDR3 SUPPORT AND BITSWAPS

33

32

K62

01/06/2011

PCI-E Wireless Connector

34

33

K62

01/06/2011

USB HUB 1

35

34

K62

01/06/2011

USB HUB 2

36

35

K62

01/06/2011

CAESAR IV SUPPORT

38

36

K62

01/06/2011

ETHERNET PHY (CAESAR IV)

39

37

K62

01/06/2011

Ethernet Connector

40

38

K60_MARK

01/06/2011

FireWire LLC/PHY (FW643)

41

39

K60_ROSITA

01/06/2011

FireWire: 1394B MISC

42

40

K62

01/06/2011

FIREWIRE CONNECTOR

43

41

K62

01/06/2011

SATA Connectors

45

42

K60_JERRY

01/06/2011

EXTERNAL USB CONNECTORS

46

43

K62

01/06/2011

Internal USB Connections

47

44

K62

01/06/2011

SD READER CONNECTOR

48

45

K62

01/06/2011

SMC

49

46

K62

01/06/2011

SMC Support

50

47

K62

01/06/2011

LPC+SPI Debug Connector

51

48

K62

01/06/2011

SCH,K60,MLB

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB CAMERA

PG 47

J47XX

J47XX

SD CARD

PG 47

TO ENET

25MHz XTAL IN 25MHz XTAL IN

25MHz XTAL IN

X4 PCI-E GEN2

PG 88

U8800

GREEN CLK

X16 PCI-E GEN2

FDI INTERFACE

DDR3 1333 CHB

DDR3 1333 CHA

J4800

SATA-A2

SATA CONN

ODD

T3900

MAGNETICS

PG 38

AND PHY

GB E-NET

SATA CONN

LGA1155 - SANDY BRIDGE

PG 19

PG 47

J4700

ALS

XDP CONN

SO-DIMMS

XDP CONN

PG 55

FAN CONN AND CONTROL

PG 56,57

J5600, J5601, J5700

FW643

SD CARD

HDA

SMB

E-NET

CONNECTOR

J4530

X1 PCIE GEN1 LANE 2.5GBITPS

X1 PCIE GEN1 LANE 2.5GBITPS

PG 19

CONTROLLER

HDMI/DVI/DP

(UP TO 14 DEVICES)

LPC

6 SATA 2.O PORTS

PG 18

X4 DMI

(PORT B)

RGB OUT

DIGITAL VIDEO OUTPUT

(PORT C)

13121110

83

SATA

(SUPPORTED UPTO 4 REQ/GNT)

E-NET

PCI

PWR

DIGITAL VIDEO OUTPUT

SATA 3.0 6GHZ.

SATA 3.0 6GHZ.

HDD

SSD

MIDBUS PROBE

PG 25

J2500

Port80,serial

PG 51

XDP

J3900

(PORT D)

PG 39

U3800

PG 18

INTERFACE

PG 18

PG 19

DMI INTERFACE

PG 18

HDMI/DVI/DP

PG 19

PG 18

PG 18

PG 18

PG 20

PG 19

PG 20

PG 25

U2510

PG 39

0 1 2 5 6 7 9

USB 2.0

DIMM’s

SPI

Boot ROM

PG 13

U6100

PG 32

PG 31

J3200, J3200

J3100, J3100

PG 53

POWER SENSE

TO BIDIVI HW

PG 10

CTRL

Fan

MIKEY

J4300

SPI

B,0 BSB

SMC

ADC

4

PG 34 PG 43

AirPort

Mini PCI-E

PG 49

U4900

DIGITAL VIDEO OUTPUT

Conn

FireWire

J3400

PG 41

U4100

HDMI/DVI/DP

U1000

2 SO-DIMMS

J5100

Prt

Ser

PG 61

CLK

LPC+SPI CONN

(PORT A)

ANALOG VIDEO OUTPUT

SATA-A0

SYNTH

PG 45

J4510

J4520

PG 45

PG 45

PCI-E GEN2

UP TO 8 LANES3

U6201

Audio

Audio
Conns

Codec

U6400, U6500

SPEAKER AMPS

HEADPHONES

INTERNAL/EXTERNAL

MICROPHONES

LINE INPUT

J6600,J6601,J6602,J6603

2 SO-DIMMS

GPIOs

SO-DIMMS

PG 48

INTEL CPU

POWER SUPPLY

TEMP SENSORS

TEMP, CURRENT SENSE

GPU HEATSINK
AMBIENT INTAKE
CPU DIE-PECI

LEFT SKIN TEMP
RIGHT SKIN TEMP

MXM CONNECTOR

J8400

X4 DP

X4 DP

LOGIC

PG 84

X4 DPX4 DP

T29 ROUTER

X4 DP

T29 LANES
T29 LANES

DP LANES TO INT MUX

EXTERNAL

PG 94

PORT CONN

DISPLAY

J9400

X4 DP

PG 90

DISP

INTERNAL

J9002

Misc

INTEL

COUGAR POINT

U1800

PG 46

PG 46

PG 47

EXTA

EXTB

BLUETOOTH

J4610

PG 46

J4700

J4600

PG 47

PG 46

EXTD

J4630

IR

EXTC

J4620

J4780

PG 36

PG 35

USB HUB1

U3500

U3600

USB HUB2

LCD TEMP

OPTICAL DRIVE

HARD DRIVE (OOB)

MXM - GPU DIE

CPU HEATSINK

SATA CONN

X1 PCIE GEN1 LANE 2.5GBITPS

SATA 2.0 3GHZ.

SATA-A1

SYNC_MASTER=K60_SIJI

System Block Diagram

SYNC_DATE=01/06/2011

2 OF 110

11.1.0

051-8115

2 OF 98

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PP12V_T29

PP12V_S5_LED 3.75A

USB Ext Port 4.7A

PP5V_USB_PORTx

Spec:14A(170W)

PM_SLP_S3

ODD_PWR_EN_L (GPIO-22)

ENET_PWR_EN(GPIO-42)

AP_PWR_EN(GPIO-59)

PP3V3_S3

BT

PAGE 34

PP3V3_S3_ENET

PM_SMC_G2_EN

PP12V_S5:Peak 6.9A(83W)

PCH

SMSC USB Hubx2

SWReg ISL8013A 1A
PAGE 78

PP3V3_S3_MINI

FET 2.75A/1.1A/0.19A

FET 0.25A/0.2A/0.06A

PP12V_G3H:

FET 7A/2.7A

SSD 0.8A

HDD 1.8A

P5VS0_EN

FET 2.9A/1.2A

PAGE 80

BOOT ROM

PAGE 80

USB_CAMERA

USB_IR

PM_EN_USB_PWR

FET 12V V@1.1A

1.1A/12V

PP12V_T29

FANS 0.75A

LCD PANEL 0.6A
PP12V_S0_FWR 1.2A

AUDIO 1.7A

PP12V_S0_HDD 1.2A

MXM 3.38A(45W TDP)

PP12V_S0:Peak 16.9A(203W)

12V_G3H

INA219

EMC1403

I2C CLK,DATA

TEMP SENSOR

PAGE 76

8.8A

VCCSA

PPVCCSA

LDO 0.925V@8.8A

PAGE 76

SWReg ISL9563A
PAGE 76

AIRPORT

DP_RDRV 0.7/0.02A

ISL62383 3.3V@6.2A

PP3V3_S5_REG

PAGE 77

P3V3S3_EN

ODD 1.5A

PAGE 38

ETHERNET

SD Card(250mA)

MXM 1A Max

FIREWIRE

FET 3.4A/ 1.9A

PCH

Lazarus(100mA)

PP3V3_S0_SD

AUDIO

PP3V3_S0

ISL62383 5V@10.3A

PP5V_S3_REG

1V05 VCCIO 6.5A (PCH)

1V05 T29 3A (T29)

PP1V05_S0

AC/DC POWER SUPPLY (Spec:215W)

PAGE 48

SMC VREF

VAXG 6.5A

CORE 75A

CPU VCCIO 8.5A (CPU)

1.1V @ 30A

PAGE 71-73

SWreg ISL6364

.65V-1.5V @ 75A/55A

PPVCORE/AXG

CPU PLL

PAGE 46

AUDIO
MXM 2.5A

PCH

FW

PAGE 42

CPU MEM

AUDIO

MEM_VTT

PP0V75_S0

TPS2560

PP5V_S0

P3V3S0_EN

PAGE 77

MAIN MEMORY

PAGE 78

PP1V5_S0

FET 6.2A/3A

PM_SLP_S3

PAGE 80

0.75V @ 0.6A
PAGE 75

PAGE 78

PP1V5_S3_REG

TPS51116, 1.5V 11A/6.7A

PP3V3_S5_AVREF_SMC

PAGE 50

LDO SN0903048

SMC

SW LT3470A

PP3V42_G3H_REG

PAGE 79

12V LED Power
Spec:3.75A (45W)

PP1V8_S0_REG

BJT 1.0V @ 0.08A

PP1V0_FWPHY

SYNC_DATE=01/06/2011

SYNC_MASTER=K60_JERRY

Power Block Diagram

3 OF 110

11.1.0

051-8115

3 OF 98

www.vinafix.vn

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

6
7

BOTTOM

4

3

5

2

TOP

POWER

GROUND

SIGNAL

POWER

SIGNAL

GROUND

SIGNAL

BOARD STACK-UP

SIGNAL

K60 ALTERNATE PARTS

BOM Variants

RAW: 335S0539

CPUS

RAW: 335S0709

RAW: 337S3997

COMMON

RAW: 335S0550

RAW: 338S0878

RAW: 335S0807

K60 PARTS

BOM GROUPS

CPU SOCKET & ILM SUB-BOMS

SYNC_MASTER=K60_AARON

BOM Configuration

SYNC_DATE=N/A

K60,2P7GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,YES_DBG

PCBA,MLB,K60,2.7G,4C,PRQ,P2_ODD

639-1820

K60,2P8GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,YES_DBG

PCBA,MLB,K60,2.8G,4C,PRQ,P2_ODD

639-1821

PCBA,MLB,K60,2.7G,4C,PRQ,P2_ODD,NO_DBG

K60,2P7GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,NO_DBG

639-2159

PCBA,MLB,K60,2.5G,4C,PRQ,P2_ODD,NO_DBG

K60,2P5GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,NO_DBG

639-2160

K60,2P5GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,YES_DBG

PCBA,MLB,K60,2.5G,4C,PRQ,P2_ODD

639-1767

PCBA,MLB,DEV,K60

085-0801

DEVELOPMENT,DEV_GROUP

BASIC2

AP,BT,IR,T29

BASIC1

COMMON,ALTERNATE,MXM,FCIM,CPU_1V5_SENSE,CPU_VCCSA_SENSE,1V05_PCH_SENSE,HUB_USX2061,PRODUCTION,VAXG,SSD

NO_DBG

MOJOMUX:NO,LPCPLUS:NO

371S0652

PIN DIODE

371S0679

USB DIODE

377S0107 377S0066

376S0972 376S0612

ROHM TRA-BJT

128S0293

330UF

128S0298

341T0184

1

FLASH,EFI BOOTROM,K60/K62

CRITICAL

U6100

U3990

SFLASH ENET 2MBIT,CIV

341T0328 CRITICAL

1

T29 ROUTER, IC ASSP

T29

338S0945 CRITICAL

1

U9700

IC,T29,SERIAL EEPROM

T29

341T0257 CRITICAL

1

U9790

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

341T0326

T29

CRITICAL

U9330

1

IC,MXM SYS ROM,24C02

U8570

341T0330

1

CRITICAL

IC,SMC,K60 CRITICAL

1

K60

341T0185

U4900

PCBF,MLB,K60

MLB1

1

K60

820-2641

K60

SCH,MLB,K60

051-8115 SCH1

1

2P5GHZ_SNB_CPU_PRQ

SNB,SR00S,PRQ,D2,2.5,65W,4+1,6M,LGA

337S4043

CPU

1

CRITICAL

2P7GHZ_SNB_CPU_PRQ

SNB,SR009,PRQ,D2,2.7,65W,4+1,6M,LGA

CPU

1

CRITICAL337S4062

2P8GHZ_SNB_CPU_PRQ

CPU

1

CRITICAL

SNB,SR00E,PRQ,D2,2.8,65W,4+1,8M,LGA

337S4061

TYCO_SOCKET

U1000

511S0071 CRITICAL

1

SOCKET,LGA1155,CPU-LF

ILM

604-1474

1

TYCO_SOCKET

ASSY,PURCHASED,ILM,TYCO

CRITICAL

U1000

MOLEX_SOCKET

CRITICAL

SOCKET,LGA1155,CPU-LF

1

511S0073

604-1161

MOLEX_SOCKET

ILM

1

ASSY,PURCHASED,ILM,MOLEX

CRITICAL

SUB ASSY,CPU SOCKET,K60,TYCO

TYCO_SOCKET

085-2452

085-2453

SKT_ILM

MOLEX ALTERNATE

085-2452

CRITICAL

1

TYCO CPU SOCKET AND ILM

SKT_ILM

085-2452

085-2453 MOLEX_SOCKET

SUB ASSY,CPU SOCKET,K60,MOLEX

DEV_GROUP

VREFMRGN_A,VREFMRGN_B,DIMM_1V5_SENSE

YES_DBG

XDP,XDP_CONN,XDP_CPU_BPM,MOJOMUX:YES,LPCPLUS:YES

IC,BCM57765,ENET&SD,8X8

CRITICAL343S0534

1

U3900

MLB LABEL,48.0X4.8

X14

CRITICAL825-7122

1

353S3055

IC,PI3VEDP212,X2 DP MUX,QFN

CRITICAL

1

U9390

IC,FW643,1394B_PCIE,PHY/LINK

U4100

CRITICAL338S0753

1

337S4088

IC,COUGAR POINT,SLJ4F,BD82Z68,PRQ,B3

1

CRITICAL

U1800

639-2118

PCBA,MLB,K60,2.5G,4C,PRQ,P1_ODD

K60,2P5GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,YES_DBG

PCBA,MLB,K60,2.7G,4C,PRQ,P1_ODD

639-2122

K60,2P7GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,YES_DBG

PCBA,MLB,K60,2.8G,4C,PRQ,P1_ODD

K60,2P8GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,YES_DBG

639-2119

PCBA,MLB,K60,2.5G,4C,PRQ,P1_ODD,NO_DBG

K60,2P5GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,NO_DBG

639-2132

PCBA,MLB,K60,2.7G,4C,PRQ,P1_ODD,NO_DBG

K60,2P7GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,NO_DBG

639-2133

K60,2P8GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,NO_DBG

639-2134

PCBA,MLB,K60,2.8G,4C,PRQ,P1_ODD,NO_DBG

PCBA,MLB,K60,2.8G,4C,PRQ,P2_ODD,NO_DBG

K60,2P8GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,NO_DBG

639-2161

4 OF 110

11.1.0

051-8115

4 OF 98

www.vinafix.vn

IN

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D

S

IN

G

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IN

G

D

S

IN

IN

G

D

S

G

D

S

IN

G

D

S

IN

G

D

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IN

G

D

S

IN

IN

G

D

S

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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SHEET

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A

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

S5 Led

SILKSCREEN:1

SILKSCREEN:6

SILKSCREEN:7

SILKSCREEN:8

SILKSCREEN:10

SILKSCREEN:11

VIDEO ON Led

MXM PWR GOOD Led

SILKSCREEN:4

SILKSCREEN:3

SILKSCREEN:2

SILKSCREEN:9

SILKSCREEN:12

ALL_SYS_PWRGD Led

PROTO DEBUG LEDS ARE SHOWN BELOW

SILKSCREEN:5

19 26 32 36 46 47 63 82 97

K

A

LED550

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

SILK_PART=VCORE_PGOOD

4

5

3

Q540

SOT-363

2N7002DW-X-G

DEVELOPMENT

25 64 65 97

K

A

LED500

2.0X1.25MM-SM

DEVELOPMENT

GREEN-3.6MCD

SILK_PART=SLP_S4

K

A

LED530

SILK_PART=DDR_PGOOD

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

2

1

R540

DEVELOPMENT

MF-LF

5%

3.3K

1/16W
402

1

2

6

Q520

2N7002DW-X-G

SOT-363

DEVELOPMENT

63 71 97

K

A

LED540

SILK_PART=PCHCORE_PGOOD

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

1

2

6

Q540

SOT-363

2N7002DW-X-G

DEVELOPMENT

64 97

2

1

R500

3.3K

5%
MF-LF

DEVELOPMENT

1/16W
402

2

1

R530

DEVELOPMENT

3.3K

5%
MF-LF

1/16W
402

2

1

R550

3.3K

5%
MF-LF

DEVELOPMENT

1/16W
402

2

1

R502

1/16W

5%
MF-LF

1K

402

81

K

A

LED502

GREEN-3.6MCD

2.0X1.25MM-SM

4

5

3

Q502

2N7002DW-X-G

SOT-363

4

5

3

Q500

DEVELOPMENT

SOT-363

2N7002DW-X-G

2

1

R504

5%
MF-LF

1/16W
402

1K

32 64 97

K

A

LED504

GREEN-3.6MCD

2.0X1.25MM-SM

2

1

R505

DEVELOPMENT

MF-LF

5%

1K

1/16W
402

K

A

LED505

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

2

1

R501

1K

1/16W
402

MF-LF

5%

K

A

LED501

2.0X1.25MM-SM

GREEN-3.6MCD

2

1

R510

402

1/16W

DEVELOPMENT

5%

3.3K

MF-LF

2

1

R503

402

1K

5%
1/16W
MF-LF

K

A

LED503

2.0X1.25MM-SM

GREEN-3.6MCD

1

2

6

Q502

2N7002DW-X-G

SOT-363

21 25 97

2

1

R549

DEVELOPMENT

3.3K

MF-LF

5%
1/16W

402

K

A

LED542

GREEN-3.6MCD

2.0X1.25MM-SM

SILK_PART=VAXG_PGOOD

DEVELOPMENT

4

5

3

Q520

2N7002DW-X-G

SOT-363

DEVELOPMENT

65 97

K

A

LED510

SILK_PART=SLP_S3

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

2

1

R560

DEVELOPMENT

5%
MF-LF

3.3K

1/16W
402

K

A

LED560

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

SILK_PART=SLP_S5

4

5

3

Q530

2N7002DW-X-G

SOT-363

DEVELOPMENT

19 46 47 63 97

2

1

C501

20%

0.1UF

10V
402

CERM

19 32 46 47 63 97

1

2

6

Q500

SOT-363

DEVELOPMENT

2N7002DW-X-G

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

DEBUG LEDS

=PP3V3_S5_LED

=PP3V3_S5_LED

CORE_VOLTAGES_ON

PM_PGOOD_PVCORE_CPU

=PP3V3_S0_LED

GPU_PRESENT_R

VIDEO_ON_L

PM_LED1_AXG

=PP3V3_S0_LED

PM_LED_AXG

PM_LED_PCHCORE

PM_LED1_PCHCORE

PGOOD_PCH_S0

MXM_GOOD

GPU_PRESENT_DRAIN

=PP3V3_S0_LED

LCD_SHOULD_ON_R

=PP3V3_S0_LED

PM_LED1_DDRREG

PM_LED_DDRREG

PM_LED1_S3

PM_LED_S3

PM_LED1_PVCORE

CORE_VOLTAGES_ON_R

=PP3V3_S3_LED

ITS_PLUGGED_IN

PM_PGOOD_DDR1V5_S3_REG

PM_LED_PVCORE

PM_PGOOD_PVAXG

=PP3V3_S3_LED

ITS_ALIVE

PM_SLP_S4_L

PM_LED1_S4

=PP3V3_S5_LED

PM_LED_S4

PM_LED_S5

=PP3V3_S5_LED

PM_LED1_S5

PM_SLP_S5_L

PM_SLP_S3_L

ALL_SYS_PWRGD_R

=PP3V3_S5_LED

=PP3V3_S0_LED

5 OF 110

11.1.0

051-8115

5 OF 98

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5 6

5 6

5 6

5 6

5 6

5 6

5 6

5 6

5 6

5 6

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IN

BI

G

S

D

IN

G

S D

BI

IN

G

S D

IN

IN

BI

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

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8 7 5 4 2 1

3V3 RISES BEFORE

MLB TO BLC

ISOLATION CIRCUIT

FET DIODE IS S TO D

MLB 3V3).

(FACES BLC WHICH

POWER SUPPLY TO MLB

"G3H" RAILS

T29 RAILS

ON IN RUN AND SLEEP

BLC SDA/SCL

518S0543

MLB TO PS

518S0813

518-0373

ALWAYS ON WHEN UNIT HAS AC POWER AND IN S5

ONLY ON IN RUN

"S0" RAILS

"S5" RAILS

GND RAILS

"S3" RAILS

ALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC

G3H: ALIASES

2

1

C602

402

CERM

50V

5%

47PF

21

R602

402

1/16W

0

5%

2

1

C604

CERM
402

50V

47PF

5%

21

R601

402

0

5%

1/16W

2

1

C603

0.001UF

10%
X7R

50V
402

PLACE C603 CLOSE TO CONNECTOR

49

49

2

1

C610

603-1

PLACE C610 CLOSE TO CONNECTOR

25V
X5R

10%

1UF

21

R605

0

402

5%

1/16W

6

5

4

3

2

1

J600

M-RT-TH

76833-0106

2

1

3

Q610

2N7002

SOT23-HF1

2

1

C606

X7R

PLACE C606 CLOSE TO CONNECTOR

10%

0.001UF

50V
402

63 97

2

1

C611

PLACE C611 CLOSE TO CONNECTOR

25V
X5R

10%

1UF

603-1

7

6

5

4

3

2

1

J601

50293-00771-H01

M-ST-SM

CRITICAL

21

R631

0

1/16W

402

5%

2

1

C628

NOSTUFF

402

47PF

5%
50V
CERM

8

7

6

5

4

3

2

1

10

9

J602

CRITICAL

F-RT-SM

53780-8608

2

1

R620

402

MF-LF

1/16W

5%

0

21

R622

0

1/16W

402
5%

21

L602

FERR-1000-OHM

0402

2

1

C627

NOSTUFF

47PF

402

5%
50V
CERM

21

R630

5%

1/16W

0

402

1

2

6

Q600

2N7002DW-X-G

SOT-363

49 81 94

49 81 94

2

1

C621

47PF

5%

402

CERM

50V

NOSTUFF

21

R617

1/16W

402

5%

0

NOSTUFF

21

R618

5%

402

0

NOSTUFF

1/16W

4

5

3

Q600

2N7002DW-X-G

SOT-363

15 21 91

81 97

49

49

2

1

C622

NOSTUFF

50V

5%

402

47PF

CERM

Power Conn / Alias

SYNC_MASTER=K60_MARK SYNC_DATE=12/30/2010

GND

MAX_NECK_LENGTH=4.1 MM

MIN_LINE_WIDTH=0.6MM

NET_SPACING_TYPE=GND

VOLTAGE=0V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

=PP3V3_G3H_LPCPLUS

=PP3V3_G3H_SMCUSBMUX

=PP3V3_G3H_SMC

PP3V42_G3H_REG

=PP12V_S5_T29_A

=PP12V_S5_PWRCTL

=PP12V_S5_P5VS3_VREG

PP12V_S5_FET

PP5V_S5_LDO

=PP5V_S5_PCH

NET_SPACING_TYPE=POWER

MIN_LINE_WIDTH=0.6MM

VOLTAGE=3.42V
MIN_NECK_WIDTH=0.2MM

MAKE_BASE=TRUE

MAX_NECK_LENGTH=3 MM

PP3V42_G3H

VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=POWER

MAKE_BASE=TRUE

MAX_NECK_LENGTH=3 MM

PP12V_S5

MAKE_BASE=TRUE

NET_SPACING_TYPE=POWER

VOLTAGE=5V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm

MAX_NECK_LENGTH=3 MM

PP5V_S5

=PP3V3_S5_RSTBUF

=PP3V3_S5_PCH_VCCSUS3_3_USB

=PP3V3_S0_SMC_LS

=PP3V3_S0_SMBUS

=PP3V3_S0_ENET_PHY

=PP3V3_S0_T29I2C

=PP3V3_S0_DP
=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_S0_PCH_PM

=PP3V3_S0_P1V05_VREG
=PP3V3_S0_PCH_VCC3V3

=PP3V3_S3_VRD

=PP3V3_S3_VREFMRGN

=PP3V3_S0_DPSDRVA
=PP3V3_S0_INTDPMUX

=PP1V5_S0_CK505

=PP3V3_S0_SATALED

=PP3V3_S0_PCH_VCC3_3_GPIO

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.4MM

NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM

MIN_NECK_WIDTH=0.2MM

MAKE_BASE=TRUE

PP1V5_S0

=PP1V5_S0_PWR

PP1V5_S0_FET
=PP1V5_S0_AUD_DIG

=PPVCCSA_S0_PWRCTL

=PPVCCIO_S0_CPU_VCCSA

PPVCCSA_S0_INPUT_SNS

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.05V

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

NET_SPACING_TYPE=POWER

PP1V05_S0_INPUT_VCCSA

=PP3V3_S0_T29PWRCTL

=PP3V3_S0_P3V3T29FET

=PP3V3_S0_LED

=PP3V3_S0_VRD

=PP3V3_S0_SDCARD

=PP3V3_S0_SMBUS_SMC_BSA

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_STRAPS

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_FWPHY

=PP3V3_S0_PWRCTL

=PP3V3_S0_SENSE

=PP3V3_S0_ODD

=PP3V3_S0_MXM

=PP3V3_S0_SMBUS_SMC_0

=PPSPD_S0_MEM_B

=PP3V3_S0_PCH

PP3V3_S0_FET

=PP1V5_S0_CPU_MEM

PPVAXG_S0

MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=POWER

PP1V05_S0_REG
=PP1V05_S0_PWR

PP12V_S0_PS

=PP5V_S0_LPCPLUS

=PP5V_S3_P3V3R2V9_REG_A

=PP5V_S3_VREFMRGN

=PP5V_S3_DDR_VREG

=PP5V_S3_MEMRESET

=PP5V_S3_IR

=PP5V_S3_CAMERA

MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER

VOLTAGE=5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM

PP5V_S3

=PP3V3_S5_CPU_VCCSA

=PP3V3_S5_MEMRESET

=PP3V3_S5_PCH

=PP3V3_S5_PCH_GPIO

=PP3V3_S5_PCH_VCCSPI

=PP3V3_S5_S3FET

=PP3V3_S5_VRD

PP3V3_S5_REG

NET_SPACING_TYPE=POWER

MIN_NECK_WIDTH=0.25MM

MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM

MAX_NECK_LENGTH=3 MM

PP1V05_S0

=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCC_CORE

=PP12V_S0_CPU_VCCSA

PP12V_S0_MXM_SNS

=PP12V_S0_MXM

=PP12V_S0_SENSE

=PP12V_S0_PWRCTL

=PP12V_S0_P1V05_VREG

=PP12V_S0_LCD

=PP12V_S0_VRD

=PP12V_S0_AUDIO_SPKRAMP

=PP3V3_SW_DPAPWR

=PP3V3_S3_MEMRESET

=PP1V05_S0_PCH_VCCADPLL

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=POWER

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.05V

PP1V05_S0_PCH

=PPVCCIO_S0_CPU

=PPVCCIO_S0_XDP

=PP12V_S0_MXM_PWR

PP1V5_S3_REG

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

VOLTAGE=12V

NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM

PP12V_S0_MXM

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH

=PP1V8_S0_PCH

=PP5V_S0_P1V8_REG

PPVCORE_S0_CPU_REG

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_PWR

=PP3V3R1V8_S0_PCH_VCCDFTERM

=PP1V8_S0_CPU_PLL

=PP0V75_S0_MEM_VTT_A

=PPVCORE_S0_CPU

=PPVCCSA_S0_INPUT_PWR

=PP5V_S0_P1V05_VREG

=PP5V_S0_PCH

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_PWR

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_PWRCTL

PP1V8_S0_REG

PP0V75_S0

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0.75V

=PP1V05_S0_PCH_V_PROC_IO

NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.5V

MAKE_BASE=TRUE

PP1V5_S3

=PP12V_S0_SATA

PPVAXG_S0_REG

=PP3V3_T29_RTR

=PP12V_G3H_S5_FET

=PP1V05_S0_PCH_VCCSSC

=PP0V75_S0_MEM_VTT_B

PPVTT_S0_DDR_FET

MAX_NECK_LENGTH=3 MM

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
NET_SPACING_TYPE=POWER

MAKE_BASE=TRUE

PPVCORE_S0_CPU

=PP5V_S0_MXM

=PP5V_S0_AUDIO

=PP5V_S0_VRD

PP1V05_T29_FET
=PP1V05_T29_RTR
=PP1V05_T29

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=POWER

VOLTAGE=1.05V
MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

PP1V05_S0_T29

=PPVCCIO_S0_SMC

=PP1V5_S3_S0FET

PP3V3_T29_FET

=PP1V05_S0_PCH_VCCDIFFCLK

PP1V05_S0_PCH_SNS

=PP5V_S0_ISENSE

=PP1V05_S0_CK505

PP12V_G3H_ACDC

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=POWER

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PP3V3_S0_T29

=PP0V75_S0_MEM_VTT_S0FET

PP5V_S0_FET

=PP12V_G3H_3V42

MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm

NET_SPACING_TYPE=POWER

MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM

PP12V_G3H

=PP12V_S0_FAN

=PP5V_S0_SATA

=PP3V3_S3_LED

MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm

NET_SPACING_TYPE=POWER

MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM

PP5V_S0

PP1V5_S3_MEM_SNS

NET_SPACING_TYPE=POWER

VOLTAGE=1.5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAX_NECK_LENGTH=3 MM

PP1V5_S3_MEM

=PP3V3_S3_SDCARD

=PP3V3_S3_ENET_PHY

=PP3V3_S3_USB_HUB

=PP3V3_S3_PWRCTL

=PP3V3_S3_SMBUS_SMC_A

=PP3V3_S0_AUDIO

=PP3V3_S5_ROM

=PP3V3_S5_PCH_STRAPS

=PP3V3_S5_P3V3R2V9_A

MAKE_BASE=TRUE

NET_SPACING_TYPE=POWER

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

MAX_NECK_LENGTH=3 MM

PP3V3_S5

=PP3V3_S5_SMCUSBMUX
=PP3V3R1V5_S5_PCH_VCCSUSHDA

=PP12V_S0_FW

NET_SPACING_TYPE=POWER

MIN_NECK_WIDTH=0.5mm

MIN_LINE_WIDTH=1mm

VOLTAGE=12V

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

PP12V_S0

=PP1V05_S0_P1V05T29FET

=PP1V05_S0_PCH_VCCIO_DMI

=PP1V05_S0_PCH_VCCIO_USB

=PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.4MM
NET_SPACING_TYPE=POWER

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM

VOLTAGE=3.3V

PP3V3_S0

=PP1V5_S0_MINI

PPVTT_S0_DDR_LDO

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5MM
NET_SPACING_TYPE=POWER

VOLTAGE=1.8V

MAX_NECK_LENGTH=3 MM

MIN_NECK_WIDTH=0.25MM

PP1V8_S0

=PP3V3_S0_SMBUS_SMC_B
=PP3V3_S0_SMBUS_SMC_MGMT

NET_SPACING_TYPE=POWER

PPVTT_S0_DDR

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MAX_NECK_LENGTH=3 MM

VOLTAGE=0.75V

PP12V_G3H_ACDC

PP12V_S0_PS

PS_ON

BL_PWM

BL_EN

SMB_ACDC_SCL_RC

ISOLATED_GND2

=SMB_ACDC_SDA

PM_EN_P12V_S0_FET

=SMB_ACDC_SCL

SMB_BLC_PCH_SDA_R

ISOLATED_GND

VSYNC_DP_CONN_R

BLC_GPIO_R

VSYNC_DP_CONN

BLC_GPIO

=SMB_BLC_PCH_SCL

=PP3V3_G3H_RTC_D

=PP12V_S5_DDR_VREG

=PP3V3_S5_LED

=PP3V3_S5_USB_HUB

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_LPCPLUS

=PP3V3_S5_XDP

=PP3V3_S5_S0FET

=PP3V3_S5_PWRCTL

SMB_BLC_TCON_SCL

=PP1V5_S0_DP

=PPVAXG_S0_CPU

SMB_BLC_TCON_SCL_R

SMB_BLC_TCON_SDA_R

SMB_BLC_TCON_SDA

SMB_BLC_PCH_SCL_R

=PP3V3_S0_CK505

PP1V5_S0_CPU_MEM_SNS

PP1V5_S0_CPU_MEM

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=POWER

VOLTAGE=1.5V

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2MM

=SMB_BLC_PCH_SDA

=PP3V3_S0_SMBUS

SMB_ACDC_SDA_RC

VOLTAGE=0.925V
MIN_NECK_WIDTH=0.3MM

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER

MAX_NECK_LENGTH=3 MM

PPVCCSA_S0_CPU PPVCCSA_S0_FET

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PPSPD_S0_MEM_A

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_FAN

=PP5V_S3_S0FET

=PP5V_S3_USB

PP5V_S3_REG

=PP3V3_S3_SYSCLK

=PP3V3_S3_MINI

=PP3V3_S3_BT

PP3V3_S3_FET

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A

=PP3V3_S3_P3V3R2V9_REG_A
=PP3V3_S3_PCH

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=POWER

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

PP3V3_S3

6 OF 110

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051-8115

6 OF 98

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43

46 47

72

82

33 64 73

70

74 95

70

24

95

95

95

27

22 24

47 51

6

49

36 37

49

81

22 24

27

68

22 24

71

28

84

83

26

18 42

22 24

95

50

73

56

64

69

50 95

80

80

5

65 68

45

49

11 27

22 24

15

20 45

39 40 41

63 64 73 80

50 52

42

21 64 75 76

49

31

18 21 24

73

11 13 16 28 29

95

68

50

6

48

82

28

71

32

44

44

95 98

69

32

18 19 21 24

20

22 24

73

70

70

95

18 22 24

18 19 22 24

22 24

69

50

75

51

63 64 80

68

81

65

58 59

78

32

17

95

10 11 13 16 65

25

50

71

95

22 24

18 24 79

19

71

66

32

50

22 24

13 16

30

13 16 50 65

50 69 68

24

22 24

50

24 79

64

71

95

22 24

95

42

67

79 80 86 87

74

22 24

31

32

95

75

56

65 67

80

87

80

95

46 47

73

80

22 24

50

50

26

6

95

32

73

72

95

53 54

42

5

95 98

50 95

44 45

36

34 35

64 73 82

49

56 58 59 60 61 62

48 55

15

82

95

43

24

41

95

80

22 24

22 24

13 50

95

33

71

95

49

49

95

6

6

83 97

81 97

27

71

5

34

22 24

48

25

73

11 63 64

83

13 17 50 65

26

50 95

6

49

95 69

24

30 47

17

53 54

73

43

70

79

33

44

73

28 29 31

28 29 30

82

21

95 98

www.vinafix.vn

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MXM STANDOFFS (835-0272)

Rear Cover

Standoffs (was 860-1255 but now replaced with 860-1430)

4mm Plated Holes (998-0850)

DIMM CONNECTOR NUTS

Nuts (805-9582)

CPU Heatsink

PCH HEATSINK

MOUNTING HOLES (998-0873, 998-0976)

EMC Spring (870-1577); Near DIMMs

For EMC

1

ZH0700

OMIT

4P75R4

1

ZH0701

OMIT

4P75R4

1

ZH0702

OMIT

4P75R4

1

ZH0703

OMIT

4P75R4

1

SC0702

NOSTUFF

EMI-SPRING

CLIP-SM-K2

1

SDF0713

CRITICAL

STDOFF-6.8OD15.0H-1.56-TH

OMIT_TABLE

1

NUT0753

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

NUT0752

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

NUT0751

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

NUT0750

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

SDF0714

CRITICAL

STDOFF-6.8OD15.0H-1.56-TH

OMIT_TABLE

1

SDF0715

CRITICAL

STDOFF-6.8OD15.0H-1.56-TH

OMIT_TABLE

1

SDF0717

CRITICAL

STDOFF-6.8OD15.0H-1.56-TH

OMIT_TABLE

1

SDF0718

CRITICAL

STDOFF-6.8OD15.0H-1.56-TH

OMIT_TABLE

1

ZH0711

OMIT

5P45R3P6

1

ZH0712

5P45R3P6

OMIT

1

SDF0721

CRITICAL

NUT-6.5OD2.7H-1.56-3.8-TH

1

SDF0720

NUT-6.5OD2.7H-1.56-3.8-TH

CRITICAL

Holes

SYNC_MASTER=K74_MASTER

SYNC_DATE=N/A

STANDOFF,MLB,K60/K62

860-1430

5

SDF0713,SDF0714,SDF0715,SDF0717,SDF0718

7 OF 110

11.1.0

051-8115

7 OF 98

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC ON UNUSED PCI ALIASES

UNUSED CPU SIGNALS

NC ON UNUSED MISC ALIASES

NC ON UNUSED FDI ALIASES

NC ON UNUSED MEM ALIASES

NC ON UNUSED DISPLAY ALIASES

NC ON UNUSED USB ALIASES

NC ON UNUSED SATA ALIASES

NC ON UNUSED PCIE ALIASES

SYNC_DATE=01/06/2011

UNUSED SIGNAL ALIAS

SYNC_MASTER=K62

TP_CRT_IG_HSYNC

NC_DP_IG_C_AUXN

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_DP_IG_C_HPD

TP_SATA_E_R2D_CN

TP_SATA_D_D2RN

TP_SATA_F_D2RN

NC_PE_RXN<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_DP_IG_B_MLN<3..0>
TP_DP_IG_B_MLP<3..0>
TP_DP_IG_B_AUX_N
TP_DP_IG_B_AUX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_R2D_PETP4

TP_PCIE_D2R_PERP4

TP_PCIE_R2D_PETP4

TP_PCIE_R2D_PETN4 NC_PCIE_R2D_PETN4

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_D2R_PERN4

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_D2R_PERP4

TP_USB_13N

MAKE_BASE=TRUE

NC_USB_13N

NO_TEST=TRUE

TP_USB_13P

MAKE_BASE=TRUE

NC_USB_13P

NO_TEST=TRUE

TP_USB_12P NC_USB_12P

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_USB_12N NC_USB_12N

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_USB_11P

NO_TEST=TRUE

NC_USB_11P

MAKE_BASE=TRUE

TP_USB_11N

MAKE_BASE=TRUE

NC_USB_11N

NO_TEST=TRUE

TP_USB_10N NC_USB_10N

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_USB_10P NC_USB_10P

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_USB_7N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_7N

TP_USB_7P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_7P

TP_USB_6P

NO_TEST=TRUE

NC_USB_6P

MAKE_BASE=TRUE

TP_USB_6N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_6N

TP_USB_5N NC_USB_5N

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_USB_5P

NO_TEST=TRUE

NC_USB_5P

MAKE_BASE=TRUE

TP_USB_4P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_4P

TP_USB_3P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_3P

TP_USB_4N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_4N

TP_USB_3N NC_USB_3N

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_USB_2P

NO_TEST=TRUE

NC_USB_2P

MAKE_BASE=TRUE

TP_USB_2N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_2N

TP_USB_1P

NO_TEST=TRUE

NC_USB_1P

MAKE_BASE=TRUE

TP_USB_1N

NO_TEST=TRUE

NC_USB_1N

MAKE_BASE=TRUE

TP_CRT_IG_BLUE

TP_PCI_RESET_L

MAKE_BASE=TRUE

NC_PCI_RESET_L

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_AD<31..0>

NC_PCI_PAR

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_DP_IG_B_DDC_DATA

MAKE_BASE=TRUE

NC_MEM_A_DQ_CB<7..0>

NO_TEST=TRUE

TP_PE_RX_N<3..0>

NC_PE_TXN<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_DP_IG_C_CTRL_CLK

TP_PCH_FDI_RX_P<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_MLP<3..0>

NO_TEST=TRUE

NC_DP_IG_B_AUXN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_MLN<3..0>

TP_PCI_C_BE_L<3..0>

TP_PCH_L_BKLTCTL

TP_PCH_L_BKLTEN

TP_PCH_L_VDD_EN

TP_SDVO_TVCLKINN

NC_SDVO_TVCLKINP

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCH_FDI_RX_N<7..0>

TP_CPU_FDI_TX_N<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_D_D2RN

NC_PCH_FDI_RXN<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE7N

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE7P

MAKE_BASE=TRUE

TP_DP_IG_B_HPD

TP_DP_IG_C_AUX_N

TP_CRT_IG_DDC_DATA

TP_MEM_A_DQS_N<8>

MAKE_BASE=TRUE

NC_MEM_A_DQSN<8>

NO_TEST=TRUE

TP_MEM_A_DQ_CB<7..0>

MAKE_BASE=TRUE

NC_PCH_CL_RST1

NO_TEST=TRUE

TP_PCH_SST

TP_PCH_PWM2

MAKE_BASE=TRUE

NC_PCH_L_BKLTEN

NO_TEST=TRUE

TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP

NC_PCH_CLKOUT_DPN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_CLKOUT_DPP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_L_VDD_EN

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_MLN<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_E_R2D_CP

NC_SATA_E_R2D_CN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_D_R2D_CP

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_D_R2D_CN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_D_D2RP

TP_SATA_E_D2RP

TP_SATA_D_D2RP

TP_SATA_E_D2RN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_F_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_RXP<7..0>

TP_CPU_FDI_TX_P<7..0>

NC_CPU_FDI_TXN<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

NO_TEST=TRUE

NC_DP_IG_D_CTRL_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_AUXN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_MLP<3..0>

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_HPD

NC_DP_IG_B_CTRL_DATA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_CTRL_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_BLUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_GREEN

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_DDC_DATA

TP_CRT_IG_RED

TP_MEM_B_DQS_P<8>

NC_HDA_SDIN1

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_DP_IG_D_HPD

TP_DP_IG_D_CTRL_DATA

TP_SDVO_STALLN

TP_DP_IG_D_MLP<3..0>

TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUX_P

TP_DP_IG_C_MLP<3..0>

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_B_DDC_CLK

TP_CRT_IG_VSYNC

NO_TEST=TRUE

NC_PCH_PWM0

MAKE_BASE=TRUE

NC_HDA_SDIN3

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HDA_SDIN2

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_DQSP<8>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_DQSN<8>

TP_MEM_B_DQS_N<8>

NC_MEM_B_DQ_CB<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_DQSP<8>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MEM_A_DQS_P<8>

TP_PCH_PWM1

TP_HDA_SDIN1

TP_MEM_B_DQ_CB<7..0>

TP_HDA_SDIN3

TP_HDA_SDIN2

NC_SATA_F_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_DATA

NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CN

NC_DP_IG_D_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_MLN<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_FDI_TXP<7..0>

NO_TEST=TRUE

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_AUXP

MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_CLK

NO_TEST=TRUE

NC_DP_IG_D_AUXP

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUE

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

MAKE_BASE=TRUE

NC_SDVO_INTP

NO_TEST=TRUE

NO_TEST=TRUE

NC_SDVO_INTN

MAKE_BASE=TRUE

NC_PCH_L_BKLTCTL

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_AUXP

NO_TEST=TRUE

TP_DP_IG_D_AUXN

NC_SDVO_STALLP

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCH_PWM3

NO_TEST=TRUE

NC_PCH_SST

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_PWM3

MAKE_BASE=TRUE

TP_PCH_CL_DATA1

TP_PCH_CL_RST1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_PWM2

MAKE_BASE=TRUE

NC_PCH_PWM1

NO_TEST=TRUE

TP_PCH_PWM0

NC_PCH_CL_DATA1

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCH_CL_CLK1 NC_PCH_CL_CLK1

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCI_AD<31..0>

TP_LPC_DREQ0_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

TP_DP_IG_D_MLN<3..0>

TP_CRT_IG_DDC_CLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PE_RXP<3..0>

TP_PE_RX_P<3..0>

TP_PE_TX_N<3..0>

NC_PE_TXP<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_RED

NO_TEST=TRUE

NO_TEST=TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

TP_SDVO_TVCLKINP

TP_CRT_IG_GREEN

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N

NO_TEST=TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE6N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE7P

TP_CPU_RSVD<46..19>

TP_CPU_RSVD<16..1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_RSVD<16..1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_RSVD<46..19>

TP_PCI_PAR

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LPC_DREQ0_L

TP_PCIE_D2R_PERN4

TP_PE_TX_P<3..0>

8 OF 110

11.1.0

051-8115

8 OF 98

19

19

18

18

18

19

19

19

19

18

18

18

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

19

20

19

10

19

19

20

18

18

18

19

19

10

19

19

19

12

12

21

21

18

18

18

18

18

18

18

18

18

18

18

10

19

12

19

19

19

19

19

19

19

19

19

19

12

12

21

18

12

18

18

19

19

19

19

19

19

21

18

18

21

18

20

18

19

19

10

10

19

19

18

18

21

21

18

18

21

21

10

10

20

18

10

www.vinafix.vn

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

OUT

OUT

IN

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

THIS SIGNAL NAME IS CONNECTED TO MXM

PEG Slot Support

77 90

77 90 10

10

77 90

77 90

10

10

18

18

19 91 97

21

R929

PLACEMENT_NOTE=PLACE CLOSE TO U1800

1/16W

5%

MF-LF

22

402

46 91 97

75 97 21

75

75

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

Signal Aliases

CLK_100M_MXM_P

MAKE_BASE=TRUE

PEG_RESET_LMXM_RESET_L

PEG_CLK100M_P

PM_CLK32K_SUSCLK_R

PM_CLK32K_SUSCLK

=PEG_D2R_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

=PEG_R2D_C_N<0..15>

=PEG_D2R_N<0..15>

MAKE_BASE=TRUE

MXM_CLKREQ_LPEG_CLKREQ_L

=PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

GPU_CLK100M_PCIE_N

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

CLK_100M_MXM_N

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

GPU_CLK100M_PCIE_P

MAKE_BASE=TRUE

PEG_CLK100M_N

9 OF 110

11.1.0

051-8115

9 OF 98

27 97 75

90

90

www.vinafix.vn

IN
IN
IN
IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

PEG_TX_6*

PEG_RX_5*

PEG_RX_0*

PEG_RX_2*

PEG_RX_7*
PEG_RX_8*
PEG_RX_9*

PEG_RX_10*

PEG_RCOMPO

PEG_RX_14

PEG_RX_13

PEG_RX_6*

PEG_RX_12*

PEG_RX_14*

PEG_RX_1

PEG_ICOMPO

PEG_COMPI

FDI_INT

FDI_ICOMPO

FDI_COMPIO

DMI_RX_0

DMI_RX_0*

DMI_RX_1

DMI_RX_1*

DMI_RX_2

DMI_RX_2*

DMI_RX_3

DMI_RX_3*

DMI_TX_0

DMI_TX_0*

DMI_TX_1
DMI_TX_2

DMI_TX_2*

DMI_TX_3

DMI_TX_3*

FDI_FSYNC_0
FDI_FSYNC_1

FDI_LSYNC_0
FDI_LSYNC_1

FDI_TX_0

FDI_TX_0*

FDI_TX_1

FDI_TX_1*

FDI_TX_2

FDI_TX_2*

FDI_TX_3

FDI_TX_3*

FDI_TX_4

FDI_TX_4*

FDI_TX_5

FDI_TX_5*

FDI_TX_6

FDI_TX_6*

FDI_TX_7

FDI_TX_7*

PEG_RX_0

PEG_RX_1*

PEG_RX_2
PEG_RX_3

PEG_RX_3*

PEG_RX_4

PEG_RX_4*

PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11

PEG_RX_11*

PEG_RX_12

PEG_RX_13*

PEG_RX_15

PEG_RX_15*

PEG_TX_0

PEG_TX_0*

PEG_TX_1

PEG_TX_1*

PEG_TX_2

PEG_TX_2*

PEG_TX_3

PEG_TX_3*

PEG_TX_4

PEG_TX_4*

PEG_TX_5

PEG_TX_5*

PEG_TX_6

PEG_TX_7

PEG_TX_7*

PEG_TX_8

PEG_TX_8*

PEG_TX_9

PEG_TX_9*

PEG_TX_10

PEG_TX_10*

PEG_TX_11

PEG_TX_11*

PEG_TX_12

PEG_TX_12*

PEG_TX_13

PEG_TX_13*

PEG_TX_14

PEG_TX_14*

PEG_TX_15

PEG_TX_15*

PE_RX_0

PE_RX_0*

PE_RX_1

PE_RX_1*

PE_RX_2

PE_RX_2*

PE_RX_3

PE_RX_3*

PE_TX_0

PE_TX_0*

PE_TX_1

PE_TX_1*

PE_TX_2

PE_TX_2*

PE_TX_3

PE_TX_3*

DMI_TX_1*

PCI EXPRESS

DMI

FLEXIBLE DISPLAY INTERFACE

(1 OF 10)

PCI EXPRESS -- GRAPHICS

RSVD_C39
RSVD_D38

RSVD_C38

RSVD_H7
RSVD_H8
RSVD_J9

RSVD_AY10

RSVD_AW34

RSVD_AV34

RSVD_AU10

RSVD_AT14

RSVD_AT11

RSVD_AP20

RSVD_AN20

RSVD_AJ31

RSVD_AJ30

RSVD_AJ29

RSVD_AJ11

RSVD_AG4

RSVD_AF4

RSVD_AE6

RSVD_AD37

RSVD_AD35

RSVD_AD34

RSVD_AB7

RSVD_AB6

RSVD_R40

RSVD_R38

RSVD_R36

RSVD_R34

RSVD_P39

RSVD_P37

RSVD_P35

RSVD_N34

RSVD_N33

RSVD_M34

RSVD_L34

RSVD_L33

RSVD_L31

RSVD_L9

RSVD_K34

RSVD_K31

RSVD_K9

CFG_17

CFG_16

CFG_15

CFG_14

CFG_13

CFG_12

CFG_11

CFG_10

CFG_9

CFG_7

CFG_6

CFG_5

CFG_4

CFG_3

CFG_2

CFG_1

CFG_0

RSVD_J31
RSVD_J33
RSVD_J34

CFG_8

NCTF_A38

NCTF_C2

NCTF_D1
NCTF_AU40
NCTF_AW38

RSVD_NCTF_B39

RSVD_NCTF_AY3

RSVD_NCTF_AW2

RSVD_NCTF_AV1

RESERVED

(5 OF 10)

OUT
OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(Unused)

ThermDC
ThermDA

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1
ROUTE B5 TO R1010.1 AS A SEPERATE 10 MIL TRACE.

FOR SANDYBRIDGE PROCESSOR

CFG [6:5] :PCIE CONFIGURATION SELECT 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

INTEL SUGGESTS TO KEEP THESE TPS

CFG [2] :PCIE LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(Available for Workstation only)

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

21

R1010

MF-LF

1%

1/16W

24.9

402

PLACEMENT_NOTE=Place within 12.7MM of CPU

15 25 90

15 25 90

25 90

25 90

25 90

25 90

25 90

25 90

25 90

25 90

25 90

15 25 90

15 25 90

25 90

15 25 90

15 25 90

15 25 90

25 90

G9

G10

F7

F8

E5

E6

C3

D3

D7

D8

J13

J14

F11

F12

G13

G14

N6

N5

L5

L6

M7

M8

J6

J5

K8

K7

G6

G5

E13

E14

C14

C13

G1

G2

F3

F4

E1

E2

A6

A5

C5

C6

B7

B8

E9

E10

C9

C10

N2

N1

M4

M3

L2

L1

K4

K3

J2

J1

H4

H3

D11

D12

B12

B11

C4

B5

B4

U6

U5

R5

R6

T8

T7

P7

P8

U1

U2

T3

T4

R1

R2

P4

P3

AG1

AG2

AF2

AF3

AE8

AE7

AD6

AD7

AD3

AD4

AD1

AD2

AC3

AC2

AC7

AC8

AE4

AC4

AG3

AE1

AE5

AC5

AE2

AA8

AA7

Y7

Y6

W8

W7

V6

V7

AA5

AA4

Y4

Y3

V4

V3

W4

W5

U1000

LGA1155-SKT

SANDY_BRIDGE

OMIT

R40

R38

R36

R34

P39

P37

P35

B39

AY3

AW2

AV1

N34

N33

M34

L9

L34

L33

L31

K9

K34

K31

J9

J34

J33

J31

H8

H7

D38

C39

C38

AY10

AW34

AV34

AU10

AT14

AT11

AP20

AN20

AJ31

AJ30

AJ29

AJ11

AG4

AF4

AE6

AD37

AD35

AD34

AB7

AB6

D1

C2

AW38

AU40

A38

L35

J38

M36

L37

N35

L36

K36

J37

G36

G37

N40

N37

N39

N38

N36

M38

J36

H36

U1000

SANDY_BRIDGE

LGA1155-SKT

OMIT

52 94

52 94

2

1

R1011

PLACEMENT_NOTE=Place within 12.7MM of CPU

402

1/16W
MF-LF

5%

0

CPU DMI/PEG/FDI/RSVD

TP_CPU_FDI_TX_P<6>

TP_CPU_RSVD_NCTF<3>

TP_CPU_NCTF<2>
TP_CPU_NCTF<3>

CPU_CFG<6>

CPU_CFG<5>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<8>

DMI_N2S_N<0>

TP_CPU_FDI_TX_N<6>

TP_CPU_FDI_TX_N<4>

DMI_S2N_P<2>
DMI_S2N_P<3>

CPU_FDI_LSYNC<0>

TP_PE_RX_N<1>

TP_PE_TX_P<1>

TP_PE_TX_N<1>

TP_PE_RX_P<3>

TP_PE_RX_P<2>

TP_PE_RX_P<1>

CPU_FDI_INT

DMI_S2N_N<0>

DMI_S2N_P<1>

DMI_S2N_P<0>

TP_PE_TX_P<2>

TP_PE_TX_N<3>

CPU_CFG<8>

=PEG_R2D_C_P<3>

TP_CPU_RSVD<8>

CPU_CFG<13>

CPU_CFG<9>

TP_CPU_RSVD<35>

CPU_CFG<11>

TP_CPU_RSVD<36>

TP_PE_TX_N<2>

TP_PE_TX_N<0>

TP_PE_RX_P<0>

=PEG_R2D_C_N<9>

TP_CPU_FDI_TX_P<2>

TP_CPU_FDI_TX_P<1>

TP_CPU_FDI_TX_P<0>

CPU_FDI_FSYNC<1>

DMI_N2S_P<1>

CPU_FDI_LSYNC<1>

=PEG_R2D_C_P<11>

=PEG_R2D_C_P<13>

TP_CPU_RSVD<38>

TP_CPU_RSVD<5>

TP_CPU_RSVD<28>

TP_CPU_RSVD<21>

TP_CPU_RSVD<10>

CPU_CFG<12>

TP_CPU_NCTF<4>

TP_CPU_RSVD<41>

TP_CPU_RSVD<39>

CPU_CFG<1>

TP_CPU_RSVD<23>

CPU_CFG<10>

TP_CPU_RSVD<40>

TP_CPU_RSVD<20>

TP_CPU_RSVD<34>

TP_CPU_RSVD<37>

TP_CPU_RSVD<16>

TP_CPU_RSVD<15>

TP_CPU_RSVD<14>

SNS_CPU_THERMD_N
SNS_CPU_THERMD_P

TP_CPU_FDI_TX_N<7>

TP_CPU_RSVD<25>
TP_CPU_RSVD<26>

TP_CPU_FDI_TX_N<1>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<11>

TP_CPU_FDI_TX_N<2>

DMI_S2N_N<3>

TP_CPU_FDI_TX_P<5>

TP_CPU_FDI_TX_N<5>

DMI_N2S_P<2>

TP_PE_TX_P<3>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<9>

TP_PE_RX_N<3>

TP_PE_RX_N<2>

TP_CPU_RSVD<22>

=PEG_D2R_P<9>

TP_CPU_FDI_TX_N<0>

TP_CPU_FDI_TX_P<7>

CPU_FDI_FSYNC<0>

TP_PE_RX_N<0>

TP_PE_TX_P<0>

TP_CPU_RSVD<29>

TP_CPU_RSVD<27>

TP_CPU_RSVD<33>

TP_CPU_RSVD<19>

TP_CPU_RSVD<32>

TP_CPU_RSVD<31>

DMI_N2S_P<0>

DMI_N2S_N<1>
DMI_N2S_N<2>

TP_CPU_RSVD<9>

CPU_CFG<17>

=PEG_R2D_C_P<2>

TP_CPU_RSVD<46>

TP_CPU_RSVD<45>

TP_CPU_RSVD<43>

TP_CPU_RSVD<42>

TP_CPU_RSVD_NCTF<1>

TP_CPU_NCTF<5>

TP_CPU_FDI_TX_N<3>

MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=CPU_RCOMP

MIN_NECK_WIDTH=0.2MM

CPU_FDI_COMPIO

=PEG_R2D_C_N<6>

=PEG_R2D_C_P<15>

=PEG_R2D_C_P<14>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<7>

=PEG_D2R_P<10>

=PEG_D2R_P<6>

=PEG_R2D_C_P<4>

=PEG_D2R_P<3>

=PEG_R2D_C_N<2>

=PEG_D2R_N<14>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_N2S_N<3>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<1>

TP_CPU_FDI_TX_P<4>

DMI_N2S_P<3>

=PEG_D2R_P<1>

=PEG_D2R_P<4>

=PEG_D2R_N<13>

=PEG_D2R_N<11>

=PEG_D2R_N<1>

=PEG_D2R_P<8>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<6>

=PEG_D2R_N<5>

=PEG_D2R_P<0>

=PEG_D2R_N<15>

=PEG_R2D_C_N<0>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<0>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<12>

=PEG_D2R_N<12>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

CPU_PEG_COMP

NET_SPACING_TYPE=CPU_RCOMP

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

=PEG_D2R_N<0>

=PEG_D2R_N<2>

TP_CPU_RSVD<13>

TP_CPU_RSVD<12>

TP_CPU_RSVD<11>

TP_CPU_RSVD<7>

TP_CPU_RSVD<30>

TP_CPU_RSVD<2>

=PPVCCIO_S0_CPU

=PEG_D2R_P<2>

=PEG_D2R_P<7>

=PEG_D2R_P<5>

TP_CPU_RSVD_NCTF<2>

TP_CPU_RSVD_NCTF<4>

TP_CPU_NCTF<1>

CPU_CFG<16>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<7>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<0>

CPU_CFG<4>

TP_CPU_RSVD<44>

=PEG_D2R_N<10>

=PEG_D2R_N<9>

TP_CPU_RSVD<6>

TP_CPU_RSVD<4>

TP_CPU_RSVD<3>

TP_CPU_RSVD<1>

TP_CPU_RSVD<24>

=PEG_D2R_P<13>

TP_CPU_FDI_TX_P<3>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<5>

10 OF 110

11.1.0

051-8115

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IN

IN

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IN
IN

OUT

OUT

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G

D

S

IN

NC

IN

IN

OUT

IN
IN

IN

OUT

IN

IN
IN

IN

IN

FC_AH4

FC_AH1

SM_VREF

SM_DRAMRST*

SM_DRAMPWROK

PM_SYNC

PREQ*

TMS

TRST*

TDI
TDO

DBR*

BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*
BPM[4]*
BPM[5]*
BPM[6]*
BPM[7]*

TCK

PRDY*

BCLK_ITP

BCLK_0

BCLK_ITP*

BCLK_0*

UNCOREPWRGOOD

SKTOCC*

RESET*

THERMTRIP*

CATERR*

PECI

PROCHOT*

PROC_SEL

THERMAL

DDR3 MISC

PWR MGMT

CLOCKS

(2 OF 10)

JTAG & BPM

OUT

OUT

BI
BI
BI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

PM_MEM_PWRGD MUST ASSERT MIN. 100ns AFTER =PP1V5_S0_CPU_MEM IS STABLE

CAN ADJUST R1190 AND C1180

OPEN-DRAIN BUFFER

FROM PCH

BASED ON INTEL MOBILE SOLUTION

25 90

25 90

25 90

25 90

25 90

2

1

R1111

MF-LF

1/16W

402

5%

1K

28 89

21 25 97

2

1

C1111

NOSTUFF

402

16V
X5R

10%

0.1UF

2

1

C1110

16V

0.1UF

NOSTUFF

10%
X5R

402

32 97

18 90

18 90

19 97

47 97

47 65 97

21 46 97

2

1

R1126

1/16W
MF-LF

402

NOSTUFF

5%

0

2

1

R1124

PLACEMENT_NOTE=PLACE WITHIN 2 INCHES OF CPU

402

5%

MF-LF

1/16W

75

2 1

R1121

1%

402

MF-LF

121

1/16W

2

1

R1120

402

200

1%
1/16W
MF-LF

1

2

6

Q1180

SOT-563

DMB53D0UV

19 97

2

1

R1183

4.7K

402

MF-LF

1/16W

5%

4

3

5

Q1180

SOT-563

DMB53D0UV

2

1

C1180

0.015UF

16V
402

10%
X7R

2

1

R1190

402

5%
1/16W
MF-LF

12K

4

5

3

2

U1190

74LVC1G07

SC70

2

1

C1190

402

20%
10V

CERM

0.1UF

64 73 97

2

1

R1101

MF-LF

402

51

5%

1/16W

2

1

R1100

1K

1/16W

402

MF-LF

5%

NOSTUFF

25

25

25 90

25 90

25 90

25 90

25 90

18 90

18 90

19 97

2

1

R1104

1/16W

402

MF-LF

5%

51

NOSTUFF

2 1

R1125

1/16W
MF-LF

402

5%

43

27 97

J40

J39

L38

G35

L39

L40

M40

AJ22

AW18

AJ19

AJ33

F36

H34

K32

K40

K38

E38

J35

AH4

AH1

E39

E37

F40

E40

F38

G39

G40

G38

H38

H40

D40

C40

W1

W2

U1000

SANDY_BRIDGE

LGA1155-SKT

OMIT

63 97

2

1

R1102

402

NOSTUFF

1K

MF-LF

5%

1/16W

25 97

25 90

25 90

25 90

CPU CLOCK/MISC/JTAG

ITPCPU_CLK100M_P
ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

CPU_PROC_SEL

CPU_CATERR_L

CPU_SKTOCC_L

PM_SYNC

CPU_MEM_RESET_L

CPU_DDR_VREF

CPU_PECI

CPU_PROCHOT_L

CPU_THRMTRIP_L

CPU_PWRGD

CPU_RESET_L

PM_MEM_PWRGD_L

PM_PGOOD_P1V5_S0_FET

=PPVCCIO_S0_CPU

TP_CPU_DIMM_VREF_A

TP_CPU_DIMM_VREF_B

PLT_RESET_LS1V05_L

PGOOD_P1V5_S0_DLY

PM_MEM_PWRGD_R

=PP1V5_S0_CPU_MEM

=PPVCCIO_S0_CPU

=PP3V3_S5_PWRCTL

=PP3V3_S0_RSTBUF

NO_TEST=TRUE

NC_U1190_P1

=PP3V3_S0_RSTBUF

PM_MEM_PWRGD

11 OF 110

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051-8115

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OUT

OUT

OUT

OUT

OUT

OUT

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OUT
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OUT

OUT
OUT

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OUT
OUT

OUT

OUT
OUT

OUT
OUT

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OUT

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OUT

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OUT

OUT

OUT

OUT OUT

DDR SYSTEM MEMORY A

(3 OF 10)

SA_ODT_3

SA_MA_9

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_15

SA_MA_14

SA_MA_13

SA_MA_12

SA_MA_11

SA_MA_10

SA_MA_1

SA_MA_0

SA_ECC_CB_7

SA_ECC_CB_6

SA_ECC_CB_5

SA_ECC_CB_4

SA_ECC_CB_3

SA_ECC_CB_2

SA_ECC_CB_1

SA_ECC_CB_0

SA_DQS_8

SA_DQS_7*

SA_DQS_7

SA_DQS_6*

SA_DQS_6

SA_DQS_5*

SA_DQS_5

SA_DQS_4*

SA_DQS_4

SA_DQS_3*

SA_DQS_3

SA_DQS_2*

SA_DQS_2

SA_DQS_1*

SA_DQS_1

SA_DQS_0*

SA_DQS_0

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_51

SA_DQ_50

SA_DQ_5

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_43

SA_DQ_42

SA_DQ_41

SA_DQ_40

SA_DQ_4

SA_DQ_39

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_35

SA_DQ_34

SA_DQ_31

SA_DQ_30

SA_DQ_3

SA_DQ_29

SA_DQ_28

SA_DQ_27

SA_DQ_26

SA_DQ_25

SA_DQ_24

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_20

SA_DQ_2

SA_DQ_19

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_15

SA_DQ_14

SA_DQ_13

SA_DQ_12

SA_DQ_11

SA_DQ_10

SA_DQ_1

SA_DQ_0

SA_CS_3*

SA_CS_2*

SA_CS_1*

SA_CS_0*

SA_CKE_3

SA_CKE_2

SA_CKE_1

SA_CKE_0

SA_CK_3*

SA_CK_3

SA_CK_2*

SA_CK_2

SA_CK_1*

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_ODT_0
SA_ODT_1
SA_ODT_2

SA_CK_1

SA_DQ_9

SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SA_BS_0
SA_BS_1

SA_CAS*

SA_BS_2

SA_DQS_8*

SA_DQ_33

SA_DQ_32

DDR SYSTEM MEMORY B

(4 OF 10)

SB_ODT_3

SB_ODT_2

SB_ODT_1

SB_ODT_0

SB_MA_9

SB_MA_8

SB_MA_7

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_15

SB_MA_14

SB_MA_13

SB_MA_12

SB_MA_11

SB_MA_10

SB_MA_1

SB_MA_0

SB_ECC_CB_7

SB_ECC_CB_6

SB_ECC_CB_5

SB_ECC_CB_4

SB_ECC_CB_3

SB_ECC_CB_2

SB_ECC_CB_1

SB_ECC_CB_0

SB_DQS_8

SB_DQS_7*

SB_DQS_7

SB_DQS_6*

SB_DQS_6

SB_DQS_5*

SB_DQS_5

SB_DQS_4*

SB_DQS_3

SB_DQS_2*

SB_DQS_1*

SB_DQS_1

SB_DQS_0*

SB_DQS_0

SB_DQ_9

SB_DQ_8

SB_DQ_7

SB_DQ_63

SB_DQ_62

SB_DQ_61

SB_DQ_60

SB_DQ_6

SB_DQ_59

SB_DQ_58

SB_DQ_57

SB_DQ_56

SB_DQ_55

SB_DQ_54

SB_DQ_53

SB_DQ_52

SB_DQ_51

SB_DQ_50

SB_DQ_5

SB_DQ_49

SB_DQ_48

SB_DQ_47

SB_DQ_46

SB_DQ_45

SB_DQ_44

SB_DQ_43

SB_DQ_42

SB_DQ_41

SB_DQ_40

SB_DQ_4

SB_DQ_39

SB_DQ_38

SB_DQ_37

SB_DQ_36

SB_DQ_35

SB_DQ_34

SB_DQ_32

SB_DQ_31

SB_DQ_30

SB_DQ_3

SB_DQ_29

SB_DQ_28

SB_DQ_27

SB_DQ_26

SB_DQ_25

SB_DQ_24

SB_DQ_23

SB_DQ_22

SB_DQ_21

SB_DQ_20

SB_DQ_2

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_1

SB_DQ_0

SB_CKE_2

SB_CKE_1

SB_CKE_0

SB_CK_3*

SB_CK_3

SB_CK_2*

SB_CK_2

SB_CK_1

SB_CK_0*

SB_CK_0

SB_BS_2

SB_BS_1

SB_BS_0

SB_WE*

SB_RAS*

SB_CAS*

SB_CS_3*

SB_CS_2*

SB_CS_1*

SB_CS_0*

SB_CKE_3

SB_DQS_8*

SB_DQS_2

SB_DQS_4

SB_DQ_33

SB_DQS_3*

SB_CK_1*

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

32 89

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32 89

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32 89

32 89

32 89

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32 89

32 89

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32 89

32 89

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32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

30 89

30 89

30 89

30 89

30 89

30 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

32 89

32 89

30 89

32 89

32 89

30 89

30 89

30 89

30 89

30 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

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32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

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32 89

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32 89

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32 89

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31 89

31 89

31 89

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31 89

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31 89

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30 89

30 89

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32 89

32 89

30 89

32 89

32 89

30 89

32 89

32 89

31 89

32 89

32 89

31 89

31 89

31 89

31 89

31 89

30 89 31 89

AW29

AU28

AW33

AU30

AU32

AV31

AT22

AV22

AU22

AT23

AT24

AV23

AW23

AW24

AT20

AU20

AW32

AT21

AU21

AV28

AY24

AV27

AW12

AY12

AU11

AU13

AY13

AW13

AU14

AU12

AV12

AV13

AF39

AF38

AK39

AK38

AP39

AP38

AV36

AV37

AW8

AV8

AV4

AW4

AP2

AP3

AK2

AK3

AN4

AN1

AL1

AE40

AE39

AG38

AG39

AL2

AE37

AE38

AG37

AG40

AJ40

AJ39

AL38

AL39

AJ37

AJ38

AJ1

AL37

AL40

AN40

AN39

AR38

AR39

AN37

AN38

AR37

AR40

AJ2

AU37

AU38

AY36

AW35

AU36

AU39

AW37

AU35

AY9

AW9

AL4

AW7

AV7

AU9

AV9

AU7

AY7

AY5

AU5

AU3

AU2

AL3

AW5

AV5

AW3

AV2

AR1

AR2

AN3

AN2

AR4

AR3

AJ4

AJ3

AU33

AW30

AV32

AU29

AV18

AU18

AT19

AV19

AW26

AV26

AY27

AW27

AU25

AU24

AW25

AY25

AV30

AV20

AW28

AY29

U1000

OMIT

LGA1155-SKT

SANDY_BRIDGE

AR25

AP24

AK26

AM26

AP26

AL26

AY17

AN18

AL18

AM18

AP18

AP19

AK18

AM19

AV16

AY16

AR26

AT18

AU17

AN23

AM20

AK24

AP15

AR15

AM15

AL15

AR16

AP16

AM16

AL16

AN15

AN16

AG34

AG35

AM33

AL33

AR33

AP33

AN28

AN29

AN12

AN13

AP8

AR8

AL8

AM8

AH6

AH7

AM7

AL7

AJ7

AF35

AF33

AJ34

AJ35

AJ6

AE35

AE34

AH34

AH35

AL34

AM35

AL31

AM34

AL32

AL35

AG6

AM31

AM32

AR34

AR35

AR31

AR32

AP34

AP35

AP31

AP32

AG5

AM29

AM28

AP29

AP28

AL29

AL28

AR29

AR28

AP12

AR12

AJ8

AL13

AL12

AP13

AR13

AM13

AM12

AR9

AP9

AR6

AP6

AJ9

AR10

AP10

AR7

AP7

AM9

AL9

AM6

AL6

AL10

AM10

AG8

AG7

AT26

AL25

AN26

AN25

AV15

AW15

AY15

AU16

AN21

AP21

AM22

AL23

AK20

AL20

AL22

AL21

AK25

AW17

AM24

AP23

U1000

OMIT

LGA1155-SKT

SANDY_BRIDGE

SYNC_DATE=01/06/2011

CPU DDR3 INTERFACES

TP_MEM_B_DQS_P<8>

MEM_B_A<6>

TP_MEM_A_DQ_CB<7>

MEM_A_DQ<26>

MEM_A_DQ<17>

MEM_A_DQ<12>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_DQ<32>
MEM_A_DQ<33>

TP_MEM_A_DQS_N<8>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<9>

MEM_A_CLK_P<1>

MEM_A_ODT<2>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<2>
MEM_A_CLK_N<2>

MEM_A_CLK_P<3>
MEM_A_CLK_N<3>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CS_L<2>
MEM_A_CS_L<3>

MEM_A_DQ<0>
MEM_A_DQ<1>

MEM_A_DQ<10>
MEM_A_DQ<11>

MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>

MEM_A_DQ<18>
MEM_A_DQ<19>

MEM_A_DQ<2>

MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>

MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>

MEM_A_DQ<3>

MEM_A_DQ<30>
MEM_A_DQ<31>

MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>

MEM_A_DQ<4>

MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>

MEM_A_DQ<5>

MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>

MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

TP_MEM_A_DQS_P<8>

TP_MEM_A_DQ_CB<0>
TP_MEM_A_DQ_CB<1>
TP_MEM_A_DQ_CB<2>
TP_MEM_A_DQ_CB<3>
TP_MEM_A_DQ_CB<4>
TP_MEM_A_DQ_CB<5>
TP_MEM_A_DQ_CB<6>

MEM_A_A<0>
MEM_A_A<1>

MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>

MEM_A_ODT<3> MEM_B_ODT<3>

MEM_B_ODT<2>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<0>

TP_MEM_B_DQ_CB<7>

TP_MEM_B_DQ_CB<6>

TP_MEM_B_DQ_CB<5>

TP_MEM_B_DQ_CB<4>

TP_MEM_B_DQ_CB<3>

TP_MEM_B_DQ_CB<2>

TP_MEM_B_DQ_CB<1>

TP_MEM_B_DQ_CB<0>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<6>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<5>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<4>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<3>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<2>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_CKE<2>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CLK_N<3>

MEM_B_CLK_P<3>

MEM_B_CLK_N<2>

MEM_B_CLK_P<2>

MEM_B_CLK_P<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_BA<0>

MEM_B_CS_L<3>

MEM_B_CS_L<2>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CKE<3>

TP_MEM_B_DQS_N<8>

MEM_B_DQS_P<2>

MEM_B_DQS_P<4>

MEM_B_DQ<33>

MEM_B_DQS_N<3>

MEM_B_CLK_N<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L

12 OF 110

11.1.0

051-8115

12 OF 98

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

www.vinafix.vn

CPU CORE SUPPLY

VCCSA

NCTF

CPU CORE SUPPLY

(10 OF 10)

POWER

VCC_097

VCC_092

VCC_091

VCC_090

VCC_089

VCC_088

VCC_087

VCC_083

VCC_112

VCC_117

VCC_113
VCC_114
VCC_115
VCC_116

VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125

VCC_128
VCC_129
VCC_130

VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153

VCC_156
VCC_157
VCC_158
VCC_159
VCC_160

VCCSA0
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6

VCCSA8
VCCSA9

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_073

VCC_072

VCC_071

VCC_155

VCC_154

VCC_084

VCC_093

VSS_NCTF0

VCC_100
VCC_101

VCC_104

VCC_106

VCC_105

VCC_096

VCC_095

VCC_094

VCC_086

VCC_085

VCCSA7

VCCSA10

VCC_107

VCC_082

VCC_077

VCC_074

VCC_076

VCC_161

VCC_126
VCC_127

VCC_111

VCC_098
VCC_099

VCC_075

VCC_081

VCC_103

VCC_102

VCC_078
VCC_079
VCC_080

VCC_108
VCC_109
VCC_110

VCCSA_VID

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_32

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_21

VCCIO_22

VCCIO_18

VCCIO_17

VCCIO_15

VCC_019

VCCIO_03

VCC_053
VCC_054
VCC_055
VCC_056

VCC_SENSE

VCCIO_41

VSS_SENSE

VIDSOUT

VIDSCLK

VIDALERT*

VCCSA_SENSE

VCCIO_19

VCCIO_16

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_08

VCCIO_07

VCCIO_06

VCCIO_05

VCCIO_04

VCCIO_43

VCCIO_40

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_26

VCCIO_20

VCCIO_01
VCCIO_02

VCC_070

VCC_069

VCC_068

VCC_067

VCC_066

VCC_065

VCC_064

VCC_063

VCC_062

VCC_061

VCC_060

VCC_059

VCC_058

VCC_057

VCC_052

VCC_051

VCC_050

VCC_049

VCC_048

VCC_047

VCC_046

VCC_045

VCC_044

VCC_043

VCC_042

VCC_041

VCC_040

VCC_039

VCC_037

VCC_036

VCC_035

VCC_034

VCC_033

VCC_032

VCC_031

VCC_030

VCC_029

VCC_028

VCC_027

VCC_026

VCC_025

VCC_023

VCC_022

VCC_021

VCC_020

VCC_018

VCC_017

VCC_016

VCC_014

VCC_013

VCC_011

VCC_010

VCC_009

VCC_008

VCC_007

VCC_006

VCC_005

VCC_015

VCC_012

VCCIO_27

VCC_004

VCC_003

VCC_002

VCC_001

VCCIO_09

VCCIO_28
VCCIO_29

VCCIO_42

VCC_038

VCC_024

VCCIO_SENSE
VSSIO_SENSE

VCCAXG_SENSE
VSSAXG_SENSE

VCCIO_30

VCCIO_45

VCCIO_SEL

VCCIO_44

VCCIO_31

SENSE LINES

CPU CORE SUPPLY

IO POWER

POWER

CPU VIDS

(6 OF 10)

VCCAXG_08

VCCAXG_01

VDDQ5

VDDQ18

VDDQ17

VDDQ15

VCCAXG_20

VCCAXG_23

VCCAXG_17
VCCAXG_18
VCCAXG_19

VCCAXG_21
VCCAXG_22

VCCAXG_24
VCCAXG_25
VCCAXG_26
VCCAXG_27
VCCAXG_28
VCCAXG_29
VCCAXG_30
VCCAXG_31
VCCAXG_32
VCCAXG_33
VCCAXG_34
VCCAXG_35
VCCAXG_36
VCCAXG_37
VCCAXG_38
VCCAXG_39
VCCAXG_40
VCCAXG_41
VCCAXG_42

VCCAXG_04
VCCAXG_05
VCCAXG_06
VCCAXG_07

VCCAXG_09
VCCAXG_10
VCCAXG_11
VCCAXG_12
VCCAXG_13
VCCAXG_14
VCCAXG_15
VCCAXG_16

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ11
VDDQ12
VDDQ13
VDDQ14

VDDQ16

VDDQ19
VDDQ20
VDDQ21
VDDQ22

VCCPLL0
VCCPLL1

VDDQ10

VCCAXG_03

VCCAXG_02

VCCAXG_43
VCCAXG_44

GRAPHICS

DDR3-1.5V RAILS

POWER

1.8V

( 7 OF 10 )

OUT

OUT
OUT

OUT
OUT

IN

BI

OUT

OUT
OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Fixed at 1.05V

PLACEMENT NOTE:

R1302 NEAR CPU

PLACE R1300 AND

(NOT controlled by VCCIO_SEL)

AY37

AV39

B3

A4

M11

M10

L12

L11

K11

K10

J10

H12

M12

H11

H10

M30

M28

M27

M25

M24

M22

M21

M19

M18

M16

M15

M14

L30

L28

L27

L25

L24

L22

L21

L19

L18

L16

L15

L14

L13

K30

K28

K27

K25

K24

K22

K21

K19

K18

K16

K15

J30

J28

J27

J25

J24

J22

J21

J19

J18

J16

J15

J12

H32

H31

H30

H28

H27

H25

H24

H22

H21

H19

H18

H16

H15

H14

H13

G33

G32

G31

G30

G28

G27

G25

G24

G22

G21

G19

G18

G16

G15

F34

F33

F32

F31

F30

F28

F27

F25

F24

F22

F21

F19

F18

F16

U1000

OMIT

SANDY_BRIDGE

LGA1155-SKT

AB3

M32

B36

B37

C37

A37

P34

T2

AB4

P33

W3

V8

U7

U4

U3

R7

R4

R3

N7

N4

N3

M13

L7

L4

L3

J8

J7

J4

J3

G4

G3

E4

E3

D6
D10

B9

AK30

AK29

AK27

AK23

AK21

AK19

AK17

AK15

AJ32

AJ28

AJ26

AJ17

AJ16

AG33

AF8

AB8

AA3

A7

A11

L32

A36

F15

E35

E34

E33

E31

E30

E28

E27

E25

E24

E22

E21

E19

E18

E16

E15

D36

D35

D34

D33

D31

D30

D28

D27

D25

D24

D22

D21

D19

D18

D16

D15

D14

D13

C36

C34

C33

C31

C30

C28

C27

C25

C24

C22

C21

C19

C18

C16

C15

B34

B33

B31

B30

B28

B27

B25

B24

B18

B16

B15

A28

A27

A25

A24

A18

A16

A15

A14

A13

A12

U1000

OMIT

LGA1155-SKT

SANDY_BRIDGE

AR24

AR23

AR22

AR21

AR20

AJ24

AJ23

AY28

AY26

AY23

AJ20

AW31

AV33

AV29

AV25

AV24

AV21

AU31

AU27

AU23

AU19

AJ14

AJ13

AK12

AK11

Y38

Y37

Y36

Y35

Y34

Y33

W38

W37

W36

W35

W34

W33

U40

U39

U38

U37

U36

U35

U34

U33

T40

T39

T38

T37

T36

T35

T34

T33

AC40

AC39

AC38

AC37

AC36

AC35

AC34

AC33

AB40

AB39

AB38

AB37

AB36

AB35

AB34

AB33

U1000

OMIT

LGA1155-SKT

SANDY_BRIDGE

69 95

65 95

65 95

68 95

68 95

2

1

R1300

PLACEMENT_NOTE=Place close to CPU

MF-LF

75

1/16W

402

1%

2

1

R1302

402

1/16W
MF-LF

110

1%

PLACEMENT_NOTE=Place close to CPU

21

R1310

402

MF-LF

1/16W

1%

44.2

65 95

21

R1312

MF-LF

402

1/16W

5%

0

65 95

21

R1311

402

5%

1/16W

MF-LF

0

65 95

65 95

65 95

SYNC_DATE=01/06/2011

CPU POWER

SYNC_MASTER=K62

=PPVAXG_S0_CPU

=PP1V5_S0_CPU_MEM

=PP1V8_S0_CPU_PLL

=PPVCCIO_S0_CPU

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

CPU_VAXG_SENSE_N

CPU_VAXG_SENSE_P

CPU_VCCIO_SENSE_N

CPU_VCCIO_SENSE_P

CPU_VCCSA_SENSE

CPU_VIDALERT_L_R

CPU_VCC_SENSE_N

CPU_VCC_SENSE_P

TP_CPU_VCCSA_VID

CPU_VIDSOUT_R

CPU_VIDSCLK_R

=PPVCORE_S0_CPU

=PPVCCIO_S0_CPU

TP_CPU_VCCIO_SEL

=PPVCORE_S0_CPU

=PPVCCSA_S0_CPU

13 OF 110

11.1.0

051-8115

13 OF 98

6

17 50 65

6

11 16 28 29

6

16

6

10 11 13 16 65

95

95

95

6

13 16 50 65

6

10 11 13 16 65

6

13 16 50 65

6

50

www.vinafix.vn

VSS

( 8 OF 10 )

VSS_018

VSS_017

VSS_016

VSS_022

VSS_021

VSS_015

VSS_014

VSS_013

VSS_011

VSS_010

VSS_009

VSS_008

VSS_007

VSS_006

VSS_012

VSS_005

VSS_004

VSS_003

VSS_002

VSS_001

VSS_019
VSS_020

VSS_023
VSS_024
VSS_025
VSS_026
VSS_027
VSS_028
VSS_029
VSS_030
VSS_031
VSS_032
VSS_033
VSS_034
VSS_035
VSS_036
VSS_037
VSS_038
VSS_039
VSS_040
VSS_041
VSS_042
VSS_043
VSS_044
VSS_045
VSS_046
VSS_047
VSS_048
VSS_049
VSS_050
VSS_051
VSS_052
VSS_053
VSS_054
VSS_055
VSS_056
VSS_057
VSS_058
VSS_059
VSS_060
VSS_061
VSS_062
VSS_063
VSS_064
VSS_065
VSS_066
VSS_067
VSS_068
VSS_069
VSS_070
VSS_071
VSS_072
VSS_073
VSS_074
VSS_075
VSS_076
VSS_077
VSS_078
VSS_079
VSS_080
VSS_081
VSS_082
VSS_083
VSS_084
VSS_085
VSS_086
VSS_087
VSS_088
VSS_089
VSS_090

VSS_091
VSS_092
VSS_093
VSS_094
VSS_095
VSS_096
VSS_097
VSS_098
VSS_099
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180

VSS

(9 OF 10)

VSS_183
VSS_184
VSS_185

VSS_181

VSS_186
VSS_187

VSS_182

VSS_189
VSS_190
VSS_191
VSS_192
VSS_193

VSS_188

VSS_197
VSS_198
VSS_199
VSS_200

VSS_194
VSS_195
VSS_196

SKT_MNT_HOLE

VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270

VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AV10

AU8

AU6

AU4

AU34

AU26

AU15

AU1

AT9

AT8

AT7

AT6

AT5

AT40

AT4

AT39

AT38

AT37

AT36

AT35

AT34

AT33

AT32

AT31

AT30

AT3

AT29

AT28

AT27

AT25

AT2

AT17

AT16

AT15

AT13

AT12

AT10

AT1

AR5

AR36

AR30

AR27

AR19

AR18

AR17

AR14

AR11

AP5

AP40

AP4

AP37

AP36

AP30

AP27

AP25

AP22

AP17

AP14

AP11

AP1

AN9

AN8

AN7

AN6

AN5

AN36

AN35

AN34

AN33

AN32

AN31

AN30

AN27

AN24

AN22

AN19

AN17

AN14

AN11

AN10

AM5

AM40

AM4

AM39

AM38

AM37

AM36

AM30

AM3

AM27

AM25

AM23

AM21

AM2

AM17

AM14

AM11

AM1

AL5

AL36

AL30

AL27

AL24

AL19

AL17

AL14

AL11

AK9

AK8

AK7

AK6

AK5

AK40

AK4

AK37

AK36

AK35

AK34

AK33

AK32

AK31

AK28

AK22

AK16

AK14

AK13

AK10

AK1

AJ5

AJ36

AJ27

AJ25

AJ21

AJ18

AJ15

AJ12

AH8

AH5

AH40

AH39

AH38

AH37

AH36

AH33

AH3

AH2

AG36

AF7

AF6

AF5

AF40

AF37

AF36

AF34

AF1

AE36

AE33

AE3

AD8

AD5

AD40

AD39

AD38

AD36

AD33

AC6

AC1

AB5

AA6

AA38

AA37

AA36

AA35

AA34

AA33

A35

A29

A26

A23

A17

U1000

SANDY_BRIDGE

LGA1155-SKT

OMIT

Y8

Y5

W6

V5

V40

V39

V38

V37

V36

V35

V34

V33

V2

V1

U8

T6

T5

T1

R8

R39

R37

R35

R33

P6

P5

P40

P38

P36

P2

P1

N8

M9

M6

M5

M39

M37

M35

M33

M29

M26

M23

M20

M2

M17

M1

L8

L29

L26

L23

L20

L17

L10

K6

K5

K39

K37

K35

K33

K29

K26

K23

K20

K2

K17

K14

K13

K12

K1

J32

J29

J26

J23

J20

J17

J11

H9

H6

H5

H39

H37

H35

H33

H29

H26

H23

H20

H2

H17

H1

G8

G7

G34

G29

G26

G23

G20

G17

G12

G11

F9

F6

F5

F39

F37

F35

F29

F26

F23

F20

F2

F17

F14

F13

F10

F1

E8

E7

E36

E32

E29

E26

E23

E20

E17

E12

E11

D9

D5

D4

D39

D37

D32

D29

D26

D23

D20

D2

D17

C8

C7

C35

C32

C29

C26

C23

C20

C17

C12

C11

B6

B38

B35

B32

B29

B26

B23

B17

B14

B13

B10

AY8

AY6

AY4

AY35

AY18

AY14

AY11

AW6

AW36

AW16

AW14

AW11

AW10

AV6

AV38

AV35

AV3

AV17

AV14

AV11

1158

1157

1156

U1000

SANDY_BRIDGE

LGA1155-SKT

OMIT

CPU GROUNDS

14 OF 110

11.1.0

051-8115

14 OF 98

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

REMOVE THESE PULL DOWN RESISTORS AFTER PROTO

REMOVE THESE PULL DOWN RESISTORS AFTER PROTO

These can be Placed close to J2500 and Only for debug access

New SP_DESCRIPTOR_OVERRIDE_L strap

Multiplux with Mini

2

1

R1500

1K

5%
1/16W
MF-LF

402

2

1

R1556

1/16W

10K

MF-LF

402

5%

2

1

R1572

NOSTUFF

10K

1/16W
MF-LF

5%

402

2

1

R1573

10K

MF-LF

5%

1/16W

402

2

1

R1574

1/16W

5%

MF-LF

402

10K

2

1

R1575

1/16W
MF-LF

5%

402

10K

2

1

R1585

1K

1/16W

402

5%

MF-LF

NOSTUFF

2

1

R1586

1K

NOSTUFF

5%

MF-LF

402

1/16W

2

1

R1587

1K

NOSTUFF

MF-LF

5%

402

1/16W

2

1

R1588

NOSTUFF

1K

MF-LF

5%

402

1/16W

2

1

R1576

10K

402

MF-LF

5%

1/16W

2

1

R1571

1/16W

5%

MF-LF

10K

402

NOSTUFF

2

1

R1592

NOSTUFF

1/16W

5%

10K

MF-LF

402

21

R1595

402

0

5%
1/16W
MF-LF

21

R1596

NOSTUFF

0

MF-LF

402

1/16W

5%

2

1

R1509

MF-LF

1/16W

5%

10K

402

2

1

R1520

NOSTUFF

402

MF-LF

5%

1/16W

4.7K

2

1

R1541

NOSTUFF

1K

5%

402

1/16W
MF-LF

2

1

R1521

NOSTUFF

1K

MF-LF

5%

402

1/16W

2

1

R1515

402

1/16W

10K

NOSTUFF

MF-LF

5%

2

1

R1525

1/16W

NOSTUFF

10K

5%

402

MF-LF

2

1

R1524

MF-LF

1/16W

402

5%

10K

2

1

R1523

MF-LF

402

5%

1/16W

10K

2

1

R1530

1/16W

10K

MF-LF

5%

402

2

1

R1527

10K

402

5%
1/16W
MF-LF

NOSTUFF

2

1

R1528

MF-LF

402

1/16W

5%

10K

NOSTUFF

2

1

R1526

5%

10K

402

MF-LF

1/16W

2

1

R1535

MF-LF

402

10K

5%

1/16W

2

1

R1538

1/16W

NOSTUFF

4.7K

5%

402

MF-LF

2

1

R1539

10K

402

1/16W

5%

MF-LF

2

1

R1543

5%

402

4.7K

MF-LF

1/16W

2

1

R1550

402

MF-LF

1K

5%

NOSTUFF

1/16W

2

1

R1551

NOSTUFF

10K

5%
1/16W
MF-LF

402

2

1

R1552

NOSTUFF

10K

5%

MF-LF

402

1/16W

2

1

R1553

5%

MF-LF

402

1/16W

10K

NOSTUFF

2

1

R1554

1/16W

NOSTUFF

402

MF-LF

5%

10K

2

1

R1564

NOSTUFF

5%

MF-LF

402

1/16W

1K

2

1

R1563

NOSTUFF

MF-LF

402

1/16W

5%

1K

2

1

R1503

1/16W
MF-LF

5%

402

10K

2

1

R1562

NOSTUFF

5%

MF-LF

402

1/16W

1K

2

1

R1561

NOSTUFF

5%

402

1/16W
MF-LF

1K

2

1

R1560

NOSTUFF

402

MF-LF

1/16W

5%

1K

2

1

R1569

NOSTUFF

1K

402

MF-LF

5%

1/16W

2

1

R1568

NOSTUFF

MF-LF

1K

5%

1/16W

402

2

1

R1567

1K

MF-LF

NOSTUFF

1/16W

402

5%

2

1

R1566

NOSTUFF

1K

MF-LF

402

5%

1/16W

2

1

R1565

NOSTUFF

1K

5%
1/16W
MF-LF

402

2

1

R1504

NOSTUFF

MF-LF

402

1/16W

5%

10K

2

1

R1570

NOSTUFF

10K

5%

402

1/16W
MF-LF

2

1

R1506

10K

MF-LF

1/16W

5%

NOSTUFF

402

2

1

R1507

5%

402

10K

1/16W
MF-LF

2

1

R1508

10K

5%

1/16W

402

MF-LF

2

1

R1510

402

MF-LF

1/16W

5%

10K

2

1

R1511

10K

1/16W

5%

MF-LF

402

2

1

R1590

1/16W

10K

MF-LF

5%

402

2

1

R1591

1/16W

5%

10K

MF-LF

402

2

1

R1512

10K

5%

MF-LF

402

1/16W

2

1

R1519

402

1/16W

5%

MF-LF

10K

2

1

R1517

1/16W
MF-LF

5%

10K

402

NOSTUFF

2

1

R1522

402

NOSTUFF

10K

5%

MF-LF

1/16W

2

1

R1534

5%

MF-LF

402

1/16W

10K

NOSTUFF

2

1

R1548

10K

1/16W
MF-LF

5%

402

2

1

R1555

402

5%
1/16W
MF-LF

10K

NOSTUFF

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

PM_CLKRUN_L

PCH_GPIO70_TACH6
PCH_GPIO71_TACH7
JTAG_T29_TMS

SDCARD_RESET

PCH_SPKR

CPU_CFG<2>

ENET_SW_RESET_L

PCH_GPIO19_SATA1GP

FW_PME_L
BLC_GPIO

PCH_GPIO0_BMBUSY_L

DP_AUXCH_ISOL

PCH_GPIO49_SATA5GP

T29_SW_RESET_L

FW_PWR_EN
FW_MINI_CLKREQ_L

JTAG_T29_TCK

=PP3V3_S0_PCH_STRAPS

PCH_GPIO36_SATA2GP

PCH_GPIO7_TACH3

=PP3V3_S0_PCH_STRAPS

JTAG_T29_TDI

MINI_CLKREQ_L

=PP3V3_S0_PCH_STRAPS

MINI_CLKREQ_L

ENET_MEDIA_SENSE

PCH_GPIO24

FW_CLKREQ_L

PCH_GPIO8

HDA_SDOUT

SMC_WAKE_SCI_L

PCH_GPIO29_SLP_LAN_L

CPU_CFG<0>

PCH_GPIO30_SUSWARN_L

PCH_FDI_FSYNC<1>

PCH_FDI_LSYNC<0>

PCH_FDI_LSYNC<1>

PCH_FDI_INT

CPU_FDI_FSYNC<0>

CPU_FDI_INT

CPU_FDI_FSYNC<1>

CPU_FDI_LSYNC<1>
CPU_FDI_LSYNC<0>

ODD_PWR_EN_L

PCH_PCI_GNT0_L

PCH_PCI_GNT1_L

PCH_INIT3V3_L

CPU_CFG<5>

T29_CLKREQ_L

FW_MINI_CLKREQ_L

CPU_CFG<1>

JTAG_T29_TDO

PCH_FDI_FSYNC<0>

PCH_GPIO15

CPU_CFG<3>

CPU_CFG<16>

CPU_CFG<6>

=PP3V3_S5_PCH_STRAPS

ENET_CLKREQ_L

PM_BATLOW_L

=PP3V3_S0_PCH_STRAPS

PCH_PCI_GNT2_L

PCH_PCI_GNT3_L

ENET_LOW_PWR

=PP3V3_S5_PCH_STRAPS

15 OF 110

11.1.0

051-8115

15 OF 98

19 46 48 97

21

21

18 86 96

21 44 97 98

18

10 25 90

21 36 91

18 25

21 39 97

6

21 91

21 25

18 25 84 91

21 25

21 80 91

21 97

15 18 91

21 25 86 96

6

15

21 25

21

6

15

21 86 96

15 33 97

6

15

15 33 97

18 37 92

21

39 97

21

18 56 91

18 21 46 97

19

10 25 90

19

19

19

19

19

10

10

10

10

10

21 42 97

20

20

21

10 25 90

21 80 91

15 18 91

10 25 90

21 86 96

19

21 25

10 25 90

10 25 90 10 25 90

6

15

18 36 91

19 46 97

6

15

20

20

21 37 97

6

15

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

10x 10UF and 10x 1UF CAPACITORS

Note: VCCSA decoupling is on regulator page

INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders

BULK CAPS ON VTT REG PAGE 78

PLACEMENT_NOTE (C1660-C1665):

BULK CAPS ON CPU VREG PAGE 72

PLL (CPU VCCSFR) DECOUPLING

CPU VCORE DECOUPLING

2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 10x 10uF 0805

8X 22UF 0805, 6X 10UF 0805

BULK CAPS ON CPU VREG PAGE 72

PLACEMENT_NOTE (C1650-C1657):

CPU VCCIO DECOUPLING

PLACEMENT_NOTE (C1600-C1613):

14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)

6x 22uF 0805, 5x 1uF 0402. INTEL RECOMMENDATION 9X 22uF 0805

Memory (CPU VCCDDR) DECOUPLING

2

1

C1693

X5R

10%

1UF

402

10V

2

1

C1692

402

2.2UF

6.3V

10%
X5R

2

1

C1691

4.7UF

X5R-CERM

6.3V

603

10%

2

1

C1690

20%

6.3V

22uF

CERM-X5R
805

2

1

C1681

CERM-X5R
805

20%

22uF

6.3V
2

1

C1685

1UF

10%

402

X5R

10V

2

1

C1684

10V

402

1UF

10%
X5R

2

1

C1686

10V

402

10%
X5R

1UF

2

1

C1609

Place inside socket cavity

805-3

22UF

20%

6.3V
CERM-X5R

2

1

C1608

20%

6.3V
CERM-X5R

Place inside socket cavity

22UF

805-3

2

1

C1607

Place inside socket cavity

22UF

20%

6.3V
CERM-X5R
805-3

2

1

C1613

20%

6.3V
CERM-X5R
805-3

22UF

Place inside socket cavity

2

1

C1612

22UF

20%

6.3V
CERM-X5R
805-3

Place inside socket cavity

2

1

C1611

805-3

6.3V

20%

22UF

CERM-X5R

Place inside socket cavity

2

1

C1610

805-3

CERM-X5R

6.3V

20%

22UF

Place inside socket cavity

2

1

C1629

Place inside socket cavity

X5R
603

10V

20%

10UF

2

1

C1600

805-3

22UF

CERM-X5R

6.3V

20%

Place inside socket cavity

2

1

C1628

X5R
603

10UF

10V

20%

Place inside socket cavity

2

1

C1627

X5R
603

10UF

10V

20%

Place inside socket cavity

2

1

C1626

X5R
603

10UF

10V

Place inside socket cavity

20%

2

1

C1624

20%
10V

10UF

603

X5R

Place inside socket cavity

2

1

C1623

603

X5R

10V

20%

10UF

Place inside socket cavity

2

1

C1622

20%
10V

10UF

603

X5R

Place inside socket cavity

2

1

C1621

20%
10V

603

X5R

10UF

Place inside socket cavity

2

1

C1620

10UF

20%
X5R

603

10V

Place inside socket cavity

2

1

C1630

1UF

10%
16V
X5R
402

Place inside socket cavity

2

1

C1625

X5R

10UF

10V

20%

Place inside socket cavity

603

2

1

C1631

1UF

10%
16V
X5R
402

Place inside socket cavity

2

1

C1632

1UF

10%
16V
X5R
402

Place inside socket cavity

2

1

C1633

X5R
402

1UF

16V

10%

Place inside socket cavity

2

1

C1634

10%
16V
X5R
402

Place inside socket cavity

1UF

2

1

C1635

1UF

10%
X5R

402

16V

Place inside socket cavity

2

1

C1636

1UF

10%
16V
X5R
402

Place inside socket cavity

2

1

C1637

1UF

10%
X5R

16V

Place inside socket cavity

402

2

1

C1638

1UF

10%
16V
X5R
402

Place inside socket cavity

2

1

C1639

402

X5R

16V

10%

1UF

Place inside socket cavity

2

1

C1601

20%

805-3

22UF

6.3V
CERM-X5R

Place inside socket cavity

2

1

C1670

POLY

2V

330UF-0.0045OHM

20%

CASE-D2-SM

2

1

C1696

6.3V

20%

47UF

0805

X5R

2

1

C1695

20%

6.3V

10UF

603

X5R

2

1

C1697

X5R
0805

47UF

20%

6.3V

2

1

C1679

6.3V

22uF

20%

805

CERM-X5R

2

1

C1678

20%

6.3V

22uF

CERM-X5R
805

2

1

C1677

6.3V

22uF

20%

805

CERM-X5R

2

1

C1676

20%

6.3V

22uF

CERM-X5R
805

2

1

C1602

805-3

CERM-X5R

Place inside socket cavity

6.3V

20%

22UF

2

1

C1603

805-3

CERM-X5R

6.3V

20%

22UF

Place inside socket cavity

2

1

C1604

805-3

6.3V

Place inside socket cavity

22UF

20%
CERM-X5R

2

1

C1650

6.3V

22UF

805

20%
CERM-X5R

Place under socket cavity on secondary side.

2

1

C1605

Place inside socket cavity

22UF

20%

6.3V
CERM-X5R
805-3

2

1

C1606

6.3V

Place inside socket cavity

22UF

20%

805-3

CERM-X5R

2

1

C1651

CERM-X5R

Place under socket cavity on secondary side.

22UF

20%

6.3V

805

2

1

C1652

Place under socket cavity on secondary side.

805

20%
CERM-X5R

6.3V

22UF

2

1

C1653

Place under socket cavity on secondary side.

CERM-X5R
805

22UF

20%

6.3V
2

1

C1654

Place under socket cavity on secondary side.

805

20%

6.3V
CERM-X5R

22UF

2

1

C1655

6.3V
CERM-X5R

Place under socket cavity on secondary side.

805

20%

22UF

2

1

C1656

CERM-X5R
805

22UF

Place under socket cavity on secondary side.

20%

6.3V
2

1

C1657

6.3V

20%

22UF

805

Place under socket cavity on secondary side.

CERM-X5R

2

1

C1665

603

6.3V

20%

10uF

X5R

Place at edge of socket.

2

1

C1664

Place at edge of socket.

X5R

6.3V

20%

603

10uF

2

1

C1663

20%

Place at edge of socket.

603

X5R

6.3V

10uF

2

1

C1662

10uF

20%

Place at edge of socket.

X5R

6.3V
603

2

1

C1661

603

6.3V

10uF

20%
X5R

Place at edge of socket.

2

1

C1660

6.3V

10uF

20%

Place at edge of socket.

603

X5R

2

1

C1680

805

CERM-X5R

22uF

6.3V

20%

2

1

C1682

402

10V
X5R

10%

1UF

2

1

C1683

10V

10%
X5R

402

1UF

2

1

C1694

10V

402

10%
X5R

1UF

SYNC_DATE=01/06/2011

CPU NON-GFX DECOUPLING

SYNC_MASTER=K62

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU

=PPVCCIO_S0_CPU

=PP1V5_S0_CPU_MEM

=PP1V8_S0_CPU_PLL

16 OF 110

11.1.0

051-8115

16 OF 98

6

13 16 50 65

6

13 16

50 65

6

10 11 13

65

6

11 13 28

29

6

13

www.vinafix.vn

TABLE_5_ITEM

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

PLACEMENT_NOTE (C1704-C1709):

INTEL RECOMMENDATION 6X22UF 0805,3X 4.7UF

VAXG DECOUPLING

BULK CAPS ON CPU VREG PAGE 73

21

R1760

1/16W

5%

0

402

MF-LF

21

R1765

5%

1/16W

0

402

MF-LF

21

R1750

0

402

5%
1/16W
MF-LF

2

1

C1709

22UF

20%

6.3V
CERM-X5R
805-3

VAXG

Place inside socket cavity

2

1

C1708

6.3V

22UF

20%
CERM-X5R

805-3

VAXG

Place inside socket cavity

2

1

C1707

22UF

20%

6.3V
CERM-X5R
805-3

Place inside socket cavity

VAXG

2

1

C1706

805-3

CERM-X5R

6.3V

20%

22UF

Place inside socket cavity

VAXG

2

1

C1705

805-3

CERM-X5R

6.3V

20%

Place inside socket cavity

22UF

VAXG

2

1

C1704

805-3

20%

Place inside socket cavity

CERM-X5R

6.3V

22UF

VAXG

2

1

C1710

603

X5R-CERM

4.7UF

10%

Place inside socket cavity

6.3V

OMIT

2

1

C1711

X5R-CERM

Place inside socket cavity

603

VAXG

4.7UF

10%

6.3V
2

1

C1712

X5R-CERM

10%

6.3V

Place inside socket cavity

603

VAXG

4.7UF

GFX DECOUPLING & PCH PWR ALIAS

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

C1710

1

CAP,4.7UF,10%,6.3V,0603

138S0586 VAXG

NO_VAXG

RES,0 OHM,5%,0603

1

113S0022

C1710

PP1V05_S0_PCH_VCCADPLLB_F

VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

PP1V05_S0_PCH_VCCADPLLA_F

=PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCCA_DAC_F

=PPVAXG_S0_CPU

=PP3V3_S0_PCH_VCCADAC

17 OF 110

11.1.0

051-8115

17 OF 98

22 95

22 95

6

22 95

6

13 50 65

6

www.vinafix.vn

IN

IN

OUT

OUT

OUT

IN

BI

BI

BI

BI

OUT

BI

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN
IN

IN
IN

IN
IN

OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

OUT
OUT

OUT

OUT

OUT

OUT

IN

IN

IN
IN

IN
IN

IN

IN

IN

OUT

OUT

OUT

BI

OUT

BI

IN
IN
OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

OUT

BI

OUT
OUT

IN

IN
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN
IN

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN
SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

L_BKLTEN
L_VDD_EN

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0
HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1
RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME*

SATA1RXP
SATA1TXN

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN

SATA5TXN
SATA5TXP

SATAICOMPO
SATAICOMPI

SATALED*

SATA0GP/GPIO21
SATA1GP/GPIO19

L_BKLTCTL

JTAG

SPI

SATA

LPC

IHDA

RTC

SYM 1 OF 10

SMBDATA

SML0CLK

SML0ALERT*/GPIO60

SML0DATA

SML1ALERT*/PCHHOT*/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PETP1

PERP2

PERN2

PERP3
PETN3

PERN4

PETP3

PERP4
PETN4

PERN5

PETP4

PERP5
PETN5
PETP5

PERN6
PERP6

PETP6

PETN6

PERN7
PERP7
PETN7

PERN8

PETP7

PETN8

PERP8

PETP8

SMBALERT*/GPIO11

SMBCLK

PERN1

PETN1

CLKOUT_PCIE0P

CLKOUT_PCIE0N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE3N

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE5P

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_P

CLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKIN_GND0_P

CLKIN_GND0_N

CLKIN_GND1_N
CLKIN_GND1_P

CL_CLK1

CL_DATA1

CL_RST1*

PERP1

PETN2
PETP2

PERN3

SMBUS

FLEX

CLOCK

FROM CLK BUFFER

PEG

PCI-E*

SYM 2 OF 10

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)

DOES THIS NEED LENGTH MATCH???

PLACE THIS RESISTOR NEAR THE PCH PIN

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

27 91

56 91

48 55
91

48 91

48 55
91

48 55 91

46 48 91

46 48 91

46 48 91

46 48 91

46 48 91

46 48

42 90

42 90

42 90

42 90

42 90

42 90

42 90

42 90

37 92

37 92

33 90

33 90

39 90

39 90

37 92

37 92

33 90

33 90

39 90

39 90

37 90

37 90

33 90

33 90

39 90

39 90

15 91

11 90

11 90

9

9

8

8

26 90

26 90

26 90

26 90

26 90

26 90

26 91

27 91

27 79 91

27 91

27 91

49 94

49 94

49 94

49 94

8

8

8

8

2

1

R1800

390K

402

1/16W

5%

MF-LF

2

1

R1801

402

MF-LF

5%
1/16W

1M

2

1

R1802

402

MF-LF

5%

1/16W

20K

2

1

R1803

20K

1/16W

5%

402

MF-LF

2

1

C1803

1UF

10%

402

10V
X5R

2

1

C1802

X5R
402

1UF

10%
10V

2

1

R1830

37.4

MF-LF

402

1/16W

1%

PLACE R1830 AT BALL AJ53

2

1

R1820

402

1/16W

10K

5%

MF-LF

86 96

86 96

2

1

R1890

PLACE R1890 AT BALL AL2

MF-LF

402

1%

1/16W

90.9

21

R1810

402

MF-LF

1/16W

5%

33

21

R1811

402

MF-LF

33

1/16W

5%

21

R1812

1/16W
MF-LF

33

402

5%

21

R1813

402

1/16W

5%

MF-LF

33

56 91

56 91

56 91

15 56 91

2

1

R1850

MF-LF

402

10K

5%

1/16W

15 36 91

49 94

49 94

2

1

R1853

1/16W

10K

MF-LF
402

5%

2

1

R1854

10K

MF-LF

1/16W

5%

402

2

1

R1855

MF-LF

1/16W

5%

402

10K

8

8

42 90

42 90

42 90

42 90

21

R1860

1/16W MF-LF

402

5%

33

21

R1861

402

5%

33

MF-LF1/16W

21

R1862

5%

33

402

1/16W MF-LF

21

R1863

5%331/16W

402

MF-LF

21

R1864

402

1/16W33MF-LF

5%

21

R1822

5%

1/16W22MF-LF

402

21

R1823

1/16W MF-LF

22

402

5%

8

8

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

BN37

BE56

AU53

AT55

AR56

AT57

AR54

AV52

BF57

AJ53
AJ55

AV49

AV50

AT44

AT46

AT49

AT50

AN50

AN49

AM55

AN56

AN44

AN46

AE52
AC52

AE54

AL53

AL56

AL49

AL50

AG47

AG49

AA56

AA53

AY52

AE44

AE46

AB55

AC56

BC54

BN39

BR39

BT41

BA20

BK17

AG17

AG18

AG12

BC50

BF47

BC52

BA43

BN41

BM38

BP23

BT23

BJ22

BK22

BF22

BD22

BC22

BA25

BC25

BU22

BG17

BG20

BJ20

BJ17

BK15

U1800

OMIT

WLCSP

COUGAR-POINT

AJ5

AJ3

AL2

BK46

BJ46

BR46

BM50

BT51

BU49

BR49

BT47

BN49

AN8

D13

F13

B15

C16

E17

B21

A22

F23

B13

F15

A16

B17

F18

E21

C22

F25

J10

H12

L15

M15

M17

J17

R20

L20

H10

J12

J15

N15

P17

H17

P20

J20

BL54

AV43

BA2

AW5

BA5

AT9

AE11

AE12

AG9

AG8

AG2

AF3

Y8

Y9

AB8

AB9

AB14

AB12

W5

AA5

AC6

AE6

N52

R52

M55

N56

R31

P31

AG56

AF55

BD15

P27

R27

V52

W53

BF38

BD38

R33

P33

BF49

BF50

BA50

U1800

OMIT

COUGAR-POINT

WLCSP

2

1

R1832

PLACE R1832 AT BALL AC52

1/16W

402

1%

MF-LF

750

2

1

R1831

1/16W

PLACE R1831 AT BALL AE52

402

MF-LF

1%

49.9

2

1

R1870

402

5%
1/16W
MF-LF

10K

2

1

R1871

MF-LF

1/16W

402

10K

5%

2

1

R1873

10K

402

5%

MF-LF

1/16W

2

1

R1872

MF-LF

1/16W

5%

402

10K

21

R1841

402

MF-LF

1/16W

0

5%

NOSTUFF

21

R1840

NOSTUFF

0

5%

MF-LF

1/16W

402

46 97

21

R1880

PLACE R1880 CLOSE TO R1813

MF-LF

NOSTUFF

0

5%

1/16W

402

21

R1895

0

MF-LF

402

1/16W

5%

NOSTUFF

SYNC_MASTER=K62

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_DATE=01/06/2011

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_ENET_N

PCIE_T29_R2D_C_N<2>

FW_MINI_CLKREQ_L

PCIE_CLK100M_T29_N

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5N

TP_DMI_MIDBUS_CLK100M_PEGB1N
TP_DMI_MIDBUS_CLK100M_PEGB1P

TP_PCIE_CLK100M_PE5P

SATA_SSD_D2R_P

PCH_SATAICOMP

TOTAL_ETCH_LENGTH=5 MM

PCIE_T29_R2D_C_P<1>

PCIE_T29_R2D_C_N<1>

PCIE_T29_D2R_N<1>

TP_PCH_L_BKLTCTL

PCH_SATA3COMP

TOTAL_ETCH_LENGTH=5 MM

=PP1V05_S0_PCH

PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P

PCH_CLK33M_PCIIN

LPC_R_AD<0>

PCIE_ENET_R2D_C_N

=PP1V05_S0_PCH_VCCIO_SATA

PCH_CLK32K_RTCX2

=PP3V3_S0_PCH

LPC_FRAME_R_L

T29_PWR_EN

TP_LPC_DREQ0_L

LPC_AD<1>

LPC_SERIRQ

PCH_GPIO19_SATA1GP

DP_AUXCH_ISOL

PCH_SATALED_L

LPC_FRAME_L

PCH_SRTCRST_L

HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3

HDA_SDOUT_R

PCH_INTRUDER_L

PCH_INTVRMEN_L

TP_SATA_D_R2D_CP

TP_PCIE_CLK100M_PE4P

PCIE_CLK100M_T29_P

PEG_CLK100M_N

SML_PCH_0_DATA

PCIE_FW_R2D_C_N

PCH_SPKR

HDA_RST_R_L

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

DP_GPU_T29_SEL

TP_PCH_GPIO67_CLKOUTFLEX3

ITPXDP_CLK100M_N
ITPXDP_CLK100M_P

PCH_CLK25M_XTALOUT

PCH_CLK25M_XTALIN

ENET_CLKREQ_L

HDA_SYNC_R

HDA_BIT_CLK_R

SPI_DESCRIPTOR_OVERRIDE_L

PP3V3_G3H_RTC

SPI_MOSI_R

HDA_SYNC_R

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_T29_D2R_P<2>

PCIE_T29_R2D_C_P<2>

PCIE_T29_D2R_N<3>

PCIE_T29_R2D_C_P<3>

PCIE_CLK100M_ENET_P

SATA_ODD_R2D_C_N

SATA_SSD_D2R_N

XDP_PCH_TDO

SPI_MOSI_1_R

PCH_CLKIN_GNDP0

PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1

TP_PCH_CL_DATA1

PCH_SRTCRST_L

LPC_R_AD<1>

TP_PCH_CL_CLK1

LPC_R_AD<3>

PCH_CLK100M_SATA_N

PCH_CLK100M_DMI_N

HDA_RST_L

HDA_RST_R_L

HDA_SDOUT

LPC_AD<0>

SPI_CLK_R

SPI_CLK_1_R

PCH_INTVRMEN_L

RTC_RESET_L

PCH_INTRUDER_L

PCIE_MINI_R2D_C_P

PCIE_T29_D2R_N<2>

HDA_SYNC

HDA_SDOUT_R

ITPXDP_CLK100M_P

TP_PCH_CL_RST1

PCH_CLK14P3M_REFCLK

PCH_CLK100M_SATA_P

PCH_CLK100M_DMI_P

SPI_CS0_R_L

=PP1V05_S0_PCH_VCCIO_PCIE

SPI_MISO

XDP_PCH_TMS

TP_SPI_CS1_L

=PP3V3_S0_SATALED

PCIE_MINI_D2R_N

LPC_AD<3>

ITPCPU_CLK100M_N

PCH_CLKIN_GNDN0

SATA_SSD_R2D_C_P

LPC_AD<2>

ITPXDP_CLK100M_N

HDA_BIT_CLK

HDA_SDOUT_R

TP_PCH_CLKOUT_DPP

SML_PCH_1_DATA

SML_PCH_1_CLK

SML_PCH_1_ALERT_L

LPC_R_AD<2>

PCIE_T29_R2D_C_N<3>

PCIE_T29_D2R_P<3>

PCIE_FW_D2R_P

PCIE_T29_D2R_P<0>

PCIE_T29_R2D_C_P<0>

TP_PCIE_R2D_PETP4

TP_PCIE_R2D_PETN4

PCIE_FW_R2D_C_P

TP_PCH_L_VDD_EN

TP_PCH_L_BKLTEN

TP_SATA_E_R2D_CP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_SATA_E_D2RN

PCIE_T29_D2R_P<1>

PCIE_T29_R2D_C_N<0>

PCIE_T29_D2R_N<0>

SATA_ODD_D2R_P

SATA_ODD_R2D_C_P

TP_SATA_D_D2RN

TP_SATA_D_R2D_CN

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_D_D2RP

PCH_SATA3RBIAS

XDP_PCH_TCK

ENET_MEDIA_SENSE

JTAG_T29_TMS

PCH_SATALED_L

XDP_PCH_TDI

PCIE_MINI_R2D_C_N

PCIE_FW_D2R_N

PCIE_MINI_D2R_P

SML_PCH_0_CLK

TOTAL_ETCH_LENGTH=5 MM

PCH_XCLK_RCOMP

PCH_GPIO11_SMBALERT_L

ITPCPU_CLK100M_P

SML_PCH_0_ALERT_L

PCH_GPIO11_SMBALERT_L

=PP3V3_S5_PCH

PCIE_ENET_D2R_N

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

PEG_CLK100M_P

SML_PCH_0_ALERT_L

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P

SATA_ODD_D2R_N

TP_SATA_F_D2RP

TP_SATA_F_R2D_CP

RTC_RESET_L

PCH_CLK32K_RTCX1

HDA_BIT_CLK_R

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

SATA_SSD_R2D_C_N

TP_PCIE_D2R_PERP4

TP_PCIE_D2R_PERN4

SML_PCH_1_ALERT_L

SMC_WAKE_SCI_L

18 OF 110

11.1.0

051-8115

18 OF 98

91

8

91

6

24 79

91

6

22 24

6

21 24

91

80 97

8

15 25

15 25 84 91

18 42

18 97

8

8

8

18 91

18

18 97

8

15

18 91

61 83 91

18 25 90

18 25 90

18 91

18 91

19 22 27 95

18 91

25 91

8

18 97

91

8

91

18 91

91

18 97

18 27 97

18

18 91

18 25 90

8

6

19 22 24

25 91

6

42

11 90 18 25 90

18 91

18

8

8

8

8

8

8

8

8

8

8

8

91

25 91

15 37 92

15 86 96

18 42

25 91

91

18

11 90

18

6

19 21 24

18

8

8

18 27 97

18 91

18

15 21 46 97

www.vinafix.vn

IN

OUT

OUT
OUT

OUT
OUT

IN

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

SUSWARN*/SUSPWRDNACK/GPIO30

DPWROK

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

RSMRST*

APWROK

PWRBTN*

SLP_S3*

DMI_IRCOMP

DMI0TXN

DMI2RXN

DRAMPWROK

FDI_RXN6
FDI_RXN7

FDI_RXP0

FDI_RXP3

FDI_RXP1
FDI_RXP2

FDI_RXP5

FDI_RXP4

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI_LSYNC1

WAKE*

CLKRUN*/GPIO32

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S5*/GPIO63

SLP_S4*

SLP_A*

SLP_LAN*/GPIO29

TP23

PMSYNCH

DF_TVS

DSWVRMEN

SLP_SUS*

SUSACK*

DMI2TXN

DMI1TXN

DMI0TXP

DMI3TXN

DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

SYS_RESET*

SYS_PWROK

PWROK

GPIO31

BATLOW*/GPIO72

RI*

FDI_RXN0
FDI_RXN1

FDI_RXN3

FDI_RXN2

FDI_RXN4
FDI_RXN5

DMI0RXN

DMI3RXN

FDI_RXP6

DMI2RBIAS

DMI1RXN

FDI

DMI

SYSTEM POWER

MANAGEMENT

SYM 3 OF 10

DAC_IREF
CRT_IRTN

CRT_VSYNC

CRT_HSYNC

CRT_DDC_DATA

CRT_DDC_CLK

CRT_RED

CRT_GREEN

CRT_BLUE

RESERVED_1

RESERVED_0

RESERVED_2

RESERVED_28

RESERVED_26
RESERVED_27

RESERVED_23
RESERVED_24
RESERVED_25

RESERVED_22

RESERVED_21

RESERVED_20

RESERVED_18
RESERVED_19

RESERVED_16

RESERVED_15

RESERVED_17

RESERVED_13
RESERVED_14

RESERVED_10

RESERVED_12

RESERVED_11

RESERVED_9

RESERVED_8

RESERVED_6

RESERVED_5

RESERVED_7

RESERVED_3
RESERVED_4

SDVO_TVCLKINP

SDVO_TVCLKINN

SDVO_STALLP

SDVO_STALLN

SDVO_INTP

SDVO_INTN

SDVO_CTRLDATA

SDVO_CTRLCLK

DDPB_AUXN
DDPB_AUXP

DDPB_0N

DDPB_HPD

DDPB_0P
DDPB_1N
DDPB_1P

DDPB_2P

DDPB_2N

DDPB_3N
DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_1P

DDPC_0P
DDPC_1N

DDPC_2P

DDPC_2N

DDPC_3P

DDPC_3N

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXP

DDPD_AUXN

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N

DDPD_3N

DDPD_2P

DDPD_3P

CRT

DIGITAL DISPLAY INTERFACE

SYM 4 OF 10

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

KEEPING TP, IF NEED TO USE IT LATER

PLACE CLOSE TO U1800 PIN

INTERNAL DP

EXTERNAL DP

SHORT THESE TWO PINS VERY NEAR THE PINS

PLACE THE RESISTOR VERY CLOSE TO COMMON POINT

10 90

15

15

15

15

15

2

1

R1900

PLACE R1900 AT BALL E31

402

1%

MF-LF

49.9

1/16W

19 33 36 78 97

15 46 48 97

9

91 97

5

46 47 63 97

5

32 46 47 63 97

5

26 32 36 46 47 63 82 97

11 97

19 27 97

25 46 97

19

15 46 97

64 97

19 97

21 64 97

32 64 97

25 27 46 97

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

2

1

R1905

5%

10K

402

MF-LF

1/16W

11 97

46 48 97

2

1

R1925

MF-LF

1K

1%

1/16W

402

2

1

R1951

402

MF-LF

1/16W

5%

1K

2 1

R1960

MF-LF

NOSTUFF

5%

0

402

1/16W

2

1

R1961

5%

1/16W

402

10K

MF-LF

2

1

R1909

5%

10K

1/16W
MF-LF

402

BC44

J25

BE52

BJ53

BU46

BA47

BP45

BN54

BD43

BH50

BN52

BM53

BH49

BC41

BK38

BJ48

BJ38

BT43

F55

BG43

P43

H43

C49

A46

D47

J41

F43

B43

M43

J43

B47

B45

C46

H41

F45

C42

D51

E49

H46

C52

B51

BR42

BG46

BT37

E31
B31

P41

M41

F38

E37

J38

H38

C36

B37

A32

R38

P38

B35

A36

H36

J36

B33

D33

R47

BC56

AV46

BC46

U1800

OMIT

WLCSP

COUGAR-POINT

U8

U9

W3

U5

U2

T3

AL17

AL15

U50

U46

U44

H50

Y41

R50

M50

M48

K50

K49

AB46

G56

Y44

L53

AB50

Y50

M49

K46

L56

J55

F53

H52

E52

AB49

AB44

U49

R44

U43

J57

M1

AL8

AL9

N6

R6

E11

B11

B7

C9

C6

D7

D5

B5

N2

AL14

AL12

U14

U12

E4

E2

F3

F5

G2

G4

L2

J3

T1

R8

R9

L5

M3

H8

K8

M11

M12

R14

R12

AT3

AR2

AN6

AM6

AR4

AN2

AW1

AW3

AM1

U1800

WLCSP

COUGAR-POINT

OMIT

2

1

R1915

MF-LF

1/16W

402

390K

5%

2

1

R1920

PLACE R1920 AT BALL A32

402

MF-LF

1/16W

750

1%

2 1

R1990

0

5%

1/16W

402

MF-LF

2

1

R1981

5%

2.2K

402

MF-LF

1/16W

2 1

R1980

4.7K

5%
1/16W
MF-LF

402

PCH DMI/FDI/GRAPHICS

TP_PCH_RESERVE_28

LPC_PWRDWN_L

TP_PCH_SLP_SUS_L

TP_PCH_SUSACK_L

PCH_DAC_IREF

TP_CRT_IG_VSYNC

PM_SYS_PWRGD

PCH_DF_TVS

PCH_DSWVRMEN

DMI_N2S_N<1>

DMI_N2S_N<3>

PM_SLP_S4_L

PM_SLP_S5_L

PCIE_WAKE_L

DMI_S2N_P<3>

=PP3V3_S5_PCH

=PP1V05_S0_PCH_VCCIO_PCIE

TP_PCH_FDI_RX_N<7>

TP_PCH_FDI_RX_P<0>

TP_PCH_FDI_RX_N<3>

TP_CRT_IG_RED

PM_SYNC

TP_PCH_RESERVE_0

TP_PCH_FDI_RX_P<1>

TP_PCH_FDI_RX_P<4>

PCH_FDI_INT

PCH_FDI_FSYNC<0>
PCH_FDI_FSYNC<1>

DMI_S2N_P<2>

TP_PCH_FDI_RX_N<4>

DMI_N2S_N<2>

PM_PCH_PWRGD

PM_MEM_PWRGD

PCH_GPIO31_ACPRESENT

PP3V3_G3H_RTC

TP_PCH_FDI_RX_P<5>

TP_PCH_FDI_RX_P<7>

TP_PCH_RESERVE_8
TP_PCH_RESERVE_9

DMI_N2S_P<3>

DMI_S2N_P<0>

=PP3V3_S5_PCH

PCH_DSWVRMEN

CPU_PROC_SEL

=PP1V8_S0_PCH

TP_PCH_RESERVE_27

PCH_DF_TVS

SMC_ADAPTER_EN

PM_CLK32K_SUSCLK_R

PM_SLP_S3_L

TP_PM_SLP_A_L

PCH_GPIO29_SLP_LAN_L

PM_RSMRST_PCH_L

DMI_S2N_N<0>

TP_PCH_TP23

TP_PCH_RESERVE_18

TP_PCH_RESERVE_17

TP_PCH_RESERVE_15

TP_PCH_RESERVE_22

TP_CRT_IG_HSYNC

TP_CRT_IG_DDC_DATA

TP_CRT_IG_DDC_CLK

TP_CRT_IG_GREEN

TP_CRT_IG_BLUE

TP_PCH_RESERVE_1
TP_PCH_RESERVE_2

TP_PCH_RESERVE_26

TP_PCH_RESERVE_23
TP_PCH_RESERVE_24
TP_PCH_RESERVE_25

TP_PCH_RESERVE_21

TP_PCH_RESERVE_20

TP_PCH_RESERVE_19

TP_PCH_RESERVE_16

TP_PCH_RESERVE_13
TP_PCH_RESERVE_14

TP_PCH_RESERVE_10

TP_PCH_RESERVE_12

TP_PCH_RESERVE_11

TP_PCH_RESERVE_6

TP_PCH_RESERVE_5

TP_PCH_RESERVE_7

TP_PCH_RESERVE_3
TP_PCH_RESERVE_4

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

TP_DP_IG_B_DDC_DATA

TP_DP_IG_B_DDC_CLK

TP_DP_IG_B_AUX_N
TP_DP_IG_B_AUX_P

TP_DP_IG_B_MLN<0>

TP_DP_IG_B_HPD

TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>

TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUX_N
TP_DP_IG_C_AUX_P
TP_DP_IG_C_HPD

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD

TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLP<3>

TP_PCH_FDI_RX_N<5>

DMI_N2S_P<2>

DMI_S2N_N<2>

PM_PWRBTN_L

PCH_GPIO31_ACPRESENT

TP_PCH_FDI_RX_N<2>

TP_PCH_FDI_RX_N<6>

TP_PCH_FDI_RX_N<1>

TP_PCH_FDI_RX_N<0>

DMI_S2N_P<1>

DMI_N2S_P<0>

PCH_FDI_LSYNC<0>

PCH_GPIO30_SUSWARN_L

PM_CLKRUN_L

PM_BATLOW_L

PM_SYSRST_L

PCH_FDI_LSYNC<1>

DMI_N2S_P<1>

PM_DSW_PWRGD

PCIE_WAKE_L

=PP3V3_S5_PCH

DMI_N2S_N<0>

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_AUXN

TP_PCH_FDI_RX_P<6>

PCH_RI_L

PM_RSMRST_PCH_L

PM_ASW_PWRGD

PM_DSW_PWRGD

TOTAL_ETCH_LENGTH=5 MM

PCH_DMI_COMP

PCH_DMI2RBIAS

DMI_S2N_N<3>

DMI_S2N_N<1>

TP_PCH_FDI_RX_P<3>

TP_PCH_FDI_RX_P<2>

19 OF 110

11.1.0

051-8115

19 OF 98

8

19 97

19 97

6

18 19 21 24

6

18 22 24

8

8

8

8

8

8

8

19

18 22 27 95

8

8

6

18 19 21 24

19 97

11 97

6

19 97

46 47 97

15

19 27 97

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

15

19 97

19 33 36 78 97

6

18 19 21 24

8

8

8

91

91

8

8

www.vinafix.vn

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI
BI

BI
BI

OUT

OUT

OUT

OUT

BI
BI

BI

BI

BI
BI

USBP2P

USBP3N
USBP3P

USBP4N
USBP4P

USBP5P

USBP5N

USBP6P

USBP6N

USBP7P

USBP7N

USBP8N
USBP8P

USBP9N
USBP9P

USBP10N
USBP10P

USBP11N
USBP11P

USBP12N
USBP12P

USBP13N
USBP13P

USBRBIAS

USBRBIAS*

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43

OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

AD6
AD7

AD9

AD8

AD12

AD10
AD11

AD14

AD13

AD17

AD16

AD15

AD18
AD19
AD20

AD22

AD21

AD24

AD23

AD25

AD27

AD26

AD29

AD28

AD30

C/BE0*

AD31

C/BE2*

C/BE1*

PIRQA*

C/BE3*

PIRQB*
PIRQC*
PIRQD*

REQ0*
REQ1*/GPIO50

REQ3*/GPIO54

REQ2*/GPIO52

GNT1*/GPIO51

GNT0*

GNT2*/GPIO53

PIRQE*/GPIO2

GNT3*/GPIO55

PIRQG*/GPIO4

PIRQF*/GPIO3

PCIRST*

PIRQH*/GPIO5

PERR*

SERR*

PAR

IRDY*

DEVSEL*
FRAME*

PLOCK*

STOP*
TRDY*

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI3
CLKOUT_PCI4

USBP0P

USBP0N

USBP1P

USBP1N

USBP2N

AD1

AD0

AD2
AD3
AD4
AD5

PCI

USB

SYM 5 OF 10

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH SATA PORT 1 OPTION SELECT IS ODD OR SSD

PLACE THE RESISTOR CLOSE TO COMMON POINT

USB CAMERA

Unused

TIE TRACES TOGETHER CLOSE TO PINS

Unused

Unused

Unused

USB HUB 1

Unused

Unused

Unused

USB HUB 2

Unused

Unused

Unused

Unused

K60E MLB CFG SELECT

2

1

R2065

PRODUCTION

1/16W

10K

5%

402

MF-LF

2

1

R2063

402

5%

10K

1/16W
MF-LF

21

R2017

ODD_SATA:P2

1/16W

402

MF-LF

5%

10K

21

R2098

ODD_SATA:P1

402

MF-LF

10K

5%

1/16W

21

R2018

402

MF-LF1/16W

10K

5%

T29

21

R2099

10K

402

1/16W MF-LF

5%

NO_T29

34 92

34 92

8

8

8

8

8

8

8

8

8

8

8

8

35 92

35 92

8

8

2

1

R2066

10K

402

1/16W
MF-LF

5%

2

1

R2064

402

10K

1/16W

5%

MF-LF

2

1

R2062

402

MF-LF

5%

10K

1/16W

2

1

R2061

MF-LF

1/16W

5%

402

10K

8

8

8

8

2

1

R2070

22.6

1%

MF-LF

1/16W

402

PLACE R2070 AT BALL BM25

21

R2010

1/16W

5%

402

10K

MF-LF

21

R2011

1/16W

5%

10K

402

MF-LF

21

R2012

10K

1/16W

5%

402

MF-LF

21

R2013

10K

MF-LF5%402

1/16W

21

R2015

5%

1/16W

402

MF-LF

10K

21

R2016

402

10K

5%

MF-LF1/16W

21

R2020

10K

5%

402

MF-LF1/16W

21

R2021

10K

MF-LF

402

1/16W

5%

21

R2022

10K

5%

402

1/16W MF-LF

27 97

27 91

27 91

27 91

21

R2023

10K

5%

MF-LF1/16W

402

21

R2024

5%

10K

MF-LF1/16W

402

21

R2026

10K

5%

1/16W MF-LF

402

21

R2025

1/16W5%MF-LF

10K

402

21

R2027

1/16W5%MF-LF

10K

402

8

8

8

8

21

R2030

MF-LF1/16W

10K

5%

402

21

R2031

1/16W

10K

402

MF-LF

5%

44 92

44 92

BP25
BM25

BT27

BR26

BR29

BN27

BD31

BF31

BJ33

BK33

BM30

BN29

BT31

BR32

BU32

BT33

BM35

BM33

BA33

BC33

BK27

BJ27

BD27

BF27

BK31

BJ31

BJ25

BK25

BD36

BF36

BC8

BC12

BR6

AV11

BK8

BT5

BG5

AV15

BK48

BA17

BR4

BT15

AV9

BN9

BP5

BM15

BJ5

BK10

BM3

AV14

BH8

BM45

BT45

BJ41

BP43

BK43

BG41

BD41

BM43

BF11

BE2

BU12

AV8

BA15

BC11

BH9

AT14

AT17

AT12

AN14

AT11

BP13

BG2

BP7

BN4

BJ3

BR12

BU9

BJ12

BN11

BG12

BK12

AV17

BT13

BF8

BA8

BF9

BA9

BM13

BC2

BL4

BC4

BL2

BA14

BT7

BT11

BC6

BG15

BE6

BE4

BN2

BF3

BM8

BJ10

BR9

BF17

BF15

U1800

WLCSP

COUGAR-POINT

OMIT

2

1

R2068

1/16W

5%

402

MF-LF

10K

2

1

R2060

5%

402

1/16W
MF-LF

10K

PCH PCI/FLASHCACHE/USB

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_GPIO

PCI_REQ2_L

PCI_REQ3_L

PCI_STOP_L

PCI_REQ3_L

PCI_REQ2_L

TP_PCI_AD<25>

TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>

PCI_REQ0_L

PCI_INTB_L

PCI_INTA_L

PCI_INTD_L

PCH_PCI_GNT3_L

T29_MCU_INT_L

PCI_PERR_L

TP_PCI_PAR

TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>

TP_PCI_AD<10>

TP_PCI_AD<9>

TP_PCI_AD<8>

TP_PCI_C_BE_L<0>

TP_PCI_AD<21>

AP_PWR_EN

SDCONN_STATE_CHANGE

T29_DP_PORTA_PWR_EN

TP_USB_10N

USB_CAMERA_P

PLT_RESET_L

TP_PCI_AD<23>

USB_HUB2_UP_N

TP_USB_7P

TP_USB_6P

TP_PCI_AD<3>

=PP3V3_S5_PCH_GPIO

TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>

PCI_INTC_L

USE_HDD_OOB_L

AUD_I2C_INT_L

PCI_SERR_L

TP_PCI_RESET_L

TP_USB_10P

TP_USB_11P

TP_USB_12P

TP_PCI_AD<0>

TP_PCI_AD<6>

TP_PCI_AD<22>

TP_USB_11N

TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

TP_PCI_PME_L

TP_PCI_C_BE_L<3>

TP_PCI_AD<24>

TP_PCI_AD<20>

TP_PCI_AD<19>

TP_PCI_AD<4>

TP_PCI_AD<17>

TP_PCI_AD<15>

TP_PCI_AD<5>

TP_PCI_AD<18>

TP_PCI_AD<7>

TP_PCI_AD<16>

TP_USB_2N

TP_USB_5N

TP_PCI_AD<1>

TP_USB_5P

TP_USB_6N

USB_HUB2_UP_P

TP_PCI_AD<14>

TP_USB_3P

TP_USB_3N

TP_USB_4P

TP_USB_4N

TP_USB_7N

TP_USB_2P

USB_HUB1_UP_P

TP_PCI_AD<31>

TP_USB_13P

AUD_IP_PERIPHERAL_DET

TP_USB_1P

TP_USB_1N

USB_HUB1_UP_N

TP_PCI_AD<2>

TP_PCI_AD<26>

TP_PCI_AD<30>

PCH_PCI_GNT2_L

PCH_PCI_GNT1_L

PCH_PCI_GNT0_L

TP_USB_12N

PCH_USB_RBIAS

USB_CAMERA_N

TP_USB_13N

USB_HUB_SOFT_RESET_L

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

T29_DP_PORTB_PWR_EN

ENET_PWR_EN

PCI_REQ1_L

PCI_TRDY_L

PCI_PLOCK_L

PCI_FRAME_L

PCI_DEVSEL_L

PCI_IRDY_L

=PP3V3_S0_PCH_GPIO

20 OF 110

11.1.0

051-8115

20 OF 98

6

20 45

6

20 45 20 91

20 91

20 91

20 91

8

8

8

8

91

15

84 91

8

8

8

8

8

8

8

8

8

25 33 97

25 45 97

25 82 91 97

8

8

6

8

8

51 97

62 97

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

61 97

8

8

8

15

15

15

91

25 34 97

25

25

25 91

25 36 97

91

6

20 45

www.vinafix.vn

OUT

IN

IN

OUT

OUT

IN

PWM3

SST

PWM2

PWM1

PWM0

VSSADAC

TS_VSS3
TS_VSS4

TS_VSS2

VSS_NCTF_13

TS_VSS1

VSS_NCTF_12

VSS_NCTF_11

VSS_NCTF_8

VSS_NCTF_10

VSS_NCTF_9

VSS_NCTF_6
VSS_NCTF_7

VSS_NCTF_4
VSS_NCTF_5

VSS_NCTF_3

VSS_NCTF_1
VSS_NCTF_2

VSS_NCTF_0

INIT3_3V*

NC_1

TP36

TP35

TP34

TP33

TP32

TP31

TP30

TP28

TP29

TP27

TP26

TP25

TP24

TP22

TP21

TP20

TP19

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

TP7

TP5

TP6

TP4

TP3

TP2

TP1

PROCPWRGD

THRMTRIP*

RCIN*

PECI

TACH1/GPIO1

TACH2/GPIO6

BMBUSY*/GPIO0

CLKOUT_PCIE6P

CLKOUT_PCIE7N

CLKOUT_PCIE6N

TACH7/GPIO71

TACH6/GPIO70

GPIO57

TACH4/GPIO68

SDATAOUT1/GPIO48

SATA5GP/GPIO49

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

SDATAOUT0/GPIO39

SLOAD/GPIO38

SATA2GP/GPIO36

GPIO35

GPIO28

GPIO27

SCLOCK/GPIO22

GPIO24/MEM_LED

TACH0/GPIO17

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

A20GATE

CLKOUT_PCIE7P

SATA4GP/GPIO16

GPIO15

STP_PCI*/GPIO34

TP18

TACH5/GPIO69

SATA3GP/GPIO37

RSVD

GPIO

SYM 6 OF 10

MISC

NCTF

CPU

D

GS

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

Place this near the T point

MXM CLKREQ ISOLATION

11 25 97

47 97

2

1

R2155

402

MF-LF

1/16W

5%

10K

2

1

R2150

10K

5%

MF-LF

1/16W

402

15

6

15 91

25 32 97

2

1

R2190

47K

MF-LF

5%

402

1/16W

48

AU2

BU52

BU4

BT2

BP57

BP1

BM57

BM1

B2

F1

D1

BU6

BU54

A6

A4

D57

F57

A52

A54

AB17

AB18

Y17

Y18

L36

M38

D25

B27

E27

E29

B25

C26

F28

L33

C29

J22

L25

L27

J31

L22

J27

H31

Y12

L31

Y14

AY36

BA36

AE50

AE43

AE41

AE49

BC49

BA27

BM46

P22

E56

BP15

BN17

BM18

BU16

BR16

BA22

BR19

BT17

BL56

BC43

BE54

AW53

BF55

BA53

BA56

AU56

BG53

BB55

BG56

BN19

BM20

BT21

BN21

D53

H48

BP55

AV44

AY20

BK50

BN56

BP51

BT53

BJ57

BJ55

BJ43

BP53

BM55

AF1

AE2

AA2

AB3

AW55

BB57

U1800

WLCSP

OMIT

COUGAR-POINT

21

R2170

NOSTUFF

1/16W

5%

402

MF-LF

0

21

R2140

1/16W

5%

402

MF-LF

0

21

R2134

402

5%

MF-LF1/16W

0

2

1

3

Q2100

SOD-VESM-HF

SSM3K15FV

21

R2160

NOSTUFF

0

MF-LF

402

5%

1/16W

2

1

R2161

MF-LF

5%

10K

402

1/16W

5

4

1

2

3

U2100

SOT23-5-HF

MC74VHC1G08

2

1

C2110

0.1UF

CERM

402

10V

20%

PCH MISC

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

AUD_IPHS_SWITCH_EN

PM_PCH_PWRGD

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S3_PCH

PCH_GPIO8

AUD_IPHS_SWITCH_EN_PCH

LPCPLUS_GPIO

ODD_PWR_EN_L

PCH_GPIO24

SMC_WAKE_SCI_L

TP_PCH_TP15

FW_PME_L

BLC_GPIO

PCH_GPIO7_TACH3

ENET_LOW_PWR

PCH_GPIO15

PCH_GPIO49_SATA5GP

SPIROM_USE_MLB

SDCARD_RESET

PCH_PEG_CLKREQ_L

PEG_CLKREQ_L

=PP3V3_S5_PCH

=PP3V3_S0_MXM

JTAG_T29_TDI

=PP3V3_S0_PCH

PCH_A20GATE

FW_PWR_EN

TP_PCIE_CLK100M_PE7P

PCH_PECI

PCH_GPIO0_BMBUSY_L

SMC_RUNTIME_SCI_L

ISOLATE_CPU_MEM_L

T29_SW_RESET_L

MXM_GOOD

PCH_GPIO36_SATA2GP

JTAG_T29_TCK

JTAG_T29_TDO

PCH_PEG_CLKREQ_L

T29_CLKREQ_L

ENET_SW_RESET_L

PCH_GPIO70_TACH6

PCH_GPIO71_TACH7

TP_PCH_TP12

TP_PCH_PWM0

PM_THRMTRIP_L

TP_PCH_TP20

TP_PCH_TP16

TP_PCH_TP17

TP_PCH_TP9

TP_PCH_TP10

CPU_PECI

TP_PCH_PWM1

PCH_INIT3V3_L

TP_PCH_TP5

TP_PCH_TP24

TP_PCH_TP25

TP_PCH_TP26

TP_PCH_TP27

TP_PCH_TP28

TP_PCH_TP30

TP_PCH_TP31

TP_PCH_TP32

TP_PCH_TP33

TP_PCH_TP34

TP_PCH_TP35

TP_PCH_TP8

TP_PCH_TP14

TP_PCH_TP36

TP_PCH_NC

CPU_PWRGD

TP_PCH_TP3

TP_PCH_TP2

TP_PCH_TP13

TP_PCH_TP18

TP_PCH_TP11

TP_PCH_TP1

TP_PCH_TP7

TP_PCH_TP29

TP_PCH_TP22

TP_PCH_TP19

TP_PCH_SST

TP_PCH_PWM3

TP_PCH_TP21

TP_PCH_PWM2

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE6N

=PP3V3_S0_PCH

TP_PCH_TP4

TP_PCH_TP6

PCH_RCIN_L

PCH_PROCPWRGD

21 OF 110

11.1.0

051-8115

21 OF 98

62 97

19 64 97

21 25 91

6

15

21 25 91

15 42 97

15 18 46 97

15 39 97

15

15 37 97

15 25

15 25

48 91

15 44 97 98

21 91

9

6

18 19 24

6

64 75 76

15 86 96

6

18 21 24

15 97

8

15 25

46 47 97

15 80 91

5

25 97

15 25

15 25 86 96

15 86 96

21 91

15 80 91

15 36 91

15

15

8

11 46 97

8

15

8

8

8

8

8

8

6

18 21 24

97

www.vinafix.vn

VCCIO_14

DCPSUSBYP

VCCACLK

DCPRTC

DCPRTC_NCTF

VCCVRM_2

VCCADPLLA

VCCADPLLB

DCPSST

DCPSUS_0

DCPSUS_2

DCPSUS_1

VCC3_3_6

V_PROC_IO

VCCDFTERM_1

VCCDIFFCLKN_2

VCCDIFFCLKN_1

VCCDIFFCLKN_0

VCCDSW3_3

VCCSPI

VCCSSC_0
VCCSSC_1

VCCRTC

VCCDFTERM_0

V_PROC_IO_NCTF

VCC3_3_5

VCCSUS3_3_0
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_9

VCCSUS3_3_10

V5REF_SUS

V5REF

VCC3_3_8
VCC3_3_9

VCCSUSHDA

VCCIO_8

VCCIO_15

VCCIO_4

VCCIO_13

VCCIO_7

VCCIO_6

VCCIO_5

VCC3_3_4

VCC3_3_7

VCCIO_12

VCCAPLLSATA

VCCVRM_3

VCCIO_0

VCCIO_3

VCCIO_1

VCCIO_2

SATA

HDA

CPU

PCI/GPIO/LPC

USB

CLOCK AND MISCELLANEOUS

RTC

SYM 10 OF 10

PCI/GPIO/LPC

VCCCORE_15

VCCASW_4
VCCASW_5
VCCASW_6
VCCASW_7
VCCASW_8

VCCASW_1
VCCASW_2
VCCASW_3

VCCAPLLDMI2

VCCAFDIPLL

VCC3_3_2

VCC3_3_1

VCC3_3_3

VCCCORE_20
VCCCORE_21

VCCCORE_19

VCCCORE_18

VCCCORE_14

VCCCORE_13

VCCCORE_12

VCCASW_20

VCCASW_10
VCCASW_11
VCCASW_12
VCCASW_13
VCCASW_14
VCCASW_15
VCCASW_16
VCCASW_17
VCCASW_18
VCCASW_19

VCCASW_9

VCCVRM_0

VCCASW_22

VCCASW_21

VCCDMI_1

VCCVRM_1

VCCADAC

VCCCORE_2
VCCCORE_3
VCCCORE_4
VCCCORE_5
VCCCORE_6
VCCCORE_7
VCCCORE_8

VCCCORE_9
VCCCORE_10
VCCCORE_11

VCCCORE_0

VCCCORE_1

VCCAPLLEXP

VCCDMI_0

VCCIO_16
VCCIO_28
VCCIO_17
VCCIO_9
VCCIO_23
VCCIO_10
VCCIO_22
VCCIO_19

VCCIO_26

VCCASW_0

VCCIO_27

VCC3_3_0

VCCCORE_17

VCCCORE_16

VCCCLKDMI

VCCIO_30
VCCIO_31
VCCIO_24
VCCIO_25
VCCIO_11
VCCIO_29
VCCIO_20
VCCIO_21
VCCIO_18

VCCIO_PCIE

VCCASW

VCCIO_DMI/CLK

SMY 7 OF 10

CRTDMI

VCC CORE

HVCMOS

FDI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

10 mA Max, 1mA Idle

40mA Max, 5mA Idle

1.61A Max, 433mA Idle

PCH output, for decoupling only

Need to check layout decoupling

40mA Max, 10mA Idle

Max and Idle = 1mA

105mA Max, 90mA Idle

Max and Idle = 1mA

PCH output, for decoupling only

57 mA Max, 30mA Idle

97mA Max, 15mA Idle
(VCCSUS3_3 - 11 TOTAL)

(VCC3_3[1-9] total)

1.44 A Max, 474mA Idle

20mA Max, 1mA Idle

Max and Idle = 1mA

55mA Max, 5mA Idle

3mA Max, 1mA Idle

200 mA Max, 2mA Idle

409 mA Max, 42mA Idle

(VCCVRM 4 total)

159mA Max, 114mA Idle

Max and Idle = 1 MA

(VCCIO[1-31] total)

3.456A Max, 426mA Idle

20mA Max, 10mA Idle

2

1

C2210

20%

0.1UF

402

10V

PLACE C2210 AT BR54

CERM

2

1

C2222

20%
10V
CERM
402

0.1UF

PLACE CAP AT BALL BA46

2

1

C2230

CERM

20%

402

0.1UF
NOSTUFF

10V

PLACE C2230 AT BALL A39

R2

R54

AV28

AU38

AT40

BM36

BK36

BJ36

AY33

AY31

AV32

BT35

AV30

U31

AE20

AC20

AN52

BU42

AJ38

AN41

AN40

AL40

AG41

AY27

AY25

AG40
AG38

BA38

AE40

AV26

AV24

AV40

AG15

AE17

AE15

T57

T55

U56

AC2

AB1

AL5

AV20

AU20

A12

AU22

AN38

AL38

B56

D55

BT25

BF1

AV41

A39

AT41

AA32

BA46

BT56

BR54

U1800

COUGAR-POINT

OMIT

WLCSP

R56

AJ1

Y36

Y22

Y20

V22

Y34

Y32

Y30

Y26

Y24

V33

V31

V27

V25

F30

F20

AA36

AA34

Y28

V36

B41

E41

AE34

AE32

AE30

AE28

AE24

AC32

AC30

AR34

AR32

AC28

AN34

AN32

AL34

AL32

AJ36

AJ34

AJ32

AG34

AG32

AE36

AC26

AC24

AJ20

AL24

AJ28

AJ26

AJ24

AG28

AG26

AG24

AU36

AU30

AR38

AU34

AR36

AR30

AR28

AR26

AR24

AN28

AN26

AN24

AN22

AL28

AV36

AU32

B53

A19

C54

AT1

BD20

BD17

BC17

AF57

U1800

WLCSP

OMIT

COUGAR-POINT

2

1

C2232

10V

20%

402

CERM

0.1UF

PLACE C2231 AT BALL BU42

2

1

C2231

402

CERM

6.3V

1UF

PLACE C2232 AT BALL BU42

10%

PCH POWER

PP1V05_S0_PCH_VCCAPLL_EXP_F

PP1V8R1V5_S0_PCH_VCCVRM_F

PP1V05_S0_PCH_VCCADPLLB_F

PP1V8R1V5_S0_PCH_VCCVRM_F

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCCDIFFCLK

=PP3V3R1V8_S0_PCH_VCCDFTERM

=PP3V3_S5_PCH_VCCDSW

PP3V3_G3H_RTC

=PP3V3_S5_PCH_VCCSPI

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCIO_PCIE

=PP5V_S0_PCH_V5REF

PP1V05_S0_PCH_VCCAPLL_SATA_F

=PP3V3_S5_PCH_VCCSUS3_3_USB

=PP1V05_S0_PCH_VCCIO_USB

=PP5V_S5_PCH_V5REFSUS

PP1V8R1V5_S0_PCH_VCCVRM_F

PP3V3_S0_PCH_VCCA_DAC_F

PP1V05_S0_PCH_VCCADPLLA_F

=PP3V3_S0_PCH_VCC3_3_PCI

=PP1V05_S0_PCH_V_PROC_IO

PP1V8R1V5_S0_PCH_VCCVRM_F

PPVOUT_S5_PCH_DCPSUS

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

TP_DCPSUS_0

=PP1V05_S0_PCH_VCCASW

PP1V05_S0_PCH_VCCAPLLDMI2_F

=PP3V3_S0_PCH_VCC3_3_SATA

=PP1V05_S0_PCH_VCCIO_DMI

PP1V05_S0_PCH_VCCCLKDMI_F

=PP3V3_S0_PCH_VCC3V3

TP_1V05_S0_PCH_FDIPLL

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PPVOUT_G3_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm

TP_1V05_S0_PCH_VCCA_CLK

TP_PPVOUT_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

TP_DCPSUS_1

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP1V05_S0_PCH_VCCIO_SATA

PP3V3R1V5_PCH_VCCSUSHDA

22 OF 110

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SYM 9 OF 10

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THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

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8 7 5 4 2 1

AU26

AU24

AT8

AT6

AT52

AT47

AT43

AT18

AT15

AR6

AA20

AR52

AR22

AR20

AN9

AN54

AN47

AN43

AN4

AN36

AN30

A9

AN20

AN18

AN17

AN15

AN12

AN11

AM57

AM52

AM3

AL47

A49

AL46

AL41

AL36

AL30

AL26

AL22

AL20

AL18

AL11

AK6

A42

AK52

AJ57

AJ30

AJ22

AH6

AH52

AG53

AG50

AG5

AG46

A29

AG44

AG43

AG36

AG30

AG22

AG20

AG14

AG11

AF6

AF52

A26

AE9

AE8

AE47

AE4

AE38

AE26

AE22

AE18

AE14

AC54

AY22

AC4

AC38

AC36

AC34

AC22

AB6

AB57

AB52

AB47

AB43

C12

AB41

AB40

AB15

AB11

AA38

BG36

BG33

BG31

BG27

BG25

BG22

BF6

BF52

BF46

AA30

BF43

BF41

BF33

BF25

BF20

BF12

BD33

BD25

BC9

BC47

AA28

BC38

BC36

BC31

BC27

BC20

BC15

BC14

BB6

BB52

BB3

AA26

BB1

BA49

BA44

BA41

BA31

BA12

BA11

B23

AY6

AY38

AA24

AW57

AV6

AV47

AV38

AV34

AV22

AV18

AV12

AU5

AU28

AA22

BR36

AE56

U1800

WLCSP

COUGAR-POINT

OMIT

P25

R25

P36

R36

AL44

AL43

Y6

Y52

Y49

Y47

Y46

Y43

Y40

Y38

Y15

Y11

W57

W55

W1

V6

V38

V20

U53

U47

U41

U38

U36

U33

U27

U25

U22

U20

U17

U15

U11

T6

T52

R49

R46

R43

R41

R4

R22

R17

R15

R11

N54

N4

M9

M8

M6

M57

M52

M46

M36

M33

M31

M27

M25

M22

M20

L43

L41

L38

L17

L12

K9

K6

K52

J53

J5

J48

J46

J33

J1

H6

H33

H27

H25

H22

H20

H15

G54

F8

F50

F48

F46

F42

F40

F36

F35

F33

F32

F26

F22

F16

F12

F10

E9

E6

E54

E39

E19

D45

D43

D35

D3

D23

D15

C4

C39

C32

C19

BU39

BU36

BU29

BU26

BU19

BR52

BR22

BP35

BP33

BP3

BN6

BN47

BN31

BM5

BM48

BM42

BM40

BM32

BM28

BM26

BM23

BM22

BM16

BM12

BM10

BK6

BK52

BK41

BK20

BJ15

BJ1

BH6

BH52

BG38

U1800

COUGAR-POINT

WLCSP

OMIT

PCH GROUNDS

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

23 OF 110

11.1.0

051-8115

23 OF 98

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NC

NC

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

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B

8 7 5 4 2 1

PLACEMENT_NOTE:

PLACEMENT_NOTEs (all 3):

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PCH VCCCORE BYPASS

PLACEMENT_NOTE:

(PCH DMI 1.05V PWR)

PCH VCCIO BYPASS

(PCH 1.05V CORE PWR)

1 mA

PCH VCCSATAPLL Filter

PLACEMENT_NOTE:

(PCH SATA PLL PWR)

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

(PCH USB 1.05V PWR)

PLACEMENT_NOTEs:

PCH V5REF_SUS Filter & Follower

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PLACEMENT_NOTE:

(PCH Reference for 5V Tolerance on PCI)

(PCH Reference for 5V Tolerance on USB)

1 mA S0-S5

<1 MA

PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

(PCH SUSPEND USB 3.3V PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCIO BYPASS

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PLACEMENT_NOTE:

PCH V5REF Filter & Follower

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCCSUSHDA BYPASS

PLACEMENT_NOTEs:

<1 MA S0-S5

2

1

C2439

X5R

10%
10V

402

1UF

PLACE C2439 AT BALL BF1

1

2

R2405

MF-LF

1/16W

402

5%

100

2

1

C2438

PLACE C2438 AT BALL BT25

10V

0.1UF

CERM

402

20%

6

1

D2400

BAT54DW-X-G

SOT-363

1

2

R2404

10

1/16W
MF-LF

5%

402

3

4

D2400

SOT-363

BAT54DW-X-G

2

1

C2409

NOSTUFF

X5R

16V

10%

402

1UF

PLACE C2409 AT BALL U56

21

R2400

402

MF-LF

0

5%

1/16W

2

1

C2423

0.1UF

PLACE C2423 AT BALL AF57

402

X5R

16V

10%

2

1

C2440

0.1UF

10V
CERM

20%

PLACE C2440 AT BALL T55

402

2

1

C2441

PLACE C2441 AT BALL AV28

10V
402

CERM

20%

0.1UF

2

1

C2450

6.3V

10%

402

CERM

1UF

PLACE C2450 AT BALL AV26

2

1

C2419

CERM

6.3V

1UF

10%

402

PLACE C2419 AT BALL B41

2

1

C2421

0.1UF

402

PLACE C2421 AT BALL A12

X5R

10%
16V

2

1

C2422

PLACE C2422 AT BALL AU20

10%

402

6.3V

1UF

CERM

2

1

C2449

6.3V

10%

1UF

402

CERM

PLACE C2449 AT BALL AY27

2

1

C2413

PLACE C2413 AT BALL BT35

402

X5R

0.1UF

16V

10%

2

1

C2455

2.2UF

603

PLACE C2455 AT BALL AV30

16V

10%
X5R

2

1

C2417

PLACE C2417 AT BALL D55

X5R

16V

10%

402

0.1UF

2

1

C2416

402

20%
X5R

6.3V

4.7UF

PLACE C2416 AT BALL D55

21

L2401

NOSTUFF

1210

1.0UH-0.5A

2

1

C2400

X5R-CERM

10UF

10%
16V

NOSTUFF

0805

21

L2404

1210

NOSTUFF

1.0UH-0.5A

2

1

C2406

16V

NOSTUFF

10UF

0805

X5R-CERM

10%

2

1

C2408

X5R-CERM

16V

NOSTUFF

10UF

0805

10%

21

L2405

10UH-0.45A

NOSTUFF

1210

2

1

C2484

PLACE C2484 AT BALL U31

0.1UF

402

16V
X5R

10%

2

1

C2485

PLACE C2485 AT BALL AL38

402

0.1UF

25V

10%
X5R

2

1

C2410

805-1

PLACE C2410 AT BALL Y20

6.3V

20%

10UF

CERM

2

1

C2463

402

CERM

6.3V

10%

1UF

PLACE C2463 AT BALL V25

2

1

C2480

805-1

PLACE C2480 AT BALL AC20

20%

10UF

CERM

6.3V

2

1

C2475

1UF

10%

6.3V
CERM
402

PLACE C2475 AT BALL AE20

2

1

C2437

805-1

PLACE C2437 AT BALL AE15

6.3V

20%

CERM

10UF

2

1

C2435

CERM
402

6.3V

10%

1UF

PLACE C2435 AT BALL AE17

2

1

C2434

10%
CERM

402

6.3V

1UF

PLACE C2434 AT BALL AE15

2

1

C2471

PLACE C2471 AT BALL AA34

CERM

6.3V

20%

10UF

805-1

2

1

C2469

PLACE C2469 AT BALL V36

402

6.3V
CERM

1UF

10%

2

1

C2414

CERM
402

PLACE C2414 AT BALL Y26

6.3V

10%

1UF

2

1

C2401

805

10UF

CERM

20%

6.3V

PLACE C2401 AT BALL V22

2

1

C2487

6.3V

1UF

CERM
402

10%

PLACE C2487 AT BALL E41

2

1

C2489

6.3V

10%

1UF

NOSTUFF

CERM

PLACE C2489 AT BALL B53

402

2

1

C2488

PLACE C2488 AT BALL A19

CERM

10%

402

1UF

NOSTUFF

6.3V

2

1

C2452

10%

402

6.3V
CERM

1UF

PLACE C2452 AT BALL AG38

2

1

C2453

10%

402

6.3V
CERM

1UF

PLACE C2453 AT BALL AJ38

2

1

C2412

402

10%

2.2UF

X5R

PLACE C2415 AT BALL AT40

6.3V

2

1

C2499

PLACE C2499 AT BALL AV40

0.1UF

10V

CERM

20%

402

2

1

C2442

402

1UF

10%

6.3V

PLACE C2442 AT BALL AN52

CERM

2

1

C2445

PLACE C2445 AT BALL R2

10UF

20%

6.3V
CERM

805-1

2

1

C2443

CERM

10%

1UF

402

6.3V

PLACE C2443 AT BALL AJ1

2

1

C2436

402

6.3V

10%

1UF

PLACE C2436 AT BALL R54

CERM

2

1

C2447

10%

402

0.1UF

PLACE C2447 AT BALL R56

X5R

16V

2

1

C2486

25V

402

PLACE C2486 AT BALL AU22

X5R

10%

0.1UF

2

1

C2444

1UF

CERM

6.3V

402

10%

PLACE C2444 AT BALL BA38

2

1

C2446

10%

6.3V
CERM
402

1UF

PLACE C2446 AT BALL AY25

2

1

C2472

PLACE C2472 AT BALL V31

6.3V
CERM

10UF

20%

805-1

2

1

C2470

10%
CERM

6.3V

402

1UF

PLACE C2470 AT BALL Y32

2

1

C2473

805-1

20%

10UF

6.3V
CERM

PLACE C2473 AT BALL F30

2

1

C2425

CERM

PLACE C2425 AT BALL BD20

1UF

6.3V

402

10%

2

1

C2424

0.1UF

10%
X5R

PLACE C2424 AT BALL BC17

402

16V

2

1

C2427

1UF

CERM

PLACE C2427 AT BALL BD17

6.3V

402

10%

2

1

C2461

805-1

PLACE C2461 AT BALL AR32

CERM

20%

10UF

6.3V

2

1

C2460

805-1

PLACE C2460 AT BALL AJ34

6.3V

10UF

20%

CERM

2

1

C2482

CERM

10%

1UF

6.3V

402

PLACE C2482 AT BALL AC24

2

1

C2481

PLACE C2481 AT BALL AC32

6.3V

402

1UF

10%
CERM

2

1

C2483

6.3V

1UF

10%
CERM

402

PLACE C2483 AT BALL AL34

2

1

C2407

6.3V

10%

1UF

CERM
402

PLACE C2407 AT BALL Y28

2

1

C2415

805-1

PLACE C2415 AT BALL F20

CERM

6.3V

20%

10UF

2

1

C2429

CERM

1UF

10%

6.3V

402

PLACE C2429 AT BALL Y24

2

1

C2428

805-1

20%

CERM

6.3V

10UF

PLACE C2428 AT BALL AJ24

2

1

C2420

805-1

10UF

CERM

20%

6.3V

PLACE C2420 AT BALL AU32

2

1

C2418

805-1

PLACE C2418 AT BALL AN32

10UF

20%

6.3V
CERM

2

1

C2498

402

1UF

10%

6.3V
CERM

PLACE C2498 AT BALL AR24

2

1

C2496

402

CERM

1UF

10%

6.3V

PLACE C2496 AT BALL AR36

2

1

C2456

6.3V

10%

1UF

402

CERM

PLACE C2456 AT BALL AG28

2

1

C2426

PLACE C2426 AT BALL AU30

10%

6.3V
CERM
402

1UF

2

1

C2448

10UF

16V

X5R-CERM

0805

10%

21

L2406

1210-HF

10UH-0.45A

21

R2415

MF-LF

5%

1/16W

402

1

2

1

C2411

10%
X5R

16V
402

1UF

PLACE C2411 AT BALL AJ20

2

1

C2430

0.1UF

10%
16V
X5R

PLACE C2430 AT BALL B56

402

21

R2406

NOSTUFF

1/16W

5%

0

MF-LF

402

21

R2407

1/16W
MF-LF

402

5%

0

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

PCH DECOUPLING

=PP3V3R1V5_S5_PCH_VCCSUSHDA

PP3V3R1V5_PCH_VCCSUSHDA

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

=PP3V3_S0_PCH_VCC3_3_SATA

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM
VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCAPLL_SATA_F

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S5_PCH_VCCSPI

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_PCH_VCCSUS3_3_USB

=PP1V05_S0_PCH_VCCSSC

=PP5V_S5_PCH

=PP3V3_S5_PCH

=PP5V_S0_PCH

MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

=PP5V_S5_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MM

PP5V_S5_PCH_V5REFSUS

MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V

=PP1V05_S0_PCH_VCCDIFFCLK

PP3V3R1V5_PCH_VCCSUSHDA

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3R1V8_S0_PCH_VCCDFTERM

=PP3V3_S0_PCH_VCC3V3

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCIO_USB

=PP3V3_S0_PCH_VCC3_3_PCI

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_S0_PCH

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCIO_DMI

=PP1V05_S0_PCH

PP1V8R1V5_S0_PCH_VCCVRM_F

MIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.8V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F

VOLTAGE=1.05V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLLDMI2_F

PP1V05_S0_PCH_VCCCLKDMI_L

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_EXP_F

=PP3V3R1V5_S0_PCH_VCCSUSHDA

24 OF 110

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051-8115

24 OF 98

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6

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www.vinafix.vn

IN

IN

IN
IN

IN

IN
IN
IN
IN

IN
IN
IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT

NC

IN

IN

IN

OUT

IN

IN

BI
IN

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

IN
IN

NC

BI

IN

IN

IN

IN
IN

BI
IN

OUT

IN

IN

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OC4#/GPIO43

OC3#/GPIO42

OBSFN_A0
OBSFN_A1

OBSDATA_A2

OBSFN_B1

OBSDATA_A3

OBSDATA_B0

OC5#/GPIO9

OC2#/GPIO41

OC0#/GPIO59

PWRGD/HOOK0

VCC_OBS_AB

OBSDATA_A0

SATA0GP/GPIO21

GPIO35

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

SATA3GP/GPIO37

<- 1K SERIES R ON PCH SUPPORT P. 28

SATA4GP/GPIO16

OBSDATA_C2

SDA

PLACE TCK/TDI/TMS/TRST*

XDP_PRESENT#

TRSTn

OBSDATA_C1

OBSDATA_D3

VCC_OBS_CD

OBSDATA_A1

OBSDATA_B1

RESET#/HOOK6

PLACEMENT NOTE:

SDA

OBSFN_D0

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_A2

HOOK1

OBSDATA_C3

SCL

TCK1

SCL

TCK0

TMS

TRSTn

ITPCLK/HOOK4

OBSDATA_D2

HOOK1

HOOK2

ITPCLK/HOOK4

OBSDATA_B2

OBSDATA_C3

TDO

TMS

VCC_OBS_CD

OBSFN_C0
OBSFN_C1

HOOK3

XDP_PRESENT#

OBSDATA_D2

TDO

OBSDATA_D1

OBSDATA_D0

OBSDATA_C0

HOOK2

PLACEMENT NOTE:

TERM NEAR CPU

ODT AVAILABLE ON JTAG

PLACEMENT NOTE:

SNB XDP CONN

PLACE TDO TERM NEAR

DESIGN NOTE:

PLACE TDO TERM NEAR

PLACEMENT NOTE:

PCH XDP CONN

OBSFN_B0

DBR#/HOOK7

OBSFN_D1

OBSFN_D1

OBSDATA_B3

PLACE TCK/TDI/TMS/TRST*

OBSDATA_C0

OBSFN_B0

PROCESSOR MINI XDP

OBSFN_A0

To Reset Button

OBSDATA_C2

OBSDATA_C1

OBSDATA_D1

TERM NEAR PCH

This is to derive 1.05V SUS RAIL

OBSDATA_D0

<- 1K SERIES R ON PCH SUPPORT P. 28

OBSDATA_A0

TDI

OBSDATA_B3

OBSFN_D0

OBSFN_C1

OBSFN_C0

TDI

DBR#/HOOK7

RESET#/HOOK6

ITPCLK#/HOOK5

SATA2GP/GPIO36

OBSDATA_B2

TCK1
TCK0

OBSFN_A1

OBSDATA_A1

OBSDATA_A3

OBSFN_B1

PCH MINI XDP

OC1#/GPIO40

PWRGD/HOOK0

VCC_OBS_AB

HOOK3

MGPIO7/GPIO28

GPIO15

OBSDATA_B0
OBSDATA_B1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

518S0774

518S0774

10 15 90

27 91

11 90

11 90

10 90

5

6

7

8

4

3

2

1

RP2500

XDP_CPU_BPM

SM-LF

1/16W

5%

0

5

6

7

8

4

3

2

1

RP2501

PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs

SM-LF

XDP_CPU_CFG

1/16W

0
5%

11 90

11 90

11 90

11 90

10 90

10 90

10 90

21

R2501

PLACEMENT_NOTE=Place close to CPU

402

5%

XDP

1/16W

1K

MF-LF

10 15 25 90

21 32 97

5

21 97

10 90

15 21 86 96

21

R2576

PLACEMENT_NOTE=Place close to PCH

1/16W

MF-LF

0

5%

402

XDP

21

R2577

PLACEMENT_NOTE=Place close to PCH

MF-LF

0

5%

402

XDP

1/16W

15 21

15 18

21

R2573

XDP

PLACEMENT_NOTE=Place close to PCH

5%
MF-LF

1/16W

402

0

15 21

10 15 90

27 97

18 25 91

18 25 91

18 25 91

10 90

21

R2580

PLACEMENT_NOTE=Place close to PCH

1/16W

5%

MF-LF

402

0

XDP

20

20

18 25 91

10 15 90

20 34 97

9

87

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J2550

XDP_CONN

F-ST-SM-HF

CRITICAL

DF40C-60DS-0.4V

2

1

R2553

XDP

1/16W

PLACEMENT_NOTE=Place close to PCH

5%

100

402

MF-LF

2

1

R2554

100

MF-LF

402

1/16W

5%

PLACEMENT_NOTE=Place close to PCH

XDP

2

1

R2550

PLACEMENT_NOTE=Place close to J2550

402

MF-LF

5%

1/16W

XDP

200

2

1

R2551

1/16W

402

MF-LF

5%

XDP

200

PLACEMENT_NOTE=Place close to PCH

2

1

R2552

402

1/16W
MF-LF

XDP

PLACEMENT_NOTE=Place close to PCH

5%

200

2

1

R2555

402

100

MF-LF

1/16W

5%

PLACEMENT_NOTE=Place close to PCH

XDP

2

1

R2556

PLACEMENT_NOTE=Place close to PCH

402

XDP

5%
1/16W
MF-LF

51

25 49

25 49

11 25 97

2

1

C2580

0.1uF

16V

402

X5R

10%

XDP

2

1

C2581

0.1uF

16V

XDP

402

10%

X5R

21

R2502

0

XDP

5%

1/16W

MF-LF

402

PLACEMENT_NOTE=Place close to SMC

19 25 46 97

21

R2585

MF-LF

XDP

0

402

5%

1/16W

PLACEMENT_NOTE=Place close to SMC

19 25 46 97

21

R2504

1/16W

5%

XDP

0

MF-LF

402

5

64 65 97

21

R2584

XDP

1/16W

MF-LF

5%

PLACEMENT_NOTE=Place close to J2550

1K

402

6

25

21

R2581

1/16W

5%

XDP

0

MF-LF

PLACEMENT_NOTE=Place close to PCH

402

20 45 97

19 27 46 97

21

R2506

PLACEMENT_NOTE=Place close to SW2800

MF-LF

5%

XDP

1/16W

0

402

11 25 90

11 25 97

11 25 97

21

R2582

1/16W

5%

0

XDP

402

MF-LF

PLACEMENT_NOTE=Place close to PCH

20 33 97

21

R2578

PLACEMENT_NOTE=Place close to PCH

5%

XDP

402

0

MF-LF

1/16W

15 21

21

R2587

MF-LF

5%

PLACEMENT_NOTE=Place close to PCH

XDP

0

1/16W

402

20 36 97

10 90

11 25 90

18 90

18 90

21

R2515

PLACEMENT_NOTE=Place close to R1841

0

XDP

5%

1/16W

MF-LF

402

21

R2516

MF-LF

5%

402

0

XDP

1/16W

PLACEMENT_NOTE=Place close to R1840

11 25 90

15 21

21 91

21

R2579

PLACEMENT_NOTE=Place close to PCH

XDP

MF-LF

402

1/16W

5%

0

15 18 84 91

21

R2575

PLACEMENT_NOTE=Place close to PCH

1/16W

XDP

402

5%

0

MF-LF

21

R2583

PLACEMENT_NOTE=Place close to PCH

1/16W

5%

MF-LF

402

XDP

0

20 82 91 97

21

R2586

PLACEMENT_NOTE=Place close to PCH

0

5%

402

MF-LF

XDP

1/16W

20 91

11 25 90

10 15 25 90

2

1

C2501

16V

402

X5R

10%

0.1uF

XDP

10 15 90

2

1

C2500

16V

XDP

402

X5R

10%

0.1uF

11

11

10 90

10 90

10 15 90

10 15 90

25 49

25 49

11 25 90

21

R2500

PLACEMENT_NOTE=Place close to CPU

1K

XDP

5%

1/16W

MF-LF

402

10 90

11 21 97

10 90

9

87

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J2500

DF40C-60DS-0.4V

CRITICAL

F-ST-SM-HF

XDP_CONN

2

1

R2510

402

51

XDP

1/16W
MF-LF

5%

PLACEMENT_NOTE=Place close to J2500

2

1

R2511

XDP

51

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=Place close to CPU

2

1

R2512

402

MF-LF

1/16W

PLACEMENT_NOTE=Place close to CPU

5%

51

XDP

2

1

R2513

1/16W

5%

51

MF-LF

402

XDP

PLACEMENT_NOTE=Place close to CPU

2

1

R2514

XDP

51

1/16W

5%

PLACEMENT_NOTE=Place close to CPU

402

MF-LF

11 90

11 90

SYNC_DATE=01/06/2011

CPU & PCH XDP

SYNC_MASTER=K62

CPU_CFG<8>

CPU_CFG<6>

XDP_CPU_TMS

XDP_CPU_PWRGD

XDP_OBSDATA_B<1>

XDP_OBSDATA_B<0>

MXM_GOOD

=SMBUS_XDP_SCL

XDP_PCH_PWRBTN_L

TP_XDP_PCH_TRST_L

XDP_PCH_TMS

TP_XDPPCH_HOOK3

XDP_CPU_CLK100M_N

XDP_CPU_CLK100M_P

XDP_CPU_PWRBTN_L

XDP_PCH_T29_DP_PORTA_PWR_EN

XDP_VR_READY

XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>

XDP_CPU_CFG<0>

XDP_CPU_TCK

CPU_CFG<11>

=SMBUS_XDP_SDA

XDP_PCH_T29_DP_PORTB_PWR_EN

AP_PWR_EN

=SMBUS_XDP_SCL

=PP3V3_S5_XDP

TP_XDP_PCH_OBSFN_B<0>

TP_XDP_PCH_OBSFN_A<0>

XDP_PCH_SDCONN_CHANGE

USB_HUB_SOFT_RESET_L

PCH_GPIO36_SATA2GP

XDP_PCH_GPIO15

XDP_PCH_ISOLATE_CPU_MEM_L

XDP_BPM_L<0>

PCH_GPIO0_BMBUSY_L

PCH_GPIO19_SATA1GP

TP_XDP_PCH_OBSFN_D<0>

XDPPCH_PLTRST_L

TP_XDP_PCH_HOOK4

ISOLATE_CPU_MEM_L

PCH_GPIO49_SATA5GP

XDP_DBRESET_L

XDP_PCH_TDI

=PPVCCIO_S0_XDP

PM_PWRBTN_L

CPU_CFG<15>

ITPXDP_CLK100M_P

TP_XDP_PCH_HOOK5

XDP_DBRESET_L

CPU_CFG<7>

CPU_CFG<9>

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TDO

TP_XDP_PCH_OBSFN_D<1>

CPU_CFG<16>

CPU_CFG<1>

ITPXDP_CLK100M_N

CPU_CFG<0>

CPU_CFG<4>
CPU_CFG<5>

CPU_CFG<2>
CPU_CFG<3>

XDPCPU_PLTRST_L

PM_SYSRST_L

XDP_CPU_TRST_L

CPU_CFG<10>

CPU_CFG<17>

XDP_BPM_L<3>

XDP_CPU_TRST_L

XDP_PCH_TMS

XDP_BPM_L<2>

XDP_PCH_TDO
XDP_PCH_TDI

=PP3V3_S5_XDP

=PPVCCIO_S0_XDP

XDP_CPU_TCK

XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TMS

XDP_BPM_L<7>

CPU_CFG<0>

CPU_CFG<12>

XDP_BPM_L<1>

CPU_CFG<14>

XDP_BPM_L<5>

CPU_CFG<13>

XDP_BPM_L<6>

PM_PGOOD_PVCORE_CPU

CPU_PWRGD

XDP_PCH_TDO

SDCONN_STATE_CHANGE

XDP_BPM_L<4>

PM_PWRBTN_L

XDP_PCH_TCK

XDP_CPU_TDI

PCH_GPIO15

XDP_DBRESET_L

XDP_PCH_AUD_IPHS_SWITCH_EN

XDP_PCH_JTAG_T29_TCK

AUD_IPHS_SWITCH_EN_PCH

JTAG_T29_TCK

XDP_PCH_TCK

XDP_PCH_MXM_GOOD

DP_AUXCH_ISOL

XDP_PCH_DP_AUXCH_ISOL

T29_DP_PORTA_PWR_EN

ENET_PWR_EN

=PP3V3_S5_XDP

=SMBUS_XDP_SDA

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_B<1>

XDP_PCH_ENET_PWR_EN

XDP_PCH_AP_PWR_EN
XDP_PCH_USB_HUB_SOFT_RST_L

TP_XDP_PCH_OBSFN_A<1>

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

T29_DP_PORTB_PWR_EN

XDP_PCH_S5_PWRGD

25 OF 110

11.1.0

051-8115

25 OF 98

90

90

90

90

90

90

90

6

25

6

25

11 25 90

18 25 91

18 25 91

18 25 91

6

25

6

25

11 25 90

11 25 90

11 25 90

11 25 90

18 25 91

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REF

CPU

CPU*

SRC_2*

SRC_2

SATA*

SATA

27MHZ

27MHZ_SS

DOT_96*

X2

X1

SCL

SDA

CKPWRGD/PD*

VDD_CORE

VDD_REF

VDD_96_IO

VDD_27

VDD_SATA_IO

VDD_SRC_IO

VDD_CPU_IOVSS_CPU

VSS_27

VSS_96

THRM

VSS_SATA

VSS_SRC

VSS_REF

VSS_CORE

DOT_96

27MHZ_EN

PAD

BI

OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

STUFF THIS TO POWER DOWN CK505 ->

R2605 OR R2606 CAN BE CHANGED TO "BUF_CLK" OPTION LATER
WHEN FCIM IS FULLY VALIDATED ->

PCH BCLK 133MHZ

PCH USB Clock 96MHz

PCH DMI/PCIe 100MHz

PCH SATA 100MHZ

PLACE IT CLOSE TO POWER PINS

PLACE IT CLOSE TO L2650

PLACE IT CLOSE TO POWER PINS

PLACE IT CLOSE TO POWER PINS

PLACE IT CLOSE TO L2610

PLACE IT CLOSE TO L2600

UNUSED clock terminations for FCIM MODE

2

1

C2616

BUF_CLK

402

10%
16V

0.1UF

X5R

2

1

C2615

X5R
402

10%
16V

0.1UF

BUF_CLK

2

1

C2610

X5R

20%

6.3V

10UF

BUF_CLK

603

21

L2610

BUF_CLK

0402

FERR-120-OHM-1.5A

2

1

C2605

X5R

0.1UF

10%
16V

402

BUF_CLK

2

1

C2604

X5R

16V

10%

0.1UF

402

BUF_CLK

2

1

C2603

X5R

10%

402

0.1UF

BUF_CLK

16V

2

1

C2602

16V

402

X5R

10%

0.1UF

BUF_CLK

2

1

C2600

BUF_CLK

603

6.3V

10UF

X5R

20%

21

L2600

0402

FERR-120-OHM-1.5A

BUF_CLK

23

24

12

13

272021

5

28

9

16

251722

4

8

31

33

11
10

2

3

15
14

26

7
6

18
19

1

30

32

29

U2600

QFN

CRITICAL

OMIT

SLG2AP108

2

1

C2621

CERM
402

18pF

50V

5%

BUF_CLK

21

Y2620

5X3.2-SM

BUF_CLK

CRITICAL

14.31818

2

1

C2620

BUF_CLK

CERM

18pF

50V

5%

402

49

2

1

C2652

BUF_CLK

0.1UF

X5R
402

10%
16V

2

1

C2651

BUF_CLK

0.1UF

X5R
402

10%
16V

2

1

C2650

BUF_CLK

10UF

X5R
603

20%

6.3V

21

L2650

0402

FERR-120-OHM-1.5A

BUF_CLK

18 26 91

21

R2650

2.2

5%
1/16W
MF-LF

402

BUF_CLK

2

1

R2690

BUF_CLK

10K

5%

402

MF-LF

1/16W

2

1

R2616

1/16W

402

5%
MF-LF

10M

NOSTUFF

21

R2699

5%

PLACE R2699 NEAR PIN 26

402

33

1/16W MF-LF

BUF_CLK

2

1

R2600

BUF_CLK

1/16W

5%

402

10K

MF-LF

18 26 90

18 26 90

18 26 90

18 26 90

21

R2615

BUF_CLK

1/16W

5%

MF-LF0402

18 26 90

18 26 90

2

1

R2657

10K

FCIM

402

1/16W

5%
MF-LF

2

1

R2651

FCIM

10K

MF-LF
402

1/16W

5%

2

1

R2652

FCIM

10K

MF-LF
402

1/16W

5%

2

1

R2653

FCIM

10K

MF-LF
402

1/16W

5%

2

1

R2654

10K

FCIM

MF-LF
402

1/16W

5%

2

1

R2655

FCIM

10K

MF-LF
402

1/16W

5%

2

1

R2656

10K

5%
1/16W

402

MF-LF

FCIM

21

R2605

NOSTUFF

1/16W

MF-LF

0

402

5%

5

19 32 36 46 47 63 82 97

49

2

1

R2620

BUF_CLK

10K

5%

1/16W

402

MF-LF

21

R2606

5%

0

MF-LF

1/16W

NOSTUFF

402

64

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

CLOCK (CK505)

PM_PGOOD_CK505

PM_SLP_S3_L

CK505_CKPWRGD_PD_L

PCH_CLK100M_DMI_N

TP_CLK133M_PCH_P

PCH_CLK14P3M_REFCLK

=PP3V3_S0_CK505

=PP1V5_S0_CK505

PP1V5_S0_CK505_F

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=1.5V

CK505_XTAL_IN

CK505_27MHZ_EN

=SMBUS_CK505_SDA

=SMBUS_CK505_SCL

PCH_CLK96M_DOT_N

TP_CK505_CLK27M_SS

PCH_CLK100M_SATA_P

PCH_CLK100M_DMI_P

TP_CLK133M_PCH_N

PCH_CLK14P3M_REFCLK_R

CK505_CLK27M

PCH_CLK14P3M_REFCLK

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_P

PCH_CLK100M_DMI_P

PCH_CLK100M_DMI_N

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N

CK505_XTAL_OUT_R

MIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK505_F

MIN_LINE_WIDTH=0.5mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm
VOLTAGE=1.05V

PP1V05_S0_CK505_F

MIN_LINE_WIDTH=0.5mm

PP1V5_S0_CK505_R=PP1V05_S0_CK505

CK505_XTAL_OUT

26 OF 110

11.1.0

051-8115

26 OF 98

90

18 26 91

6

6

95

91

97

90

18 26 90

18 26 90

18 26 90

18 26 90

18 26 90

18 26 90

91

95

95 95

6

91

www.vinafix.vn

OUT

NCNC

OUT

OUT

IN

OUT

IN

IN

NC
NC

NCNC

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

NC

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OPEN-DRAIN BUFFER

MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED

Platform Reset Connections

PCH 25MHZ CRYSTAL

PGOOD PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON AN UN-EXPECTED EXIT FROM S5 (POWER LOSS)

SMC MAY FORCE A RSMRST_L ASSERTION WITHOUT AN S5 POWER TRANSITION IN SOME ERROR CASES

SMC PROVIDES RSMRST_L DE-ASSERTION DELAY UPON ENTRY TO S5

Coin-Cell Holder

Unbuffered

PLACE THIS ON THE BOTTOM SIDE

Reset Button

Buffered

SMC PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON EXPECTED EXIT FROM S5

VTT VOLTAGE DIVIDER AND PU ON CPU PAGE

RTC Power Sources

fault protection for RTC battery.

NOTE: R2800 and D2800 form the double-

511-0054

PCH RTC Crystal

19 25 46 97

12

R2800

1/16W

402

MF-LF

5%

1K

21

C2810

50V
402

12pF

5%

CERM

PLACE C2810 CLOSE TO Y2810

21

C2811

CERM

PLACE C2811 CLOSE TO Y2810

12pF

5%

50V
402

31

42

Y2810

CRITICAL

SM-2

PLACE Y2810 CLOSE TO U1800

32.768K

3

6

4

1

D2800

SOT-363

BAT54DW-X-G

21

R2881

33

1/16W

5%

402

MF-LF

21

R2890

33

MF-LF

402

1/16W

5%

48 97

9

97

18 91

18 91

20 97

21

R2826

33

PLACEMENT_NOTE=Place close to U1800

5%

MF-LF

1/16W

402

21

R2825

33

PLACEMENT_NOTE=Place close to U1800

1/16W
MF-LF

5%

402

20 91

39 97

21

R2892

402

MF-LF

1/16W

5%

33

48 91

46 91

11 97

20 91

18 91

21

R2827

PLACEMENT_NOTE=Place close to U1800

33

402

MF-LF

1/16W

5%

20 91

2

1

C2880

20%
10V

402

CERM

0.1UF

2

1

R2880

402

5%

100K

1/16W
MF-LF

36 97

21

R2882

33

402

5%

MF-LF

1/16W

1

2

J2800

BB10201-C1403-7H

SM

2

1

R2897

1/16W

402

MF-LF

5%

4.7K

2

1

R2811

402

MF-LF

1/16W

5%

10M

5

4

1

2

3

U2880

SOT23-5-HF

MC74VHC1G08

2

1

C2890

0.1UF

10V

20%

CERM

402

21

R2810

MF-LF

5%

0

402

1/16W

25 97

21

R2899

1/16W
MF-LF

402

1K

5%

XDP

21

C2815

50V

5%

402

CERM

22pF

PLACE C2815 CLOSE TO Y2815

DEVELOPMENT

21

C2816

CERM

402

50V

5%

22pF

PLACE C2816 CLOSE TO Y2815

DEVELOPMENT

21

R2815

NOSTUFF

5%

MF-LF

402

1/16W

0

2

1

R2816

5%

1/16W

402

1M

MF-LF

DEVELOPMENT

18 91

18 79 91

21

Y2815

8X4.5MM-SM3

25.0000M

CRITICAL

PLACE Y2815 CLOSE TO U1800

DEVELOPMENT

43

21

SW2800

NTC020-CC1J-B260T

SM

SILK_PART=SYS RESET

DEVELOPMENT

2

1

C2899

NONE

NONE

OMIT

603

NONE

NOSTUFF

21

R2850

NOSTUFF

402

1/16W
MF-LF

5%

0

33 97

21

R2888

1/16W
MF-LF

5%

33

402

80 97

21

R2855

MF-LF

402

33

5%

1/16W

T29

46 97

21

R2883

5%

402

1/16W

33

MF-LF

4

5

3

2

U2890

74LVC1G07

SC70

21

R2898

XDP

MF-LF

402

5%

1/16W

1K

25 91

21

R2870

1/16W
MF-LF

402

5%

0

21

R2872

0

5%

402

MF-LF

1/16W

NOSTUFF

5

4

1

2

3

U2870

MC74VHC1G08

SOT23-5-HF

2

1

C2870

20%
10V

402

CERM

0.1UF

21

R2884

402

33

5%

MF-LF

1/16W

44 97

CHIPSET SUPPORT

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

PCH_CLK25M_XTALIN_R

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PCH_CLK32K_RTCX2_R

PM_PGOOD_P3V3_S5_REG

PM_RSMRST_L

PM_RSMRST_PCH_L

=PP3V3_S5_RSTBUF

FW_RESET_L

ENET_RESET_L

PM_SYSRST_L

PCH_CLK33M_PCIOUT

LPC_CLK33M_SMC_R

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIIN

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

XDPCPU_PLTRST_L

PEG_RESET_L

RTC_RESET_L

=PP3V3_G3H_RTC_D

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

PPVBATT_G3_RTC_R

=PP3V3_S0_RSTBUF

DEBUG_RESET_L

PPVBATT_G3_RTC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PCH_CLK32K_RTCX1_R

=PP3V3_S0_PCH_PM

PCH_CLK25M_XTALOUT_R

PCH_CLK25M_XTALOUT

PCH_CLK25M_XTALIN

SMC_LRESET_L

T29_RESET_L

MINI_RESET_L

XDPPCH_PLTRST_L

CPU_RESET_L

=PP3V3_S0_RSTBUF

PLT_RESET_L

MAKE_BASE=TRUE

NC_U2890_P1

NO_TEST=TRUE

PLT_RST_BUF_L

SDCARD_PLT_RST_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm

PP3V3_G3H_RTC

MIN_NECK_WIDTH=0.2 mm

28 OF 110

11.1.0

051-8115

27 OF 98

2

5

1

91

91

64 70 97

46 97

19 97

6

18 97

6

95

6

11 27

95

91

6

91

6

11 27

91

18 19 22 95

www.vinafix.vn

IN

BI

OUT

OUT

SCL

RH

RW

VDD

SDA

GND

SCL

RH

RW

VDD

SDA

GND

IN

IN

OUT

OUT

OUT

OUT

BI

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

R2956 change to NOSTUFF if use VREFMARGIN_DIMMB_DQ

353S2369

to drive both VREFCA_A and VREFCA_B

PLACE IT CLOSE TO DIMM CONNECTOR PIN

PLACEMENT NOTE:

PLACE R2968, R2969 and C2961 near CPU

CPU VREF

353S2370

353S1961

PLACEMENT NOTE:

I2C ADDR = 0X5C (WRITE)

PLACEMENT NOTE:

EMPTY ONE SET OF OP-AMP & POT WHEN R2960 IS STUFF

PLACEMENT NOTE:

PLACE R2978, R2979 and C2991 close to DIMM PIN

PLACEMENT NOTE:

DIMM VREFDQ

I2C ADDR = 0X5D (READ)

353S1961

DIMM VREFCA

I2C ADDR = 0X7D (READ)

I2C ADDR = 0X7C (WRITE)

PLACE R2988, R2989 and C2921 close to DIMM PIN

PLACE R2970, R2971 and C2950 close to DIMM PIN

PLACE R2975, R2976 and C2951 close to DIMM PIN

5

2

4

1

3

U2901

VREFMRGN_A

LM321
SOT23-5

2

1

R2975

402

1%
1/16W
MF-LF

1K

2

1

C2951

NOSTUFF

10%
X5R

402

16V

0.1UF

2

1

R2976

1/16W

1%

402

1K

MF-LF

21

R2956

MF-LF

1/16W

5%

402

VREFMRGN_B

0

2

1

C2912

6.3V

1UF

10%

402

CERM

VREFMRGN_B

2

1

R2903

1%
MF-LF

12.1K

1/16W
402

VREFMRGN_A

21

R2914

MF-LF

402

2.2

5%

1/16W

VREFMRGN_B

2

1

C2911

X5R

0.1UF

16V

10%

VREFMRGN_B

402

2

1

R2915

VREFMRGN_B

402

MF-LF

1/16W

1%

1K

21

R2919

VREFMRGN_B

402

10

1%

MF-LF

1/16W

5

2

4

1

3

U2911

VREFMRGN_B

SOT23-5

LM321

2

1

R2913

1/16W
402

12.1K

1%

VREFMRGN_B

MF-LF

21

R2902

VREFMRGN_A

12.1K

1/16W
MF-LF

402

1%

21

R2912

MF-LF

402

1/16W

1%

VREFMRGN_B

12.1K

2

1

C2910

0.1UF

402

16V
X5R

10%

VREFMRGN_B

21

R2910

MF-LF

5%

402

0

1/16W

VREFMRGN_B

21

R2911

1/16W

0

5%

402

VREFMRGN_B

MF-LF

49

49

28 30 95

28 31 95

1

4

3

5

6

2

U2910

SC-70

ISL90728WIE627ZTK

VREFMRGN_B

1

4

3

5

6

2

U2900

SC-70

ISL90727WIE627ZTK

VREFMRGN_A

28 89

28 89

30 95

31 95

11 89

2

1

C2961

X5R

10%

402

16V

0.1UF

2

1

R2968

402

1/16W

1%
MF-LF

100

2

1

R2969

402

1%
MF-LF

1/16W

100

21

R2960

MF-LF

1/16W

5%

0

402

NOSTUFF

28 89

2

1

C2902

VREFMRGN_A

CERM
402

10%

6.3V

1UF

2

1

C2900

402

10%
X5R

16V

0.1UF

VREFMRGN_A

21

R2900

MF-LF

402

5%

VREFMRGN_A

0

1/16W

21

R2901

VREFMRGN_A

MF-LF

402

1/16W

0

5%

49

49

21

R2904

MF-LF

5%

2.2

402

VREFMRGN_A

1/16W

2

1

R2988

MF-LF

1%
1/16W

402

1K

2

1

C2921

X5R

10%

0.1UF

402

16V

NOSTUFF

2

1

R2989

1K

1/16W
MF-LF

1%

402

2

1

R2905

VREFMRGN_A

402

1/16W

1%
MF-LF

1K

21

R2995

5%

0

402

1/16W

NOSTUFF

MF-LF

2

1

C2901

VREFMRGN_A

0.1UF

16V

10%

402

X5R

2

1

R2978

1K

MF-LF

1%
1/16W

402

2

1

C2991

10%

402

X5R

16V

NOSTUFF

0.1UF

2

1

R2979

1K

402

1%
1/16W
MF-LF

21

R2996

NOSTUFF

1/16W

5%

0

402

MF-LF

2

1

C2950

16V
402

10%
X5R

0.1UF

NOSTUFF

2

1

R2970

1K

1/16W

1%

402

MF-LF

2

1

R2971

402

1%
MF-LF

1/16W

1K

21

R2958

402

MF-LF

1/16W

5%

0

VREFMRGN_A

21

R2909

VREFMRGN_A

1/16W

402

1%

10

MF-LF

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

DDR3 VREF MARGINING

=PP3V3_S3_VREFMRGN

=PP5V_S3_VREFMRGN

VREFMARGIN_DIMMA_DACOUT

VREFMARGIN_DIMMB_OPFB

=PP5V_S3_VREFMRGN

VREFMARGIN_DIMMB_DACOUT

PP5V_S3_VREFMRGN_B

=PP1V5_S3_MEM_B

=PP1V5_S0_CPU_MEM

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_B

=PP1V5_S3_MEM_A

VREFMARGIN_DIMMB_DQ

PP0V75_S3_MEM_VREFCA_A

CPU_DDR_VREF

I2C_VREFMRGN_DIMMB_SDA

=I2C_VREFMRGN_B_SDA

I2C_VREFMRGN_DIMMB_SCL

=I2C_VREFMRGN_B_SCL

I2C_VREFMRGN_DIMMA_SDA

=I2C_VREFMRGN_A_SDA

=I2C_VREFMRGN_A_SCL

I2C_VREFMRGN_DIMMA_SCL

=PP3V3_S3_VREFMRGN

=PP1V5_S3_MEM_B

VREFMARGIN_DIMMB_DQ

VREFMARGIN_DIMMB_DQ

=PP1V5_S3_MEM_A

VREFMARGIN_DIMMA_DQ

VREFMARGIN_DIMMA_OPFB

PP5V_S3_VREFMRGN_A

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_B

29 OF 110

11.1.0

051-8115

28 OF 98

6

28

6

28

89

89

6

28

89

95

6

28 29 31

6

11 13 16 29

6

28 29 30

6

28 29 31

28 30 95 28 31 95

6

28 29 30

94

94

94

94

6

28

6

28 29 31

6

28 29 30

89

89

95

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL A DIMM CONNECTOR

EXTRA DECOUPLING CAPS FOR 1V5_CPU_MEM RAIL

DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL B DIMM CONNECTOR

DIMM A (CLOSER TO CPU)

DIMM B (FURTHER FROM CPU)

CAPS TO STITCH 1V5_CPU_MEM TO GND NEAR DIMM

2

1

C3058

CERM

10%

1UF

6.3V
402

2

1

C3057

402

CERM

10%

1UF

6.3V

2

1

C3056

402

CERM

10%

1UF

6.3V

2

1

C3055

402

CERM

10%

1UF

6.3V

2

1

C3054

402

1UF

CERM

10%

6.3V

2

1

C3053

402

CERM

1UF

6.3V

10%

2

1

C3052

6.3V

1UF

CERM

10%

402

2

1

C3051

20%

X5R

6.3V

10UF

603

2

1

C3050

20%

603

6.3V
X5R

10UF

2

1

C3085

6.3V

1UF

10%
CERM

402

2

1

C3084

6.3V

1UF

10%
CERM

402

2

1

C3083

6.3V

1UF

10%
CERM

402

2

1

C3082

6.3V

1UF

10%
CERM

402

2

1

C3081

402

CERM

10%

1UF

6.3V

2

1

C3080

402

CERM

10%

1UF

6.3V

2

1

C3079

402

CERM

10%

1UF

6.3V

2

1

C3078

402

CERM

10%

1UF

6.3V

2

1

C3077

402

CERM

10%

1UF

6.3V

2

1

C3076

402

CERM

10%

1UF

6.3V

2

1

C3075

402

CERM

10%

1UF

6.3V

2

1

C3074

402

CERM

10%

1UF

6.3V

2

1

C3073

402

CERM

1UF

6.3V

10%

2

1

C3072

6.3V

1UF

CERM

10%

402

2

1

C3071

20%

X5R

6.3V

10UF

603

2

1

C3070

20%

6.3V
X5R
603

10UF

2

1

C3094

6.3V

1UF

10%
CERM

402

2

1

C3093

6.3V

1UF

10%
CERM

402

2

1

C3092

10%
CERM

6.3V
402

1UF

2

1

C3091

6.3V
402

CERM

10%

1UF

2

1

C3090

6.3V
402

CERM

10%

1UF

2

1

C3049

6.3V
402

CERM

10%

1UF

2

1

C3048

1UF

6.3V
402

CERM

10%

2

1

C3047

CERM

1UF

6.3V
402

10%

2

1

C3045

6.3V

1UF

10%
CERM

402

2

1

C3043

402

10%

1UF

CERM

6.3V

2

1

C3040

6.3V
CERM

10%

402

1UF

2

1

C30A4

1UF

6.3V
CERM
402

10%

2

1

C30A3

1UF

6.3V

10%

402

CERM

2

1

C30A2

10%

6.3V
402

CERM

1UF

2

1

C30A1

10%

402

CERM

1UF

6.3V

2

1

C30A0

6.3V
CERM

10%

402

1UF

2

1

C30AE

402

CERM

1UF

6.3V

10%

2

1

C30AD

10%

402

CERM

1UF

6.3V

2

1

C30AC

402

10%

1UF

CERM

6.3V

2

1

C30AB

10%

402

1UF

6.3V
CERM

2

1

C30AA

CERM
402

10%

1UF

6.3V

2

1

C30A9

CERM
402

10%

1UF

6.3V

2

1

C30A8

1UF

CERM

10%

402

6.3V

2

1

C30A7

402

CERM

10%

1UF

6.3V

2

1

C30A6

10%

402

CERM

1UF

6.3V

2

1

C30A5

1UF

6.3V
CERM
402

10%

2

1

C3066

1UF

6.3V

10%
CERM

402

2

1

C3067

6.3V

10%

1UF

402

CERM

2

1

C3068

6.3V

1UF

10%
CERM

402

2

1

C3069

402

CERM

10%

1UF

6.3V

2

1

C3089

402

CERM

10%

1UF

6.3V

2

1

C3088

402

CERM

10%

1UF

6.3V

2

1

C3087

402

CERM

10%

1UF

6.3V

2

1

C3086

402

CERM

10%

1UF

6.3V

2

1

C3016

402

CERM

10%

1UF

6.3V
2

1

C3017

402

CERM

10%

1UF

6.3V
2

1

C3018

402

CERM

10%

6.3V

1UF

2

1

C3019

402

CERM

1UF

6.3V

10%

2

1

C3010

CERM

10%

1UF

6.3V
402

2

1

C3025

6.3V

1UF

10%
CERM

402

2

1

C3026

6.3V

1UF

10%
CERM

402

2

1

C3027

6.3V

1UF

10%
CERM

402

2

1

C3028

6.3V

1UF

10%
CERM

402

2

1

C3029

402

CERM

10%

1UF

6.3V
2

1

C3020

10%

6.3V

1UF

CERM
402

2

1

C3021

6.3V

1UF

10%
CERM

402

2

1

C3022

6.3V

1UF

10%
CERM

402

2

1

C3023

6.3V

1UF

10%
CERM

402

2

1

C3014

6.3V

1UF

10%
CERM

402

2

1

C3030

402

6.3V

1UF

10%
CERM

2

1

C3031

402

6.3V

1UF

10%
CERM

2

1

C3032

6.3V

1UF

10%
CERM

402

2

1

C3033

402

CERM

10%

1UF

6.3V

2

1

C3041

10%
CERM

6.3V

1UF

402

2

1

C3042

402

10%
CERM

6.3V

1UF

2

1

C3044

402

10%
CERM

6.3V

1UF

2

1

C3046

10%

1UF

6.3V
CERM
402

2

1

C3096

402

CERM

10%

1UF

6.3V

2

1

C3095

402

CERM

10%

1UF

6.3V

2

1

C30AG

402

CERM

10%

1UF

6.3V

2

1

C30AF

402

CERM

10%

1UF

6.3V

2

1

C3039

6.3V

1UF

10%
CERM

402

2

1

C3038

6.3V

1UF

10%
CERM

402

2

1

C3037

6.3V

1UF

10%
CERM

402

2

1

C3036

6.3V

1UF

10%
CERM

402

2

1

C3035

6.3V

1UF

10%
CERM

402

2

1

C3034

10%

6.3V

1UF

CERM
402

2

1

C3015

6.3V
402

CERM

10%

1UF

2

1

C3065

402

CERM

10%

1UF

6.3V

2

1

C3064

402

CERM

10%

1UF

6.3V

2

1

C3063

6.3V
402

CERM

10%

1UF

2

1

C3062

CERM
402

10%

1UF

6.3V

2

1

C3061

402

CERM

10%

1UF

6.3V

2

1

C3060

402

CERM

10%

1UF

6.3V

2

1

C3059

402

CERM

10%

1UF

6.3V

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

MEMORY CAPS

=PP1V5_S3_MEM_A

=PP1V5_S0_CPU_MEM

=PP1V5_S0_CPU_MEM

=PP1V5_S3_MEM_B

=PP1V5_S0_CPU_MEM

30 OF 110

11.1.0

051-8115

29 OF 98

6

28 30

6

11 13 16 28 29

6

11 13 16 28 29

6

28 31

6

11 13 16 28 29

www.vinafix.vn

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6
DQ7

VREFDQ
VSS_1

VSS_3

DQ0
DQ1

DM0
VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30
DQ31

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA
SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1*
DQS1
VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2
VSS_17

DQS2*

VSS_14

VSS_21

DQ24
DQ25

DQ19
VSS_19

VSS_24

DQ27

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6*
DQS6

VSS_40

DQ49

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9
VSS_8
DQS1*
DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP
BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47
DM7

DQ58
DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6
VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26
DQ32
DQ33

TEST

VDD_16

S1*

A13

CAS*
VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0
NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0
VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46
DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38
DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6
A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15
A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30
DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18
DQ19

DQ25

DQ24

DM3
VSS_22

DQ27
VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DIMM0

(Section A)

(Section B)

DIMM2

BOM options provided by this page:

Signal aliases required by this page:

(NONE)

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

Page Notes

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S0_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PP1V5_S3_MEM_A

TO FACILITATE BITSWAPS WITH ALIASES

- ALL DQ, DQS, DM SIGNALS;

DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD)

DIMM 0

DIMM 2

DIMM2 SPD ADDR=0XA2(WR)/0XA3(RD)

STACKED SO-DIMM CONN.

Power aliases required by this page:

CPU - MEM Ch. A

2

1

C3131

402

10V

0.1UF

20%

CERM

2

1

C3130

CERM
402-LF

20%

2.2UF

6.3V

2

1

C3136

10V

20%

0.1UF

402

CERM

2

1

C3135

402-LF

20%

CERM

6.3V

2.2UF

2

1

C3151

2.2UF

CERM
402-LF

6.3V

20%

2

1

C3150

6.3V

20%

CERM
402-LF

2.2UF

2

1

R3141

MF-LF

5%

10K

1/16W

402

2

1

R3140

5%

10K

1/16W

402

MF-LF

2

1

C3140

402-LF

6.3V
CERM

20%

2.2UF

2

1

R3142

MF-LF

10K

5%

402

1/16W

2

1

R3143

10K

402

5%
1/16W
MF-LF

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A

99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A
202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A
188A

169A
171A

152A
154A

135A
137A

62A
64A

45A
47A

27A
29A

10A
12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A
97A

78A
80A

119A

83A 84A

107A

98A

J3100

DDR3-SODIMM-DUAL

F-RT-TH

CRITICAL

113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B

99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B
202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B
188B

169B
171B

152B
154B

135B
137B

62B
64B

45B
47B

27B
29B

10B
12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B
97B

78B
80B

119B

83B 84B

107B

98B

J3100

F-RT-TH

DDR3-SODIMM-DUAL

CRITICAL

DDR3 SO-DIMM 0 & 2

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

=I2C_SODIMMA_SDA

=MEM_A_DQ<62>

=MEM_A_DQ<52>

MEM_A_ODT<0>

MEM_A_CS_L<0>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<1>

=MEM_A_DQ<8>

=MEM_A_DQ<20>

=MEM_A_DQ<14>

=MEM_A_DQ<8>

=MEM_A_DQ<2>

=MEM_A_DQ<10>

=MEM_A_DQ<31>

=PP1V5_S3_MEM_A

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<6>

MEM_DIMM2_SA<0>
=PPSPD_S0_MEM_A

MEM_DIMM0_SA<0>
=PPSPD_S0_MEM_A
MEM_DIMM0_SA<1>
=PP0V75_S0_MEM_VTT_A

=MEM_A_DQ<58>

=MEM_A_DQ<51>

=MEM_A_DQ<44>
=MEM_A_DQ<45>

MEM_A_A<7>

MEM_A_A<15>

MEM_A_CKE<1>

=MEM_A_DQ<19>

=MEM_A_DQS_P<2>

=MEM_A_DQ<29>

MEM_A_CAS_L

MEM_A_ODT<2>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_CLK_P<2>
=MEM_A_CLK_N<2>

=MEM_A_DQ<27>

MEM_A_CKE<0>

=MEM_A_DQ<22>

=MEM_A_DQ<3> =MEM_A_DQ<7>

=MEM_A_DQ<17>

=MEM_A_DQ<16>

=MEM_A_DQ<60>

=MEM_A_DQS_N<1>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQS_P<1>

=PP1V5_S3_MEM_A

MEM_A_A<4>

MEM_A_A<6>

MEM_A_RAS_L

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<9>

=MEM_A_DQ<13>

=MEM_A_DQ<0>
=MEM_A_DQ<1>

MEM_A_A<14>

=PPSPD_S0_MEM_A

=MEM_A_DQ<9>

=MEM_A_DQ<2>

=MEM_A_DQ<1>

=MEM_A_DQ<50>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<41>

=MEM_A_DQ<34>

=MEM_A_DQS_N<4>

MEM_A_WE_L

MEM_A_A<10>

MEM_A_A<5>

MEM_A_A<12>
MEM_A_A<9>

MEM_A_A<8>

=MEM_A_DQ<36>

=PP1V5_S3_MEM_A

=MEM_A_DQ<0>

=MEM_A_DQ<24>
=MEM_A_DQ<25>

=MEM_A_DQ<16>

=MEM_A_DQ<7>

=MEM_A_DQS_N<0>

=MEM_A_DQ<32>

MEM_A_ODT<3>

=MEM_A_DQ<10>

=MEM_A_DQ<3>

=MEM_A_DQ<28>

=MEM_A_DQS_N<3>

=MEM_A_DQ<61>

=MEM_A_DQ<49>

=MEM_A_DQ<48>

MEM_A_ODT<1>

MEM_A_CKE<2>

=MEM_A_DQ<38>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DQ<14>

MEM_RESET_L

=MEM_A_DQ<30>

=MEM_A_DQ<11>

=MEM_A_DQ<6>

=MEM_A_DQ<11>

MEM_A_CKE<3>

MEM_A_A<7>

MEM_A_A<0>

=MEM_A_DQ<24>

=MEM_A_DQ<12>

MEM_A_A<13>

=MEM_A_CLK_N<0>

=MEM_A_DQ<29>

=MEM_A_DQ<18>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

MEM_A_A<6>

=MEM_A_DQ<23>

=MEM_A_DQS_P<3>

=MEM_A_DQ<44>

=MEM_A_DQ<52>

=MEM_A_DQ<49>

MEM_A_A<2>MEM_A_A<2>

=MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_A<4>

MEM_A_A<11>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_CS_L<1>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQ<41>

=MEM_A_DQ<38>

=MEM_A_DQ<26>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<1>

MEM_A_A<12>

=MEM_A_DQ<22>

=MEM_A_DQ<25>

MEM_A_A<5>

MEM_A_A<3>
MEM_A_A<1>

=MEM_A_CLK_P<3>

MEM_A_A<14>

=MEM_A_DQ<30>=MEM_A_DQ<26>

=MEM_A_DQ<27>

MEM_A_A<1>

=MEM_A_DQS_P<6>

=MEM_A_DQ<5>

=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>

=MEM_A_DQ<17>

=MEM_A_DQ<39>

=MEM_A_DQ<21>

=MEM_A_DQS_P<7>

=MEM_A_DQ<63>

MEM_EVENT_L

=I2C_SODIMMA_SCL

=PPSPD_S0_MEM_A

=MEM_A_DQ<43>

MEM_A_A<15>

=MEM_A_DQ<19>

=MEM_A_DQ<18>

MEM_A_BA<0>

MEM_DIMM0_SA<0>

MEM_DIMM0_SA<1>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

MEM_DIMM2_SA<1>
=PP0V75_S0_MEM_VTT_A

=MEM_A_DQ<51>

MEM_A_BA<2>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<48>

=MEM_A_DQ<40>

=MEM_A_DQ<35>

=MEM_A_DQS_P<4>

=MEM_A_DQ<33>

=MEM_A_DQS_N<7>

=PP0V75_S0_MEM_VTT_A

=MEM_A_DQ<53>

=MEM_A_DQ<60>

=MEM_A_DQ<45>

=MEM_A_DQ<46>
=MEM_A_DQ<47>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DQ<36>
=MEM_A_DQ<37>

=MEM_A_DQ<39>

MEM_A_CS_L<2>

MEM_A_BA<1>

=MEM_A_CLK_N<3>

MEM_A_RAS_L

=MEM_A_DQ<6>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_A_CAS_L

MEM_A_A<13>
MEM_A_CS_L<3>

=MEM_A_CLK_N<1>

=MEM_A_DQS_N<2>

=MEM_A_DQ<21>

=MEM_A_DQ<4>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

MEM_A_A<11>

=MEM_A_DQS_P<5>

=MEM_A_DQ<47>

=MEM_A_DQ<46>

=MEM_A_DQ<61>

=MEM_A_DQ<54>

=MEM_A_DQ<53>

=MEM_A_DQ<62>

MEM_EVENT_L

=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>

=MEM_A_DQ<63>

=PP0V75_S0_MEM_VTT_A

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

=MEM_A_CLK_P<0>

=MEM_A_DQ<33>

=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<40>

=MEM_A_DQ<42>

=MEM_A_DQS_N<6>

=MEM_A_DQ<50>

=MEM_A_DQ<56>
=MEM_A_DQ<57>

=MEM_A_DQ<59>

MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<3>

=MEM_A_DQ<37>

MEM_A_BA<1>

=MEM_A_DQ<55>

=MEM_A_DQS_N<5>

=MEM_A_DQ<15>

=MEM_A_DQ<4>
=MEM_A_DQ<5>

=MEM_A_DQ<13>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<0>

MEM_RESET_L

=MEM_A_DQ<12>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>

=MEM_A_DQ<31>

=PP1V5_S3_MEM_A

=PP0V75_S0_MEM_VTT_A

PP0V75_S3_MEM_VREFDQ_A

31 OF 110

11.1.0

051-8115

30 OF 98

30 49

30 32

30 32

12 89

12 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

6

28 29 30

30 32

30 32

30

6

30 47

30

6

30 47

30

6

30

30 32

30 32

30 32

30 32

12 30 89

12 30 89

12 89

30 32

30 32

30 32

12 30 89 12 89

28 30 95

32

32

30 32

12 89

30 32

30 32 30 32

30 32

30 32

30 32

30 32

28 30 95

30 32

6

28 29 30

12 30 89

12 30 89

12 30 89

28 30 95

30 32 30 32

30 32

30 32

12 30 89

6

30 47

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

30 32

6

28 29 30

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 89

12 89

30 32

28 30 95

30 32

30 31 32 89 97

30 32

30 32

30 32

30 32

12 89

12 30 89

12 30 89

30 32

30 32

12 30 89

32

30 32

30 32

30 32

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

12 30 89 12 30 89

32

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

12 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 30 89

30 32

30 32

12 30 89

12 30 89

12 30 89

32

12 30 89

30 32 30 32

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 31 47

30 49

6

30 47

30 32

12 30 89

30 32

30 32

12 30 89

30

30

30

30

30

6

30

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

6

30

30 32

30 32

30 32

30 32

30 32

28 30 95

30 32

30 32

30 32

12 89

12 30 89

32

12 30 89

30 32

30 32

30 32

12 30 89

12 30 89

12 89

32

30 32

30 32

30 32

30 32

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 31 47

30 32

30 32

30 32

6

30

30 49

30 49

32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 30 89

12 30 89

12 30 89

12 30 89

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 31 32 89 97

30 32

30 32

30 32

30 32

30 32

6

28 29 30

6

30

28 30 95

www.vinafix.vn

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6
DQ7

VREFDQ
VSS_1

VSS_3

DQ0
DQ1

DM0
VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30
DQ31

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA
SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1*
DQS1
VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2
VSS_17

DQS2*

VSS_14

VSS_21

DQ24
DQ25

DQ19
VSS_19

VSS_24

DQ27

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6*
DQS6

VSS_40

DQ49

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9
VSS_8
DQS1*
DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP
BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47
DM7

DQ58
DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6
VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26
DQ32
DQ33

TEST

VDD_16

S1*

A13

CAS*
VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0
NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0
VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46
DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38
DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6
A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15
A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30
DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18
DQ19

DQ25

DQ24

DM3
VSS_22

DQ27
VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU - MEM Ch. B

STACKED SO-DIMM CONN.

- =PP1V5_S3_MEM_B

(Section A)

DIMM3

DIMM1
(Section B)

Power aliases required by this page:

- =PP1V5_S0_MEM_B

DIMM1 SPD ADDR=0XA4(WR)/0XA5(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)

(NONE)

- =I2C_SODIMMB_SCL

- =PP0V75_S0_MEM_VTT_B

- =I2C_SODIMMB_SDA

BOM options provided by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Page Notes

- ALL DQ, DQS, DM SIGNALS;

Signal aliases required by this page:

TO FACILITATE BITSWAPS WITH ALIASES

DIMM 3

DIMM 1

2

1

C3231

0.1UF

20%
10V
CERM
402

2

1

C3230

CERM

2.2UF

20%

6.3V

402-LF

2

1

C3236

10V

20%

0.1UF

402

CERM

2

1

C3235

2.2UF

402-LF

20%

CERM

6.3V

2

1

C3251

CERM

6.3V

20%

402-LF

2.2UF

2

1

C3250

6.3V

20%

CERM
402-LF

2.2UF

2

1

R3243

402

5%
1/16W
MF-LF

10K

2

1

R3242

MF-LF

1/16W

5%

402

10K

2

1

C3240

20%

2.2UF

6.3V

402-LF

CERM

2

1

R3240

10K

5%

402

1/16W
MF-LF

2

1

R3241

MF-LF

1/16W

5%

402

10K

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A

99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A
202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A
188A

169A
171A

152A
154A

135A
137A

62A
64A

45A
47A

27A
29A

10A
12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A
97A

78A
80A

119A

83A 84A

107A

98A

J3200

F-RT-TH

CRITICAL

DDR3-SODIMM-DUAL

113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B

99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B
202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B
188B

169B
171B

152B
154B

135B
137B

62B
64B

45B
47B

27B
29B

10B
12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B
97B

78B
80B

119B

83B 84B

107B

98B

J3200

CRITICAL

F-RT-TH

DDR3-SODIMM-DUAL

DDR3 SO-DIMM 1 & 3

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

=MEM_B_DQS_P<4>

MEM_B_A<2>

=MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_A<0>

=MEM_B_DQS_P<2>

MEM_B_A<11>

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_CKE<0>

=MEM_B_DQ<2>

=MEM_B_DQ<34>
=MEM_B_DQ<35>

=PP1V5_S3_MEM_B

=MEM_B_DQ<10>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<0>
=MEM_B_DQ<1>

=MEM_B_DQ<7>

=MEM_B_DQ<12>

MEM_B_A<13>

=MEM_B_DQ<32>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DQ<31>

=MEM_B_DQ<13>

MEM_B_WE_L

=MEM_B_DQ<27>

MEM_B_A<9>

MEM_B_A<12>

=PPSPD_S0_MEM_B
MEM_DIMM3_SA<1>
=PP0V75_S0_MEM_VTT_B

MEM_DIMM3_SA<0>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<49>

=MEM_B_DQS_N<6>

=MEM_B_DQ<42>
=MEM_B_DQ<43>

=MEM_B_DQ<40>
=MEM_B_DQ<41>

=MEM_B_DQS_N<4>

=MEM_B_DQ<33>

=MEM_B_CLK_P<2>

=MEM_B_DQ<26>

=MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62>
=MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

=PP0V75_S0_MEM_VTT_B

=MEM_B_DQ<53>

=MEM_B_DQ<60>

=MEM_B_DQ<47>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

MEM_B_CS_L<2>

MEM_B_BA<1>

=MEM_B_CLK_N<3>

MEM_B_RAS_L

MEM_B_ODT<2>

MEM_B_ODT<3>

=MEM_B_CLK_P<3>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_CKE<3>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<21>

=MEM_B_DQ<14>
=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<6>

=MEM_B_DQ<4>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_CS_L<3>

=MEM_B_DQ<27>

=MEM_B_DQ<24>
=MEM_B_DQ<25>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<17>

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<0>

=MEM_B_DQ<4>
=MEM_B_DQ<5>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

MEM_B_CKE<1>

MEM_B_A<14>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQS_P<5>

=MEM_B_DQ<47>

=MEM_B_DQ<46>

=MEM_B_DQS_N<5>

=MEM_B_DQ<44>

=MEM_B_DQ<52>

=MEM_B_DQ<61>

=MEM_B_DQ<53>

=MEM_B_DQ<60>

=MEM_B_DQ<62>

MEM_EVENT_L

=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>

=MEM_B_DQ<63>

=PP0V75_S0_MEM_VTT_B

=MEM_B_DQ<1>

=MEM_B_DQ<0>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<8>

=MEM_B_DQ<10>

=MEM_B_DQ<16>

=MEM_B_DQ<11>

MEM_B_A<12>

MEM_B_A<5>

MEM_B_A<3>
MEM_B_A<1>

=MEM_B_CLK_P<0>

MEM_B_WE_L
MEM_B_CAS_L

MEM_B_A<13>
MEM_B_CS_L<1>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>

=MEM_B_DQ<34>
=MEM_B_DQ<35>

=MEM_B_DQ<41>

=MEM_B_DQ<42>
=MEM_B_DQ<43>

=MEM_B_DQ<48>
=MEM_B_DQ<49>

=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>

=MEM_B_DQ<50>
=MEM_B_DQ<51>

=MEM_B_DQ<56>

MEM_B_BA<0>

MEM_B_A<10>

=MEM_B_CLK_N<0>

MEM_B_A<8>

MEM_B_A<9>

=MEM_B_DQ<26>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CS_L<0>

=MEM_B_CLK_P<1>

=MEM_B_DQ<22>

=MEM_B_DQS_N<3>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<14>

MEM_B_A<15>

=MEM_B_DQ<2>

=MEM_B_DQ<15>

=MEM_B_DQ<46>

=MEM_B_DQ<52>=MEM_B_DQ<48>

=MEM_B_DQS_P<6>

=MEM_B_DQ<40>

=MEM_B_DQ<3>

=MEM_B_DQ<12>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQS_P<5>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<39>

MEM_B_CAS_L

=MEM_B_DQ<17>

=MEM_B_DQ<25>

MEM_B_CKE<2>

MEM_B_BA<2>

=PP1V5_S3_MEM_B

=MEM_B_DQ<39>

=MEM_B_DQ<51>

=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

MEM_B_A<15>

=MEM_B_DQ<9>

=MEM_B_DQS_N<0>

=MEM_B_DQ<20>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

MEM_B_A<4>

MEM_B_A<6>

=PP1V5_S3_MEM_B

MEM_B_A<7>

MEM_B_A<11>

MEM_B_BA<2>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<1>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQ<24>

MEM_B_A<7>

MEM_DIMM1_SA<1>
=PP0V75_S0_MEM_VTT_B

=MEM_B_DQ<36>

=MEM_B_DQ<57>

=MEM_B_DQ<58>
=MEM_B_DQ<59>

=PPSPD_S0_MEM_B

=MEM_B_DQS_N<5>

MEM_B_BA<0>

=MEM_B_CLK_N<2>

MEM_EVENT_L

MEM_DIMM1_SA<0>

MEM_B_RAS_L

MEM_RESET_L

=MEM_B_DQ<29>

MEM_DIMM3_SA<0>

=PPSPD_S0_MEM_B

MEM_DIMM3_SA<1>

MEM_DIMM1_SA<1>
MEM_DIMM1_SA<0>

=PPSPD_S0_MEM_B =PPSPD_S0_MEM_B

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<54>
=MEM_B_DQ<55>

MEM_RESET_L

=MEM_B_DQ<45>

=MEM_B_DQ<61>

=MEM_B_DQ<5>

=MEM_B_DQ<50>

=MEM_B_DQ<56>

=PP0V75_S0_MEM_VTT_B

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www.vinafix.vn

G

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D

S

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G

D

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G

D

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PAD

VCC

THRM

GND

1RD*

1Q

2SD*
2D
2CP
2RD*

2Q

2Q*

1CP

1D 1Q*

1SD*

G

D

S

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D

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL B DQS 0 -> DIMM B DQS 7

CPU CHANNEL A DQS 6 -> DIMM A DQS 1 CPU CHANNEL B DQS 6 -> DIMM B DQS 1

CPU CHANNEL A DQS 3 -> DIMM A DQS 4

CPU CHANNEL A DQS 5 -> DIMM A DQS 2

CPU CHANNEL A DQS 4 -> DIMM A DQS 3

CPU CHANNEL A DQS 1 -> DIMM A DQS 6

CPU CHANNEL A DQS 0 -> DIMM A DQS 7

CPU CHANNEL A DQS 2 -> DIMM A DQS 5

CPU CHANNEL B DQS 1 -> DIMM B DQS 6

CPU CHANNEL B DQS 2 -> DIMM B DQS 5

CPU CHANNEL B DQS 4 -> DIMM B DQS 3

CPU CHANNEL B DQS 5 -> DIMM B DQS 2

CPU CHANNEL B DQS 3 -> DIMM B DQS 4

CPU CHANNEL B DQS 7 -> DIMM B DQS 0CPU CHANNEL A DQS 7 -> DIMM A DQS 0

MEMORY CLOCK ALIASING

0 0 1.5V

0 3.3V 0

1.5V 3.3V 1.5V

0 3.3V 0

1.5V 3.3V 1.5V

0 3.3V 0

CPU_RESET_L ISOLATE_L MEM_RESET_L

H H POSEDGE H H L

L L X X H H

H L X X L H

L H X X H L

H H POSEDGE L L H

S R CLK D Q QB

S0

S5

S0

S3

S0

S5

SNB? CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.

DDR3 RESET SUPPORT

2

1

R3353

402

MF-LF

5%
1/16W

20K

2

1

C3353

402

10%

CERM

0.0022UF

50V

2

1

R3382

MEM_RESET_HW

10K

MF-LF

1/16W

402

5%

2

1

3

Q3350

MEM_RESET_HW

2N7002

SOT23-HF1

2

1

R3381

5%

402

1/16W
MF-LF

10K

MEM_RESET_HW

2

1

R3384

1/16W
MF-LF
402

5%

20K

2

3

1

Q3360

SOT23-HF

MEM_RESET_HW

2N3904

4

5

3

Q3370

SOT-363

2N7002DW-X-G

21

R3355

NOSTUFF

1/16W
MF-LF

0

5%

402

2

1

3

Q3304

2N7002

SOT23-HF1

2

1

R3352

5%

20K

1/16W

402

MF-LF

4

5

3

Q3306

2N7002DW-X-G

SOT-363

2

1

R3351

20K

5%
1/16W

402

MF-LF

2

1

R3350

1/16W

5%

402

MF-LF

20K

1

2

6

Q3306

SOT-363

2N7002DW-X-G

21

R3380

MF-LF

MEM_RESET_HW

402

5%

1/16W

10K

21

R3385

5%

0

1/16W
MF-LF

402

21

R3383

402

MF-LF

5%

0

1/16W

NOSTUFF

2

1

R3387

5%

402

MF-LF

1/16W

20K

21

R3393

402

5%

0

MF-LF

1/16W

NOSTUFF

21

R3394

0

402

MF-LF

1/16W

5%

2

1

C3300

MEM_RESET_HW

402

0.1UF

20%

CERM

10V

14

15

10

4

13

1

8

6

9

5

7

12

2

11

3

U3300

MEM_RESET_HW

DHVQFN

74LVC74ABQ

2

1

C3390

NOSTUFF

CERM

20%
10V

0.1UF

402

5

4

1

2

3

U3390

SOT23-5-HF

NOSTUFF

MC74VHC1G08

1

2

6

Q3370

2N7002DW-X-G

SOT-363

21

R3391

1/16W
MF-LF

402

NOSTUFF

5%

0

21

R3386

0

5%
1/16W
MF-LF

402

NOSTUFF

2

1

R3388

402

5%

MF-LF

10

1/16W

2

1

3

Q3380

2N7002

SOT23-HF1

3
2
1

4

5

Q3375

POWER33

FDMC8296

2

1

R3340

402

5%

MF-LF

1/16W

100K

21

R3390

0

5%

NOSTUFF

MF-LF

1/16W

402

DDR3 SUPPORT AND BITSWAPS

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>

=MEM_B_DQ<32>
=MEM_B_DQ<39>

PM_EN_DDRVTT_S0_REG

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQ<28>

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>

=MEM_B_DQ<59>

PPVTT_S0_DDR_FET

CPU_MEM_RESET3V3_L
PM_SLP_S3_L

PM_SYS_PWRGD

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<5>

TP_PM_SLP_S4_D

PM_SLP_S4_L

=PP3V3_S3_MEMRESET

PM_SLP_S4_D_L

PM_SLP_S4_D_L

=PP3V3_S3_MEMRESET

SLP_S3_CTL_L

CPU_MEM_RESET_R_L

CPU_MEM_RESET_L

ISOLATE_CPU_MEM_L

=PP3V3_S5_MEMRESET

=PP5V_S3_MEMRESET

CPU_MEM_RESET3V3

=PP3V3_S5_MEMRESET

ISOLATE_CPU_MEM_L_R1

=PP5V_S3_MEMRESET

MEM_RESET_L

CPU_MEM_RESET_L

=PP1V5_S3_MEMRESET

PM_SLP_S3_5V_L

CPU_MEM_RESET3V3_L

=PP3V3_S3_MEMRESET

MAKE_BASE=TRUE

MEM_B_CLK_P<2>

NO_TEST=TRUE

=MEM_B_CLK_P<2>

MAKE_BASE=TRUE

MEM_B_CLK_N<1>

NO_TEST=TRUE

=MEM_B_CLK_N<1>

MAKE_BASE=TRUE

MEM_B_CLK_N<2>

NO_TEST=TRUE

=MEM_B_CLK_N<2>

MAKE_BASE=TRUE

MEM_B_CLK_P<3>

NO_TEST=TRUE

=MEM_B_CLK_P<3>

MAKE_BASE=TRUE

MEM_B_CLK_N<3>

NO_TEST=TRUE

=MEM_B_CLK_N<3>

MAKE_BASE=TRUE

MEM_A_CLK_N<3>

NO_TEST=TRUE

=MEM_A_CLK_N<3>

MEM_B_CLK_P<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_B_CLK_P<0>

MAKE_BASE=TRUE

MEM_B_CLK_P<1>

NO_TEST=TRUE

=MEM_B_CLK_P<1>

MEM_B_CLK_N<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_B_CLK_N<0>

MAKE_BASE=TRUE

MEM_A_CLK_P<1>

NO_TEST=TRUE

=MEM_A_CLK_P<1>

MAKE_BASE=TRUE

MEM_A_CLK_N<1>

NO_TEST=TRUE

=MEM_A_CLK_N<1>

MAKE_BASE=TRUE

MEM_A_CLK_P<2>

NO_TEST=TRUE

=MEM_A_CLK_P<2>

MAKE_BASE=TRUE

MEM_A_CLK_N<2>

NO_TEST=TRUE

=MEM_A_CLK_N<2>

MAKE_BASE=TRUE

MEM_A_CLK_P<3>

NO_TEST=TRUE

=MEM_A_CLK_P<3>

MAKE_BASE=TRUE

MEM_A_CLK_N<0>

NO_TEST=TRUE

=MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<57> =MEM_A_DQ<7>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<49>

=MEM_A_DQ<11>

MAKE_BASE=TRUE

MEM_A_DQ<50> =MEM_A_DQ<9>

MEM_A_DQ<51>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<52>

=MEM_A_DQ<10>

=MEM_A_DQ<13>

=MEM_A_DQ<12>

=MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

NO_TEST=TRUE

=MEM_A_DQS_N<1>

=MEM_A_DQ<20>

=MEM_A_DQ<22>

MEM_A_DQS_P<5>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_A_DQ<30>

=MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MEM_A_DQ<39>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

NO_TEST=TRUE

=MEM_A_DQS_N<3>

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<25>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<27>

=MEM_A_DQ<36>

=MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MEM_A_DQ<30>

MAKE_BASE=TRUE

=MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQ<31>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<17>

=MEM_A_DQ<43>

MEM_A_DQ<18>

MAKE_BASE=TRUE

=MEM_A_DQ<44>

=MEM_A_DQ<41>

MEM_A_DQ<20>

MAKE_BASE=TRUE

=MEM_A_DQ<47>

MEM_A_DQ<21>

MAKE_BASE=TRUE

=MEM_A_DQ<46>

=MEM_A_DQ<40>

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<55>
=MEM_A_DQ<54>

MEM_B_DQ<56>

MAKE_BASE=TRUE

=MEM_B_DQ<0>

MEM_B_DQ<57>

MAKE_BASE=TRUE

=MEM_B_DQ<6>

MEM_B_DQ<59>

MAKE_BASE=TRUE

=MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<58> =MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<60> =MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQ<61> =MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<63> =MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<62> =MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

NO_TEST=TRUE

=MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_B_DQS_N<0>

MEM_B_DQ<48>

MAKE_BASE=TRUE

=MEM_B_DQ<13>

MEM_B_DQ<49>

MAKE_BASE=TRUE

=MEM_B_DQ<12>

MAKE_BASE=TRUE

MEM_B_DQ<50>

=MEM_B_DQ<15>

MEM_B_DQ<51>

MAKE_BASE=TRUE

=MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<52>

=MEM_B_DQ<11>

MAKE_BASE=TRUE

MEM_B_DQ<54>

=MEM_B_DQ<14>

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<55>

MAKE_BASE=TRUE

=MEM_B_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQS_P<6>

NO_TEST=TRUE

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<17>

MEM_B_DQ<40>

MAKE_BASE=TRUE

=MEM_B_DQ<16>

MEM_B_DQ<42>

MAKE_BASE=TRUE

=MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<43>

=MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQ<45>

=MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQ<44>

=MEM_B_DQ<22>

MAKE_BASE=TRUE

MEM_B_DQ<46>

=MEM_B_DQ<20>

MEM_B_DQ<47>

MAKE_BASE=TRUE

=MEM_B_DQ<18>

MEM_B_DQS_P<5>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_B_DQS_P<2>

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_B_DQS_N<2>

MEM_B_DQ<32>

MAKE_BASE=TRUE

=MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<33>

=MEM_B_DQ<27>

MEM_B_DQ<34>

MAKE_BASE=TRUE

=MEM_B_DQ<25>

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

=MEM_B_DQ<24>

MEM_B_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<24>

=MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<25>

=MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<27>

=MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<26>

=MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<28>

=MEM_B_DQ<38>

MEM_B_DQ<29>

MAKE_BASE=TRUE

=MEM_B_DQ<37>

MEM_B_DQ<30>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQS_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

NO_TEST=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

=MEM_B_DQ<43>

MEM_B_DQ<18>

MAKE_BASE=TRUE

=MEM_B_DQ<41>

MAKE_BASE=TRUE

MEM_B_DQ<17>

=MEM_B_DQ<46>

MEM_B_DQ<19>

MAKE_BASE=TRUE

=MEM_B_DQ<44>

=MEM_B_DQ<47>

MAKE_BASE=TRUE

MEM_B_DQ<21>

=MEM_B_DQ<42>

MAKE_BASE=TRUE

MEM_B_DQ<23>
MEM_B_DQ<22>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_P<2>

NO_TEST=TRUE

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<8>

MAKE_BASE=TRUE

=MEM_A_DQ<48>

MEM_A_DQ<12>

MAKE_BASE=TRUE

=MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

NO_TEST=TRUE

=MEM_A_DQS_N<6>

MEM_A_DQ<3>

MAKE_BASE=TRUE

=MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<4>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<11>

=MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQ<13>

=MEM_B_DQ<53>

MEM_B_DQ<12>

MAKE_BASE=TRUE

=MEM_B_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<14>

=MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<15>

=MEM_B_DQ<51>

=MEM_B_DQS_N<6>

MEM_B_DQS_P<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQ<0>

MEM_B_DQ<1>

MAKE_BASE=TRUE

=MEM_B_DQ<58>

MEM_B_DQ<2>

MAKE_BASE=TRUE

=MEM_B_DQ<57>

MEM_B_DQ<4>

MAKE_BASE=TRUE

=MEM_B_DQ<63>
=MEM_B_DQ<56>

MEM_B_DQ<5>

MAKE_BASE=TRUE

=MEM_B_DQ<62>

MEM_B_DQ<6>

MAKE_BASE=TRUE

=MEM_B_DQ<60>

=MEM_B_DQ<61>

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

ISOLATE_CPU_MEM

PM_SLP_S3_5V

=MEM_B_DQ<55>

=MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<10>

=MEM_A_DQ<53>

PM_SLP_S3_5V_L

VTT_R

=PP0V75_S0_MEM_VTT_S0FET

PM_SLP_S3_5V

=MEM_B_DQ<40>

ISOLATE_CPU_MEM_L_R1

ISOLATE_CPU_MEM_5V_L

TP_ISOLATE_CPU

ISOLATE_CPU_MEMHW_L

PM_SLP_S3_L

=PP3V3_S5_MEMRESET

PM_SLP_S3_5V_R2

DDRSYS_EN

ALL_SYS_PWRGD_R

MEM_B_DQ<20>

MAKE_BASE=TRUE

=MEM_A_DQ<32>

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<37>

MAKE_BASE=TRUE

=MEM_A_DQ<59>

MEM_A_DQ<13>

MAKE_BASE=TRUE

=MEM_A_DQ<62>

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

=MEM_A_DQ<56>

=MEM_A_DQS_P<7>

=MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<15>

=MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<11>
MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MAKE_BASE=TRUE

=MEM_A_DQ<63>

=MEM_A_DQ<61>

MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MAKE_BASE=TRUE

=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_A_DQ<39>

=MEM_A_DQ<35>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQ<1>

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_A_DQ<45>

MEM_B_DQ<41>

MAKE_BASE=TRUE

=MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQS_N<6>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MEM_A_DQ<55>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<6>

NO_TEST=TRUE

=MEM_A_DQS_N<2>

=MEM_A_DQ<26>

=MEM_A_DQ<31>

=MEM_A_DQ<27>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<25>

MEM_A_DQ<26>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_N<5>

NO_TEST=TRUE

MEM_A_DQ<35>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE

=MEM_A_DQ<19>

MEM_A_DQ<34>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQ<33>
MEM_A_DQ<32>

MAKE_BASE=TRUE

=MEM_A_DQS_P<2>

=MEM_A_DQ<16>

=MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

=MEM_A_DQ<38>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQ<45>

=MEM_A_DQ<23>
=MEM_A_DQ<21>

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

=MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<0>

=MEM_A_DQ<6>

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>

=MEM_A_DQ<3>

=MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

NO_TEST=TRUE

=MEM_A_DQ<8>

=MEM_A_DQ<14>

=MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

NO_TEST=TRUE

=MEM_A_CLK_P<0>

MAKE_BASE=TRUE

MEM_B_DQS_N<1>

NO_TEST=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

NO_TEST=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

NO_TEST=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

=MEM_A_DQS_P<3>

MEM_A_DQ<28>

MAKE_BASE=TRUE

33 OF 110

11.1.0

051-8115

32 OF 98

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30 31 89 97

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www.vinafix.vn

IN

KEY

IN
IN

OUT

OUT

IN

IN

G

D

S

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

IN

OUT

OUT

IN

D

GS

OUT

OUT

D

GS

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: CURRENT DATA PER APR 5,2010 PCIE MINI CEM ECN

AP WAKE# ISOLATION

RESET HAS 100MS DELAY ONCE ENABLE IS HIGH

AP PWR EN ISOLATION

516S0457

NC

RESERVED

NC

| MAX CONT. 1100MA 190MA |

| 3.3V S3 CURRENT D0-D2,D3HOT D3COLD |

NC

| |

NC

NC

NC

NC

NC

NC
NC

NC

NC

NC

NC

| 1.5V CURRENT |
| MAX CONT. N/U N/U |
| MAX PEAK N/U N/U |

-----------------------------------------

| MAX PEAK 2750MA 2750MA |

-----------------------------------------

RESERVED

NO AVAILALBLE USB ON THIS PLATFORM
TARGET CARDS DO NOT USE IT

NC

21

R3491

MF-LF

0

5%

1/16W

402

NOSTUFF

33 97

9

87

6

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

16

15

1413

1211

10

1

54

53

J3400

F-RT-SM

CRITICAL

AS0B226-S40N-7F

18 90

18 90

21

R3400

5%

1/16W

402

MF-LF

0

NOSTUFF

21

R3401

MF-LF

5%

402

1/16W

0

NOSTUFF

21

C3431

0.1uF

10%
16V

402

X5R

PLACEMENT_NOTE=PLACE CLOSE TO U1800.

21

C3430

PLACEMENT_NOTE=PLACE CLOSE TO U1800.

X5R

0.1uF

10%
16V

402

18 90

18 90

18 90

18 90

2

1

C3461

10%
16V
X5R

0.1UF

402

1

4

5

Q3403

CRITICAL

PQFN

IRFH3702TRPBF

1

9

6

8

2

4

7

5

U3404

CRITICAL

SLG5AP001

TDFN

1

9

2

4

8

3

7

5

6

Q3406

SLG4AP016V

TDFN

2

1

C3408

402

16V
X5R

0.1UF

10%

2

1

R3410

10K

MF-LF

1/16W

5%

402

27 97

33

15 97

2

1

R3412

402

1/16W
MF-LF

1%

100K

33 97

33

2

1

R3470

1/16W
MF-LF

5%

10K

402

2

1

3

Q3470

SOD-VESM-HF

SSM3K15FV

33

19 36 78 97

2

1

R3471

MF-LF

5%

10K

402

1/16W

2

1

3

Q3471

AP

SOD-VESM-HF

SSM3K15FV

2

1

C3421

X5R
603

6.3V

20%

10uF

2

1

C3401

20%
X5R

603

10uF

6.3V

NOSTUFF

2

1

C3420

402

20%

CERM

10V

0.1uF

2

1

C3410

402

0.1uF

20%
10V

CERM

2

1

C3400

20%
10V

402

CERM

0.1uF

NOSTUFF

21

R3490

402

0

5%
1/16W
MF-LF

NOSTUFF

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

PCI-E Wireless Connector

AP_PWR_EN

PCIE_MINI_R2D_P

PCIE_MINI_R2D_N

=PP1V5_S0_MINI

AP_MINI_RESET_L

RSVD_MINI_BT_ACTIVE
AP_MINI_CLKREQ_L

SMB_MINI_SDA

PCIE_MINI_R2D_C_P

PCIE_MINI_D2R_P

SMB_MINI_SCL

MINI_RESET_L

MINI_CLKREQ_L

=PP3V3_S3_MINI_CONN

=PP3V3_S3_MINI

TP_USB_MININ

PCIE_MINI_R2D_C_N

TP_USB_MINIP

=SMB_MINI_SCL

=SMB_MINI_SDA

P3V3_S0_MINI_EN_G

AP_MINI_RESET_L

AP_MINI_CLKREQ_L

PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P

RSVD_MINI_WLAN_ACTIVE

=PP3V3_S3_MINI

AP_PWR_EN_FET

=PP3V3_S3_MINI

AP_PWR_EN_FET

PM_PGOOD_MINI

PP3V3_S3_MINI_CONN

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=3.3V

=PP12V_S5_PWRCTL

=PP3V3_S3_MINI_CONN

=PP3V3_S3_MINI_CONN

AP_WAKE_L

PCIE_WAKE_L

PCIE_MINI_D2R_N

=PP3V3_S3_MINI_CONN

=PP3V3_S3_MINI

PM_PGOOD_MINI

34 OF 110

11.1.0

051-8115

33 OF 98

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90

6

33

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6

33

33

6

33

33 97

95

6

64 73

33

33

33

6

33

33 97

www.vinafix.vn

IN
IN

IN

SCL

THRM_PAD

E0
E1
E2

VSS

SDA

VCC

WC*

G

D

S

G

D

S

TEST

RESET*

USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3

USBDM_DN4/PRT_DIS_M4
USBDP_DN4/PRT_DIS_P4

PRTPWR2/BC_EN2*

PRTPWR1/BC_EN1*

PRTPWR4/BC_EN4*

PRTPWR3/BC_EN3*

OCS2*

OCS1*

OSC3*
OSC4*

RBIAS

USBDP_UP

USBDM_UP

VBUS_DET

THRM_PAD

XTALIN/CLKIN
XTALOUT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

CRFILT

PLLFILT

VDD33

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

DEFAULT K23F ==>

SEL1 SEL0 DESCRIPTION

DEFAULT K23F ==>

0 0 Internal Default with Self powered Operation

1 1 EEPROM Supported

0 1 SMBUS Slave Config

0 0 All ports are Non removable
0 1 Port1 is non removable
1 0 Port 1 and 2 are non removable
1 1 Port1,2 and 3 are non Removable

USB HUB-1

1 0 Internal Default with Bus powered Operation

NON_REM1 NON_REM0 DESCRIPTION

BOM TABLE

21

Y3500

CRITICAL

5X3.2X1.4-SM

24.000M-60PPM-16PF

2

1

C3520

50V

5%
CERM

402

18PF

21

R3591

5%

1/16W

1M

MF-LF

402

2

1

C3519

18PF

402

5%
CERM

50V

2

1

C3534

402

0.1UF

X5R

16V

10%

2

1

R3599

402

100K

5%
1/16W
MF-LF

NOSTUFF

2

1

C3537

402

50V

5%
CERM

100PF

2

1

C3543

402

CERM

50V

100PF

5%

2

1

R3597

NOSTUFF

10K

5%
1/16W
MF-LF

402

2

1

C3539

16V
402

10%
X7R-CERM

0.1UF

2

1

C3545

10%

402

16V
X7R-CERM

0.1UF

2

1

C3546

16V
402

X7R-CERM

10%

0.1UF

2

1

C3547

0.1UF

10%
16V
X7R-CERM
402

2

1

C3525

402

X7R-CERM

10%
16V

0.1UF

2

1

C3523

0.1UF

16V
402

10%
X7R-CERM

2

1

C3524

X7R-CERM

0.1UF

16V

10%

402

2

1

C3528

16V
X7R-CERM

10%

402

0.1UF

2

1

C3536

0.01UF

10%
16V
CERM
402

2

1

C3542

10%
16V

402

0.01UF

CERM

2

1

C3529

0.01UF

10%

402

16V
CERM

2

1

C3526

10%
CERM

16V

0.01UF

402

20 92

20 92

34 35

21

R3500

12K

MF

1%

402

1/16W

2

1

C3518

20%

603

6.3V

10UF

X5R

21

L3559

0402

FERR-120-OHM-1.5A

2

1

R3598

MF-LF

1/16W

10K

5%

402

2

1

R3592

10K

5%

1/16W

402

MF-LF

2

1

R3594

5%
1/16W

402

MF-LF

10K

NOSTUFF

2

1

R3504

MF-LF

1/16W

10K

5%

402

2

1

R3550

MF-LF

5%

402

1/16W

10K

2

1

R3580

402

MF-LF

1/16W

5%

10K

2

1

R3581

MF-LF

1/16W

5%

402

10K

2

1

R3565

5%
MF-LF

402

1/16W

10K

2

1

R3566

MF-LF

5%

10K

402

1/16W

NOSTUFF

2

1

R3567

1/16W

5%
MF-LF

10K

402

2

1

R3501

5%

402

MF-LF

1/16W

10K

7

489

5

6

3

2

1

U3514

MLP8

NOSTUFF

CRITICAL

M24C02

21

R3755

1/16W

402

0

5%

MF-LF

2

1

R3741

MF-LF

5%
1/16W

402

10K

2

1

R3740

20K

1/16W

5%

402

MF-LF

2

1

C3741

5%

402

NOSTUFF

100PF

50V

CERM

4

5

3

Q3740

SOT-363

2N7002DW-X-G

21

R3745

MF-LF

0

1/16W

5%

402

1

2

6

Q3740

2N7002DW-X-G

SOT-363

2

1

C3740

CERM-X5R

0.47UF

10%

402

6.3V

NOSTUFF

2

1

C3530

1UF

402

X5R

16V

10%

2

1

C3527

402

X5R

1UF

16V

10%

2

1

C3538

20%

603

6.3V
X5R

10UF

2

1

C3544

603

6.3V

20%

10UF

X5R

21

L3558

0402

FERR-120-OHM-1.5A

32

33

3629231510

5

27

31

9

7

4

2

30

8

6

3

1

37

11

28

22

24

26

35

20

18

16

12

34

21

19

17

13

25

14

U3500

USB2514-AEZG

QFN

OMIT

CKPLUS_WAIVE=NDIFPR_BADTERM

2

HUB_USX2061

338S0721

CRITICAL

U3500,U3600

SMSC USX2061-AEZG

SYNC_DATE=01/06/2011

USB HUB 1

SYNC_MASTER=K62

SMSC USB2514B

338S0824

HUB_USB2514B

U3500,U3600

2

CRITICAL

USB_EXTA_OC_L

USB_HUB1_SMBDATA

USB_HUB1_UP_N
USB_HUB1_UP_P

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.25MM

USB_HUB1_VBUS_DET

USB_HUB1_RBIAS

USB_EXTC_OC_L

=PP3V3_S3_USB_HUB

TP_USB_HUB1_PRTPWR1

TP_USB_HUB1_OCS1_L

TP_USB_HUB1_PRTPWR4

TP_USB_HUB1_PRTPWR3

TP_USB_HUB1_OCS2_L

USB_SDCARD_P

USB_SDCARD_N

=PP3V3_S3_USB_HUB

USB_HUB_SOFT_RESET_L

USB_HUB1_VDDPLL3V3

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.25MM

=PP3V3_S3_USB_HUB

=PP3V3_S3_USB_HUB

USB_HUB1_LOCAL_PWR

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

USB_HUB1_VDD1V8

=PP3V3_S3_USB_HUB

USB_HUB1_XTAL1
USB_HUB1_XTAL2

USB_HUB1_CFG_SEL1

MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

USB_HUB1_VDD1V8PLL

USB_HUB_RESET_L

USB_EXTC_P

USB_IR_N
USB_IR_P

USB_EXTA_N
USB_EXTA_P

USB_EXTC_N

USB_HUB1_TEST

USB_HUB1_VDDA3V3

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

WP_HUB1

USB_HUB1_SMBCLK

=PP3V3_S3_USB_HUB

=PP3V3_S5_USB_HUB

USB_PON_RESET_L

USB_PON_RESET

PM_PGOOD_P3V3_S3_FET

USB_HUB_RESET_L

TP_USB_HUB1_PRTPWR2

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6

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6

34 35

95

6

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91

91

95

43 92

44 92

44 92

43 92

43 92

43 92

95

6

34 35

6

73 97

34
35

www.vinafix.vn

IN
IN

IN

SCL

THRM_PAD

E0
E1
E2

VSS

SDA

VCC

WC*

TEST

RESET*

USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3

USBDM_DN4/PRT_DIS_M4
USBDP_DN4/PRT_DIS_P4

PRTPWR2/BC_EN2*

PRTPWR1/BC_EN1*

PRTPWR4/BC_EN4*

PRTPWR3/BC_EN3*

OCS2*

OCS1*

OSC3*
OSC4*

RBIAS

USBDP_UP

USBDM_UP

VBUS_DET

THRM_PAD

XTALIN/CLKIN
XTALOUT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

CRFILT

PLLFILT

VDD33

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB HUB-2

21

1

Y3600

5X3.2X1.4-SM

CRITICAL

24.000M-60PPM-16PF

2

1

C3620

CERM

50V

5%

402

18PF

21

R3691

MF-LF

5%

1/16W

402

1M

2

1

C3619

CERM

50V

18PF

5%

402

2

1

C3637

402

CERM

5%
50V

100PF

2

1

C3643

50V

5%

402

CERM

100PF

2

1

C3639

16V
402

10%

0.1UF

X7R-CERM

2

1

C3645

X7R-CERM

16V

10%

0.1UF

402

2

1

C3646

402

0.1UF

10%
X7R-CERM

16V

2

1

C3647

402

16V

10%

0.1UF

X7R-CERM

2

1

C3625

10%

402

0.1UF

X7R-CERM

16V

2

1

C3623

16V

10%

402

0.1UF

X7R-CERM

2

1

C3624

402

10%
16V

0.1UF

X7R-CERM

2

1

C3628

0.1UF

X7R-CERM

10%

402

16V

2

1

C3636

CERM

16V

10%

402

0.01UF

2

1

C3642

0.01UF

402

16V

10%
CERM

2

1

C3629

16V
CERM
402

0.01UF

10%

2

1

C3626

10%
16V
CERM
402

0.01UF

20 92

20 92

34

2

1

C3618

20%

603

X5R

10UF

6.3V

2

1

R3697

NOSTUFF

MF-LF

402

10K

5%

1/16W

2

1

R3698

1/16W

10K

5%

402

MF-LF

2

1

R3699

5%

402

1/16W
MF-LF

100K

NOSTUFF

21

L3629

0402

FERR-120-OHM-1.5A

2

1

R3692

402

MF-LF

5%

10K

1/16W

2

1

R3694

10K

402

MF-LF

1/16W

5%

NOSTUFF

2

1

R3682

MF-LF

10K

1/16W

402

5%

2

1

R3680

402

1/16W

5%

MF-LF

10K

2

1

R3681

402

1/16W

5%

MF-LF

10K

2

1

R3666

10K

402

5%
MF-LF

1/16W

2

1

R3665

402

10K

MF-LF

1/16W

5%

NOSTUFF

2

1

R3667

1/16W
MF-LF
402

5%

10K

2

1

R3601

MF-LF

402

10K

5%

1/16W

2

1

R3604

1/16W
MF-LF

5%

10K

402

2

1

C3634

X5R
402

16V

10%

0.1UF

7

489

5

6

3

2

1

U3614

M24C02

NOSTUFF

MLP8

CRITICAL

2

1

R3660

402

1/16W

5%

MF-LF

10K

2

1

R3661

10K

MF-LF

5%

1/16W

402

2

1

C3630

402

X5R

16V

10%

1UF

2

1

C3627

10%

402

16V
X5R

1UF

2

1

C3638

603

6.3V

10UF

X5R

20%

2

1

C3644

20%

603

X5R

6.3V

10UF

21

L3658

0402

FERR-120-OHM-1.5A

21

R3600

1%

12K

MF

402

1/16W

32

33

3629231510

5

27

31

9

7

4

2

30

8

6

3

1

37

11

28

22

24

26

35

20

18

16

12

34

21

19

17

13

25

14

U3600

USB2514-AEZG

QFN

OMIT

CKPLUS_WAIVE=NDIFPR_BADTERM

SYNC_DATE=01/06/2011

USB HUB 2

SYNC_MASTER=K62

USB_HUB2_VBUS_DET

USB_EXTD_OC_L

USB_HUB2_RBIAS

USB_HUB2_UP_P

USB_EXTB_OC_L

TP_USB_HUB2_OCS2

=PP3V3_S3_USB_HUB

=PP3V3_S3_USB_HUB

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

USB_HUB2_VDDPLL3V3

USB_HUB2UNUSED_P

USB_HUB2UNUSED_N

USB_BT_P

=PP3V3_S3_USB_HUB

USB_HUB2_XTAL2

=PP3V3_S3_USB_HUB

USB_BT_N

USB_EXTD_N

USB_HUB2_UP_N

TP_USB_HUB2_PRTPWR2

TP_USB_HUB2_PRTPWR1

USB_EXTB_P

TP_USB_HUB2_OCS1

TP_USB_HUB2_PRTPWR4

TP_USB_HUB2_PRTPWR3

USB_EXTD_P

USB_HUB2_XTAL1

MIN_LINE_WIDTH=0.5MM

USB_HUB2_VDD1V8PLL

MIN_NECK_WIDTH=0.25MM

USB_HUB2_CFG_SEL1

USB_HUB_RESET_L

=PP3V3_S3_USB_HUB

WP_HUB2

USB_HUB2_SMBDATA

USB_HUB2_VDD1V8

MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

USB_HUB2_SMBCLK

USB_HUB2_LOCAL_PWR

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

USB_HUB2_VDDA3V3

=PP3V3_S3_USB_HUB

USB_EXTB_N

USB_HUB2_TEST

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43 92

43 92

91

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6

34 35

95

95

6

34 35

43 92

www.vinafix.vn

D

GS

IN

SGD

IN

OUT

IN

IN

OUT

IN

D

GS

G

D

S

G

D

S

IN

IN

OUT

IN

OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CAESAR IV SW RESET GATING

CAESAR IV CLKREQ ISOLATION

CAESAR IV WAKE# ISOLATION

CAESAR IV RESET CONNECTION

FROM PCH GPIO ->

3V3_ENET_PHY_FET = S0 || (S3 POWER && ENET_PWR_EN)

CAESAR IV POWER ENABLE CIRCUIT

CAESAR IV ACTIVITY LED

SILKSCREEN:ENET ACT

197S0177

CAESAR IV 1.2V INT.VR CMPTS

CAESAR IV 25MHZ XTAL

CAESAR IV STRAPS (NONE)

K

A

LED3800

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

2

1

R3815

402

MF-LF

1/16W

5%

330

DEVELOPMENT

2

1

3

Q3870

SSM3K15FV

SOD-VESM-HF

2

1

R3870

402

1/16W

10K

5%
MF-LF

21

L3800

PCAA031B-SM

4.7UH-0.8A

PLACEMENT_NOTE=PLACE L3800 CLOSE TO U3900

2

1

C3826

X5R

0.1UF

10%

402

16V

PLACEMENT_NOTE=PLACE CLOSE TO L3800

2

1

C3825

PLACEMENT_NOTE=PLACE CLOSE TO L3800

6.3V

20%

10UF

603-2

X5R

21

C3850

NOSTUFF

27pF

50V

5%

402

CERM

21

R3850

NOSTUFF

200

MF-LF

402

1/16W

1%

37 92

21

C3851

NOSTUFF

402

5%

27pF

50V

CERM

31

42

Y3850

NOSTUFF

25.0000M

SM-3.2X2.5MM

CRITICAL

2

1

R3851

NOSTUFF

1/16W

402

5%

MF-LF

10M

21

C3852

16V

X5R

10%

0.1UF

402

21

R3856

805

1/8W

0

5%

NOSTUFF

MF-LF

4

3

6521

Q3850

FDC606P_G

SOT-6

2

1

C3853

402

X7R-CERM

10%
16V

0.1UF

2

1

R3853

MF-LF
402

5%

10K

1/16W

NOSTUFF

21

R3852

1/16W

100K

402

MF-LF

5%

2

1

R3855

1/16W
402

5%
MF-LF

10K

20 25 97

21

R3801

402

MF-LF

1/16W

0

5%

2

1

C3827

0.1UF

10%
X5R

402

16V

2

1

C3828

0.1UF

10%
X5R

402

16V

2

1

C3829

0.1UF

10%
X5R

402

16V

2

1

C3830

0.1UF

X5R

10%
16V

402

2

1

C3831

0.1UF

10%
X5R

402

16V

21

R3854

NOSTUFF

1/16W

402

0

5%

MF-LF

37 92

21

R3857

PLACEMENT_NOTE=PLACE CLOSE TO U3900

1/16W

402

0

5%

MF-LF

79 96

36 91 37

37

2

1

R3872

402

1/16W

10K

5%
MF-LF

2

1

3

Q3872

SSM3K15FV

SOD-VESM-HF

1

2

6

Q3852

SOT-363

2N7002DW-X-G

4

5

3

Q3852

2N7002DW-X-G

SOT-363

21

R3802

402

MF-LF

5%

1/16W

0

5

4

1

2

3

U3880

SOT23-5-HF

MC74VHC1G08

27 97

15 21 91

2

1

C3880

20%
10V

402

CERM

0.1UF

36 91

37 19 33 78 97

15 18 91 37 91

21

R3829

MF-LF

5%

0

402

1/16W

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

CAESAR IV SUPPORT

ENET_PWR_EN_L

PM_SLP_S3_L

PM_SLP_S3_R3802_L

=PP3V3_S3_ENET_PHY_FET

ENET_CLK25M_XTALI

ENET_CLK25M_XTALO_R

ENET_CLK25M_XTALI_R

ENET_CLK25M_XTALI_OSC

ENET_CLK25M_XTALO

=PP3V3_S3_ENET_PHY_FET

MIN_LINE_WIDTH=1.0MM
VOLTAGE=1.2V

DIDT=TRUE

ENET_SR_LX

MIN_NECK_WIDTH=0.2MM

SWITCH_NODE=TRUE

MAKE_BASE=TRUE
MIN_LINE_WIDTH=1.0MM

PP1V2_S3_ENET_INTREG

MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V

=PP3V3_S3_ENET_PHY_FET

=PP3V3_S3_ENET_PHY_FET

ENET_ACT

VOLTAGE=3.3V

MAKE_BASE=TRUE

NET_SPACING_TYPE=SWITCHNODE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.0 MM

PP3V3_S3_ENET_PHY_FET

=PP3V3_S3_ENET_PHY

ENET_LED_ACT_L

MAKE_BASE=TRUE

ENET_TRAFFICLED_L

ENET_PWR_ENABLE_L

=PP1V2_S3_ENET_PHY

MIN_LINE_WIDTH=1.0MM

ENET_SR_VFB

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

ENET_PWR_EN

ENET_CLKREQ_FET_L

=ENET_WAKE_L

ENET_CLKREQ_L

ENET_PWR_EN_R

=PP3V3_S0_ENET_PHY

ENET_RESET_L

ENET_SW_RESET_L

ENET_RESET_LOGIC_L

ENET_RESET_LOGIC_R_L

ENET_RESET_LOGIC_L

ENET_WAKE_L

MAKE_BASE=TRUE

PCIE_WAKE_L

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6

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www.vinafix.vn

IN

IN

IN

OUT

IN

IN
OUT

OUT

OUT

IN

IN

BI

BI
BI

BI
BI
BI
BI
BI

NC

BI

BI
BI

OUT

IN

IN

IN

OUT

VDDC

SR_LX

PCIE_PLLVDDL

SR_VFB

SR_VDDP

SR_VDD

SCLK
SI/LINKLED*

CS*

SO

SPD100LED*/SERIAL_DO
TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

TRD2_P

TRD3_N

TRD3_P

GPIO_1/CR_BUS_PWR

GPIO_0

RE*/GPIO_2

VMAIN_PRSNT

PCIE_TXD_N
PCIE_TXD_P

PCIE_RXD_N

PCIE_RXD_P

PCIE_REFCLK_N

PCIE_REFCLK_P

PERST*

CLKREQ*

WAKE*

LOW_PWR

SD_DETECT/WE*

CR_CMD/CLE

CR_CLK/RY_BY*

CR_DATA0
CR_DATA1

CR_DATA3

CR_DATA2

CR_DATA4
CR_DATA5
CR_DATA6

CE*/MS_INS*

CR_DATA7

CR_LED/ALE

XD_DETECT

THRM_PAD

XTALI
XTALO

RDAC

GPHY_PLLVDDL

AVDDH

VDDO

XTALVDDH

BIASVDDH

AVDDL

SMD_DATA

SMB_CLK

CR_WP*/XD_WP*

OUT

IN

IN

OUT

IN

OUT

BI

BI
BI

IN

BI

BI

BI

BI
BI

IN

SI

WP*

SO

SCK

CS*

RESET*

VCC

GND

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PHY Non-Volatile Memory

ROM contains MAC address, PCIe config

Avoids need for EFI to program at startup.

Limiting

Current

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
the card reader on-chip I/O.

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

(IPD)

(IPD-ENETM)

(OD)

VDD for Card Reader I/O

(IPU-ENET)

If ENET switching regulator is

SD_DETECT can only be used active low due to errata.

Resistor

=ENET_WAKE_L to PCIE_WAKE_L.

WAKE#

(See note)

Must isolate from PCIe WAKE# if PHY

(See note)

ENET supports both active-levels for WP.

info as well as code for Bonjour proxy.

(Required ROM size 1 Mbit)

used, this pin can float (alias to
TP_). If not used, must be pulled
to 3.3V ENET via 1K resistor (not

Atmel AT45DB011D (1Mbit) ROM. If a different

(OD)

o

(IPU-ENET)

(OD)

(IPU-ENET)

(OD)

BCM requests SD CR[0:7], CMD, CLK termination.

ENET_SR_DISABLE

ENET_CR Signals

Internal 1.2V Switching Regulator pins.

(IPD-ENET)

other 3 SPI pins configures ENET for the

ROM is used then the straps must change.

NOTE: Pull-down on SO plus internal pull-ups on

NOTE: ENETM requires SI pull-down instead of SO.

Special Star routing needed on these pins. Decoupling on Pg 37.

(IPx-ENET)

provided on this page).

(IPU)

(IPD)

NOTE: "IPx" == Programmable pull-up/down

(IPD)

(IPU-ENET)

281mA (1000base-T max power, Caesar IV)

Connect only to U3900 pin 20.

Control signal to light LED or control SD bus power.

No MS (Memory Stick) Insert feature needed.

(IPU-ENET)

If PHY is always powered then alias

N-channel FET isolation suggested.

is powered-down in S3/S5. Standard

396mA (1000base-T, Caesar II)

MUST DO: REMOVE C/R3959 AFTER PROTO 2

ENET 1.2V SR IS ENABLED IF FLOATING.

(NO IPU OR IPD-ENET)

2

1

C3921

402

16V

10%

X7R-CERM

0.1UF

2

1

C3935

X5R

10%

805

6.3V

10UF

2

1

C3925

4.7UF

6.3V

10%

603

X5R-CERM

21

L3925

SM

FERR-600-OHM-0.5A

CRITICAL

2

1

C3920

10%

6.3V

603

X5R-CERM

4.7UF

21

L3920

SM

FERR-600-OHM-0.5A

CRITICAL

21

L3900

CRITICAL

SM

FERR-600-OHM-0.5A

21

L3905

FERR-600-OHM-0.5A

SM

CRITICAL

2

1

R3942

1K

MF-LF

1/16W

402

5%

18 90

18 90

36

36 91

15 21 97

36 92

36 92

21

C3951

10%
16V

402

0.1uF

X5R

21

C3950

0.1uF

16V

10%

X5R
402

21

C3956

0.1uF

402

X5R

10%
16V

21

C3955

0.1uF

10%
16V
X5R
402

2

1

R3965

MF-LF

1%

402

1/16W

1.24K

18 92

18 92

18 92

18 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

2

1

R3941

402

5%
1/16W
MF-LF

4.7K

2

1

R3940

1/16W

4.7K

5%

402

MF-LF

21

R3978

PLACEMENT_NOTE=PLACE R3978 NEAR U3900

402

5%

MF-LF1/16W

33

DEVELOPMENT

45 92

21

R3977

MF-LF

402

5%

1/16W

PLACEMENT_NOTE=PLACE R3977 NEAR U3900

33

DEVELOPMENT

21

R3976

PLACEMENT_NOTE=PLACE R3976 NEAR U3900

5%

1/16W MF-LF

402

33

DEVELOPMENT

21

R3975

1/16W MF-LF

5%

PLACEMENT_NOTE=PLACE R3975 NEAR U3900

402

33

DEVELOPMENT

45 92

45 92

45 92

21

R3961

MF-LF

5%

PLACEMENT_NOTE=PLACE R3979 NEAR U3900

1/16W

402

PLACEMENT_NOTE=PLACE NEAR U3900

33

DEVELOPMENT

21

R3960

402

0

5%

MF-LF1/16W

DEVELOPMENT

45

21

R3943

5%

MF-LF

1/16W

402

0

21

R3900

0

402

1/16W

5%

MF-LF

2

1

R3990

NOSTUFF

MF-LF

1/16W

5%

402

4.7K

45 92

45

2

1

C3970

603

X5R-CERM

6.3V

10%

4.7UF

DEVELOPMENT

2

1

C3971

16V
X7R-CERM

10%

402

0.1UF

DEVELOPMENT

2

1

C3972

16V

0.1UF

X7R-CERM

10%

402

DEVELOPMENT

15 18 92

2

1

R3910

1/16W

5%

4.7K

MF-LF

402

17

19

18

68

3

58

625620

7

61

35

50
49

46
47

44
43

40
41

67

69

13

151416

2

65

10

6

64

1

66

9

38

11

28

27

33
34

31
30

32

29

4

8

5

36

63

57

60

55

54

53

52

22

23

24

25

26

21

12

59

37

514539

48

42

U3900

QFN-8X8

OMIT

BCM57765

21

R3979

402

MF-LF1/16W

PLACEMENT_NOTE=PLACE R3961 NEAR U3900

33

5%

PLACEMENT_NOTE=PLACE NEAR U3900

DEVELOPMENT

21

R3980

1K

1/16W

5%

402

NOSTUFF

MF-LF

36

37

37

37

37

45

21

L3910

CRITICAL

SM

FERR-600-OHM-0.5A

37

37

37

37

45 92

21

R3971

PLACEMENT_NOTE=PLACE R3971 NEAR U3900

402

33

1/16W5%MF-LF

DEVELOPMENT

45 92

45 92

2

1

C3910

402

10%
16V
X7R-CERM

0.1UF

45 92

45 92

21

R3972

402

PLACEMENT_NOTE=PLACE R3972 NEAR U3900

33

5%

MF-LF1/16W

DEVELOPMENT

21

R3973

PLACEMENT_NOTE=PLACE R3973 NEAR U3900

5%

MF-LF33402

1/16W

DEVELOPMENT

21

R3974

PLACEMENT_NOTE=PLACE R3974 NEAR U3900

MF-LF1/16W

5%

33

402

DEVELOPMENT

21

R3901

MF-LF

5%

402

0

1/16W

2

1

R3992

MF-LF

1/16W

5%

402

4.7K

2

1

R3993

4.7K

402

5%
1/16W
MF-LF

21

R3904

0

1/16W
MF-LF

402

5%

21

R3981

5%

1/16W

402

1K

MF-LF

2

1

C3918

0.1UF

402

16V
X7R-CERM

10%

2

1

C3917

10%

402

16V
X7R-CERM

0.1UF

36

2

1

R3959

1/16W

402

5%

150

MF-LF

NOSTUFF

2

1

C3980

402

10%
X5R

16V

0.1UF

2

1

C3911

0.1UF

10%
16V
X7R-CERM
402

2

1

C3979

20%

6.3V
CERM

4.7UF

603

2

1

C3981

0.1UF

16V
X5R

10%

402

2

1

C3959

10PF

CERM

50V

5%

NOSTUFF

402

5

6

8

12

3

7

4

U3990

OMIT_TABLE

SOIC-8S1

AT45DB021D

2

1

C3990

0.1UF

X7R-CERM
402

16V

10%

2

1

C3900

0.1UF

16V
402

10%

X7R-CERM

2

1

C3905

10%

0.1UF

16V
X7R-CERM
402

2

1

C3930

4.7UF

10%

6.3V
X5R-CERM
603

2

1

C3931

16V

10%

0.1UF

402

X7R-CERM

21

L3930

SM

FERR-600-OHM-0.5A

CRITICAL

2

1

C3915

603

6.3V

4.7UF

10%

X5R-CERM

2

1

C3916

10%

402

16V
X7R-CERM

0.1UF

2

1

R3997

1/16W

4.7K

MF-LF
402

5%

2

1

C3936

X7R-CERM

0.1UF

10%

402

16V

2

1

C3926

16V

10%

X7R-CERM

0.1UF

402

ETHERNET PHY (CAESAR IV)

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

ENET_WAKE_R_L

ENET_LOW_PWR

ENET_SMB_CLK
ENET_SMB_DATA

ENET_MISO
ENET_MOSI
ENET_CS_L

TP_ENET_SPD100LED_L

PCIE_ENET_D2R_C_P

PCIE_ENET_R2D_P
PCIE_ENET_R2D_N

PCIE_CLK100M_ENET_P

ENET_VMAIN_PRSNT

=PP3V3_S3_ENET_PHY_FET

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP3V3R1V8_ENET_LR_OUT_REG

ENET_MEDIA_SENSE

ENET_SD_DETECT_L

PCIE_ENET_D2R_P

PCIE_CLK100M_ENET_N

ENET_RESET_LOGIC_R_L

ENETCONN_MDI_P<3>

PCIE_ENET_D2R_C_N

SDCONN_DETECT_L

SDCONN_CMD

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V2_S3_ENET_PHY_AVDDL

ENET_3V3_S3_SR_IN

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE
DIDT=TRUE

MIN_LINE_WIDTH=0.4 MM

NET_SPACING_TYPE=SWITCHNODE

NO_TEST=TRUE

NC_ENET_CE_L_MS_INS_L

ENET_CR_DATA<7>

ENET_CR_DATA<6>

ENET_CR_DATA<4>

ENET_CR_DATA<3>

ENET_CR_DATA<2>

ENET_CR_DATA<1>

ENET_CR_DATA<0>

SDCONN_DATA<0>
SDCONN_DATA<1>

SDCONN_DATA<3>

SDCONN_DATA<2>

ENET_CR_DATA<5>

SDCONN_DATA<4>

=PP3V3_S3_ENET_PHY_FET

=PP3V3R1V8_ENET_LR_OUT

=PP3V3R1V8_ENET_LR_OUT

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V2_S3_ENET_PHY_GPHYPLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_S3_ENET_PHY_AVDDH

PP1V2_S3_ENET_PHY_PCIEPLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

ENET_SR_VFB

ENETCONN_MDI_N<1>

ENET_SCLK

ENET_SR_LX

SDCONN_DATA<7>

SDCONN_DATA<6>

SDCONN_CLK

ENET_SD_CMD

ENET_CR_PWREN

ENET_SR_DISABLE

ENET_SCLK

ENET_TRAFFICLED_L

ENET_CLK25M_XTALI

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

=ENET_WAKE_L

ENET_CLKREQ_FET_L

ENETCONN_MDI_N<0>

SDCONN_DATA<5>

SDCONN_WP

ENETCONN_MDI_P<1>

ENETCONN_MDI_N<2>

ENETCONN_MDI_P<2>

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

ENET_XTALVDDH

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_S3_ENET_PHY_XTALVDDH

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

PP3V3_S3_ENET_PHY_BIASVDDH

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

ENETCONN_MDI_P<0>

ENETCONN_MDI_N<3>

PCIE_ENET_R2D_C_N

=PP1V2_S3_ENET_PHY

ENET_SD_CLK

=PP3V3_S0_ENET_PHY

ENET_CLK25M_XTALO

ENET_RDAC

=PP3V3_S3_ENET_PHY_FET

ENET_SRESET_L

ENET_CS_L

ENET_SCLK_R

ENET_MISO

ENET_SWP_L

ENET_MOSI

37 OF 98

051-8115

11.1.0

39 OF 110

92

92

92

36 37 79

95

92

92

95

95

92

92

92

92

92

92

92

92

36 37 79

37

37

95

95

95

36 95

36 95

92

95 95

95

36

92

6

36

92

36 37 79

www.vinafix.vn

TD4-

TCT4

TD4+

TD3-

TCT3

TD3+

TD2-

TD2+

TD1-

TCT2

TCT1

TD1+

MX4-

MX4+

MCT4

MX3-

MX3+

MCT3

MX2-

MX2+

MCT2

MX1-

MX1+

MCT1

1CT:1CT

1CT:1CT

1CT:1CT

1CT:1CT

ENET_MDI

TRAN_P0
TRAN_N0
TRAN_P1
TRAN_P2
TRAN_N2
TRAN_N1
TRAN_P3
TRAN_N3

PINS

SHIELD

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI

BI

BI

BI

BI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NO PAIR AND PIN POLARITY SWAPS

514-0767

NOTE: BOB SMITH TERMINATION FOR EMC.

NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps.

PLACE ONE CAP PER TCT PIN

157S0071

THIS PAGE DIFFERENT BETWEEN K60 and K62.

2

1

R4000

75

5%
MF-LF

1/16W
402

PLACE_NEAR=T4000.15:6 mm

2

1

R4001

MF-LF

75

5%
1/16W

402

PLACE_NEAR=T4000.18:6 mm

2

1

R4002

75

1/16W
MF-LF
402

5%

PLACE_NEAR=T4000.21:6 mm

2

1

R4003

MF-LF
402

1/16W

5%

75

PLACE_NEAR=T4000.24:6 mm

2

1

C4000

1206

10%

NOSTUFF

2KV

1000PF

CERM

2

1

C4001

CERM

10V

20%

402

0.1UF

2

1

C4002

CERM

10V

0.1UF

20%

402

2

1

C4003

10V
CERM

0.1UF

20%

402

2

1

C4004

CERM

10V

0.1UF

20%

402

11

12

8

9

5

6

2

3

10

7

4

1

14

13

17

16

20

19

23

22

15

18

21

24

T4000

CKPLUS_WAIVE=NDIFFPR_BADTERM

SOI

LFE9249APF

CRITICAL

CKPLUS_WAIVE=NDIFPR_BADTERM

CKPLUS_WAIVE=NDIFPR_BADTERM

CKPLUS_WAIVE=NDIFPR_BADTERM

CKPLUS_WAIVE=NDIFPR_BADTERM

7

4

3

1

8

5
6

2

9

10

J4000

CRITICAL

F-ANG-TH

RJ45-K60K62

38 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

37 92

37 92

37 92

37 92

37 92

37 92

37 92

37 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

SYNC_MASTER=K60_MARK

Ethernet Connector

SYNC_DATE=01/06/2011

ENETCONN_MDI_P<1>

ENETCONN_MDI_P<0>

ENETCONN_MDI_P<2>

ENETCONN_MCT2

ESD_HOT=TRUE

ENETCONN_MDI_T_P<3>

ENETCONN_MDI_T_P<0>

ENETCONN_MDI_T_P<1>
ENETCONN_MDI_T_P<2>
ENETCONN_MDI_T_N<2>

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_P<3>

ENETCONN_MDI_N<3>

ENETCONN_MDI_N<2>

MIN_LINE_WIDTH=0.4 MM

ENETCONN_MCT_BS

MIN_NECK_WIDTH=0.2 mm

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_N<1>
ENETCONN_MDI_T_P<3>

ENETCONN_MDI_N<0>

ENETCONN_MDI_T_P<2>

ESD_HOT=TRUE

ENETCONN_MCT3

ENETCONN_TCT

ENETCONN_MDI_N<1>

ENETCONN_MDI_T_N<3>

ESD_HOT=TRUE

ESD_HOT=TRUE

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_N<2>

ESD_HOT=TRUE

ENETCONN_MDI_T_P<0>

ESD_HOT=TRUE

ESD_HOT=TRUE

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_P<1>

ESD_HOT=TRUE

ENETCONN_MCT0

ENETCONN_MCT1

40 OF 110

11.1.0

051-8115

38 OF 98

www.vinafix.vn

DS2

ATBUSH
ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N
TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620*
JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK
SCIFDAIN
SCIFDOUT

SCIFMC

SCL
SDA

SE
SM

TDO

TPA1N

TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P

TPBIAS0
TPBIAS1
TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC
NC
NC

NC

IN
IN

IN

IN

OUT

OUT

OUT

OUT

IN
IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI

IN

NC

NC

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Per LSI, R4162 and C4162 can be NOSTUFF ->

NT-1 (IPU)

(IPD) NT-21

(IPU)

NT-9

APN: 338S0753 ->

NT-2 (IPU)

NT-12 (IPD)

NT-10 (IPD)

NT-16 (IPD)

FIXME!!! - TYPO IN SYMBOL REGCTL

FIXME!!! - TYPO IN SYMBOL VAUX_ENABLE

NT-13

NT-5

NOTE: NT-xx notes show
NAND tree order.

114 mA FireWire PHY

17 mA PCIe SerDes

NT-3 (IPU)

NT-4 (IPU)

(IPU)

(IPD)

(Reserved)

NT-14 (IPD)

NT-6

NT-7

(OD)

135 mA

25 mA PCIe SerDes

0 mA VReg PWR

7 mA I/O

(IPD)

(IPD)

(IPU) NT-8

110 mA Digital Core

138 mA

NT-OUT

NT-17

NT-15 (IPD)

(IPD) NT-18

(IPD) NT-11

(IPD) NT-19
(IPD) NT-20

External power-on reset (IPU 100K):

K18 has 0.475-ohm upstream of L4110

2

1

R4170

402

MF-LF

1/16W

1%

191

2

1

C4162

10%

402

6.3V

0.33UF

CERM-X5R

2

1

R4162

402

5%
1/16W
MF-LF

470K

F13

G13

C2

F6F4E9E5E4

D10

K10

K6L7K9

K8D9K7K5K4

J10

J9J5J4

H10

H8

H7D7H6

H4

G10

G8G7G6

G4

F10

F8

F7

D4

B2

L12

K12

L9

L6

L10

L5

D8D6D5

A12

M2

L11L3J1

G12F1C12

C1

L1K2H12H2E10E2C13

B12

N11

N3

M12

B1

A1

H13

D2

E1

N1

B10

A2

C3

B7

A4

B4

A6

B6

A9

B9

A3

B3

A5

B5

A8

B8

M3

M1

N2

M4

N13

M13

M11

N12

F2

H1

G1

G2

L8

D13

N10

N9

B11

N4

N6

N5

N7

N8

J13

J12

K1

J2

D1

K13

D12

E13

E12

F12

L2

L13

A10

A11

A13

B13

U4100

FW643

OMIT

CRITICAL

BGA

21

C4151

22PF

50V
402

5%

CERM

21

C4150

50V

CERM

5%

402

22PF

2

1

R4160

402

PLACEMENT_NOTE=Place close to U4100.B10

MF-LF

1/16W

1%

200K

21

R4150

MF-LF

412

1%

1/16W

402

2

1

R4163

402

1/16W
MF-LF

10K

5%

2

1

R4164

5%
1/16W
MF-LF

10K

402

2

1

R4165

402

10K

MF-LF

5%

1/16W

NOSTUFF

21

C4176

16V

X5R 402

0.1UF

10%

PLACEMENT_NOTE=PLACE C4176 CLOSE TO U4100

21

C4175

402

16V

0.1UF

10%

PLACEMENT_NOTE=PLACE C4175 CLOSE TO U4100

X5R

2

1

R4166

MF-LF

1/16W

10K

5%

402

21

C4171

PLACEMENT_NOTE=Place C4171 close to U1800

16V

X5R 402

0.1UF

10%

21

C4170

X5R 402

PLACEMENT_NOTE=Place C4170 close to U1800

16V

0.1UF

10%

2

1

C4130

402

CERM

6.3V

10%

1UF

2

1

C4131

10%

1UF

6.3V
CERM

402

2

1

C4100

CERM

1UF

6.3V

402

10%

2

1

C4101

10%

1UF

402

6.3V
CERM

2

1

C4132

10%

1UF

402

6.3V
CERM

2

1

C4102

10%

1UF

402

CERM

6.3V
2

1

C4103

10%

1UF

402

6.3V
CERM

2

1

C4135

10%

1UF

6.3V
CERM

402

2

1

C4136

10%

1UF

402

6.3V
CERM

2

1

C4104

402

10%

6.3V
CERM

1UF

2

1

C4110

10%

1UF

402

6.3V
CERM

2

1

C4105

10%

1UF

402

6.3V
CERM

2

1

C4106

1UF

402

6.3V
CERM

10%

2

1

C4120

10%

1UF

402

6.3V
CERM

2

1

C4121

10%

1UF

402

6.3V
CERM

2

1

C4122

10%

402

6.3V
CERM

1UF

2

1

C4123

10%

1UF

402

6.3V
CERM

2

1

C4124

1UF

402

6.3V
CERM

10%

2

1

C4141

402

10V

CERM

0.1UF

20%

2

1

C4111

10%

1UF

402

6.3V
CERM

2

1

C4140

402

10%

1UF

6.3V
CERM

18 90

18 90

18 90

18 90

18 90

18 90

15 21 97

15 97

2

1

R4161

1/16W

402

2.94K

1%

MF-LF

40

40

40

40

40

40 92

40 92

40 92

40 92

40

40

40 92

40 92

40 92

40 92

40

40

40

21

L4130

0402-LF

120-OHM-0.3A-EMI

21

L4135

0402-LF

120-OHM-0.3A-EMI

27 97

21

L4110

120-OHM-0.3A-EMI

0402-LF

3 1

4 2

Y4150

CRITICAL

24.576MHZ

SM-3.2X2.5MM

SYNC_MASTER=K60_ROSITA

SYNC_DATE=01/06/2011

FireWire LLC/PHY (FW643)

FW_CLK24P576M_XO

=PP1V0_S0_FWPHY

FW_CLK24P576M_XI

TP_FW643_TCK

FW643_REXT

TP_FW643_NAND_TREE

TP_FW643_CE
TP_FW643_FW620_L

TP_FW643_SM

FW643_OCR10_CTL

PCIE_FW_D2R_P

=PP3V3_S0_FWPHY

FW_PHY_DS2

TP_FW643_SE

TP_FW643_MODE_A

FW_P0_TPB_N

FW_P1_TPB_N
FW_P1_TPB_P

FW_PHY_DS1

TP_FW643_VBUF

FW_P2_TPBIAS

FW_P0_TPBIAS

FW_P2_TPB_P

FW643_PU_RST_L

TP_FW643_SCIFDOUT

PCIE_FW_R2D_N

FW_P2_TPA_N

FW_P1_TPA_P

FW643_TRST_L

PCIE_FW_D2R_N

TP_FW643_TMS

TP_FW643_AVREG

TP_FW643_JASI_EN

TP_FW643_SDA

FW_P2_TPA_P

FW_P0_TPA_N

TP_FW643_TDO

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

PCIE_FW_D2R_C_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_FW_FWPHY_VP25

FW_P0_TPB_P

FW_CLK24P576M_XO_R

FW_P1_TPA_N

TP_FW643_SCIFDAIN

TP_FW643_SCIFCLK

FW643_REGCTL

FW_CLKREQ_L

TP_FW643_VAUX_ENABLE

PCIE_FW_R2D_P

TP_FW643_TDI

FW_RESET_L

FW643_SCL

TP_FW643_SCIFMC

FW_PME_L

FW_P0_TPA_P

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_FWPHY_AVDD

VOLTAGE=1.0V

PCIE_FW_D2R_C_P

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VDDA

MIN_LINE_WIDTH=0.4 MM

FW643_VAUX_DETECT

PPVP_FW_PHY_CPS

FW_PHY_DS0

=PP3V3_S0_FWPHY

FW_P2_TPB_N

FW643_TPCPS

FW643_R0

FW_P1_TPBIAS

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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

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B

8 7 5 4 2 1

1394 PHY DATA/STROBE OPTIONS

2ND & 3RD TPA/TPB PAIR UNUSED

NOTE: AGERE’S RECOMMENDATION FOR UNUSED PORTS

THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE, FW643
HAS INTERNAL 100K PULL-DOWNS, ONLY PULL-UPS NECESSARY.

Place close to FireWire PHY

Termination

NOTE: Q4200 COLLECTOR CONNECT TO CAPS WITH 0.4 SQ-IN HEAT SINK

NOTE: MULTIPLE VIAS TO DGND

FW643 1.0V GENERATION

2

1

R4255

402

10K

MF-LF

5%
1/16W

NOSTUFF

3 4

2

1

Q4200

SOT223-4

CRITICAL

BCP6916DG

2

1

C4213

CERM

10UF

20%

805-1

6.3V

2

1

C4211

10V

20%

402

CERM

0.1UF

21

R4200

1/16W

75

5%

MF-LF

402

2

1

C4200

CERM

6.3V

2.2UF

402-LF

20%

2

1

C4201

402-LF

6.3V
CERM

2.2UF

20%

2

1

C4212

805-1

20%
CERM

6.3V

10UF

2

1

C4210

0.1UF

20%

402

CERM

10V

2

1

R4256

402

MF-LF

1/16W

5%

10K

2

1

R4257

10K

1/16W

5%

402

MF-LF

2

1

C4250

402

10%
CERM-X5R

6.3V

0.33UF

2

1

R4251

56.2

1%

402

MF-LF

1/16W

2

1

R4250

1%

MF-LF

402

1/16W

56.2

2

1

R4253

SIGNAL_MODEL=EMPTY

56.2

MF-LF
402

1/16W

1%

2

1

R4252

SIGNAL_MODEL=EMPTY

1%

1/16W

56.2

MF-LF

402

2

1

R4254

MF-LF

1/16W

1%

4.99K

402

2

1

C4254

5%

402

220PF

CERM

25V

2

1

R4258

1/16W

5%
MF-LF

402

10K

FireWire: 1394B MISC

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

NET_SPACING_TYPE=POWER

PP1V0_S0_FW_VDD
MAX_NECK_LENGTH=3MM

VOLTAGE=1.0V

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.1MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.25MM

NET_SPACING_TYPE=SWITCHNODE

FW643_OCR10_CTL

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.25MM

NET_SPACING_TYPE=SWITCHNODE

FW_OCR10_CTL_R

FW_P0_TPB_N

VOLTAGE=1.86V

MIN_NECK_WIDTH=0.08MM

MIN_LINE_WIDTH=0.1MM

FW_P0_TPBIAS

FW_PORT0_TPB_P

MAKE_BASE=TRUE

FW_PHY_DS0

FW_PHY_DS1

FW_PHY_DS2

FW_P0_TPA_P
FW_P0_TPA_N

MAKE_BASE=TRUE

FW_PORT0_TPB_N

FW_PORT0_TPA_N

MAKE_BASE=TRUE

FW_PORT0_TPA_P

MAKE_BASE=TRUE

FW_P0_TPA_C

=PP3V3_S0_FWPHY

=PP3V3_S0_FWPHY

FW_P0_TPB_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW_PORT1_TPBIASFW_P1_TPBIAS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW_PORT1_TPA_P

FW_P1_TPA_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW_PORT1_TPA_N

FW_P1_TPA_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW_PORT1_TPB_P

FW_P1_TPB_P

FW_P1_TPB_N

FW_P2_TPBIAS

NC_FW_PORT2_TPA_P

NO_TEST=TRUE

MAKE_BASE=TRUE

FW_P2_TPA_P

NC_FW_PORT2_TPA_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW_PORT2_TPB_P

MAKE_BASE=TRUE

NO_TEST=TRUE

FW_P2_TPB_P

NC_FW_PORT2_TPB_N

NO_TEST=TRUE

MAKE_BASE=TRUE

FW_P2_TPB_N

=PP1V0_S0_FWPHY

FW_P2_TPA_N

NC_FW_PORT2_TPBIAS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW_PORT1_TPB_N

NO_TEST=TRUE

MAKE_BASE=TRUE

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39

39

39 92

39 92

39 92

39 92

39

39 92

39 92

39 92

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V+

GND

SHIELD

PINS

VG

TPA-

TPA(R)

TPB-

TPB(R)

TPB+ VP

TPA+

SC/NC

VCC

VCLMP

D1-

GND

D2-

D2+

D1+

FWPWR_EN

OUT

OUT

IN

IN

BI

BI

BI

BI

IN

G

S

D

BI
BI

BI
BI

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

POUR COPPER TO SINK HEAT

FAST NON-RESETABLE FUSE
THIS FUSE WILL NOT BLOW

beta-only device, there is no DC path

BREF should be hard-connected to logic
ground for speed signaling and connection

When a billingual device is connected to a

AREF needs to be isolated from all

SHOULD BE DONE AS A POWER STRIP(SUBPLANE)

ACTIVE "LATE VG" + ESD PROTECTION

12 VOLTS

PLACE CLOSE TO COMPARATOR

1394B

PORT 0

5.1V

PLACE CLOSE TO COMPARATOR

5.1V
NC

NC

INRUSH RESETABLE PTC

POUR COPPER TO SINK HEAT

14 WATTS MAX PER PORT

IT IS HERE FOR SAFETY ONLY

between them (to avoid ground offset issue)

local grounds per 1394b spec

514-0769

21

L4300

CRITICAL

FERR-250-OHM

SM

2

1

C4332

50V

CERM

402

10%

0.001UF

NOSTUFF

2

1

C4335

0.1UF

X7R

50V
603-1

10%

2

1

R4335

402

1%

MF-LF

1/16W

1M

2

1

C4300

X7R
603-1

50V

10%

0.01UF

3

1

D4301

SOT23

MMBZ5231BXG

21

F4301

SMD030F-SM

0.3AMP-60V

CRITICAL

4

3

6521

Q4300

CRITICAL

SSOT6

FDC610PZ

21

R4300

MF

1W

5%

0.33

2512

2

3

1

Q4301

SOT23

60V-600MA

MMBT2907AXG

21

R4352

402

MF-LF

1/16W

51.1K

1%

21

D4300

CRITICAL

SM

CRS08-1.5A-30V

2

1

R4303

MF-LF

1/16W

5%

20K

402

2

1

R4302

15K

603

5%
MF-LF

1/10W

2

1

R4307

MF-LF

1/16W
402

5%

20K

2

1

C4302

0.01UF

16V

CERM

20%

402

2

1

R4301

10K

MF-LF

5%

402

1/16W

2

3

1

Q4302

SOT23

MMBT2222A7F

31

D4302

BAS40XG

SOT23

2

1

C4304

402

16V

10%

0.1UF

X7R-CERM

8

1

7

3

5

2

6

4

U4300

LM393

SOI-HF

21

R4304

5%

1/16W

100K

MF-LF

402

2

1

R4306

402

5%
MF-LF

1/16W

200K

2

1

C4305

16V

10%

603

2.2UF

X5R

3 1

D4303

MMBZ5231BXG

SOT23

21

R4305

MF-LF

1/16W

100K

402

5%

21

F4300

603

3AMP-32V

CRITICAL

21

XW4300

PLACEMENT_NOTE=PLACE CLOSE TO F4300

SM

8

6

9
2

1

5
4

3

7

11

10

J4300

FWB-PL-K60-K62

CRITICAL

F-ANG-TH

3

1

2

4

6
5

8
7

U4350

PLACEMENT_NOTE=PLACE U4350 CLOSE TO J4300

CRITICAL

LLP

TPD4S1394

2

1

C4350

10%
16V

X7R-CERM

402

0.1UF

41

41

41

41

40 41 92

40 41 92

40 41 92

40 41 92

41

4

3

6521

Q4350

SSOT6

CRITICAL

FDC610PZ

2

1

3

Q4351

SOT23-HF1

2N7002

2

1

R4350

100K

402

5%
MF-LF

NOSTUFF

1/16W

40 41 92

40 41 92

40 41 92

40 41 92

2

1

R4351

5%

402

1/16W
MF-LF

1K

2

1

C4351

0.001UF

NOSTUFF

402

50V

CERM

20%

2

1

R4355

1K

402

MF-LF

1/16W

5%

39 95

3

1

D4305

SOT23

MMBD914XG

NOSTUFF

FIREWIRE CONNECTOR

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

NO_TEST=TRUE

FW_PORT0_TPA_P

FW_TURN_ON_V

FW_CURRENT_LIMIT

FWPWR_ON_L

FW_PORT0_TPA_R

=PP12V_S0_FW

FW_CURRENT_LIMIT

FWPWR_EN_L

MIN_NECK_WIDTH=0.5MM

P12V_FW_R

MIN_LINE_WIDTH=1.7MM
VOLTAGE=12V

=PP12V_S0_FW

FW_FET_LINEAR_LIMIT_OUT

TP_FW_LATEVG_VCLMP

FW_PORT0_TPB_P

NO_TEST=TRUE

FW_FET_LINEAR_LIMIT_FB

MIN_NECK_WIDTH=0.5MM

MIN_LINE_WIDTH=1.7MM

FW_PORT0_VP

VOLTAGE=12V

FW_CURRENT_LIMIT_RD

FW_PORT0_VP_F

MIN_LINE_WIDTH=1.7MM
VOLTAGE=12V

MIN_NECK_WIDTH=0.5MM

FW_PORT0_TPB_P

FW_PORT0_TPA_P

=PP3V3_S0_FWPHY

FW_CURRENT_LIMIT_Q

FW_FET_LINEAR_LIMIT_IN

FW_FET_LINEAR_LIMIT_OUT

FW_FET_LINEAR_LIMIT_IN

FW_CURRENT_LIMIT_R

VOLTAGE=12V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PPVP_FW_PHY_CPS

MIN_LINE_WIDTH=1.7MM
VOLTAGE=12V

MIN_NECK_WIDTH=0.5MM

P12V_FW_D

VOLTAGE=12V

MIN_NECK_WIDTH=0.5MM

MIN_LINE_WIDTH=1.7MM

P12V_FW_CL

PP12V_S0_VG_OK

MIN_LINE_WIDTH=1.7MM
VOLTAGE=12V

MIN_NECK_WIDTH=0.5MM

FW_PORT0_TPB_N

FW_PORT0_TPA_N

FWPWR_EN

NO_TEST=TRUE

FW_PORT0_TPA_N

NO_TEST=TRUE

FW_PORT0_TPB_N

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IN

IN

OUT

OUT

IN

IN

OUT

OUT

G

D

S

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

NC

G

S

D

NC

NC

IN

IN

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SILKSCREEN:SATA1

SATA PORT A1 FOR SSD/ODD

ODD PWR CONTROL

SATA PORT A0 FOR HDD

K60E should stuff S_P1_ODD:YES because it has no SSD option.

ODD X

BOMOPTION OPTIONS FOR SATA PORT A1 AND A2

5V 1.4A/0.8A/ 0.032A

518S0812

SILKSCREEN:SATA0

SSD ODD X

518S0813

SSD Power

HDD Power

518S0792

12V 1.2Amp

518S0251

5V 1.7Amp

518S0251

518S0251

353S2499

On= 2-5V

SATA Activity LED

SATA PORT A2 FOR ODD

A1 A2 ODD_SATA:P1 ODD_SATA:P2

SILKSCREEN:SATA2

USE OF PORT A2 FOR SSD IS NOT INTENDED VIA BOMOPTION THOUGH MLB SUPPORTS IT.

7

6

5

4

3

2

1

J4510

CRITICAL

EP00-081-91

M-ST-SM

18 90

18 90

18 90

18 90

21

C4530

SSD

10%

0.01UF

CERM

16V 402

21

C4531

SSD

10% 402

0.01UF

CERM

16V

21

C4532

SSD

402

CERM

0.01UF

16V10%

21

C4533

SSD

40210%

CERM

0.01UF

16V

7

6

5

4

3

2

1

J4530

SSD

M-ST-SM

EP00-081-91

CRITICAL

2

1

R4503

100K

5%

402

MF-LF

1/16W

21

R4550

5%

805

0

NOSTUFF

1/8W

MF-LF

18 90

18 90

18 90

18 90

21

C4520

0.01UF

402

CERM

10% 16V

ODD_SATA:P2

21

C4521

0.01UF

10% 16V 402

CERM

ODD_SATA:P2

21

C4523

CERM

16V 402

0.01UF

10%

ODD_SATA:P2

21

C4522

16V

CERM

402

0.01UF

10%

ODD_SATA:P2

7

6

5

4

3

2

1

J4520

EP00-081-91

M-ST-SM

CRITICAL

ODD_SATA:P2

5

4

3

2

1

J4521

50293-0057N-001

M-ST-SM

CRITICAL

321

4

5

Q4500

CRITICAL

FDMC8298

MLP3.3X3.3

1

9

6

8

2

4

7

5

Q4501

CRITICAL

TDFN

SLG5AP001

2

1

C4500

0.1UF

10%
16V
X5R
402

2

1

C4517

20%

10UF

603

X5R

10V

2

1

C4537

SSD

10UF

10V

20%

603

X5R

2

1

C4527

10V
X5R
603

10UF

20%

2

1

C4518

25V
X5R

10%

10UF

1206-1

4

3

2

1

J4531

SSD

50293-00471-H01

M-ST-SM

CRITICAL

21

L4511

FERR-220-OHM

0402

2

1

R4520

33K

1/16W
MF-LF

402

5%

21

R4501

5%

1/16W

0

402

MF-LF

2

1

3

Q4502

SOT23-HF1

2N7002

2

1

C4525

1UF

10%
X5R

402

10V

7

6

5

4

3

2

1

J4511

50293-00771-H01

M-ST-SM

CRITICAL

21

C4510

16V

0.01UF

10% 402

CERM

21

C4511

10% 16V

0.01UF

402

CERM

21

C4515

40210%

0.01UF

16V

CERM

21

C4516

CERM

0.01UF

16V 40210%

18 90

18 90

18 90

18 90

2

1

R4599

1/10W

DEVELOPMENT

5%

330

603

MF-LF

K

A

DS4599

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

SILK_PART=SATA ACTIVE

SYNC_DATE=01/06/2011

SYNC_MASTER=K60_JERRY

SATA Connectors

SATA_ODD_R2D_P

SATA_HDD_D2R_C_N

SATA_SSD_R2D_P

SATA_HDD_D2R_C_P

SATA_SSD_R2D_C_N

SATA_SSD_D2R_C_P

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

SATA_SSD_R2D_N

=PP5V_S0_SATA

HDD_OOB_TEMP_FB

SMC_ODD_DETECT

ODD_PWR_GATE

ODD_PWR_EN_LD

ODD_PWR_EN_L

SATA_HDD_D2R_N

SATA_HDD_R2D_P

SATA_ODD_R2D_C_N

PCH_SATALED_L

MAKE_BASE=TRUE

SATALED_L

SATALED_R_L

=PP3V3_S0_SATALED

HDD_OOB_TEMP_FILT

SATA_HDD_R2D_N

=PP5V_S0_SATA

NET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=POWER

=PP12V_S0_SATA

ODD_PWR_EN_L_R

=PP12V_S0_SATA

SATA_HDD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_SSD_D2R_C_N

SATA_HDD_D2R_P

=PP3V3_S0_ODD

NET_PHYSICAL_TYPE=POWER

VOLTAGE=5V

PP5V_S0_SATA_FET

SATA_SSD_D2R_P

SATA_SSD_D2R_N

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_R2D_N

=PP5V_S0_SATA

SATA_SSD_R2D_C_P

SATA_HDD_R2D_C_P

45 OF 110

11.1.0

051-8115

42 OF 98

3

90

90

90

90

90

90

90

90

6

42

94

46 98

15 21 97

90

18

6

18

51 94 98

90

6

42

6

42

6

42

90

6

95

90

6

42

www.vinafix.vn

IOIONC

GND

VBUS

NC

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

VCC

GND

SELOE*

D+
D-

Y+
Y-

M+
M-

GND

THRM

OUT2

OUT1

ILIM

IN_0
IN_1

EN2

FAULT1*
FAULT2*

EN1

PAD

GND

THRM

OUT2

OUT1

ILIM

IN_0
IN_1

EN2

FAULT1*
FAULT2*

EN1

PAD

VBUS
DATA-

GND

DATA+

VBUS
DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

VBUS
DATA-

GND

DATA+

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ADDED AT EVT & SWITCH TO S5 RAIL

USB/SMC DEBUG MUX

Current Limit at 2.1Amp (@ S3 & S0)

USB PORT POWER:

SOFTWARE WILL ALOW 500MA/PORT, PLUS 2700MA EXTRA POWER TO BE

WHEN CURRENT HITS LIMIT, TPS2561 BECOME CONSTANT CURRENT MODE

STATE MAX MIN ( WITHIN THE TOLERANCE)

PORT 0

514-0770

Place R4600 very close to ILIM pin

(PUT CAP ON CONNECTOR SIDE)

Place R4620 very close to ILIM pin

PORT 1

514-0768

514-0768

514-0770

155S0329

SEL=1: CHOOSE USB

155S0329

155S0329

PORT 2

PORT 3

SEL=0: CHOOSE SMC

(PUT CAP ON CONNECTOR SIDE)

TOTAL: 4700MA

EACH PORT IS HARDWARE Capable of :

PORT 4 - USB 2.0 500MA = 500MA

Port 3 - iPhone fast charging = 1000mA

Port 2 - Wired Keyboard = 1100mA

EXAMPLE: Port 1 - iPad fast charging = 2100mA

distributed to approved devices on a 1st-come, 1st-served basis.

AND STAY AT THE LIMIT LEVEL UNTIL THERMAL SHUTDOWN WHEN JUNCTION REACH 130C

S0, S3 2.7A 2.1A -- PER PORT

155S0329

2

1

C4650

MOJOMUX:YES

20%
10V

402

CERM

0.1UF

21

R4651

MOJOMUX:NO

MF-LF

1/16W

402

0

5%

21

R4652

MOJOMUX:NO

1/16W

5%

402

MF-LF

0

2

1

C4622

330UF

CRITICAL

6.3V
POLY-TANT

20%

CASE-D3L-SM

2

1

C4601

0.1UF

20%

CERM

10V
402

2

1

C4621

402

0.1UF

10V

20%

CERM

2

1

C4623

402

20%
10V

0.1UF

CERM

2

1

C4603

CERM

10V

20%

402

0.1UF

6

45

1

D4630

CRITICAL

RCLAMP0502N

SLP1210N6

2

1

C4602

POLY-TANT

330UF

20%

6.3V

CRITICAL

CASE-D3L-SM

2

1

C4624

402

CERM

20%
16V

0.01uF

4 3

21

L4601

CRITICAL

120-OHM-90MA

DLP0NS

4 3

21

L4611

CRITICAL

120-OHM-90MA

DLP0NS

4 3

21

L4621

120-OHM-90MA

DLP0NS

CRITICAL

4 3

21

L4631

DLP0NS

CRITICAL

120-OHM-90MA

1
2

9

10

8

5
4

3

7
6

U4650

MOJOMUX:YES

PI3USB102ZLE

CRITICAL

TQFN

2

1

C4633

20%

CERM

10V
402

0.1UF

2

1

C4600

20%

0.01uF

CERM
402

16V

2

1

C4660

402

CERM

16V

0.01uF

20%

2

1

C4661

CERM

10V

20%

0.1UF

402

2

1

C4630

16V

0.01uF

20%

402

CERM

2

1

R4600

23.2K

MF-LF

402

1/16W

1%

2

1

R4620

1/16W

1%

23.2K

MF-LF

402

11

8

9

3

2

7

1

6

10

5

4

U4600

CRITICAL

SON

TPS2561DR

11

8

9

3

2

7

1

6

10

5

4

U4620

TPS2561DR

CRITICAL

SON

21

L4630

FERR-220-OHM-2.5A

0603

CRITICAL

21

L4660

0603

FERR-220-OHM-2.5A

CRITICAL

21

L4600

FERR-220-OHM-2.5A

0603

CRITICAL

21

L4620

0603

FERR-220-OHM-2.5A

CRITICAL

1

6

5

4

3

2

J4630

F-ANG-TH

USB-K60K62

1

6

5

4

3

2

J4620

USB-K60K62

F-ANG-TH

1

6

5

4

3

2

J4610

USB-MG6-K60-K62

F-ANG-TH

1

6

5

4

3

2

J4600

USB-MG6-K60-K62

F-ANG-TH

21

R4654

MOJOMUX:YES

MF-LF

1/16W

5%

0

402

21

R4653

NOSTUFF

MF-LF

1/16W

402

0

5%

6

45

1

D4620

CRITICAL

RCLAMP0502N

SLP1210N6

6

45

1

D4610

CRITICAL

RCLAMP0502N

SLP1210N6

6

45

1

D4600

SLP1210N6

RCLAMP0502N

CRITICAL

EXTERNAL USB CONNECTORS

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

PM_EN_USB_PWR

USB_DEBUGPRT_EN_L

USB_D_MUXED_N

USB_D_MUXED_P

USB_EXTB_N

=PP5V_S3_USB

USB_EXTD_OC_L

ILIM_IN1

USB_EXTC_OC_L

USB_EXTA_OC_L
USB_EXTB_OC_L

=PP5V_S3_USB

ILIM_IN2

USB_EXTD_P

SMC_TX_L

USB_EXTC_N
USB_EXTC_P

USB_EXTA_N
USB_EXTA_P

USB_EXTB_P

SMC_RX_L

MIN_LINE_WIDTH=0.6MM

PP5V_USB_PORT3

VOLTAGE=5V
MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MM

PP5V_USB_PORT0

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

USB_EXTD_N

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

PP5V_USB_PORT1

VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

PP5V_USB_PORT0_F

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

PP5V_USB_PORT2_F

USB_PORT0_N
USB_PORT0_P

USB_PORT2_N

USB_PORT2_P

USB_PORT3_N

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

PP5V_USB_PORT1_F

USB_PORT1_N
USB_PORT1_P

USB_PORT3_P

PP5V_USB_PORT2

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_USB_PORT3_F

MIN_LINE_WIDTH=0.6MM

PP3V3_SMCUSBMUX

=PP3V3_S5_SMCUSBMUX

=PP3V3_G3H_SMCUSBMUX

46 OF 110

11.1.0

051-8115

43 OF 98

2 3

2 3

2 3

2 3

63 91

46 47

92

92

35 92

6

43

35

34

34

35

6

43

35 92

46 47 48

34 92
34 92

34 92

34 92

35 92

46 47 48

95

95

35 92

95

95

95

92

92

92

92

92

95

92

92

92

95

95

95

6

6

www.vinafix.vn

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CAMERA/ALS & BLUETOOTH (K37A) CONNECTOR

SD Card Reader Board ( Lazarus )

Skin Temp sense at upper Left Screen corner

IR RECEIVER CONNECTOR

518S0667

518S0785

518S0751

4 3

21

L4702

IR

120-OHM-90MA

CRITICAL

DLP0NS

4

3

2

1

6

5

J4780

IR

M-RT-SM

CRITICAL

53261-8604

4 3

21

L4701

120-OHM-90MA

DLP0NS

CRITICAL

2

1

C4701

402

0.1UF

20%
10V

CERM

4 3

21

L4720

BT

DLP0NS

120-OHM-90MA

CRITICAL

2

1

C4721

BT

20%
CERM

10V
402

0.1UF

2

1

C4720

BT

CERM

10UF

20%

6.3V
805-1

9

8

7

6

5

4

3

2

13

12

11

10

1

15

14

J4700

CRITICAL

50224-01311-001

M-RT-SM

21

L4703

IR

CRITICAL

220-OHM-1.4A

0603

21

L4721

BT

0603

220-OHM-1.4A

CRITICAL

21

L4700

CRITICAL

220-OHM-1.4A

0603

2

1

C4700

20%

10UF

805

X5R

10V

2

1

C4781

IR

603

X5R

1UF

10%
16V

2

1

C4750

10%

1UF

6.3V
CERM

402

21

R4750

402

MF-LF

10K

1%

1/16W

4 3

21

L4750

CRITICAL

120-OHM-90MA

DLP0NS

21

L4751

FERR-250-OHM

SM

CRITICAL

1

2

6

Q4710

SOT-363

2N7002DW-X-G

2

1

R4751

402

10K

1%
1/16W
MF-LF

4

5

3

Q4710

2N7002DW-X-G

SOT-363

6

5

4

3

2

1

8

7

J4750

F-RT-SM

CRITICAL

SM06B-SRKS-G-TB-HF

SYNC_MASTER=K62

Internal USB Connections

SYNC_DATE=01/06/2011

SDCARD_RESET_L

USB_SDCARD_L_N
USB_SDCARD_L_P

PP3V3_S3_SDCARD_FLT

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM

VOLTAGE=3.3V

=SMB_ALS_SCL

USB_CAMERA_N

USB_CAMERA_P

USB_CAMERA_L_P

USB_BT_P

USB_BT_N

NET_PHYSICAL_TYPE=POWER

=PP5V_S3_CAMERA

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S3_CAMERA_FLT

MIN_LINE_WIDTH=0.6MM

PP5V_S3_IR_FLT

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM

USB_IR_L_P

USB_BT_L_N

=SMB_ALS_SDA

VOLTAGE=3.3V

PP3V3_S3_BT_FLT

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

SNS_SKIN_LEFT_N

SNS_SKIN_LEFT_P

NET_PHYSICAL_TYPE=POWER

=PP3V3_S3_BT

USB_SDCARD_N
USB_SDCARD_P

NET_PHYSICAL_TYPE=POWER

=PP3V3_S3_SDCARD

SDCARD_RESET

SDCARD_PLT_RST_R_L

SDCARD_PLT_RST_L

USB_IR_L_N

=PP5V_S3_IR

NET_PHYSICAL_TYPE=POWER

USB_IR_P

USB_IR_N

USB_CAMERA_L_N

USB_BT_L_P

47 OF 110

11.1.0

051-8115

44 OF 98

97

92

92

95

49

20 92

20 92

92 98

35 92

35 92

6

95

95 98

92 98

92 98

49

95

52 94 98

52 94 98

6

34 92

34 92

6

45

15 21 97 98

27 97

92 98

6

34 92

34 92

92 98

92 98

www.vinafix.vn

OUT

BI

BI

OUT

BI

BI

BI

BI

BI

BI

OC*

OUT2

OUT1

OUT0

THRM

GND

EN

IN1

IN0

PAD

NC

G

S

D

IN

OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SDCONN DETECT DEBOUNCE, INVERSION, AND DETECT-CHANGED PCH GPIO CIRCUIT

GENERATE A 1 PULSE ON

SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE

-> FROM SD CONN

Vil = 0.8V

Vih = 2.0V

NC

X

-> TO ENET CHIP

CARD INSERT OR REMOVAL

-> TO PCH GPIO

SD CARD CONNECTOR

(CARD INSERTED = OPEN)

353S0004

MAKES THE ACTIVE-HIGH CASE UNUSABLE.

SD SPEC REQUIRES 47 UF
CAPACITANCE ON 3.3V INPUT.
22 + 10 + 10 + 2.2 (FLEX)

CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG

998-3513

TPS2065-1 (1.0A LIMIT) HAS ACTIVE LOAD DISCHARGE SO R4800 IS NOSTUFF.

37 92

37 92

37 92

37

37 92

37 92

37 92

37 92

37 92

37 92

9

8

7

6

5

3

2

1

4

U4800

TPS2065-1

DGN

CRITICAL

DEVELOPMENT

2

1

C4802

DEVELOPMENT

6.3V

20%

603

10UF

X5R

2

1

C4803

0.1UF

DEVELOPMENT

16V

10%

402

X7R-CERM

2

1

R4800

NOSTUFF

47K

1/16W
MF-LF
402

5%

2

1

C4800

20%

603

6.3V
X5R

10UF

DEVELOPMENT

2

1

C4801

X7R-CERM

16V

10%

402

0.1UF

DEVELOPMENT

21

R4802

0

1/16W

402

MF-LF

5%

DEVELOPMENT

2

1

R4801

10K

5%

402

1/16W
MF-LF

DEVELOPMENT

6

4

2

1

3

U4810

DEVELOPMENT

SOT891

74LVC1G86GF

2

1

R4810

10K

5%

402

1/16W
MF-LF

DEVELOPMENT

21

R4812

DEVELOPMENT

MF-LF

1/16W

402

5%

33K

2

1

C4810

DEVELOPMENT

10V

10%

402-1

1UF

X5R

2

1

C4812

0.1UF

402

20%

CERM

10V

DEVELOPMENT

21

R4811

DEVELOPMENT

SDCONN_DETECT_SHORT_DLY

1/16W
MF-LF

402

5%

33K

2

1

C4811

DEVELOPMENT

20%

0.1UF

402

CERM

10V

2

1

3

Q4810

2N7002

SOT23-HF1

NOSTUFF

45 20 25 97

37

21

R4814

DEVELOPMENT

0

MF-LF

1/16W

5%

402

2

1

C4805

805-3

CERM-X5R

6.3V

20%

22UF

DEVELOPMENT

9

8

7

6

5

4

3

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

27

28

J4800

F-RT-SM

50671-02641

CRITICAL

DEVELOPMENT

21

L4800

DEVELOPMENT

FERR-10-OHM-500MA

SM

37 92

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

SD READER CONNECTOR

=PP3V3_S0_SDCARD

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_S0_SW_SD_PWR

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=PP3V3_S0_PCH_GPIO

ENET_CR_PWREN

SDCONN_OC_L_R

TP_SDCONN_OC_L

=PP3V3_S0_SW_SD_PWR

SDCONN_DATA<5>

SDCONN_DATA<4>

SDCONN_DATA<2>

SDCONN_DATA<3>

=PP3V3_S0_SW_SD_PWR

SDCONN_CMD

SDCONN_DATA<6>

SDCONN_WP
SDCONN_DATA<7>

SDCONN_DATA<0>

SDCONN_DETECT

SDCONN_CLK_L

SDCONN_DATA<1>

=PP3V3_S3_SDCARD

SDCONN_DETECT_LONG_DLY

SDCONN_DETECT

SDCONN_STATE_CHANGE

SDCONN_DETECT_L

SDCONN_DETECT_PULSE

SDCONN_CLK

48 OF 110

11.1.0

051-8115

45 OF 98

5

6

95

6

20

37

45

45

45

6

44

www.vinafix.vn

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN
IN
IN
IN
IN
IN
IN
IN

IN

OUT

IN

BI

IN

IN

OUT

OUT

IN

IN

IN

OUT
OUT

IN

IN

IN
IN

IN

IN

IN
IN

IN

IN

IN

IN

OUT

IN

BI

BI
BI
BI
BI
BI

OUT
OUT

IN

IN

OUT

IN

IN

BI

OUT

IN

OUT

OUT

OUT

OUT

OUT

NC

NC
NC

NC
NC
NC

NC

NC

NC

IN

OUT

NC

OUT

BI

IN

OUT

ININ

IN

OUT

NC
NC

NC

IN

NC
NC

IN

NC

NC

NC
NC

NC

NC

NC

P82
P83

P35

P97

P96

P95

P94

P93

P92

P91

P90

P86

P85

P84

P81

P80

P77

P76

P75

P74

P73

P72

P71

P70

P67

P65

P64

P63

P62

P61

P60

P52

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

P37

P36

P34

P33

P32

P31

P30

P27

P26

P25

P24

P23

P22

P21

P20

P17

P11

P10

P66P16

P15

P14

P13

P12

(1 OF 4)

PE1*
PE2*
PE3*
PE4*

PC0
PC1

PB7

PB6

PB5

PB4

PB3

PA5

PA4

PA0
PA1
PA2
PA3

PA6
PA7

PB0
PB1
PB2

PC2
PC3
PC4
PC5
PC6
PC7

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

PE0

PF0

PF1
PF2
PF3
PF4
PF5
PF6
PF7

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

PH0
PH1
PH2
PH3
PH4
PH5

(2 OF 4)

ETRST*

EXTAL

RES*

XTAL

NMI

VSS

VCLVCC

MD2

MD1

AVSS

AVREF

AVCC

(3 OF 4)

PI6
PI7

PI4
PI5

PI1
PI2
PI3

PJ7

PI0

PJ5
PJ6

PJ2
PJ3
PJ4

PJ0
PJ1

VSS

VCC3

AVSS1

AVCC1

AVREF1

NC

(4 OF 4)

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

OUT

IN

NC

NC

NC

OUT

NC

NC

NC

NC

IN

NC

OUT

BI
BI
BI
BI

IN
IN
IN

BI

IN

IN

BI

BI

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

338S0878

K62 PROTO-2:NEW

K62 NEW:NOT USE

K62 NEW:NOT USE

Peak/Ave/Standby= 2mA/1mA/5uA

K62 NEW:NOT USE,PULLED UP

K62 NEW:NOT USE,PULLED UP

(OC)

(OC)

K62 NEW:NOT USE

(IMON)

(OC)

(OC)

(IMON)

(OC)

(OC)

(OC)

SMS Interrupt can be active high or low, rename net accordingly.

If SMS interrupt is not used, pull up to SMC rail.

SMC PG1:

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

SMC_IG_THROTTLE_L for MG systems.

SMC PB3:

those designated as inputs require pull-ups.

Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA

Peak/Ave/Standby = 2mA/1mA/5uA

(OC)

(OC)

(OC)

PEVSTP

NOTE: Unused pins have "SMC_Pxx" names. Unused

PEVref

(OC)

(OC)

(OC)

(IMON)

pins designed as outputs can be left floating,

K60 New Change
K60 New Change

PECI

(IMON)

(OC)

(OC)

(IMON)

(IMON)

K62 P1 NOT USED, WAS OOB_TEMP

K62 NEW:NOT USE,PULLED UP

K62 NEW:NOT USE,PULLED UP

(See below)

(OC)

(OC)

PROTO-3, Change back to WAKE_SCI_L

PROTO-3:back to K75F

2

1

C4902

805

22UF

CERM

20%

6.3V

19 48 97

47 48 97

47 97

2

1

C4907

PLACEMENT_NOTE=Place C4907 close to U4900 pin 13

402

CERM-X5R

0.47UF

6.3V

10%

2

1

C4903

402

10V

0.1UF

CERM

20%

2

1

C4920

10V
402

0.1UF

CERM

20%

PLACEMENT_NOTE=Place C4920 close to U4900 pin 76

21

R4999

4.7

1/16W
MF-LF

402

5%

PLACEMENT_NOTE=Place R4999 close to U4900 pin 76

2

1

C4904

10V

402

CERM

20%

0.1UF

2 1

XW4900

SM

19 25 97

47

2

1

C4905

10V

402

CERM

20%

0.1UF

27 97

64 97

64 97

47

2

1

C4906

20%
CERM

0.1UF

10V

402

50 94

50 94

50 94

50 94

50 94

50 94

50 94

50 94

47

43 46 47 48

43 46 47 48

49

2

1

R4909

5%

10K

1/16W
MF-LF

402

48

48

2

1

R4901

10K

MF-LF

5%
1/16W

402

2

1

R4902

402

10K

5%

MF-LF

1/16W

2

1

R4903

402

1/16W

5%

MF-LF

0

NOSTUFF

2

1

R4998

10K

1/16W
MF-LF
402

5%

43 47

15 19 97

42 98

51 94

53

53

53

53

50 94

50 94

50 94

50 94

50 94

50 94

50 94

47 48

47

47 48

47 48

47 48

49

49

49

49

49

49

47 97

47

50 94

43 46 47 48

43 46 47 48

47

47

18 48

19 25 27 97

48

15 18
21 97

15 19 48 97

47

47

19 47 97

47

47

18 97

47

47

47

47 47

5

19 47 63

97

74 97

5

19 32 47

63 97

47

G2

H1

H2

J4

J3

J1

J2

K4

B6

A6

C6

D6

B7

A7

C7

P15

N13

R15

P14

R14

P13

R13

N12

J13

J12

K14

K13

K12

L15

L14

L13

F2

G4

G1

C1

D3

C2

B1

C3

D5

B5

A5

D7

A8

C8

D8

B9

A9

C9

D9

F14

E13

E15

E14

E12

D15

D14

D13

C15

D12

C14

B15

B14

A15

C13

B12

U4900

LFBGA

OMIT

H8S2117

B3

D4

C4

K2

F3

E1

R7

P7

M8

R8

P8

N9

R9

P9

N5

P5

R5

M6

N6

R6

P6

M7

L2

L4

M1

M2

M3

M10

N10

R10

P10

N11

R11

P11

M11

H12

H13

H15

H14

G12

G13

G15

G14

D11

A12

C11

B11

A11

D10

A10

B10

N1

M4

N2

R1

N3

R2

P3

R3

U4900

OMIT

LFBGA

H8S2117

A2

A4

B13

F12

P4

D2

F1

J15

P1

A1

E3

F4

K1

E2

B2

L1

R12

M14

N14

U4900

H8S2117

OMIT

LFBGA

D1

B4

A13

F13

R4

P2

K15

J14

F15

A14

C12

C10

B8

C5

G3

H4

H3

K3

L3

M5

N7

N8

A3

L12

M13

M12

M9

N4

E4

P12

M15

N15

U4900

OMIT

LFBGA

H8S2117

2

1

C4910

0.1UF

10V

20%
CERM

402

21

R4911

0

402

1/16W

5%

MF-LF

21

R4910

1/16W

5%0402

MF-LF

21

R4912

MF-LF 1/16W

5%

402

0

54

54

21 47 97

47

83 97

18 48 91

18 48 91

18 48 91

18 48 91

18 48 91

27 97

27 91

49

5

19 26 32 36 47 63 82 97

9

91 97

49

49

47 97

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

SMC

LPC_CLK33M_SMC

SMC_SMS_INT
SMB_BSA_DATA

SMC_FAN_0_CTL

SMC_PE0

SMC_PB6

SMC_PB3

SMC_HDD_OOB_TEMP

PM_BATLOW_L

MEM_EVENT_B_L

MEM_EVENT_A_L

USB_DEBUGPRT_EN_L

PM_SYSRST_L

PM_PECI_PWRGD_R

PVCCIO_S0_SMC_R

CPU_PECI_R

SMC_THRMTRIP

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_CLK

SMB_A_S3_DATA

SMC_DIMM_VSENSE

SMC_DIMM_ISENSE

SMC_GPU_VSENSE

SMC_GPU_ISENSE

SMC_PCH_1V05_VSENSE

SMC_PCH_1V05_ISENSE

SMC_1V05_VSENSE

SMC_1V05_ISENSE

SMC_FAN_3_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SYS_ONEWIRE

SMC_GFX_OVERTEMP_L

SMC_FAN_1_CTL

SMC_RESET_L

GND_SMC_AVSS

SMC_MD1

SMC_XTAL

SMC_TRST_L

SMC_NMI

SMC_KBC_MDE

GND_SMC_AVSS

PP3V3_G3H_AVREF_SMC

PP3V3_G3H_AVREF_SMC

=PP3V3_G3H_SMC

MIN_NECK_WIDTH=0.20 MM

PP3V3_G3H_SMC_AVCC

VOLTAGE=3.4V

MIN_LINE_WIDTH=0.25 MM

=PP3V3_G3H_SMC

SMC_EXTAL

PP3V3_G3H_SMC_AVCC

PM_PECI_PWRGD

=PPVCCIO_S0_SMC

CPU_PECI

SMC_PA0

SPI_DESCRIPTOR_OVERRIDE_L

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

ALL_SYS_PWRGD_SMC
RSMRST_PWRGD

PM_RSMRST_L
CPUIMVP_VR_ON

SMC_PROCHOT_3_3_L

SMC_EXCARD_PWR_EN
SMC_RSTGATE_L

PM_PWRBTN_L

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L

LPC_SERIRQ

SMB_MGMT_DATA
SMS_ONOFF_L

SMC_GFX_THROTTLE_L

SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK

SMC_PM_G2_EN

SMC_ADAPTER_EN

SMC_BIL_BUTTON_L

SMC_VCORE_ISENSE
SMC_VCORE_VSENSE
SMC_CPU_1V5_ISENSE
SMC_CPU_1V5_VSENSE
SMC_VCCSA_ISENSE
SMC_VCCSA_VSENSE
SMC_VAXG_ISENSE
SMC_VAXG_VSENSE

SMC_WAKE_SCI_L

SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK

SMC_ONOFF_L
SMC_BC_ACOK

PM_SLP_S3_L

PM_CLK32K_SUSCLK
SMB_0_S0_DATA

SMC_LRESET_L

LPC_PWRDWN_L

PM_CLKRUN_L

PM_SLP_S4_L

PM_SLP_S5_L

SMC_LID

SMC_SYS_LED

G3_POWERON_L

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

BDV_BKL_PWM

SMC_VCL

SMB_BSA_CLK

49 OF 110

11.1.0

051-8115

46 OF 98

97

97

46 47 50 94

47 94

46 47 50 94

46 47 95

46 47 95

6

46 47

46 95

6

46 47

47 94

46 95

64 97

6

47

11 21 97

47

www.vinafix.vn

G

D

S

IN

OUT

G

D

S

OUT

IN

IN

G

D

S

G

D

S

IN

OUT

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

IN

BI

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

UNUSED PORT 7 ANALOG SENSORS

MISC. SIGNAL ALIASES

SMC Reset "Button", Supervisor & AVREF Supply

UNUSED TP/NC ALIASES

MEM_EVENT

518S0665

(IPU)

NC
NC

POWER BUTTON

FROM DIMMS

TO/FROM SMC

TO SMC

To PCH

FROM MXM

FROM SMC

FROM CPU

TO SMC

SMC PROCHOT 3.3V LEVEL SHIFTING

Can be driven by VREG or CPU

FROM SMC

(IPU)

MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.

NOTE: Internal pull-ups are to VIN, not V+.

SMC Crystal Circuit

SMC & MXM THERMTRIP LEVEL SHIFTING

4

5

3

Q5095

SOT-363

2N7002DW-X-G

21

R5020

402

5%

MF-LF1/16W

10K

21

R5021

1/16W

10K

402

5%

MF-LF

21

R5022

MF-LF5%402

1/16W

100K

21

R5023

2.0K

402

5%

MF-LF1/16W

21

R5024

5%

402

1/16W MF-LF

10K

21

R5025

10K

5%

402

1/16W MF-LF

21

R5026

10K

5%

MF-LF

402

1/16W

21

R5027

402

1/16W MF-LF

5%

10K

21

R5041

MF-LF1/16W

5%

402

100K

46 97

2

1

C5014

CERM

0.1UF

402

10V

20%

21

R5012

402

1/16W
MF-LF

5%

1K

1

6

2

Q5077

SOT-363-LF

MMDT3904-X-G

21

R5094

402

5%
1/16W
MF-LF

3.3K

4

3

5

Q5077

MMDT3904-X-G

SOT-363-LF

2

1

R5077

3.3K

5%

MF-LF

402

1/16W

2

1

R5078

402

1/16W
MF-LF

5%

470

46 97

21

R5042

100K

5%

402

MF-LF1/16W

21

R5028

10K

5%

1/16W

402

MF-LF

21

R5029

10K

5%

1/16W

402

MF-LF

21

R5030

402

MF-LF1/16W

5%

10K

21

R5031

402

MF-LF1/16W

5%

10K

1

2

6

Q5095

SOT-363

2N7002DW-X-G

21 97

46

76

21

R5095

402

0

MF-LF

1/16W

5%

21

R5035

10K

5%

1/16W MF-LF

402

1

2

6

Q5096

SOT-363

2N7002DW-X-G

4

5

3

Q5096

2N7002DW-X-G

SOT-363

2

1

R5096

1/16W
MF-LF
402

5%

3.3K

2

1

R5097

10K

5%
1/16W
MF-LF

402

2

1

4

3

J5010

CRITICAL

M-RT-SM

53261-8602

SILK_PART=PWR BTN

2

1

R5040

10K

1/16W
MF-LF

5%

402

30 31

21

R5034

402

MF-LF1/16W

5%

10K

43

21

S5000

SM

NTC020-CC1J-B260T

SILK_PART=SMC RESET

DEVELOPMENT

43

21

S5010

DEVELOPMENT

SILK_PART=SYS POWER

NTC020-CC1J-B260T

SM

21

R5043

100K

402

MF-LF

5%

1/16W

46 48 97

2

1

R5010

MF-LF

1K

1/16W

5%

402

2

1

C5013

10%
CERM

0.01UF

402

16V

2

1

C5012

X5R

10uF

6.3V

603

20%

3

1

9

5

8

7

6

2

4

U5010

VREF-3.3V-VDET-3.0V

DFN

2

1

C5010

CERM-X5R

0.47UF

402

6.3V

10%

2

1

C5011

10%

402

0.01UF

16V

CERM

I581

2

1

R5086

3.3K

5%

402

MF-LF

1/16W

11 97

21

R5088

0

402

5%

MF-LF

1/16W

2

1

R5087

402

MF-LF

1/16W

5%

51

1

6

2

Q5086

MMDT3904-X-G

SOT-363-LF

4

3

5

Q5086

C_THRMTRP1

MMDT3904-X-G

SOT-363-LF

21

R5085

3.3K

MF-LF

1/16W

5%

402

21

R5032

5%

10K

402

MF-LF1/16W

21

R5033

5%

MF-LF1/16W

402

10K

11 65 97

21

R5037

MF-LF

402

1/16W

5%

100K

21

R5038

100K

402

MF-LF

5%

1/16W

21

R5036

402

MF-LF

5%

1/16W

100K

2

1

Y5020

5X3.2-SM

CRITICAL

20.00MHZ

21

C5020

15PF

5%

50V

CERM

402

21

C5021

15PF

5%

50V

CERM

402

21

R5044

402

MF-LF1/16W

5%

10K

46 47 97

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

SMC Support

SMC_PB6

SMC_LID

SMC_PA0

SMC_PE0

MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

SMC_GFX_OVERTEMP_L

SMC_EXTAL

SMC_XTAL

MAKE_BASE=TRUE

TP_SMC_PB3

SMC_RX_L
SYS_ONEWIRE

G3_POWERON_L

SMC_GFX_OVERTEMP_L

SMC_ONOFF_L

SMC_PROCHOT

CPU_PROCHOT_L

CPU_PROCHOT_BUF

=PP3V3_S0_SMC_LS

CPRCHOT_R

CPU_THRMTRIP_L

MXM_OVERT_L

C_THRMTRP_L

MXM_THRMTRIP_L

C_THRMTRP

MXM_THRMTRIP

=PP3V3_S0_SMC_LS

PM_THRMTRIP_L

SMC_THRMTRIP

=PP3V3_S0_SMC_LS

=PPVCCIO_S0_SMC

SMC_TDI

SMC_TDO

SMC_TMS

TP_SMC_SYS_LED

MAKE_BASE=TRUE

SMS_ONOFF_L

SMC_EXCARD_PWR_EN

SMC_SYS_LED

SMC_PB3

SMC_RSTGATE_L

MEM_EVENT_B_L

MEM_EVENT_A_L

MAKE_BASE=TRUE

MEM_EVENT_L

=PPSPD_S0_MEM_A

SMC_ONOFF_L

POWER_BUTTON_L

SMC_RESET_L

SMC_MANUAL_RST_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

TP_SMS_ONOFF_L

MAKE_BASE=TRUE

SMC_PROCHOT_3_3_L

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

SMC_ADAPTER_EN

SMC_TCK

SMC_BC_ACOK

USB_DEBUGPRT_EN_L

SMC_SMS_INT

SMC_TX_L

SMC_BIL_BUTTON_L

CPUIMVP_VR_ON

SMC_GFX_THROTTLE_L

MXM_ALERT_L

MAKE_BASE=TRUE

MXM_PWR_LEVEL

MAKE_BASE=TRUE

SMC_DELAYED_PWRGD

MAKE_BASE=TRUE

=PP3V3_S0_SMC_LS

SMC_RUNTIME_SCI_L

=PP3V3_G3H_SMC

=PP3V3_G3H_SMC

PP3V3_G3H_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

50 OF 110

11.1.0

051-8115

47 OF 98

46

46

46

46

46 50 94

46 47

46 94

46 94

43 46 48

46

46

46 47

46 47 97

6

47 51

6

47 51

6

47 51

6

46

46 48

46 48

46 48

46

46

46

46

46

46

46

6

30

97

97

5

19 32 46 63 97

5

19 46 63 97

5

19 26 32 36 46 63 82 97

19 46 97

46 48

46

43 46

46

43 46 48

46

46

46

76

76

64 97

6

47 51

21 46 97

6

46 47

6

46 47

46 95

www.vinafix.vn

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Alternate SPI ROM Support

LPC+SPI Connector

Pull-up on debug card

516S0573

FRANK CONNECTOR

SPI Bus Series Resistance Option

2

1

C5144

LPCPLUS:YES

CERM
402

20%
10V

0.1UF

21

R5145

MF-LF

LPCPLUS:YES

1/16W

0

5%

402

PLACEMENT_NOTE=Place near U1800

18 91

43 46 47

46

46 47

46

27 97

46 47

15 19 46 97

48 91

18 46 91

18 46 91

48 91

18 46 91

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J5100

LPCPLUS:YES

M-ST-SM

CRITICAL

55909-0374

21

43 46 47

46

46 47 97

46 47

46 47

19 46 97

18 46

48 91

48 91

21 48 91

18 46 91

18 46 91

27 91

18 55 91

21

R5156

LPCPLUS:YES

402

5%

MF-LF

1/16W

PLACEMENT_NOTE=Place next to R6150

33

48 91

18 55 91

21

R5157

LPCPLUS:YES

PLACEMENT_NOTE=Place next to R6152

402

MF-LF

5%

1/16W

33

48 91

18 55 91

21

R5158

LPCPLUS:YES

1/16W

5%

MF-LF

402

PLACEMENT_NOTE=Place next to R6105

33

48 91

2

1

R5140

100K

1/16W

5%

402

MF-LF

48 91

55 91

5

6

2

1

3 4

U5100

LPCPLUS:YES

PATH=I96

CRITICAL

SC70

NC7SB3157P6XG

2

1

R5144

1/16W

5%

MF-LF

402

20K

21

R5146

LPCPLUS:NO

402

0

MF-LF

PLACEMENT_NOTE=PLACE NEXT TO U5100

1/16W

5%

SYNC_DATE=11/30/2009

LPC+SPI Debug Connector

SYNC_MASTER=K62_AARON

SPI_MLB_CS_L

SPI_ALT_CLK

SPI_MISO

SPI_MOSI_R

SPI_ALT_MISO

SPI_ALT_MOSI

SPI_CLK_R

=PP3V3_S5_ROM

=PP5V_S0_LPCPLUS

=PP3V3_G3H_LPCPLUS

LPC_CLK33M_LPCPLUS

LPC_AD<3>

SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L

LPC_SERIRQ

SMC_TDI

SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO

SPI_CS0_L

LPC_AD<1>

LPC_AD<0>

SPI_ALT_MOSI
SPI_ALT_MISO

DEBUG_RESET_L

SMC_TMS

SMC_TDO

SMC_MD1
SMC_TX_L

SPI_ALT_CS_L

SMC_TCK

LPC_PWRDWN_L

PM_CLKRUN_L

LPC_FRAME_L

SPI_CS0_R_L

LPC_AD<2>

SMC_TRST_L

=PP3V3_S5_LPCPLUS

=PP3V3_S5_LPCPLUS

SPIROM_USE_MLB

MAKE_BASE=TRUE

51 OF 110

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6

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www.vinafix.vn

OUT

BI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

U9700

NOTE: O2Micro BLC HAS NO PU.

T29 I2C CONNECTIONS

T29 IC

(MASTER)

AC/DC PS POWER

INA219: ACDC THRU J600

(WRITE: 0X80, READ: 0X81)

SMC "0" SMBUS CONNECTIONS

USES INTERNAL SMC CONTROLLER CHANNEL 0 ONLY

BLC MICRO

AND EDID ROM.

(WRITE: 0X9E READ: 0X9F)

SMC

(DIMM3: WRITE: 0XA6 READ: 0XA7)

NOTE: SPTX BLC HAS 4.7K PU.

NOTE: DISPLAY TCON HAS 4.7K PU.

DISPLAY TCON TO SPTX OR O2M BLC

U4900

THIS PAGE DIFFERENT BETWEEN K60 AND K62.

MEMORY A DIMMS

PCH "SMBUS" CONNECTIONS

DISPLAY TCON

PCH "SML 0" CONNECTIONS

USES INTERNAL SMC CONTROLLER CHANNEL 1 ONLY

(SLAVE)

PARADE ON TCON BOARD VIA J9002

(TBD WRITE: 0X1A READ: 0X1B)

(TO READ VENDOR ID

DISPLAY TCON

(WRITE: 0X5C READ: 0X5D)

MASTER BUS TO LUT ROM

U9330

WHEN USB POWER (VBUS) IS VALID.

T29 PORT A MCU

(WRITE: 0X86 READ: 0X89)

PCH "SML 1" CONNECTIONS

DP SDRV "A"

THE PCH address is user programmable by SPI ROM

(WRITE: 0X6E READ: 0X6F)

SPTX BLC MICRO

PCH (FOR TEMP)

EMC1402 ON AMD MXM CARD (WRITE: 0X98 READ: 0X99)

TMP421 ON TCON BOARD VIA J9002

PANEL TEMP SENSOR

SMC "MANAGEMENT" SMBUS (BUS 1)

(WRITE: 0X52 READ: 0X53)

PCH

U6806

XDP (PCH)

XDP (CPU)

J2550

J2500

(WRITE: 0X72 READ: 0X73)

(WRITE: 0XD2 READ: 0XD3)

MEM VREF MARGIN A

CK505

(WRITE: 0X7C READ: 0X7D)

U2910

MIKEY

U2900

U9310, PS8301

(WRITE: 0X94, READ: 0X95)

U1800

(SLAVE)

PCIE MINI-CARD

MEMORY B DIMMS

X18 WI-FI MODULE

TMP106: J3400

ALS

(MASTER)

(DIMM0: WRITE: 0XA0 READ: 0XA1)

SMC

U4900

(MASTER)

U4900

SMC

(SLAVE)

BUS A CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K74 CHOOSES 1

NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE

SMC "A" SMBUS CONNECTIONS

U1800

PCH

(MASTER)

U4900

(MASTER)

U2600

(DIMM1: WRITE: 0XA4 READ: 0XA5)

SMC

U1800

USES INTERNAL SMC CONTROLLER CHANNEL 2 ONLY (NO CONNECTIONS, JUST PULLUP)

J3200-A/B

(SLAVE)

AND PANEL ID)

TCON ALSO HAS

(MASTER)

(MASTER)

(MASTER)

SMC

U4900

EMC1428: U5500

GPU ON CARD - J8400

MXM TEMP

Also reserve 0x56 and 0x32 per spec

(WRITE: 0x92 READ:0x93)

PROD: AMB,L-SKIN,R-SKIN,ODD,

DEV: CPU D,CPU HTSK

LCD,CPU PROX,MXM TEMPS

NV INSIDE (WRITE: 0X9E READ: 0X9F)

(WRITE: 0X78 READ: 0X79)

VIA J602

(DIMM2: WRITE: 0XA2 READ: 0XA3)

(WRITE: 0X6E READ: 0X6F)

SMC SLAVE SMBUS "2" CONNECTIONS

EMC1414: U5520

J3100-A/B

(SLAVE)

VIA J9002

OUTPUT VOLTAGE, CURRENT, POWER

(WRITE: 0X90 READ: 0X91)

VIA J602

MEM VREF MARGIN B

I2C BUS PULL-UP RAIL MUST REFLECT

(WRITE: 0X26 READ: 0X27)

3 SENSE POINTS - PRIMARY, SECONDARY, AMB

SMC "B" SMBUS CONNECTIONS

BUS B CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K60/62 CHOOSES 0

(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)

EMC1403-[1,2] : ACDC THRU J600

AC/DC PS TEMPS

2

1

R5280

100K

MF-LF

1/16W

5%

402

2

1

R5281

MF-LF

1/16W

100K

402

5%

2

1

R5291

MF-LF
402

1/16W

5%

2.2K

2

1

R5290

5%

402

MF-LF

1/16W

2.2K

2

1

R5261

MF-LF

5%
1/16W

402

2.0K

2

1

R5260

5%

402

1/16W
MF-LF

2.0K

2

1

R5251

2.2K

MF-LF

1/16W

402

5%

2

1

R5250

2.2K

1/16W

402

5%

MF-LF

2

1

R5203

MF-LF
402

1/16W

5%

8.2K

2

1

R5202

1/16W

5%

MF-LF

402

8.2K

2

1

R5204

MF-LF

1/16W

402

5%

NOSTUFF

8.2K

2

1

R5205

MF-LF

1/16W

402

5%

8.2K

NOSTUFF

21

R5206

402

1/16W

0

MF-LF

5%

21

R5207

402

5%

0

MF-LF

1/16W

2

1

R5270

4.7K

402

1/16W
MF-LF

5%

2

1

R5271

MF-LF

4.7K

5%

402

1/16W

2

1

R5208

2.2K

402

5%

MF-LF

1/16W

2

1

R5209

1/16W
MF-LF

2.2K

5%

402

2

1

R5210

2.2K

5%

402

1/16W
MF-LF

2

1

R5211

5%

402

1/16W
MF-LF

2.2K

6

81

94

6
81

94

2

1

R5230

T29

5%

1/16W

402

4.7K

MF-LF

2

1

R5231

T29

MF-LF
402

4.7K

5%
1/16W

SYNC_MASTER=K60_MARK

SMBUS CONNECTIONS

SYNC_DATE=01/06/2011

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

=I2C_VREFMRGN_A_SDA

=SMB_ACDC_SDA

SMB_0_S0_DATA

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

=SMB_ALS_SCL

MAKE_BASE=TRUE

SML_PCH_0_CLK

SMB_0_S0_CLK

=I2C_SODIMMA_SCL

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS

=SMB_SNS1_SCL

=SMB_SNS1_SDA

=SMB_MXM_THRM_SDA

SMB_MGMT_CLK

=PP3V3_S0_SMBUS_SMC_MGMT

SMB_A_S3_DATA

=SMB_ACDC_SCL

SMB_BSA_CLK

MAKE_BASE=TRUE

SML_PCH_0_DATA

SMB_B_S0_DATA

=PP3V3_S3_SMBUS_SMC_A

SMB_BSA_DATA

=PP3V3_S0_SMBUS_SMC_B

SMB_A_S3_CLK

=SMB_MINI_SCL

=SMB_MINI_SDA

=I2C_SODIMMA_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMB_B_S0_CLK

=I2C_AUDIO_SDA

=I2C_SODIMMB_SDA

=SMBUS_CK505_SCL

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

=SMBUS_CK505_SDA

=I2C_AUDIO_SCL

=I2C_VREFMRGN_B_SDA

=I2C_VREFMRGN_A_SCL

=SMBUS_XDP_SCL

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

=SMBUS_XDP_SDA

=PP3V3_S0_SMBUS_SMC_0

=SMB_ALS_SDA

SMB_DP_TCON_SLA_SCL

=SMB_BLC_PCH_SCL

=SMB_BLC_PCH_SDA

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

=SMB_MXM_THRM_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SML_PCH_1_DATA
MAKE_BASE=TRUE

MAKE_BASE=TRUE

SML_PCH_1_CLK

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS

=SMB_DP_TCON_SDA

MAKE_BASE=TRUE

SMB_BLC_TCON_SDA

=PP3V3_S0_SMBUS

SMB_MGMT_DATA

=PP3V3_S0_SMBUS_SMC_BSA

=I2C_VREFMRGN_B_SCL

SMB_DP_TCON_SLA_SDA

=I2C_T29AMCU_SDA

=I2C_T29AMCU_SCL

MAKE_BASE=TRUE

SMB_BLC_TCON_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_CLK
MAKE_BASE=TRUE

=I2C_DPSDRVA_SCL

=I2C_DPSDRVA_SDA

=I2C_SODIMMB_SCL

=SMB_DP_TCON_SCL

MAKE_BASE=TRUE

I2C_T29_SDA

MAKE_BASE=TRUE

I2C_T29_SCL

=PP3V3_S0_T29I2C

52 OF 110

11.1.0

051-8115

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94

94

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46

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94

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52

52

76

46

6

46

6

46

18 94

46

6

46

6

46

33

33

30

94

94

46

62

31

26

94

26

62

28

28

25 49

25 49

25 49

25 49

6

44

81

6

6

94

76

94

18 94

18 94

6

49

6

49

6

49

46

6

28

81

84

84

18 94

18 94

84

84

31

86 96

86 96

6

www.vinafix.vn

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

V+

REFIN+

IN-

OUT

GND

OUT

OUT

V+

REFIN+

IN-

OUT

GND

OUT

OUT

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

OUT

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

DIMM VDD 1.5V (LIKELY DEVELOPMENT ONLY)

IMAX = 8.25A

IMAX = 8.25A

353S2073

GAIN = 200V/V

353S2073

GAIN = 200V/V

IMAX = 8.25A

IMAX = 8.25A

IMAX = 8.25A

353S2073

GAIN = 200V/V

NO_CPU_VCCSA_SENSE, AND

THE NO_1V05_PCH_SENSE,
NO_CPU_1V5_SENSE

BOMOPTIONS SHOULD IDEALLY
NEVER BE USED AS TOTAL CPU POWER
SENSING REQUIRES ALL
3 SENSORS.

IMAX = 2.79V

IMON MAX = 0.9V

353S2073

GAIN = 200V/V

NOTE: TOTAL CPU POWER =

+ VC5R*IC5R

VC0C*IC0C

+ VCSR*ICSR
+ VC0G*IC0G
+ VV1R*IC1R

where

IC1R = IV1R - IN1R - ICSR

SENSE RESISTOR CURRENT (ICSR) AND VOLTAGE (VCSR) SENSE

CPU VAXG

IMON CURRENT (IC0G) AND VOLTAGE (VC0G) SENSE

IMON CURRENT (IC0C) AND VOLTAGE (VC0C) SENSE

GPU MXM

SENSE RESISTOR CURRENT (IG0R) AND VOLTAGE (VG0R) SENSE

CPU VCCSA

IMON MAX = 0.9V

IMAX = 2.7V

PCH 1.05V

IMON MAX = 2.7V

CPU VDD 1.5V

SENSE RESISTOR CURRENT (IC5R) AND VOLTAGE (VC5R) SENSE

SENSE RESISTOR CURRENT (IN1R) AND VOLTAGE (VN1R) SENSE

PLACE C CLOSE TO SMC

CPU VCC (VCORE)

SENSE RESISTOR CURRENT (IM0R) AND VOLTAGE (VM0R) SENSE

IMAX = 2.79V

IMON CURRENT (IV1R) AND VOLTAGE (VV1R) SENSE

1.05V FOR CPU VCCIO, CPU VCCSA & PCH 1.05V

46 94

2

1

C5332

PLACEMENT_NOTE=PLACE C5332 NEAR SMC

10%
CERM-X5R

6.3V
402

0.22UF

21

R5332

PLACEMENT_NOTE=PLACE R5332 NEAR SMC

402

5%

5.1K

1/16W
MF-LF

21

C5331

402

CERM

0.01UF

20%
16V

21

R5331

1%
1/16W
MF-LF

9.31K

OMIT_TABLE

402

21

R5333

1/16W
MF-LF

402

10K

1%

65 95

5

2

4

1

3

U5330

CRITICAL

SC70-5

OPA348

2

1

R5334

10K

1%
1/16W

402

MF-LF

3

1

6

4

5

2

U5300

CPU_1V5_SENSE

INA210

SC70

2

1

C5302

PLACEMENT_NOTE=PLACE C5302 NEAR SMC

OMIT_TABLE

0.22UF

402

X5R

20%

6.3V

43

21

R5300

1/4W
1206

0.002

MF-LF

1%

OMIT_TABLE

21

R5302

PLACEMENT_NOTE=PLACE R5302 NEAR SMC

1/16W

402

MF-LF

1%

4.53K

CPU_1V5_SENSE

21

R5301

402

1/16W
MF-LF

1%

4.53K

CPU_1V5_SENSE

PLACEMENT_NOTE=PLACE R5301 NEAR CPU

2

1

C5301

OMIT_TABLE

PLACEMENT_NOTE=PLACE C5301 NEAR SMC

0.22UF

20%

402

X5R

6.3V

21

R5360

18.2K

1/16W

1%

402

MF-LF

PLACEMENT_NOTE=PLACE R5360 NEAR CPU

2

1

C5362

PLACEMENT_NOTE=PLACE C5362 NEAR SMC

6.3V

20%
X5R

402

0.22UF

2

1

R5362

402

MF-LF

1/16W

1%

6.04K

21

C5351

402

16V

CERM

20%

0.01UF

46 94

2

1

C5352

CERM-X5R

0.22UF

402

10%

6.3V

PLACEMENT_NOTE=PLACE C5352 NEAR SMC

21

R5352

5%

MF-LF

PLACEMENT_NOTE=PLACE R5352 NEAR SMC

402

1/16W

5.1K

5

2

4

1

3

U5350

CRITICAL

OPA348
SC70-5

21

R5353

1/16W

402

1K

5%

MF-LF

68 95

46 94

2

1

C5350

X5R

20%

6.3V

PLACEMENT_NOTE=PLACE C5350 NEAR SMC

402

0.22UF

21

R5350

4.53K

1/16W

1%

MF-LF

402

PLACEMENT_NOTE=PLACE R5350 NEAR CPU

46 94

46 94

2

1

C5340

OMIT_TABLE

6.3V

PLACEMENT_NOTE=PLACE C5340 NEAR SMC

X5R

0.22UF

20%

402

21

R5340

VAXG

PLACEMENT_NOTE=PLACE R5340 NEAR CPU

1%

4.53K

402

MF-LF

1/16W

21

R5342

402

5.1K

PLACEMENT_NOTE=PLACE C5342 NEAR SMC

VAXG

1/16W
MF-LF

5%

21

C5341

VAXG

16V
402

20%

0.01UF

CERM

21

R5341

VAXG

1/16W

21K

MF-LF

402

1%

5

2

4

1

3

U5340

CRITICAL

VAXG

SC70-5

OPA348

2

1

C5342

CERM-X5R

0.22UF

OMIT_TABLE

402

10%

PLACEMENT_NOTE=PLACE R5342 NEAR SMC

6.3V

21

R5343

1/16W

VAXG

1%

MF-LF

402

10K

65 95

2

1

R5344

1/16W

VAXG

1%

402

MF-LF

10K

46 94

46 94

46 94

46 94

21

C5300

CPU_1V5_SENSE

20%

6.3V
X5R
402

0.22UF

46 94

46 94

2

1

C5311

PLACEMENT_NOTE=PLACE R5311 NEAR CPU

OMIT_TABLE

402

20%

6.3V

0.22UF

X5R

21

R5311

402

1%

CPU_VCCSA_SENSE

1/16W

PLACEMENT_NOTE=PLACE C5311 NEAR SMC

MF-LF

4.53K

2

1

C5312

PLACEMENT_NOTE=PLACE C5312 NEAR SMC

402

X5R

20%

6.3V

0.22UF

OMIT_TABLE

21

R5312

MF-LF

402

PLACEMENT_NOTE=PLACE R5312 NEAR SMC

1/16W

4.53K

1%

CPU_VCCSA_SENSE

3

1

6

4

5

2

U5310

INA210

CPU_VCCSA_SENSE

SC70

21

C5310

20%

6.3V
X5R
402

0.22UF

CPU_VCCSA_SENSE

46 94

46 94

21

R5321

402

1%

PLACEMENT_NOTE=PLACE C5321 NEAR SMC

MF-LF

1/16W

4.53K

1V05_PCH_SENSE

2

1

C5321

OMIT_TABLE

20%

402

X5R

6.3V

PLACEMENT_NOTE=PLACE R5321 NEAR CPU

0.22UF

2

1

C5322

OMIT_TABLE

0.22UF

20%

6.3V
X5R

PLACEMENT_NOTE=PLACE C5322 NEAR SMC

402

21

R5322

1%

402

1/16W

4.53K

1V05_PCH_SENSE

PLACEMENT_NOTE=PLACE R5322 NEAR SMC

MF-LF

43

21

R5320

OMIT_TABLE

1/4W

1%

0.002

1206

MF-LF

3

1

6

4

5

2

U5320

1V05_PCH_SENSE

SC70

INA210

21

C5320

0.22UF

402

X5R

6.3V

20%

1V05_PCH_SENSE

46 94

46 94

21

R5371

PLACEMENT_NOTE=PLACE R5371 NEAR CPU

DIMM_1V5_SENSE

4.53K

1%

MF-LF

402

1/16W

2

1

C5371

PLACEMENT_NOTE=PLACE C5372 NEAR SMC

OMIT_TABLE

402

X5R

0.22UF

20%

6.3V

21

R5372

DIMM_1V5_SENSE

4.53K

1/16W

402

1%

MF-LF

2

1

C5372

OMIT_TABLE

X5R

6.3V

0.22UF

20%

402

43

21

R5370

1206

MF-LF

1/4W

0.002

1%

21

C5370

X5R
402

DIMM_1V5_SENSE

0.22UF

6.3V

20%

3

1

6

4

5

2

U5370

SC70

INA210

DIMM_1V5_SENSE

43

21

R5310

OMIT_TABLE

1/4W

MF-LF

1206

1%

0.002

3

1

6

4

5

2

U5360

CRITICAL

INA210

SC70

43

21

R5361

1%

MF-LF

1/4W

0.002

CRITICAL

1206

2

1

C5360

0.22UF

402

X5R

6.3V

20%

21

R5363

402

MF-LF

1%

1/16W

4.53K

2

1

C5363

402

20%

0.22UF

6.3V
X5R

46 94

21

R5330

1%

MF-LF

402

1/16W

4.53K

PLACEMENT_NOTE=PLACE R5330 NEAR CPU

2

1

C5330

20%

X5R

6.3V

PLACEMENT_NOTE=PLACE C5330 NEAR SMC

0.22UF

402

116S0004

RES,0 OHM,402

NO_VAXG

2

C5340,C5342

132S0080

CAP,0.22UF,402

VAXG

2

C5340,C5342

CPU/PCH/GPU POWER SENSE

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

R5310

1

104S0018

RES,2 MILLIOHM,1206

CPU_VCCSA_SENSE

C5301,C5302

132S0080

2

CAP,0.22UF,402

CPU_1V5_SENSE

1

101S0414

R5320

RES,0 OHM,1206,20 MILLIOHM MAX

NO_1V05_PCH_SENSE

132S0080

2

CAP,0.22UF,402

C5321,C5322

1V05_PCH_SENSE

RES,0 OHM,1206,20 MILLIOHM MAX

NO_CPU_1V5_SENSE

101S0414

1

R5300

1

104S0018

R5320

RES,2 MILLIOHM,1206

1V05_PCH_SENSE

C5321,C5322

2

RES,0 OHM,402

116S0004

NO_1V05_PCH_SENSE

R5331

CPUVCORE-3PH

1

114S0312

RES,MTL FILM,1/16W,9.31K,0402

RES,MTL FILM,1/16W,21K,0402

R5331

1

CPUVCORE-4PH

114S0345

CPU_1V5_SENSE

RES,2 MILLIOHM,1206

1

104S0018

R5300

NO_CPU_1V5_SENSE

RES,0 OHM,402

116S0004

2

C5301,C5302

NO_CPU_VCCSA_SENSE

RES,0 OHM,1206,20 MILLIOHM MAX

101S0414

1

R5310

C5311,C5312

CAP,0.22UF,402

2

132S0080

CPU_VCCSA_SENSE

NO_CPU_VCCSA_SENSE

C5311,C5312

RES,0 OHM,402

116S0004

2

132S0080

DIMM_1V5_SENSE

2

CAP,0.22UF,402

C5371,C5372

PRODUCTION

2

116S0004

C5371,C5372

RES,0 OHM,402

SMC_1V05_VSENSE

GND_SMC_AVSS

VR_ISNS_VAXG_N

SNS_PS_VAXG_ISNS

SMC_DIMM_VSENSE

SMC_DIMM_ISENSE

GND_SMC_AVSS

PP1V5_S0_CPU_MEM_SNS

=PPVCORE_S0_CPU

SNS_CPU_1V5_P

GND_SMC_AVSS

VR_ISNS_N_1V05

P1V05_IMON

VR_ISNS_P_1V05

=PP5V_S0_ISENSE

SMC_VCORE_ISENSE

=PPVCCSA_S0_CPU

PPVCCSA_S0_INPUT_SNS

PP1V5_S3_MEM_SNS

=PP3V3_S0_SENSE

GND_SMC_AVSS

SMC_GPU_ISENSE

SNS_DIMM_1V5_N

=PP3V3_S0_SENSE

SNS_I_MXM_P

PP12V_S0_MXM_SNS

=PP12V_S0_MXM_PWR

SMC_PCH_1V05_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

PP1V05_S0_PCH_SNS

=PP1V5_S0_PWR

SMC_VCCSA_VSENSE

SNS_CPU_1V5_N

SMC_CPU_1V5_ISENSE_R

SMC_VCCSA_ISENSE

GND_SMC_AVSS

SMC_DIMM_1V5_R

GND_SMC_AVSS

GND_SMC_AVSS

SMC_GPU_VSENSE

SMC_CPU_1V5_VSENSE

GND_SMC_AVSS

SNS_1V05_PCH_R

SMC_VCCSA_ISENSE_R

=PPVCCSA_S0_INPUT_PWR

SMC_CPU_1V5_ISENSE

=PP3V3_S0_SENSE

SNS_1V05_PCH_N

SNS_VCCSA_N

SNS_VCCSA_P

GND_SMC_AVSS

SMC_PCH_1V05_ISENSE

=PP1V05_S0_PCH_PWR

SNS_DIMM_1V5_P

SNS_I_MXM_N

GND_SMC_AVSS

=PP1V05_S0_PWR

=PP1V5_S3_MEM_PWR

VR_ISNS_VCORE_P

VR_CPU_IMON

SMC_VCORE_VSENSE

SMC_1V05_ISENSE

SMC_GPU_R

=PP5V_S0_ISENSE

SNS_1V05_PCH_P

=PP3V3_S0_SENSE

GND_SMC_AVSS

VR_ISNS_VCORE_N

GND_SMC_AVSS

SNS_PS_VCORE_ISNS

GND_SMC_AVSS

GND_SMC_AVSS

=PP5V_S0_ISENSE

SMC_VAXG_VSENSE

=PPVAXG_S0_CPU

VR_AXG_IMON

VR_ISNS_VAXG_P

=PP3V3_S0_SENSE

SMC_VAXG_ISENSE

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6

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94

46 47 50 94

6

50

6

13

6

6

6

50 52

46 47 50 94

94

6

50 52

94

6

6

46 47 50 94

46 47 50 94

6

6

94

94

46 47 50 94

94

46 47 50 94

46 47 50 94

46 47 50 94

94

6

69

6

50 52

94

94

94

46 47 50 94

6

94

94

46 47 50 94

6

6

94 95

6

50

94

6

50 52

46 47 50 94

46 47 50 94

46 47 50 94

46 47 50 94

6

50

6

13 17 65

6

50 52

www.vinafix.vn

IN

OUT

GND

V+

IN

GND

V+

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DRIVE ASLEEP = HDD DRIVES HDD_OOB_TEMP LOW

BOTH FUNCTIONS NOT USED.

NOTE: WILL BE CONNECTED TO SATA PWR CONNECTOR PIN 11
THIS PIN IS ORIGINALLY INTENDED FOR HDD LED OUTPUT,
AND ALSO FOR HDD STAGGERED PIN UP (FLOATING) OR IMMEDIATE SPIN-UP (GROUND).

DRIVE ACTIVE = VALID SIGNAL PROTOCOL BETWEEN 0-2.0V.

HIGH: 1.2V TO 2.0V

DRIVE ABSENT = OOB IS PULLED HIGH UNLESS PCH DETERMINES SSD PRESENT AND DRIVES USE_HDD_OOB_L LOW WHICH THEN PULLS HDD_OOB_TEMP LOW.

LOW: 0.0V TO 0.3V

FROM DRIVE:

Pull up 1.5V.

1.5V

Trip point 1.0V.

HDD OOB TEMPERATURE SENSING

2

1

R5405

MF-LF

1/16W

1K

402

5%

2

1

R5402

1/16W

5%
MF-LF

402

180K

2

1

R5404

150K

1/16W

5%

MF-LF

402

2

1

C5401

20%
16V
CERM
603

0.1UF

42 94 98

2

1

C5400

0.1UF

16V

20%

CERM
603

46 94

8

7

5

6

4

U5400

LM393

CRITICAL

SOI-HF

21

R5407

10K

MF-LF

402

5%

1/16W

2

1

R5406

0

1/16W
402

MF-LF

5%

NOSTUFF

20 97

8

1

3

2

4

U5400

SOI-HF

CRITICAL

LM393

2

1

R5400

1%

402

1/16W
MF-LF

110K

2

1

R5401

402

1%

10K

1/16W
MF-LF

21

R5403

MF-LF

402

5%

1/16W

3.3K

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

HDD OOB SENSE

=PP12V_S0_SENSE

=PP3V3_S0_SMC_LS

SMC_HDD_OOB_TEMP

HDD_OOB_TEMP_FILT

USE_HDD_OOB_PD

USE_HDD_OOB_L_R

USE_HDD_OOB_L

HDD_OOB_1V00_REF

=PP3V3_S0_SMC_LS HDD_OOB_1V00_REF

HDD_OOB_TEMP_R

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051-8115

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6

47 51

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6

47 51

51 97

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www.vinafix.vn

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

BI

IN

VDD

DP6/DN7
DN6/DP7

DN4/DP5

DP2/DN3
DN2/DP3

DP4/DN5

DN1

DP1

THRM_PAD

GND

NC

TRIP/SET

SMDATA

SMCLK

SYS_SHND*

ALERT*

BI

IN

NC

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ON K60 IT IS SHARED.

AMBIENT TEMP SENSOR ON K62 GOES TO J5500.

ODD TEMP SENSOR

MXM HTSK TEMP SENSOR

CPU PROXIMITY TEMP SENSOR

Place Q5500 (CPU Proximity Sensor) at the solder side

CPU HTSK TEMP SENSOR

THIS PAGE DIFFERENT BETWEEN K60 AND K62.

EMC1414-A-AIZL: 33K PULL UP: I2C ADDRESS: WRITE: 0x78, READ: 0x79

SNS T1: PRODUCTION TEMP SENSOR IC

518S0665

SNS T2: DEVELOPMENT TEMP SENSOR IC

EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93

MLB Prox 0 (Tm0p)

AMB (TA0p)

ODD (TO0p)

at edge near backer plate of CPU to replace HeatSink Temp Sensor

(TL2p)

MLB Prox 1 (Tm1p)

CPU HTSK (TC0h)

MXM HTSK (TG0h)

RIGHT SKIN (TS0p)

LEFT SKIN (TS2p)

CPU PROX (TC0p)

RIGHT SKIN TEMP SENSOR

LCD TEMP

CPU THERMAL DIODE
(TC0D)

ONLY DP/N1 compatible with CPU thermal diode

518S0665

LEFT SKIN TEMP SENSOR

CONNECTOR COMBINED WITH CAMERA/BT

518S0678

Set trip point to 125 C.

518S0678

518S0677

518S0698

AMBIENT TEMP SENSOR

Place Hsk sensor conn top side next MXM or CPU

2

1

C5521

0.0022UF

50V
CERM

10%

402

DEVELOPMENT

2

1

C5520

DEVELOPMENT

X5R

10%

402-1

1UF

6.3V

21

L5510

FERR-220-OHM

0402

21

L5511

FERR-220-OHM

0402

21

L5500

FERR-220-OHM

0402

21

L5501

0402

FERR-220-OHM

21

L5540

MXM

0402

FERR-220-OHM

21

L5541

FERR-220-OHM

0402

MXM

2

1

4

3

J5530

CRITICAL

53398-8602

M-ST-SM

MXM

SILK_PART=MXM HSK

21

L5520

0402

FERR-220-OHM

21

L5521

FERR-220-OHM

0402

2

1

4

3

J5520

53261-8602

M-RT-SM

CRITICAL

SILK_PART=SKIN RIGHT TEMP

2

1

R5520

1%

MF-LF
402

1/16W

DEVELOPMENT

33.2K

2

1

C5500

10%
X5R

402-1

10V

1UF

2

1

R5521

402

DEVELOPMENT

10K

MF-LF

5%
1/16W

1

7

9

10

6

4

2

5

3 8

U5520

DEVELOPMENT

MSOP

EMC1414-A

2

1

C5504

NOSTUFF

10%

0.0022UF

50V
CERM
402

2

3

1

Q5500

SOT23

MMBT3904G

2

1

C5550

0.0022UF

CERM

DEVELOPMENT

10%

402

50V

21

L5550

0402

FERR-220-OHM

DEVELOPMENT

21

L5551

0402

FERR-220-OHM

DEVELOPMENT

49 52

49 52

16

5

17

6

11

12

8

15

10

3

1

14

9

4

2

7

U5500

CRITICAL

QFN

EMC1428-7

PLACEMENT_NOTE=PLACE U5500 UNDER MXM HTSK TO GET MXM PROX TEMP

2

1

XW5504

SM

OMIT

2

1

XW5505

OMIT

SM

2

1

XW5503

SM

OMIT

2

1

XW5502

SM

OMIT

2

1

XW5501

SM

OMIT

2

1

XW5500

SM

OMIT

49 52

49 52

2

1

R5501

402

5%

10K

MF-LF

1/16W

2

1

R5500

1%

6.81K

402

1/16W
MF-LF

2

1

R5502

1/16W
MF-LF

20K

5%

402

2 1

L5522

FERR-220-OHM

0402

2 1

L5523

FERR-220-OHM

0402

2

1

C5522

10%

0.0022UF

CERM

50V

402

2

1

C5501

0.0022UF

50V
CERM

10%

402

2

1

C5511

0.0022UF

402

10%
CERM

50V

2

1

C5512

402

CERM

50V

10%

0.0022UF

2

1

C5513

0.0022UF

402

10%
CERM

50V

2

1

C5514

MXM

0.0022UF

50V
CERM

10%

402

2

1

4

3

J5510

SILK_PART=ODD TEMP

CRITICAL

M-RT-SM

53780-8602

21

L5530

0402

FERR-1000-OHM

21

L5531

0402

FERR-1000-OHM

2

1

4

3

J5521

CRITICAL

53398-8602

M-ST-SM

SILK_PART=CPU HSK

2

1

4

3

J5550

M-RT-SM

53261-8602

CRITICAL

SILK_PART=LCD TEMP

DEVELOPMENT

SYNC_DATE=01/06/2011SYNC_MASTER=K60_MARK

TEMP SENSORS

SNS_T1_5_P

SNS_SKIN_LEFT_N

SNS_AMB_P

SNS_T1_1_N

SNS_SKIN_RIGHT_N

SNS_T1_3_N

SNS_T1_5_N

SNS_MXM_N

SNS_MXM_P

SNS_SKIN_RIGHT_P

SNS_T1_3_N

SNS_T1_7_P

SNS_T1_5_P

SNS_T1_1_P

=SMB_SNS1_SDA

=SMB_SNS1_SCL

SNS_T1_2_P

SNS_T1_5_N

SNS_T1_7_N

SNS_T1_6_N

SNS_T1_4_P

SNS_T1_4_N

SNS_T1_TRIPSET

SNS_T1_6_N

SNS_T1_6_P

SNS_SKIN_LEFT_P

SNS_T1_7_N

SNS_LCD_H_P
SNS_LCD_H_N

SNS_T1_2_P

SNS_T1_2_N

SNS_T1_3_P

SNS_CPU_H_N

SNS_T2_DP2

=SMB_SNS1_SCL

SNS_T2_ALERT_L

SNS_T2_ADDR

=SMB_SNS1_SDA

SNS_T1_3_P

SNS_T1_4_N

SNS_T1_2_N

SNS_ODD_N

SNS_T1_1_P
SNS_T1_1_N

SNS_CPU_THERMD_P

SNS_CPU_THERMD_N

SNS_CPU_H_P

SNS_T1_6_P

SNS_T1_4_P

=PP3V3_S0_SENSE

SNS_T1_ADDR

=PP3V3_S0_SENSE

SNS_T1_ALERT_L

SNS_T2_DN2

SNS_ODD_P

SNS_AMB_N

SNS_T1_7_P

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94

94

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52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

44 94 98

52 94

94

94

52 94

52 94

52 94

94

94

52 94

52 94

52 94

94 98

52 94

52 94

10 94

10 94

94

52 94

52 94

6

50 52

6

50 52

94

94 98

54 94 98

52 94

www.vinafix.vn

G

S

D

G

S

D

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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SHEET

PAGE TITLE

C

A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

HD FAN

ODD FAN

NOTE: ADDED TO PROTECT SMC

FAN 1

518S0730

12V DC

GND

FAN 0

TACH

MOTOR CONTROL

C5605 IS POLY-TANT BECAUSE IT MUST BE PLACED ON THE BOTTOM

12V DC

MOTOR CONTROL
TACH
GND

518S0730

2

1

R5600

402

MF-LF

1/16W

10K

5%

2

1

R5601

402

1/16W

10K

5%
MF-LF

2

1

R5602

1206

MF-LF

1/4W

1.5K

5%

5

4

87632

1

Q5600

1206A-03-HF

NTHS5443T1H

CRITICAL

2

1

R5603

1.5K

MF-LF

1/8W

5%

805

3

1

D5600

SOT23

MMBD914XG

2

1

C5601

X7R

10%
16V

805

0.47UF

21

R5605

805

1/8W

MF-LF

3.9K

5%

2

1

R5606

5%

402

10K

1/16W
MF-LF

5

4

87632

1

Q5603

NTHS5443T1H

1206A-03-HF

CRITICAL

2

1

R5607

1/8W

1.5K

5%

MF-LF

805

2

1

C5603

0.47UF

10%

805

X7R

16V

21

R5609

805

5%

1/8W

MF-LF

3.9K

3

1

D5601

SOT23

MMBD914XG

2

1

R5610

1/4W
1206

5%

MF-LF

1.5K

2

1

R5611

10K

MF-LF

402

5%

1/16W

21

R5699

402

1/16W

47K

5%

MF-LF

21

R5698

47K

5%
1/16W
MF-LF

402

2

1

3

Q5602

2N7002

SOT23-HF1

2

1

3

Q5605

2N7002

SOT23-HF1

2

1

C5602

100UF

6.3X5.5-SM1-HF

ELEC

16V

CRITICAL

20%

4

3

2

1

6

5

J5601

M-RT-SM

53780-8604

CRITICAL

4

3

2

1

6

5

J5600

CRITICAL

M-RT-SM

53780-8604

2

1

C5607

0.01UF

16V
CERM

20%

402

2

1

C5606

20%
CERM

1206-1

16V

4.7UF

2

1

C5609

16V

20%

0.01UF

402

CERM

2

1

C5608

2.2UF

16V

10%
603

X5R

21

L5600

0402

CRITICAL

FERR-220-OHM

21

L5601

CRITICAL

0402

FERR-220-OHM

21

L5610

220-OHM-1.4A

CRITICAL

0603

21

L5620

220-OHM-1.4A

0603

CRITICAL

21

L5630

0603

220-OHM-1.4A

CRITICAL

21

L5640

CRITICAL

0603

220-OHM-1.4A

2

1

R5620

MF-LF

1/10W

5%

0

603

PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3

2

1

R5630

PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3

5%
1/10W
MF-LF
603

0

2

1

C5628

X5R
603

2.2UF

10%
16V

2

1

C5605

TANT

16V

20%

100UF

D-HF

CRITICAL

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

HD AND OD FAN

FAN_TACH1_L

VOLTAGE=12V

MIN_LINE_WIDTH=0.5MM

PP12V_S0_FAN1_L

MIN_NECK_WIDTH=0.25MM

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

FAN_1_GND

MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

FAN_1_PWR_L

VOLTAGE=12V

MIN_LINE_WIDTH=0.5MM

PP12V_S0_FAN0_L

MIN_NECK_WIDTH=0.25MM

FAN_TACH0_L

=PP3V3_S0_FAN

F0_GATESLOWDN

FAN_0_PWR

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.25MM

F0_VOLTAGE8R5

MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

FAN_0_PWR_L

FAN_0_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

=PP3V3_S0_FAN

FAN_TACH0

SMC_FAN_0_TACH

SMC_FAN_0_CTL

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.25MM

FAN_1_PWR

F1_GATESLOWDN

FAN_TACH1

=PP3V3_S0_FAN

SMC_FAN_1_TACH

=PP12V_S0_FAN

F1_VOLTAGE8R5

=PP12V_S0_FAN

SMC_FAN_1_CTL

=PP3V3_S0_FAN

56 OF 110

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98

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46

6

53 54

46

6

53 54

6

53 54

46

6

53 54

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G

S

D

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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SHEET

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FAN 3 SMC CONTROL (UNUSED)

SMC’S FAN3 OUTPUT CONTROL FAN 2

12V DC

GND

TACH

MOTOR CONTROL

518S0778

CPU FAN

2

1

3

Q5702

SOT23-HF1

2N7002

2

1

C5702

100UF

20%
16V
ELEC

6.3X5.5-SM1-HF

CRITICAL

2

1

C5708

1206-1

CERM

16V

20%

4.7UF

2

1

C5709

20%
16V

0.01UF

CERM
402

21

L5701

CRITICAL

FERR-220-OHM

0402

21

L5710

0603

220-OHM-1.4A

CRITICAL

21

L5720

0603

220-OHM-1.4A

CRITICAL

2

1

R5720

MF-LF

0

5%
1/10W

603

PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3

6

5

4

3

2

1

8

7

J5700

CRITICAL

M-RT-SM

53780-8606

2

1

R5700

1/16W
MF-LF
402

5%

10K

5

4

87632

1

Q5700

NTHS5443T1H

1206A-03-HF

CRITICAL

3

1

D5700

SOT23

MMBD914XG

2

1

R5701

1/8W

805

5%

1.5K

MF-LF

2

1

C5701

0.47UF

10%
16V
X7R
805

21

R5703

1/8W

5%

3.9K

MF-LF

805

2

1

R5704

5%
1/4W

1.5K

1206

MF-LF

2

1

R5705

MF-LF

10K

402

5%
1/16W

21

R5797

47K

5%
1/16W
MF-LF

402

CPU FAN

SYNC_DATE=01/06/2011

SYNC_MASTER=K60_JERRY

SNS_AMB_N

SNS_AMB_P

FAN_2_PWR_L

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.25MM

FAN_TACH2_L

VOLTAGE=12V

PP12V_S0_FAN2_L

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

FAN_2_GND

MIN_NECK_WIDTH=0.25MM

FAN_TACH2

F2_GATESLOWDN

SMC_FAN_3_TACH

F2_VOLTAGE8R5

=PP12V_S0_FAN

FAN_2_PWR

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

=PP3V3_S0_FAN

=PP3V3_S0_FAN

SMC_FAN_3_CTL

57 OF 110

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98

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6

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OUT

IN

IN IN

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

2

1

C6100

10%

1UF

6.3V
402

CERM

2

1

R6101

5%

402

3.3K

1/16W
MF-LF

2

1

R6100

1/16W

5%

MF-LF

3.3K

402

18 48 91

48 91

18 48 91 18 48 91

21

R6105

33

MF-LF

5%

1/16W

402

21

R6152

33

402

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

21

R6150

1/16W

402

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

33

3

4 8

2

5

6

7

1

U6100

SOIC

CRITICAL

OMIT

64MBIT

SST25VF064C

SYNC_DATE=01/06/2011

SPI ROM

SYNC_MASTER=K62

SPI_WP_L
SPI_HOLD_L

SPI_MOSI

SPI_MISO_R

SPI_CLK

SPI_CLK_R

SPI_MOSI_R

SPI_MISO

SPI_MLB_CS_L

=PP3V3_S5_ROM

61 OF 110

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051-8115

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IN

IN

IN

IN

OUT

IN

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

IN

IN
IN

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

NR/FB

NC

IN

EN

GND

OUT

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

L2L1

IN
IN

OUT

GND

SHDN*/SS

FB

SW

IN

SYM VER 2

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC
FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+
MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI
SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+
LINEOUT_L2­LINEOUT_R2+

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE XWS 6202 & 6203 NEAR PINS 35 & 36

ISOLATED 5 V POWER SUPPLY FOR HP AMP

SE FSINPUT= 1.22VRMS

DIFF FSINPUT= 2.45VRMS

APPLE P/N 353S2592

AUDIO CODEC

PLACE C6200 AS CLOSE TO PIN 9 AS POSSIBLE

APN 353S3080

4.5V POWER SUPPLY FOR CODEC

NC

HP AMP

APPLE P/N 353S2456

WOOFERS

TWEETERS

HP AMP/LINE OUT

VD MUST BE LESS THAN OR EQUAL TO VL_HD

NC

DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS

APN 128S0271

APN 152S1314

PLACE TP FOR ALL HDA SIGNALS NEAR CODEC

SPEAKERS

NC

NC

NC

NC

PLACE XWS 6200 & 6201 NEAR PINS 38 & 40

2

1

C6211

402-LF

6.3V

20%
CERM

2.2UF

2

1

C6212

2.2UF

CERM

402-LF

20%

6.3V

18 91

18 91

18 91

15 18 91

18 91

61

58

59 62

58 62

57 62

57 62

59 62

58 62

57

57

62

62

57

21

L6210

FERR-220-OHM

0402

2

1

C6221

10%

NOSTUFF

1UF

10V
402-1

X5R

2

1

C6204

402

0.47UF

10V
X5R

10%

2

1

C6200

402

0.47UF

10%
X5R

10V

2

1

C6206

0.47UF

10%
10V
X5R
402

2

1

R6200

MF-LF

1%
1/16W

2.67K

402

21

R6201

1/16W

22

5%

402

MF-LF

2

1

C6202

10V

10%
X5R

0.47UF

402

2

1

C6214

10UF

CASE-B2-SM

16V

CRITICAL

20%
POLY-TANT

2

1

C6203

CASE-B2-SM

POLY-TANT

16V

20%

10UF

2

1

C6208

10UF

20%

CASE-B2-SM

POLY-TANT

16V

6

56

6

56

56 61 95

56 61 95

56 61 95

6

58 59 60 61 62

56 95

2

1

C6205

10%

402-1

X5R

10V

1UF

1

3

6

2

4

VR6201

CRITICAL

SON

TPS71745

2

1

C6223

402

0.1UF

10%

X7R-CERM

16V

21

R6202

1/16W
MF-LF

22

402

5%

60 91

83 97

2

1

R6203

MF-LF

1/16W

402

1%

100K

2

1

C6222

1UF

402-1

10%
X5R

10V

2

1

C6224

10V
X5R

10%

1UF

402-1

2

1

C6213

10%

CRITICAL

1UF

20V
TANT

CASE-P3-HF

56 95

2

1

C6207

0402-1

20%

10UF

CERM-X5R

6.3V

CRITICAL

2

1

XW6211

SM

21

R6210

MF-LF

603

5%

0

1/10W

2

1

C6250

603

20%
X5R

10V

10UF

6

56

2

1

R6252

402

12.4K

MF-LF

1/16W

1%

2

1

C6253

NOSTUFF

1UF

10%
X5R

10V

402-1

2

1

C6252

X7R-CERM

10%

0.1UF

16V
402

2

1

R6250

1%

MF-LF

402

1/16W

40.2K

2

1

C6251

X7R-CERM

0.1UF

16V

10%

402

2 1

D6251

BAT54XV2T1

SOD-523

2

1

D6250

SOD-523

BAT54XV2T1

5

6

1

Q6250

DMMT3906W-7-F

CRITICAL

SOT-363

43

2

Q6250

SOT-363

DMMT3906W-7-F

CRITICAL

2

1

C6254

0.01UF

16V

CERM

10%

402

2

1

C6255

0.001UF

50V
X7R
402

10%

21

R6212

402

1/16W

5%

MF-LF

NOSTUFF

0

21

D6252

DO222-SM

STPS1L30MF

2

1

C6259

10UF

603

X5R

10V

20%

2

1

C6257

0.1UF

X7R-CERM

402

10%
16V

2

1

R6258

1%
MF-LF

402

1/16W

1K

NOSTUFF

2

1

R6255

1/10W

1%

603

1.0K

MF-LF

2

1

C6256

10%

1UF

25V
X5R
402

CRITICAL

2

1

R6254

603

1%

20

1/10W
MF-LF

2

1

C6261

10%

0.001UF

NOSTUFF

402

X7R

50V

2

1

R6259

100K

1%

NOSTUFF

1/16W
402

MF-LF

2

1

R6257

603

1/10W

1%

4.99K

MF-LF

21

R6260

1%

603

MF-LF

1/10W

10

2

1

C6209

2.2UF

6.3V

20%

402-LF

CERM

2

1

C6210

CERM

6.3V

20%

2.2UF

402-LF

57

21

L6212

0402

NOSTUFF

FERR-220-OHM

2

1

XW6200

SM

59 62

58 62

2

1

XW6201

SM

2

1

XW6203

SM

59 62

58 62

2

1

XW6202

SM

2

1

R6205

0

5%
1/16W

402

MF-LF

57 62

57 62

4

3

2

1

T6250

1.8UH-1.6A-243MOHM

LPD3015-SM

CRITICAL

21

R6213

1/10W
MF-LF

603

0

5%

2

1

C6258

20%

TANT

6.3V

150UF-.025-OHM

CASE-B2-SM

CRITICAL

2

1

XW6212

SM

61 62

61 62

21

R6253

MF-LF

1/16W

402

43.2K

1%

2

1

R6251

3.40K

1%
MF-LF

402

1/16W

2

1

R6256

1%
1/16W
MF-LF

49.9K

402

61

21

R6220

0

MF-LF

5%

1/16W

402

2

1

C6201

4V

X5R-1

402

4.7UF

20%

145

2

3

U6250

TSOT-23

SC4503

CRITICAL

27

1

3

44
41

9

28

29

24

46

25

49

10

48

47

13

5

8

11

19
20

18
17

16

32
33

36
37

31
30

35
34

23

21

22

39

40

38

15

14

12

2

45

42

43

4

7

6

26

U6201

CS4206B

QFN

CRITICAL

SYNC_DATE=01/06/2011

AUDIO: CODEC/REGULATOR

SYNC_MASTER=K60_DAVID

353S2592

U6201

CS4206A

353S3199

GND_AUDIO_CODEC

SC4503_FB_RDIV

SC4503_FB_PNP

SC4503_FB_FILT

SC4503_SW_D

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

AUD_XFRMR_SEC

GND_AUDIO_ISO

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

GND_AUDIO_ISO

PP5V_AUDIO_ISO

MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

MIN_LINE_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

4V5_NR

AUD_LO2_L_N

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

GND_AUDIO_HPAMP

HDA_SDIN0

AUD_HP_R_N

AUD_HP_L_N

GND_AUDIO_HPAMP

GND_AUDIO_HPAMP

AUD_SPDIF_OUT

VOLTAGE=4.5V

4V5_OUT

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

SC4503_SW_SNBR

PP5V_LAMP_VREG

=PP5V_S0_AUDIO

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.5V

PP5V_AUDIO_HPAMP

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.5V

4V5_REG_IN

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM

4V5_REG_EN

=PP5V_S0_AUDIO

GND_AUDIO_HPAMP

MIN_LINE_WIDTH=0.2MM
VOLTAGE=0V

MIN_NECK_WIDTH=0.1MM

SC4503_SW

AUD_LO2_R_N

=PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

SC4503_SW

SC4503_FB

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

SC4503_SHDN_L

SC4503_FB_DDROP

AUD_LO2_R_P

AUD_LO2_L_P

MIN_LINE_WIDTH=0.20MM

CS4206_VREF_ADC

MIN_NECK_WIDTH=0.15MM

AUD_MIC_INR_P
AUD_MIC_INR_N

HDA_BIT_CLK

HDA_SDOUT

AUD_SDI_R

TP_CS4206_DMIC_SCL

HDA_SYNC

AUD_CODEC_MICBIAS

AUD_MIC_INN_L

AUD_MIC_INP_L

AUD_LI_P_L

AUD_LI_P_R

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

CS4206_VCOM

AUD_HP_R_P

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.1MM

GND_AUDIO_HPAMP

AUD_LO1_L_P

AUD_SPDIF_IN_CODEC

CS4206_FLYN

CS4206_FLYC

AUD_LI_COM

AUD_SPDIF_CHIP

AUD_LO1_R_P
AUD_LO1_R_N

CS4206_FN

AUD_GPIO_3

CS4206_FLYP

VBIAS_DAC

HDA_RST_L

AUD_GPIO_2

CS4206_FP

TP_AUD_DMIC_SDA1
TP_AUD_GPIO_1

AUD_SENSE_A

=PP3V3_S0_AUDIO

=PP1V5_S0_AUD_DIG

PP5V_AUDIO_HPAMP

PP4V5_AUDIO_ANALOG

MIN_NECK_WIDTH=0.1MM

AUD_HP_L_P

MIN_LINE_WIDTH=0.1MM

AUD_HP_PORT_REF

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM

AUD_LO1_L_N

TP_AUD_LO2_N_L

TP_AUD_LO2_N_R

62 OF 110

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051-8115

56 OF 98

5

56 57 60 61 62

56 57 60 62

56 57 60 62

57 61

56 57 60 61 62

56

56

56

59 95

56 57 60 61 62

95

97

56

56

56

91

56 57 60 61 62

56

91

6

www.vinafix.vn

PGND

SGND

PVSS

THM_PAD

PVDD

SVDD

BIAS

OUTL

OUTR

C1P
C1N

SVDD2
INL­INL+

INR-

INR+

SHDN*

IN

IN

IN

IN

IN
IN

IN
IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

FC = 3.62 HZ
NET RIN = 18K OHMS

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

CODEC Nom SE RIN = 20K OHMS

2

1

C6354

1UF

10%
10V
X5R
402-1

2

1

C6352

402-1

X5R

10V

10%

1UF

2

1

C6356

X5R

10V

10%

1UF

402-1

2

1

C6355

1UF

10%
10V
X5R
402-1

2

1

C6351

10V

20%

10UF

603

X5R

2

1

C6350

X7R-CERM

402

16V

10%

0.1UF

17

9

13

16

6

5

1

3

10

12

7
8

15

14

2
4

11

U6350

TQFN

CRITICAL

MAX97220AETE

21

L6350

FERR-220-OHM

0402

2

1

R6350

1/16W
MF-LF

402

5%

100K

56 62

56 62

56 62

56 62

57 62

57 62

57 62

57 62

56

57 62

57 62

57 60

57 62

57 62

57 60

57 60

57 60

2

1

C6353

10V

10%

1UF

X5R
402-1

21

R6365

0

1/16W

5%

402

MF-LF

21

C6361

CRITICAL

33UF

CASE-A

TANT

6.3V

20%

21

C6363

33UF

CRITICAL

CASE-A

TANT

6.3V

20%

21

C6373

CRITICAL

20%

6.3V
TANT

CASE-A

33UF

21

C6371

20%

6.3V
TANT

CASE-A

33UF

CRITICAL

21

C6362

SIGNAL_MODEL=EMPTY

220PF

402

CERM

25V

5%

2

1

C6364

SIGNAL_MODEL=EMPTY

220PF

402

CERM

25V

5%

2

1

C6374

SIGNAL_MODEL=EMPTY

220PF

402

CERM

25V

5%

21

C6372

SIGNAL_MODEL=EMPTY

220PF

402

CERM

25V

5%

2 1

C6300

20%
10V

TANT

SM-HF-PL

22UF

CRITICAL

2 1

C6302

SM-HF-PL

20%
10V

TANT

22UF

CRITICAL

2 1

C6303

CRITICAL

22UF

SM-HF-PL

TANT

10V

20%

56

56

56

60

60

56 60 61 62

60

21

R6300

1/16W
MF-LF

402

1%

7.87K

2

1

R6301

MF-LF

402

1/16W

1%

21.5K

2

1

C6301

402

10%
50V
CERM

NOSTUFF

820PF

2

1

R6303

1%
1/16W
MF-LF

10

402

21

R6306

1%

7.87K

402

1/16W
MF-LF

2

1

C6304

402

NOSTUFF

820PF

10%
50V
CERM

2

1

R6305

MF-LF

1/16W

1%

21.5K

402

21

R6361

1%

402

1/16W
MF-LF

10K

21

R6363

1%

MF-LF

402

10K

1/16W

21

R6373

1%

1/16W

402

MF-LF

10K

21

R6371

MF-LF

1/16W

402

10K

1%

2

1

R6364

SIGNAL_MODEL=EMPTY

1%

1/16W

402

7.87K

MF-LF

2

1

R6374

SIGNAL_MODEL=EMPTY

402

MF-LF

1/16W

1%

7.87K

21

R6362

SIGNAL_MODEL=EMPTY

7.87K

1%

402

1/16W
MF-LF

21

R6372

1%

402

1/16W

7.87K

MF-LF

SIGNAL_MODEL=EMPTY

AUDIO: FILTER/BUFFER

SYNC_DATE=01/06/2011

SYNC_MASTER=K60_DAVID

AUD_LI_P_R

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

AUD_LI_RF

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

AUD_LI_COM

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

AUD_LI_GND

AUD_LI_P_L

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

AUD_LI_LF

MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

AUD_LI_R

MAX97220_SGND

MAX97220_INR_P

MAX97220_INL_P

MAX97220_INL_N

MAX97220_OUTL

MAX97220_INR_N

MAX97220_OUTR

PP5V_AUDIO_ISO

MAX97220_INL_P

AUD_GPIO_2

MAX97220_INL_N

GND_AUDIO_ISO

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAX97220_OUTR

MAX97220_OUTL

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

GND_AUDIO_ISO

MAX97220_C1N

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.2MM

AUD_LI_L

MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

MAX97220_PVSS

VOLTAGE=0V

MAX97220_INR_N

MIN_NECK_WIDTH=0.2MM

MAX97220_C1P

MIN_LINE_WIDTH=0.4MM

GND_AUDIO_ISO

MAX97220_SHDN_L

MAX97220_INR_P

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAX97220_BIAS

AUD_LO1_R_C_N

AUD_LO1_R_N

AUD_LO1_R_C_P

AUD_LO1_R_P

AUD_LO1_L_C_P

AUD_LO1_L_P

AUD_LO1_L_C_N

AUD_LO1_L_N

GND_AUDIO_ISO

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56 57 60 62

62

62

62

62

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IN

REG_OUT

PLIMIT

FSEL

SD*

PVCCL

AGND

PGND

THRM

GAIN1

GAIN0

LINP

LINN

RINN

RINP

AVCC

NC

PVCCR

OUTNL

OUTPL

BSNL

BSPL

BSNR

OUTNR

OUTPR

BSPR

PBTL

PAD

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FC_HPF, WOOFERS = ~22.5 HZ (0.068 UF)

FC_HPF, TWEETERS = ~850 HZ (0.0018 UF)

SPEAKER AMP RIN = 104K NOMINAL W/ +15.2 DB GAIN

SPEAKER AMP GAIN = +15.2 DB

R6402 = HIGH = 400 KHZ

APPLE P/N 353S3069

RIGHT CH SPEAKER AMP

21

R6400

MF-LF

402

1/16W

5%

0

6

59

21

L6404

SIGNAL_MODEL=EMPTY

CRITICAL

220-OHM-25%-2.5A

0603

21

L6405

SIGNAL_MODEL=EMPTY

0603

CRITICAL

220-OHM-25%-2.5A

21

L6406

CRITICAL

SIGNAL_MODEL=EMPTY

220-OHM-25%-2.5A

0603

21

L6407

SIGNAL_MODEL=EMPTY

220-OHM-25%-2.5A

0603

CRITICAL

33

30

9
8

6

15

14

27

26

7

23

18

11

17

24

19

22

10

29

28

13

12

32

1

3

2

31

16

25

20

21

4

5

U6400

CRITICAL

QFN

TPA3117D2

2

1

C6421

SIGNAL_MODEL=EMPTY

NP0-C0G

25V

5%

1000PF

CRITICAL

402

2

1

C6419

SIGNAL_MODEL=EMPTY

25V
NP0-C0G
402

1000PF

5%

CRITICAL

2

1

C6420

SIGNAL_MODEL=EMPTY

5%

1000PF

402

NP0-C0G

25V

CRITICAL

2

1

C6422

SIGNAL_MODEL=EMPTY

5%

1000PF

402

NP0-C0G

25V

CRITICAL

2

1

R6401

MF-LF

1/16W

5%

100K

402

2

1

C6412

5%

100PF

CERM

50V
402

NOSTUFF

21

R6408

1%

MF-LF

10

1/16W

402

21

C6415

603

20%
25V
X5R

0.22UF

2

1

C6417

20%

402

X5R-CERM

10V

2.2UF

21

R6409

5%

402

MF-LF

1/16W

0

2

1

R6410

1%

402

MF-LF

1/16W

10K

NOSTUFF

2

1

C6406

16V
TANT
D-HF

20%

CRITICAL

100UF

2

1

C6407

20%

100UF

D-HF

TANT

16V

CRITICAL

56 62

56 62

2

1

R6406

0

5%
1/16W
MF-LF
402

2

1

R6407

NOSTUFF

0

5%
1/16W
MF-LF
402

2

1

R6404

402

MF-LF

1/16W

5%

0

NOSTUFF

2

1

R6405

402

MF-LF

1/16W

5%

0

2

1

R6402

MF-LF

402

1/16W

0

5%

2

1

R6403

0

5%
1/16W
MF-LF
402

21

C6408

0.0018UF

50V
402

10%

CERM

21

C6409

CERM

0.0018UF

50V
402

10%

21

C6416

25V
X5R

0.22UF

603

20%

21

C6411

X5R

0402

25V

10%

0.068UF

21

C6410

X5R

25V

10%

0402

0.068UF

21

C6413

25V
X5R

20%

603

0.22UF

21

C6414

603

X5R

0.22UF

20%
25V

2

1

C6401

0.1UF

10%
X5R

25V
402

2

1

C6400

25V
X5R

10%

805

10UF

21

L6400

FERR-1000-OHM

0402

2

1

C6404

0.1UF

402

X5R

10%
25V

21

L6401

0402

FERR-1000-OHM

21

L6402

FERR-1000-OHM

0402

21

L6403

0402

FERR-1000-OHM

2

1

C6402

0.1UF

10%

402

X5R

25V

2

1

C6403

10%
X5R

25V
603-1

1UF

2

1

C6405

603-1

1UF

10%
X5R

25V

56 62

56 62

56

60 62

60 62

60 62

60 62

59

2

1

C6418

10%
10V
X5R
402

1UF

SYNC_DATE=01/06/2011

AUDIO: SPEAKER AMP_1

SYNC_MASTER=K60_DAVID

MIN_NECK_WIDTH=0.25MM

AUD_RAMP_OUTNL

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_OUTPL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_GAIN1

=PP12V_S0_AUDIO_SPKRAMP

AUD_RAMP_RINC_P

AUD_RAMP_RIN_P

AUD_RAMP_RINC_N

AUD_RAMP_RIN_N

AUD_RAMP_LINC_N

AUD_RAMP_LIN_N

AUD_RAMP_LINC_P

AUD_RAMP_LIN_P

AUD_RAMP_FSEL

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_RWFR_OUT_N

AUD_RAMP_BSPR

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

AUD_RAMP_GAIN0

AUD_RAMP_OUTPR

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LO2_R_N

AUD_HP_R_N

AUD_LO2_R_P

AUD_SPKRAMP_MUTE_L

AUD_RAMP_PBTL

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM

AUD_RAMP_REG_OUT

=PP3V3_S0_AUDIO

VOLTAGE=5V

PP5V_RAMP_VREG

AUD_GPIO_3

AUD_SPKR_RTWT_OUT_N

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BSPL

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BSNL

AUD_SPKR_RTWT_OUT_P

AUD_RAMP_PLIMIT

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_OUTNR

MIN_NECK_WIDTH=0.25MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BSNR

AUD_HP_R_P

64 OF 110

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051-8115

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62 62

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62 62

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IN

REG_OUT

PLIMIT

FSEL

SD*

PVCCL

AGND

PGND

THRM

GAIN1

GAIN0

LINP

LINN

RINN

RINP

AVCC

NC

PVCCR

OUTNL

OUTPL

BSNL

BSPL

BSNR

OUTNR

OUTPR

BSPR

PBTL

PAD

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LEFT CH SPEAKER AMP

APPLE P/N 353S3069

SPEAKER AMP RIN = 104K NOMINAL W/ +15.2 DB GAIN

SPEAKER AMP GAIN = +15.2 DB

R6502 = LOW = 300 KHZ

FC_HPF, TWEETERS = ~850 HZ (0.0018 UF)
FC_HPF, WOOFERS = ~22.5 HZ (0.068 UF)

21

L6501

0402

FERR-1000-OHM

21

L6500

0402

FERR-1000-OHM

2

1

C6517

2.2UF

10V
402

20%
X5R-CERM

21

R6509

0

1/16W
MF-LF

5%

402

2

1

R6510

MF-LF

1%

402

10K

1/16W

NOSTUFF

2

1

C6518

402

X5R

10V

10%

1UF

21

R6508

10

1%
1/16W
MF-LF

402

6

58

2

1

C6500

10UF

10%

805

X5R

25V

2

1

C6501

0.1UF

25V
X5R

10%

402

33

30

9
8

6

15

14

27

26

7

23

18

11

17

24

19

22

10

29

28

13

12

32

1

3

2

31

16

25

20

21

4

5

U6500

CRITICAL

TPA3117D2

QFN

21

C6516

0.22UF

20%
X5R

25V
603

21

C6515

0.22UF

X5R

25V

20%

603

21

C6514

25V

0.22UF

X5R
603

20%

21

C6513

603

20%
X5R

25V

0.22UF

21

L6506

0603

CRITICAL

220-OHM-25%-2.5A

SIGNAL_MODEL=EMPTY

56 62

21

L6507

0603

CRITICAL

SIGNAL_MODEL=EMPTY

220-OHM-25%-2.5A

2

1

C6519

CRITICAL

5%

1000PF

402

NP0-C0G

25V

SIGNAL_MODEL=EMPTY

21

L6504

0603

220-OHM-25%-2.5A

CRITICAL

SIGNAL_MODEL=EMPTY

21

L6505

0603

CRITICAL

220-OHM-25%-2.5A

SIGNAL_MODEL=EMPTY

2

1

C6520

CRITICAL

25V

NP0-C0G

402

1000PF

5%

SIGNAL_MODEL=EMPTY

2

1

C6521

402

CRITICAL

1000PF

5%
25V
NP0-C0G

SIGNAL_MODEL=EMPTY

2

1

C6522

25V

NP0-C0G

402

1000PF

5%

CRITICAL

SIGNAL_MODEL=EMPTY

2

1

C6502

X5R

0.1UF

25V
402

10%

2

1

C6503

25V
X5R

10%

603-1

1UF

2

1

C6504

25V

10%
X5R

402

0.1UF

56 62

2

1

C6505

X5R

25V

10%

1UF

603-1

60 62

60 62

60 62

60 62

58

2

1

C6507

100UF

D-HF

TANT

16V

CRITICAL

20%

2

1

C6506

20%

100UF

D-HF

16V

CRITICAL

TANT

56 62

56 62

2

1

R6503

0

5%
1/16W
MF-LF
402

2

1

R6507

NOSTUFF

0

5%
1/16W

402

MF-LF

2

1

R6505

402

5%

0

1/16W
MF-LF

2

1

R6506

0

5%
1/16W
MF-LF
402

2

1

R6504

402

MF-LF

1/16W

5%

0

NOSTUFF

2

1

R6502

5%

MF-LF

402

0

1/16W

21

C6508

0.0018UF

402

CERM

50V

10%

21

C6509

10%
50V

CERM

402

0.0018UF

21

C6511

10%

0402

X5R

25V

0.068UF

21

C6510

0402

10%
25V

0.068UF

X5R

21

L6503

FERR-1000-OHM

0402

21

L6502

FERR-1000-OHM

0402

SYNC_DATE=01/06/2011

SYNC_MASTER=K60_DAVID

AUDIO: SPEAKER AMP

AUD_HP_L_P

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_OUTPR

AUD_LO2_L_N

AUD_HP_L_N

AUD_LO2_L_P

AUD_LAMP_REG_OUT

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_BSPL

AUD_LAMP_GAIN1

=PP3V3_S0_AUDIO

AUD_LAMP_BSNR

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

AUD_LAMP_FSEL

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_LAMP_GAIN0

=PP12V_S0_AUDIO_SPKRAMP

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

AUD_LAMP_OUTNR

AUD_LAMP_BSNL

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

AUD_LAMP_PBTL

AUD_LAMP_OUTPL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

AUD_LAMP_OUTNL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_PLIMIT

AUD_SPKRAMP_MUTE_L

VOLTAGE=5V

PP5V_LAMP_VREG

AUD_LAMP_LIN_P

AUD_LAMP_LINC_P

AUD_LAMP_LINC_N

AUD_LAMP_RINC_N

AUD_LAMP_RINC_P

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_BSPR

AUD_LAMP_LIN_N

AUD_LAMP_RIN_N

AUD_LAMP_RIN_P

65 OF 110

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62

62

62

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IN

OUT

IN

IN

IN
IN
IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

INTERNAL MIC CON

APPLE P/N 518S0677

WOOFER (BR)

TWEETER (FR)

APPLE P/N 518S0656

APPLE P/N 518S0748

SPEAKER CABLE CONNECTORS

PROPERTIES FOR ALL SPKR NETS

APPLE P/N 518S0723

REMOTE I/O CONNECTOR

AUD_LI_GND_JACK

AUD_HP_GND_JACK

PP3V3_AUDIO_SPDIF_JACK

PROPERTIES FOR ALL SPKR NETS

WOOFER (BL)

TWEETER (FL)

NC

21

L6604

0402

FERR-1000-OHM

2

1

DZ6605

6.8V-100PF

402

CRITICAL

2

1

DZ6609

402

CRITICAL

6.8V-100PF

21

L6614

0402

FERR-1000-OHM

2

1

DZ6607

6.8V-100PF

402

CRITICAL

56 91

61

6

56 58 59 61
62

58 62

58 62

58 62

58 62

59 62

59 62

59 62

59 62

2

1

C6601

10V
X5R

10%

0.47UF

402

21

L6607

0402

FERR-1000-OHM

57

21

L6608

0402

FERR-1000-OHM

57

21

L6609

0402

FERR-1000-OHM

56 57 61 62

62

56 57 62

61 62

2

1

DZ6612

6.8V-100PF

402

CRITICAL

2

1

DZ6610

CRITICAL

402

6.8V-100PF

2

1

DZ6603

CRITICAL

6.8V-100PF

402

2

1

C6600

10V
X5R

1UF

10%

402-1

21

L6615

0402

FERR-1000-OHM

21

L6605

FERR-1000-OHM

0402

21

R6601

1/16W

402

MF-LF

22

5%

83 91 97

61

21

L6606

FERR-1000-OHM

0402

21

L6612

FERR-1000-OHM

0402

61

57

21

R6617

1/10W

5%

0

603

MF-LF

5

4

3

2

1

J6603

M-RT-SM

78048-0573

CRITICAL

4

3

2

1

J6602

M-RT-SM

78048-0473

CRITICAL

21

L6610

10-OHM-1A

0402

CRITICAL

2

1

DZ6606

SOD882

CRITICAL

ESDALC5-1BM2

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J6600

F-RT-SM

20143-020E-20F

CRITICAL

57

57

61 62

61 62

21

L6602

FERR-1000-OHM

0402

2

1

DZ6600

SIGNAL_MODEL=EMPTY

CRITICAL

402

6.8V-100PF

2

1

DZ6601

CRITICAL

SIGNAL_MODEL=EMPTY

6.8V-100PF

402

2

1

R6600

0

402

1/16W
MF-LF

5%

3

2

1

5

4

J6601

53780-8603

CRITICAL

M-RT-SM

21

L6600

FERR-1000-OHM

0402

21

L6616

FERR-120-OHM-1.5A

0402

CRITICAL

21

L6618

FERR-120-OHM-1.5A

CRITICAL

0402

2

1

C6604

402

CERM

16V

10%

0.01UF

2

1

C6608

CERM

16V

10%

0.01UF

402

2

1

C6611

0.01UF

10%
16V
CERM
402

2

1

C6613

0.01UF

10%
16V
CERM
402

2

1

C6615

0.01UF

10%
16V
CERM
402

2

1

C6614

402

CERM

16V

10%

0.01UF

SYNC_DATE=01/06/2011

SYNC_MASTER=K60_DAVID

Audio: MLB to I/O Conn.

MAX97220_OUTR

MAX97220_OUTL

AUD_MIC1_IN_N

AUD_SPKR_RWFR_OUT_N

AUD_SPKR_LWFR_OUT_P
AUD_SPKR_LWFR_OUT_N

NO_TEST

NC_J6702_3

AUD_SPKR_LTWT_OUT_P
AUD_SPKR_LTWT_OUT_N

AUD_SPKR_RTWT_OUT_P

AUD_SPKR_RWFR_OUT_P

AUD_SPDIF_IN

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

AUD_LI_GND

=PP3V3_S0_AUDIO

MIN_NECK_WIDTH=0.1MM

AUD_IP_PERPH_DET

MIN_LINE_WIDTH=0.2MM

AUD_LI_TIP_DET

AUD_SPKR_RTWT_OUT_N

AUD_HP_TYPE

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

AUD_MIC1_IN_P

AUD_MIC_IN1_CONN_N

AUD_MIC_IN1_CONN_P

VOLTAGE=0V

GND_AUDIO_MIC1_CONN

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

AUD_SPDIFIN_JACK

AUD_LI_R

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

HS_MIC_HI

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

AUD_HP_TIP_DET

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

GND_AUDIO_ISO

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

AUD_LI_L

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_LI_L_JACK

MIN_LINE_WIDTH=0.4MM

VOLTAGE=3.3V

PP3V3_AUDIO_SPDIF_JACK

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_GND_DET_JACK

AUD_LI_DET_JACK

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_LI_GND_JACK

AUD_HP_R_JACK

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_HP_TIPDET_JACK

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_HP_TYPEDET_JACK

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_IP_PERPH_JACK

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_LI_R_JACK

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_HP_L_JACK

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_SPDIF_OUT

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_HP_GND_JACK

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

HS_MIC_HI_JACK

66 OF 110

11.1.0

051-8115

60 OF 98

62

62

98

98

95 98

98

98

98

98

98

98

98

98

98

98

www.vinafix.vn

G

S

D

G

S

D

G

S

D

OUT

IN

IN

IN

IN

IN

IN

G

S

D

IN

IN

G

S

D

G

S

D

IN

G

S

D

G

S

D

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(DETECT C)(DETECT D)

Digital Out

(DETECT B)

LI Insert Detect

IPHS HS Detect Debounce CKT

DP Audio Enable

NC

Headphone Out

NC

Internal Microphone Impedance Matching

1

2

6

Q6700

SOT-563-HF

NTZD3154NT1H

1

2

6

Q6702

NTZD3154NT1H

SOT-563-HF

4

5

3

Q6702

NTZD3154NT1H

SOT-563-HF

2

1

R6790

5%
MF-LF

402

1/16W

10K

2

1

R6795

1/16W

5%

MF-LF

402

100K

2

1

R6794

402

MF

1/16W

0.1%

CRITICAL

20K

20 97

21

R6799

MF-LF

5%

0

402

1/16W

2

1

C6797

16V

10%

402

X5R

0.1UF

NOSTUFF

21

R6796

5%

402

MF-LF

1/16W

0

2

1

R6701

402

1%

10K

MF-LF

1/16W

56 61

60

60

56 61

60

56 61

2

1

R6798

100K

MF-LF

5%

1/16W

402

4

5

3

Q6701

NTZD3154NT1H

SOT-563-HF

2

1

R6797

5%
1/16W

402

MF-LF

10K

21

R6700

402

1/16W

17.4K

1%

MF-LF

2

1

C6740

16V

0.1UF

10%
X5R

402

60 62

2

1

R6730

1/16W

5%

MF-LF

402

10K

56 61 95

1

2

6

Q6703

NTZD3154NT1H

SOT-563-HF

4

5

3

Q6700

SOT-563-HF

NTZD3154NT1H

2

1

R6762

402

5%
1/16W
MF-LF

10K

61

2

1

R6768

100K

402

MF-LF

5%

1/16W

1

2

6

Q6701

SOT-563-HF

NTZD3154NT1H

4

5

3

Q6703

SOT-563-HF

NTZD3154NT1H

18 83 91

56 57

61

21

R6712

5%

1/16W

0

MF-LF

402

21

R6710

1/16W
MF-LF

5%

402

0

21

R6711

MF-LF

5%

1/16W

0

402

2

1

R6744

MF-LF

1%
1/16W

5.11K

402

2

1

R6792

1%
MF-LF

1/16W

SIGNAL_MODEL=EMPTY

3.40K

402

21

XW6702

SM

60 62

60 62

2

1

C6750

402

25V
X7R

10%

0.0082UF

2

1

R6791

MF-LF
402

1/16W

5%

100K

2

1

R6793

402

MF-LF

1/16W

1%

3.40K

SIGNAL_MODEL=EMPTY

21

C6796

402

X5R

10%

0.1UF

16V

21

C6795

402

16V
X5R

10%

0.1UF

2

1

C6751

TANT

603-HF

6.3V

20%

4.7UF

CRITICAL

21

R6743

2.2K

5%

402

MF-LF

1/16W

56 62

56 62

56

21

L6700

0402

FERR-220-OHM

21

L6701

0402

FERR-220-OHM

NOSTUFF

2

1

C6700

X5R
402

10%
16V

0.1UF

61

61

AUDIO: Detects/Grounding

SYNC_DATE=11/24/2010

SYNC_MASTER=K60_DAVID

AUD_MIC1_IN_N

AUD_MIC1_IN_P

AUD_IP_PERIPHERAL_DET

AUD_HP_TYPE_INV

PP4V5_AUDIO_ANALOG

=PP3V3_S0_AUDIO

=PP3V3_S0_AUDIO

PP5V_AUDIO_ISO

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_HP_TYPE

AUD_MIC_INR_N

AUD_HP_TIP_DET

AUD_CODEC_MICBIAS

AUD_MIC_INR_P

AUD_INTMICBIAS

AUD_Q6701_D6

AUD_SENSE_A

JACK_DET_V_FILT

GND_AUDIO_CODEC JACK_L_RTN_2JACK_L_RTN_1

AUD_Q6702_D3

GND_AUDIO_CODEC

AUD_LI_TIP_DET_INV

AUD_IP_PERPH_DET_DB

DP_GPU_T29_SEL

GND_AUDIO_CODEC

AUD_MIC1_IN_G

JACK_DET_V_FILT

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

AUD_IP_PERPH_DET

GND_AUDIO_CODEC JACK_L_RTN_0

AUD_SENSE_A

PP4V5_AUDIO_ANALOG

AUD_IP_PERPH_DET_INV

AUD_IP_PERPH_DET_R

AUD_LI_TIP_DET

AUD_HP_TIP_DET_INV

GND_AUDIO_CODEC

AUD_IP_PER_DEB

AUD_SENSE_A

JACK_DET_V_FILT

JACK_DET_V_FILT

67 OF 110

11.1.0

051-8115

61 OF 98

56 61 95

6

56 58 59 60 61 62

6

56 58 59 60 61 62

56 57 60 61 62

56 57 60 61 62

56 57 60 61 62

56 57 60 61 62

56 57 60 61 62

56 57 60 61 62

56 57 60 61 62

www.vinafix.vn

IN

BI

OUT

IN

IN

CS

HDET

AGND

DGND

ENABLE

AVDD

SDA

BYPASS

DETECT

MICBIAS

INT*

SCL

OUT

OUT

IN

2E

1E

1Y 1Z

2Z

GND

VCC

2Y

OUT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

WRITE: 0X72 READ: 0X73

PHYSICAL

APN 353S2640

FHP = 80 HZ

FLP = 8.82 KHZ

PIN COMPLEX

ENABLE/CONTROL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

LINE IN
SPDIF IN
INTERNAL MIC
EXTERNAL MIC

FUNCTION

SPDIF OUT

0X02 (2)

0X04 (4)

N/A

0X03 (3)

0X06 (6)

0X04 (4)

0X08 (8)

0X02 (2)

0X03 (3)

CONVERTER

0X06 (6)

0X05 (5)

0X0D (13,V22,B,LEFT)

0X0E (14,LEFT & RIGHT)

0x0F (15)

0X12 (12,C)

0X0A (10,D)
0X0B (11)

0x10 (16)

0X09 (09)

PIN COMPLEX

GPIO_3
N/A

N/A

N/A

N/A

COUGAR POINT GPIO 5 (RCVR INT)
COUGAR POINT GPIO 3 (PERIPH DET)

DET ASSIGNMENT

0X0D (B)

DET ASSIGNMENT

N/A

N/A

0X12 (C)

N/A

N/A

0X0A (D)

FUNCTION

HP/LINE OUT
PRIMARY SPKRS (WFR)

COUGAR POINT GPIO 16

GPIO_3

GPIO_2

SHDN

CODEC INPUT SIGNAL PATHS

SECONDARY SPKRS (TWT)

CODEC OUTPUT SIGNAL PATHS

0X07 (7)

CONVERTER

VOLUME/MUTE

MIKEY RECEIVER CKT

21

L6800

0402

FERR-1000-OHM

21

R6802

402

MF-LF

1/16W

0

5%

21

R6803

5%
1/16W
MF-LF

402

0

21

R6804

402

MF-LF

5%
1/16W

0

21

R6805

0

5%
MF-LF

402

1/16W

49

49

20 97

21 97

2

1

C6803

CRITICAL

4.7UF

603-HF

20%

6.3V
TANT

6

56 58 59 60 61

2

1

R6812

100K

MF-LF

1/16W

5%

402

21

R6810

MF-LF

1/16W

402

5%

2.2K

2

1

C6806

402

25V
X7R

10%

0.0082UF

21

C6804

402

16V
X5R

10%

0.1UF

21

C6805

0.1UF

10%
X5R

402

16V

2

1

R6806

MF-LF
402

5%
1/16W

10K

2

1

C6800

10%
X5R

1UF

10V
402

2

1

C6801

10%

0.1UF

402

X5R

16V

2

1

R6811

1/16W
MF-LF

0

5%

402

B3

C3

C1

D3

A1

A3

C2

B1

B2

D1

A2

D2

U6806

CRITICAL

WCSP

CD3282A1

56

56

60

8

4

65

3

21

7

U6807

NX3L2G66GD

SOT996-2

2 1

R6814

402

5%

MF-LF

1/16W

0

2

1

C6810

402

10V

1UF

10%
X5R

2

1

C6811

0.1UF

402

10%
X5R

16V

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I213

I214
I215

I216

I217
I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

2 1

R6815

402

5%

MF-LF

1/16W

0

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241
I242

I243

I244

I245

I246

I247

60 61

2

1

R6807

402

5%
1/16W

100K

MF-LF

2 1

R6816

5%
1/16W
MF-LF

402

0

I252

I253
I254

I255

I256
I257

2

1

R6809

2.2K

5%
MF-LF

1/16W
402

2

1

R6808

5%
1/16W
MF-LF

1K

402

2

1

C6802

0.01UF

402

10%
25V
X7R

SYNC_MASTER=K60_DAVID

AUDIO: Mikey

SYNC_DATE=01/06/2011

AUDIODIFF

*

AUDIODIFF

*

SPKROUTDIFF SPKROUTDIFF

*

Y

10 MM

0.2 MM

0.25 MM

0.6 MM

0.2 MM

SPKROUTDIFF

AUDIODIFF

Y

*

0.1 MM

10 MM

0.1 MM

0.1 MM0.1 MM

0.2 MM

SPKROUT

*

?

?

AUDIO

*

0.1 MM

HS_MIC_LO

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

VOLTAGE=0V

GND_AUDIO_CODEC

HS_MIC_LO_SW

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

GND_AUDIO_ISO

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

HS_MIC_HI

HS_RST

HS_SCL

AUDIO

AUD_LO2_R_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_MIC_IN1_CONN_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_MIC_IN1_CONN_N

AUD_MIC1_IN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

SPKROUTDIFF

SPKROUT

AUD_SPKR_LTWT_OUT_N

SPKROUT_DIFFPAIR

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_MIC_INR_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_MIC_INR_P

MIN_LINE_WIDTH=0.15MM

HS_MIC_BIAS

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.3V

PP3V3_S0_HS_F

AUDIO

AUDIODIFF

MAX97220_INR_P

AUDIO_DIFFPAIR

MAX97220_INR_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_SPKR_RWFR_OUT_N

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

SPKROUTDIFF

SPKROUT

AUD_SPKR_LTWT_OUT_P

SPKROUT_DIFFPAIR

=I2C_AUDIO_SCL

HS_SDA
HS_INT_L

AUD_IPHS_SWITCH_EN

AUD_I2C_INT_L

AUD_IP_PERPH_DET

HS_HDET

=I2C_AUDIO_SDA

HS_SW_DET

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

AUD_RAMP_LINC_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_RINC_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO2_L_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_R_P

AUDIO_DIFFPAIR

AUD_RAMP_RINC_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LAMP_LINC_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LAMP_RINC_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LAMP_LIN_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUD_LAMP_RIN_N

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUD_LAMP_RIN_P

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_L_C_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_R_C_P

AUDIO_DIFFPAIR

AUD_LO1_L_C_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

MAX97220_INL_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_R_C_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

MAX97220_INL_N

AUDIO_DIFFPAIR

AUD_SPKR_RTWT_OUT_N

SPKROUT

SPKROUT_DIFFPAIR

SPKROUTDIFF

AUD_SPKR_RTWT_OUT_P

SPKROUT

SPKROUT_DIFFPAIR

SPKROUTDIFF

AUD_SPKR_RWFR_OUT_P

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

AUD_LAMP_LIN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_RIN_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LAMP_LINC_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_RAMP_LIN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_LIN_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_LINC_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUD_LO2_L_N

AUDIO

AUDIO_DIFFPAIR

AUDIO

AUD_LO1_L_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_HP_L_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_L_N

AUDIO_DIFFPAIR

AUD_LAMP_RINC_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_RIN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO2_R_P

AUDIO_DIFFPAIR

AUDIODIFF

AUD_LO1_R_N

AUDIO

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_HP_R_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_HP_L_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_HP_R_P

AUDIO_DIFFPAIR

MIN_LINE_WIDTH=0.15MM

AUD_MIC_INP_L

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

AUD_MIC_INN_L

MIN_NECK_WIDTH=0.1MM

HS_RX_BP

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

=PP3V3_S0_AUDIO

HS_RST

PP3V3_S0_HS_F

AUD_SW_SEL

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

HS_MIC_HI_SW

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

AUD_MIC_INF

GND_AUDIO_CODEC

SPKROUT

AUD_SPKR_LWFR_OUT_N

SPKROUT_DIFFPAIR

SPKROUTDIFF

SPKROUT

AUD_SPKR_LWFR_OUT_P

SPKROUT_DIFFPAIR

SPKROUTDIFF

AUD_MIC1_IN_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

68 OF 110

11.1.0

051-8115

62 OF 98

56 57 60 61 62

56 57 60

62

56 58

60

60

60 61

59 60

56 61

56 61

62 95

57

57

58 60

59 60

58

58

56 59

56 57

58

59

59

59

59

59

57

57

57

57

57

57

58 60

58 60

58 60

59

58

59

58

58

58

56 59

56 57

56 59

56 57

59

58

56 58

56 57

56 58

56 59

56 58

62

62 95

56 57 60 61 62

59 60

59 60

60 61

www.vinafix.vn

08

08

G

S

D

08

08

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OPTION TO DELAY 1V05

OPTION TO DELAY 1V8

Enable regulator

PLACE TOP SIDE
REWORK TO POWER UP WITH NO CPU

SLP_S4 ENABLES

OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:

OPTIONAL SEQUENCE TO DELAY 3V,1V5

Enable FET

Enable regulator

SLP_S3 ENABLES

MEMVTT_EN SEQUENCE

NOTE: PM_PGOOD_P1V05_S0_REG ENABLES VCCSA REGULATOR CIRCUIT ON PAGE 70

Enable FET

Enable regulator

TO ENABLE OF CPU VCORE

CPUVTT VREG/

VCCSA REGULATOR

ENABLE REGULATOR

Enable FET

Enable FET

PCH CORE

PP1V8_S0 VREG (CPU PLL)

21

R6946

MF-LF

402

33

5%

1/16W

NOSTUFF

2

1

R6916

MF-LF

5%

100K

402

1/16W

2

1

R6915

402

10K

MF-LF

1/16W

5%

14

8

9

10

7

U6900

TSSOP-HF

74LVC08

14

3

2

1

7

U6900

74LVC08

TSSOP-HF

2

1

R6917

10K

1/16W
402

MF-LF

NOSTUFF

5%

2

1

C6944

NOSTUFF

402

0.47UF

6.3V
CERM-X5R

10%

2

1

R6944

33

1/16W
MF-LF

5%

402

NOSTUFF

2 1

C6910

0.1UF

CERM

402

10V

20%

2

1

C6921

6.3V

NOSTUFF

0.47UF

CERM-X5R
402

10%

2

1

C6920

10%

6.3V

402

CERM-X5R

0.47UF

NOSTUFF

2

1

C6946

NOSTUFF

10%

6.3V
CERM-X5R
402

0.47UF

2

1

C6945

NOSTUFF

0.47UF

6.3V
CERM-X5R

10%

402

2

1

C6924

0.47UF

10%

6.3V

402

CERM-X5R

NOSTUFF

2

1

C6947

CERM-X5R

NOSTUFF

10%

6.3V

402

0.47UF

2

1

C6952

NOSTUFF

6.3V

10%

402

0.47UF

CERM-X5R

1

6

2

Q6911

MMDT3904-X-G

SOT-363-LF

2

1

C6951

NOSTUFF

5%

402

CERM

100PF

50V

2

1

R6951

10K

402

1/16W
MF-LF

5%

4

3

5

Q6911

MMDT3904-X-G

SOT-363-LF

2

1

C6953

10%
X5R

402

16V

NOSTUFF

0.1UF

21

R6950

5%
1/16W
MF-LF

402

10K

2

1

R6952

10K

402

1/16W
MF-LF

5%

2

1

3

Q6910

2N7002

SOT23-HF1

21

R6990

1/16W

5%

33

402

MF-LF

NOSTUFF

2

1

C6994

NOSTUFF

CERM-X5R

6.3V

10%

402

0.47UF

2

1

C6942

NOSTUFF

402

CERM

6.3V

10%

1UF

21

R6942

1/16W

5%

33

402

MF-LF

NOSTUFF

21

R6972

NOSTUFF

5%
1/16W
MF-LF

402

0

21

R6971

MF-LF

1/16W

5%

402

0

14

6

5

4

7

U6900

TSSOP-HF

74LVC08

14

11

12

13

7

U6900

74LVC08

TSSOP-HF

21

R6970

0

1/16W

5%

MF-LF

402

21

R6955

1/16W

5%

402

10K

MF-LF

21

R6930

1/16W

5%

33

402

MF-LF

21

R6931

NOSTUFF

1/16W

5%

33

402

MF-LF

21

R6932

1/16W
MF-LF

402

33

5%

21

R6933

MF-LF

402

5%

1/16W

33

2

1

R6934

MF-LF
402

1/16W

5%

82K

2

1

R6935

33K

5%
MF-LF

1/16W
402

21

R6936

1/16W
MF-LF

402

33

5%

73 97

63 73 97

2

1

R6941

1/16W

5%

402

10K

MF-LF

NOSTUFF

2

1

C6941

0.47UF

NOSTUFF

10%

402

CERM-X5R

6.3V

21

R6911

1/16W

33

402

MF-LF

5%

21

R6912

402

5%

MF-LF

33

1/16W

21

R6947

MF-LF

402

33

5%

1/16W

POWER SEQUENCING ENABLES

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

PM_EN_P1V5_S0_FET

PM_EN_P12V_S0_FET

=PP3V3_S0_PWRCTL

=PP3V3_S5_PWRCTL

PM_EN_DDR1V5_S3_REG

PM_EN_P3V3_S0_FET

PM_EN_DDRVTT_S0_REG

PM_SLP_S4_L

PM_PGOOD_P5V_S3_REG

PM_SLP_S4_1_L_R

PM_SLP_S5_L

CPU_SKTOCC

S4_ENABLES

PM_EN_P5V_S3_REG

PM_PGOOD_P1V05_S0_REG

PM_SLP_S4_L

=PP3V3_S5_PWRCTL

CPUVTT_REG_PGOOD_R

CPU_SKTOCC_L

VTT_REG_PGOOD_L

PM_PGOOD_PVCCSA_S0_REG

MAKE_BASE=TRUE

PM_PGOOD_P1V05_S0_REG
MAKE_BASE=TRUE

P3V3_S5_PWRCTL_U6900_R

=PM_EN_VCCSA_S0_CPU

PM_EN_PVCORE_CPU

PM_SLP_S3_BUF_L

PM_PGOOD_P5V_S0_FET

=PP3V3_S5_PWRCTL

PM_EN_DDRVTT_S0_REG

PM_PGOOD_P5V_S0_FET

=PP12V_S0_PWRCTL

=PP3V3_S5_PWRCTL

PM_PGOOD_DDR1V5_S3_REG

PM_SLP_S3_L

PM_EN_USB_PWR

PM_PGOOD_P5V_S3_REG

PM_EN_P3V3_S0_FET

PM_EN_P5V_S0_FET

PM_PGOOD_P5V_S0_FET

PM_EN_P1V5_S0_FET

PM_PGOOD_P3V3_S0_FET

PM_EN_P1V5_S0_FET

PM_EN_P3V3_S3_FET

=PP3V3_S5_PWRCTL

PM_PGOOD_P3V3_S0_FET

PM_PGOOD_P5V_S0_FET

PM_EN_P1V05_S0_REG

PM_EN_P1V8_S0_REG

PM_PGOOD_P3V3_S0_FET

PGOOD_P12V_S0

69 OF 110

11.1.0

051-8115

63 OF 98

63 73 97

6

97

6

64 73 80

6

11 63 64

71 97

63 73 97

32 63 71 97

5

19 32 46 47 63 97

63 70 82 97

97

5

19 46 47 97

91

97

70 97

63 64
68 97

5

19 32 46 47 63 97

6

11 63 64

97

11 97

64 97

63 64 68 97

65 97

97

63 64 73 97

6

11 63 64

32 63 71 97

63 64 73 97

6

64 80

6

11 63 64

5

71 97

5

19 26 32 36 46 47 82 97

43 91 63 70 82 97

63 64 73 97

63 73 97

63 64 73 97

63 73 97

73 97

6

11 63 64

63 64 73 97

63 64 73 97

68 97

71 97

63 64 73 97

64 97

www.vinafix.vn

OUT

OUT

08

08

08

08

08

GND

V+

G

D

S

G

D

S

GND

V+

08

08

G

S

D

08

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SMC

OPTION FOR SMC TO OUPUT
DELAYED PWRGD (BY 99MS)

VCCSA POWERGOOD

PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0

PULL-UP ON MXM PAGE

TO BE DRIVEN BY SAME SIGNAL

OPTION FOR PCH PWROK AND SYSPWROK

ALL_SYS_PWRGD CIRCUIT

VCCSA ENABLE SIGNAL

DELAY IS ABOUT 200MS

To SMC (2)

WHICH GOES INTO RSMRST_L OF PCH

FROM THIS SMC GENERATES PM_RSMRST_L

(1.67V/1.22V; 132mV Hysteresis)

(9V/9.58V; 580mV Hysteresis)

S0 RAILS PGOOD

46 97

2

1

C7022

20%

CERM

0.1UF

10V

402

2

1

R7050

1/16W

402

5%

MF-LF

1K

NOSTUFF

2

1

C7059

10%

0.1UF

402

X5R

16V

NOSTUFF

2

1

R7007

1%

49.9K

402

1/16W
MF-LF

21

R7022

33

5%
1/16W
MF-LF

402

NOSTUFF

21

R7023

1/16W

5%

33

402

MF-LF

5

32 97

2

1

R7020

1%

402

1/16W
MF-LF

64.9K

2

1

R7021

1%

10K

1/16W
MF-LF
402

21

R7002

1%

1/16W

402

2.0K

MF-LF

2

1

R7017

402

10K

5%
1/16W
MF-LF

2

1

R7018

5%
1/16W
MF-LF
402

10K

14

6

5

4

7

U7000

TSSOP-HF

74LVC08

14

8

9

10

7

U7050

74LVC08

TSSOP-HF

14

11

12

13

7

U7000

TSSOP-HF

74LVC08

14

3

2

1

7

U7050

TSSOP-HF

74LVC08

21

R7054

402

5%

MF-LF

1/16W

0

4

3

5

Q7011

SOT-363-LF

MMDT3904-X-G

1

6

2

Q7011

MMDT3904-X-G

SOT-363-LF

21

R7028

33

1/16W
MF-LF

402

5%

2

1

C7023

10%

NOSTUFF

0.47UF

CERM-X5R

6.3V
402

2

1

R7031

100K

5%
MF-LF

402

1/16W

2

1

R7061

MF-LF
402

1/16W

10K

5%

21

R7060

MF-LF

5%

0

402

1/16W

14

11

12

13

7

U7050

TSSOP-HF

74LVC08

21

R7029

MF-LF

402

0

5%

1/16W

21

R7032

MF-LF

5%

1/16W

402

33

2

1

C7080

603

CERM

16V

20%

0.1UF

2

1

R7086

1/16W

10K

MF-LF
402

5%

2

1

R7084

MF-LF
402

10K

1/16W

5%

2

1

R7083

1%

402

MF-LF

1/16W

49.9K

8

1

3

2

4

U7080

SOI-HF

CRITICAL

LM393

2

1

R7080

1/16W
MF-LF

33.2K

1%

402

2

1

R7081

402

1%

MF-LF

100K

1/16W

21

R7082

1%

MF-LF

402

2.0K

1/16W

1

2

6

Q7080

SOT-363

2N7002DW-X-G

4

5

3

Q7080

SOT-363

2N7002DW-X-G

8

7

5

6

4

U7080

LM393

CRITICAL

SOI-HF

14

3

2

1

7

U7000

74LVC08

TSSOP-HF

21

R7063

MF-LF

33

5%

402

1/16W

2

1

C7066

10%

NOSTUFF

X5R

16V
402

0.1UF

2

1

R7092

MF-LF

1/16W

10K

5%

402

4

3

5

Q7090

SOT-363-LF

MMDT3904-X-G

21

R7093

MF-LF

1/16W

5%

402

10K

2

1

R7091

1/16W
MF-LF

10K

5%

402

1

6

2

Q7090

MMDT3904-X-G

SOT-363-LF

2

1

C7091

16V
402

NOSTUFF

X5R

10%

0.1UF

21

R7090

1K

1/16W
MF-LF

5%

402

21

R7078

33

MF-LF

402

1/16W

5%

21

R7079

MF-LF

402

5%

1/16W

33

2

1

C7050

CERM

20%
10V

402

0.1UF

14

8

9

10

7

U7000

74LVC08

TSSOP-HF

2

1

3

Q7010

SOT23-HF1

2N7002

2

1

C7061

0.1UF

16V
X5R
402

NOSTUFF

10%

21

R7094

5%

MF-LF

1/16W

33

402

21

R7099

33

402

1/16W
MF-LF

5%

NOSTUFF

14

6

5

4

7

U7050

74LVC08

TSSOP-HF

21

R7035

33

1/16W

5%

MF-LF

402

21

R7066

402

1/16W
MF-LF

5%

0

2

1

R7067

10K

1/16W

402

5%

MF-LF

2

1

C7055

10%

NOSTUFF

0.47UF

CERM-X5R

6.3V
402

2

1

C7056

402

6.3V

0.47UF

NOSTUFF

10%
CERM-X5R

21

R7024

402

5%

MF-LF

1/16W

0

NOSTUFF

21

R7030

0

1/16W
MF-LF

5%

402

21

R7052

33

5%

402

MF-LF

1/16W

NOSTUFF

21

R7053

33

1/16W

5%

MF-LF

402

NOSTUFF

POWER SEQUENCING PGOOD

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_PGOOD_P1V05_S0_REG

PM_PGOOD_P5V_S0_FET

PGOOD_CPU_UNCORE

PGOOD_CPU_S0

PM_PGOOD_P1V8_S0_REG

PM_PGOOD_PVCORE_CPU

PGOOD_P1V8_S0

=PP3V3_S0_PWRCTL

=PP3V3_S0_PWRCTL

PM_PGOOD_P3V3_S0_FET

PM_PGOOD_CK505

PM_PGOOD_P1V5_S0_FET

=PP3V3_S0_PWRCTL

=PP12V_S5_PWRCTL

PGOOD_1V8_S0_G2

=PP12V_S0_PWRCTL

PGOOD_1V8_S0_G1

VCCSAPG_1

PVCCSA_L

PVCCSA_R_L

PGOOD_12V_S0_G1

=PP3V3_S0_PWRCTL

=PP12V_S0_PWRCTL

1V60_COMP_REF

PVCCSA_EN_L

=PP12V_S5_PWRCTL

PGOOD_12V_S0_G2

=PP3V3_S0_PWRCTL

=PPVCCSA_S0_PWRCTL

PGOOD_P12V_S0

=PP1V8_S0_PWRCTL

=PP3V3_S0_PWRCTL

9V_COMP_REF

12V_COMP_REF

=PM_EN_VCCSA_S0_CPU

PGOOD_5V_1V05_3V3

PM_PGOOD_PVCCSA_S0_REG

PM_PGOOD_P1V5_S0_FET

PGOOD_3V3_1V05

1V80_COMP_REF

PM_PGOOD_PVCCSA_S0_REG

=PP3V3_S0_PWRCTL

=PP3V3_S3_PWRCTL

=PP3V3_S0_PWRCTL

PM_EN_PVCCSA_S0_REG_L

VTTS3PG_1

=PP3V3_S0_PWRCTL

=PP3V3_S5_PWRCTL

RSMRST_PWRGD

PM_PGOOD_P3V3_S5_REG

PM_ASW_PWRGD

PM_PCH_PWRGD

PM_PCH_PWRGD_RPGOOD_PCH_S0_R

PGOOD_PCH_S0_R

SMC_DELAYED_PWRGD

PM_SYS_PWRGD

ALL_SYS_PWRGD_R

PM_ASW_PWRGD

PGOOD_PCH_S0

ALL_SYS_PWRGD_SMC

PM_MXM_PGOOD

ALL_SYS_PWRGD

=PP3V3_S0_PWRCTL

=PM_MXM_PGOOD_PULLUP

=PP3V3_S0_MXM

PM_PGOOD_P1V05_S0_REG

PGOOD_PCH_S0

PM_MXM_EN

PGOOD_SYSPWROK

ALL_SYS_PWRGD_SMC

PM_PECI_PWRGD

PGOOD_SYSPWROK_R

SMC_DELAYED_PWRGD

70 OF 110

11.1.0

051-8115

64 OF 98

6

11 63 64

6

63 64 73

80

63 64 68 97

63 73 97

91 97

97

71 97

5

25 65 97

97

6

63 64 73 80

6

63 64 73 80

63 73 97

26

11 64 73 97

6

63 64 73 80

6

33 64 73

6

63 64 80

6

63 64 73 80

6

63 64 80

6

33 64 73

6

63 64 73 80

6

63 97

6

6

63 64 73 80

97

97

63

91 97

63 64 97

11 64 73 97

91 97

63 64 97

6

63 64 73 80

6

73 82

6

63 64 73 80

97

6

63 64 73 80

6

11 63 64

27 70 97

19 64 97

19 21 97

97 64 91 97

64 91 97

47 64 97

19 32 97

19 64 97

5

64 97

46 64 97

76 97

91 97

6

63 64 73 80

76

6

21 75 76

63 64 68 97

5

64 97

76 97

97

46 64 97

46 97

97

47 64 97

www.vinafix.vn

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

OUT

IN

OUT

OUT
BI

IN

IN

IN

IN

IN

VR_RDYS

IMONS

FS_DRP

VCC

ISEN1+

PWM1

ISEN1-

PWM2
ISEN2+
ISEN2-

PWM3

ISEN3-

ISEN3+

TMS

ISEN4-

ISEN4+

PWM4

FSS_DRPS

EN_VTT

RSET

VSENS

RAMP_ADJ

FBS

RGNDS

VR_RDY

COMPS

SVCLK

SVDATA

SVALERT*

VSEN

FB

RGND

PSICOMP

COMP

IMON

VR_HOT*
TM

THRM

ISENS-

ISENS+

PWMS

HFCOMPS/DVCS

EN_PWR

ADDR_IMAXS_TMAX

NPSI_DE_IMAX

BT_FDVID_TCOMP

BTS_DES_TCOMPS

SICI

HFCOMP

PAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CORE/AXG REG 1.1V/75A O/P= PPVCORE_S0_CPU_REG

1.25 mOhm loadline

LOCAL 5V

1.25 mOhm loadline

CPU CORE INPUT FILTER

AVG = 55A

CPU VCORE

PEAK = 75A

VOUT = VCORE

67 95

67 95

67 95

2

1

C7101

X5R

10%

402

16V

0.1UF

VAXG

66 95

66 95

2 1

R7110

402

5%

0

1/16W MF-LF

50 95

21

R7109

MF-LF

402

1/16W

1%

1.02K

VAXG

2

1

C7103

220PF

X7R-CERM

50V

10%

402

21

R7108

110

1%

MF-LF

1/16W

402

VAXG

2

1

C7104

16V
402

X5R

10%

0.1UF

2

1

C7100

10%

220PF

X7R-CERM

50V
402

VAXG

2

1

R7100

0

1/16W
MF-LF
402

5%

NO_VAXG

2

1

C7102

X7R-CERM
402

220PF

10%
50V

VAXG

2

1

R7107

402

0

5%
1/16W
MF-LF

VAXG

2

1

R7103

402

MF-LF

NOSTUFF

0

1/16W

5%

2

1

R7104

0

MF-LF

1/16W

5%

NOSTUFF

402

2

1

R7105

1/16W

5%

NOSTUFF

0

402

MF-LF

2

1

R7106

0

5%
1/16W
MF-LF
402

66 95

66 95

2

1

C7106

16V
X5R

10%

0.1UF

402

2 1

R7112

0

5%

MF-LF

402

1/16W

2

1

C7105

X7R-CERM

220PF

50V

10%

402

66 95

66 95

2 1

R7114

0

402

MF-LF

5%

1/16W

2

1

C7108

16V
402

X5R

0.1UF

10%

2

1

C7107

220PF

X7R-CERM

50V
402

10%

66 95

66 95

66 95

2

1

R7102

NOSTUFF

1/16W

0

5%
MF-LF

402

2

1

R7155

402

MF-LF

1/16W

1%

105K

2

1

C7111

0.1UF

X5R

16V
402

10%

2

1

R7125

1K

402

MF-LF

5%
1/16W

2

1

R7126

13.7K

1%
1/16W
MF-LF
402

2

1

R7101

NOSTUFF

MF-LF

0

5%
1/16W

402

2

1

R7120

1/16W

1%

124K

402

MF-LF

50 95

2

1

R7118

1/16W

1.18M

1%
MF

402

2

1

C7112

402

X5R

16V

10%

0.1UF

PP12V_S0_CPU_FLTRD

2

1

R7122

100K

MF-LF

1/16W

5%

402

2

1

R7123

402

2.74K

1/16W

1%
MF-LF

2

1

R7124

6.65K

1/16W
402

1%
MF-LF

63 97

2

1

R7119

11K

1/16W

402

1%

MF-LF

2

1

C7113

0.1UF

X5R
402

16V

10%

2

1

C7115

0.01UF

20%
16V
CERM
402

NOSTUFF

21

R7141

1.21K

402

MF-LF1/16W

1%

21

C7117

0402

10%

3900PF

X7R

50V

21

C7118

39PF

50V

5%

402

CERM

21

R7132

9.09K

1%

1/16W

402

MF-LF

21

R7130

402

309

1/16W

1%

MF-LF

21

R7129

499

1%

402

MF-LF

1/16W

21

R7128

1%
1/16W
MF-LF

249

402

21

R7131

402

10

1/16W

5%

MF-LF

5

25 64 97

21

R7140

953K

402

1%

1/16W MF-LF

21

R7156

953K

MF-LF

1%

402

1/16W

2

1

R7151

255K

MF-LF

402

1/16W

1%

2

1

R7150

17.8K

1/16W
MF-LF

402

1%

21

R7143

15.0K

1/16W MF-LF

1%

402

2

1

R7149

30.1K

1%
1/16W
MF-LF

402

2

1

R7146

110

MF-LF

1/16W

5%

402

13 95

13 95

13 95

2

1

R7147

MF-LF

1/16W

NOSTUFF

402

1%

90.9

2

1

R7148

1/16W

1%

402

MF-LF

54.9

2

1

C7126

0.1UF

16V
X5R

10%

402

21

R7136

215

MF-LF

1/16W

402

1%

21

R7133

402

402

1/16W

1%

MF-LF

21

R7135

1.3K

1/16W
MF-LF

402

1%

21

C7120

10%
50V

CERM

402

390PF

21

C7122

50V

CERM

402

5%

82PF

21

R7134

249

402

MF-LF

1%

1/16W

21

R7144

MF-LF

2.32K

402

1%

1/16W

2

1

C7124

0.01UF

16V
402

CERM

20%

21

R7121

5%

MF-LF1/16W

10

402

21

R7145

1/16W

1%

402

4.99K

MF-LF

2

1

C7127

10%

402

10V
X5R

27.0NF

2

1

R7153

0

5%

402

1/16W
MF-LF

2

1

R7154

11K

MF-LF

1%

402

1/16W

2

1

R7152

MF-LF

402

5%

1/16W

0

2

1

C7132

X5R

16V

10%

0.1UF

402

21

R7111

1/16W

402

MF-LF

1%

1.02K

21

R7113

MF-LF

1%

1/16W

402

1.02K

21

R7115

402

MF-LF

1%

1/16W

1.02K

2

1

R7158

255K

402

1/16W

1%
MF-LF

21

L7100

TH-VERT-HF

1UH-20A-4.5MOHM

21

R7199

MF-LF

0

402

5%

1/16W

2

1

C7155

SIGNAL_MODEL=EMPTY

NOSTUFF

402

CERM

50V

10%

0.0022UF

21

R7162

10

1/16W

5%

MF-LF

402

21

R7160

1/16W

402

5%

1K

MF-LF

21

R7161

0

MF-LF

402

1/16W

5%

21

XW7120

SM

OMIT

13 95

13 95

2

1

C7157

402

50V
CERM

10%

0.0022UF

2

1

C7156

402

0.0022UF

10%
50V
CERM

21

R7164

MF-LF

1/16W

5%

10

402

21

R7165

5%

402

1K

1/16W
MF-LF

21

R7163

1/16W

5%

MF-LF

0

402

21

XW7130

SM

OMIT

2

1

C7158

SIGNAL_MODEL=EMPTY

NOSTUFF

0.0022UF

402

CERM

50V

10%

21

R7167

10

1/16W

5%

MF-LF

402

21

R7166

402

5%

MF-LF

1/16W

1K

21

R7168

1/16W

5%

402

MF-LF

0

21

XW7123

SM

OMIT

13 95

13 95

2

1

C7160

402

50V
CERM

10%

0.0022UF

2

1

C7159

0.0022UF

402

50V
CERM

10%

21

R7170

MF-LF

1/16W

5%

10

402

21

R7171

1K

5%
1/16W
MF-LF

402

21

R7169

402

1/16W

5%

MF-LF

0

21

XW7133

OMIT

SM

2

1

R7195

10K

1/16W
MF-LF
402

5%

2

1

R7189

1K

1/16W

5%
MF-LF

402

21

RT7104

6.8K

0603

2

1

R7159

5%

1K

402

1/16W
MF-LF

21

RT7103

6.8K

0603

2

1

R7157

MF-LF

1/16W

402

5%

1K

2

1

R7179

100K

5%

402

1/16W
MF-LF

NOSTUFF

2

1

R7180

MF-LF

1/16W

402

5%

NOSTUFF

100K

2

1

R7181

10K

MF-LF

1/16W

402

5%

NOSTUFF

21

C7116

50V

CERM

402

0.001UF

10%

21

C7119

4700PF

100V

402

10%

CERM

21

C7123

10%
50V

CERM

402

0.0012UF

21

R7142

MF-LF

23.2K

402

1%

1/16W

21

XW7101

SM

OMIT

20

4

17

13

15

35

23

31

49

10

12
11

32

33

21

3

2

26

37

39

36

38

6

28

24
25

44
43

48
47

42
41

46
45

14

9

16

5

22

34

19

7

40

1

18

8

30
29

27

U7100

ISL6364

QFN

2 1

R7127

MF-LF

2.2

1/8W

805

5%

2

1

C7114

10%
25V

805

10UF

X5R

SYNC_MASTER=K60_AARON

VREG: PPVCORE_S0_CPU

SYNC_DATE=N/A

VR_AXG_PWM

PP5V_S0_CPU_VCORE_VCC

MIN_NECK_WIDTH=0.3MM
VOLTAGE=5V

MAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.6MM

VR_CPU_SW_FREQ

VR_CPU_ISNS3_R_N

VR_CPU_RAMP_ADJ

VR_CPU_PWM2

VR_CPU_VSEN

VR_CPU_RGND

CPU_VIDALERT_L

VR_CPU_FB

CPU_VIDSCLK

VR_CPU_IMON

VR_CPU_TM

VR_CPU_SUTH

VR_AXG_VSEN

VR_CPU_N_PSI

VR_AXG_FB

VR_AXG_RGND

CPU_VIDSOUT

PM_PGOOD_PVCORE_CPU

VR_AXG_SW_FREQ

VR_CPU_PSICOMP1

VR_CPU_VSNS_XW_P

VOLTAGE=1.1V

NET_PHYSICAL_TYPE=SNS_DIFF

AGND_CPU

VR_AXG_COMP_RC

NET_PHYSICAL_TYPE=SNS_DIFF

VOLTAGE=1.1V

VR_AXG_VSNS_XW_P

VR_AXG_VSNS_R_P

VR_SEN_R1

VR_SEN_R3

VR_CPU_PSICOMP2

AGND_CPU

MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

VR_AXG_IMON

VR_AXG_TM

=PP3V3_S0_VRD

VR_AXG_HFREQ_COMP

VR_RSET

AGND_CPU

AGND_CPU

=PPVAXG_S0_CPU

CPU_VAXG_SENSE_P

VOLTAGE=12V

NET_PHYSICAL_TYPE=POWER

PP12V_S0_CPU_FLTRD

VR_CPU_FB2

VR_AXG_VSNS_R_N

PP5V_S0_CPU_VCORE_VCC

VR_CPU_IMON_R

CPU_PROCHOT_L

=PPVCORE_S0_CPU

VR_EN_PWR_OVP_R

VR_CPU_ISNS1_N

DIFFERENTIAL_PAIR=VR_CPU_ISNS1

AGND_CPU

AGND_CPU

AGND_CPU

VR_CPU_ISNS3_N

DIFFERENTIAL_PAIR=VR_CPU_ISNS3

VR_CPU_PWM1

VR_AXG_IMON_R

=PP12V_S0_VRD

CPU_VCC_SENSE_P
CPU_VCC_SENSE_N

AGND_CPU

VR_CPU_VSNS_R_N

NET_PHYSICAL_TYPE=SNS_DIFF

VR_CPU_VSNS_XW_N

VOLTAGE=0V

VR_CPU_VSNS_R_P

DIFFERENTIAL_PAIR=VR_CPU_ISNS2

VR_CPU_ISNS2_N

CPU_VAXG_SENSE_N

VR_AXG_VSNS_XW_N

VOLTAGE=0V

NET_PHYSICAL_TYPE=SNS_DIFF

PP5V_S0_CPU_VCORE_VCC

VR_CPU_PWM3

AGND_CPU

AGND_CPU

AGND_CPU

AGND_CPU

DIFFERENTIAL_PAIR=VR_AXG_ISNS

VR_AXG_ISNS_P

AGND_CPU

AGND_CPU

VR_AXG_PWM_R

VR_AXG_ISNS_R_N

VR_HOT_L

PM_EN_PVCORE_CPU

VR_CPU_PWM4_R

DIFFERENTIAL_PAIR=VR_CPU_ISNS3

VR_CPU_ISNS3_P

VR_CPU_PWM3_R

VR_CPU_ISNS2_R_N

VR_CPU_PWM2_R

VR_CPU_ISNS1_R_N

VR_CPU_PWM1_R

PM_PGOOD_PVAXG

AGND_CPU

VR_SEN_R2

AGND_CPU

VR_AXG_COMP

PP5V_S0_CPU_VCORE_VCC

VR_CPU_COMP

=PPVCCIO_S0_CPU

=PP5V_S0_VRD

AGND_CPU

VR_CPU_ISNS1_P

DIFFERENTIAL_PAIR=VR_CPU_ISNS1

VR_CPU_ISNS2_P

DIFFERENTIAL_PAIR=VR_CPU_ISNS2

VR_AXG_TCOMP

VR_CPU_FDVID

VR_CPU_IAUTO

VR_CPU_PSICOMP

VR_CPU_HFREQ_COMP

VR_EN_PWR_OVP

PP5V_S0_CPU_VCORE_VCC

VR_CPU_FB_R

VR_CPU_FB_RC

DIFFERENTIAL_PAIR=VR_AXG_ISNS

VR_AXG_ISNS_N

VR_AXG_ISNS_R_P

=PP3V3_S0_VRD

71 OF 110

11.1.0

051-8115

65 OF 98

65 66 67 95

65 95

95

95

95

95

95

95

95

95

95

95

95

95

95

95

65

95

95

95

95

95

65

95

6

65 68

95

95

65

65

6

13 17 50

65 66 67 95

95

65 95

95

11
47

97

6

13 16 50

95

65

65

65

95

6

65

95

95

65 95

65

65

65

65

65

95

95

95

95

95

95

95

95

65

95

65

95

65 95

95

6

10 11 13 16

6

67

65

95

95

95

95

95

95

65 95

95

95

95

6

65 68

www.vinafix.vn

OUT

IN

IN

OUT

OUT

OUT

OUT

BOOT

UGATE

PHASE

NC
NC

GND

LGATE

VCC

PVCC

THRML

PWM

PAD

BOOT

UGATE

PHASE

NC
NC

GND

LGATE

VCC

PVCC

THRML

PWM

PAD

S

G

D

D

G

S

S

G

D

S

G

D

D

G

S

D

G

S

IN

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

THESE TWO CAPS ARE FOR EMC

THESE TWO CAPS ARE FOR EMC

PHASE 3

PHASE 2

OUTPUT BULK DECOUPLING:

PHASE 1

376S0771

152-0118

376S0771

376S0772

376S0771

75A MAX

152-0118

376S0772

128S0209

376S0772

THESE TWO CAPS ARE FOR EMC

65 95

2

1

C7282

X5R

10%
603

16V

1UF

2

1

C7226

CRITICAL

0805

10%
16V

10UF

X5R-CERM

2

1

R7226

MF-LF

1/8W

NOSTUFF

805

2.2

5%

2

1

C7206

CRITICAL

16V

10UF

10%

0805

X5R-CERM

2

1

C7228

0.001UF

402

50V

10%
CERM

NOSTUFF

2

1

C7223

603

0.22UF

X7R

16V

10%

2

1

R7224

0

1/10W

603

MF-LF

5%

2

1

C7221

16V

1UF

603

10%
X5R

2

1

R7221

1/10W

10

603

MF-LF

5%

2

1

R7225

1/10W

603

NOSTUFF

MF-LF

5%

0

2

1

R7222

10

MF-LF

603

5%

1/10W

2

1

C7220

603

X5R

1UF

16V

10%

NOSTUFF

2

1

C7222

16V

1UF

10%
X5R

603

2

1

R7227

MF-LF
603

NOSTUFF

0

5%
1/10W

65 95

2

1

C7283

10%

1UF

16V
X5R
603

2

1

C7246

CRITICAL

10UF

16V

10%

0805

X5R-CERM

2

1

R7206

NOSTUFF

2.2

MF-LF

805

5%

1/8W

2

1

R7246

5%

1/8W

MF-LF

2.2

805

NOSTUFF

2

1

C7248

50V

0.001UF

10%

402

CERM

NOSTUFF

2

1

C7243

16V

10%
X7R

603

0.22UF

2

1

R7244

0

5%

603

1/10W
MF-LF

2

1

C7241

1UF

16V
603

X5R

10%

2

1

C7208

50V
CERM
402

10%

0.001UF

NOSTUFF

2

1

R7241

MF-LF
603

1/10W

5%

10

2

1

R7245

0

5%

MF-LF

NOSTUFF

603

1/10W

2

1

R7242

10

5%

603

MF-LF

1/10W

2

1

C7240

603

X5R

1UF

16V

10%

NOSTUFF

2

1

C7242

16V
X5R

1UF

10%

603

2

1

R7247

MF-LF

0

603

1/10W

5%

NOSTUFF

65 95

2

1

C7207

1UF

10%
16V

603

X5R

2

1

C7211

10%

402

1UF

25V
X5R

2

1

C7215

10%
X5R-CERM

0805

16V

10UF

CRITICAL

2

1

C7229

16V
X5R-CERM

CRITICAL

10%
0805

10UF

2

1

C7249

CRITICAL

X5R-CERM
0805

10%
16V

10UF

43

21

R7208

0.0005

MF

1W

1%

0612

CRITICAL

43

21

R7228

0612

MF

1W

0.0005

1%

CRITICAL

65 95

65 95

65 95

65 95

43

21

R7248

1%

0.0005

CRITICAL

MF

1W

0612

2

1

C7270

CRITICAL

220UF

ALUM-POLY
8X7-TH

16V

20%

2

1

C7271

ALUM-POLY
8X7-TH

20%
16V

220UF

CRITICAL

2

1

C7203

0.22UF

10%
16V
X7R
603

2

1

C7205

220UF

20%
16V

CRITICAL

ALUM-POLY
8X7-TH

2

1

C7225

16V

20%
ALUM-POLY

8X7-TH

220UF

CRITICAL

2

1

C7245

20%
16V

CRITICAL

ALUM-POLY
8X7-TH

220UF

7

1

11

4

9

10

8

3

6

5

2

U7221

CRITICAL

QFN1

ISL6612

7

1

11

4

9

10

8

3

6

5

2

U7241

QFN1

ISL6612

CRITICAL

2

1

C7210

0.001UF

50V

10%

402

X7R

2

1

C7230

10%
402

50V
X7R

0.001UF

2

1

C7231

402

10%

1UF

25V
X5R

2

1

C7250

10%
X7R

50V
402

0.001UF

2

1

C7251

10%

402

1UF

25V
X5R

2

1

C7263

330UF-0.0045OHM

20%
2V
POLY
CASE-D2-SM

2

1

C7264

POLY

2V

20%

330UF-0.0045OHM

CASE-D2-SM

2

1

C7262

CASE-D2-SM

330UF-0.0045OHM

20%
2V
POLY

2

1

C7260

CASE-D2-SM

330UF-0.0045OHM

20%
2V
POLY

2

1

C7261

CASE-D2-SM

330UF-0.0045OHM

20%
2V
POLY

3

4 6

5

2

1

Q7201

CRITICAL

S1

IRF6710

43

5

7621

Q7202

IRF6795

DIRECTFET-MX

CRITICAL

3

4 6

5

2

1

Q7221

IRF6710

CRITICAL

S1

3

4 6

5

2

1

Q7241

IRF6710

S1

CRITICAL

2

1

R7204

0

603

MF-LF

1/10W

5%

43

5

7621

Q7222

DIRECTFET-MX

IRF6795

CRITICAL

43

5

7621

Q7242

IRF6795

DIRECTFET-MX

CRITICAL

21

L7201

0.24UH+/-20%-0.00042OHM-40A

SDP1108M-TH

CRITICAL

21

L7221

CRITICAL

SDP1108M-TH

0.24UH+/-20%-0.00042OHM-40A

21

L7241

CRITICAL

0.24UH+/-20%-0.00042OHM-40A

SDP1108M-TH

2

1

C7265

CASE-D2-SM

330UF-0.0045OHM

20%
2V
POLY

2

1

C7272

220UF

8X7-TH

ALUM-POLY

16V

CRITICAL

20%

2

1

C7281

X5R
603

16V

10%

1UF

2

1

C7227

10%
603

16V
X5R

1UF

2

1

C7247

603

X5R

16V

1UF

10%

65 95

9

8

1

11

4

10

7

6

5

3 2

U7201

ISL6622

CRITICAL

DFN

2

1

C7202

16V
603

X5R

10%

1UF

65 95

2

1

C7201

X5R

16V
603

10%

1UF

2

1

R7201

MF-LF

5%

NOSTUFF

603

1/10W

10

2

1

R7202

5%

603

MF-LF

1/10W

10

2

1

R7207

5%
1/10W
MF-LF
603

0

NOSTUFF

2

1

R7205

MF-LF

1/10W

5%

603

0

2

1

C7200

16V
X5R
603

1UF

10%

SYNC_DATE=01/06/2011

VREG: CPU CORE - PHASES 1-3

SYNC_MASTER=K62

PP12V_S0_CPU_FLTRD

NET_SPACING_TYPE=POWER

PPVCORE_S0_CPU_REG

NET_SPACING_TYPE=VR_CONTROL

NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_DRV2_LGATE

DIDT=TRUE

NO_TEST=TRUE

VR_CPU_BOOT1_RC

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

NO_TEST=TRUE

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

VR_CPU_DRV1_UGATE

NET_PHYSICAL_TYPE=VR_CTL_PHY

NO_TEST=TRUE

NET_PHYSICAL_TYPE=POWER

NO_TEST=TRUE

VR_CPU_DRV1_VCC

VR_CPU_ISNS3_N

PPVCORE_S0_CPU_REG

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

NO_TEST=TRUE

VR_CPU_BOOT3_RC

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=VR_CONTROL

VR_CPU_DRV1_BOOT

DIDT=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY
NO_TEST=TRUE

NET_SPACING_TYPE=VR_CONTROL

VR_CPU_DRV1_LGATE

NET_PHYSICAL_TYPE=VR_CTL_PHY

DIDT=TRUE

NO_TEST=TRUE

NET_SPACING_TYPE=VR_CONTROL

NET_PHYSICAL_TYPE=VR_CTL_PHY

DIDT=TRUE

VR_CPU_DRV2_UGATE

NO_TEST=TRUE

NET_SPACING_TYPE=VR_CONTROL

VR_CPU_DRV3_BOOT

DIDT=TRUE

NO_TEST=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

VR_CPU_DRV3_LGATE

NO_TEST=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY

DIDT=TRUE

NET_SPACING_TYPE=VR_CONTROL

VR_CPU_DRV3_UGATE

NO_TEST=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=SWITCHNODE

VR_CPU_PHASE3

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

SWITCH_NODE=TRUE

VR_CPU_PHASE2

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

NET_SPACING_TYPE=SWITCHNODE

SWITCH_NODE=TRUE

VR_CPU_DRV3_GDSEL

VR_CPU_PWM3

VR_CPU_DRV1_GDSEL

PPVCORE_S0_CPU_REG2

PPVCORE_S0_CPU_REG1

VR_CPU_PWM2

VR_CPU_ISNS2_P

VR_CPU_ISNS1_P

PPVCORE_S0_CPU_REG

VR_CPU_DRV2_GDSEL

VR_CPU_ISNS1_N

PPVCORE_S0_CPU_REG3

VR_CPU_PH3_SNUB

NET_SPACING_TYPE=SWITCHNODE

NET_PHYSICAL_TYPE=VR_CTL_PHY

DIDT=TRUE

VR_CPU_PH2_SNUB

NET_SPACING_TYPE=SWITCHNODE

DIDT=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_PH1_SNUB

NET_SPACING_TYPE=SWITCHNODE

DIDT=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_DRV3_VCC

NO_TEST=TRUE

NET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV3_UVCC

VR_CPU_DRV3_PVCC

NO_TEST=TRUE

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV2_VCC

NO_TEST=TRUE

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV2_UVCC

NET_PHYSICAL_TYPE=POWER

NO_TEST=TRUE

VR_CPU_DRV1_PVCC

NET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_BOOT2_RC

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE
NO_TEST=TRUE

VR_CPU_DRV2_PVCC

NO_TEST=TRUE

NET_PHYSICAL_TYPE=POWER

VR_CPU_PWM1

NO_TEST=TRUE

VR_CPU_DRV2_BOOT

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_PHASE1

NET_SPACING_TYPE=SWITCHNODE

DIDT=TRUE

NET_PHYSICAL_TYPE=POWER

SWITCH_NODE=TRUE

VR_CPU_ISNS2_N

VR_CPU_ISNS3_P

VR_CPU_DRV1_UVCC

NO_TEST=TRUE

NET_PHYSICAL_TYPE=POWER

PPVCORE_S0_CPU_REG

72 OF 110

11.1.0

051-8115

66 OF 98

65 67 95

6

66

95

95

95

95

6

66

95

95

95

95

95

95

95

95

95

95

95

95

6

66

95

95

95

95

95

95

95

95

95

95

95

95

95

95

95

95

6

66

www.vinafix.vn

IN

VSW

PGND

TGR

TG

BG

VIN

THRML

VCC

LGATE

GND

NC

NC

PHASE

UGATE

BOOT

PWM

EN

PAD

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

THESE TWO CAPS ARE FOR EMC

376S0906

AXG PHASE (MAX 15A)

152S1268

65 95

2

1

C7322

VAXG

10V

10UF

20%
X5R

603

2

1

C7323

VAXG

603

X5R

20%

10UF

10V

8

7

6

1

4

3

9

5

Q7301

VAXG

SON5X6

CSD58864Q5D

CRITICAL

7

1

11

4

10

8

3

6

5

9

2

U7301

VAXG

QFN

ISL6620

CRITICAL

2 1

R7305

VAXG

1

5%

603

MF-LF

1/10W

2

1

C7320

VAXG

CASE-D2-SM

330UF-0.0045OHM

20%
2V
POLY

2

1

C7321

VAXG

CASE-D2-SM

POLY

2V

20%

330UF-0.0045OHM

2

1

C7310

VAXG

1UF

10%
16V
X5R
603

2

1

C7307

VAXG

603

X5R

16V

10%

1UF

2

1

C7315

10UF

10%
X5R-CERM

VAXG

16V

CRITICAL

0805

43

21

R7308

VAXG

1W
MF

0612

CRITICAL

1%

0.0005

21

L7301

0.68UH-7.6MOHM-12A

VAXG

PIC0504H-SM

CRITICAL

2

1

R7306

MF-LF

805

5%

1/8W

NOSTUFF

2.2

65 95

65 95

2

1

C7308

402

50V
CERM

10%

0.001UF

NOSTUFF

2

1

C7303

VAXG

0.22UF

16V

10%
X7R

603

2

1

R7304

VAXG

603

1/10W

5%

MF-LF

1

2

1

C7301

VAXG

1UF

16V
X5R
603

10%

2

1

R7301

VAXG

MF-LF
603

1/10W

5%

0

VREG:AXG PHASE/CORE - CAPS

SYNC_MASTER=K60_AARON

SYNC_DATE=N/A

PP12V_S0_CPU_FLTRD

MIN_LINE_WIDTH=0.6MM
VOLTAGE=12V

MIN_NECK_WIDTH=0.3MM

VR_AXG_DRV1_PVCC

NET_PHYSICAL_TYPE=POWER

VR_AXG_DRV1_BOOT

NET_PHYSICAL_TYPE=VR_CTL_PHY
NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

PPVCORE_S0_AXG_REGOUT

VR_AXG_ISNS_P
VR_AXG_ISNS_N

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=SWITCHNODE

DIDT=TRUE

VR_AXG_PH1_SNUB

PPVCORE_S0_AXG_REG1

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=VR_CONTROL

VR_AXG_DRV1_LGATE

DIDT=TRUE

VR_AXG_DRV1_UGATE

DIDT=TRUE

VR_CONTROL

NET_PHYSICAL_TYPE=VR_CTL_PHY NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CTL

DIDT=TRUE

VR_AXG_DRV1_UGATE_R

=PP5V_S0_VRD

VR_AXG_PWM

DIDT=TRUE

NET_SPACING_TYPE=VR_CONTROL

VR_AXG_BOOT1_RC

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=SWITCHNODE

VR_AXG_PHASE1

DIDT=TRUE

NET_SPACING_TYPE=SWITCHNODE

NET_PHYSICAL_TYPE=POWER

PPVAXG_S0_REG

73 OF 110

11.1.0

051-8115

67 OF 98

65 66 95

95

95

95

95

95

95 95

6

65

95

95

6

www.vinafix.vn

D

G

S

NC

OUT

OUT

IN

SOFT

RBIAS

VIN

UGATE

VW

VSS

VSEN

VR_ON

VO

VID1

VID0

THRM_PAD

RTN

PVCC

PHASEPGOOD

PGND

FDE

FB

BOOT

VDD

VID2
VID3

IMON

AF_EN

VDIFF

COMP

LGATE

ICOMP

ISN

OCSET

ISP

NC

S

G

D

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.05V DEFAULT, OTHER VALUES TBD

(P1V05S0_PHASE)

(P1V05S0_LGATE)

(PP1V05S0_UGATE)

(P1V05S0_V0)

(P1V05S0_ICOMP)

(P1V05S0_ISN)

(P1V05S0_ISP)

(P1V05S0_VO)

(P1V05S0_VDIFF)

(P1V05S0_FB)

(P1V05S0_COMP)

(P1V05S0_VW)

(P1V05S0_RTN)

(P1V05S0_VSEN)

OUTPUT BULK DECOUPLING

376S0771

376S0772

0000 +1.100V
0011 +1.050V

VID<3:0> Voltage

1V05 REGULATOR for CPU & PCH VCCIO O/P= PP1V05_S0_REG

THESE TWO CAPS ARE FOR EMC

2

1

C7429

CERM-X5R

6.3V

20%

22UF

805

2

1

R7491

20.0K

MF-LF
402

1%
1/16W

2

1

R7492

MF-LF

1/16W

1%

NOSTUFF

20.0K

402

2

1

R7490

MF-LF

1/16W

20.0K

402

1%

43

5

7621

Q7421

IRF6795

DIRECTFET-MX

2

1

R7493

NOSTUFF

1%
MF-LF

1/16W

20.0K

402

2

1

R7494

MF-LF

NOSTUFF

1%
1/16W

20.0K

402

2

1

R7495

20.0K

1%
1/16W
MF-LF
402

2

1

R7476

1%

6.65K

1/16W
MF-LF
402

21

R7477

150K

1%
1/16W
MF-LF

402

21

C7480

33PF

5%

50V

CERM

402

21

C7481

0.001UF

402

CERM

50V

10%

2

1

R7475

MF-LF

1%

45.3K

1/16W
402

2

1

R7484

MF-LF

20.0K

NOSTUFF

1/16W

1%

402

50 95

63 64 97

2

1

C7430

1UF

402

16V
X5R

10%

21

R7480

603

MF-LF

1/10W

5%

2.2

2

1

C7465

1UF

X5R

16V
402

10%

NOSTUFF

21

R7467

MF-LF

1/10W

2.2

5%

603

2

1

C7426

CRITICAL

20%

8X7-TH

16V
ALUM-POLY

220UF

2

1

C7420

16V

CRITICAL

20%
ALUM-POLY

8X7-TH

220UF

2

1

C7427

CRITICAL

20%
16V
POLY

6.3X6-TH

100UF

2

1

C7445

CASE-D2-SM

20%
2V
POLY

330UF-0.0045OHM

2

1

R7411

10K

402

MF-LF

1/16W

5%

43

21

R7420

MF

1W

1%

0612

0.0005

2

1

C7424

X5R

10%

1UF

603

16V

2

1

C7425

16V
603

1UF

10%
X5R

2

1

R7462

603

1/10W

0.499

MF

1%

NOSTUFF

2

1

C7463

0.0022UF

CERM
402

10%
50V

NOSTUFF

2

1

R7464

402

1K

1%
MF-LF

1/16W

2

1

R7470

1/16W

NOSTUFF

MF-LF

1%

10K

402

2

1

C7478

X5R

25V

0.1UF

10%

402

2

1

C7473

0.01UF

50V
402

X7R

10%

2

1

C7477

X5R

25V

10%

0.1UF

402

21

R7460

2.2

5%
1/10W
MF-LF

603

21

C7464

0.22UF

X7R
16V
603

10%

2

1

R7469

9.31K

1%
MF-LF

402

1/16W

2

1

C7462

10%
X5R

16V
402

1UF

21

R7474

MF-LF

1/10W

5%

0

603

2

1

R7473

MF-LF

1/16W

10K

1%

402

21

XW7461

OMIT

SM

2

1

C7461

16V
X5R
402

10%

1UF

2

1

R7461

1/16W
MF-LF
402

1K

5%

63 97

2

1

R7463

MF-LF

1%

402

100

1/16W

2

1

C7470

0.001UF

10%
X7R

402

50V

21

R7466

20

402

1/16W
MF-LF

1%

21

R7468

1/16W

402

MF-LF

1%

20

2

1

C7476

X7R-CERM

0.1UF

402

10%
16V

2

1

R7472

150K

402

1%
MF-LF

1/16W

2

1

R7471

1%
1/16W

402

100

MF-LF

2

1

C7479

50V

10%
X7R

402

0.001UF

21

C7482

0.001UF

10%
50V

CERM

402

21

R7478

200

1/16W

402

MF-LF

1%

21

R7479

1%

402

MF-LF

2.21K

1/16W

2

1

R7483

MF-LF

20.0K

1/16W

1%

402

4

15

8

29

12

14

27

26

25

24

7

16

18

33

2

9

1

22

1931

20

3

21

13
11

28

10

32

6

5

17

30

U7401

CRITICAL

ISL9563A

QFN

2

1

C7423

16V
603

1UF

10%
X5R

2

1

C7422

CRITICAL

0805

16V

10%

10UF

X5R-CERM

2

1

C7421

0805

X5R-CERM

CRITICAL

10%
16V

10UF

3

4 6

5

2

1

Q7420

S1

IRF6710

21

L7420

CRITICAL

0.36UH-45A-0.76MOHM

MSQ1211R36LF-TH

2

1

C7443

CASE-D2-SM

POLY

2V

20%

330UF-0.0045OHM

2

1

C7444

CASE-D2-SM

POLY

2V

20%

330UF-0.0045OHM

2

1

C7446

CASE-D2-SM

POLY

2V

20%

330UF-0.0045OHM

2

1

C7428

CERM-X5R

6.3V

20%

22UF

805

SYNC_DATE=01/06/2011

1V05 REGULATOR

SYNC_MASTER=K62

P1V05S0_VO

P1V05S0_OCSET

P1V05S0_ISP

P1V05S0_VW

PP1V05_S0_REG

CPU_VCCIO_SENSE_P

DIDT=TRUE

=PP12V_S0_P1V05_VREG

NET_SPACING_TYPE=POWER

0.25 MM

0.2 MM

P1V05S0_BOOT

DIDT=TRUE

NET_SPACING_TYPE=VR_CTL

0.2 MM

DIDT=TRUE

0.25 MM

P1V05S0_BOOT_R

NET_SPACING_TYPE=VR_CTL

DIDT=TRUE

P1V05S0_LGATE

MIN_LINE_WIDTH=0.5 MM

NET_SPACING_TYPE=SWITCHNODE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

P1V05S0_UGATE

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

NET_SPACING_TYPE=SWITCHNODE

P1V05_REG_VID0

P1V05S0_VDIF_C

CPU_VCCIO_SENSE_N

P1V05S0_COMP_C

P1V05S0_RTN

P1V05S0_VSEN

P1V05_REG_VID2

P1V05S0_FDE

P1V05_REG_VID3

=PP3V3_S0_P1V05_VREG

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

P1V05S0_PHASE_L

PP1V05_S0_REG

P1V05S0_ISP_R

=PP5V_S0_P1V05_VREG

0.6 mm

VOLTAGE=5V

0.2 MM

5V_S0_P1V05REG_VDD

P1V05_REG_VID1

PM_EN_P1V05_S0_REG

PM_PGOOD_P1V05_S0_REG

VOLTAGE=5V

0.6 mm

0.2 MM

5V_S0_P1V05REG_VIN

=PP3V3_S0_VRD

GND_P1V05S0_AGND

VOLTAGE=12V

0.6 mm

0.2 MM

PP12V_S0_P1V05_VREG_VIN

P1V05_IMON

P1V05S0_SNUBBER

MIN_NECK_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MM

DIDT=TRUE

NET_SPACING_TYPE=VR_CTL

P1V05S0_RBIAS

P1V05S0_SOFT

P1V05S0_PHASE

NET_PHYSICAL_TYPE=POWER

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

DIDT=TRUE

NET_SPACING_TYPE=SWITCHNODE

PP1V05_S0_REG

P1V05S0_FB

P1V05S0_COMP

P1V05_S0_VDIFF

GND_P1V05S0_AGND

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm

P1V05S0_ICOMP

P1V05S0_ISN

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G

D

S

VIN

VOUT

GND

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER

SIZE

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

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A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

CPU VCCSA 0.925V (8.8A MAX)

NOTE: THIS POWER RAIL IS BEFORE THE SENSE RES R5310

NOTE: THIS RAIL IS COMING FROM PPVCCSA_S0_INPUT_SNS AFTER SENSE RES

376S0910

4

8

1

3

2

U7501

LM358-SOI-HF

21

R7503

0

5%

402

1/16W
MF-LF

2

1

C7502

603-1

10%

1UF

25V
X5R

2

1

C7501

CERM
402

5%
50V

100PF

21

R7507

5.49K

1%

1/16W

402

MF-LF

21

R7506

402

5%

MF-LF

1/16W

1K

NOSTUFF

21

R7505

MF-LF

5%

1/16W

0

402

2

1

C7507

10%
X5R

6.3V

10UF

805

Place C7507 inside cavity

2

1

C7508

10UF

805

X5R

6.3V

10%

Place C7508 inside cavity

2

1

R7504

MF-LF

5%

2.2

1/10W
603

2

1

C7509

CASE-D2E-SM

6V

20%
POLY-TANT

220UF-25MOHM

OMIT_TABLE

2

1

C7510

CASE-D2E-SM

220UF-25MOHM

6V

20%
POLY-TANT

OMIT_TABLE

1

4

5

Q7500

IRFH3702TRPBF

PQFN

4

8

7

5

6

U7501

LM358-SOI-HF

2

1

R7533

402

MF-LF

10K

1/16W

1%

21

C7512

NOSTUFF

5%

50V

10PF

402

CERM

21

R7535

402

1/16W
MF-LF

5%

22

2

1

C7505

402

10V
CERM

20%

0.1UF

2

1

C7504

402

6.3V
X5R-CERM1

20%

4.7UF

2

1

C7506

CASE-D2-HF

20%
POLY

2V

CRITICAL

330UF-0.009OHM

21

R7550

1%

MF-LF

402

1/16W

49.9K

21

C7550

10%

560PF

CERM

50V
402

21

C7551

10PF

CERM

50V

5%

402

21

C7552

25V

NP0-C0G

402

5%

1000PF

21

R7552

MF-LF

1/16W

5%

402

1K

21

3

U7505

CRITICAL

ISL21070

SOT23-3

21

R7531

402

5%
1/16W
MF-LF

100

2

1

C7515

10%

1UF

10V
X5R
402

2

1

C7516

10%
10V

1UF

X5R
402

128S0330

2

POLYTANT,6V,220UF,25MOHM

C7509,C7510

SYNC_DATE=11/15/2010

CPU VCCSA REGULATOR

SYNC_MASTER=K62

VCCSA_CNTRL_INPUT2_R

VCCSA_CRL

NET_SPACING_TYPE=VR_CTL

DIDT=TRUE

VCCSA_OUT

NET_PHYSICAL_TYPE=VR_CTL_PHY

VCCSA_FIL

VCCSA_GATE

DIDT=TRUE

NET_SPACING_TYPE=VR_CTL

NET_PHYSICAL_TYPE=VR_CTL_PHY

VCCSA_CNTRL_INPUT2

VCCSA_PWR_RC

=PPVCCSA_S0_INPUT_PWR

=PPVCCIO_S0_CPU_VCCSA

=PP12V_S0_CPU_VCCSA

CPU_VCCSA_SENSE

VCCSA_REF

=PP3V3_S5_CPU_VCCSA

VCCSA_CNTRL_INPUT1

DIDT=TRUE

NET_SPACING_TYPE=POWER

NET_PHYSICAL_TYPE=POWER

PPVCCSA_S0_FET

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OUT

D1

G1

S2

G2

S1/D2

G

D

S

G

D

S

PGOOD2

FCCM

VIN

FB1

FSET1

EN2

FSET2

BOOT2

THRM

PGND

EN1

FB2

VOUT2VOUT1

ISEN2ISEN1

OCSET1

OCSET2

LGATE1

LGATE2

PHASE2

BOOT1

UGATE1

LDO5

PGOOD1

VCC1

VCC2

UGATE2

PHASE1

PAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

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A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

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8 7 5 4 2 1

3V3 S5 REGULATOR

OUTPUT BULK DECOUPLING:

376S0875

PLACE AT L7750.2

OUTPUT BULK DECOUPLING:

5V S3 REGULATOR

RB

(P3V3S5_PHASE)

RA

TO L

PLACE CLOSE

EMC CAPS

<Ra>

5V OUTPUT

Power Rating ?

<Rb>

EMC CAPS

(P3V3S5_LGATE)

PLACE CLOSE TO FET

(P3V3S5_UGATE)

EMC: C7763,C7764

PLACE AT Q7330

376S0917

Vout = 0.6V * (1 + Ra / Rb)

128S0237

376S0801

EMC: C7754,C7755

3V3 OUTPUT

2

1

C7762

330UF

POLY-TANT
CASE-D3L-SM

CRITICAL

20%

6.3V

2

1

R7747

402

MF-LF

1/16W

1%

16.5K

2

1

C7747

10%
16V
CERM
402

0.01UF

2

1

C7777

0.001UF

402

10%
50V
CERM

NOSTUFF

2

1

C7757

NOSTUFF

50V

10%

0.001UF

402

CERM

2

1

C7721

CRITICAL

6.3V

POLY-TANT

330UF

20%

CASE-D3L-SM

2

1

R7723

MF-LF

5%

33K

402

1/16W

2

1

R7722

402

MF-LF

1/16W

68K

5%

63 82 97

2

1

R7724

976

1%

402

MF-LF

1/16W

2

1

R7759

976

MF-LF

1%

1/16W

402

2

1

R7755

75K

1%
1/16W
MF-LF

402

543

7

6

1

2

Q7710

RJK0384DPA

WPAK

321

4

5

Q7750

CRITICAL

FDMS0346

POWER56

2

1

C7764

10%
X7R

50V
402

0.001UF

2

1

C7718

6.3X6-TH

POLY

16V

20%

100UF

2

1

C7763

10%
X7R

50V

0.001UF

402

21

L7750

CRITICAL

2.2UH+/-20%-0.0069OHM-16A

PIC1005H-SM

2

1

C7760

CERM

10UF

20%

6.3V
805-1

321

4

5

Q7751

FDMS0355S

POWER56

CRITICAL

2

1

C7719

6.3X6-TH

POLY

16V

100UF

20%

2

1

C7766

100UF

16V

20%

POLY

6.3X6-TH

2

1

C7767

6.3X6-TH

100UF

16V

POLY

20%

2

1

C7768

6.3X6-TH

POLY

100UF

20%
16V

2

1

R7741

MF-LF

5%
1/8W

805

1

2

1

C7743

603

16V

10%
X5R

1UF

2

1

R7725

NOSTUFF

1/16W

20K

5%

402

MF-LF

2

1

R7726

5%
1/16W

20K

MF-LF
402

2

1

XW7751

OMIT

SM

2 1

R7776

1/4W

0.002

MF-LF

1%

1206

2 1

R7775

MF-LF

0.002

1206

1/4W

1%

21

C7770

27.0NF

402

X5R

10V

10%

2

1

C7754

10%
16V

1UF

X5R
603

2

1

C7755

603

X5R

1UF

16V

10%

2

1

C7711

10%
16V

1UF

X5R
603

2

1

C7722

10%
16V

1UF

X5R
603

2

1

C7761

CASE-D3L-SM

330UF

20%

6.3V

POLY-TANT

CRITICAL

2

1

C7769

CERM

20%

805-1

6.3V

10UF

2

1

C7759

25V
402

5%

1000PF

NP0-C0G

2

1

R7756

402

MF-LF

1/16W

1%

10K

2 1

C7756

25V

10%
X5R

402

0.1UF

2

1

C7765

10UF

16V

10%

X5R-CERM

0805

2

1

R7752

MF

603

NOSTUFF

1/10W

1%

0.499

2 1

R7750

1/10W

603

5%

MF-LF

0

2

1

C7758

X5R-CERM

16V

10%

10UF

0805

2

1

C7710

X5R-CERM

10%
16V

0805

10UF

21

XW7716

SM

OMIT

PLACEMENT_NOTE=PLACE NEXT TO C7716

2

1

C7720

NP0-C0G

1000PF

402

5%

25V

2

1

R7720

45.3K

1/16W

402

1%

MF-LF

2

1

R7721

1/16W

0.5%

402

MF

10.0K

2

1

C7712

16V

X5R-CERM

10%

0805

10UF

2

1

C7717

0805

16V

X5R-CERM

10UF

10%

2

1

C7715

10UF

X5R-CERM

0805

16V

10%

279

17

4

5

2214

29

2313

1

7

19

2511

2016

18

26

10

2

6

3

28

8

2412

2115

U7700

ISL62383

CRITICAL

QFN

2

1

C7716

0.1UF

603

20%
16V
CERM

2

1

C7723

0.1UF

16V
CERM
603

20%

21

C7790

10%

16V

402

CERM

0.01UF

2

1

R7791

1/16W

402

1%

MF-LF

15.8K

2

1

C7730

1000PF

25V
NP0-C0G
402

5%

NOSTUFF

2

1

R7730

1/10W
MF

1%

NOSTUFF

603

0.499

21

C7714

0.1UF

603-1

50V

10% X7R

21

R7710

1/10W

603

5%

0

MF-LF

21

R7790

1/16W
MF-LF

1%

402

15.8K

2 1

R7770

9.76K

402

MF-LF

1/16W

1%

2

1

R7771

9.76K

MF-LF

402

1/16W

1%

21

L7710

MMD06CZ-SM

CRITICAL

2.2UH-14A

2

1

C7740

1UF

X5R

10%

603

16V

2

1

C7741

10%
16V

1UF

X5R
603

2

1

R7740

1/8W

2.2

5%
MF-LF

805

2

1

C7742

6.3V
CERM

20%

603

4.7UF

2

1

C7701

0.01UF

10%
16V
CERM
402

2

1

R7701

402

MF-LF

1/16W

1%

16.5K

SYNC_MASTER=K62

5V_S3 / 3V3_S5 VREGS

SYNC_DATE=01/06/2011

P3V3S5_REG_VOUT1

PP5V_S3_REG_R

NET_PHYSICAL_TYPE=POWER

P5VS3_REG_UGATE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

NET_SPACING_TYPE=VR_CONTROL

MIN_LINE_WIDTH=0.6MM

P3V3S5_REG_UGATE

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
GATE_NODE=TRUE

NET_SPACING_TYPE=VR_CONTROL

P3V3S5_REG_LGATE

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

GATE_NODE=TRUE

NET_SPACING_TYPE=VR_CONTROL

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

=PP12V_S5_P5VS3_VREG

NET_SPACING_TYPE=POWER

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

PP3V3_S5_REG_R

NET_PHYSICAL_TYPE=POWER

=PP12V_S5_P5VS3_VREG

PM_PGOOD_P5V_S3_REG

P5VS3_REG_VOUT2

P3V3S5_REG_OCSET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6MM

NET_SPACING_TYPE=VR_CONTROL

P5VS3_REG_BOOT

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6MM

NET_SPACING_TYPE=VR_CONTROL

P5VS3_REG_LGATE

DIDT=TRUE

P3V3S5_REG_SNUB

DIDT=TRUE

NET_SPACING_TYPE=VR_CTL

P5VS3_REG_FB

P3V3S5_REG_PHASE

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

NET_SPACING_TYPE=SWITCHNODE

MIN_LINE_WIDTH=0.6MM

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

NET_PHYSICAL_TYPE=POWER

VIN_5V_S5_REG_RC

P5VS3_REG_BOOT_R

MIN_LINE_WIDTH=0.25MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

P3V3S5_REG_BOOT

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

NET_SPACING_TYPE=VR_CONTROL

P3V3S5_REG_FSET1

PP5V_S3_REG

=PP3V3_S5_VRD

P3V3S5_REG_BOOT_R

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

NET_SPACING_TYPE=VR_CONTROL

P5V_S5_LDO_R

P3V3S5_REG_FB

P3V3S5_REG_FB_R

P5VS5_REG_FB_R

TP_P5VS3_REG_FCCM

PM_EN_P3V3_S5_REG

P5VS3_REG_FSET2

PP3V3_S5_REG

PM_EN_P5V_S3_REG

5V_SNUBBER

MIN_LINE_WIDTH=0.4MM

NET_SPACING_TYPE=SWITCHNODE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

P3V3S5_REG_ISEN

P5V_S5_VCC1

PM_PGOOD_P3V3_S5_REG

P5VS3_REG_ISEN

P5VS3_REG_PHASE

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2 MM

NET_SPACING_TYPE=SWITCHNODE

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

P5VS3_REG_OCSET

NET_PHYSICAL_TYPE=POWER

PP5V_S5_LDO

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MODE

VDDQSNS

COMP

NC0
NC1

VTTSNS

VTT

VTTREF

PGOOD

S3
S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

NC
NC

IN
IN

OUT

NC

VFB

LX2

LX1

LX0

SYNCH

PG

SGND PGND

THRM_PAD

VIN

VDD

EN

VSW

PGND

TGR

TG

BG

VIN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(DDRREG_DRVH)

<Ra>

VTTREF

Vout = VTTREF

1.8 V SUPPLY

(DDRREG_FB)

(DDRREG_VDDQSNS)

VDDQ/VTTREF Enable

OUTPUT BULK DECOUPLING:

PPDDR_S3_REG

PEAK = 11A

Vout = 0.75V * (1 + Ra / Rb)

1A Average current

VDDQ PGOOD

S5

<Ra>

<Rb>

AVG = 6.7A

EMC CAPS
PLACE CLOSE TO L7830

<Rb>

LO

S0
S5

S3

STATE

HI
HILO

LO

HI

OFF

ON
OFF

ON ON

ON ON

OFF

VDDQ

VTT

(DDRREG_CSGND)

FEEDBACK THROUGH SHORT
SHOULD NOT NEED TP

Vout = VDDQSNS/2

Vo=0.8*(1+ Ra/Rb)

10mA max load

(NOT USED)

OFF

CONTINUOUS MODE

Vo=0.8*(1+ 59/47)=1.804V

VOUT = 1.5V

S3

1.5 V DDR SUPPLY

(DDRREG_DRVL)

(DDRREG_LL)

PLACE CLOSE TO FET

EMC CAPS

VTT Enable

2

1

C7837

X5R

10UF

20%

6.3V

603

2

1

C7841

1000PF

25V

5%

402

NP0-C0G

NOSTUFF

2

1

C7832

16V

0805

10%

10UF

X5R-CERM

2

1

R7831

NOSTUFF

0.499

603

MF

1/10W

1%

21

XW7831

SM

OMIT

PLACEMENT_NOTE=PLACE NEXT TO Q7831

21

C7840

25V

603

0.1UF

CERM

20%

21

R7840

MF-LF

5%

0

603

1/10W

2

1

C7815

6.3V
X5R

20%

603

10UF

2

1

C7839

50V
X7R
402

0.001UF

10%

2

1

R7810

3.57K

1%
1/16W
MF-LF

402

2

5

1

24

23

8

9

22

15

14

25

11

10

13

18

12

7

4

20

3

19

21

17

16

6

U7800

QFN

CRITICAL

TPS51116

2

1

XW7801

OMIT

SM

2

1

XW7800

SM

OMIT

2

1

C7801

10%

1UF

10V
X5R
402

21

R7801

402

MF-LF

1/16W

5%

4.7

2

1

C7805

10%

0.033UF

402

X5R

16V

2

1

C7800

603

CERM

6.3V

4.7UF

20%

21

XW7803

OMIT

SM

2

1

C7803

22UF

CERM-X5R
805-3

CRITICAL

20%

6.3V

2

1

C7804

CERM-X5R

805-3

22UF

20%

6.3V

CRITICAL

32 63 97

63 97

2

1

R7854

MF-LF
402

1/16W

5%

100K

2

1

XW7830

PLACEMENT_NOTE=PLACE NEXT TO L7830

OMIT

SM

21

L7850

CRITICAL

MMD04BZ-SM

1.5UH-4A

2

1

R7851

1/16W

1%
402

47.0K

MF-LF

2

1

R7850

1/16W

402

1%

MF-LF

59.0K

2

1

C7850

5%

CERM

50V

402

47PF

2

1

R7832

15.0K

MF-LF

1/16W

1%

402

5

63 97

2

1

C7820

100PF

402

CERM

5%

50V

NOSTUFF

2

1

C7830

8X9-TH1

270UF

16V

ELEC

20%

CRITICAL

2

1

C7831

8X9-TH1

270UF

20%
16V

ELEC

CRITICAL

2

1

C7835

20%

CRITICAL

2.5V
POLY-TANT

330UF

CASE-D2E-SM3

2

1

C7836

20%

CRITICAL

2.5V
POLY-TANT

330UF

CASE-D2E-SM3

2

1

8

3

17

4

10912

11

7

16
6

15

14

13

5

U7850

QFN

ISL8013A

CRITICAL

2

1

R7853

402

5%
1/16W
MF-LF

100K

8

7

6

1

4

3

9

5

Q7830

CRITICAL

SON5X6

CSD58864Q5D

2

1

R7833

1/16W

402

15.0K

1%
MF-LF

2

1

C7854

X5R-CERM-1

22UF

603

6.3V

20%

2

1

C7855

X5R-CERM-1
603

20%

22UF

6.3V

2

1

C7852

6.3V

20%

22UF

603

X5R-CERM-1

2

1

C7853

603

22UF

6.3V

20%
X5R-CERM-1

2

1

R7820

MF-LF

10K

5%

1/16W

402

2

1

R7860

5%
1/16W
MF-LF

100K

NOSTUFF

402

21

R7841

1/10W

603

MF-LF

5%

4.7

21

L7830

CRITICAL

1.5UH-15%-22A-3.3MOHM

SDP1182M-TH

2

1

C7833

603

1UF

10%
16V
X5R

2

1

C7834

X5R

16V

10%

1UF

603

2

1

C7838

50V
X7R
402

0.001UF

10%

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

1.5V / 1.8V VREGS

NET_PHYSICAL_TYPE=POWER

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S3_DDR_REG_V5FILT

VOLTAGE=5V

PP1V5_S3_REG

NET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=POWER

DDR_REG_CS

DDR_REG_UGATE_R

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VR_CTL

NET_SPACING_TYPE=SWITCHNODE

DDR_REG_PHASE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

NET_SPACING_TYPE=VR_CONTROL

DDR_REG_UGATE

DIDT=TRUE

DDR_REG_VDDQSNS

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

AGND_DDR_REG

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

NET_PHYSICAL_TYPE=POWER

=PP5V_S3_DDR_VREG

NET_PHYSICAL_TYPE=POWER

=PP12V_S5_DDR_VREG

NET_SPACING_TYPE=POWER

DIDT=TRUE

1V5_SNUBBER

MIN_LINE_WIDTH=0.4MM

DIDT=TRUE
NET_SPACING_TYPE=SWITCHNODE

MIN_NECK_WIDTH=0.4MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DDR_REG_PHASE_R

NET_SPACING_TYPE=VR_CTL

DDR_REG_LGATE

MIN_NECK_WIDTH=0.2 mm

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DDR_REG_BOOT

NET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

TP_PPVTT_S3_DDR_BUF

NET_PHYSICAL_TYPE=POWER

PP1V8_S0_REG

PM_EN_P1V8_S0_REG

PM_PGOOD_P1V8_S0_REG

PM_PGOOD_DDR1V5_S3_REG

=PP3V3_S3_VRD

DDR_REG_VTTSNS

NO_TEST=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

DDR_REG_PGND

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DDR_REG_BOOT_R

NET_SPACING_TYPE=VR_CONTROL

P1V8_REG_SYNC

=PP5V_S0_P1V8_REG

SWITCHNODE

DIDT=TRUE

P1V8_REG_PHASE

NET_PHYSICAL_TYPE=POWER

P1V8_REG_VFB

DDR_REG_FB

PM_EN_DDRVTT_S0_REG
PM_EN_DDR1V5_S3_REG

PPVTT_S0_DDR_LDO

DDR_REG_CSGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

78 OF 110

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051-8115

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95

6

95

95

95

95

6

6

95

95

95

95

6

63 97

64 97

6

95

95

95

95

6

95

95

95

6

95

www.vinafix.vn

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

PAGE TITLE

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A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

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A

B

C

345678

D

B

8 7 5 4 2 1

Vout = 1.25V * (1 + Ra / Rb)

353S2171

(Switcher limit)

Vout = 3.425

<Rb>

250mA max output

<Ra>

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

2

1

C7910

10UF

X5R

10%
25V

805

6

9

48

5

1

3

2

U7900

DFN

LT3470A

CRITICAL

2

1

C7900

6.3V

20%

402

X5R

0.22UF

21

L7900

CDPH4D19FHF-SM

33UH

CRITICAL

2

1

R7901

402

MF-LF

1/16W

1%

200K

2

1

C7901

22pF

50V
402

5%

CERM

2

1

R7900

348K

402

1%
1/16W
MF-LF

2

1

C7902

22UF

6.3V

20%

603

X5R-CERM-1

2

1

C7911

402

25V
NP0-C0G

1000PF

5%

2

1

R7910

6.98K

MF-LF

1/16W

1%

402

2

1

R7911

1%

MF-LF

1/16W

402

2.1K

SYNC_MASTER=K62

3.42 G3HOT SUPPLY

SYNC_DATE=01/06/2011

3V42G3H_SHDN_L

NET_SPACING_TYPE=POWER

=PP12V_G3H_3V42

PP3V42_G3H_REG

P3V42G3H_FB

DIDT=TRUE

P3V42G3H_SW

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

NET_SPACING_TYPE=SWITCHNODE

MIN_NECK_WIDTH=0.25 mm

P3V42G3H_BOOST

79 OF 110

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95

95

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G

D

S

G

D

S

G

D

S

G

D

S

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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R

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SHEET

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A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3.3V S0 FET (2.9APK / 2.0A AVG)

3.3V S3 FET (3.4A PK / 1.6A AVG)

1.5V S0 FET (4.8A PK / 4.8A AVG)

5V S0 FET (6.6A PK/3.1A AVG)

2

1

C8050

402

0.1UF

10%
X5R

16V

1

4

5

Q8000

IRFH3702TRPBF

PQFN

CRITICAL

1

4

5

Q8053

CRITICAL

PQFN

IRFH3702TRPBF

1

4

5

Q8050

IRFH3702TRPBF

PQFN

CRITICAL

1

4

5

Q8025

IRFH3702TRPBF

PQFN

CRITICAL

1

9

6

8

2

4

7

5

U8053

SLG5AP001

CRITICAL

TDFN

63 97

2

1

C8000

0.1UF

10%
16V
X5R
402

1

9

6

8

2

4

7

5

U8000

SLG5AP001

TDFN

CRITICAL

2

1

C8025

402

10%
X5R

16V

0.1UF

1

9

6

8

2

4

7

5

U8025

TDFN

CRITICAL

SLG5AP001

63 97

63 97

2

1

C8053

0.1UF

402

10%
X5R

16V

1

9

6

8

2

4

7

5

U8050

SLG5AP001

TDFN

CRITICAL

2

1

R8000

NOSTUFF

402

5%
1/16W

10K

MF-LF

2

1

R8050

10K

402

5%
1/16W
MF-LF

2

1

R8051

MF-LF

1/16W

5%

402

10K

2

1

R8020

402

MF-LF

10K

1/16W

5%

63 97

SYNC_DATE=01/06/2011

S3+S0 FETS

SYNC_MASTER=K62

=PP3V3_S0_PWRCTL

PM_PGOOD_P5V_S0_FET

=PP1V5_S3_S0FET

PP1V5_S0_FET

P1V5_S0_EN_G

P3V3_S3_EN_G

PP3V3_S3_FET

=PP3V3_S5_S3FET

PP3V3_S0_FET

P3V3_S0_EN_G

=PP3V3_S5_S0FET

=PP5V_S3_S0FET

PP5V_S0_FET

P5V_S0_EN_G

=PP12V_S5_PWRCTL

PM_PGOOD_P1V5_S0_FET

=PP12V_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_EN_P1V5_S0_FET

PM_PGOOD_P3V3_S0_FET

PM_EN_P3V3_S0_FET

PM_EN_P5V_S0_FET

=PP3V3_S3_PWRCTL

=PP12V_S5_PWRCTL

=PP12V_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_EN_P3V3_S3_FET

PM_PGOOD_P3V3_S3_FET

80 OF 110

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3

3

3

6

63 64 73 80

63 64
97

6 6

6

6

6

6

6

6

6

33 64 73

11 64 97

6

33 64 73

6

63 64 73 80

63 64 97

6

64 82

6

33 64 73

6

33 64 73

6

63 64 73 80

34 97

www.vinafix.vn

NC

NC

G

S

D

G

D

S

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

D

R

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SHEET

PAGE TITLE

C

A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Proto-3:Add C8111

376S0933

P-CH MOSFET 376S0933 4.6-MOHM 20A (WHEN USED W/Q8112)

10Amp-7Amp

Short R8132 BEFORE DVT

(2.4-5.5V)

High=3.3V

43

21

R8132

MF

1W

2512

0.005

1%

2

1

C8110

X7R
805-1

0.47UF

10%
16V

21

R8111

1/16W

5%

MF-LF

402

10K

2

1

R8110

10K

1/16W

5%

MF-LF

402

2

1

3

Q8112

SOT23-HF1

2N7002

2

1

R8112

402

MF-LF

1/16W

5%

10K

21

R8113

MF-LF

1/16W

402

0

5%

1

4

5

Q8110

CRITICAL

PQFN

IRFH9310PBF

2

1

R8115

1/16W

402

5%

100K

MF-LF

2

1

C8111

805

2.2UF

10%
16V

X7R-CERM

SYNC_DATE=01/06/2011

12V_S0 & 12V_S5 switch

SYNC_MASTER=K60_JERRY

PP12V_S5_FET

MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.5mm

NET_PHYSICAL_TYPE=POWER
VOLTAGE=12V

PP12V_S5_RSN

SMC_PM_G2_EN

SMC_PM_G2_EN_R

S5_DG_1

SMC_PM_G2_EN_L

S5_MSFT_G1

=PP12V_G3H_S5_FET

81 OF 110

11.1.0

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95

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97

97

97

97

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3V3

5V

PWR_SRC

(4 OF 4)

PCI-E

DP

(2 OF 4)

PEX_TX15*

DP_A_AUX*

PEX_TX1*

PEX_TX13

PEX_TX11*

PEX_TX7*

PEX_TX8*

PEX_TX9

PEX_TX10

PEX_STD_SW*

PEX_TX15

PEX_TX14*
PEX_TX14

PEX_TX13*

PEX_TX12*
PEX_TX12

PEX_TX11

PEX_TX10*

PEX_TX9*

PEX_TX8

PEX_TX7

PEX_TX6*
PEX_TX6

PEX_TX5*
PEX_TX5

PEX_TX4*
PEX_TX4

PEX_TX3*
PEX_TX3

PEX_TX2*
PEX_TX2

PEX_TX1

PEX_TX0*
PEX_TX0

PEX_REFCLK*

PEX_REFCLK

PEX_RST*

DP_C_HPD

DP_D_HPD

DP_B_HPD

DP_A_HPD

PEX_RX15*
PEX_RX15

PEX_RX14*
PEX_RX14

PEX_RX13*
PEX_RX13

PEX_RX12*
PEX_RX12

PEX_RX11*
PEX_RX11

PEX_RX10*
PEX_RX10

PEX_RX9*
PEX_RX9

PEX_RX8*
PEX_RX8

PEX_RX7*
PEX_RX7

PEX_RX6*
PEX_RX6

PEX_RX5*
PEX_RX5

PEX_RX4*
PEX_RX4

PEX_RX3*
PEX_RX3

PEX_RX2*
PEX_RX2

PEX_RX1*
PEX_RX1

PEX_RX0*
PEX_RX0

CLK_REQ*

DP_C_L0*

DP_C_L0

DP_C_L1*

DP_D_L0*

DP_C_L1

DP_D_L0

DP_C_L2*

DP_D_L1*

DP_C_L2

DP_D_L1

DP_C_L3*

DP_D_L2*

DP_C_L3

DP_D_L2

DP_D_L3*

DP_D_L3

DP_B_L0*

DP_B_L0

DP_B_L1*

DP_A_L0*

DP_B_L1

DP_A_L0

DP_B_L2*

DP_A_L1*

DP_B_L2

DP_A_L1

DP_B_L3*

DP_A_L2*

DP_B_L3

DP_A_L2

DP_A_L3*

DP_A_L3

DP_C_AUX*

DP_C_AUX

DP_D_AUX*

DP_D_AUX

DP_B_AUX*

DP_B_AUX

DP_A_AUX

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Page Notes

VOLTAGE CURRENT

POWER

BOM options provided by this page:

- MXM

- =PPV_S0_MXM_PWRSRC

Power aliases required by this page:

(NONE)

- =PP3V3_S0_MXM

Signal aliases required by this page:

(NOT NECESSARILY THE SAME FOR EVERY MODULE)

MXM SPEC POWER REQUIREMENTS

5V

3V3

PWR (7-20V)

UP TO 10 A

2.5 A

1.0 A 3.3 W

12.5 W
PLATFORM DEPENDENT

DP B
DP C
DP D
DP E

EXT DP2

INT DP

INT DP

DP A

EXT DP1

T29 DP1

T29 DP1

T29 DP2 T29 DP2

EXT DP1

K62 K60

MXM DP PORT ROUTING

- =PP5V_S0_MXM

APPLE P/N: 516S0699

2

1

C8400

22UF

35V

ELEC

6.3X5.5-SM1

20%

MXM

2

1

C8401

805-3

CERM-X5R

MXM

6.3V

20%

22UF

2

1

C8410

50V
402

X7R

10%

MXM

0.001UF

2

1

C8412

0.001UF

50V
402

10%
X7R

MXM

2

1

C8413

0.001UF

50V

10%
X7R

402

MXM

2

1

C8414

0.001UF

50V
402

10%
X7R

MXM

2

1

R8400

MXM

MF-LF

1/16W

402

100K

5%

2

1

C8416

805-3

CERM-X5R

MXM

6.3V

20%

22UF

2

1

C8415

10%
X7R

402

50V

0.001UF

MXM

E2
E1

9

7

5

3

1

280

278

J8400

F-RT-SM

B35P101-0121

MXM

84
86

90
92

96
98

102
104

108
110

114
116

120
122

136
138

48
50

54
56

60
62

66
68

72
74

78
80

142
144

148
150

19

85
87

91
93

97
99

103
105

109
111

115
117

121
123

135
137

49
51

55
57

61
63

67
69

73
75

79
81

141
143

147
149

156

153

155

224
226

218
220

212
214

206
208

236

230
232

217
219

211
213

205
207

199
201

234

223
225

264
266

258
260

252
254

246
248

274

270
272

271
273

265
267

259
261

253
255

276

277
279

154

J8400

F-RT-SM

B35P101-0121

MXM

CRITICAL

SYNC_MASTER=K62

MXM PCIe, DP & Power

SYNC_DATE=01/06/2011

MXM_DP_A_ML_N<2>

MXM_DP_A_ML_P<1>

MXM_DP_A_ML_P<0>

MXM_DP_A_ML_N<0>

MXM_RESET_L

MXM_DP_C_ML_N<0>
MXM_DP_C_ML_P<0>

MXM_DP_C_ML_P<1>

MXM_DP_C_ML_N<3>

MXM_DP_D_ML_N<1>

MXM_PCIE_STD_SWING_L

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_N<11>

MXM_DP_A_ML_N<1>

MXM_DP_A_ML_P<2>

MXM_PCIE_D2R_N<2>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<6>

MXM_PCIE_D2R_P<12>

MXM_PCIE_D2R_N<12>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<15>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_P<11>

MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_D2R_N<15>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<0>

MXM_PCIE_D2R_N<0>

MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<5>
MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<8>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_P<10>

MXM_PCIE_R2D_N<10>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_P<0>

MXM_PCIE_R2D_N<11>

MXM_PCIE_R2D_P<12>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_P<14>

MXM_PCIE_R2D_N<14>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_N<15>

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_P<11>

MXM_PCIE_R2D_N<13>

MXM_PCIE_R2D_N<12>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_N<0>

MXM_DP_C_AUX_P

MXM_DP_B_ML_N<0>

MXM_CLKREQ_L

MXM_DP_B_AUX_P

MXM_DP_B_HPD

MXM_DP_B_ML_P<0>

CLK_100M_MXM_N

CLK_100M_MXM_P

MXM_DP_C_HPD

MXM_DP_D_HPD

MXM_DP_A_HPD

MXM_DP_C_ML_N<1>

MXM_DP_D_ML_N<0>
MXM_DP_D_ML_P<0>

MXM_DP_C_ML_N<2>
MXM_DP_C_ML_P<2>

MXM_DP_D_ML_P<1>
MXM_DP_D_ML_N<2>

MXM_DP_C_ML_P<3>

MXM_DP_D_ML_P<2>
MXM_DP_D_ML_N<3>
MXM_DP_D_ML_P<3>

MXM_DP_B_ML_N<1>
MXM_DP_B_ML_P<1>
MXM_DP_B_ML_N<2>
MXM_DP_B_ML_P<2>
MXM_DP_B_ML_N<3>
MXM_DP_B_ML_P<3>

MXM_DP_C_AUX_N

MXM_DP_D_AUX_N
MXM_DP_D_AUX_P

MXM_DP_B_AUX_N

=PP3V3_S0_MXM

MXM_DP_A_AUX_N
MXM_DP_A_AUX_P

MXM_PCIE_D2R_N<3>

MXM_DP_A_ML_N<3>
MXM_DP_A_ML_P<3>

=PP3V3_S0_MXM

=PP12V_S0_MXM

=PP5V_S0_MXM

84 OF 110

11.1.0

051-8115

75 OF 98

78

78

78

78

9

83 93

83 93

83 93

83 93

78 93

76

77 90

77 90

77 90

77 90

78

78

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

83 93

78 93

9

97

78 93

78

78 93

9

9

83

78

78

83 93

78 93

78 93

83 93

83 93

78 93

78 93

83 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

83 93

78 93

78 93

78 93

6

21 64 75 76

78

78

77 90

78

78

6

21 64 75 76

6

6

www.vinafix.vn

GPIO0

VGA_DISABLE*

TH_OVERT*
TH_PWM

LVDS_DDC_CLK

LVDS_UTX1

LVDS_UTX2*

RSVD1

PNL_PWR_EN

LVDS_UTX1*

RSVD2

LVDS_UTX2

LVDS_UTX3*

LVDS_LCLK

PRSNT_R*

LVDS_LTX3

DVI_HPD

PWR_EN

SMB_CLK

LVDS_LTX0

LVDS_LTX0*

LVDS_LTX1

LVDS_LTX2

LVDS_LTX2*

LVDS_LTX3*

LVDS_UTX0

LVDS_UTX0*

LVDS_UTX3

PNL_BL_EN

PRSNT_L*

PWRGOOD

VGA_BLUE
VGA_GREEN
VGA_HSYNC
VGA_RED
VGA_VSYNC

VGA_DDC_DAT

GPIO1
GPIO2

HDMI_CEC

OEM0
OEM1
OEM2
OEM3
OEM4
OEM5

OEM7

VGA_DDC_CLK

RSVD3
RSVD4
RSVD5

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19

RSVD21

SMB_DAT

TH_ALERT*

LVDS_UCLK*
LVDS_UCLK

RSVD20

LVDS_LCLK*

LVDS_LTX1*

RSVD6

RSVD0

RSVD22
RSVD23

PWR_LEVEL

LVDS_DDC_DAT

PNL_BL_PWM

OEM6

WAKE*

SYSTEM MANAGEMENT

(1 OF 4)

LVDS

ANALOG DISPLAY

POWER/THERMAL

MANAGEMENT

GNDGND

(3 OF 4)

SCL

THRM_PAD

E0
E1
E2

VSS

SDA

VCC

WC*

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

I2C ADDRESS: A8

- =PP3V3_S0_MXM

STUFF FOR WRITE PROTECT

PLACE CLOSE TO J8400

FLOAT = LOW SWING
GND = HIGH SWING

Signal aliases required by this page:

Page Notes

Power aliases required by this page:

- =PM_MXM_PGOOD_PULLUP

PULLED TO GROUND ON MXM
WE DON’T USE CARD DETECT

OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR

SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,

- =SMB_MXM_THRM_DATA

PULLUPS & PULLDOWNS AT MXM CONNECTOR

FLOAT = NORMAL VGA MODE
GND = SECONDARY DISPLAY CARD

BOM options provided by this page:

- =SMB_MXM_THRM_CLK

MXM SYSTEM INFORMATION ROM

2

1

R8570

1/16W

5%

NOSTUFF

0

MF-LF

402

2

1

C8570

0.1UF

402

CERM

20%
10V

MXM

21

R8500

100K

1/16W

5%

402

MF-LF

21

R8501

100K

5%

MF-LF 1/16W

402

2 1

R8503

402

MF-LF

5%

10K

1/16W

4

162

168

164

170

21

158

160

172

24

20

22

32

34

231

229

227

167

165

163

161

16

14

249

247

12

245

243

242

241

240

239

238

237

235

233

159

10

6

18

8

2

281

23

27

25

45

44

43

42

41

40

39

38

175
177

181
183

187
189

193
195

169
171

182
184

188
190

194
196

200
202

176
178

33

35

29

30

28

2631

J8400

B35P101-0121

MXM

F-RT-SM

53

52

283

282

E4

275

269

268

263

47

262

257

256

251

250

E3

244

228

222

221

46

216

215

210

209

204

203

198

197

192

191

37

186

185

180

179

174

173

166

157

152

151

36

146

145

140

139

134

133

125

124

119

118

17

113

112

107

106

101

100

95

94

89

88

15

83

82

77

76

71

70

65

64

59

58

13

11

J8400

F-RT-SM

MXM

B35P101-0121

2 1

R8504

MXM

0

402

5%

MF-LF 1/16W

2 1

R8510

NOSTUFF

0

5%

402

MF-LF 1/16W

7

489

5

6

3

2

1

U8570

OMIT

M24C02

MLP8

CRITICAL

2

1

R8575

4.7K

MF-LF

1/16W

5%

402

2

1

R8576

402

5%
1/16W
MF-LF

4.7K

2

1

R8579

4.7K

402

MF-LF

NOSTUFF

5%

1/16W

2

1

R8580

1/16W

5%

4.7K

MF-LF

NOSTUFF

402

SYNC_MASTER=K60_MASTER

MXM I/O

SYNC_DATE=N/A

=PP3V3_S0_MXM

MXM_PNL_PWR_EN

TP_MXM_N_TDI
TP_MXM_N_TCK
TP_MXM_N_TMS

MXM_A_TESTEN

TP_MXM_A_TDO

TP_MXM_A_TRST_L

MXM_PNL_BL_PWM

TP_MXM_A_TCK

TP_MXM_N_TRST_L

=PP3V3_S0_MXM

TP_MXM_VGA_DDC_DAT

TP_MXM_N_TDO

=PP3V3_S0_MXM

TP_MXM_A_TDI
TP_MXM_A_TMS

MXM_LVDS_A_CLK_P

MXM_PNL_BL_EN

TP_MXM_HDMI_CEC

MXM_VGA_DISABLE_L

TP_MXM_GPIO0

MXM_LVDS_DDC_DAT

MXM_DETECT_L

TP_MXM_WAKE_L

PM_MXM_PGOOD

MXM_VGA_DISABLE_L

MXM_PCIE_STD_SWING_L

MXM_DETECT_R

MXM_LVDS_A_DATA_N<0>
MXM_LVDS_A_DATA_P<0>

MXM_DETECT_L

PM_MXM_EN

MXM_PWR_LEVEL

=SMB_MXM_THRM_SCL
=SMB_MXM_THRM_SDA

MXM_LVDS_A_DATA_N<1>
MXM_LVDS_A_DATA_P<1>

MXM_LVDS_A_DATA_P<2>

MXM_LVDS_A_DATA_N<3>
MXM_LVDS_A_DATA_P<3>

MXM_LVDS_B_CLK_P

MXM_LVDS_B_CLK_N

MXM_LVDS_B_DATA_P<3>

MXM_LVDS_B_DATA_N<3>

MXM_LVDS_B_DATA_N<2>

MXM_LVDS_B_DATA_P<1>

MXM_LVDS_B_DATA_N<1>

MXM_LVDS_B_DATA_P<0>

MXM_LVDS_B_DATA_N<0>

MXM_LVDS_B_DATA_P<2>

PM_MXM_PGOOD

MXM_LVDS_A_DATA_N<2>

TP_MXM_VGA_BLUE

TP_MXM_VGA_RED

TP_MXM_VGA_DDC_CLK

MXM_LVDS_A_CLK_N

TP_MXM_DVI_HPD

MXM_LVDS_DDC_DAT

MXM_LVDS_DDC_CLK

TP_MXM_GPIO1
TP_MXM_GPIO2

=PM_MXM_PGOOD_PULLUP

MXM_ALERT_L
MXM_OVERT_L

TP_MXM_VGA_VSYNC

TP_MXM_VGA_HSYNC

TP_MXM_TH_PWM

TP_MXM_VGA_GREEN

MXM_DETECT_R

MXM_ROM_WP

MXM_LVDS_DDC_CLK

85 OF 110

11.1.0

051-8115

76 OF 98

6

21 64 75 76

78

83 97

6

21 64 75 76

6

21 64 75 76

78 93

78

76

76

76

64 76 97

76

75

76

78 93

78 93

76

64 97

47

49

49

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

64 76 97

78 93

78 93

76

76

64

47

47

76

76

www.vinafix.vn

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MXM TX CAPS

MXM RX CAPS

9

90

2

1

C8636

10% X5R

0.1UF

40216V

MXM

75 90

75 90

2

1

C8600

40216V

0.1UF

X5R10%

MXM

2

1

C8602

402X5R10% 16V

0.1UF

MXM

2

1

C8601

0.1UF

16V X5R10% 402

MXM

2

1

C8604

10%

0.1UF

X5R 40216V

MXM

2

1

C8603

0.1UF

402X5R10% 16V

MXM

9

90

9

90

9

90

75 90

9

90

9

90

2

1

C8605

10% 402

0.1UF

X5R16V

MXM

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

2

1

C8606

10% 16V 402

0.1UF

X5R

MXM

2

1

C8607

X5R10% 16V

0.1UF

402

MXM

2

1

C8608

MXM

16V X5R 402

0.1UF

10%

2

1

C8609

10% 16V X5R 402

0.1UF

MXM

2

1

C8610

0.1UF

16V10% X5R 402

MXM

2

1

C8611

0.1UF

10% 16V X5R 402

MXM

2

1

C8612

10% X5R

0.1UF

40216V

MXM

2

1

C8613

10% 16V X5R 402

0.1UF

MXM

2

1

C8614

16V10% X5R 402

0.1UF

MXM

2

1

C8615

16V10% X5R 402

0.1UF

MXM

75 90

2

1

C8616

0.1UF

16V10% X5R 402

MXM

2

1

C8618

16V10% X5R 402

0.1UF

MXM

2

1

C8617

16V10% X5R 402

0.1UF

MXM

2

1

C8620

16V10% X5R 402

0.1UF

MXM

2

1

C8619

10% X5R 402

0.1UF

MXM

16V

2

1

C8622

0.1UF

402X5R10% 16V

MXM

2

1

C8621

16V10% X5R 402

0.1UF

MXM

9

90

9

90

9

90

2

1

C8637

10%

0.1UF

X5R 40216V

MXM

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

2

1

C8623

0.1UF

402X5R10% 16V

MXM

2

1

C8624

16V10% X5R 402

0.1UF

MXM

2

1

C8625

16V10% X5R 402

0.1UF

MXM

2

1

C8626

0.1UF

402X5R10% 16V

MXM

2

1

C8628

402X5R10% 16V

0.1UF

MXM

9

90

2

1

C8627

0.1UF

402X5R10% 16V

MXM

2

1

C8630

0.1UF

402X5R10% 16V

MXM

2

1

C8629

0.1UF

402X5R10% 16V

MXM

2

1

C8631

0.1UF

402X5R10% 16V

MXM

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

2

1

C8638

0.1UF

X5R10% 40216V

MXM

2

1

C8639

0.1UF

402X5R10% 16V

MXM

2

1

C8641

0.1UF

16V 402X5R10%

MXM

2

1

C8640

0.1UF

40210% X5R16V

MXM

2

1

C8642

0.1UF

402X5R10% 16V

MXM

2

1

C8643

402X5R10% 16V

0.1UF

MXM

9

90

2

1

C8644

0.1UF

402X5R10% 16V

MXM

2

1

C8645

402X5R10% 16V

0.1UF

MXM

2

1

C8646

0.1UF

402X5R10% 16V

MXM

2

1

C8647

0.1UF

10% 16V 402X5R

MXM

2

1

C8648

0.1UF

16V10% X5R 402

MXM

2

1

C8649

40216V10% X5R

0.1UF

MXM

2

1

C8652

16V10% X5R 402

0.1UF

MXM

2

1

C8653

16V10% X5R 402

0.1UF

MXM

2

1

C8651

0.1UF

16V10% X5R 402

MXM

2

1

C8650

0.1UF

16V10% X5R 402

MXM

2

1

C8632

0.1UF

40210% 16V X5R

MXM

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

2

1

C8633

0.1UF

40210% 16V X5R

MXM

75 90

75 90

75 90

75 90

75 90

75 90

75 90

2

1

C8654

16V10% X5R

0.1UF

402

MXM

2

1

C8655

16V10% X5R

0.1UF

402

MXM

2

1

C8657

16V X5R 402

0.1UF

10%

MXM

2

1

C8635

16V10% 402

0.1UF

X5R

MXM

2

1

C8656

10% X5R 402

0.1UF

16V

MXM

2

1

C8658

MXM

16V10% X5R 402

0.1UF

2

1

C8662

16V X5R10% 402

MXM

0.1UF

2

1

C8663

16V10% X5R 402

0.1UF

MXM

2

1

C8660

16V X5R 40210%

0.1UF

MXM

2

1

C8659

16V10% X5R 402

0.1UF

MXM

2

1

C8661

16V10% X5R 402

0.1UF

MXM

75 90

75 90

75 90

2

1

C8634

16V 40210%

0.1UF

X5R

MXM

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

SYNC_MASTER=K62

MXM PCIE CAPS

SYNC_DATE=01/06/2011

PEG_R2D_C_N<1>

PEG_R2D_C_N<2>

PEG_R2D_C_P<3>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<8>

MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_P<2>

PEG_D2R_P<14>

MXM_PCIE_D2R_N<5>

PEG_R2D_C_P<4>

MXM_PCIE_R2D_N<14>

PEG_R2D_C_P<11>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>

MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<11>

MXM_PCIE_D2R_N<15>

PEG_D2R_N<0>

PEG_D2R_N<3>

PEG_D2R_N<12>

PEG_D2R_N<10>

PEG_R2D_C_N<5>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<0>

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<12>

PEG_R2D_C_N<0>

MXM_PCIE_R2D_P<14>

MXM_PCIE_R2D_N<10>

PEG_R2D_C_P<13>

PEG_R2D_C_P<14>
PEG_R2D_C_N<14>

PEG_R2D_C_P<15>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_N<12>

MXM_PCIE_D2R_N<14>

MXM_PCIE_D2R_P<14>

MXM_PCIE_R2D_P<10>

PEG_R2D_C_P<10>

MXM_PCIE_R2D_P<5>

PEG_D2R_P<4>

PEG_R2D_C_N<12>

PEG_R2D_C_P<12>

PEG_R2D_C_N<10>

PEG_R2D_C_P<5>

PEG_R2D_C_P<6>
PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_P<8>
PEG_R2D_C_N<8>

PEG_R2D_C_N<11>

PEG_R2D_C_N<9>

PEG_R2D_C_P<9>

PEG_R2D_C_N<7>

MXM_PCIE_R2D_N<5>

MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_N<2>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_N<0>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_P<0>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_N<11>

MXM_PCIE_D2R_P<11>

PEG_D2R_P<7>

PEG_D2R_P<12>

PEG_D2R_N<6>

PEG_D2R_N<7>

PEG_D2R_P<10>

PEG_D2R_N<4>

PEG_D2R_N<9>
PEG_D2R_P<9>

PEG_D2R_N<11>

PEG_D2R_P<13>
PEG_D2R_N<13>

PEG_D2R_P<15>

PEG_D2R_N<15>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<11>

PEG_D2R_P<6>

PEG_D2R_P<2>

PEG_D2R_N<2>

MXM_PCIE_R2D_N<13>

PEG_D2R_P<3>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<15>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<0>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_P<6>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_R2D_C_P<0>

PEG_R2D_C_N<4>

PEG_R2D_C_N<3>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_N<15>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_P<12>

MXM_PCIE_D2R_N<2>

PEG_D2R_N<14>

86 OF 110

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051-8115

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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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R

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SHEET

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

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345678

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8 7 5 4 2 1

Unused T29 Interfaces

UNUSED MXM CONTROL SIGNALS

T29 MXM DP ALIAS

T29 CONN POWER CONTROL ALIAS

Unused MXM Interfaces

MXM ALIAS

BOM options provided by this page:

Signal aliases required by this page:
(NONE)

Power aliases required by this page:

(NONE)

Page Notes

DDC/AUX ALIAS

SYNC_MASTER=K60_AARON

DP ALIAS AND CONTROL

SYNC_DATE=07/18/2010

DP_EXTA_AUXCH_C_P

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA

DP_EXTA_AUXCH_C_N

MAKE_BASE=TRUE

DP_EXTA_DDC_CLK

NC_MXM_LVDS_A_DATA_N<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MXM_LVDS_B_DATA_N<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MXM_PNL_PWR_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_MXM_PNL_BL_EN

MAKE_BASE=TRUE

MXM_DP_A_HPD

MXM_DP_A_AUX_N

MXM_DP_A_AUX_P

MXM_DP_A_ML_N<0..3>

MXM_DP_A_ML_P<0..3>

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_N

NO_TEST=TRUE

DP_EXTA_ML_C_P<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_EXTA_ML_C_N<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_P

NO_TEST=TRUE

=T29_WAKE_LPCIE_WAKE_L

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_T29SNK0_AUXCH_C_N

DP_T29SNK0_ML_C_P<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_T29SNK0_AUXCH_C_P

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_T29SNK0_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_T29SNK1_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_T29SNK1_AUXCH_C_P

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_T29SNK1_ML_C_N<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_T29SNK1_ML_C_P<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MXM_DP_B_ML_P<0..3>

MXM_DP_B_ML_N<0..3>

MXM_DP_B_AUX_P

MXM_DP_B_AUX_N

MXM_DP_B_HPD

DP_EXTA_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

MXM_LVDS_B_DATA_N<3..0>

MXM_LVDS_B_DATA_P<3..0>

NC_MXM_LVDS_A_DATA_P<3..0>
MAKE_BASE=TRUE

NO_TEST=TRUE

MXM_LVDS_A_DATA_P<3..0>

T29_D2R_N<2..3>

T29_D2R_P<2..3>

MXM_LVDS_B_CLK_N

MXM_LVDS_B_CLK_P

NC_MXM_LVDS_B_CLK_P
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MXM_LVDS_A_CLK_P
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MXM_LVDS_A_CLK_N
MAKE_BASE=TRUE

NO_TEST=TRUE

MXM_LVDS_A_CLK_P

MXM_LVDS_A_CLK_N

NC_MXM_LVDS_B_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

MXM_LVDS_A_DATA_N<3..0>

MXM_PNL_BL_EN

MXM_PNL_PWR_EN

NO_TEST=TRUE

NC_T29_R2D_C_P<2..3>
MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_T29_D2R_N<2..3>

T29_LSEO<2>

T29_R2D_C_N<2..3>

T29_LSEO<3> T29_LSOE<3>

T29_R2D_C_P<2..3>

PP3V3_SW_DPAPWR

=PP3V3_SW_DPAPWR

MXM_DP_D_AUX_N

MXM_DP_D_HPD

DP_T29SNK0_ML_C_N<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_T29SNK1_AUXCH_C_N

MXM_DP_D_AUX_P

MXM_DP_D_ML_N<0..3>

MXM_DP_D_ML_P<0..3>

T29_LSOE<2>

MAKE_BASE=TRUE

T29_LSEO_LSEO2

NO_TEST=TRUE

MAKE_BASE=TRUE

T29_LSEO_LSOE3

NO_TEST=TRUE

NO_TEST=TRUE

NC_T29_R2D_C_N<2..3>
MAKE_BASE=TRUE

NC_T29_D2R_P<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

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051-8115

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75

75

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78 84 93

84 19 33 36 97

86 96

86 96

86 96

86

86

86 96

86 96

86 96 75 93

75 93

75 93

75 93

75

84

76 93

76 93

76 93

86 96

86 96

76 93

76 93

76 93

76 93

76 93

76

76

86

86 96

86 86

86 96

84 95

6

75 93

75

86 96

86 96

75 93

75 93

75 93

86

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NC

NC

OUT

OUT

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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A

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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8 7 5 4 2 1

For SB RTC Power

For Caesar-IV (BCM57765): VDDIO = XTALVDDH (3.3V), Vclk = 3.3V Max. No Divider Necessary

VDD_25M: 3.3V matching ’highest’ VDDIO power state (ENET)

VDDIO_25M_A: SB power rail for XTAL circuit.

VDDIO_25M_C: T29 power rail for XTAL circuit.

VBAT: Alias as appropriate (see note below & Desktop Example)

System RTC Power Source & 32kHz / 25MHz Clock Generator

For Cougar Point Mobile: VDDIO = VCCVRM (1.5V), Vclk = 1.1V Max, Divider: 332 / 1000

GreenCLK Implementation Notes:

VDDIO_25M_B: Ethernet power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

For Cougar Point Desktop: VDDIO = VCCVRM (1.8V), Vclk = 1.1V Max, Divider: 604 / 1000

(1.1V)

+V3.3A should be first

(3.3V)

+V3.3A: Alias as appropriate (see note below)

Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5

internally ORed to

to reduce VBAT draw.

available ~3.3V power

(1.8V)

VBAT and +V3.3A are

create VDD_RTC_OUT.

No Coin-Cell: 3.3V S5

No bypass necessary

NOTE: 30 PPM crystal required

2

1

R8816

1/16W

1M

402

5%

MF-LF

NOSTUFF

2

1

C8802

10%

6.3V

CERM
402

1UF

2

1

C8810

CERM

6.3V

10%

402

1UF

21

C8806

402

50V

5%

12PF

CERM

2 1

C8805

12PF

CERM

5%

50V

402

2

1

C8824

T29

CERM

402

20%

10V

0.1UF

2

1

C8822

CERM

402

0.1UF

20%

10V

2

1

C8820

402

CERM

20%

10V

0.1UF

31

42

Y8805

CRITICAL

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM

2

1

R8826

1%

MF-LF
402

1/16W

140

21

R8825

40.2

MF-LF

1%

402

1/16W

18 27 91

86 96

21

R8843

33

MF-LF

1/16W

402

5%

36 96

2

1

R8808

402

MF-LF

1/16W

5%

10K

21

R8806

1/16W

402

MF-LF

5%

NOSTUFF

0

21

R8807

402

MF-LF

5%

0

1/16W

21

R8810

T29

1/16W

5%

0

402

MF-LF

21

R8809

5%

MF-LF

0

NOSTUFF

402

1/16W

21

R8812

402

0

1/16W
MF-LF

5%

21

R8815

402

0

1/16W

5%

MF-LF

3
4

14

6

11

1

5172

13

16107

12

15

8

9

U8800

TQFN

CRITICAL

SLG3NB148V

21

R8845

T29

5%

402

1/16W
MF-LF

47

GREEN CLOCK

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_X1

=PP3V3_S3_SYSCLK

PPVBAT_G3_SYSCLK_R

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVDDIO_25M_A

=PP3V3_T29_RTR

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVDDIO_25M_C

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PPVDDIO_25M_B

MIN_LINE_WIDTH=0.3 mm

ENET_CLK25M_XTALI_OSC

=PP3V3_S3_ENET_PHY_FET

SYSCLK_CLK25M_SB

PCH_CLK25M_XTALIN

TP_SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_T29_CLK

SYSCLK_CLK25M_T29

SYSCLK_CLK25M_X2

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_S3_ENET_PHY_FET

=PP1V8R1V5_S0_PCH_VCCVRM

TP_PPVRTC_G3_OUT

SYSCLK_CLK25M_ENET

=PP1V05_S0_PCH

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6

24 79

96

6

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www.vinafix.vn

GND

VOUT

ON

VIN

OUT

IN

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

D

GS

OUT

D

S

G

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

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R

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SHEET

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C

A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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8 7 5 4 2 1

Max Output: 2A

R(on)

TPS22924C

3.3V T29 Switch

T29 CLKREQ# ISOLATION

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

- =PP1V05_T29_FET (1.05V FET Output)

1.05V T29 Switch

DLY = 60 ms +/- 20%

- T29_RESET_L

Signal aliases required by this page:

- =PP3V3_T29_FET (3.3V FET Output)

- =PP3V3_S0_T29PWRCTL

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

Page Notes

Power aliases required by this page:

Pull-up provided by SB page.

Platform (PCIe) Reset

18 mOhm Typ

BOM options provided by this page:

Open-Drain GPIO

Max Current = 1.7A (85C)

Supervisor & CLKREQ# Isolation

(NONE)

- =T29_CLKREQ_L

Load Switch

50 mOhm Max

U8910

Part

Type

B1

A1

B2

A2

C2

C1

U8910

T29

CRITICAL

CSP

TPS22924

86 97

1

2

R8903

1/16W

5%

10K

402

MF-LF

2

1

C8900

T29

0.1UF

25V
X5R

10%

402

27 97

86

2

1

C8910

T29

402

CERM

6.3V

10%

1UF

1

9

2

4

8

3

7

5

6

U8900

SLG4AP016V

T29

CRITICAL

TDFN

2

1

R8907

T29

MF-LF

100K

1/16W

402

5%

15 21 91

2

1

R8906

1/16W

10K

402

5%

MF-LF

2

1

C8930

T29

402

X5R

16V

10%

0.1UF

2

1

R8930

T29

MF-LF

10K

1/16W

5%

402

1

9

6

8

2

4

7

5

U8930

T29

CRITICAL

TDFN

SLG5AP001

18 97

2

1

3

Q8950

T29

SOD-VESM-HF

SSM3K15FV

15 21 91

1

2

R8904

T29

MF-LF

402

10K

5%

1/16W

321

4

5

Q8930

T29

BSZ035N03MSG

P-TSDSON-8

CRITICAL

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

T29 POWER

PM_PGOOD_P1V05_S0_T29_FET

PP3V3_T29_FET

T29_RESET_RTR_L

=PP3V3_T29_RTR

=PP12V_S0_PWRCTL

=PP3V3_S0_PWRCTL

=PP3V3_S0_P3V3T29FET

T29_SW_RESET_L

=PP1V05_T29

T29_RESET_L

=PP3V3_S0_T29PWRCTL

T29_CLKREQ_ISOL_L

MAKE_BASE=TRUE

=T29_CLKREQ_L

T29_CLKREQ_L

=PP3V3_T29_RTR

T29_PWR_EN

P1V05_S0_T29_EN

PP1V05_T29_FET

=PP1V05_S0_P1V05T29FET

T29_CLKREQ_FET_L

89 OF 110

11.1.0

051-8115

80 OF 98

3

6

6

79 80 86 87

6

63 64

6

63 64 73

6

6

6

6

79 80 86 87

6

6

www.vinafix.vn

IN
IN

IN
IN

IN
IN

IN

IN

OUT

OUT

BI
BI

OUT

BI

OUT

OUT

OUT

BI

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

used by diag LED

I2C MASTER ON TCON

BACKLIGHT CONTROL SUPPORT

only on when Panel has valid video

guarantee backlight is

- =PP12V_S0_LCD

- =PP3V3_S0_VIDEO

I2C SLAVE ON TCON

518S0787

INTERNAL DP POWER

518S0778

IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

Page Notes

INTERNAL DP INTERFACE

Power aliases required by this page:

21

R9050

1/16W

5%

402

MF-LF

0

21

R9051

1/16W
MF-LF

402

0

5%

83 93

2

1

C9001

CERM

0.001uF

402

20%
50V

83 93

83 93

83 93

83 93

83 93

83 93

83 93

2

1

C9020

X5R-CERM
0805

10%

10UF

16V

31

D9000

SOT23

BAT54XG

21

R9009

19.1K

402

1%
1/16W
MF-LF

21

R9011

47

1/16W
MF-LF

402

5%

6

97

2

1

C9005

805

20%

22UF

CERM

6.3V

4

5

2

3

U9000

74AUP2G14GM

SOT886

5

21

R9010

5%

603

0

MF-LF

1/10W

83 93

83 93

6

49 94

6

49 94

6

5

2

1

U9000

74AUP2G14GM

SOT886

2

1

C9006

402

10V

0.1UF

CERM

20%

83 97

81 97

83 97

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9002

CABLINE-CA

CRITICAL

F-RT-SM

6

5

4

3

2

1

8

7

J9001

53780-8606

M-RT-SM

CRITICAL

49

49

2

1

C9010

NOSTUFF

5%

47PF

50V
CERM
402

2

1

C9011

NOSTUFF

5%

47PF

50V
CERM
402

21

L9000

SM

FERR-250-OHM

SYNC_DATE=01/06/2011

Display: Int DP Connector

SYNC_MASTER=K62

NO_TEST

DP_INTPNL_ML_P<1>

SMB_BLC_TCON_SDA

I2C_TCON_SDA

SMB_BLC_TCON_SCL

DP_INTPNL_AUX_P

DP_INT_SPDIF_AUDIO

TP_OPTION1

DP_INTPNL_AUX_N

TP_OPTION2

=PP3V3_S0_DP

BL_EN

PP12V_LCD
VOLTAGE=12V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

=PP12V_S0_LCD

SMB_DP_TCON_SLA_SCL

SMB_DP_TCON_SLA_SDA

LCD_BKL_ON_DLY

VIDEO_ON

=PP3V3_S0_DP

VIDEO_ON

DP_INTPNL_HPD

VIDEO_ON_L_DLY

VIDEO_ON_L

NO_TEST

DP_INTPNL_ML_P<3>

NO_TEST

DP_INTPNL_ML_N<1>

VSYNC_DP_CONN

NO_TEST

DP_INTPNL_ML_N<3>

NO_TEST

DP_INTPNL_ML_N<2>

NO_TEST

DP_INTPNL_ML_P<2>

VSYNC_DP

DP_INTPNL_ML_N<0>

NO_TEST

NO_TEST

DP_INTPNL_ML_P<0>

I2C_TCON_SCL

90 OF 110

11.1.0

051-8115

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94

6

81

95

6

81 97

6

81

6

97

94

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SS

ENABLE

GND

THRM

VIN

PG

VOUT

ADJ

ISET

PAD

CT

EN*

RTRY*

VIN

THRM

GND

IFLT

ILIM

FLT*

VOUT

PAD

G

D

S

G

D

S

D

G S

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VO=3.304V

<RB2>

2V9 measured at CDR

(IPU-Weak!)

TSD = CCT * 100000

ILIM = 201K / RLIM = 1.155A.

IFLT = 200K / RFLT = 2A

TFLT = CCT * 38900

<CT>

HI: 2V9 FOR T29

<RB1>

LO: 3V3 FOR DP

TSD 470ms 235ms 724ms

<RFLT>

12V T29 PORTA SUPPLY

3V3(DP)/2V9(T29) PORTA SUPPLY

<RA>

12 WATTS MAX PER PORT

12 VOLTS

<RLIM>

(*) U9410 tolerance unknown

TFLT 18.3ms 13.4ms 26.7ms

ILIM 935mA 925mA 944mA (*)

IFLT 885mA 876mA 894mA (*)

Nominal Min Max

NEED TO UPDATE TABLE BELOW LATER

VO=0.5*(1+ RA/RB)

2

1

R9150

1/10W
MF-LF

5%

603

2.2K

21

D9105

DSN2

NSR20F20NXT5G

T29

5

4

1

2

3

U9120

MC74VHC1G08

SOT23-5-HF

T29

2

1

C9150

10%
16V

402

X5R

0.1UF

T29

2

1

C9124

16V

10%

10UF

X5R-CERM
0805

2

1

R9112

MF-LF

1/16W

402

5%

0

T29

3

1

D9103

SOT23

MMBZ5227BLT1H

CRITICAL

T29

2

1

R9117

13K

NOSTUFF

1/16W

5%

402

MF-LF

21

R9128

0

402

5%

MF-LF

1/16W

NO_T29

2

1

10

9

11

6

4

8

5

7 3

U9101

CRITICAL

DFN

ISL80101A

2

1

R9124

11.5K

1/16W
MF-LF

1%

402

12

11

10

4

3

2

1

17

6 7

8

14

13

5

1516

9

U9110

T29

CRITICAL

SN1010017

QFN

2

1

C9123

330PF

50V

10%

402

CERM

2

1

C9120

X5R-CERM

10%

0805

16V

10UF

2

1

C9121

CERM-X5R

16V

0.022UF

10%

402

2

1

C9125

NOSTUFF

0805

16V

10%

10UF

X5R-CERM

2

1

C9122

10UF

0805

10%
X5R-CERM

16V

2

1

R9121

402

5%

1/16W

20K

MF-LF

2

1

R9123

2.05K

1/16W
MF-LF

402

1%

4

5

3

Q9120

SOT-363

2N7002DW-X-G

NOSTUFF

2

1

R9126

NOSTUFF

402

MF-LF

1/16W

5%

10K

1

2

6

Q9120

NOSTUFF

2N7002DW-X-G

SOT-363

2

1

R9125

NOSTUFF

402

1%

1/16W
MF-LF

15.0K

2

1

R9122

MF-LF

1/16W

5%

100K

402

21

D9101

POWERDI-123

DFLS260

2

1

R9130

1%

1/16W

25.5K

MF-LF

402

2

1

C9111

X7R

0.1UF

10%
50V

603-1

T29

2

1

C9110

0.1UF

10%

X7R

50V

603-1

T29

2

1

R9116

1/16W

5%

402

MF-LF

15K

T29

2

1

R9111

174K

1%

402

1/16W
MF-LF

T29

2

1

R9110

100K

1%

1/16W

402

MF-LF

T29

2

1

3

Q9115

SSM3K15FV

SOD-VESM-HF

T29

84 97

SYNC_MASTER=K62

SYNC_DATE=11/14/2010

2V9/3V3/12V POWER SWITCH

=PP5V_S3_P3V3R2V9_REG_A

DPAPWRSW_HVEN_L_R

DPAPWRSW_CT

=PP12V_S5_T29_A

DPAPWRSW_IFLT

DPAPWRSW_ILIM

TP_DPAPWRSW_FLT_L

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=12V

PP3V3R12V_SW_DPAPWR_D

3V3R2V9_SS_A

T29_DP_PORTA_PWR_EN_REG

PM_PGOOD_P3V3_2V9_A

NET_PHYSICAL_TYPE=POWER

MIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PP3V3R2V9_DPAPWR_D

3V3R2V9_DPAPWR_ADJ

80101A1_ISET

DP_A_PWRDWN_FET_R

T29_A_BIAS

PP3V3R12V_SW_DPAPWR

VOLTAGE=12V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

=PP3V3_S3_PWRCTL

T29_A_HV_EN

NET_PHYSICAL_TYPE=POWER

MIN_LINE_WIDTH=0.38 MM
VOLTAGE=12V

PP3V3R12V_SW_DPAPWR

MIN_NECK_WIDTH=0.20 MM

=PP3V3_S5_P3V3R2V9_A

PM_SLP_S3_L

PM_PGOOD_P5V_S3_REG

=PP3V3_S3_P3V3R2V9_REG_A

DP_A_PWRDWN_INV

T29_DP_PORTA_PWR_EN

T29_DP_PORTA_PWR_EN_REG

91 OF 110

11.1.0

051-8115

82 OF 98

6

97

97

6

97

97

95

82 97

95 97

84 85 96

82 85

6

64 73

82 85

6

5

19 26

32 36 46

47 63 97

63
70

97

6

97

20
25

91

97

82 97

www.vinafix.vn

S

GND

OUTPUT

MUX

SELECTOR

I1
I0

Y

VCC

IN
IN

IN

OUT

IN

DDC_DAT2

XSD*

GPU_SEL

HPD_2

DDC_CLK2

DIN2_3-

DIN2_3+

DIN2_2-

DIN2_2+

DIN2_1-

DIN2_1+

DAUX2+
DAUX2-

DIN2_0+
DIN2_0-

DDC_DAT1

DDC_CLK1

HPD_1

DAUX1-

DAUX1+

DIN1_0-

DIN1_1+

DIN1_3-

DIN1_1-

DIN1_2+

DIN1_0+

DIN1_2-

DIN1_3+

TST0

DDC_AUX_SEL

HPDIN

AUX+
AUX-

DOUT_3-

DOUT_3+

DOUT_1-

DOUT_2-

DOUT_2+

DOUT_1+

DOUT_0+
DOUT_0-

GND

VDD

BI
BI

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN
IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

NC
NC

OUT

NC

NC

IN

IN
IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

S

GND

OUTPUT

MUX

SELECTOR

I1

I0

Y

VCC

IN

IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(For each pair)

4

5

6

1
3

2

U9220

SOT487

74LVC1G157

T29

46 97

76 97

18 61 83 91

2 1

R9222

1/16W

5%

402

47

MF-LF

21

L9201

0402

FERR-220-OHM

6

97

2

1

R9227

NOSTUFF

MF-LF

5%

1/16W

100K

402

2

1

R9230

NOSTUFF

MF-LF

402

10K

5%

1/16W

2

1

R9237

10K

1/16W

5%

402

MF-LF

81 97

21

C9211

402X5R

10% 16V

0.1uF

T29

21

C9212

0.1uF

402

16V10%

X5R

T29

B7

J4

A2

G2

J1

H3

J2

A1

H7H4G8C8B3

F2
F1

E2
E1

D2
D1

B2
B1

F8
F9

E8
E9

D8
D9

B8
B9

A8
A9

B6
A6

B5
A5

B4
A4

J5

J8

H5

H8

C2

H6
J6

H9
J9

H2
H1

U9200

TFBGA

CBTL06142CEEG

CRITICAL

21

C9213

0.1uF

X5R

10% 16V

402

21

C9214

402

0.1uF

X5R

10%16V

2

1

R9240

402

5%
1/16W
MF-LF

470K

2

1

R9242

1/16W
MF-LF

402

5%

470K

2

1

R9245

402

MF-LF

1/16W

5%

470K

T29

2

1

R9244

402

5%

1/16W

470K

MF-LF

T29

2

1

R9249

100K

5%
1/16W
MF-LF

402

2

1

R9248

470K

1/16W
MF-LF

5%

402

NOSTUFF

2

1

R9250

100K

MF-LF

402

5%

1/16W

2

1

R9251

470K

5%

1/16W

402

MF-LF

NOSTUFF

81 93

81 93

21

C9210

10% 16V
X5R 402

0.1uF

21

C9215

0.1uF

X5R

10% 16V

402

21

C9250

402X5R

16V10%

0.1uF

T29

21

C9251

10% 16V
X5R 402

0.1uF

T29

21

C9252

X5R

16V10%
402

0.1uF

T29

21

C9253

10% 16V
X5R 402

0.1uF

T29

21

C9254

X5R

16V10%
402

0.1uF

T29

21

C9255

10% 16V
X5R 402

0.1uF

T29

21

C9256

X5R

16V10%
402

0.1uF

T29

21

C9257

10% 16V
X5R 402

0.1uF

T29

2

1

R9261

MF-LF

402

5%

1/16W

470K

T29

2

1

R9263

MF-LF

470K

1/16W

5%

402

T29

2

1

R9265

1/16W
MF-LF

5%

402

470K

T29

2

1

R9267

1/16W
MF-LF

5%

402

470K

T29

2

1

R9266

402

5%

MF-LF

1/16W

470K

T29

2

1

R9264

MF-LF

5%

402

470K

1/16W

T29

2

1

R9262

470K

1/16W
MF-LF

402

5%

T29

2

1

R9260

402

5%

MF-LF

1/16W

470K

T29

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

83 96

83 96

83 96

83 96

83 96

83 96

83 96

83 96

2

1

C9209

10%

1UF

10V
X5R
402-1

2

1

R9228

100K

1/16W

5%

MF-LF

402

2 1

R9223

5%

MF-LF

1/16W

0

402

2

1

C9273

10%
16V
X5R
402

0.1uF

NOSTUFF

2 1

R9225

NO_T29

402

5%

MF-LF

1/16W

0

2 1

R9226

NO_T29

1/16W
MF-LF

5%

402

0

83 96

83 96

83 96

83 96

83 96

83 96

83 96

83 96

86 96

86 96

86

75

2

1

C9269

402

10%
16V
X5R

0.1uF

2

1

C9268

X5R

16V

402

10%

0.1uF

18 61 83 91

75 93

75 93

75 93

75 93

75 93

75 93

75 93

75 93

75 93

75 93

21

C9207

10% 16V
X5R 402

0.1uF

21

C9208

0.1uF

X5R

16V
402

10%

21

C9205

0.1uF

X5R 402

16V10%

21

C9206

0.1uF

16V
402

10%
X5R

21

C9203

X5R 402

16V10%

0.1uF

21

C9204

402

10% 16V
X5R

0.1uF

21

C9201

X5R

16V10%
402

0.1uF

21

C9202

10% 16V
X5R 402

0.1uF

81 93

81 93

81 93

81 93

81 93

81 93

81 93

81 93

2

1

R9220

402

MF-LF

1/16W

5%

10K

4

5

6

1
3

2

U9210

74LVC1G157

SOT487

T29

2

1

C9272

402

0.1uF

10%
16V
X5R

T29

60 91 97

81 97

18 61 83 91

56 97

2

1

C9270

0.1uF

16V

10%

402

X5R

T29

SYNC_MASTER=K62_AARON

Internal DP MUXing

SYNC_DATE=N/A

PP1V5_S0_DP_R

=PP1V5_S0_DP

MXM_DP_C_ML_P<1>

DP_INTMUX_XSD

PP1V5_S0_DP_R

=PP3V3_S0_INTDPMUX

PP1V5_S0_DP_R

MXM_DP_C_HPD

DP_T29SRC_AUXCH_R_C_N

=PP3V3_S0_INTDPMUX

DP_T29SRC_ML_C_P<0>

DP_T29SRC_ML_C_N<0>

DP_T29SRC_ML_C_P<1>

MXM_DP_C_AUX_P

MXM_DP_C_ML_N<2>

DP_INTCONN_ML_C_N<3>

MXM_DP_C_ML_N<0>

DP_T29SRC_ML_C_N<3>

DP_T29SRC_ML_C_P<3>

DP_T29SRC_ML_N<0>

DP_T29SRC_ML_P<1>

DP_T29SRC_ML_N<1>

DP_T29SRC_ML_P<2>

DP_T29SRC_ML_N<2>

DP_T29SRC_ML_P<3>

DP_T29SRC_ML_P<0>

DP_T29SRC_ML_C_P<0>
DP_T29SRC_ML_C_N<0>

DP_T29SRC_ML_C_N<1>

DP_T29SRC_ML_C_P<1>

DP_T29SRC_ML_C_P<2>

DP_T29SRC_ML_C_P<3>
DP_T29SRC_ML_C_N<3>

DP_INTCONN_ML_C_N<0>

MXM_DP_C_ML_N<3>

DP_INTPNL_AUX_N

DP_INTPNL_AUX_P

MXM_DP_C_ML_P<2>

=PP3V3_S0_INTDPMUX

DP_INTPNL_HPD

MXM_DP_C_ML_P<0>

MXM_DP_C_ML_N<1>

DP_T29SRC_AUXCH_C_N

=PP3V3_S0_INTDPMUX

BL_PWM

LCD_BL_FILT

BDV_BKL_PWM

DP_GPU_T29_SEL

DP_INTPNL_ML_N<3>

DP_INTPNL_ML_P<3>

DP_INTCONN_ML_C_P<1>

DP_INTCONN_ML_C_P<2>

DP_INTCONN_ML_C_N<1>

DP_INTPNL_ML_N<2>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_P<2>

DP_INTPNL_ML_N<1>

DP_INTPNL_ML_N<0>

DP_T29SRC_AUXCH_C_P

DP_T29SRC_HPD

MXM_DP_C_AUX_N

DP_INTCONN_ML_C_N<2>

DP_INTCONN_ML_C_P<3>

DP_T29SRC_ML_C_N<2>

DP_T29SRC_ML_C_P<2>

DP_T29SRC_ML_C_N<2>

DP_INTCONN_ML_C_P<0>

DP_INTPNL_ML_P<0>

MXM_DP_C_ML_P<3>

MXM_DP_C_AUX_R_P
MXM_DP_C_AUX_R_N

DP_T29SRC_ML_C_N<1>

DP_T29SRC_AUXCH_R_C_P

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.5V

PP1V5_S0_DP_R

MIN_NECK_WIDTH=0.2MM

DP_T29SRC_ML_N<3>

=PP3V3_S0_INTDPMUX

DP_INT_SPDIF_AUDIO

AUD_SPDIF_IN

AUD_SPDIF_IN_CODEC

MXM_PNL_BL_PWM

LCD_BL_PWM

=PP3V3_S0_INTDPMUX

DP_GPU_T29_SEL

DP_GPU_T29_SEL

DP_INTCONN_AUXCH_C_P
DP_INTCONN_AUXCH_C_N

92 OF 110

11.1.0

051-8115

83 OF 98

83 95

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83 95

6

83

83 95

96

6

83

93

93

6

83

6

83

97

93

93

93

93

93

93

93

93

96

83 95

6

83

97

6

83

93

93

www.vinafix.vn

OUT
OUT

BI

OUT

OUT

IN

IN

IN
IN

OUT
OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN
BI

BI

BI

NC

IN
BI

THMPAD

GND

VDD

OUT_D0P
OUT_D0N

OUT_D1P

OUT_D2P

OUT_D1N

OUT_D3P

OUT_D2N

OUT_D3N

AC_AUXP
AC_AUXN

OUT_HPD

CEXT

IN_D0P
IN_D0N

IN_D1N

IN_D2N

IN_D3P

IN_SDA

IN_AUXP
IN_AUXN

IN_HPD

I2C_CTL_EN

I2C_ADDR0
I2C_ADDR1

SCL_CTL
SDA_CTL

REXT

AUXDDC_OFF

PD

CA_DET

IN_SCL

IN_D3N

IN_D2P

IN_D1P

OUT_AUXN_SDA

OUT_AUXP_SCL

BI
BI

IN

BI

OUT

IN

OUT

OUT

OUT

VDD

PIO1_8/CT16B1_CAP0

PIO1_7/TXD

XTALIN

PIO1_4/AD5/WAKEUP

PIO1_6/RXD

SWDIO/PIO1_3/AD4

R/PIO1_2/AD3

R/PIO1_1/AD2

R/PIO1_0/AD1

RESET#/PIO0_0
PIO0_1/CLKOUT

SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO0_9/MOSI/CT16B0_MAT1

PIO0_8/MISO/CT16B0_MAT0

PIO0_2/SSEL/CT16B0_CAP0

R/PIO0_11/AD0

PIO0_7/CTS#

PIO0_6/SCK

PIO0_4/SCL
PIO0_5/SDA

VSS

THRM

PAD

BI

OUT
OUT

IN

IN

IN

IN

IN

IN

AUX-

AUX+

DOUT_1+
DOUT_1-

NC

GND

THMPAD

GPU_SEL

HPD_2

AUX2-

AUX2+

DIN2_1-

DIN2_1+

DIN2_0-

HPD_1

AUX1-

AUX1+

DIN1_1-

DOUT_0-

DIN1_0+
DIN1_0-

DIN1_1+

HPD_IN

DOUT_0+

DIN2_0+

VDD

AUX_SEL

OUT

IN

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(P2R = PLUG TO RECEPTACLE)

pin 10 for ML and pin 11 for HPD.

similar pinouts. NXP uses pin

footprint-compatible parts with

HI=Port B

DP/T29 A Low-Speed MUX

pull-ups on ML<3>. U9390 AUX defaults to DP mode
because 100-ohm pull-downs would defeat DP Sink’s
detection of DP Source.

CBTL04DP081 (353S3151) and

10 for ML and HPD, Pericom uses

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29

Must be 3.3V DP A port power

Port A MCU

~150K pull-down on PD
pin. Okay to drive this
pin even when VCC=0V per
Parade (pin is 5V-tolerant).

(R2P = RECEPTACLE TO PLUG)

LO=Port A

(OD)

R9330 provides pads for programming/debug of MCU, please make accessible.

Display can detect host T29 support using I2C

(All 4 L’s)

T29 A High-Speed Signals

(C9370/C9371)

(Both L’s)

P/N-swapped after AC

(DP_SDRVA_AUXCH_P)

(IPU)

(OD)

T29 signals are

R9308/R9309 maintain bias on C9308/C9309

transitions from high to low.

caps to improve layout.

AUXCH Snoop Port,

high while Vcc = 0V.

DP A Super-Driver

and DDC, alias nets together at GPU.

If GPU uses common pins for AUX_CH

(D9360/D9361)

(D9382/D9383)

(C9380/C9381)

(C9372.2)

PS8301 I2C Addresses:

T29: TX_1

Both R’s:

(D9361.2)

(IPD)

If project has space for 10-pin programming header it should be used.

PS8301 has internal

(OD)

during training.

used by PS8301

=T29_WAKE_L:

SWDIO

SWCLK

(OD)

T29: LSX_A_R2P/P2R (P/N)

T29: Unused

T29: RX_1 Bias Sink

(IPU)

(IPD)

1 0 0x94/0x95

0 0 0x96/0x97
0 1 0xB6/0xB7

Note: Other Parade
devices use 96/B6,

(D9365.2)

(DP_SDRVA_HPD)

(DP_SDRVA_AUXCH_N)

A1 A0 Addr (W/R)

1 1 0xB4/0xB5

so only 94/B4 are

(IPD)

used for this part.

(IPD)

Biasing

(D9364.2)

DP Path Biasing

T29: TX_0

(D9372/D9373)

(All 4 D’s)

D9372/D9373:
D9364/D9365:

(All 4 D’s)

(D9382/D9383)

(D9360.2)

(T29_A_LSX_R2P)

Mobiles use S4 WAKE#

Desktops use PCIe WAKE#

(IPD)

(C9383.2)

(C9383.2)

(Both L’s)

to prevent spikes when U9310 AUXDDC_OFF

IC supports input

T29 Path

(C9373.2)

0x26/0x27 (Wr/Rd)

I2C Addr:

(T29_A_LSX_P2R)

Must be 3.3V DP A port power

PI3vEDP212 (353S3055) are

86 96

86 96

85 96

85 96

2

1

R9312

MF-LF

1/16W

1K

5%

402

2

1

R9319

4.02K

1/16W

1%

402

MF-LF

78

2

1

R9311

NO STUFF

MF-LF

5%

402

1/16W

1K

2

1

R9310

1/16W

5%

402

MF-LF

1K

2

1

C9311

0.1UF

10V

20%
CERM

402

2

1

C9312

0.1UF

20%
10V

402

CERM

2

1

C9319

20%

6.3V
CERM

2.2UF

PLACE_NEAR=U9310.11:2 mm

402-LF

86 96

86 96

86 96

86 96

86 96

86 96

21

C9306

402

0.1uF

16V

X5R

10%

21

C9307

0.1uF

16V
402X5R

10%

78 93

78 93

21

C9304

0.1uF

10%

402X5R

16V

78 93

21

C9305

10%

402

16V

X5R

0.1uF

78 93

21

C9302

X5R

0.1uF

10%

402

16V

78 93

21

C9303

X5R 402

16V10%

0.1uF

78 93

21

C9300

16V
402

0.1uF

10%
X5R

78 93

21

C9301

10% 16V

0.1uF

402X5R

78 93

49

49

21

C9308

0.1uF

16V

X5R 402

10%

21

C9309

0.1uF

16V10%

X5R 402

78 93

78 93

2

1

R9399

100K

MF-LF

1/16W

5%

402

2

1

R9398

MF-LF
402

1/16W

5%

100K

78

78

40

21

41

37

38

12

34

31

23
22

25
24

28
27

30
29

18
17

13

14

3

9

10

7
8

4
5

1
2

16
15

26

35

36

33

6

11

32

39

20
19

U9310

CRITICAL

QFN

PS8301TQFN40GTR-A2

2

1

C9310

2.2UF

6.3V

402-LF

CERM

20%

85 96

85 96

21

C9363

10% 16V
X5R-CERM

0201

0.1UF

21

C9362

16V

X5R-CERM

0.1UF

10%

0201

21

C9367

0.1UF

16V10%

X5R-CERM

0201

21

C9366

0.1UF

10% 16V
X5R-CERM

0201

84

85 96

85 96

84

21

C9369

16V10%
402X5R

0.1uF

21

C9368

16V10%

X5R 402

0.1uF

20 91

78

86

4

21

3

22

5

25

19

14

1

18

17

16

15

6

24

23

20

13

12

11

10

9

8

7

2

U9330

HVQFN25

LPC1112A

CRITICAL

OMIT

49

82 84 85 96

86

49

86

2

1

R9335

T29

402

MF-LF

1K

5%
1/16W

2

1

R9336

T29

MF-LF
402

1/16W

10K

5%

2

1

C9330

0.1UF

CERM

10V

20%

402

T29

86

85

84 85

2

1

C9331

20%

T29

402

0.1UF

10V
CERM

1

2

R9397

MF-LF

T29

402

5%

1K

1/16W

1

2

R9396

T29

1K

5%

MF-LF

1/16W

402

2

1

R9339

1M

402

1/16W
MF-LF

5%

T29

2

1

R9338

MF-LF

402

T29

5%

10K

1/16W

84 85

2

1

R9330

5%

MF-LF

1/16W

402

OMIT

0

2

1

R9393

T29

51

5%
1/16W

402

MF-LF

2

1

R9392

T29

51

MF-LF

5%

402

1/16W

292016129

3

33

8

13

17

10

28

21

4
5

1
2

23
22

25
24

27
26

31
30

32

6
7

15
14

19
18

U9390

CKPLUS_WAIVE=NdifPr_badTerm

OMIT

CBTL04DP081

CRITICAL

HVQFN

SIGNAL_MODEL=T29DP_MUX

82 97

21

R9334

MF-LF

T29

1/16W

5%

402

10K

15 18 25 91

1

2

R9318

MF-LF

1/16W

5%

0

SDRV_PD

402

21

R9308

1/16W

1M

5%

402

MF-LF

21

R9309

1M

402

5%

MF-LF

1/16W

85 96

85 96

85 96

85 96

85 96

85 96

21

D9364

SIGNAL_MODEL=EMPTY

TSLP-2-7

CRITICAL

GND_VOID=TRUE

BAR90-02LRH

21

D9373

T29

SIGNAL_MODEL=T29PIN

TSLP-2-7

BAR90-02LRH

CRITICAL

GND_VOID=TRUE

21

D9372

T29

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

BAR90-02LRH

TSLP-2-7

CRITICAL

21

D9365

SIGNAL_MODEL=EMPTY

TSLP-2-7

BAR90-02LRH

GND_VOID=TRUE

CRITICAL

21

D9360

BAR90-02LRH

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

TSLP-2-7

CRITICAL

21

D9382

BAR90-02LRH

CRITICAL

GND_VOID=TRUE

SIGNAL_MODEL=T29PIN

TSLP-2-7

T29

21

D9383

T29

BAR90-02LRH

SIGNAL_MODEL=T29PIN

TSLP-2-7

CRITICAL

GND_VOID=TRUE

21

D9361

SIGNAL_MODEL=EMPTY

CRITICAL

TSLP-2-7

GND_VOID=TRUE

BAR90-02LRH

21

C9370

0.47UF

20%

4V

CERM-X5R-1

201

GND_VOID=TRUE

T29

21

R9372

SIGNAL_MODEL=EMPTY

MF

1/20W

5%

GND_VOID=TRUE

201

1.5K

T29

21

R9373

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

201

5%

1/20W

MF

1.5K

T29

21

R9382

MF 201

1/20W

5%

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

1.5K

T29

21

R9383

SIGNAL_MODEL=EMPTY

1/20W

5%

GND_VOID=TRUE

201MF

1.5K

T29

21

C9373

T29

0.47UF

CERM-X5R-1

4V

20%

201

GND_VOID=TRUE

21

C9372

T29

201

CERM-X5R-1

20%

GND_VOID=TRUE

4V

0.47UF

21

C9371

T29

4V

CERM-X5R-1

0.47UF

GND_VOID=TRUE

201

20%

21

C9381

T29

GND_VOID=TRUE

4V

20%

201

CERM-X5R-1

0.47UF

21

C9380

T29

GND_VOID=TRUE

CERM-X5R-1

4V

20%

201

0.47UF

21

C9382

T29

20%
CERM-X5R-1

4V

GND_VOID=TRUE

0.47UF

201

21

C9383

T29

CERM-X5R-1

201

GND_VOID=TRUE

0.47UF

20%

4V

21

C9364

6.3V

0.22UF

20%
X5R

0201

21

C9365

20%

6.3V

0.22UF

X5R

0201

21

C9361

X5R

20%

0.22UF

6.3V
0201

21

C9360

6.3V

0.22UF

20%
X5R

0201

21

R9385

1/20W

201

5%
MF

GND_VOID=TRUE

1.5K

SIGNAL_MODEL=EMPTY

21

R9384

SIGNAL_MODEL=EMPTY

1/20W

201

5%
MF

1.5K

GND_VOID=TRUE

85 96

85 96

21

R9375

GND_VOID=TRUE
SIGNAL_MODEL=EMPTY

1/20W

201MF

5%

1.5K

21

R9374

SIGNAL_MODEL=EMPTY

201

1/20W

MF

GND_VOID=TRUE

5%

1.5K

21

L9383

0201-1

OVERSIZE_PAD=0.875 mm^2

1.0NH+/-0.1NH

T29

21

L9382

T29

1.0NH+/-0.1NH

OVERSIZE_PAD=0.875 mm^2

0201-1

21

L9372

T29

1.0NH+/-0.1NH

0201-1

OVERSIZE_PAD=0.875 mm^2

21

L9373

T29

0201-1

OVERSIZE_PAD=0.875 mm^2

1.0NH+/-0.1NH

21

R9355

5%
MF 201

1/20W

22

21

R9354

MF

1/20W

201

5%

22

21

R9350

5%
MF

201

1/20W

22

21

R9351

5%

201

1/20W

MF

22

2

1

C9390

0.1UF

CERM
402

10V

20%

2

1

C9391

402

CERM

0.1UF

10V

20%

21

R9360

1.5K

1/20W

5%
MF

201

21

R9361

5%
MF 201

1/20W

1.5K

21

R9364

5%

1/20W

MF 201

1.5K

21

R9365

201MF

1/20W

5%

1.5K

4

5

3

2

U9359

74LVC1G04DBDCK

CRITICAL

SC70

2

1

C9359

402

X5R

16V

10%

0.1UF

2

1

R9352

5%

1/20W

201

MF

390

2

1

R9353

201

MF

1/20W

5%

390

21

C9358

0201

0.1UF

X5R-CERM

10%
16V

85

85

21

R9362

1/20W

5%

20151MF

21

R9363

201

MF5%

1/20W

51

21

R9366

201

MF5%511/20W

21

R9367

MF

201

1/20W

5%

51

85

85

2

1

R9370

1/20W

5%

201

MF

390

2

1

R9371

201

MF

5%
1/20W

390

21

R9380

5%

MF

201

0

1/20W

NO_T29

21

R9381

MF

5%

0

201

1/20W

NO_T29

21

R9378

5%

0

1/20W

201

MF

NO_T29

21

R9379

0

201

MF

5%

1/20W

NO_T29

SYNC_MASTER=K62

SYNC_DATE=11/14/2010

DisplayPort/T29 A MUXing

PP3V3_SW_DPAPWR

T29_A_LSX_P2R

DP_A_EXT_AUXCH_N

T29DPA_ML_N<1>

T29DPA_HPD

T29DPA_ML_P<3>

PP3V3_SW_DPAPWR

T29_A_LSX_R2P

T29_A_BIAS

DP_A_CA_DET

DP_SDRVA_HPD

T29_A_BIAS

DP_A_PWRDWN

DP_SDRVA_ML_P<0>
DP_SDRVA_ML_N<0>

DP_SDRVA_ML_P<2>

VOLTAGE=3.3V

T29_A_BIAS_R2D_N0

T29DPA_ML_C_P<2>

DP_SDRVA_ML_P<3>

=I2C_T29AMCU_SDA

DP_SDRVA_ML_C_P<0>

DP_SDRVA_ML_C_P<2>

T29_R2D_C_P<1>

T29_R2D_N<1>

T29_R2D_P<1>

VOLTAGE=3.3V

T29_A_BIAS_R2D_N1

T29_R2D_C_P<0>
T29_R2D_C_N<0>

DP_SDRVA_AUXCH_C_N

DP_A_PWRDWN

DP_SDRVA_ML_C_N<1>

DP_EXTA_ML_C_P<0>

DP_SDRVA_ML_R_N<0>

DP_A_BIAS

T29_D2R_C_P<1>

DP_SDRVA_ML_N<2>

T29_R2D_N<0>

T29DPA_ML_C_N<0>

VOLTAGE=3.3V

DP_A_BIAS_N_2

T29DPA_ML_C_N<2>

DP_A_BIAS_P_0

VOLTAGE=3.3V

DP_A_BIAS_N_0

VOLTAGE=3.3V

DP_EXTA_ML_P<1>

DPSDRVA_I2C_CTL_EN

=I2C_DPSDRVA_SCL

DPSDRVA_I2C_ADDR1

DPSDRVA_I2C_ADDR0

DP_EXTA_DDC_CLK

DP_SDRVA_ML_C_P<3>

DPSDRVA_REXT

=PP3V3_S0_DPSDRVA

DP_A_PWRDWN_R

DP_SDRVA_ML_N<3>

DP_AUXCH_ISOL

DP_EXTA_AUXCH_N
DP_EXTA_HPD

DPSDRVA_CEXT

T29DPA_ML_C_P<0>

T29_LSEO<0>

T29_LSOE<1>

DP_EXTA_ML_N<1>

DP_EXTA_ML_N<0>
DP_EXTA_ML_P<1>

DP_EXTA_ML_P<2>

DP_EXTA_ML_N<3>

DP_A_CA_DET

DP_EXTA_ML_P<3>

DP_EXTA_ML_N<2>

DP_EXTA_ML_P<0>

T29DPA_ML_N<3>

T29DPA_ML_P<1>

DP_A_EXT_AUXCH_P

T29DPA_CONFIG1_RC

T29_A_UC_ADDR

DP_EXTA_ML_N<0>

DP_EXTA_ML_C_N<0>

DP_EXTA_ML_N<1>

DP_EXTA_ML_N<2>

DP_EXTA_ML_P<2>

DP_EXTA_ML_N<3>

DP_EXTA_ML_C_P<1>

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_P<2>

DP_EXTA_ML_C_N<2>

DP_EXTA_AUXCH_C_P

=PP3V3_S0_DPSDRVA

DP_EXTA_DDC_DATA
DP_EXTA_AUXCH_P

=I2C_DPSDRVA_SDA

DP_A_PWRDWN

T29_R2D_C_N<1>

DP_EXTA_ML_P<3>

=PP3V3_S0_DPSDRVA

DP_A_BIAS_P_2

VOLTAGE=3.3V

=I2C_T29AMCU_SCL

T29_R2D_P<0>

T29_D2R_C_N<0>

DP_EXTA_ML_P<0>

VOLTAGE=3.3V

T29_A_BIAS_R2D_P0

DP_SDRVA_ML_R_P<2>

DP_EXTA_AUXCH_C_N

DP_EXTA_ML_C_N<3>

DP_EXTA_ML_C_P<3>

DP_SDRVA_ML_C_N<2>

DP_EXTA_AUXCH_P

DP_EXTA_AUXCH_N

VOLTAGE=3.3V

T29_A_BIAS_R2D_P1

T29_D2R_C_P<0>

DP_SDRVA_ML_C_N<3>

T29_R2D_C_F_P<0>

DP_SDRVA_ML_C_N<0>

DP_SDRVA_ML_R_N<2>

T29_R2D_C_F_N<0>

T29_R2D_C_F_N<1>
T29_R2D_C_F_P<1>

T29_D2R_N<1>

=T29_WAKE_L

T29_LSEO<1>T29_LSOE<0>

T29DPA_HPD

DP_A_PWRDWN

DP_SDRVA_AUXCH_C_P

T29_D2R1_BIASP
T29_D2R1_BIASN

DP_SDRVA_ML_P<1>

T29_D2R_P<0>

T29_D2R_N<0>

T29_D2R_C_N<1>

T29_D2R_P<1>

DP_SDRVA_ML_R_P<0>

DP_SDRVA_ML_C_P<1>

T29_MCU_INT_L

T29_A_BIAS

T29DPA_CONFIG1_RC

T29_A_RSVD_N
T29_A_RSVD_P

DP_A_EXT_HPD

DP_A_EXT_HPD

DP_SDRVA_AUXCH_N

DP_SDRVA_AUXCH_P

DP_SDRVA_ML_N<1>

DP_A_CA_DET

T29_A_HV_EN_R
T29_A_UC_ADDR
DP_A_EXT_HPD

T29DPA_CONFIG2_RC

T29_A_HV_EN

93 OF 110

11.1.0

051-8115

84 OF 98

11

78 84 95

84 85

78 84 95

82 84 85 96

84

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96

96

96

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96

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96

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84 97

96

96

96

96

96

85

85

85

84 93

96

6

84

96

84 93

84 93

84 93

84 93

84 93

84 93

84 93

84 93

84 93

84

84 93

84 93

84 93

84 93

84 93

6

84

84 93

84 97

84 93

6

84

85

96

84 93

96

96

84 93

84 93

96

96

96

96

96

96

96

84 97

96

96

96

96

82 84 85 96

84
85

96

96

84

96

96

96

84

84

84

www.vinafix.vn

OUT

OUT

IN
IN

BI

IN

OUT
OUT

BI
BI

BI

OUT

OUT

OUT

BI

IN
IN

IN

ML_LANE2P
ML_LANE2N

RETURN

GND

ML_LANE1N

ML_LANE0N

GND

ML_LANE1P

ML_LANE0P

GND

AUX_CHP
AUX_CHN
DP_PWR

GND

ML_LANE3N

ML_LANE3P

GND

HPD
CONFIG1
CONFIG2

SHIELD PINS

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

DP BIAS CAPS

(Both L’s)

T29: Unused

High: 2.0 - 5.0V

Circuit threshold range: 2.877-2.941V (2.903V nominal)

470k R’s for ESD protection
on AC-coupled signals.

(Both C’s)

T29 Dir

DP Dir

(Both C’s)

T29: TX_1

DP Dir

T29 BIAS RC

T29: LSX_R2P/P2R (P/N)

(3, 5, 17 & 19):

For J9400 T29 SMT pads

DisplayPort/T29 A Connector

T29 Dir

to C in star topology.

All 3 R’s must connect

Sink HPD range:

T29: TX_0

Low: 0 - 0.8V

2

1

C9400

50V

10%

0.01UF

X7R
402

84 96

84 96

84 96

84 96

84 96

84 96

21

R9407

12

GND_VOID=TRUE

5%
MF

201

1/20W

21

R9403

GND_VOID=TRUE

201

MF

5%

12

1/20W

21

R9404

GND_VOID=TRUE

5%

12

MF

1/20W

201

21

R9408

5%

12

MF

1/20W

201

2

1

C9402

X5R

10%

201

10V

0.01UF

21

L9408

FERR-120-OHM-3A

0603

21

R9402

201

1/20W

MF

12

5%

21

R9401

201

MF

12

5%

1/20W

2

1

C9401

10%
50V
X7R
402

0.01UF

2

1

R9494

OMIT_TABLE

201

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

1/20W

MF

1K

5%

2

1

R9495

OMIT_TABLE

SIGNAL_MODEL=EMPTY

1K

5%

GND_VOID=TRUE

MF

1/20W
201

2

1

C9498

5%

50V

CERM

402

30PF

T29

2

1

C9499

5%

30PF

402

50V
CERM

T29

2

1

R9441

402

1/16W

5%

100K

MF-LF

2 1

L9498

OMIT_TABLE

CRITICAL

0603

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.052OHM

2 1

L9499

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

0603

CRITICAL

OMIT_TABLE

650NH-5%-0.430MA-0.052OHM

84 96

84 96

84 96

84 96

84 96

2

1

R9452

1M

5%
1/16W
MF-LF

402

2

1

R9451

402

1/16W

1M

MF-LF

5%

2

1

C9494

201

10%

330PF

16V
X7R

OMIT_TABLE

2

1

C9495

201

X7R

16V

10%

330PF

OMIT_TABLE

2

1

R9498

5%

201

MF

2.2K

SIGNAL_MODEL=EMPTY

1/20W

GND_VOID=TRUE

T29

2

1

R9499

SIGNAL_MODEL=EMPTY

2.2K

MF

GND_VOID=TRUE

T29

201

1/20W

5%

21

L9400

FERR-120-OHM-3A

0603

84

84

84

84 96

21

D9499

BAR90-02LRH

TSLP-2-7

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

CRITICAL

T29

21

D9498

CRITICAL

BAR90-02LRH

TSLP-2-7

GND_VOID=TRUE

SIGNAL_MODEL=T29PIN

T29

2

1

R9470

GND_VOID=TRUE

5%

470K

MF

1/20W
201

2

1

R9471

1/20W

GND_VOID=TRUE

5%

470K

MF
201

21

C9471

CERM-X5R-1

201

20%

4V

GND_VOID=TRUE

0.47UF

21

C9470

0.47UF

GND_VOID=TRUE

4V

20%

201

CERM-X5R-1

84 96

84 96

21

C9472

0.47UF

CERM-X5R-1

201

20%

4V

GND_VOID=TRUE

21

C9473

CERM-X5R-1

201

20%

4V

GND_VOID=TRUE

0.47UF

2

1

R9473

201

1/20W
MF

GND_VOID=TRUE

5%

470K

2

1

R9472

GND_VOID=TRUE

201

1/20W
MF

5%

470K

2

1

R9491

SIGNAL_MODEL=EMPTY

201

51

5%

1/20W

MF

T29

2

1

R9492

51

5%
1/20W
MF
201

SIGNAL_MODEL=EMPTY

T29

21

C9490

6.3V

0.1UF

201

X5R

10%

T29

82 84 85 96

19

10
12

15
17

9
11

3
5

22

21

2

14 13

8 7

1

20

6

4

16
18

J9400

CRITICAL

MDP-K60K62

F-ANG-TH

GND_VOID=TRUE

21

C9493

0.01UF

10%
X5R

201

10V

T29

SIGNAL_MODEL=EMPTY

21

C9492

10V

SIGNAL_MODEL=EMPTY

T29

10%
X5R

201

0.01UF

2

1

C9410

201

X5R

0.01UF

10%
10V

T29

SIGNAL_MODEL=EMPTY

2

1

C9417

SIGNAL_MODEL=EMPTY

X5R

10V
201

10%

0.01UF

2

1

C9416

SIGNAL_MODEL=EMPTY

X5R

10V
201

10%

0.01UF

2

1

C9415

SIGNAL_MODEL=EMPTY

X5R

10V
201

10%

0.01UF

2

1

C9414

SIGNAL_MODEL=EMPTY

0.01UF

10%

201

10V
X5R

21

R9410

1/20W

5%

51

SIGNAL_MODEL=EMPTY

MF

201

T29

2

1

C9411

SIGNAL_MODEL=EMPTY

X5R

10V
201

10%

0.01UF

T29

21

R9411

SIGNAL_MODEL=EMPTY

201

51

1/20W

MF

5%

T29

2

1

C9412

SIGNAL_MODEL=EMPTY

X5R

10V
201

10%

0.01UF

T29

21

R9412

SIGNAL_MODEL=EMPTY

51

201

1/20W

MF

5%

T29

2

1

C9413

SIGNAL_MODEL=EMPTY

X5R

10V
201

10%

0.01UF

T29

21

R9413

SIGNAL_MODEL=EMPTY

201

51

1/20W

MF

5%

T29

21

C9405

201

0.1UF

X5R

10%

6.3V

21

C9406

201

10%

0.1UF

X5R

6.3V

DisplayPort/T29 A Connector

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

2

113S0022 NO_T29

L9498,L9499

RES,0R,5%,0603

IND,650NH,5%,0.052OHM,0603

152S1300

L9498,L9499

2

T29

RES,1K,5%,0201

R9494,R9495

2

T29

117S0006

132S0165

C9494,C9495

2

T29

CAP,330PF,10%,16V,0201

RES,0R,5%,0201

2

R9494,R9495

NO_T29117S0002

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM
VOLTAGE=0V

GND_DPACONN_13

T29DPA_ML_P<1>

T29DPA_ML_P<0>
T29DPA_ML_N<0>

GND_DPACONN_1

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3R12V_SW_DPAPWR_R

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=12V

MIN_LINE_WIDTH=0.38 MM

T29DPA_ML_P<3>

T29DPA_CONFIG1_RC
T29DPA_CONFIG2_RC

T29_D2R_C_P<0>
T29_D2R_C_N<0>

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=12V

MIN_LINE_WIDTH=0.38 MM

DPACONN_20_RC

T29_A_BIAS_N1

T29_D2R_C_P<1>

DP_A_BIAS_P_0

VOLTAGE=3.3V

T29_A_BIAS_P1

VOLTAGE=3.3V

GND_DPACONN_7

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

T29DPA_ML_N<1>

T29DPA_ML_P<2>

T29DPA_ML_C_N<2>

T29_A_BIAS

T29_A_BIAS

T29_A_BIAS

PP3V3R12V_SW_DPAPWR

MIN_LINE_WIDTH=0.38 MM
VOLTAGE=12V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_8

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

T29DPA_ML_C_P<2>

T29DPA_ML_C_N<0>

T29DPA_ML_C_P<0>

T29DPA_ML_N<2>

VOLTAGE=3.3V

T29_A_BIAS_R2D_N0

VOLTAGE=3.3V

T29_A_BIAS_R2D_P0

VOLTAGE=3.3V

T29_A_BIAS_R2D_P1

VOLTAGE=3.3V

T29_A_BIAS_R2D_N1

VOLTAGE=3.3V

DP_A_BIAS_N_2

VOLTAGE=3.3V

DP_A_BIAS_P_2

VOLTAGE=3.3V

DP_A_BIAS_N_0

T29DPA_D2R1_AUXCH_P

DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N

T29_D2R_C_N<1>

T29DPA_HPD_R

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_19

T29DPA_ML_N<3>

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_14

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

T29DPA_D2R1_AUXCH_N

T29DPA_HPD

94 OF 110

11.1.0

051-8115

85 OF 98

96

96

95

84

96

82 84
85 96

82 84 85 96

82

96

84

84 84

84

84 84 84

96

96

www.vinafix.vn

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT
OUT

IN

IN

IN

OUT

IN
IN

OUT

OUT

BI

DPSNK0_ML_LANE_3P
DPSNK0_ML_LANE_3N

DPSNK0_ML_LANE_2P

DPSRC0_HOT_PLUG_DET

TEST_POINT_2
TEST_POINT_3

DPSNK0_HOT_PLUG_DET

DPSNK0_AUX_CHN

DPSNK0_AUX_CHP

DPSNK0_ML_LANE_0N

DPSNK0_ML_LANE_0P

DPSNK0_ML_LANE_1N

DPSNK0_ML_LANE_1P

DPSNK0_ML_LANE_2N

TEST_POINT_0

TEST_EN

THERM_DP

EE_CLK

EE_CS*

EE_DO

EE_DI

PCIE_CLKREQ_3*

PCIE_CLKREQ_2*

PCIE_CLKREQ_1*

PCIE_CLKREQ_0*

DPSNK1_ML_LANE_1P

DPSNK1_ML_LANE_2N

DPSNK1_ML_LANE_2P

DPSNK1_ML_LANE_3N

DPSNK1_ML_LANE_3P

DP_RES_1

DP_RES_0

DP_ATEST

DPSRC0_AUX_CHN

DPSRC0_AUX_CHP

DPSRC0_ML_LANE_0N

DPSRC0_ML_LANE_0P

DPSRC0_ML_LANE_1N

DPSRC0_ML_LANE_1P

DPSRC0_ML_LANE_2N

DPSRC0_ML_LANE_2P

DPSRC0_ML_LANE_3N

DPSRC0_ML_LANE_3P

TMU_CLK_OUT

TMU_CLK_IN

XTAL_25_IN

XTAL_25_OUT

REFCLK_100_IN_P
REFCLK_100_IN_N

TDO

TCK

TMS

TDI

PCIE_RST_3*

PCIE_RST_1*
PCIE_RST_2*

PCIE_RST_0*

RBIAS

RSENSE

PERST*

WAKE*

PER_1_P

PER_2_P

PER_3_P

MONDC0

MONOBSN

MONOBSP

MONDC1

PER_3_N

PER_2_N

PER_0_N

PER_0_P

PET_3_P
PET_3_N

PET_2_N

PET_2_P

PET_1_P
PET_1_N

PET_0_N

PET_0_P

TEST_POINT_1

DPSNK1_ML_LANE_0N

PER_1_N

DPSNK1_ML_LANE_0P

DPSNK1_ML_LANE_1N

DPSNK1_AUX_CHP

DPSNK1_HOT_PLUG_DET

DPSNK1_AUX_CHN

PRT0_T29T_N

PRT0_T29R_P
PRT0_T29R_N

T29_0_LSEO
T29_0_LSOE

PRT1_T29T_P
PRT1_T29T_N

PRT1_T29R_P
PRT1_T29R_N

T29_1_LSEO
T29_1_LSOE

T29_SDA
T29_SCL

PRT2_T29T_P
PRT2_T29T_N

PRT2_T29R_P
PRT2_T29R_N

T29_2_LSEO
T29_2_LSOE

PRT3_T29T_P
PRT3_T29T_N

PRT3_T29R_P
PRT3_T29R_N

T29_3_LSEO
T29_3_LSOE

PRT0_T29T_P

PORT2

PCIE GEN2

RECEIVE

TRANSMIT

PORTS

(SYM 1 OF 2)

JTAG

POWER ON RESET

MISC

CLOCKS

SOURCE PORT 0

DISPLAY

PORT3

PORT0PORT1

CLK REQUEST

EEPROM

TEST PORT

SINK PORT 0SINK PORT 1

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

OUT

IN

OUT

IN

IN

C

VCC

THM

VSS

PAD

D Q

S_L

W_L

HOLD_L

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SNK0 AC Coupling

SNK1 AC Coupling

(T29_SPI_MOSI) (T29_SPI_MISO)

NOTE: All unused LSOE/EO pairs should be aliased

(T29_SPI_CLK)

(T29_SPI_CS_L)

together. Other signals okay to float (TP/NC).

DEBUG: For monitoring current/voltage

100pF SRF > 40MHz

Not used in host mode.

DEBUG: For monitoring clock

Use B1 GND ball for THERM_DN

2

1

R9790

T29

3.3K

MF-LF

402

5%

1/16W

2

1

R9785

T29

14.0K

MF-LF

1%

1/16W

402

2

1

C9785

T29

CERM

50V

5%

BYPASS=U3600.Y19::2mm

100PF

402

2

1

C9786

T29

10%
16V
CERM
402

BYPASS=U3600.Y19::5.08mm

0.01UF

78

78

2

1

R9725

T29

0

5%
1/16W
MF-LF
402

2

1

R9732

T29

MF-LF

5%
1/16W

100K

402

84

84 96

84 96

84

84 96

84 96

84 96

84 96

84 96

84 96

78

78 96

78 96

78

78 96

78 96

78 96

78 96

78 96

78 96

2

1

R9730

T29

5%

402

MF-LF

1/16W

100K

2

1

R9731

T29

1/16W

5%

MF-LF

100K

402

2

1

R9799

10K

1/16W
MF-LF

402

5%

NOSTUFF

49 96

49 96

R16

P17

F1

U2

E2

R4

A2

L6

M5

N6

P5

E4

T1

T3

R2

F3
F5

H1

G2

H3

G4

H5

G6

K5

J6

E14

H17
G16

E16

A18
A16

C16

C14

A14
A12

C12

C10

A10

A8

C8

C6

A6
A4

C4

C2

F21

D21

K21

H21

P21
M21

V21
T21

E6

F19

D19

K19

H19

P19
M19

V19
T19

J4

K3

J2

K1

L4

M3

N4

P3

K17

M17

A20

B21

M1

P1

N2

L2

AA18

Y17

AA16

Y15

AA14

Y13

AA12

Y11

V3

W16
U16

V9

U8

V11

U10

V13
U12

V15

U14

U4

V7
U6

AA4

Y3

AA6

Y5

AA8

Y7

AA10

Y9

V5

V1
W2

AA20

Y21

Y19

U9700

CRITICAL

FCBGA

T29

OMIT

2

1

R9729

T29

1/16W

402

0

5%

MF-LF

2

1

R9793

T29

3.3K

1/16W
MF-LF

5%

402

2

1

R9798

T29

5%
1/16W

10K

402

MF-LF

2

1

R9723

T29

10K

MF-LF

1/16W

5%

402

2

1

R9722

T29

5%

402

1/16W

10K

MF-LF

2

1

R9721

T29

402

MF-LF

10K

5%
1/16W

21

C9729

T29

X5R

16V

0.1uF

10%

402

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

21

C9728

T29

0.1uF

X5R

10% 16V

402

21

C9727

T29

X5R

0.1uF

16V
402

10%

21

C9726

T29

402

0.1uF

X5R

10% 16V

21

C9725

T29

402

16V

X5R

0.1uF

10%

21

C9724

T29

0.1uF

10%

402X5R

16V

21

C9723

T29

402X5R

16V10%

0.1uF

21

C9722

T29

X5R

0.1uF

10% 16V

402

2

1

R9755

T29

603

MF-LF

1/16W

0.5%

1.0K

21

C9721

T29

0.1uF

16V
402X5R

10%

21

C9720

T29

16V
402

0.1uF

10%
X5R

21

C9730

T29

16V
402X5R

10%

0.1uF

21

C9731

T29

16V
402X5R

10%

0.1uF

21

C9732

T29

402

16V10%

X5R

0.1uF

21

C9733

T29

0.1uF

16V
402

10%
X5R

21

C9734

T29

16V
402

10%
X5R

0.1uF

21

C9735

T29

16V
402X5R

10%

0.1uF

21

C9736

T29

16V
402

10%
X5R

0.1uF

21

C9737

T29

16V
402X5R

10%

0.1uF

21

C9738

T29

16V
402X5R

10%

0.1uF

21

C9739

T29

16V10%

0.1uF

X5R 402

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

2

1

C9790

T29

402

6.3V

1UF

10%

CERM

78 96

78 96

12

R9751

T29

402

5%

1/16W MF-LF

10K

2

1

R9796

T29

1%

150

402

1/16W
MF-LF

21

R9795

T29

1%

64.9

MF-LF

1/16W

402

79 96

84

84

78

78

6

5

4

3

2

1

8

7

J9700

T29

M-RT-SM

78171-6006

18 96

2

1

R9743

NOSTUFF

100K

5%
1/16W
MF-LF

402

2

1

R9744

402

NOSTUFF

100K

MF-LF

5%

1/16W

2

1

R9741

NOSTUFF

100K

5%
1/16W
MF-LF

402

2

1

R9742

MF-LF

402

NOSTUFF

100K

5%

1/16W

3

489

1

2

7

5

6

U9790

M95320-RMB6TG

MLP

OMIT_TABLE

CRITICAL

80

18 96

21

C9701

T29

0.1uF

10% 16V X5R 402

21

C9700

T29

X5R

0.1uF

10% 16V 402

21

C9702

T29

0.1uF

402X5R16V10%

21

C9703

T29

0.1uF

402X5R16V10%

21

C9715

16V10%

0.1uF

402X5R

NOSTUFF

21

C9716

0.1uF

X5R 40210% 16V

NOSTUFF

2

1

R9792

T29

MF-LF

1/16W

402

5%

3.3K

21

R9711

0

402

MF-LF

5%

1/16W

NOSTUFF

21

R9710

0

MF-LF

402

1/16W

5%

NOSTUFF

21

C9704

T29

0.1uF

10% 16V X5R 402

21

C9705

T29

10% 16V X5R 402

0.1uF

21

C9706

T29

X5R 40210% 16V

0.1uF

21

C9707

T29

0.1uF

16V10% 402X5R

21

C9740

T29

0.1uF

10% X5R 40216V

21

C9741

T29

16V

0.1uF

10% 402X5R

21

C9742

T29

X5R

0.1uF

10% 40216V

2

1

R9791

T29

1/16W

5%

MF-LF
402

3.3K

21

C9743

T29

0.1uF

40210% 16V X5R

21

C9745

T29

0.1uF

16V X5R 40210%

21

C9744

T29

0.1uF

40216V X5R10%

21

C9746

T29

0.1uF

16V10% 402X5R

21

C9747

T29

402X5R

0.1uF

10% 16V

80 97

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

T29 Host (1 of 2)

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

TP_T29_PCIE_RESET3_L

JTAG_T29_TCK

T29_TMU_CLK_IN

DP_T29SRC_AUXCH_C_P
DP_T29SRC_AUXCH_C_N

T29_DP_ATEST

T29_R2D_C_P<2>

T29_D2R_P<3>

DP_T29SRC_ML_P<3>

DP_T29SNK1_ML_C_N<2>

DP_T29SNK1_AUXCH_P

DP_T29SNK1_AUXCH_N

=PP3V3_T29_RTR

DP_T29SNK0_AUXCH_N

=PP3V3_T29_RTR

JTAG_T29_TDI

PCIE_T29_R2D_P<1>

PCIE_T29_D2R_C_N<0>

T29_LSEO<0>

DP_T29SNK0_ML_P<3>

T29_MONOBSP

TP_T29_MONOBSP

TP_T29_PCIE_RESET1_L

JTAG_T29_TMS

JTAG_T29_TDO

=PP3V3_T29_RTR

=PP3V3_T29_RTR

SYSCLK_CLK25M_T29

SYSCLK_CLK25M_T29_R

TP_T29_MONDC0

PCIE_T29_R2D_C_P<3>

PCIE_T29_R2D_N<3>

TP_T29_PCIE_RESET2_L

TP_T29_PCIE_RESET0_L

PCIE_CLK100M_T29_P

DP_T29SNK1_ML_P<3>

DP_T29SNK1_AUXCH_N

T29_LSOE<2>

T29_D2R_N<2>

DP_T29SRC_ML_P<1>

DP_T29SRC_ML_N<2>

DP_T29SRC_ML_P<2>

DP_T29SRC_HPD

DP_T29SNK0_HPD

DP_T29SRC_ML_P<0>

PCIE_CLK100M_T29_N

TP_T29_XTAL25OUT

T29_LSEO<3>
T29_LSOE<3>

T29_LSEO<2>

PCIE_T29_R2D_C_N<2>

I2C_T29_SCL

I2C_T29_SDA

PCIE_T29_D2R_P<1>

PCIE_T29_D2R_P<2>

PCIE_T29_D2R_N<3>

PCIE_T29_D2R_N<0>

TP_T29_MONDC1

PCIE_T29_R2D_C_N<1>

PCIE_T29_R2D_C_P<1>

PCIE_T29_R2D_C_P<0>

PCIE_T29_R2D_C_P<2>

PCIE_T29_D2R_N<1>

PCIE_T29_D2R_P<0>

PCIE_T29_D2R_P<3>

PCIE_T29_R2D_C_N<0>

DP_T29SNK0_ML_C_P<0>

DP_T29SNK0_ML_C_N<0>

DP_T29SNK0_ML_C_P<1>

DP_T29SNK0_ML_C_N<1>

DP_T29SNK0_ML_C_N<2>

DP_T29SNK0_ML_C_P<2>

DP_T29SNK0_ML_C_P<3>

DP_T29SNK1_ML_C_N<0>

DP_T29SNK1_ML_C_P<1>

DP_T29SNK1_ML_C_P<2>

DP_T29SNK1_ML_C_P<3>

DP_T29SNK1_ML_C_N<3>

DP_T29SNK1_AUXCH_C_P

DP_T29SNK1_AUXCH_C_N

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<0>

DP_T29SNK0_ML_N<1>

DP_T29SNK1_ML_N<0>

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_N<2>

DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_N<3>

DP_T29SNK1_AUXCH_P

DP_T29SNK1_AUXCH_N

DP_T29SNK1_ML_P<1>

DP_T29SNK1_ML_N<1>

DP_T29SNK1_ML_P<2>

DP_T29SNK1_ML_P<3>

T29_R2D_C_P<0>

T29_D2R_N<3>

T29_R2D_C_N<3>

T29_R2D_C_P<3>

T29_D2R_P<2>

T29_R2D_C_N<2>

T29_D2R_N<1>

T29_D2R_P<1>

T29_R2D_C_N<1>

T29_R2D_C_P<1>

T29_LSOE<0>

T29_D2R_N<0>

T29_D2R_P<0>

T29_R2D_C_N<0>

DP_T29SNK1_AUXCH_P

DP_T29SNK1_ML_P<0>

PCIE_T29_R2D_N<1>

DP_T29SNK1_ML_N<0>

TP_T29_TEST_POINT_1

PCIE_T29_D2R_C_P<0>

PCIE_T29_D2R_C_N<1>

PCIE_T29_D2R_C_P<1>

PCIE_T29_D2R_C_P<2>
PCIE_T29_D2R_C_N<2>

PCIE_T29_D2R_C_N<3>

PCIE_T29_D2R_C_P<3>

PCIE_T29_R2D_P<0>
PCIE_T29_R2D_N<0>

PCIE_T29_R2D_N<2>

T29_MONDC1

T29_MONDC0

PCIE_T29_R2D_P<3>

PCIE_T29_R2D_P<2>

T29_RESET_RTR_L

T29_RSENSE

T29_TMU_CLK_OUT

DP_T29SRC_ML_N<1>

DP_T29SRC_ML_N<0>

DP_T29SNK1_ML_N<3>

DP_T29SNK1_ML_P<2>
DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_P<1>

=T29_CLKREQ_L
T29_GPIO<1>
T29_GPIO<2>
T29_RSVD

TP_T29_THERM_DP

T29_TEST_EN
TP_T29_TEST_POINT_0

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_P<1>
DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_P<0>
DP_T29SNK0_ML_N<0>

TP_T29_TEST_POINT_2

DP_T29SNK0_ML_P<2>

DP_T29SNK0_ML_N<3>

T29_PCIE_WAKE_L

T29_MONOBSN

DP_T29SNK0_ML_C_N<3>

DP_T29SNK0_ML_N<3>

T29_LSEO<1>
T29_LSOE<1>

DP_T29SNK1_ML_C_P<0>

DP_T29SNK1_ML_C_N<1>

DP_T29SNK1_ML_P<0>

DP_T29SNK0_AUXCH_N

DP_T29SNK0_ML_P<3>

DP_T29SNK0_AUXCH_N

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_P<0>

T29_RBIAS

=PP3V3_T29_RTR

DP_T29SNK1_HPD

DP_T29SNK1_ML_N<1>

T29_DP_RES

T29_TEST_POINT_3

DP_T29SNK0_ML_P<2>

DP_T29SNK0_AUXCH_P

DP_T29SRC_ML_N<3>

DP_T29SNK0_AUXCH_C_N

DP_T29SNK0_AUXCH_C_P

T29_SPI_MISO

T29ROM_WP_L

T29ROM_HOLD_L

=PP3V3_T29_RTR

T29_SPI_CS_L
T29_SPI_CLK

T29_SPI_MOSI

TP_T29_MONOBSN

PCIE_T29_D2R_N<2>

PCIE_T29_R2D_C_N<3>

97 OF 110

11.1.0

051-8115

86 OF 98

15 21

25 96

83 96

83 96

83 96

86
96

86
96

6

79 80 86 87

86 96

6

79 80 86 87

15 21

96

96

96

86 96

15 18

96

15 21

96

6

79 80 86 87

6

79 80 86 87

96

96

86 96

86 96

83 96

83 96

83 96

83

83 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

96

86 96

96

96

96

96

96

96

96

96

96

96

96

96

96

83 96

83 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

96

6

79 80 86 87

86 96

86 96

86 96

83 96

96

6

79 80 86 87

96

96

96

www.vinafix.vn

VCC3P3_DP_RX1
VCC3P3_DP_RX1

VCC3P3_DP_TXRX
VCC3P3_DP_TXRX

VDD3P3DP_PLL

VCC3P3_DP_TXRXBIAS

VSSDP

VSSDP

VSSDP

VSSDP
VSSDP
VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP_PLL

VSSDP

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0
VCC1P0

VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

VDD1P0_DP_TXRX

VDD1P0_DP_RX1

VDD1P0_DP_TXRX

VDD1P0_DP_PLL

VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE
VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VCC1P0_PE

VCC1P0_PE

VCC3P3
VCC3P3
VCC3P3

VCC3P3_T29
VCC3P3_T29

GND VCC

(SYM 2 OF 2)

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

0-ohms are placeholders for now, replace
with proper values after characterization.

2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA

135 mA (Single-Port)
152 mA (Dual-Port)
EDP: 200 mA

21

L9830

T29

0402

FERR-120-OHM-1.5A

2

1

C9812

T29

6.3V

1UF

CERM
402

10%

2

1

C9813

T29

1UF

6.3V

10%

402

CERM

21

R9820

T29

402

5%

MF-LF

1/16W

0

2

1

C9814

T29

6.3V

10%

402

CERM

1UF

2

1

C9830

T29

CERM

6.3V

20%

2.2UF

402-LF

2

1

C9820

T29

6.3V

10%

402

CERM

1UF

2

1

C9821

T29

6.3V

10%

402

CERM

1UF

2

1

C9822

T29

6.3V

10%

402

CERM

1UF

2

1

C9808

T29

1UF

CERM
402

10%

6.3V

2

1

C9800

T29

10UF

X5R
603

20%

6.3V

2

1

C9801

T29

6.3V

20%

603

X5R

10UF

2

1

C9853

T29

6.3V

10%

402

CERM

1UF

2

1

C9852

T29

6.3V

10%

402

CERM

1UF

2

1

C9844

T29

6.3V

10%

402

CERM

1UF

2

1

C9843

T29

6.3V

10%

402

CERM

1UF

2

1

C9809

T29

1UF

402

10%

6.3V
CERM

2

1

C9870

T29

6.3V
CERM

20%

2.2UF

402-LF

2

1

C9860

T29

CERM

6.3V

20%

2.2UF

402-LF

21

L9870

T29

FERR-120-OHM-1.5A

0402

2

1

C9851

T29

CERM

6.3V

10%

402

1UF

2

1

C9850

T29

CERM

1UF

402

10%

6.3V

21

R9860

T29

MF-LF

0

402

5%

1/16W

21

R9850

T29

MF-LF

0

402

5%

1/16W

2

1

C9845

T29

1UF

CERM

402

10%

6.3V
2

1

C9846

T29

603

6.3V

20%

10UF

X5R

2

1

C9847

T29

6.3V

20%

603

X5R

10UF

2

1

C9810

T29

1UF

6.3V

10%

402

CERM

2

1

C9811

T29

1UF

CERM
402

10%

6.3V

B19

B17

B15

B13

B11

W20

W18

U20

U18

R20

R18

B9

N20

N18

N16

L20

L18

L16

J20

J18

J16

G20

B7

G18

F17

F15

F13

F11

F9

F7

E20

E18

D17

B5

D15

D13

D11

D9

D7

D5

D3

D1

C20

C18

B3

B1

T13

W8

W6

W4

V17

T17

T15

T11

T9

AA2

Y1

W14

W12

W10

T7

T5

N8

L14

L12

L10

L8

J14

J12

J10

N14

N12

N10

J8

G8

P13

R12

R10

R8

R14

G12

G10

P15

P11

P9

R6

P7

K7

M7

H7

G14

E12

E10

E8

M15

K15

H15

M13

M11

M9

K13

K11

K9

H13

H11

H9

U9700

FCBGA

T29

CRITICAL

OMIT

2

1

C9805

T29

1UF

6.3V

10%

402

CERM

2

1

C9806

T29

CERM
402

10%

6.3V

1UF

2

1

C9807

T29

CERM
402

10%

6.3V

1UF

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

T29 Host (2 of 2)

PP1V05_T29_VDD_DP

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

=PP1V05_T29_RTR

=PP3V3_T29_RTR

PP1V05_T29_VDD_DPPLL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=1.05V

PP3V3_T29_DPBIAS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_T29_PLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_T29_DP

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

98 OF 110

11.1.0

051-8115

87 OF 98

6

6

79 80 86

www.vinafix.vn

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

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SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TWO OZ POWER

HALF OZ SIGNAL

0.071 PREPREG

TOP

BOARD STACK-UP

2

6

7

0.370 PREPREG

HALF OZ SIGNAL

ONE OZ SIGNAL

0.076 PREPREG

TWO OZ GND

BOTTOM

0.101 CORE

TWO OZ POWER

4

PHYSICAL CONSTRAINTS

BOARD THICKNESS = 62 MIL (1.5748 mm)

SPACING RULE SET

0.071 PREPREG

TWO OZ GND

0.370 PREPREG
ONE OZ SIGNAL

0.076 PREPREG

5

3

CONSTRAINTS FOR BGA AREA

K60/62 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

0.085 MM

=STANDARD

0.1 MM

*

1:1_DIFFPAIR

=STANDARD=STANDARD

Y

0.200 MM

* Y

POWER_WIDTH

3.0 MM

=STANDARD =STANDARD

0.600 MM

0.300 MM

Y

3.0 MM

=STANDARD =STANDARD

POWER_CTL

0.200 MM

*

=STANDARD

=STANDARD

=STANDARD

* N

110_OHM_DIFF

=STANDARD =STANDARD

=STANDARD

0.075 MM

110_OHM_DIFF

0.075 MM

0.15 MM

TOP,BOTTOM

Y

0.320 MM

0.085 MM

100_OHM_DIFF

0.091 MM

Y

TOP,BOTTOM

0.1 MM0.25 MM

=STANDARD

=STANDARD

=STANDARD

=STANDARD

110_OHM_DIFF

=STANDARDISL3,ISL6 =STANDARD

Y

=STANDARD

100_OHM_DIFF

0.081 MM0.081 MM

0.25 MM

ISL3,ISL6

Y

0.1 MM

=STANDARD

100_OHM_DIFF

N

=STANDARD=STANDARD

*

=STANDARD=STANDARD

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

K60/K62 RULE DEFINITIONS

=STANDARD=STANDARD

=STANDARD=STANDARD

* N

68_OHM_DIFF

=STANDARD

0.13 MM

Y

68_OHM_DIFF

0.090 MM

=STANDARD

0.1 MMISL3,ISL6

0.16 MM

0.1 MM0.2 MM

Y

85_OHM_DIFF

=STANDARD

TOP,BOTTOM

0.085 MM0.125 MM

=STANDARD

85_OHM_DIFF

0.085 MM

Y

0.2 MM 0.1 MM

0.115 MM

ISL3,ISL6

55_OHM_SE

0.076 MM

=STANDARD

*

=STANDARD

Y

=STANDARD

0.076 MM

=STANDARD55_OHM_SE

Y

TOP,BOTTOM

0.085 MM 0.085 MM

0.085 MM

15 MM

Y

TOP,BOTTOM

0.1 MM50_OHM_SE

=STANDARD

=STANDARD

Y*

42_OHM_SE

0.135 MM 0.090 MM

=STANDARD

MM

15.5.1

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM NO_TYPE,BGA,BGA_P1MM

0.21 MM

Y

=STANDARD

TOP,BOTTOM

34_OHM_SE

0.090 MM

=STANDARD

=STANDARD

*

39_OHM_SE

Y

0.090 MM

=STANDARD

0.159 MM

0.085 MM

=STANDARD

=STANDARD

* Y

0.1 MM50_OHM_SE

=STANDARD

* N

90_OHM_DIFF

=STANDARD

=STANDARD =STANDARD

=STANDARD =STANDARD

ISL3,ISL6

0.085 MM

12 MM

0.1 MM

Y

0.2 MM

90_OHM_DIFF

0.099 MM

0.1 MM0.13 MM

TOP,BOTTOM

Y

=STANDARD

0.090 MM

68_OHM_DIFF

0.165 MM

TOP,BOTTOM

0.110 MM 0.085 MM

Y

=STANDARD

0.2 MM

90_OHM_DIFF

0.1 MM

STANDARD

*

VR_CONTROLVR_CONTROL

=STANDARD

85_OHM_DIFF

N*

=STANDARD

=STANDARD=STANDARD=STANDARD

*

STANDARD

SWITCHNODEVR_CONTROL

BGA

*

BGA_P1MMCLK_PCIE

*

MEM_CLK

BGA_P1P5MM

BGA

**

BGA

BGA_P1MM

BGA_P1MM

*

BGA_P1MM

*

*

0.2 MM

?

BGA_P2MM

*

0.8 MM

SWITCHNODE

1000

* ?

BGA_P1P5MM

0.15 MM

=DEFAULT

?

BGA_P1MM

*

=STANDARD39_OHM_SE

TOP,BOTTOM

Y

0.175 MM 0.090 MM

POWER_CTL

POWER

BGA_P1MM

POWER_WIDTH

*

POWER

* *

VR_CONTROL SWITCHNODE

BGA

*

CLK_PCI

BGA_P1MM

6:1_SPACING

*

0.6 MM

?

*

0.5 MM

?

5:1_SPACING

*

0.4 MM

?

4:1_SPACING

*

0.3 MM

?

3:1_SPACING

STANDARD

*

=DEFAULT

?

2:1_SPACING

?

0.2 MM

*

TOP,BOTTOM

=STANDARD42_OHM_SE

Y

0.151 MM 0.090 MM

* ?

7X_DIELECTRIC

0.532 MM

0.497 MM

?

TOP,BOTTOM

7X_DIELECTRIC

=STANDARD

* Y

=STANDARD34_OHM_SE

0.19 MM

0.090 MM

=STANDARD

DEFAULT

VR_CTL_PHY

BGA_P1MM

?*

0.380 MM

5X_DIELECTRIC

0.285 MM

?

TOP,BOTTOM

4X_DIELECTRIC

5X_DIELECTRIC

TOP,BOTTOM

?

0.355 MM

3.5:1_SPACING

*

?

0.35 MM

2.5:1_SPACING

*

?

0.25 MM

DEFAULT

* ?

0.1 MM

0.215 MM

?

TOP,BOTTOM

3X_DIELECTRIC

POWER

**

STANDARD

GND

**

STANDARD

* ?

2X_DIELECTRIC

0.155 MM

0.145 MM

?

2X_DIELECTRIC

TOP,BOTTOM

0.230 MM

3X_DIELECTRIC

* ?

0.305 MM

* ?

4X_DIELECTRIC

=DEFAULT

=DEFAULT

Y

=DEFAULT

=DEFAULTSTANDARD

12.7 MM

*

* Y

=50_OHM_SE

0 MM0 MM

100 MM

DEFAULT

=50_OHM_SE

0.2 MM

*

PWR_P2MM

1000

BGA

BGA_P1MM

*

CLK_LPC

GND_P2MM

*

0.2 MM

1000

GND =STANDARD

*

?

GND

VR_CONTROL

*

STANDARD

VR_CTL_PHY

POWER_CTL

*

100 OF 110

11.1.0

051-8115

88 OF 98

www.vinafix.vn

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

NET_TYPE

SPACING

SPACING

NET_TYPE

Memory Bus Constraints

ELECTRICAL_CONSTRAINT_SET

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICALPHYSICAL

NET_TYPE

VOLTAGEVOLTAGE

Memory Bus Spacing Group Assignments

MEMORY MISC PROPERTIES

PHYSICAL

I162

I168
I169

I170

I171

I172

I173

I174

I175

I177

*

MEM_DQ_BYTE4

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE0

MEM_DQ_BYTE1

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE0

MEM_DQ_BYTE2

MEM_DQ_DIFFBYTE

*

MEM_DQ_BYTE0

MEM_DQ_BYTE0 MEM_DQ_BYTE0

*

MEM_DQ_SAMEBYTE

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE2 MEM_DQ_BYTE5

MEM_DQ_BYTE4MEM_DQ_BYTE2

*

MEM_DQ_DIFFBYTE

MEM_DATA2MEM

MEM_CMD

*

MEM_DQ_BYTE2

MEM_DATA2MEM

MEM_CTRL

*

MEM_DQ_BYTE0

MEM_CMD

*

MEM_DATA2MEMMEM_DQ_BYTE0

MEM_DATA2MEM

MEM_CMD

*

MEM_DQ_BYTE4

MEM_DQ_BYTE4

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE7

MEM_DQ_BYTE2MEM_DQ_BYTE2

*

MEM_DQ_SAMEBYTE

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE2 MEM_DQ_BYTE6

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE4MEM_DQ_BYTE1

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE3MEM_DQ_BYTE1

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE5

*

MEM_DQ_BYTE1

MEM_DATA2MEM

*

MEM_DQ_BYTE4

MEM_CTRL

MEM_DQ_DIFFBYTE

*

MEM_DQ_BYTE3MEM_DQ_BYTE2

MEM_DQ_BYTE4

MEM_2OTHER

**

MEM_DQ_BYTE4

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE6

MEM_DQ_BYTE4

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE5

MEM_DQ_SAMEBYTE

MEM_DQ_BYTE4

*

MEM_DQ_BYTE4

MEM_DQ_BYTE3 MEM_DQ_BYTE7

MEM_DQ_DIFFBYTE

*

MEM_DQ_BYTE3

MEM_DQ_SAMEBYTE

MEM_DQ_BYTE3

*

MEM_DATA2MEM

MEM_CTRL

*

MEM_DQ_BYTE2

MEM_CMD

*

MEM_CMD2MEM

MEM_CTRL

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

**

MEM_2OTHER

*

MEM_DQS

MEM_DQS2MEM

MEM_CTRL

MEM_CMD

MEM_DQS2MEM

*

MEM_DQS

MEM_DQS2MEM

MEM_DQS

MEM_DQ_BYTE1

*

MEM_DQ_BYTE0

MEM_DQS

MEM_DQS2MEM

*

MEM_DQ_BYTE2

MEM_DQS

MEM_DQS2MEM

*

MEM_DQ_BYTE3

MEM_DQS

MEM_DQS2MEM

*

MEM_DQ_BYTE4

MEM_DQS

MEM_DQS2MEM

*

MEM_DQ_BYTE5

MEM_DQS

MEM_DQS2MEM

*

MEM_DQ_BYTE6

MEM_DQS2MEM

MEM_DQS

*

**

MEM_DQS

MEM_2OTHER

MEM_DQS

MEM_DQ_BYTE7

MEM_DQS2MEM

*

MEM_DQ_BYTE5

*

MEM_CTRL

MEM_DATA2MEM

MEM_DQ_BYTE5

*

MEM_CMD

MEM_DATA2MEM

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE5

*

MEM_DQ_BYTE7

*

MEM_DQ_BYTE5MEM_DQ_BYTE5

MEM_DQ_SAMEBYTE

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE6MEM_DQ_BYTE5

*

=STANDARD

=34_OHM_SE

=STANDARD

=34_OHM_SE=34_OHM_SE

*

MEM_34S

=34_OHM_SE

=42_OHM_SE

=STANDARD

*

=42_OHM_SE =42_OHM_SE

=STANDARD

MEM_42S

=42_OHM_SE

=68_OHM_DIFF

=68_OHM_DIFF=68_OHM_DIFF

=68_OHM_DIFF=68_OHM_DIFF=68_OHM_DIFF

*

MEM_68D

=STANDARD

MEM_39S

*

=39_OHM_SE

=STANDARD

=39_OHM_SE=39_OHM_SE =39_OHM_SE

*

=4:1_SPACING

?

MEM_CLK2MEM

=4:1_SPACING

*

MEM_DQS2MEM

?

?

=5:1_SPACING

*

MEM_DQ_DIFFBYTE

MEM_2OTHER

MEM_CMD

**

MEM_CMD2CMD

MEM_CMD

*

MEM_CMD

*

MEM_CLK

MEM_2OTHER

*

MEM_CLK

*

MEM_CLK

MEM_CLK2MEM

=50_OHM_SE

*

=STANDARD

=50_OHM_SE

MEM_50S

=50_OHM_SE

=STANDARD

=50_OHM_SE

?*

MEM_CMD2MEM

=3:1_SPACING

MEM_CMD2CMD

?

=2:1_SPACING

*

MEM_DATA2MEM

*

MEM_CTRL

MEM_DQ_BYTE1

MEM_CMD

*

MEM_DQ_BYTE1 MEM_DATA2MEM

*

MEM_DQ_BYTE2MEM_DQ_BYTE1

MEM_DQ_DIFFBYTE

MEM_DQ_SAMEBYTE

*

MEM_DQ_BYTE1 MEM_DQ_BYTE1

=42_OHM_SE

*

=42_OHM_SE

0.1016 MM0.1016 MM

=42_OHM_SE =42_OHM_SE

MEM_42S_D

*

MEM_DQ_BYTE0 MEM_DQ_BYTE3

MEM_DQ_DIFFBYTE

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE0 MEM_DQ_BYTE5

*

MEM_2OTHER

* ?

=5:1_SPACING

* ?

=4:1_SPACINGMEM_DATA2MEM

?

=3:1_SPACING

MEM_DQ_SAMEBYTE

*

?

=3:1_SPACINGMEM_CTRL2MEM

*

?*

=2.5:1_SPACING

MEM_CTRL2CTRL

MEM_DQ_BYTE3

* *

MEM_2OTHER

MEM_DATA2MEM

*

MEM_CMD

MEM_DQ_BYTE3

*

MEM_DQ_BYTE7MEM_DQ_BYTE2

MEM_DQ_DIFFBYTE

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE0

*

MEM_DQ_BYTE6

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE0

*

MEM_DQ_BYTE7

*

MEM_DQ_BYTE0

MEM_2OTHER

*

MEM_POWER_WIDTH

MEM_POWER_PHY

*

MEM_2OTHER

**

MEM_DQ_BYTE5

MEM_DQ_BYTE7

MEM_2OTHER

**

MEM_DQ_SAMEBYTE

MEM_DQ_BYTE7

*

MEM_DQ_BYTE7

*

MEM_CMD

MEM_DQ_BYTE7 MEM_DATA2MEM

*

MEM_CTRL

MEM_DQ_BYTE7 MEM_DATA2MEM

* *

MEM_2OTHER

MEM_DQ_BYTE6

MEM_DQ_BYTE7

MEM_DQ_DIFFBYTE

*

MEM_DQ_BYTE6

MEM_DQ_BYTE6

*

MEM_DQ_BYTE6

MEM_DQ_SAMEBYTE

MEM_CMD

MEM_DQ_BYTE6

*

MEM_DATA2MEM

MEM_DATA2MEM

*

MEM_DQ_BYTE6

MEM_CTRL

MEM_DQ_BYTE3 MEM_DQ_BYTE6

*

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE5MEM_DQ_BYTE3

MEM_DQ_DIFFBYTE

*

*

MEM_2OTHER

MEM_DQ_BYTE1

*

MEM_DQ_DIFFBYTE

*

MEM_DQ_BYTE1 MEM_DQ_BYTE7

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE6

*

MEM_DQ_BYTE1

MEM_DQ_BYTE4

MEM_DQ_DIFFBYTE

MEM_DQ_BYTE3

*

MEM_CTRL

MEM_DQ_BYTE3

*

MEM_DATA2MEM

SYNC_DATE=01/06/2011

Memory Constraints

SYNC_MASTER=K60_ROSITA

* Y =STANDARD

MEM_POWER_WIDTH

=STANDARD

=STANDARD

0.500 MM 0.250 MM

?*

MEM_POWER

=3:1_SPACING

MEM_2OTHER

*

MEM_DQ_BYTE2

*

MEM_POWER

MEM_POWER_PHY

CPU_DIMM_VREF_B_SW

MEM_POWER_PHY

MEM_POWER

VREFMARGIN_DIMMB_DQ

PM

MEM_50S

MEM_RESET_L

MEM_DQS

MEM_A_DQS_N<7>

MEM_42S_D

MEM_A_DQS_N<6>

MEM_42S_D

MEM_DQS

MEM_DQS

MEM_42S_D

MEM_A_DQS_P<7>

MEM_42S_D

MEM_A_DQS_P<2>

MEM_DQS

MEM_DQS

MEM_A_DQS_N<2>

MEM_42S_D

MEM_B_DQ<55..48>

MEM_42S

MEM_DQ_BYTE6

MEM_A_ODT<3..0>

MEM_CTRL

MEM_39S

MEM_B_DQS_P<5>

MEM_DQS

MEM_42S_D

MEM_DQS

MEM_B_DQS_N<3>

MEM_42S_D

MEM_DQ_BYTE5

MEM_42S

MEM_B_DQ<47..40>

MEM_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_42S

MEM_DQ_BYTE3

MEM_42S

MEM_B_DQ<31..24>

MEM_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_42S

MEM_DQ_BYTE1

MEM_42S

MEM_B_DQ<15..8>

MEM_DQ_BYTE0

MEM_42S

MEM_B_DQ<7..0>

MEM_42S

MEM_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_DQS

MEM_A_DQS_P<0>

MEM_42S_D

MEM_CMD

MEM_B_WE_L

MEM_34S

MEM_B_CAS_L

MEM_CMDMEM_34S

MEM_CTRL

MEM_B_ODT<3..0>

MEM_39S

MEM_34S

MEM_B_RAS_L

MEM_CMD

MEM_34S

MEM_B_A<15..0>

MEM_CMD

MEM_A_BA<2..0>

MEM_CMDMEM_34S

MEM_A_A<15..0>

MEM_CMDMEM_34S

MEM_42S

MEM_A_DQ<39..32>

MEM_DQ_BYTE4

MEM_42S

MEM_A_DQ<31..24>

MEM_DQ_BYTE3

MEM_42S

MEM_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_A_DQ<15..8>

MEM_42S

MEM_DQ_BYTE1

MEM_A_DQ<7..0>

MEM_42S

MEM_DQ_BYTE0

MEM_A_DQS_N<0>

MEM_DQS

MEM_42S_D

MEM_42S_D

MEM_A_DQS_P<3>

MEM_DQS

MEM_42S_D

MEM_A_DQS_N<1>

MEM_DQS

MEM_DQS

MEM_B_DQS_N<2>

MEM_42S_D

MEM_B_DQS_P<6>

MEM_DQS

MEM_42S_D

MEM_DQS

MEM_42S_D

MEM_B_DQS_N<7>

MEM_68D

MEM_A_CLK_P<3..0>

MEM_CLK
MEM_CLKMEM_68D

MEM_A_CLK_N<3..0>

MEM_CTRL

MEM_39S

MEM_A_CKE<3..0>

MEM_B_DQS_N<6>

MEM_DQS

MEM_42S_D

MEM_42S_D

MEM_DQS

MEM_A_DQS_P<1>

MEM_A_CAS_L

MEM_CMDMEM_34S

MEM_DQS

MEM_B_DQS_P<7>

MEM_42S_D

MEM_CMD

MEM_A_WE_L

MEM_34S

MEM_B_CLK_N<3..0>

MEM_CLKMEM_68D

MEM_B_CLK_P<3..0>

MEM_CLKMEM_68D

MEM_B_CKE<3..0>

MEM_39S

MEM_CTRL

MEM_A_RAS_L

MEM_CMDMEM_34S

MEM_DQS

MEM_B_DQS_P<2>

MEM_42S_D

MEM_B_DQS_N<5>

MEM_DQS

MEM_42S_D

MEM_B_DQS_N<4>

MEM_DQS

MEM_42S_D

MEM_DQS

MEM_B_DQS_P<4>

MEM_42S_D

MEM_B_DQS_P<3>

MEM_42S_D

MEM_DQS

MEM_B_DQS_N<1>

MEM_DQS

MEM_42S_D

MEM_CTRL

MEM_B_CS_L<3..0>

MEM_39S

MEM_34S MEM_CMD

MEM_B_BA<2..0>

MEM_DQS

MEM_B_DQS_P<0>

MEM_42S_D

MEM_B_DQS_N<0>

MEM_DQS

MEM_42S_D

MEM_42S

MEM_B_DQ<63..56>

MEM_DQ_BYTE7

MEM_42S

MEM_A_DQ<47..40>

MEM_DQ_BYTE5

MEM_42S

MEM_A_DQ<63..56>

MEM_DQ_BYTE7

MEM_42S_D

MEM_DQS

MEM_A_DQS_N<4>

MEM_42S_D

MEM_DQS

MEM_A_DQS_N<3>

MEM_42S_D

MEM_A_DQS_P<6>

MEM_DQS

MEM_42S_D

MEM_DQS

MEM_A_DQS_P<4>

MEM_CTRL

MEM_39S

MEM_A_CS_L<3..0>

MEM_DQS

MEM_B_DQS_P<1>

MEM_42S_D

MEM_42S_D

MEM_A_DQS_N<5>

MEM_DQS

MEM_42S_D

MEM_A_DQS_P<5>

MEM_DQS

MEM_POWER_PHY

MEM_POWER

CPU_DIMM_VREF_A

MEM_POWER

MEM_POWER_PHY

CPU_DIMM_VREF_B

MEM_POWER_PHY

MEM_POWER

CPU_DDR_VREF

MEM_POWER

MEM_POWER_PHY

VREFMARGIN_DIMMA_DACOUT

MEM_POWER

MEM_POWER_PHY

VREFMARGIN_DIMMA_OPFB

MEM_POWER_PHY

MEM_POWER

VREFMARGIN_DIMMA_DQ

MEM_POWER_PHY

MEM_POWER

CPU_DIMM_VREF_A_SW

MEM_POWER_PHY

MEM_POWER

VREFMARGIN_DIMMB_DACOUT

MEM_POWER_PHY

MEM_POWER

VREFMARGIN_DIMMB_OPFB

101 OF 110

11.1.0

051-8115

89 OF 98

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DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SPACING

CPU

UNUSED PCIE

UNUSED CLOCKS

CLOCKS

SATA

PCIE GRAPHICS

PCI-Express

SATA Interface Constraints

PCIE REF CLOCKS

PCIE I/O

DMI

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SATA

PHYSICAL

CPU ITP

CPU_MISC

PCIE

ANY OTHER LYNNFIELD CONSTRAINTS NOT COVERED ON PAGES 101 AND 107 SHOULD GO ON THIS PAGE TOO

I299

I300

I301

I302
I303

I304

I305
I306

I315

I316

I317

I318

I319
I320

I321

I322
I323

I324
I325

I326

I327

I328

I329

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I332

I333
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I335
I336

I337
I338

I339

I340

I341

I342

I343

I344

I345

I347
I348

I349

I350

=6:1_SPACING

?

TOP,BOTTOM

SATA

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

SATA_90D

*

*

0.2 MM

CPU_ITP

?

CPU_RCOMP_PHY

0.254 MM

* Y

3.0 MM

=STANDARD

0.200 MM

=STANDARD

?

0.2 MM

*

CPU_RCOMP

=4:1_SPACING

?

TOP,BOTTOM

PCIE

*

PCIE

=4X_DIELECTRIC

?

*

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFFCLK_PCIE_90D

=85_OHM_DIFF

*

=85_OHM_DIFF

PCIE_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

=6:1_SPACING

SATA

* ?

=50_OHM_SE=50_OHM_SE =50_OHM_SE

=STANDARD=STANDARD

*

CPU_50S

=50_OHM_SE

CLK_PCIE

* ?

0.5 MM

PCIE/DMI/FDI/SATA CONSTRAINTS

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

PCIE_85D

PCIE

PCIE_USB3_1_D2R_P

PCIE_85D

PCIE

PCIE_USB3_1_D2R_C_N

XDP_CPU_TRST_L

CPU_50S CPU_ITP

XDP_CPU_TMS

CPU_ITPCPU_50S

XDP_CPU_TCK

CPU_50S CPU_ITP

XDP_CPU_TDI

CPU_50S CPU_ITP

XDP_CPU_TDO

CPU_ITPCPU_50S

PCIE

PCIE_USB3_2_R2D_C_N

PCIE_85D

PCIE_85D

PCIE_USB3_1_D2R_N

PCIE

PCIE_USB3_1_D2R_C_P

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_USB3_2_R2D_N

PCIE

PCIE_USB3_2_R2D_C_P

PCIE_85D

PCIE_USB3_2_D2R_P

PCIE

PCIE_85D

PCIE_85D

PCIE

PCIE_USB3_2_D2R_C_P

CPU_ITPCPU_50S

XDP_OBSDATA_B<3..0>

PCIE_USB3_2_D2R_N

PCIE

PCIE_85D

CPU_CFG<17..0>

CPU_ITPCPU_50S

PCIE_85D

PCIE

PCIE_USB3_1_R2D_N

PCIE

PCIE_85D

PCIE_USB3_1_R2D_C_N

PCIE_85D

PCIE

PCIE_USB3_1_R2D_C_P

PCIE_USB3_2_D2R_C_N

PCIE

PCIE_85D

CPU_50S

XDP_CPU_CFG<0>

CPU_ITP

CPU_RCOMP

CPU_RCOMP_PHY

CPU_PEG_COMP

CPU_ITPCPU_50S

XDP_BPM_L<7..0>

PCIE_USB3_2_R2D_P

PCIE_85D

PCIE

SATA_SSD_R2D_N

SATA

SATA_90D

CLK_PCIE

DMI_CLK100M_CPU_N

CLK_PCIE_90D

DMI_MIDBUS_CLK100M_P

CLK_PCIE_90D

CLK_PCIE

PCIE_85D

PCIE

DMI_S2N_P<3..0>

CLK_PCIE

CLK_PCIE_90D

DMI_MIDBUS_CLK100M_N

PCIE_85D

PCIE

DMI_S2N_N<3..0>

PCIE_CLK100M_MINI_P

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE

GPU_CLK100M_PCIE_N

CLK_PCIE_90D

PCIE_CLK100M_FW_N

CLK_PCIE

CLK_PCIE_90D

PEG_R2D_C_N<15..0>

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE_MINI_R2D_N

PCIE_CLK100M_ENET_P

ENET_MII

ENET_100D

CLK_PCIE_90D

PCIE_CLK100M_FW_P

CLK_PCIE

PCIE

PEG_D2R_N<15..0>

PCIE_85D

PCIE

PCIE_85D

PCIE_MINI_R2D_C_N

ENET_MII

PCIE_CLK100M_ENET_N

ENET_100D

CLK_PCIE

PCIE_CLK100M_MINI_N

CLK_PCIE_90D

GPU_CLK100M_PCIE_P

CLK_PCIE

CLK_PCIE_90D

DMI_CLK100M_CPU_P

CLK_PCIE

CLK_PCIE_90D

PCIE_85D

PCIE_MINI_D2R_P

PCIE

PCIE_FW_R2D_C_N

PCIE

PCIE_85D

PCIE_FW_D2R_P

PCIE

PCIE_85D

PEG_R2D_C_P<15..0>

PCIE

PCIE_85D

PEG_D2R_P<15..0>

PCIE

PCIE_85D

PCIE_MINI_R2D_P

PCIE_85D

PCIE

PCIE

PCIE_85D

PCIE_MINI_R2D_C_P

PCIE_85D

PCIE_MINI_D2R_N

PCIE

PCIE_85D

PCIE

DMI_N2S_N<3..0>

PCIE_85D

PCIE

DMI_N2S_P<3..0>

PCIE_FW_D2R_C_N

PCIE_85D

PCIE

PCIE_FW_D2R_C_P

PCIE_85D

PCIE

PCIE_FW_D2R_N

PCIE

PCIE_85D

PCIE_FW_R2D_C_P

PCIE_85D

PCIE

PCIE_FW_R2D_N

PCIE_85D

PCIE

PCIE_85D

PCIE_FW_R2D_P

PCIE

MXM_PCIE_D2R_P<7..0>

PCIE_85D

PCIE

MXM_PCIE_R2D_N<7..0>

PCIE

PCIE_85D

MXM_PCIE_R2D_P<7..0>

PCIE_85D

PCIE

MXM_PCIE_D2R_N<7..0>

PCIE_85D

PCIE

SATA

SATA_HDD_R2D_N

SATA_90D

SATA_HDD_R2D_C_N

SATA

SATA_90D

SATA

SATA_HDD_R2D_P

SATA_90D

SATA

SATA_HDD_R2D_C_P

SATA_90D

SATA_ODD_D2R_C_N

SATA

SATA_90D

SATA

SATA_ODD_D2R_N

SATA_90D

SATA_ODD_D2R_C_P

SATA

SATA_90D

SATA

SATA_ODD_R2D_N

SATA_90D

SATA

SATA_ODD_R2D_P

SATA_90D

SATA_ODD_D2R_P

SATA

SATA_90D

SATA

SATA_ODD_R2D_C_P

SATA_90D

SATA

SATA_ODD_R2D_C_N

SATA_90D

SATA

SATA_90D

SATA_HDD_D2R_C_P

PCH_CLK100M_DMI_P

CLK_PCIE

CLK_PCIE_90D

PCH_CLK100M_DMI_N

CLK_PCIE

CLK_PCIE_90D

PCH_CLK96M_DOT_P

CLK_PCIE

CLK_PCIE_90D

PCH_CLK96M_DOT_N

CLK_PCIE

CLK_PCIE_90D

PCH_CLK100M_SATA_P

CLK_PCIE

CLK_PCIE_90D

PCH_CLK100M_SATA_N

CLK_PCIE

CLK_PCIE_90D

ITPXDP_CLK100M_P

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

ITPXDP_CLK100M_N

CLK_PCIE_90D

CLK_PCIE

ITPCPU_CLK100M_P

CLK_PCIE_90D

CLK_PCIE

ITPCPU_CLK100M_N

CLK_PCIE_90D

CLK_PCIE

TP_CLK133M_PCH_N

CLK_PCIE_90D

CLK_PCIE

TP_CLK133M_PCH_P

CLK_PCIE_90D

XDP_CPU_CLK100M_P

CLK_PCIE_90D

CLK_PCIE

XDP_CPU_CLK100M_N

CLK_PCIE_90D

CLK_PCIE

PCIE_85D

PCIE

MXM_PCIE_D2R_P<8..15>

PCIE

PCIE_85D

MXM_PCIE_R2D_N<8..15>

PCIE_85D

PCIE

MXM_PCIE_R2D_P<8..15>

PCIE_85D

PCIE

MXM_PCIE_D2R_N<8..15>

PCIE_USB3_1_R2D_P

PCIE_85D

PCIE

SATA

SATA_90D

SATA_SSD_D2R_C_N

SATA

SATA_90D

SATA_SSD_D2R_C_P

SATA

SATA_90D

SATA_SSD_D2R_N

SATA

SATA_90D

SATA_SSD_D2R_P

SATA_SSD_R2D_P

SATA

SATA_90D

SATA_SSD_R2D_C_N

SATA

SATA_90D

SATA

SATA_90D

SATA_SSD_R2D_C_P

SATA

SATA_HDD_D2R_P

SATA_90D

SATA

SATA_HDD_D2R_N

SATA_90D

SATA

SATA_HDD_D2R_C_N

SATA_90D

102 OF 110

11.1.0

051-8115

90 OF 98

11 25

11 25

11 25

11 25

11 25

25

10 15 25

25

10

11 25

42

11 18

10 19

10 19

18 33

9

18 39

9

77

33

18 37

18 39

9

77

18 33

18 37

18 33

9

11 18

18 33

18 39

18 39

9

77

9

77

33

18 33

18 33

10 19

10 19

39

39

18 39

18 39

39

39

75 77

75 77

75 77

75 77

42

18 42

42

18 42

42

18 42

42

42

42

18 42

18 42

18 42

42

18 26

18 26

18 26

18 26

18 26

18 26

18 25

18 25

11 18

11 18

26

26

25

25

75 77

75 77

75 77

75 77

42

42

18 42

18 42

42

18 42

18 42

18 42

18 42

42

www.vinafix.vn

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NET_TYPE

SPACING

PCI Bus Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPI Interface Constraints

HD Audio Interface Constraints

SMBus Interface Constraints

XTAL Constraints

LPC Bus Constraints

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SPACING

PCH CONSTRAINTS

PHYSICAL

SPACING

NET_TYPE

NET_TYPE

SPACING

PHYSICAL

I322

I323

I324

I325
I326

I327

I328

I329
I330

I331

I332
I334

I335

I336

I337

I338

I339
I340

I341

I342
I343

I344

I345

I346

I347

I348
I349

I350
I351

I352

I354

I355

I356

I357

I372
I373

I374

I375

I376

I377

I378
I379

I380

I381

I382

IBEX PEAK CONSTRAINTS

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

CLK_PCH_55S

=55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE

=STANDARD

*

=55_OHM_SE

=STANDARDPCI

* ?

*

0.15 MM

?

LPC

=STANDARD

=55_OHM_SE

CLK_LPC_55S

*

=55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE

=STANDARD

=55_OHM_SE

PCH_55S

*

=55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE

0.2 MM

CLK_PCI

* ?

XTAL

=4X_DIELECTRIC

?*

SPI

?*

0.2 MM

=55_OHM_SE

=STANDARD

=55_OHM_SE =55_OHM_SE

SMB_55S

*

=STANDARD

=55_OHM_SE

=2x_DIELECTRIC

SMB

* ?

0.2 MM

*

CLK_LPC

?

=55_OHM_SE

=STANDARD

*

LPC_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

*

=STANDARD=STANDARD

HDA_55S

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

=2x_DIELECTRIC

HDA

* ?

=55_OHM_SE

*

=STANDARD =STANDARD

SPI_55S

=55_OHM_SE =55_OHM_SE=55_OHM_SE

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF

CLK_XTAL

=100_OHM_DIFF

=100_OHM_DIFF

0.2 MM

?*

ITP_PCH

0.2 MM

?

COMP_PCH

*

=4:1_SPACING

CLK_PCH

* ?

=STANDARD

=55_OHM_SE

PCI_55S

=STANDARD

=55_OHM_SE

*

=55_OHM_SE=55_OHM_SE

=55_OHM_SE

=STANDARD

CLK_PCI_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

PCI_REQ0_L

PCI

PCI_55S

PCI_55S

PCI

PCI_REQ2_L
PCI_REQ3_L

PCI_55S

PCI

PCI_55S

PCI

PCI_REQ1_L

PCH_PEG_CLKREQ_L

PM

LPC

LPC_55S

LPC_FRAME_L

LPC_AD<3..0>

LPC

LPC_55S

CLK_PCI_55S

CLK_PCI

PCH_CLK33M_PCIOUT

CLK_PCI

PCH_CLK33M_PCIIN

CLK_PCI_55S

DP_AUXCH_ISOL

PM

PM

XDPCPU_PLTRST_L

CPU_SKTOCC

PM

PM

PLT_RST_BUF_L

ENET_SW_RESET_L

PM

ENET_RESET_LOGIC_L

PM

ALL_SYS_PWRGD

PM

PM

AUD_IPHS_SWITCH_EN_PCH

ENET_RESET_FET_L

PM

ENET_CLKREQ_FET_L

PM

PGOOD_5V_1V05_3V3

PM

PGOOD_CPU_UNCORE

PM

PGOOD_3V3_1V05

PM

PGOOD_PCH_S0_R

PM

PM_EN_USB_PWR

PM

T29_DP_PORTA_PWR_EN

PM

DP_GPU_T29_SEL

PM

PM

T29_CLKREQ_L

PM

FW_MINI_CLKREQ_L

PM

T29_MCU_INT_L

PM

T29_DP_PORTB_PWR_EN

ENET_CLKREQ_L

PM

T29_SW_RESET_L

PM

PM

BLC_GPIO

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_LPCPLUS

CLK_LPC_55S

PM

PM_CLK32K_SUSCLK_R

CLK_LPC_55S

PM

PM_CLK32K_SUSCLK
LPC_CLK33M_LPCPLUS_R

CLK_LPC_55S

CLK_LPC

LPC_R_AD<3..0>

LPC_55S

LPC

LPC_FRAME_R_L

LPC_55S

LPC

SPI_MOSI_1_R

SPI_55S

SPI

SPI

SPI_55S

SPI_CS0_R_L

SPI_MISO_R

SPI_55S

SPI

SPI_MOSI

SPI

SPI_55S

SPI_55S

SPI

SPI_MOSI_R

SPI_CLK_R

SPI_55S

SPI

SPI_CLK

SPI

SPI_55S

SPI_ALT_CS_L

SPI_55S

SPI

SPI_55S

SPI

SPIROM_USE_MLB

SPI

SPI_55S

SPI_ALT_MOSI

SPI_MLB_CS_L

SPI_55S

SPI

SPI_55S

SPI

SPI_ALT_MISO

HDA

HDA_55S

HDA_SDOUT_R

HDA

HDA_55S

HDA_SDIN0

HDA_SYNC_R

HDA

HDA_55S

SPI_55S

SPI

SPI_ALT_CLK

LPC_CLK33M_SMC_R

CLK_LPC

CLK_LPC_55S

HDA

HDA_55S

HDA_RST_R_L

PCH_55S

PCH_DMI2RBIAS

COMP_PCH

PCH_55S

ITP_PCH

XDP_PCH_TDI

XTAL

CLK_XTAL

CK505_XTAL_IN

CK505_XTAL_OUT_R

XTAL

CLK_XTAL

CLK_XTAL

XTAL

CK505_XTAL_OUT

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_SMC

HDA_55S

AUD_SPKR_OUTLO1R_POUT

HDA

AUD_SPKR_OUTLO1R_NOUT

HDA

HDA_55S

PCH_55S

COMP_PCH

PCH_XCLK_RCOMP

PCH_55S

ITP_PCH

XDP_PCH_TCK

PCH_55S

COMP_PCH

PCH_SATA3RBIAS

SPI

SPI_MISO

SPI_55S

PCH_CLK32K_RTCX1

CLK_XTAL

XTAL

PCH_CLK32K_RTCX2

CLK_XTAL

XTAL

XTAL

CLK_XTAL

PCH_CLK32K_RTCX2

XTAL

CLK_XTAL

PCH_CLK32K_RTCX1

CLK_XTAL

XTAL

PCH_CLK32K_RTCX2_R

XTAL

CLK_XTAL

PCH_CLK32K_RTCX1_R

HDA_55S

AUD_SPKR_OUTLO2L_NOUT

HDA

HDA_55S

HDA

HDA_SDOUT

HDA

HDA_55S

HDA_BIT_CLK_R

HDA_55S

HDA

HDA_BIT_CLK

XTAL

CLK_XTAL

PCH_CLK25M_XTALIN

AUD_SPKR_OUTLO2R_POUT

HDA

HDA_55S

SPI_CLK_1_R

SPI_55S

SPI

HDA

HDA_55S

HDA_RST_L

HDA

HDA_SYNC

HDA_55S

HDA_55S

HDA

AUD_SDI_R

HDA

AUD_SPDIF_OUT

HDA_55S

HDA

AUD_SPKR_OUTLO1L_NOUT

HDA_55S

AUD_SPKR_OUTLO1L_POUT

HDA

PCH_55S

COMP_PCH

PCH_SATA3COMP

XTAL

CLK_XTAL

PCH_CLK25M_XTALOUT

CLK_XTAL

XTAL

PCH_CLK25M_XTALIN_R

CLK_XTAL

XTAL

PCH_CLK25M_XTALOUT_R

HDA_55S

AUD_SPKR_OUTLO2R_NOUT

HDA

HDA_55S

HDA

AUD_SPKR_OUTLO2L_POUT

XTAL

CLK_XTAL

USB_HUB2_XTAL1

XTAL

CLK_XTAL

USB_HUB2_XTAL2

HDA

AUD_SPDIF_CHIP

CLK_PCH

CLK_PCH_55S

PCH_CLK14P3M_REFCLK

XTAL

CLK_XTAL

USB_HUB1_XTAL1

COMP_PCH

PCH_55S

PCH_USB_RBIAS

PCH_55S

PCH_SATAICOMP

COMP_PCH

PCH_55S

XDP_PCH_TDO

ITP_PCH

PCH_55S

ITP_PCH

XDP_PCH_TMS

XTAL

CLK_XTAL

USB_HUB1_XTAL2

PCH_55S

COMP_PCH

PCH_DMI_COMP

COMP_PCH

PCH_55S

USB_HUB1_RBIAS

PCH_55S

COMP_PCH

USB_HUB2_RBIAS

PM

AUD_SPDIF_IN

SPI

SPI_55S

SPI_CS0_L

103 OF 110

11.1.0

051-8115

91 OF 98

20

20

20

20

21

18 46 48

18 46 48

20 27

18 27

15 18 25 84

25 27

63

27

15 21 36

36

64 97

21 25

36 37

64 97

64 97

64 97

64 97

43 63

20 25 82 97

18 61 83

15 21 80

15 18

20 84

20 25

15 18 36

15 21 80

6

15 21

27 48

9

19 97

9

46 97

20 27

18

18

18

18 48

55

55

18 48 55

18 48 55

55

48

21 48

48

48 55

48

18

18 56

18

48

20 27

18

19

18 25

26

26

26

27 46

98

98

18

18 25

18

18 48 55

18 27 91

18 27 91

18 27 91

18 27 91

27

27

98

15 18 56

18

18 56

18 27 79

98

18

18 56

18 56

56

56 60

98

98

18

18 27

27

27

98

98

35

35

56

18 26

34

20

18

18 25

18 25

34

19

34

35

60 83 97

48

www.vinafix.vn

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NET_TYPE

UNUSED FW NETS PHYSICAL PROPERTIES

ELECTRICAL_CONSTRAINT_SET

FireWire Net Properties

NET_TYPE

PHYSICAL

SPACING

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

SOURCE:BROADCOM 5764M-DS04-RDS. PAGE 38

CAESAR II (ETHERNET) CONSTRAINTS

FireWire Interface Constraints

PHYSICAL

USB 2.0 Interface Constraints

CAESAR II (ETHERNET) CONSTRAINTS

CAESAR IV (SD) CONSTRAINTS

I243

I244

I245

I246

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259
I260

I261

I262

I263

I264

I265
I266

I267
I268

I269

I270
I271

I272

I273

I274

I275

I276
I277

I278
I279

I280

I281

I282

I283
I284

I285

I286

I287

I288
I289

I290
I291

USB/ENET/SD/FW/AUD CONSTRAINTS

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

?*

=STANDARD

ENET_SE

ENET_100D

=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

?*

50MIL_SPACING

1.27 MM

* ?

0.6 MMENET_DIFF

?*

ENET_2OTHER

=50MIL_SPACING

?*

ENET_DIFF2DIFF

=3:1_SPACING

*

ENET_DIFF ENET_DIFF

ENET_DIFF2DIFF

**

ENET_2OTHERENET_DIFF_T

=50_OHM_SE =50_OHM_SE

=STANDARD=50_OHM_SE

SD_50S

*

=STANDARD

=50_OHM_SE

=110_OHM_DIFF

FW_110D

*

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

*

=3:1_SPACING

FW_TP

?

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

USB_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=3:1_SPACING

SD

?*

*

0.3 MM

?

ENET_MII

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE =50_OHM_SE

*

=STANDARD

ENET_50S

=STANDARD

=3:1_SPACING

* ?

USB

=4x_DIELECTRIC

?

TOP,BOTTOM

USB

ENET_RDAC

ENET_SE

ENET_50S
CLK_PCH_55S

XTAL

ENET_CLK25M_XTALI

USB

USB_90D

USB_PORT1_P

ENET_100D

ENETCONN_MDI_T_N<3..0>

ENET_DIFF_T

SD

SD_50S

ENET_SD_CMD

USB_90D

USB

USB_CAMERA_N

USB_IR_L_P

USB_90D

USB

USB_90D

USB

USB_EXTA_P

USB

USB_90D

USB_EXTA_N

USB

USB_90D

USB_PORT0_P

USB

USB_90D

USB_EXTB_N

USB

USB_90D

USB_EXTC_N

USB_CAMERA_L_P

USB_90D

USB

USB_HUB2_UP_N

USB_90D

USB

USB_HUB2_UP_P

USB

USB_90D

SD

SD_50S

SDCONN_CLK

USB_90D

USB

USB_HUB1_UP_N

USB_90D

USB

USB_SDCARD_P

USB_90D

USB

USB_CAMERA_L_N

USB

USB_90D

USB_BT_P

USB

USB_90D

USB_BT_L_P

USB

USB_IR_P

USB_90D

USB

USB_IR_N

USB_90D

PM

SD_50S

SDCONN_DETECT_BUF_L

CLK_PCH_55S

XTAL

ENET_CLK25M_XTALO_R

CLK_PCH_55S

ENET_CLK25M_XTALO

XTAL

ENET_100D

ENETCONN_MDI_T_P<3..0>

ENET_DIFF_T

ENET_MIIPCIE_85D

PCIE_ENET_R2D_P

ENET_MIIPCIE_85D

PCIE_ENET_D2R_P

ENET_MII

PCIE_ENET_D2R_C_N

PCIE_85D

SDCONN_CMD

SD_50S

SD

ENET_MEDIA_SENSE_R

SD

SD_50S

USB_90D

USB

USB_HUB1_UP_P

PM

ENET_MEDIA_SENSE

SD_50S

SD

SD_50S

ENET_SD_CLK

SD

SD_50S

ENET_CR_DATA<7..0>

USB

USB_PORT0_N

USB_90D

USB

USB_90D

USB_EXTB_P

USB

USB_90D

USB_EXTC_P

USB

USB_90D

USB_PORT1_N

USB

USB_90D

USB_PORT2_P

USB

USB_90D

USB_PORT2_N

USB

USB_90D

USB_EXTD_N

USB

USB_90D

USB_EXTD_P

USB

USB_90D

USB_D_MUXED_N

USB

USB_90D

USB_D_MUXED_P

USB_PORT3_P

USB

USB_90D

USB

USB_90D

USB_CAMERA_P

USB_PORT3_N

USB

USB_90D

USB_90D

USB

USB_BT_L_N

ENET_SD_DETECT_L

SD

SD_50S

SDCONN_DATA<7..0>

SD

SD_50S

ENET_MII

PCIE_ENET_D2R_C_P

PCIE_85D

ENET_MII

PCIE_ENET_R2D_C_N

PCIE_85D

ENET_MII

PCIE_ENET_R2D_C_P

PCIE_85D

PCIE_ENET_D2R_N

ENET_MIIPCIE_85D

ENET_MIIPCIE_85D

PCIE_ENET_R2D_N

ENET_DIFFENET_100D

ENETCONN_MDI_N<3..0>

ENET_100D ENET_DIFF

ENETCONN_MDI_P<3..0>

CLK_PCH_55S

XTAL

FW_CLK24P576M_XI

CLK_PCH_55S

XTAL

FW_CLK24P576M_XO_R

XTAL

CLK_PCH_55S

FW_CLK24P576M_XO

FW_110D

FW_TP

FW_PORT0_TPA_P

FW_PORT0_TPB_P

FW_110D

FW_TP

FW_110D

FW_TP

FW_PORT0_TPA_N

FW_P2_TPA_N

FW_110D

FW_TP

FW_110D

FW_TP

FW_P1_TPA_N

FW_TP

FW_110D

FW_P1_TPA_P

FW_TP

FW_110D

FW_P2_TPA_P

FW_P1_TPB_N

FW_TP

FW_110D

FW_P1_TPB_P

FW_110D

FW_TP

FW_P2_TPB_P

FW_110D

FW_TP

FW_P2_TPB_N

FW_TP

FW_110D

FW_110D

FW_PORT0_TPB_N

FW_TP

USB_90D

USB

USB_SDCARD_N

USB_IR_L_N

USB

USB_90D

USB

USB_90D

USB_BT_N

USB_90D

USB

USB_SDCARD_L_P

USB

USB_90D

USB_SDCARD_L_N

USB_90D

USB

USB_HUB2UNUSED_N

USB

USB_90D

USB_HUB2UNUSED_P

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37

36 37

43

38

37

20 44

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34 43

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43

35 43

34 43

44 98

20 35

20 35

37 45

20 34

34 44

44 98

35 44

44 98

34 44

34 44

97

36

36 37

38

37

18 37

37

37 45

20 34

15 18 37

37

37

43

35 43

34 43

43

43

43

35 43

35 43

43

43

43

20 44

43

44 98

37

37 45

37

18 37

18 37

18 37

37

37 38

37 38

39

39

39

40 41

40 41

40 41

39 40

39 40

39 40

39 40

39 40

39 40

39 40

39 40

40 41

34 44

44 98

35 44

44

44

35

35

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LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

B

8 7 5 4 2 1

PAIRS SHOULD BE WITHIN 100 MILS OF CLOCK LENGTH.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

GRAPHICS CONSTRAINTS

USE 5X_DIELECTRIC IN K62

SPACING

PHYSICAL

NET_TYPE

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

ASSINGED IN CONT. MGR.

ELECTRICAL_CONSTRAINT_SET

UNUSED VIDEO NET PHYSICAL CONSTRAINTS

I153
I154

I169
I170

I171

I172
I173

I174

I185
I186

I187

I188

I191
I192
I193
I194
I195
I196

I197

I198

I199
I200
I201
I202
I203
I204
I205
I206

I207
I208
I209
I210

I211
I212

SYNC_DATE=01/06/2011

GRAPHICS CONSTRAINTS

SYNC_MASTER=K62

=85_OHM_DIFF

=85_OHM_DIFF

DP_85D

=85_OHM_DIFF

=85_OHM_DIFF

0.08MM

*

=85_OHM_DIFF

DISPLAYPORT

* ?

=3:1_SPACING

DP_85D

MXM_LVDS_B_CLK_N

DISPLAYPORT

DP_85D

MXM_LVDS_B_CLK_P

DISPLAYPORT

DP_85D

MXM_LVDS_A_CLK_N

DISPLAYPORT

DP_85D

MXM_DP_B_ML_P<3..0>

DISPLAYPORT

DP_EXTB_AUXCH_C_N

DP_85D

DISPLAYPORT

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH_C_P

DP_EXTA_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH_N

DISPLAYPORT

DP_85D

DP_EXTA_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_EXTB_ML_P<3..0>

DP_85D

DISPLAYPORT

MXM_DP_D_AUX_N

DP_85D

DISPLAYPORT

MXM_DP_C_AUX_R_N

DP_85D

DISPLAYPORT

MXM_DP_C_AUX_R_P

MXM_DP_C_AUX_N

DISPLAYPORT

DP_85D

MXM_DP_C_AUX_P

DISPLAYPORT

DP_85D

DP_85D

DISPLAYPORT

MXM_DP_C_ML_N<3..0>

DP_85D

DISPLAYPORT

MXM_DP_C_ML_P<3..0>

DP_85D

DISPLAYPORT

MXM_DP_B_AUX_N

DP_85D

DISPLAYPORT

MXM_DP_D_AUX_P

MXM_DP_D_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_85D

DISPLAYPORT

MXM_DP_D_ML_P<3..0>

DP_85D

MXM_DP_B_ML_N<3..0>

DISPLAYPORT

DP_85D

MXM_DP_B_AUX_P

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_EXTB_AUXCH_N

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH_P

DISPLAYPORT

DP_85D

DP_EXTA_ML_N<3..0>

DP_85D

DP_INTCONN_AUXCH_C_N

DISPLAYPORT

DISPLAYPORT

DP_85D

DP_INTPNL_AUX_N

DP_85D

DISPLAYPORT

DP_EXTA_ML_C_N<3..0>

DISPLAYPORT

MXM_LVDS_B_DATA_N<3..0>

DP_85D

DISPLAYPORT

DP_85D

MXM_LVDS_B_DATA_P<3..0>

DISPLAYPORT

MXM_LVDS_A_DATA_P<3..0>

DP_85D

MXM_LVDS_A_DATA_N<3..0>

DP_85D

DISPLAYPORT

DP_85D

MXM_LVDS_A_CLK_P

DISPLAYPORT

DP_EXTB_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_85D

DP_EXTB_ML_C_N<3..0>

DISPLAYPORT

DP_INTPNL_ML_N<3..0>

DP_85D

DISPLAYPORT

DP_85D

DP_EXTB_AUXCH_P

DP_85D

DISPLAYPORT

DP_EXTB_ML_N<3..0>

DP_85D

DISPLAYPORT

DP_INTCONN_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_INTCONN_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DP_INTCONN_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_INTPNL_ML_P<3..0>

DP_85D

DP_INTPNL_AUX_P

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_EXTB_AUXCH_C_P

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75 78

75 78

75 78

75 78
75 78

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84

83

81 83

78 84

76 78

76 78

76 78

76 78

76 78

81 83

83
83

83

81 83

81 83

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MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ELECTRICAL_CONSTRAINT_SET

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

SMBus Interface Constraints

PHYSICAL

SMC VOLTAGE/CURRENT NET PROPERTIES

SMC THERMAL NET PROPERTIES

SMC SMBus Net Properties

I206

I207

I208

I209
I210

I211

I212

I213
I214

I215

I216

I217

I218

I219

I220

I221

I222
I223

I224

I225

I226

I227

I228

I229
I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244
I245

I246

I247
I248

I251

I252

I253

I254

I255

I256

I264

I265

I266

I267

I268
I269

SMC Constraints

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

POWER

PWR_P2MM

THERMAL

*

THERMAL

*

GND

GND_P2MM

THERMAL

*

4:1_SPACING

*

THERM_DIFF

*

1:1_DIFFPAIR

SNS_DIFF

1:1_DIFFPAIR

*

?

=2x_DIELECTRIC

*

SMB

=55_OHM_SE=55_OHM_SE

SMB_55S

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

=STANDARD

THERM_DIFF

THERMAL

SNS_T1_7_N

SMB_55S

SMB

I2C_VREFMRGN_DIMMA_SDA

I2C_TCON_SCL

SMB

SMB_55S

I2C_TCON_SDA

SMB

SMB_55S

SMB_55S

SMB

SMB_BLC_TCON_SCL

SMB

SMB_55S

SMB_BLC_TCON_SDA

SMB_55S

SMB

SMB_BLC_PCH_SDA_R

SMB_55S

SMB

SMB_BLC_PCH_SCL_R

SMBUS_SMC_BSA_SCL

SMB

SMB_55S

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMB_55S

SMBUS_SMC_0_S0_SDA

SMB

SMB

SMB_55S

SMBUS_SMC_A_S3_SCL

SMB_55S

SMB

SML_PCH_1_DATA

SMB_55S

SMB

I2C_VREFMRGN_DIMMB_SCL

SMB_55S

SMB

SML_PCH_1_CLK

CLK_XTAL

SMC_EXTAL

XTAL

CLK_XTAL

SMC_XTAL

XTAL

SMB_55S

SMB

I2C_VREFMRGN_DIMMA_SCL

THERMAL

THERM_DIFF

SNS_T1_1_P

THERMAL

HDD_OOB_TEMP_FB

SMC_VCORE_VSENSE

THERMAL

THERMAL

SMC_VCORE_ISENSE

SMC_GPU_VSENSE

THERMAL

SMC_VAXG_ISENSE

THERMAL

THERMAL

SMC_CPU_1V5_ISENSE_R

THERMAL

SMC_CPU_1V5_VSENSE

SMC_VAXG_VSENSE

THERMAL

SMC_1V05_ISENSE

THERMAL

GND_SMC_AVSS

THERMAL

SMC_PCH_1V05_VSENSE

THERMAL

THERMAL

GND_SMC_AVSS

THERMAL

SMC_CPU_1V5_ISENSE

SNS_1V05_PCH_N

THERM_DIFF

THERMAL

THERMAL

SNS_1V05_PCH_P

THERM_DIFF

THERMAL

THERM_DIFF

SNS_VCCSA_N

THERMAL

THERM_DIFF

SNS_CPU_1V5_N

THERM_DIFF

THERMAL

SNS_CPU_1V5_P

THERMAL

SNS_DIFF

VR_ISNS_1V05_N

SNS_DIFF

VR_ISNS_VAXG_N

THERMAL

SNS_DIFF

VR_ISNS_VAXG_P

THERMAL

THERMAL

SMC_VCCSA_VSENSE

THERMAL

SMC_VCCSA_ISENSE_R

SMC_VCCSA_ISENSE

THERMAL

THERMAL

GND_SMC_AVSS

THERMAL

SMC_DIMM_VSENSE

SMC_DIMM_ISENSE

THERMAL

SMC_DIMM_1V5_R

THERMAL

SMC_CPU_VSENSE

THERMAL

SMC_1V05_VSENSE

THERMAL

THERMAL

THERM_DIFF

SNS_VCCSA_P

SNS_I_MXM_N

THERM_DIFF

THERMAL

SNS_DIFF

VR_ISNS_1V05_P

THERMAL

SNS_DIFF

THERMAL

VR_ISNS_VCORE_N

THERMAL

SNS_DIFF

VR_ISNS_VCORE_P

THERM_DIFF

THERMAL

SNS_DIMM_1V5_N

SNS_DIMM_1V5_P

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

SNS_I_MXM_P

THERMAL

GND_SMC_AVSS

SMC_PCH_1V05_ISENSE

THERMAL

SMBUS_SMC_A_S3_SDA

SMB_55S

SMB

SMBUS_SMC_B_S0_SCL

SMB_55S

SMB
SMB

SMB_55S

SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL

SMB

SMB_55S

THERM_DIFF

THERMAL

SNS_T2_DP2

THERMAL

SNS_T1_1_N

THERM_DIFF

THERMAL

THERM_DIFF

SNS_T2_DN2

THERMAL

THERM_DIFF

SNS_T1_2_P

THERM_DIFF

THERMAL

SNS_T1_2_N

THERMAL

SNS_T1_3_P

THERM_DIFF

THERM_DIFF

THERMAL

SNS_T1_3_N

THERM_DIFF

THERMAL

SNS_T1_4_P

THERMAL

THERM_DIFF

SNS_T1_5_P

THERM_DIFF

THERMAL

SNS_T1_4_N

THERMAL

THERM_DIFF

SNS_T1_5_N

THERM_DIFF

THERMAL

SNS_T1_6_P

THERM_DIFF

THERMAL

SNS_T1_6_N

THERMAL

THERM_DIFF

SNS_T1_7_P

THERM_DIFF

THERMAL

SNS_CPU_THERMD_P

THERM_DIFF

SNS_LCD_H_P

THERMAL

THERMAL

THERM_DIFF

SNS_CPU_THERMD_N

THERM_DIFF

THERMAL

SNS_ODD_P

SNS_LCD_H_N

THERM_DIFF

THERMAL

THERMAL

THERM_DIFF

SNS_ODD_N
SNS_CPU_H_P

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

SNS_CPU_H_N

SNS_SKIN_RIGHT_P

THERM_DIFF

THERMAL

SNS_SKIN_RIGHT_N

THERM_DIFF

THERMAL

SNS_SKIN_LEFT_P

THERMAL

THERM_DIFF

SNS_SKIN_LEFT_N

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

SNS_AMB_P

THERM_DIFF

THERMAL

SNS_AMB_N

THERM_DIFF

THERMAL

SNS_MXM_P

THERM_DIFF

THERMAL

SNS_MXM_N

THERMAL

HDD_OOB_TEMP_FILT

HDD_OOB_TEMP_R

THERMAL

SMC_HDD_OOB_TEMP

THERMAL

SMC_GPU_ISENSE

THERMAL

THERMAL

GND_SMC_AVSS

SMB

I2C_VREFMRGN_DIMMB_SDA

SMB_55S

SMB_55S

SMB

SML_PCH_0_CLK

SMB_55S

SMB

SML_PCH_0_DATA

SMB

SMB_55S

SMBUS_PCH_DATA

SMB_55S

SMB

SMBUS_PCH_CLK

SMB_55S

SMBUS_SMC_MGMT_SDA

SMB

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

106 OF 110

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81

6

49 81

6

49 81

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49

49

18 49

28

18 49

46 47

46 47

28

52

42

46 50

46 50

46 50

46 50

50

46 50

46 50

46 50

46 47 50 94

46 50

46 47 50 94

46 50

50

50

50

50

50

95

50 95

50 95

46 50

50

46 50

46 47 50 94

46 50

46 50

50

46 50

50

50

95

50 95

50 95

50

50

50

46 47 50 94

46 50

49

49

49

49

52

52

52

52

52

52

52

52

52

52

52

52

52

52

10 52

52

10 52

52 98

52

52 98

52

52

52 98

52 98

44 52 98

44 52 98

52 54 98

52 54 98

52

52

42 51 98

51

46 51

46 50

46 47 50 94

28

18 49

18 49

18 49

18 49

49 94

49 94

49 94

www.vinafix.vn

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

VR CTRL NET PROPERTIES

VOLTAGE

NET_TYPE

PHYSICAL

NET_TYPE

SENSING NET PROPERTIES

VOLTAGE

PHYSICAL

NET_TYPE

VR VID NET PROPERTIES

SPACING

VID LENGTH SKEW < 1-INCH

PULL-UP STUB < 1-INCH

VID LENGTH RANGE< 1 TO 15-INCH

NET_TYPE

PHYSICAL PHYSICAL

SPACING

SPACING

NET_TYPE

NET_TYPE

SPACING

PHYSICAL

PHYSICAL

SPACING

VR CTRL NET PROPERTIES

POWER NET PROPERTIES

SPACING

POWER NET PROPERTIES

I128
I129
I130

I132
I133
I134

I136
I137

I139
I140

I141
I142
I143
I144

I148
I149

I151

I152
I153

I154

I155
I156

I158

I159

I160

I162

I163

I164
I166

I171

I172

I173

I174

I175

I177

I178

I179

I182

I184

I185

I188

I193

I194

I198

I207
I209
I212

I216
I218

I221

I223

I224

I231

I234

I235

I236

I237

I238

I239

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251
I252
I253
I255

I257

I258

I259

I260

I262

I263
I266

I267

I268

I270

I278
I338
I339

I341

I343
I344
I345

I347
I348
I349
I350

I351

I352

I353

I354

I357
I359

I360

I361

I363

I365
I367
I368
I370

I371
I374
I376
I377

I387
I388
I389
I390

I393

I394

I395

I396

I398
I399

I401

I402

I403

I404

I405

I406

I408
I412

I413

I419

I437

I439

I441

I442

I443

I444

I450

I451

I452

I453

I454

I455

I457

I458

I459
I461

I462
I463
I464

I466

I491
I492
I521

I536

I544

I545

I546

I557

I56

I563
I564

I57

I575

I577

I58

I587

I59

I594

I595

I596

I604

I606

I607
I608

I613

I615
I616

I619
I620

I621

I622

I623

I624

I625

I626

I627

I628

I629

I630

I631

I632
I633

I634

I635

I636

I637
I638

I639

I641

I642

I644

I645

I646

I647

I649

I650

I651
I652

I653

I654

I655

I656

I657

I658

I659
I660
I661
I662

I663

I664

I665

I666

I667

I668

I669

I670

I671

I672
I673

I674

I675
I676

I677

I678

I679

I680

I681

I682

I683
I684

I685
I686

I687

I688

I689

I690
I691
I692
I693

I694

I695

I696

I697
I698
I699
I700

I703

I704

I707

I708

I709

I710

I711

I712

I713

I714

I715

I716

I717

I718
I719

I720
I721

I723

I726
I727

I728

I729

I730

I732

I733

I734

I736

I737

I742

I743
I744

I745

I746

I747

I748

I752

I753

I754

I755

I756

I758
I759

I760

I762

I763

I764

I765

I766

I767

I768

I769

I770

I771
I772
I773

I774
I775

I776

I777

I778
I779

I780
I781

I782

I783

I784

I785

I786

I787

I788
I789
I790

I791

I792

I794

I796

I797

I798
I799

I800
I801

I802
I803

I805

I808

I810

I816
I821

I824

I825

I826

I827

I828

I830
I831

I832

I833
I834
I835
I836
I837
I838

I839

*

SWITCHNODE

BGA_P2MMBGA_P1MM

?*

VR_CTL 0.35MM

SWITCHNODESWITCHNODE

BGA_P1MM BGA_P2MM

* *

SWITCHNODE SWITCHNODE

=4X_DIELECTRIC

* ?

VR_CTL_VIDS

GND

*

6:1_SPACING

SWITCHNODE

BGA_P1MM

GND

SWITCHNODE

BGA_P2MM

VID_PHY

50_OHM_SE

*

POWER

6:1_SPACING

*

SWITCHNODE

BGA_P2MM

SWITCHNODE POWER

BGA_P1MM

SYNC_MASTER=K62

SYNC_DATE=01/06/2011

POWER CONSTRAINTS

SWITCHNODE

VR_CPU_PHASE3

POWER

1.5V

USB_HUB1_VDD1V8

1.8V

POWERPOWER

PP3V3R1V8_ENET_LR_OUT_REG

POWER

1.8V

POWER

USB_HUB1_VDDPLL3V3

3.3V

POWER POWER

3.3V

PPVBAT_G3_SYSCLK_R

POWERPOWER

USB_HUB1_VDDA3V3

POWERPOWER

3.3V

PP3V3R1V5_PCH_VCCSUSHDA

POWERPOWER

3.3V

SWITCHNODE

ENET_SR_LX

POWER

1.2V

3.3V

POWER

PP3V3_S0_SW_SD_PWR

POWER

PP3V3_S0

POWER POWER

3.3V

POWER

12V

PP12V_SLG1

POWER

POWER

USB_HUB2_VDD1V8PLL

1.8V

POWER

1.8V

POWER

PP1V8_S0

POWER

1.8V

POWER

USB_HUB1_VDD1V8PLL

POWER

PP3V3_S0_CK505_F

3.3V

POWER POWER

PP3V3_S0_HS_F

POWER POWER

3.3V

PP12V_S0_MXM

POWER

12V

POWER

PPVDDIO_25M_A

POWER

1.05V

PPVDDIO_25M_C

POWER

3.3V

POWERPOWER

PP5V_S5_PCH_V5REFSUS

5V

5V

PP5V_USB_PORT0

POWERPOWER

POWER

5V

PP5V_USB_PORT0_F

POWER
POWER

PP5V_USB_PORT1

5V

POWER

PP5V_USB_PORT1_F

POWERPOWER

5V

PP5V_USB_PORT3

POWER POWER

5V
5V

POWER POWER

PP5V_USB_PORT3_F

PP5V_USB_PORT2

5V

POWER POWER

3V3R2V9_DPAPWR_ADJ

VR_CTL_PHY

PM

VR_CTL_PHY

VR_CPU_DRV2_LGATE

VR_CONTROL

VR_CTL_PHY

VR_CONTROL

VR_CPU_DRV3_BOOT

VR_CTL_PHY

VR_CTL

VR_CPU_DRV3_GDSEL

VR_CONTROL

VR_CPU_DRV3_UGATE

VR_CTL_PHY

VR_CPU_DRV4_BOOT

VR_CONTROL

VR_CTL_PHY

VR_CPU_DRV4_GDSEL

VR_CTL

VR_CTL_PHY

VR_CONTROL

VR_CPU_DRV4_LGATE

VR_CTL_PHY

VR_CONTROLVR_CTL_PHY

VR_CPU_DRV4_UGATE

VR_CONTROL

VR_CTL_PHY

VR_AXG_DRV1_BOOT

VR_CTL

VR_AXG_DRV1_UGATE_R

VR_CTL_PHY

VR_CTL_PHY

VR_CTL

CPU_VCCSA_SENSE

VR_CTL_PHY

VCCSA_CRL

VR_CTL

VR_CPU_FB_RC

VR_CTL_PHY

VR_CTL

VR_CTL_PHY

VR_CTL

VR_CPU_SUTH

VR_CPU_RAMP_ADJ

VR_CTL

VR_CTL_PHY

VR_CPU_FB

VR_CTL

VR_CTL_PHY

VR_CPU_VSNS_R_N

SNS_DIFF

VR_CPU_RGND

SNS_DIFF

VR_CTL_PHY

VR_CONTROL

VR_AXG_DRV1_LGATE

SNS_DIFF

VR_AXG_RGND

1.8V

POWER

PP1V8R1V5_S0_PCH_VCCVRM_F

POWER

P5VS3_REG_PHASE

POWER5VSWITCHNODE

VR_AXG_PHASE1

SWITCHNODE

1.5V

POWER

SWITCHNODE

P1V05_REG_PHASE

1.05V

POWER

VR_ISNS_1V05_N

THERMAL

SNS_DIFF

SNS_DIFF

VR_AXG_ISNS_P

THERMAL

SNS_DIFF

VR_AXG_ISNS_N

THERMAL

SNS_DIFF

THERMAL

VR_AXG_ISNS_R_N

ENET_3V3_S3_SR_IN

POWER

3.3V

SWITCHNODE

1.5V

POWER

DDR_REG_PHASE

SWITCHNODE

PP0V75_S3_MEM_VREFCA_A

POWER POWER

0.75V

PP0V75_S3_MEM_VREFDQ_A

0.75V

POWERPOWER

3.3V

PP3V3_S3

POWERPOWER

3.3V

POWERPOWER

PP3V3_S3_ENET_PHY_AVDDH

3.3V

POWERPOWER

ENET_XTALVDDH

3.3V

POWERPOWER

PP3V3_S5_REG_R

PPVOUT_S0_PCH_DCPSST

3.3V

POWERPOWER
POWER

PPVOUT_PCH_DCPSUSBYP

3.3V

POWER

POWER

3.3V

POWER

PPVOUT_G3_PCH_DCPRTC

3.3V

POWERPOWER

PPVBATT_G3_RTC

POWER

3.3V

POWER

PP3V3_AUDIO_SPDIF_JACK

3.3V

POWERPOWER

PP3V3_FW_FWPHY_VP25

POWER

3.3V

POWER

PP3V3_S0_T29

3.3V

POWER

POWER

PP3V3_SW_DPAPWR

4.5V

4V5_REG_IN

POWER POWER

4.5V

POWER POWER

PP4V5_AUDIO_ANALOG

POWER

4.5V

POWER

PP5V_AUDIO_HPAMP

VR_CPU_VSEN

SNS_DIFF

VR_CPU_VSNS_R_P

SNS_DIFF

VR_CPU_VSNS_XW_N

SNS_DIFF

CPU_VCCIO_SENSE_P

SNS_DIFF

CPU_VCCIO_SENSE_N

SNS_DIFF

P1V05S0_RTN

SNS_DIFF

VR_CTL_PHY

P1V05S0_UGATE

SWITCHNODE

VR_CTL_PHY

P1V05S0_LGATE

SWITCHNODE

P1V05S0_BOOT_R

VR_CTL_PHY

VR_CTL

VR_CPU_DRV1_UVCC

12V

POWERPOWER

USB_HUB2_VDDPLL3V3

POWER POWER

3.3V

USB_HUB2_VDDA3V3

POWER

3.3V

POWER

PP3V3_S3_SDCARD_FLT

POWER POWER

3.3V

12V

POWER

PP12V_S0_CPU_FLTRD

POWER

POWER

3.3V

POWER

PP3V3_G3H_RTC

POWER

3.3V

PP3V3_G3H_AVREF_SMC

POWER

POWER

POWER

PP3V3_SW_DPBPWR

3.3V

POWERPOWER

3.4V

PP3V3_G3H_SMC_AVCC

CPU_VAXG_SENSE_N

SNS_DIFF

SNS_DIFF

VR_AXG_VSNS_R_N

POWER

SWITCHNODE

1.5V

VR_CPU_PHASE1

POWER

PP3V3R12V_SW_DPAPWR_1

12V

POWER

3.42V

POWER POWER

PP3V42_G3H

PP5V_RAMP_VREG

5V

POWER POWER

PP5V_S0

5V

POWER POWER

POWER5VPOWER

PP5V_S0_PCH_V5REF

1.05V

POWER POWER

PPVOUT_S5_PCH_DCPSUS

5V_S0_P1V05REG_VIN

5V

POWERPOWER

5V

POWERPOWER

PP5V_S0_CPU_VCORE_VCC

POWER

1.05V

POWER

PP1V05_S0

POWER

1.05V

PP1V05_S0_PCH_VCCAPLL_EXP_F

POWER

PP1V05_S0_PCH_VCCAPLLDMI2_F

POWER POWER

1.05V

1.1V

POWER POWER

PPVCORE_S0_AXG_REGOUT

PPVCORE_S0_CPU_REG3

POWER POWER

1.1V

POWER

1.5V

POWER

PP1V5_S0_CPU_SNS

VR_CTL_PHY

VR_CTL

VCCSA_CNTRL_INPUT2_R

T29BST_FBX

VR_CTL

VR_CTL_PHY

VR_CPU_PWM2_R

VR_CTL

VR_CTL_PHY

VR_CTL

VR_CPU_PWM3

VR_CTL_PHY

THERMAL

SNS_DIFF

VR_AXG_ISNS_R_P

VR_CONTROL

VR_CTL_PHY

VR_CPU_BOOT2_RC

VR_CTL_PHY

VR_CPU_BOOT4_RC

VR_CTL

VR_CPU_DRV1_BOOT

VR_CTL_PHY VR_CONTROL
VR_CTL_PHY

VR_CTL

VR_CPU_DRV1_GDSEL

VR_ISNS_VAXG_P

SNS_DIFF

THERMAL

VR_ISNS_VAXG_N

SNS_DIFF

THERMAL

0.75V

POWER

PP0V75_S3_MEM_VREFDQ_B

POWER

VR_CTL_PHY

VR_CTL

VR_AXG_IMON

VR_CPU_PH1_SNUB

VR_CTL_PHY

SWITCHNODE

VR_CPU_PWM4

VR_CTL_PHY

VR_CTL

VR_RSET

VR_CTL_PHY

VR_CTL

SWITCHNODE

VR_CPU_PH3_SNUB

VR_CTL_PHY

VR_CTL_PHY

VR_CTL

VR_CPU_PWM1
VR_CPU_PWM1_R

VR_CTL_PHY

VR_CTL

VR_CPU_PWM4_R

VR_CTL

VR_CTL_PHY

VR_EN_PWR_OVP

VR_CTL

VR_CTL_PHY

VR_CONTROL

VR_CPU_BOOT3_RC

VR_CTL_PHY

VR_AXG_BOOT1_RC

VR_CTL_PHY

VR_CONTROL

VR_CPU_DRV1_LGATE

VR_CTL_PHY

VR_CONTROL

VCCSA_CNTRL_INPUT2_R

VR_CTL

VR_CTL_PHY

VR_CTL

P5VS3_REG_FSET2

VR_CTL_PHY

P5VS3_REG_OCSET

VR_CTL

VR_CTL_PHY

P5VS3_REG_ISEN

VR_CTL_PHY

VR_CTL

PPVCORE_S0_CPU_REG1

POWER

1.1V

POWER

PP1V2_S3_ENET_PHY_PCIEPLL

POWER POWER

1.2V

VR_CPU_PWM2

VR_CTL

VR_CTL_PHY

VR_CPU_PWM3_R

VR_CTL

VR_CTL_PHY

VR_CPU_PH4_SNUB

VR_CTL_PHY

SWITCHNODE

VR_CPU_HFREQ_COMP

VR_CTL_PHY

VR_CTL

VR_CTL

VR_CPU_IMON_R

VR_CTL_PHY

VR_CPU_PSICOMP2

VR_CTL_PHY

VR_CTL

VR_CPU_FDVID

VR_CTL_PHY

VR_CTL

VR_CPU_SW_FREQ

VR_CTL_PHY

VR_CTL

VR_CTL_PHY VR_CONTROL

VR_AXG_DRV1_UGATE

VR_CTL_PHY

VR_CTL

VR_CPU_DRV2_GDSEL

POWERPOWER

12V

FW_PORT0_VP

VR_CTL

VR_CTL_PHY

DDR_REG_UGATE_R

VR_CTL_PHY

P1V05_IMON

VR_CTL

VR_CTL_PHY

VR_CTL

VR_AXG_FB

VR_CTL_PHY

VR_CTL

VR_SEN_R1

P1V05S0_ICOMP

VR_CTL

VR_CTL_PHY

VR_CTL

VR_CTL_PHY

P1V05S0_VO

VR_CTL_PHY

VR_CTL

P1V05S0_VDIF_C

P1V05S0_COMP_C

VR_CTL

VR_CTL_PHY

VR_CPU_ISNS2_R_N

THERMAL

SNS_DIFF

VR_CTL

DDR_REG_VDDQSNS

VR_CTL_PHY

VR_CTL

DDR_REG_CS

VR_CTL_PHY
VR_CTL_PHY

VR_CTL

DDR_REG_FB

VR_CTL_PHY

VR_CONTROL

DDR_REG_LGATE

VR_CONTROL

DDR_REG_UGATE

VR_CTL_PHY

VR_CONTROL

DDR_REG_BOOT

VR_CTL_PHY

VR_CPU_PH2_SNUB

VR_CTL_PHY

SWITCHNODE

VR_CONTROL

DDR_REG_BOOT_R

VR_CTL_PHY

VR_ISNS_1V05_P

THERMAL

SNS_DIFF

P1V05S0_VSEN

SNS_DIFF

SNS_DIFF

CPU_VCC_SENSE_P

VR_CTL_PHY

SWITCHNODE

VR_AXG_PH1_SNUB

P1V05S0_FB

VR_CTL_PHY

VR_CTL
VR_CTL

VR_CTL_PHY

P1V05S0_PHASE_L
P1V05S0_VW

VR_CTL

VR_CTL_PHY

P1V05_S0_VDIFF

VR_CTL

VR_CTL_PHY

P1V05S0_OCSET

VR_CTL

VR_CTL_PHY

P1V05S0_COMP

VR_CTL

VR_CTL_PHY

P1V05S0_BOOT

VR_CTL

VR_CTL_PHY

P1V05S0_SNUBBER

VR_CTL_PHY

VR_CTL

VID_PHY

CPU_VIDSCLK

VR_CTL_VIDS

CPU_VIDALERT_L

VR_CTL_VIDS

VID_PHY
VID_PHY

CPU_VIDSOUT

VR_CTL_VIDS

VID_PHY

VR_CTL_VIDS

CPU_VIDSOUT_R

VID_PHY

VR_CTL_VIDS

CPU_VIDALERT_L_R

VR_CTL_VIDS

VID_PHY

CPU_VIDSCLK_R

SNS_DIFF

CPU_VAXG_SENSE_P

0.75V

PP0V75_S3_MEM_VREFCA_B

POWER POWER

POWERPOWER

1.05V

PP1V05_S0_CK505_F

PPVCORE_S0_CPU

1.1V

POWER POWER

POWER POWER

1.5V

PP1V5_S3

1.5V

POWER POWER

PP1V5_S3_MEM

12V

POWER

PP12V_S5

POWER

POWER

PP1V0_S0_FW_VDD

POWER

1.0V

VR_CTL

VR_CTL_PHY

P1V8_REG_VFB

P3V3S5_REG_BOOT

VR_CONTROL

VR_CTL_PHY

VR_CONTROL

VR_CTL_PHY

P3V3S5_REG_BOOT_R

VR_CTL_PHY

P1V8_REG_SYNC

VR_CTL

VR_CTL_PHY

P3V3S5_REG_FB

VR_CTL

P3V3S5_REG_ISEN

VR_CTL

VR_CTL_PHY

VR_CONTROLVR_CTL_PHY

P3V3S5_REG_VOUT1

VR_CTL

DDR_REG_PHASE_R

VR_CTL_PHY

VR_CTL_PHY

VR_CTL

DDR_REG_VTTSNS

VR_CTL

VR_CPU_COMP

VR_CTL_PHY

VR_AXG_TM

VR_CTL_PHY

VR_CTL

VR_CTL_PHY

VR_AXG_PWM_R

VR_CTL

VR_AXG_PWM

VR_CTL

VR_CTL_PHY

1.8V

SWITCHNODE

POWER

P1V8_REG_PHASE

SWITCHNODE

P3V3S5_REG_PHASE

3.3V

POWER

12V

PP12V_S0_FAN0_L

POWERPOWER

12V

VR_CPU_DRV3_VCC

POWER POWER

VR_CPU_ISNS2_N

SNS_DIFF

THERMAL

VR_CPU_ISNS1_N

SNS_DIFF

THERMAL

VR_CPU_ISNS2_P

THERMAL

SNS_DIFF

VR_CPU_ISNS1_R_N

THERMAL

SNS_DIFF

VR_CPU_ISNS1_P

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

P1V05S0_ISN

SNS_DIFF

P1V05S0_ISP

THERMAL

SNS_DIFF

THERMAL

VR_CPU_ISNS3_P

SNS_DIFF

THERMAL

VR_CPU_ISNS3_N

THERMAL

SNS_DIFF

VR_CPU_ISNS4_N
VR_CPU_ISNS4_R_N

SNS_DIFF

THERMAL

VR_CPU_ISNS4_P

THERMAL

SNS_DIFF

12V

POWER

PP12V_S0

POWER

12V

PP12V_S0_FAN1_L

POWERPOWER

POWER

12V

PP12V_S0_FAN2_L

POWER

VR_CPU_DRV4_PVCC

POWER POWER

12V

POWER

12V

VR_CPU_DRV4_VCC

POWER

POWERPOWER

P12V_FW_D

12V

POWER

12V

POWER

PPVP_FW_PHY_CPS

POWER POWER

12V

FW_PORT0_VP_F

VR_CPU_DRV4_UVCC

POWER

12V

POWER

VR_CPU_DRV2_UVCC

12V

POWERPOWER

P1V05S0_PHASE

1.05V

POWER

SWITCHNODE

POWERPOWER

P12V_FW_CL

12V

POWER

PP12V_S0_VG_OK

12V

POWER

VR_CPU_DRV1_PVCC

12V

POWERPOWER

VR_CPU_DRV2_PVCC

POWER

12V

POWER

VR_CPU_DRV3_PVCC

POWERPOWER

12V

VR_CPU_DRV3_UVCC

POWERPOWER

12V

POWER

VR_AXG_DRV1_PVCC

12V

POWER

POWERPOWER

12V

PP12v_S0_P1V05_VREG_VIN

SNS_DIFF

CPU_VCC_SENSE_N

VR_CTL_PHY

VR_CPU_DRV2_UGATE

VR_CONTROL

SNS_DIFF

VR_AXG_VSNS_R_P

PP1V2_S3_ENET_PHY_GPHYPLL

1.2V

POWER POWER

PPVCORE_S0_CPU_REG4

POWER

1.1V

POWER

VR_CTL_PHY

VR_CTL

P1V05_REG_VFB

VR_CTL_PHY

VR_CTL

ENET_SR_VFB

VR_CTL

VR_CTL_PHY

P1V05S0_ISP_R

5V_S0_P1V05REG_VDD

POWERPOWER

5V

POWER POWER

PP5V_S3

5V

POWER POWER

PP5V_S3_VREFMRGN_B

5V

POWERPOWER

5V

PP5V_S3_CAMERA_FLT

POWER5VPOWER

PP5V_S3_REG_R

POWER POWER

5V

PP5V_S3_IR_FLT

PP5V_S3_DDR_REG_V5FILT

POWERPOWER

5V

POWERPOWER

0.75V

PPVTT_S0_DDR

PP1V2_S3_ENET_PHY_AVDDL

POWER POWER

1.2V

1.5V

POWERPOWER

PP1V5_S0

POWERPOWER

PPVCORE_S0_CPU_REG2

1.1V

POWER POWER

1.5V

PP1V5_S0_CPU_MEM

VR_CPU_BOOT1_RC

VR_CTL_PHY VR_CONTROL

VR_CTL_PHY

VR_EN_PWR_OVP_R

VR_CTL

VR_CTL

VR_CTL_PHY

VR_AXG_SW_FREQ

THERMAL

SNS_DIFF

VR_CPU_ISNS3_R_N

SWITCHNODE

1.5V

POWER

VR_CPU_PHASE2

1.5V

VR_CPU_PHASE4

SWITCHNODE

POWER

PP1V05_S0_PCH

POWERPOWER

1.05V

POWER

PPVAXG_S0

POWER

1.05V

POWERPOWER

1.0V

PP1V0_FW_FWPHY_AVDD

POWER

12V

POWER

VCCSA_PWR_RC

POWER

12V

POWER

PP12V_S0_BL_R

POWER

12V

POWER

PP12V_S5_FET

12V

POWERPOWER

PP12V_LCD

P12V_FW_R

POWERPOWER

12V

POWER POWER

12V

VR_CPU_DRV2_VCC

12V

POWERPOWER

VR_CPU_DRV1_VCC

POWER

12V

POWER

VR_AXG_DRV1_UVCC

VR_CPU_PSICOMP1

VR_CTL_PHY

VR_CTL

VR_CPU_FB2

VR_CTL_PHY

VR_CTL

VR_CTL

VR_CTL_PHY

VR_AXG_IMON_R

VR_CTL

VR_CTL_PHY

VR_AXG_HFREQ_COMP

VR_CTL_PHY

VR_CTL

VR_SEN_R2

VR_CTL

VR_CTL_PHY

VR_AXG_TCOMP

VR_CTL

VR_CTL_PHY

VR_AXG_COMP

VR_CTL

VR_CTL_PHY

VR_AXG_COMP_RC

VR_CTL

VR_CTL_PHY

VR_SEN_R3

VR_CPU_PSICOMP

VR_CTL

VR_CTL_PHY

VR_CPU_VSNS_XW_P

SNS_DIFF

SNS_DIFF

VR_AXG_VSNS_XW_P

VR_AXG_VSNS_XW_N

SNS_DIFF

SNS_DIFF

VR_AXG_VSEN

SNS_DIFF

VR_ISNS_VCORE_N

THERMAL

POWERPOWER

0.925V

PPVCCSA_S0_CPU

POWER

0.75V

PP0V75_S0

POWER

12V

POWER POWER

PP12V_S5_RSN

POWER

12V

POWER

PP12V_G3H

1.05V

PP1V05_S0_PCH_VCCAPLL_SATA_F

POWERPOWER

1.05V

POWER

PP1V05_S0_PCH_VCCCLKDMI_F

POWER

POWERPOWER

1.8V

USB_HUB2_VDD1V8

PP1V05_S0_PCH_VCCADPLLB_F

POWER

1.05V

POWER

PP1V05_S0_PCH_VCCADPLLA_F

1.05V

POWERPOWER

PPVCORE_S0_AXG_REG1

1.1V

POWER POWER

PP1V05_S0_INPUT_VCCSA

1.05V

POWER POWER

POWER

POWER

1.05V

PP1V05_S0_T29

VR_CTL_PHY

P3V42G3H_FB

VR_CTL

VR_CTL

P3V42G3H_BOOST

VR_CTL_PHY

3.3V

POWERPOWER

PP3V3_S3_ENET_PHY_BIASVDDH

PP3V3_S3_ENET_PHY_XTALVDDH

3.3V

POWERPOWER

PP3V3_S3_MINI_CONN

3.3V

POWER POWER

3.3V

POWER POWER

PP3V3_SMCUSBMUX

VR_ISNS_VCORE_P

SNS_DIFF

THERMAL

VR_CTL_PHY

VR_CPU_DRV1_UGATE

VR_CONTROL

VR_CTL_PHY

VR_CONTROL

VR_CPU_DRV2_BOOT

VR_CTL

VR_CPU_FB_R

VR_CTL_PHY

VR_CPU_IMON

VR_CTL_PHY

VR_CTL

VCCSA_OUT

VR_CTL_PHY

VR_CTL

VCCSA_CNTRL_INPUT2

VR_CTL

VR_CTL_PHY

VCCSA_CNTRL_INPUT1

VR_CTL

VR_CTL_PHY

VR_CONTROL

P5VS3_REG_VOUT2

VR_CTL_PHY

P5VS3_REG_UGATE

VR_CONTROLVR_CTL_PHY

VR_CTL_PHY

P3V3S5_REG_SNUB

VR_CTL

VR_CONTROL

P3V3S5_REG_UGATE

VR_CTL_PHY

VR_CONTROLVR_CTL_PHY

P3V3S5_REG_FSET1

VR_CTL

P3V3S5_REG_OCSET

VR_CTL_PHY

VR_CTL_PHY

P3V3S5_REG_LGATE

VR_CONTROL

P5VS3_REG_LGATE

VR_CONTROL

VR_CTL_PHY

VR_CTL_PHY

VR_CTL

P5VS3_REG_FB

P5VS3_REG_BOOT

VR_CTL_PHY

VR_CONTROL

VR_CTL_PHY

VR_CTL

VCCSA_GATE

VR_CPU_DRV3_LGATE

VR_CONTROL

VR_CTL_PHY

VR_CTL_PHY

VR_CPU_TM

VR_CTL

VCCSA_REF

VR_CTL

VR_CTL_PHY

POWER

3.3V

POWER

PP3V3_S5

1V5_SNUBBER

VR_CTL_PHY

SWITCHNODE

PP5V_USB_PORT2_F

POWER5VPOWER

3.3V

PPVDDIO_25M_B

POWER

VR_CPU_N_PSI

VR_CTL

VR_CTL_PHY

VR_CPU_IAUTO

VR_CTL_PHY

VR_CTL

POWER

PP3V3R12V_SW_DPBPWR_1

12V

POWER

POWER

PP3V3_S0_PCH_VCCA_DAC_F

3.3V

POWER

3.3V

POWER POWER

PP3V3_S3_BT_FLT

PP3V3_S3_ENET_PHY_FET

3.3V

POWER

SWITCHNODE

3.3V

POWER POWER

PPVBATT_G3_RTC_R

3.3V

POWERPOWER

PP3V3_FW_FWPHY_VDDA

5V

POWERPOWER

PP5V_LAMP_VREG

POWER

5V

PP5V_S0_SATA_FET

POWER

POWER

5V

POWER

PP5V_S3_VREFMRGN_A

PP5V_S5

POWER POWER

5V

1.2V

VR_CTL

PP1V2_S3_ENET_INTREG

VR_CTL_PHY

PP1V5_S0_CK505_F

POWER POWER

1.5V

PP1V5_S0_CK505_R

1.5V

POWERPOWER

DDR_REG_CSGND

POWERPOWER

DDR_REG_PGND

POWERPOWER

3.4V

POWER

P3V42G3H_SW

SWITCHNODE

1.5V

PP1V5_S0_DP_R

POWER

POWER

12V

PP3V3R12V_SW_DPAPWR_D

12V

POWER

PP3V3R12V_SW_DPAPWR_R

107 OF 110

11.1.0

051-8115

95 OF 98

66

34

37

34

79

34

22 24

36 37

45

6

35

6

34

26

62

6

79
79

24

43
43
43
43

43
43

43

82 97

66

66
66

66

67

67

13 69

69

65

65

65

65

65

65

67

65

22 24

70

67

94

65 67

65 67

65

37

71

28 30

28 30

6

98

37
37

70

22

22

27

60 98

39
6

78 84

56
56 61
56

65

65

65

13 68

13 68

68

68
68

68

66

35
35

44

65 66 67

18 19 22 27
46 47

46

13 65

65

66

6

58
6

98

24

22

68

65

6

22 24

22 24

67

66

69 95

65
65 66

65

66

66
66

50 94

50 94

28 31

50 65

66

65

66

65 66

65

65

65

66
67

66

69 95

70

70

70

66

37

65 66

65

65

65

65

65

65

67

66

41

71

50 68

65
65

68

68

68

68

65

71

71
71
71
71
71

66

71

94

68

13 65

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68
68
68

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68

68

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68

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13 65
13 65

13

13

13

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68
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65

65

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69

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65

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17 22

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69

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70

70

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39

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42

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www.vinafix.vn

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

T29 BIAS CONSTRAINTS

T29 ELECTRICAL ROUTES

T29 PCI-EXPRESS (SAME RULE AS PCIE)

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

T29 NET PROPERTIES

T29 XTAL CONSTRAINTS

T29 SPI INTERFACE CONSTRAINTS

T29 SMBUS INTERFACE CONSTRAINTS

ELECTRICAL_CONSTRAINT_SET

T29 NET PROPERTIES

GREEN CLOCK CONSTRAINTS

I421
I422

I423

I424

I425
I426

I427

I428

I431

I432

I433

I434
I435
I436

I437

I438

I439
I440

T29 CONSTRAINTS

SYNC_DATE=01/06/2011

SYNC_MASTER=K62

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

*

CLK_25M_55S

*

=55_OHM_SE =55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

T29_55S

?*

T29_COMP

0.2 MM

=2x_DIELECTRIC

* ?

T29_SMB

T29_SMB_55S

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

*

T29_XTAL_100D

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

T29_XTAL

?*

=4X_DIELECTRIC

T29_SPI

0.2 MM

?*

T29

=7X_DIELECTRIC

?

TOP,BOTTOM

T29_SPI_55S

=STANDARD

=55_OHM_SE=55_OHM_SE

*

=STANDARD

=55_OHM_SE=55_OHM_SE

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

T29_90D

*

T29

* ?

=5X_DIELECTRIC

* ?

CLK_25M =5X_DIELECTRIC

T29_COMP

T29_B_BIAS

DP_A_BIAS

T29_COMP

T29_SMB_55S

I2C_T29_SCL

T29_SMB

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_SB

CLK_25M_55S

SYSCLK_CLK25M_ENET

CLK_25M

ENET_CLK25M_XTALI_OSC

CLK_25M

CLK_25M_55S

T29_XTAL_100D

SYSCLK_CLK25M_X2

T29_XTAL

T29_XTAL_100D

SYSCLK_CLK25M_X2_R

T29_XTAL

T29_XTAL_100D

SYSCLK_CLK25M_X1

T29_XTAL

T29_RSENSE

T29_COMP

T29_55S

T29_RBIAS

T29_COMP

T29_55S

T29_COMP

T29_A_BIAS

T29_SMB_55S

I2C_T29_SDA

T29_SMB

SYSCLK_CLK25M_T29_R

CLK_25M_55S

CLK_25M

PCIE_T29_R2D_P<3..0>

PCIE

NO_TEST=TRUE

PCIE_85D

PCIE_T29_R2D_C_P<3..0>

PCIE_85D

NO_TEST=TRUE

PCIE

DP_T29SRC_ML_C_N<3..0>

DP_85D

NO_TEST=TRUE

DISPLAYPORT

DISPLAYPORT

NO_TEST=TRUE

DP_85D

DP_T29SNK0_AUXCH_C_N

T29_90D

T29_B_RSVD_P

DISPLAYPORT

NO_TEST=TRUE

T29_SPI_55S

JTAG_T29_TDO

T29_SPI

T29_90D

T29

NO_TEST=TRUE

T29_R2D_C_P<3..0>

T29

NO_TEST=TRUE

T29_90D

T29_R2D_C_N<3..0>

T29

NO_TEST=TRUE

T29_90D

T29_D2R_C_P<3..0>

T29_SPI

T29_SPI_55S

T29_SPI_CLK

T29_SPI

T29_SPI_55S

T29_SPI_CS_L

T29_SPI

T29_SPI_55S

T29_SPI_MISO

T29_SPI

T29_SPI_55S

T29_SPI_MOSI

JTAG_T29_TDI

T29_SPI_55S

T29_SPI

T29_SPI_55S

JTAG_T29_TMS

T29_SPI

T29_SPI_55S

JTAG_T29_TCK

T29_SPI

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_T29_R

SYSCLK_CLK25M_T29

CLK_25M_55S

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_T29_CLK

CLK_25M

SYSCLK_CLK25M_T29

CLK_25M_55S

CLK_25M

NO_TEST=TRUE

T29

T29_D2R_P<3..0>

T29_90D
T29_90D

NO_TEST=TRUE

T29_D2R_N<3..0>

T29

NO_TEST=TRUE

T29_90D

T29_R2D_C_F_P<3..0>

T29

NO_TEST=TRUE

T29_90D

T29

T29_D2R_C_N<3..0>

NO_TEST=TRUE

T29

DP_SDRVA_AUXCH_C_P

T29_90D

DP_T29SRC_ML_N<3..0>

DISPLAYPORT

NO_TEST=TRUE

DP_85D

DP_T29SRC_AUXCH_R_C_N

DISPLAYPORT

DP_85D

NO_TEST=TRUE

NO_TEST=TRUE

DP_SDRVA_AUXCH_P

DISPLAYPORT

T29_90D
T29_90D

NO_TEST=TRUE

DP_SDRVA_AUXCH_N

DISPLAYPORT

T29_90D

DISPLAYPORT

DP_SDRVB_AUXCH_P

NO_TEST=TRUE

T29_90D

DISPLAYPORT

DP_SDRVB_AUXCH_N

NO_TEST=TRUE

DISPLAYPORT

DP_SDRVA_ML_C_N<3..0>

NO_TEST=TRUE

T29_90D

DP_SDRVA_ML_P<3..0>

DISPLAYPORT

T29_90D

NO_TEST=TRUE

NO_TEST=TRUE

DISPLAYPORT

DP_SDRVA_ML_R_P<3..0>

T29_90D

DP_SDRVA_ML_N<3..0>

NO_TEST=TRUE

DISPLAYPORT

T29_90D

DP_SDRVA_ML_R_N<3..0>

DISPLAYPORT

T29_90D

NO_TEST=TRUE

DISPLAYPORT

DP_SDRVB_ML_C_N<3..0>

T29_90D

NO_TEST=TRUE

NO_TEST=TRUE

DP_SDRVB_ML_C_P<3..0>

DISPLAYPORT

T29_90D

DISPLAYPORT

T29_90D

DP_SDRVB_ML_P<3..0>

NO_TEST=TRUE

NO_TEST=TRUE

DISPLAYPORT

T29_90D

DP_SDRVB_ML_R_P<3..0>

T29_90D

DISPLAYPORT

DP_SDRVB_ML_R_N<3..0>

NO_TEST=TRUE

NO_TEST=TRUE

DP_SDRVB_ML_N<3..0>

DISPLAYPORT

T29_90D

T29_90D

NO_TEST=TRUE

T29_A_RSVD_N

DISPLAYPORT

T29_90D

DISPLAYPORT

T29_B_RSVD_N

NO_TEST=TRUE

T29_90D

DISPLAYPORT

T29_A_RSVD_P

NO_TEST=TRUE

DP_T29SNK1_ML_C_P<3..0>

DP_85D

NO_TEST=TRUE

DISPLAYPORT

DP_T29SNK1_ML_C_N<3..0>

DP_85D

NO_TEST=TRUE

DISPLAYPORT

DP_T29SNK1_ML_N<3..0>

NO_TEST=TRUE

DP_85D

DISPLAYPORT

DP_SDRVB_AUXCH_C_P

T29

NO_TEST=TRUE

T29_90D

NO_TEST=TRUE

T29

DP_A_EXT_AUXCH_N

T29_90D

T29

NO_TEST=TRUE

T29_90D

DP_A_EXT_AUXCH_P

NO_TEST=TRUE

T29

T29_90D

T29DPA_ML_N<3..0>

DP_SDRVA_AUXCH_C_N

NO_TEST=TRUE

T29

T29_90D

T29DPA_D2R1_AUXCH_P

T29

NO_TEST=TRUE

T29_90D

DP_T29SRC_AUXCH_C_N

DP_85D

DISPLAYPORT

NO_TEST=TRUE

NO_TEST=TRUE

T29_R2D_P<3..0>

T29_90D

T29

T29DPB_ML_C_P<0>

NO_TEST=TRUE

T29

T29_90D

DP_SDRVB_AUXCH_C_N

NO_TEST=TRUE

T29

T29_90D

DP_B_EXT_AUXCH_P

NO_TEST=TRUE

T29

T29_90D

NO_TEST=TRUE

T29

T29_90D

T29DPA_ML_P<3..0>

DP_85D

DISPLAYPORT

NO_TEST=TRUE

DP_T29SRC_AUXCH_R_C_P

DP_T29SNK1_AUXCH_P

NO_TEST=TRUE

DISPLAYPORT

DP_85D

PCIE_T29_R2D_N<3..0>

PCIE

NO_TEST=TRUE

PCIE_85D

NO_TEST=TRUE

DISPLAYPORT

DP_SDRVA_ML_C_P<3..0>

T29_90D

DISPLAYPORT

DP_85D

DP_T29SRC_AUXCH_C_P

NO_TEST=TRUE

DP_85D

DP_T29SNK1_AUXCH_C_N

NO_TEST=TRUE

DISPLAYPORT

NO_TEST=TRUE

T29

T29_90D

T29DPB_ML_N<3..0>

DP_T29SNK0_ML_P<3..0>

NO_TEST=TRUE

DP_85D

DISPLAYPORT

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_N<3..0>

NO_TEST=TRUE

DP_85D

DISPLAYPORT

DP_T29SNK0_AUXCH_P

NO_TEST=TRUE

NO_TEST=TRUE

PCIE

PCIE_T29_D2R_P<3..0>

PCIE_85D

T29DPA_ML_C_P<2>

T29

NO_TEST=TRUE

T29_90D

T29DPA_ML_C_N<2>

T29

NO_TEST=TRUE

T29_90D

T29

NO_TEST=TRUE

T29DPA_ML_C_P<0>

T29_90D

T29

T29_90D

NO_TEST=TRUE

T29DPB_D2R3_AUXCH_N

PCIE

PCIE_85D

PCIE_T29_R2D_C_N<3..0>

NO_TEST=TRUE

PCIE_T29_D2R_C_P<3..0>

NO_TEST=TRUE

PCIE_85D

PCIE

PCIE_85D

PCIE

NO_TEST=TRUE

PCIE_T29_D2R_C_N<3..0>

DP_T29SRC_ML_C_P<3..0>

DP_85D

NO_TEST=TRUE

DISPLAYPORT

DP_T29SRC_ML_P<3..0>

DISPLAYPORT

NO_TEST=TRUE

DP_85D

DISPLAYPORT

NO_TEST=TRUE

DP_85D

DP_T29SNK0_ML_C_P<3..0>

DP_85D

NO_TEST=TRUE

DISPLAYPORT

DP_T29SNK0_AUXCH_N

NO_TEST=TRUE

T29

T29DPB_ML_C_P<2>

T29_90D

T29DPB_ML_C_N<0>

T29

NO_TEST=TRUE

T29_90D

T29DPB_D2R3_AUXCH_P

T29

T29_90D

NO_TEST=TRUE

DP_B_EXT_AUXCH_N

NO_TEST=TRUE

T29

T29_90D

T29

NO_TEST=TRUE

T29_90D

T29_R2D_N<3..0>

T29

NO_TEST=TRUE

T29_90D

T29_R2D_C_F_N<3..0>

NO_TEST=TRUE

T29

T29_90D

T29DPB_ML_P<3..0>

T29DPA_D2R1_AUXCH_N

T29

T29_90D

NO_TEST=TRUE

T29DPA_ML_C_N<0>

T29

NO_TEST=TRUE

T29_90D

T29DPB_ML_C_N<2>

NO_TEST=TRUE

T29

T29_90D

DP_T29SNK0_AUXCH_C_P

NO_TEST=TRUE

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_C_P

DP_85D

NO_TEST=TRUE

DISPLAYPORT

DP_T29SNK1_AUXCH_N

NO_TEST=TRUE

DP_85D

DISPLAYPORT

DP_T29SNK1_ML_P<3..0>

NO_TEST=TRUE

DP_85D

DISPLAYPORT

DP_T29SNK0_ML_C_N<3..0>

DP_85D

DISPLAYPORT

NO_TEST=TRUE

NO_TEST=TRUE

PCIE_CLK100M_T29_P

CLK_PCIE

CLK_PCIE_90D

PCIE_T29_D2R_N<3..0>

NO_TEST=TRUE

PCIE_85D

PCIE

CLK_PCIE_90D

CLK_PCIE

NO_TEST=TRUE

PCIE_CLK100M_T29_N

108 OF 110

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051-8115

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TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NET_TYPE

SPACING

PHYSICAL

PHYSICAL

SPACING

NET_TYPE

SPACING

PHYSICAL

PM NET PROPERTIES

NET_TYPE

(PM, RESET, EN, PGOOD)

I137

I138

I139

I140

I141

I142

I143

I152

I164

I166

I167
I168

I169

I170
I171

I172

I173
I174

I175
I176

I177

I178

I179

I180

I181

I182
I183

I184

I186
I187

I188
I189

I190

I191
I192

I193

I227
I229

I231

I236
I237

I238

I248

I250

I251

I252
I253

I254
I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274
I275

I276

I277

I278
I279

I280
I281

I282
I283

I284

I285
I286
I287

I288

I289

I290

I291

I292

I293

I294
I295
I296

I297

I298

I299
I300

I301
I302
I303

I304
I305

I307
I308
I309

I310

I311

I312

I313

I314

I315

I318

I319

I320

I323
I324
I325

I344

I348

I349

I350

I351

I352
I353
I354
I355

I357
I358

I359

I360

I361

I362

I363

I364

I365

I366
I367

I368

I369

I370

I371

I372

I373

I374

I375

I376

I377
I378

I379
I380

I381

I382

I383

I384

I385

I386

I387

I388

I389

I390

I391

I392

I393
I394

I395

I396
I397

I398

I399
I400

I401

I402
I403

I404

I405

I406

I407

I408
I409

I410
I411

I412

I413

I414

I415

I416

I417

I418

I419

I420

I421

I422

I423
I424
I425

I426

I427

I428

I429

I430

I431

I432

I47

I48

I68

SYNC_MASTER=K62

PM RESETS ENABLES PGOOD CONST

SYNC_DATE=01/06/2011

DEFAULT

GNDPM_VTT

*

*

DEFAULT

GND

PM

PM_VTT

* *

3:1_SPACING

PM_VTT PM_VTT

*

2:1_SPACING

2:1_SPACING

*

PM

*

PM

SPI_DESCRIPTOR_OVERRIDE_L

PGOOD_P1V5_S0_DLY

PM

SMC_PROCHOT_3_3_L

PM

PM

PM_SYSRST_L

PM

PM_SLP_S3_5V_L

PM

PM_SLP_S3_5V_R2

PM

PM_SLP_S4_1_L_R
PM_SLP_S4_D_L

PM
PM

PM_SLP_S4_L

PM_VTT

PM_THRMTRIP_L
PM_SLP_S3_BUF_L

PM

PM

PM_SYS_PWRGD

PM_VTT

PM_SYNC

PM

PM_SLP_S5_L

PM

PM_SLP_S4_L

PM

PM_SLP_S3_L

PM_PCH_PWRGD

PM

PM

PM_SLP_S3_5V

PM_MXM_PGOOD

PM

PM

PM_MEM_PWRGD_L

PM_MEM_PWRGD

PM_VTT

PM

HDD_OOB_1V00_REF

PM

USE_HDD_OOB_L

MINI_RESET_L

PM

MXM_CLKREQ_L

PM
PM

MXM_GOOD

PM

ODD_PWR_EN_L

PM

RSMRST_PWRGD

SMC_PM_G2_EN

PM

PM

S5_DG_1

SMC_WAKE_SCI_L

PM

PM

SMC_ONOFF_L

PM

T29_PWR_EN

PM

T29_RESET_L

PM

LPC_PWRDWN_L

PM

ISOLATE_CPU_MEM_L

PM_EN_P1V05_S3_REG

PM

PM_EN_P1V5_S0_FET

PM
PM

PM_EN_P1V8_S0_REG

PM

PM_EN_P3V3_S0_FET

PM

PM_EN_P5V_S3_REG

PM

PM_EN_VCCSA_S0_CPU

PM

PM_PCH_PWRGD_R

PM

PM_PECI_PWRGD_R

PM_PGOOD_DDR1V5_S3_REG

PM

PM_PGOOD_P1V05_S0_REG

PM

PM_PGOOD_P1V5_S0_FET

PM

PM_PGOOD_P3V3_S3_FET

PM

PM_PGOOD_P3V3_S5_REG

PM

PM

PM_PGOOD_PVCCSA_S0_REG

PM

PM_PGOOD_P5V_S3_REG

PM

PM_PGOOD_PVAXG

PM

PM_PGOOD_PVCORE_CPU

PM

SMC_PM_G2_EN_R

PM

S4_ENABLES

PM

3V42G3H_SHDN_L

ALL_SYS_PWRGD_R

PM

ALL_SYS_PWRGD_SMC

PM

PM

AUD_IPHS_SWITCH_EN

PM

SDCARD_PLT_RST_L_R

PM

PLT_RESET_L

PM_CLK32K_SUSCLK_R

PM

PM_CLK32K_SUSCLK

PM

PM

PM_BATLOW_L

PLT_RESET_LS1V05_L

PM_VTT

ENET_PWR_EN

PM

ENET_LOW_PWR

PM
PM

FW_RESET_L

PM

ENET_RESET_L

PM

PM_RSMRST_L

PM

PM_RSMRST_PCH_L

PM

PM_PWRBTN_L

PM_CLKRUN_L

PM

SMC_ADAPTER_EN

PM

PM

S5_MSFT_G1

PM

SDCARD_PLT_RST_L

PM

RTC_RESET_L

PM

3V3R2V9_DPAPWR_ADJ

PM

AUD_SPDIF_IN

PM

BDV_BKL_PWM

PM

SDCARD_RESET_L

PM

SDCONN_STATE_RST_L
SDCONN_DETECT_BUF_L

PM

PM

FW_PWR_EN
FW_CLKREQ_L

PM

PM

MEM_RESET_L

PM_VTT

PM_MEM_PWRGD

PM

PM_EN_P5V_S0_FET

MINI_CLKREQ_L

PM

PM

VTT_REG_PGOOD_L

VIDEO_ON

PM

VSYNC_DP

PM

VSYNC_DP_CONN

PM

PM

XDPPCH_PLTRST_L

USB_HUB_SOFT_RESET_L

PM

XDP_PWRGD

PM_VTT

PM_VTT

XDP_DBRESET_L

PM

SDCONN_STATE_CHANGE

PM

SMC_PM_G2_EN_L

PM

AUD_IP_PERIPHERAL_DET

PM

SDCARD_RESET

PM

RTC_RESET_L

PM

FW_PME_L

PM

PM_PGOOD_MINI

PM_PGOOD_P5V_S0_FET

PM

PM_PGOOD_P3V3_S0_FET

PM

PM_PGOOD_P1V8_S0_REG

PM

PM

PM_PECI_PWRGD

PM

PM_MXM_EN

PM_EN_PVCORE_CPU

PM

PM

PM_EN_PVCCSA_S0_REG_L

PM

PM_EN_P3V3_S5_REG

PM_EN_P3V3_S3_FET

PM

PM

PM_EN_P12V_S0_FET
PM_EN_P1V05_S0_REG

PM

PM

PM_EN_DDR1V5_S3_REG

PM

PM_EN_DDRVTT_S0_REG

PM

PM_MEM_PWRGD_R

PM

PM_ASW_PWRGD

PM

PM_DSW_PWRGD

PCIE_WAKE_L

PM

PCH_DF_TVS

PM

PCH_PROCPWRGD

PM

PCH_DSWVRMEN

PM

PM

PCH_INTVRMEN_L

PM

PCH_SRTCRST_L

AUD_I2C_INT_L

PM

BL_PWM

PM

PM

AUD_SPDIF_IN_CODEC

PM

AP_MINI_RESET_L

BL_EN

PM

BDV_BKL_PWM

PM

PM

AP_PWR_EN

4V5_REG_EN

PM

PM

MXM_PNL_BL_PWM

PM

CK505_27MHZ_EN

PM

CPUVTT_REG_EN
CPUVTT_REG_PGOOD_R

PM_VTT

PM

CPU_MEM_RESET_L

PM

CPU_PECI_R

PM_VTT

CPU_PWRGD
CPU_RESET_L

PM

CPU_PECI

PM

CPU_PROC_SEL

PM

PM

DEBUG_RESET_L
DP_INT_SPDIF_AUDIO

PM

DDRVTT_EN

PM

DPAPWRSW_CT

PM

T29_A_HV_EN

PM

3V3R2V9_DPBPWR_ADJ

PM

DP_B_PWRDWN_INV

PM

DPBPWRSW_CT

PM

PM

DP_INTPNL_HPD

DPBPWRSW_IFLT

PM

PM

LCD_BL_PWM

LCD_BLK_ON_DLY

PM

LCD_BL_FILT

PM

SMC_DELAYED_PWRGD

PM

PM

SMC_RUNTIME_SCI_L

PM

T29_DP_PORTA_PWR_EN

PM

SMC_LRESET_L

PM

DP_A_PWRDWN_INV

SMC_RESET_L

PM
PM

SMC_PROCHOT

PM

SMC_MANUAL_RST_L

XDP_CPUPWRGD

PM_VTT

PM

T29_DP_PORTA_PWR_EN_REG

DP_B_PWRDWN_FET_R

PM

CPU_PROCHOT_L

PM

CPU_SKTOCC_L

PM

PM

T29_B_HV_EN

DPBPWRSW_ILIM

PM

DPBPWRSW_HVEN_L_R

PM

DP_B_PWRDWN

PM

DP_A_PWRDWN_FET_R

PM

CPU_THRMTRIP_L

PM

CPU_CATERR_L

PM

T29_PWR_EN

PM

T29_RESET_RTR_L

PM

PM

DP_A_PWRDWN

DPAPWRSW_HVEN_L_R

PM

DPAPWRSW_ILIM

PM
PM

DPAPWRSW_IFLT

PM

PGOOD_1V8_S0_G2

PM

PGOOD_1V8_S0_G1

PGOOD_P12V_S0

PM

PGOOD_PCH_S0

PM

PGOOD_P1V8_S0

PM

PM

PGOOD_PCH_S0_R

PGOOD_CPU_UNCORE

PM

PM

POWER_BUTTON_L

PGOOD_SYSPWROK_R

PM

PGOOD_SYSPWROK

PM

12V_COMP_REF

PM
PM

ALL_SYS_PWRGD

PM

9V_COMP_REF

PM

PGOOD_12V_S0_G2

PGOOD_12V_S0_G1

PM

PM

PGOOD_3V3_1V05

PM

PGOOD_5V_1V05_3V3

PM

PGOOD_CPU_S0

PM

PEG_RESET_L

109 OF 110

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5

19 32 46 47 63 97

5

19 26 32 36 46 47 63 82

19 21 64

32

64 76

11

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51

20 51

27 33

9

75

5

21 25

15 21 42

46 64

46 74

74

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46 47

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27 80

19 46 48

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63 73

63 71

63 73

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64

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63 71

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11 64 73

34 73

27 64 70

63 64

63 70 82

5

65

5

25 64 65

74

63

72

5

32 64

46 64

21 62

20 27

9

19 91

9

46 91

15 19 46

11

20 25 36
15 21 37

27 39

27 36

27 46
19 27

19 25 46

15 19 46 48

19 46 47

74

27 44

18 27 97

82 95

60 83 91

46 83 97

44

92

15 21

15 39

30 31 32 89

11 19 97

63 73

15 33

63

81

81

6

81

25 27
20 25 34

11 25

20 25 45

74

20 61

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18 27 97

15 21 39

33

63 64 73

63 64 73

64 71

46 64

64 76

63 65

64

70

63 73

6

63

63 68

63 71

32 63 71

11

19 64

19

19 33 36 78

19

21

19

18

18

20 62

6

83

56 83

33

6

81

46 83 97

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56

76 83

26

63

11 32

46

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46 47

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11

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80 86

84

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82

64

64

63 64

5

64

64

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64 91

47

64

64

64

64 91

64

64

64

64 91

64 91

64

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www.vinafix.vn

IN

IN

IN

IN

IN
IN
IN
IN

IN
IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN
IN

IN

IN

IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN
IN
IN
IN
IN

IN
IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

J5551 ODD TEMP SENSOR

17 TP’S

J4780 IR BOARD

1 PP5V_S3_REG Testpoint near J4700

1 PP3V3_S3 TESTPOINT NEAR J4700

J5600 ODD FAN

J4700 USB CAMERA

2 TP’S

2 Ground Testpoints near J4750

J5400 HDD TEMP SENSOR

1 GROUND TESTPOINTS NEAR J5400

J5560 SKIN TEMP SENSOR

1 GROUND TESTPOINT NEAR J5700

1 PP3V3_S3 Testpoint near J4750

6 GROUND TESTPOINTS NEAR J4700

1 GROUND TESTPOINT NEAR J4780

J5601 HD FAN

J4750 USB CARD READER

J6603 AUDIO LEFT SPEAKER

J6602 AUDIO RIGHT SPEAKER

2 TP’S

4 GROUND TESTPOINTS NEAR J6600

1 PP5V_S0 Testpoint near J4520

J4520 SATA ODD (HIGH SPEED)

1 GROUND TESTPOINTS NEAR J4520

J6600 AUDIO AUXILIARY CONNECTOR

J5700 CPU FAN

44 92

44 92

44 92

44 92

53

53

53 95

53

54

54

54

54 95

53 95

53

53

53

6

95

44 92

44 92

52 94

52 94

42 46

6

95

91

91

91

91

91

91

91

91

6

95

15 21 44 97

42 51 94

44 52 94

44 52 94

52 54 94

52 54 94

44 95

60

60 95

60

60

60

60

60

60

60

60

60

60

60

52 94

52 94

SYNC_DATE=01/06/2011

K60/K62 ICT/FCT

SYNC_MASTER=K62

FUNC_TEST=TRUE

FAN_2_PWR_L

FUNC_TEST=TRUE

AUD_HP_L_JACK

FUNC_TEST=TRUE

HS_MIC_HI_JACK

FUNC_TEST=TRUE

AUD_HP_TIPDET_JACK

FUNC_TEST=TRUE

MIN_ALLOWED_TPS=2

PP3V3_S3

FUNC_TEST=TRUE

AUD_LI_R_JACK

AUD_HP_GND_JACK

FUNC_TEST=TRUE

FUNC_TEST=TRUE

SMC_ODD_DETECT

AUD_SPDIFIN_JACK

FUNC_TEST=TRUE

FUNC_TEST=TRUE

AUD_IP_PERPH_JACK

AUD_HP_TYPEDET_JACK

FUNC_TEST=TRUE

AUD_HP_R_JACK

FUNC_TEST=TRUE

FUNC_TEST=TRUE

AUD_LI_L_JACK

FUNC_TEST=TRUE

AUD_LI_GND_JACK

FUNC_TEST=TRUE

AUD_LI_DET_JACK

PP3V3_AUDIO_SPDIF_JACK

MIN_ALLOWED_TPS=2

FUNC_TEST=TRUE

FUNC_TEST=TRUE

AUD_SPKR_OUTLO1L_NOUT

FUNC_TEST=TRUE

AUD_SPKR_OUTLO1L_POUT

FUNC_TEST=TRUE

AUD_SPKR_OUTLO2L_POUT
AUD_SPKR_OUTLO2L_NOUT

FUNC_TEST=TRUE

FUNC_TEST=TRUE

AUD_SPKR_OUTLO1R_POUT
AUD_SPKR_OUTLO1R_NOUT

FUNC_TEST=TRUE

FUNC_TEST=TRUE

AUD_SPKR_OUTLO2R_POUT
AUD_SPKR_OUTLO2R_NOUT

FUNC_TEST=TRUE

FUNC_TEST=TRUE

SNS_SKIN_RIGHT_P

FUNC_TEST=TRUE

SNS_SKIN_RIGHT_N

FUNC_TEST=TRUE

SNS_SKIN_LEFT_N

FUNC_TEST=TRUE

SNS_SKIN_LEFT_P

USB_CAMERA_L_N

FUNC_TEST=TRUE

USB_BT_L_P

FUNC_TEST=TRUE

USB_BT_L_N

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FAN_0_PWR_L

FUNC_TEST=TRUE

FAN_TACH2_L
PP12V_S0_FAN2_L

FUNC_TEST=TRUE

SNS_AMB_N

FUNC_TEST=TRUE

PP12V_S0_FAN1_L

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FAN_1_PWR_L
FAN_TACH1_L

FUNC_TEST=TRUE

FAN_1_GND

FUNC_TEST=TRUEFUNC_TEST=TRUE

PP5V_S3_IR_FLT

USB_IR_L_N

FUNC_TEST=TRUE

FUNC_TEST=TRUE

USB_IR_L_P

FUNC_TEST=TRUE

MIN_ALLOWED_TPS=1

PP5V_S3

USB_CAMERA_L_P

FUNC_TEST=TRUE

FUNC_TEST=TRUE

PP12V_S0_FAN0_L

FUNC_TEST=TRUE

FAN_0_GND

FAN_TACH0_L

FUNC_TEST=TRUE

FUNC_TEST=TRUE

SDCARD_RESET

SNS_AMB_P

FUNC_TEST=TRUE

HDD_OOB_TEMP_FILT

FUNC_TEST=TRUE

SNS_ODD_N

FUNC_TEST=TRUE

MIN_ALLOWED_TPS=1

PP5V_S0

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FAN_2_GND

SNS_ODD_P

FUNC_TEST=TRUE

GND

MIN_ALLOWED_TPS=17

FUNC_TEST=TRUE

110 OF 110

11.1.0

051-8115

98 OF 98

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