Apple A1304 Schematic

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

08/01/2008

EVT

SCHEM,MLB,M96

Schematic / PCB #’s

LPC+SPI Debug Connector

41

01/24/2008

CHANGZHANG

51

SMC SUPPORT

40

01/09/2007

M70

50

SMC

39

02/21/2008

M97

49

IPD Connector

38

48

USB EXTERNAL CONNECTORS

37

01/09/2007

M70

46

SATA Connectors

36

02/05/2008

CHANGZHANG

45

Hatch and Audio Connectors

35

(MASTER)

42

Wireless M93 Connector

34

01/09/2007

M70

41

Memory Active Termination

33

01/09/2007

M70

37

DDR BYPASSING 2

32

06/20/2005

MEMORY

36

DDR BYPASSING 1

31

06/20/2005

MEMORY

35

DDR3 DRAM Channel B (32-63)

30

34

DDR3 DRAM Channel B (0-31)

29

(MASTER)

33

DDR3 DRAM Channel A (32-63)

28

32

DDR3 DRAM Channel A (0-31)

27

(MASTER)

31

DDR3 Support

26

01/30/2008

T18_MLB

30

FSB/DDR3 Vref Margining

25

01/15/2008

BEN

29

SB Misc

24

02/04/2008

M97

28

MCP Graphics Support

23

02/04/2008

M97

26

MCP Standard Decoupling

22

02/04/2008

M97

25

MCP Power & Ground

21

02/04/2008

M97

22

MCP HDA & MISC

20

02/04/2008

M97

21

MCP SATA & USB

19

02/04/2008

M97

20

MCP PCI & LPC

18

02/04/2008

M97

19

MCP Ethernet & Graphics

17

02/04/2008

M97

18

MCP PCIe Interfaces

16

02/04/2008

M97

17

MCP Memory Misc

15

02/04/2008

M97

16

MCP Memory Interface

14

02/04/2008

M97

15

MCP CPU Interface

13

02/04/2008

M97

14

eXtended Debug Port (XDP)

12

02/04/2008

M97

13

CPU Decoupling & VID

11

04/26/2006

MSARWAR

12

CPU Power & Ground

10

(MASTER)

11

CPU FSB

9

02/04/2008

M97

10

SIGNAL ALIAS /RESET

8

(MASTER)

9

Power Aliases

7

06/15/2006

WFERRY

8

Functional Test and No-Tests

6

(MASTER)

7

Acoustic Cap BOM Config Tables

5

N/A

5

CONFIGURATION OPTIONS

4

(N/A)

4

Power Block Diagram

3

06/30/2005

POWER

3

System Block Diagram

2

05/11/2006

WFERRY-WF

2

M96 RULE DEFINITIONS

109

71

M97

02/04/2008

M96 Power and Ground Nets

108

70

(MASTER)

SMC Constraints

106

69

M97

02/04/2008

MCP Constraints 2

103

68

M97

02/04/2008

MCP Constraints 1

102

67

M97

02/04/2008

Memory Constraints

101

66

M97

02/04/2008

CPU/FSB Constraints

100

65

M97

02/04/2008

Additional CPU/GPU Decoupling

99

64

LCD Backlight Support

98

63

M97

02/04/2008

LED Backlight Driver

97

62

(MASTER)

DisplayPort Connector

94

61

M98_MLB

01/17/2008

DISPLAYPORT SUPPORT

93

60

NMARTIN

12/18/2007

LVDS,Camera Conn. and ALS Conn.

90

59

GPU

06/23/2006

PBUS Supply/Battery Charger

79

58

M70

01/09/2007

POWER FETS

78

57

YUAN.MA

02/04/2008

POWER SEQUENCING

77

56

YUAN.MA

02/04/2008

5V / 3.3V Power Supply

76

55

RXU_K20

05/21/2008

1.5V/0.75V Supplies

75

54

M70

01/09/2007

1V05 S5 Power Supply

74

53

RXU_K20

05/21/2008

1.8V LDO Supply

73

52

MCP CORE REGULATOR

72

51

MINGJING

06/24/2008

IMVP6 CPU VCore Regulator

71

50

POWER

07/13/2005

DC-In & Battery Connectors

69

49

M70

01/09/2007

SPI ROM

61

48

CHANGZHANG

02/15/2008

Sudden Motion Sensor (SMS)

59

47

M76_MLB

01/12/2007

Fan

56

46

M70

01/09/2007

TEMPERATURE SENSORS

55

45

M70

01/09/2007

Current Sensing

54

44

YUNWU

02/04/2008

Voltage Sensors

53

43

M70

01/09/2007

Contents

Sync

Date

Page

(.csa)

SCH

CRITICAL

1

SCHEM,MLB,M96

051-7631

820-2375

1

PCB

CRITICAL

PCBF,MLB,M96

LAST_MODIFIED=Fri Aug 1 09:54:13 2008

TITLE=M96_MLB

ABBREV=DRAWING

Table of Contents

1

N/A

1

SyncPage

Date

(.csa)

Contents

M97 SMBUS CONNECTIONS

52

42

BEN

02/04/2008

1

71

2.3.0

051-7631

SCHEM,MLB,M96

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1066 MHz

800 MHz

0.75V - 64 Bits

VOLTAGE SENSORS PG 45

PG 40

IPD

J4800

MEM Active

Parallel

Term

USB

J5100

U4900

PG 12

MINI XDP CONN

J1300

CPU

U1000

Pg 10

FSB

64-Bit

FSB

HDMI

J9000

J4200

3

LPC SMB

Ln2

Pg18

PG 38

J4260

J4100

Display Port

2

Controller

LVDS Int Disp

5

U6100

ADC

Prt

DC/Batt

Power

Supplies

Pg 14

Ln0 Ln1

Flash

Ln3

Pg20

SATA DACS

Pg18

LAN

Pg 19

PCI

Pg 21

HDA SPI

Pg 24

1 4

USB

6

Misc

Pg 15/16

Main Memory

U3130

U3120

U3110

U3100

A B 0

BSA

SMC

MGMT

Fan

Ser

Conn

J4200

External

Trackpad/Keyboard

J4800

DIGITAL MIC

CONNECTOR

PG 60

Connector

Audio

M93 AirPort/BT

LVDS

Pg 19

Well Spring

J9050

0

Pg 20

7

Pg 21

SPI

Boot ROM

Pg 21

PG 50

Pg 17

Pg 18

1.6/1.8 GHz

Pg 11

PG 37

Conn

Camera

PG 60

PG 63PG 64

Conn

NAND

U9500U9601

U9600

NAND Flash

HDD SATA

Pg 36

Pg 37

PG 40

J4500

PG 37

PG 41

FrankCard Conn

PG 43

Local TEMP near power supplies

U5550

U5560

Local TEMP near Air Vent

Local TEMP near Front Edge

U5570

PG 47

PG 47U5515

CPU/MCP T-Diode Thermal Sensor

PG 47

SUDDEN MOTION DETECT U5900 PG 49

FAN CONN J5600

PG 48

J9000

TOP ALS

J4100

PG 36

M93

PG 51

PG 52-59

J6900/80

DDR3 RAM

U3210 U3220 U3230 U3240

Pg29/30

U3300 U3310 U3320 U3330 U3410 U3420 U3430 U3440

Pg31/32

Pg 35

PG 60

DDR3 RAM

DDR3 - Dual Channel

FLAT PANEL

PCI-E

Core

MCP79U

U1400

2.3.0

71

SYNC_DATE=05/11/2006

System Block Diagram

2

SYNC_MASTER=WFERRY-WF

051-7631

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BATTERY ONLY:

U7740

SENSE

MR

PS_PWRGD

PPBUSB_G3H

VO1

MEM_VTT_EN_R

R2870

DDRVTT_EN

TPS51116

(PAGE 55)

PP0V75_S0_REG

S5

MCPDDR_EN

BATTERY

SLP_S3*

CHGR_BGATE

Q5315

D6901

V

(S0)

D6901

01

2S2P

J6980

DC-JACK

U7900

VIN

02

04

MCP79U

U5000

RN5VD30A-F

SMC PWRGD

(PAGE 10)

U1000

RESET*

CPU

FC_RESET_L

PCA9557D_RESET_L

BKLT_PLT_RST_L

PG1

ENA2

VIN

SMC_LRESET_L

PPDCIN_G3H

PPVBATT_G3H_R

ENABLE

VOUT1

PPVIN_G3H_DCIN

A

Q7950

F6900

PP18V5_DCIN

6A FUSE

PP18V5_G3H_CHGR

ENABLES

(PAGE 59)

PBUS Supply/

SMBUS_SMC_BSA_SCL

BATTERY CHARGER

=PPBUSB_G3H

02

VIN

(S0)

VIN

VR_PWRGOOD_DELAY

02

PGOOD1,2

D6901

P1V05_S5_PGOOD

(PAGE 51)

VIN

U6900

LTC3470A

SMC_ONOFF_L

PM_SLP_S3_L

13

RST*

DELAY

C-0.47uF

PM_SLP_S4_L

R-5.1K

09

C-NoStuff

R-100K

PP3V3_S5_PWRCTI

04

VLDOIN

DELAY

SMBUS_SMC_BSA_SDA

P3V3S3_EN

VOUT2

22

Q7710

15

SLP_S5*

MCP79U

DDRREG_EN

WOW_EN

PCI_RESET0*

09

DELAY

(S0)

DELAY

R-0

(S0)

C-0.47uF

R-0

R-33k

C-0.47uF

DELAY

R-22k

C-0.47uF

C-0,47uF

PM_SLP_S3_L

R-5.1k

DELAY

C-0.47uF

P1V05S0_EN

P1V8S0_EN

MCPDDR_EN (S0)

U2850

PP1V05_S0_FET

03

PP3V3_S5

EN2

Q7801

P5VS0_EN

P3V3S0_EN

EN

SMC_RESET_L

26

(30 A MAX CURRENT)

ADJ1

31

33

PBUSA_G3H

R7980

10

34

PPVCORE_S0_CPU_REG

35

R-1K

36

PP1V5_S0_VMON

37

39

40

41

LPC_RESET*

AIRPORT_RST_L

42

43

44

ISL6258

EN1

(S5)

PM_WLAN_EN_L

PP3V3S5_EN_L

Q7621

P5VS0_EN_L

PP5V_S3

VR_ON

(PAGE 52)

ISL6261CRZ

SMC_PM_G2_EN

Q7700

10

PM_G2_P3V3S5_EN_L

DELAY

R-5.1K C-0.47uF

DELAY

C-NoStuff

R-100K

PP3V42_G3H_PWRCTL

03

07

CPUVCORE

VOUT

LTC2909

U7100

IMVP_VR_ON

PGOOD

(S5)

PP3V42_G3H_REG

1.05V

RESET

U4900

VOUT2

PPDCIN_G3H_R

7A FUSE

(200 mA MAX CURRENT)

FSB_CPURST_L

DEBUG_RESET_L

12

PG2

VOUT

S0PGOOD_PWROK

PBUSVSENS_EN

5V

3.3V

CPU_PWRGD

SLP_S3_L(P93)

IMVP_VR_ON

PLT_RST*

SLP_S4_L(P94)

SLP_S5_L(P95)

RSMRST_PWRGD

14

PM_SLP_S5_L

PM_SLP_S4_L

15

24

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

ENA1

PP1V05_S0_VMON

U7770

ALL_SYS_PWRGD

PPBUSB_G3H

R7930

BATT_POS_F

PWR_BUTTON(P90)

05

P17(BTN_OUT)

06

ADJ2

P5V3V3_PGOOD

MCPCORES0_PGOOD

PP3V3_S3

PP3V3S5_EN_L

P1V05_S5_EN

SMC

U4900

(PAGE 41)

P60

SMC_PM_G2_EN

Q7840

02

3.425V G3HOT

33

(S0)

MCPCORES0_EN

(S5)

ISL6236

U7200

(PAGE 53)

(PAGE 42)

PP3V42_G3H_SMC

M96 POWER SYSTEM ARCHITECTURE

(0.002)

P1V05_S5_EN

MCPCORE

PP1V05_S5_REG

(7 A MAX CURRENT)

PPMCPCORE_S0_REG

(25 A MAX CURRENT)

Q7853

11

MCPCORES0_PGOOD

35

MCP_PS_PWRGD

CPU_RESET*

VR_PWRGOOD_DELAY

SMC_LRESET_L

PM_PWRBTN_L

RSMRST_IN(P13)

SMC

PM_RSMRST_L

37

FSB_CPURST_L

CPU_PWRGD

PCIE_RESET*

PWRBTN*

U1400

PWRGOOD

SMC_RESET_L

PWRGD(P12)

RSMRST*

U7600

19

C-0.47uF

DELAY

16

PPBUSA_G3H

IMVP_VR_ON

17

P5V3V3_PGOOD

TPS51120

CURRENT)

PP5V_S3_REG

(? A MAX

(PAGE 60)

TPS19918

1.8V S0

12

P3V3_S5_PWRCTL

08

Q7810

Q7830

(PAGE 54)

VIN

U7360

VOUT

32

TPS19918

(PAGE 57)

PP1V8_S0_REG

VO2

PP3V3_S5_REG

(? A MAX CURRENT)

VOUT1

0.75V

DDRREG_EN

22

VIN

24

23

(11 A MAX CURRENT)

DDRREG_PGOOD

U7500

PP0V75_S3_VTTREF

1.5V

S3

CPUVTTS0_EN

SMC_ADAPTER_PRESENT

26

25

26

16

PP1V5_S3_P1V5S0FET

PP1V5_S3_REG

28

27

28

P1V05S0_EN

26

27

P5VS3_EN_L

18

38

PPVCORE_S0_CPU

PPVBAT_G3H_CHGR_REG

MCPCORES0_EN

(PAGE 41)

RSMRST_PWRGD

26

27

22

ALL_SYS_PWRGD

P3V3S3_EN_L

20

21

(200 mA MAX)

P3V3S0_EN_L

PPVIN_S0_P1V8S0

P1V8_S0_EN

09

PP1V5_S5_PGOOD

27

PP3V3_S0_FET

=PP1V5_S0_FET

RST*

(PAGE 57)

08

PP5V_S0_FET

26

(S3)

P5VS3_EN_L

PP3V3_S5_PWRCTL

29

30

29

71

2.3.0

SYNC_DATE=06/30/2005

SYNC_MASTER=POWER

3

051-7631

Power Block Diagram

DESCRIPTION

REFERENCE DES

BOM OPTIONQTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

REFERENCE DESIGNATOR(S)

BOM OPTION

DESCRIPTION

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTIONQTY

PART NUMBER

CRITICAL

Module Parts

BOMOPTION Groups

Bar Code Label / EEE #’s

BOMs

Alternate Parts

[EEE:4DA]

EEE_4DA

CRITICAL826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_2AL

CRITICAL

[EEE:2AL]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_2AN,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_8GHZ

630-9516

PCBA,MLB,1.8GHZ,HY 2GB,MU CAP,M96

IC,GMCP,MCP79U-B02,27MMX27MM,BGA1588

338S0637

MCP_B02

CRITICAL

1

U1400

U6100

341S2326

1

CRITICAL

BOOTROM_FINAL

IC,EFI,BOOTROM FINAL (LOCKED),M96

IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M96

341S2382

CRITICAL

BOOTROM_DEVEL

1

U6100

IND,IHLP4040CZ,0.68uH,18A

152S0861152S0905 ALL

POWER NFET, 30V, 18A

376S0627 376S0723 ALL

152S0684 ALL152S0421

1.0UH,22A,10MOHM

376S0410 ALL376S0466

Si4413 for Si4405

128S0092 ALL128S0093

33UF 20% 16V DCASE

IC,ISL6258,REV2,BAT CHGR, 28P QFN

CRITICALU79001

353S1938

ALTERNATE,COMMON,M96_COMMON1,M96_COMMON2,M96_COMMON3

M96_COMMON

MCP_B02,BOOTROM_DEVEL,SMC_PRGRM,BOOT_MODE_USER,JTAG_ALLDEV,MEMRESET_HW,MEMRESET_MCP,VREFMRGN

M96_COMMON1

104S0018104S0023 ALL

1206 1/4W .002 OHM

[EEE:4DB]

EEE_4DB

CRITICAL826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:4DC]

EEE_4DC

826-4393

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_2AN

[EEE:2AN]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

740S0028740S0067 ALL

0.5A OC FUSE

IC,PRGRM,SMC (NEW),M96

341S2327

1

U4900

SMC_PRGRM

CRITICAL

MICRON,DDR3,128M16,9x11.5

CRITICAL4

DRAM_MICRON

333S0475

U3200,U3210,U3220,U3230

HYNIX,DDR3,128M16,9x11.5

333S0476

U3100,U3110,U3120,U3130

DRAM_HYNIX

CRITICAL4

4

HYNIX,DDR3,128M16,9x11.5

U3300,U3310,U3320,U3330

CRITICAL

DRAM_HYNIX

333S0476 333S0476

HYNIX,DDR3,128M16,9x11.5

DRAM_HYNIX

CRITICAL

U3400,U3410,U3420,U3430

4

DRAM_MICRON

MICRON,DDR3,128M16,9x11.5

4 CRITICAL

U3400,U3410,U3420,U3430

333S0475

MICRON,DDR3,128M16,9x11.5

4

DRAM_MICRON

U3300,U3310,U3320,U3330

CRITICAL

333S0475

4

MICRON,DDR3,128M16,9x11.5

U3100,U3110,U3120,U3130

CRITICAL

DRAM_MICRON

333S0475

338S0563

1

U4900

CRITICAL

SMC_BLANK

IC,SMC,HS8/2117

SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF

M96_SS_CAP

DRAM_HYNIX

M96_HYNIX

MCP_CS1_NO

M96_COMMON3

DRAM_MICRON,DRAM_SPD_2

M96_MICRON

PCBA,MLB,1.6GHZ,HY 2GB,TY CAP,M96

630-9514

EEE_2AL,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_6GHZ

PCBA,MLB,1.6GHZ,HY 2GB,MU CAP,M96

630-9735

EEE_4DB,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_6GHZ

EEE_4DA,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_6GHZ

PCBA,MLB,1.6GHZ,HY 2GB,SS CAP,M96

630-9734

EEE_4DC,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_8GHZ

630-9738

PCBA,MLB,1.8GHZ,HY 2GB,SS CAP,M96

EEE_2AP,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_8GHZ

PCBA,MLB,1.8GHZ,HY 2GB,TY CAP,M96

630-9517

EEE_2AP

[EEE:2AP]

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

4

333S0476

DRAM_HYNIX

U3200,U3210,U3220,U3230

CRITICAL

HYNIX,DDR3,128M16,9x11.5

IC, 32MBIT 8-PIN SERIAL FLASH, WSON8

U6100

CRITICAL

BOOTROM_BLANK_4MB

1

335S0615

338S0601

U1400

1

MCP_B01

CRITICAL

IC,GMCP,MCP79U-B01,27MMX27MM,BGA1588

SYNC_DATE=(N/A)

SYNC_MASTER=(N/A)

051-7631

71

4

2.3.0

PAGE_BORDER=TRUE

CONFIGURATION OPTIONS

LPCPLUS,XDP,XDP_CONN

M96_COMMON2

MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF

M96_MU_CAP

M96_TY_CAP

TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF

MCP_A01Q

U1400

CRITICAL

338S0604

1

IC,GMCP,MCP79U-A01Q,27MMX27MM,BGA1588

IC,PDC,QS,1.60GHZ,17W,1066,6M

CPU_1_6GHZ

CRITICAL

U1000

1

337S3658 337S3659

CRITICAL

CPU_1_8GHZ

1

U1000

IC,PDC,QS,1.80GHZ,17W,1066,6M

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

MURATA

SAMSUNG

TAIYO YUDEN

SAMSUNG

1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG

MURATA

2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

TAIYO YUDEN

10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS

CAP, 10UF, 6.3V, 20%, 0603

138S0626

C7266,C7267,C7269,C7401,C7605

5

CRITICAL

SS_CAP_10UF

CAP, 10UF, 6.3V, 20%, 0603

CRITICAL

C7266,C7267,C7269,C7401,C7605

5

MU_CAP_10UF

138S0625

CRITICAL

MU_CAP_10UF

C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229

10

CAP, 10UF, 6.3V, 20%, 0603

138S0625

CRITICAL

3

C1230,C1231,C1280

CAP, 10UF, 6.3V, 20%, 0603

MU_CAP_10UF

138S0625

MU_CAP_10UF

CRITICAL

138S0625

CAP, 10UF, 6.3V, 20%, 0603

8

C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012

CRITICAL

C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219

10

CAP, 10UF, 6.3V, 20%, 0603

MU_CAP_10UF

138S0625

C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209

MU_CAP_10UF

CAP, 10UF, 6.3V, 20%, 0603

CRITICAL

10

138S0625

138S0626

CAP, 10UF, 6.3V, 20%, 0603

CRITICAL

SS_CAP_10UF

8

C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012

138S0626

3

CRITICAL

CAP, 10UF, 6.3V, 20%, 0603

C1230,C1231,C1280

SS_CAP_10UF

138S0626

10

CRITICAL

CAP, 10UF, 6.3V, 20%, 0603

SS_CAP_10UF

C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209

7

138S0632

SS_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C2530,C2531,C2532,C2533,C2534,C2535,C2536

8

138S0632

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655

CRITICAL

SS_CAP_2_2UF

138S0632

10

C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641

CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402

C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641

MU_CAP_2_2UF

CRITICAL

10

138S0633

C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

8

138S0633

MU_CAP_2_2UF

138S0633

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

8

C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610

MU_CAP_2_2UF

138S0633

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

3

C4800,C7362,C7511

MU_CAP_2_2UF

9

CRITICAL

CAP, 1UF, 6.3V, 10%, 0402

SS_CAP_1UF

138S0629

C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603 C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603

9

CRITICAL

CAP, 1UF, 6.3V, 10%, 0402

138S0628

MU_CAP_1UF

CRITICAL

SS_CAP_1UF

138S0629

CAP, 1UF, 6.3V, 10%, 0402

C2506,C2507,C2516,C2517,C7100,C7101,C7103

7

CRITICAL

SS_CAP_1UF

138S0629

CAP, 1UF, 6.3V, 10%, 0402

C7947,C7360,C2504,C2505

4

CAP, 1UF, 6.3V, 10%, 0402

CRITICAL

TY_CAP_1UF

138S0630

7

C2506,C2507,C2516,C2517,C7100,C7101,C7103

CRITICAL

TY_CAP_1UF

CAP, 1UF, 6.3V, 10%, 0402

138S0630

4

C7947,C7360,C2504,C2505

C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL8MU_CAP_2_2UF

138S0627

10

TY_CAP_10UF

CRITICAL

C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209

CAP, 10UF, 6.3V, 20%, 0603

TY_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C4800,C7362,C7511

3

138S0634

CAP, 2.2UF, 6.3V, 20%, 0402

138S0632

10

CRITICAL

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

SS_CAP_2_2UF

CRITICAL

138S0627

TY_CAP_10UF

3

C1230,C1231,C1280

CAP, 10UF, 6.3V, 20%, 0603

TY_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564

8

138S0634

TY_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919

10

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

TY_CAP_2_2UF

138S0634

8

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655

TY_CAP_2_2UF

138S0634

8

TY_CAP_2_2UF

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267

CRITICAL

138S0634

CAP, 2.2UF, 6.3V, 20%, 0402

8

138S0634

TY_CAP_2_2UF

CRITICAL

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

TY_CAP_2_2UF

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296

12

138S0634

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516

TY_CAP_2_2UF

10

138S0634

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541

TY_CAP_2_2UF

138S0634

10

CRITICAL

C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616

TY_CAP_2_2UF

10

CAP, 2.2UF, 6.3V, 20%, 0402

138S0634

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641

TY_CAP_2_2UF

138S0634

10

TY_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610

138S0634

8

TY_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929

10

138S0634

TY_CAP_2_2UF

CRITICAL

C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

CAP, 2.2UF, 6.3V, 20%, 0402

10

138S0634

TY_CAP_2_2UF

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL10MU_CAP_2_2UF

138S0633

CRITICAL

C2530,C2531,C2532,C2533,C2534,C2535,C2536

7

MU_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919

MU_CAP_2_2UF

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

MU_CAP_2_2UF

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

10

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

8

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267

CRITICAL

MU_CAP_2_2UF

TY_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C2530,C2531,C2532,C2533,C2534,C2535,C2536

7

138S0634

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

MU_CAP_2_2UF

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

8

138S0633

MU_CAP_2_2UF

C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

CRITICAL

138S0627

TY_CAP_10UF

10

C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229

CAP, 10UF, 6.3V, 20%, 0603

138S0627

TY_CAP_10UF

CRITICAL

10

C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219

CAP, 10UF, 6.3V, 20%, 0603

CRITICAL

TY_CAP_10UF

CAP, 10UF, 6.3V, 20%, 0603

138S0627

8

C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012

CAP, 1UF, 6.3V, 10%, 0402

CRITICAL

MU_CAP_1UF

138S0628

4

C7947,C7360,C2504,C2505

138S0632

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

8

C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564

C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541

CRITICAL

SS_CAP_2_2UF

138S0632

10

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

138S0632

12

CAP, 2.2UF, 6.3V, 20%, 0402

SS_CAP_2_2UF

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296

138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919

SS_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

138S0633

MU_CAP_2_2UF

C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616

CRITICAL

10

C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541

138S0633

MU_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CAP, 1UF, 6.3V, 10%, 0402

CRITICAL

MU_CAP_1UF

138S0628

7

C2506,C2507,C2516,C2517,C7100,C7101,C7103

CRITICAL

C4800,C7362,C7511

3

CAP, 2.2UF, 6.3V, 20%, 0402

138S0632

SS_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

SS_CAP_2_2UF

138S0632

8

C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610

C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

SS_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

138S0632

8

CRITICAL

138S0632

10

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516

CRITICAL

10

CAP, 2.2UF, 6.3V, 20%, 0402

138S0632

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939

SS_CAP_2_2UF

CRITICAL

138S0632

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

10

C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929

TY_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939

10

138S0634

CRITICAL

SS_CAP_2_2UF

138S0632

10

CAP, 2.2UF, 6.3V, 20%, 0402

C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616

138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

CRITICAL10SS_CAP_2_2UF

10

SS_CAP_10UF

138S0626

CRITICAL

C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219

CAP, 10UF, 6.3V, 20%, 0603

10

138S0626

C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229

CAP, 10UF, 6.3V, 20%, 0603

CRITICAL

SS_CAP_10UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516

138S0633

MU_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

12

138S0633

MU_CAP_2_2UF

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296

MU_CAP_2_2UF

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939

10

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929

MU_CAP_2_2UF

CRITICAL

138S0632

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

8

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267

CAP, 2.2UF, 6.3V, 20%, 0402

C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

10

138S0632

SS_CAP_2_2UF

CRITICAL

71

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-7631

2.3.0

5

Acoustic Cap BOM Config Tables

C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603

9

CAP, 1UF, 6.3V, 10%, 0402

CRITICAL

138S0630

TY_CAP_1UF

5

C7266,C7267,C7269,C7401,C7605

CRITICAL

CAP, 10UF, 6.3V, 20%, 0603

138S0627

TY_CAP_10UF

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FUNC TEST - SATA HDD

FUNC TEST - FAN CONNECTOR

FUNC TEST - DC-IN CONNECTOR

FUNC TEST - M93 WIRELESS CONNECTOR

x10

FUNC TEST - RIO HATCH CONNECTOR

FUNC TEST - CAMERA USB, LVDS, ALS

FUNC TEST - AUDIO CONNECTOR

FUNC TEST - IPD CONNECTOR

FUNC TEST - MIC

FUNC TEST - AIRPORT

NICE2HAVE NETS

FUNC TEST - BATTERY CONNECTOR

FUNC TEST - Power Supplies

NO_TEST

CLOCK NO_TESTS

NO_TEST

LVDS NO_TESTS

NO_TEST

Power Supply NO_TESTs

NO_TEST

NB NO_TESTS

These are normally testpoints but become NC

Functional Test Points

x13

.

x6

x2 x2

REQUIRED NETS

FUNC TEST - XDP/ITP CONNECTOR

x2

I454

I455 I457

I458

I459

I460

I461

I462

I463

I466

I467

I469

I470

I471

I472

I473

I474

I475

I476

I477

I478

I479

I480

I482

I483

I484

I499 I500

I501

I502 I503

I506

I507

I508

I509 I510

I511

I512

I513

I514 I515

I516

I517

I518

I519

I520

I521

I522

I593

I595

I638

I639

I640

I645 I646

I647

I648

I649

I650

I654 I655

I656 I657

I658

I659 I660

I661

I662 I663

I664

I665 I666

I667

I668

I669

I676

I680

I681

I682

I683

I684

I685

I686

I687

I688 I689

I690

I691

I692

I694 I695

I696

I697 I698

I699

I700

I701

I702 I703

I704

I705

I706

I711 I712

I713

I714

I716

I717

I718 I719

I720 I721

I722

I723 I725

I726

I727 I728

I734

I735

I736 I737

I738

I739

I740

I741

I742 I743

I744 I745

I746

I747

I748 I749

I750

I751

I752

I753 I754

I755

I756

I757

I92

Functional Test and No-Tests

2.3.0

6

051-7631

71

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

PP1V5_S3

TRUE

AUD_MIC_DATA HDA_SDOUT

TRUE

HDA_SDIN0

TRUE

SATA_HDD_R2D_N

TRUE

PP3V3_S0_HDD_F

TRUE

=I2C_ALS_SCL

PP3V3_LCDVDD_SW_F

TRUE

PP3V3_S0_LCD_F

LVDS_IG_DDC_CLK

TRUE

LVDS_IG_A_CLK_F_P

TRUE

LVDS_IG_A_CLK_F_N

TRUE

PPVOUT_S0_LCDBKLT

LCDBKLT_RTN<1..6>

TRUE

USB2_CAMERA_F_N

TRUE

USB2_CAMERA_F_P

TRUE

PP5V_S3_CAMERA_F

TRUE

PCIE_E_R2D_C_P_F

TRUE

PCIE_E_R2D_C_N_F

TRUE

PCIE_E_R2D_C_N_F

TRUE

=PP1V05_S0_CPU

TRUE

=PP3V3_S0_XDP

TRUE

XDP_TMS

TRUE

XDP_TDI

TRUE

XDP_TRST_L

TRUE

XDP_DBRESET_L

TRUE

XDP_CPURST_L

TRUE

FSB_CLK_ITP_N

TRUE

FSB_CLK_ITP_P

TRUE

JTAG_MCP_TMS

TRUE

MCP_DEBUG<7..0>

TRUE

JTAG_MCP_TRST_L

TRUE

PP18V5_DCIN

ADAPTER_SENSE

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SDA

PP1V05_S5

PP1V5_S0

PP0V75_S0

PPVCORE_S0_CPU

PP5V_S0

BATT_POS

TRUE

PPMCPCORE_S0

PP1V05_S0

PP3V3_S0

DP_ML_C_P<3..0>

TRUE

FAN_RT_PWM

TRUE

=PP5V_S0_FAN

TRUE

FAN_RT_TACH

TRUE

CK505_SRC_CLKREQ6_L

TRUE

PCIE_WAKE_L AIRPORT_RST_L

TRUE

=SMB_AIRPORT_DATA

TRUE

=SMB_AIRPORT_CLK

TRUE

PP3V3_S0_MIC_F

AUD_MIC_CLK_F

TRUE TRUE

GND_MIC_F

TRUE

HDA_SYNC HDA_BIT_CLK

TRUE

AUD_MIC_CLK

TRUE

PM_SLP_S3_L

TRUE

SMC_LID

SMC_SYS_KBDLED

TRUE

SMC_SYS_LED

TRUE

=USB2_TPAD_N

TRUE

SMC_ONOFF_L

TRUE

=USB2_TPAD_P

TRUE

PP5V_S0_KBDLED_F

TRUE

PP5V_S3_TOPCASE_F

TRUE

=I2C_TPAD_SDA

TRUE TRUE

SMC_ONOFF_L =USB2_IR_N

TRUE TRUE

=USB2_IR_P PP5V_S0_KBDLED_F

TRUE

LSOC_PRESS_H_R

TRUE

XDP_TCK

TRUE

JTAG_MCP_TDO_CONN

TRUE

XDP_TDO_CONN

TRUE

LVDS_IG_A_DATA_P<0..2>

TRUE

LVDS_IG_A_DATA_N<0..2>

TRUE

SMBUS_MCP_0_CLK

TRUE

TP_XDP_OBSFN_B0

TRUE

XDP_BPM_L<0..5>

TP_XDP_OBSDATA_B3

TRUE

SMBUS_MCP_0_DATA

TRUE

XDP_OBS20

TRUE

XDP_PWRGD

TRUE

JTAG_MCP_TDI

TRUE

TP_XDP_OBSDATA_B2

TRUE

TP_XDP_OBSDATA_B1

TRUE

TP_XDP_OBSDATA_B0

TRUE

TP_XDP_OBSFN_B1

TRUE

=PPVIN_S0_AUDIO

PP3V3_S3_AP_AUX

TRUE

=SMB_AIRPORT_DATA

TRUE

AIRPORT_RST_L

TRUE

PCIE_E_R2D_C_P_F

TRUE

PCIE_E_D2R_N_F

TRUE

CK505_SRC_CLKREQ6_L

TRUE

PCIE_CLK100M_MINI_P_F

TRUE

PCIE_E_D2R_P_F

TRUE

SATA_HDD_R2D_P

TRUE

SATA_HDD_D2R_C_P

TRUE

DP_AUX_CH_C_N

TRUE

DP_AUX_CH_C_P

TRUE

DP_CA_DET_Q

TRUE

PP3V3_S0_DPPWR

=SMB_AIRPORT_CLK

TRUE

PCIE_CLK100M_MINI_N_F

TRUE

PCIE_WAKE_L

TRUE

AIRPORT_RST_L

TRUE

PP3V42_G3H_IPD_F

TRUE

=USB2_IR_N

TRUE

=USB2_IR_P

=I2C_TPAD_SCL

TRUE

SMC_BS_ALRT_L

TRUE

=I2C_ALS_SDA

LVDS_IG_DDC_DATA

TRUE

GND

TRUE

PP5V_S3_USB2_EXTA_F

TRUE

USB2_EXTA_F_N

TRUE

USB2_EXTA_F_P

TRUE

DP_HPD_Q

HDMI_CEC

TRUE

DP_ML_C_N<3..0>

TRUE

SATA_HDD_D2R_C_N

TRUE

PP3V3_S3 PP5V_S3 PP3V3_S5 PP3V42_G3H PP18V5_G3H PPDCIN_G3H PPBUS_G3H PPBUS_R_G3H PP1V8_S0

AUD_MIC_DATA_F

TRUE

12

56

11

39

40

68

67

68

70

10

65

24

65

68

34

42

68

35

40

39

70

39

38

70

65

67

42

65

42

34

61

70

42

34

38

49

70

59

35

67

70

59

70

59

67

62

70

34

9

12

65

13

20

18

20

70

69

70

67

46

16

24

34

70

35

59

34

39

38

70

42

38

8

38

12

59

20

12

20

35

70

34

24

34

67

60

61

34

16

24

70

8

42

40

59

37

61

67

70

7

35

20

36

42

59

17

59

6

7

9

12

49

42

7

49

7

61

46

7

46

6

59

20

35

20

38

8

6

8

6

38

6

38

9

12

17

12

9

12

7

34

6

34

6

34

36

35

6

34

6

38

6

38

39

42

17

35

61

36

7

59

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

5.027 A

2.046 A

315 mA

57 mA (A01)

"S3" RAILS

13 A

6.207 A

165 mA

4.011 A

7.368 A

12.984 A

11.551 A

27 A

1.075 A

3.134 A

562 mA

19 mA

7.047 A

PEX & SATA AVDD/DVDD aliases

57 mA (A01)

"S5" RAILS"S0" RAILS

"G3H" RAILS

206 mA (A01)

"RMGT" RAILS

7

2.3.0

SYNC_MASTER=WFERRY

71

051-7631

Power Aliases

SYNC_DATE=06/15/2006

=PPVIN_S5_1V05

MIN_LINE_WIDTH=0.5MM

PPBUS_R_G3H

VOLTAGE=12.6V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MM

=PPVIN_S5_1V5S30V75S0 =PPVIN_S0_MCPCORES0

=PPVIN_S5_CPU_IMVP

=PP5V_S3_TOPCASE

=PP5V_S3_CAMERA

=PP3V3_S3_SMBUS_SMC_MGMT

=PP5V_S3_P1V05S0FET

=PP3V3_ENET_MCP_RMGT

=PP3V3_S3_VREFMRGN

MIN_LINE_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

VOLTAGE=1.05V

=PP3V3_S3_FET

=PP5V_S3_REG

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_DVDD0

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

=PP1V05_RMGT_FET

=PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_RMGT

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD1

=PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD

=PP3V3_S0_DPCONN =PP3V3_S0_FAN

=PP1V05_S0_CPU

=PP1V05_S0_FET

=PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_FSB =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_SMC_LS =PP1V05_S0_VMON

=PP0V75_S3_VTTREF

=PP3V42_G3H_REG

=PP5V_S0_FET

=PP3V3R1V8_S0_MCP_IFP_VDD

=PPVTT_S3_DDR_BUF

=PP0V75_S0_MEM_VTT_A

PP0V75_S0

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.25 mm

=PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

=PP0V75_S0_REG

MIN_NECK_WIDTH=0.20 MM VOLTAGE=0.9V

PPMCPCORE_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 MM

=PP3V3_S3_BT

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PP18V5_G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

=PP18V5_G3H_CHGR

=PP3V42_G3H_SMC=PPVCORE_S0_CPU

=PPMCPCORE_S0_REG

=PPVCORE_S0_CPU_REG

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.20 MM MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 MM

PPVCORE_S0_CPU

=PPVCORE_S0_MCP_VSENSE

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0

=PP5V_S0_DP_AUX_MUX =PP5V_S0_FAN =PP5V_S0_KBDLED =PP5V_S0_LPCPLUS

VOLTAGE=1.8V

PP1V5_S3

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP1V5_S3_REG

=PP1V5_S3_P1V5S0FET

=PP1V5_S3_MEM_B

=PP1V5_S3_MEMRESET

=PP5V_S0_CPU_IMVP

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

PP5V_S0

MIN_LINE_WIDTH=0.25 mm

=PP1V5_S3_MEM_A

=PP3V42_G3H_SMCVREF

=PP3V42_G3H_LPCPLUS

=PP3V42_G3H_CHGR

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_SMBUS_SMC_BSA

MIN_NECK_WIDTH=0.2 mm

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.42V

MAKE_BASE=TRUE

=PP3V42_G3H_IPD

=PP1V05_S5_P1V05S0FET =PP1V05_RMGT_P1V05RMGTFET

=PP3V3_S5_LCD

=PP3V3_S5_AIRPORT_AUX

MIN_NECK_WIDTH=0.25MM MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.5MM

PPDCIN_G3H

=PPVIN_G3H_P3V42G3H

=PP1V5_S0_FET

=PP1V5_S0_CPU

=PP1V05_S0_MCP_PEX_DVDD

=PP3V3_S5_REG

=PP3V3_RMGT_FET

=PP3V3_S0_IMVP

=PP1V5_S0_VMON =PP1V8R1V5_S0_MCP_MEM

MIN_LINE_WIDTH=0.25 mm

MAKE_BASE=TRUE

PP1V5_S0

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_MCP_GPIO =PP3V3_S5_P1V05FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P3V3S3FET =PP3V3_S5_PWRCTL =PP3V3_S5_ROM =PP3V3_S5_SMBUS_MCP_1 =PP3V3_S5_MEMRESET

=PP3V3_S5_P1V05RMGTFET

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP3V3_S5

VOLTAGE=3.3V

=PP3V3_S0_LCDBKLT

=PPVIN_S3_5VS3

=PPBUSB_G3H

=PPBUS_S0_LCDBKLT

=PPVIN_S0_AUDIO

=PPVIN_S5_3V3S5

=PPBUS_G3HRS5

=PP5V_S3_MCPREG

=PPDCIN_G3H

=PP1V05_S5_REG

=PPVCORE_S0_MCP

=PPBUSA_G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=12.6V

=PPVIN_G3H_DCIN

PP1V05_RMGT

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

PP3V3_RMGT

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

=PP5V_S3_P5VS0FET

=PP5V_S3_EXTUSB

=PP5V_S3_1V5S30V75S0

=PP5V_S3_VTTCLAMP

=PP5V_S3_MCPDDRFET

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S3

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_SMS

=PP3V3_S3_SMC

=PP3V3_S3_DDRREG =PP3V3_S3_MCPREG =PP3V3_S3_MCP_GPIO

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 mm

PP3V3_S3

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_P3V3RMGTFET

=PP1V05_S5_MCP_VDD_AUXC

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.25 mm

PP1V05_S5

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

PP0V75_S3

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 mm

=PP3V3_S0_MCP

=PP3V3_S0_LCD

=PP3V3_S0_MCP_GPIO =PP3V3_S0_MCP_PLL_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_PWRCTL =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_THRM_SNR

=PPVIN_S0_P1V8S0

=PP3V3_S0_VMON =PP3V3_S0_XDP

MIN_LINE_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

=PP3V3_S0_LPCPLUS =PP3V3_S0_HDD =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_SMC_LS =PP3V3_S0_MIC

=PP3V3_S0_FET

=PP1V8_S0_REG

12 11

22

33

10

21

64

32

31

66

20

22

20

70

22

70

22

9

13

23

22

49

23

70

70 58

40 11

70

46

70

30

70

28

70

11

22

70

19

48

70

58

35

22

58

70

22

70

21

18

56

12

70

22

53

6

54

51

50

38

59

42

57

17

25

6

57

55

16

22

57

22

17

16

21

24

61

46

6

57

22

8

17

7

22

19

40

56

54 24

57

17

25

33

6

33

57

54

6

34

6

49

39 10

51

50

6

43

6

60

6

38

41

6

54

57

29

26

50

6

27

40

41

58

37

42

6

38

57

59

34

6

49

57

10

7

55

57

50

56

15

6

17

57

56

41

42

26

57

6

62

55

44

63

6

55

43

51

49

53

21

44

6

49

70

57

37

54

57

6

42

47

40

54

51

20

6

57

21

6

70

20

59

17

22

23

24

42

45

52

56

6

41

36

42

20

40

59

57

52

OUT

IN

OUT OUT OUT OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU FSB FREQUENCY STRAPS

Extra FSB Pull-ups

Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa

LAN ALIASES

UNUSED ETHERNET RG/MII INTERFACE

USB ALIASES

EXTERNAL PORT A

CAMERA

PLACE CLIPS PER MCO ON TOPSIDE NEAR BATTERY CONNECTOR J6900

UNUSED USB PORTS

HDA PULL-DOWN

LVDS ALIASES

DACS ALIASES

UNUSED CRT & TV-OUT INTERFACE

EMI SPRING CLIPS

AIRPORT CARD AND TURBOMEM PRESENT SIGNAL

UNUSED GPU LANES

PCI-E ALIASES

UNUSED LVDS SIGNALS

UNUSED IPHS SIGNAL(FOR IPHONE JACK)

AUD_I2C_INT_L IS PU ON MCP PAGE

IR

BT (M93)

TRACKPAD(WELLSPRING)

STANDOFFS

BOSSES

SMC ALIASES

NO-CONNECT UNUSED SMC INTERFACE PORTS

DP HOTPLUG PULL-DOWN

FSB MHZ

266 133 200

(166)0 1 1

0 0 1 0 1 0

BSEL<2..0>

0 0 0

(RSVD)

(400)

333 100

1 1 1

1 1 0

1 0 1

1 0 0

MISC NC MCP79 ALIASES

NO_TEST

MEM ALIASES

UNUSED SATA ODD SIGNALS

SATA ALIASES

SC0900

1

PS-25N

CRITICAL

EMI-SPRING

Z0900

1

4.5OD2.0H-M1.6X0.35

Z0902

1

4.5OD2.0H-M1.6X0.35

Z0903

1

4.5OD2.0H-M1.6X0.35

Z0911

1

STDOFF-4.0OD2.4H-0.5-THNP

Z0912

1

STDOFF-4.0OD2.4H-0.5-THNP

Z0910

1

STDOFF-4.0OD2.4H-0.5-THNP

13

9

65

R0920

1

2

201

1/20W MF

5%

100K

R0940

1

2

201

MF

1/20W

5%

20K

RP0930

1 2 3 4

8 7 6 5

1/32W

5% 4X0201-HF

10K

RP0931

1 2 3 4

8 7 6 5

1/32W

10K

5% 4X0201-HF

RP0932

1 2 3 4

8 7 6 5

10K

5% 4X0201-HF

1/32W

R0999

1

2

1/20W

MF

201

5%

150

NO STUFF

R0998

1

2

201

150

5% 1/20W MF

NO STUFF

R0997

1

2

NO STUFF

201

200

5%

MF

1/20W

R0995

1

2

NO STUFF

1/20W

5%

220

201

MF

R0996

1

2

NO STUFF

62

201

MF

1/20W

5%

9

13 50 65

9

13 65

9

12 13 65

9

13 65

9

13 65

Z0901

1

4.5OD2.0H-M1.6X0.35

Z0904

1

4.5OD2.0H-M1.6X0.35

8

71

2.3.0

051-7631

SIGNAL ALIAS /RESET

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

ENET_RESET_L

MCP_CLK25M_BUF0_R

ENET_PWRDWN_L

ENET_MDC ENET_TX_CTRL ENET_TXD<3..0>

NC_ENET_TXD<3..0>

MAKE_BASE=TRUE

NC_ENET_RESET_L

ENET_CLK125M_RXCLK

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N

MAKE_BASE=TRUE

TP_SATA_ODD_R2D_C_N

MAKE_BASE=TRUE

TP_SATA_ODD_D2R_N

=PP1V05_S0_MCP_FSB

LVDS_IG_B_DATA_N<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2R_N<15:0>

MAKE_BASE=TRUE

NC_MEM_B_CKE<3>

TRUE

NC_SMC_PA0

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_MEM_A_CLK4P

MAKE_BASE=TRUE

NC_MEM_A_CLK4N

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK3P

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK3N

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CS_L<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CS_L<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CKE<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CKE<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK4P

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK4N

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK3P

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK3N

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CS_L<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CS_L<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_ODT<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_ODT<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CKE<2>

TRUE

TP_MEM_B_CS_L<2>

TP_MEM_B_ODT<3> TP_MEM_B_CKE<2> TP_MEM_B_CKE<3>

TP_MEM_B_CS_L<3> TP_MEM_B_ODT<2>

TP_MEM_B_CLK4N TP_MEM_B_CLK3P TP_MEM_B_CLK3N

TP_MEM_A_CKE<2> TP_MEM_A_CKE<3> TP_MEM_B_CLK4P

TP_MEM_A_CLK3N TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3>

TP_MEM_A_CLK3P

TP_MEM_A_CLK4N

TP_MEM_A_CLK4P

TP_ODD_PWR_EN_L

MAKE_BASE=TRUE

TP_FW_PME_L

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

ODD_PWR_EN_L

FW_PME_L

CPU_PECI_MCP

FSB_BREQ0_L

CPU_DPRSTP_L

=MCP_BSEL<0:2>

FSB_CPURST_L CPU_INTR CPU_NMI

TP_SATA_ODD_R2D_C_P

MAKE_BASE=TRUE

TP_USB_EXCARD_P

MAKE_BASE=TRUE

TP_SATA_ODD_D2R_P

MAKE_BASE=TRUE

TP_USB_EXTB_N

SATA_ODD_D2R_P SATA_ODD_D2R_N

HPLUG_DET2

MAKE_BASE=TRUE

=DVI_HPD_GMUX_INT

NC_LVDS_IG_B_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_ESTARLDO_EN

SMC_P26

SMC_PA1

NC_SMC_PA1

TRUE

MAKE_BASE=TRUE

SMC_PA0

ENET_MDIO

=USB2_EXTA_P

MAKE_BASE=TRUE

USB_EXTA_P =USB2_EXTA_N =EXTAUSB_OC_L USB_EXTA_OC_L

MAKE_BASE=TRUE

=USB2_CAMERA_P

USB_CAMERA_P

MAKE_BASE=TRUE

=USB2_CAMERA_N

USB_CAMERA_N

MAKE_BASE=TRUE

USB_TPAD_P

MAKE_BASE=TRUE

=USB2_TPAD_N

USB_TPAD_N

MAKE_BASE=TRUE

=USB2_IR_P

USB_IR_P

MAKE_BASE=TRUE

USB_IR_N

MAKE_BASE=TRUE

USB_BT_N

MAKE_BASE=TRUE

=USB2_BT_P USB_BT_P

MAKE_BASE=TRUE

AUD_IPHS_SWITCH_EN

NC_ENET_PWRDWN_L

MAKE_BASE=TRUE

NC_ENET_MDC

MAKE_BASE=TRUE

SMC_ADAPTER_EN

MAKE_BASE=TRUE

SMC_ADAPTER_PRESENT

NC_LVDS_IG_A_DATA_P3

MAKE_BASE=TRUE

NO_TEST=TRUE

ENET_RXD<2>

MAKE_BASE=TRUE

NC_MCP_CLK25M_BUF0_R

USB_EXCARD_P

USB_EXTD_N

USB_MINI_P

MAKE_BASE=TRUE

TP_USB_EXTC_N

NC_ENEX_TX_CTRL

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<3>

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

PEG_CLK100M_N

PEG_CLK100M_P

USB_MINI_N

USB_EXCARD_N

MAKE_BASE=TRUE

TP_USB_EXTD_P

NC_LVDS_IG_A_DATA_N3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATA_P<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

=PEG_D2R_P<15:0>

MAKE_BASE=TRUE

TP_PEG_PRSNT_L

MAKE_BASE=TRUE

TP_PEG_CLKREQ_L

ENET_RXD<3>

ENET_RX_CTRL ENET_CLK125M_TXCLK MCP_MII_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

MCP_TV_DAC_RSET

LVDS_IG_B_CLK_P

CRT_IG_B_COMP_PB CRT_IG_HSYNC

CRT_IG_G_Y_Y

MCP_CLK27M_XTALOUT CRT_IG_R_C_PR

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2R_P<15:0>

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

TP_EXTGPU_PWR_EN

MAKE_BASE=TRUE

TP_EXTGPU_RESET_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15:0>

NC_LVDS_IG_B_DATA_N<3:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_IG_B_CLK_N

EXTGPU_RESET_L

EXTGPU_PWR_EN

=PEG_R2D_C_N<15:0>

=PEG_D2R_N<15:0>

PEG_PRSNT_L

=PEG_R2D_C_P<15:0>

PEG_CLKREQ_L

LVDS_IG_B_DATA_P<3:0>

USB_EXTC_N USB_EXTD_P

USB_EXTB_N

=USB2_BT_N

=USB2_IR_N

=USB2_TPAD_P

USB_EXTA_N

MAKE_BASE=TRUE

ENET_INTR_L

USB_EXTC_P

MAKE_BASE=TRUE

TP_USB_EXTC_P

PCIE_MINI_PRSNT_L PCIE_FC_PRSNT_L

USB_EXTB_P

MAKE_BASE=TRUE

TP_USB_EXCARD_N

TP_USB_MINI_N

MAKE_BASE=TRUE

TP_USB_MINI_P

MAKE_BASE=TRUE

TP_USB_EXTD_N

TP_USB_EXTB_P

MAKE_BASE=TRUE

CRT_IG_VSYNC

MAKE_BASE=TRUE

CPU_BSEL<0:2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLK_P

LVDS_IG_A_DATA_N<3>

ENET_RXD<0> ENET_RXD<1>

MAKE_BASE=TRUE

TRUE

NC_SMC_P41

SMC_P41

ESTARLDO_EN

MAKE_BASE=TRUE

TRUE

NC_SMC_P26

MAKE_BASE=TRUE

TRUE

NC_SMC_P67

SMC_BIL_BUTTON_L

NC_SMC_GFX_OVERTEMP_L

TRUE

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_L

TRUE

MAKE_BASE=TRUE

NC_EXCARD_OC_L

SMC_EXCARD_OC_L

NC_ALS_RIGHT

TRUE

MAKE_BASE=TRUE

ALS_RIGHT

NC_ALS_GAIN

TRUE

MAKE_BASE=TRUE

ALS_GAIN

TRUE

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

SMC_FAN_3_CTL

TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

SMC_FAN_2_CTL

NC_SMC_FAN_1_CTL

TRUE

MAKE_BASE=TRUE

SMC_FAN_1_CTL

TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

SMC_FAN_2_TACH

TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

SMC_FAN_1_TACH

NC_SMC_P24

TRUE

MAKE_BASE=TRUE

SMC_P24

NC_SMC_EXCARD_CP

TRUE

MAKE_BASE=TRUE

SMC_EXCARD_CP

MAKE_BASE=TRUE

TRUE

NC_SMC_PA5

SMC_PA5

MAKE_BASE=TRUE

TRUE

NC_SMC_GPU_ISENSE

SMC_GPU_ISENSE

NC_SMC_P10

MAKE_BASE=TRUE

TRUE

SMC_P10

NC_SMC_NB_DDR_ISENSE

MAKE_BASE=TRUE

TRUE

SMC_NB_DDR_ISENSE

NC_ALS_LEFT

MAKE_BASE=TRUE

TRUE

ALS_LEFT

NC_SMC_FWE

TRUE

MAKE_BASE=TRUE

SMC_FWE

SMC_EXCARD_PWR_EN

TRUE

NC_ISENSE_CAL_EN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SMC_ANALOG_ID

SMC_ANALOG_ID

TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

TRUE

NC_SMC_RSTGATE_L

ISENSE_CAL_EN

SMC_FAN_3_TACH

SMC_SMS_INT_L

MAKE_BASE=TRUE

=SMC_SMS_INT

SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM

VOLTAGE=0V

GND

22 21

40

13

67

68

38 68

68

39

68

67

68

67

68

38

68

67

17

19

7

17

15

20

18

13

19

17

39

17

37 19

37

37 19

59 19

19

6

19

6

19

34 19

18

20

34

17

68

19

17

16

19

68

16

17

16

17

68

19

34

6

19

17

68

19

17

39

40 39

39 20

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN

IN IN

IN

OUT

BI BI BI BI

D11*

D7*

D6*

D5*

D4*

D3*

D17*

D16*

DINV0*

DSTBP0*

DSTBN0*

D10*

D2*

SLP*

PWRGOOD

PSI*

GTLREF

DSTBP3*

DSTBP2*

DSTBN3*

DSTBN2*

DSTBN1*

DPWR*

DPSLP*

DPRSTP*

DINV3*

DINV2*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D53*

D52*

D51*

D50*

D49*

D48*

D47*

D46*

D45*

D44*

D43*

D42*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

D31*

D30*

D26*

D25*

D24*

D23*

D22*

D21*

D20*

D13*

D12*

D1*

D0*

COMP3

COMP2

COMP1

COMP0

BSEL2

BSEL1

BSEL0

D27*

D29*

D8*

DINV1*

DSTBP1*

D28*

D14* D15*

D9*

D19*

D18*

D41*

(2 OF 8)

DATA GRP 3

DATA GRP1

MISC

DATA GRP 0

DATA GRP 2

A6*

BR0*

BPM0*

DBR*

DEFER*

DBSY*

A7*

A15*

A14*

REQ2*

A17* A18*

PREQ*

IERR*

BPRI*

BNR*

A4*

TRST*

LINT1

TEST2

TEST4

A16*

A20M*

A3*

A30* A31* A32*

A34* A35*

A5*

A8*

ADSTB0*

ADSTB1*

BCLK1

BPM2* BPM3*

FERR*

HIT*

HITM*

IGNNE*

LINT0

RSVD7

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

TEST1

TEST3

TEST5 TEST6

PROCHOT*

REQ0* REQ1*

REQ3* REQ4*

SMI*

TCK

TDO

THERMTRIP*

THRMDA THRMDC

TMS

PRDY*

BPM1*

RS2*

RS1*

RS0*

RESET*

DRDY*

ADS*

A19* A20* A21*

A23*

A22*

A24* A25* A26* A27* A28* A29*

A33*

STPCLK*

A13*

A12*

A11*

BCLK0

TDI

TRDY*

LOCK*

INIT*

A10*

A9*

(1 OF 8)

XDP/ITP SIGNALS

ADDR GROUP0ADDR GROUP1

THERMAL

H CLK

ICH

CONTROL

OUT

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SYNC FROM M97

CPU JTAG Support

PLACEMENT_NOTE (all 4 resistors):

R1000

1

2

MF

1/20W

1%

54.9

201

R1002

1

2

MF

1/20W

5%

68

201

R1005

1

2

1/20W

1%

MF

1K

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

201

R1006

1

2

2K

201

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

1% MF

1/20W

R1023

1

2

201

MF

1/20W

1%

54.9

Place within 12.7mm of CPU

R1022

1

2

201

MF

1/20W

1%

27.4

Place within 12.7mm of CPU

R1021

1

2

54.9

1%

1/20W

MF

201

Place within 12.7mm of CPU

R1020

1

2

201

MF

1/20W

1%

27.4

Place within 12.7mm of CPU

13 65

8

13 50 65

13 65

12 13 65

13 65

8

65

8

65

8

65

13 65

8

13 65

6

12 65

6

12 65

6

12 65

6

12 65

6

12 65

6

12 65

9

12 65

13 40 50 65

45

13 40 65

13 65

8

12 13 65

13 65

6 9

12 65

6 9

12 65

6 9

12 65

6 9

12 65

45

13 65

8

13 65

8

13 65

R1010

1 2

NO STUFF

201

0

1/20W

MF

5%

R1011

1

2

1K

MF

5%

1/20W

NO STUFF

201

R1001

1

2

1/20W

1%

MF

54.9

201

R1090

1 2

201

MF

1/20W

54.9

1%

R1091

1 2

201

54.9

1/20W

MF

1%

R1093

1 2

1/20W

201

54.9

MF

1%

13 65

R1094

1 2

201

649

1/20W

MF

1%

R1012

1

2

NO STUFF

1/20W

5%

1K

MF 201

C1014

1

2

0.1uF

16V

10%

X5R

NO STUFF

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

402

U1000

OMIT

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

BGA

PENRYN-SFF

R1092

1 2

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

201

1%

MF

1/20W

54.9

U1000

AC5 AD2 AD4 AA5 AE5 AB2 AC1

AN1 AK4 AG1 AT4

C7

AK2 AT2 AH2 AF4 AJ5 AH4 AM4 AP4 AR5

P2

AJ1 AL1 AM2 AU5 AP2 AR1

V4 W1

T4 AA1 AB4

T2

M4

Y4

AN5

A35 C35

J5

AY8 BA7 BA5 AY2

L5

M2

J7

J1

N5 F38

D4

H2 F2

B40

F10

D8

C9

C5

N1

AV10 AV2

D38

R1

R5

U1

P4

W5

G5 K2 H4 K4

H8 V2 Y2 AG5 AL5

J9 F4

E5

F8

AV4 AW7 AU1

E37 D40 C43

AE41 AY10 AC43

B10

BB34 BD34

AW5

L1

AV8

PENRYN-SFF

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

OMIT

BGA

6

12 24

13 65

71

051-7631

2.3.0

9

CPU FSB

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

CPU_GTLREF

FSB_D_L<24>

FSB_D_L<23>

FSB_DSTB_L_N<2>

CPU_DPRSTP_L

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<21>

CPU_PROCHOT_L

PM_THRMTRIP_L

FSB_A_L<6>

FSB_BREQ0_L

XDP_BPM_L<0>

XDP_DBRESET_L

FSB_DEFER_L

FSB_DBSY_L

FSB_A_L<7>

FSB_A_L<15>

FSB_A_L<14>

FSB_REQ_L<2>

FSB_A_L<17> FSB_A_L<18>

XDP_BPM_L<5>

CPU_IERR_L

FSB_BPRI_L

FSB_BNR_L

FSB_A_L<4>

XDP_TRST_L

CPU_NMI

CPU_TEST2

CPU_TEST4

FSB_A_L<16>

CPU_A20M_L

FSB_A_L<3>

FSB_A_L<30> FSB_A_L<31> FSB_A_L<32>

FSB_A_L<34> FSB_A_L<35>

FSB_A_L<5>

FSB_A_L<8>

FSB_ADSTB_L<0>

FSB_ADSTB_L<1>

FSB_CLK_CPU_N

XDP_BPM_L<2> XDP_BPM_L<3>

CPU_FERR_L

FSB_HIT_L FSB_HITM_L

CPU_IGNNE_L

CPU_INTR

NC_CPU_RSVD_J9

NC_CPU_RSVD_F4 NC_CPU_RSVD_H8 NC_CPU_RSVD_V2 NC_CPU_RSVD_Y2 NC_CPU_RSVD_AG5

NC_CPU_RSVD_AL5

CPU_TEST1

TP_CPU_TEST3

TP_CPU_TEST5 TP_CPU_TEST6

FSB_REQ_L<0> FSB_REQ_L<1>

FSB_REQ_L<3> FSB_REQ_L<4>

CPU_SMI_L

XDP_TCK

XDP_TDO

CPU_THERMD_P CPU_THERMD_N

XDP_BPM_L<4>

XDP_BPM_L<1>

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

FSB_DRDY_L

FSB_ADS_L

FSB_A_L<19> FSB_A_L<20> FSB_A_L<21>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>

FSB_A_L<33>

CPU_STPCLK_L

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_CLK_CPU_P

XDP_TDI

FSB_TRDY_L

FSB_LOCK_L

CPU_INIT_L

FSB_A_L<10>

FSB_A_L<9>

XDP_TMS

XDP_TCK

XDP_TRST_L

XDP_TDI

XDP_TDO

FSB_D_L<41>

FSB_D_L<18> FSB_D_L<19>

FSB_D_L<9>

FSB_D_L<15>

FSB_D_L<14>

FSB_DSTB_L_P<1> FSB_DINV_L<1>

FSB_D_L<8>

FSB_D_L<29>

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

CPU_COMP<3>

FSB_D_L<0> FSB_D_L<1>

FSB_D_L<12> FSB_D_L<13>

FSB_D_L<20>

FSB_D_L<22>

FSB_D_L<25>

FSB_D_L<30> FSB_D_L<31>

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40>

FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47>

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_DINV_L<2>

CPU_DPSLP_L FSB_DPWR_L

FSB_DSTB_L_N<1> FSB_DSTB_L_N<3>

FSB_DSTB_L_P<2>

TP_CPU_PSI_L

CPU_PWRGD FSB_CPUSLP_L

FSB_D_L<2>

FSB_D_L<10>

FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<16> FSB_D_L<17>

FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7>

FSB_D_L<11>

=PP1V05_S0_CPU

XDP_TMS

CPU_TEST4

CPU_TEST1 CPU_TEST2

12

65

11

65

12

65

10

12

65

9

12

7

9

25

65

9

6

9

65

6

9

VSSVSS

(4 OF 8)

VSSVSS

(5 OF 8)

VSS VSS

(6 OF 8)

VCC VCC

(7 OF 8)

VCCP VCCP

(8 OF 8)

OUT

OUT OUT

VCCA

VID

VCC

VCCP

(3 OF 8)

VSSSENSE

VCCSENSE

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

ZO=27.4 OHM DIFFERENTIAL TRACE ROUTING.

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE

VCCA=1.5 ONLY

0.130A

(CPU IO POWER 1.05V)

27A

(CPU CORE POWER)

WITHIN 1 INCH OF CPU W/ NO STUB

LAYOUT NOTE: PLACE R1100 AND R1101

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB)

BETWEEN VCCSENSE AND VSSSENSE

TO CONNECT A DIFFERENTIAL PROBE

(CPU INTERNAL PLL POWER 1.5V)

2.5A

U1000

B42 H42

P42

G29 E27 E29 N31 L31 J31 N27 N29 L27 L29

AD42

J27 J29 W31 W27 W29 U31 R31 U27 U29 R27

AB42

R29 AC31 AA31 AC27 AC29 AA27 AA29 AJ31 AG31 AE31

Y42

AJ27 AJ29 AG27 AG29 AE27 AE29 AR31 AR27 AR29 AN31

AK42

AL31 AN27 AN29 AL27 AL29 AW31 AU31 AW27 AW29 AU27

AH42

AU29 BC31 BA31 BC27 BC29 BA27 BA29 C25 C23 C21

AF42

G21 G23 G25

AP42 AM42 AY42

F42

AV42 AT42 AV44 AY44 BB42 BA43

C39 H38 G37 E39

D42

N39 M38 L39 J39 W39 U39 T38

R39 AD38 AC39

D44

AA39

Y38 AJ39 AH38 AG39 AE39 AR37 AR39 AN39 AM38

F44

AL39 AW37 AW39 AU37 AU39 AT38 BD38 BD40 BC41 BA39

M42

B36

D36

H34

M36

M34

K34

T36

V34

T34

P34

K42

AD36

Y36 AD34 AB34

Y34 AK34 AH36 AH34 AF34 AR35

V42

AM36

AP34 AM34 AV36 AT36 AY34 AW33 AW35 AV34 AU35

T42

BD36 BB36 BC33 BA33 C31 C29 C27 G31 E31 G27

OMIT

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

PENRYN-SFF

BGA

U1000

E21 E23 E25 N21 N23 N25 L21 L23 L25 J21 J23 J25 W21 W23 W25 U21 U23 U25 R21 R23

R25 AC21 AC23 AC25 AA21 AA23 AA25 AJ21 AJ23 AJ25 AG21 AG23 AG25 AE21 AE23 AE25 AR21 AR23 AR25 AN21 AN23 AN25 AL21 AL23 AL25 AW21 AW23 AW25 AU21 AU23 AU25 BC21 BC23 BC25 BA21 BA23 BA25

C19

C17

G17

G19

E17

E19

N17

N19

L17

L19

J17

J19

W17

W19

U17

U19

R17

R19 AC17 AC19 AA17 AA19 AJ17 AJ19 AG17 AG19

AE17 AE19 AR17 AR19 AN17 AN19 AL17 AL19 AW17 AW19 AU17 AU19 BC17 BC19 BA17 BA19 C15 C11 H10 G15 E15 M10 N15 L15 J15 M12 T10 W15 U15 R15 T12 AD10 Y10 AC15 AA15 AD12 Y12 AH10 AJ15 AG15 AE15 AH12 AM10 AR15 AN15 AL15 AM12 AT10 AW15 AU15 AY12 AW11 AW13 AV12 AT12 BC15 BA15 BC11

BB12 BA11 BA13 B6 H6 G9 F6 E9 D6 M6 M8 K6 K8 U5 V6 V8 T6 T8 P6 P8 AD6 AD8 AB6 AB8

OMIT

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

PENRYN-SFF

BGA

U1000

Y6

Y8 AK6 AK8 AH6 AH8 AF6 AF8 AP6 AP8 AM6 AM8 AY6 AW9 AU7 AV6 AU9 AT6 AT8 BD6 BC9 BB6 BA9

C3

B4

G3

E3

D2

N3

L3

J3

W3

U3

R3 AC3 AA3

AJ3 AG3 AE3 AR3 AN3 AL3 AW3 AU3 BD4 BC3 BB2 BA3 G1 E1 AW1 BA1 A39 A41 A31 A27 A29 A21 A23 A25 A17 A19 A15 A11 A9 A5 A7

OMIT

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

PENRYN-SFF

BGA

U1000

BD30 BB28 BB30

B24 B22 H22 H24 F22 F24 D24 D22 M22 M24 K22 K24 V22 V24 T22 T24 P22

P24 AD22 AD24 AB22 AB24

Y22

Y24 AK22 AK24 AH22 AH24 AF22 AF24 AP22 AP24 AM22 AM24 AY22 AY24 AV22 AV24 AT22 AT24 BD22 BD24 BB22 BB24

B20

B18

B16

H20

F20

D20

H16

H18

F16

F18

D18

D16

M20

K20 M16 M18 K16 K18 V20 T20 P20 V16 V18 T16 T18 P16 P18 AD20 AB20 Y20 AD16 AD18 AB16 AB18 Y16 Y18 AK20 AK16 AK18 AH20 AF20 AH16 AH18 AF16 AF18 AP20 AM20 AP16 AP18 AM16 AM18 AY20 AV20 AT20 AY16 AY18 AV16 AV18 AT16 AT18 BD20 BB20 BD16 BD18 BB16 BB18 AP14 AM14 AY14 AV14 AT14 BD14 BB14

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

OMIT

PENRYN-SFF

BGA

U1000

AH14 AG11 AG13 AF12 AF14 AE11 AE13 AP10 AR11 AR13 AP12 AN11 AN13 AL11 AL13 AU11 AU13 N7 N9 L7 L9 W7 W9 U7 U9 R7 R9 AC7 AC9 AA7 AA9 AJ7 AJ9 AG7 AG9 AE7 AE9 AR7 AR9 AN7 AN9 AL7 AL9 A33 A13

AE37 AP38 AN37 AL37

C33 B32 H36 F36 G35 F34 E33 E35 D32 K36 N35 L35 J35 W35 V36 P36 U35

R35 AB36 AC35 AA35 AK36 AF36 AJ35 AG35 AE35 AP36 AN35 AL35

C13

B14

B12

H12

H14

G11

G13

F12

F14

E11

E13

D14

D12

K10

N11

N13

M14

L11

L13

K12

K14

J11

J13

V10

P10

W11

W13

V12

V14

U11

U13

T14

R11

R13 P12 P14 AB10 AD14 AC11 AC13 AB12 AB14 AA11 AA13 Y14 AK10 AF10 AK12 AK14 AJ11 AJ13

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

OMIT

PENRYN-SFF

BGA

50 65

R1100

1

2

1% 1/20W

201

MF

100

R1101

1

2

201

MF

1/20W

1%

100

50 65

11 50 65

U1000

H32 G33

U33 T32 R33

P32 AD32 AC33 AB32 AA33

Y32 AK32

F32

AJ33 AH32 AG33 AF32 AE33 AR33 AP32 AN33 AM32 AL33

N33

AY32 AV32 AU33 AT32 AT34 BD32 BB32

B26

B30

B28

M32

H26

F26

D26

H28

H30

F28

F30

D30

D28

M26

L33

K26

M28

M30

K28

K30

V26

T26

P26

V28

V30

K32

T28

T30

P28

P30 AD26 AB26

Y26

AD28 AD30 AB28

J33

AB30 Y28 Y30 AK26 AH26 AF26 AK28 AK30 AH28 AH30

W33

AF28 AF30 AP26 AM26 AP28 AP30 AM28 AM30 AY26 AV26

V32

AT26 AY28 AY30 AV28 AV30 AT28 AT30 BD26 BB26 BD28

B34 D34

N37 L37

AB38 AA37 AK38 AJ37 AG37 AF38

K38 J37 W37 V38 U37 R37 P38 AC37

BD12

BD8 BC7 BB10 BB8 BC5 BB4 AY4

BC13

OMIT

PDC-Q9YM-ES1-1.86-17W-1066-CO-6M

PENRYN-SFF

BGA

11 50 65

CPU Power & Ground

051-7631

7110

2.3.0

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VCCSENSE_N

12

11

64

10

64

10

11

9

11

9

10

7

10

7

11

7

6

7

6

7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

10UF 0603 = APN:138S0568 = MURATA,TAIYO,TDK,SAMSUNG

3x 330uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402

1x 10uF, 1x 0.01uF

LAYOUT NOTE: PLACE C1290 CLOSE TO CPU

PLACE C1281 NEAR PIN B34 OF U1000

VCCP (CPU I/O) DECOUPLING

1X 330UF, 12X 2.2UF

PLACE C1291-C1296 CLOSE TO FSB DATA PINS

VCCA (CPU AVdd) DECOUPLING

CPU VCORE HF AND BULK DECOUPLING

PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS

PLACE ON SAME SIDE AS CPU

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

CPU VCORE VID CONNECTIONS

LAYOUT NOTE:

LAYOUT NOTE: PLACE ON SAME SIDE AS CPU

Intel recommends 3x220UF @ 9mOHM

C1210

X5R

6.3V 603

10UF

CRITICAL

20%

OMIT

C1216

X5R

6.3V 603

CRITICAL

10UF

20%

OMIT

C1201

X5R

6.3V

10UF

603

20%

CRITICAL

OMIT

C1202

X5R

6.3V

CRITICAL

603

10UF

20%

OMIT

C1203

X5R

6.3V

CRITICAL

603

10UF

20%

OMIT

C1204

X5R

6.3V 603

10UF

20%

CRITICAL

OMIT

C1205

X5R

6.3V 603

CRITICAL

10UF

20%

OMIT

C1206

X5R

6.3V

CRITICAL

603

10UF

20%

OMIT

C1207

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1208

X5R

6.3V

CRITICAL

603

10UF

20%

OMIT

C1209

X5R

6.3V

CRITICAL

603

20%

10UF

OMIT

C1229

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1228

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1227

X5R

CRITICAL

6.3V

10UF

20%

603

OMIT

C1226

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1225

X5R

6.3V 603

CRITICAL

10UF

20%

OMIT

C1224

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1223

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1214

X5R

6.3V

10UF

CRITICAL

20%

603

OMIT

C1222

X5R

CRITICAL

6.3V

10UF

603

20%

OMIT

C1221

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1220

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1231

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1230

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1249

402-LF

6.3V

2.2UF

20% CERM

CRITICAL

OMIT

C1259

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1248

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1258

CRITICAL

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C1247

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1246

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1257

2.2UF

6.3V

20%

402-LF

CERM

CRITICAL

OMIT

C1256

402-LF

6.3V

2.2UF

20% CERM

CRITICAL

OMIT

C1245

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1244

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1255

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1254

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1243

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1253

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1242

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1241

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1252

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1251

6.3V

2.2UF

20% CERM

CRITICAL

402-LF

OMIT

C1240

6.3V CERM

CRITICAL

2.2UF

402-LF

20%

OMIT

C1250

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1267

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1266

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1265

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1264

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1263

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1262

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1261

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1260

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

OMIT

C1291

1

2

6.3V CERM

2.2UF

20%

402-LF

OMIT

C1292

1

2

6.3V CERM

2.2UF

20%

402-LF

OMIT

C1293

1

2

6.3V CERM

2.2UF

402-LF

20%

OMIT

C1294

1

2

6.3V CERM

2.2UF

402-LF

20%

OMIT

C1295

1

2

6.3V CERM

2.2UF

402-LF

20%

OMIT

C1296

1

2

6.3V CERM

2.2UF

402-LF

20%

OMIT

C1283

1

2

6.3V CERM

20%

2.2UF

402-LF

OMIT

C1288

1

2

6.3V CERM 402-LF

2.2UF

20%

OMIT

C1287

1

2

6.3V CERM 402-LF

2.2UF

20%

OMIT

C1286

1

2

6.3V CERM 402-LF

2.2UF

20%

OMIT

C1285

1

2

6.3V CERM

2.2UF

402-LF

20%

OMIT

C1284

1

2

6.3V CERM 402-LF

2.2UF

20%

OMIT

C1290

1

2

CASE-C2-SM

POLY-TANT

2.5V

330UF

20%

CRITICAL

C1213

X5R

6.3V 603

10UF

CRITICAL

20%

OMIT

C1212

X5R

6.3V

10UF

CRITICAL

20%

603

OMIT

C1211

X5R

6.3V

10UF

CRITICAL

603

20%

OMIT

C1219

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1200

X5R

6.3V 603

CRITICAL

10UF

20%

OMIT

C1215

X5R

6.3V

20%

10UF

603

CRITICAL

OMIT

C1217

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1218

X5R

6.3V

10UF

603

CRITICAL

20%

OMIT

C1281

1

2

10%

X5R

10V

0.01UF

201

C1280

1

2

X5R

6.3V

603

20%

10uF

OMIT

C1270

1

23

D2T-SM1

POLY-TANT

330UF

20%

CRITICAL

2.0V

C1271

1

23

D2T-SM1

20%

POLY-TANT

2.0V

CRITICAL

330UF

C1272

1

23

D2T-SM1

POLY-TANT

CRITICAL

2.0V

20%

330UF

CPU Decoupling & VID

71

2.3.0

SYNC_DATE=04/26/2006

SYNC_MASTER=MSARWAR

11

051-7631

IMVP6_VID<0..6>

MAKE_BASE=TRUE

CPU_VID<0..6>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

12 10

65

9

64

50

10

7

10

65

10

7

6

7

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

B1

OE*

VCCB

B2 B3 B4

GND

A4

A3

A2

A1

VCCA

OUT

IN IN IN IN

OUT

IN

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

To XDP connector and/or level translator

OBSDATA_A3

OBSFN_B0 OBSFN_B1

ITPCLK/HOOK4

OBSDATA_B0

OBSDATA_A2

MCP

U1400

U1000

CPU

TCK0

VCC_OBS_AB

HOOK3

SCL

SDA

HOOK2

HOOK1

TCK1

PWRGD/HOOK0

OBSDATA_B3

OBSDATA_B2

OBSDATA_A0

OBSFN_A1

OBSFN_A0

OBSDATA_B1

OBSDATA_A1

TMS

TDI

TRSTn

TDO

VCC_OBS_CD

OBSDATA_D3

ITPCLK#/HOOK5

RESET#/HOOK6 DBR#/HOOK7

OBSDATA_D2

XDP_PRESENT#

OBSDATA_C0

OBSFN_C0

OBSFN_D0

OBSDATA_D0

OBSDATA_C2

OBSFN_C1

OBSDATA_C3

OBSDATA_C1

OBSDATA_D1

OBSFN_D1

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

MCP79-specific pinout

XDP connector

From XDP connector

998-1571

9

13 65

R1399

1 2

201

MF

1/20W

5%

XDP

1K

6

20 42 68

6

20 42 68

R1305

1

2

201

MF

1/20W

54.9

1%

XDP

C1300

1

2

10%

0.1uF

X5R

XDP

6.3V

201

J1300

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

78 9

F-ST-SM

LTH-030-01-G-D-NOPEGS

CRITICAL

XDP_CONN

C1301

1

2

10%

X5R

XDP

0.1UF

6.3V

201

6 9

65

6 9

65

6 9

12 65

8 9

13 65

R1303

1 2

201

MF

1/20W

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1K

5%

XDP

6 9

65

6 9

65

6 9

65

6 9

65

6

12 20

6

12 20

6

12 20

6

18 68

6

18 68

6

18 68

6

18 68

6

18 68

6

18 68

6

18 68

6

18 68

12 20

6

12

6

13 65

6

13 65

6

12

6 9

12 65

6 9

12 65

6 9

12 65

6 9

24

C1316

1

2

201

X5R

6.3V

JTAG_ALLDEV

10%

0.1UF

U1310

2 3 4 5

10 9 8 7

6

12

1

11

JTAG_ALLDEV

UQFN

NLSV4T244

C1311

1

2

201

X5R

6.3V

10%

JTAG_ALLDEV

0.1UF

R1311

1

2

5% MF

1/20W

201

10K

JTAG_ALLDEV

R1312

1

2

1/20W

201

MF

5%

0

NO STUFF

6

12

R1313

1 2

MF

0

5%

1/20W

201

XDP

6 9

12 65

6 9

12 65

6 9

12 65

6 9

12 65

6

12

R1314

1 2

201

MF

1/20W

0

5%

XDP

6 9

12 65

6 9 12 65

eXtended Debug Port (XDP)

71

2.3.0

12

SYNC_MASTER=M97

051-7631

SYNC_DATE=02/04/2008

XDP_TDO_CONN

XDP_TDO

JTAG_MCP_TDO

XDP_TRST_L

=PP1V05_S0_CPU

JTAG_MCP_TDO_CONN

JTAG_MCP_TDI

FSB_CPURST_L

CPU_PWRGD

XDP_TMS

XDP_TCK XDP_TDI

=PP3V3_S0_XDP

XDP_TCK

XDP_TMS XDP_TRST_L

JTAG_LVL_TRANS_EN_L

JTAG_MCP_TMS JTAG_MCP_TRST_L

JTAG_MCP_TCK

JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L

MCP_DEBUG<0> MCP_DEBUG<1>

MCP_DEBUG<2> MCP_DEBUG<3>

JTAG_MCP_TMS

JTAG_MCP_TDI

MCP_DEBUG<5>

MCP_DEBUG<4>

MCP_DEBUG<6>

FSB_CLK_ITP_P

MCP_DEBUG<7>

=PP3V3_S0_XDP

FSB_CLK_ITP_N

XDP_CPURST_L

XDP_DBRESET_L

XDP_TDI

XDP_TRST_L

XDP_TDO_CONN

XDP_TMS

XDP_BPM_L<5> XDP_BPM_L<4>

XDP_BPM_L<3> XDP_BPM_L<2>

XDP_BPM_L<1> XDP_BPM_L<0>

TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B2

XDP_PWRGD

TP_XDP_OBSDATA_B3

XDP_OBS20

=PP1V05_S0_CPU

PM_LATRIGGER_L JTAG_MCP_TCK

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

12

11

10

9

20

12

20

12

9

65

7

12

7

12

20

7

65

7

9

20

6

12

6

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

IN

BI BI

CPU_A12#

V1P1_PLL_CPU

V1P1_PLL_FSB

V1P1_PLL_MCLK

V1P1_DLLDLCELL_AVDD

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3# CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_A24#

CPU_A4#

CPU_REQ1#

CPU_BR1#

FSB

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Loop-back clock for delay matching.

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

270 mA (A01)

206 mA

15 mA

29 mA

20 mA

(MCP_BSEL<0>)

(MCP_BSEL<1>)

(MCP_BSEL<2>)

8

9

65

8 9

12 65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

8 9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

9

65

6

12 65

6

12 65

9

65

9

65

9

65

9

65

9

65

8 9

65

8 9

65

9

65

9

12 65

9

65

9

65

9

65

9

65

8 9

50 65

9

40 50 65

9

40 65

9

65

9

65

R1436

1

2

MF 201

1% 1/20W

49.9

R1431

1

2

49.9

MF

201

1%

1/20W

R1430

1

2

1/20W

1%

201

MF

49.9

R1435

1

2

MF 201

1% 1/20W

49.9

R1422

1

2

201

MF

NO STUFF

1/20W

5%

1K

R1421

1

2

201

MF

1/20W

5%

NO STUFF

1K

R1420

1

2

201

MF

1/20W

NO STUFF

5%

1K

R1415

1

2

201

1/20W

MF

5%

62

R1410

1

2

201

1/20W

MF

1%

54.9

R1440

1

2

NO STUFF

5%

MF 201

1/20W

150

R1416

1

2

1/20W MF 201

5%

62

U1400

BV60 BW61

BN59

BP58

BU59

BT58

BP60

BN61

BM56

BN57

AV60 AV58 AW61 AR61 AW59 AT58 AU59 AU57 AP56 AM54 AY56

BG61

AP54 AY54 AM56 AK56 AN55 AL57 AR55 AV54 AW55

AH60

AN57 AR57 AT56 BA57 AV56 AW57

AM60 AN59 AL59 AR59 AT60 AK60

AH56

AP60 AT54

AH54

AY60

BB60 AV52

C59

C61

E59

BL59

BU61

AG59 AD58

V58 U59 V60 AD60 W59 Y60 AF56 AC57 AB54 V56

AE59

AD54 AA55 AG57 AD56 V54 U55 T56 U57 W57 Y54

AA61

Y56 AC55 R55 R57 G57 L57 H56 J57 K56 E57

AF58

M54 P56 N57 J55 L55 T54 P54 M56 M60 P58

AC59

R59 P60 M58 R61 H60 H58 F60 T60 F58 J59

AG61

L61 J61 E61 N59

AF60 Y58 AA59

U61

AE57

F56

G59

AK54

AF54

BH58

BT60 BM60

AJ57

AB60

AB56

H54

L59

AC61

AA57

J53

K60

BH60

AG55 AJ55

BC59 BK60 BF60

BG59

BB58

B60

BJ59

BR59

AJ61 AK58 AM58 AJ59 AN61

D60

BA59 BA61 BE61

BK58

BE59

BD58

BL61

BD60

AR37

AR43

AR41

AR39

BGA

MCP79U

(1 OF 12)

OMIT

8

SYNC_MASTER=M97

13 71

051-7631

MCP CPU Interface

SYNC_DATE=02/04/2008

2.3.0

CPU_PECI_MCP

FSB_LOCK_L

CPU_PROCHOT_L

PM_THRMTRIP_L CPU_FERR_L

FSB_CLK_ITP_N

FSB_CLK_CPU_N

FSB_BPRI_L

FSB_D_L<54> FSB_D_L<55>

FSB_ADS_L FSB_BNR_L

=PP1V05_S0_MCP_FSB

FSB_BREQ1_L

FSB_D_L<63>

FSB_A_L<12>

PP1V05_S0_MCP_PLL_FSB

FSB_BREQ0_L

FSB_CLK_MCP_N

FSB_REQ_L<4>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<34>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32>

FSB_A_L<22> FSB_A_L<23>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_DINV_L<3>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_DPWR_L

FSB_RS_L<1>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

FSB_TRDY_L

=MCP_BSEL<0>

FSB_RS_L<2>

=MCP_BSEL<1>

FSB_CLK_MCP_P

CPU_PWRGD

FSB_DSTB_L_P<0>

FSB_DSTB_L_P<1>

FSB_DINV_L<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<0>

FSB_DINV_L<2>

FSB_DSTB_L_P<2> FSB_DSTB_L_N<2>

FSB_DSTB_L_P<3> FSB_DSTB_L_N<3>

FSB_A_L<3>

FSB_A_L<5>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<6> FSB_A_L<7>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<11>

FSB_A_L<15> FSB_A_L<16>

FSB_A_L<19>

FSB_A_L<17> FSB_A_L<18>

FSB_A_L<20> FSB_A_L<21>

FSB_A_L<35>

FSB_A_L<33>

FSB_ADSTB_L<0>

FSB_REQ_L<0>

FSB_HIT_L FSB_HITM_L

MCP_CPU_COMP_GND

FSB_D_L<0> FSB_D_L<1>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<4> FSB_D_L<5> FSB_D_L<6>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<9>

FSB_D_L<15>

FSB_D_L<17> FSB_D_L<18>

FSB_D_L<16>

FSB_D_L<19> FSB_D_L<20> FSB_D_L<21>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40> FSB_D_L<41>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47>

FSB_D_L<52> FSB_D_L<53>

FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59>

FSB_DEFER_L

FSB_CLK_CPU_P

FSB_CLK_ITP_P

CPU_A20M_L

CPU_NMI

CPU_INTR

CPU_SMI_L

FSB_CPURST_L

FSB_CPUSLP_L CPU_DPSLP_L

CPU_STPCLK_L CPU_DPRSTP_L

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_ADSTB_L<1>

CPU_IGNNE_L CPU_INIT_L

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<0>

FSB_A_L<10>

=MCP_BSEL<2>

FSB_DBSY_L FSB_DRDY_L

FSB_A_L<24>

FSB_A_L<4>

FSB_REQ_L<1>

=PP1V05_S0_MCP_FSB

22

21

13

8

70

8

7

65

22

65

7

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

NC

MCLK0A_0_P MCLK0A_0_N

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_1_N

MCLK0A_1_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

MCAS0#

MRAS0#

MDQS0_7_P

MDQ0_1

MEMORY PARTITION 0

0A

MEMORY

CONTROL

NC

MCLK1A_1_N

MCLK1A_1_P

MCLK1A_0_P MCLK1A_0_N

MDQ1_18

MA1_8

MA1_5

MDQ1_6

MDQ1_7

MDQ1_24

MA1_0

MDQ1_21

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25

MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_8

MDQ1_9

MDQ1_3 MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9

MA1_7 MA1_6

MA1_4 MA1_3 MA1_2 MA1_1

MCS1A_1# MCS1A_0#

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

1A

CONTROL

MEMORY

MEMORY PARTITION 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

28 66

27 66

28 66

27 66

27 28 33 66

33

27 28 33 66

28 66

27 66

30 66

29 66

30 66

29 66

30 66

29 30 33 66

33

29 30 33 66

30 66

29 66

30 66

29 66

30 66

29 66

U1400

BV26

BT24

BR23

BH28

BK24

BK26

BP28

BV24

BU25

BU23

BU27

BT26

BK28

BP26

BR27

BN27

BP24

BM26

BP22

BT22

BR21

BH32

BJ33

BJ29

BH30

BN23

BT20

BU57

BU55

BV44

BU43

BT48

BV48

BU49

BT44

BP48

BN45

BP40

BP42

BU51

BP46

BN47

BM42

BN41

BU41

BU39

BV38

BU35

BT42

BV42

BT52

BV36

BT40

BV20

BU19

BT14

BU13

BT18

BU21

BT16

BU15

BT56

BP16

BM14

BP10

BN11

BL13

BN17

BN15

BM12

BT10

BU11

BV56

BT6

BU5

BT12

BV12

BU7

BV6

BM8

BL7

BL5

BP4

BU53

BN9

BL9

BM6

BN5

BR51

BV50

BT50

BR53

BU45

BN43

BT38

BV14

BP12

BV8

BP6

BT54

BV54

BT46

BU47

BP44

BM44

BU37

BT36

BV18

BU17

BP14

BN13

BU9

BT8

BP8

BN7

BN21

BP20

BN25

BM24

AC41 AC43

OMIT

MCP79U

(2 OF 12)

BGA

U1400

BV30

BT32

BV32

BN33

BP36

BU31

BK36

BK32

BR33

BP34

BT34

BM36

BN35

BR35

BU33

BM32

BP32

BK34

BK30

BP38

BK38

BJ21

BH20

BH18

BJ17

BM38

BN37

BW57

CA57

CA45

BY46

BY52

BW51

BW47

BW45

BY42

CA41

BW37

BW43

BY54

BY44

BW41

BY38

BY36

CA33

BW35

BY28

CA29

CA35

BY34

CA53

BW33

BW31

BW23

BY26

CA23

BY20

BW25

BW27

CA21

BY24

BW59

BW17

BW15

CA15

BW11

BY18

BW19

BY12

BY16

BW9

BY6

BY58

CA3

BW5

CA11

BY10

BY4

CA5

BV2

BY2

BN1

BU1

BW53

BW3

BP2

BN3

BW1

CA59

CA47

CA51

BY60

BY48

CA39

BY32

CA27

CA17

CA9

BU3

BY56

BW55

BY50

BW49

BW39

BY40

BW29

BY30

BW21

BY22

BW13

BY14

BW7

BY8

BT2

BR3

BH34

BN39

BM30

BN31

AD42 AD44

BGA

MCP79U

(3 OF 12)

OMIT

71

051-7631

2.3.0

14

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

MCP Memory Interface

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<1> MEM_A_CKE<0>

MEM_A_ODT<1> MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<8> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<13> MEM_A_A<12>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_WE_L

MEM_A_DQS_P<0> MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DQ<0>

MEM_A_DM<7>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12>

MEM_A_DQ<16>

MEM_A_DQ<21> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<17>

MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22>

MEM_A_DQ<26>

MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<35> MEM_A_DQ<34>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<33>

MEM_A_DQ<41>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<40> MEM_A_DQ<39>

MEM_A_DQ<42>

MEM_A_DQ<47> MEM_A_DQ<46>

MEM_A_DQ<43>

MEM_A_DQ<45> MEM_A_DQ<44>

MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<52>

MEM_A_DQ<48>

MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<61> MEM_A_DQ<60>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_P<7>

MEM_A_DQ<1>

MEM_B_DQ<3>

MEM_B_CKE<1> MEM_B_CKE<0>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_N<2> MEM_B_DQS_P<1>

MEM_B_DQS_N<3> MEM_B_DQS_P<2>

MEM_B_DQS_N<4> MEM_B_DQS_P<3>

MEM_B_DQS_P<4>

MEM_B_DQS_P<5> MEM_B_DQS_N<5>

MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6>

MEM_B_DQS_P<7>

MEM_B_DQ<40>

MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<7>

MEM_B_DQ<0>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DQ<1>

MEM_B_DQ<5> MEM_B_DQ<4>

MEM_B_DQ<2>

MEM_B_DQ<9> MEM_B_DQ<8>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12>

MEM_B_DQ<16>

MEM_B_DQ<20> MEM_B_DQ<19>

MEM_B_DQ<17>

MEM_B_DQ<23>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<22>

MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<49>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<53>

MEM_B_DQ<57>

MEM_B_DQ<61>

MEM_B_DQ<58>

MEM_B_DQ<62>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<63>

MEM_B_DQ<21>

MEM_B_A<0>

MEM_B_DQ<24>

MEM_B_DQ<7> MEM_B_DQ<6>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_DQ<18>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

NC NC

MRESET0#

MODT1B_1

MCKE1B_0 MCKE1B_1

MODT1B_0

MCLK1B_0_N

MCS1B_0# MCS1B_1#

MCLK1B_0_P

MCLK1B_1_N

NC NC

GND56

GND58 GND59

MCLK0B_1_P

MCLK0B_0_P MCLK0B_0_N

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCS0B_1#

MEM_COMP_GND

MEM_COMP_1P8V

GND2 GND3 GND4

GND1

GND8 GND9

GND7

GND6

GND5

GND13 GND14

GND10

GND12

GND11

GND17

GND16

GND15

GND22 GND23

GND25

GND28 GND29

GND27

GND26

GND30

GND35

GND34

GND39 GND40

GND38

GND37

GND36

GND43

GND45

GND44

GND42

GND41

GND46 GND47

GND50

GND49

GND51

GND54

GND53

GND52

MCS0B_0#

V1P1_PLL_CORE

V1P1_PLL_DP

V1P1_PLL_XREF_XS

V1P1_PLL_V

MCLK0B_1_N

MCLK1B_1_P

GND48

GND64

GND55

GND57

GND60 GND61

GND63

GND62

V1P8_MEM_VDDP

GND33

GND32

GND31

GND20

GND19

GND18

GND24

GND21

NC

MEMORY CONTROL 1B

MEMORY CONTROL 0B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

17 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

87 mA (A01)

4771 mA (A01, DDR3)

TP or NC for DDR2.

39 mA

19 mA

12 mA

U1400

A13

A7

AB10

AB4 AB52 AB58 AC19 AC21 AC23 AC25 AC27

A19

AC29 AC31 AC33 AC35 AC37 AC39 AD16 AD48

AE1 AE13

A25

AE19 AE21 AE23 AE25 AE27 AE29 AE31 AE33 AE35 AE37

A31

AE39 AE43 AE49 AE55 AE61

AE7 AF16 AF48 AG13 AG19

A37

AG21 AG23 AG25 AG27 AG29

AG31 AG33 AG35 AG37 AG39

A43

AH10 AH12 AH16 AH4 AH46

A49

A55

A61

BK20 BP18

BU29 BR29

BH36

BJ35

BH38

BJ39

BJ23

BH24

BH26

BJ27

BM20 BN19

BT30 BN29

BP56 BR57

BK18 BM18

BP30 BT28

J27

AF42 AF44

AR23 AR25 AR27 AR29 AR31 AR33 AR35 AR53 AT10 AT16 AT18 AT20 AT24 AT26 AT28 AT32 AT34 AT42

AD46 AE41

W39

W41

V42

Y38

BD12 BD14

BD34 BD36 BD38 BD42 BD44 BF12 BF14 BF18 BF20 BF24

BD16

BF26 BF30 BF32 BF36 BF38 BF42 BF44

BD18 BD20 BD24 BD26 BD28 BD30 BD32

OMIT

(4 OF 12)

MCP79U

BGA

R1610

1

2

201

MF

1/20W

40.2

1%

R1611

1

2

201

40.2

1/20W

1%

MF

26

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

051-7631

2.3.0

7115

MCP Memory Misc

TP_MEM_A_CLK4P

TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3>

TP_MEM_B_CLK4P TP_MEM_B_CLK4N

TP_MEM_B_CLK3P

TP_MEM_B_CKE<2> TP_MEM_B_CKE<3>

TP_MEM_B_ODT<3>

TP_MEM_B_ODT<2>

TP_MEM_B_CS_L<3>

TP_MEM_B_CLK3N

TP_MEM_A_CKE<3>

TP_MEM_A_CKE<2>

TP_MEM_A_ODT<3>

TP_MEM_A_ODT<2>

TP_MEM_A_CLK3N

TP_MEM_A_CLK4N

=PP1V8R1V5_S0_MCP_MEM

PP1V05_S0_MCP_PLL_CORE

MCP_MEM_COMP_VDD MCP_MEM_COMP_GND

TP_MEM_A_CLK3P

TP_MEM_B_CS_L<2>

MCP_MEM_RESET_L

66

22

15

70

8

7

22

66

8

PE0_RX1_N

PE0_RX1_P

PE0_RX4_N

PE0_RX3_N

PE0_RX5_P

PE0_RX3_P

PE0_RX7_N

PE0_RX6_N PE0_RX7_P

PE0_RX5_N

PE0_RX9_N

PE0_RX8_N

PE0_RX10_P

PE0_RX8_P

PE0_RX10_N

PE0_RX13_P

PE0_RX15_N

PE0_RX15_P

PE0_RX13_N

PE0_PRSNT_16#

PE_WAKE#

PE1_RX2_N

PE1_RX3_P PE1_RX3_N

PEX_CLK_COMP

PE0_TX0_P

PE0_TX1_P PE0_TX1_N

PE0_TX0_N

PE0_TX2_P PE0_TX2_N

PE0_TX4_P

PE0_TX3_P PE0_TX3_N

PE0_TX5_P

PE0_TX4_N

PE0_TX6_P

PE0_TX5_N

PE0_TX6_N PE0_TX7_P PE0_TX7_N

PE0_TX9_P

PE0_TX8_P PE0_TX8_N

PE0_TX10_P

PE0_TX9_N

PE0_TX10_N PE0_TX11_P PE0_TX11_N

PE0_TX13_P

PE0_TX12_P PE0_TX12_N

PE0_TX14_P

PE0_TX13_N

PE0_TX15_P

PE0_TX14_N

PE0_TX15_N

PE0_REFCLK_P PE0_REFCLK_N

PE2_REFCLK_P

PE1_REFCLK_N

PE2_REFCLK_N

PE4_REFCLK_P PE4_REFCLK_N

PE1_TX0_P

PEX_RST0#

PE1_TX1_P

PE1_TX0_N

PE1_TX2_P

PE1_TX1_N

PE1_TX2_N

PE0_RX6_P

PE0_RX4_P

PE0_RX2_P

PE0_RX0_N

PE0_RX2_N

PE0_RX0_P

PE0_RX11_P

PE0_RX14_N

PE0_RX9_P

PE0_RX12_P

PE1_RX1_N

PE1_RX2_P

PE1_RX1_P

PE1_RX0_N

PE0_RX11_N

PE0_RX14_P

PE0_RX12_N

PE3_REFCLK_N

PE3_REFCLK_P

PE1_REFCLK_P

PE1_RX0_P

PEB_CLKREQ#

PEF_CLKREQ# PEF_PRSNT#

PEG_CLKREQ# PEG_PRSNT#

PEC_CLKREQ#

PED_CLKREQ#

PED_PRSNT#

PEE_CLKREQ# PEE_PRSNT#

PE1_TX3_N

PE1_TX3_P

V1P1_PEX_DVDD0

V1P1_PEX_DVDD1

V1P1_PLL_PEX

V1P1_PEX_AVDD1

V1P1_PEX_DVDD1

V1P1_PEX_AVDD0

NC

NC NC

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Int PU (S5)

Int PU

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

206 mA (A01)

57 mA (A01)

Int PU

84 mA (A01)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX

U1400

AW19

AW21

AW23 AW25

AW27 AW29

M12 E1

E3

AB2

AA3

AM6

AP6

AN3

AP2

AW3

AY2

AT4

AR5

AW5

AV6

BD2

BE1

U1

U3

AC3

AC1

P4

R5

AN1

AM2

AJ3

AJ1

AL3

AK2

AB6

AA5

AT2

AU3

AK6

AJ5

Y2

AA1

AV2

AW1

AL5

AK4

AT6

AR7

BA3

BA1

AV4

AU5

BB2

BC3

W3

V2

Y4

V4

T2

R3

AD4

AF4

AE3

AD2

AG3

AH2

AF2

AG1

AN5

AM4

AR3

AR1

F4

H4

N5

M4

K2

J3

R1

P2

F2

G3

N3

M2

L3

L1

P6

M6

H2

J1

H6

J5

G5

F6

C1

D2

J19

C5

J9

H8

D6

E7 E5

A3 B2

B4 A5

C3

J17

AA9 AB8

AF8 AG9

AC13 AC9 AD10 AD12 AD8 AE9 AF10 AF12

N11 N9 P10

AA13

AA7 AD14 AF14

W9 Y10 Y12

Y8

T6

U7

V14

BGA

MCP79U

OMIT

(5 OF 12)

8

67

8

67

8

34 67

6

34

34 67

8

R1710

1

2

201

MF

1/20W

2.37K

1%

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

24

8

SYNC_MASTER=M97

MCP PCIe Interfaces

16 71

2.3.0

051-7631

SYNC_DATE=02/04/2008

TP_MCP_GPIO_17

PCIE_WAKE_L

=PP1V05_S0_MCP_PEX_AVDD0

TP_PCIE_CLK100M_FC_N

TP_PCIE_FC_R2D_C_P

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_R2D_C_P

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_DVDD0

MCP_PEX_CLK_COMP

TP_PCIE_FC_D2R_N

TP_PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_N

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<1>

=PEG_D2R_P<1>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_P<5>

=PEG_D2R_P<3>

=PEG_D2R_N<7>

=PEG_D2R_N<6> =PEG_D2R_P<7>

=PEG_D2R_N<5>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_P<10>

=PEG_D2R_P<8>

=PEG_D2R_N<10>

=PEG_D2R_P<13>

=PEG_D2R_N<15>

=PEG_D2R_P<15>

=PEG_D2R_N<13>

PEG_PRSNT_L

TP_PCIE_EXCARD_D2R_N

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1> =PEG_R2D_C_N<1>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<2> =PEG_R2D_C_N<2>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3> =PEG_R2D_C_N<3>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<6> =PEG_R2D_C_P<7> =PEG_R2D_C_N<7>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<8> =PEG_R2D_C_N<8>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<10> =PEG_R2D_C_P<11> =PEG_R2D_C_N<11>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<12> =PEG_R2D_C_N<12>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<15> =PEG_R2D_C_N<15>

PEG_CLK100M_N

TP_PCIE_CLK100M_FW_P

PCIE_CLK100M_MINI_N

TP_PCIE_CLK100M_FW_N

TP_PCIE_CLK100M_FC_P

PCIE_MINI_R2D_C_N

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2>

=PEG_D2R_N<0>

=PEG_D2R_N<2>

=PEG_D2R_P<0>

=PEG_D2R_P<11>

=PEG_D2R_N<14>

=PEG_D2R_P<9>

=PEG_D2R_P<12>

=PEG_D2R_N<11>

=PEG_D2R_P<14>

=PEG_D2R_N<12>

TP_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_MINI_P

MINI_CLKREQ_L

TP_FW_CLKREQ_L

TP_PCIE_FC_R2D_C_N

TP_PCIE_CLK100M_EXCARD_P

PEG_CLK100M_P

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<14>

TP_EXCARD_CLKREQ_L

TP_PCIE_FC_D2R_P

TP_PCIE_FW_D2R_N

TP_PCIE_EXCARD_PRSNT_L

PCIE_MINI_R2D_C_P

PCIE_RESET_L

PEG_CLKREQ_L

EXTGPU_PWR_EN

TP_PCIE_FC_PRSNT_L

TP_FC_CLKREQ_L

EXTGPU_RESET_L

TP_PCIE_EXCARD_D2R_P

TP_PCIE_FW_D2R_P

PCIE_MINI_D2R_N

PCIE_MINI_D2R_P

70

7

67

22

IN

BI

IN IN IN IN

IN IN

IN

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

OUT

HPLUG_DET3

HPLUG_DET2

VAP8_IFPA_VDD_0 V1P8_IFPB_VDD_1

V1P1_HDMI_VDD

V3P3_PLL_HDMI

V3P3_PLL_IFPAB

HDMI_TXD0_N

HDMI_TXC_P

XTALIN_TV

GPIO_6 GPIO_7

TV_DAC_GREEN

TV_DAC_HSYNC TV_DAC_VSYNC

TV_DAC_BLUE

NC NC

NC NC NC

NC

MII_RXD3

MII_RXDV

NC

V1P1_DUAL_MACPLL

V1P0_DUAL_RMGT

MII_TXD0 MII_TXD1

V3P3_DUAL_RMGT

V1P0_DUAL_RMGT

NC

RGMII_INTR

MII_TXCLK

MII_TXEN

MII_RXCLK

DDC_DATA2

DDC_CLK2

HDMI_TXD2_P HDMI_TXD2_N

HDMI_TXD1_P HDMI_TXD1_N

HDMI_TXD0_P

LCD_PANEL_PWR

LCD_BKL_ON

LCD_BKL_CTL

HDMI_TXC_N

RGMII_PWRDWN

MII_MDIO

MII_MDC

MII_TXD3

MII_TXD2

MII_RXD2

MII_RXD1

MII_RXD0

IFPA_TXD3_N

MII_VREF

MII_RESET#

TV_DAC_RSET

IFPAB_VPROBE

IFPAB_RSET

DDC_CLK3

DDC_DATA3

IFPB_TXD7_N

IFPB_TXD7_P

IFPB_TXD6_N

IFPB_TXD5_N IFPB_TXD6_P

IFPB_TXD4_N

IFPB_TXD4_P

IFPB_TXD5_P

IFPB_TXC_N

IFPB_TXC_P

IFPA_TXD2_N IFPA_TXD3_P

IFPA_TXD1_N

IFPA_TXD1_P

IFPA_TXD2_P

IFPA_TXD0_N

IFPA_TXD0_P

IFPA_TXC_P

TV_DAC_RED

DDC_CLK0

DDC_DATA0

BUF_25MHZ

HDMI_VPROBE

HDMI_RSET

DP_AUX_CH0_N

DP_AUX_CH0_P

TV_DAC_VREF

IFPA_TXC_N

XTALOUT_TV

MII_COMP_VDD MII_COMP_GND

NC

NC NC

DACS

LAN

FLAT PANEL

BI

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

C / Pr Y / Y Comp / Pb

RGB ONLY

131 mA (A01)

Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

5 mA (A01)

95 mA (A01)

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

8 mA

DP_IG_ML_P/N<2> DP_IG_ML_P/N<1>

NOTE: 20K pull-down required on DP_HOTPLUG_DET.

MCP79 requires a S5 pull-up.

190 mA (A01, 1.8V)

16 mA (A01)

83 mA (A01)

Okay to float XTALIN_TV and XTALOUT_TV.

DDC_CLK0/DDC_DATA0 pull-ups still required.

TV DAC Disable:

Okay to float all TV_DAC signals.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<0> DP_IG_DDC_CLK DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N

TP_DP_IG_AUX_CHP/N

TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

Interface Mode

TMDS/HDMI

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0>

MCP Signal

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_DDC_DATA

level-shifters.

TMDS_IG_HPD

=MCP_HDMI_HPD DP_IG_AUX_CH_P/N

8 mA

TV / Component

RGB DAC Disable:

MII, RGMII products will enable

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

LVDS: Power +VDD_IFPx at 1.8V

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<1>

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

63

59

62 63

60

60 67

8

60

23 67

8

R1810

1

2

49.9

1/20W

1%

201

MF

R1811

1

2

1%

201

49.9

MF

1/20W

60

8

U1400

B30

C43

G39

B44

F40

H38

A45

H50

J49

H18 F16

A59

E51

F50

F52

E53

B54

C53

H48

J47

A57

D42 B46

F48

E49

H44

J43

F46

E47

B52

C51

H46

J45

A51 B50

E43

F42

H42

J41

F44

E45

B48

C47

H40

J39

J37 C45 D44

H32

E33

H28

F28 E29

C35

B32

G29

A33 J29 A35 C31

D30

F32

E31 D32 J31 B34

C33

B36

BA19

BA23

BA25

BA27

BA29

BA31

BA33

BA35

AW31 AW33 AW35

AW39 AW41

D56

E55

A47

F54

H52 J51

E41

V28 W29

V30

T42

N41 P38

P28

T44

T38

F26 E27

OMIT

MCP79U

BGA

(6 OF 12)

R1861

1

2

100K

5%

201

MF

1/20W

R1860

1

2

100K

5%

MF

201

1/20W

41

R1820

1

2

1/20W

MF

201

47K

5%

59 67

6

59 67

6

59 67

6

59 67

6

59 67

6

59 67

6

59 67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

6

59

6

59

60

23 67

8

17 71

2.3.0

051-7631

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

MCP Ethernet & Graphics

LVDS_IG_A_DATA_N<1>

ENET_MDC ENET_MDIO

ENET_RESET_L

ENET_CLK125M_TXCLK ENET_TX_CTRL

ENET_PWRDWN_L

MCP_DDC_CLK0

MCP_MII_COMP_GND

MCP_TV_DAC_RSET MCP_TV_DAC_VREF

MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT

LPCPLUS_GPIO DP_IG_CA_DET

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N

=DVI_HPD_GMUX_INT

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_P<0>

DP_IG_AUX_CH_P DP_IG_AUX_CH_N

=PP3V3R1V8_S0_MCP_IFP_VDD

LVDS_IG_B_CLK_P

=PP3V3_S5_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

MCP_MII_COMP_VDD

LVDS_IG_A_CLK_N

MCP_HDMI_RSET MCP_HDMI_VPROBE

MCP_CLK25M_BUF0_R

CRT_IG_R_C_PR

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0>

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3>

=MCP_HDMI_DDC_DATA

=MCP_HDMI_DDC_CLK

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

MCP_MII_VREF

ENET_RXD<0> ENET_RXD<1> ENET_RXD<2>

ENET_TXD<2>

=MCP_HDMI_TXD_N<1>

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

ENET_CLK125M_RXCLK

ENET_INTR_L

=PP3V3_ENET_MCP_RMGT

ENET_TXD<1>

=PP1V05_ENET_MCP_RMGT

PP1V05_ENET_MCP_PLL_MAC

ENET_RX_CTRL

ENET_RXD<3>

CRT_IG_B_COMP_PB

CRT_IG_VSYNC

CRT_IG_HSYNC

CRT_IG_G_Y_Y

=MCP_HDMI_TXD_N<0>

PP3V3_S0_MCP_VPLL

=PP1V05_S0_MCP_HDMI_VDD

=MCP_HDMI_HPD

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1>

MCP_DDC_DATA0

ENET_TXD<3>

ENET_TXD<0>

20

22

20

22

23

19

17

18

17

22

70

23

8

7

7 8

8

7

8

7

22

23

7

8

OUT

BI BI BI BI

NC

LPC_DRQ0#

PCI_REQ1#

PCI_GNT4#

PCI_GNT3#

PCI_GNT2#

LPC_PWRDWN#

LPC_DRQ1#

PCI_CLKRUN#

PCI_REQ4#

PCI_REQ3#

PCI_REQ2#

PCI_REQ0#

GND129 GND130

GND128

GND127

GND126

GND124 GND125

GND123

GND122

GND121

GND118 GND119 GND120

GND117

GND116

GND113 GND114 GND115

GND112

GND111

GND110

GND108 GND109

GND107

GND106

GND105

GND103 GND104

GND101 GND102

GND100

GND98 GND99

LPC_AD2 LPC_AD3

LPC_CLK0

LPC_RESET0#

LPC_AD0 LPC_AD1

LPC_FRAME#

PCI_CLKIN

PCI_CLK0

PCI_CLK2

PCI_RESET1#

PCI_RESET0#

GND97

GND96

GND95

GND93 GND94

GND92

GND91

GND90

GND88 GND89

GND87

GND86

GND85

GND82 GND83 GND84

GND81

GND80

GND78 GND79

GND77

GND76

GND75

GND73 GND74

GND72

GND71

GND70

GND68 GND69

GND67

GND66

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD1 PCI_AD2 PCI_AD3

PCI_AD0

PCI_AD4

LPC_SERIRQ

GND65

NC

NCNC

GND LPC PCI

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FIXME: ADJUST PINOUT PER LAYOUT

Int PU (S5)

Int PU

FIXME: USED TO BE PM_LATRIGGER_L

Strap for Boot ROM Selection (See HDA_SDOUT)

39 41 68

24 68

39 41 68

U1400

AM48 AN13 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 AN39 AN53 AP10 AP12 AP16 AP4 AP42 AP44 AP46 AP48 AP52 AP58 AT14 AT30 AT36 AT38 AT48 AU1 AU13

AH48 AH52 AH58 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AJ39 AK16 AK48

AL1 AL13 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AL39 AL43 AL49 AL55 AL61

AL7 AM16

AM8 AK8 AK10 AR9

BB4

AN7

AN9

AJ7 AL9

E17

AT8

BA39

BA41

BA43

BA49

BA53

BA55

BA7

BA9

BB10

BB20

BB24

BB26

BB28

BB30

BB32

BB34

BB36

BB38

BB42

BB44

BB46

BB48

BB50

BB52

BB54

BB56

BB6

BB8

BC53

BC57 BC9

BD48

BD50

BD52

BD54

BD56

BD6

BD8

BE49

BE53

BE55

BE57

BE7

BE9

BC5

BK4

BE5

BH4

BE3

BA5

BJ3

BJ5

AM10

AG5

AG7

AH8

AE5 AC7 AF6

AJ9

AD6

AH6

AP8

AC5

G17 G21

BGA

MCP79U

OMIT

(7 OF 12)

39 41

39 41 24 68

39 41

R1910

1

2

201

22

5% 1/20W MF

PLACEMENT_NOTE=Place close to pin R8

18

R1965

1

2

1/20W MF 201

5%

10K

R1960

1 2

1/20W

201

5%

22

MF

24

18

8

18

6

12 68

6

12 68

6

12 68

6

12 68

6

12 68

6

12 68

6

12 68

6

12 68

RP1901

4 5

4X0201-HF

1/32W

5%

8.2K

RP1901

2 7

4X0201-HF

1/32W

5%

8.2K

RP1901

1 8

4X0201-HF

1/32W

5%

8.2K

RP1900

4 5

8.2K

4X0201-HF

1/32W

5%

RP1900

3 6

4X0201-HF

8.2K

5%

1/32W

R1961

1 2

201

MF

22

1/20W

5%

R1962

1 2

MF

22

1/20W

201

5%

R1963

1 2

22

1/20W

201

MF5%

R1964

1 2

5%

22

MF

201

1/20W

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

MCP PCI & LPC

18 71

2.3.0

051-7631

LPC_RESET_L

LPC_FRAME_L

=PP3V3_S0_MCP_GPIO

MCP_RS232_SIN_L

MCP_DEBUG<1> MCP_DEBUG<2>

MCP_DEBUG<4>

AUD_IPHS_SWITCH_EN

CRTMUX_SEL_TV_L

MCP_RS232_SOUT_L

PCI_REQ1_L

PCI_REQ0_L

LPC_CLK33M_SMC_R

LPC_AD_R<1>

LPC_FRAME_R_L

PCI_CLK33M_MCP

LPC_AD<1>

LPC_AD<0>

LPC_PWRDWN_L

LPC_AD_R<0>

PM_CLKRUN_L

TP_LPC_DRQ0_L

FW_PME_L

PCI_REQ1_L

TP_DPMUX_SEL_IG_L

TP_LVDSMUX_SEL_IG_L

MCP_RS232_SIN_L

PCI_REQ0_L

TP_PCI_CLK0

PCI_CLK33M_MCP_R

TP_PCI_RESET1_L

MEM_VTT_EN_R

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

MCP_DEBUG<3>

MCP_DEBUG<0>

LPC_SERIRQ

LPC_AD<2> LPC_AD<3>

LPC_AD_R<3>

LPC_AD_R<2>

20 17

68

7

18

41

68

8

18

68

BI BI

IN IN IN IN

NC

V3P3_PLL_USB

V1P1_SATA_AVDD1

V1P1_SATA_DVDD1 V1P1_SATA_DVDD1

NC

V1P1_PLL_SATA

GND131 GND132

NC

SATA_A1_RX_N

NC

NC NC

NC

USB6_N

USB_OC3#/GPIO_28/MGPIO

USB_OC2#/GPIO_27/MGPIO

USB_OC1#/GPIO_26

USB_OC0#/GPIO_25

SATA_A0_TX_N

SATA_A0_RX_N

USB3_N

USB3_P

GND135

GND137 GND138

SATA_A0_TX_P

SATA_A1_TX_N

SATA_A1_RX_P

SATA_TERMP

USB0_P

USB1_P USB1_N

USB0_N

USB2_P USB2_N

USB4_P USB4_N

USB5_N

USB6_P

USB7_P USB7_N

USB_RBIAS_GND

GND134

GND133

GND136

GND139 GND140 GND141 GND142

GND144

GND143

GND145 GND146 GND147

GND149

GND148

GND150 GND151 GND152

GND154

GND153

GND155 GND156 GND157

GND159

GND158

GND160

SATA_A1_TX_P

SATA_A0_RX_P

SATA_LED#

NC

USB5_P

SATA

USB

OUT OUT

IN

OUT OUT

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Wellspring Trackpad/Keyboard

127 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

AirPort (PCIe Mini-Card)

External D

External A

Camera

Bluetooth

IR

External B

84 mA (A01)

43 mA (A01)

19 mA (A01)

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

R2010

1

2

MF

1% 1/20W

201

2.49K

R2060

1

2

806

MF

1%

1/20W

201

R2053

1

2

5%

8.2K

MF

1/20W

201

R2052

1

2

201

1/20W

MF

5%

8.2K

R2051

1

2

201

MF

1/20W

5%

8.2K

R2050

1

2

201

1/20W

MF

5%

8.2K

U1400

AU19 AU25 AU31 AU37 AU43 AU49 AU55 AU61 AU7 AU9 AV14 AV8 AY10 AY4 AY52 AY58 BB12 BB14 BB16 BB18 BC1 BC13 BC19 BC21 BC23 BC25 BC27 BC29 BC31 BC33

BF48

BF50

BF54

BF56

BF6

BF8

BG5

BG53

BG7

BG9

BH10

BH16

BH46

BH48

BH50

BH52

BH54

BH56

BH6

BH8

BJ11

BJ41

BJ45

BJ53

BJ9

BK12

BK16

BK44

BK46

BK48 BK50

BK52

BK54

BK56

BK6

BK8

BL49

BG1 BF2

BG3

BH2

BL3 BM2

BK2

BL1

E9

AW7

E37

F36

F34

E35

C37

B38

B42

C41

E39

F38

H36

J35

C39

B40

J33

H34

F24 H24 E25 J23

A41

AP14

AR13 AT12 AV10

AW9

AV12 AW13

V36

MCP79U

OMIT

(8 OF 12)

BGA

36 67

8

SYNC_MASTER=M97

MCP SATA & USB

051-7631

2.3.0

7119

SYNC_DATE=02/04/2008

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

=PP3V3_S5_MCP_GPIO

USB_TPAD_P

SATA_HDD_D2R_P

MCP_USB_RBIAS_GND

USB_EXTB_N

USB_EXTB_P

USB_BT_P

USB_TPAD_N

USB_IR_N

USB_IR_P

USB_EXTD_N

USB_EXTD_P

USB_EXTA_N

USB_MINI_N

USB_MINI_P

USB_EXTA_P

MCP_SATA_TERMP

SATA_HDD_R2D_C_P

USB_CAMERA_P USB_CAMERA_N

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L

USB_BT_N

SATA_ODD_D2R_N

PP1V05_S0_MCP_PLL_SATA

=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDD

PP3V3_S0_MCP_PLL_USB

SATA_ODD_R2D_C_P

20 17

70

22

70

7

68

67

22

7

22

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

V3P3_DUAL_HDA V3P3_DUAL_HDA

GPIO_10 GPIO_11

GPIO_8 GPIO_9

CPUVDD_EN

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANRPM0/GPIO_60

SMB_DATA1/MSMB_DATA

SMB_DATA0

SMB_CLK0

GPIO_15

THERM_DIODE_N

THERM_DIODE_P

SLP_RMGT#

SLP_S5#

GPIO_12

GPIO_1

V1P1_PLL_SP_SPREF

V1P1_PLL_NV_H

HDA_RESET#

GPIO_5

GPIO_4

GPIO_3

GPIO_2

SUS_CLK/GPIO_34

EXT_SMI/GPIO_32#

FANCTL0/GPIO_61

SMB_ALERT#/GPIO_64

SMB_CLK1/MSMB_CLK

HDA_PULLDN_COMP

HDA_SDATA_IN0

A20GATE

SLP_S3#

CPU_DPRSLPVR

RSTBTN#

PWRBTN#

LLB#

LID#

INTRUDER#

PWRGD_SB PS_PWRGD

RTC_RST#

JTAG_TDO

JTAG_TDI

CPU_VLD

JTAG_TMS

JTAG_TCK

XTALIN

JTAG_TRST#

XTALOUT_RTC

XTALOUT

XTALIN_RTC

HDA_BITCLK

HDA_SYNC

SPKR

BUF_SIO_CLK

TEST_MODE_EN

PKG_TEST

KBRDRSTIN# SIO_PME#

HDA_SDATA_OUT

GPIO_13 GPIO_14

HDA

MISC

IN

OUT

IN

OUT

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SPI0

Int PD

42 MHz

31 MHz

BUF_SIO_CLK Frequency

HDA_SYNC

Int PD

Int PU (S5) Int PU (S5)

Int PU (S5) Int PU

14.31818 MHz

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

17 mA

20 mA

7 mA (A01)

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

25 MHz

0

SPI1 option.

LPC ROMs. So Apple designs will

0

124 MHz

0

1

0

SPI_CLKSPI_DO

0

1

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI1

I/F

HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

37 mA (A01)

Int PU (S5)

NOTE: MCP79 rev A01 does not support

Frequency

MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE

41 68

6

34 35 39 56

34 39 40 56

6

12 42 68

42 68

6

12 42 68

42 68

20 51

45

20

20 51

20 34

45

57

50 65

39

6

35 68

6

35 68

6

35 68

6

35 68

R2121

1

2

49.9K

201

1% 1/20W MF

R2120

1

2

201

MF

49.9K

1%

1/20W

R2190

1

2

1K

MF

1% 1/20W

201

24 68

39

R2170

1 2

22

5%

201

1/20W

MF

R2171

1 2

22

201

1/20W

5%

MF

R2173

1 2

201

1/20W

22

5%

MF

R2163

1

2

10K

MF 201

5% 1/20W

R2160

1

2

201

MF

8.2K

1/20W

5%

R2180

1

2

5%

10K

MF

BOOT_MODE_SAFE

1/20W

201

R2181

1

2

1/20W MF 201

10K

5%

BOOT_MODE_USER

R2172

1 2

MF

1/20W

22

5%

201

41

R2110

1

2

201

1% 1/20W MF

49.9

R2150

1

2

10K

5%

MF

1/20W

201

6

12

6

12

6

12

C2171

1

2

33PF

NP0-C0G

5% 25V

201

C2173

1

2

201

25V NPO

5%

10PF

C2170

1

2

33PF

NP0-C0G

5%

25V

201

C2172

1

2

201

NPO

25V

10PF

5%

U1400

B6

BD4

D12

D20 E19

F20

B10

C9

A9

D8

C21

E15 G15

J25

B8 F12 C11

J15

B14

B16 D14

A15 C15

C13

B12

A11

F14 H14

E13

C29

H22

J21 B22 F22 E21

C7

A27 B20

H26

A23

F18

G27

D18

A29

C23

H16

C19

C17

B24

A17

E23

B18

G23

H12

H20

A21

G11

E11

AP20 AP18

P20 T20

B26

B28

C25

C27

BGA

MCP79U

OMIT

(9 OF 12)

20

24 24

20 39

R2147

1

2

100K

5%

MF

1/20W

201

R2142

1

2

201

MF

5%

10K

1/20W

R2141

1

2

201

1/20W MF

5%

10K

R2157

1

2

201

1/20W MF

5%

22K

R2156

1

2

22K

5%

MF

1/20W

201

R2155

1

2

201

1/20W MF

5%

22K

R2195

1

2

201

1K

DRAM_4GB

1/20W MF

5%

20

R2197

1

2

201

1K

1/20W MF

5%

DRAM_SPD_2

R2151

1

2

5%

MF

1/20W

201

100K

R2158

1

2

MF

100K

201

1/20W

5%

R2143

1

2

10K

5%

MF

1/20W

201

R2182

1 2

201

MF

1/20W

5%

0

39

8

39 40

R2140

1

2

201

1/20W MF

5%

10K

24

39

24

41 68

051-7631

2.3.0

7120

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

MCP HDA & MISC

HDA_SDOUT_R HDA_BIT_CLK_R

=PP3V3_S0_MCP_GPIO

HDA_SYNC_R

ARB_DETECT

MLB_RAM_VENDOR_0

=PP3V3_S5_MCP_GPIO

AP_PWR_EN

MLB_RAM_SIZE_0

HDA_BIT_CLK

HDA_RST_L

MCP_VID<0> MCP_VID<1> MCP_VID<2>

=PP3V3R1V5_S0_MCP_HDA

PP3V3_G3_RTC

HDA_SDOUT

HDA_SYNC

HDA_RST_R_L HDA_SYNC_R

MEM_EVENT_L

AUD_I2C_INT_L

=PP3V3_S3_MCP_GPIO

=PP3V3_S0_MCP

MCP_SAFE_MODE

MCP_VID<1>

MCP_VID<0>

HDA_SDOUT_R

MCP_TEST_MODE_EN

TP_MCP_BUF_SIO_CLK

MCP_SPKR

HDA_BIT_CLK_R

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

JTAG_MCP_TRST_L

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

JTAG_MCP_TMS

MCP_CPU_VLD

JTAG_MCP_TDI JTAG_MCP_TDO

RTC_RST_L

MCP_PS_PWRGD

PM_RSMRST_L

PM_BATLOW_L

PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L

PM_DPRSLPVR

TP_SB_A20GATE

HDA_SDIN0

MCP_HDA_PULLDN_COMP

SMBUS_MCP_1_CLK

AP_PWR_EN

PM_CLK32K_SUSCLK_R

MLB_RAM_SIZE_0

MLB_RAM_VENDOR_0

AUD_I2C_INT_L

HDA_RST_R_L

PP1V05_S0_MCP_PLL_NV

=SPI_CS1_R_L_USE_MLB

PM_SLP_S4_L

MCP_THMDIODE_P MCP_THMDIODE_N

MCP_VID<2>

SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA

SMBUS_MCP_1_DATA

MCP_CPUVDD_EN

=PP3V3R1V5_S0_MCP_HDA

TP_MCP_LID_L

SM_INTRUDER_L

SMC_RUNTIME_SCI_L

SMC_WAKE_SCI_L

TP_MCP_KBDRSTIN_L

SMC_ADAPTER_EN

MEM_EVENT_L ODD_PWR_EN_L

SPI_MOSI_R

SPI_MISO

SPI_CLK_R

SPI_CS0_R_L

ARB_DETECT

SMC_IG_THROTTLE_L

MCP_GPIO_4

PM_SLP_S3_L PM_SLP_RMGT_L

MCP_GPIO_4 SMC_IG_THROTTLE_L

18

19

22

68

17

68

17

34

51

20

24

68

39

21

68

70

20

7

20

7

20

7

21

20

7

20

68

20

22

7

8

20

8

20

8

GND

V1P2_CPUCLK_VTT

V3P3

V3P3_DUAL

V3P3_TVDAC_VDD

V3P3_VBAT

V3P3_DUAL_USB

V1P0_VDD_AUXC

VDD

V1P2_CPU_VTT

NC

POWER

NC

(12 OF 12)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

80 uA (S0)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

250 mA

16 mA

266 mA (A01)

1139 mA

1182 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

105 mA (A01)

10 uA (G3)

450 mA (A01)

43 mA

U1400

BC35 BC37 BC39 BC41 BC43 BC49 BC55 BC61

BC7 BD10 BD46 BE13 BF10 BF16 BF28 BF34

BF4 BF46 BF52 BF58 BH12 BH14 BH42 BH44

BJ1 BJ13 BJ19 BJ25 BJ31 BJ37 BJ43 BJ49 BJ55 BJ61

BJ7 BM10 BM16 BM22 BM28 BM34

BM4 BM40 BM46 BM52 BM58

BR1 BR13 BR19 BR25 BR31 BR37 BR43 BR49 BR55 BR61

BR7 BV10 BV16 BV22 BV28 BV34

BV4 BV40 BV46 BV52 BV58

CA1 CA13 CA19 CA25 CA31 CA37 CA43 CA49 CA55 CA61

CA7

D10

D16

D22

D28

D34

D4 D40 D46

D52 D58 G1 G13 G19 G25 G31 G37 G43 G49 G55 G61 G7 K10 K16 K22 K28 K34 K4 K40 K46 K52 K58 M10 M20 M24 N1 N13 N17 N19 N25 N27 N29 N31 N33 N35 N37 N43 N49 N55 N61 N7 P42 P50 P8 R7 R9 T10 T16 T18 T28 T34 T36 T4 T46 T48 T52 T58 T8 U13 V10 V24 V34 V38 V48 V52 V8 W1 W13 W19 W25 W27 W31 W37 W43 W49 W53 W55 W61 W7 Y14 Y28 Y42 Y48 Y6

BGA

MCP79U

(11 OF 12)

OMIT

U1400

AH42 AH44 AJ13 AJ41 AJ43 AK12 AK42 AK44 AK46 AL41 AM12 AM14 AM42 AM44 AM46 AN41 AN43 AP24 AP26 AP28 AP30 AP32 AP34 AP36 AP38 AR19 AR21

T26 V26

AA49 AA53

AG53 AH50 AJ49 AJ53 AK50 AK52 AL53 AM50 AM52 AN49

AC49

AP50 AR49 AT50 T50 U49 V50 Y50 Y52

AC53 AD50 AD52 AE53 AF50 AF52 AG49

BL57

AK14 AU29 P18 P36

N21 N23 P24 T24

P32 P34 T30 T32

V44

P26

AA19 AA21

AA39 AD18 AD20 AD24 AD26 AD28 AD30 AD32 AD34 AD36

AA23

AD38 AF18 AF20 AF24 AF26 AF28 AF30 AF32 AF34 AF36

AA25

AF38 AH18 AH20 AH24 AH26 AH28 AH30 AH32 AH34 AH36

AA27

AH38 AK18 AK20 AK24 AK26 AK28 AK30 AK32 AK34 AK36

AA29

AK38 AM18 AM20 AM24 AM26 AM28 AM30 AM32 AM34 AM36

AA31

AM38

AA33 AA35 AA37

BGA

MCP79U

OMIT

(10 OF 12)

U1400

A39 A53

AW43 AW49 AW53

AY6 AY8 B56

B58 BA13 BA21 BA37

AF46 AG41 AG43 AH14

BG55 BG57 BJ51 BJ57 BK10 BK14 BK42

AA41

BL11 BL51 BL53 BL55 BM48 BM50 BM54 BN49 BN51 BN53 BN55 BP50 BP52 BP54 BR11 BR15 BR17 BR39 BR41 BR45 BR47

BR5

BR9

BT4

C49

C55

C57

D24

D26

D36

D38

D48

D50

D54

F10

F30

F8 G33 G35 G41

G45 G47 G51 G53 G9 H10 H30 J11 J13 J7 K12 K14 K18 K20 K24 K26 K30 K32 K36 K38 K42 K44 K48 K50 K54 K6 K8 L11 L13 L49 L5 L51 L53 L7 L9 M14 M16 M18 M26 M28 M30 M32 M34 M36 M38 M42 M44 M46 M48 M50 M52 M8 N39 N45

AA43

N51 N53 P12 P14 P16 P30 P44 P46 P48 P52 R53 T12 T14 U5 U53 U9 V12 V16 V18 V20 V32 V46 V6 W21 W23 W33 W35 W5 Y16 Y18 Y20 Y24 Y26 Y30 Y32 Y34 Y36 Y44 Y46

AT44 AT46 AT52 AU21 AU23 AU27 AU33 AU35 AU39 AU41 AU53 AV16 AV18 AV20 AV24 AV26 AV28 AV30 AV32 AV34 AV36 AV38 AV42 AV44 AV46 AV48 AV50 AW37

BGA

MCP79U

OMIT

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

051-7631

2.3.0

7121

MCP Power & Ground

=PP3V3_S0_MCP

=PP3V3_S5_MCP

=PP1V05_S0_MCP_FSB

=PPVCORE_S0_MCP

PP3V3_G3_RTC

PP3V3_S0_MCP_DAC

=PP1V05_S5_MCP_VDD_AUXC

22

13

20

22

8

22

24

70

22

7

7 7

20

23

7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP SATA (DVDD) Power

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

19 mA (A01)

206 mA (A01)

5 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)

1182 mA (A01)

7 mA (A01)

333 mA (A01)

4771 mA (A01, DDR3)

MCP Core Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power

MCP Memory Power

MCP FSB (VTT) Power

Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

Apple: 5x 2.2uF 0402 (11 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

MCP 1.05V AUX Power

MCP 3.3V/1.5V HDA Power

266 mA (A01)

MCP 3.3V AUX/USB Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Ethernet Power

270 mA (A01)

(No IG vs. EG data)

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

MCP PCIE (DVDD) Power

105 mA (A01)

83 mA (A01)

84 mA (A01)

87 mA (A01)

37 mA (A01)

562 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

127 mA (A01)

57 mA (A01)

450 mA (A01)

19 mA (A01)

43 mA (A01)

Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

5 mA (A01)

131 mA (A01)

MCP 1.05V RMGT Power

Apple: 7x 2.2uF 0402 (15.4 uF)

C2582

1

2

4V

4.7UF

20% X5R

402

C2588

1

2

20%

4.7UF

4V X5R 402

C2584

1

2

4.7UF

20%

4V X5R 402

C2586

1

2

4V

4.7UF

20% X5R

402

C2555

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C2502

1

2

4.7UF

4V

20% X5R

402

C2507

1

2

X5R 402-1

1UF

10%

6.3V

OMIT

C2506

1

2

X5R 402-1

1UF

10%

6.3V

OMIT

C2505

1

2

X5R 402-1

1UF

10%

6.3V

OMIT

C2504

1

2

X5R 402-1

1UF

10%

6.3V

OMIT

C2511

1

2

0.1UF

201

6.3V X5R

10%

C2510

1

2

0.1UF

201

6.3V X5R

10%

C2509

1

2

0.1UF

201

6.3V X5R

10%

C2508

1

2

0.1UF

201

6.3V X5R

10%

C2513

1

2

0.1UF

201

6.3V X5R

10%

C2512

1

2

0.1UF

201

6.3V X5R

10%

C2536

1

2

2.2UF

6.3V

20% CERM

402-LF

OMIT

C2535

1

2

2.2UF

20%

402-LF

CERM

OMIT

6.3V

C2534

1

2

6.3V

20% CERM

402-LF

2.2UF

OMIT

C2533

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2532

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2531

1

2

CERM 402-LF

6.3V

2.2UF

20%

OMIT

C2530

1

2

20%

402-LF

2.2UF

6.3V CERM

OMIT

C2517

1

2

X5R 402-1

1UF

10%

6.3V

OMIT

C2516

1

2

X5R 402-1

1UF

10%

6.3V

OMIT

C2515

1

2

4.7UF

4V

20% X5R

402

C2572

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2571

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2520

1

2

4V

4.7UF

20% X5R

402

C2570

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2574

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2573

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2576

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C2575

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2553

1

2

2.2UF

6.3V

20%

402-LF

CERM

OMIT

C2552

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2551

1

2

2.2UF

6.3V

20%

402-LF

CERM

OMIT

C2550

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2549

201

6.3V

0.1UF

X5R

10%

C2548

0.1UF

6.3V

201

X5R

10%

C2547

201

6.3V

0.1UF

X5R

10%

C2546

0.1UF

6.3V

201

X5R

10%

C2545

201

6.3V

0.1UF

X5R

10%

C2544

0.1UF

6.3V

201

X5R

10%

C2543

201

6.3V

0.1UF

X5R

10%

C2542

0.1UF

6.3V

201

X5R

10%

C2541

0.1UF

6.3V

201

X5R

10%

C2540

1

2

20%

4.7UF

4V X5R 402

C2562

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2564

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C2580

1

2

4.7UF

20%

4V X5R 402

L2570

1 2

0603

30-OHM-5A

L2575

1 2

30-OHM-5A

0603

L2582

1 2

30-OHM-1.7A

0402

L2584

1 2

30-OHM-1.7A

0402

L2588

1 2

30-OHM-1.7A

0402

L2586

1 2

0402

30-OHM-1.7A

L2555

1 2

0402

30-OHM-1.7A

C2500

1

2

4.7UF

4V

20% X5R

402

C2501

1

2

4.7UF

4V

20% X5R

402

L2580

1 2

30-OHM-1.7A

0402

C2560

1

2

6.3V

2.2UF

20%

402-LF

CERM

OMIT

C2589

0.1UF

6.3V

201

X5R

10%

C2590

201

6.3V

0.1UF

X5R

10%

C2595

1

2

20%

4.7UF

4V X5R 402

L2595

1 2

30-OHM-1.7A

0402

C2521

201

6.3V

0.1UF

X5R

10%

C2518

0.1UF

6.3V

201

X5R

10%

C2519

201

6.3V

0.1UF

X5R

10%

C2581

0.1UF

6.3V

201

X5R

10%

C2583

0.1UF

6.3V

201

X5R

10%

C2585

0.1UF

6.3V

201

X5R

10%

C2587

0.1UF

6.3V

201

X5R

10%

C2529

201

6.3V

0.1UF

X5R

10%

C2528

1

2

X5R

20%

4V

4.7uF

402

C2526

1

2

6.3V

10%

0.1UF

X5R 201

C2525

1

2

0.1UF

6.3V

201

X5R

10%

C2596

1

2

0.1UF

6.3V

201

X5R

10%

C2503

1

2

4.7UF

4V

20% X5R

402

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

MCP Standard Decoupling

22

2.3.0

051-7631

71

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_SATA_DVDD

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PP1V05_S0_MCP_AVDD_UF

=PP3V3_S5_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP

=PP1V05_ENET_MCP_PLL_MAC

VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_SATA_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PP1V05_ENET_MCP_RMGT

=PP1V05_S0_MCP_PEX_DVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_FSB

PP1V05_S0_MCP_PLL_PEX

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_SATA

PP1V05_S0_MCP_PLL_CORE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PP1V05_S0_MCP_FSB

=PP1V05_S5_MCP_VDD_AUXC

=PP1V8R1V5_S0_MCP_MEM

=PPVCORE_S0_MCP

21

13

66

70

19

17 21

20

70

70 17

70

8

21

15

21

17

7

19

7

13

16

19

15

20

19

7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

16 mA (A01)

95 mA (A01)

190 mA (A01, 1.8V)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: ???

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

SYNC FROM M97

C2620

1

2

201

6.3V

0.1UF

NO STUFF

X5R

10%

R2630

1

2

MF

1/20W

1%

1K

201

NO STUFF

C2630

1

2

201

6.3V

NO STUFF

0.1UF

X5R

10%

C2615

1

2

4.7UF

20%

4V X5R 402

C2640

1

2

CERM

4.7UF

6.3V

20%

603

L2640

1 2

30-OHM-1.7A

0402

C2641

1

2

6.3V

201

0.1uF

X5R

10%

C2616

1

2

201

0.1UF

6.3V X5R

10%

R2650

1

2

5%

0

402

MF-LF

1/16W

R2620

1

2

201

1/20W

1%

1K

MF

C2610

1

2

20%

2.2UF

6.3V

402-LF

CERM

OMIT

051-7631

2.3.0

7123

MCP Graphics Support

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

MCP_HDMI_VPROBE

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

PP3V3_S0_MCP_VPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MCP_HDMI_RSET

=PP1V05_S0_MCP_HDMI_VDD

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP3V3_S0_MCP_VPLL_UF

PP3V3_S0_MCP_DAC

67

70

67

17

17 70

17

7

21

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

Y

B

A

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Place near MCP ball A20

PCIE Reset (Unbuffered)

MCP 25MHz Crystal

Reset Button

RTC Power Sources

LPC Reset (Unbuffered)

Platform Reset Connections

RTC Crystal

10K pull-up to 3.3V S0 inside MCP

Place R2890 on BOTTOM of board near edge

CHANGED RTC POWER SOURCE TO DIRECT CONNECTION

SYNC FROM M97

ADDED MCPSEQ_SMC LOGIC

MCP S0 PWRGD & CPU_VLD

C2810

1 2

12pF

201

25V

5%

NP0-C0G

C2811

1 2

NP0-C0G

201

5%

12pF

25V

R2811

1

2

NO STUFF

MF-LF

1/16W

5%

10M

402

18 68

R2883

1 2

201

1/20W

5%

MF

33

PLACEMENT_NOTE=Place close to U1400

R2881

1 2

201

PLACEMENT_NOTE=Place close to U1400

MF

1/20W

5%

33

R2891

1 2

201

MF

1/20W

5%

0

41

39

6

34

20

16

R2826

1 2

33

5%

201

MF

1/20W

PLACEMENT_NOTE=Place close to U1400

R2825

1 2

201

33

1/20W

5%

MF

PLACEMENT_NOTE=Place close to U1400

18 68

C2815

1 2

25V

5%

12PF

NP0-C0G

201

C2816

1 2

25V

NP0-C0G

5%

12pF

201

Y2815

2 4

1 3

SM-3.2X2.5MM

25.0000M

CRITICAL

R2816

1

2

402

NO STUFF

5%

MF-LF

1/16W

1M

20

39 68

R2829

1 2

22

5%

201

MF

1/20W

PLACEMENT_NOTE=Place close to U1400

20 68

62

R2892

1 2

201

MF

1/20W

5%

0

54 57

R2870

1 2

33

5%

201

MF

1/20W

18

C2850

1

2

6.3V

201

X5R

10%

0.1UF

39 56

50

20

41 68

39 68

20

C2899

1

2

10V X5R 402-1

1UF

10%

NO STUFF

R2899

1 2

MF

201

5%

1/20W

33

R2890

1

2

NO STUFF

0

5%

MF-LF

1/16W

SILK_PART=SYS RST

402

R2898

1 2

0

XDP

1/20W

5%

201

MF

39

6 9

12

25

R2871

1 2

MF

1/20W

5%

0

201

Y2810

1 4

7X1.5X1.4-SM

32.768K

CRITICAL

U2850

2

1

3

5

4

SOT665

TC7SZ08AFEAPE

R2810

1

2

201

MF

1/20W

5%

0

R2815

1

2

201

MF

0

1/20W

5%

R2853

1 2

MF

201

5%

0

1/20W

R2850

1 2

PLACEMENT_NOTE=Place close to U1400

MF

201

5%

0

1/20W

20

C2860

1

2

1UF

402

CERM

6.3V

10%

OMIT

R2851

1

2

1.8K

1%

1/20W

MF

201

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

SB Misc

71

2.3.0

24

051-7631

=PP3V3_S0_PWRCTL

VR_PWRGOOD_DELAY

=PP3V3_S5_MCPPWRGD

MCP_CLK25M_XTALOUT

MCP_PS_PWRGD

MCP_CPU_VLD

MCP_CPUVDD_EN

ALL_SYS_PWRGD

XDP_DBRESET_L

PM_SYSRST_DEBOUNCE_L

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT_R

RTC_CLK32K_XTALOUT

DEBUG_RESET_L

PM_CLK32K_SUSCLK

LPC_CLK33M_SMC

SMC_LRESET_L

BKLT_PLT_RST_L

LPC_CLK33M_LPCPLUS

=DDRVTT_EN

AIRPORT_RST_L

PCA9557D_RESET_L

PP3V3_G3_RTC

PM_SYSRST_L

LPC_CLK33M_SMC_R

MCP_CLK25M_XTALOUT_R

RTC_CLK32K_XTALIN

S0_AND_IMVP_PGOOD

PM_CLK32K_SUSCLK_R

MAKE_BASE=TRUE

MEM_VTT_EN

LPC_RESET_L

=PP3V42_G3H_REG

MEM_VTT_EN_R

PCIE_RESET_L

56

21 49

7

20

7

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

V-

V+

V-

V+

NC

OUT

NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU FSB VREF

10mA max load

- =I2C_VREFDACS_SCL

Page Notes

- =PPVTT_S3_DDR_BUF

ADDR=0x30(WR)/0x31(RD)

BOM options provided by this page: VREFMRGN

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

Signal aliases required by this page:

- =PP3V3_S5_VREFMRGN

- =PP3V3_S3_VREFMRGN

Power aliases required by this page:

ADDR=0x98(WR)/0x99(RD)

MEM B VREF CAMEM B VREF DQMEM A VREF DQ

(per DAC LSB)

Required zero ohm resistors when no VREF margining circuit stuffed

DAC channel A B A B C

MEM A VREF CA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Min DAC code 0x00 0x00 0x00 0x00 0x00 Max DAC code 0x87 0x87 0x87 0x87 0x55

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

R2902

1 2

201

MF

1/20W

5%

100K

VREFMRGN

U2900

C3

C2

C1

C4

B1

B4

CRITICAL

VREFMRGN

MAX4253

UCSP

C2920

1

2

201

X5R

6.3V

10%

VREFMRGN

0.1UF

U2900

A3

A2

A1

A4

B1

B4

CRITICAL

VREFMRGN

MAX4253

UCSP

R2901

1 2

1/20W

201

MF

VREFMRGN

100K

5%

R2904

1 2

1/20W

MF

201

100

1%

R2903

MF

201

VREFMRGN

1/20W

5%

200

R2905

MF

201

5%

VREFMRGN

1/20W

200

R2906

1 2

201

MF

1%

1/20W

100

U2920

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

CRITICAL

VREFMRGN

PCA9557

QFN

24

42

U2910

9

10

3

6

7

8

1

2

4

5

CRITICAL

VREFMRGN

DAC5574

MSOP

42 42

C2910

1

2

201

X5R

6.3V

10%

0.1UF

VREFMRGN

C2915

VREFMRGN

20%

6.3V 402-LF

2.2UF

CERM

C2903

1

2

201

X5R

6.3V

10%

0.1UF

VREFMRGN

R2907

1 2

201

1% MF

1/20W

100

R2908

1 2

100K

1/20W

201

MF

VREFMRGN

5%

U2903

A3

A2

A1

A4

B1

B4

CRITICAL

VREFMRGN

MAX4253

UCSP

U2903

C3

C2

C1

C4

B1

B4

CRITICAL

VREFMRGN

MAX4253

UCSP

C2900

1

2

201

X5R

6.3V

10%

VREFMRGN

0.1UF

9

65

SYNC_DATE=01/15/2008

25 71

2.3.0

051-7631

SYNC_MASTER=BEN

FSB/DDR3 Vref Margining

CRITICALR2903

NO_VREFMRGN

1116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL1

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R2905

VREFMRGN_VREFCA

VREFMRGN_VREFDQ

PP0V75_S3_MEM_VREFDQ

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPU_GTLREF

=PP3V3_S3_VREFMRGN

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB_EN

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA

=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA

PCA9557D_RESET_L

=I2C_PCA9557D_SCL

VREFMRGN_DQ_EN

VREFMRGN_CA_EN

VREFMRGN_CPUFSB_EN

=I2C_PCA9557D_SDA

VREFMRGN_DQ_EN

VREFMRGN_CPUFSB

VREFMRGN_CA_EN

VREFMRGN_CA_BUF

VREFMRGN_DQ_BUF

=PPVTT_S3_DDR_BUF

70

30

29

28

27

7

25

27

25

7

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

before 1.5V starts to rise to avoid glitch on MEM_RESET_L.

3.3V input must be stable before

R3010

1

2

1K

201

MF

5% 1/20W

C3000

1

2

10%

6.3V X5R

0.1UF

201

MEMRESET_HW

R3000

1

2

MF

1/20W

201

MEMRESET_HW

10K

5%

15

R3009

1

2

201

0

1/20W

5%

MF

MEMRESET_MCP

Q3005

5

3

4

SOT-363-LF

MMDT3904-X-G

MEMRESET_HW

R3005

1

2

1/20W

5%

MEMRESET_HW

201

MF

20K

Q3005

2

6

1

MMDT3904-X-G

SOT-363-LF

MEMRESET_HW

27 28 29 30 66

R3001

1

2

MF

1/20W

201

MEMRESET_HW

20K

5%

051-7631

2.3.0

7126

SYNC_MASTER=T18_MLB

SYNC_DATE=01/30/2008

DDR3 Support

MEM_RESET

=PP1V5_S3_MEMRESET

=PP3V3_S5_MEMRESET

MEM_RESET_RC_L

MCP_MEM_RESET_L

MEM_RESET_L

7

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

NC NC

NC

NCNC

NC

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

U3100

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

MEM_A_ZQ0

MT41J128M8HX-187E

OMIT

128MX8-SDRAM-1066MHZ

C3102

1

2

201

4V CERM-X5R

0.47UF

20%

C3101

1

2

4V

201

CERM-X5R

0.47UF

20%

C3100

1

2

4V

20%

201

0.47UF

CERM-X5R

R3100

1 2

240

1%MF1/20W

201

C3112

1

2

CERM-X5R 201

4V

20%

0.47UF

C3111

1

2

4V

20%

0.47UF

201

CERM-X5R

C3110

1

2

4V

20%

0.47UF

201

CERM-X5R

R3110

1 2

240

201

1/20WMF1%

U3110

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

OMIT

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

C3122

1

2

CERM-X5R 201

4V

20%

0.47UF

C3121

1

2

4V

20%

0.47UF

201

CERM-X5R

C3120

1

2

4V

20%

0.47UF

201

CERM-X5R

R3120

1 2

240

201

1/20WMF1%

U3120

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

OMIT

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

C3132

1

2

CERM-X5R 201

4V

20%

0.47UF

C3131

1

2

4V

20%

0.47UF

201

CERM-X5R

C3130

1

2

4V

20%

0.47UF

201

CERM-X5R

R3130

1 2

240

201

1/20WMF1%

U3130

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

OMIT

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

DDR3 DRAM Channel A (0-31)

SYNC_MASTER=(MASTER)

051-7631

27 71

SYNC_DATE=(MASTER)

2.3.0

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_CLK_N<0>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

=PP1V5_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_DQ<0>

MEM_A_DQ<4> MEM_A_DQ<2> MEM_A_DQ<5> MEM_A_DQ<6>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DM<0>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<9> MEM_A_A<10>

MEM_A_ODT<1>

MEM_A_ZQ0

MEM_A_A<14>

MEM_A_CKE<1>

MEM_A_DQ<7>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_RAS_L

=PP1V5_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ3

MEM_A_DQ<25>

MEM_A_DQ<28>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQS_N<3>

MEM_A_DM<3>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<9>

MEM_A_ODT<1>

MEM_A_ZQ3

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_CLK_N<0>

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

=PP1V5_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ2

MEM_A_DQ<17>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<23>

MEM_A_DQ<22> MEM_A_DQ<16> MEM_A_DQ<18> MEM_A_DQ<21>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<9> MEM_A_A<10>

MEM_A_ZQ2

MEM_A_A<14>

MEM_A_CKE<1>

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_CAS_L

=PP1V5_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_ZQ1

MEM_A_DQ<12> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<13> MEM_A_DQ<15>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DM<1>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<9> MEM_A_A<10>

MEM_A_CKE<1>

MEM_A_ZQ1

MEM_A_RAS_L

MEM_A_ODT<1>

MEM_A_CLK_N<0>

MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_DQ<8> MEM_A_DQ<14> MEM_A_DQ<9>

MEM_A_DM<2>

MEM_A_A<6>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_A<14>

MEM_A_DQ<30> MEM_A_DQ<31>

MEM_A_CKE<1>

MEM_A_DQS_P<3>

MEM_A_DQ<24>

70

66

70

66

70

66

70

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

28

27

66

27

66

27

66

27

66

27

27 66

66

27

66

27

66

27

66

14

25

14

26

14

27

14

25

14

26

14

27

14

25

14

26

14

27

14

14 14

14

25

14

26

14

27

14

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

NCNC

NC

A14/A15 FOR 2G/4G MONO ONLY

NC

NC NC

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

C3232

1

2

0.47UF

20% 4V

201

CERM-X5R

C3220

1

2

CERM-X5R

201

0.47UF

20%

4V

R3230

1 2

240

201

1/20WMF1%

U3230

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

OMIT

R3220

1 2

240

201

1/20WMF1%

U3220

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

OMIT

C3212

1

2

0.47UF

20% 4V

201

CERM-X5R

C3211

1

2

CERM-X5R

201

0.47UF

20%

4V

C3210

1

2

CERM-X5R

201

0.47UF

20%

4V

C3202

1

2

0.47UF

20% 4V

201

CERM-X5R

C3201

1

2

CERM-X5R

201

0.47UF

20%

4V

C3200

1

2

CERM-X5R

201

0.47UF

20%

4V

C3231

1

2

CERM-X5R

201

0.47UF

20%

4V

R3210

1 2

240

201

1/20WMF1%

U3210

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

OMIT

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

FBGA

R3200

1 2

240

201

1/20WMF1%

U3200

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

128MX8-SDRAM-1066MHZ

OMIT

MT41J128M8HX-187E

C3230

1

2

CERM-X5R

201

0.47UF

20%

4V

C3222

1

2

0.47UF

20% 4V

201

CERM-X5R

C3221

1

2

CERM-X5R

201

0.47UF

20%

4V

2.3.0

7128

DDR3 DRAM Channel A (32-63)

051-7631

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ11

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<1> MEM_A_A<2>

MEM_A_A<0>

PP0V75_S3_MEM_VREFDQ

PP0V75_S3_MEM_VREFCA

MEM_A_DM<7>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<60>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<58>

MEM_A_DQ<63> MEM_A_DQ<56>

MEM_A_DQ<59> MEM_A_DQ<57>

MEM_A_ZQ11

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PP1V5_S3_MEM_A

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ10

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<1> MEM_A_A<2>

MEM_A_A<0>

PP0V75_S3_MEM_VREFDQ

PP0V75_S3_MEM_VREFCA

MEM_A_DM<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<48>

MEM_A_DQ<55> MEM_A_DQ<51>

MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_ZQ10

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PP1V5_S3_MEM_A

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ8

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<1> MEM_A_A<2>

MEM_A_A<0>

PP0V75_S3_MEM_VREFDQ

PP0V75_S3_MEM_VREFCA

MEM_A_DM<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQ<32>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<39> MEM_A_DQ<33>

MEM_A_ZQ8

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PP1V5_S3_MEM_A

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ9

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<1> MEM_A_A<2>

MEM_A_A<0>

PP0V75_S3_MEM_VREFDQ

PP0V75_S3_MEM_VREFCA

MEM_A_DM<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQ<42>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQ<43>

MEM_A_DQ<44> MEM_A_DQ<45>

MEM_A_DQ<41> MEM_A_DQ<46>

MEM_A_ZQ9

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PP1V5_S3_MEM_A

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

66

70

66

70

66

70

66

70

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

28

27

66

27

66

27

66

27

66

27

14

28

14

26

14

25

14

28

14

26

14

25

14

28

14

26

14

25

14

28

14

26

14

25

14

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC NC

NCNC

NC

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

NC

NCNC

NC

U3300

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

MEM_B_ZQ0

OMIT

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

C3302

1

2

CERM-X5R 201

4V

20%

0.47UF

C3301

1

2

4V

201

CERM-X5R

0.47UF

20%

C3300

1

2

4V

20%

201

0.47UF

CERM-X5R

R3300

1 2

240

1%MF1/20W

201

C3312

1

2

CERM-X5R 201

4V

20%

0.47UF

C3311

1

2

4V

20%

0.47UF

201

CERM-X5R

C3310

1

2

4V

20%

0.47UF

201

CERM-X5R

R3310

1 2

240

201

1/20WMF1%

U3310

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

OMIT

C3322

1

2

CERM-X5R 201

4V

20%

0.47UF

C3321

1

2

4V

20%

0.47UF

201

CERM-X5R

C3320

1

2

4V

20%

0.47UF

201

CERM-X5R

R3320

1 2

240

201

1/20WMF1%

U3320

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

OMIT

C3332

1

2

CERM-X5R 201

4V

20%

0.47UF

C3331

1

2

4V

20%

0.47UF

201

CERM-X5R

C3330

1

2

4V

20%

0.47UF

201

CERM-X5R

R3330

1 2

240

201

1/20WMF1%

U3330

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

FBGA

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

OMIT

DDR3 DRAM Channel B (0-31)

SYNC_MASTER=(MASTER)

051-7631

29 71

SYNC_DATE=(MASTER)

2.3.0

MEM_B_DQ<12>

MEM_B_A<3>

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<7>

MEM_B_A<1>

MEM_B_DQ<3>

MEM_B_A<3>

MEM_B_ODT<0>

MEM_B_CKE<1>

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ3

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<28>

MEM_B_DQ<24>

MEM_B_DQ<27> MEM_B_DQ<25> MEM_B_DQ<31> MEM_B_DQ<26>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DM<3>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9> MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ3

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ2

MEM_B_DQ<22>

MEM_B_DQ<16>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<23>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DM<2>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9> MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ2

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_ZQ1

MEM_B_DQ<9>

MEM_B_DQ<14>

MEM_B_DQ<8>

MEM_B_DQ<10> MEM_B_DQ<13> MEM_B_DQ<11> MEM_B_DQ<15>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DM<1>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9> MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ1

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_DQ<4> MEM_B_DQ<2>

MEM_B_DQ<5> MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DM<0>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9> MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ0

MEM_B_A<14>

70

66

70

66

70

66

70

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

30

28

30

28

30

28

30

28

30

28

30

28

30

28

30

28

30

66 29

66

29

66 29

29

66

27

29

27

29

66

27

29

27

29

66

27

29

27

29

66

27

29

27

29

14 14

14

14 14

14

25

14

26

14

29

14

25

14

26

14

29

14

25

14

26

14

29

14

25

14

26

14

29

14

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4 DQ5 DQ6 DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9 A10/AP

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

A14/A15 FOR 2G/4G MONO ONLY

NC

NC NC

NC

C3432

1

2

0.47UF

20% 4V

201

CERM-X5R

C3420

1

2

CERM-X5R

201

0.47UF

20%

4V

R3430

1 2

240

201

1/20WMF1%

U3430

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

OMIT

FBGA

R3420

1 2

240

201

1/20WMF1%

U3420

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

OMIT

FBGA

C3412

1

2

0.47UF

20% 4V

201

CERM-X5R

C3411

1

2

CERM-X5R

201

0.47UF

20%

4V

C3410

1

2

CERM-X5R

201

0.47UF

20%

4V

C3402

1

2

0.47UF

20% 4V

201

CERM-X5R

C3401

1

2

CERM-X5R

201

0.47UF

20%

4V

C3400

1

2

CERM-X5R

201

0.47UF

20%

4V

C3431

1

2

CERM-X5R

201

0.47UF

20%

4V

R3410

1 2

240

201

1/20WMF1%

U3410

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

OMIT

FBGA

R3400

1 2

240

201

1/20WMF1%

U3400

K3 L7

H7 M7 K7 N3

L3 K2 L8 L2 M8 M2 N8 M3

J2 K8 J3

G3

F7 G7

G9

H2

B7

B3 C7 C2 C8 E3 E8 D2 E7

C3

D3

A3

J7

N7

F9

H1

F1

H9

G1

F3

N2

A7

A2A9D7G2G8K1K9M1M9B9C1E2E9

J8

E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

OMIT

FBGA

C3430

1

2

CERM-X5R

201

0.47UF

20%

4V

C3422

1

2

0.47UF

20% 4V

201

CERM-X5R

C3421

1

2

CERM-X5R

201

0.47UF

20%

4V

DDR3 DRAM Channel B (32-63)

2.3.0

7130

051-7631

MEM_B_CAS_L

MEM_B_CLK_P<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ11

MEM_B_DQ<57>

MEM_B_DQ<61>

MEM_B_DQ<56>

MEM_B_DQ<58>

MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DM<7>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ11

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_RAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ10

MEM_B_DQ<53>

MEM_B_DQ<48> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<54> MEM_B_DQ<52>

MEM_B_DM<6>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9> MEM_B_A<10>

MEM_B_ZQ10

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ9

MEM_B_DQ<41>

MEM_B_DQ<43>

MEM_B_DQ<47>

MEM_B_DQ<42>

MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<40>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DM<5>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9> MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ9

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP1V5_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ8

MEM_B_DQ<33>

MEM_B_DQ<38>

MEM_B_DQ<32>

MEM_B_DQ<35>

MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<34> MEM_B_DQ<39>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DM<4>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9> MEM_B_A<10>

MEM_B_ZQ8

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_ODT<1>

MEM_B_A<14>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<49>

MEM_B_A<8> MEM_B_A<9>

70

66

70

66

70

66

70

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

30

66

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

29

33

30

28

30

28

30

28

30

28

30

28

30

28

30

28

30

28

30

29

66

27

29

27

29

66

27

29

27

29

66

27

29

27

29

66

27

29

27

29

66

29

14

25

14

26

14

30

14

25

14

26

14

30

14

25

14

26

14

30

14

25

14

26

14

30

14

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES

TWO 0402 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE 2 CAPS ALONG PACKAGE EDGE

APPROXIMATE CAP ARRANGEMENT

C3540

1

2

CERM 402-LF

2.2UF

6.3V

20%

OMIT

C3541

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3542

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3550

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3551

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3530

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3531

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3554

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3555

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3544

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3545

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3546

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3534

1

2

CERM

20%

2.2UF

6.3V 402-LF

OMIT

C3535

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3520

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3521

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3510

1

2

CERM

20%

2.2UF

6.3V 402-LF

OMIT

C3511

1

2

CERM

20%

2.2UF

6.3V 402-LF

OMIT

C3512

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3500

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3501

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3524

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3525

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3514

1

2

CERM

20%

402-LF

6.3V

2.2UF

OMIT

C3515

1

2

20% CERM

402-LF

6.3V

2.2UF

OMIT

C3516

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3504

1

2

CERM 402-LF

20%

6.3V

2.2UF

OMIT

C3505

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

DDR BYPASSING 1

SYNC_MASTER=MEMORY

SYNC_DATE=06/20/2005

051-7631

71

2.3.0

31

=PP1V5_S3_MEM_A =PP1V5_S3_MEM_A

33 33 31 31 28 28 27 27

7 7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

APPROXIMATE CAP ARRANGEMENT

2 CAPS ALONG PACKAGE EDGE

TWO 0402 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGESCOLUMN OF THREE CAPS BETWEEN PACKAGES

C3640

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3641

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3642

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3650

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3651

1

2

2.2UF

CERM 402-LF

20%

6.3V

OMIT

C3630

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3631

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3654

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3655

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3644

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3645

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3646

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3634

1

2

CERM

20%

2.2UF

6.3V 402-LF

OMIT

C3635

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3620

1

2

CERM

20%

2.2UF

6.3V 402-LF

OMIT

C3621

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3610

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3611

1

2

6.3V 402-LF

CERM

20%

2.2UF

OMIT

C3612

1

2

CERM 402-LF

20%

6.3V

2.2UF

OMIT

C3600

402-LF

CERM

6.3V

20%

2.2UF

OMIT

C3601

1

2

CERM 402-LF

2.2UF

20%

6.3V

OMIT

C3624

1

2

20%

402-LF

CERM

6.3V

2.2UF

OMIT

C3625

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3614

1

2

2.2UF

20% CERM

402-LF

6.3V

OMIT

C3615

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3616

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3604

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

C3605

1

2

CERM 402-LF

20%

2.2UF

6.3V

OMIT

SYNC_DATE=06/20/2005

051-7631

71

2.3.0

32

SYNC_MASTER=MEMORY

DDR BYPASSING 2

=PP1V5_S3_MEM_B=PP1V5_S3_MEM_B

33 33 32 32 30 30 29 29

7 7

IN

IN IN IN

IN IN IN IN

IN IN IN

IN

IN IN

IN

IN IN

IN IN IN

IN

IN IN IN IN IN IN IN IN

IN

IN IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Unused Clock Termination

MEM CLOCK TERMINATION

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

Place Source Cterm at neckdown at first DRAM

Place RC end termination after last DRAM

14 27 28 66

RP3702

1 8

1/32W

5%

36

4X0201

RP3702

2 7

1/32W

5%

4X0201

36

RP3706

4 5

36

5%

1/32W

4X0201

RP3702

3 6

36

1/32W

5%

4X0201

RP3702

4 5

1/32W

5%

36

4X0201

RP3704

1 8

4X0201

36

1/32W

5%

RP3707

3 6

4X0201

1/32W

5%

36

RP3703

2 7

36

5%

1/32W

4X0201

RP3704

3 6

36

1/32W

5%

4X0201

RP3703

4 5

36

4X0201

1/32W

5%

RP3703

3 6

36

1/32W

5%

4X0201

RP3703

1 8

36

5%

1/32W

4X0201

RP3704

4 5

36

5%

1/32W

4X0201

R3790

1 2

36

201

5%

1/20W

RP3706

2 7

4X0201

1/32W

5%

36

RP3706

1 8

4X0201

1/32W365%

RP3701

4 5

36

4X0201

5%

1/32W

RP3701

2 7

36

4X0201

1/32W

5%

14 27 28 66

R3700

1 2

201

30

MF

1/20W

5%

R3701

1 2

201

30

MF

1/20W

5%

C3700

1

2

6.3V

X5R

10%

0.1UF

201

MEM_A_CLK_TERM_R

C3702

1

2

10%

0.1UF

X5R

6.3V

201

R3704

1 2

201

5%

1/20W

MF

30

R3705

1 2

201

1/20W

MF

5%

30

RP3701

1 8

4X0201

36

1/32W

5%

RP3701

3 6

4X0201

36

1/32W

5%

RP3707

2 7

4X0201

36

1/32W

5%

RP3704

2 7

36

1/32W

5%

4X0201

RP3706

3 6

36

1/32W

5%

4X0201

14 27 28 66

RP3715

3 6

4X0201

36

5%

1/32W

RP3715

4 5

1/32W

4X0201

36

5%

RP3715

2 7

4X0201

36

5%

1/32W

RP3711

1 8

4X0201

36

5%

1/32W

RP3709

1 8

4X0201

36

5%

1/32W

RP3715

1 8

4X0201

5%361/32W

RP3710

3 6

5%361/32W

4X0201

RP3709

3 6

36

5%

1/32W

4X0201

RP3711

2 7

4X0201

36

5%

1/32W

RP3709

2 7

36

1/32W

5%

4X0201

RP3708

1 8

4X0201

36

1/32W

5%

RP3708

2 7

4X0201

36

1/32W

5%

RP3711

3 6

4X0201

1/32W365%

RP3709

4 5

1/32W

5%

36

4X0201

RP3708

3 6

4X0201

1/32W365%

RP3711

4 5

4X0201

36

1/32W

5%

RP3713

4 5

4X0201

1/32W365%

RP3710

4 5

4X0201

1/32W365%

RP3710

2 7

4X0201

36

1/32W

5%

RP3710

1 8

4X0201

36

1/32W

5%

RP3708

4 5

5%

4X0201

36

1/32W

RP3713

3 6

4X0201

36

1/32W

5%

RP3714

2 7

36

4X0201

5%

1/32W

RP3714

1 8

36

4X0201

5%

1/32W

RP3714

4 5

4X0201

36

5%

1/32W

RP3714

3 6

4X0201

36

5%

1/32W

RP3713

2 7

4X0201

36

5%

1/32W

14 29 30 66

C3704

1

2

201

3.3PF

5% 25V CERM

C3706

1

2

201

3.3PF

CERM

25V

5%

C3710

1

2

201

4V CERM-X5R

0.47UF

20%

C3713

1

2

20%

0.47UF

201

CERM-X5R

4V

C3712

1

2

20%

201

CERM-X5R

4V

0.47UF

C3715

1

2

201

20%

0.47UF

4V CERM-X5R

C3714

1

2

20%

0.47UF

201

CERM-X5R

4V

C3717

1

2

201

4V

0.47UF

20% CERM-X5R

C3716

1

2

20%

0.47UF

201

4V CERM-X5R

C3718

1

2

0.47UF

CERM-X5R

20%

201

4V

C3720

1

2

0.47UF

20%

201

CERM-X5R

4V

C3722

1

2

20%

0.47UF

201

CERM-X5R

4V

C3724

1

2

0.47UF

20%

201

CERM-X5R

4V

C3727

1

2

20%

0.47UF

CERM-X5R

4V 201

C3726

1

2

20%

0.47UF

CERM-X5R 201

4V

C3729

1

2

20%

0.47UF

CERM-X5R

4V 201

C3728

1

2

20%

201

CERM-X5R

0.47UF

4V

C3730

1

2

20%

0.47UF

201

CERM-X5R

4V

C3733

1

2

20%

0.47UF

201

CERM-X5R

4V

C3732

1

2

20%

0.47UF

201

CERM-X5R

4V

R3706

1

2

201

75

5% 1/20W MF

R3707

1

2

201

MF

1/20W

5%

75

RP3707

1 8

4X0201

36

5%

1/32W

14 27 28 66

R3791

1 2

1/20W

36

5%

201

R3793

1 2

1/20W

36

5%

201

R3792

1 2

5%

36

1/20W

201

14 27 28 66

2.3.0

71

Memory Active Termination

33

051-7631

MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_ODT<0> MEM_A_ODT<1>

=PP0V75_S0_MEM_VTT_B

MEM_A_CAS_L

MEM_A_A<14>

MEM_B_RAS_L MEM_B_CAS_L

MEM_B_WE_L MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_A<2>

MEM_B_CS_L<0>

MEM_A_WE_L

MEM_A_BA<1> MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_RAS_L

=PP1V5_S3_MEM_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_CKE<1>

MEM_B_CS_L<1> MEM_B_CKE<0>

MEM_B_A<13> MEM_B_A<14>

MEM_B_A<12>

MEM_B_A<10> MEM_B_A<11>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<0> MEM_B_A<1>

MEM_B_A<7>

VOLTAGE=0V

MEM_B_CLK_TERM_R

VOLTAGE=0V

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

=PP1V5_S3_MEM_B

MEM_A_A<4>

MEM_A_CS_L<0>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_CKE<0>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

=PP0V75_S0_MEM_VTT_A

31 66

66

32

28 28

28

30

27 27

27

29

7

14

7

D

SG

D

SG

D

SG

D

SG

OUT

IN

OUT

IN

BI BI

IN

OUT

BI

SYM_VER-2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE C4100,C4101 < 250 MILS FROM MCP

APN:516S0580

PLACE FILTERS NEAR CONNECTOR

M93 WIRELESS AIRPORT & BT CONNECTOR

C4109

1

2

20%

6.3V

10UF

X5R 603

OMIT

C4108

1

2

10%

X5R 201

6.3V

0.1UF

C4111

1

2

10% CERM

33NF

402

25V

R4105

12

100K

201

MF

1/20W

5%

Q4102

3

5

4

SSM6N15FEAPE

SOT563

R4104

1 2

1/20W

201

MF

100K

5%

Q4103

6

2

1

SSM6N15FEAPE

SOT563

Q4103

3

5

4

SOT563

SSM6N15FEAPE

Q4102

6

2

1

SSM6N15FEAPE

SOT563

Q4101

1

2

5

6

3

4

SM

FDC638P_G

CRITICAL

C4112

1

2

10%

X5R

10V

0.01UF

201

J4100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

CRITICAL

F-ST-SM

CPB6330-0101F

C4100

1 2

10%

X5R

6.3V

0.1UF

201

C4101

1 2

10%

X5R

6.3V

201

0.1UF

34

16 67

34

6

24

6

42

6

42

6

16

8

L4101

1 2

34

90-OHM-100MA

DLP11S

CRITICAL

C4107

1

2

X5R 201

0.1UF

6.3V

10%

C4110

1

2

10%

X5R 201

6.3V

0.1UF

L4104

12

FERR-120-OHM-1.5A

0402-LF

L4100

1 2

34

90-OHM-100MA

DLP11S

CRITICAL

L4103

1 2

34

90-OHM-100MA

DLP11S

CRITICAL

L4102

1 2

34

90-OHM-100MA

DLP11S

CRITICAL

2.3.0

34 71

051-7631

Wireless M93 Connector

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

MIN_LINE_WIDTH=0.2MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PP3V3_S3_AP_AUX

=PP3V3_S5_AIRPORT_AUX

SMC_ADAPTER_PRESENT

AP_PWR_EN

=PP3V3_S3_BT

MINI_CLKREQ_L

PCIE_MINI_R2D_C_P

=USB2_BT_N

=SMB_AIRPORT_CLK

PCIE_E_D2R_P_F

=SMB_AIRPORT_DATA

AIRPORT_RST_L

PCIE_WAKE_L

PP3V3_S3_AP_AUX_F

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM VOLTAGE=3.3V

PCIE_E_R2D_C_P

=PP3V3_S5_AIRPORT_AUX

PM_SLP_S3_L

PM_WLAN_EN_L2

PCIE_E_D2R_N

MAKE_BASE=TRUE

PCIE_MINI_D2R_N

PCIE_E_D2R_P

MAKE_BASE=TRUE

PCIE_MINI_D2R_P

MAKE_BASE=TRUE

PCIE_E_R2D_C_N

PCIE_MINI_R2D_C_N

PCIE_E_R2D_C_P

MAKE_BASE=TRUE

PM_WLAN_EN_L

PM_WLAN_EN_L_SS

PCIE_E_R2D_C_P_F

PCIE_E_R2D_P

PCIE_E_R2D_C_N_F

PCIE_E_R2D_N

USB2_BT_N_F

=USB2_BT_P

PCIE_CLK100M_MINI_N_F

PCIE_CLK100M_MINI_P_F

PCIE_E_D2R_N_F

PCIE_E_D2R_P

USB2_BT_P_F

PCIE_E_R2D_C_N

PM_SLP_S4_L

PM_WLAN_EN_L1

PCIE_E_D2R_N

56 39

56

35

40

70

34

67

34

20

67

39

6

7

8

20

7

16

6

70

7

6

34 16

34

6

20

IN

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Micro-DisplayPort / USB to RIO Hatch Assembly

Audio Connector

516S0350

516S0710

J4260

1

10 11 12 13 14 15 16

2

3 4 5 6 7 8 9

M-ST-SM

QT500166-L020

CRITICAL

J4200

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40

5 6 7 8 9

54102-8640

F-ST-SM

CRITICAL

6

20 34 39 56

6

20 68

6

20 68

6

20 68

6

20 68

6

59

6

59

20 68

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

051-7631

2.3.0

7135

Hatch and Audio Connectors

PP5V_S3_USB2_EXTA_F

PM_SLP_S3_L

HDA_SDOUT

PP3V3_S0_DPPWR

DP_CA_DET_Q

HDMI_CEC

DP_ML_F_N<2>

DP_AUX_CH_C_P DP_AUX_CH_C_N

DP_ML_F_P<1>

DP_ML_F_N<0>

DP_ML_F_P<0>

DP_ML_F_N<1>

AUD_MIC_CLK

HDA_SDIN0

AUD_MIC_DATA

HDA_SYNC

USB2_EXTA_F_P USB2_EXTA_F_N

HDA_RST_L

=PPVIN_S0_AUDIO

HDA_BIT_CLK

DP_ML_F_P<2>

DP_ML_F_P<3>

DP_HPD_Q

DP_ML_F_N<3>

67

70

61

37

61

67

60

67

37

7

67

61

67

6

61

6

61

6

61

6

61

SYM_VER-2

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SATA HDD PORT

516S0678

FL4501

12

3 4

CRITICAL

DLP11S

90-OHM-100MA

FL4502

1 2

34

CRITICAL

DLP11S

90-OHM-100MA

C4501

1

2

6.3V

0.1UF

201

X5R

10%

C4502

1

2

6.3V

0.1UF

201

X5R

10%

J4500

1

10

1112 1314 1516 1718 19

2

20

34 56 78 9

54167-0201

CRITICAL

F-ST-SM

L4500

1 2

CRITICAL

FERR-120-OHM-1.5A

0402-LF

C4510

1 2

X7R

4700PF

20110V10%

C4511

1 2

X7R

4700PF

20110V10%

C4515

1 2

201

4700PF

X7R10V10%

C4516

1 2

10V 201X7R

4700PF

10%

19 67

051-7631

2.3.0

7136

SATA Connectors

SYNC_MASTER=CHANGZHANG

SYNC_DATE=02/05/2008

PP3V3_S0_HDD_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

SATA_HDD_R2D_P

SATA_HDD_R2D_UF_N

SATA_HDD_R2D_UF_P

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_D2R_UF_N

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

=PP3V3_S0_HDD

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_N

PLACEMENT_NOTE=Place FL4501 close to J4501

PLACEMENT_NOTE=Place FL4502 close to MCP79

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4500 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4500

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510

PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501

70

67

6

67

7

6

SYM_VER-1

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

OUT1

GND

TPAD

OUT2

OC1*

IN

EN1

EN2

OC2*

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DUAL SWITCH HAS GANGED OUTPUT BOTH SWITCHES WILL TRIP TOGETHER AT 1.5A-2.2A

CONNECT TO RIO CONNECTOR J4200

LAYOUT NOTE:C4602 IS AN EMC BY-PASS CAP FOR J4200

SEL=1 CHOOSE USB

PLACE C4675 NEAR U4675

USB/SMC MUX

SEL=0 CHOOSE SMC

PLACE NEAR U4675

USB 2.0 CONNECTOR

ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS

CONNECT TO 5V S5 or S3 PER LAYOUT

C4602

1

2

10% X5R

10V 201

0.01UF

L4600

90-OHM-100MA

CRITICAL

DLP11S

C4610

1

2

20%

6.3V

CRITICAL

100UF

POLY-TANT

CASE-B2-SM

C4613

1

2

X5R

10uF

20%

603

6.3V

OMIT

C4612

1

2

6.3V 201

X5R

10%

0.1UF

L4602

CRITICAL

FERR-120-OHM-3A

0603

R4677

1

2

201

1/20W MF

5%

10K

U4675

6

7

3

4

5

8

10

9

2

1

CRITICAL

PI3USB102ZLE

TQFN

R4675

1 2

5% MF

1/20W

100

201

C4675

1

2

10% X5R

201

0.1UF

6.3V

D4600

3

1

2

RCLAMP0502B

SC-75

CRITICAL

R4650

12

402

1/16W MF-LF

5%

1K

C4650

1

2

0.47UF

10%

402

CERM-X5R

6.3V

U4600

3

4

1

2

8

5

7

6

9

MSOP

CRITICAL

TPS2052B

R4678

1 2

0

NOSTUFF

5% MF

1/20W

201

SIGNAL_MODEL=EMPTY

R4679

1 2

0

201

1/20W

MF

5%

NOSTUFF

SIGNAL_MODEL=EMPTY

051-7631

71

2.3.0

SYNC_DATE=01/09/2007

USB EXTERNAL CONNECTORS

37

SYNC_MASTER=M70

USB_DEBUGPRT_EN_L

USB_EXTA_MUXED_P

=USB2_EXTA_P

USB_EXTA_MUXED_N

USB_EXTA_MUXED_P

=PP3V42_G3H_SMCUSBMUX

SMC_TX_L

SMC_RX_L

=USB2_EXTA_N

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.42V

PP3V42_G3H_SMCUSBMUX_R

USB_EXTA_MUXED_N

USB2_EXTA_F_P

USB2_EXTA_F_N

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

PP5V_S3_USB2_EXTA_F

=PP5V_S3_EXTUSB

PP5V_S3_USB2_EXTA

VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

=EXTAUSB_OC_L

EXTAUSB_OC_F_L

=USBPWR_EN

70

41

37

68

40

68

35

39

37

8

37

7

39

8

70

37

6

6 6

7

70

8

56

BI

BI BI

BI

D

G S

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Inverted to drive SMC_RESET logic

IPD Connector

516S0591

Power Button Inverter

PLACE R4800,R4801 UNDER L4800

6 8

6

42

6

42

C4800

1

2

OMIT

CERM 402-LF

20%

2.2UF

6.3V

C4801

1

2

6.3V

0.1UF

201

X5R

10%

C4810

1

2

201

0.01UF

10V X5R

10%

C4812

1

2

201

0.01UF

10V X5R

10%

L4812

1 2

0402

600-OHM-300MA

CRITICAL

J4800

25 26

27 28

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24

3 4 5 6 7 8 9

51338-0249

F-ST-SM

CRITICAL

L4813

1 2

0402

CRITICAL

600-OHM-300MA

C4813

1

2

0.01UF

201

10V X5R

10%

R4830

1

2

201

1/20W

MF

5%

1M

Q4830

3

1

2

SSM3K15FV

SOD-VESM-HF

R4831

12

MF

201

5%

1/20W

10K

C4831

1

2

6.3V

0.1UF

201

X5R

10%

L4800

1

2 3

4

CRITICAL

470UH-0.3A-80V ZCYS9480-SM-HF

R4800

1 2

MF-LF

1/10W

603

0

5%

NO STUFF

R4801

1 2

NO STUFF

MF-LF

1/10W

603

0

5%

IPD Connector

051-7631

71

2.3.0

38

TPAD_GND_F

MIN_NECK_WIDTH=0.2mm VOLTAGE=0V

MIN_LINE_WIDTH=0.2mm

=PP5V_S3_TOPCASE

PP5V_S3_TOPCASE_F

MIN_LINE_WIDTH=0.3mm MIN_NECK_WIDTH=0.2mm

VOLTAGE=5V

PP5V_S0_KBDLED_F

PP5V_S3_TOPCASE_F

PP3V42_G3H_IPD_F

LSOC_PRESS_H

SMC_ONOFF_L

SMC_SYS_KBDLED

=USB2_IR_N

=USB2_TPAD_N

=USB2_IR_P

=I2C_TPAD_SDA

=USB2_TPAD_P

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM

VOLTAGE=5V

PP5V_S0_KBDLED_F

PP3V42_G3H_IPD_F

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=3.42V

MIN_LINE_WIDTH=0.20 MM

=PP5V_S0_KBDLED

=PP3V42_G3H_IPD

SMC_ONOFF_L

SMC_ONOFF_H

=PP3V42_G3H_IPD

SMC_SYS_LED

LSOC_PRESS_H_R

=I2C_TPAD_SCL

TPAD_GND_F

SMC_LID

40

70

39

70

39

40

38

49

38

39

38

38 38

38

49

38

39

38

7 6

6

40

6

7

6

40

7

6

38

6

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(OC)

If SMS interrupt is not used, pull up to SMC rail.

(OC)

(DEBUG_SW_1) (DEBUG_SW_2)

(OC)

those designated as inputs require pull-ups.

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

(OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

NOTE: P94 and P95 are shorted, P95 could be spare.

C4902

1

2

603

X5R-CERM

22UF

6.3V

20%

18 41

40 41

6

38 40

C4907

1

2

6.3V

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

0.47UF

CERM-X5R

402

10%

C4903

1

2

0.1UF

X5R

6.3V

10%

201

C4920

1

2

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

0.1UF

201

X5R

6.3V

10%

R4999

1 2

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

402

MF-LF

5%

1/16W

4.7

C4904

1

2

0.1UF

X5R

6.3V

10%

201

XW4900

12

SM

20

50

C4905

1

2

0.1UF

X5R

6.3V

10%

201

20

56

24 56

8

C4906

1

2

0.1UF

X5R

6.3V

10%

201

50

43

8

43

58

43

58

44

6

40 49

40 49 58

37 39 40 41

56

42

R4909

1

2

5%

10K

MF

1/20W

201

41

R4901

1

2

5%

10K

MF

1/20W 201

R4902

1

2

10K

5%

MF

1/20W

201

R4903

1

2

5%

0

NO STUFF

201

MF

1/20W

R4998

1

2

5%

10K

MF

1/20W

201

37

40 49

20

8

40

8

20

8

46

8

46

47

44

47

8

40 41

40

40 41

6

38 40

42

40

8

37 39 40 41

8

18 41

20

24

41

20

18 41

U4900

B12

A13 A12

B13

D11 C13

C12

D10

D13

E11

D12 F11

E13

E12 F13

E10

A9

D9 C8

B7 A8

D8

D7 D6

D4

A5

B4 A1

C2 B2

C1

C3

G2 F3

E4

L13

K12 K11

J12

K13 J10

J11

H12

N10

M11

L10 N11

N12

M13 N13

L12

A7

B6 C7

D5 A6

B5

C6

J4 G3

H2

G1 H4

G4 F4

F1

LGA-HF

OMIT

HS82117

U4900

N3

N1

M3 M2

N2

L1 K3

L2

B8

C9 B9

A10 C10

B10

C11 A11

G11

G13

F12 H13

G10 G12

H11

J13

M10

N9

K10

L8 M9

N8

K9 L7

K1

J3

K2 J1

K4

K5

N5 M6

L5

M5 N4

L4 M4

M8

N7

K8 K7

K6

N6 M7

L6

E2 F2

J2

A4 B3

C4

LGA-HF

OMIT

HS82117

U4900

M12

L11

L9

H3

A2

D1 H1

E5

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

OMIT

LGA-HF

HS82117

8

47

8

20 40

8

6

38

20

18 41 68

24

24 68

6

38

42

6

20 34 35 56

20 34 40 56

40

24 68

42

40

051-7631

2.3.0

7139

SMC

SYNC_MASTER=M97

SYNC_DATE=02/21/2008

RSMRST_PWRGD

PM_RSMRST_L IMVP_VR_ON

SMC_PROCHOT_3_3_L

SMC_P10 SMC_EXCARD_PWR_EN ALL_SYS_PWRGD

PM_PWRBTN_L

ESTARLDO_EN

SMC_P24

SMC_P26

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

LPC_CLK33M_SMC LPC_SERIRQ

SMC_P41 SMB_MGMT_DATA SMS_PWRDN

SMC_GFX_THROTTLE_L SMC_SYS_KBDLED

SMC_TX_L SMC_RX_L SMB_0_S0_CLK

SMC_PM_G2_EN

SMC_ADAPTER_EN

SMC_BIL_BUTTON_L

SMC_CPU_ISENSE SMC_ACIN_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_PBUS_ISENSE

SMC_WAKE_SCI_L

SMC_TX_L SMC_RX_L SMB_MGMT_CLK

SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK SMB_0_S0_DATA

SMC_LRESET_L

LPC_PWRDWN_L

PM_CLKRUN_L

SMC_XTAL

GND_SMC_AVSS

SMC_RESET_L

SMC_NMI

SMC_VCL

SMC_KBC_MDE

SMC_TRST_L

PP3V3_S5_AVREF_SMC =PP3V42_G3H_SMC

PP3V3_S5_SMC_AVCC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

ALS_GAIN

SMC_FWE

SMC_THRMTRIP

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_CLK

SMB_A_S3_DATA

SMB_BSA_CLK

SMB_BSA_DATA

=SMC_SMS_INT

MCP_SAFE_MODE

SMC_LID

SMC_SYS_LED

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

SMC_CASE_OPEN

ALS_RIGHT

ALS_LEFT

SMC_NB_DDR_ISENSE

SMC_NB_CORE_ISENSE

SMC_ANALOG_ID

SMS_Z_AXIS

SMS_Y_AXIS

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_RUNTIME_SCI_L

PM_SYSRST_L

SMC_PA1

SMC_PA0

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

SMC_PA5 SYS_ONEWIRE

SMC_ODD_DETECT ISENSE_CAL_EN SMC_EXCARD_CP

PM_BATLOW_L

MEM_EVENT_L

USB_DEBUGPRT_EN_L

SMC_EXTAL

SMC_MD1

58 44 43

70

40

8

40

7

70

8

40

D

SG

D

SG

GND

OUT

IN

CD

GND

NC

OUT

IN

D

SG

D

SG

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SMC 3.3V to 1.05V Level Shifting

Place R5011 on top side Place R5010 on bottom side Place both near board edge

SMC AVREF Supply

SMC Crystal Circuit

Silk: "PWR BTN"

SMC 1.05V to 3.3V Level Shifting

APN: 197S0231

Debug Power Button

SMC Reset Button / Brownout Detect

NC

SMC_MANUAL_RST_L in the event of a keyboard SMC Reset generated when left shift,option,and control and the power button is depressed.

Q5030 will pull down

Place R5001 on bottom side

Silk: "SMC RST" near board edge

C5021

1 2

15PF

NPO 201

5%

25V

R5080

1 2

10K

R5081

1 2

100K

R5096

1 2

10K

R5082

1 2

2.0K

R5083

1 2

470K

R5071

1 2

3.3K

MF

201

5%

1/20W

R5070

1

2

3.3K

MF 201

5% 1/20W

Q5077

2

6

1

BC847BV-X-F

SOT563-HF

Q5077

5

3

4

SOT563-HF

BC847BV-X-F

R5078

1

2

470

MF 201

5% 1/20W

Y5020

2 4

1 3

CRITICAL

20MHZ

SM-2.5X2.0MM

R5097

1 2

10K

R5085

1 2

10K

R5086

1 2

10K

R5092

1 2

10K

R5095

1 2

100K

R5087

1 2

10K

R5049

1 2

10K

R5073

1 2

100K

R5084

1 2

10K

Q5030

6

2

1

SSM6N15FEAPE

SOT563

Q5030

3

5

4

SOT563

SSM6N15FEAPE

VR5065

3

1 2

CRITICAL

REF3333

SOT23-3

R5011

1

2

NOSTUFF

402

0

MF-LF

5% 1/16W

R5098

1 2

10K

U5000

5

3

2

4

1

CRITICAL

NCP303LSN

SOT23-5-HF

Q5001

3

5

4

SSM6N15FEAPE

SOT563

Q5001

6

2

1

SOT563

SSM6N15FEAPE

39 41

R5000

1

2

1K

MF 201

5% 1/20W

C5000

1

2

10% X5R

0.1UF

201

6.3V

C5001

1

2

10% 10V

0.01UF

201

X5R

R5001

1

2

603

NOSTUFF

0

MF-LF

5% 1/10W

C5020

1 2

201

15PF

NPO

5%

25V

C5067

1

2

10% X5R

10V 201

0.01UF

C5066

1

2

6.3V

20% 603

10uF

X5R

OMIT

6

38 39 40

R5010

1

2

NOSTUFF

0

MF-LF

5% 1/8W

805

C5065

1

2

10% 402

0.47UF

CERM-X5R

6.3V

71

SYNC_DATE=01/09/2007

2.3.0

SYNC_MASTER=M70

40

051-7631

SMC SUPPORT

SMC_RESET_L

SMC_MANUAL_RST_L1

SMC_MANUAL_RST_L

=PP3V42_G3H_SMC

SMC_ONOFF_H

LSOC_PRESS_H

SMC_LID

SMC_SMS_INT_L

SMC_ONOFF_L

SMC_PROCHOT

SYS_ONEWIRE

SMC_BC_ACOK

MIN_NECK_WIDTH=0.2 MM

GND_SMC_AVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

SMC_TX_L SMC_RX_L

SMC_ODD_DETECT

SMC_BS_ALRT_L

SMC_TDI

SMC_TMS SMC_TDO

SMC_EXTAL

SMC_XTAL

SMC_ONOFF_L

CPU_PROCHOT_L_R

SMC_PROCHOT_3_3_L

=PP3V3_S0_SMC_LS

=PP1V05_S0_SMC_LS

CPU_PROCHOT_BUF

CPU_PROCHOT_L

=PP3V42_G3H_SMCVREF

SMC_THRMTRIP

=PP3V42_G3H_SMC

SMC_ADAPTER_EN

SMC_CASE_OPEN

MAKE_BASE=TRUE

PM_SLP_S4_LPM_SLP_S5_L

CPU_PROCHOT_L

=PP3V3_S3_SMC

PM_THRMTRIP_L

SMC_TCK

65

58

40

50

56

50

40

39

58

44

41

49

39

40

39

40

65

39

49

38

49

43

70

39

41

38

13

39

20

34

13

41

7

38

6

8

39

37

39

6

39

6

39

7

9

7

39

7

8

39

20 39

9

7

9

39

BI

IN

OUT

IN

OUT

IN

BI

IN

BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

OUT OUT

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

IN

OUT

IN

OUT

IN

OUT

IN

OUT

GS

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1 MHz

42 MHz

Frequency

25 MHz

31 MHz

MCP79 SPI Frequency Select

selected w/ R5190,R5191,R5192,R5193

Any of the 4 frequencies can be

1

SPI_MOSI

0

SPI_CLK

0

1

0

1

Now MCP_CS1_YES and MCP_CS1_NO determines external MUX option.

From Frank Card

To Frank Card

SPI MUX BYPASS

Internal MUX in rev B01 does not work as intended.

Pull-up on debug card

516S0573

MCP79 Internal SPI MUX Support

LPC+SPI Connector

Not supported in Rev A01 MCP79 silicon

MCP SPI Override Options

SEL LOW WILL OUTPUT TO M (FRANKCARD ROM)

SEL HIGH WILL OUTPUT TO D (ON BOARD ROM)

R5143

1 2

MCP_CS1_YES

0

PLACEMENT_NOTE=PLACE NEAR R5147

5%

1/20W

MF

201

R5142

1 2

MCP_CS1_NO

1/20W

MF

0

5%

PLACEMENT_NOTE=Place near J5100

201

20

37 39 40

39

39 40

39

24

39 40

18 39

41

18 39 68

41

18 39 68

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

LPCPLUS

55909-0374

M-ST-SM

CRITICAL

17

37 39 40

39

39 40

18 39

41

18 39 68

24 68

20 41 68

41

41 48 68

48 68

R5144

1

2

MCP_CS1_NO

201

MF

1/20W

5%

20K

R5126

1 2

201

MF

1/20W

MCP_CS1_NO

0

5%

41

41 48 68

C5114

1

2

LPCPLUS

0.1UF

6.3V X5R

10% 201

R5127

1 2

201

MF

1/20W

MCP_CS1_NO

0

5%

C5124

1

2

LPCPLUS

0.1UF

10%

6.3V X5R 201

R5190

1

2

10K

5%

1/20W

MF

201

U5110

6

7

3

4

5

8

10

9

2

1

LPCPLUS

PI3USB102ZLE

CRITICAL

TQFN

U5120

6

7

3

4

5

8

10

9

2

1

LPCPLUS

TQFN

PI3USB102ZLE

CRITICAL

20 68

20 41 68

R5146

1 2

MCP_CS1_YES&LPCPLUS_NOT

201

MF

1/20W

5%

PLACEMENT_NOTE=PLACE NEXT TO U1400

0

R5157

1 2

201

MF

1/20W

0

LPCPLUS_NOT

5%

R5156

1 2

201

MF

1/20W

LPCPLUS_NOT

5%

0

R5158

1 2

201

MF

1/20W

LPCPLUS_NOT

5%

0

20 41 68

R5191

1

2

10K

5%

1/20W

MF

201

41 48 68

R5193

1

2

NO STUFF

5%

10K

201

MF

1/20W

R5192

1

2

NO STUFF

1/20W

10K

5%

201

MF

R5141

1

2

MCP_CS1_YES

201

1/20W

MF

470

5%

18

Q5140

3

1

2

MCP_CS1_YES

SOD-VESM-HF

SSM3J16FV

R5140

1

2

201

MF

1/20W

5%

100K

SYNC_DATE=01/24/2008

2.3.0

051-7631

41 71

LPC+SPI Debug Connector

SYNC_MASTER=CHANGZHANG

SPI_CLK_R

SPI_MOSI_R

SPIROM_USE_MLB

=PP3V42_G3H_LPCPLUS

SMC_MD1 SMC_TX_L

=PP3V3_S5_ROM

SPI_CLK_MUX SPI_MOSI_MUX

SPI_ALT_CLK SPI_ALT_MOSI

=PP3V42_G3H_LPCPLUS

LPC_AD<1>

=PP3V3_S0_LPCPLUS

SMC_TRST_L

SMC_TDO

DEBUG_RESET_L

SMC_TMS

LPC_FRAME_L

SPI_ALT_MISO

PM_CLKRUN_L

SPI_ALT_MOSI

LPC_AD<0>

SMC_TDI

LPC_SERIRQ

SPI_ALT_CLK

LPC_AD<3>

LPC_AD<2>

LPC_CLK33M_LPCPLUS

=PP5V_S0_LPCPLUS

=PP3V42_G3H_LPCPLUS

=SPI_CS1_R_L_USE_MLB

SPIROM_USE_MLB

SPI_ALT_CS_L

LPC_PWRDWN_L

LPC_FRAME_R_L

SMC_TCK

LPCPLUS_GPIO

LPC_FRAME_PU

SMC_RESET_L

MAKE_BASE=TRUE

SPI_CS1_R_L_USE_MLB

SPI_MISO

SPI_ALT_CS_L_MUX

=PP3V42_G3H_LPCPLUS

SPI_MLB_CS_L_MUX

SPI_ALT_MISO

SPI_MOSI_R

SPI_MISO

SPI_CLK_MUX

SPI_MOSI_MUX

SPI_MISO_MUX

SMC_NMI SMC_RX_L

SPIROM_USE_MLB

SPI_ALT_CS_L

=PP3V3_S5_ROM

SPI_MLB_CS_L

SPI_MISO_MUX

SPI_CLK_R

SPI_CS0_R_L

25MHz is selected with R5190 and R5191

48

41

7

41

7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP79 SMBUS "0" CONNECTIONS

Battery Manager - (Write: 0x?? Read: 0x??)

Battery Temp - (Write: 0x?? Read: 0x??)

Battery

TMP102: U5550

(Write: 0x90 Read: 0x91)

Power Supply Temp

MCP79

MCP79 SMBUS "1" CONNECTIONS

(MASTER?)

SMC

(MASTER)

U4900

SMC "0" SMBus Connections

(Write: 0x92 Read: 0x93)

(Write: 0x90 Read: 0x91)

TRACKPAD

J4800

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC

U4900

(MASTER)

U4900

SMC

U2900

U2901

Vref DACs

The bus formerly known as "Battery B"

(Write: 0x98 Read: 0x99)

Margin Control

(Write: 0x30 Read: 0x31)

SMC "Management" SMBus Connections

(MASTER)

U4900

SMC

MCP79

(MASTER)

U1400

J4100

M93 Wireless Card

(Write: 0x98 Read: 0x99)

CPU Temp

EMC1403-5: U5515

Air Vent Temp

(Write: 0x92 Read: 0x93)

TMP102: U5560

(Write: 0x92 Read: 0x93)

Front Edge Temp

TMP102: U5570

(Write: 0x12 Read: 0x13)

Battery Charger

(See Table)

J6950

ISL6258A - U7900

Battery

SMC "Battery A" SMBus Connections

U4900

SMC

(MASTER)

(Write: 0x72 Read: 0x73)

ALS

J9000

SMC "B" SMBus Connections

R5250

1

2

10K

MF

1/20W

201

5%

R5251

1

2

201

5%

10K

1/20W MF

R5230

1

2

402

MF-LF

1/16W

5%

2.2K

R5231

1

2

402

MF-LF

1/16W

5%

2.2K

R5211

1

2

1/20W MF

4.7K

201

5%

R5210

1

2

4.7K

5%

MF

1/20W

201

R5201

1

2

5% 1/20W

201

MF

4.7K

R5200

1

2

4.7K

MF

201

5%

1/20W

R5221

1

2

5% 1/20W

201

MF

4.7K

R5220

1

2

MF

201

5%

1/20W

4.7K

R5261

1

2

201

MF

1/20W

5%

10K

R5260

1

2

MF

201

5%

10K

1/20W

R5240

1

2

MF

5%

201

1/20W

2.2K

R5241

1

2

5% 1/20W

201

MF

2.2K

2.3.0

42 71

051-7631

SYNC_MASTER=BEN

SYNC_DATE=02/04/2008

M97 SMBUS CONNECTIONS

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

=I2C_ALS_SDA

SMB_BSA_DATA

SMB_BSA_CLK

=SMBUS_CHGR_SDA

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

=PP3V42_G3H_SMBUS_SMC_BSA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

THRM_FRONT_SMB_CLK THRM_FRONT_SMB_DATA

THRM_VENT_SMB_CLK THRM_VENT_SMB_DATA

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

=SMB_AIRPORT_DATA

=I2C_TPAD_SDA

=I2C_TPAD_SCL

SMB_MGMT_DATA

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

MAKE_BASE=TRUE

SMBUS_MCP_1_CLK

=PP3V3_S5_SMBUS_MCP_1

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

SMB_MGMT_CLK

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

=PP3V3_S3_SMBUS_SMC_MGMT

SMB_B_S0_DATA

SMB_B_S0_CLK

SMB_A_S3_DATA

SMB_A_S3_CLK

=SMB_AIRPORT_CLK

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_0_S0

SMB_0_S0_CLK

SMB_0_S0_DATA

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

=I2C_ALS_SCL

MAKE_BASE=TRUE

SMBUS_MCP_0_CLK

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

THRM_PS_SMB_CLK THRM_PS_SMB_DATA

=PP3V3_S0_SMBUS_MCP_0

=SMBUS_CHGR_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

68

20

59

34

38

68

12

34

59

12

69

6

39

58

49

7

69

45

6

39

20

7

6

39

25

7

39

6

7

69

7

39

69

6

69

45

7

58

OUT

D

N-CHANNEL

P-CHANNEL

G

S

D

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE R5310.C5310 NEAR SMC

PBUS VOLTAGE SENSE

ACIN VOLTAGE SENSE

MCP VOLTAGE SENSE

divider when high.

Enables PBUS VSense

TO PBUS CURRENT SENSOR

Place RC close to SMC

RTHEVENIN = 4573 OHMS

MAX 16.5V + 10% ACIN = 3.0V SMC_ACIN_VSENSE

R5300 and R5301 VALUES CHOSEN FOR RC FILTER @ 4.53KOHM THEVENIN RESISTANCE

PLACE C5300 NEAR SMC

C5300

1

2

CERM-X5R 402

6.3V

10%

0.22UF

R5300

1

2

201

27.4K

MF

1% 1/20W

R5301

1

2

5.36K

201

MF

1/20W

1%

C5310

1

2

402

10%

0.22UF

6.3V CERM-X5R

R5310

1 2

1/20W

MF

1%

201

4.53K

39

R5385

1

2

MF

1/20W

201

1%

12.7K

C5385

1

2

0.22UF

X5R

20%

6.3V

402

R5386

1

2

201

MF

1/20W

1%

6.98K

R5316

1

2

100K

201

MF

1/20W

1%

Q5315

6

3

2

5

1

4

NTUD3127CXXG

SOT-963

56

R5315

1

2

402

1/16W MF-LF

100K

1%

Voltage Sensors

43

SYNC_MASTER=M70

71

2.3.0

SYNC_DATE=01/09/2007

051-7631

SMC_PBUS_VSENSE

=PBUSVSENS_EN

GND_SMC_AVSS

SMC_GPU_VSENSE

GND_SMC_AVSS

SMC_ACIN_VSENSE

PPVDCIN_G3H_PRE

GND_SMC_AVSS

PBUSVSENS_EN_L

PBUSISENSE_EN_L

=PPVCORE_S0_MCP_VSENSE

MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.20 mm

PPBUS_G3HRS5_VSENSE

=PPBUS_G3HRS5

PBUSVSENS_EN_L_DIV

58

44

43

40

70

40

39

58

39

7

70

7

OUT

V+

-INF

+IN

V-

VREG

OUT

THM PAD

SHDN

-INS

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP VCore Current Sense

PLACE C CLOSE TO SMC

LTC6102 DISABLED WHEN SHDN=1 LTC6102 ENABLED WHEN SHDN=0

PBUS Current Sense

MCP VCore Current Sense Filter

Place RC close to SMC

39

C5472

1

2

402

20%

X5R

6.3V

0.22UF

R5416

1 2

201

MF

1/20W

4.53K

1%

C5489

1

2

0.22UF

6.3V X5R

20%

402

R5489

1

2

201

MF

4.53K

1% 1/20W

C5480

1

2

16V

10%

402

X5R

0.1UF

R5481

1

2

MF-LF

1%

402

21

1/16W

U5480

2

8

1

4

3

9

5

7

6

CRITICAL

DFN

LTC6102AP

51

Current Sensing

SYNC_DATE=02/04/2008

2.3.0

7144

051-7631

SYNC_MASTER=YUNWU

MCPCORE_IOUT

SMC_NB_CORE_ISENSE

GND_SMC_AVSS

=PPBUSB_G3H

PBUSISENSE_EN_L

=PPBUSA_G3H

PBUS_ISENSE_VREG

PBUS_ISENSE_IN_NEG

SMC_PBUS_ISENSE

GND_SMC_AVSS

58

44

43

40

58

40

39

7

43

7

39

GND

V+

ADD0

ALERT

SCL

SDA

BI

VDD

THERM*

DN2

SMDATA

SMCLK

ALERT*

GND

DP1

THRM_PAD

DN1

DP2

BI

GND

V+

ADD0

ALERT

SCL

SDA

BI

GND

V+

ADD0

ALERT

SCL

SDA

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LOCAL TEMP NEAR POWER SUPPLIES

(Write: 0x90 Read: 0x91)

LOCAL TEMP NEAR AIR VENT

(Write: 0x92 Read: 0x93)

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

PLACEMENT NOTE: PLACE U5515 NEAR CPU

LOCAL TEMP NEAR FRONT EDGE

CPU/MCP T-Diode Thermal Sensor

(Write: 0x92 Read: 0x93)

DETECT CPU DIE TEMPERATURE

DETECT MCP DIE TEMPERATURE

U5550

4

3

2

1

6

5

CRITICAL

HPA00330AI

SOT563

R5517

1

2

5%

10K

MF

1/20W 201

R5516

1

2

201

1/20W

MF

5%

10K

42

C5515

1

2

201

0.1uF

X5R

6.3V

10%

U5515

CRITICAL

EMC1403-1

DFN

C5521

1

2

2.2NF

201

SIGNAL_MODEL=EMPTY

10V X5R

10%

R5515

1 2

47

5% MF

1/20W

201

C5520

1

2

10% X5R

10V

SIGNAL_MODEL=EMPTY

201

2.2NF

9

C5560

1

2

10% X5R

6.3V 201

0.1UF

U5560

4

3

2

1

6

5

SOT563

CRITICAL

HPA00330AI

42

20

C5570

1

2

10% X5R

6.3V 201

0.1UF

U5570

4

3

2

1

6

5

SOT563

CRITICAL

HPA00330AI

42

C5550

1

2

10% X5R

0.1UF

201

6.3V

TEMPERATURE SENSORS

SYNC_DATE=01/09/2007

7145

2.3.0

SYNC_MASTER=M70

051-7631

=PP3V3_S0_THRM_SNR

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

MCP_THMDIODE_N

MCP_THMDIODE_P

CPU_THERMD_N

CPU_THERMD_P

CPUTHMSNS_THERM_L

CPUTHMSNS_ALERT_L

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

THRM_FRONT_SMB_DATA

THRM_FRONT_SMB_CLK

=PP3V3_S0_THRM_SNR

THRM_VENT_SMB_DATA

THRM_VENT_SMB_CLK

=PP3V3_S0_THRM_SNR

THRM_PS_SMB_DATA THRM_PS_SMB_CLK

45

7

70

7

D

GS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0658

GND

MOTOR CONTROL

NC

FAN CONNECTOR

NC

TACH

5V DC

R5665

1 2

47K

201

MF

1/20W

5%

R5660

1

2

201

47K

1/20W

5% MF

R5661

1

2

100K

MF

1/20W

5%

201

Q5660

3

1

2

SOD-VESM-HF

SSM3K15FV

J5600

5

6

1 2 3 4

SM04B-SURKHF-GAN-TF-LF-SN

F-RT-SM

CRITICAL

051-7631

71

SYNC_MASTER=M70

46

2.3.0

SYNC_DATE=01/09/2007

Fan

FAN_RT_PWM

FAN_RT_TACH

SMC_FAN_0_CTL

SMC_FAN_0_TACH

=PP5V_S0_FAN =PP3V3_S0_FAN

7

6

39

6

7

OUT

FS PD ST

RES RES

GND

NC

NC NC

NC

NC NC

VOUTX

VOUTY

VOUTZ

VDD

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Desired orientation when

SUDDEN MOTION SENSOR

Front of system

+X

in correct orientation

Circle indicates pin 1 location when placed

+Y

NC

placed on board top-side:

+Z (up)

C5922

1

2

0.1UF

10% X5R

6.3V 201

39

C5925

1

2

201

X5R

10%

0.01UF

10V

C5924

1

2

X5R

10%

201

0.01UF

10V

C5923

1

2

201

10% X5R

0.01UF

10V

U5900

1

7

3 6 9

11 13 16

5

15

4

2

14

12

10

8

CRITICAL

AP344ALH

LGA

R5922

1

2

201

MF

10K

1/20W

5%

39

C5900

1

2

X5R

4V 603

10UF

20%

R5921

1

2

201

10K

5%

1/20W

MF

051-7631

47 71

2.3.0

SYNC_MASTER=M76_MLB

SYNC_DATE=01/12/2007

Sudden Motion Sensor (SMS)

SMS_Y_AXIS

SMS_SELFTEST

SMS_Z_AXIS

SMS_X_AXIS

=PP3V3_S3_SMS

SMS_PWRDN

7

IN

W*/VPP

VCC

C

Q

HOLD*

S*

D

PAD

VSS

THM

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

R6100

1

2

1/20W

MF

201

3.3K

5%

R6150

1 2

201

MF

1/20W

5%

0

PLACEMENT_NOTE=Place close to U6100

41 68

U6100

6

5

7

2

1

9

8

4

3

VFQFPN

OMIT

CRITICAL

M25P32

R6152

1 2

201

MF

1/20W

5%

0

PLACEMENT_NOTE=Place close to U6100

41 68

R6105

1 2

0

5%

MF-LF

1/16W

402

C6100

1

2

201

X5R

6.3V

10%

0.1UF

R6101

1

2

201

MF

1/20W

3.3K

5%

48 71

2.3.0

051-7631

SPI ROM

SYNC_MASTER=CHANGZHANG

SYNC_DATE=02/15/2008

SPI_MISO_MUX

SPI_WP_L

SPI_MISO_R

SPI_HOLD_L

=PP3V3_S5_ROM

SPI_MLB_CS_L

SPI_MOSI

SPI_MOSI_MUX

SPI_CLK_MUX

SPI_CLK

41

68

7

68

D

SG

D

SG

D

GS

D

S G

V-

V+

G

S

D

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

D

SG

D

SG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BATTERY INTERFACE

(PP3V42_G3H_REG)

<Ra>

(Switcher limit)

200mA max output

Vout = 3.425V

P3V42G3H_SHDN_L in the event

OneWire OVP

518S0507

and the power button is depressed.

generated when left shift,option,and control

of a keyboard SMC Reset

Q6990 will pull down

NC

Vout = 1.25V * (1 + Ra / Rb)

<Rb>

DC-JACK INTERFACE

518S0540

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

R6932

1

2

1/16W MF-LF

24.3K

402

1%

C6930

1

2

25V

0.1UF

10%

402

X5R

J6980

1 2 3 4 5

CRITICAL

M-RT-SM

WTB-PWR-M82

R6900

1

2

MF-LF

5%

100K

1/16W 402

C6903

1

2

0.001UF

10% 50V

402

CERM

R6901

1

2

402

1%

24.3K

1/16W MF-LF

R6904

1

2

MF-LF 402

1/16W

5%

47K

R6911

1 2

5%

100K

402

MF-LF

1/16W

R6905

1 2

1/8W

5%

805

MF-LF

47

R6902

1 2

1/16W MF-LF

5% 402

1K

C6907

1

2

50V

0.001UF

10% CERM

402

Q6920

6

2

1

SOT563

SSM6N15FEAPE

Q6910

3

5

4

SSM6N15FEAPE

SOT563

Q6980

3

1

2

SSM3K15FV

SOD-VESM-HF

R6940

1 2

10

5% 1/8W

805

MF-LF

Q6920

3

5

4

SSM6N15FEAPE

SOT563

C6902

1

2

0.01UF

10%

402

X7R

25V

R6906

1

2

MF-LF

200K

5% 1/16W

402

R6903

1

2

5% 1/16W MF-LF

200K

402

R6931

1

2

1/20W

5% MF

201

100K

R6933

1

2

MF

1/20W 201

5%

100K

U6990

2

4

1

3

5

LM397

SOT23-5-HF

CRITICAL

J6900

1 2 3 4 5 6 7 8 9

WTB-PWR-M82

M-RT-SM

CRITICAL

C6900

1

2

X7R 402

25V

10%

0.01UF

L6900

1 2

SM-LF

FERR-50-OHM

CRITICAL

D6901

6

5

4

1

2

3

HN2S02FUAPE

SOT-363

CRITICAL

Q6940

3

1

2

SOT-723-HF

SSM3J15FVAPZE

U6900

2

3

1

5

7

8 4

9

6

LTC3470A

DFN

CRITICAL

C6994

1

2

CERM-X5R

10%

402

6.3V

0.22UF

C6995

1

2

22PF

5% 50V CERM 201

C6999

1

2

22UF

20%

6.3V CERM 805

C6990

25V CASE-B2-SM

20%

5.6UF

POLY-TANT

CRITICAL

C6991

1

2

0.22UF

10%

6.3V

CERM-X5R

402

R6995

1

2

348K

1%

1/20W

MF

201

R6996

1

2

200K

1%

1/20W

MF

201

R6990

1

2

5% MF

1/20W

201

100K

Q6990

6

2

1

SSM6N15FEAPE

SOT563

Q6990

3

5

4

SSM6N15FEAPE

SOT563

L6995

1 2

CDPH4D19FHF-SM

33UH

CRITICAL

D6900

3

1

2

NO STUFF

SC-75

RCLAMP2402B

CRITICAL

F6900

1 2

1206-1

6AMP-24V

CRITICAL

SYNC_MASTER=M70

DC-In & Battery Connectors

SYNC_DATE=01/09/2007

49 71

051-7631

2.3.0

SMC_BC_ACOK

ADAPTER_SENSE

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=18.5V MIN_LINE_WIDTH=0.6 MM

PP18V5_DCIN

SYS_ONEWIRE_BILAT

ONEWIRE_EN

=PPVIN_G3H_P3V42G3H

PP18V5_DCIN_ONEWIRE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=18.5V MIN_LINE_WIDTH=0.25 MM

P3V42G3H_BOOST

ONEWIRE_DCIN_DIV

MIN_NECK_WIDTH=0.2 mm

PP3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm VOLTAGE=3.42V

=SMBUS_BATT_SCL

P3V42G3H_SHDN_L

LSOC_PRESS_H

SMC_ONOFF_H

P3V42G3H_SHDN_L1

=PPVIN_G3H_DCIN

=PPDCIN_G3H

ONEWIRE_PWR_EN_L

BATT_POS_F

PPVBATT_G3H_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

SYS_ONEWIRE

BATT_POS_F

SMC_BS_ALRT_L

=SMBUS_BATT_SDA

ONEWIRE_ESD

ONEWIRE_OV

SMC_BC_ACOK_ONEWIRE_R

BATT_POS

=PP3V42_G3H_REG

P3V42G3H_FB

PPDCIN_G3H_R

MIN_LINE_WIDTH=0.3 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

ONEWIRE_PWR_EN_L_DIV

=PP18V5_G3H_CHGR

58

40

70

40

58

40

58

39

24

58

39

6

7

70

42

38

7

49

39

49

6

42

6

7

IN

OUT

IN

DPRSLPVR

VID6 VID5

SOFT

VID4

RBIAS

PGOOD VR_TT*

VDIFF

COMP

FDE

3V3 CLK_EN* VR_ON

NTC

FB

VW

NC

VSS

TPAD

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

PMON

PHASE

UGATE

VSSP

LGATE

VCCP

VDDVIN

DPRSTP*

VID0

VID1

VID3 VID2

BOOT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

(GND)

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

(IMVP6_VW)

NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY.

MIN_LINE_WIDTH MIN_NECK_WIDTH

(IMVP6_VO)

MIN_NECK_WIDTH

(IMVP6_VSUM)

ERT-J1VR103J

(IMVP6_FB)

FROM SMC

PLACE R7110 WITH NO STUB ON PM_DPRSLPVR

MIN_LINE_WIDTH

IMVP6 CPU VCORE REGULATOR

(IMVP6_PHASE)

MAX CURRENT = 30A

(IMVP6_VO)

PWM FREQ. = 300kHz

(IMVP6_VO)

XW7100

1

2

SM

OMIT

R7142

1

2

201

20K

MF

1/20W

1%

8 9

13 65

39

24

R7145

1

2

1% 1/20W

4.53K

MF 201

R7146

1

2

1%

MF-LF

1/16W

7.68K

402

R7101

1 2

0

5%

MF-LF

1/16W

402

C7101

1

2

6.3V CERM

OMIT

402

1UF

10%

R7103

1 2

5%

0

1/20W MF 201

C7103

1

2

402-1

X5R

1UF

10%

6.3V

OMIT

R7120

1

2

2.21K

201

1/20W MF

1%

R7122

1

2

1/20W

15K

MF

1%

201

C7122

1

2

25V NP0-C0G

5%

56PF

201

C7123

1

2

16V X7R 201

1000PF

10%

R7123

1

2

6.04K

1/20W

1%

201

MF

R7141

1%

MF

1/20W

201

8.66K

R7140

1

2

MF 201

806

1/20W

1%

C7140

1

2

330PF

16V X7R

201

10%

C7143

1

2

201

0.01UF

10% 10V X5R

C7130

1 2

16V

201

X7R

1000PF

10%

C7131

1 2

1000PF

201

16V X7R

10%

C7132

1 2

330PF

201

X7R

16V

10%

R7131

1

2

1/20W

5%

0

MF 201

C7142

1

2

10.0V CERM-X5R 402

0.12UF

10%

C7111

1 2

16V X7R

0.015uF

402

10%

R7116

1 2

147K

201

MF

1/20W

1%

C7120

1

2

50V CERM

5%

180PF

402

C7141

1

2

1000PF

201

X7R

16V

NO STUFF

10%

R7143

1

2

1/20W MF

1%

3.57K

201

C7133

1 2

6.3V

201

0.1UF

X5R

10%

R7144

1

2

CRITICAL

10KOHM-5%

0603-LF

20 65

R7104

1 2

2.2

MF-LF

5% 1/16W

402

R7115

1 2

5%

MF

1/20W

0

NO STUFF

201

Q7100

5

4

1 2 3

RJK0305DPB

CRITICAL

LFPAK-HF

R7121

1

2

1%

201

1/20W MF

374K

C7121

1

2

50V X7R-CERM

270PF

402

10%

R7102

1 2

MF-LF

1/16W

402

5%

0

L7100

1 2

CRITICAL

0.36UH-30A-1.05M-OHM

PCMB103T

R7134

1 2

1/20W

1%

201

MF

100

C7102

1

2

603

0.22UF

16V X7R

10%

R7100

1 2

MF-LF 402

1/16W

5%

0

C7153

1

2

25V X5R

1UF

10%

603-1

R7130

1

2

1/20W

1% MF

100

201

C7150

1

2

CASE-B2-SM

POLY-TANT

CRITICAL

20%

47UF

10V

C7151

1

2

CRITICAL

CASE-B2-SM

POLY-TANT

47UF

20% 10V

C7152

1

2

25V X5R

1UF

10%

603-1

C7100

1

2

CERM

6.3V

1UF

10%

402

OMIT

R7111

1

2

MF

1%

201

1/20W

499

C7104

1

2

10% 16V

603

X7R

0.22UF

R7132

1

2

5%

0

MF 201

1/20W

R7110

1

2

499

1%

201

1/20W

MF

U7100

39

22

38

9

15

36

37

14

10

1

26

21

5

7

40

24

2

3

13

6

41

23

27

20

11

28

29

30

31

32

33

34

18

16

35

4

12

19

25

17

8

CRITICAL

ISL6261A

QFN

R7124

1 2

1K

201

MF

1/20W

1%

C7124

1

2

0.01UF

201

10V X5R

10%

R7190

1 2

1%

4.53K

1/20W MF 201

C7190

1

2

0.22UF

20%

6.3V X5R 201

Q7151

5

4

1 2 3

RJK0328DPB

CRITICAL

LFPAK-HF

SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

IMVP6 CPU VCore Regulator

2.3.0

50 71

051-7631

IMVP6_BOOT_RC

IMVP6_LGATE

IMVP6_CPU_ISENSE

IMVP6_DROOP

IMVP6_VSEN_P

IMVP6_RBIAS

IMVP6_VSEN_N

=PPVCORE_S0_CPU_REG

MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

MIN_LINE_WIDTH=0.25 MM

PP5V_S0_IMVP6_VDD

IMVP6_BOOT

IMVP6_OCSET IMVP6_VO

IMVP6_DFB

IMVP6_VSUM

IMVP6_PVCC

VOLTAGE=5V

=PP5V_S0_CPU_IMVP

GND_IMVP6_SGND

CPU_VID<6>

CPU_VID<3>

CPU_VID<0>

IMVP_DPRSLPVR

IMVP6_VR_TT

IMVP6_SOFT

IMVP6_FB IMVP6_COMP IMVP6_VW

=PPVIN_S5_CPU_IMVP

IMVP6_PHASE

PM_DPRSLPVR

GND_IMVP6_SGND

0.50 MM 0.20 MM

IMVP6_FB_RC

CPU_VCCSENSE_P

CPU_PROCHOT_L

0.20 MM

1.5 MM

IMVP6_LGATE

0.20 MM

IMVP6_PHASE

1.5 MM

0.20 MM

1.5 MM

IMVP6_UGATE

IMVP6_VDIFF_RC

0.20 MM0.25 MM

IMVP6_BOOT

=PP3V3_S0_IMVP

IMVP6_VSUM

0.25 MM 0.20 MM

IMVP6_VDIFF

0.20 MM0.25 MM

0.25 MM 0.20 MM

IMVP6_COMP IMVP6_VW

0.25 MM 0.20 MM

0.25 MM

IMVP6_PVCC

0.20 MM

IMVP6_COMP_R

IMVP6_OCSET

0.25 MM 0.20 MM

IMVP6_VO

0.20 MM0.25 MM

IMVP6_DROOP

0.20 MM0.25 MM

IMVP6_DFB IMVP6_SOFT

0.20 MM0.25 MM

IMVP6_RBIAS

0.20 MM0.25 MM

0.25 MM 0.20 MM

IMVP6_FB

IMVP6_COMP_R

0.25 MM 0.20 MM

IMVP6_VDIFF_RC

0.25 MM 0.20 MM

IMVP6_FB_RC

0.25 MM 0.20 MM

CPU_VCCSENSE_N

SMC_CPU_ISENSE

CPU_VID<1>

CPU_DPRSTP_L

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=18.5V

PPVIN_S5_IMVP6_VIN

IMVP6_UGATE

GND_IMVP6_SGND

VOLTAGE=0 V

IMVP6_VDIFF

CPU_VID<5>

=PPVIN_S5_CPU_IMVP

CPU_VID<4>

CPU_VID<2>

PP3V3_S0_IMVP6_3V3

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

IMVP_VR_ON

VR_PWRGOOD_DELAY

IMVP6_VO_R

65

40

65

11

50

65

13

65

11

50

11

50

65

50

65

7

70

50

7

50

10

65

50

7

50

10

9

50

7

50

10

39

10

70

50

10

7

10

70

OUT

IN

OUT

OCSET

ICOMP

RBIAS

LGATE

THRM_PAD

FDE

IMON

PVCC

PHASE

UGATE

BOOT

VDD

VSS

VIN

VO

VSEN

VDIFF

FB

COMP

VW

SOFT

PGND

ISN

ISP

RTN

PGOOD

AF_EN

VR_ON

OFFSET1

OFFSET0

VID2

VID1

VID0

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CONNET OFFSET1 TO 3V3 FOR +25.0MV

CONNET OFFSET0 TO 3V3 FOR +12.5MV

OF MCP

MCPCORE AND GND BALL

CONNECT SENSE LINES TO CLOSEST

PLACE XW NEAR THE MCP,

000 +1.224V +1.355V +1.060V

Rev A01 Rev A01P Production

(Also A01Q)

110 +0.913V +0.977V +0.752V

VID<2:0> Voltage Voltage Voltage

NEED NEW TABLE?

111 +0.876V +0.917V +0.719V

101 +0.952V +0.994V +0.789V

100 +0.996V +1.065V +0.830V

011 +1.047V +1.124V +0.885V

010 +1.101V +1.216V +0.937V

001 +1.158V +1.243V +0.994V

(MCPCORES0_LGATE)

(MCPCORES0_UGATE)

F = 300 KHZ

Vout = See below MAX CURRENT: 20A

(MCPCORES0_VO)

(MCPCORES0_ICOMP)

(MCPCORES0_ISN)

MCP CORE POWER SUPPLY

(MCPCORES0_PHASE)

PLACE AT U7200.14

(=PPMCPCORE_S0_REG)

(MCPCORES0_ISP)

C7268

1

2

CASE-C2-SM

CRITICAL 330UF

POLY-TANT

20%

2.5V

C7262

1

2

CASE-B2-SM

10V

20%

POLY-TANT

47UF

CRITICAL

R7267

1

2

1K

MF 201

1% 1/20W

XW7260

1

2

SM

OMIT

C7266

1

2

X5R 603

4V

20%

10UF

OMIT

R7265

1 2

10KOHM-5%

0603-LF

CRITICAL

R7264

1

2

1%

201

11.3K

1/20W

MF

R7270

1

2

1/20W

10K

MF 201

1%

C7278

1

2

201

0.1UF

X5R

10%

6.3V

C7273

1

2

0.047UF

10% 402

16V X7R

C7277

1

2

6.3V X5R 201

10%

0.1UF

R7260

1 2

2.2

MF-LF

603

5%

1/10W

C7264

1 2

10V

5%

603

CERM-X7R

0.22UF

C7272

1

2

1UF

X5R 603-1

10% 25V

C7255

1

2

25V

10%

402

X5R

0.1UF

R7269

1

2

1/20W

1%

201

MF

4.99K

C7296

1

2

OMIT

1UF

X5R 402

10% 16V

R7274

1 2

603

MF-LF

5%

1/10W

0

R7273

1

2

201

10K

MF

1% 1/20W

R7275

1

2

10K

MF 201

1% 1/20W

XW7261

1 2

OMIT

SM

C7297

1

2

OMIT

1UF

X5R 402

10% 16V

R7261

1

2

1/20W

1%

201

MF

20

56

R7291

1 2

0

1/20W

5%

201

MF

C7265

1

2

CRITICAL 330UF

2.5V

20%

CASE-C2-SM

POLY-TANT

R7290

1 2

1/20W

5%

201

MF

0

R7263

1

2

100

MF 201

1% 1/20W

R7292

1 2

5%

201

0

MF

1/20W

C7270

1

2

1000PF

X7R 201

10% 16V

R7266

1 2

201

20

MF

1%

1/20W

R7268

1 2

1%

20

MF

201

1/20W

C7276

1

2

0.015UF

X7R 402

10% 16V

R7272

1

2

201

150K

MF

1/20W

1%

R7276

1

2

6.98K

MF 201

1% 1/20W

R7271

1

2

201

100

MF

1% 1/20W

C7279

1

2

1000PF

X7R 402

10% 25V

C7282

1 2

560PF

CERM

402

10% 50V

C7281

1 2

50V

5%

402

CERM

180PF

C7280

1 2

68PF

CERM

201

5%

25V

R7278

1 2

4.99K

MF

201

1%

1/20W

R7277

1 2

1/20W

1%

201

MF

374K

R7279

1 2

1/20W

1%

201

MF

2.21K

20

XW7263

1 2

OMIT

SM

XW7262

1 2

OMIT

SM

C7267

1

2

10UF

X5R 603

20%

4V

OMIT

C7269

1

2

10UF

X5R 603

20%

4V

OMIT

Q7260

5

4

1 2 3

LFPAK-HF

RJK0305DPB

CRITICAL

Q7265

5

4

1 2 3

RJK0328DPB

LFPAK-HF

CRITICAL

L7200

12

0.68UH-3.9MOHM

CRITICAL

IHLP4040CZ-SM

C7260

1

2

10V

20%

CASE-B2-SM

POLY-TANT

CRITICAL

47UF

C7299

1

2

X7R

16V

10%

1000PF

201

C7298

1

2

16V

10% 201

X7R

1000PF

44

XW7202

1

2

OMIT

SM

U7200

30

17

5

6

32

10

28

11

13

21

3

23 24

20

31 19

22

1

9

2

33

18

16

7

25 26 27

14

12

29

8

15

4

QFN

ISL6263D

CRITICAL

R7294

1

2

MF 201

1/20W

5%

0

R7293

1

2

0

5% 1/20W

201

MF

C7261

1

2

25V

10% X5R

1UF

603-1

MCP CORE REGULATOR

SYNC_DATE=06/24/2008

051-7631

7151

2.3.0

SYNC_MASTER=MINGJING

=PPVIN_S0_MCPCORES0

MCPCORES0_ISP

0.25 MM

0.2 MM

MCPCORES0_BOOT_R

MCPCORES0_UGATE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

MCPCORES0_OCSET

MCPCORES0_ISN_R

MCPCORES0_ICOMP

MCPCORES0_ISN

MCPCORES0_ISP_R

SWITCHNODE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

MCPCORES0_PHASE

MCPCORES0_RTN

=MCPCORES0_EN

MCPCORES0_RBIAS

MCPCORES0_FDE

MCPCORES0_VSEN

MCPCORES0_VW

GND_MCPCORES0_AGND

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

MCPCORES0_SOFT

5V_S3_MCPREG_VIN

VOLTAGE=5V

0.2 MM

0.6 mm

GND_MCPCORES0_AGND

=PP5V_S3_MCPREG

=PP3V3_S3_MCPREG

MCPCORES0_VDIF_C

MCPCORES0_COMP_C

MCP_VID<0>

MCP_VID<1>

MCP_VID<2>

GND_MCPCORES0_AGND

MCPCORES0_OFFSET1

MCPCORES0_PGOOD

MCPCORES0_COMP

MCPCORES0_FB MCPCORES0_VDIFF

0.2 MM

0.25 MM

MCPCORES0_BOOT

MCPCORE_IOUT

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_LGATE

MCP_VID0_R MCP_VID1_R MCP_VID2_R

MCPCORES0_OFFSET0

MCPCORES0_RSEN_H

=PPMCPCORE_S0_REG

MCPCORES0_RSEN_L

=PPMCPCORE_S0_REG

MCPCORES0_VO

=PPMCPCORE_S0_REG

51

7

51

7

51

7

NR

OUT

IN

EN

NC

THRML

GND

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MAX CURRENT = 200MA

1.8V S0 LDO

C7362

1

2

2.2UF

20% CERM

6.3V 402-LF

OMIT

C7361

1

2

X5R

10V 201

0.01UF

10%

U7360

4

3

6

5

2

1

7

CRITICAL

SON

TPS79918

C7360

1

2

10%

402

6.3V CERM

1UF

OMIT

SYNC_DATE=

051-7631

52 71

2.3.0

1.8V LDO Supply

SYNC_MASTER=

=PP1V8_S0_REG

=PPVIN_S0_P1V8S0

P1V8S0_NR

=P1V8S0_EN

7 7

56

BST

V5V

FB

TON

VLDO

FBL

EN/PSV

DL

ILIM

LX4

LX3

LX2

LX0

DH

VIN2

VIN1

PGOOD

ENL

LX5

LX1

VIN0

VIN3 VIN4VOUT

PGNDAGND

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MAX CURRENT = 12A

PWM FREQ = 400KHZ

NC

1V05 S5 POWER SUPPLY

NC

(1V05S5_VLDO)

supply for MCP1V05 AUX, FSB (CPU & MCP) VTT, 1V05 S0

5V LDO ENABLE EITHER FROM S5 CONTROL OR PBUS POWER

R7440

1

2

130K

MF

201

1%

1/20W

C7450

1

2

CRITICAL

10V

20%

CASE-B2-SM

POLY-TANT

47UF

C7451

1

2

25V

10% 603-1

X5R

1UF

C7492

1

2

OMIT

X5R 402

10% 10V

1UF

U7400

4

30

34

8

12

14

29

32

1

2

27

13 23 24 25 28 33

15161718192021

22

26

31

3

6 9 10 11 35

7

5

CRITICAL

SC417

MLPQ

XW7402

1 2

SM

R7420

1 2

1/20W

1%

201

MF

12.1K

C7420

12

0.22UF

CERM 402

10% 10V

C7400

1

2

CRITICAL

CASE-C2-SM

2.5V

20% POLY-TANT

330UF

R7411

1

2

11.5K

1/20W

1%

201

MF

C7401

1

2

603

20% X5R

10UF

OMIT

4V

R7410

1

2

12.1K

201

1/20W

1% MF

C7410

1

2

NO STUFF

50V

180PF

CERM 402

5%

XW7400

1 2

SM

XW7401

1 2

SM

R7412

1

2

1/20W

MF

201

10K

1%

C7411

1

2

0.01UF

X5R 201

10% 10V

C7412

1

2

10% X7R

16V

330PF

201

56

L7400

1 2

1.0UH-22A-10M-OHM

SM-IHLP

CRITICAL

C7402

1

2

10V

10% 201

X5R

0.01UF

R7431

1 2

1/20W

5%

201

MF

100K

NO STUFF

R7430

1 2

1/20W

5%

MF

0

201

R7490

1 2

63.4K

1/20W

1%

201

MF

R7491

1 2

11K

1/20W

1%

201

MF

R7421

1 2

MF-LF

402

1/16W

0

5%

R7432

1 2

5%

1K

1/20W

201

MF

C7430

1

2

20%

0.47UF

201

CERM-X5R

4V

1V05 S5 Power Supply

2.3.0

SYNC_DATE=05/21/2008

SYNC_MASTER=RXU_K20

051-7631

7153

1V05S5_FB

=PP1V05_S5_REG

1V05S5_VBST_R

PP1V05_S5_REG_XW

=PPVIN_S5_1V05

1V05S5_FB_C

1V05S5_LL_XW

=PPVIN_S5_1V05

GND_1V05S5_SGND

1V05S5_EN

1V05S5_FBL

1V05S5_TON

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=5V

1V05S5_VLDO

1V05S5_VBST

=P1V05_S5_EN

P1V05_S5_PGOOD

1V05S5_ENL

1V05S5_ILIM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

1V05S5_LL

53

7

VDDQSET

S3

COMP

VTT

THRM_PAD

DRVH

LL

PGND

CS_GND

CS

PGOOD

NC1

S5

NC0

GND

VTTGND

MODE

DRVL

VTTREF VLDOIN

VBST V5IN

VDDQSNS

VTTSNSV5FILT

SYM (1 OF 2)

S

D

G

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(1V5S3_VDDQSNS)

NC

PLACE C7543 NEAR NB

Routing Note:

CONNECT VTTSNS TO C7507 PIN1

MAX CURRENT = 11A

PWM FREQ. = 400 kHz

<Rb>

PP0V75_S0

PP1V5_S3

PM_SLP_S3_L

0.0V

LOW

HIGH LOW

LOW

HIGH HIGH

PM_S4_STATE_L

<Ra>

S5/G3Hot

Vout = 0.75V * (1 + Ra / Rb)

0.0V

1.5V

0.75V

1.5V/0.75V POWER SUPPLY

State S0 S3

(inductor limited)

PLACE XW7502 NEAR L7520

Placement Note:

PLACE XW7500, NEAR C7542 PIN 2

Placement Note:

Routing Note:

using Kelvin connection.

Connect CS_GND to Q7521 PIN1,2.3

put 6 vias under the thermal pad

Routing Note:

PLACE C7507,C7508 GND NEAR PIN 1

Placement Note:

using separate trace.

NC

(GND)

U7500

6

16

17

21

19

3

20

4

7 12

18

1310

11

25

141522

9

8

23

24

1

5

2

QFN

TPS51116

CRITICAL

L7520

1 2

CRITICAL

1.0UH-22A-10M-OHM

SM-IHLP

R7500

1 2

MF-LF 402

0

5% 1/16W

C7509

1

2

10% X5R

402

16V

0.1uF

C7530

1

2

47UF

20%

CRITICAL

10V POLY-TANT CASE-B2-SM

C7541

1

2

20%

603

X5R

6.3V

10UF

OMIT

C7502

1

2

OMIT

X5R 603

6.3V

20%

10UF

R7510

1

2

1/20W

1%

201

MF

9.76K

R7507

1 2

5% 1/16W MF-LF 402

4.7

R7521

1 2

20K

MF 201

1% 1/20W

R7522

1 2

1/20W

1%

201

MF

20K

C7503

1 2

25V

5%

201

CERM

100PF

NO STUFF

C7540

1 2

16V

10%

402

X5R

0.033UF

C7507

1

2

6.3V

20%

603

X5R-CERM

22UF

C7508

1

2

X5R-CERM

22UF

6.3V

20%

603

C7500

1 2

OMIT

10V

10%

402-1

X5R

1UF

C7543

1

2

2.5V

20% POLY-TANT

330UF

CRITICAL

CASE-C2-SM1

C7531

1

2

25V

10%

603-1

X5R

1UF

Q7520

5

4

1 2 3

CRITICAL

SI7110DN

PWRPK-1212-8-HF

Q7521

5

4

1 2 3

PWRPK-1212-8-HF

CRITICAL

SI7108DN

C7542

1

2

2.5V

20% CASE-C2-SM1

POLY-TANT

330UF

CRITICAL

C7532

1

2

10V

20% POLY-TANT

47UF

CRITICAL

CASE-B2-SM

C7511

1

2

402-LF

CERM

6.3V

2.2UF

20%

OMIT

XW7501

1 2

SM

XW7500

1 2

SM

XW7502

1 2

SM

R7599

1 2

1/20W MF 201

1%

100K

051-7631

SYNC_DATE=01/09/2007

SYNC_MASTER=M70

54 71

2.3.0

1.5V/0.75V Supplies

MIN_LINE_WIDTH=0.6 mm

1V5S3_LL

MIN_NECK_WIDTH=0.2 mm

1V5S3_DRVL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

1V5S3_VDDQSNS

=PP1V5_S3_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.8V

=PP0V75_S3_VTTREF

MEMVTT_VREF

1V5S3_CS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

GND_1V5S3_CSGND

=PP0V75_S0_REG

1V5S3_V5FILT

1V5S3_VDDQSET

=PP3V3_S3_DDRREG

1V5S3_VBST

=PPVIN_S5_1V5S30V75S0

DDRREG_PGOOD

=PP5V_S3_1V5S30V75S0

1V5S3_VBST_RC

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

1V5S3_DRVH

=DDRREG_EN

=DDRVTT_EN

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.3 mm

GND_1V5S3_SGND

57

7

56

7

56

24

OUT

VREG3

COMP1 COMP2

CSN1 CSN2

CSP1 CSP2

DRVH1 DRVH2

FUNC

GND

PGOOD1 PGOOD2

RF

SW1 SW2

THRM_PAD

TRIP

VFB1 VFB2

VIN

VREF2

VREG5

VBST1 VBST2

V5SW

DRVL1

SKIPSEL2

SKIPSEL1

DRVL2

EN1 EN2

EN

IN

D

S

G

D

S

G

D

S

G

D

S

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 5.0V

.

Vout = 3.3V

F=300KHZ

4A MAX OUTPUT

(Q7660 limit)

4A MAX OUTPUT

(Q7620 limit)

F=300KHZ

5V_S3 / 3V3_S5 POWER SUPPLY

One master PGOOD for both 5V and 3V3

C7600

1

2

1UF

10% 25V

603-1

X5R

L7620

1 2

CRITICAL

3.3UH

IHLP

C7681

1

2

1UF

X5R 603-1

10% 25V

C7664

1

2

0.1UF

10% 16V X5R 402

C7650

1

2

OMIT

10UF

X5R 603

20%

6.3V

C7624

1

2

402

X5R

16V

0.1UF

10%

C7690

1

2

OMIT

603

6.3V

20% X5R

10UF

C7641

1

2

1UF

X5R 603-1

10% 25V

L7660

1 2

IHLP

CRITICAL

3.3UH

C7603

1

2

1UF

CERM

402

10%

6.3V

OMIT

C7605

1

2

OMIT

10UF

X5R 603

20%

6.3V

R7606

1

2

1/20W

1%

332K

MF 201

56

XW7605

1

2

SM

C7601

1

2

0.22UF

CERM 402

10% 10V

R7660

1

2

1%

23.2K

1/20W MF 201

R7661

1

2

1%

10K

1/20W MF 201

R7620

1

2

201

MF

1/20W

40.2K

1%

R7621

1

2

201

MF

1/20W

10K

1%

U7600

10

15

8

17

7

18

1

24

30

27

12

4

21

11

28

5

20

3

6

19

32

25

33

14

2

31

26

9

16

23

13

22

29

TPS51220

CRITICAL

LLP

XW7601

1 2

SM

PLACEMENT_NOTE=Place XW7601 between U7600 pins 28 and 33.

R7616

1

2

4.87K

1% 1/20W MF 201

C7688

1 2

0.1UF

402

X5R

25V

10%

R7646

1 2

1%

1.24K

1/20W

MF

201

XW7606

1

2

PLACEMENT_NOTE=PLACE XW7605 AND XW7606 NEXT TO L7620 .

SM

C7618

1 2

0.1UF

402

X5R

16V

10%

R7647

1 2

MF

1.24K

1/20W

1%

201

R7656

1

2

1%

4.87K

1/20W

MF

201

XW7602

1

2

SM

XW7607

1

2

PLACEMENT_NOTE=PLACE XW7602 AND XW7607 NEXT TO L7660.

SM

R7636

1

2

1%

1/20W

MF

201

6.04K

XW7604

1

2

SM

PLACEMENT_NOTE=PLACE XW7604 NEXT TO L7620

XW7603

1

2

PLACEMENT_NOTE=PLACE XW7603 NEXT TO L7660

SM

56

Q7620

6

2

1

CRITICAL

PWRPK-1212-8

SI7904BDN

Q7620

5

4

3

CRITICAL

PWRPK-1212-8

SI7904BDN

C7652

1

2

CRITICAL

6.3V POLY-TANT CASE-B2-SM

150UF

20%

C7651

1

2

20%

150UF

CASE-B2-SM

POLY-TANT

6.3V

CRITICAL

C7640

1

2

20%

47UF

CASE-B2-SM

POLY-TANT

10V

CRITICAL

C7680

1

2

20%

47UF

CASE-B2-SM

POLY-TANT

10V

CRITICAL

C7691

1

2

CRITICAL

6.3V

POLY-TANT

CASE-B2-SM

150UF

20%

C7692

1

2

NO STUFF

CRITICAL

6.3V

POLY-TANT

CASE-B2-SM

150UF

20%

XW7608

1

2

PLACEMENT_NOTE=PLACE XW7608 NEXT TO C7691.

SM

R7637

1

2

1%

6.04K

201

MF

1/20W

R7699

1

2

5%

0

201

MF

1/20W

R7698

1

2

5%

201

MF

1/20W

0

Q7660

6

2

1

PWRPK-1212-8

CRITICAL

SI7904BDN

Q7660

5

4

3

PWRPK-1212-8

CRITICAL

SI7904BDN

SYNC_DATE=05/21/2008

051-7631

2.3.0

7155

SYNC_MASTER=RXU_K20

5V / 3.3V Power Supply

P5VS3_CSN1

P5VS3_VFB1

P5VS3_PGOOD1

P5VP3V3_VREG3

P5VP3V3_VREG5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

GND_P5VP3V3_SGND

SWITCH_NODE=TRUE

P3V3S5_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVH

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P3V3S5_VBST

P3V3S5_CSN2

P3V3S5_RF

P5V3V3_PGOOD

=P5VS3_EN

P5VS3_COMP1

=PPVIN_S5_3V3S5

P3V3S5_CSP2-R

P3V3S5_VFB2

P5VP3V3_VREF2 P5VP3V3_VREF2

P3V3S5_VFB2-R

=PP3V3_S5_REG

P5VP3V3_VREG3

=PP5V_S3_REG

P3V3S5_COMP2

P5VP3V3_V5SW

=PP5V_S3_REG

P5VS3_VFB1-R

P3V3S5_CSP2

P3V3S5_DRVL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

=P3V3S5_EN

P5VS3_PGOOD2

P5VS3_CSP1-R

P5VS3_CSP1

P5VP3V3_VREF2

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P5VS3_VBST

=PPVIN_S3_5VS3

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

P5VS3_DRVH

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

P5VS3_DRVL

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

P5VS3_LL

55

7

55 55

7

55

7

55

7

Y

B

A

OUT

SENSE

CT

VDD

GND

RESET*

MR*

ADJ1

SEL

ADJ2

REF

VCC

TMR

GND

THRM_PAD

RST*

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Power Control Signals

OTHER S0 RAILS PGOOD

S3 ENABLE

S5 ENABLE

S0 ENABLE

(PM_SLP_S3_L)

(PM_SLP_S3_L_BUF)

TRST = 200MS

NC

1.5V 1.05V COMPARED TO 0.5V

LTC2909 THRESHOLD IS 95% (3.136V)

Unused PGOOD signal

TPS3808 MR* HAS INTERNAL PULLUP

TIE TMR TO GND

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

C7758

12

10%

X5R

6.3V

0.1UF

201

C7784

1

2

NO STUFF

10%

6.3V

0.47UF

402

CERM-X5R

R7784

1

2

5%

201

MF

1/20W

0

U7759

2

1

3

5

4

TC7SZ08AFEAPE

SOT665

57

R7740

1

2

1/20W MF

100K

5%

201

U7740

4

2

3

15

6

CRITICAL

TPS3808G33DBVRG4

SOT23-6

C7740

1

2

10%

X5R

6.3V

0.1uF

201

C7741

1

2

201

10%

1000PF

X7R

16V

U7770

8 7

5

6

4

1

9

2

3

CRITICAL

LTC2909

DFN

C7770

1

2

10%

X5R

6.3V

0.1uF

201

55

53

C7701

1

2

201

CERM-X5R

0.47UF

4V

20%

R7702

12

1/20W

MF

5%

201

10K

C7702

1

2

10%

402

10V

NO STUFF

CERM

0.068UF

R7700

1

2

MF

1/20W

100K

5%

201

39

55

57

R7721

1 2

1/20W

5%

201

0

MF

51

R7720

1

2

10K

201

MF

1/20W

5%

55

R7722

1 2

5%

201

1/20W

MF

0

24 39

R7723

1 2

5%

201

1/20W

MF

0

C7712

1 2

NO STUFF

6.3V

0.47UF

402

10%

CERM-X5R

R7712

1 2

1K

5%

1/20W

MF

201

R7713

1 2

201

MF

1/20W

5%

1K

C7713

1 2

6.3V

0.47UF

402

10%

CERM-X5R

R7711

1 2

201

5%

1/20W

MF

5.1K

R7701

12

5.1K

1/20W

MF

5%

201

R7781

1 2

4.7K

5%

MF

1/20W

201

C7781

1

2

10%

6.3V

0.47UF

402

CERM-X5R

37

61

R7785

1

2

5%

22K

MF

1/20W

201

C7785

1

2

10%

402

6.3V

0.47UF

CERM-X5R

C7714

1 2

10%

CERM-X5R

0.47UF

6.3V

402

R7714

1 2

5.1K

MF

1/20W

5%

201

57

20 34 39 40

C7711

1 2

0.47UF

6.3V

CERM-X5R

402

10%

54

43

R7710

1

2

100K

1/20W

MF

5%

201

52

R7783

1

2

5%

201

MF

5.1K

1/20W

R7782

1

2

1/20W

MF

5%

0

201

R7780

1

2

201

1/20W

22K

MF

5%

C7783

1

2

6.3V

10%

402

CERM-X5R

0.47UF

C7782

1

2

10%

402

CERM-X5R

0.47UF

NO STUFF

6.3V

C7780

1

2

10%

402

6.3V

0.47UF

CERM-X5R

6

20 34 35 39

R7779

1

2

201

5%

100K

MF

1/20W

51

57

SYNC_DATE=02/04/2008

56

2.3.0

71

051-7631

SYNC_MASTER=YUAN.MA

POWER SEQUENCING

MAKE_BASE=TRUE

PM_SLP_S4_L

USBPWR_EN

MAKE_BASE=TRUE

=USBPWR_EN

=PP3V3_S5_PWRCTL

P5V3V3_PGOOD

MCPCORES0_PGOOD

=PP3V3_S0_PWRCTL

=PP3V3_S0_VMON

P1V05_S5_PGOOD

RSMRST_PWRGD

DDRREG_PGOOD

=P3V3S5_EN

CT

=PP1V5_S0_VMON

=PP1V05_S0_VMON

SMC_PM_G2_EN

=P1V05_S5_EN

PM_G2_P1V05S5_EN

MAKE_BASE=TRUE

P3V3S5_EN

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

S0PGOOD_PWROK

MAKE_BASE=TRUE

ALL_SYS_PWRGD

P5VS3_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

=P5VS3_EN

=P3V3S3_EN

=DDRREG_EN

P3V3S0_EN

MAKE_BASE=TRUE

PM_SLP_S3_L

=P5VS0_EN

=PBUSVSENS_EN

=P3V3S0_EN

=P1V8S0_EN

=MCPDDR_EN

=MCPCORES0_EN

=DPPWR_EN

P1V8S0_EN

MAKE_BASE=TRUE

P1V05S0_EN

MCPCORES0_EN

MAKE_BASE=TRUE

DPPWR_EN

MAKE_BASE=TRUE

MCPDDR_EN

MAKE_BASE=TRUE

PM_SLP_S3_L_BUF

=PP3V3_S5_PWRCTL

56

24

56

7

53

39

54

7

D

G S

IN

G

DS

D

SG

IN

D

S

G

D

SG

D

SG

IN

S

D

G

IN

D

SG

D

SG

IN

D

SG

D

SG

IN

D

G S

D

G S

SGD

D

SG

D

SG

IN

S

D

G

SGD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MOSFET

CHANNEL

RDS(ON)

LOADING

2.046 A (EDP)

5V S0 FET

3.3V S0 FET

1.05V S0 FET

LOADING

5.027A (EDP)

6 MOHM @3.5V VGSRDS(ON)

0.315 A (EDP)

3.3V S3 FET

48 mOhm @4.5V

8.25A (EDP)

RDS(ON)

MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY. MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

MCP79 DDRVTT FET

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE

3.3V RMGT FET

@ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C)

CHANNEL

LOW THROUGH VTT TERMINATION RESISTORS.

90mA max load @ 0.9V

.

FDC638P

P-TYPE

3.3V S3 FET

MOSFET

LOADING

RDS(ON)

5V S0 FET

P-TYPE

FDC606P

26 MOHM @4.5V

P-TYPE

MOSFET

CHANNEL

N-TYPE

1.05V S0 FET

LOADING

RDS(ON)

CHANNEL

MOSFET

81mW max power

CKT FROM T18

SI7108DNS

1.5V S0 FET

N-TYPE

MOSFET

CHANNEL

LOADING

(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)

1.5V S0 FET

1.05V RMGT FET

@ 1.8V Vgs: Rds(on) = 47mOhm max I(max) = 3.1A (70C)

0.562 A (EDP)

26 MOHM @4.5V

SI7108DN

6.1 MOHM @4.5V VGS

3.3V S0 FET

Q7810

1

2

5

6

3

4

SM

FDC638P_G

CRITICAL

R7840

1 2

201

33K

1/20W

5%

MF

R7842

1

2

100K

5%

1/20W

MF

201

Q7845

3

1

2

SSM3K15FV

SOD-VESM-HF

56

Q7820

3

1

2

SOT-23-HF

CRITICAL

NTR4101P

C7820

12

CERM

16V

0.01UF

402

10%

C7821

1

2

0.033UF

10% X5R

402

16V

R7821

1 2

5%

100K

MF

1/20W

201

R7820

1

2

5%

10K

MF

1/20W

201

Q7821

3

5

4

SOT563

SSM6N15FEAPE

20 57

C7860

1

2

402

CERM

0.1UF

10V

20%

C7861

1

2

0.068UF

10% 10V CERM 402

Q7860

3

1

2

SI2312BDS

CRITICAL

SOT23

Q7861

6

2

1

SSM6N15FEAPE

SOT563

R7860

1 2

1%

1/20W

MF

201

10K

R7861

1 2

15K

1%

MF

1/20W

201

R7864

1

2

1%

MF

1/20W

201

69.8K

Q7861

3

5

4

SOT563

SSM6N15FEAPE

20 57

Q7853

5

4

1 2 3

PWRPK-1212-8-HF

CRITICAL

SI7108DN

C7811

1

2

201

33000PF

6.3V X5R

10%

R7810

1 2

MF

47K

5%

1/20W

201

R7812

1

2

5%

MF

1/20W

201

10K

C7830

1 2

0.01UF

10V

201

10%

X5R

C7831

1

2

201

6.3V X5R

10%

33000PF

R7830

1 2

47K

MF

201

5%

1/20W

R7832

1

2

100K

201

MF

1/20W

5%

56

C7803

1

2

0.068UF

CERM

10V

402

10%

C7802

1

2

0.1UF

6.3V

201

X5R

10%

Q7871

6

2

1

SSM6N15FEAPE

SOT563

R7871

1 2

201

MF

1/20W

5%

47K

R7801

1 2

5%

10K

201

MF

1/20W

R7803

1

2

201

1/20W

MF

100K

5%

Q7871

3

5

4

SOT563

SSM6N15FEAPE

56

Q7875

6

2

1

SSM6N15FEAPE

SOT563

C7876

1

2

10%

X7R

16V

NO STUFF

201

1000PF

R7875

12

MF-LF

603

10

5%

1/10W

R7876

1

2

5%

1/20W

201

MF

100K

Q7875

3

5

4

SOT563

SSM6N15FEAPE

24 54

Q7803

3

1

2

SSM3K15FV

SOD-VESM-HF

Q7805

3

1

2

SSM3K15FV

SOD-VESM-HF

Q7830

1 2 5 6

3

4

FDC606P_G

SOT-6

CRITICAL

R7853

1

2

5%

201

1/20W

MF

10K

R7852

1 2

1/20W

220K

5%

MF

201

C7852

12

6.3V

NO STUFF

0.1UF

201

X5R

10%

Q7851

3

5

4

SSM6N15FEAPE

SOT563

C7853

1

2

10%

402

10V CERM

0.068UF

Q7851

6

2

1

SOT563

SSM6N15FEAPE

R7851

1 2

MF

1/20W

201

5%

100K

C7810

1 2

0.01UF

201

10V X5R

10%

56

R7854

1 2

NO STUFF

510

5%

1/20W

201

MF

Q7801

5

4

1 2 3

CRITICAL

SI7108DN

PWRPK-1212-8-HF

Q7840

1 2 5 6

3

4

CRITICAL

SOT-6

FDC606P_G

C7840

1 2

0.01UF

10%

X5R

10V

201

C7841

1

2

X5R

6.3V

10%

33000PF

201

POWER FETS

SYNC_DATE=02/04/2008

051-7631

57 71

2.3.0

SYNC_MASTER=YUAN.MA

P5VS0_SS

=PP5V_S0_FET

P3V3S3_SS

=P3V3S0_EN

P3V3S0_SS

=PP3V3_S5_P3V3S0FET

=PP3V3_S0_FET

P3V3S0_EN_L

P1V05S0_EN

P1V05_EN_L

P1V05_EN_L_RC

=PP5V_S3_P1V05S0FET

P1V05S0_RC

=PP1V05_S0_FET

=PP3V3_S5_P1V05FET

P1V05S0_SS

=PP1V05_S5_P1V05S0FET

=PP3V3_S5_P3V3RMGTFET

=PP3V3_S5_P1V05RMGTFET

P1V05RMGT_EN_L

=PP1V05_RMGT_FET

P1V05RMGT_SS

P3V3RMGT_SS

PM_SLP_RMGT_L

P3V3RMGT_EN_L

=MCPDDR_EN

MCPDDR_EN_L

=PP5V_S3_MCPDDRFET

MCPDDR_EN_L_RC

MCPDDR_SS

=PP1V5_S0_FET

=PP1V5_S3_P1V5S0FET

=PP3V3_S5_P3V3S3FET

=P5VS0_EN

P5VS0_EN_L

=P3V3S3_EN

P3V3S3_EN_L

VTTCLAMP_EN

VTTCLAMP_L

=PP5V_S3_VTTCLAMP

=DDRVTT_EN

=PPVTT_S0_VTTCLAMP

=PP3V3_RMGT_FET

PM_SLP_RMGT_L

P1V05RMGT_EN_L_RC

=PP1V05_RMGT_P1V05RMGTFET

=PP5V_S3_P5VS0FET

=PP3V3_S3_FET

7

G

S

D

G

S

D

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF ACIN

SDA

VHST SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

D

G

S

D

G

S

GND

VCC

D

SG

D

SG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ACOK pullup/down on SMC page

PLACE RC CLOSE TO SMC

(AC adapter limited?)

MAX CURRENT = 5.35A??

PWM FREQ. = 400 kHz

TO CURRENT SENSOR U5480

KELVIN CONNECTION

TO SYSTEM

NC

(CHGR_CSON)

(CHGR_CSOP) (CHGR_CSOP)

PBUS SUPPLY / BATTERY CHARGER

TO BATTERY

AMON PULLDOWN LOGIC

BATTERY CHARGING

(CHGR_ACIN)

pullups offpage

F7900

1 2

1206

CRITICAL

7AMP-24V

R7920

1

2

0612

1W

0.02

CRITICAL

0.5% MF

C7971

1

2

10%

402

CERM

0.68UF

6.3V

R7940

1 2

402

4.7

1/16W

5% MF-LF

R7921

1 2

10

201

MF

1/20W

5%

C7925

1

2

10% 402

0.1UF

25V X5R

R7930

1 2

CRITICAL

1W

0612

MF

0.5%

0.01

C7930

1

2

CASE-B2-SM

10V POLY-TANT

47UF

20%

CRITICAL

C7935

1

2

603-1

10%

1UF

X5R

25V

C7941

1 2

OMIT

10%

1UF

X5R

10V 402-1

C7923

1

2

1UF

603-1

25V X5R

10%

C7922

1

2

603-1

10%

1UF

X5R

25V

C7920

1

2

CASE-D2-SM

CRITICAL

POLY-TANT

25V

20%

22UF

C7921

1

2

CRITICAL

22UF

20%

CASE-D2-SM

POLY-TANT

25V

C7931

1

2

10V CASE-B2-SM

POLY-TANT

47UF

20%

CRITICAL

C7940

1

2

OMIT

10%

1UF

X5R

10V 402-1

C7947

1

2

OMIT

6.3V

10%

1UF

X5R

402-1

R7911

1

2

1%

201

9.76K

MF

1/20W

R7910

1

2

1% MF

1/20W

201

30.1K

C7910

1

2

10% 402

X5R

0.1UF

25V

D7910

1

2

B0530WS-X-G

CRITICAL

SOD-323

C7943

1 2

10%

402

X5R

16V

0.1UF

C7944

1

2

10% X5R

10V

0.01UF

201

R7945

1

2

56.2K

MF-LF

1%

1/16W

402

C7945

1

2

10%

402

CERM

50V

0.001UF

R7946

1

2

402

MF-LF

3.01K

1%

1/16W

C7946

1

2

10%

402

50V

CERM

470PF

C7942

1

2

10% X5R

201

6.3V

33000PF

XW7900

1 2

SM

R7980

1 2

1206

MF-LF

0.002

CRITICAL

1%

1/4W

R7931

1

2

201

MF

1/20W

5%

10

R7923

12

1/20W

10

MF

201

5%

R7971

1 2

0

5%

MF-LF

1/16W

402

Q7920

FDMC8296

POWER33

CRITICAL

Q7921

CRITICAL

POWER33

FDMC8296

XW7930

1

2

SM

XW7931

1

2

SM

XW7920

1 2

SM

C7924

1

2

10%

402

CERM

16V

0.047UF

XW7921

1 2

SM

C7926

1

2

1000PF

10% 16V X7R 201

R7947

1

2

1/20W

MF

201

5%

10

R7970

1 2

0

5%

1/16W MF-LF

402

C7972

1

2

402

6.3V CERM

10%

0.68UF

Q7950

CRITICAL

SO-8

FDS6681Z

U7900

3

14

1

6

26

9

16

15

25

27

28

17

18

2

5

21

22

23

11 10

29

13

24

7

19

20

12

8

4

CRITICAL

OMIT

QFN

ISL6258

R7900

1

2

201

MF

1/20W

5%

100K

Q7900

5

4

1 2 3

LFPAK-SM

CRITICAL

HAT1127H

Q7901

5

4

1 2 3

LFPAK-SM

HAT1127H

CRITICAL

U7960

1

3

4

5

2

CRITICAL

TL331

SOT23-5

R7960

1

2

201

MF

1/20W

1%

57.6K

R7961

1

2

1.82K

1%

201

MF

1/20W

C7900

1

2

10%

402

X5R

25V

0.1UF

R7962

1

2

201

MF

1/20W

5%

62K

C7960

1

2

10%

402

X5R

0.1UF

25V

R7999

12

100K

5%

1/20W

MF

201

C7996

1

2

10%

402

X5R

25V

0.1UF

C7995

1

2

10%

402

X5R

25V

0.1UF

R7901

12

201

5% MF

1/20W

62K

Q7970

3

5

4

SSM6N15FEAPE

SOT563

R7974

1

2

1M

5%

1/20W

MF

201

Q7970

6

2

1

SSM6N15FEAPE

SOT563

R7973

1

2

1/20W

MF

201

5%

100K

R7975

1

2

1M

5% 1/20W MF 201

NO STUFF

L7900

12

IHLP4040CZ-SM

4.7UH-7.5A

CRITICAL

C7950

1

2

10% X5R

10V 201

0.01UF

C7951

1

2

10% 402

X5R

16V

0.1UF

2.3.0

051-7631

SYNC_DATE=01/09/2007

SYNC_MASTER=M70

PBUS Supply/Battery Charger

58 71

CHGR_SCL

CHGR_ACIN

CHGR_ICOMP

CHGR_VCOMP_R

CHGR_VCOMP

CHGR_SDA

CHGR_VNEG CHGR_CSOP CHGR_CSON

PPVBAT_G3H_CHGR_OUT

CHGR_BGATE

CHGR_CSIN

CHGR_CSIP

=PP18V5_G3H_CHGR

CHGR_AMON

=PP3V42_G3H_CHGR

CHGR_VDD_L

CHGR_AMON

=PP3V42_G3H_CHGR

CHGR_LOWCURRENT_REF

CHGR_AGATE

CHGR_SCL

CHGR_VNEG_R

CHGR_DCIN

=SMBUS_CHGR_SCL

CHGR_DCIN

CHGR_AMON

CHGR_ACOK

CHGR_VDD

=PP3V42_G3H_CHGR

CHGR_ACOK

GND_SMC_AVSS

SMC_BATT_ISENSE

SMC_DCIN_ISENSE

GND_SMC_AVSS

CHGR_BMON

CHGR_AMON

GND_CHGR_SGND

CHGR_SDA

CHGR_VDD

CHGR_VDD_R

CHGR_BGATE

CHGR_BOOT CHGR_UGATE

CHGR_VDDP

CHGR_LOWCURRENT_GATE

CHGR_LGATE

GND_CHGR_SGND

CHGR_BMON

=SMBUS_CHGR_SDA

=PPBUSA_G3H

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP18V5_S5_CHGR_SW_R

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM

GND_CHGR_SGND

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.2MM

PPVBAT_G3H_CHRGR_REG_0

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

BATT_POS_F

PPVBAT_G3H_CHRGR_REG_R

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

CHGR_SGATE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVBAT_G3H_CHGR_OUT

PPVDCIN_G3H_PRE_0

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

PPVDCIN_G3H_PRE_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVDCIN_G3H_PRE

MIN_NECK_WIDTH=0.2 MM

PPVDCIN_G3H_PRE2

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

CHGR_PHASE

SMC_BC_ACOK

MAKE_BASE=TRUE

=PPBUSB_G3H

58

44

43

49

70

49

58

40

44

70

40

44

58

7

58

7

58

42

58

7

58

39

58

42

7

70

58

70

49

70

58

70

43

70

39

7

BI

D

G S

SYM_VER-1

BI

SYM_VER-2

BI

SYM_VER-2

BI BI

BI

BI BI

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE FILTERS AND CAPS NEAR PINS ON CONNECTOR

MIC CONNECTOR

NC

(LVDS DDC POWER)

LCD + CAMERA CONNECTOR

CAMERA I/F

LCD I/F

518S0433

APN:518S0536

C9012

1

2

OMIT

10UF

20%

6.3V 603

X5R

C9011

1

2

0.1UF

10%

6.3V X5R 201

8

R9002

1

2

1/20W

5%

201

MF

100K

Q9003

1

2

5

6

3

4

SM

FDC638P_G

CRITICAL

Q9004

3

1

2

SOD-VESM-HF

SSM3K15FV

J9000

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

31 32 33 34 35 36 37

38

39

4 5 6 7 8 9

20347-130E-11

F-RT-SM

CRITICAL

L9005

1 2

CRITICAL

0402-LF

FERR-120-OHM-1.5A

L9007

1

2 3

4

90-OHM-100MA

1210-4SM1

CRITICAL

R9009

1

2

10K

MF 201

5% 1/20W

R9008

1

2

10K

MF

1/20W

5%

201

L9008

1 2

120-OHM-0.3A-EMI

0402-LF

R9023

1

2

1/20W

5%

201

MF

10K

C9016

1

2

10%

1000PF

X7R

201

16V

C9015

1

2

1000PF

X7R

10% 201

16V

C9010

1

2

10% 201

16V

X7R

1000PF

6

17

6

17

L9012

1

2 3

4

90-OHM-100MA

1210-4SM1

CRITICAL

L9006

1

2 3

4

90-OHM-100MA

1210-4SM1

CRITICAL

17 67

L9011

1

2 3

4

1210-4SM1

CRITICAL

90-OHM-100MA

L9010

1

2 3

4

CRITICAL

90-OHM-100MA

1210-4SM1

6

17 67

6

17 67

6

17 67

6

17 67

6

17 67

6

17 67

C9050

1

2

16V

CERM

402

10%

0.01UF

J9050

7

8

1 2 3 4 5 6

GS03067-11131-7F

CRITICAL

F-RT-SM

C9030

1

2

10PF

NPO

5%

25V

201

NO STUFF

C9031

1

2

10PF

NPO

5% 25V

201

NO STUFF

L9052

1 2

240-OHM-0.2A-0.8-OHM

0201

L9051

1 2

240-OHM-0.2A-0.8-OHM

0201

C9051

1

2

10PF

NPO

5%

25V

201

C9052

1

2

201

25V NPO

10PF

5%

17

C9040

1

2

10% X5R

6.3V 201

0.1UF

R9014

1

2

1/20W 201

MF

100K

5%

L9050

1 2

600-OHM-300MA

0402

CRITICAL

L9030

1 2

CRITICAL

0402

600-OHM-300MA

L9031

1 2

0402

600-OHM-300MA

CRITICAL

L9053

1 2

CRITICAL

600-OHM-300MA

0402

C9053

1

2

0.01UF

10%

402

CERM

16V

L9004

1 2

0402-LF

CRITICAL

FERR-120-OHM-1.5A

C9013

1 2

10% X5R

10V

3300PF

201

SYNC_DATE=06/23/2006

LVDS,Camera Conn. and ALS Conn.

2.3.0

7159

SYNC_MASTER=GPU

051-7631

AUD_MIC_DATA_F

LCDBKLT_RTN<3>

LVDS_IG_A_DATA_F_P<2>

AUD_MIC_CLK_F

GND_MIC_F

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.20MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM

PP3V3_S0_MIC_F

AUD_MIC_CLK

AUD_MIC_DATA

=PP3V3_S0_MIC

=PP3V3_S5_LCD

LVDS_IG_DDC_CLK

LVDS_IG_A_DATA_F_N<0>

LVDS_IG_A_DATA_F_N<2>

LVDS_IG_A_CLK_F_N

PPVOUT_S0_LCDBKLT

LVDS_IG_A_DATA_F_P<0>

LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1>

LVDS_IG_A_CLK_F_P

LCDBKLT_RTN<4>

LVDS_IG_A_DATA_F_N<1> LVDS_IG_A_DATA_F_P<1>

LCDBKLT_RTN<1>

LCDBKLT_RTN<5>

MIN_LINE_WIDTH=0.3MM

PP3V3_LCDVDD_SW_F

MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

LCDBKLT_RTN<2>

=I2C_ALS_SCL

USB2_CAMERA_F_P

LVDS_IG_A_DATA_N<2>

=USB2_CAMERA_N

=USB2_CAMERA_P

=PP5V_S3_CAMERA

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<0>

LCDVDD_PWREN_L

LCDVDD_PWREN_L_R

LVDS_IG_PANEL_PWR

=PP3V3_S0_LCD

PP5V_S3_CAMERA_F

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

USB2_CAMERA_F_N

=I2C_ALS_SDA

I2C_ALS_SDA_F

I2C_ALS_SCL_F

LVDS_IG_A_DATA_P<0>

LCDBKLT_RTN<6>

VOLTAGE=3.3V

PP3V3_S0_LCD_F

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

LVDS_IG_DDC_DATA

PP3V3_LCDVDD_SW

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

70

62

35

67

62

67

62

70

62

42

70

42

62

70

6

67

6

7

67

6

67

6

67

6

7

6

70

D

SG

D

GS

BI

D

S G

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Q9300

6

2

1

SSM6N15FEAPE

SOT563

R9301

1 2

201

1/20W

MF

33

5%

R9300

1 2

1/20W

33

5% MF

201

C9300

1 2

201

6.3V X5R

10%

0.1UF

Q9301

3

1

2

SSM3K15FV

SOD-VESM-HF

60

17 67

6

35 61 67

6

35 61 67

Q9300

3

5

4

SOT563

SSM6N15FEAPE

61

17

C9301

1 2

201

6.3V

0.1UF

10% X5R

R9302

1

2

5% MF

1/20W 201

100K

R9306

1

2

MF

1/20W 201

1K

5%

SYNC_MASTER=NMARTIN

SYNC_DATE=12/18/2007

DISPLAYPORT SUPPORT

7160

2.3.0

051-7631

DP_AUX_CH_C_N

=MCP_HDMI_TXC_P

MAKE_BASE=TRUE

DP_ML_P<3>

DP_IG_AUX_CH_P

DP_CA_DET

DDC_CA_DET_LS5V_L

DP_IG_DDC_DATA

MAKE_BASE=TRUE

DP_IG_DDC_CLK

MAKE_BASE=TRUE

=MCP_HDMI_DDC_DATA

MAKE_BASE=TRUE

DP_ML_N<1>

MAKE_BASE=TRUE

DP_ML_P<0>

=MCP_HDMI_TXC_N

MAKE_BASE=TRUE

DP_ML_N<3>

=MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2>

MAKE_BASE=TRUE

DP_ML_N<0>

MAKE_BASE=TRUE

DP_ML_P<1>

MAKE_BASE=TRUE

DP_ML_N<2>

MAKE_BASE=TRUE

DP_ML_P<2>

=MCP_HDMI_HPD

DP_HPD

MAKE_BASE=TRUE

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXD_P<0>

DP_AUX_CH_SW_N

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_IG_CA_DET

DP_AUX_CH_SW_P

DP_IG_AUX_CH_N

=PP5V_S0_DP_AUX_MUX

DP_AUX_CH_C_P

67

17 61

60

17

61

17 61

17

17 61

61

17 61

17

67

7

BI

IN

IO NC NC

IO

GND

OUT

IO NC NC

IO

GND

IO NC NC

IO

GND

IO NC NC

IO

GND

IN

G

D

S

SYM_VER-2

G

D

S

G

D

S

G

D

S

OUT

IN

OUT

EN

OC*

GND

THRML

PAD

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

These nets connect to RIO connector @ J4200

pullup to DP_PWR.

(CA) has 100k

Cable Adapter

DP to DVI/HDMI

DP Source must pull

Q9440 must have Drain to Gate leakage of <500nA

and Gate to Source resistance of >5MOhm

MCP requires pull

down HPD input with greater than or equal to 100K (DPv1.1a).

down HPD input with

(DP_HPD_Q)

(DP_CA_DET_Q)

100K if DP_HPD is used.

NC

6

35 60 67

60 67

R9421

1

2

201

MF

5%

100K

1/20W

D9410

3

2 1

9

10

DP_ESD

CRITICAL

SLP2510P8

RCLAMP0524P

C9415

1 2

X5R10%

0.1uF

201

6.3V

C9414

1 2

201

6.3V

0.1uF

X5R10%

60

C9411

1 2

6.3V

X5R 201

0.1uF

10%

C9410

1 2

10% 201X5R

0.1uF

6.3V

R9420

1

2

1/20W

5%

100K

201

MF

D9411

3

5 4

6 7

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

D9400

1

3

4

6

2 5

CRITICAL

RCLAMP0504F

DP_ESD

SC70-6-1

D9411

3

2 1

9

10

DP_ESD

SLP2510P8

CRITICAL

RCLAMP0524P

R9425

1

2

1/20W MF 201

1M

5%

D9410

3

5 4

6 7

DP_ESD

RCLAMP0524P

SLP2510P8

CRITICAL

C9417

1 2

10% X5R

0.1uF

201

6.3V

C9416

1 2

0.1uF

10% X5R 201

6.3V

C9413

1 2

0.1uF

10% X5R

6.3V

201

C9412

1 2

6.3V

0.1uF

10% 201X5R

60 67

C9400

1

2

201

X5R

10V

10%

0.01UF

L9400

FERR-120-OHM-3A

0603

R9440

1

2

201

1/20W

MF

100K

5%

Q9440

3

5

4

SOT-363

2N7002DW-X-G

R9441

1

2

1/20W

100K

201

MF

5%

R9423

1

2

201

MF

1/20W

1%

100K

FL9400

1

2 3

4

TCM1210-4SM

12-OHM-100MA

FL9420

1

2 3

4

TCM1210-4SM

12-OHM-100MA

FL9410

1

2 3

4

12-OHM-100MA

TCM1210-4SM

FL9430

1

2 3

4

12-OHM-100MA

TCM1210-4SM

R9444

1

2

MF

201

1/20W

5%

10K

Q9440

6

2

1

SOT-363

2N7002DW-X-G

R9445

1

2

MF

1/20W

201

5%

10K

Q9441

6

2

1

2N7002DW-X-G

SOT-363

Q9441

3

5

4

2N7002DW-X-G

SOT-363

60

R9446

1

2

100K

1%

1/20W

MF

201

C9450

1

2

603

20%

X5R-CERM

6.3V

22UF

NO STUFF

U9450

4

1

2

3

5

8

7

6

9

CRITICAL

MSOP

TPS2051

C9451

1

2

6.3V

0.1UF

10%

X5R 201

56

R9422

1

2

5%

1M

201

MF

1/20W

6

35 60 67

DisplayPort Connector

SYNC_MASTER=M98_MLB

SYNC_DATE=01/17/2008

051-7631

2.3.0

7161

DP_HPD_DET_L

=PP3V3_S0_DPCONN

DP_HPD

DP_CA_DET_Q

=DPPWR_EN

=PP3V3_S0_DPCONN

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3_S0_DPFUSE

DP_ML_C_N<0>

DP_ML_C_P<0>

DP_AUX_CH_C_P

DP_ML_F_N<0>

DP_ML_F_P<0>

DP_ML_F_N<2>

DP_ML_F_P<2>

DP_HPD_Q

DP_ML_F_N<1>

DP_AUX_CH_C_N

DP_ML_N<3>

DP_ML_P<3>

DP_ML_N<1>

DP_ML_N<0>

DP_ML_P<0>

DP_ML_C_N<2>

DP_ML_N<2>

DP_ML_C_P<2>

DP_ML_P<1>

DP_ML_C_N<3>

DP_ML_C_P<1>

DP_ML_C_P<3>

DP_ML_C_N<1>

DP_ML_P<2>

DP_ML_F_P<1>

HDMI_CEC

DP_CA_DET

DP_CA_DET_L

=PP3V3_S0_DPCONN

DP_ML_F_P<3> DP_ML_F_N<3>

MIN_LINE_WIDTH=0.38 MM

PP3V3_S0_DPPWR

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

70

61

35

61

67

35

67

35

61

67

35

7

6

7

70

6

35

6

35

6

35

6

7

35

6

VIN

OVP

ISEN6

ISEN5

ISEN4

ISEN3

ISEN2

ISEN1

SW

SSTCMP

ISET

NC4

NC3

NC2

NC1

GNDA

VREF

RT

PWM

PAD

ENA

THRML

IN

Y

B

A

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

>2V = ON, <1V = OFF

ILED[A] = 1500/R9766

OVP Threshold: 37.9V

Place R9771-R9776,C9771-C9776 close to J9000

NC

NC NC

LED Backlight Driver

f=500KHz

100Hz - 20KHz

FOP[Mhz] = 50000/R9764

C9758

1

2

50V X7R-CERM 1206

10%

4.7UF

D9750

1 2

CRITICAL

SM

PD3S140XF

C9755

1

2

50V X7R-CERM

10%

4.7UF

1206

R9755

1

2

1% MF

1M

1/20W

201

R9756

1

2

78.7K

1% MF

1/20W

201

L9750

IHLP2020CZ11-SM

22UH-1.7A

CRITICAL

C9750

1

2

10UF

25V

10%

1206-1

X5R

U9750

1

13

10

11

12

14

15

16

8

2

7 17 19

6

20

5

9

18

21

4

3

OZ9956ALN

QFN

CRITICAL

C9763

1

2

10%

402

50V

CERM

0.001UF

C9760

1

2

OMIT

402-1

10V

10%

1UF

X5R

C9762

1

2

402

CERM

0.01UF

16V

20%

C9757

1

2

4.7UF

50V X7R-CERM

10%

1206

C9740

1

2

0.1UF

X5R

10%

6.3V 201

R9762

1

2

201

MF

10K

1% 1/20W

R9766

1

2

75K

201

MF

1/20W

1%

R9764

1

2

100K

1% 1/20W

201

MF

XW9750

1 2

SM

17 63

24

63

C9756

1

2

50V

10%

1206

4.7UF

X7R-CERM

C9751

1

2

X5R

25V

10%

1UF

603-1

R9772

1 2

1

5%

1/20W

MF

201

R9773

1 2

1

5%

1/20W

MF

201

R9774

1 2

1

5%

1/20W

MF

201

R9775

1 2

1

MF

201

5%

1/20W

R9776

1 2

201

MF

1/20W

5%

1

U9740

2

1

3

5

4

TC7SZ08AFEAPE

SOT665

C9771

1

2

10% 16V

1000PF

201

X7R

C9772

1

2

10% 16V

1000PF

201

X7R

C9774

1

2

1000PF

X7R 201

16V

10%

R9771

1 2

201

1

5%

1/20W

MF

C9773

1

2

16V

1000PF

X7R 201

10%

C9776

1

2

X7R 201

1000PF

16V

10%

C9775

1

2

10% X7R

201

1000PF

16V

R9740

1

2

NO STUFF

5%

100K

201

MF

1/20W

R9741

1 2

10K

1/20W

MF

5%

201

C9741

1

2

X5R

16V

10%

402

0.1UF

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

62 71

2.3.0

051-7631

LED Backlight Driver

LCDBKLT_ENA_RC

LCDBKLT_SSTCMP

LCDBKLT_ENA

BKLT_PLT_RST_L

LVDS_IG_BKL_ON

=PP3V3_S0_LCDBKLT

MIN_NECK_WIDTH=0.2 mm

LCDBKLT_RTN_RC<4>

MIN_LINE_WIDTH=0.25 mm

LCDBKLT_OVP

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

LCDBKLT_RTN_RC<3>

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

LCDBKLT_RTN_RC<2>

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

LCDBKLT_RTN_RC<5>

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

GND_LCDBKLT_GNDA

PPBUS_S0_LCDBKLT_PWR

PPVOUT_S0_LCDBKLT_SW

MIN_LINE_WIDTH=0.5 mm SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=35V

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 mm

LCDBKLT_SSTCMP_RC

MIN_NECK_WIDTH=0.2 mm

LCDBKLT_RTN<1>

MIN_LINE_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

LCDBKLT_RTN<2>

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

LCDBKLT_RTN<3>

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

LCDBKLT_RTN<4>

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

LCDBKLT_RTN<5>

MIN_NECK_WIDTH=0.2 mm

LCDBKLT_RTN<6>

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

LCDBKLT_RTN_RC<1>

LCDBKLT_RTN_RC<6>

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

LCDBKLT_ISET

LCDBKLT_VREF

LCDBKLT_RT

BKLT_PWM

70 70 59

59

63

7

63

70

6

IN

OUT

IN

D

G S

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

.

17 63

F9800

1 2

CRITICAL

0402-HF

2AMP-32V

62

62 70

R9808

1

2

1%

301K

MF-LF 402

1/16W

R9809

1

2

1%

147K

402

1/16W MF-LF

C9802

1

2

16V

10%

X5R 402

0.1UF

7

Q9807

3

1

2

SSM3K15FV

SOD-VESM-HF

Q9806

1 2 5 6

3

4

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

R9840

1

2

1/20W MF 201

100K

5%

R9841

1

2

1/20W MF 201

5%

100K

62

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

LCD Backlight Support

63 71

2.3.0

051-7631

PPBUS_S0_LCDBKLT_EN_DIV

=PPBUS_S0_LCDBKLT

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

MIN_LINE_WIDTH=0.4 mm

LVDS_IG_BKL_PWM

LVDS_IG_BKL_ON

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_PWR

PPBUS_S0_LCDBKLT_EN_L

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

BKLT_PWM

LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

LCDBKLT_ENA

63

62

70

17

70

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

ADDITIONAL CPU VCORE HF DECOUPLING

40x 2.2uF 0402

C9909

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9908

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9907

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9906

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9905

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9904

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9903

OMIT

6.3V 402-LF

2.2UF

20% CERM

CRITICAL

C9902

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9901

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9900

OMIT

CERM

6.3V

CRITICAL

2.2UF

20%

402-LF

C9919

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9918

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9917

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9916

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9915

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9914

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9913

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9912

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9911

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9910

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9929

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9928

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9927

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9926

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9925

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9924

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9923

OMIT

CRITICAL

6.3V

2.2UF

20%

402-LF

CERM

C9922

OMIT

2.2UF

6.3V

20%

402-LF

CERM

CRITICAL

C9921

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9920

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9939

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9938

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9937

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9936

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9935

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9934

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9933

OMIT

6.3V

2.2UF

20%

402-LF

CERM

CRITICAL

C9932

OMIT

6.3V

20% CERM

2.2UF

402-LF

CRITICAL

C9931

OMIT

2.2UF

CRITICAL

20% CERM

6.3V 402-LF

C9930

OMIT

CERM 402-LF

20%

2.2UF

6.3V

CRITICAL

71

2.3.0

64

051-7631

SYNC_DATE=

SYNC_MASTER=

Additional CPU/GPU Decoupling

=PPVCORE_S0_CPU

11 10

7

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

Some signals require 27.4-ohm single-ended impedance.

FSB Clock Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

PHYSICAL

FSB 2X

FSB 4X Signal Groups

SPACING

NET_TYPE

Signals

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)

CPU / FSB Net PropertiesFSB (Front-Side Bus) Constraints

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe.

FSB 2X signals / groups shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.

SR DG recommends at least 25 mils, >50 mils preferred

FSB 1X Signals

ELECTRICAL_CONSTRAINT_SET

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

CPU_50S

=STANDARD=STANDARD

*

CPU_27P4S

7 MIL 7 MIL

=27P4_OHM_SE=27P4_OHM_SE

*

=27P4_OHM_SE

=2x_DIELECTRIC

TOP,BOTTOM

?

CPU_AGTL

=STANDARD=STANDARD

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

MCP_50S

=50_OHM_SE

*

CLK_FSB

?

=3x_DIELECTRIC

CLK_FSB_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

MCP_FSB_COMP

?*

8 MIL

25 MIL

?

CPU_VCCSENSE

*

?*

CPU_GTLREF

25 MIL

=2:1_SPACING

?*

CPU_ITP

25 MIL

*

CPU_COMP

?

* ?

CPU_8MIL

8 MIL

=STANDARD

* ?

CPU_AGTL

TOP,BOTTOM

?

CLK_FSB =4x_DIELECTRIC

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

CPU/FSB Constraints

051-7631

2.3.0

7165

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

FSB_DSTB_50S

=50_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=4x_DIELECTRIC

?

FSB_ADSTB

TOP,BOTTOM

=50_OHM_SE

=STANDARD

=50_OHM_SE=50_OHM_SE

FSB_50S

=STANDARD

*

=50_OHM_SE

=4x_DIELECTRIC

FSB_DATA

?

TOP,BOTTOM

=5x_DIELECTRIC

?

FSB_DSTB

TOP,BOTTOM

=3x_DIELECTRIC

?

TOP,BOTTOM

FSB_ADDR

=3x_DIELECTRIC

?

TOP,BOTTOM

FSB_1X

=2x_DIELECTRIC

?*

FSB_DATA

=3x_DIELECTRIC

*

FSB_DSTB

?

FSB_ADDR

*

=STANDARD

* ?

FSB_1X =STANDARD

=2x_DIELECTRIC

* ?

FSB_ADSTB

FSB_50S

FSB_CPURST_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_LOCK_L

FSB_50S

FSB_1X FSB_1X

FSB_HITM_L

FSB_50S

FSB_1X

FSB_HIT_L

FSB_1X

FSB_ADDR

FSB_ADDR_GROUP0

FSB_A_L<16..3>

FSB_50S

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB3

FSB_DSTB_L_N<3>

FSB_DATA_GROUP0

FSB_50S

FSB_D_L<15..0>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB0

FSB_DSTB_L_P<0>

FSB_DSTB_50S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_50S

FSB_DATA_GROUP1

FSB_D_L<31..16>

FSB_DATA

FSB_50S

FSB_DATA_GROUP1

FSB_DINV_L<1>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_50S

FSB_DATA_GROUP2

FSB_DINV_L<2>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB2

FSB_DSTB_L_N<2>

FSB_50S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_DATA

FSB_50S

FSB_DATA_GROUP3

FSB_DINV_L<3>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_ADDR_GROUP0

FSB_REQ_L<4..0>

FSB_ADDR

FSB_50S

FSB_ADDR_GROUP1

FSB_ADDR

FSB_A_L<35..17> FSB_ADSTB_L<1>

FSB_ADSTB1

FSB_ADSTB

FSB_50S

FSB_1X FSB_1X

FSB_ADS_L

FSB_50S

FSB_BREQ0_L

FSB_1X

FSB_50S

FSB_BREQ1_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_BNR_L

FSB_50S

FSB_1X FSB_1X

FSB_BPRI_L

FSB_50S

FSB_1X

FSB_DBSY_L

FSB_1X

FSB_50S

FSB_1X

FSB_DEFER_L

FSB_1X

FSB_50S

FSB_1X

FSB_DRDY_L

FSB_1X

FSB_50S

FSB_1X

FSB_RS_L<2..0>

FSB_1X

FSB_50S

FSB_1X

FSB_TRDY_L

FSB_1X

CPU_50S

CPU_BSEL

CPU_BSEL<2..0>

CPU_AGTL

CPU_50S

CPU_FERR_L

CPU_8MIL

CPU_50S

CPU_ASYNC

CPU_IGNNE_L

CPU_AGTL

CPU_50S

CPU_INIT_L

CPU_AGTL

CPU_50S

CPU_ASYNC_R

CPU_INTR

CPU_AGTL

CPU_50S

CPU_ASYNC_R

CPU_NMI

CPU_AGTL

CPU_50S

CPU_PROCHOT_L

CPU_AGTL

CPU_50S

CPU_PWRGD

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_SMI_L

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_STPCLK_L

CPU_AGTL

CPU_50S

PM_THRMTRIP_L

CPU_8MIL

CPU_50S

FSB_CPUSLP_L

CPU_AGTL

CPU_50S

CPU_FROM_SB

CPU_DPSLP_L

CPU_AGTL

CPU_50S

CPU_DPRSTP_L

CPU_AGTL

CPU_50S

CPU_ASYNC

FSB_DPWR_L

CPU_AGTL MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_VDD

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_GND

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_VCC

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_GND

MCP_50S

FSB_CLK_CPU

FSB_CLK_CPU_P

CLK_FSB

CLK_FSB_100D

FSB_CLK_CPU

FSB_CLK_CPU_N

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP_P

FSB_CLK_ITP

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP_N

FSB_CLK_MCP

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_P

FSB_CLK_MCP

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_N

CPU_IERR_L

CPU_50S

CPU_IERR_L

CPU_50S

PM_DPRSLPVR

CPU_AGTL

PM_DPRSLPVR

CPU_50S

CPU_AGTL

IMVP_DPRSLPVR

CPU_GTLREF

CPU_50S

CPU_GTLREF

CPU_COMP

CPU_50S

CPU_COMP<3>

CPU_COMP

CPU_COMP<2>

CPU_27P4S

CPU_COMP

CPU_COMP<1>

CPU_50S

CPU_COMP

CPU_COMP CPU_COMP

CPU_27P4S

CPU_COMP<0>

XDP_TDI CPU_50S CPU_ITP

XDP_TDI

XDP_TDO CPU_50S CPU_ITP

XDP_TDO

XDP_TMS CPU_50S CPU_ITP

XDP_TMS

XDP_TCK CPU_50S CPU_ITP

XDP_TCK

XDP_TRST_L

CPU_50S CPU_ITP

XDP_TRST_L

XDP_BPM_L

CPU_50S

XDP_BPM_L<4..0>

CPU_ITP

XDP_BPM_L5

CPU_50S CPU_ITP

XDP_BPM_L<5> XDP_CPURST_L

CPU_ITPCPU_50S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

IMVP6_VSEN_N

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_50S

IMVP6_VID<6..0>

CPU_8MIL

CPU_VID<6..0>

CPU_50S

CPU_8MIL

FSB_ADSTB

FSB_50S

FSB_ADSTB_L<0>

FSB_ADSTB0

FSB_DSTB_L_N<1>

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB1

FSB_50S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

CPU_50S

CPU_ASYNC

CPU_A20M_L

CPU_AGTL

FSB_DATA_GROUP0

FSB_50S

FSB_DINV_L<0>

FSB_DATA

13

50

12

13

40

13

40

13

12

50

9

13

9

13

9

13

9

13

12

13

9

13

12

50

25

9

12

9

12

50

11

13

8

9

8

13

9

8

9

8

9

8

9

13

9

6

13

9

20

50

9

6

9

6

10

50

11

10

9

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MCP MEM COMP Signal Constraints

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps

DQ signals should be matched within 5 ps of associated DQS pair.

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

A/BA/cmd signals should be matched within 5 ps of CLK pairs.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.

No DQS to clock matching requirement.

DDR3:

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

Memory Bus Spacing Group Assignments

ELECTRICAL_CONSTRAINT_SET

Memory Net Properties

PHYSICAL

NET_TYPE

SPACING

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Constraints

0.110 MM

=50_OHM_SE

=STANDARD

*

=STANDARD

MEM_50S

=50_OHM_SE=50_OHM_SE

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

Memory Constraints

66 71

2.3.0

051-7631

GND

BUS2PWR_GND

*

MEM_DQS

*

GND

MEM_DATA

BUS2PWR_GND

PWR

*

MEM_DQS

BUS2PWR_GND

*

PWR

BUS2PWR_GND

MEM_DATA

*

BUS2PWR_GND

GND

MEM_CMD

*

BUS2PWR_GND

PWR

MEM_CMD

BUS2PWR_GND

PWR

*

MEM_CTRL

*

BUS2PWR_GND

GND

MEM_CTRL

*

BUS2PWR_GND

GND

MEM_CLK

*

BUS2PWR_GND

PWR

MEM_CLK

GND_P2MM

MEM_DQS

*

GND

PP1V5_MEM

PWR_P2MM

*

MEM_CLK

PP1V5_MEM

PWR_P2MM

*

MEM_CTRL

PWR_P2MM

PP1V5_MEM

*

MEM_DQS

?

MEM_2OTHER

*

25 MIL

MEM_CLK

MEM_DATA

*

MEM_DATA2MEM

MEM_CTRLMEM_DATA

*

MEM_CMD

MEM_DATA2MEM

MEM_DATA

*

MEM_DATA

MEM_DATA2DATA

MEM_DATA

*

MEM_2OTHER

MEM_CTRL

* *

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_DATA

* *

MEM_2OTHER

MEM_DQS

**

MEM_CMD2CMD

MEM_CMD

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

*

MEM_CMD

MEM_DATA2MEM

MEM_DATA

*

MEM_DQS

MEM_2OTHER

MEM_CLK

**

MEM_DQSMEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2MEM

MEM_CLK

*

=1.1:1_SPACING

MEM_DATA2DATA

* ?

MEM_CMDMEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

=2.28:1_SPACING

MEM_DATA2MEM

* ?

=2.28:1_SPACING

?

MEM_DQS2MEM

*

MEM_CLK MEM_CLK

MEM_CLK2MEM

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

*

MEM_CMD2MEM

MEM_DQSMEM_CMD

*

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_CLK2MEM

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

MEM_CMDMEM_CLK

*

=2.28:1_SPACING

MEM_CMD2MEM

* ?

=2.28:1_SPACING

MEM_CLK2MEM

* ?

=1.1:1_SPACING

?

MEM_CMD2CMD

*

=2.28:1_SPACING

MEM_CTRL2MEM

* ?

=1.1:1_SPACING

?*

MEM_CTRL2CTRL

MCP_MEM_COMP

8 MIL

* ?

MEM_CLK

GND

GND_P2MM

*

MEM_CTRL GND_P2MM

*

GND

*

MEM_CMD

GND_P2MM

GND

MEM_DATA

GND

GND_P2MM

*

PP1V5_MEM

MEM_CMD

*

PWR_P2MM

PP1V5_MEM

*

PWR_P2MMMEM_DATA

=STANDARD

7 MIL7 MIL

Y

MCP_MEM_COMP

*

=STANDARD

MEM_CMD2MEM

MEM_CTRL

*

MEM_CMD

MEM_CMD2MEM

MEM_CLKMEM_CMD

*

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

MEM_90D_VDD

*

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

*

MEM_90D

=50_OHM_SE =50_OHM_SE

MEM_50S_VDD

=STANDARD

*

=STANDARD

=50_OHM_SE

0.110 MM

VOLTAGE=0V

MCP_MEM_COMP_VDD

MCP_MEM_COMP MCP_MEM_COMPMCP_MEM_COMP

VOLTAGE=1.5V

MCP_MEM_COMP_GND

MCP_MEM_COMPMCP_MEM_COMP MCP_MEM_COMP

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_90D MEM_DQS

MEM_B_DQS6

MEM_B_DQS_N<6>

MEM_90D MEM_DQS

MEM_90D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_DQS

MEM_B_DQS5

MEM_B_DQS_N<5>

MEM_90D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_90D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_90D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_DQSMEM_90D

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_90D MEM_DQS

MEM_B_DQS0

MEM_B_DQS_N<0>

MEM_90D MEM_DQS

MEM_B_DQ_BYTE7

MEM_B_DM<7>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DM<5>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DM<0>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_50S

MEM_DATA

MEM_B_DQ<7..0>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_50S

MEM_DATA

MEM_50S

MEM_B_CMD

MEM_B_WE_L

MEM_CMD

MEM_B_CMD

MEM_CMD

MEM_B_CAS_L

MEM_50S

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_DQSMEM_90D

MEM_A_DQS5

MEM_A_DQS_N<5>

MEM_DQSMEM_90D

MEM_90D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_DQS

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_DQSMEM_90D

MEM_A_DQS_P<3>

MEM_90D MEM_DQS

MEM_A_DQS3

MEM_90D

MEM_A_DQS2

MEM_A_DQS_N<2>

MEM_DQS

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_DQSMEM_90D

MEM_90D

MEM_B_CLK

MEM_CLK

MEM_B_CLK_P<0>

MEM_CLK

MEM_B_CLK

MEM_B_CLK_N<0>

MEM_90D

MEM_A_CLK

MEM_CLK

MEM_A_CLK_N<0>

MEM_90D

MEM_A_CLK

MEM_CLK

MEM_A_CLK_P<0>

MEM_50S

MEM_CTRL

MEM_A_CNTL

MEM_A_CKE<1..0> MEM_A_CS_L<1..0>

MEM_CTRL

MEM_A_CNTL

MEM_50S

MEM_CTRL

MEM_A_CNTL

MEM_A_ODT<1..0>

MEM_50S

MEM_A_CMD

MEM_CMD

MEM_A_A<14..0>

MEM_50S

MEM_A_CMD

MEM_CMD

MEM_A_BA<2..0>

MEM_50S

MEM_A_CAS_L

MEM_CMD

MEM_A_CMD

MEM_50S MEM_CMD

MEM_A_RAS_L

MEM_A_CMD

MEM_50S MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_50SMEM_A_DQ_BYTE0

MEM_DATA

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE1 MEM_50S

MEM_DATA

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE3

MEM_DATA

MEM_A_DQ<31..24>

MEM_50S

MEM_A_DQ_BYTE2

MEM_DATA

MEM_50S

MEM_A_DQ<23..16>

MEM_A_DQ<47..40>

MEM_DATA

MEM_A_DQ_BYTE5 MEM_50S

MEM_A_DQ<39..32>

MEM_DATA

MEM_A_DQ_BYTE4 MEM_50S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_50S

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_DATA

MEM_50S

MEM_DATA

MEM_A_DM<0>

MEM_A_DQ_BYTE0 MEM_50S

MEM_A_DM<2>

MEM_A_DQ_BYTE2 MEM_50S

MEM_DATA

MEM_A_DM<1>

MEM_A_DQ_BYTE1 MEM_50S

MEM_DATA

MEM_A_DM<4>

MEM_A_DQ_BYTE4 MEM_50S

MEM_DATA

MEM_A_DM<3>

MEM_A_DQ_BYTE3 MEM_50S

MEM_DATA

MEM_A_DM<5>

MEM_A_DQ_BYTE5 MEM_50S

MEM_DATA

MEM_A_DM<7>

MEM_A_DQ_BYTE7 MEM_50S

MEM_A_DM<6>

MEM_A_DQ_BYTE6 MEM_50S

MEM_DATA

MEM_A_DQS0

MEM_DQSMEM_90D

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_DQSMEM_90D

MEM_90D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQS MEM_DQS

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_90D

MEM_A_DQS3

MEM_A_DQS_N<3>

MEM_DQSMEM_90D

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQSMEM_90D

MEM_B_CS_L<1..0>

MEM_B_CNTL

MEM_CTRL

MEM_50S

MEM_CMD

MEM_B_A<14..0>

MEM_B_CMD

MEM_50S

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE4 MEM_50S

MEM_B_DQ<39..32>

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DM<1>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DM<2>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DM<3>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_B_DM<4>

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DM<6>

MEM_50S

MEM_DATA

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_90D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_N<2>

MEM_90D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_90D MEM_DQS

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_90D MEM_DQS

MEM_B_DQS4

MEM_90D

MEM_B_DQS_N<4>

MEM_DQS

MEM_B_CMD

MEM_B_BA<2..0>

MEM_CMDMEM_50S

MEM_B_CMD

MEM_B_RAS_L

MEM_CMDMEM_50S

MEM_DQS

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_90D

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_90D MEM_DQS

MEM_B_ODT<1..0>

MEM_B_CNTL

MEM_CTRL

MEM_50S

MEM_B_CKE<1..0>

MEM_B_CNTL

MEM_CTRL

MEM_50S

MEM_90D

MEM_A_DQS_N<7>

MEM_DQS

MEM_A_DQS7

MEM_90D

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQS

MEM_90D

MEM_A_DQS6

MEM_A_DQS_N<6>

MEM_DQS

NET_SPACING_TYPE=PP1V5_MEM

=PP1V8R1V5_S0_MCP_MEM

MEM_CLK

MEM_RESET_L

GND

NET_SPACING_TYPE=GND

30

33

29

30

28

30

22

28

30

29

30

29

30

29

28

27

29

27

28

27

28

27

28

27

28

29

30

29

30

29

30

29

30

29

28

15

27

15

14

7

26

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

CRT signal single-ended impedence varies by location:

- 50-ohm from first to second termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible). R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

Digital Video Signal Constraints

PCI-Express

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

Analog Video Signal Constraints

- 37.5-ohm from MCP to first termination resistor.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SATA Interface Constraints

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

=3x_DIELECTRIC

TOP,BOTTOM

?

SATA

SATA_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

LVDS

TOP,BOTTOM

=4x_DIELECTRIC

?

DP_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

PCIE_90D

*

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

PCIE

TOP,BOTTOM

=4X_DIELECTRIC

?

CLK_PCIE

*

20 MIL

?

MCP_PEX_COMP

*

8 MIL

?

PCIE

*

=3X_DIELECTRIC

?

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?

CLK_PCIE_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

CRT_SYNC

16 MIL

?

LVDS

*

=3x_DIELECTRIC

?

SATA_100D_HDD

*

=100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD =100_OHM_DIFF_HDD

DISPLAYPORT

*

=3x_DIELECTRIC

?

LVDS_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

=4x_DIELECTRIC

SATA

* ?

SATA_TERMP

*

8 MIL

?

SYNC_MASTER=M97

MCP Constraints 1

051-7631

67

SYNC_DATE=02/04/2008

2.3.0

71

MCP_DV_COMP

*

Y 20 MIL =STANDARD

=STANDARD =STANDARD

20 MIL

MCP_DAC_COMP

*

=2:1_SPACING

?

CRT_50S

*

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

*

=4:1_SPACING

?

CRT

CRT_2CRT

=STANDARD

?*

CRT_2CLK

*

50 MIL

?

CRT_2SWITCHER

*

250 MIL

?

MCP_DV_COMP

MCP_HDMI_RSET

MCP_DV_COMP

MCP_HDMI_VPROBE

MCP_HDMI_VPROBE LVDS_IG_A_CLK_F_P

LVDS_100D

LVDS_IG_A_CLK

LVDS

DP_AUX_CH

DP_100D

DISPLAYPORT

DP_AUX_CH_SW_P

DP_100D

DP_AUX_CH

DISPLAYPORT

DP_AUX_CH_SW_N

DP_100D

DP_AUX_CH

DISPLAYPORT

DP_AUX_CH_C_N

DP_AUX_CH

DP_100D

DISPLAYPORT

DP_AUX_CH_C_P

SATA_HDD_D2R_UF_N

SATA

SATA_100D_HDD

MCP_SATA_TERMP

SATA_TERMP

MCP_SATA_TERMP

SATA_HDD_D2R_UF_P

SATA

SATA_100D_HDD

SATA

SATA_HDD_D2R_C_N

SATA_100D_HDD

SATA_HDD_D2R_C_P

SATA

SATA_100D_HDD

SATA_HDD_D2R_P

SATA_HDD_D2R

SATA

SATA_100D_HDD

SATA_HDD_D2R_N

SATA

SATA_100D_HDD

SATA_HDD_R2D_UF_P

SATA_100D_HDD

SATA

SATA_HDD_R2D_UF_N

SATA_100D_HDD

SATA

SATA_HDD_R2D_N

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA_HDD_R2D_P

SATA

SATA_100D_HDD

SATA_HDD_R2D_C_N

SATA

SATA_HDD_R2D_C_P

SATA_100D_HDD

SATA

SATA_HDD_R2D

MCP_IFPAB_VPROBE

LVDS_IG_B_DATA_N<3>

LVDS

LVDS_100D

LVDS_IG_B_DATA3

MCP_IFPAB_RSET

MCP_DV_COMP

MCP_IFPAB_RSET

LVDS_IG_B_DATA_P<3>

LVDS_100D

LVDS

LVDS_IG_B_DATA3

LVDS_IG_B_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_IG_B_DATA

LVDS_100D

LVDS

LVDS_IG_B_DATA

LVDS_IG_B_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_IG_B_CLK

LVDS_IG_B_CLK_N

LVDS_100D

LVDS

LVDS_IG_A_DATA3

LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P

LVDS_100D

LVDS

LVDS_IG_B_CLK

LVDS_IG_A_DATA_P<3>

LVDS

LVDS_100D

LVDS_IG_A_DATA3

LVDS_IG_A_DATA

LVDS

LVDS_IG_A_DATA_N<2..0>

LVDS_100D

LVDS_IG_A_DATA_F_N<2..0>

LVDS_100D

LVDS

LVDS_IG_A_DATA

LVDS_IG_A_DATA_F_P<2..0>

LVDS_100D

LVDS

LVDS_IG_A_DATA

LVDS

LVDS_IG_A_DATA_P<2..0>

LVDS_100D

LVDS_IG_A_CLK

LVDS

LVDS_100D

LVDS_IG_A_CLK_N

LVDS

LVDS_IG_A_CLK

LVDS_IG_A_CLK_P

LVDS_100D

LVDS_IG_A_CLK_F_N

LVDS_100D

LVDS

LVDS_IG_A_CLK

DP_IG_AUX_CH_P

DP_AUX_CH

DP_100D

DISPLAYPORT

DP_100D

DP_AUX_CH

DP_IG_AUX_CH_N

DISPLAYPORT

DP_ML

DP_ML_F_N<3..0>

DP_100D

DISPLAYPORT DISPLAYPORT

DP_100D

DP_ML

DP_ML_P<3..0>

DP_100D

DP_ML

DP_ML_N<3..0>

DISPLAYPORT

DP_ML

DP_ML_F_P<3..0>

DP_100D

DISPLAYPORT

TMDS_IG_TXD_N<2..0>

DP_100D

TMDS_IG_TXD

TMDS_IG_TXC_P

DP_100D

TMDS_IG_TXC DISPLAYPORT

DP_100D

TMDS_IG_TXC

TMDS_IG_TXC_N

DISPLAYPORT

DP_ML_C_P<3..0>

DISPLAYPORT

DP_100D

DP_ML

DP_ML_C_N<3..0>

DP_100D

DP_ML

DISPLAYPORT

PCIE_CLK100M_MINI_N

CLK_PCIE_100D

CLK_PCIE

PCIE

PCIE_90D

PCIE_FW_R2D_N

PCIE_MINI_R2D

PCIE_90D

PCIE

PCIE_MINI_R2D_C_P

PCIE_90D

PCIE

PCIE_MINI_R2D_N

PCIE_MINI_R2D_C_N

PCIE_90D

PCIE

PCIE_90D

PCIE_FW_R2D_P

PCIE

PCIE_90D

PCIE_FW_D2R_C_N PCIE_EXCARD_R2D_P

PCIE_90D

PCIE

PCIE_EXCARD_R2D

PCIE_90D

PCIE

PCIE_EXCARD_R2D_C_P

PCIE_90D

PCIE_EXCARD_R2D_C_N

PCIE

PCIE_90D

PCIE_FC_R2D_C_N

PCIE

PCIE_FC_D2R_P

PCIE_FC_D2R

PCIE

PCIE_90D

PCIE_FC_R2D_P

PCIE

PCIE_90D

PCIE_EXCARD_D2R_N

PCIE

PCIE_90D

PCIE_FW_D2R_C_P

PCIE

PCIE_90D

PCIE_FW_R2D_C_N

PCIE_MINI_D2R_P

PCIE_MINI_D2R

PCIE_90D

PCIE

PCIE_90D

PCIE_FW_D2R_N

PCIE

PCIE_90D

PCIE

PCIE_EXCARD_R2D_N

PCIE_EXCARD_D2R

PCIE_EXCARD_D2R_P

PCIE_90D

PCIE

PCIE_90D

PCIE_FC_R2D_N

PCIE

PCIE_FC_R2D

PCIE

PCIE_90D

PCIE_FC_R2D_C_P

CLK_PCIE_100D

PEG_CLK100M_P

CLK_PCIE

MCP_PE0_REFCLK

MCP_PE4_REFCLK

PCIE_CLK100M_FC_P

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_FC_N

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_FW_P

CLK_PCIE

CLK_PCIE_100D

MCP_PE2_REFCLK

MCP_PE1_REFCLK

PCIE_CLK100M_MINI_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_FW_N

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_EXCARD_P

MCP_PE3_REFCLK

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_EXCARD_N

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

PEG_CLK100M_N

CLK_PCIE

PCIE_90D

PCIE_FC_D2R_N

PCIE

MCP_PEX_CLK_COMP

MCP_PEX_COMP

TMDS_IG_TXD_P<2..0>

DP_100D

TMDS_IG_TXD DISPLAYPORT

PCIE_FW_D2R_P

PCIE_90D

PCIE_FW_D2R

PCIE

PCIE_90D

PCIE_FW_R2D

PCIE_FW_R2D_C_P

PCIE

PCIE_MINI_D2R_N

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_MINI_R2D_P

PEG_D2R_C_N<15..0>

PCIE

PCIE_90D

PEG_D2R_C_P<15..0>

PCIE

PCIE_90D

PEG_D2R_N<15..0>

PCIE

PCIE_90D

PEG_D2R_P<15..0>

PCIE

PCIE_90D

PEG_D2R

PEG_R2D_C_N<15..0>

PCIE

PCIE_90D

PEG_R2D_C_P<15..0>

PCIE

PCIE_90D

PEG_R2D

PEG_R2D_N<15..0>

PCIE

PCIE_90D

PEG_R2D_P<15..0>

PCIE

PCIE_90D

61

60

59

23

59

35

36

23

17

23

17

59

60

61

34

16

34

16

34

17

6

60

6

36

19

36

6

19

36

6

19

17

8

17

8

6

59

6

17

6

17

35

60

35

6

16

8

16

8

16

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PCI Bus Constraints

LPC Bus Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPI Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SIO Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

HD Audio Interface Constraints

SMBus Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

=55_OHM_SE=55_OHM_SE

=STANDARD

CLK_PCI_55S

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

=STANDARD

*

=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

PCI_55S

=55_OHM_SE

USB_90D

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

*

=90_OHM_DIFF

=STANDARD=STANDARD

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

SPI_55S

=55_OHM_SE

*

=STANDARD =STANDARD

SMB_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

USB

?

TOP,BOTTOM

=4x_DIELECTRIC

=STANDARD

*

LPC_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

* ?

USB

=2x_DIELECTRIC

MCP_USB_RBIAS

8 MIL 8 MIL

=STANDARD=STANDARD

=STANDARD =STANDARD

*

=2x_DIELECTRIC

?*

SMB

=2x_DIELECTRIC

HDA

* ?

?*

8 MIL

MCP_HDA_COMP

*

CLK_SLOW

?

8 MIL

* ?

PCI =STANDARD

* ?

CLK_PCI

8 MIL

=STANDARD =STANDARD

CLK_SLOW_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

=STANDARD=STANDARD

HDA_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

*

SPI

?

8 MIL

?*

8 MIL

CLK_LPC

* ?

LPC

6 MIL

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

CLK_LPC_55S

*

051-7631

2.3.0

7168

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

MCP Constraints 2

PCI_AD24

PCI

PCI_AD<24>

PCI_55S

PCI

PCI_C_BE_L<3..0>

PCI_55S

PCI_C_BE_L

PCI

PCI_AD

PCI_PAR

PCI_55S

PCI_CNTL

PCI

PCI_IRDY_L

PCI_55S

PCI_CNTL

PCI

PCI_PERR_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI_STOP_L

PCI_CNTL

PCI

PCI_SERR_L

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_TRDY_L

PCI

PCI_55S

PCI_INTX_L

PCI_55S

PCI_INTY_L

PCI

CLK_PCI_55S

CLK_PCI

PCI_CLK33M_MCP

MCP_PCI_CLK2

CLK_PCI

CLK_PCI_55S

PCI_CLK33M_MCP_R

LPC_CLK33M_LPCPLUS

CLK_LPC

CLK_LPC_55S

MCP_DEBUG<7..0>

MCP_DEBUG

PCI

PCI_55S

PCI_AD<23..8>

PCI_AD

PCI

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_DEVSEL_L

PCI_AD

PCI_AD<31..25>

PCI

PCI_55S

PCI_REQ0_L

PCI

PCI_REQ0_L

PCI_55S

PCI

PCI_FRAME_L

PCI_55S

PCI_CNTL

USB_EXTA_P

USB_90D

USB

USB_EXTA

MCP_LPC_CLK0

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_SMC_R LPC_CLK33M_SMC

CLK_LPC

CLK_LPC_55S

LPC_55S

LPC_RESET_L

LPC

LPC_RESET_L

LPC_55S

LPC

LPC_FRAME_L

LPC_55S

LPC_AD

LPC

LPC_AD<3..0>

PCI_INTZ_L

PCI

PCI_55S

PCI_INTZ_L

PCI_INTW_L

PCI

PCI_INTW_L

PCI_55S

PCI

PCI_GNT1_L

PCI_55S

PCI_REQ1_L

PCI

PCI_55S

PCI

PCI_55S

PCI_GNT0_L

USB_90D

USB_EXTD_P

USB

USB_EXTD

USB

USB_90D

USB_EXTA_MUXED_P

USB_90D

USB_CAMERA

USB

USB_CAMERA_P

USB

USB_90D

USB_CAMERA_N

USB

USB_90D

USB_CAMERA_CONN_P

USB_90D

USB_EXTA_N

USB

USB_90D

USB_EXTD_N

USB

USB_90D

USB

USB_CAMERA_CONN_N USB_BT_P

USB

USB_90D

USB_BT

USB_90D

USB

CONN_USB2_BT_N

USB_90D

USB

CONN_USB2_BT_P

USB

USB_90D

USB_TPAD

USB_TPAD_P

USB_90D

USB

USB_MINI_N

USB_MINI_P

USB_MINI

USB_90D

USB

USB_90D

CONN_USB_EXTA_N

USB

USB_90D

CONN_USB_EXTA_P

USB

USB_90D

USB_EXTA_MUXED_N

USB_90D

USB

USB_EXTB_N

SMB_55S

SMB

SMBUS_MCP_1_DATA

HDA_55S

HDA

HDA_BIT_CLK

HDA_55S

HDA

HDA_BIT_CLK_R

HDA_55S

HDA

HDA_SYNC_R

HDA_55S

HDA_SYNC

HDA

HDA_SYNC

HDA_RST_L

HDA_55S

HDA

HDA_RST_R_L

HDA_55S

HDA_SDOUT

HDA

HDA_SDOUT

MCP_HDA_PULLDN_COMP

MCP_HDA_COMP

PM_CLK32K_SUSCLK_R

CLK_SLOW

CLK_SLOW_55S

MCP_SUS_CLK

SPI_MISO

SPI_55S

SPI_MISO

SPI

HDA_55S

HDA

HDA_SDOUT_R

HDA

HDA_SDIN_CODEC

HDA_55S

HDA

HDA_SDIN0

HDA_55S

HDA

HDA_RST_L

USB

CONN_TPAD_USB_N

USB_90D

USB

CONN_TPAD_USB_P

USB_90D

USB

USB_EXTB

USB_EXTB_P

USB

USB_90D

USB_IR

USB_IR_P

USB

USB_90D

USB_IR_N

MCP_USB_RBIAS

MCP_USB_RBIAS_GND

MCP_USB_RBIAS

USB_90D

USB

CONN_USB_EXTB_P CONN_USB_EXTB_N

USB

USB_90D

USB

USB_EXCARD

USB_EXCARD_P

USB_90D

USB

USB_EXCARD_N

USB_90D

USB

USB_EXTC

USB_EXTC_P USB_EXTC_N

USB_90D

USB

SMB_55S

SMBUS_MCP_0_CLK

SMB

SMBUS_MCP_0_DATA

SMB

SMBUS_MCP_0_DATA

SMB_55S SMB_55S

SMB

SMBUS_MCP_1_CLK

USB

USB_90D

USB_BT_N

USB

USB_90D

USB_TPAD_N

SPI_CS0_R_L

SPI_CS0 SPI_55S

SPI

SPI_MISO_R

SPI_55S

SPI

SPI_CS0_L

SPI_55S

SPI

SPI_CLK

SPI_CLK_MUX

SPI_55S

SPI

SPI_55S

SPI

SPI_MOSI

PM_CLK32K_SUSCLK

CLK_SLOW_55S

CLK_SLOW

SPI_55SSPI_CLK

SPI

SPI_CLK_R

SPI_55S

SPI_CLK

SPI

SPI_55S

SPI

SPI_MOSI

SPI_MOSI_R

SPI_CS0

SPI_MLB_CS_L

SPI_55S

SPI

SPI_MOSI_MUX

SPI_MOSI

SPI_55S

SPI

SPI_MISO

SPI_MISO_MUX

SPI_55S

SPI

42

18

41

35

20

41

12

19

24

39

24

39

19

42

20

24

41

20

35

19

12

42

19

41

48

39

41

48

18

24

6

18

8

18

24

18

8

37

8

37

8

20

6

20

6

20

6

20

6

20

8

19

8

6

20

8

20

48

41

48

24

20

48

20

41

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMC Constraints

051-7631

2.3.0

7169

SYNC_MASTER=M97

SYNC_DATE=02/04/2008

=STANDARD =STANDARD

0.1 MM 0.1 MM

*

=STANDARD=STANDARD

1TO1_DIFFPAIR

SMB

SMBUS_SMC_B_S0_SCL

SMB_55S

SMB

SMBUS_SMC_MGMT_SDA

SMB_55S

SMBUS_SMC_A_S3_SDA

SMB

SMB_55S

SMBUS_SMC_A_S3_SCL

SMB

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSO_N

1TO1_DIFFPAIR

SMB_55S

SMB

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMB_55S

SMBUS_SMC_BSA_SCL

SMB

SMBUS_SMC_BSA_SCL

SMBUS_SMC_B_S0_SDA

SMB_55S

SMBUS_SMC_B_S0_SDA

SMB

SMBUS_SMC_BSA_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMBUS_SMC_MGMT_SCL

1TO1_DIFFPAIR

CHGR_CSI_P

CHGR_CSI

42

6

42

6

42

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

I1

PP0V75_S0

I10

PP1V05_ENET_MCP_PLL_MAC

I100

PP1V5_S0

I101

PP1V5_S0_FC_AVDDL_F

I102

PPVBATT_G3H_R

I103

PPVBAT_G3H_CHGR_OUT

I104

PPVBAT_G3H_CHGR_REG

I105

PPVBAT_G3H_CHRGR_REG_0

I106

PPVBAT_G3H_CHRGR_REG_R

I107

PPVDCIN_G3H_PRE2

I108

PPVCORE_S0_CPU

I109

PPVDCIN_G3H_PRE

I11

PP1V05_S0_MCP_PEX_AVDD

I110

PPVDCIN_G3H_PRE_0

I111

PPVOUT_S0_LCDBKLT

I112

PPVDCIN_G3H_PRE_R

I113

PPVIN_S5_IMVP6_VIN

I114

PPVOUT_S0_LCDBKLT_SW

I12

PP1V05_S0

I13

PP1V05_S0_MCP_PEX_AVDD_R

I14

PP1V05_S0_MCP_PEX_DVDD_R

I15

PP1V05_S0_MCP_PLL_FSB

I16

PP1V05_S0_MCP_PLL_CORE

I17

PP1V05_S0_MCP_PLL_PEX

I18

PP1V05_S0_MCP_PLL_NV

I19

PP1V05_S0_MCP_PLL_SATA

I2

PP0V75_S3

I20

PP1V05_S5

I21

PP1V05_S0_MCP_SATA_AVDD

I22

PP1V5_S0_FC_AVDDT_F

I23

PP1V2_S0_FC_VDD

I24

PP1V5_S3

I25

PP1V8_S0

I26

PP2V_S0_MCPREG_REF

I27

PP3V3_LCDVDD_SW_F

I28

PP3V3_LCDVDD_SW

I29

PP3V3_S0

I3

PP0V75_S3_MEM_VREFCA

I30

PP3V3_RMGT

I31

PP3V3_S0_CPUTHMSNS_R

I32

PP3V3_S0_DPPWR

I33

PP3V3_S0_DPFUSE

I34

PP3V3_S0_HDD_F

I35

PP3V3_S0_FC_AVDD_F

I36

PP3V3_S0_IMVP6_3V3

I37

PP3V3_S0_MCPREG_VREF3

I38

PP3V3_S0_LCD_F

I39

PP3V3_S0_MCP_DAC

I4

PP0V75_S3_MEM_VREFDQ

I40

PP3V3_S0_MCP_VPLL

I41

PP3V3_S0_MCP_PLL_USB

I42

PP3V3_S3_AP_AUX

I43

PP3V3_S3

I44

PP3V3_S3_AP_AUX_F

I45

PP3V3_S5

I46

PP3V3_S0_MIC_F

I47

PP3V3_S5_MCP

I48

PP3V3_S5_AVREF_SMC

I49

PP3V3_S5_SMC_AVCC

I5

PP18V5_DCIN

I50

PP3V42G3H_SW

I51

PP3V42_G3H_IPD_F

I52

PP3V42_G3H

I53

PP5V_S0

I54

PP3V42_G3H_SMCUSBMUX_R

I55

PP5V_S0_IMVP6_VDD

I56

PP5V_S0_MCPREG_VCC

I57

PP5V_S0_KBDLED_F

I58

PP5V_S3_CAMERA_F

I59

PP5V_S3

I6

PP18V5_DCIN_ONEWIRE

I7

PP18V5_G3H

PP5V_S3_TOPCASE_F

I71

PP5V_S3_MCPREG_LDO

I72

PP5V_S3_USB2_EXTA

I73

PP5V_S3_USB2_EXTA_F

I74

PPBUS_G3HRS5_VSENSE

I75

PPBUS_G3H

I76

PPBUS_S0_LCDBKLT_EN_DIV

I77

PPBUS_R_G3H

I78

PPBUS_S0_LCDBKLT_EN_L

I79

I8

PP18V5_S5_CHGR_SW_R

PPBUS_S0_LCDBKLT_PWR

I80

PPBUS_S0_LCDBKLT_FUSED

I81

PPDCIN_G3H_R

I82

PPDCIN_G3H

I83

PPMCPCORE_S0

I84

PPVBAT_G3H_CHGR_OUT

I85

PPVBATT_G3H_R

I86

I9

PP1V05_RMGT

=STANDARDPWR

* ?

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7631

2.3.0

7170

M96 Power and Ground Nets

BUS2PWR_GND

?

*

0.228 MM

NET_SPACING_TYPE=GND

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PP1V5_MEM NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PWR

NET_SPACING_TYPE=PP1V5_MEM

NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR

30

29

62

28

61

28

37

7

22

7

70

7

58

22

59

7

22

7

22

7

59

7

27

35

36

59

23

27

23

22

34

7

59

40

49

38

7

38

59

7

38

35

7

63

7

70

6

17

6

49

58

6

43

7

58

6

58

50

62

6

13

15

16

20

19

7

6

19

6

59

6

25

7

45

6

61

6

50

6

21

25

17

19

6

34

6

39

6

49

6

37

50

6

49

6

37

6

43

6

63

6

63

58

62

63

49

6

58

49

7

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

M96 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

Y

90_OHM_DIFF

TOP,BOTTOM

0.205 MM

0.160 MM 0.160 MM

0.200 MM

90_OHM_DIFF

0.250 MM

ISL2,ISL4,ISL5,ISL10,ISL11,ISL13

0.085 MM

0.250 MM

0.085 MM

Y

*

=STANDARD=STANDARD

90_OHM_DIFF

=STANDARD

N

0.150 MM

0.180 MM

Y

70_OHM_DIFF

TOP,BOTTOM

0.180 MM

0.150 MM

70_OHM_DIFF

ISL2,ISL4,ISL5,ISL10,ISL11,ISL13

Y

0.200 MM

0.132 MM

0.200 MM

0.132 MM

=STANDARD

70_OHM_DIFF

=STANDARD

* N

=STANDARD

=STANDARD=STANDARD

Y*

27P4_OHM_SE

=STANDARD

0.215 MM 0.215 MM

Y

27P4_OHM_SE

TOP,BOTTOM

0.215 MM 0.200 MM

0.210 MM

TOP,BOTTOM

Y

55_OHM_SE

0.200 MM

0.075 MM0.075 MM

ISL2,ISL13

=STANDARD

55_OHM_SE =STANDARD

=STANDARD

Y

0.066 MM0.066 MM

Y

=STANDARD

=STANDARD55_OHM_SE

*

=STANDARD

Y

50_OHM_SE

TOP,BOTTOM

0.250 MM 0.200 MM

=STANDARD

=STANDARD=STANDARD

Y

50_OHM_SE

ISL2,ISL13

0.085 MM 0.085 MM

=STANDARD

0.066 MM0.066 MM

=STANDARD

Y*

50_OHM_SE

=DEFAULT

Y

12.7 MM

=DEFAULT

*

=DEFAULT

STANDARD

0.200 MM

30 MM

0 MM

Y*

=50_OHM_SE

DEFAULT

0 MM

M96 RULE DEFINITIONS

SYNC_DATE=02/04/2008

SYNC_MASTER=M97

051-7631

2.3.0

7171

0.122 MM0.122 MM

ISL2,ISL13

=STANDARD

Y

40_OHM_SE

=STANDARD

0.110 MM0.110 MM

=STANDARD

*

40_OHM_SE

Y

=STANDARD

=STANDARD=STANDARD

=STANDARD

*

=STANDARD

N

=STANDARD

100_OHM_DIFF

=STANDARD=STANDARD

Y

=STANDARD

0.1 MM 0.1 MM

*

1:1_DIFFPAIR

0.066 MM0.122 MM

ISL2,ISL13

40_OHM_SE_MEM

Y

=STANDARD

170 MM

=STANDARD

Y

100_OHM_DIFF_HDD

TOP,BOTTOM

0.179 MM 0.179 MM

0.200 MM 0.200 MM

0.065 MM

0.280 MM

ISL2,ISL4,ISL5,ISL10,ISL11,ISL13

Y

0.280 MM

0.065 MM

100_OHM_DIFF

Y

TOP,BOTTOM

100_OHM_DIFF

0.179 MM 0.179 MM

0.200 MM 0.200 MM

=STANDARD

N

100_OHM_DIFF_HDD

=STANDARD

*

0.065 MM

0.280 MM0.280 MM

ISL2,ISL4,ISL5,ISL10,ISL11,ISL13100_OHM_DIFF_HDD

Y

0.065 MM

0.066 MM

40_OHM_SE_MEM

Y

0.110 MM

=STANDARD

*

=STANDARD

170 MM

0.110 MM0.170 MM

Y

TOP,BOTTOM

40_OHM_SE_MEM

10 MM

0.350 MM

Y

40_OHM_SE

TOP,BOTTOM

0.200 MM

PP1V5_MEM

?

*

=STANDARD

=STANDARDGND

*

?

4X_DIELECTRIC

ISL2,ISL13

0.220 MM

5X_DIELECTRIC

?

ISL2,ISL13

0.275 MM

?

3X_DIELECTRIC

ISL2,ISL13

0.165 MM

?

ISL2,ISL13

0.110 MM

2X_DIELECTRIC

FSB_DSTBFSB_DSTB BGA_P1MM BGA_P3MM

CLK_PCI

*

BGA_P2MMBGA_P1MM

CLK_PCIE

*

BGA_P1MM BGA_P2MM

BGA_P1MM

CLK_FSB

*

BGA_P2MM

*

CLK_SLOW BGA_P1MM

*

?

2X_DIELECTRIC

0.120 MM

1000

GND_P2MM

0.2 MM

*

0.2 MM

1000

PWR_P2MM

*

?

4X_DIELECTRIC

0.240 MM

MCP_STATIC

?

=STANDARD

*

?

5X_DIELECTRIC

0.300 MM

?

*

3X_DIELECTRIC

0.180 MM

2.28:1_SPACING

?

*

0.228 MM

?

TOP,BOTTOM

0.230 MM

2X_DIELECTRIC

MEM_50S

STANDARDBGA_P1MM

DEFAULT

?

0.1 MM

*

=DEFAULT

?*

STANDARD

?*

0.2 MM

2:1_SPACING

*

2.5:1_SPACING

?

0.25 MM

=DEFAULT

* ?

BGA_P1MM

?*

BGA_P2MM =DEFAULT

?

0.15 MM

*

1.5:1_SPACING

BGA_P3MM

?

=DEFAULT

*

4:1_SPACING

?

0.4 MM

*

3:1_SPACING

?

0.3 MM

*

4:1_SPACING

?

0.4 MM

*

BGA_P1MM

*

BGA_P2MM

CLK_LPC

MEM_CLK

BGA_P1MM BGA_P2MM

*

BGA_P1MMBGA_P1MM

**

0.110 MM

?

*

1.1:1_SPACING

TOP,BOTTOM

?

0.345 MM

3X_DIELECTRIC

TOP,BOTTOM

4X_DIELECTRIC

?

0.460 MM

TOP,BOTTOM

5X_DIELECTRIC

?

0.575 MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,ISL12,ISL13,BOTTOM

NO_TYPE,BGA_P1MM

MM

15.2

Apple A1304 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual