The Harris CD74HC138, CD74HC238 and CD74HCT138,
CD74HCT238 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic. Both circuits
have three binary select inputs(A0, A1 and A2). If the device
is enabled, these inputs determine which one of the eight
normally high outputs of the HC/HCT138 series will go low
or which of the normally low outputs of the HC/HCT238
series will go high.
Two active low and one active high enables (
E1, E2, and E3)
are provided to ease the cascading of decoders. The
decoder’s 8 outputs can drive 10 low power Schottky TTL
equivalent loads.
Ordering Information
PKG.
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC138E-55 to 12516 Ld PDIPE16.3
NO.
Ordering Information
PKG.
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HCT138E-55 to 12516 Ld PDIPE16.3
CD74HC238E-55 to 12516 Ld PDIPE16.3
CD74HCT238E-55 to 12516 Ld PDIPE16.3
CD74HC138M-55 to 12516 Ld SOICM16.15
CD74HCT138M-55 to 12516 Ld SOICM16.15
CD74HC238M-55 to 12516 Ld SOICM16.15
CD74HCT238M-55 to 12516 Ld SOICM16.15
CD74HC138SM-55 to 12516 Ld SSOP M16.209
NOTES:
1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
= 6ns
t
PLH
t
f
1.3V
10%
t
90%
TLH
tr = 6ns
INPUT
t
INVERTING
OUTPUT
THL
t
2.7V
1.3V
0.3V
PHL
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
3V
GND
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CERT AIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1999, Texas Instruments Incorporated
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