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CD74HCT175M
Datasheet
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Texas Instruments CD74HCT175M96, CD74HCT175M, CD74HCT175E, CD74HC175M96, CD74HC175M Datasheet

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CD74HC175,
/ j
[ /Title (CD74 HC175 , CD74 HCT17
5) Sub­ect
(High Speed CMOS Logic Quad D­Type Flip-
Data sheet acquired from Harris Semiconductor SCHS160
August 1997
Features
• Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
• Positive Edge Pulse Triggering
• Complementary Outputs
• Typical f T
= 25oC
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 50MHz at VCC = 5V, CL = 15pF,
MAX
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
o
C to 125oC
CC
OH
CD74HCT175
High Speed CMOS Logic
Quad D-Type Flip-Flop with Reset
Description
The Harris CD74HC175 and CD74HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.
Information at the D input is transferred to the Q, the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (
MR). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four
Q outputs to a logic 1.
Ordering Information
TEMP.RANGE
PART NUMBER
CD74HC175E -55 to 125 16 Ld PDIP E16.3
CD74HCT175E -55 to 125 16 Ld PDIP E16.3
CD74HC175M -55 to 125 16 Ld SOIC M16.15
CD74HCT175M -55 to 125 16 Ld SOIC M16.15
CD74HCT175W -55 to 125 Wafer NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
(oC) PACKAGE
Q outputs on
PKG.
NO.
Q
Pinout
CD74HC175, CD74HCT175
(PDIP, SOIC)
TOP VIEW
V
MR
1 2
Q
0
Q
3
0
D
4
0
D
5
1
Q
6
1
Q
7
1
GND
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
1
16
CC
Q
15
3
Q
14
3
D
13
3
D
12
2
Q
11
2
Q
10
2
9
CP
File Number 1474.1
Functional Diagram
CD74HC175, CD74HCT175
D CP
MR
D
D
D
4
0
9 1
5
1
12
2
13
3
D CP R
D CP R
D CP R
D CP R
2
Q
Q
0
3
Q
Q
0
7
Q
Q
1
6
Q
Q
1
10
Q
Q
2
11
Q
Q
2
15
Q
Q
3
14
Q
Q
3
TRUTH TABLE
INPUTS OUTPUTS
RESET (MR) CLOCK CP DATA D
n
Q
n
Q
n
LXXLH
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,↑ = Transition from Low to High Level, Q0= Level Before the Indicated Steady-State Input Conditions Were Established.
Logic Diagram
4 (5, 12, 13) D
D
n
1
MR
9
CP
H ↑ HHL H ↑ LLH HLXQ
C
L
p n
C
C
L
R
L
p n
C
L
CP
C
L
p n
C
L
C
L
0
ONE OF FOUR F/F
C
L
p n
C
L
C
L
TO OTHER THREE F/F
TO OTHER THREE F/F
Q
0
3( 6, 11, 14)
2( 7, 10, 15)
816
V
GND
CC
Q
n
Q
n
2
CD74HC175, CD74HCT175
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
25oC -40oC TO +85oC -55oC TO 125oC
VCC (V)
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V
VIH or
V
-0.02 2 1.9 - - 1.9 - 1.9 - V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIH or
V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1 µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
3
CD74HC175, CD74HCT175
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
HCT TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4)
NOTES:
4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
5. Die for this part number is available which meets all electrical specifications.
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
∆I
CC
- - 4.5 to
- - 4.5 to
VIH or
V
VIH or
V
VCC to
GND
VCC or
GND
V
CC
-2.1
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
IL
IL
VCC (V)
5.5
5.5
-4 4.5 3.98 - - 3.84 - 3.7 - V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V
0 5.5 - - ±0.1 - ±1-±1 µA
0 5.5 - - 8 - 80 - 160 µA
- 4.5 to
5.5
25oC -40oC TO +85oC -55oC TO 125oC
2-- 2 - 2 - V
- - 0.8 - 0.8 - 0.8 V
- 100 360 - 450 - 490 µA
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
MR 1 CP 0.60
D 0.15
NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Specifications
TEST
PARAMETER SYMBOL
HC TYPES
Clock Pulse Width t
MR Pulse Width t
CONDITIONS
w
w
V
CC
(V)
- 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns
- 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
4
CD74HC175, CD74HCT175
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOL
Setup Time, Data to Clock t
Hold Time, Data to Clock t
Removal Time, MR to Clock t
Clock Frequency f
HCT TYPES
Clock Pulse Width t MR Pulse Width t Setup Time Data to Clock t Hold Time Data to Clock t Removal Time MR to Clock t Clock Frequency f
SU
H
REM
MAX
w w
SU
H REM MAX
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
- 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns
-25--5-5-ns
4.5 5 - - 5 - 5 - ns 65--5-5-ns
-25--5-5-ns
4.5 5 - - 5 - 5 - ns 65--5-5-ns
- 2 6 - - 5 - 4 - MHz
4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz
- 4.5 20 - - 25 - 30 - ns
- 4.5 20 - - 25 - 30 - ns
- 4.5 20 - - 25 - 30 - ns
- 4.5 5 - - 5 - 5 - ns
- 4.5 5 - - 5 - 5 - ns
- 4.5 25 - - 20 - 16 - MHz
UNITSMIN TYP MAX MIN MAX MIN MAX
Switching Specifications Input t
PARAMETER SYMBOL
HC TYPES
PropagationDelay, Clockto Q or Q
Propagation Delay, MR to Q or Q
Output Transition Times t
Input Capacitance C Power Dissipation
Capacitance (Notes 6, 7)
t
PLH
t
PLH
TLH
, t
PHLCL
, t
PHLCL
, t
THLCL
IN
C
PD
, tf = 6ns
r
-55oC TO
TEST
25oC -40oC TO 85oC
125oC
CONDITIONS VCC (V)
= 50pF 2 - 175 220 265 ns
4.5 - 35 44 53 ns 6 - 30 37 45 ns
CL= 15pF 5 14 - - - ns
= 50pF 2 - 175 220 265 ns
4.5 - 35 44 53 ns 6 - 30 37 45 ns
CL= 15pF 5 14 - - - ns
= 50pF 2 - 75 95 110 ns
4.5 - 15 19 22 ns 6 - 13 16 19 ns
---1010 10pF
- 5 65 - - - pF
UNITSTYP MAX MAX MAX
5
CD74HC175, CD74HCT175
Switching Specifications Input t
, tf = 6ns (Continued)
r
TEST
PARAMETER SYMBOL
CONDITIONS VCC (V)
HCT TYPES
Propagation Delay, Clock to Q or Q
Propagation Delay, MR to Q or Q
Output Transition Times t Input Capacitance C Power Dissipation
t
PLH
t
PLH
TLH
, t
PHLCL
, t
PHLCL
, t
THLCL
IN
C
PD
= 50pF 4.5 - 33 41 50 ns
CL= 15pF 5 13 - - - ns
= 50pF 4.5 - 35 44 53 ns
CL= 15pF 5 17 - - - ns
= 50pF 4.5 - 15 19 22 ns
---1010 10pF
- 5 67 - - - pF Capacitance (Notes 6, 7)
NOTES:
6. CPD is used to determine the dynamic power consumption, per flip-flop.
7. PD=V
CC
2
fi+∑ (CLV
2
+fO)where fi=Input Frequency, fO=Input Frequency, CL=Output Load Capacitance, VCC=Supply Voltage.
CC
Test Circuits and Waveforms
25oC -40oC TO 85oC
-55oC TO 125oC
UNITSTYP MAX MAX MAX
90%
t
PLH
IC
t
TLH
tfC
L
50%
t
H(L)
t
SU(L)
t
THL
90%
50%
10%
t
PHL
C
L
50pF
V
CC
GND
V
CC
50% GND
GND
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
OUTPUT
t
REM
V
CC
SET, RESET OR PRESET
trC
L
90%
10%
t
H(H)
50%
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
OUTPUT
t
REM
3V SET, RESET OR PRESET
trC
L
2.7V
0.3V
t
H(H)
1.3V
1.3V
1.3V
90%
t
PLH
IC
1.3V
t
TLH
tfC
L
1.3V
t
H(L)
1.3V
t
SU(L)
t
THL
90%
1.3V 10%
t
PHL
C
L
50pF
3V
GND
3V
GND
GND
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,
AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
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