INTEGRATED CIRCUITS
DATA SHEET
PCF8566
Universal LCD driver for low multiplex rates
Product specification |
1998 May 04 |
Supersedes data of 1997 Apr 02
File under Integrated Circuits, IC12
Philips Semiconductors Product specification
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Universal LCD driver for low multiplex |
PCF8566 |
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CONTENTS |
8 |
LIMITING VALUES |
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1 |
FEATURES |
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HANDLING |
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DC CHARACTERISTICS |
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GENERAL DESCRIPTION |
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AC CHARACTERISTICS |
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ORDERING INFORMATION |
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APPLICATION INFORMATION |
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BLOCK DIAGRAM |
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CHIP DIMENSIONS AND BONDING PAD |
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PINNING |
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LOCATIONS |
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FUNCTIONAL DESCRIPTION |
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PACKAGE OUTLINES |
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6.1Power-on reset
6.2LCD bias generator
6.3LCD voltage selector
6.4LCD drive mode waveforms
6.5Oscillator
6.6Internal clock
6.7External clock
6.8Timing
6.9Display latch
6.10Shift register
6.11Segment outputs
6.12Backplane outputs
6.13Display RAM
6.14Data pointer
6.15Subaddress counter
6.16Output bank selector
6.17Input bank selector
6.18Blinker
15 SOLDERING
15.1Introduction
15.2DIP
15.2.1Soldering by dipping or by wave
15.2.2Repairing soldered joints
15.3SO and VSO
15.3.1Reflow soldering
15.3.2Wave soldering
15.3.3Repairing soldered joints
16DEFINITIONS
17LIFE SUPPORT APPLICATIONS
18PURCHASE OF PHILIPS I2C COMPONENTS
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I2C-BUS DESCRIPTION |
7.1Bit transfer
7.2Start and stop conditions
7.3System configuration
7.4Acknowledge
7.5PCF8566 I2C-bus controller
7.6Input filters
7.7I2C-bus protocol
7.8Command decoder
7.9Display controller
7.10Cascaded operation
1998 May 04 |
2 |
Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex
PCF8566
rates
1 FEATURES
·Single-chip LCD controller/driver
·Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing
·Selectable display bias configuration: static, 1¤2 or 1¤3
·Internal LCD bias generation with voltage-follower buffers
·24 segment drives: up to twelve 8-segment numeric characters; up to six 15-segment alphanumeric characters; or any graphics of up to 96 elements
·24 ´ 4-bit RAM for display data storage
·Auto-incremented display data loading across device subaddress boundaries
·Display memory bank switching in static and duplex drive modes
·Versatile blinking modes
·LCD and logic supplies may be separated
·2.5 to 6 V power supply range
·Low power consumption
·Power saving mode for extremely low power consumption in battery-operated and telephone applications
·I2C-bus interface
·TTL/CMOS compatible
·Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers
·May be cascaded for large LCD applications (up to 1536 segments possible)
·Cascadable with the 40 segment LCD driver PCF8576C
·Optimized pinning for single plane wiring in both single and multiple PCF8566 applications
·Space-saving 40 lead plastic very small outline package (VSO40; SOT158-1)
·No external components required (even in multiple device applications)
·Manufactured in silicon gate CMOS process.
2 GENERAL DESCRIPTION
The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) having low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 24 segments and can easily be cascaded for larger LCD applications. The PCF8566 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes).
3 ORDERING INFORMATION
TYPE NUMBER |
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PACKAGE |
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VERSION |
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PCF8566P |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
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PCF8566T |
VSO40 |
plastic very small outline package; 40 leads |
SOT158-1 |
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1998 May 04 |
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04 May 1998 |
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pagewidth full andbook, |
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DIAGRAMBLOCK 4 |
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BP0 BP2 BP1 BP3 |
S0 to S23 |
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VDD |
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BACKPLANE |
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DISPLAY SEGMENT OUTPUTS |
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OUTPUTS |
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R |
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LCD |
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DISPLAY LATCH |
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R |
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VOLTAGE |
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SELECTOR |
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LCD BIAS |
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SHIFT REGISTER |
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GENERATOR |
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VLCD |
12 |
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4 |
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PCF8566 |
INPUT |
DISPLAY |
OUTPUT |
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CLK |
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TIMING |
BLINKER |
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SYNC |
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BANK |
RAM |
BANK |
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SELECTOR |
24 × 4 BITS |
SELECTOR |
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DISPLAY |
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CONTROLLER |
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OSC |
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OSCILLATOR |
POWER- |
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DATA |
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ON |
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POINTER |
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RESET |
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VSS |
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COMMAND |
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DECODER |
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SCL |
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INPUT |
I2 C-BUS |
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SUB- |
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1 |
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ADDRESS |
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SDA |
FILTERS |
CONTROLLER |
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COUNTER |
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SA0 |
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A0 |
A1 |
A2 |
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MGG383 |
Fig.1 Block diagram.
multiplex low for driver LCD Universal rates
PCF8566
Semiconductors Philips
specification Product
Philips Semiconductors |
Product specification |
|
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Universal LCD driver for low multiplex
PCF8566
rates
5 PINNING
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SYMBOL |
PIN |
DESCRIPTION |
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SDA |
1 |
I2C-bus data input/output |
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SCL |
2 |
I2C-bus clock input/output |
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3 |
cascade synchronization |
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SYNC |
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input/output |
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CLK |
4 |
external clock input/output |
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VDD |
5 |
positive supply voltage |
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OSC |
6 |
oscillator input |
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A0 |
7 |
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I2C-bus subaddress inputs |
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A1 |
8 |
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A2 |
9 |
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SA0 |
10 |
I2C-bus slave address bit 0 input |
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VSS |
11 |
logic ground |
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VLCD |
12 |
LCD supply voltage |
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BP0 |
13 |
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BP2 |
14 |
LCD backplane outputs |
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BP1 |
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BP3 |
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S0 to S23 |
17 to 40 |
LCD segment outputs |
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handbook, halfpage
SDA |
1 |
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40 |
S23 |
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SCL |
2 |
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S22 |
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SYNC |
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S21 |
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CLK |
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S20 |
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VDD |
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S19 |
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OSC |
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S18 |
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A0 |
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S17 |
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A1 |
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33 |
S16 |
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A2 |
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32 |
S15 |
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SA0 |
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S14 |
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VSS |
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PCF8566 |
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S13 |
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VLCD |
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12 |
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S12 |
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BP0 |
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S11 |
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BP2 |
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S10 |
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BP1 |
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S9 |
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BP3 |
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S8 |
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S0 |
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24 |
S7 |
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S1 |
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S6 |
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S2 |
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S5 |
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S3 |
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S4 |
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MGG382 |
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Fig.2 Pin configuration.
1998 May 04 |
5 |
Philips Semiconductors |
Product specification |
|
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Universal LCD driver for low multiplex
PCF8566
rates
6 FUNCTIONAL DESCRIPTION
The PCF8566 is a versatile peripheral device designed to interface any microprocessor to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to 4 backplanes and up to 24 segments. The display configurations possible with the PCF8566 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1.
All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.3.
The host microprocessor/microcontroller maintains the two-line I2C-bus communication channel with the PCF8566. The internal oscillator is selected by tying OSC (pin 6) to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the
system are to the power supplies (VDD, VSS and VLCD) and to the LCD panel chosen for the application.
Table 1 Selection of display configurations
ACTIVE |
NUMBER OF |
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14-SEGMENT |
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BACKPLANE |
7-SEGMENT NUMERIC |
DOT MATRIX |
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SEGMENTS |
ALPHANUMERIC |
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OUTPUTS |
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4 |
96 |
12 digits + 12 indicator |
6 characters + 12 indicator |
96 dots (4 × 24) |
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symbols |
symbols |
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3 |
72 |
9 digits + 9 indicator |
4 characters + 16 indicator |
72 dots (3 × 24) |
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symbols |
symbols |
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2 |
48 |
6 digits + 6 indicator |
3 characters + 6 indicator |
48 dots (2 × 24) |
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symbols |
symbols |
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1 |
24 |
3 digits + 3 indicator |
1 character + 10 indicator |
24 dots |
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symbols |
symbols |
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handbook, full pagewidth VDD
R ≤ |
trise |
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2 Cbus |
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VDD |
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VLCD |
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SDA |
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1 |
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17 to 40 |
24 segment drives |
LCD PANEL |
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MICRO- |
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SCL |
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PCF8566 |
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PROCESSOR/ |
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MICRO- |
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OSC |
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elements) |
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CONTROLLER |
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6 |
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13 to 16 |
4 backplanes |
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A0 |
A1 |
A2 |
SA0 VSS |
MGG385 |
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VSS
Fig.3 Typical system configuration.
1998 May 04 |
6 |
Philips Semiconductors |
Product specification |
|
|
Universal LCD driver for low multiplex
PCF8566
rates
6.1Power-on reset
At power-on the PCF8566 resets to a defined starting condition as follows:
1.All backplane outputs are set to VDD
2.All segment outputs are set to VDD
3.The drive mode ‘1 : 4 multiplex with 1¤3bias’ is selected
4.Blinking is switched off
5.Input and output bank selectors are reset (as defined in Table 5)
6.The I2C-bus interface is initialized
7.The data pointer and the subaddress counter are cleared.
Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action.
6.2LCD bias generator
The full-scale LCD voltage (Vop) is obtained from
VDD - VLCD. The LCD voltage may be temperature compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected
between VDD and VLCD. The centre resistor can be switched out of circuit to provide a 1¤2bias voltage level for
the 1 : 2 multiplex configuration.
6.3LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD according to the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing
characteristics as functions of Vop = VDD - VLCD and the resulting discrimination ratios (D), are given in Table 2.
A practical value of Vop is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is Vop ³ 3 Vth. Multiplex drive
ratios of 1 : 3 and 1 : 4 with 1¤2 bias are possible but the discrimination and hence the contrast ratios are smaller
( 3 = 1.732 for 1 : 3 multiplex or 21 ¤ 3 = 1.528 for 1 : 4 multiplex). The advantage of these modes is a reduction of the LCD full scale voltage Vop as follows:
1 : 3 multiplex (1¤2bias):
Vop = 6Vop(mrs) = 2.449Voff ( rms)
1 : 4 multiplex (1¤2bias):
Vop = 4 3 ¤ 3Voff ( rms) = 2.309Voff ( rms)
These compare with Vop = 3 Voff(rms) when 1¤3bias is used.
Table 2 Preferred LCD drive modes: summary of characteristics
LCD DRIVE MODE |
LCD BIAS |
Voff ( rms) |
Von ( rms) |
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Von ( rms) |
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CONFIGURATION |
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D = ----------------------- |
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Vop |
Vop |
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Voff ( rms) |
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Static (1 BP) |
static (2 levels) |
0 |
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¥ |
1 : 2 MUX (2 BP) |
1¤2 (3 levels) |
2 ¤ 4 = 0.354 |
10 ¤ 4 |
= 0.791 |
5 |
= 2.236 |
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1 : 2 MUX (2 BP) |
1¤3 (4 levels) |
1¤3 = 0.333 |
5 ¤ 3 |
= 0.745 |
5 |
= 2.236 |
1 : 3 MUX (3 BP) |
1¤3 (4 levels) |
1¤3 = 0.333 |
33 ¤ 9 |
= 0.638 |
33 ¤ 3 = 1.915 |
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1 : 4 MUX (4 BP) |
1¤3 (4 levels) |
1¤3 = 0.333 |
3 ¤ 3 |
= 0.577 |
3 |
= 1.732 |
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1998 May 04 |
7 |
Philips Semiconductors |
Product specification |
|
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Universal LCD driver for low multiplex
PCF8566
rates
6.4LCD drive mode waveforms
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.4.
When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The PCF8566 allows use of 1¤2 or 1¤3 bias in this mode as shown in Figs 5 and 6.
The backplane and segment drive waveforms for the 1 : 3 multiplex drive mode (three LCD backplanes) and for the 1 : 4 multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively.
handbook, full pagewidth |
Tframe |
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VDD |
LCD segments |
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BP0 |
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VLCD |
state 1 |
state 2 |
VDD |
(on) |
(off) |
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Sn |
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VLCD |
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VDD |
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Sn + 1 |
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VLCD |
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(a) waveforms at driver |
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Vop |
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Vstate 1(t) = VSn(t) − VBP0(t) |
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Von(rms) = Vop |
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Vop |
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Vstate 2(t) = VSn + 1(t) − VBP0(t) |
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state 2 |
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Voff(rms) = 0 V |
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at LCD segment |
MGG392 |
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Fig.4 Static drive mode waveforms: Vop = VDD - VLCD.
1998 May 04 |
8 |
Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex
PCF8566
rates
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VDD |
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Tframe |
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BP0 |
(VDD + VLCD)/2 |
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VLCD |
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VDD |
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BP1 |
(VDD + VLCD)/2 |
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VLCD |
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Sn |
VDD |
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VLCD |
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Sn + 1 |
VDD |
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VLCD |
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(a) waveforms at driver |
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Vop |
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Vop/2 |
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state 1 |
0 |
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-Vop |
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Vop |
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state 2 |
0 |
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-Vop/2 |
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-Vop |
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(b) resultant waveforms |
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at LCD segment |
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LCD segments
state 1
state 2
At any instant (t):
Vstate 1(t) = VSn(t) - VBP0(t)
Von(rms) = VopÖ10 = 0.791Vop 4
Vstate 2(t) = VSn(t) - VBP1(t)
Voff(rms) = VopÖ2 = 0.354Vop
4
MGG394
Fig.5 Waveforms for 1 : 2 multiplex drive mode with 1¤2 bias: Vop = VDD - VLCD.
1998 May 04 |
9 |
Philips Semiconductors |
Product specification |
|
|
Universal LCD driver for low multiplex
PCF8566
rates
handbook, full pagewidth
BP0
BP1
Sn
Sn + 1
state 1
state 2
Tframe
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3 VLCD
(a) waveforms at driver
Vop
2Vop/3 Vop/3 0
-Vop/3 -2Vop/3 -Vop
Vop
2Vop/3 Vop/3 0
-Vop/3 -2Vop/3
-Vop
(b) resultant waveforms at LCD segment
LCD segments
state 1 state 2
At any instant (t):
Vstate 1(t) = VSn(t) - VBP0(t)
Von(rms) = VopÖ5 = 0.745Vop 3
Vstate 2(t) = VSn(t) - VBP1(t)
Voff(rms) = Vop = 0.333Vop
3
MGG393
Fig.6 Waveforms for 1 : 2 multiplex drive mode with 1¤3 bias: Vop = VDD - VLCD.
1998 May 04 |
10 |
Philips Semiconductors |
Product specification |
|
|
Universal LCD driver for low multiplex
PCF8566
rates
BP0
BP1
BP2
Sn
Sn + 1
Sn + 2
Tframe
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
(a) waveforms at driver
LCD segments
state 1 |
state 2 |
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Vop |
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2Vop/3 |
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Vop/3 |
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state 1 |
0 |
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At any instant (t): |
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-Vop/3 |
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Vstate 1(t) = VSn(t) - VBP0(t) |
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-2Vop/3 |
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-Vop |
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Von(rms) = |
Vop |
Ö33 = 0.638Vop |
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Vop |
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9 |
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Vstate 2(t) = VSn(t) - VBP1(t) |
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Voff(rms) = |
Vop |
= 0.333Vop |
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state 2 |
0 |
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-Vop |
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(b) resultant waveforms |
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MGG395 |
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at LCD segment |
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Fig.7 Waveforms for 1 : 3 multiplex drive mode: Vop = VDD − VLCD.
1998 May 04 |
11 |
Philips Semiconductors |
Product specification |
|
|
Universal LCD driver for low multiplex
PCF8566
rates
handbook, full pagewidth
BP0
BP1
BP2
BP3
Sn
Sn + 1
Sn + 2
Sn + 3
state 1
state 2
Tframe
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
VDD
VDD - Vop/3
VDD - 2Vop/3
VLCD
(a) waveforms at driver
Vop 2Vop/3 Vop/3
0 -Vop/3
-2Vop/3 -Vop
Vop
2Vop/3 Vop/3 0
-Vop/3 -2Vop/3
-Vop (b) resultant waveforms at LCD segment
LCD segments
state 1 |
state 2 |
At any instant (t):
Vstate 1(t) = VSn(t) - VBP0(t)
Von(rms) = VopÖ3 = 0.577Vop 3
Vstate 2(t) = VSn(t) - VBP1(t)
Voff(rms) = Vop = 0.333Vop
3
MGG396
Fig.8 Waveforms for 1 : 4 multiplex drive mode: Vop = VDD − VLCD.
1998 May 04 |
12 |
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