October 1991
TP3064, TP3067 ``Enhanced'' Serial Interface
CMOS CODEC/Filter COMBOÉ
General Description
The TP3064 (m-law) and TP3067 (A-law) are monolithic PCM CODEC/Filters utilizing the A/D and D/A conversion architecture shown in Figure 1 , and a serial PCM interface. The devices are fabricated using National's advanced dou- ble-poly CMOS process (microCMOS).
Similar to the TP305X family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The receive gain can be adjusted by means of two external resistors for an output level of up to g6.6V across a balanced 600X load.
Also included is an Analog Loopback switch and a TSX output.
See also AN-370, ``Techniques for Designing with CODEC/ Filter COMBO Circuits.''
COMBOÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
Features
YComplete CODEC and filtering system including:
ÐTransmit high-pass and low-pass filtering
ÐReceive low-pass filter with sin x/x correction
ÐActive RC noise filters
Ðm-law or A-law compatible COder and DECoder
ÐInternal precision voltage reference
ÐSerial I/O interface
ÐInternal auto-zero circuitry
ÐReceive push-pull power amplifiers
Ym-lawÐTP3064
YA-lawÐTP3067
YDesigned for D3/D4 and CCITT applications
Yg5V operation
YLow operating powerÐtypically 70 mW
YPower-down standby modeÐtypically 3 mW
YAutomatic power-down
YTTL or CMOS compatible digital interfaces
YMaximizes line interface card circuit density
Block Diagram
TL/H/5070 ± 1
FIGURE 1
COMBO CODEC/Filter CMOS Interface Serial ``Enhanced'' TP3067 TP3064,
C1995 National Semiconductor Corporation |
TL/H/5070 |
RRD-B30M115/Printed in U. S. A. |
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
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TL/H/5070 ± 2 |
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Top View |
Pin Description |
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Symbol |
Function |
VPOa |
The non-inverted output of the receive power |
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amplifier. |
GNDA |
Analog ground. All signals are referenced to |
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this pin. |
VPOb |
The inverted output of the receive power |
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amplifier. |
VPI |
Inverting input to the receive power amplifier. |
VFRO |
Analog output of the receive filter. |
VCC |
Positive power supply pin. VCCea5Vg5%. |
FSR |
Receive frame sync pulse which enables |
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BCLKR to shift PCM data into DR. FSR is an |
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8 kHz pulse train. See Figures 2 and 3 for |
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timing details. |
DR |
Receive data input. PCM data is shifted into |
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DR following the FSR leading edge. |
BCLKR/ |
The bit clock which shifts data into DR after |
CLKSEL |
the FSR leading edge. May vary from 64 kHz |
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to 2.048 MHz. Alternatively, may be a logic |
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input which selects either |
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1.536 MHz/1.544 MHz or 2.048 MHz for |
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master clock in synchronous mode and |
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BCLKX is used for both transmit and receive |
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directions (see Table I). |
MCLKR/ |
Receive master clock. Must be 1.536 MHz, |
PDN |
1.544 MHz or 2.048 MHz. May be |
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asynchronous with MCLKX, but should be |
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synchronous with MCLKX for best |
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performance. When MCLKR is connected |
continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down.
TL/H/5070 ± 6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
Order Number TP3064V or TP3067V
See NS Package V20A
Symbol |
Function |
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MCLKX |
Transmit master clock. Must be 1.536 MHz, |
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1.544 MHz or 2.048 MHz. May be |
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asynchronous with MCLKR. Best |
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performance is realized from synchronous |
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operation. |
BCLKX |
The bit clock which shifts out the PCM data |
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on DX. May vary from 64 kHz to 2.048 MHz, |
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but must be synchronous with MCLKX. |
DX |
The TRI-STATEÉ PCM data output which is |
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enabled by FSX. |
FSX |
Transmit frame sync pulse input which |
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enables BCLKX to shift out the PCM data on |
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DX. FSX is an 8 kHz pulse train, see Figures 2 |
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and 3 for timing details. |
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TSX |
Open drain output which pulses low during |
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the encoder time slot. |
ANLB |
Analog Loopback control input. Must be set |
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to logic `0' for normal operation. When pulled |
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to logic `1', the transmit filter input is |
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disconnected from the output of the transmit |
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preamplifier and connected to the VPOa |
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output of the receive power amplifier. |
GSX |
Analog output of the transmit input amplifier. |
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Used to externally set gain. |
VFXIb |
Inverting input of the transmit input amplifier. |
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VFXIa |
Non-inverting input of the transmit input |
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amplifier. |
VBB |
Negative power supply pin. VBBeb5Vg5%. |
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2
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializes the COMBOTM and places it into a power-down state. All non-essential circuits are deactivated and the DX, VFRO, VPOb and VPOa outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin high; the alternative is to hold both FSX and FSR inputs continuously lowÐthe device will power-down approximately 2 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRI-STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLKR/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BLCKX will be selected as the bit clock for both the transmit and receive directions. Table I indicates the frequencies of operation which can be selected, depending on the state of BCLKR/ CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX.
Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRI-STATE DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R.
TABLE I. Selection of Master Clock Frequencies
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Master Clock |
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BCLKR/CLKSEL |
Frequency Selected |
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TP3067 |
TP3064 |
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Clocked |
2.048 MHz |
1.536 MHz or |
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1.544 MHz |
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0 |
1.536 MHz or |
2.048 MHz |
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1.544 MHz |
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1 |
2.048 MHz |
1.536 MHz or |
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1.544 MHz |
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ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be 2.048 MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the TP3064, and need not be synchronous. For best transmis-
sion performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal MCLKR functions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in Table I are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse (the same as the TP3020/21 CODECs) or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock period long, with timing relationships specified in Figure 2 . With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long (TP5116A/56 CODECs) frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in Figure 3 . Based on the transmit frame sync, FSX, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The DX TRISTATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR(BCLKX in synchronous mode). All devices may utilize the long frame sync pulse in synchronous or asynchronous mode.
TRANSMIT SECTION
The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4 . The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-ca- pacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to m-law (TP3064) or A-law (TP3067) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (see
3
Functional Description (Continued)
table of Transmission Characteristics). The FSX frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through DX at the next FSX pulse. The total encoding delay will be approximately 165 ms (due to the transmit filter) plus 125 ms (due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3067) or m-law (TP3064) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter with its output at VFRO. The receive section is unity-gain, but gain can be added by using the power amplifiers. Upon the occurrence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX) peri-
ods. At the end of the decoder time slot, the decoding cycle begins, and 10 ms later the decoder DAC output is updated. The total decoder delay is E10 ms (decoder update) plus 110 ms (filter delay) plus 62.5 ms ((/2 frame), which gives approximately 180 ms.
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for directly driving a matched line interface transformer. The gain of the first power amplifier can be adjusted to boost the g2.5V peak output signal from the receive filter up to g3.3V peak into an unbalanced 300X load, or g4.0V into an unbalanced 15 kX load. The second power amplifier is internally connected in unity-gain inverting mode to give 6 dB of signal gain for balanced loads.
Maximum power transfer to a 600X subscriber line termination is obtained by differentially driving a balanced trans-
former with a S2:1 turns ratio, as shown in Figure 4 . A total peak power of 15.6 dBm can be delivered to the load plus termination.
ENCODING FORMAT AT DX OUTPUT
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TP3064 |
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TP3067 |
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A-Law |
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m-Law |
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(Includes Even Bit Inversion) |
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VIN e aFull-Scale |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
VIN e 0V |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
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Ð0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
VIN e bFull-Scale |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
4
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
VCC to GNDA |
7V |
VBB to GNDA |
b7V |
Voltage at any Analog Input |
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or Output |
VCCa0.3V to VBBb0.3V |
Voltage at any Digital Input |
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or Output |
VCCa0.3V to GNDAb0.3V |
Operating Temperature Range |
b25§C to a125§C |
Storage Temperature Range |
b65§C to a150§C |
Lead Temp. (Soldering, 10 sec.) |
300§C |
ESD (Human Body Model) J |
1000V |
ESD (Human Body Model) N |
1500V |
Latch-Up Immunity |
100 mA on Any Pin |
Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e a5.0V g5%, VBB e b5.0V g5%; TA e 0§C to 70§C by correlation with 100% electrical testing at TA e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e a5.0V, VBB e b5.0V, TA e 25§C.
Symbol |
Parameter |
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Conditions |
Min |
Typ |
Max |
Units |
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POWER DISSIPATION (ALL DEVICES) |
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ICC0 |
Power-Down Current |
(Note) |
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0.5 |
1.5 |
mA |
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IBB0 |
Power-Down Current |
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(Note) |
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0.05 |
0.3 |
mA |
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ICC1 |
Active Current |
VPIe0V; VFRO, VPOa and VPOb unloaded |
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7.0 |
10.0 |
mA |
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IBB1 |
Active Current |
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VPIe0V; VFRO, VPOa and VPOb unloaded |
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7.0 |
10.0 |
mA |
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DIGITAL INTERFACE |
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VIL |
Input Low Voltage |
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0.6 |
V |
VIH |
Input High Voltage |
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2.2 |
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V |
VOL |
Output Low Voltage |
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DX, ILe3.2 mA |
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0.4 |
V |
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TSX |
, ILe3.2 mA, Open Drain |
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0.4 |
V |
VOH |
Output High Voltage |
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DX, IHeb3.2 mA |
2.4 |
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V |
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IIL |
Input Low Current |
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GNDAsVINsVIL, All Digital Inputs |
b10 |
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10 |
mA |
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IIH |
Input High Current |
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VIHsVINsVCC |
b10 |
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10 |
mA |
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IOZ |
Output Current in High Impedance |
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DX, GNDAsVOsVCC |
b10 |
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10 |
mA |
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State (TRI-STATE) |
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Note: ICC0 and IBB0 are measured after first achieving a power-up state.
5
Electrical Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e a5.0Vg5%, VBB e b5.0Vg5%; TA e 0§C to 70§C by correlation with 100% electrical testing at TA e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e a5.0V, VBB e b5.0V, TA e 25§C.
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) |
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IIXA |
Input Leakage Current |
b2.5VsVsa2.5V, VFXIa or VFXIb |
b200 |
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200 |
nA |
RIXA |
Input Resistance |
b2.5VsVsa2.5V, VFXIa or VFXIb |
10 |
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MX |
ROXA |
Output Resistance |
Closed Loop, Unity Gain |
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1 |
3 |
X |
RLXA |
Load Resistance |
GSX |
10 |
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kX |
CLXA |
Load Capacitance |
GSX |
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50 |
pF |
VOXA |
Output Dynamic Range |
GSX, RLt10 kX |
b2.8 |
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a2.8 |
V |
AVXA |
Voltage Gain |
VFXIa to GSX |
5000 |
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V/V |
FUXA |
Unity-Gain Bandwidth |
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1 |
2 |
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MHz |
VOSXA |
Offset Voltage |
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b20 |
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20 |
mV |
VCMXA |
Common-Mode Voltage |
CMRRXA l 60 dB |
b2.5 |
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2.5 |
V |
CMRRXA |
Common-Mode Rejection Ratio |
DC Test |
60 |
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dB |
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PSRRXA |
Power Supply Rejection Ratio |
DC Test |
60 |
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dB |
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ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) |
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RORF |
Output Resistance |
Pin VFRO |
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1 |
3 |
X |
RLRF |
Load Resistance |
VFROeg2.5V |
10 |
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kX |
CLRF |
Load Capacitance |
Connect from VFRO to GNDA |
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25 |
pF |
VOSRO |
Output DC Offset Voltage |
Measure from VFRO to GNDA |
b200 |
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200 |
mV |
ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES) |
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IPI |
Input Leakage Current |
b1.0VsVPIs1.0V |
b100 |
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100 |
nA |
RIPI |
Input Resistance |
b1.0VsVPIs1.0V |
10 |
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MX |
VIOS |
Input Offset Voltage |
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b25 |
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25 |
mV |
ROP |
Output Resistance |
Inverting Unity-Gain at |
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1 |
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X |
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VPOa or VPOb |
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FC |
Unity-Gain Bandwidth |
Open Loop (VPOb) |
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400 |
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kHz |
CLP |
Load Capacitance |
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100 |
pF |
GAPa |
Gain from VPOb to VPOa |
RLe600X VPOa to VPOb |
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b1 |
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V/V |
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Level at VPObe1.77 Vrms |
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PSRRP |
Power Supply Rejection of |
VPOb Connected to VPI |
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VCC or VBB |
0 kHzb4 kHz |
60 |
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dB |
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4 kHzb50 kHz |
36 |
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dB |
RLP |
Load Resistance |
Connect from VPOa to VPOb |
600 |
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X |
6
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