National Semiconductor MM54HC155, MM74HC155 Service Manual

January 1988

MM54HC155/MM74HC155 Dual 2-To-4

Line Decoder/Demultiplexers

General Description

The MM54HC155/MM74HC155 is a high speed silicon-gate CMOS decoder/demultiplexer. It utilizes advanced silicongate CMOS technology and features dual 1-line-to-4-line demultiplexers with independent strobes and common bina- ry-address inputs. When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied to C2 is non-inverted at its outputs. The inverter following the C1 data input permits use as a 3-to-8-line decoder, or 1-to-8- line demultiplexer, without gating.

All inputs to the decoder are protected from damage due to electrostatic discharge by diodes to VCC and Ground.

The device is capable of driving 10 low power Schottky TTL equivalent loads.

The MM54HC155/MM74HC155 is functionally and pin equivalent to the 54LS155/74LS155 with the advantage of reduced power consumption.

Features

Y Applications

Dual 2-to-4-line decoder Dual 1-to-4-line demultiplexer 3-to-8-line decoder 1-to-8-line demultiplexer

YTypical propagation delay: 22 ns

YLow quiescent current: 80 mA maximum (74HC series)

YWide operating range: 2V ± 6V

Connect and Logic Diagram	Truth Tables
						2-to-4-Line Decoder
				or 1-Line to 4-line Demultiplexer
				Inputs					Outputs
	Select			Strobe			Data
	B	A		G1			C1	1Y0	1Y1	1Y2	1Y3
	X	X		H			X	H	H	H	H
	L	L		L			H	L	H	H	H
	L	H		L			H	H	L	H	H
	H	L		L			H	H	H	L	H
	H	H		L			H	H	H	H	L
	X	X		X			L	H	H	H	H
				Inputs					Outputs
	Select			Strobe			Data
	B	A		G2			C2	2Y0	2Y1	2Y2	2Y3
	X	X		H			X	H	H	H	H
	L	L		L			L	L	H	H	H
	L	H		L			L	H	L	H	H
TL/F/8364 ± 1	H	L		L			L	H	H	L	H
Order Number MM54HC155 or	H	H		L			L	H	H	H	L
MM74HC155	X	X		X			H	H	H	H	H
				3-Line-to-8-Line Decoder
				or 1-Line-to-8-Line Demultiplexer
		Inputs						Outputs
	Select		Strobe			(0) (1)		(2) (3)	(4)	(5) (6)	(7)
			Or Data
	IC B A			IG	2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
	X X X		H			H H H H H H H H
	L L L			L		L H H H H H H H
	L L H			L		H L H H H H H H
	L H L			L		H H L H H H H H
	L H H			L		H H H L H H H H
	H L L			L		H H H H L H H H
	H L H			L		H H H H H L H H
	H H L			L		H H H H H H L H
	H H H		L			H H H H H H H L

IC e inputs C1 and C2 connected together

IG e inputs G1 and G2 connected together

H e high level L e low level X e don't care

Decoder/Demultiplexers Line 4-To-2 Dual MM54HC155/MM74HC155

C1995 National Semiconductor Corporation

TL/F/8364

RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 and 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VCC)	b0.5V to a7.0V
DC Input Voltage (VIN)	b1.5V to VCC a1.5V
DC Output Voltage (VOUT)	b0.5 to VCC a0.5V
Clamp Diode Current (IIK, IOK)	20 mA
DC Output Current, per pin (IOUT)	25 mA
DC VCC or GND Current, per Pin (ICC)	50 mA
Storage Temperature Range (TSTG)	b65§C to a150§C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temp. (TI) (Soldering 10 sec)	260§C

DC Electrical Characteristics (Note 4)

Operating Conditions

		Min	Max	Unit
Supply Voltage (VCC)		2	6	V
DC Input or Output Voltage
(VIN, VOUT)		0	VCC	V
Operating Temperature Range (TA)		b40	a85
MM74HC				C
MM54HC		b55	a125	C
Input Rise/Fall Time VCC e 2.0V			1000	ns
(tr, tf)	VCC e 4.5V		500	ns
	VCC e 6.0V		400	ns

						74HC	54HC
Symbol	Parameter	Conditions	VCC	TA e 25§C		TA e b40§ to a85§C	TA e b 55§ to a125§C	Units
				Typ		Guaranteed Limits
VIH	Minimum High Level		2.0V		1.5	1.5	1.5	V
	Input Voltage		4.5V		3.15	3.15	3.15	V
			6.0V		4.2	4.2	4.2	V
VIL	Maximum Low Level		2.0V		0.5	0.5	0.5	V
	Input Voltage**		4.5V		1.35	1.35	1.35	V
			6.0V		1.8	1.8	1.8	V
VOH	Minimum High Level	VIN e VIH or VIL	2.0V	2.0	1.9	1.9	1.9	V
	Output Voltage	lIOUTl s 20 mA	4.5V	4.5	4.4	4.4	4.4	V
			6.0V	6.0	5.9	5.9	5.9	V
		VIN e VIH or VIL	4.5V	4.2	3.98	3.84	3.7	V
		lIOUTl s 4.0 mA	6.0V	5.7	5.48	5.34	5.2	V
		lIOUTl s 5.2 mA
VOL	Maximum Low Level	VIN e VIH or VIL	2.0V	0	0.1	0.1	0.1	V
	Output Voltage	lIOUTl s 20 mA	4.5V	0	0.1	0.1	0.1	V
			6.0V	0	0.1	0.1	0.1	V
		VIN e VIH or VIL	4.5V	0.2	0.26	0.33	0.4	V
		lIOUTl s 4.0 mA	6.0V	0.2	0.26	0.33	0.4	V
		lIOUTl s 5.2 mA
IIN	Maximum Input	VIN e VCC or GND	6.0V		g0.1	g1.0	g1.0	mA
	Current
ICC	Maximum Quiescent	VIN e VCC or GND	6.0V		8.0	80	160	mA
	Supply Current	IOUT e 0 mA

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified, all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating Ð plastic ``N'' package: b12 mW/§C from 65§C to 85§C; ceramic ``J'' package: b12 mW/§C from 100§C to 125§.

Note 4: For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89.

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