National Semiconductor MM54HC390, MM74HC390, MM54HC393, MM74HC393 Service Manual

January 1988

MM54HC390/MM74HC390

Dual 4-Bit Decade Counter

MM54HC393/MM74HC393

Dual 4-Bit Binary Counter

General Description

These counter circuits contain independent ripple carry counters and utilize advanced silicon-gate CMOS technology. The MM54HC390/MM74HC390 incorporate dual decade counters, each composed of a divide-by-two and a di- vide-by-five counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-qui- nary, or various combinations up to a single divide-by-100 counter. The MM54HC393/MM74HC393 contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter.

Each of the two 4-bit counters is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide-by- N counter configurations.

Each of the counters outputs can drive 10 low power Schottky TTL equivalent loads. These counters are func-

tionally as well as pin equivalent to the 54LS390/74LS390 and the 54LS393/74LS393, respectively. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features

YTypical operating frequency: 50 MHz

YTypical propagation delay: 13 ns (Ck to QA)

YWide operating supply voltage range: 2 ± 6V

YLow input current: k1 mA

YLow quiescent supply current: 80 mA maximum (74HC Series)

YFanout of 10 LS-TTL loads

Connection Diagrams

Dual-In-Line Package

Dual-In-Line Package

	TL/F/5337 ± 1
	Top View	TL/F/5337 ± 2
		Top View
	Order Number MM54HC390 or MM74HC390
		Order Number MM54HC393 or MM74HC393

Counter Decade Bit-4 Dual MM54HC390/MM74HC390

Counter Binary Bit-4 Dual MM54HC393/MM74HC393

C1995 National Semiconductor Corporation

TL/F/5337

RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VCC)	b0.5 to a7.0V
DC Input Voltage (VIN)	b1.5 to VCCa1.5V
DC Output Voltage (VOUT)	b0.5 to VCCa0.5V
Clamp Diode Current (IIK, IOK)	g20 mA
DC Output Current, per pin (IOUT)	g25 mA
DC VCC or GND Current, per pin (ICC)	g50 mA
Storage Temperature Range (TSTG)	b65§C to a150§C
Power Dissipation (PD)
(Note 3)	600 mW
S.O. Package only	500 mW
Lead Temp. (TL) (Soldering 10 seconds)	260§C

DC Electrical Characteristics (Note 4)

Operating Conditions

	Min	Max	Units
Supply Voltage (VCC)	2	6	V
DC Input or Output Voltage	0	VCC	V
(VIN, VOUT)
Operating Temp. Range (TA)	b40	a85	§C
MM74HC
MM54HC	b55	a125	§C
Input Rise or Fall Times
(tr, tf) VCCe2.0V		1000	ns
VCCe4.5V		500	ns
VCCe6.0V		400	ns

				TAe25§C		74HC	54HC
Symbol	Parameter	Conditions	VCC			TAeb40 to 85§C	TAeb55 to 125§C	Units
				Typ		Guaranteed Limits
VIH	Minimum High Level		2.0V		1.5	1.5	1.5	V
	Input Voltage		4.5V		3.15	3.15	3.15	V
			6.0V		4.2	4.2	4.2	V
VIL	Maximum Low Level		2.0V		0.5	0.5	0.5	V
	Input Voltage**		4.5V		1.35	1.35	1.35	V
			6.0V		1.8	1.8	1.8	V
VOH	Minimum High Level	VINeVIH or VIL
	Output Voltage	lIOUTls20 mA	2.0V	2.0	1.9	1.9	1.9	V
			4.5V	4.5	4.4	4.4	4.4	V
			6.0V	6.0	5.9	5.9	5.9	V
		VINeVIH or VIL
		lIOUTls4.0 mA	4.5V	4.2	3.98	3.84	3.7	V
		lIOUTls5.2 mA	6.0V	5.7	5.48	5.34	5.2	V
VOL	Maximum Low Level	VINeVIH or VIL
	Output Voltage	lIOUTls20 mA	2.0V	0	0.1	0.1	0.1	V
			4.5V	0	0.1	0.1	0.1	V
			6.0V	0	0.1	0.1	0.1	V
		VINeVIH or VIL
		lIOUTls4.0 mA	4.5V	0.2	0.26	0.33	0.4	V
		lIOUTls5.2 mA	6.0V	0.2	0.26	0.33	0.4	V
IIN	Maximum Input	VINeVCC or GND	6.0V		g0.1	g1.0	g1.0	mA
	Current
ICC	Maximum Quiescent	VINeVCC or GND	6.0V		8.0	80	160	mA
	Supply Current	IOUTe0 mA

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating Ð plastic ``N'' package: b12 mW/§C from 65§C to 85§C; ceramic ``J'' package: b12 mW/§C from 100§C to 125§C.

Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89.

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AC Electrical Characteristics MM54HC390/MM74HC390

VCCe5V, TAe25§C, CLe15 pF, tretfe6 ns

Symbol	Parameter	Conditions	Typ	Guaranteed Limit	Units
fMAX	Maximum Operating Frequency, Clock A or B		50	30	MHz
tPHL, tPLH	Maximum Propagation Delay, Clock A to QA Output		12	20	ns
tPHL, tPLH	Maximum Propagation Delay, Clock A to QC		32	50	ns
	(QA Connected to Clock B)
tPHL, tPLH	Maximum Propagation Delay, Clock B to QB or QD		15	21	ns
tPHL, tPLH	Maximum Propagation Delay, Clock B to QC		20	32	ns
tPHL	Maximum Propagation Delay, Clear to any Output		15	28	ns
tREM	Minimum Removal Time, Clear to Clock		b2	5	ns
tW	Minimum Pulse Width, Clear or Clock		10	16	ns

AC Electrical Characteristics CLe50 pF, tretfe6 ns (unless otherwise specified)

				TAe25§C		74HC	54HC
Symbol	Parameter	Conditions	VCC			TAeb40 to 85§C	TAeb55 to 125§C	Units
				Typ		Guaranteed Limits
fMAX	Maximum Operating		2.0V		5	4	3	MHz
	Frequency		4.5V		27	21	18	MHz
			6.0V		31	24	20	MHz
tPHL, tPLH	Maximum Propagation		2.0V	45	120	150	180	ns
	Delay, Clock A to QA		4.5V	15	24	30	35	ns
			6.0V	13	21	26	31	ns
tPHL, tPLH	Maximum Propagation		2.0V	100	290	360	430	ns
	Delay, Clock A to QC		4.5V	35	58	72	87	ns
	(QA Connected to Clock B)		6.0V	30	50	62	75	ns
tPHL, tPLH	Maximum Propagation		2.0V	50	130	160	195	ns
	Delay, Clock B to QB or		4.5V	16	26	33	39	ns
	QD		6.0V	13	22	28	33	ns
tPHL, tPLH	Maximum Propagation		2.0V	60	185	230	280	ns
	Delay, Clock B to QC		4.5V	20	37	46	55	ns
			6.0V	17	32	40	48	ns
tPHL	Maximum Propagation		2.0V	55	165	210	250	ns
	Delay, Clear to any Q		4.5V	17	33	41	49	ns
			6.0V	15	28	35	42	ns
tREM	Minimum Removal Time		2.0V		25	25	25	ns
	Clear to Clock		4.5V		5	5	5	ns
			6.0V		5	5	5	ns
tW	Minimum Pulse Width		2.0V	30	80	100	120	ns
	Clear or Clock		4.5V	10	16	20	24	ns
			6.0V	9	14	18	20	ns
tTHL, tTLH	Maximum Output Rise		2.0V	30	75	95	110	ns
	and Fall Time		4.5V	8	15	19	22	ns
			6.0V	7	13	16	19	ns
tr, tf	Maximum Input Rise		2.0V		1000	1000	1000	ns
	and Fall Time		4.5V		500	500	500	ns
			6.0V		400	400	400	ns
CPD	Power Dissipation	(per counter)		55				pF
	Capacitance (Note 5)
CIN	Maximum Input Capacitance			5	10	10	10	pF

Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC.

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