NATIONAL SEMICONDUCTOR TP3057WM-X, TP3057WM, TP3057V-X, TP3057V, TP3057N Datasheet

August 1994

TP3054, TP3057 ``Enhanced'' Serial Interface

CODEC/Filter COMBOÉ Family

General Description

The TP3054, TP3057 family consists of m-law and A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in Figure 1 , and a serial PCM interface. The devices are fabricated using National's advanced double-poly CMOS process (microCMOS).

The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded m-law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded m-law or A-law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats.

Features

YComplete CODEC and filtering system (COMBO) including:

ÐTransmit high-pass and low-pass filtering

ÐReceive low-pass filter with sin x/x correction

ÐActive RC noise filters

Ðm-law or A-law compatible COder and DECoder

ÐInternal precision voltage reference

ÐSerial I/O interface

ÐInternal auto-zero circuitry

Ym-law, 16-pinÐTP3054

YA-law, 16-pinÐTP3057

YDesigned for D3/D4 and CCITT applications

Yg5V operation

YLow operating powerÐtypically 50 mW

YPower-down standby modeÐtypically 3 mW

YAutomatic power-down

YTTL or CMOS compatible digital interfaces

YMaximizes line interface card circuit density

YDual-In-Line or surface mount packages

YSee also AN-370, ``Techniques for Designing with CODEC/Filter COMBO Circuits''

Connection Diagrams

Dual-In-Line Package

Plastic Chip Carriers

TL/H/5510 ± 1

Top View

Order Number TP3054J or TP3057J

See NS Package Number J16A

Order Number TP3054N or TP3057N

See NS Package Number N16A

Order Number TP3054WM or TP3057WM

See NS Package Number M16B

COMBOÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.

TL/H/5510 ± 10

Top View

Order Number TP3057V

See NS Package Number V20A

C1995 National Semiconductor Corporation

TL/H/5510

RRD-B30M125/Printed in U. S. A.

Family COMBO CODEC/Filter Interface Serial ``Enhanced'' TP3057 TP3054,

Block Diagram

FIGURE 1

TL/H/5510 ± 2

Pin Description

Symbol	Function
VBB	Negative power supply pin.
	VBB e b5V g5%.
GNDA	Analog ground. All signals are referenced
	to this pin.
VFRO	Analog output of the receive power ampli-
	fier.
VCC	Positive power supply pin.
	VCC e a5V g5%.
FSR	Receive frame sync pulse which enables
	BCLKR to shift PCM data into DR. FSR is
	an 8 kHz pulse train. See Figures 2 and 3
	for timing details.
DR	Receive data input. PCM data is shifted
	into DR following the FSR leading edge.

BCLKR/CLKSEL The bit clock which shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see Table I).

MCLKR/PDN	Receive master clock. Must be
	1.536 MHz, 1.544 MHz or 2.048 MHz.
	May be asynchronous with MCLKX, but

Symbol		Function
		should be synchronous with MCLKX for best per-
		formance. When MCLKR is connected continu-
		ously low, MCLKX is selected for all internal tim-
		ing. When MCLKR is connected continuously
		high, the device is powered down.
MCLKX		Transmit master clock. Must be 1.536 MHz,
		1.544 MHz or 2.048 MHz. May be asynchronous
		with MCLKR. Best performance is realized from
		synchronous operation.
FSX		Transmit frame sync pulse input which enables
		BCLKX to shift out the PCM data on DX. FSX is
		an 8 kHz pulse train, see Figures 2 and 3 for
		timing details.
BCLKX		The bit clock which shifts out the PCM data on
		DX. May vary from 64 kHz to 2.048 MHz, but
		must be synchronous with MCLKX.
DX		The TRI-STATEÉ PCM data output which is en-
		abled by FSX.
TSX		Open drain output which pulses low during the
		encoder time slot.
GSX		Analog output of the transmit input amplifier.
		Used to externally set gain.
VFXIb		Inverting input of the transmit input amplifier.
VFXIa		Non-inverting input of the transmit input amplifi-
		er.

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Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down state. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin high; the alternative is to hold both FSX and FSR inputs continuously lowÐthe device will power-down approximately 1 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRI-STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse.

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLKR/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.

With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKR/ CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX.

Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRI-STATE DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R.

TABLE I. Selection of Master Clock Frequencies

	Master Clock
BCLKR/CLKSEL	Frequency Selected
	TP3057	TP3054
Clocked	2.048 MHz	1.536 MHz or
		1.544 MHz
0	1.536 MHz or	2.048 MHz
	1.544 MHz
1	2.048 MHz	1.536 MHz or
		1.544 MHz

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be 2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal MCLKR functions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock period long, with timing relationships specified in Figure 2 . With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode.

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in Figure 3 . Based on the transmit frame sync, FSX, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The DX TRI-STATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode.

In applications where the LSB bit is used for signalling with FSR two bit clock periods long, the decoder will interpret the lost LSB as ``(/2'' to minimize noise and distortion.

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Functional Description (Continued)

TRANSMIT SECTION

The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4 . The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-ca- pacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to m-law (TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (see table of Transmission Characteristics). The FSX frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through DX at the next FSX pulse. The total encoding delay will be approximately 165 ms (due to the transmit filter) plus 125 ms

(due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration.

RECEIVE SECTION

The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or m-law (TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/ power amplifer capable of driving a 600X load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occurrence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins, and 10 ms later the decoder DAC output is updated. The total decoder delay is E 10 ms (decoder update) plus 110 ms (filter delay) plus 62.5 ms ((/2 frame), which gives approximately 180 ms.

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5.0V, VBB e b5.0V, TA e 25§C.

Electrical Characteristics

Absolute Maximum Ratings

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

VCC to GNDA	7V
VBB to GNDA	b7V
Voltage at any Analog Input
or Output	VCCa0.3V to VBBb0.3V

Voltage at any Digital Input or
Output	VCCa0.3V to GNDAb0.3V
Operating Temperature Range	b25§C to a 125§C
Storage Temperature Range	b65§C to a150§C
Lead Temperature (Soldering, 10 seconds)		300§C
ESD (Human Body Model)		2000V
Latch-Up Immunity e 100 mA on any Pin

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g5%, VBB e b5.0V g5%; TA e 0§C to 70§C by correlation with 100% electrical testing at TA e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e

Symbol			Parameter			Conditions		Min	Typ	Max	Units
DIGITAL INTERFACE
VIL			Input Low Voltage							0.6	V
VIH			Input High Voltage					2.2			V
VOL			Output Low Voltage		DX, ILe3.2 mA					0.4	V
					SIGR, ILe1.0 mA					0.4	V
					TSX	, ILe3.2 mA, Open Drain				0.4	V
VOH			Output High Voltage		DX, IHeb3.2 mA			2.4			V
					SIGR, IHeb1.0 mA			2.4			V
IIL			Input Low Current		GNDAsVINsVIL, All Digital Inputs			b10		10	mA
IIH			Input High Current		VIHsVINsVCC			b10		10	mA
IOZ			Output Current in High Impedance		DX, GNDAsVOsVCC			b10		10	mA
			State (TRI-STATE)
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA			Input Leakage Current		b2.5VsVsa2.5V, VFXIa or VFXIb			b200		200	nA
RIXA			Input Resistance		b2.5VsVsa2.5V, VFXIa or VFXIb			10			MX
ROXA			Output Resistance		Closed Loop, Unity Gain				1	3	X
RLXA			Load Resistance		GSX			10			kX
CLXA			Load Capacitance		GSX					50	pF
VOXA			Output Dynamic Range		GSX, RLt10 kX			b2.8		2.8	V
A	V	XA	Voltage Gain		VF Ia to GS		X	5000			V/V
					X
FUXA			Unity Gain Bandwidth					1	2		MHz
VOSXA			Offset Voltage					b20		20	mV
VCMXA			Common-Mode Voltage		CMRRXA l 60 dB			b2.5		2.5	V
CMRRXA			Common-Mode Rejection Ratio		DC Test			60			dB
PSRRXA			Power Supply Rejection Ratio		DC Test			60			dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF			Output Resistance		Pin VFRO				1	3	X
RLRF			Load Resistance		VFROeg2.5V			600			X
CLRF			Load Capacitance							500	pF
VOSRO			Output DC Offset Voltage					b200		200	mV
POWER DISSIPATION (ALL DEVICES)
ICC0			Power-Down Current		No Load (Note)				0.5	1.5	mA
IBB0			Power-Down Current		No Load (Note)				0.05	0.3	mA
ICC1			Power-Up Active Current		No Load				5.0	9.0	mA
IBB1			Power-Up Active Current		No Load				5.0	9.0	mA

Note: ICC0 and IBB0 are measured after first achieving a power-up state.

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