COP87L88EGN-XE
August 1996
COP688EG/COP684EG/COP888EG/COP884EG/ COP988EG/COP984EG 8-Bit Microcontroller with UART and Three Multi-Function Timers
General Description
The COP8TM feature family of microcontrollers use an 8-bit single-chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888EG/COP884EG are members of this expandable 8-bit core processor family of microcontrollers. (Continued)
Key Features
YFull duplex UART
YThree 16-bit timers, each with two 16-bit registers supporting
ÐProcessor Independent PWM mode
ÐExternal Event counter mode
ÐInput Capture mode
YQuiet design (low radiated emissions)
Y8k bytes on-board ROM
Y256 bytes on-board RAM
Additional Peripheral Features
YIdle Timer
YMulti-Input Wake-Up (MIWU) with optional interrupts (8)
YTwo analog comparators
YWATCHDOGTM and clock monitor logic
YMICROWIRE/PLUSTM serial I/O
I/O Features
YMemory mapped I/O
YSoftware selectable I/O options (TRI-STATEÉ Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input)
YSchmitt trigger inputs on ports G and L
YPackages:
Ð28 SO or 28 DIP, each with 24 I/O pins
Ð40 DIP with 36 I/O pins
Ð44 PQFP with 40 I/O pins
Ð44 PLCC with 40 I/O pins
CPU/Instruction Set Features
Y1 ms instruction cycle time
YFourteen multi-source vectored interrupts servicing
ÐExternal Interrupt with selectable edge
ÐIdle Timer T0
ÐThree Timers (each with 2 Interrupts)
ÐMICROWIRE/PLUS
ÐMulti-Input Wake-Up
ÐSoftware Trap
ÐUART (2)
ÐDefault VIS (default interrupt)
YVersatile and easy to use instruction set
Y8-bit Stack Pointer (SP) stack in RAM
YTwo 8-bit Register Indirect Data Memory Pointers (B and X)
Fully Static CMOS
YTwo power saving modes: HALT and IDLE
YLow current drain (typically k1 mA)
YSingle supply operation: 2.5V to 6.0V
YTemperature ranges: 0§C to a70§C, b40§C to a85§C, b55§C to a125§C
Development Support
YEmulation and OTP devices
YReal time emulation and full program debug offered by MetaLink Development System
Block Diagram
TL/DD/11214 ± 1
FIGURE 1. Block Diagram
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUSTM, M2CMOSTM, COPSTM microcontrollers, MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation. IBMÉ, PCÉ, PC-ATÉ and PC-XTÉ are registered trademarks of International Business Machines Corporation.
iceMASTERTM is a trademark of MetaLink Corporation.
C1996 National Semiconductor Corporation |
TL/DD11214 |
RRD-B30M106/Printed in U. S. A. |
http://www.national.com |
COP688EG/COP684EG/COP888EG/COP884EG/COP988EG/COP984EG Timers Function-Multi Three and UART with Microcontroller Bit-8
General Description (Continued)
They are fully static parts, fabricated using double-metal silicon gate microCMOS technology. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUS serial I/O, three 16-bit timer/counters supporting three modes (Processor Independent PWM generation, External Event counter, and Input Capture mode capabilities), full duplex UART, two comparators, and two power savings modes (HALT and IDLE), both with a multi-sourced wakeup/interrupt capability. This multi-sourced interrupt capability may
Connection Diagrams
Plastic Chip Carrier
TL/DD/11214 ± 2
Top View
Order Number COP888EG-XXX/V
See NS Plastic Chip Package Number V44A
Molded Plastic Quad Flat Package
also be used independent of the HALT or IDLE modes. Each I/O pin has software selectable configurations. The device operates over a voltage range of 2.5V to 6V. High throughput is achieved with an efficient, regular instruction set operating at a maximum rate of 1 ms per instruction.
Low radiated emissions are achieved by gradual turn-on output drivers and internal ICC smoothing filters on the chip logic and crystal oscillator.
Dual-In-Line Package
TL/DD/11214 ± 3
Top View
Order Number COP888EG-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
|
TL/DD/11214 ± 4 |
TL/DD/11214 ± 30 |
Top View |
Top View |
Order Number COP884EG-XXX/WM |
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Order Number COP888EG-XXX/VEJ |
or COP884EG-XXX/N |
See NS Package Number VEJ44A |
See NS Molded Package Number M28B or N28A |
FIGURE 2a. Connection Diagrams
http://www.national.com |
2 |
Connection Diagrams (Continued)
Pinouts for 28-, 40and 44-Pin Packages
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Port |
Type |
Alt. Fun |
Alt. Fun |
28-Pin |
40-Pin |
44-Pin |
44-Pin |
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DIP/SO |
DIP |
PLCC |
PQFP |
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L0 |
I/O |
MIWU |
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11 |
17 |
17 |
11 |
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L1 |
I/O |
MIWU |
CKX |
12 |
18 |
18 |
12 |
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L2 |
I/O |
MIWU |
TDX |
13 |
19 |
19 |
13 |
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L3 |
I/O |
MIWU |
RDX |
14 |
20 |
20 |
14 |
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L4 |
I/O |
MIWU |
T2A |
15 |
21 |
25 |
19 |
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L5 |
I/O |
MIWU |
T2B |
16 |
22 |
26 |
20 |
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L6 |
I/O |
MIWU |
T3A |
17 |
23 |
27 |
21 |
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L7 |
I/O |
MIWU |
T3B |
18 |
24 |
28 |
22 |
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G0 |
I/O |
INT |
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25 |
35 |
39 |
33 |
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G1 |
WDOUT |
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26 |
36 |
40 |
34 |
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G2 |
I/O |
T1B |
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27 |
37 |
41 |
35 |
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G3 |
I/O |
T1A |
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28 |
38 |
42 |
36 |
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G4 |
I/O |
SO |
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1 |
3 |
3 |
41 |
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G5 |
I/O |
SK |
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2 |
4 |
4 |
42 |
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G6 |
I |
SI |
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3 |
5 |
5 |
43 |
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G7 |
I/CKO |
HALT Restart |
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4 |
6 |
6 |
44 |
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D0 |
O |
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19 |
25 |
29 |
23 |
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D1 |
O |
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20 |
26 |
30 |
24 |
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D2 |
O |
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21 |
27 |
31 |
25 |
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D3 |
O |
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22 |
28 |
32 |
26 |
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D4 |
O |
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29 |
33 |
7 |
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D5 |
O |
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30 |
34 |
8 |
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D6 |
O |
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31 |
35 |
9 |
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D7 |
O |
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32 |
36 |
10 |
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I0 |
I |
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7 |
9 |
9 |
27 |
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I1 |
I |
COMP1INb |
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8 |
10 |
10 |
28 |
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I2 |
I |
COMP1INa |
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9 |
11 |
11 |
29 |
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I3 |
I |
COMP1OUT |
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10 |
12 |
12 |
30 |
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I4 |
I |
COMP2INb |
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13 |
13 |
3 |
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I5 |
I |
COMP2INa |
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14 |
14 |
4 |
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I6 |
I |
COMP2OUT |
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15 |
15 |
5 |
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I7 |
I |
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16 |
16 |
6 |
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C0 |
I/O |
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39 |
43 |
37 |
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C1 |
I/O |
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40 |
44 |
38 |
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C2 |
I/O |
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1 |
1 |
39 |
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C3 |
I/O |
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2 |
2 |
40 |
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C4 |
I/O |
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21 |
15 |
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C5 |
I/O |
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22 |
16 |
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C6 |
I/O |
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23 |
17 |
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C7 |
I/O |
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24 |
18 |
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VCC |
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6 |
8 |
8 |
2 |
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GND |
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23 |
33 |
37 |
31 |
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CKI |
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5 |
7 |
7 |
1 |
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RESET |
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24 |
34 |
38 |
32 |
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3 |
http://www.national.com |
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) |
7V |
Voltage at Any Pin |
b0.3V to VCC a 0.3V |
Total Current into VCC Pin (Source) |
100 mA |
Total Current out of GND Pin (Sink) |
110 mA |
Storage Temperature Range |
b65§C to a140§C |
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics 98XEG: 0§C s TA s a70§C unless otherwise specified
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Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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Operating Voltage COP98XEG |
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2.5 |
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4.0 |
V |
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COP98XEGH |
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4.0 |
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6.0 |
V |
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Power Supply Ripple (Note 1) |
Peak-to-Peak |
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0.1 VCC |
V |
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Supply Current (Note 2) |
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CKI e 10 MHz |
VCC e 6V, tc e 1 ms |
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12.5 |
mA |
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CKI e 4 MHz |
VCC e 6V, tc e 2.5 ms |
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5.5 |
mA |
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CKI e 4 MHz |
VCC e 4V, tc e 2.5 ms |
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2.5 |
mA |
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CKI e 1 MHz |
VCC e 4V, tc e 10 ms |
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1.4 |
mA |
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HALT Current (Note 3) |
VCC e 6V, CKI e 0 MHz |
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k0.7 |
8 |
mA |
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VCC e 4V, CKI e 0 MHz |
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k0.3 |
4 |
mA |
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IDLE Current |
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CKI e 10 MHz |
VCC e 6V, tc e 1 ms |
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3.5 |
mA |
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CKI e 4 MHz |
VCC e 6V, tc e 2.5 ms |
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2.5 |
mA |
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CKI e 1 MHz |
VCC e 4V, tc e 10 ms |
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0.7 |
mA |
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Input Levels |
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RESET |
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Logic High |
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0.8 VCC |
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V |
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Logic Low |
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0.2 VCC |
V |
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CKI (External and Crystal Osc. Modes) |
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Logic High |
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0.7 VCC |
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V |
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Logic Low |
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0.2 VCC |
V |
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All Other Inputs |
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Logic High |
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0.7 VCC |
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V |
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Logic Low |
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0.2 VCC |
V |
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Hi-Z Input Leakage |
VCC e 6V |
b1 |
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a1 |
mA |
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Input Pullup Current |
VCC e 6V, VIN e 0V |
b40 |
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b250 |
mA |
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G and L Port Input Hysteresis |
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0.35 VCC |
V |
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Output Current Levels |
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D Outputs |
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Source |
VCC e 4V, VOH e 3.3V |
b0.4 |
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mA |
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VCC e 2.5V, VOH e 1.8V |
b0.2 |
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mA |
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Sink |
VCC e 4V, VOL e 1V |
10 |
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mA |
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VCC e 2.5V, VOL e 0.4V |
2.0 |
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mA |
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All Others |
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Source (Weak Pull-Up Mode) |
VCC e 4V, VOH e 2.7V |
b10 |
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b100 |
mA |
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VCC e 2.5V, VOH e 1.8V |
b2.5 |
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b33 |
mA |
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Source (Push-Pull Mode) |
VCC e 4V, VOH e 3.3V |
b0.4 |
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mA |
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VCC e 2.5V, VOH e 1.8V |
b0.2 |
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mA |
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Sink (Push-Pull Mode) |
VCC e 4V, VOL e 0.4V |
1.6 |
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mA |
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VCC e 2.5V, VOL e 0.4V |
0.7 |
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mA |
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TRI-STATE Leakage |
VCC e 6.0V |
b1 |
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a1 |
mA |
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Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0-G5 configured as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.
http://www.national.com |
4 |
DC Electrical Characteristics 98XEG: 0§C s TA s a70§C unless otherwise specified (Continued)
Parameter |
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Conditions |
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Min |
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Typ |
Max |
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Units |
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Allowable Sink/Source |
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Current per Pin |
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D Outputs (Sink) |
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15 |
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mA |
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All others |
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3 |
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mA |
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Maximum Input Current |
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TA e 25§C |
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g100 |
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mA |
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without Latchup (Note 5) |
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RAM Retention Voltage, Vr |
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500 ns Rise |
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2 |
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V |
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and Fall Time (Min) |
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Input Capacitance |
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7 |
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pF |
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Load Capacitance on D2 |
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1000 |
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pF |
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AC Electrical Characteristics 98XEG: 0§C s TA s a70§C unless otherwise specified |
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Parameter |
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Conditions |
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Min |
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Typ |
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Max |
Units |
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Instruction Cycle Time (tc) |
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4V s VCC s 6V |
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1 |
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DC |
ms |
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Crystal, Resonator, |
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2.5V s VCC k 4V |
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2.5 |
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DC |
ms |
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R/C Oscillator |
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4V s VCC s 6V |
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3 |
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DC |
ms |
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2.5V s VCC k 4V |
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7.5 |
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DC |
ms |
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Inputs |
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tSETUP |
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4V s VCC s 6V |
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200 |
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ns |
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2.5V s VCC k 4V |
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500 |
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ns |
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tHOLD |
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4V s VCC s 6V |
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60 |
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ns |
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2.5V s VCC k 4V |
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150 |
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ns |
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Output Propagation Delay (Note 6) |
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RL e 2.2k, CL e 100 pF |
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tPD1, tPD0 |
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SO, SK |
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4V s VCC s 6V |
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0.7 |
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ms |
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2.5V s VCC k 4V |
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1.75 |
ms |
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All Others |
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4V s VCC s 6V |
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1 |
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ms |
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2.5V s VCC k 4V |
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2.5 |
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ms |
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MICROWIRETM Setup Time (tUWS) |
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20 |
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ns |
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MICROWIRE Hold Time (tUWH) |
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56 |
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ns |
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MICROWIRE Output Propagation Delay (tUPD) |
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220 |
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ns |
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Input Pulse Width |
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Interrupt Input High Time |
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1 |
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tc |
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Interrupt Input Low Time |
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1 |
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tc |
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Timer Input High Time |
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1 |
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tc |
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Timer Input Low Time |
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1 |
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tc |
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Reset Pulse Width |
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1 |
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ms |
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Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
5 |
http://www.national.com |
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) |
7V |
Voltage at Any Pin |
b0.3V to VCC a 0.3V |
Total Current into VCC Pin (Source) |
100 mA |
Total Current out of GND Pin (Sink) |
110 mA |
Storage Temperature Range |
b65§C to a140§C |
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics 888EG: b40§C s TA s a85§C unless otherwise specified
|
|
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
|
|
|
|
|
|
|
|
|
Operating Voltage |
|
2.5 |
|
6 |
V |
|
|
|
|
|
|
|
|
|
|
Power Supply Ripple (Note 1) |
Peak-to-Peak |
|
|
0.1 VCC |
V |
|
|
Supply Current (Note 2) |
|
|
|
|
|
|
|
CKI e 10 MHz |
VCC e 6V, tc e 1 ms |
|
|
12.5 |
mA |
|
|
CKI e 4 MHz |
VCC e 6V, tc e 2.5 ms |
|
|
5.5 |
mA |
|
|
CKI e 4 MHz |
VCC e 4.0V, tc e 2.5 ms |
|
|
2.5 |
mA |
|
|
CKI e 1 MHz |
VCC e 4.0V, tc e 10 ms |
|
|
1.4 |
mA |
|
|
HALT Current (Note 3) |
VCC e 6V, CKI e 0 MHz |
|
k1 |
10 |
mA |
|
|
|
|
VCC e 4.0V, CKI e 0 MHz |
|
k0.5 |
6 |
mA |
|
IDLE Current |
|
|
|
|
|
|
|
CKI e 10 MHz |
VCC e 6V, tc e 1 ms |
|
|
3.5 |
mA |
|
|
CKI e 4 MHz |
VCC e 6V, tc e 2.5 ms |
|
|
2.5 |
mA |
|
|
CKI e 1 MHz |
VCC e 4.0V, tc e 10 ms |
|
|
0.7 |
mA |
|
|
Input Levels |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESET |
|
|
|
|
|
|
|
Logic High |
|
0.8 VCC |
|
|
V |
|
|
Logic Low |
|
|
|
0.2 VCC |
V |
|
CKI (External and Crystal Osc. Modes) |
|
|
|
|
|
||
|
Logic High |
|
0.7 VCC |
|
|
V |
|
|
Logic Low |
|
|
|
0.2 VCC |
V |
|
All Other Inputs |
|
|
|
|
|
||
|
Logic High |
|
0.7 VCC |
|
|
V |
|
|
Logic Low |
|
|
|
0.2 VCC |
V |
|
|
Hi-Z Input Leakage |
VCC e 6V |
b2 |
|
a2 |
mA |
|
|
Input Pullup Current |
VCC e 6V, VIN e 0V |
b40 |
|
b250 |
mA |
|
|
G and L Port Input Hysteresis |
|
|
|
0.35 VCC |
V |
|
|
Output Current Levels |
|
|
|
|
|
|
|
D Outputs |
|
|
|
|
|
|
|
Source |
VCC e 4V, VOH e 3.3V |
b0.4 |
|
|
mA |
|
|
|
|
VCC e 2.5V, VOH e 1.8V |
b0.2 |
|
|
mA |
|
Sink |
VCC e 4V, VOL e 1V |
10 |
|
|
mA |
|
|
|
|
VCC e 2.5V, VOL e 0.4V |
2.0 |
|
|
mA |
|
All Others |
|
|
|
|
|
|
|
Source (Weak Pull-Up Mode) |
VCC e 4V, VOH e 2.7V |
b10 |
|
b100 |
mA |
|
|
|
|
VCC e 2.5V, VOH e 1.8V |
b2.5 |
|
b33 |
mA |
|
Source (Push-Pull Mode) |
VCC e 4V, VOH e 3.3V |
b0.4 |
|
|
mA |
|
|
|
|
VCC e 2.5V, VOH e 1.8V |
b0.2 |
|
|
mA |
|
Sink (Push-Pull Mode) |
VCC e 4V, VOL e 0.4V |
1.6 |
|
|
mA |
|
|
|
|
VCC e 2.5V, VOL e 0.4V |
0.7 |
|
|
mA |
|
TRI-STATE Leakage |
VCC e 6.0V |
b2 |
|
a2 |
mA |
|
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a crystal/resonator oscillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C, and G0-G5 configured as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.
http://www.national.com |
6 |
DC Electrical Characteristics 888EG: b40§C s TA s a85§C unless otherwise specified (Continued)
Parameter |
|
Conditions |
|
Min |
|
Typ |
Max |
|
|
Units |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Allowable Sink/Source |
|
|
|
|
|
|
|
|
|
|
|
|
|
Current per Pin |
|
|
|
|
|
|
|
|
|
|
|
|
|
D Outputs (Sink) |
|
|
|
|
|
|
|
|
15 |
|
|
mA |
|
All others |
|
|
|
|
|
|
|
|
3 |
|
|
|
mA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum Input Current |
|
TA e 25§C |
|
|
|
|
|
g100 |
|
|
mA |
||
without Latchup |
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RAM Retention Voltage, Vr |
|
500 ns Rise |
|
2 |
|
|
|
|
|
|
|
V |
|
|
|
and Fall Time (Min) |
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input Capacitance |
|
|
|
|
|
|
|
|
7 |
|
|
|
pF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Load Capacitance on D2 |
|
|
|
|
|
|
|
|
1000 |
|
|
pF |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
AC Electrical Characteristics 888EG: b40§C s TA s a85§C unless otherwise specified |
|
|
|
||||||||||
Parameter |
|
Conditions |
|
Min |
|
Typ |
|
Max |
Units |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Instruction Cycle Time (tc) |
|
|
|
|
|
|
|
|
|
|
|
|
|
Crystal, Resonator, |
|
4V s VCC s 6V |
|
|
1 |
|
|
|
DC |
ms |
|||
R/C Oscillator |
|
2.5V s VCC k 4V |
|
2.5 |
|
|
|
DC |
ms |
||||
|
|
|
4V s VCC s 6V |
|
|
3 |
|
|
|
DC |
ms |
||
|
|
|
2.5V s VCC k 4V |
|
7.5 |
|
|
|
DC |
ms |
|||
Inputs |
|
|
|
|
|
|
|
|
|
|
|
|
|
tSETUP |
|
4V s VCC s 6V |
|
|
200 |
|
|
|
|
|
ns |
||
|
|
|
2.5V s VCC k 4V |
|
500 |
|
|
|
|
|
ns |
||
tHOLD |
|
4V s VCC s 6V |
|
|
60 |
|
|
|
|
|
ns |
||
|
|
|
2.5V s VCC k 4V |
|
150 |
|
|
|
|
|
ns |
||
Output Propagation Delay (Note 4) |
|
RL e 2.2k, CL e 100 pF |
|
|
|
|
|
|
|
|
|||
tPD1, tPD0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
SO, SK |
|
4V s VCC s 6V |
|
|
|
|
|
|
0.7 |
|
ms |
||
|
|
|
2.5V s VCC k 4V |
|
|
|
|
|
1.75 |
ms |
|||
All Others |
|
4V s VCC s 6V |
|
|
|
|
|
|
1 |
|
ms |
||
|
|
|
2.5V s VCC k 4V |
|
|
|
|
|
2.5 |
|
ms |
||
MICROWIRETM Setup Time (tUWS) |
|
|
|
|
|
20 |
|
|
|
|
|
ns |
|
MICROWIRE Hold Time (tUWH) |
|
|
|
|
|
56 |
|
|
|
|
|
ns |
|
MICROWIRE Output Propagation Delay (tUPD) |
|
|
|
|
|
|
|
220 |
|
ns |
|||
Input Pulse Width |
|
|
|
|
|
|
|
|
|
|
|
|
|
Interrupt Input High Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
|
Interrupt Input Low Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
|
Timer Input High Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
|
Timer Input Low Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
|
Reset Pulse Width |
|
|
|
|
|
1 |
|
|
|
|
|
ms |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tc e Instruction cycle time.
Note 4: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
7 |
http://www.national.com |
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) |
7V |
Voltage at Any Pin |
b0.3V to VCC a 0.3V |
Total Current into VCC Pin (Source) |
100 mA |
Total Current out of GND Pin (Sink) |
110 mA |
Storage Temperature Range |
b65§C to a140§C |
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics 688EG: b55§C s TA s a125§C unless otherwise specified
|
|
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
|
|
|
|
|
|
|
|
|
Operating Voltage |
|
4.5 |
|
5.5 |
V |
|
|
|
|
|
|
|
|
|
|
Power Supply Ripple (Note 1) |
Peak-to-Peak |
|
|
0.1 VCC |
V |
|
|
Supply Current (Note 2) |
|
|
|
|
|
|
|
CKI e 10 MHz |
VCC e 5.5V, tc e 1 ms |
|
|
12.5 |
mA |
|
|
CKI e 4 MHz |
VCC e 5.5V, tc e 2.5 ms |
|
|
5.5 |
mA |
|
|
HALT Current (Note 3) |
VCC e 5.5V, CKI e 0 MHz |
|
k10 |
30 |
mA |
|
|
IDLE Current |
|
|
|
|
|
|
|
CKI e 10 MHz |
VCC e 5.5V, tc e 1 ms |
|
|
3.5 |
mA |
|
|
CKI e 4 MHz |
VCC e 5.5V, tc e 2.5 ms |
|
|
2.5 |
mA |
|
|
Input Levels |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESET |
|
|
|
|
|
|
|
Logic High |
|
0.8 VCC |
|
|
V |
|
|
Logic Low |
|
|
|
0.2 VCC |
V |
|
CKI (External and Crystal Osc. Modes) |
|
|
|
|
|
||
|
Logic High |
|
0.7 VCC |
|
|
V |
|
|
Logic Low |
|
|
|
0.2 VCC |
V |
|
All Other Inputs |
|
|
|
|
|
||
|
Logic High |
|
0.7 VCC |
|
|
V |
|
|
Logic Low |
|
|
|
0.2 VCC |
V |
|
|
Hi-Z Input Leakage |
VCC e 5.5V |
b5 |
|
a5 |
mA |
|
|
Input Pullup Current |
VCC e 5.5V, VIN e 0V |
b35 |
|
b400 |
mA |
|
|
G and L Port Input Hysteresis |
|
|
|
0.35 VCC |
V |
|
|
Output Current Levels |
|
|
|
|
|
|
|
D Outputs |
|
|
|
|
|
|
|
Source |
VCC e 4.5V, VOH e 3.3V |
b0.4 |
|
|
mA |
|
|
Sink |
VCC e 4.5V, VOL e 1V |
9 |
|
|
mA |
|
|
All Others |
|
|
|
|
|
|
|
Source (Weak Pull-Up Mode) |
VCC e 4.5V, VOH e 2.7V |
b9 |
|
b140 |
mA |
|
|
Source (Push-Pull Mode) |
VCC e 4.5V, VOH e 3.3V |
b0.4 |
|
|
mA |
|
|
Sink (Push-Pull Mode) |
VCC e 4.5V, VOL e 0.4V |
1.4 |
|
|
mA |
|
|
TRI-STATE Leakage |
VCC e 5.5V |
b5 |
|
a5 |
mA |
|
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a crystal/resonator oscillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C, and G0-G5 configured as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.
http://www.national.com |
8 |
DC Electrical Characteristics 688EG: b55§C s TA s a125§C unless otherwise specified (Continued)
Parameter |
Conditions |
|
Min |
|
Typ |
Max |
|
|
Units |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Allowable Sink/Source |
|
|
|
|
|
|
|
|
|
|
|
|
Current per Pin |
|
|
|
|
|
|
|
|
|
|
|
|
D Outputs (Sink) |
|
|
|
|
|
|
|
12 |
|
|
mA |
|
All others |
|
|
|
|
|
|
|
2.5 |
|
|
mA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum Input Current |
TA e 25§C |
|
|
|
|
|
g100 |
|
|
mA |
||
without Latchup |
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RAM Retention Voltage, Vr |
500 ns Rise |
|
2 |
|
|
|
|
|
|
|
V |
|
|
and Fall Time (Min) |
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
Input Capacitance |
|
|
|
|
|
|
|
7 |
|
|
|
pF |
|
|
|
|
|
|
|
|
|
|
|
|
|
Load Capacitance on D2 |
|
|
|
|
|
|
|
1000 |
|
|
pF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC Electrical Characteristics 688EG: b55§C s TA s a125§C unless otherwise specified |
|
|
|
|||||||||
Parameter |
|
Conditions |
|
Min |
|
Typ |
|
Max |
Units |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Instruction Cycle Time (tc) |
|
|
|
|
|
|
|
|
|
|
|
|
Crystal, Resonator, |
|
VCC t 4.5V |
|
|
1 |
|
|
|
DC |
ms |
||
R/C Oscillator |
|
VCC t 4.5V |
|
|
3 |
|
|
|
DC |
ms |
||
Inputs |
|
|
|
|
|
|
|
|
|
|
|
|
tSETUP |
|
VCC t 4.5V |
|
|
200 |
|
|
|
|
|
ns |
|
tHOLD |
|
VCC t 4.5V |
|
|
60 |
|
|
|
|
|
ns |
|
Output Propagation Delay (Note 4) |
|
RL e 2.2k, CL e 100 pF |
|
|
|
|
|
|
|
|
||
tPD1, tPD0 |
|
|
|
|
|
|
|
|
|
|
|
|
SO, SK |
|
VCC t 4.5V |
|
|
|
|
|
|
0.7 |
|
ms |
|
All Others |
|
VCC t 4.5V |
|
|
|
|
|
|
1 |
|
ms |
|
MICROWIRE Setup Time (tUWS) |
|
|
|
|
|
20 |
|
|
|
|
|
ns |
MICROWIRE Hold Time (tUWH) |
|
|
|
|
|
56 |
|
|
|
|
|
ns |
MICROWIRE Output Propagation Delay (tUPD) |
|
|
|
|
|
|
|
220 |
|
ns |
||
Input Pulse Width |
|
|
|
|
|
|
|
|
|
|
|
|
Interrupt Input High Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
Interrupt Input Low Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
Timer Input High Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
Timer Input Low Time |
|
|
|
|
|
1 |
|
|
|
|
|
tc |
Reset Pulse Width |
|
|
|
|
|
1 |
|
|
|
|
|
ms |
Note 4: The output propagation delay is referenced to the end of instruction cycle where the output change occurs.
9 |
http://www.national.com |
Comparators AC and DC Characteristics VCC e 5V, TA e 25§C
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
|
|
|
|
|
|
Input Offset Voltage |
0.4V s VIN s VCC b 1.5V |
|
g10 |
g25 |
mV |
Input Common Mode Voltage Range |
|
0.4 |
|
VCC b 1.5 |
V |
Low Level Output Current |
VOL e 0.4V |
1.6 |
|
|
mA |
High Level Output Current |
VOH e 4.6V |
1.6 |
|
|
mA |
DC Supply Current Per Comparator |
|
|
|
250 |
mA |
(When Enabled) |
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
Response Time |
TBD mV Step, TBD mV |
|
1 |
|
ms |
|
Overdrive, 100 pF Load |
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
TL/DD/11214 ± 5
FIGURE 2. MICROWIRE/PLUS Timing
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10 |
Typical Performance Characteristics (b40§C s TA s a85§C)
HaltÐIDD |
IdleÐIDD (Crystal Clock Option) |
TL/DD/11214 ± 7 TL/DD/11214 ± 8
DynamicÐIDD vs VCC |
Port L/C/G Weak Pull-Up |
(Crystal Clock Option) |
Source Current |
TL/DD/11214 ± 9 TL/DD/11214 ± 10
Port L/C/G Push-Pull Source Current Port L/C/G Push-Pull Sink Current
TL/DD/11214 ± 11 |
TL/DD/11214 ± 12 |
Port D Source Current |
Port D Sink Current |
TL/DD/11214 ± 13 |
TL/DD/11214 ± 14 |
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Pin Descriptions
VCC and GND are the power supply pins.
CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description section.
The device contains three bidirectional 8-bit I/O ports (C, G and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 3 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:
CONFIGURATION |
DATA |
Port Set-Up |
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Register |
Register |
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0 |
0 |
Hi-Z Input |
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(TRI-STATE Output) |
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0 |
1 |
Input with Weak Pull-Up |
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1 |
0 |
Push-Pull Zero Output |
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1 |
1 |
Push-Pull One Output |
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PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.
The Port L supports Multi-Input Wake Up on all eight pins. L1 is used for the UART external clock. L2 and L3 are used for the UART transmit and receive. L4 and L5 are used for the timer input functions T2A and T2B. L6 and L7 are used for the timer input functions T3A and T3B.
The Port L has the following alternate features:
L0 MIWU
L1 MIWU or CKX
L2 MIWU or TDX
L3 MIWU or RDX
L4 MIWU or T2A
L5 MIWU or T2B
L6 MIWU or T3A
L7 MIWU or T3B
Port G is an 8-bit port with 5 I/O pins (G0, G2 ± G5), an input pin (G6), and two dedicated output pins (G1 and G7). Pins G0 and G2 ± G6 all have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output, while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the single-pin R/C oscillator mask option selected, G7 serves as a general purpose input pin but is also used to bring the device out of HALT mode with a low to high transition on G7. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 5 I/O bits (G0, G2 ± G5) can be individually configured under software control.
TL/DD/11214 ± 6
FIGURE 3. I/O Port Configurations
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Pin Descriptions (Continued)
Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R/C clock option), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeros.
Note that the chip will be placed in the HALT mode by writing a ``1'' to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writing a ``1'' to bit 6 of the Port G Data Register.
Writing a ``1'' to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used.
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Config Reg. |
Data Reg. |
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G7 |
CLKDLY |
HALT |
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G6 |
Alternate SK |
IDLE |
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Port G has the following alternate features:
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
G4 SO (MICROWIRETM Serial Data Output)
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated output
G7 CKO Oscillator dedicated output or general purpose input
Port C is an 8-bit I/O port. The 40-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation for these unterminated pins will return unpredicatable values.
PORT I is an eight-bit Hi-Z input port. The 28-pin device does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw power only when addressed.
Port I1 ± I3 are used for Comparator 1. Port I4 ± I6 are used for Comparator 2.
The Port I has the following alternate features.
I1 COMP1bIN (Comparator 1 Negative Input)
I2 COMP1aIN (Comparator 1 Positive Input)
I3 COMP1OUT (Comparator 1 Output)
I4 COMP2bIN (Comparator 2 Negative Input)
I5 COMP2aIN (Comparator 2 Positive Input)
I6 COMP2OUT (Comparator 2 Output)
Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.8 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to less than 1000 pF.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tc) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256 data segments of 128 bytes each.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 8192 bytes of ROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts in the devices vector to program memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X, SP pointers and S register.
The data memory consists of 256 bytes of RAM. Sixteen bytes of RAM are mapped as ``registers'' at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, B and S are memory mapped into this space at address locations 0FC to 0FF Hex respectively, with the other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
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Data Memory Segment RAM Extension
Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows an addressing range of 256 locations from 00 to FF hex. The upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously. With the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000 to 00FF) is extended. If this upper bit equals one (representing address range 0080 to 00FF), then address extension does not take place. Alternatively, if this upper bit equals zero, then the data segment extension register S is used to extend the base address range (from 0000 to 007F) from XX00 to XX7F, where XX represents the 8 bits from the S register. Thus the 128-byte data segment extensions are located from addresses 0100 to 017F for data segment 1, 0200 to 027F for data segment 2, etc., up to FF00 to FF7F for data segment 255. The base address range from 0000 to 007F represents data segment 0.
Figure 4 illustrates how the S register data memory extension is used in extending the lower half of the base address range (00 to 7F hex) into 256 data segments of 128 bytes each, with a total addressing range of 32 kbytes from XX00 to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are available for all data segments. The S register must be changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers, control registers, etc.) is always available regardless of the contents of the S register, since the upper base segment (address range 0080 to 00FF) is independent of data segment extension.
The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the stack (used with subroutine linkage and interrupts) is always located in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of reset.
The 128 bytes of RAM contained in the base segment are split between the lower and upper base segments. The first 112 bytes of RAM are resident from address 0000 to 006F in the lower base segment, while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM is located at the upper sixteen addresses (0070 to 007F) of the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will always be memory mapped in groups of 128 bytes (or less) at the data segment address extensions (XX00 to XX7F) of the lower base segment. The additional 128 bytes of RAM are memory mapped at address locations 0100 to 017F hex.
TL/DD/11214 ± 15
*Reads as all ones.
FIGURE 4. RAM Organization
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is pulled low. Upon initialization, the data and configuration registers for ports L, G and C are cleared, resulting in these Ports being initialized to the TRI-STATE mode. Pin G1 of the G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and/or Clock Monitor error output pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL, T2CNTRL and T3CNTRL control registers are cleared. The UART registers PSR, ENU (except that TBMT bit is set), ENUR and ENUI are cleared. The Comparator Select Register is cleared. The S register is initialized to zero. The Multi-Input Wakeup registers WKEN, WKEDG and WKPND are cleared. The stack pointer, SP, is initialized to 6F Hex.
The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tC clock cycles. The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will continue until 16 tC ± 32 tC clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 5 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes.
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Reset (Continued)
TL/DD/11214 ± 16
RC l 5 c Power Supply Rise Time
FIGURE 5. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction cycle clock (1/tc).
Figure 6 shows the Crystal and R/C oscillator diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
Table A shows the component values required for various standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart input.
Table B shows the variation in the oscillator frequencies as functions of the component (R and C) values.
TL/DD/11214 ± 18
TL/DD/11214 ± 17
FIGURE 6. Crystal and R/C Oscillator Diagrams
TABLE A. Crystal Oscillator Configuration, TA e 25§C
R1 |
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R2 |
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C1 |
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C2 |
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CKI Freq |
Conditions |
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(kX) |
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(MX) |
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(pF) |
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(pF) |
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(MHz) |
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0 |
1 |
30 |
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30 ± 36 |
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10 |
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VCC e 5V |
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0 |
1 |
30 |
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30 ± 36 |
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4 |
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VCC e 5V |
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0 |
1 |
200 |
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100 ± 150 |
0.455 |
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VCC e 5V |
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TABLE B. RC Oscillator Configuration, TA e 25§C |
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R |
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C |
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CKI Freq |
Instr. Cycle |
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Conditions |
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(kX) |
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(pF) |
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(MHz) |
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(ms) |
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3.3 |
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82 |
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2.2 to 2.7 |
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3.7 to 4.6 |
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VCC e 5V |
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5.6 |
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100 |
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1.1 to 1.3 |
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7.4 to 9.0 |
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VCC e 5V |
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6.8 |
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100 |
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0.9 to 1.1 |
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8.8 to 10.8 |
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VCC e 5V |
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Note: 3k s R s 200k |
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50 pF s C s 200 pF |
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Control Registers
CNTRL Register (Address XÊ00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
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by (00 e 2, 01 e 4, 1x e 8) |
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IEDG |
External interrupt edge polarity select |
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(0 e Rising edge, 1 e Falling edge) |
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MSEL |
Selects G5 and G4 as MICROWIRE/PLUS |
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signals SK and SO respectively |
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T1C0 |
Timer T1 Start/Stop control in timer |
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modes 1 and 2 |
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Timer T1 Underflow Interrupt Pending Flag in |
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timer mode 3 |
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T1C1 |
Timer T1 mode control bit |
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T1C2 |
Timer T1 mode control bit |
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T1C3 |
Timer T1 mode control bit |
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T1C3 |
T1C2 |
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T1C1 |
T1C0 |
MSEL |
IEDG |
SL1 |
SL0 |
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Bit 7 |
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Bit 0 |
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15 |
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