MM54HC76
January 1988
MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear
General Description
These high speed (30 MHz minimum) J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve, the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads.
Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs and Q and Q outputs. These devices are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
YTypical propagation delay: 16 ns
YWide operating voltage range
YLow input current: 1 mA maximum
YLow quiescent current: 40 mA maximum (74HC Series)
YHigh output drive: 10 LS-TTL loads
Connection and Logic Diagrams |
Truth Table |
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Dual-In-Line Package |
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Inputs |
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Outputs |
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PR |
CLR |
CLK |
J |
L |
Q |
Q |
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L |
H |
X |
X |
X |
H |
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L |
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H |
L |
X |
X |
X |
L |
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H |
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L |
L |
X |
X |
X |
L* |
L* |
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H |
H |
v |
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L |
L |
Q0 |
Q0 |
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H |
H |
v |
H |
L |
H |
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L |
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H |
H |
v |
L |
H |
L |
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H |
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H |
H |
v |
H |
H |
TOGGLE |
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H |
H |
H |
X |
X |
Q0 |
Q0 |
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*This is an unstable condition, and is not guaranteed
TL/F/5074 ± 1
Top View
Order Number MM54HC76 or MM74HC76
TL/F/5074 ± 3
TL/F/5074 ± 2
(1 of 2)
Clear and Preset with Flops-Flip K-J Dual MM54HC76/MM74HC76
C1995 National Semiconductor Corporation |
TL/F/5074 |
RRD-B30M105/Printed in U. S. A. |
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) |
b0.5 to a7.0V |
DC Input Voltage (VIN) |
b1.5 to VCCa1.5V |
DC Output Voltage (VOUT) |
b0.5 to VCCa0.5V |
Clamp Diode Current (IIK, IOK) |
g20 mA |
DC Output Current, per pin (IOUT) |
g25 mA |
DC VCC or GND Current, per pin (ICC) |
g50 mA |
Storage Temperature Range (TSTG) |
b65§C to a150§C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temp. (TL) (Soldering 10 seconds) |
260§C |
DC Electrical Characteristics (Note 4)
Operating Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
0 |
VCC |
V |
(VIN, VOUT) |
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Operating Temp. Range (TA) |
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§C |
MM74HC |
b40 |
a85 |
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MM54HC |
b55 |
a125 |
§C |
Input Rise or Fall Times |
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(tr, tf) VCCe2.0V |
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1000 |
ns |
VCCe4.5V |
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500 |
ns |
VCCe6.0V |
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400 |
ns |
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TAe25§C |
74HC |
54HC |
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Symbol |
Parameter |
Conditions |
VCC |
TAeb40 to 85§C |
TAeb55 to 125§C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum High Level |
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2.0V |
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1.5 |
1.5 |
1.5 |
V |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
V |
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VIL |
Maximum Low Level |
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2.0V |
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0.5 |
0.5 |
0.5 |
V |
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Input Voltage** |
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4.5V |
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1.35 |
1.35 |
1.35 |
V |
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6.0V |
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1.8 |
1.8 |
1.8 |
V |
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VOH |
Minimum High Level |
VINeVIH or VIL |
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Output Voltage |
lIOUTls20 mA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
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VINeVIH or VIL |
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lIOUTls4.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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lIOUTls5.2 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
VOL |
Maximum Low Level |
VINeVIH or VIL |
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Output Voltage |
lIOUTls20 mA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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VINeVIH or VIL |
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lIOUTls4.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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lIOUTls5.2 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
IIN |
Maximum Input |
VINeVCC or GND |
6.0V |
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g0.1 |
g1.0 |
g1.0 |
mA |
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Current |
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ICC |
Maximum Quiescent |
VINeVCC or GND |
6.0V |
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4 |
40 |
80 |
mA |
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Supply Current |
IOUTe0 mA |
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Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ``N'' package: b12 mW/§C from 65§C to 85§C; ceramic ``J'' package: b12 mW/§C from 100§C to 125§C.
Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89.
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