January 1992
MM74HC160 Synchronous
Decade Counter with Asynchronous Clear
MM54HC161/MM74HC161 Synchronous
Binary Counter with Asynchronous Clear
MM54HC162/MM74HC162 Synchronous
Decade Counter with Synchronous Clear
MM54HC163/MM74HC163 Synchronous
Binary Counter with Synchronous Clear
General Description
T h e M M 5 4 H C 1 6 0 / M M 7 4 H C 1 6 0 , M M 5 4 H C 1 6 1 / M M 7 4 H C 1 6 1 , M M 5 4 H C 1 6 2 / M M 7 4 H C 1 6 2 , a n d MM54HC163/MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high speed counting applications. They offer the high noise immunity and low power consumption inherent to CMOS with speeds similar to low power Schottky TTL. The 'HC160 and the 'HC162 are 4 bit decade counters, and the 'HC161 and the 'HC163 are 4 bit binary counters. All flip-flops are clocked simultaneously on the low to high transition (positive edge) of the CLOCK input waveform.
These counters may be preset using the LOAD input. Presetting of all four flip-flops is synchronous to the rising edge of CLOCK. When LOAD is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken high before the positive edge of CLOCK the count operation will be unaffected.
All of these counters may be cleared by utilizing the CLEAR input. The clear function on the MM54HC162/MM74HC162 and MM54HC163/MM74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive edge of CLOCK while the clear input is held low.
T h e M M 5 4 H C 1 6 0 / M M 7 4 H C 1 6 0 a n d M M 5 4 H C 1 6 1 / MM74HC161 counters are cleared asynchronously. When the CLEAR is taken low the counter is cleared immediately regardless of the CLOCK.
Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be high to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high level portion of the QA output. The RC output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
YTypical operating frequency: 40 MHz
YTypical propagation delay; clock to Q: 18 ns
YLow quiescent current: 80 mA maximum (74HC Series)
YLow input current: 1 mA maximum
YWide power supply range: 2 ± 6V
Connection Diagram |
Truth Tables |
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'HC160/HC161 |
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CLK |
CLR |
ENP |
ENT |
Load |
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Function |
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X |
L |
X |
X |
X |
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Clear |
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X |
H |
H |
L |
H |
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Count & RC disabled |
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X |
H |
L |
H |
H |
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Count disabled |
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X |
H |
L |
L |
H |
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Count & RC disabled |
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u |
H |
X |
X |
L |
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Load |
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u |
H |
H |
H |
H |
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Increment Counter |
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H e high level, L e low level |
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X e don't care, u e low to high transition |
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'HC162/HC163 |
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CLK |
CLR |
ENP |
ENT |
Load |
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Function |
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u |
L |
X |
X |
X |
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Clear |
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X |
H |
H |
L |
H |
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Count & RC disabled |
TL/F/5008 ± 1 |
X |
H |
L |
H |
H |
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Count disabled |
Order Number MM54HC161/162/163 |
X |
H |
L |
L |
H |
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Count & RC disabled |
or MM74HC160/161/162/163 |
u |
H |
X |
X |
L |
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Load |
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u |
H |
H |
H |
H |
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Increment Counter |
74HC160/MM54/74HC161/MM54/74HC162/MM54/74HC163
C1995 National Semiconductor Corporation |
TL/F/5008 |
RRD-B30M115/Printed in U. S. A. |
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) |
b0.5 to a7.0V |
DC Input Voltage (VIN) |
b1.5 to VCCa1.5V |
DC Output Voltage (VOUT) |
b0.5 to VCCa0.5V |
Clamp Diode Current (IIK, IOK) |
g20 mA |
DC Output Current, per pin (IOUT) |
g25 mA |
DC VCC or GND Current, per pin (ICC) |
g50 mA |
Storage Temperature Range (TSTG) |
b65§C to a150§C |
Power Dissipation (PD) |
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(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temp. (TL) (Soldering 10 seconds) |
260§C |
DC Electrical Characteristics (Note 4)
Operating Conditions
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Min |
Max |
Units |
Supply Voltage (VCC) |
2 |
6 |
V |
DC Input or Output Voltage |
0 |
VCC |
V |
(VIN, VOUT) |
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Operating Temp. Range (TA) |
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§C |
MM74HC |
b40 |
a85 |
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MM54HC |
b55 |
a125 |
§C |
Input Rise or Fall Times |
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(tr, tf) VCCe2.0V |
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1000 |
ns |
VCCe4.5V |
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500 |
ns |
VCCe6.0V |
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400 |
ns |
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TAe25§C |
74HC |
54HC |
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Symbol |
Parameter |
Conditions |
VCC |
TAeb40 to 85§C |
TAeb55 to 125§C |
Units |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum High Level |
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2.0V |
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1.5 |
1.5 |
1.5 |
V |
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Input Voltage |
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4.5V |
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3.15 |
3.15 |
3.15 |
V |
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6.0V |
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4.2 |
4.2 |
4.2 |
V |
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VIL |
Maximum Low Level |
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2.0V |
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0.5 |
0.5 |
0.5 |
V |
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Input Voltage** |
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4.5V |
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1.35 |
1.35 |
1.35 |
V |
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6.0V |
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1.8 |
1.8 |
1.8 |
V |
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VOH |
Minimum High Level |
VINeVIH or VIL |
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Output Voltage |
lIOUTls20 mA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
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VINeVIH or VIL |
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lIOUTls4.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
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lIOUTls5.2 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
VOL |
Maximum Low Level |
VINeVIH or VIL |
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Output Voltage |
lIOUTls20 mA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
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6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
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VINeVIH or VIL |
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lIOUTls4.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
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lIOUTls5.2 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
IIN |
Maximum Input |
VINeVCC or GND |
6.0V |
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g0.1 |
g1.0 |
g1.0 |
mA |
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Current |
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ICC |
Maximum Quiescent |
VINeVCC or GND |
6.0V |
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8.0 |
80 |
160 |
mA |
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Supply Current |
IOUTe0 mA |
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Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ``N'' package: b12 mW/§C from 65§C to 85§C; ceramic ``J'' package: b12 mW/§C from 100§C to 125§C.
Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89.
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