January 1988
MM54HC365/MM74HC365 Hex TRI-STATEÉ Buffer
MM54HC366/MM74HC366 Inverting Hex TRI-STATE Buffer
MM54HC367/MM74HC367 Hex TRI-STATE Buffer
MM54HC368/MM74HC368 Inverting Hex TRI-STATE Buffer
General Description
These TRI-STATE buffers are general purpose high speed inverting and non-inverting buffers that utilize advanced sili- con-gate CMOS technology. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. All 4 circuits are capable of driving up to 15 low power Schottky inputs.
The MM54/74HC366 and the MM54/74HC368 are inverting buffers, where as the MM54/74HC365 and the MM54/ 74HC367 are non-inverting buffers. The MM54/74HC365 and the MM54/74HC366 have two TRI-STATE control inputs (G1 and G2) which are NORed together to control all
six gates. The MM54/74HC367 and the MM54/74HC368 also have two output enables, but one enable (G1) controls 4 gates and the other (G2) controls the remaining 2 gates.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
YTypical propagation delay: 15 ns
YWide operating voltage range: 2V ± 6V
YLow input current: 1 mA maximum
YLow quiescent current: 80 mA maximum (74 Series)
YOutput drive capability: 15 LS-TTL loads
Connection Diagrams |
Dual-In-Line Packages/Top Views |
TL/F/5209 ± 1 |
TL/F/5209 ± 2 |
Order Number MM54HC365 or MM74HC365 |
Order Number MM54HC366 or MM74HC366 |
TL/F/5209 ± 3 |
TL/F/5209 ± 4 |
Order Number MM54HC367 or MM74HC367 |
Order Number MM54HC368 or MM74HC368 |
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation |
TL/F/5209 |
RRD-B30M105/Printed in U. S. A. |
MM74HC365/MM74HC366/MM74HC367/MM74HC368 |
MM54HC365/MM54HC366/MM54HC367/MM54HC368/ |
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) |
b0.5 to a7.0V |
DC Input Voltage (VIN) |
b1.5 to VCCa1.5V |
DC Output Voltage (VOUT) |
b0.5 to VCCa0.5V |
Clamp Diode Current (IIK, IOK) |
g20 mA |
DC Output Current, per pin (IOUT) |
g35 mA |
DC VCC or GND Current, per pin (ICC) |
g70 mA |
Storage Temperature Range (TSTG) |
b65§C to a150§C |
Power Dissipation (PD) |
|
(Note 3) |
600 mW |
S.O. Package only |
500 mW |
Lead Temp. (TL) (Soldering 10 seconds) |
260§C |
DC Electrical Characteristics (Note 4)
Operating Conditions
Supply Voltage (VCC) |
Min |
Max |
Units |
2 |
6 |
V |
|
DC Input or Output Voltage |
0 |
VCC |
V |
(VIN, VOUT) |
|
|
|
Operating Temp. Range (TA) |
|
|
§C |
MM74HC |
b40 |
a85 |
|
MM54HC |
b55 |
a125 |
§C |
Input Rise or Fall Times |
|
|
|
(tr, tf) VCCe2.0V |
|
1000 |
ns |
VCCe4.5V |
|
500 |
ns |
VCCe6.0V |
|
400 |
ns |
|
|
|
|
|
|
TAe25§C |
74HC |
54HC |
|
|
Symbol |
Parameter |
|
|
Conditions |
VCC |
TAeb40 to 85§C |
TAeb55 to 125§C |
Units |
||
|
|
|
|
|
|
Typ |
|
Guaranteed Limits |
|
|
|
|
|
|
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|
|
|
|
|
|
VIH |
Minimum High Level Input |
|
|
|
2.0V |
|
1.5 |
1.5 |
1.5 |
V |
|
Voltage |
|
|
|
4.5V |
|
3.15 |
3.15 |
3.15 |
V |
|
|
|
|
|
6.0V |
|
4.2 |
4.2 |
4.2 |
V |
VIL |
Maximum Low Level Input |
|
|
|
2.0V |
|
0.5 |
0.5 |
0.5 |
V |
|
Voltage** |
|
|
|
4.5V |
|
1.35 |
1.35 |
1.35 |
V |
|
|
|
|
|
6.0V |
|
1.8 |
1.8 |
1.8 |
V |
|
|
|
|
|
|
|
|
|
|
|
VOH |
Minimum High Level Output |
|
VINeVIH or VIL |
|
|
|
|
|
|
|
|
Voltage |
|
lIOUTls20 mA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
|
|
|
|
|
|
4.5V |
4.5 |
4.4 |
4.4 |
4.4 |
V |
|
|
|
|
|
6.0V |
6.0 |
5.9 |
5.9 |
5.9 |
V |
|
|
|
|
|
|
|
|
|
|
|
|
|
VINeVIH or VIL |
|
|
|
|
|
|
||
|
|
|
lIOUTls6.0 mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 |
V |
|
|
|
|
lIOUTls7.8 mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 |
V |
|
VOL |
Maximum Low Level Output |
|
VINeVIH or VIL |
|
|
|
|
|
|
|
|
Voltage |
|
lIOUTls20 mA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
|
|
|
|
|
|
4.5V |
0 |
0.1 |
0.1 |
0.1 |
V |
|
|
|
|
|
6.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
|
|
|
|
|
|
|
|
|
|
|
|
|
VINeVIH or VIL |
|
|
|
|
|
|
||
|
|
|
lIOUTls6.0 mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
|
|
|
|
lIOUTls7.8 mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 |
V |
|
IIN |
Maximum Input Current |
|
VINeVCC or GND |
6.0V |
|
g0.1 |
g1.0 |
g1.0 |
mA |
|
IOZ |
Maximum TRI-STATE Output |
|
VOUTeVCC or GND |
6.0V |
|
g0.5 |
g5.0 |
g10 |
mA |
|
|
Leakage Current |
|
G |
eVIH |
|
|
|
|
|
|
ICC |
Maximum Quiescent Supply |
|
VINeVCC or GND |
6.0V |
|
8.0 |
80 |
160 |
mA |
|
|
Current |
IOUTe0 mA |
|
|
|
|
|
|
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ``N'' package: b12 mW/§C from 65§C to 85§C; ceramic ``J'' package: b12 mW/§C from 100§C to 125§C.
Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89.
2
AC Electrical Characteristics MM54HC365/MM74HC365
VCCe5V, TAe25§C, tretfe6 ns
Symbol |
Parameter |
Conditions |
Typ |
Guaranteed |
Units |
|
Limit |
||||||
|
|
|
|
|
||
|
|
|
|
|
|
|
tPHL, tPLH |
Maximum Propagation |
CLe45 pF |
15 |
22 |
ns |
|
|
Delay |
|
|
|
|
|
|
|
|
|
|
|
|
tPZH, tPZL |
Maximum Output Enable |
RLe1 kX |
29 |
40 |
ns |
|
|
Time |
CLe45 pF |
|
|
|
|
tPHZ, tPLZ |
Maximum Output Disable |
RLe1 kX |
25 |
36 |
ns |
|
|
Time |
CLe5 pF |
|
|
|
AC Electrical Characteristics MM54HC365/MM74HC365
VCCe2.0 ± 6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified)
|
|
|
|
TAe25§C |
74HC |
54HC |
|
|
Symbol |
Parameter |
Conditions |
VCC |
TAeb40 to 85§C |
TAeb55 to 125§C |
Units |
||
|
|
|
|
Typ |
|
Guaranteed Limits |
|
|
|
|
|
|
|
|
|
|
|
tPHL, tPLH |
Maximum Propagation |
CLe50 pF |
2.0V |
35 |
105 |
130 |
150 |
ns |
|
Delay |
CLe150 pF |
2.0V |
45 |
135 |
168 |
205 |
ns |
|
|
CLe50 pF |
4.5V |
14 |
24 |
30 |
36 |
ns |
|
|
CLe150 pF |
4.5V |
17 |
29 |
36 |
45 |
ns |
|
|
CLe50 pF |
6.0V |
11 |
19 |
24 |
28 |
ns |
|
|
CLe150 pF |
6.0V |
15 |
24 |
30 |
36 |
ns |
tPZH, tPZL |
Maximum Output Enable |
RLe1 kX |
|
|
|
|
|
|
|
Time |
CLe50 pF |
2.0V |
90 |
230 |
287 |
345 |
ns |
|
|
CLe150 pF |
2.0V |
98 |
245 |
306 |
367 |
ns |
|
|
CLe50 pF |
4.5V |
31 |
44 |
55 |
66 |
ns |
|
|
CLe150 pF |
4.5V |
38 |
53 |
66 |
80 |
ns |
|
|
CLe50 pF |
6.0V |
25 |
35 |
43 |
52 |
ns |
|
|
CLe150 pF |
6.0V |
29 |
41 |
51 |
62 |
ns |
tPHZ, tPLZ |
Maximum Output Disable |
RLe1 kX |
2.0V |
58 |
175 |
218 |
260 |
ns |
|
Time |
CLe50 pF |
4.5V |
26 |
44 |
55 |
66 |
ns |
|
|
|
6.0V |
22 |
37 |
46 |
55 |
ns |
|
|
|
|
|
|
|
|
|
tTHL, tTLH |
Maximum Output Rise |
CLe50 pF |
2.0V |
25 |
60 |
75 |
90 |
ns |
|
and Fall Time |
|
4.5V |
7 |
12 |
15 |
18 |
ns |
|
|
|
6.0V |
6 |
10 |
13 |
15 |
ns |
|
|
|
|
|
|
|
|
|
CPD |
Power Dissipation |
Any Enabled |
|
45 |
|
|
|
pF |
|
Capacitance (Note 5) |
A Input |
|
|
|
|
|
|
|
|
Any Disabled |
|
8 |
|
|
|
pF |
|
|
A Input |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CIN |
Maximum Input |
|
|
5 |
10 |
10 |
10 |
pF |
|
Capacitance |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
COUT |
Maximum Output |
|
|
10 |
20 |
20 |
20 |
pF |
|
Capacitance |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC.
Truth Table
'HC365
|
|
|
Inputs |
|
Output |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
G1 |
|
G2 |
A |
Y |
|||
|
|
|
|
|
|
||
|
H |
|
X |
X |
Z |
||
|
X |
|
H |
X |
Z |
||
|
L |
|
L |
H |
H |
||
|
L |
|
L |
L |
L |
||
|
|
|
|
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|
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3