National Semiconductor DS90CR215, DS90CR216 Technical data

DS90CR216

March 1999

DS90CR215/DS90CR216

+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel

Link - 66 MHz

General Description

The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.

The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.

Features

nSingle +3.3V supply

nChipset (Tx + Rx) power consumption <250 mW (typ)

nPower-down mode (<0.5 mW total)

nUp to 173 Megabytes/sec bandwidth

nUp to 1.386 Gbps data throughput

nNarrow bus reduces cable size

n290 mV swing LVDS devices for low EMI

n+1V common mode range (around +1.2V)

nPLL requires no external components

nLow profile 48-lead TSSOP package

nRising edge data strobe

nCompatible with TIA/EIA-644 LVDS standard

nESD Rating > 7 kV

nOperating Temperature: −40ÊC to +85ÊC

Block Diagrams

DS90CR215

DS90CR216

DS012909-1	DS012909-27
Order Number DS90CR215MTD	Order Number DS90CR216MTD
See NS Package Number MTD48	See NS Package Number MTD48

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

MHz 66-Link Channel Bit-21 LVDS Strobe Data Edge Rising 3V.+3 DS90CR215/DS90CR216

© 1999 National Semiconductor Corporation

DS012909

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Pin Diagrams

	DS012909-21	DS012909-22
DS90CR215		DS90CR216

Typical Application

DS012909-23

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (VCC)	−0.3V to +4V
CMOS/TTL Input Voltage	−0.3V to (V CC + 0.3V)
CMOS/TTL Output Voltage	−0.3V to (V CC + 0.3V)
LVDS Receiver Input Voltage	−0.3V to (V CC + 0.3V)
LVDS Driver Output Voltage	−0.3V to (V CC + 0.3V)
LVDS Output Short
Circuit Duration	Continuous
Junction Temperature	+150ÊC
Storage Temperature Range	−65ÊC to +150ÊC
Lead Temperature
(Soldering, 4 sec.)	+260ÊC

Maximum Package Power Dissipation @ +25ÊC

MTD48 (TSSOP) Package:

DS90CR215	1.98 W
DS90CR216	1.89 W
Package Derating
DS90CR215	16 mW/ÊC above +25ÊC
DS90CR216	15 mW/ÊC above +25ÊC
ESD Rating
(HBM, 1.5 kΩ, 100 pF)	> 7 kV

Recommended Operating

Conditions

	Min	Nom	Max	Units
Supply Voltage (VCC)	3.0	3.3	3.6	V
Operating Free Air
Temperature (TA)	−40	+25	+85	ÊC
Receiver Input Range		0	2.4	V
Supply Noise Voltage (VCC)			100 mVPP

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol	Parameter			Conditions	Min	Typ	Max	Units
CMOS/TTL DC SPECIFICATIONS
VIH	High Level Input Voltage				2.0		VCC	V
VIL	Low Level Input Voltage				GND		0.8	V
VOH	High Level Output Voltage		I OH = −0.4 mA		2.7	3.3		V
VOL	Low Level Output Voltage		I OL = 2 mA			0.06	0.3	V
VCL	Input Clamp Voltage		I CL = −18 mA			−0.79	−1.5	V
IIN	Input Current		V IN = VCC, GND,			±5.1	±10	µA
		2.5V or 0.4V
IOS	Output Short Circuit Current		V OUT = 0V			-60	−120	mA
LVDS DRIVER DC SPECIFICATIONS
VOD	Differential Output Voltage		R L = 100Ω		250	290	450	mV
VOD	Change in V OD between						35	mV
	Complimentary Output States
VOS	Offset Voltage (Note 4)				1.125	1.25	1.375	V
VOS	Change in V OSbetween						35	mV
	Complimentary Output States
IOS	Output Short Circuit Current		V OUT = 0V,			−3.5	−5	mA
		R L = 100Ω
IOZ	Output TRI-STATE® Current					±1	±10	µA
			PWR DWN	= 0V,
		V OUT = 0V or VCC
LVDS RECEIVER DC SPECIFICATIONS
VTH	Differential Input High Threshold		V CM = +1.2V				+100	mV
VTL	Differential Input Low Threshold				−100			mV
I IN	Input Current		V IN = +2.4V, VCC = 3.6V				±10	µA
		V IN = 0V, VCC = 3.6V					±10	µA

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Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol	Parameter			Conditions		Min	Typ	Max	Units
TRANSMITTER SUPPLY CURRENT
ICCTW	Transmitter Supply Current		RL = 100Ω,		f = 32.5 MHz		31	45	mA
	Worst Case (with Loads)	CL = 5 pF,
		Worst Case
					f = 37.5 MHz		32	50	mA
		Pattern
		(Figures 1, 2),
		TA = −10ÊC to			f = 66 MHz		37	55	mA
		+70ÊC
		RL = 100Ω,			f = 40 MHz		38	51	mA
		CL = 5 pF,
		Worst Case
		Pattern
					f = 66 MHz		42	55	mA
		(Figures 1, 2),
		TA = −40ÊC to
		+85ÊC
ICCTZ	Transmitter Supply Current						10	55	µA
			PWR DWN	= Low
	Power Down	Driver Outputs in TRI-STATE
		under Powerdown Mode
RECEIVER SUPPLY CURRENT
ICCRW	Receiver Supply Current Worst		CL = 8 pF,		f = 32.5 MHz		49	65	mA
	Case	Worst Case
		Pattern			f = 37.5 MHz		53	70	mA
		(Figures 1, 3),
		TA = −10ÊC to			f = 66 MHz		78	105	mA
		+70ÊC
		CL = 8 pF,			f = 40 MHz		55	82	mA
		Worst Case
		Pattern
		(Figures 1, 3),			f = 66 MHz		78	105	mA
		TA = −40ÊC to
		+85ÊC
ICCRZ	Receiver Supply Current Power						10	55	µA
			PWR DWN	= Low
	Down	Receiver Outputs Stay Low during
		Powerdown Mode

Note 1: ªAbsolute Maximum Ratingsº are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of ªElectrical Characteristicsº specify conditions for device operation.

Note 2: Typical values are given for VCC = 3.3V and TA = +25ÊC.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and VOD).

Note 4: VOS previously referred as VCM.

Transmitter Switching Characteristics

Over recommended operating supply and −40ÊC to +85ÊC ranges unless otherwise specified

Symbol	Parameter		Min	Typ	Max	Units
LLHT	LVDS Low-to-High Transition Time (Figure 2)			0.5	1.5	ns
LHLT	LVDS High-to-Low Transition Time (Figure 2)			0.5	1.5	ns
TCIT	TxCLK IN Transition Time (Figure 4)				5	ns
TCCS	TxOUT Channel-to-Channel Skew (Figure 5)			250		ps
TPPos0	Transmitter Output Pulse Position for	f = 40 MHz	−0.4	0	0.4	ns
	Bit0 (Note 7) (Figure 16)
TPPos1	Transmitter Output Pulse Position for		3.1	3.3	4.0	ns
	Bit1
TPPos2	Transmitter Output Pulse Position for		6.5	6.8	7.6	ns
	Bit2

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Transmitter Switching Characteristics (Continued)

Over recommended operating supply and −40ÊC to +85ÊC ranges unless otherwise specified

Symbol	Parameter		Min	Typ	Max	Units
TPPos3	Transmitter Output Pulse Position for		10.2	10.4	11.0	ns
	Bit3
TPPos4	Transmitter Output Pulse Position for		13.7	13.9	14.6	ns
	Bit4
TPPos5	Transmitter Output Pulse Position for		17.3	17.6	18.2	ns
	Bit5
TPPos6	Transmitter Output Pulse Position for		21.0	21.2	21.8	ns
	Bit6
TPPos0	Transmitter Output Pulse Position for	f = 66 MHz	−0.4	0	0.3	ns
	Bit0 (Note 6) (Figure 16)
TPPos1	Transmitter Output Pulse Position for		1.8	2.2	2.5	ns
	Bit1
TPPos2	Transmitter Output Pulse Position for		4.0	4.4	4.7	ns
	Bit2
TPPos3	Transmitter Output Pulse Position for		6.2	6.6	6.9	ns
	Bit3
TPPos4	Transmitter Output Pulse Position for		8.4	8.8	9.1	ns
	Bit4
TPPos5	Transmitter Output Pulse Position for		10.6	11.0	11.3	ns
	Bit5
TPPos6	Transmitter Output Pulse Position for		12.8	13.2	13.5	ns
	Bit6
TCIP	TxCLK IN Period (Figure 6)		15	T	50	ns
TCIH	TxCLK IN High Time (Figure 6)		0.35T	0.5T	0.65T	ns
TCIL	TxCLK IN Low Time (Figure 6)		0.35T	0.5T	0.65T	ns
TSTC	TxIN Setup to TxCLK IN (Figure 6)		2.5			ns
THTC	TxIN Hold to TxCLK IN (Figure 6)		0			ns
TCCD	TxCLK IN to TxCLK OUT Delay @ 25ÊC,VCC=3.3V		3	3.7	5.5	ns
	(Figure 8)
TPLLS	Transmitter Phase Lock Loop Set (Figure 10)				10	ms
TPDD	Transmitter Powerdown Delay (Figure 14)				100	ns

Receiver Switching Characteristics

Over recommended operating supply and −40ÊC to +85ÊC ranges unless otherwise specified

Symbol	Parameter		Min	Typ	Max	Units
CLHT	CMOS/TTL Low-to-High Transition Time (Figure 3)			2.2	5.0	ns
CHLT	CMOS/TTL High-to-Low Transition Time (Figure 3)			2.2	5.0	ns
RSPos0	Receiver Input Strobe Position for Bit 0 (Note 7)(Figure 17)	f = 40 MHz	1.0	1.4	2.15	ns
RSPos1	Receiver Input Strobe Position for Bit 1		4.5	5.0	5.8	ns
RSPos2	Receiver Input Strobe Position for Bit 2		8.1	8.5	9.15	ns
RSPos3	Receiver Input Strobe Position for Bit 3		11.6	11.9	12.6	ns
RSPos4	Receiver Input Strobe Position for Bit 4		15.1	15.6	16.3	ns
RSPos5	Receiver Input Strobe Position for Bit 5		18.8	19.2	19.9	ns
RSPos6	Receiver Input Strobe Position for Bit 6		22.5	22.9	23.6	ns

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