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Passport 2®/Passport 2 LT™ Service Manual0070-10-0441
Table of Contents
Contents ........................................................................................................................................................ v
Theory of Operation ......................................................................................................... 2 - 1
CPU Control Module ....................................................................................................................................... 2 - 2
MPC860T Host CPU, U2 .......................................................................................................................... 2 - 2
Serial Communications Channels............................................................................................................... 2 - 2
Fast Ethernet Controller............................................................................................................................. 2 - 3
DRAM Memory, U8, U10......................................................................................................................... 2 - 4
RTC with CPU Supervisor.......................................................................................................................... 2 - 4
3.3 Volt Power........................................................................................................................................ 2 - 9
-12 Volts DC ........................................................................................................................................... 2 - 9
Communications Processor and Support ..................................................................................................... 2 - 9
D/A Analog Outputs................................................................................................................................ 2 - 10
Analog Inputs.......................................................................................................................................... 2 - 10
Keypad and Rotary Knob ......................................................................................................................... 2 - 10
Control Functions..................................................................................................................................... 2 - 11
Module Bus ............................................................................................................................................ 2 - 11
Front End Module ........................................................................................................................................... 2 - 12
Power Supply.......................................................................................................................................... 2 - 12
Communication Isolation .......................................................................................................................... 2 - 12
Data Acquisition...................................................................................................................................... 2 - 12
Analog to Digital Converter ...................................................................................................................... 2 - 13
Microcontroller and Data Processing.......................................................................................................... 2 - 13
I/O Ports and Software Register Programming ............................................................................................ 2 - 15
Signal Acquisition.................................................................................................................................... 2 - 16
Lead Fault Detection................................................................................................................................. 2 - 16
Data Packets........................................................................................................................................... 2 - 20
TFT Display / Monochrome Interface Board and Keypad Board (P/N 0670-00-0686 or 0670-00-0726).................. 2 - 21
The EPLD Interface to the CPU Board VIA SPI .............................................................................................. 2 - 21
Video display connections ........................................................................................................................ 2 - 21
Patient and Power Isolation....................................................................................................................... 2 - 29
Provide mating for ECG, Temperature and two IBP connectors ......................................................................2-29
Patient and Power Isolation....................................................................................................................... 2 - 31
Provide Mating for ECG, Temperature and two IBP connectors......................................................................2-31
Power Supply ................................................................................................................................................. 2 - 36
Part Numbers 0014-00-0250 and 0014-00-0190-01 .................................................................................. 2-36
Part Number 0014-00-0251..................................................................................................................... 2 - 37
Communication Isolation.................................................................................................................................. 2 - 39
El Display Interface Board................................................................................................................................ 2 - 40
Assembly and Schematic Diagrams................................................................................... 4 - 1
Replacement Parts ............................................................................................................ 5 - 1
Parts List Front Housing .................................................................................................................................... 5 - 5
Parts List Rear Housing..................................................................................................................................... 5 - 15
Communication Ports Parts List .......................................................................................................................... 5 - 25
Passport 2®/Passport 2 LT™ Service Manual0070-10-0441iii
Warning and Guidelines ................................................................................................................................. 6 - 2
Test Equipment and Special Tools Required........................................................................................................ 6 - 2
Diagnostic Test Menu ............................................................................................................................... 6 - 3
Keypad / Control Knob Test ..................................................................................................................... 6 - 4
Recorder Test .......................................................................................................................................... 6 - 5
Pixel Test ................................................................................................................................................ 6 - 6
Color Test............................................................................................................................................... 6 - 7
IBP 1 and IBP 2 Verification ...................................................................................................................... 6 - 20
Temperature Verification........................................................................................................................... 6 - 20
User Preventive Maintenance Introduction .......................................................................................................... 7 - 2
Care And Cleaning Of The Monitor .................................................................................................................. 7 - 3
Care and Cleaning of SpO
Cleaning CO
Sensors, Adapters And Sampling Components.............................................................................. 7 - 3
2
Sterilization and Cleaning of Reusable Cuffs ...................................................................................................... 7 - 4
Battery Replacement and Maintenance .............................................................................................................. 7 - 4
Recorder Paper Replacement............................................................................................................................ 7 - 5
Care and Storage of Thermal Chart Paper ......................................................................................................... 7 - 5
How to Get Help ............................................................................................................................................ 7 - 6
This Service Manual is intended as a guide for technically qualified personnel during repair
and calibration procedures. The information has been divided into the eight chapters listed
above. A detailed table of contents is provided on the first page of each chapter.
This publication may have been updated to reflect product design changes and/or manual
improvements. Any such changes to this manual would be accomplished by supplying
replacement pages and instructions for inserting or affixing them into the manual.
Note
Unauthorized servicing may void the remainder of the warranty. Check with the factory or
with a local authorized representative to determine the warranty status of a particular
instrument.
Warning
The Passport 2 operates on line voltages. Therefore, an electric shock hazard may exist
when the instrument covers are removed. Repair and calibration procedures should only be
performed by qualified personnel who proceed with care and follow proper servicing
techniques. Warnings are given in Chapters 4 and 7, as well as in other appropriate
locations.
Passport 2®/Passport 2 LT™ Service Manual0070-10-0441v
IntroductionWar nin g
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vi0070-10-0441Passport 2®/Passport 2 LT™ Service Manual
2.14 NEC 10.4” Display/Keypad Interface Board .............................. 2-43
2.15 Passport 2 NIBP Module
(P/N 0670-00-0730 or 0670-00-0746-01) .............................. 2-45
2.16 SpO2 Interface Board (Nellcor, Nell-3™ and Masimo) ................ 2-54
2.17 Power Supply ........................................................................... 2-55
2.18 SpO2 UART Serial Interface ...................................................... 2-56
Passport 2®/Passport 2 LT™ Service Manual0070-10-04412 - 1
CPU Control ModuleTheory of Operation
2.1CPU Control Module
Overview
This board has the main program and system controller for the Passport 2. It also contains
the Communications Coprocessor, PCMCIA interface, RTC, Audio, CRT/LCD controller,
Serial Channels and module bus interface connectors.
2.1.1MPC860T Host CPU, U2
Device U2, is a MPC860T Microcontroller, which contains a PowerPC core, 32 bit address
and data bus, Memory Controller (8 banks), general purpose timers, System Integration Unit
(SIU), Multi-Level Interrupts, Communications Processor module, SPI port, 100 Mbit Ethernet
Controller, and a Dual PCMCIA interface. Clock oscillator Y1, 5 Mhz, is multiplied by the
MPC860T's PLL circuit to achieve the 45MHz for Passport 2. There are six serial channels,
of which five are used. Two are full RS-232 compliant and are used for external
communications: one is used for the Recorder module; one is used to connect to the
Instrument Radio; and one is used for the Audio Synthesizer which goes to the Keypad/
Display connector.
There are eight programmable chip select/wait state control groups, only six are used. They
are listed below.
The power-on reset to the microcontroller is generated by U14, MAX814L CPU Supervisor.
The signal generated is active low for 140ms. PORESET* is generated whenever both VCC
rises from 0 to 4.75 volts and the 3.3V rises from 0 to 2.75V. The PORESET* signal is
distributed to other components that require a power on reset by using a spoke distribution
with series resistors instead of a daisy chain to better balance the signal paths. The U1 CPLD
in turn generates a HRESET* signal and a buffered BRESET* signal that is used to reset all
external components that require a reset other than PORESET*.
All high speed clock signal and control lines have series terminating resistors to reduce EMI.
2.1.2Serial Communications Channels
There are four serial communications channels called SCC's that are part of the MPC860T's
Communication Processor Module. The following describes the function of each of them.
SCC1 - This channel is assigned to external communication use. It is buffered (U49) to RS232 levels before connection to the docking connector which is part of the base station or
comm-port system. SCC1 will operate in the standard UART mode with all hardware control
lines available.
SCC2 - This channel is assigned to external communication use. It is buffered (U50) to RS232 levels before connection to the docking connector which is part of the base station or
comm-port system. SCC2 will operate in the standard UART mode with all hardware control
lines available.
SCC3 - This channel is assigned to the Instrument Radio on connector J15.
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Theory of OperationCPU Control Module
SCC4 - This channel is assigned to the serial Recorder. It operates at 3V logic levels and is
connected to Recorder Connector J8. SCC4 will operate in the standard UART mode with all
hardware control lines available.
There are two Serial management Channels called SMC's that are part of the MPC860T's
Communication Processor Module. The following describes the function of each of them.
SMC1 - Not used. Pins used as general purpose I/O.
SMC2 - This channel is assigned to Audio. The audio circuit is composed of three integrated
circuits, Wave Table Music Synthesizer, a 24 Bit Stereo D/A Converter and a one watt
Power Amplifier. It operates at 3V logic levels and is connected to the Keypad/Display J5.
SMC2 will operate in the standard UART mode with no hardware control lines available.
2.1.3Fast Ethernet Controller
The MPC860T includes a 10/100 BASE-T Ethernet channel. The fast Ethernet Controller is
implemented independently providing fast Ethernet connectivity without effecting the
performance of the CPM. Full duplex 100 Mbps operation is supported at a system clock of
45 Mhz and higher. A 25 Mhz system clock supports 10 Mbps operation or half duplex 100
Mbps operation.
2.1.4Power-On Reset, U14
The Power-On reset signal is created by components U14, R1, R12, R13 and Q4. The active
low power-on reset signal required by the MPC860T, as well as other components that
require reset, is generated for both logic voltages 5V and 3.3V. This keeps the CPU in reset
until the power for all the digital components are above minimum operating levels. The reset
signal PORESET is distributed in a spoke pattern with the following references, PORESET*,
POREST2*, PORESET3*, PORESET4*, and PORESET5*. The duration of the power-on reset
signal is 140ms min. The MPC860T requires only 3us minimum after power is stable and all
other components that receive this reset require less than 1ms.
Program code is stored in eight flash memory devices configured as 2M x 32 bytes in 2
banks for a total of 16 Mbytes. These devices allow for in circuit programming via the
MPC860T background debug mode (BDM). There are no special programming voltages,
programming is done using the existing 3.3Volts.
This is one way to allow for initial factory programming as well as software upgrades.
Alternately a boot loader can be programmed into the flash parts using the BDM, and the
initial software and all upgrades can be programmed into the flash by the boot loader from
a PCMCIA memory card.
The Flash devices are configured and connected to the processor in the byte mode. The
specified access time for the Flash devices is 90nsec and will therefore require 4 wait states.
Upon reset, the MPC860T provides a boot chip select CS(0) which is hard wired to the flash
memory to allow boot of the operating software. The board support software must execute
prior to any other external or internal hardware, in order to function properly.
Passport 2®/Passport 2 LT™ Service Manual0070-10-04412 - 3
CPU Control ModuleTheory of Operation
The Flash devices are provided a buffered reset by FET Q9 and associated components. This
reset signal is generated from the MPC860T's HRESET. The reset is required to place the
Flash devices' internal state machine in a known state after power is applied for either
fetching or programming.
Bank decoding is performed by a sub-circuit of CPLD U1, and is dependent on the state of
Address line A(8) in conjunction with active CS0*.
2.1.6DRAM Memory, U8, U10
This memory is made up of two 4M x 16 devices which form a 4M x 32 byte memory array.
These memories are volatile as well as requiring special timing and control signals, RAS*
and CAS* to operate. The type of DRAM is Fast Page Mode with an access time of 50nsec.
The special timing signals required are generated by an internal timing circuit contained in
the MPC860T. This timing generator is called Universal Programmable Machine A (UPMA).
There is another one called Universal Programmable Machine B (UPMB), which is not used.
The universal programmable machines are flexible interfaces that connect to a wide range of
memory devices, such as Fast Page Mode Dram's. At the heart of the UPM is an internal
memory RAM that specifies the logical value driven on the external memory controller pins
for each clock cycle. Each word in the RAM array provides bits that allow a memory access
to be controlled with a resolution of one quarter of the external bus clock period on the byteselect and chip-select lines. The RAM array contains 64, 32 bit words. The internal signal
timing generator loads the RAM word from the RAM array to drive the general-purpose lines,
byte-selects, and chip-selects.
The UPM RAM array is to be loaded by the board support software at power-on. The
following is UPM RAM array values to support 50nsec Fast Page Mode DRAM with the
processor operating at 50MHz.
UPMA Initializations for 50nsec DRAM's @ 50Mhz.
2.1.7RTC with CPU Supervisor
The Real Time Clock module, BQ4847, integrates a time of day clock, a 100 year calendar,
a CPU supervisor, a battery and a crystal in a 28 pin DIP module. There are 16 registers
which contain real-time clock and alarm functions. The clock has an accuracy of +/-1 minute
per month. The duration of the power-on reset signal is 100ms min. The MPC860T requires
only 3us minimum.
Using the BQ4747’s CE out and battery voltage out, Vout, static RAM U9 is made to be nonvolatile. The internal battery powers the real time clock and maintains SRAM information in
the absence of system voltage. When an out of tolerance (4.3 to 4.5 volt) condition is
detected the BQ4747 generates an interrupt warning. The interrupt is fed to the IRQ0 NMI
input on the MPC860T. This will allow 90us min. to save any data to the non-volatile SRAM.
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Theory of OperationCPU Control Module
2.1.8Battery Backup SRAM, U9
The SRAM is configured as 128K x 8 bits and is used to store system configuration settings.
These settings are required to be non-volatile, therefore the SRAM is battery backed-up when
system power is removed. This is achieved by the battery output that is contained in the RTC
module, U7, and is outputted on pin 1.
2.1.9Dual Port RAM, U604, U777
There is a high speed 2K x 8 Dual Port RAM with internal logic for inter-processor
communications. The device has two independent ports with separate control, address, and
I/O pins that permit independent asynchronous access for reads to any location in memory.
However, an attempt by one of the processors to access ('READ' or 'WRITE') an address
location at the same time the other processor is attempting to access the identical location
results in a 'BUSY' condition, and results in a 'write inhibit' to whichever side asserted the
chip enable last (Not all such accesses will be 'WRITE LEFT/WRITE RIGHT'). The 'BUSY'
condition is not reported to either processor in this implementation, and therefore, the
software must be designed so as to avoid the possibility of concurrent access by both
processors to an identical location.
The device is used for inter-communication between the main processor, MPC860T (U2) and
the communication processor MCF5282 (U22). Refer to the Module Bus Protocol
Specification (See Appendix).
The implementation uses the interrupt function. There are two flags, one for each side of the
DPRAM. A memory location within the DPRAM is assigned to each flag. The interrupt line to
the MPC860T is asserted when the MCF5282 writes to memory location CS1 + 0x0000
07FE. In order to reset this interrupt flag, the MPC860T must access memory location CS3
+0x0000 0FFE. Similarly, the interrupt line to the MCF5282 is asserted when the MPC860T
writes to memory location CS3 + 0x0000 0FFF. In order to reset this interrupt flag, the
MCF5282 must access memory location CS1 + 0x0000 07FF. Please note that in addition to
the flag functions described above, these two addresses are valid memory locations and may
be used for message passing.
A 5V to 3.3V conversion is performed with U777. This is to protect the DPRAM, which
cannot have 5V logic on any of its pins, even if it is not accessing the bus.
2.1.10Audio Generator Circuit, U12, U27, U13
The audio circuit is composed of three integrated circuits, Wave Table Music Synthesizer, a
24 Bit Stereo D/A Converter and a one watt Power Amplifier.
U12 is a complete general MIDI wave table synthesizer on a single integrated circuit. The
MIDI interpreter, synthesis engine, effects processing, and all memory are included on chip.
The device receives a standard serial MIDI data stream at 31.25 +/-1% kbits/s, and outputs
a stereo 16 bit digital audio stream at 44.1kHz.
Passport 2®/Passport 2 LT™ Service Manual0070-10-04412 - 5
CPU Control ModuleTheory of Operation
The digital outputs LRCLK and SOUT from the U12 provide the clock and the digital audio
data input to the stereo D/A converter. This is a complete stereo digital to analog system
including digital interpolation, 128X third order delta-sigma D/A conversion, digital deemphasis and analog filtering. The de-emphasis circuit is not used in this application.
The stereo outputs from the U27 are summed together and is fed to the power amplifier U13,
which is a bridge connected audio power amplifier capable of delivering 1watt of
continuous average power to an 8 ohm speaker load. The circuit is optimized for a
frequency range of 100Hz to 10KHz.
2.1.11Module ID, U44
There is a Module ID port implemented by U44 that is used to read the ID code from any
device that is connected to Docking connector, J9. These devices can be either a Base Station
or Comm Ports. Each of these devices has a unique code. The base station is hot swappable,
while the Comm Ports are not hot swappable. When any base station is connected or
removed from the Docking connector J9 using live insertion, an interrupt IRQ4* is generated.
When a Comm Port, which is not hot swappable, is powered up with a Passport 2
monitor, the module ID is read by software, and is in the flow of the start-up code. This
reading of the module ID upon power up is automatic and is not dependent on whether there
is an IRQ4* or not, or if a base station or Comm Port is connected. Therefore a duplicate
IRQ4*, which may be generated by the modules upon power up, is redundant.
This IRQ4* interrupt is falling edge triggered and can be sourced only when IRQB* is
previously low and IRQA* then follows and goes low. The state diagram for the IRQA* /
IRQB* logic is such that IRQB* must be low prior to an IRQA* falling edge. In the Comm
Ports, IRQB* is tied to GND and IRQA* is driven low after the circuitry becomes active, thus
the condition is met. In the base station, IRQB* is driven low whenever there is power
applied to the base station, and IRQA* is driven low whenever the base station is powered
AND the monitor's 3.3V power is within regulation, again, meeting the condition.
IRQA* and IRQB* (on J9-17, J9-67) are both generated external to the CPU board.
Components involved in the state control logic on the CPU board, affecting the rise time of
IRQA* and IRQB*, are components R185, R174, C427, and D9. U64 is used to generate
IRQ4*.
The signal that enables U44 to drive the Module ID field onto the data bus is MODIDCS*,
active low. It is generated by a sub-circuit of CPLD U1 by decoding Address lines A[18:20]
in conjunction with an active CS3*.
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Theory of OperationCPU Control Module
2.1.12Tone Generator, U39
The tone generator is implemented using an eight bit microcontroller. The device generates a
tone signal of 909Hz for a duration of 300ms. The tone is generated in response to the
following input conditions:
1. When the system is first turned on, the level of the MPC860T's BRESET* (same as
HRESET*) signal is monitored. If this level is detected as high, the tone is generated.
2. When an active low status signal input is detected, the tone is generated. The status
signal tone 769Hz for a duration of 300ms is generated by the MPC860T on Port A, bit
4 (PA4). The signal can be repeated as required in order to create a series of tones.
2.1.13LCD/CRT VGA Controller, U16
The LCD/VGA controller is a SPC8110 with an integrated RAMDAC, PLL Bit Block Transfer
engine and a VL Local Bus interface. It is capable of displaying 256 colors. Support for video
modes of 640 X 480 and 800 X 600 is required. The display controller needs to be able to
drive a TFT color LCD (10.4" or 12.1") (single scan), or EL panel (dual scan), or
Monochrome LCD Passive (dual scan) and an external VGA color CRT simultaneously.
The display system consists of the LCD/CRT VGA controller (U16), clock oscillator (U65), the
programmable clock synthesizer (Y2 & U66), and video display RAM (U18 & U19). The
signals required by the various display panels are routed to the Keypad/Display board
through connector J5. The various Keypad/Display boards have specific interface connectors
for each display type, requiring only a simple one-to-one cable assembly. The display panel
identifies itself to the CPU module by connecting selected pins in the VIDSEL[4:1] field
directly to the power net. These signals are pulled down to 3VGND on the CPU module
through 33.2K resistors, and their assigned value is then read, in order to identify the panel
type.
2.1.14PCMCIA Interface
The PCMCIA interface is a dual interface called Socket A and Socket B. The PCMCIA cards
plug into a dual stacked connector assembly, J14. The MPC860T's PCMCIA host adapter
module provides all the control logic for each PCMCIA socket interface and requires only
power switching logic and buffering. The additional external buffering allows the PCMCIA
host adapter module to support up to two PCMCIA sockets and provide electrical isolation.
Because the PCMCIA interface specification was designed around the Intel (Little Endian)
method of storing 16 bit words, a byte swapping scheme had to be employed in order to
conform to the standard. Motorola follows the Big Endian method.
2.1.15Serial EEPROM
The memory is made up of 512 bytes of non-volatile memory. U45 is a dip part and is
socketed to allow programming the memory with an external programmer. This device is
used to store network settings. Communications from the device is done via the MPC860T's
SPI interface. To select this SPI device the MPC860T's, SPISEL signal (PB31) should be set to
logic '0'.
Passport 2®/Passport 2 LT™ Service Manual0070-10-04412 - 7
CPU Control ModuleTheory of Operation
2.1.16CO Interface Connector, J4
This connector connects the Communications Processor Module Bus to the External Parameter
Module. In addition power (+5Vdc and +12V2) and ground are provided. The digital
signals are protected from ESD by capacitors C489 to C494.
2.1.17Recorder Interface
The recorder interface (J8) is a serial interface which is 8 bit, 1 stop bit, no parity and a
baud rate of 38.4K. The recorder interface is implemented using the MPC860T SCC4.
The recorder is controlled by sending a series of software commands along with data over
the serial interface. The recorders electronics process the incoming commands and data and
send print information to the print head.
Hardware handshaking is provided using the RTS*/CTS* control lines. Handshaking signals
are used to control the transmission of data to the recorder and to ensure that the MPC860T
does not send another command until the current one has been processed.
The RECRST* signal is used to reset the recorder. This signal is an active low output from
PB(16) of the MPC860T and is a software control function.
There is an additional signal which is located on the connector, IRQ3*, which indicates
when data can be sent.
This connector also provides an interface to the fan for control and monitoring. There is a
control line from the MPC860T to turn the fan on or off and a status signal that indicates if its
functioning.
2.1.18CO2 Interface Connector, J23
This connector connects the Communications Processor Module Bus to the external CO2
module. In addition power (+5 Vdc and +12V2) and ground are provided. The digital
signals are protected from ESD by capacitors C136 to C139.
2.1.19NIBP Interface Connector, J25
This connector connects the Communications processor module bus to the external NIBP
module. In addition power (+5 Vdc, +12V2) and ground are provided.
2.1.20Defib Connector, J24
This connector provides the interface to an external Defibrillator. SMC1 is provided if serial
communications is necessary. There is a provision to accept a logic signal that is monitored
by input PB(14) on the MPC860T. There is a provision for an analog input signal that is fed
to the 10 bit A/D converter that is contained with the Communication processor (916X1). In
addition there is a re-created analog output (ECG_OUT) of the ECG waveform and a
ECG_SYNC signal which is the E trigger from the front end electronics. The ECG_SYNC
signal which is the E trigger from the front end electronics or ECG_SYNC created by the 12
lead communications data from the Mortara card within the MPC860T. The source is
controlled by the MPC860T. All signals are filtered with T-Pole filter devices.
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Theory of OperationCPU Control Module
2.1.21SYNC Connector, J22
This connector provides the interface to an external device. There is a provision for an
analog input signal that is fed to the 10 bit A/D converter that is contained with the
Communication processor (916X1). In addition there is a re-created analog output
(ECG_OUT) of the ECG waveform and blood pressure (IBP_OUT).
2.1.22Docking Connector, J9
The docking interface connector provides the interface between the CPU Control module and
the Base Station or a Comm-Port. The main purpose of the Base Station or Comm-Port is to
provide interface connectors and some interface circuitry that is not part of the CPU Control
module. It is not feasible or practical to include all the connectors on the CPU Control module
itself. The signal groups that are part of the docking interface are shown in the table below:
2.1.233.3 Volt Power
The 3.3 Vdc is generated by Synchronous Step-Down Power Supply Controller U47
(MAX767) and associated discrete components. The input to the power supply controller is
+5 Vdc and its output is +3.3 Vdc +/-5% at 750ma. The controller operates a frequency of
300 Khz. The current sense resistor (R32) is connected to the controller using a Kelvin
connection (no current flow in sense lines). The current limit is controlled by current sense
resistor R32.
2.1.24-12 Volts DC
There is a limited requirement for -12 Vdc @ 30 ma max. The supply voltage was created by
using power inverter U51 (LTC1144) operating at 10KHz. This device takes the +12V1 as
an input and generates -12 Vdc +/- 10% as an output. The -12 Vdc is used by RS-232
buffers U49 and U50 as well as Op-Amp U101.
2.1.25Communications Processor and Support
The Communications Processor is U22, a Motorola MCF5282 microcontroller operating in
master mode. The board pulls CPRCON* low, which causes the processor to enter this mode
as it comes out of reset. The internal 64.0 MHz clock is generated by the internal synthesizer
from a 8.000 MHz reference crystal, Y600. The crystal operates with roughly sinusoidal
waveforms, and therefore generates less EMI than a square-wave oscillator module. To
further minimize EMI and avoid the need for external pull up resistors, all unneeded dynamic
I/O pins are set as outputs and disabled. This is performed at initial software boot up. This
also helps reduce power dissipation.
The purpose of the Communications Processor is to communicate with Passport 2
measurement modules such as NIBP, Front End, etc. The communications is handled over a
RS-485 module bus, where the Communications Processor is the master and everyone else is
a slave. This processor also handles scanning the front panel keypad, rotary knob, and
updating its LEDs.
Passport 2®/Passport 2 LT™ Service Manual0070-10-04412 - 9
CPU Control ModuleTheory of Operation
2.1.26D/A Analog Outputs
There are two analog outputs for recreation of the ECG waveform and IBP measurement.
Both analog signals are created using a dual 12-bit D/A, U724 and Op-Amp, U701. The
required 4.096V reference is supplied by U638.
The ECG_OUT channel is composed of half of U701. The first stage is a low pass filter with
a gain of 2 and a level shift to allow a maximum output swing of ± 4.096V. The second
stage provides a gain of 1.25. The IBP_OUT channel is composed of half of U701. The first
stage is a low pass filter with a gain of 2 and a level shift to allow a maximum output swing
of ± 4.096V. The second stage provides a gain of 1.25 allowing the maximum amplitude to
be ± 5V. The dual 12 bit D/A converter gets its data from the Communications Processor's
SPI port qualified by PCS0. Clock and data to U724 are buffered by. The data is recreated
from measurement data received by the Communications Processor over the module bus.
2.1.27Analog Inputs
The communications Processor has a 6 channel A/D converter, only 4 channel are used at
this time. The A/D converter is only for monitoring voltages and not for critical
measurements. AN0 and AN1 are assigned to external analog inputs. There is an attenuator
circuit provided to keep the input to the A/D within its limits. AN3 and AN4 are assigned to
measure the internal battery voltages. They also have an attenuator circuit which attenuates
the battery voltage by 1/4, to stay within the limits of the A/D converter (5 Vdc).
2.1.28SRAM
There is 128K x 8 bytes SRAM which is used to store temporary variables and data required
by the Communications Processor.
2.1.29Keypad and Rotary Knob
The front panel keypad is interfaced to the QSPI port qualified by PCS1. In order to read a
key, keypad scanning is used. The actual scanning logic is contained on the Interconnect
board, 0670-00-0686 and 0670-00-0714 in CPLD, U1. The keypad rows are exercised
with a Awalking zero pattern. This means that three out of four lines will always be at a logic
1 with one line driven low. In a complete cycle, each line will sequentially go low, driving a
different row on the keypad. This cycle is repeated continuously at a fast rate. The eight
columns are read, whenever a key is depressed, the coordinates of that key will be
determined by knowing which column line. The Communications Processor sends the scan
pattern on the QSPI port transmit output (MOSI) and receives the keypressed response on the
QSPI receive input (MISO). The QSPI signal are connected to the Interconnect board through
connector J5. The keypad connects to mating connectors on the Interconnect Board.
The front panel rotary selector is quadrature encoder with an integral switch. The purpose of
this device is for LCD menu scroll and selection. The quadrature signals CHA and CHB are
input from connector J5-70 and J5-71. The Communications Processor interprets the serial
data stream and sends it to the MPC860T through the Dual Port Ram, representing direction
and speed as well as the status of the integral switch.
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Theory of OperationCPU Control Module
2.1.30Control Functions
There is a DC/DC converter module, PS1 which provides isolated DC power to the front end
circuitry. The module can be turned on by a logic 1 on the Communications Processor port
pin PGP7.The Communications Processor reset input is controlled by a signal from the
MPC860T, port pin PA(6). The signal required for reset is a logic 1. The signal is inverted by
FET Q1 before being connected to the Communications Processor RESET* pin.
2.1.31Module Bus
Communications with all measurement modules in the ECM is through a RS-485 module bus.
The Communications processor is the host and all modules are slave devices. The
Communications Processor UART connects to the module bus through RS-485 buffer/driver
U20. The direction of the data flow through the RS-485 buffer driver is controlled by two
different signals from port pins on the Communications Processor. Receive is controlled by an
logic 0 on port pin PGP6 and logic 0 on PGP0 Transmit is controlled by a logic 1 on PGP0
and a logic 1 on PGP6.There is a module bus connection from the isolated front end through
RS-485 buffer driver, U28. The isolation is provided by opto couplers. The front end transmit
data is provided by opto coupler U230 and receive data by opto coupler U231 along with
Q2 and part of U100. The direction of data flow is controlled by opto coupler U232 along
with part of U100.
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Front End ModuleTheory of Operation
2.2Front End Module
Overview
This document describes the theory of operation of the ECM Frontend module. This module is
responsible for acquisition of most of the patient-safety isolated signals, namely the ECG,
Respiration (by impedance), Temperature, and two channels of Invasive Blood Pressure.
The Front End Module consists of a common isolated power supply, data isolation,
microcontroller, and A/D converter, shared between the various patient signals.
2.2.1Power Supply
The power supply takes a raw +12v DC supply voltage and generates the highly isolated
operating voltages required by the front end module. Since the input voltage varies over a +/
-5% range, some form of regulation is required. To preserve efficiency, a modular switching
supply is used.
This power supply requires sufficient isolation between the input and output to withstand the
open circuit voltage of a defibrillator, up to 5 kV. Further, it requires low capacitance
between the input and output, to minimize leakage currents which may flow should the
patient accidently contact line voltage.
2.2.2Communication Isolation
The communication between the front end module and the host must be isolated to the same
degree as the power supply. The communications consist of an asynchronous bidirectional
serial data stream at 500 k baud. Since these signals are all digital, the isolation is
performed with optocouplers. All these devices are a special type which feature very high
isolation voltage.
2.2.3Data Acquisition
The various signal processing blocks, such as ECG, IBP, etc., generate both analog
(waveform) and digital (status) signals. The purpose of the data acquisition system is to
capture these signals and to format them into a data stream suitable for transmission through
the communication isolation circuits. The system consists of a multiplexed analog to digital
converter, a single-chip microcontroller, and some digital level shifters. The microcontroller
serves the additional purpose of interpreting commands received from the host.
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Theory of OperationFront End Module
2.2.4Analog to Digital Converter
The MAX147 ADC is operated in the single ended bipolar mode, with external clock. The
control byte sent to the converter by the QSPI is %1mm, where mm is the ADC multiplexer
channel. Since the entire analog signal path is “floated” on the +2.5 volt reference, the ADC
analog common is referenced to this voltage also. The ADC therefore produces signed output
data for analog inputs corresponding to nominally ±1.25 volts around the +2.5 volt
reference. The ADC results are read into the QSPI receive RAM as words, and are leftjustified. That is, the sign bit of the ADC data is the msb of the word, and the 12 bit ADC
data is padded with 4 trailing zeros. The ADC regards the leading “1" in the command byte
as a synchronization bit. Therefore, the output data justification is controlled by the
justification of the command byte within the word transmitted by the QSPI.
2.2.5Microcontroller and Data Processing
The Front End is controlled by U224, a Motorola MCF5282 microcontroller operating in the
single-chip mode. The board pulls RCON* high, which causes the processor to enter this
mode as it comes out of reset. The internal 64.0MHz clock is generated by the internal
synthesizer from a 8.000 MHz reference crystal. The crystal operates with roughly sinusoidal
waveforms, and therefore generates less EMI than a square-wave oscillator module. To
further minimize EMI and avoid the need for external pull up resistors, all unneeded dynamic
I/O pins are set as outputs and disabled. This is performed by programming all the unused
general purpose I/O pins as outputs at initial software boot up. This also helps reduce power
dissipation. The other default values that are set by RCON* high are: boot port size - internal
(32 bits); pad driver load - full drive strength; PLL reference - crystal; boot select - internal boot
device; PLL mode - normal.
Two SCI ports are used. The first SCI port is used to interface to the host communication
controller across the isolation barrier via the opto-couplers. The processor lies on the patient
isolated side of the barrier, and communicates using the serial module bus. The required SCI
baud rate is 500K baud. A second SCI is used to communicate to the SpO
third SCI is used for debugging purposes.
Power for the core is supplied by a +3.3VD switching power supply. Power for the internal
A/D converter is supplied by a +5V linear regulator. The processor is resetable by a hard
reset using several methods: 1) on power up; 2) generated locally by monitoring a voltage
supervisory chip; and 3) the provision is made to have the module bus reset from the CPU
side sent across the isolation barrier optocouplers, and then go to the microcontroller reset
pin causing a hard reset. The Communications Processor will reset all the modules on the
module bus at the beginning of its operation (after its own initialization).
A general purpose timer is used for several functions. One input capture channel is used for
the pacer detection edge capture. Two output compare channels are used to implement the
38.4KHz respiration clock. The real time ECG trigger pulse is used with a general purpose
I/O.
The periodic interrupt timer has the capability to be set to interrupt every 2ms and 0.5ms for
software ISRs.
boards. The
2
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Front End ModuleTheory of Operation
Emulation capabilities and high level debugging are included using a JTAG port configured
as a Background Debug Mode (BDM) connector. A 26-pin header connector, J204, is
provided.
Hardware multiply and accumulate (MAC) functionality for implementing the digital software
filters is provided.
No external hardware interrupts are required.
2.2.6Memory
Since the processor operates in the single chip mode, only internal memory is used. The
device contains a ColdFire Flash Module (CFM), which is constructed with eight banks of
32K x 16-bit Flash to generate a 512-Kbyte, 32-bit wide electrically erasable and
programmable read-only memory array. The CFM is ideal for program and data storage for
single-chip applications and allows for field reprogramming without external high-voltage
sources. The voltage required to program and erase the Flash is generated internally by onchip charge pumps. Program and erase operations are performed under CPU control
through a command driven interface to an internal state machine. All Flash physical blocks
can be programmed or erased at the same time, however, it is not possible to read from a
Flash physical block while the same block is being programmed or erased. The array used in
the MCF5282 makes it possible to program or erase one pair of Flash physical blocks under
the control of software routines executing out of another pair.
Some of the requirements satisfied by the design are 8KB SRAM and 96KB Flash EEPROM.
The SRAM is used for the BOOT RAM, stack, and vector table. The Flash is used for the runtime code and satisfies the minimum of 64K, but expandable to at least 96K for ST/
Arrhythmia and future growth. The 96K is divided into 2 blocks: 8K minimum for the
bootloader code, and 88K minimum for the application code.
The Flash has a bulk erase mode. It is intended that the bootloader can be erased and
changed only at the factory, while the application code can be reloaded in the field. The
Flash has a security register, a protection register, and a lock control bit, all used to protect
the boot code from accidental erasure. For added protection, a separate external program/
erase jumper J7 is supplied, giving the capability to use jumpers for factory programming.
The jumper is connected to a general purpose I/O pin and is only read by software in order
to have permission to program the boot code. The application code is that which actually
runs the module, following initialization, and is field downloadable via the module bus. The
bootloader code performs basic initialization of the system, then passes control to the
application. The bootloader also contains support for module bus downloads of the
application code, in the event the application code is corrupted or is to be updated. The
system can always recover from a failed download, since the bootloader cannot be
accidentally erased or corrupted outside the factory.
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Theory of OperationFront End Module
The processor is to be soldered to the board unprogrammed. Initial programming of the
bootloader is to be performed by the J204 BDM connector (Background Debug Mode). The
application code can also be installed by the BDM, or it can be downloaded via the module
bus once the bootloader is installed. Note that the BDM can also be used to facilitate board
testing, besides downloading code.
The RAM requirements are met by the internal SRAM array. The vector table lies within the
RAM. This allows the bootloader and application code to each install its own vectors at
runtime. Note that when a Flash module (in this case the bootloader module) is configured as
bootable, the initial PC, stack pointer, etc., are fetched from the module's shadow registers,
not the usual vector table. Therefore, the system is able to boot despite having undefined
RAM contents in the vector table at startup. One of the first tasks of the code is then to install
a valid vector table in the SRAM. This must be done before any exception processing can
occur.
2.2.7I/O Ports and Software Register Programming
The interfaces to the processor are through the general purpose I/O ports, the QSPI, the SCI
(UART), and the timer ports. The internal ADC is also used for status monitoring.
General purpose I/O expansion is available principally on ports TA[2], TB[2:1], NQ,
SD[5:3], TD, TC[1:0], QS[6:4], QA[4].
Ports EL, EH, and AS[5:2] are used for microprocessor control signals and are configured as
outputs, except for Port EH bit 1, which is an input. The table below shows the bit
assignments for the ports. Port SD[2:0] is used for the SpO
TA and TB are used for the general purpose timer signals and are listed below. Port QS is
used for the QSPI signals and is listed below. Ports UA, TC, and AS are used for the SCI
signals and are listed below. Port DD is used for the BDM signals, but is not listed below.
Several ports are reserved for future interfaces using external address and data bus lines.
These ports are A, B, C, D, E, F, G, H, and J. All of the unused I/O are all configured as
outputs to eliminate the need to terminate these pins to a valid logic level.
ADC inputs and general purpose I/O are provided by Port QA and QB. The ports can be
used for all the ADC signals, but have multiple functions. They can be configured with
external analog multiplexer chips to accept as many as 18 analog inputs, utilizing the
multiplexed signals MA1 and MA0 on port QA bits 1 and 0. This is used to extend the
capabilities of the internal ADC. In this design, we accept 7 ADC inputs and don't need an
external analog multiplexer chip.
The function and pin assignments of these ports are described in the tables below. The exact
function of each signal will be more fully described in the discussion of the individual signal
processing circuits. Each pin can be individually configured as an input or output. Software
performs this configuration during initialization, and no subsequent changes are made
during operation.
ID bits and is listed below. Ports
2
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Front End ModuleTheory of Operation
2.2.8Signal Acquisition
ECG
The ECG signal acquisition consists of three differential amplifier channels, which can be
configured to support either 3 lead or 5 lead operation. These are connected to channels 0
through 2 of the MAX147 ADC. In the 5 lead mode, a dedicated electrode (RL) is used for
patient drive. This allows all of the remaining electrodes (RA, LA, LL, and C) to be used for
signal acquisition. There are 7 standard vectors (“leads”) which can be obtained
simultaneously from these electrodes. However, these vectors contain much redundant
information. In fact, only 3 channels of data are required to allow derivation of any or all of
the 7 standard vectors. The ECM module bus therefore caries only lead I, Lead II, and V as
the requisite data channels. In three lead mode, only three electrodes are attached to the
patient. Further, one of these electrodes must be used for the patient drive, precluding its use
for signal acquisition. Therefore, only vectors Lead I, Lead II, and Lead III are available, with
only a single vector being available at a time. Two of the 3 differential amplifiers are
configured to acquire Lead I and Lead II. The third amplifier is reconfigurable, by means of
an analog switch, to acquire either the V lead or Lead III. The configuration of the amplifiers
and the driven lead is controlled by the two ECG lead select bits, LS0 and LS1.
2.2.9Lead Fault Detection
Lead fault detection is performed by observing the voltage on the ECG amplifier inputs. Due
to the bias networks included in the lead buffers, an open circuited electrode will develop a
strong negative voltage. The lead fault signal is then generated by the microcontroller, which
is actively monitoring the voltage via its A/D converter.
In leads I, II, and III, the operation of the lead fault detection is very simple. When all leads
are attached, both ECG amplifier inputs are approximately at the value of the drive amplifier
bias voltage, which is about +2.5 volts nominal. This voltage is not sufficiently negative, so
no lead fault condition is indicated. If one of the active electrodes becomes detached, the
voltage on the corresponding amplifier input swings to about -5 volts. This is well beyond the
threshold, so a lead fault condition is indicated. The effect is the same if either active lead is
detached. If the drive electrode becomes detached, this is equivalent to both active leads
being open, so the operation is the same. Note that the margins between the common mode
voltage established by the drive amplifier and the lead fault threshold are large enough that
the possibility of a 300 mV electrode polarization offset does not affect lead fault detection.
Note also that this lead fault detection scheme only tests those electrodes which are
necessary to view a particular lead selection. Therefore, to view leads I, II, or III, only RA, LA,
and LL are needed. The lead fault detection is indifferent to the state of the unnecessary RL
and C electrodes.
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It is necessary to detect pacer pulses so that the rate meter can be made unresponsive to
them, and so that enhancement of the pacer pulse can be indicated on the monitor display.
Electrosurgical interference is similar in nature to pacer pulses, but while a pacer pulse
occurs at a repetition rate related to the normal range of heart rates, electrosurgical noise
has much higher repetition rates, due to rapid sparking at the active electrode. Therefore, a
single circuit can detect both types of signal, and categorize the detected event as a pacer or
noise according to the repetition rate. The detection circuit processes the ECG signal present
at the I, II, and III/V outputs.
The basis for detection of the pacer pulses is frequency - the frequency content of a pacer
being assumed to be higher than any normal physiologic signal. The most difficult pacer to
discriminate would therefore be one with the lowest slew rate, that is, the slowest rise time
and smallest amplitude. From the range of pacers defined in AAMI EC13-1992, this is a
pulse amplitude of 2 mV and a duration of 2 ms. The means of performing the frequency
discrimination is shown in the figure below.
In order to identify the pacer or noise spike, a window comparator, U214, is used to detect
when the output of U212 has a moderately high frequency content signal. U212 provides
rejection of the Respiration excitation carrier, but permits passage of pacer signals. Positive
and negative input pins of this comparator are biased near half of the +5 rail voltages. The
threshold of the window is approximately 0.4 volts wide. The comparator output network
consisting of C246 and R261, provides stretching for narrow input pulses of variable width
to output pulses having a wider width. Since the window comparator is symmetrical, the
system works equally well for pacer/noise pulses of either polarity. The outputs (open
collectors tied together) are used as the pacer flag connected to the microcontroller.
2.2.11Respiration
Respiration is obtained through the ECG electrodes by impedance pneumography, in which
the AC impedance between a pair of the ECG electrodes is monitored. This impedance
varies with the chest motions associated with breathing. The respiration signal consists of a
small modulation on the order of 1 ohm, superimposed on a much larger baseline
impedance. The baseline impedance measured at the patient has a typical value of 500
ohms, and may reach 2000 ohms. However, when AAMI connector ECG cables are used,
the cable contains 1000 ohm resistors in series with each leadwire. Since the respiration is
measured through a pair of leadwires, 2000 ohms are added to the patient impedance.
When the connector board is equipped with additional defibrillation protection provisions
(series ECG resistors and high voltage respiration coupling capacitors), the front end board
can be used with resistor less ECG cables. Therefore, the total range of baseline impedance
ranges from somewhat less than 500 to 4000 ohms.
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Front End ModuleTheory of Operation
The respiration signal is isolated from the baseline by a fixed analog highpass filter at 0.1
Hz, and a lowpass at about 3 Hz. The signal is amplified and acquired by channel 3 of the
MAX147 ADC. Although the QSPI scans all channels every 2 ms, the respiration is to be
sampled at only 100 Hz. Therefore, the data processing software takes data from the QSPI
buffer in only 1 out of every 5 scans. The highpass filter is equipped with a reset function
activated by a control line in Port A. The respiration reset is controlled in a manner similar to
the ECG reset, in that it is activated whenever the respiration signal appears stuck offscale,
and must remain asserted for a settling period after the signal is brought back in range. The
baseline impedance is also monitored, by a channel in the 68HC16 internal ADC. When the
baseline impedance exceeds about 4000 ohms (patient plus cable resistors), a high
impedance flag must be set by the software. This flag indicates that the respiration signal is
no longer reliable.
When monitoring neonatal patients, it is desirable to raise the highpass corner frequency to
0.2 Hz. Since the analog filter is fixed, this is done by refiltering the signal with a digital filter
in software. In the adult mode, this digital filter remains active, but is set to a very low corner
frequency, 0.0125 Hz. Therefore, the analog 0.1 Hz filter dominates the response. This
relaxes the design constraints on the respiration filter and DC amplifier circuits, as any
residual offset voltage present in these stages is now removed by the digital filter, even in the
adult mode. In the neonatal mode, the digital filter is set to 0.155 Hz, which produces a 0.2
Hz 3 dB point when cascaded with the analog filter. A Mathcad document fully documents
the digital filter. Note that these filters are based on the 100Hz sampling rate. Whenever
software resets the analog filter, the cascaded digital filter must also be reset, or the baseline
will not settle properly. The assembler code shows the method of resetting the digital filter.
Note also that the detection of an offscale condition for reset generation must be done on the
raw ADC data, before the digital filter.
The respiration can be configured to sense impedance in either a lead I (RA/LA) or lead II
(RA/LL) axis, by means of the Respiration Lead Select bit in Port A. The respiration can be
disabled by the Respiration Enable bit in Port A. It is necessary to disable the respiration
when the carrier might cause interference with other electromedical devices. The table below
summarizes the respiration control bits in Port A.
2.2.12Invasive Blood Pressure
An interface is provided for two standard 5mV/mmHg/V transducers. This consists of a
common excitation power source and a pair of differential amplifiers with lowpass filters,
one for each channel. The excitation source is monitored by the 68HC16 ADC, while the
pressure waveforms are acquired by the MAX147. The frequency response can be modified
by digital filters processing the acquired signals.
The excitation voltage is nominally +5 volts, but tracks the ADC reference. In this way, the
actual value of the ADC reference does not affect accuracy, since the transducer is a
ratiometric device. The excitation source has current limiting, which prevents the module
power supply from being disrupted if the transducer excitation becomes shorted. The
excitation regulator’s error amplifier output is monitored by the 68HC16 internal ADC. This
signal will abruptly jump to almost zero when the excitation source begins to current limit.
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Theory of OperationFront End Module
2.2.13Temperature
Patient temperature is monitored by a thermistor probe. Either YSI 400 series or 700 series
probes can be used, with autodetection of probe type. When the 400 series is used, the
temperature channel is accurate to 0.2 °C. Correct calibration is continuously verified, as is
required by European standards.
The YSI 400 series probes contain a single thermistor, wired between the tip and sleeve of a
two-circuit ¼ inch phone plug. The 700 series probes contain two thermistors, and use a
three-circuit plug. The sleeve of the plug is connected to the common of the two thermistors.
The primary thermistor is connected to the tip contact, and a secondary thermistor is
connected to the ring contact. However, only the primary thermistor is used for temperature
measurement. The secondary thermistor is used as the basis for probe type autodetection.
The ring contact of the probe socket is biased through a resistor from the +5 volt supply, and
has its voltage monitored by the 68HC16 internal ADC. When a series 400 probe is
connected, the solid metal sleeve of the plug shorts the socket’s ring contact to ground, so the
ADC reads essentially zero. If no probe is connected, the ADC reads near full scale.
However, if a series 700 probe is connected, a voltage divider is formed by the bias resistor
and the secondary thermistor. Therefore, the ADC reads an intermediate value which
depends on the probe temperature, but is easily distinguished from the readings obtained
when a 400 series probe or no probe is present.
2.2.14Timers
The only digital input to the processor is Timer Input Compare 1 (Port GP 0), which is used for
pacer detection. This line exhibits a falling edge each time a pacer is detected. Therefore,
this input should be configured to generate an interrupt on falling edges, which invokes the
pacer handling ISR. A timer channel, rather than interrupt input, has been used so that the
exact time of arrival of the pacer is logged; this may prove helpful in generating some of the
timing based on the pacer, although it is not necessary to use this feature. The latency of the
pacer ISR must be minimized, a consideration which must be remembered when assigning
timer interrupt priorities. Timer Output Compare 1 (port GP 3) is the pacer blanking output.
When the monitor is used with patients having conventional implanted pacemakers, this
signal is not used, and is maintained at logic low. In the case of external pacemakers, a
much stronger pacer overload signal results, and the pacer blanking output is used to
activate a sample and hold of the ECG signal for the duration of the pacer overload. In
external pacer mode, TOC 1 is used to generate the pacer blanking pulse. The Pacer ISR sets
the TOC 1 output high, initiating the pulse. It further programs the TOC 1 register to
terminate the pulse after the requisite duration. Therefore, the TOC 1 function is set to drive
the pin low on timer match. Low ISR latency is necessary to ensure that the pulse starts
promptly upon pacer detection.
Timer Output Compare 2 (Port GP4) is used to define the E-trigger pulse sent to the module
bus. The E-trigger pulse is initiated by the R-wave detection software, which also programs
TOC 2 to terminate the pulse after the requisite width.
Passport 2®/Passport 2 LT™ Service Manual0070-10-04412 - 19
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