Datasheet WM5620CD, WM5620LIN, WM5620LID, WM5620LCN, WM5620LCD Datasheet (Wolfson)

WM5620L, WM5620

R

R

R

L

A

B

C

D

V

3 & 5V Quad 8-Bit Voltage Output DAC

with Serial Interface

Production Data

Sept. 1996 Rev 2

Description

WM5620L and WM5620 are quad 8-bit digital to analogue
converters (DAC) controlled via a serial interface. Each
DAC's output voltage range isprogrammable for either x1
or x 2 its reference input voltage, allowing near rail to rail
operation for the x 2 output range. Separate high
impedance buffered voltage reference inputs are provided
for each DAC. WM5620L operates on a single supply

Features

• Four 8-bit voltage output DAC's

• Three wire serial interface

• Programmable x1 or x 2 output range.

• Power-on-reset sets outputs to zero

• Buffered voltage reference inputs

• Simultaneous DAC output update

• 14 pin SO or DIP package

voltage of 3 V while WM5620 operates on 5 V .
WM5620/L interfaces to all popular microcontrollers and
microprocessors via a three wire serial interface with CMOS
compatible, schmitt trigger, digital inputs. An 11 bit
command word comprises 2 DAC select bits, an output
range selection bit and 8-bits of data.
Individual or all DAC outputs are changed using WM5620/
L's double buffered DAC registers and the separate LOAD
and LDAC inputs. DAC outputs are updated
simultaneously by writing a complete set of new values
and then pulsing the LDAC input.
The DAC outputs are optimised for single supply
operation and driving ground referenced loads.
An internal power-on-reset function sets the DAC's input
codes to zero at power up.
Ideal in space critical applications WM5620/L is available
in small outline and DIP packages for commercial (0

o

C) and industrial (-40oC to 85oC) temperature ranges.

70

o

C to

Block Diagram

2

ef A

9

3

Ref B

4

ef C

ef D

Production Data data sheets contain
final specifications current on publication
date. Supply of products conforms to
Wolfson Microelectronics standard terms
and conditions

Data

oad

5

7

Clk

6

Serial Interface

8

Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK

Tel: [phone] Fax: [phone]

Latch

9

Latch

9

Latch

9

Latch

Wolfson Microelectronics

email: [e-mail]

www: http://www.wolfson.co.uk

Key Specifications

• Single supply operation:

• 0 to 4 V output (x 2 output range) at 5 V VDD

• 0 to 2.5 V output (x 2 output range) at 3 V VDD

• Low power: 5.1 mW at 3 V, 10 mW at 5 V max.

• Guaranteed monotonic output

WM5620L : 3 V
WM5620 : 5 V

Applications

• Programmable d.c. voltage sources

• Digitally controlled attenuator/amplifier

• Signal synthesis

• Mobile communications

• Automatic test equipment

• Process control

DD

14

12

DAC

11

DAC

10

DAC

9

DAC

© 1996 Wolfson Microelectronics

Latch

Latch

Latch

Latch

DAC

8

DAC

8

DAC

8

DAC

8

Power-on-Reset

x 2

x 2

x 2

x 2

WM5620L, WM5620

Pin Configuration Ordering Information

Top View N and D packages

Absolute Maximum Ratings (note 1)

Supply Voltage (VDD - VGND) . . . . . . . . . . . . +7V

Digital Inputs . . . . . . . . . . GND - 0.3 V, VDD + 0.3 V

Reference inputs . . . . . . . GND - 0.3 V, VDD + 0.3 V

Recommended Operating Conditions

SYMBOL MIN NOMINAL MAX UNIT

Supply voltage WM5620 VDD 4.75 5.25 V
Supply Voltage WM5620L VDD 2.7 3.3 5.25 V
Reference input range x1 gain V
DAC output load resistance to GND RL 10 kΩ
High level digital input voltage VIH 0.8 VDD V
Low level digital input voltage VIL 0.8 V
Clock frequency FCLK 1 MHz

REF [A/B/C/D] V DD - 1.5 V

DEVICE TEMP. RANGE PACKAGE

WM5620CN 0
WM5620CD 0oC to 70oC 14 pin plastic SO
WM5620IN -40oC to 85oC 14 pin plastic DIP
WM5620ID -40oC to 85oC 14 pin plastic SO
WM5620LCN 0oC to 70oC 14 pin plastic DIP
WM5620LCD 0oC to 70oC 14 pin plastic SO
WM5620LIN -40oC to 85oC 14 pin plastic DIP
WM5620LID -40oC to 85oC 14 pin plastic SO

Operating temperature range, T

WM5620_C_ . . . . . . . . . . . . . . . . 0oC to +70oC

WM5620_I_ . . . . . . . . . . . . . . . . -40oC to +85oC

Storage Temperature_ . . . . . . . . . . -50

Lead Temperature 1.6mm (1/16 inch) from case

(soldering, 10 sec) . . . . . . . . . . . . . . . + 260

o

C to 70oC 14 pin plastic DIP

A . . . . . . TMIN to TMAX

o

C to +150oC

o

C

Electrical Characteristics: WM5620

VDD = 5 V, GND = 0 V, VREF = 2 V, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Power Supply

Supply current I

Static Accuracy

Resolution 8 Bits
Monotonicity 8 Bits
Differential Nonlinearity DNL VREF = 2 V, Range x 2. (note 3) ± 0.1 ± 0.9 LSB
Integral Nonlinearity INL VREF = 2 V , Range x 2. (note 4) ± 1.0 LSB
Zero-code error ZCE VREF = 2 V, Range x 2. (note 5) 0 30 mV
Zero-code error Input code = 00 Hex (note 6) 10 µV/OC
temperature coefficient
Zero-code error Input code = 00 Hex (note 7) 0.5 mV/V
supply rejection

DD VDD = 5V 2 mA

Wolfson Microelectronics

2

WM5620L, WM5620

Electrical Characteristics: WM5620

VDD = 5V ±5%, GND = 0 V, VREF = 2 V, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Full scale error FSE V
Full scale error Input code = FF Hex (note 9) ± 25 µV/OC
temperature coefficient
Full scale error supply Input code= FF Hex, 0.5 mV/V
rejection (note 10)
Output sink current IO(SINK) Each DAC output 20 µA
Output source current IO(SOURCE) 2mA
Reference input current IREF VDD=5V, VREF=2V ± 10 µA

Electrical Characteristics: WM5620L

VDD = 3V , GND = 0 V , VREF =1.25 V , R L = 10 kΩ, C L = 100 pF , T A = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Power Supply

Supply current I

Static Accuracy

Resolution 8 Bits
Monotonicity 8 Bits
Differential Nonlinearity DNL VREF = 1.25 V , Range x 2. (note 3) ± 0.9 LSB
Integral Nonlinearity INL VREF = 1.25 V , Range x 2. (note 4) ± 1.0 LSB
Zero-code error ZCE VREF = 1.25 V, Range x 2. (note 5) 0 30 mV
Zero-code error Input code = 00 Hex (note 6) 10 µV/OC
temperature coefficient
Full scale error FSE VREF = 1.25 V, Range x 2. (note 8) ± 60 mV
Full scale error Input code = FF Hex (note 9) ± 25 µV/OC
temperature coefficient
Output sink current IO(SINK) Each DAC output 20 µA
Output source current IO(SOURCE) 1mA
Ref. input current IREF VDD = 3.3V; Vref = 1.5V ±10 µA

DD VDD = 3.3V 2 mA

REF = 2 V , Range x 2. (note 8) ± 60 mV

Electrical Characteristics: WM5620 & WM5620L

VDD = 2.7V to 5.5V, GND = 0 V, RL = 10 kΩ, CL = 100 pF , TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital Inputs

High level input current I
Low level input current I IL VI = 0V ±10 µA
Input capacitance CI 15 pF

Timing Parameters

Data input setup time tSD 50 n s
Data input hold time tHD 50 n s

to Load tHL 50 ns

CLK
Load to CLK tSL 50 ns

Load duration tWL 250 ns
LDAC duration tWD 250 ns

to LDAC tLD 0ns

Load

IH VI = VDD ±10 µA

Wolfson Microelectronics

3

WM5620L, WM5620

Electrical Characteristics: WM5620 & WM5620L

VDD = 2.7V to 5.5V, GND = 0 V, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Reference Inputs

Reference input voltage V
Reference input A, B, C, D, inputs 15 pF

capacitance

Reference feedthrough A, B, C, D, inputs (note 1 1) - 60 dB
Channel to channel A, B, C, D, inputs (note 12) -60 dB
isolation

Dynamic Performance

Output settling time To 1/2 LSB, VDD = 3 V & 5V 10 µs

Output slew rate 1V/µs
Input bandwidth (note 14) 100 kHz
Large Signal Bandwidth Measured at -3dB point 100 kHz
Digital Crosstalk Clk = 1MHz sq wave measured at -50 dB

Electrical Characteristics: WM5620 & WM5620L (continued)

REF A, B, C, D, inputs GND VDD - 1.5 V

(note13)

DACA - DACD

Notes:

1. Absolute Maximum Ratings are stress ratings only.
Permanent damage to the device may be caused by
continuously operating at or beyond these limits.
Device functional operating range limits are given
under Recommended Operating Conditions.
Guaranteed performance specifications are given
under Electrical Characteristics at the test conditions
specified.

2. Total Unadjusted Error is the sum of integral linear­ity error, zero code error and full scale error over the
input code range.

3. Differential Nonlinearity (DNL) is the difference
between the measured and ideal 1 LSB amplitude
change of any two adjacent codes. A guarantee of
monotonicity means the output voltage changes in
the same direction (or remains constant) as a change
in the digital input code.

4. Integral Nonlinearity (INL) is the maximum deviation
of the output from the line between zero and full scale
(excluding the effects of zero code and full-scale
errors).

5. Zero code error is the deviation from zero voltage
output when the digital input code is zero.

6. Zero code error temperature coefficient is given by:
ZCETC = (ZCE(Tmax) - ZCE(Tmin))/VREF
(Tmax - Tmin)

7. Zero-code Error Rejection Ratio (ZCE-RR) is meas­ured by varying the VDD voltage, from 4.5 to 5.5 V
d.c., and measuring the proportion of this signal im­posed on the zero-code output voltage.

8. Full-scale error is the deviation from the ideal full­scale output (VREF - 1 LSB) with an output load of
10kΩ

9. Full-Scale Temperature Coefficient is given by:
FSETC = (FSE(T

min)

T

10. Full Scale Error Rejection Ratio (FSE-RR) is meas­ured by varying the VDD voltage, from 4.5 to 5.5 V
d.c., and measuring the proportion of this signal im­posed on the full-scale output voltage.

max) - FSE(Tmin))/VREF x 10

x 106/

6

/(Tmax -

Wolfson Microelectronics

4

WM5620L, WM5620

e

)

e

)

e

)

e

)

Electrical Characteristics: WM5620 & WM5620L (continued)

11 Reference feedthrough is measured at a DAC out-

put with an input code = 00 Hex with a V

REF input = 1

Vdc + 1 VPP at 10kHz

12. Channel to channel isolation is measured at a DAC
output with an input code of one DAC to FF Hex and
the code oa all other DACs to oo Hex with a V

REF

input = 1 Vdc + 1 Vpp at 10kHz

Parameter Measurement Information

DACA
DACB
DACC
DACD

Slewing Settling Time and Linearity Measurements

10KΩ CL - 100pF

13 Setting time is the time for the output signal to remain

within ±0.5 LSB of the final measurement value for a
digital input code change of 00 Hex to FF Hex. For WM

DD = 5V, VREF = 2V and range = x 2. For

5620: V
WM5620L: V

DD = 3, VREF = 1.25V and range = x 2.

14 Reference bandwidth is the -3dB bandwidth with an

input at V

REF = 1.25 Vdc =+ 2 Vpp with a digital input

code of full-scale

Typical Performance Characteristics

Typical DNL, INL and TUE * at VDD = 5 V

Differen t i al Nonlinea rity

VDD = 5 V, Vref = 2.5 V, Range x 1, TA = 25OC

0.2

0.1
0

-0.1

Error (lsb

-0.2
0 32 64 96 128 160 192 224 256

Input Cod

Tota l Unadjuste d Error

VDD = 5 V, Vref = 2.5 V , Range = x 1, TA = 25OC

0.5

0.25
0

-0.25

Error (lsb

-0.5
0 32 64 96 128 160 192 224 256

Input Cod

Error (lsb

Int egral Non linea r ity

DD

V

0.2

0.1
0

-0.1

Error (lsb

-0.2

ref

= 5 V, V

= 2.5 V, Range = x 1, TA = 25OC

0 32 64 96 128 160 192 224 256

Input Cod

Differential Nonlinearity

VDD = 5 V, V

0.2

0.1
0

-0.1

-0.2

ref

= 2 V, Range = x 2, TA = 25OC

0 32 64 96 128 160 192 224 256

Input Cod

* see note 2

Wolfson Microelectronics

5

WM5620L, WM5620

s

)

)

V
T
V
R
I

e

)

e

)

e

)

e

)

e

)

Supply Curren t v s

)

)

V
V

V
V

R
I

5

Typical Performance Characteristics (Continued)

Typical DNL, INL and TUE * at VDD = 5 V

Integral N o nlinear ity

VDD = 5 V, V

0.2

0.1
0

-0.1

Error (lsb

-0.2
0 32 64 96 128 160 192 224 256

Typical DNL, INL and TUE at VDD = 3 V

ref

= 2 V, Range = x 2, TA = 25OC

Input Cod

0.5

0.25

-0.25

Error (lsb

-0.5

Total Unadjusted Error

VDD = 5 V, Vref = 2 V, Range = x 2, TA = 25OC

0

0 32 64 96 128 160 192 224 256

Input Cod

Differential Nonlinearity

VDD = 3 V, V

0.2

0.1
0

-0.1

Error (lsb

-0.2
0 32 64 96 128 160 192 224 256

ref

= 1.25 V, Range x 2, TA = 25OC

Input Cod

Total Unadjusted Error

0.5

0.25

0

-0.25

Error (lsb

-0.5

VDD = 3 V, V

ref

= 1.25 V, Range x 2, TA = 25OC

0 32 64 96 128 160 192 224 256

Input Cod

Output Source Cur rent v

Out put Vo ltage

8

7

6
5

DD

4

(mA

out

I

3

2
1

0

= 5 V

A

= 25OC

= 2 V

ref

ange = x 2

nput code = 255

012345

Vout (V

Integral N o nlinear ity

DD

V

0.2

0.1
0

-0.1

Error (lsb

-0.2

ref

= 3 V, V

= 1.25 V, Range x 2, TA = 25OC

0 32 64 96 128 160 192 224 256

Input Cod

Tempe rature

1.2

1.15

1.1

1.05

ange = x 2

nput code = 25

1

IDD (mA

0.95

0.9

0.85

0.8

-50 0 50 100

Temperature (OC

DD

= 3 V
= 1.25 V

ref

DD
ref

= 5 V
= 2 V

6

Wolfson Microelectronics

y

)

V
T
V
I

Typical Performance Characteristics (Continued)

y

)

V
T
V
I

WM5620L, WM5620

Large Signal Fre quenc

Response

0

-2

-4

-6

-8

-10

DD

= 5 V

-12

A

= 25OC

ref

= 1.25 Vdc + 2 V

-14

nput Code = 255

Relative Gain (dB)

-16

-18

-20
1 10 100 1000

pp

Frequency (kHz

Positive Rise and Settling Time V

500 mV/Vert. div
2 µs/Hor. div

DD = 3 V

VDD = 3 V

O

C

TA = 25
code 00 to FF Hex
Range = x 2
Vref = 1.25 V

Small Sig n al F req ue nc

Response

10

0

-10

-20

= 5 V

DD

-30

= 25OC

A

ref = 2 Vdc + 0.5 V

-40

nput code = 255

Relative Gain (dB)

-50

-60
1 10 100 1000 10000

pp

Frequency (kHz

Negative Fall and Settling Time VDD = 3 V

VDD = 3 V

O

C

TA = 25

500 mV/Vert. div
5 µs/Hor. div

code FF to 00 Hex
Range = x 2
Vref = 1.25 V

Rise time = 2.05 µs, Positive slew rate = 0.96 µ s
Settling time = 4.5 µs

Positive Rise and Settling Time VDD = 5 V

1 V/Vert. div
2 µs/Hor. div

DD = 5 V

V

O

C

TA = 25
code 00 to FF Hex
Range = x 2
Vref = 2 V

Rise time = 2.4 µs, Positive slew rate = 1.0 µs
Settling time = 5.8 µs

Fall time = 4.25 µs, Negative slew rate = 0.46 µs
Settling time = 8.5 µs

Negative Fall and Settling Time V

1 V/Vert. div
5 µs/Hor. div

DD = 5 V

DD = 5 V

V

O

C

TA = 25
code FF to 00 Hex
Range = x 2
Vref = 2 V

Fall time = 5.0 µs, Negative slew rate = 0.63 µs
Settling time = 9.5 µs

Wolfson Microelectronics

7

WM5620L, WM5620

1 2 3 4 5 6 7 8 9 10 11

L

D

Data Input Timing

Load and LDAC Timing

Equivalent Input and Output Circuits

Timing Waveforms

CLK

ata

50 %

t

SD

t

HD

CLK

Load

50 %

t

HL

t

WL

t

LD

t

SL

t

WD

LDAC

Timing Diagrams

CLK

Data

A1 A0

Load

DAC

RNG

D7 D6 D5 D4 D3 D2 D1 D0

Figure 1. Load controlled update (LDAC = 0)

8

Wolfson Microelectronics

Timing Diagrams

L

1 2 3

4

5 6 7 8 9 10 11

1 2 3 4 5 6 7 8 9 10 11

CLK

WM5620L, WM5620

Data

Load

DAC

LDAC

CLK

Data

Load

CLK

Data

Load

A1 A0

RNG

D7 D6 D5 D4 D3 D2 D1 D0

Figure 2. LDAC controlled update

A1 A0

RNG

D7 D6 D5 D4 D3 D2 D1 D0

Figure 3. Load controlled update (LDAC = 0) using 8-bit serial word.

1 2 3

A1 A0

RNG

5 6 7 8 9 10 11

4

D7 D6 D5 D4 D3 D2 D1 D0

LDAC

Figure 4. LDAC controlled update using 8-bit serial word.

Wolfson Microelectronics

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WM5620L, WM5620

Pin Descriptions

Pin Name Type Function

1 GND Supply Ground return and reference terminal
2 RefA Analogue input Reference voltage input to DACA
3 RefB Analogue input Reference voltage input to DACB
4 RefC Analogue input Reference voltage input to DACC
5 RefD Analogue input Reference voltage input to DACD
6 Data Digital input Serial interface data
7 Clk Digital input Serial interface clock, negative edge sensitive
8 Load Digital input Serial interface load
9 DACD Analogue output DAC D output
10 DACC Analogue output DAC C output
1 1 DACB Analogue output DAC B output
12 DACA Analogue output DAC A output
13 LDAC Digital input DAC update latch control
14 VDD Supply positive supply voltage

Functional Description

DAC operation

Each of WM5620/L 's four digital to analogue converters
(DACs) are implemented using a single resistor string with
256 taps corresponding to each of the input 8-bit codes.
One end of a resistor string is connected to the GND pin
and the other end is driven from the output of a reference
input buffer. The use of a resistor string guarantees
monotonicity of the DAC's output voltage. Linearity depends
upon the matching of the resistor string's individual elements
and the performance of the output buffer. The reference input
buffers present a high impedance to reference sources.

Each DAC has a voltage output amplifier which is
programmable for gains of x1 or x 2 through the serial
interface. The DAC output amplifiers feature rail to rail
output stages, allowing outputs over the full supply voltage
range to be achieved with a x 2 gain setting and a VDD/2
reference voltage input. Used in this way a slight
degradation in linearity will occur as the output voltage
approaches VDD.

A power-on-reset activates at power up resetting the DACs
inputs to code 0. Each output voltage is given by:

out = Vref x CODE/256 x (1 + RNG)

V

Where: RNG controls the output gains of x 1 and x 2

CODE is the range 0 to 255

Data Interface

WM5620/L's four double buffered DAC inputs allow
several ways of controlling the update of each DAC's
output.

Serial data is input, MSB first, into the DAT A input pin using
CLK, LOAD and LDAC control inputs and comprises 2 DAC
address bits, an output range (RNG) bit and 8 DAC input
bits.

With the LOAD pin high data is clocked into the DATA pin
on each falling edge of CLK. Any number of data bits may
be clocked in, only the last 1 1 bits are used. When all data
bits have been clocked in, a falling edge at the LOAD pin
latches the data and RNG bits into the correct 9 bit input
latch using the 2 bit DAC address.

If the LDAC input pin is low, the second latch at the DAC
input is transparent, and the DAC input and RNG bit will be
updated on the falling edge of LOAD simultaneously with
the input latch, as shown in figure 1. If the LDAC input is high
during serial data input, as shown in figure 2, the falling edge
of the LOAD input stores the data in the addressed input
latch. The falling edge of LDAC updates the second latches
from the input latches and hence the DAC outputs.

10

Wolfson Microelectronics

Functional Description (Continued)

WM5620L, WM5620

Using these inputs individual DACs can be updated using
one 11 bit serial input word and the LOAD pin. Using both
LOAD and LDAC, all or selected DACs can be updated
after an appropriate number of data words have been
inputted. Figures 3 & 4 illustrate operation with the 8 clock
pulses available from some microprocessors. If the data
input is interrupted in this way the clock input must be
held low during the break in clock pulses.

The RNG bit controls the DAC output range. When RNG
= 0 the output is between Vref(A,B,C,D) and GND and
when RNG = 1 the range is between 2 x Vref (A,B,C,D)
and GND.

Serial Input Decode

A1 A0 DAC

0 0 DACA
0 1 DACB
1 0 DACC
1 1 DACD

D7 D6 D5 D4 D3 D2 D1 D0 Output V oltage

0 0 0 0 0 0 0 0 GND
0 0 0 0 0 0 0 1 (1/256) x Ref (1 + RNG)

• • • • • • • • •

• • • • • • • • •
0 1 1 1 1 1 1 1 (127/256) x Ref (1 + RNG)
1 0 0 0 0 0 0 0 (128/256) x Ref (1 + RNG)

• • • • • • • • •

• • • • • • • • •
1 1 1 1 1 1 1 1 (255/256) x Ref (1 + RNG)

Wolfson Microelectronics

11

WM5620L, WM5620

Applications Information

Linearity, offset, and gain error using
single end supplies

When an amplifier is operated from a single supply, the
voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first
code change. With a negative offset the output voltage may
not change with the first code depending on the magni­tude of the offset voltage.

The output amplifier, with a negative voltage of fset, attempts
to drive the output to a negative voltage. However, because
the most negative supply rail is GND, the output cannot
drive to a negative voltage.
So when the output offset voltage is negative, the output
voltage remains at ZERO volts until the input code value
produces a sufficient output voltage to overcome the
inherent negative offset voltage, resulting in the transfer
function shown below.

This negative offset error, not the linearity error, produces
this breakpoint. The transfer function would have followed
the dotted line if the output buffer could drive to a nega­tive voltage.

For a DAC, linearity is measured between ZERO input code
( all inputs 0 ) and full scale code ( all inputs 1 ) after offset
and full scale are adjusted out or accounted for in some
way. However, single supply operation does not allow for
adjustment when the offset is negative due to the break­point in the transfer function. So the linearity in the unipo­lar mode is measured between full scale code and the
lowest code which produces a positive output voltage. The
code is calculated from the maximum specification for the
negative offset.

Effect of negative offset (single supply)

12

Wolfson Microelectronics

Package Descriptions

Plastic Small-Outline Package

D - 8 pins shown

WM5620L, WM5620

4.00

3.80

6.20

5.80

1.75

1.35

0.25

0.10

A

14

Pin spacing

1.27 B.S.C.

Dimension 'A' Variations

NMinMax

8 4.80 5.00
14 8.55 8.75
16 9.80 10.00

58

0.50

O

0.51

0.33

0.25

x 45 NOM

1.27

0.40

0.25

0.19

OO

0 to 8

Notes:

A. Dimensions in millimeters.
B. Complies with Jedec standard MS-012.
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion.
E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall

not exceed 0.25mm.

Rev. 1 November 96

Wolfson Microelectronics

13

WM5620L, WM5620

Package Descriptions

Dual-In-Line Package

N or P

N

0.005
Min.

1

0.070 Max.

Pin spacing

0.100 B.S.C.

A

0.045

0.030

0.022

0.014

O

105

O

90

0.014

0.008

Dimension 'A' Variations

0.325

0.290

0.280

0.240

Seating
plane

0.210 Max.

0.150

0.115

0.015
Min.

NMinMax

8 0.355 0. 400
14 0.735 0. 775
16 0.735 0. 775
20 0.940 0. 975

Notes:

A. Dimensions are in inches
B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001)
C. N is the maximum number of terminals
D. All end pins are partial width pins as shown, except the 14 pin package which is full width.

N/2

14

Rev. 1 November 96

Wolfson Microelectronics