Page 1
WM2632
Octal 8-bit, Serial Input, Vol t age Output DAC
with Internal Reference
Production Data, April 2001, Rev 1.1
FEATURES
• Eight 8-bit DACs in one package
• Dual supply 2.7V to 5.5V operation
• DNL ±0.1 LSBs, INL ±0. 3 LS Bs typical
• Programmable settling time / power
(1.0µs typical in fast mode)
• Internal programmable voltage reference
• Microcontroller compatible serial interface
• Power down mode ( < 0.1µA)
• Monotonic over temperature
• Data output for daisy chaining
APPLICATIONS
• Battery powered test instruments
• Digital offset and gain adjustment
• Battery operated / remote industrial controls
• Programmable loop controllers
• CNC machine tools
• Machine and motion control devices
• Wireless telephone and communication systems
• Robotics
ORDERING INFORMATION
DEVICE TEMP. RANGE PACKAGE
WM2632CDT 0° to 70°C 20-pin TSSOP
WM2632IDT -40° to 85°C 20-pin TSSOP
DESCRIPTION
The WM2632 is an octal, 8-bit, resistor string digital-toanalogue converter. The eight individual DA Cs contained in
the IC can be switched in pairs between fast and s low (low
power) operation modes, or powered down, under software
control. Alternatively, the whole device can be powered
down, reducing current consumpt i on to less than 0.1µA.
The DAC outputs are buffered by a rail-to-rail amplif ier with
a gain of two, which is configurable as Class A (fast mode)
or Class AB (for low-power mode).
The WM2632 has been designed to interface directly to
industry standard microprocessors and DSPs, and can
operate on two separate analogue and digital power
supplies. It is programmed with a 16-bit serial word
comprising 4 address bits and up to 12 DAC or control
register data bits. All eight DACs can be simultaneously
forced to a preset value using a pres et input pin.
A daisy-chain data output makes it possible to control
several of Wolf son’s octal DACs from t he same interface,
without increasing the number of control lines.
The device is available in a 20-pin TSSOP package.
Commercial temperature (0° to 70°C) and Industrial
temperature (-40° to 85°C) variants are supported.
BLOCK DIAGRAM TYPICAL PERFORMANCE
REF
AVDD
(11)
AGND
(10)
DVDD
(20)
DGND
(1)
(12) OUT A
(6-9, 13-15)
OUT B to H
0.04
0.03
0.02
0.01
0
-0.01
-0.02
Differential Non-Linearity (LSBs)
-0.03
-0.04
0 32 64 96 128 160 192 224 256
DIGITAL CODE
Production Data datasheets contain final
specifications current on publication date.
Supply of products conforms to Wol fson
Microelectronics’ Term s and Conditions.
2001 Wolfson Microelectronics Ltd.
(16)
1.024V / 2.048V
SELECTABLE
REFERENCE
DAC A
DIN (2)
SCLK (3)
FS (4)
MODE (17)
PREB (5)
DOUT (19)
SERIAL
INTERFACE
AND
CONTROL
LOGIC
LATCH
DACs B, C, D, E, F, G, H
LOADB
(18)
RESISTOR
POWER/SPEED
CONTROL
REF
as DAC A
STRING
WOLFSON MICROELECTRONICS LTD
Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
www.wolfsonmicro.com
Page 2
WM2632 Production Data PIN CONFIGURATION
20
DGND
DIN
SCLK
PREB
OUTE
OUTF
OUTG
OUTH
AGND
1
2
3
FS
4
5
6
7
8
9
10
DVDD
19
DOUT
18
LOADB
17
MODE
16
REF
15
OUTD
14
OUTC
13
OUTB
12
11
OUTA
AVDD
PIN DESCRIPTION
PIN NO NAME TYPE DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DGND Supply Digital Ground
DIN Digital input Digital serial data input
SCLK Digital input Serial clock input
FS Digital input Frame sync input
PREB Digital input Preset input
OUTE Analogue output DAC Output E
OUTF Analogue output DAC Output F
OUTG Analogue output DAC Output G
OUTH Analogue output DAC Output H
AGND Supply Analogue Ground
AVDD Supply Analogue positive power supply
OUTA Analogue output DAC Output A
OUTB Analogue output DAC Output B
OUTC Analogue output DAC Output C
OUTD Analogue output DAC Output D
REF Analogue I/O Voltage reference input / output
MODE Digital input Input mode
LOADB Digital input Load DAC
DOUT Digital output Serial data output
DVDD Supply Digital positive power supply
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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Production Data WM2632
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Perm anent damage t o the devi ce m ay be c aused by c ont inuousl y operating at
or beyond these limits. Device f unctional operating limits and guaranteed performance specific ations are given under Electrical
Characteristics at the test conditions s pecified.
ESD Sensitive Device. Thi s device i s m anufactured on a CMOS proc ess. It is therefore generic ally sus ceptibl e
to damage from excessive static voltages . Proper ESD precaut ions m ust be t aken during handling and s torage
of this device.
CONDITION MIN MAX
Digital supply voltages, AVDD or DVDD to GND
Reference input voltage
Digital input voltage range to GND
Operating temperature range, T
A
WM2632CDT
WM2632IDT
Storage temperature
Soldering lead temperature, 1. 6mm (1/16 inch) from package body for
-0.3V AVDD + 0.3V
-0.3V DVDD + 0.3V
0°C
-40°C
-65°C 150°C
7V
70°C
85°C
260°C
10 seconds
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Supply voltage
AVDD,
2.7 5.5 V
DVDD
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REF
V
IH
V
IL
V
REF
AVDD = 5V GND 2.048 AVDD
2V
AVDD = 3V GND 1.024 AVDD V
Output Load Resistance
Load capacitance
Operating free-air temperature
R
L
C
L
T
A
WM2632CDT 0 70 °C
2kΩ
WM2632IDT -40 85 °C
Note: Reference input voltages greater t han A V DD/2 will cause saturation for large DAC codes.
0.8 V
100 pF
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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WM2632 Production Data ELECTRICAL CHARACTERISTICS
Test Characteristics:
R
= 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, V
L
recommended operating free-ai r temperature range (unless noted otherwise).
= 2.048V and AVDD = DVDD = 3V ± 10%, V
REF
= 1.024V over
REF
PARAMETER SYMBOL
Static DAC Specifications
Resolution
Integral non-linearity
Differential non-linearity
Zero code error
Gain error
DC power supply rejection ratio
INL Code 6 to 255 (see Note 1) ±0.3 ±1 LSB
DNL Code 6 to 255 (see Note 2) ±0.1 ±1 LSB
ZCE See Note 3 ±30 mV
GE See Note 4 ±0.6 % FSR
PSRR See Note 5 -50 dB
Zero code error temperature
coefficient
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
Output load regulation
Power Supplies
Active supply current
IDD No load, V
Power down supply current
Dynamic DAC Specifications
Slew rate
Settling time
Glitch energy
Channel Crosstalk
TEST
CONDITIONS
MIN TYP MAX UNIT
8bits
See Note 6 30 µV/°C
See Note 6 10 ppm/°C
10kΩ Load 0 AVDD-0.4 V
2kΩ to 10kΩ load
See Note 7
=DVDD, VIL=0V
IH
±0.3 % Full
Scale
AVDD = DVDD = 5V,
V
= 2.048V
REF
Slow
Fast
16
6
21
8
mA
mA
See Note 8
No load, all inputs 0V
0.1 µA
or DVDD
DAC code 10%-90%
Load = 10kΩ, 100pF
Fast
Slow
4
1
10
V/µs
3
V/µs
See Note 9
DAC code 10%-90%
Load = 10kΩ, 100pF
Fast
Slow
1
3
3
7
µs
µs
See Note 10
DAC code 127 to 128 4 nV-s
10kHz sine wave, 4V pk-pk -90 dB
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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Production Data WM2632
Test Characteristics:
R
= 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, V
L
= 2.048V and AVDD = DVDD = 3V ± 10%, V
REF
= 1.024V over
REF
recommended operating free-ai r temperature range (unless noted otherwise).
PARAMETER SYMBOL
TEST
CONDITIONS
MIN TYP MAX UNIT
Reference Configured as Input
Reference input resistanc e
Reference input capacitanc e
Reference feedthrough
R
REF
C
REF
V
=2VPP at 1kHz
REF
50 kΩ
10 pF
-84 dB
+ 2.048V DC, DAC code 0
Reference input bandwidth
V
= 0.4VPP + 2.048V DC,
REF
DAC code 128
Slow
Fast
1.9
2.2
MHz
MHz
Reference Configured as Output
Low reference voltage
High reference voltage
Output source current
Output sink current
Load Capacitance
PSRR
V
REFOUTL
V
REFOUTH
I
REFSRC
I
REFSNK
1.010 1.024 1.040 V
VDD > 4.75V 2.020 2.048 2.096 V
1mA
-1 mA
in parallel with 100nF cap. 1 10 µF
60 dB
Digital Inputs
High level input current
Low level input current
Input capacitance
I
IH
I
IL
C
I
Input voltage = DVDD -1 1 µA
Input voltage = 0V -1 1 µA
8pF
Notes:
1. Integral non-linearity (INL) is the maximum deviati on of the output from the line between zero and full scale excluding
the effects of zero c ode and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in t he same
direction (or remains constant) as a change in digital i nput code.
3. Zero code error is the voltage output when the DAC input code i s zero.
4. Gain error is the deviation from the ideal full-scale output excluding the effec ts of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are norm al i sed to full-scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ
load. It is expressed as a percent age of the full scale output vol tage with a 10kΩ load.
8. I
is measured while continuous l y writing a di gi t al code of 128 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V
DD
supply current will increase.
9. Slew rate results are for the lower value of the rising and falling edge s l ew rates.
10. Settling time is the time taken for the signal to settle to within 0. 5LS B of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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WM2632 Production Data SERIAL INTERFACE
t
t
WL
WH
SCLK
DIN
DOUT
FS
(
µ
C MODE)
FS
(DSP MODE)
X1 2
t
SUD
t
HD
XD15 D14 D13
X D15 * D14 * D13 * D12 * D1 * D0 * X
t
WHFStSUFSCLK
* DIN data from previous word
(delayed by 16 clock cycles)
t
WLFS
No high to low transitions
Figure 1 Timing Diagram
SYMBOL TEST
CONDITIONS
t
SUFSCLK
t
C16-FS
Setup time, FS pin low before fi rst falling edge of SCLK
Setup time, 16th falling clock edge after FS l ow to ris i ng edge of FS
(only used in microcont rol l er mode)
t
WLOADB
t
WH
t
WL
t
SUD
t
HD
t
WHFS
t
WLFS
t
s
Pulse duration, LOADB low
Pulse duration, SCLK high
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
Pulse duration, FS low
DAC Output settling ti me
34 16
2
D1 D0 X
t
SUC16-FS
MIN TYP MAX UNIT
8ns
10 ns
10 ns
16 ns
16 ns
8ns
5ns
10 ns
10 ns
see Dynamic DAC Speci fications
X
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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Production Data WM2632
Figure
TYPICAL PERFORMANCE GRAPHS
0.3
0.2
0.1
0
-0.1
Integral Non-Linearity (LSBs)
-0.2
-0.3
0 32 64 96 128 160 192 224 256
DIGITAL CODE
Figure 2 Integral Non-Linearity
1
VDD = 3.3V
= 1.024V
V
REF
Input Code = 0
0.8
0.6
0.4
Output Voltage (V)
0.2
0
00.511.52
Sink Current (m A)
Slow
Fast
1
VDD = 5V
= 2.048V
V
REF
Input Code = 0
0.8
0.6
0.4
Output Voltage (V)
0.2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Sink Current (mA)
Slow
Fast
Figure 3 Output Load Regulation (Sink) AVDD = 3V Figure 4 Output Load Regulation (Sink) AVDD = 5V
2.1
2.08
2.06
2.04
DACA (Volts)
2.02
2
VDD=3V
V
=1.024V
REF
Input Code = 4095
Sourcing Current (mA)
Slow
Fast
-4-3.5-3-2.5-2-1.5-1-0.50
4.15
4.13
4.11
4.09
DACA (Volts)
4.07
4.05
VDD=5V
V
=2.048V
REF
Input Code = 4095
Sourcing Current (mA)
Slow
Fast
-4-3.5-3-2.5-2-1.5-1-0.50
Figure 5 Output Load Regulation (Source) AVDD = 3V
6 Output Load Regulation (Source) AVDD = 5V
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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Page 8
WM2632 Production Data DEVICE DESCRIPTION
GENERAL FUNCTION
The WM2632 is an octal 8-bi t, voltage output DAC. It contains a serial interface, control logic for
speed and power down, a programmable voltage reference, and eight digit al to analogue converters .
Each converter uses a resistor string network buffered with an op amp to convert 8-bit digital dat a to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
CODE
2
Output voltage =
INPUT OUTPUT
1111 1111
::
1000 0001
1000 0000
0111 1111
::
0000 0001
0000 0000 0V
Table 1 Binary Code Table (0V to 2V
V
()
REF
256
2
()
REFV
2
()
REFV
()
2
2
()
REFV
2
()
REFV
REF
255
256
129
256
128
REFREF VV =
256
127
256
1
256
Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to al l 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail out put with short circuit protec tion and can reliably drive a
2kΩ load with a 100pF load capacitance.
PROGRAMMABLE REFERENCE
The DAC reference can be sourced internally or externally under software control. If an external
reference voltage is applied to the REF pin, the device must be configured to accept this. If an
internal reference is selec ted, a voltage of 1.024V or 2.048 i s available. The int ernal reference can
source up to 1mA and can t heref ore be used as an external system referenc e.
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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Production Data WM2632
SERIAL INTERFACE
INTERFACE MODES
The control interface can operate in two different modes:
• In the microcontroller mode, FS needs to be held low until all 16 data bits have been
transferred. If FS is dri ven high before the 16
The DAC is updated after a rising edge on FS .
• In DSP mode, FS only needs to stay low for 20ns, and can go high before the 16
edge.
SCLK
FS
X
D15
DIN
Figure 7 Interface Timing in Microcontroller Mode
SCLK
FS
DIN
X
D14 D1 D0 X E15
D15
D14 D1 D0 E15 E14 E0 X X F15
E14
th
falling clock edge, t he data transf er is cancell ed.
E1 E0 X F15
E1
X
X
th
falling clock
F14
F14
Figure 8 Interface Timing in DSP Mode
The operating mode is selected using pin 17 (MODE).
MODE PIN (17) INTERFACE MODE
HIGH Microcontroller
LOW or unconnected DSP mode
Table 2 Interface Mode Selection
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the interface timing. The maximum serial clock rate is:
f
Since a data word contains 16 bits, the sample rate is li mited to
f
However, the DAC settling tim e to 8 bi ts acc urac y lim it s t he respons e ti m e of t he analogue output f or
large input step transitions.
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
SCLK
s
max
max
=
=
16
1
tt
+
WLWH
1
tt
+
()
WLWH
MHz
31
=
minmin
MHz
95.1
=
minmin
9
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WM2632 Production Data
DAISY CHAINING MULTIPLE DEVICES
The DOUT output (pin 19) provides the data sam pled on DIN with a delay of 16 c lock cycles. This
signal can be used to control anot her WM2632 or similar devi ce in a daisy-chain type circuit.
DIN
SCLK
LOADB
FS
FS
DIN
SCLK
DOUT
LOADB
OCTAL DAC #1
Figure 9 Daisy Chaining
SOFTWARE CONFIGURATION OPTIONS
DATA FORMAT
The WM2632 is controll ed with a 16-bi t code consisting of four address bits, A0-A3, and 12 data bi ts.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A3 A2 A1 A0 Data
Table 3 Input Data Format
Using the four address bits , 16 different registers c an be addressed.
A3 A2 A1 A0 REGISTER
0 0 0 0 DAC A Code
0 0 0 1 DAC B Code
0 0 1 0 DAC C Code
0 0 1 1 DAC D Code
0 1 0 0 DAC E Code
0 1 0 1 DAC F Code
0 1 1 0 DAC G Code
0 1 1 1 DAC H Code
1 0 0 0 Control Register 0
1 0 0 1 Control Register 1
1 0 1 0 Preset all DACs
1 0 1 1 RESERVED
1 1 0 0 DA C A and complement B
1 1 0 1 DAC C and compl ement D
1 1 1 0 DAC E and complem ent F
1 1 1 1 DAC G and complement H
Table 4 Register Map
FS
DIN
SCLK
OCTAL DAC #2
FS
DIN
DOUT
LOADB
OCTAL DAC #3
SCLK
DOUT
LOADB
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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Production Data WM2632
DAC A TO H CODE REGISTERS
Addresses 0 to 7 are the DAC registers. Bits D11 (MSB) to D4 (LSB) from these registers are
transferred to the respective DAC when the LOADB input (pin 18) is low. Bi ts D3 to D0 are unused
and must be set to 0. For i nstantaneous updating, LOADB can be hel d l ow perm anently.
CONTROL REGISTER 0
Control register 0 (address 8) is used to select func tions that apply to the whole IC, such as Power
Down and Data Input Format.
BIT D11 D10D9D8D7D6D5 D4 D3 D2 D1 D0
Function X X XXXXXPDDO R1 R0 IM
Default X X XXXXX 0 0000
Table 5 Control Register 0 Map
BIT DESCRIPTION 0 1
PD Full device Power Down Normal Power D own
DO DOUT Enable Disabled Enabled
R1 Int / Ext Reference Select External Internal
R0 Internal Reference Select 1.024V 2.048V
IM Input Mode Straight Binary Two’s Complement
X Reserved
Table 6 Control Register 0 Functionality
CONTROL REGISTER 1
Control register 1 (address 9) is used to power down individual pairs of DACs and s elect thei r set tl ing
time. Powering down a pair of DACs disabl es their am plif iers and reduces the power cons umpt ion of
the device. The settling t ime in fas t mode is typically 1µs. In s low mode, the s ettling time is typic ally
3µs and power consumption is reduced.
BIT D11 D10D9D8D7D6D5 D4 D3 D2 D1 D0
Function X X X X PGHPEFPCDP
S
S
S
AB
GH
EF
S
CD
AB
Default X X X X 0 0 0 0 0 0 0 0
Table 7 Control Register 1 Map
BIT DESCRIPTION 0 1
P
XY
S
XY
Power Down DACs X and Y Normal Power Down
Speed Setting for DACs X and Y Slow Fast
Table 8 Control Register 1 Functionality
DAC PRESET REGISTER
The Preset register (address 10) m akes it possi ble to update all eight DACs at the same t ime. The
value stored in this register becomes the digital input to all the DACs when the asynchronous PRE B
input (pin 5) is driven low. If no data has previously been written to the preset register, all DA Cs are
set to zero scale.
TWO-CHANNEL REGISTERS
The two-channel registers (addresses 12 t o 15) provide a ‘differential output’ func tion where writing
data to one DAC will automatically write the complem ent to the other DAC in the pair. For example,
writing a value of 255 to address 12 will set DAC A to full scale and DAC B to zero scale.
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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WM2632 Production Data
PROGRAMMABLE INTERNAL REFERENCE
The reference can be sourced internally or externally under software control. If an external reference
voltage is applied to the REF pin, the device must be confi gured to accept this.
If an external reference is selec ted, the reference voltage input is buffered which m akes the DAC
input resistance independent of code. The REF pin has an input res istance of 10MΩ and an input
capacitance of typical l y 55pF. The reference voltage determines t he DAC full-scale output.
If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference
can source up to 1mA and c an therefore be used as an external system ref erence.
REF1 REF0 REFERENCCE
0 0 External (default)
0 1 1.024V
1 0 2.048V
1 1 External
Table 9 Programmable Internal Reference
APPLICATIONS INFORMATION
LINEARITY, OFFSET, AND GAIN ERROR
Amplifiers operating from a single supply can have positive or negative voltage offsets. With a
positive offset, the output voltage changes on the first code transition. However, if the offset is
negative, the output voltage m ay not change with the first code, depending on t he magnitude of the
offset voltage. This i s because with the m ost negat ive supply rail being ground, any att empt to drive
the output amplifier below ground will clamp the output at 0 V. The output voltage t hen remains at
zero until the input code is s ufficiently high to overc ome the negative offs et voltage, resulting in the
transfer function shown in Figure 10.
Output
Voltage
0 V
Negative
Offset
Figure 10 Effect of Negative Offset
This offset error, not t he linearity error, produces the break point. The transfer function would follow
the dotted line if the output buf fer could drive below the ground rail.
DAC linearity is measured between zero-input code (all input bi ts at 0) and full -scale code (al l inputs
at 1), disregarding offset and full-scale errors. However, due to the break poi nt in the transfer function,
single supply operation does not al low for adjustm ent when the offs et is negative. In s uch cas es, the
linearity is therefore m easured between full-s cale and the l owest code that produces a posi tive (nonzero) output voltage.
DAC code
POWER SUPPLY DECOUPLING AND GROUNDING
Printed circuit boards with separate analogue and digital ground planes deliver the best system
performance. The two ground planes should be connected together at the low impedance power
supply source. Ground currents should be managed so as to minimise voltage drops across the
ground planes.
A 0.1µF decoupling capacitor should be connected between the pos itive supply and ground pins of
the DAC, with short leads as close as possibl e to the devic e. Use of f errite beads may f urther isolat e
the system analogue suppl y from the digital supply.
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
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Production Data WM2632
PACKAGE DIMENSIONS
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
b
A1
A2
A
e
1120
D
101
0.1
E1 E
C
-C-
SEATING PLANE
GAUGE
PLANE
DM008.D
θ
0.25
c
L
Dimensions
Symbols
(mm)
MIN NOM MAX
A
A
1
A
2
b
c
D
e
E
E
1
L
θ
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
----- ----- 1.20
0.05 ----- 0.15
0.80 1.00 1.05
0.19 ----- 0.30
0.09 ----- 0.20
6.40 6.50 6.60
0.65 BSC
6.4 BSC
4.30 4.40 4.50
0.45 0.60 0.75
o
0
----- 8
o
JEDEC.95, MO-153
WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001
13
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