Datasheet WM2619IDT, WM2619CDT Datasheet (Wolfson)

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Page 1

WM2619

DNL - LSB

12-bit Parallel Input Voltage Output DAC

Production Data, June 1999, Rev 1.0

FEATURES

• 12-bit voltage output DAC

• Single supply 2.7V to 5.5V operation

• DNL ±0.4 LSB, INL ±1.5 LSB

• Settling time 1µs typical

• Low power consumption

- 8mW typical in slow mode - 5V supply

- 4.3mW typical in fast mode - 3V supply

• Power down mode

APPLICATIONS

• Battery powered test instruments

• Digital offset and gain adjustment

• Battery operated/remote industrial controls

• Machine and motion control devices

• Wireless telephone and communication systems

• Speech synthesis

• Arbitrary waveform generation

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2619CDT 0° to 70°C 20-pin TSSOP

WM2619IDT -40° to 85°C 20-pin TSSOP

DESCRIPTION

The WM2619 is a 12-bit voltage output, resistor string, digital-toanalogue converter. A hardware controlled power down mode is provided that reduces power consumption to 50nW. In normal operation the device dissipates 8mW at 5V or 4.3mW at 3V.

The device has been designed to interface efficiently to industry standard microprocessors and DSPs.

Excellent performance is delivered with a typical DNL of 0.4 LSBs and a settling time of 1µs. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage. The 12 data bits are double-buffered enabling the output to be asynchronously updated under hardware control.

The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported.

BLOCK DIAGRAM TYPICAL PERFORMANCE

VDD (11)

VDD = 5V, V

= 2.048V, Load = 10k/100pF

REF

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1 0 512 1024 1536 2048 2559 3071 3583 4095

DIGITAL CODE

REFIN(12)

D[0-11]

(19,20, 1-10)

NWE (17)

NCS (18)

12-BIT INPUT

POWER-ON

RESET

(14)

GND

REFERENCE

INPUT BUFFER

12-BIT

data

DAC

LATCH

(16)

NLDAC

POWERDOWN

CONTROL

(15) NPD

DAC OUTPUT BUFFER

WM2619

(13) OUT

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolfson

Microelectronics’ Terms and conditions.

Masterrev1.0a.doc June 17, 1999 10:52

1999 Wolfson Microelectronics Ltd.

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WM2619 Production Data PIN CONFIGURATION

D2 D3 D4 D5 D6 D7 D8 D9

D10 D11

1 2 3 4 5 6 7

9 10

20 19 18 17 16 15 14 13

12 11

D1 D0 NCS NWE NLDAC NPD GND OUT8

REFIN

VDD

PIN DESCRIPTION

PIN NO NAME TYPE DESCRIPTION

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

D2 Digital input Digital data input. D3 Digital input Digital data input. D4 Digital input Digital data input. D5 Digital input Digital data input. D6 Digital input Digital data input. D7 Digital input Digital data input. D8 Digital input Digital data input.

D9 Digital input Digital data input D10 Digital input Digital data input. D11 Digital input Digital data input (MSB).

VDD Supply Positive power supply.

REFIN Analogue input Voltage reference input.

OUT Analogue output Analogue output. GND Ground Ground. NPD Digital input Power down. Powers down all DACs overriding their individual

power down settings and all output stages. This pin is active low.

NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to

update the DAC latch from the holding latches.

17 18 19 20

NWE Digital input Write enable (active low).

NCS Digital input Chip select (active low).

D0 Digital input Parallel data input (LSB).

D1 Digital input Parallel data input.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2619

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device

CONDITION MIN MAX

Digital Supply voltage, VDD to GND Reference input voltage Digital input voltages Operating temperature range, T

WM2619C

WM2619I Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

-0.3V VDD + 0.3V

-0.3V VDD + 0.3V 0°C

-40°C

-65°C 150°C

70°C 85°C

260°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REFIN Load resistance Load capacitance Operating free-air temperature

VDD 2.7 5.5 V

REF

VDD = 2.7V to 5.5V 2 V VDD = 2.7V to 5.5V 0.8 V

See Note VDD - 1.5 V

2 10 kΩ

WM2619C 0 70 °C

WM2619I -40 85 °C

Note: Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

100 pF

WOLFSON MICROELECTRONICS LTD Production Data Rev1.0 June 1999

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WM2619 Production Data

OUT

ELECTRICAL CHARACTERISTICS

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V temperature range (unless noted otherwise)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications

Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient

DAC Output Specifications

Output voltage range Output load regulation

Power Supplies

Active supply current

Power down supply current

Dynamic DAC Specifications

Slew rate

Settling time

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating free-air

REF

12 bits

INL See Note 1

DNL See Note 2

±±1.5 ±±4 ±±0.4 ±±1

ZCE See Note 3 3

GE See Note 4 0.25

±±20

±±0.5

LSB LSB

% FSR

d.c. PSRR See Note 5 0.5 mV/V

See Note 6 3 ppm/°C See Note 6 1 ppm/°C

0 VDD - 0.4 V

2kΩ to 10kΩ load

0.1 0.3 %

See Note 7

No load, V

VDD = 5V, V

VDD = 3V, V

= VDD, V

= 2.048V

REF

= 1.024V

REF

= 0V

1.6

1.4

3.0

2.7

mA mA

See Note 8

No load, all digital inputs

0.01 10 µA 0V or VDD See Note 9

DAC code 128 to 4095,

8 V/µs 10%-90% See Note 10

DAC code 128 to 4095

1 µs See Note 11

Glitch energy Signal to noise ratio

SNR fs = 480ksps, f

Code 2047 to 2048 5 nV-s

OUT

= 1kHz,

65 78 dB

BW = 20kHz, TA = 25°C

See Note 12

Signal to noise and distortion ratio

SNRD fs = 480ksps, f

OUT

= 1kHz,

58 67 dB

BW = 20kHz, TA = 25°C

See Note 12

Total harmonic distortion

THD fs = 480ksps, f

= 1kHz,

-68 -60 dB

BW = 20kHz, TA=25°C

See Note 12

Spurious free dynamic range

SPFDR fs = 480ksps, f

= 1kHz,

60 72 dB

BW = 20kHz, TA = 25°C

See Note 12

Reference

Reference input resistance Reference input capacitance Reference feedthrough

R C

REFIN

= 1VPP at 1kHz

REF

10 MΩ

5 pF

-60 dB

+ 1.024Vdc, DAC code 0

Reference input bandwidth

= 0.2VPP + 1.024V d.c.

REF

1.4 MHz

DAC code 2048

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2619

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating free-air

REF

temperature range (unless noted otherwise)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Inputs

High level input current Low level input current Input capacitance

Input voltage = VDD 1 µA

Input voltage = 0V -1 µA

8 pF

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.

8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase.

9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates.

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested.

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f

generated with a sampling frequency fs

OUT

WOLFSON MICROELECTRONICS LTD Production Data Rev1.0 June 1999

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WM2619 Production Data SERIAL INTERFACE

D [0:11]

SUCSWE

SUDWE

DataX X

NCS

WWE

NWE

SUWELD

WLD

NLDAC

Figure 1 Timing Diagram

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±± 10%, V

= 2.048V and VDD = 3V ±± 10%, V

REF

= 1.024V over recommended operating

REF

free-air temperature range (unless noted otherwise)

SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

SUCSWE

SUDWE

SUWELD

WWE

WLD

Setup time NCS low before positive NWE edge Setup time data ready before positive NWE edge Data hold after positive NWE edge Setup time NWE high before NLDAC low High pulse width of NWE Low pulse width of NLDAC

13 ns

9 ns 0 ns

0 ns 10 ns 10 ns

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2619

INL - LSB

OUTPUT VOLTAGE - V

TYPICAL PERFORMANCE GRAPHS

VDD = 5V, V

-1

-2

-3 0 512 1024 1536 2048 2559 3071 3583 4095

Figure 2 Integral Non-Linearity

= 2.048V, Load = 10k/100pF

REF

DIGITAL CODE

VDD = 3V, V

= 1V, Input Code = 0

REF

2.5

1.5

0.5

0 1 2 3 4 5 6 7 8 9 10

ISINK - mA

VDD = 5V, V

= 2V, Input Code = 0

4.5

3.5

2.5

1.5

0.5

REF

0 1 2 3 4 5 6 7 8 9 10

ISINK - mA

Figure 3 Sink Current VDD = 3V Figure 4 Sink Current VDD = 5V

2.065

VDD = 3V, V

= 1V, Input Code = 4095

2.06

2.055

2.05

2.045

2.04

2.035

2.03

2.025

REF

0 1 2 3 4 5 6 7 8 9 10

ISOURCE - mA

4.105

VDD = 5V, V

= 2V, Input Code = 4095

4.1

4.095

4.09

4.085

4.08

4.075

4.07

4.065

REF

0 2 4 6 8 10

ISOURCE - mA

Figure 5 Source Current VDD = 3V Figure 6 Source Current VDD = 5V

WOLFSON MICROELECTRONICS LTD Production Data Rev1.0 June 1999

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WM2619 Production Data DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:

Output voltage =

INPUT OUTPUT

1111 1111 1111

: :

1000 0000 0001

1000 0000 0000

0111 1111 1111

: :

0000 0000 0001

0000 0000 0000 0V

Table 1 Binary Code Table (0V to 2V

CODE

( )

REF

4096

( )

V2 REF

( )

REF

2048

( )

V2 =

4096

( )

V2 REF

( )

REF

Output), Gain = 2

REFIN

4095 4096

2049 4096

REFREF V

2047 4096

4096

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10MΩ and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output.

HARDWARE CONFIGURATION OPTIONS

The WM2619 has two configuration options that are controlled by device pins.

DEVICE POWERDOWN

The device can be powered-down by pulling pin NPD (pin 15) high. This powers down the DAC. This will reduce power consumption significantly. When the power down function is released the device reverts to the DAC code set prior to power down.

DAC UPDATE

The NLDAC pin (Pin 16) can be held high to prevent serial word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch.

PARALLEL INTERFACE

The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS (Pin 18) low.

WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999

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Production Data WM2619

PACKAGE DIMENSIONS

DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)

1120

101

0.05 C

E1 E

-C-

SEATING PLANE

GAUGE PLANE

DM008.C

θθ

0.25

Dimensions

Symbols

(mm)

MIN NOM MAX A A

b c D

----- ----- 1.20

0.05 ----- 0.15

0.80 1.00 1.05

0.19 ----- 0.30

0.09 ----- 0.20

6.40 6.50 6.60

e 0.65 BSC E E

θθ

4.30 4.40 4.50

0.45 0.60 0.75

REF:

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

6.4 BSC

----- 8

JEDEC.95, MO-153

WOLFSON MICROELECTRONICS LTD Production Data Rev1.0 June 1999