Datasheet WM8736EDS Datasheet (Wolfson)

Page 1

WM8736

24-bit, 96kHz 6-Channel DAC with Volume Control

Production Data, January 2001, Rev 2.1

DESCRIPTION

The WM8736 is a high performance 6-channel DAC designed for audio applications such as DV D, hom e t heatre systems, and digital TV. The W M8736 supports data input word lengths from 16 to 24-bits and s ampling rates up to 96kHz. The WM8736 consists of a serial interface port, digital interpolation fil ters, multi-bit sigma delta modulators and 6 DACs in a small 28-pin SSOP package. The WM8736 also includes a digitally controllable mute and attenuator function on each c hannel .

The WM8736 supports a variet y of connection sc hemes f or audio DAC control. The SPI-compati ble serial port provides access to a wide range of features including on-chip m ute, attenuation and phase reversal. A hardware controllable interface is also avail abl e.

The WM8736 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications.

BLOCK DIAGRAM

SCKI

(2)

ML/I2S

(12)

MC/IWL

(13)

MD/DM

(14)

FEATURES

• 6-channel DAC

• Performance:

− 102dB SNR (‘A’ weighted @ 48kHz), THD+N: -95dB

at full scale

• 5V or 3.3V supply operation

• Sampling frequency: 8kHz to 96kHz

• Input data word: 16 to 24-bit

• Hardware or SPI compatible seri al port control modes:

− Hardware mode: system cl ock, reset, mut e

− Serial control mode: mute, de-emphasis, di gi tal

attenuation (256 steps), zero mute, power down

APPLICATIONS

• DVD

• Home theatre systems

• Digital TV

• Digital broadcast receivers

MODE

RSTB

(10)

(8)

MUTE

(9)

256fs/384fs/512fs

CONTROL INTERFACE

WM8736

MUTE/ ATTEN

BCKIN (3)

LRCIN (4)

DIN0 (5)

DIN1 (6)

DIN2 (7)

SERIAL

INTERFACE

DIGITAL FILTERS

(24)

AGND2

MUTE/ ATTEN

(20)

AGND1

DGND

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] www.wolfsonmicro.com

(11)

SIGMA DELTA

MODULATOR

SIGMA DELTA

MODULATOR

SIGMA DELTA

MODULATOR

(28)

(16)

AVDD2

CAP

STEREO DAC

(15)

AVDD1

(27) OUT0R (26) GR0 (25) OUT0L

(23) OUT1R (22) GR1 (21) OUT1L

(19) OUT2R (18) GR2 (17) OUT2L

(1)

DVDD

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wol fson Microelectronics’ Term s and Conditions.

2001 Wolfson Microelectronics Ltd.

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WM8736 Production Data PIN CONFIGURATION ORDERING INFORMATION

DVDD

SCKI BCKIN LRCIN

DIN0 DIN1

DIN2 MODE MUTE

RSTB

DGND

ML/I2S

MC/IWL

MD/DM

AVDD2

1 2 3 4 5 6 7 8 9 10 11 12 13

OUT0R

GR0

OUT0L

AGND2

OUT1R

GR1

OUT1L

AGND1

OUT2R

GR2

OUT2L

CAP

AVDD1

1514

DEVICE TEMP. RANGE PACKAGE

WM8736EDS -25o to 85oC 28-pin SSOP

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c onti nuously operat ing at or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical Characteristics at the test conditions s pecified.

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage of this device.

CONDITION MIN MAX

Supply voltage Reference input Operating temperature range, T

Storage temperature Package body temperature (s ol deri ng, 10 seconds) Package body temperature (s ol deri ng, 2 minutes)

-0.3V +7V VDD + 0.3V

-25o C+85

-65

C +150oC

+240 +183

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

Page 3

Production Data WM8736

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital supply range Analogue supply range Ground Difference DGND to AGND Analogue supply current Digital supply current Analogue supply current Digital supply current

DVDD -10% 3.3 to 5 +10% V AVDD -10% 3.3 to 5 +10% V

AGND, DGND 0 V

-0.3 0 +0.3 V AVDD = 5V 50 mA DVDD = 5V 15 mA

AVDD = 3.3V 45 mA DVDD = 3.3V 15 mA

ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC Circuit Specifications

SNR (See Notes 1 and 2)

SNR with automute on

THD (full-scale) (See Note 2)

THD+N (Dynamic range) (See Note 2)

Frequency response Pass band ripple Transition band Out of band rejection Channel separation Gain mismatch

channel-to-channel

Digital Logic Levels

Input LOW level Input HIGH level Output LOW level Output HIGH level

V V V

Analogue Output Levels

Output level

Minimum resist ance load

Maximum capacitance load Output d.c. level

Reference Levels

Potential divider resis tance

Voltage at CAP

POR

POR threshold

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

AVDD, DVDD = 5V 95 102 dB

AVDD, DVDD = 3.3V 100 dB

AVDD, DVDD = 5V 110 dB

AVDD, DVDD = 3.3V 108 dB

0dB -96 -85 dB

-60dB 102 dB

0 20,000 Hz

20,000 Hz

2.0 V

OL OH

IOL = 2mA GND + 0.3V IOH = 2mA DVDD - 0.3V

Into 10kohm, full scale 0dB,

(5V supply)

Into 10kohm, full scale 0dB,

(3.3V supply)

To midrail or a.c. coupl ed

(5V supply)

To midrail or a.c. coupl ed

(3.3V supply)

5V or 3.3V 100 pF

AVDD to CAP and

CAP to AGND

0.125 dB

-40 dB 90 dB

±1 %FSR

0.8 V

1.1 V

0.72 V

1 kohms

AVDD/2 V

90 kohms

AVDD/2

1.8 V

RMS

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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WM8736 Production Data

LRCIN

BCH

BCKIN

DIN

Figure 1 Audio Data Input Timing

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

PARAMETER SYMBOL TEST CONDI TIONS MIN TYP MAX UNIT Audio Data Input Timing Information

BCKIN pulse cycle time BCKIN pulse width high BCKIN pulse width low BCKIN rising edge

t t t

BCY BCH

BCL

to LRCIN edge LRCIN rising edge

to BCKIN rising edge DIN setup time

DIN hold time

BCY

BCL

100 ns

50 ns 50 ns 30 ns

30 ns

30 ns 30 ns

SCKIL

SCKI

SCKIH

Figure 2 System Clock Timing Requirements

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information

SCKI system clock pulse

SCKIH

13 ns

width high SCKI system clock pulse

SCKIL

13 ns

width low

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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Production Data WM8736

MLS

MLL

MLH

ML/12S

MCH

MCL

MC/IWL

MCY

MD/DM

MDS

MDH

Figure 3 Program Register Input Timing

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information

MC/IWL pulse cycle time MC/IWL pulse width low MD/DM pulse width high MD/DM set-up time MC/IWL hold time ML/I2S pulse width low ML/I2S set-up time ML/I2S hold time

t t t t t

t t t

MCY MCL MCH MDS MDH

MLL MLS MLH

100 ns

50 ns 50 ns 30 ns 30 ns 30 ns 30 ns 30 ns

Notes:

1. Ratio of output level with 1kHz full scale input, to the output l evel with all zeros into t he digital input , measured “A” weighted over a 20Hz to 20kHz bandwidth.

2. All performance measurem ents done with 20kHz low pass filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics . The low pass filter removes out of band noi se; although it is not audible i t may affect dynam i c specification values.

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

Page 6

WM8736 Production Data PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 DVDD Supply 2 S CK I Digital input 3 BCKIN Digital input 4 LRCIN Digital input 5 DIN0 Digital input 6 DIN1 Digital input 7 DIN2 Digital input 8 MODE Digital input

9 MUTE Digital I/O

10 RSTB Digital input 11 DGND Supply 12 ML/I2S Digital input

13 MC/IWL Digital input

14 MD/DM Digital input

15 AVDD1 Supply 16 CAP Analogue output 17 OUT2L Analogue output 18 GR2 Analogue input 19 OUT2R Analogue output 20 AGND1 Supply 21 OUT1L Analogue output 22 GR1 Analogue input 23 OUT1R Analogue output 24 AGND2 Supply 25 OUT0L Analogue output 26 GR0 Analogue input 27 OUT0R Analogue output 28 AVDD2 Supply

Note:

Digital input pins have Schmitt trigger input buff e rs.

Digital positive supply. System clock i nput (256, 384 or 512fs). Audio data bit clock i nput . Left sample rate cl ock input. Channel 0 serial audio data input. Channel 1 serial audio data input. Channel 2 serial audio data input. Mode select pin. Low is software mode, high is hardware control.

Internal pull-down. Mute control pin, input or automute output.

Low is not mute, high is mute, Z is automute. Reset input − active low. Internal pull-up.

Digital ground supply Latch enable (software mode) or input f ormat selection (hardware mode).

Internal pull-up. Serial control data cloc k input (software mode) or input word length

selection (hardware mode). Internal pul l -up. Serial control data input (s of tware mode) or de-emphasis selec tion

(hardware mode). Analogue positive supply.

Analogue internal reference. Left channel 2 output. Channel 2 reference. Right channel 2 output. Analogue ground supply. Left channel 1 output. Channel 1 reference. Right channel 1 output. Analogue ground supply. Left channel 0 output. Channel 0 reference. Right channel 0 output. Analogue positive supply.

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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Production Data WM8736

11.2896

DEVICE DESCRIPTION

WM8736 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, mult i-bit sigma delta with dither, and switched capacitor m ulti-bit stereo DAC and output smoothing fil ters.

The device is implem ented as three separate stereo DA Cs in a single pac kage and controll ed by a single interface. Three separat e data input pins are provided for each of the three separate stereo DACs, and LRCIN, BCKIN and S CK I are shared between them.

Control of internal functionality of the device is by either hardware control (pin programmed) or software control (serial interf ace). The MODE pin sel ects between hardware and software c ontrol. In software control mode, an SPI type interf ace is used. This interface may be asynchronous to the audio data interface. Control data will be re-synchronized to the audio processing internally.

Operation using system c lock of 256fs, 384fs or 512fs is provided, selection between clock rates being automatically controlled in hardware mode, or serial c ontroll ed when in soft ware mode. S am ple rates (fs) from less than 8ks/s to 96k s/s are allowed, provided the appropriate syst em clock is input .

The data interface supports norm al (Japanese right justified) and I delayed) interface format s, in both ‘packed’ and unpacked forms . W hen in hardware m ode, the three serial interface pins bec ome control pins to allow s election of input data form at type (I input word length (16, 18, 20, or 24-bit) and de-emphasis function.

SYSTEM CLOCK

The system clock for W M8736 must be either 256fs , 384fs or 512fs, where fs is the audio sam pling frequency (LRCIN) typically 32kHz, 44.1kHz, 48 or 96kHz. The syst em clock is used to operate the digital filters and the noi se shaping circuits.

S (Philips left justified, one bit

S or normal),

WM8736 has a system clock det ection circuit that autom atically determines what the sys tem clock frequency relative to the sam pling rate is (to within +/- 8 system c locks). If greater than 8 clocks error, then the interface shuts down the DAC and m utes the output. The system clock should be synchronised with LRCIN, but W M8736 is tolerant of phase diff erences or jit ter on this cl ock. Severe distortion in the phase difference between LRCIN and the system clock will be detect ed, and cause the device to automati cally resynchronise. If the externally applied LRCIN slips in phase by more than half the internal LRCIN period, which is derived from master clock, then the interface resynchronises. Such a case would, for example, occur if repeated LRCIN clocks were received with only 252 systems c locks per period. In this case the interface would only resynchronise once every 64 LRCIN periods, even if jitt er was present on the LRCIN signal. During resynchronisation, the device will either repeat the previous sample, or drop the next s ample, depending on the nature of the phase slip. This will ensure no discernible “click“ at the analogue outputs during resynchronisation. Table 1 shows the typical system clock frequency inputs for t he WM8736.

SAMPLING RATE

Table 1 System Clock Frequencies Versus Sampling Rate

AUDIO DATA INTERFACE

The Serial Data interface to WM8736 is fully compatible with both normal (MSB first, ri ght-justified) or

S interfaces. Data m ay be ‘packed’ (number of serial bit clocks per LRCIN period is exactly 2 times the number of data bits, i.e. normally 32 in 16-bit m ode) or unpacked (more than 32 bit clocks per LRCIN period).

SYSTEM CLOCK FREQUENCY (MHZ)

(LRCIN)

32kHz 8.192 12.288 16.384

44.1kHz 48kHz 12.288 18.432 24.576 96kHz 24.576 36.864

256fs 384fs 512fs

16.9340 22.5792

The WM8736 will automatically detect 16-bit packed data being sent to the device in norm al mode, and accept the data in this i nput format accordingly.

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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WM8736 Production Data

S MODE DESCRIPTION

0 Normal format (MSB-f i rst, right Justified) 1I

Table 2 Serial Interface Formats

LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

S format (Philips serial data protocol )

1/fs

DIN

123

MSB MSB LSB

Figure 4 ‘Normal’ Data Input Timing

LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

DIN

123

MSB

Figure 5 I2S Data Input Timing

123

MSB LSBLSB

123

nn-1n-2

LSB

1/fs

nn-1n-2

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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Production Data WM8736

MODES OF OPERATION

Control of the various modes of operation i s either by software control over the serial interf ace, or by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins.

FUNCTION

OPTIONS

Input audio data format Normal format

S format

Input word length 16

18 20 24

De-emphasis selection On

Off

Mute On

Off

Reset and power down

control

WM8736 off WM8736 on

Input LRCIN polarity Lch/Rch =

High/Low

Lch/Rch =

Low/High

Volume control Lch, Rch

individually

Lch, Rch common

Infinite zero detect On

Off

Operation enable (OPE) Enabled

Disabled

DAC output control See Table 7

for all options

SOFTWARE CONTROL

DEFAULT VALUE

PIN 8: MODE = 0

S = 0 (default)

S = 1

IW[1:0] = 00 (default)

IW[1:0] = 11 IW[1:0] = 01 IW[1:0] = 10

DE = 1

DE = 0 (Default)

MU = 1

MU = 0 (default)

Pin 12, 13: ML/I2S, MC/IWL = 11 (I

HARDWARE CONTROL

BEHAVIOUR

PIN 8: MODE = 1

Pin 12, 13: ML/I2S, MC/IWL =

00 or 01 or 10 Pin 12, 13: ML/I2S, MC/IWL = 11 Pin 12, 13: ML/I2S, MC/IWL = 00

Pin 12, 13: ML/I2S, MC/IWL = 01 Pin 12, 13: ML/I2S, MC/IWL = 10

Pin 14: MD/DM = 1 Pin 14: MD/DM = 0

Pin 9: MUTE = 1 Pin 9: MUTE = 0

Available from Pin 10: RSTB Pin 10: RSTB = 0

Pin 10: RSTB = 1

LRP = 0 (default)

Not available in hardware mode,

default value set

LRP = 1

ATC = 0; 0dB (default)

Not available in hardware mode,

default 0dB

ATC = 1

IZD = 1

IZD = 0 (default)

OPE = 0 (default)

OPE = 1

Automute functi on controlled

from MUTE pin

low = not mute

Z = automute enable

high = muted

Default is PL[3:0] = 1001, stereo mode Not available in hardware mode

S only)

Table 3 Control Function Summary

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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WM8736 Production Data

HARDWARE CONTROL MODES

When the MODE pin is hel d hi gh the following hardware modes of operation are available.

MUTE AND AUTOMUTE OPERATION

In both hardware and software modes pin 9 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal.

IZD (Register Bit)

AUTOMUTED

(Internal Signal)

10k

Ω

MUTE

MU (Register Bit)

Figure 6 Mute Circuit Operation

The MUTE pin behaves as a bi-directional function, that is, as an input to selec t MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is act ive high; taking the pin high causes the filters to sof t m ut e, ram ping down the audio signal over a few m illisec onds. Tak ing MUTE low again allows data into the filter.

SOFTMUTE (Internal Signal)

The automute function det ects a series of zero value audio samples of 1024 s amples long being applied to both left and right channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kohm resist or to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE.

If MUTE is tied low, AUTOMUTED is overidden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute f unctions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) s o can be used to drive external mute circuits.

The automute signal is AND’ed with IZD, this qualified mute signal then being OR’ed into the SOFTMUTE control. Therefore, in sof tware mode, automute operation may be control led with IZD control bit.

I2S INPUT FORMAT SELECTION AND MC/IWL INPUT FORMAT SELECTION

In hardware mode, pins 12 and 13 become input controls f or selection of input data form at type and input data word length, see Table 4. I enough bit clocks are sent.

S MC/IWL INPUT DATA MODE

0 0 16-bit normal 0 1 20-bit normal 1 0 24-bit normal 11I

Table 4 Control of Input Data Format Type and Input Data Word Length

S mode is designed to support any word length provided

S mode

MD/DM DE-EMPHASIS

In hardware mode, pin 14 becomes an input control for selection of de-emphasis filtering to be applied. see Table 5.

MD/DM 0 De-emphasis off MD/DM 1 De-emphasis on

Table 5 De-emphasis Control

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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Production Data WM8736

RSTB RESET AND POWER DOWN CONTROL

In both hardware and software modes, this pin resets the entire device when taken low. The device remains powered down while RSTB is held low.

RSTB 0 Device powered down and reset RSTB 1 Device powered up and active

Table 6 Reset and Power Down Control

SOFTWARE CONTROL INTERFACE

The WM8736 can be controlled using a 3-wire serial interface. MD/DM (pin 6) is used for the program data, MC/IWL (pin 5) is used to clock in the program dat a and ML/I2S (pin 4) is use to latch i n the program data. The 3-wire interface protoc ol i s shown in Figure 7.

ML/I2S

MC/IWL

MD/DM

Figure 7 3-Wire Serial Interface

REGISTER MAP

WM8736 controls the special functions using 9 program registers, which are 16-bits long. These registers are all loaded through input pi n MD/DM. After the 16 data bits are clocked in, ML/I 2S is used to latch in the data to the appropriate regist er. Table 7 shows the complete mapping of the 9 registers.

B2 B1 B0 A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0

NOT USED ADDRESS DATA M0 M1 M2 M3 M4 M5 M6 M7 M8

Table 7 Mapping of Program Registers

- - - 0 0 0 0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0

- - - 0 0 0 1 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

- - - 0 0 1 0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DE MU

---0011IZD-----ATCLRPI

- - - 0 1 0 0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0

- - - 0 1 0 1 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

- - - 0 1 1 0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0

- - - 0 1 1 1 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

- - - 1 0 0 0 LDM AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

D6D7D8A0A1A2A3B0 D1D2D3D4D5 D0B2 B1

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WM8736 Production Data

A[3:0] = 0000

A[3:0] = 0001

A[3:0] = 0010

A[3:0] = 0011

A[3:0] = 0100

A[3:0] = 0101

A[3:0] = 0110

A[3:0] = 0111

A[3:0] = 1000

Table 8 Internal Register Mapping

AL[7:0]

LDL

AR[7:0]

LDR

OPE IW[1:0] PL[3:0]

I2S LRP ATC

SF[1:0]

IZD

AL[7:0]

LDL

AR[7:0]

LDR

AL[7:0]

LDL

AR[7:0]

LDR

AM[7:0]

LDM

1111 1111

0 0 0 0

1001

0 0 0

1111 1111

Attenuation data for left channel DAC 0 Attenuation data load control for left channel DAC 0 Attenuation data for right channel DAC 0 Attenuation data load control for right channel DAC 0 Left and right DACs soft mute control De-emphasis control Left and right DACs operation c ont rol Input audio word resolution DAC output control Audio data format select Polarity of LRCIN (pin 4) Select Attenuator control Sampling rate select Infinite zero detection circuit control and automute control Attenuation data for left channel DAC 1 Attenuation data load control for left channel DAC 1 Attenuation data for right channel DAC 1 Attenuation data load control for right channel DAC 1 Attenuation data for left channel DAC 2 Attenuation data load control for left channel DAC 2 Attenuation data for right channel DAC 2 Attenuation data load control for right channel DAC 2 DAC attenuation data for all c hannel s Attenuation data load control for all channels

DAC OUTPUT ATTENUATION

Registers M0 and M1 control the left and right channel attenuation of DAC 0. Registers M4 and M5 control the left and right channel attenuation of DAC 1. Regi st ers M6 and M7 cont rol the l eft and right channel attenuation of DAC 2. Register M8 is a master register that can be used to control attenuation of all channels .

Register M0 (A[3:0] = 0000) is used to control left channel 0 attenuat ion. Bits 0-7 (AL[ 7:0]) are used to determine the attenuat i on l evel (Tabl e 9). The level of attenuation is given by:

Attenuation = [20.log10 (At t enuation_Data/256)] dB

AX[7:0] ATTENUATION LEVEL

00(hex) -∞dB (mute) 01(hex) -48.16dB

:: ::

:: FE(hex) -0.07dB FF(hex) 0dB

Table 9 Attenuation Control Levels

Bit 8 in register M0 (LDL) is used t o control the loading of attenuation dat a in AL[7: 0]. W hen LDL is set to 0, attenuation data will be loaded into AL[7:0], but it will not affect the attenuation level unt il LDL is set to 1.

Register M1 (A[1:0] = 01) is used to control right channel attenuation in the same manner. Attenuation of DAC 1 and 2 are similarly controlled.

Bit 2 in register M3 (A[3:0] = 0011) is used to cont rol the attenuator (ATC). W hen ATC is high, the attenuation data loaded in the left channel program register is used for both the left and the right channels. Therefore, DAC 0 att enuation data for left and right channels is read f rom register M0, DAC 1 attenuation data for left and right channels is read from register M4 and DAC 2 attenuation data for left and right channels is read from regis ter M6. W hen ATC is low, attenuat ion data is read from the individual left and right DAC registers.

Eqn. 1

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Production Data WM8736

The master gain register M8 (A[3:0] = 0110) is used to write a gain value to all channels simultaneously. Bit 8 (LDM) controls the update in the sam e way as the attenuati on registers, and i s to be set to 1 for correct operat i on i n t hi s mode.

LEFT AND RIGHT DAC SOFT MUTE CONTROL

Soft mute is controlled by setting bit MU, register M2:bit 0. A high level on MU (MU = 1) will cause the output to be muted, the effect of which is t o ramp the signal down in the digital dom ain so that there is no discernible cli ck. This can be seen in Figure 6 Mute Circ ui t Operation.

DE-EMPHASIS CONTROL

Bit 1 (DE) in register M2 is us ed to c ontrol di gita l de-em phasi s. A low level on bit 1 (DE = 0) dis ables de-emphasis whilst a high level enables de-emphasis (DE = 1). De-emphasis applied to the filters shapes the frequency response of the digital filter acco rdi ng t o the input sample frequency.

LEFT AND RIGHT DAC OPERATION CONTROL

Bit 2 (OPE) in register M2 is used for operation control. W ith OPE = 0 (default ) the device functions normally. With OPE = 1 the device is disabled and the outputs are held at midrail. Current consumption of the digital section is minimized, but analogue sections remain active in order to preserve d.c. levels.

INPUT AUDIO WORD RESOLUTION

WM8736 allows maximum flexibility over the cont rol of t he audio dat a interfac e, allowing s election of format type, word length, and sample rates. Bits 3 and 4 of register M2 (IW[1:0]) are used to determine the input word resolution. W M8736 supports 16-bit, 18-bit, 20-bit and 24-bit formats as described in Table 10.

BIT 4 (IW1) BIT 3 (IW0) INPUT RESOLUTION

0 0 16-bit data word 0 1 20-bit data word 1 0 24-bit data word 1 1 18-bit data word

Table 10 Input Data Resolution

DAC OUTPUT CONTROL

Bits 5, 6, 7 and 8 (PL[3:0]) of register M2 are used to control t he out put format as shown in Table 11.

PL3 PL2 PL1 PL0 LEFT OUTPUT RIGHT OUTPUT NOTE

0 0 0 0 MUTE MUTE Mute both channels 0 001 L MUTE 0 010 R MUTE 0 011 (L + R)/2 MUTE 0 100 MUTE L 0 101 L L 0 1 1 0 R L Reverse channel s 0 111 (L + R)/2 L 1 000 MUTE R 1 0 0 1 L R S tereo mode 1 010 R R 1 011 (L + R)/2 R 1 100 MUTE (L + R)/2 1 101 L (L + R)/2 1 110 R (L + R)/2 1 1 1 1 (L + R)/2 (L + R)/ 2 Mono mode

Table 11 Programmable Output Format

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

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WM8736 Production Data

SERIAL PROTOCOL

Bits 0 (I2S) and 1 (LRP) of register M3 are used to c ontrol t he input dat a f orm at c om pletel y. A low on

bit 0 (I

S = 0) sets the format to Normal (MSB-first, right just ified Japanese format), whilst a high

S = 1) sets the format to I2S (Philips serial data protocol).

POLARITY OF LRCIN SELECT

Bit 1 (LRP) of register M3 is us ed to control t he polarity of LRCIN (s ample rate c lock). W hen bit 1 is low (LRP = 0), left channel data is ass um ed when LRCIN is in a high phase and ri ght c hannel data i s assumed when LRCIN is in a low phase. When bit 1 is high (LRP = 1), the polarity assumption is reversed.

INTERFACE CLOCKS AND SAMPLING RATES

Bits 6 (SF0) and 7 (SF1) of regist er M3 are used to control the sampli ng frequency, as shown in Table 12.

SF0 SF1 SAMPLING FREQUENCY

0 0 44.1kHz group 22.05 / 44.1 / 88.2kHz 0 1 48kHz group 24 / 48 / 96kHz 1 0 32kHz group 16 / 32 / 64kHz 1 1 Reserved Not defined

Table 12 Sampling Frequencies

INFINITE ZERO DETECTION

Bit 8 (IZD) in register M3 controls operation of the automute f unction. If IZD (I nfinite Zero Detect) is high, 1024 consecutive zero audio samples will force t he ouput to zero. See Figure 6. Note that the control of pin MUTE also affect s automute operat ion. To turn off automute, pin MUTE mus t be held low as well as IZD being low (default).

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

Page 15

Production Data WM8736

RECOMMENDED EXTERNAL COMPONENTS

DVDD

DGND

Software I/F or

Hardware Control

Audio Serial Data I/F

NOTES: 1. AGND and DGND should be connected as close to the WM8736 as possible.

, C3, C4 and C12 should be positioned as close to the WM8736 as possible.

2. C

3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance.

DVDD

DVSS

ML/I2S

MC/IWL

MD/DM0

RSTB

MODE

WM8736

MUTE

SCKI

BCKIN

LRCIN

DIN0

DIN1

DIN2

AVDD1 AVDD2

AVSS1 AVSS2

OUT0R

OUT0L

OUT1R

OUT1L

OUT2R

OUT2L

GR0 GR1 GR2

CAP

15 28

20 24

26 22 18

C3C4C

+ + + + + +

AGND

AVDD

AGND

AC-Coupled OUT0R/L to External LPF

AC-Coupled OUT1R/L to External LPF

AC-Coupled OUT2R/L to External LPF

Figure 8 External Components Diagram

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

C1 and C5 10µF

C2 to C4 0.1µF

C6 to C11 10µF

C12 0.1µF C13 10µF

Table 13 External Components Description

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

SUGGESTED

VALUE

DESCRIPTION

De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Output AC coupling caps t o remove midrail DC level from outputs. Reference de-coupling capacit ors for CAP pin.

Page 16

WM8736 Production Data APPLICATIONS RECOMMENDED

SURROUND SOUND

DECODER

(FRONT)

(SURROUND)

(CENTRES/SUBWOOFER)

BCK

LRCK

DATA

DATA DATA

WM8736

DAC

FRONT

MCU

256fs OR 384fs

DAC

SURROUND

CENTRE

SUBWOOFER

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001

Page 17

Production Data WM8736

PACKAGE DIMENSIONS

DM007.CDS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)

Symbols

A A

b c D e E E

Dimensions

(mm)

MIN NOM MAX

----- ----- 2.0

0.05 ----- -----

1.62 1.75 1.85

0.22 ----- 0.38

0.09 ----- 0.25

9.90 10.20 10.50

0.65 BSC

7.40 7.80 8.20

5.00 5.30 5.60

0.55 0.75 0.95

E1 E

0.10

-C-

SEATING PLANE

GAUGE PLANE

0.25

REF:

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

JEDEC.95, MO-150

WOLFSON MICROELECTRONICS LTD PD Rev 2.1 January 2001