Datasheet WM8143-10CFT-V Datasheet (Wolfson)

Page 1

WM8143-10

10-bit/6MSPS CCD Signal Processor

Production Data June 1998 Rev 3f

Description

The WM8143-10 integrates the analogue signal conditioning required by CCD sensors with a 10-bit ADC. The WM8143-10 requires minimal external circuitry and provides a cost-effective sensor to digital domain system solution.

Each of the three analogue conditioning channels includes reset level clamp, CDS, fine offset level shifting and programmable gain amplification. The three channels are multiplexed into the ADC. The output from the ADC is fed to the output bus pins OP[9:0] via a 10/8 bit multiplexer, enabled by the OEB signal.

The flexible output architecture allows ten-bit data to be accessed either on a ten-bit bus or via a time-multiplexed eight-bit bus. The WM8143-10 can be configured for pixel-by-pixel or line-by-line multiplexing operation. Reset level clamp and/or CDS features can be optionally bypassed. The device configuration is programmed either via a simple serial interface or via an eight-bit parallel interface.

The serial/parallel interfaces of the WM8143-10 are control compatible with those of the WM8144-10 and WM8144-12.

Features

• Reset level clamp

• Correlated double sampling (CDS)

• Fine offset level shifting

• Programmable gain amplification

• 10-bit ADC with maximum 6 MSPS

• Simple clocking scheme

• Control by serial or parallel interface

• Time multiplexed eight-bit data output mode

• 32 pin TQFP package

• Interface compatible with WM8144-10 and

WM8144-12

Applications

• Flatbed scanners

• Sheet feed scanners

• Film scanners

• CCD sensor interfaces

• Contact image sensor (CIS) interfaces

Block Diagram

VRLC VRU VRT VRB VMID

VMID

RINP

GINP

BINP

Production Data datasheets

contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronic's terms and conditions.

S/H

CDS

S/H

CDS

S/H

CDS

MUX

5-BIT REG

PGA

8-BIT + SIGN DAC

VSMP MCLK RLC DGND DVDD AVDD

TIMING CONTROL

OFFSET

+ +

VMID

OFFSET

+ +

VMID

OFFSET

+ +

VMID

M U X

AGND

Wolfson Microelectronics

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK

Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176

email: [email protected]

www: http://www.wolfson.co.uk

WM8143-10

10-bit

ADC

CONFIGURABLE

SERIAL/PARALLEL

CONTROL INTERFACE

10/8

MUX

1998 Wolfson Microelectronics Ltd.

OEB

OP[9:0]

SDI / DNA SCK / RNW SEN / STB NRESET

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WM8143-10 Production Data

AGND - 0.3V, AGND +7V

DGND - 0.3V, DGND +7V

DGND - 0.3V, DVDD +0.3V

AGND - 0.3V, AVDD +0.3V

0.3V

Pin Configuration Ordering Information

DEVICE TEMP. RANGE PACKAGE

SDI/DNA

SEN/STB

OEB

RINP

GINP

BINP

VRLC

VMID

WM8143-10CFT/V

0 - 70oC 32 Pin TQFP

SCK/RNW

RLC VSMP MCLK

DGND

DVDD

25 26 27 28 29 30

nc nc

31 32

OP[0]

WM8143-10

OP[3]

OP[2]

OP[1]

OP[4]

OP[5]

OP[6]

OP[7]

VRT

VRB

VRU

AGND

13 12

AVDD NRESET

OP[9]

OP[8]

Absolute Maximum Ratings

Analogue Supply Voltage ..........

Digital Supply Voltage ...............

Digital Inputs..........................

Digital Outputs .......................

Reference Inputs ....................

RINP, GINP, BINP.................. AGND - 0.3 V, AVDD +

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified

Operating Temperature Range, TA .......... 0°C to +70°C

Storage Temperature.......................... -50°C to +150°C

Lead Temperature (soldering 10 seconds)....... +260°C

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

As per JEDEC specifications A112-A and A113-A, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags.

Recommended Operating Conditions

PARAMETER SYMBOL TEST

Supply Voltage Operating Temperature Range Input Common Mode Range

AVDD, DVDD 4.75 5.25 V

CMR

Wolfson Microelectronics PD Rev 3f June 98

CONDITIONS

MIN TYP MAX UNIT

0 70

0.5 4.5 V

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Production Data WM8143-10

Electrical Characteristics

Test Characteristics

AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated

PARAMETER SYMBOL TEST

Supply Current - Active Supply Current - Standby

Digital Inputs

High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance

Digital Outputs

High Level Output Voltage Low Level Output Voltage High Impedance Output

Current

Input Multiplexer

CDS Mode Full Scale Input Range (VVS-VRS)

Channel to Channel Gain Matching

Input Video Set-up Time Input Video Hold Time Reset Video Set-up Time Reset Video Hold Time

Reference String

Reference Voltage – Top Reference Voltage – Bottom DAC Reference Voltage R.L.C. Switching Impedance Reset Level Clamp Options

Impedance VRT to VRB Impedance VRU to AGND

8-Bit DACs

Resolution Zero Code Voltage Full Scale Voltage Error

tVSU 10 ns

tVH 15 ns

tRSU CDS Mode only 10 ns

tRH CDS Mode only 15 ns

VRT VRU = 5V 3.47 3.5 3.53 V VRB VRU = 5V 1.47 1.5 1.53 V

VMID VRU = 5V 2.47 2.5 2.53 V

VRLC VRU=5V Voltage set

MIN TYP MAX UNIT

CONDITIONS

100 140 mA

7 15 mA

0.8*DVDD V

0.2*DVDD V 1 µA 1 µA

5 pF

IOH = 1mA DVDD-0.75 V

IOL= 1mA DGND+0.75 V

1 µA

x denotes the

channel selected

by register

configuration

1.46 1.5 1.54 V

2.46 2.5 2.54 V

3.46 3.5 3.54 V 250 500 750

1000 1500 2000

8 Bits

MID

-20 V

0 20 mV

1 %

500

MID

+20 mV

Vp-p

Ω

Ω Ω

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WM8143-10 Production Data

Test Characteristics

AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated

PARAMETER SYMBOL TEST

CONDITIONS

Differential Non Linearity Integral Non Linearity

10-bit ADC performance including CDS, PGA and Offset Functions NO MISSING CODES GUARANTEED

Resolution Maximum Sampling Rate Zero Scale Transition Error

Voltage at VINP

Full Scale Transition Error Voltage at VINP

Differential Non Linearity

PGA Gain Monotonicity Guaranteed

Red Channel Max Gain Green Channel Max Gain Blue Channel Max Gain

Switching Characteristics

MCLK Period MCLK High MCLK Low Data Set-up Time Data Hold Time Output Propagation Delay Output Enable Time Output Disable Time

Serial Interface

SCK Period SCK High SCK Low SDI Set up Time SDI Hold Time Set up Time - SCK to SEN Set up Time - SEN to SCK

DNL 0.1 0.5 LSB

INL 0.25 1 LSB

AVDD = DVDD = 5V 10 Bits AVDD = DVDD = 5V 6 MSPS

DAC Code = 000H,

AVDD = DVDD = 5V,

measured relative to

VRB

DAC Code = 000H,

AVDD = DVDD = 5V,

measured relative to

VRT

DNL AVDD = DVDD = 5V +1 LSB

Gr 7 7.5 Times Gg 7.5 8 Times Gb

tPER 83.3 ns tCKH 37.5 ns

tCKL 37.5 ns

tDSU 10 ns

tDH 10 ns

tPD IOH=1mA, IOL=1mA 75 ns tPZE 50 ns tPEZ 25 ns

tSPER 83.3 ns tSCKH 37.5 ns tSCKL 37.5 ns

tSSU 10 ns

tSH 10 ns tSCE 20 ns tSEC 20 ns

Mode 1

AVDD = DVDD = 5V

MIN TYP MAX UNIT

± 25 ±100 mV

7.5 8 Times

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Production Data WM8143-10

Test Characteristics

AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated

PARAMETER SYMBOL TEST

SEN Pulse Width

Parallel Interface

RNW Low to OP[9:2] Tri-state Address Setup Time to STB

Low DNA Low Setup Time to STB

Low Strobe Low Time Address Hold Time from STB

High DNA Low Hold Time from

STB High Data Setup Time to STB Low DNA High Setup Time to STB

Low Data Hold Time from STB

High Data High Hold Time from

STB High RNW High to OP[9:2] Output

tSEW 50 ns

tOPZ 20 ns tASU 0 ns

tADLS 10 ns

tSTB 50 ns

tAH 10 ns

tADLH 10 ns

tDSU 0 ns

tADHS 10 ns

tDH 10 ns

tADHH 10 ns

tOPD 0 ns

MIN TYP MAX UNIT

CONDITIONS

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WM8143-10 Production Data

Pin Description

PIN NAME TYPE DESCRIPTION

1 OP[0] Digital OP 2 OP1] Digital OP 3 OP[2] Digital IO

4 OP[3] Digital IO 5 OP[4] Digital IO 6 OP[5] Digital IO 7 OP[6] Digital IO 8 OP[7] Digital IO

9 OP[8] Digital IO 10 OP[9] Digital IO 11 NRESET Digital IP

12 AVDD Analogue supply 13 AGND Analogue supply 14 VRU Analogue IP

15 VRB Analogue OP 16 VRT Analogue OP 17 VMID Analogue OP

18 VRLC Analogue OP 19 BINP Analogue IP 20 GINP Analogue IP 21 RINP Analogue IP 22 OEB Digital IP 23 SEN/STB Digital IP

24 SDI/DNA Digital IP

25 SCK/RNW Digital IP

26 RLC Digital IP

27 VSMP Digital IP

28 MCLK Digital IP

Tri-state digital 10-bit bi-directional bus. There are four modes: Tri-state: when OEB = 1 Output ten-bit: ten bit data is output from bus Output 8-bit multiplexed: data output on OP[9:2] at 2 * ADC

conversion rate

Input 8-bit: control data is input on bits OP[9:2] in

parallel mode when SCK/RNW = 0.

MSB of the output word is OP[9], LSB is OP[0]

Reset input, active low. This signal forces a reset of all internal registers and selects whether serial control bus or parallel control bus is used ( see SEN/STB)

Positive analogue supply (5V) Analogue ground (0V) ADC reference voltages. The ADC reference range is applied between VRT (full

scale) and VRB (zero level). VRU can be used to derive optimal reference voltages from an external 5V reference

Buffered mid-point of ADC reference string. Selectable analogue output voltage for RLC Blue channel input video Green channel input video Red channel input video Output tri-state control: all outputs enabled when OEB=0 Serial interface: enable, active high Parallel interface: strobe, active low Latched on NRESET rising edge: If low then device control is by serial

interface, if high then device control is by parallel interface Serial interface: serial interface input data signal Parallel interface: high = data, low = address Serial interface: serial interface clock signal Parallel interface: high = OP[9:2] is output bus

low = OP[9:2] is input bus

Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is required on each pixel then this pin can be tied high

Video sample synchronisation pulse. This signal is applied synchronously with MLCK to specify the point in time that the input is sampled. The timing of internal multiplexing between the R, G and B channels is derived from this signal

Master clock. This clock is applied at eight, six, three or two times the input pixel rate depending on the operational mode. MCLK is divided internally to define the ADC sample rate and to provide the clock source for digital logic

Wolfson Microelectronics PD Rev 3f June 98

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Production Data WM8143-10

PGA Gain Code

LSB's

PIN NAME TYPE DESCRIPTION

29 DGND Digital supply 30 nc 31 nc 32 DVDD Digital supply

Digital ground (0V) Reserved, pin must be left unconnected Reserved, pin must be left unconnected Positive digital supply (5V)

Typical Performance

AVDD = DVDD = 5V, TA = 25oC

WM8143-10 DNL

1.5

0.5

-0.5

-1

-1.5

-2 0 256 512 768 1024

ADC Code

PGA Gain Code vs Actual Gain

8.25 8

7.75

7.5

7.25 7

6.75

6.5

6.25 6

5.75

5.5

5.25 5

4.75

4.5

4.25 4

3.75

3.5

3.25 3

2.75

2.5

2.25 2

1.75

1.5

1.25 1

0.75

0.5

0.25 0

0 1 2 3 4 5 6 7 8 9

Actual Gain

RED

GREEN

BLUE

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WM8143-10 Production Data

System Description

COLOUR CCD

SENSOR

RED

GREEN

BLUE

Figure 1 System Diagram

The WM8143-10 signal processing IC interfaces typically via buffering and AC coupling to the output of CCD image sensors. The WM8143-10 also interfaces to CIS image sensors via DC coupling.

Analogue output signals from the image sensor are sampled, amplified and offset-corrected by the IC before being converted into digital form by an on-board high-speed 10-bit resolution analogue to digital converter. Figure 1 illustrates a typical system implementation where the three colour outputs from the CCD image sensor are buffered and AC coupled to the analogue inputs of the WM8143-10.

BUFFERING

FOR CCD

RINP

GINP

BINP

WM8143-10

SCK/RNW

SEN/STB

The digital interface to the WM8143-10 can be divided into three distinct sections: -

• Parallel Data I/O

• Digital Control/Serial Timing

• Analogue Interface Timing

These sections are constructed for ease of use by the system designer and are described in detail on the following pages of this datasheet.

OP[9:0]

OEB

SDI/DNA

NRESET

VSMP MCLK

RLC

PARALLEL DATA I/O

CONTROL/SERIAL DATA IN

ANALOGUE INTERFACE TIMING

Wolfson Microelectronics PD Rev 3f June 98

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Production Data WM8143-10

Device Description

S/H, Offset DACs and PGA

Each analogue input (RINP, GINP, BINP) of the WM8143-10 consists of a sample and hold, a programmable gain amplifier, and a DC offset correction block. The operation of the red input stage is summarised in Figure 2.

RINP

VMID

Figure 2 Operation of Red Input Stage

The sample/hold block can operate in two modes of operation, CDS (Correlated Double Sampling) or Single Ended.

In CDS operation the video signal processed is the difference between the voltage applied at the RINP input when RS occurs, and the voltage at the RINP input when VS occurs. This is summarised in Figure 3

S/H

GAIN=G

+ +

OFFSET

ADC

VMIDV

Table 1 illustrates the PGA Gains Register codes required for typical gains. (See Typical Performance Graphs). The typical gain may also be calculated using the following equation:

Typical Gain = 0.5+(Code∗0.25).

CODE TYPICAL

GAIN

CODE TYPICAL

GAIN

00000 0.5 10000 4.5 00001 0.75 10001 4.75 00010 1 10010 5 00011 1.25 10011 5.25 00100 1.5 10100 5.5 00101 1.75 10101 5.75 00110 2 10110 6 00111 2.25 10111 6.25 01000 2.5 11000 6.5

01001 2.75 11001 6.75

RS VS

Figure 3 Video Signal Processed in CDS mode

When using CDS the actual DC value of the input signal is not important, as long as the signal extremes are maintained within 0.5 volts of the chip power supplies. This is because the signal processed is the difference between the two sample voltages, with the common DC voltage being rejected.

In Single Ended operation, the VS and RS control signals occur simultaneously, and the voltage applied to the reset switch is fixed at V

MID

. This means that the voltage processed is the difference between the voltage applied to RINP when VS/RS occurs, and V

MID

. When using Single Ended operation the DC content of the video signal is not rejected.

The Programmable Gain Amplifier block multiplies the resulting input voltage by a value between 0.5 and 8.25 which can be programmed independently for each of the three input channels via the serial (or parallel) interface.

01010 3 11010 7 01011 3.25 11011 7.25 01100 3.5 11100 7.5 01101 3.75 11101 7.75 01110 4 11110 8 01111 4.25 11111 8.25

Table 1 Typical Gain

The DC value of the gained signal can then be trimmed by the 8 bit plus sign DAC. The voltage output by this DAC is shown as V DAC is (V

MID

/2) or 1.5*(V

in Figure 2. The range of the

OFFSET

MID

/2) if the DAC_RANGE bit

in Set-up Register 4 is set. The output from the offset DAC stage is referenced to

MID

the V

voltage. This allows the input to the ADC to maximise the dynamic range, and is shown diagrammatically in Figure 2 by the final V

MID

addition.

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WM8143-10 Production Data

For the input stage, the final analogue voltage applied to the ADC can be expressed as:

MID

][

+−+−=

MIDRSVSADC V

Where V

DAC_CODE

*DSIGN)*2(1)V(V*GV

255

is the voltage applied, to the ADC

ADC

G is the programmed gain VVS is the voltage of the video sample. VRS is the voltage of the reset sample, DSIGN is the Offset DAC sign bit DAC_CODE is the offset DAC value. V

is the WM8143-10 generated VMID voltage.

MID

The ADC has a lower reference of VRB (typically 1.5 V) and an upper reference of VRT (typically 3.5 V). When an ADC input voltage is applied to the ADC equal to VRB the resulting code is 000(hex). When an ADC input voltage is applied to the ADC equal to VRT the resulting code is 3FF(hex).

Reset Level Clamp

Both CDS and Single Ended operation can be used with Reset Level Clamping. A typical input configuration is shown in Figure 4.

WM8143-10

RINP

Cin

VMIDVRLC

S/H

Gain=G

dependent on the type of sampling selected and the polarity of the input video signal.

MCLK VSMP

VS CL

RS CL

(default)

RS CL

Figure 5 Reset Sample and Clamp Timing

For CDS operation it is important to match the clamp voltage to the amplitude and polarity of the video signal. This will allow the best use of the wide input common-mode range offered by the WM8143-10. If the input video is positive going it is advisable to clamp to VCL (Lower clamp voltage). If the video is negative going it is advisable to clamp to VCU (Upper clamp voltage). Regardless of where the video is clamped the offset DAC is programmed to move the ADC output corresponding to the reset level to an appropriate value to maximise the ADC dynamic range. For Single Ended operation it is recommended that the clamp voltage is set to VCM (middle clamp voltage).

Figure 4 Typical Input Configuration Using Reset Level Clamping

The position of the clamp relative to the video sample is shown diagramatically in Figure 6 and is programmable by CDSREF1-0 (see Table 6). By default, the reset sample occurs on the fourth MCLK rising edge after VSMP. The relative timing between the reset sample (and CL) and video sample can be altered as shown in Figure 5. When the clamp pulse is active the voltage on the WM8143-10 side of Cin, i.e. RINP, will be forced to be equal to the VRLC clamp voltage. The VRLC clamp voltage is programmable to three different levels via the serial interface. The voltage to which the clamp voltage should be programmed is

Wolfson Microelectronics PD Rev 3f June 98

VIDEO INPUT

CLAMP PULSE

Figure 6 Position of Clamp Relative to Video Input

A reset level clamp is activated if the RLC pin is high on an MCLK rising edge (Figure 7). By default this initiates an internal clamp pulse three MCLK pulses later (shown as CL in Figure 5). The relationship between CL and RS is fixed. Therefore altering the RS position also alters the CL position (Figure 5). Table 6 shows the three possible voltages to which the reset level can be clamped.

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Production Data WM8143-10

Input video

to 4 MSPS. This is achieved by altering the

MCLK

VSMP

1 X X 0

RLC

r,g,b r,g,b

RLC on this pixel

0XXX

r,g,b

No RLC on this pixel

MCLK:VSMP ratio to 3:1. In this mode, the timing of RS and CL must be fixed (refer to Table 3). The sampled video data will pass through the internal pipeline and emerge on the OP[9:0] bus.

Max. Speed Monochrome Mode (Mode 4)

Figure 12 summarises the timing relationships. This

Figure 7 RLC Timing

mode allows the maximum sample rate to be increased to 6 MSPS. This is achieved by altering the

Video Sampling Options

The WM8143-10 can interface to CCD sensors using six basic modes of operation (summarised in Table 3). Mode configurations are controlled by a combination of control bits and timing applied to MCLK and VMSP pins. The default operational mode is mode 1: colour with CDS enabled.

Colour Mode Definitions (Mode 1)

Figure 9 summarises the timing relationships. MCLK is applied at twice the required ADC conversion rate. Synchronisation of sampling and channel multiplexing to the incoming video signal is performed by the VSMP pulse (active high). The three input channels (R,G,B) are sampled in parallel on the rising edge of MCLK following a VSMP pulse. The sampled data is multiplexed into a single data stream at three times the VSMP rate, passes through the internal pipeline and emerges on the OP[9:0] bus. Both Correlated Double Sampling (CDS) and Single Ended Sampling modes of operation are available.

MCLK:VSMP ratio to 2:1. The latency through the device is identical to modes 1 and 2. CDS is not available in this mode.

Slow Colour Mode (Mode 5)

Figure 13 summarises the timing relationships. This mode is identical to Mode 1 except that the MCLK to VSMP ratio is 8 : 1 and the maximum sample rate is

1.5 MSPS. To obtain a ratio of 4:4 between the video sample position and the reset sample position, Setup Register 3 CDSREF1-0 control bits b[5:4] should be set to 10. The first three of the four output words are valid.

Slow Monochrome Mode (Mode 6)

Figure 14 summarises the timing relationships. This mode is identical to mode 2 except that the MCLK to VSMP ratio is 8 : 1 and the maximum sample rate is

1.5 MSPS. To obtain a ratio of 4:4 between the video sample position and the reset sample position, Setup Register 3 CDSREF 1-0 control bits b[5:4] should be set to 10. The first of the four output words is the only valid output.

Monochrome Mode Definitions

One input channel is continuously sampled on the rising edge of MCLK following a VSMP pulse. The user can specify which input channel (R,G,B) is to be sampled by writing to the WM8143-10 internal control registers. There are four separate monochrome modes

Input Impedance

The input impedance of the WM8143-10 is dependent upon the sampling frequency of the input signal and the gain that the PGA is set to. This is due to the effective capacitance of the ‘sample and hold’ circuits (Figure 8)

with different maximum sample rates and CDS availability.

Monochrome Mode (Mode 2)

Figure 10 summarises the timing relationships. The timing in this mode is identical to mode 1 except that

RINP/VMID

S/H

PGA

VMID

one input channel is sampled three times (due to the multiplexer being held in one position) and passes

VS/RS

through the device as three separate samples. The last two samples can be ignored at the output OP[9:0].

Fast Monochrome Mode (Mode 3)

Figure 11 summarises the timing relationships. This mode allows the maximum sample rate to be increased

Figure 8 Input Impedance S/H Circuit

When the VS/RS control is activated the switch closes and the effective impedance of the input is 1/CF where the value of C changes from 0.3pF for minimum gain to

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WM8143-10 Production Data

9.6pF for maximum gain and F is the sample frequency in Hz. Table 2 illustrates the maximum and minimum input impedance at different frequencies.

SAMPLING

FREQUENCY

(MHz)

0.5 6.6 208 1 3.3 104 2 1.6 52 4 0.8 26 6 0.5 17

Table 2 Effects of Frequency on Input Impedance

IMPEDANCE

(MΩΩ) MIN.

GAIN

IMPEDANCE

(KΩΩ) MAX.

GAIN

Calibration

To achieve optimum performance of the WM8143-10, a calibration procedure must be implemented. This is achieved by using a combination of the gain and offset functions to amplify and shift the input signal so that it lies within and maximises the input ADC range.

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Production Data WM8143-10

MODE DESCRIPTION CDS

AVAIL-

ABLE

1 Colour Yes 2MSPS Three input channels

2 Monochrome Yes 2MSPS One input channel is

3 Fast

Monochrome

4 Max. Speed

Monochrome

5 Slow Colour Yes 1.5MSPS Identical to Mode 1

6 Slow

Monochrome

* Only indicates relevant register bits

Yes 4MSPS Identical to Mode 2

No 6MSPS Identical to Mode 2

Yes 1.5MSPS Identical to Mode 2

MAX.

SAMPLE

RATE

SENSOR INTERFACE

DESCRIPTION

(R, G, B) are sampled in parallel at max. 2MSPS. The sampled data is multiplexed into a single data stream before the internal ADC, giving an internal serial rate of max. 6MSPS

continuously sampled. The internal multiplexer is held in one position under control of the user.

except that max. sample rate is 4MSPS

except that max. sample rate is 6MSPS

except that max. sample rate is

1.5MSPS

except that max. sample rate is

1.5MSPS

TIMING

REQUIRE-

MENTS

MCLK max. 12MHz. MCLK: VSMP ratio is 6:1

Identical to Mode 1

MCLK max. 12MHz. MCLK: VSMP ratio is 3:1

MCLK max. 12MHz. MCLK: VSMP ratio is 2:1

MCLK max. 12MHz. MCLK: VSMP ratio is 8:1

MCLK max. 12MHz. MCLK:

VSMP ratio is 8:1

CONTENTS

WITH CDS

CONTENTS

WITHOUT

CDS*

Setup Reg. 1: 03(H)

Setup Reg. 1: 07(H) Setup Reg. 3: bits b[7-6] define which channel is sampled

Identical to Mode 2 plus Setup Reg. 3: bits b[5-4] must be set to 00(H)

Not applicable Setup Reg.

Identical to Mode 1

Identical to Mode 2

Setup Reg. 1: 01(H)

Setup Reg. 1:05(H) Setup Reg. 3: bits b[7-6] define which channel is sampled

Identical to Mode 2

1:45(H) Setup Reg. 3: bits b[7-6] define which channel is sampled

Identical to Mode 1

Identical to Mode 2

Table 3 WM8143-10 Mode Summary

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WM8143-10 Production Data

INPUT

SIGNALS

INTERNAL

SIGNALS

OUTPUT

SIGNALS

MCLK

VSMP

Input

video

ADC input

ADC sample

OP[9:0]

r1,g1,b1

16.5 MCLK periods

r2,g2,b2

g2r2 g3r3

Figure 9 Default Timing in CDS Colour Mode (Mode 1)

r3,g3,b3

b2 b3 r4

r4,g4,b4

r5,g5,b5

INPUT

SIGNALS

INTERNAL

SIGNALS

OUTPUT

MCLK

VSMP

Input

video

ADC input

ADC sample

OP[9:0] *

r1,g1,b1

16.5 MCLK periods

r2,g2,b2

r3,g3,b3

X X

SIGNALS

* This example shows function when Red channel selected.

'X' indicates don't care

Figure 10 Default Timing in CDS Monochrome Mode (Mode 2)

r4,g4,b4

r5,g5,b5

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Production Data WM8143-10

MCLK

INPUT SIGNALS

VSMP

Input video

n+1

INTERNAL

SIGNALS

OUTPUT SIGNALS

ADC input

ADC sample

OP[9:0]

23.5 MCLK periods

* This example shows function when Red channel selected.

Figure 11 Default Timing in Fast CDS Monochrome Mode (Mode 3)

MCLK

INPUT

SIGNALS

INTERNAL

SIGNALS

OUTPUT

VSMP

Input video

ADC input

ADC sample

OP[9:0]

16.5 MCLK periods

SIGNALS

* This example shows function when Red channel selected.

Figure 12 Default Timing in Max. Speed non-CDS Monochrome Mode (Mode 4)

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WM8143-10 Production Data

INPUT

SIGNALS

INTERNAL

SIGNALS

OUTPUT

SIGNALS

MCLK

VSMP

Input

video

ADC input

ADC sample

OP[9:0]

r1,g1,b1

b0g1r1

16.5 MCLK periods

'X' indicates an invalid output

r2,g2,b2

r2 X

r3,g3,b3

r1 g1 b1 X

Figure 13 Default Timing in Slow CDS Colour Mode (Mode 5)

MCLK

INPUT

SIGNALS

VSMP

r4,g4,b4

r5,g5,b5

Input

INTERNAL

SIGNALS

ADC sample

OUTPUT

SIGNALS

video

ADC input

OP[9:0]

r1,g1,b1

b0Xr1

16.5 MCLK periods

This example shows function when Red channel selected. 'X' indicated invalid output.

r2,g2,b2

r2 XX

r3,g3,b3

X X

Figure 14 Default timing in Slow Monochrome Mode (Mode 6)

Wolfson Microelectronics PD Rev 3f June 98

r4,g4,b4

r5,g5,b5

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Production Data WM8143-10

Applications Recommendations

Output Data Interface

By default, data is output from the device as a ten-bit wide word on OP[9:0]. Optionally, data can be output in an eight-bit word format. Figure 15 shows this function. Data is presented on pins OP[9:2] at twice pixel rate.

In mode 3, the output is spread over three MCLK periods. The first two periods contain byte A data and the third period has byte B data. Either of the two byte A data periods are valid.

MCLK

OP[9:2]

Figure 15 Eight-bit Multiplexed Bus Output

•

A =d9,d8,d7,d6,d5,d4,d3,d2 - First byte

•

B =d1,d0,X,X,PNS,CC1,CC0,ORNG - Second byte

•

PNS : This bit shows if the device is configured in

parallel or serial mode. 1 = Parallel, 0 = Serial.

•

CC1/CC0 : These bits show which channel the

current output was taken from. 00 = RED, 01 = GREEN, 10 = BLUE.

•

ORNG : This bit indicates if the current output pixel

has exceeded the maximum or minimum range during processing. 1 = out of range, 0 = within range

•

X: This is an invalid output.

Control Interface Selection

WM8143-10 can be controlled via a serial or parallel interface. The decision on which interface is to be used is made on the sense of the SEN/STB pin on the rising edge of the NRESET signal.

SEN/STB CONDITION MODE

0 1

NRESET rising edge Serial Interface NRESET rising edge Parallel Interface

It is expected that this would be achieved on system power-up by attaching a simple RC network to the NRESET pin. The RC network should delay the set-up on the NRESET pin until the other conditions have been established. This feature is only activated on a hardware reset (using the NRESET pin). The software reset does not sample SEN/STB.

Controlling the WM8143-10

The WM8143-10 can be configured through a serial interface or a parallel interface. Selection of the interface type is by the SEN/STB pin which must be tied high (parallel) or low (serial) as shown in Table 4.

Serial Interface

The serial interface consists of three pins (refer to Figure 16). A six-bit address is clocked in MSB first followed by an eight-bit data word, also MSB first. Each bit is latched on the rising edge of SCK. Once the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register.

Parallel Interface

The parallel interface uses bits [9:2] of the OP bus as well as the STB, DNA and RNW pins (refer to Figure

17). Pin RNW must be low during a write operation. The DNA pin defines whether the data byte is address (low) or data (high). The data bus OP[9:2] is latched in during the low period of STB.

Internal Register Definition

Table 5 summarises the internal register content. The first 5 addresses in the table are used to program setup registers and to provide a software reset feature (00H is reserved). The remaining 3 entries in the table define the address location of internal data registers. In each case, a further three sub-addresses are defined for the red, green and blue register. Selection between the red, green and blue registers is performed by address bits a1 and a0, as defined in the table. Setting both a1 and a0 equal to 1 forces all three registers to be updated to the same data value. Blank entries in Table 5 should be programmed to zero.

Table 4 WM8143-10 Interface Set-up

SCK

SDI

SEN

a4a5 a3 a2 a1 a0 b7

Address

Data Word

Figure 16 Serial Interface Timing

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WM8143-10 Production Data

STB

OP[9:2]

DNA

RNW

Address

DES-

<a5:a0>

000000 Reserved 000001 Setup

000010 Setup

000011 Setup

000100 Software

000101 Setup

1000a1a0 DAC Values 1001a1a0 DAC Signs 1010a1a0 PGA Gains

CRIPTION

Reset

Figure 17 Parallel Interface Timing

Data

DE-

BITADDRESS

FAULT

(HEX)

03 VSMP6M MONO CDS ENADC

00 INVOP MUXOP

11 CHAN[1] CHAN[0] CDSREF[1] CDSREF[0] RLC[1] RLC[0]

00 DACRNG

00 DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 00 DSIGN 00 PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

b7 b6 b5 b4 b3 b2 b1 b0

Table 5 Register Map Contents

ADDRESS LSB

a1 a0

DECODE

Red Register Green Register Blue Register Red, Green and

Blue

0 0 0 1 1 0 1 1

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Production Data WM8143-10

Setup Register 1 Address ,<a5:a0>

000001

Address ,<a5:a0> 000010

Setup Register 3 Address ,<a5:a0> 000011

Setup Register 4 Address ,<a5:a0> 000101

0 ENADC 1 1 CDS 1

2 MONO 0

6 VSMP6M 0

0 MUXOP 0 2 INVOP 0

1-0 RLC1-0 01

5-4 CDSREF1-0 01

7-6 CHAN1-0 00

1 DACRNG 0

ADC Standby Control: 0 = Standby, 1 = Active Correlated Double Sampling Mode:

0 = Single Ended Mode, 1 = CDS Mode Mono/Colour Select: 0 = Colour, 1 = Monochrome Operation Required when operating in Mode 4: 0 = Other Modes, 1 = Mode 4 Eight Bit Output Mode: 0 = 10-bit, 1 = 8-bit MultiplexedSetup Register 2 Inverts ADC Output: 0 = Non-inverting, 1 = Inverting

Reset Level Clamp Voltage: 00 = 1.5V 01 = 2.5V 10 = 3.5V 11 = Reserved CDS Mode Reset Timing Adjust: 00 = Advance 1 MCLK Period 01 = Normal 10 = Retard 1 MCLK Period 11 = Retard 2 MCLK Periods Monochrome Mode Channel Select: 00 = Red channel 01 = Green channel 10 = Blue channel 11 = Reserved Offset DAC Output Range: 0 = DAC Output Range = Vmid/2 = +/-1.25V 1 = DAC Output Range = 1.5 ∗(Vmid/2) = +/-1.875V

Table 6 Control Bit Descriptions

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WM8143-10 Production Data

Detailed Timing Diagrams

MCLK

tRH

tRSU

tDSU

tRH

tRSU

tRH

tDH

tVH

tVSU

tVSU tVH

tVH

tVSU

tVH

tVSU

tVH

tDSU

tDH

VSMP, RLC

R,G,B Video Inputs

(Default Mode)

tVSU

tVH

(CDSREF[1]=0,CDSREF[0]=0)

(CDSREF[1]=0,CDSREF[0]=1)

(CDSREF[1]=1,CDSREF[0]=0)

(CDSREF[1]=1,CDSREF[0]=1)

R,G,B Video Inputs

tVSU

tVH

Figure 18 Detailed Video Input Timing - Modes 1 and 2

tRSU

tRH

tRSU

MCLK

tDSU

VSMP, RLC

R,G,B Video Inputs

(CDSREF[1]=0,CDSREF[0]=0)

Figure 19 Detailed Video Input Timing - Mode 3

MCLK

VSMP, RLC

R,G,B Video Inputs

VIDEORESET

tDH

tVSU

tVH

DSU

VSU

tDSU

tRSU

tDH

tVSU

tVH

tRH

VSU

Figure 20 Detailed Video Input Timing - Mode 4

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Production Data WM8143-10

MCLK

tDSU

tDH

VSMP, RLC

R,G,B Video Inputs

(CDSREF[1]=0,CDSREF[0]=0)

R,G,B Video Inputs

(CDSREF[1]=0,CDSREF[0]=0)

R,G,B Video Inputs

(CDSREF[1]=0,CDSREF[0]=0)

R,G,B Video Inputs

(CDSREF[1]=0,CDSREF[0]=0)

Figure 21 Detailed Video Timing - Modes 5 and 6

tPER

MCLK

tDSU

tDH

VSMP, RLC

OP[9:0]

RED GREEN BLUE

tVSU

tDSU

tVH

tRSU

tVH

tRH

tRSU

CKH t

tRH

tRSU

CKL

tRH

tRSU

tRH

tVSU

tDH

tVH

Figure 22 Detailed Digital Timing - Modes 1 and 2

tPER

CKHtCKL

MCLK

tDSU tDH

VSMP, RLC

tPD

OP[9:0]

Figure 23 Detailed Digital Timing – Mode 3

Wolfson Microelectronics PD.Rev 3f June 98

tDSU tDH

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WM8143-10 Production Data

tPER

MCLK

CKHtCKL

tPD

VSMP, RLC

tDS

OP[9:0]

Figure 24 Detailed Digital Timing – Mode 4

tPER

MCLK

tDSU

tDH

VSMP, RLC

OP[9:0]

RED

'X' Indicates Invalid

Figure 25 Detailed Digital Timing – Modes 5 and 6

tSPER

tSCKH

SCK

tSCKL

tDS

GREEN

CKH

CKL

BLUE

tSSU

tSH

SDI

SEN

Figure 26 Detailed Timing Diagram for Serial Interface

tSTB

STB

OP[9:2]

Data Out

tASU

Address In

tADLS

DNA

RNW

tOPZ

Figure 27 Detailed Timing Diagram for Parallel Interface

Wolfson Microelectronics PD Rev 3f June 98

tSCE

tSEW

tSEC

tSTB

tDSUtAH

Data In

tADHStADLH

tDH

tADHH

Data Out

tOPD

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Production Data WM8143-10

Applications Diagram

VRLC

BINP

GINP

RINP

OEB

DVDD

SCK/RNW

RLC VSMP MCLK

DGND

DVDD

10µF

SEN/STB

SDI/DNA

25 26 27

WM8143-10

28 29 30

VMID

VRT

VRB

VRU

AGND

AVDD

NRESET

11 10

OP[9]

OP[8]

100nF

10µF

100nF

22µF

100nF

10µF

100nF

10µF

AVDD

10µF

100nF

10µF

DGND

100nF

OP[4]

OP[3]

OP[2]

OP[1]

OP[0]

Note: AGND and DGND should be starpointed as close as possible to the AGND pins

OP[5]

OP[6]

OP[7]

AGND

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WM8143-10 Production Data

Package Dimensions

1.45

1.35

0.80 BSC

1 8

7.00 BSC

9.00 BSC

0.45

0.20

0.30

0.15

0.05

Seating Plane

0.25

0.75

0.45

0.20

0.09

Gauge Plane

0o - 7

1.60MAX

Notes: A. All linear dimensions are in milimeters B The drawing is subject to change without notice C Falls within JEDEC MS-026. Refer to this specification for further details.

Last page of WM8143-10 Datasheet

Wolfson Microelectronics PD Rev 3f June 98

0.10

DM002.a 32-pin TQFP