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WM8725
99dB Stereo DAC
Production Data, July 2000, Rev 2. 0
DESCRIPTION
WM8725 is a high-performance stereo DAC designed for
use in portable audio equipment, video CD players and
similar applicat ions. It comprises selectabl e normal or I
compatible serial data interfaces for 16 to 24-bit digital
inputs, high performance digital filters, and sigma-delta
output DACs, achieving an excellent 99dB signal-to-noise
performance.
The device is available in a 14-pin SO package that offers
selectable mute and de-emphasis functions using a
minimum of external components.
2
BLOCK DIAGRAM
FEATURES
• Compatible with PCM 1725
• 99dB SNR performance
S
• Stereo DAC with input sampling from 8kHz to 96kHz
• Additional mute feature
• Normal or I
• Sigma-delta design with 64x oversamplin g
• System clock 256fs or 384fs
• Supply range 3V to 5V
• 14-pin SOIC package
2
S compatible data format
APPLICATIONS
• Portable audio equipment
• Video CD players
WM8725
FORMAT (13)
SCKI (14)
LRCIN (1)
DIN (2)
BCKIN (3)
SERIAL
INTERFACE
DIGITAL
FILTERS
(12)
DEEMPH
(10)
MUTE
DIGITAL
SIGMA-DELTA
MODULATOR
DIGITAL
SIGMA-DELTA
MODULATOR
(8)
VDD
SWITCHED
CAPACITOR
DAC
SWITCHED
CAPACITOR
DAC
(5)
CAP
(7)
GND
(6) VOUTR
(9) VOUTL
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
Production Data datasheets contain final
specifications current on publication date.
Supply of products conforms to Wol fson
Microelectronics’ Terms and Condit i ons.
2000 Wolfson Microelectronics Ltd.
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WM8725 Production Data
ORDERING INFORMATIONPIN CONFIGURATION
DEVICE TEMP. RANGE PACKAGE
LRCIN
DIN
BCKIN
NC
CAP
VOUTR
GND
1
2
3
WM8725
4
5
6
7
14
13
12
11
10
9
8
SCKI
FORMAT
DEEMPH
NC
MUTE
VOUTL
VDD
WM8725ED -25 to +85oC 14-pin SOIC
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stres s ratings only. Perm anent dam age to t he device m ay be caused by c ontinuousl y operating
at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under
Electrical Characteri stics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during
handling and storage of this devic e.
CONDITION MIN MAX
Supply voltage
Reference input
Operating temperature range, T
Storage temperature
Lead temperature (soldering, 10 s econds)
Lead temperature (soldering, 2 minutes)
A
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST
Supply Range
Ground
Supply Current
VDD -10% 3.0 to 5.0 +10% V
GND 0 V
CONDITIONS
VDD = 5V 15 25 mA
VDD = 3V 7.5 mA
-0.3V +7.0V
VCC+0.3V
+260
+183
o
C
o
C
o
C
-25oC+85
o
-65
C +150oC
MIN TYP MAX UNIT
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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Production Data WM8725
ELECTRICAL CHARACTERISTICS
Test Conditions
V
= 5V, GND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.
DD
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Logic Levels
Input LOW level
Input HIGH level
Analogue Output Levels
Minimum resist ance load
Maximum capacitance load
Output DC level
Reference Levels
Potential divider resis tance
Voltage at CAP
DAC Circuit Specifications
SNR (Note 1)
Full scale output voltage
THD (Full scale)
THD+N (Dynamic range)
Frequency response
Transition band
Out of band rejection
Channel Separation
Gain mismatch
channel-to-channel
Audio Data Input and System Clock Timing Information
BCKIN pulse cycle time
BCKIN pulse width high
BCKIN pulse width low
BCKIN rising edge to LRCIN edge
LRCIN rising edge to BCKIN
rising edge
DIN setup time
DIN hold time
System clock pul se width high
System clock pul se width low
Notes:
1. Rat i o of output level with 1kHz full scale input, to the output level with al l zeros into the digital input, measured
“A” weighted over a 20Hz to 20kHz bandwidth.
2. All performance measurement s done with 20kHz low pass filter. Failure to use such a filter will result in higher
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteri stics. The low pass
filter removes out of band noi se; although it is not audible, it may affect dynamic specific ation values.
V
V
t
BCY
t
BCH
t
BCL
t
t
t
t
t
SCKIH
t
SCKIL
IL
IH
To midrail or AC coupled
2.0 V
1 kohms
0.8 V
(5V supply)
To midrail or AC coupled
1 kohms
(3V supply)
5V or 3V 100 pF
V
/2 V
DD
V
to CAP and CAP to GND
DD
80 100 120 kohms
VDD = 5V 2.3 2.5 2.7 V
VDD = 5V 90 99 dB
VDD = 3V 97 dB
Into 10kohm VDD = 5V, 0dB 0.9 1.0 1.1 V
Into 10kohm VDD = 3V, 0dB 0.6 V
RMS
RMS
0dB 0.01 0.02 %
-60dB 92 dB
0 20,000 Hz
20,000 Hz
-40 dB
90 dB
±1 ±5 %FSR
100 ns
50 ns
50 ns
BL
LB
DS
DH
30 ns
30 ns
30 ns
30 ns
13 ns
13 ns
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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WM8725 Production Data PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LRCIN Digital input Sample rate clock input
DIN Digital input Serial data input
BCKIN Digital input Bit clock input
NC No connect No internal connection
CAP Analogue output Analogue internal reference
VOUTR Analogue output Right channel DAC output
GND Supply 0V supply
VDD Supply Positi ve s uppl y
VOUTL Analogue output Left channel DAC output
MUTE Digital input Mute control, high = muted. Internal pull-down
NC No connect No internal connection
DEEMPH Digital input De-emphasis select, high = de-emphasis ON. Internal pull-up
FORMAT Digital input Data input format select, low = normal, high = I
SCKI Digital input System clock input (256fs or 384fs)
2
S. Internal pull-up
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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Production Data WM8725
DEVICE DESCRIPTION
INTRODUCTION
WM8725 is a complete stereo audio 16-bit digital-to-analogue converter, including digital
interpolation filter, multibit sigma-delta with dither, and switched capacitor multibit stereo
DAC and output smoothing f i l ters.
Special functions of mute and de-emphasis are provided, and operation using s ystem cloc k
of 256fs or 384fs is provided, selection between either clock rate being automatically
controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the
appropriate system cl ock is input.
MUTE DESCRIPTION
0
1
Table 1 Mute Control
A novel multi bit sigma-delta DAC design is used, utilising a 64x oversampling rate, to
optimise signal t o noi se performance and offer increased clock jitter tol erance.
Internally generated midrail references are used to DC bias output signals, requiring only a
single external capacitor for decoupl i ng purposes.
The device is packaged in a small 14-pin SOIC pac kage, offering pin c ompatibility with B urr
Brown PCM1725, but with added functionality of a mute input pin, which may be left floating i f
unused, or held ‘low’ leaving the device operational.
Mute is OFF
Mute is ON
DAC CIRCUITS
Single 3V to 5V supplies m ay be used, the output amplitude scaling with abs olute supply
level. Low supply voltage operation and low current consumption, and t he low pin count small
package, make the WM8725 attractive for many consumer type applic at i ons.
The WM8725 DACs are designed t o allow playback of 16-bit PCM audio or si milar data with
high resolution and low noise and distort ion. Sample rates up to 96ks/ s may be used, with
much lower sample rates acceptable provided that the ratio of sample rate (LRCIN) to
system clock is maintained at the requi red 256fs or 384fs times.
The DACs on WM8725 are implemented using sigma-delta oversampled conversion
techniques. These require that the PCM samples are digitally filtered and interpolated to
generate a set of samples at a much higher rate than the 96ks/ s input rate. This sam ple
stream is then digitally modulated to generate a digit al pulse s tream t hat is t hen converted t o
analogue signals in a switched capacitor DAC. The advantage of this t echnique is that the
DAC is linearised using nois e shaping techniques, allowing the 16 bit resolution to be met
using non-critical analogue components. A further advantage is that the high sam ple rate at
the DAC output means that smoothing f ilters on the output of the DAC need only have fairly
crude characteristic s in order to rem ove the characteri stic s teps, or im ages, on t he output of
the DAC. To ensure that generation of tones charac teris tic t o sigm a-delta convert ors is not a
problem, dithering is used in the digital modulator and a higher order m odulator is us ed. The
switched capacitor technique used in the DAC reduces s ensitivity to c lock jitt er compared to
switched current techniques used in other implementations.
De-emphasis of 44.1kHz signals may be applied if requi red.
DEEMPH DESCRIPTION
0
1
Table 2 De-emphasis Control
De-emphasis is OFF
De-emphasis is ON
The voltage on the CAP pin is used as the reference for the DACs, t herefore the amplitude of the
signals at the DAC outputs will scale with the amplitude of the voltage at the CAP. An external
reference could be used to drive into t he CAP pin if desired, but a val ue typically of about m idrail
should be used for optimum performance.
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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WM8725 Production Data
The outputs of the 2 DACs are buff ered out of the devic e by buffer am plifiers. Thes e amplifiers will
source load current of several m A and sink current up t o 1.5mA, so allowing si gnificant loads to be
driven. The output source is ac tive and t he si nk is Clas s A , i .e. fixed value, s o greater loads m ight be
driven if an external ‘pull-down’ resistor is connected at the output.
Typically an external low pass filter circuit will be used to remove residual sampling nois e of the 64x
oversampling used and if des i red adj ust the signal amplit ude and devi ce strength.
SERIAL DATA INTERFACE
WM8725 has serial interface form ats that are fully compatibl e with both normal (MSB first,
right-justified) and I
FORMAT is LOW, norm al data format is selec ted. When the form at is HIGH, I
selected. It m ust be noted that in “packed” mode operation (exactly 32 BCLKs per LRCIN
period), the data word must align exactly with LRCIN clock edges (effectively both left and
right justified at the same time). This i s true in both normal and I
FORMAT DESCRIPTION
0
1
Table 3 Serial Interface Formats
2
S interfaces. The data form at is selected with the FORMAT pin. When
2
S modes.
2
S format is
Normal format
(MSB-first, right justified)
2
S format
I
(Philips serial data protocol)
1/fs
LEFT CHANNEL RIGHT CHANNEL
LRCIN
BCKIN
Audio Data Word = 16-Bit
DIN
123 1415
MSB MSB LSB
Figure 1 ‘Normal’ Data Input Timing
LEFT CHANNEL RIGHT CHANNEL
LRCIN
BCKIN
Audio Data Word = 16-Bit
DIN
123 141516 123141516
MSB
Figure 2 I2S Data Input Timing
16
LSB
1/fs
123 1415
MSB LSBLSB
16
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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Production Data WM8725
SYSTEM CLOCK
The system clock is used to operate the digital filters and the noise s haping circuits. The
system clock input is at pin 14 (SCK I). The frequency of W M8725’s syst em clock should be
set to 256fs or 384fs, (where fs is the audio sampling frequency). The sample rate is
typically: 32 kHz, 44.1 kHz, 48 kHz or 96kHz.
WM8725 has a system clock detection circuit that automatically determines whether the
system clock being supplied is at 256f s or 384fs. The system clock s hould be synchroni sed
with LRCIN, but WM8725 is tolerant of phase differences. Severe distortion in the phase
difference between LRCIN and the system clock will be detected, and cause the device to
automatically resynchronise. During resynchronisation, the output of the device will either
repeat the previous sample, or drop the next sample, depending on the nature of the phas e
slip. This will ensure minimal “click“ at the analogue outputs during resynchronisation.
t
SCKIL
SCKI
Figure 3 System Clock Timing Requirements
t
SCKIH
SAMPLING
RATE (LRCIN)
SYSTEM CLOCK FREQUENCY
(MHz)
256fs 384fs
32 kHz 8.192 12.288
44.1 kHz 11.2896 16.9340
48 kHz 12.288 18. 432
96kHz 24.576 36.864
Table 4 System Clock Frequencies Versus Sampling Rate
LRCIN
t
BCL
t
BL
t
DS
t
DH
BCKIN
DIN
t
BCH
t
BCY
Figure 4 Audio Data Input Timing
t
LB
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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WM8725 Production Data RECOMMENDED EXTERNAL COMPONENTS
FROM AUDIO
PROCESSOR
ANALOGUE
OUTPUT
FOR RIGHT
CHANNEL
External
LPF
10µF
1
LRCIN
2
DIN
3
BCKIN
4
NC
+
5
CAP
6
VOUTR
7
GND
WM8725
FORMAT
DEEMPH
VOUTL
SCKI
NC
MUTE
VDD
14
13
12
11
10
9
8
External
LPF
256fs/384fs CLK
ANALOGUE
OUTPUT FOR
LEFT
CHANNEL
GND
10µF
0.1µF
VDD
Figure 5 Recommended External Components
DETAIL OF RECOMMENDED EXTERNAL COMPONENTS SHOWING THE EXTERNAL LOW PASS FILTER
External LPF
x2 for Stereo Operation
VOUTR
VOUTL
10k
1500pF
10k
680pF
Ω
10k
Ω
-
+
Ω
100pF
Filtered
Analogue
Output
Figure 6 Third-Order Low Pass Filter (LPF) Example
An external low pass filter is recommended (see Figure 6) if the device is driving a wideband
amplifier. In s ome applications, s econd-order or passive RC filter m ay be adequate.
PCB LAYOUT
1. Place all supply decoupling capacitors as close as possible to their respective supply
pins and provide a low impedance path from the capacitors to the appropri ate ground.
2. Separate analogue and digital ground planes shoul d be situated under respective
analogue and digital device pins.
3. Avoid noise on the CAP reference pin. The decoupling capacitor should be placed as
close to this pin as possible with a low impedance path from the capacitor to analogue
ground.
4. Digital input signals s houl d be screened from each other and from other sources of
noise to avoid cross-talk and interference. They should als o run over the digital ground
plane to avoid introducing unwanted noise into the analogue ground plane.
5. Analogue output signal tracks should be k ept as short as possible and over the
analogue ground plane reducing the possibility of losing si gnal qualit y.
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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Production Data WM8725
PACKAGE DIMENSIONS
D: 14 PIN SOIC 3.9mm Wide Body
e
14
D
B
DM001.C
8
H
E
71
L
o
h x 45
A1
-C-
SEATING PLANE
α
A
Symbols
0.10 (0.004)
Dimensions
(MM)
Dimensions
(Inches)
MIN MAX MIN MAX
A
A1
B
C
D
E
e
H
h
L
α
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
1.35 1.75 0.0532 0.0688
0.10 0.25 0.0040 0.0098
0.33 0.51 0.0130 0.0200
0.19 0.25 0.0075 0.0098
8.55 8.75 0.3367 0.3444
3.80 4.00 0.1497 0.1574
1.27 BSC 0.05 BSC
5.80 6.20 0.2284 0.2440
0.25 0.50 0.0099 0.0196
0.40 1.27 0.0160 0.0500
o
0
o
8
o
0
8
JEDEC.95, MS-012
o
C
WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000
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