Datasheet WM9704Q Datasheet (Wolfson)

Page 1

WM9704Q

4-Channel Surround Sound Codec

Production Data, January 2001, Rev 2.3

DESCRIPTION

WM9704Q is a high quality audi o codec com pliant with the AC’97 Revision 2.1 specification. It performs full duplex 18-bit codec functions from 8 to 48k samples/s and offers excellent quality with high SNR. Features i nclude 3D sound and line-level outputs. Support is also provided for variabl e sample rates and mas t er/s lave m ode operation. Addit ionall y the WM9704Q provides two proprietary modes:

4-channel quad mode enables two channels of ADC and DAC plus an additional two DAC channels as rear outputs.

6-channel mode configures the device to provide external support for two additional stereo outputs via the GPIO pins.

WM9704Q is interchangeable with AC’97 Codecs from Wolfson and other suppliers in the basic Revision 2.1 mode. WM9704Q is fully operable with 3.3V or 5.0V or mixed

3.3/5.0V supplies and is packaged in an indus try standard 48-pin TQFP package.

BLOCK DIAGRAM

VOL/

MUTE

VOL/

MUTE

CD (18,20)

LINEIN (23,24)

VIDEO (16,17)

AUX (14,15) PHONE (13)

PCBEEP (12)

MIC[1] (21) MIC[2] (22)

MUX

0dB/ 20dB

KEY:

MONO STEREO

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

RECORD

MUTE

MUX AND

VOL/

MUTE

VOL/

MUTE

VOL

FEATURES

• 4 DAC channels, stereo ADC

• Balanced mixer architect ure

• S/N ratio > 95dB

• Variable rate audio and modem support

• Analogue 3D stereo enhancement

• Line level outputs

• Master/slave ID selection

• Low power implementation

• 3.3V or 5V operation

• 48-pin TQFP package

APPLICATIONS

• 4-channel surround sound solution implemented with 2 additional internal DACs

• 6-channel surround sound supported via connection of a stereo DAC (WM8725) to GP IO pins

• Supports 4-channel playback of anal ogue sources such as CD

(35,36) LINEOUT (FRONT)

(39,41) LINEOUT (REAR)

(37) MONOOUT

(40) MODE1 (30) MODE0 (47) EAPD

(6) BITCLK (10) SYNC (8) SDATAIN (5) SDATAOUT (11) RESETB

(45) CID0 (46) CID1

(43,44,48) GPIO[1:3]

(2) XTLIN (3) XTLOUT

REV. 2.1 SWITCH

MUX

REAR

STEREO

DAC

FRONT

STEREO

DAC

WM9704Q

STEREO

ADC

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

SRC

SERIAL SERIAL

I/F I/F

MASTER/

SLAVE

SELECT

GENERAL IO

SUPPORT

OSC

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk

Production Data datasheets contain final

specifications current on publication date.

Supply of products conforms to Wol fson Microelectronics’ Terms and Condit i ons.

2001 Wolfson Microelectronics Ltd.

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WM9704Q Production Data

PIN CONFIGURATION ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM9704CFT/V 0 to 70oC 48-pin TQFP

GPIO3

EAPD

CID1

CID0

GPIO1

GPIO2

LNLVLOUTR

AVSS2

MONOOUT

AVDD2

LNLVLOUTL

MODE1

CDR

3747 46 45 44 43 42 41 40 39 3848

LINEOUTR

LINEOUTL

CX3D2

CX3D1

CAP2

CAP1

MODE0

AFILT1

VREFOUT

VREF

AVSS1

2316 17

MIC2

MIC1

LINEINL

AVDD1

LINEINR

DVDD1

XTLIN

XTLOUT

DVSS1

SDATAOUT

BITCLK

DVSS2

SDATAIN

DVDD2

SYNC RESETB PCBEEP

1 2 3 4 5 6 7 8

9 10 11 12

13 14 15

18 19 20 21 22

AUXL

PHONE

CDL

AUXR

VIDEOL

CDGND

VIDEOR

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c onti nuously operat ing at or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical Characteristics at the test conditions s pecified

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage of this device.

As per specifications IPC/JEDEC J-STD-020A and JEDEC A113-B, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags.

CONDITION MIN MAX

Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, T

Storage temperature Package body temperature (s ol deri ng 10 seconds) Package body temperature (s ol deri ng 2 minutes)

-0.3V +7V

-0.3V +7V DVSS -0.3V DVDD +0.3V AVSS -0.3V AVDD +0.3V

+240 +183

0oC+70

-65

C +150oC

Note:

1. The digital supply voltage (DVDD) must always be less than or equal to the analogue supply voltage (AVDD).

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

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Production Data WM9704Q

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital supply range Analogue supply range Digital ground Analogue ground Difference DVSS to AVSS Analogue supply current Digital supply current Standby supply current (all P Rs set) Analogue supply current Digital supply current Standby supply current (all P Rs set)

DVDD1, DVDD2 -10% 3.3 to 5.0 +10% V AVDD1, AVDD2 -10% 3.3 to 5.0 +10% V

DVSS1, DVSS2 0 V AVSS1, AVSS2 0 V

-0.3 0 +0.3 V DVDD, AVDD = 5V 35 mA DVDD, AVDD = 5V 25 mA DVDD, AVDD = 5V 10 µA

DVDD, AVDD = 3.3V 22 mA DVDD, AVDD = 3.3V 15 mA DVDD, AVDD = 3.3V 6 µA

ELECTRICAL CHARACTERISTICS

Test Characteristics:

AVDD = 5V, GND = 0V …………..T DVDD = 3.3V, GND = 0V …………..T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital Logic Levels (DVDD = 3.3 or 5.0V)

Input LOW level V Input HIGH level V Output LOW V Output HIGH V

Analogue I/O Levels (Input Signals on any inputs, Outputs on LINEOUT L, R and MONO)

Input level

Output level

Reference Levels

Reference input/output CAP2 CAP2 impedance Mixer reference VREF

MIC reference VREFOUT

ADC reference CAP1

DAC reference AFILT1

MIDBUFF current sink (pins CAP1, AFILT2, VREF and VREFOUT)

MIDBUFF current source (pins CAP1, AFILT1, VREF and VREFOUT)

= 0oC to +70oC, unless otherwise stated

IL IH OL OH

Minimum input

impedance = 10k Into 10kohm load AVSS

AVDD = 5V -5 -15 mA

AVDD = 5V 5 15 mA

AVDD = 3.3V 5 mA

AVSS -0.3 0.8 V

2.2 AVDD +0.3 V

0.1 x DVSS V

0.9 x DVDD V

AVSS

-100mV

+100mV

Near rail to

rail

AVDD +100mV

AVDD

-100mV

2/5 AVDD AVDD/2 3/5 AVDD V

75 kohms

Buffered

CAP2

Buffered

CAP2

Buffered

CAP2

Buffered

CAP2

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

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WM9704Q Production Data

Test Characteristics:

AVDD = 5V, GND = 0V …………..T DVDD = 3.3V, GND = 0V …………..T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

DAC Circuit Specifications (AVDD = 5V) 48kHz sampling

SNR A-weighted (Note 1) Full scale output voltage THD Frequency response Transition band Stop band Out of band rejection Spurious tone reduction PSRR

ADC Circuit Specifications (AVDD = 5V) 48kHz sampling

SNR A-weighted (Note 1) ADC input for full scal e out put THD Frequency response Transition band Stop band Stop band rejection PSRR

Mixer Circuit Specificati ons (AVDD = 5V) 48kHz sampling

SNR CD path A-weighted (Note 1) SNR Other paths A-weighted

(Note 1) Maximum input voltage Maximum output voltage on

LINEOUT THD Frequency response (+/-1dB) Input impedance (CD inputs ) Input impedance (other mixer

inputs) Input impedance MIC inputs

PSRR

DAC Circuit Specifications (AVDD = 3.3V) 48kHz sampling

SNR A-weighted (Note 1) Full scale output voltage THD Frequency response Transition band Stop band Out of band rejection Spurious tone reduction PSRR

= 0oC to +70oC, unless otherwise stated

= 2.5V 1.0 Vrms

REF

-3dBFS input 74 90 dB

20 to 20kHz 40 dB

= 2.5V 1.0 Vrms

REF

-6dBV input 74 90 dB

20 to 20kHz 40 dB

0dBV input 74 90 dB

At any gain 10 15 k ohm

At max gain 10 20 kohm

At 0db gain 100 kohm

At max gain 80 kohm

At 0db gain 10 15 kohm

20 to 20kHz 40 dB

= 1.65V 0.7 Vrms

REF

-3dBFS input 90 dB

20 to 20kHz 40 dB

85 96 dB

20 19,200 Hz 19,200 28,800 Hz 28,800 Hz

-40 dB

-100 dB

75 85 dB

20 19,200 Hz 19,200 28,800 Hz 28,800 Hz

-74 dB

90 100 dB

85 95 dB

AVSS 1.0 AVDD Vrms

1.0 1.8 Vrms

20 20,000 Hz

96 dB

20 19,200 Hz 19,200 28,800 Hz 28,800 Hz

-40 dB

-100 dB

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

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Production Data WM9704Q

Test Characteristics: AVDD = 5V, GND = 0V …………..T DVDD = 3.3V, GND = 0V …………..T

= 0oC to +70oC, unless otherwise stated

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

ADC Circuit Specifications (AVDD = 3.3V) 48kHz sampling

SNR A-weighted (Note 1) ADC input for full scal e out put THD Frequency response Transition band Stop band Stop band rejection PSRR

= 1.65V 0.7 Vrms

REF

-9dBV input 80 dB 20 19,200 Hz

19,200 28,800 Hz 28,800 Hz

-74 dB

20 to 20kHz 40 dB

82 dB

Mixer Circuit Specificati ons (AVDD = 3.3V) 48kHz sampling

SNR CD path A-weighted

97 dB

(Note 1) SNR Other paths A-weighted

92 dB

(Note 1) Maximum input voltage Maximum output voltage on

0.7 Vrms

LINEOUT THD Frequency response (+/-1dB) Input impedance (CD inputs ) Input impedance (other Mixer

inputs) Input impedance MIC inputs

-3dBV input 90 dB 20 20,000 Hz

At any gain 15 kohm

At max gain 20 kohm

At 0db gain 100 kohm

At max gain 80 kohm

At 0db gain 15 kohm

PSRR

20 to 20kHz 40 dB

Clock Frequency Range

Crystal clock BIT_CLK frequency SYNC frequency

24.576 MHz

12.288 MHz

48.0 kHz

Note:

1. SNR is the ratio of 0dB signal output level to the output l evel with no signal, measured A-weighted over a 20Hz to 20k Hz bandwidth.

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

Page 6

WM9704Q Production Data PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 2 3 4 5 6

7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Note:

1. Pins 27, 29 and 31 have an internal connection.

DVDD1 Supply Digital positive supply

XTLIN Digital input Clock crystal connection or clock input (XTAL not used)

XTLOUT Digital output Clock crystal connection

DVSS1 Supply Digital ground supply

SDATAOUT Digital i nput Seri al data input

BITCLK Digi tal output (master)

Digital input (slave)

Serial interface cloc k output to AC’97 controller or input from AC’97 mas ter codec

DVSS2 Supply Digital ground supply

SDATAIN Digital output Serial data output to AC’97 controller

DVDD2 Supply Digital positive supply

SYNC Digit al i nput Seri al i nt erface sync pulse from A C’97 controller RESETB Digital input NOT reset input (active low, resets regis ters) PCBEEP Analogue input Mixer input, typically for PCBEEP signal

PHONE Analogue input Mixer input, typical l y f or P HONE signal

AUXL Analogue input Mixer input, typically for AUX signal

AUXR Analogue input Mixer input, typically for AUX signal

VIDEOL Analogue input Mixer input, typically for VIDEO s i gnal

VIDEOR Analogue input Mixer input, typically f or V IDEO signal

CDL Analogue input Mixer input, typically for CD signal

CDGND Analogue input CD input common mode reference (ground)

CDR Analogue input Mixer input, typically f or CD signal MIC1 Analogue input Mixer input with extra gain if required MIC2 Analogue input Mixer input with extra gain if required

LINEINL Anal ogue i nput Mixer input, typically for LINE signal LINEINR Analogue input Mixer input, typically for LINE signal

AVDD1 Supply Analogue positive suppl y AVSS1 Supply Analogue ground supply, chip substrat e

VREF(1) Analogue output Buffered CAP 2

VREFOUT Analogue output Reference for microphones; buffered CAP 2

AFILT1(1) Analogue output Buffered CAP2

MODE0 Digital input Mode select pin, internal pull down (6-channel support I

enable)

CAP1(1) Analogue output Buf f ered CAP2

CAP2 Analogue input Reference input/output; pulls to midrail if not driven

CX3D1 Analogue output Output pin f or 3D di fference signal CX3D2 Analogue input Input pin for 3D dif ference signal

LINEOUTL Analogue output Main analogue output for left c hannel LINEOUTR Analogue output Main analogue output for right channel MONOOUT Analogue output Main mono output

AVDD2 Supply Analogue positive suppl y

LNLVLOUTL Anal ogue output Left channel line level output

MODE1 Digital input Mode select pin, internal pull down (Quad mode select)

LNLVLOUTR Analogue output Right channel line level output

AVSS2 Supply Analogue ground supply, chip substrat e

GPIO1 Programmable I/O GPIO or I GPIO2 Programmable I/O GPIO or I

S CID0 Digital input Master/slave ID select (internal pull-up) CID1 Digital input Master/slave ID select (internal pull-up)

EAPD Digital output External amplifier power down/GPO

GPIO3 Programmable I/O GPIO or I

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

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Production Data WM9704Q

DETAILED TIMING DIAGRAMS

Test Characteristics:

AVDD = 5V, GND = 0V …………..T DVDD = 3.3V, GND = 0V …………..T All measurement s are taken at 10% to 90% VDD, unl ess otherwise stated.

AC-LINK LOW POWER MODE

= 0oC to +70oC, unless otherwise stated

COLD RESET

SYNC

SLOT 1 SLOT 2

BIT_CLK

SDATA_OUT

WRITE

TO 0X20

DATA PR4

S2_PDOWN

DON’T CARE

SDATA_IN

Figure 1 AC-Link Powerdown Timing

PARAMETER SYMBOL MIN TYP MAX UNIT

End of slot 2 to BITCLK S DA T IN low

RST_LOW

s2_PDOWN

RST2CLK

1.0 µs

RESETB

BIT_CLK

Figure 2 Cold Reset Timing

PARAMETER SYMBOL MIN TYP MAX UNIT

RESETB active low pulse width t RESETB inactive to BIT_CLK

RST_LOW

RST2_CLK

1.0 µs

162.8 ns

startup delay

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

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WM9704Q Production Data

WARM RESET

Figure 3 Warm Reset Timing

SYNC active high pulse width t SYNC inactive to BIT_CLK

startup delay

CLOCK SPECIFICATIONS

SYNC_HIGH

SYNC2CLK

SYNC

BIT_CLK

PARAMETER SYMBOL MIN TYP MAX UNIT

1.3 µs

BIT_CLK

CLK_HIGH

CLK_PERIOD

SYNC_HIGH

SYNC2_CLK

162.4 ns

CLK_LOW

SYNC_LOW

SYNC

SYNC_PERIOD

Figure 4 Clock Specifications (50pF External Load)

PARAMETER SYMBOL MIN TYP MAX UNIT

BIT_CLK frequency BIT_CLK period t BIT_CLK output jitter BIT_CLK high pulse width (Note 1) t BIT_CLK low pulse width (Note 1) t SYNC frequency SYNC period t SYNC high pulse width t SYNC low pulse width t

CLK_PERIOD

CLK_HIGH CLK_LOW

SYNC_PERIOD

SYNC_HIGH SYNC_LOW

32.56 40.7 48.84 ns

12.288 MHz

81.4 ns 750 ps

48.0 KHz

20.8 µs

1.3 µs

19.5 µs

Note: Worst case duty cycle restricted to 40/60

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

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Production Data WM9704Q

DATA SETUP AND HOLD (50pF EXTERNAL LOAD)

SETUP

BIT_CLK

HOLD

SYNC

SDATA_OUT

Figure 5 Data Setup and Hold (50pF External Load)

PARAMETER SYMBOL MIN TYP MAX UNIT

Setup to falling edge of BIT_CLK t Hold from falling edge of BI T_CLK t

SETUP

HOLD

15.0 ns

5.0 ns

Note: Setup and hold tim e parameters for SDATA_IN are with res pect to AC’97 Controller.

SIGNAL RISE AND FALL TIMES

BIT_CLK

rise

CLK

SYNC

fall

CLK

fall

SYNC

rise

DIN

fall

DIN

SDATA_IN

rise

DOUT

fall

DOUT

SDATA_OUT

Figure 6 Signal Rise and Fall Times (50pF external load)

PARAMETER SYMBOL MIN TYP MAX UNIT

BIT_CLK rise time trise BIT_CLK fall time tfall SYNC rise time trise SYNC fall time tfall SDATA_IN rise time trise SDATA_IN fall time trise SDATA_OUT rise time trise SDATA_OUT fall time tfall

CLK

SYNC

DIN DIN

DOUT

26ns 26ns 26ns 26ns 26ns 26ns 26ns 26ns

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

Page 10

WM9704Q Production Data SYSTEM INFORMATION

CD, VIDEO,

AUX,

LINEINL/R

MIC2

MIC1

PC_BEEP PHONE

22 21 12 13

AC’97

DIGITAL

CONTROLLER

RESET

BITCLK

SYNC

SDATAIN

SDATAOUT

CHIP

SELECT

{

CID0 CID1

45 46

MODE0 = 0 MODE1 = 1

WM9704Q

(QUAD MODE)

Figure 7 WM9704Q in Typical Quad Mode Application

48 43

GPIO [1:3]

S DATA LRCLK BITCLK

SCLK

LINEOUTL/R FRONT DATA

LNLVLOUTL/R REAR DATA

MONO_OUT

OPTIONAL FOR AC- 3 TYPE SURROUND SOUND (5.1)

WM8725 STEREO

DAC

SURROUND SOUND ( CENTRE & LFE DATA)

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

Page 11

Production Data WM9704Q

DEVICE DESCRIPTION

INTRODUCTION

The WM9704Q Codec compri ses two channels of ADC and four channels of DAC. This enables a four channel surround sound solution to be implemented (Quad mode). A symmetric mixer is provided which allows analogue signals such as CD inputs to be mixed into both front and rear channel paths simultaneously.

Alternatively, the device can be configured in 6-channel I GPIO pins to output rear channel and centre and LFE data in I (WM8725) to build a full 6 channel surround sound solution.

The WM9704Q can also be conf igured as a s tandard A C’97 Revis ion 2.1 com pliant device, i ncluding line level outputs and with support f or the variable rate audio sample rates (2 channel mode).

The WM9704Q compris es a stereo 18-bit Codec, (t hat is, 2 ADCs and 2 DACs ) plus two additional DACs. The WM9704Q also has a comprehensi ve analogue mixer with 4 sets of stereo inputs , plus phone, 2 microphone, and PC-beep inputs. On-chi p reference circuits generate the nec essary bias voltages for the device, and a bi-di rectional serial interfac e allows transfer of control data and DA C and ADC words to and from the AC’97 cont rol l er. The WM9704Q supports 18-bit resolution within the DAC and ADC functions, but the A C’97 seri al int erfac e spec if icat ion all ows any word length up to 20bits to be written to, or read from , the AC’97 Codec. These words are MSB jus tified, and any LSB s not used will simply default to 0. Normally it is anticipated that 16-bit words will be used in most PC type systems. Therefore, for the DAC, 16-bit words will be downloaded into the Codec from the controller, along with padding of 0s to make the 16-bit word up to 20-bit length. In this case, the WM9704Q will process the 16-bit word along with 0 padding bits in the 2 LSB locations (t o mak e 18bit). At the ADC output, WM9704Q will provide an 18-bit word, again with 0s in the two LSB locations (20-bit). The AC’97 controller will then ignore the 4 LSBs of the 20-bit word. When the W M9704Q is interrogated, it responds indi cating it is an 18-bit device.

S mode. In this mode the device uses three

S format to an external DAC

The WM9704Q has the ADC and DAC f unctions implemented using oversam pled, or sigma-delta converters, and uses on-chi p di gi t al filters to convert thes e 1-bi t signals to and from t he 48ks/s 16/18bit PCM words that the AC’97 controller requires. The digital parts of the device are powered separately from the analogue to optimise performance, and 3.3V digital and 5V analogue supplies may be used on the same devi ce to further optim ise performance. Digi tal IOs are 5V tol erant when the analogue supplies are 5V, so t he WM9704Q may be connected to a controller running on 5V supplies, but use 3.3V f or the digital section of WM9704Q. W M9704Q is also c apable of operating with a 3.3V supply only (digital and analogue).

An internally generated midrail reference is provided at pin CAP2 which is used as the chip reference. This pin should be heavily decoupled.

Additional features added to the Intel AC’97 specification, such as the EAPD (External Amplifier Power Down) bit, internal connection of PC-beep to the outputs in the case where the device is res et, are supported, along with optional features such as variable sample rat e support.

OPERATIONAL MODES

The WM9704Q is pin programmable to operate in the following modes:

MODE1

Table 1 Operating Modes

MODE0

0 0 2-channel 0 1 6-channel I2S 1 0 Quad m ode

OPERATIONAL

MODE

RESULTING DEVICE BEHAVIOUR

Rev 2.1 compliant codec (2-channel mode) Rev 2.1 compliant codec (6-channel mode) Quad DAC mode (with I

S 6-channel support)

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

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WM9704Q Production Data

QUAD MODE

In this mode the addit i onal 2 DA C channels are enabled, using the line level output pins 39 and 41 as outputs. An additional mixer block in this path allows the analogue mix, excluding the front DAC channels, to be summed into the rear channel mix. Additi onal gain controls (PGAs) are provided t o allow adjustment of front and rear mix levels separately (registers 72h and 74h) prior to s umm ing the analogue mix to these channels. The rear channel DACs als o are gain adjust able using regi ster 70h. This function duplicat es the features that are provided for the front DAC channel (gain range, step size etc).

Features in this mode are as f ol l ows:

• Vendor I D reads back WML4.

• All 6 audi o channels are flagged as supported (if I

• Headphone channel f lagged as not supported (bit ID4 in regis ter 00h).

• 4 channel s of DAC and 2 of ADC conversion availabl e, with all recommended Audi o and

modem sampl e rat es supported via the audio sampl e rate registers 2Ch (front channels; slots 3 and 4), 2Eh (rear channels; slot s 7 and 8) and 32h (ADCs) (Note if ID is sel ected as 11, register 30h is used for sample rate of LFE channel; sl ot 9).

• GPI O capability supporting Bits 11 to 13 is f l agged as supported.

• Master/slave ID0/1 are supported, with automatic re-mapping of the rear or LFE/centre DAC

slot data onto the rear DACs when ID 10 or 11 are sel ected (normally surround slots are mapped onto the rear DACs).

• LFE and Cent er channel data, plus a duplicate of t he rear channel data, is sent from the GPIO pins in I

S format, at 48ks/s rate (no variable rates supported by the I2S outputs).

• Headphone/l i ne l evel outputs are used to output the rear DAC and mixer channel, with volume controlled from register 38h.

• Wolfson 3D stereo enhancement supported.

• Master vol ume control register maps to the location dependant on s el ected ID: (ID 00 or 01

uses master volume at register 02h, ID 10 uses 38h (surround volume) and ID11 uses 36h (LFE, Center volume) In this case, bits 7 and 15 act as left and right mute.).

• DAC mute (reg18h) automatical l y de-muted, when ID is 1x, i.e. used as surround DAC or LFE/center, when surround or LFE/center master volume is de-muted.

• In order t o achieve the above functionality, the following changes to the Revisi on 2.1 compliant defaults are made.

• Revis i on 2.1 legacy compliance s witch is opened (can be closed using REV2SW bit i n regi ster 5Ah).

• Rear channel mixer PGA default is now not-mut ed, 0dB gain (same as front c hannel mixer).

• LNLVL pin vol ume control is now controlled from 02h unless ID=IO when volume control is

from 38h.

• Rear DAC le vel set by register 70h, default is 0dB not-muted.

• Front mixer and rear mixer gains set in registers 72h and 74h.

S enable bit is set).

REVISION 2.1 COMPLIANT 6-CHANNEL I2S MODE

In this mode the device now has 6-channel support and GPIO capability. Rear and LFE centre DAC data is mapped onto the GPI O output pins as I

the I

S enable bit is set in register 5Ah. Enabling of I2S overrides the GPIO funct i on.

Features in this mode are as f ol l ows:

• Vendor I D reads back as WML3.

• 2 channel s of ADC and DAC conversion provided.

• Rear and LFE/ centre DAC slots are flagged as supported in extended audio capability

• GPI O capability supporting bits 11-13 is flagged as supported.

• Master/slave ID0/1 are supported.

• Surround audio data not sent to the DACs is sent from the GPIO pins in I

rate (no variable rates supported by the I

• Headphone/li ne level outputs duplicating the main outputs are supported, with gai n control from register 04h.

• Wolfson 3D stereo enhanced sound supported.

• Master vol ume control register maps to the location dependant on s el ected ID: (ID 00 or 01

uses master volume at register 02h, ID 10 uses 38h (surround volume) and ID11 uses 36h (LFE, Centre volume) In this case, bits 7 and 15 act as left and right mute.).

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

S data when these data slots are tagged as valid, and

S outputs).

S format, at 48ks/s

Page 13

Production Data WM9704Q

REVISION 2.1 COMPLIANT 2-CHANNEL MODE

Features in this mode are as f ol l ows:

• Vendor I D reads back as WML3.

• 2 channel s of ADC and DAC conversion provided, with all recommended audio and modem

sample rates support ed vi a t he audi o sample rate registers 2Ch and 32h.

• Master/slave ID0/1 are supported.

• Headphone/li ne level outputs duplicating the main outputs, are supported, with gain control

from register 04h.

• Wolfson 3D stereo enhanced sound supported.

• Master vol ume control register maps to the location dependant on s el ected ID: (ID 00 or 01

uses master volume at register 02h, ID 10 uses 38h (surround volume) and ID11 uses 36h (LFE, Centre volume).

GPIO PINS AND I2S MODE

The AC’97 Revision 2.1 specification allows for provision of programmable IO pins, up to 16 in number. Within the 48-pin TQFP package used, provision has been made for 3 pins to be used as GPIO pins. These pins (numbers 43, 44, 48) are also used as I channel operation.

When used as GPI O pins, the pins 43, 44, 48 are mapped res pectively onto t he bits 11, 12,13 in t he AC-link slot 12. These optional locations may be configured in any way: as inputs or outputs, supporting interrupt operation etc, offering maximum flexibility to the user. The appropriate GPIO control registers are support ed to control these pins.

When used as I2S pins, pin 43 becom es the s hared LRCLK, with frequency fixed at 48k Hz. Pins 44 and 48 become the output data, clocked out at the BITCLK rate. Thus to connect an external DAC, configure it in I2S m ode:

• Connect BITCLK signal from the WM9704Q to the SCLK on the DAC.

• Connect BITCLK from the AC’97 to B CLK on the DAC.

• Connect pin 43 from the WM9704Q to the LRCLK on the DAC.

• Connect one of the two data pins 44 or 48 on WM9704Q to t he SDATA pin on the DAC.

Note that the DAC mus t s upport s erial i nterf ace dat a rates at up t o 12.5MHz (Wolfson DACs suc h as the WM8725 and WM8733 support this).

S output pins to support multi-

I2S is enabled when GPIO is not enabled (GPI O Bit 0 = 0, PRA = 1 in register 3Eh) and vendor specific I2S (bit 7) in register 5Ah is set.

The following table shows the connections to a typical I

WM9704Q CONNECTION I

BITCLK SCLK BITCLK BLCK Pin 43 – GPIO1 LRCLK Pin 44 – GPIO2 (surround data in ID00)

Pin 48 – GPIO3 (LFE/centre data in ID00) SDATA on external DAC

Table 2 Connection to External I2S DACs

Configuration of these pins as GPIO is described in the control interface descript i on.

3D STEREO ENHANCEMENT

This device contains a stereo enhancement circuit , designed to optimise the listening experience when the device is used in a typical PC operating environment. That is, with a pair of speakers placed either side of the m onitor with little s patial separation. This circuit creates a difference s ignal by differencing left and right channel playback data, then filters thi s difference signal using lowpass and highpass filters whose time constant s are set using external capacit ors connected to the CX3D pins 33 and 34. Typically the values of 100nF and 47nF set highpass and lowpass poles at about 100Hz and 1kHz respectively. This frequency band corresponds to the range over which the ear is most sensiti ve t o di rectional effects.

S compatible st ereo DAC (e.g. WM8725).

S DAC CONNECTION

SDATA on other external DAC FORMAT pin - connect for I2S mode DEEMPH (if provided) - disable

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WM9704Q Production Data

The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to register 22h bits 3 to 0. Value 0h is disable, value Fh is maximum effect. Typically a value of 8h is optimum. The user interface would mos t typically use a slider type of control to allow the user t o adjust the level of enhancem ent t o su it t he program m ateri al. B it D13 3D in regis ter 20h i s t he overall 3D enable bit. The capability register 00h reads back the value 11000 in bits D14 to D10. This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement.

Note that the external capacitors setting the filtering poles appl ied to the difference signal may be adjusted in value, or even replaced with a direct connec tion between the pins. If such adjust ments are made, then the amount of difference signal fed back into the main signal paths may be significant, and can cause large signals which may limit, distort, or overdrive signal paths or speakers. Adjust these values with care, to selec t the preferred acoustic effect.

There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied (if the signals are in phase and of the same amplitude).

Signals from the PCM DAC channels do not have stereo enhancement applied. It i s assumed that these signals will already have been processed digitally with any required 3D-enhancement effect. Applying the analogue 3D enhancement will corrupt this digital effect. This is equivalent to set ting t he POP bit in register 20h. A s a result, the readback value of this bit is fixed as 1, and attempts t o change it will be ignored. POP bit is set to one and cannot be re-set.

VARIABLE SAMPLE RATE SUPPORT

The DACs and ADCs on this devic e support all the recom mended s ample rat es spec ified in t he Int el Revision 2.1 specificat ion for both audio and modem rates. Default rat es are 48ks/s. If alternative rates are selected, the AC’97 interface continues to run at 48k words per second, but data is transferred across the li nk i n burst s s uch t hat t he net s am ple rat e selec ted i s ac hieved. I t is up t o the AC’97 Revision 2.1 compliant cont roller to ensure that data is supplied to the AC link, and received from the AC link, at the appropriate rate.

The device supports on demand sam pling. That is, when the DAC signal processing circuits need another sample, a sample request is sent to t he controll er which must respond with a data s ample i n the next frame it sends. For example, if a rate of 24ks/s is selected, on average the device will request a sample from the controll er every other frame, for each of the s tereo DACs. Note t hat if an unsupported rate is written to one of the rate registers, the rate will default to the nearest rate supported. The register will then respond when interrogated with the supported rate the device has defaulted to.

ADCs are controlled similarly but with one difference: Normally the left and right channel ADCs sample at the same rate.

AUDIO

SAMPLE RATE

8000 1F40 8400 20D0 11025 2B11 9000 2328 16000 3E80 9600 2580 22050 5622 10285.71 (72000/7) 282D 44100 AC44 12000 2EE0 48000 BB80 13714.28 (96000/7) 3592

Table 3 Variable Sample Rates Supported

CONTROL VALUE

D15 TO D0

MODEM

SAMPLE RATE

7200 1C20

8228.57 (57600/7) 2024

19200 4B00 24000 5DC0

CONTROL VALUE

D15 TO D0

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The following table shows which registers c ont rol which DAC rates, versus Mode and ID selected

MODE ID

Rev 2.1 mode (00)

Rev 2.1 6channel mode (01)

Quad mode (10)

Table 4 Variable Rate Register Location Versus Mode and ID

00 and 01 2Ch

10 2Eh 11 2Ch (centre) and 30h (LFE)

00 and 01 2Ch

10 2Eh 11 2Ch (centre) and 30h (LFE)

00 and 01 2Ch 2E h

10 2Eh 2Ch 11 2Ch (centre) and 30h (LFE) 2Eh

FRONT DAC RATE

GAIN CONTROL REGISTER LOCATION VERSUS MODE AND ID

Depending on what mode and ID the device is operated in, the various gain control registers have locations in the register map that may change. For exam ple, if the Codec is confi gured as ID 10, it means that the device will be converting the rear s urround DAC data. Therefore in this case the surround DAC volume word written to register 38h is now used to control the mas ter volume c ontrol, rather than the normal master volume 02h.

In addition, in this case when the surround volume mute control is written as de-mute, then m ute in the DAC PGA register 18h is automatically over-ridden, to avoid the user having to make an unexpected additional write to register 18h to de-mute the DAC PGA.

PGA

Front DAC

PGA

Rear DAC

PGA

Front Mixer

Rear Mixer

Front

Volume

Rear

Volume

Table 5 Gain Control Register Location Versus Mode and ID

CODEC

0x 10 11 0x 10 11 0x 10 11 0x 10 11 0x 10 11 0x 10 11

REV 2.1 MODE (0X) QUAD MODE (10)

CONTROL

REG

18h

70h

72h Not-muted (bit15) 72h Not-muted (bit15)

74h Permanently muted 74h Not-muted (bit15)

02h 38h 36h

04h

MUTE DEFAULT

Muted (bit15) AND with 38h,7,15 AND with 36h,7,15

Muted (bit15)

and powered off

Muted (15) muted (7 and 15) muted (7 and 15)

Muted (bit15) Rev 2.1

switch enabled

REAR DAC RATE

CONTROL

REG

18h

70h

02h 38h 36h 38h 02h 38h

AND with 38h,7,15 AND with 36h,7,15

Not-muted (bit15) AND with 02h, 15

AND with 38h,7,15

ADC RATE

REG

32h

MUTE DEFAULT

Muted (bit15)

Muted (15) muted (7 and 15) muted (7 and 15) Muted (7 and 15)

muted (15) muted (7 and 15)

MASTER/SLAVE ID0/1 SUPPORT

WM9704Q supports operati on as either a master or a slave codec. Conf iguration of the device as either a master or as a slave, is selected by tying the ID pins CID0 and CID1, pi ns 45 and 46 on the package.

Fundamentally, a device identi fied as a m aster (ID = 00) produces B ITCLK as an output, whereas a slave (any other ID) must be provided with BITCLK as an input. This has the obvi ous im plicat ion that if the master devic e on an AC link is disabled, the slave devices cannot function.

The AC’97 Revision 2.1 specifi cation def ines that the ID pins have inverting s ense, and are provi ded with internal weak pull ups. Therefore, if no c onnections are m ade to the CID0/1 pins , then t he pins pull hi and an ID = 00 is selected, i.e. m as ter. External connects to ground will select other IDs.

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PIN 46 CID1 PIN 45 CID0 ID SELECTED

NC NC 00 Master Output

NC Ground 01 Slave Input Ground NC 10 Slave Input Ground Ground 11 Slave Input

Table 6 ID Selection

WM9704Q supports the AMAP function whereby selection of an ID will autom atically map the data from the interface onto the PCM DACs.

AC–LINK FRAME DATA USED FOR DACS

CODEC ID

00 3 4 01 3 4 10 7 8 11 6 9

The Codec ID is available to the c ontroller via registers 28h and C3, bit s D15 and D14

Table 7 Default Slot to DAC Mappings Based on Codec ID

The above automatic mapping of data to slots is extended when the device is operated in the alternative modes selec table via the m ode pins. In t hese cases the selecti on of which data sl ots are mapped onto internal DACs or I

MODE

Rev 2.1

(00)

Rev 2.1

6-channel

(01)

Table 8 Slot to DAC and I2S Mapping Based on Mode and Codec ID

PCM left DAC uses

data from slot no.

S outputs is selec table as follows. (Note I2S enable bit must be set).

CODECIDSLOTS MAPPED

00 or 01 3 and 4

10 7 and 8 11 6 and 9

00 or 01 3 and 4 7 and 8 6 and 9

10 7 and 8 3 and 4 6 and 9 11 6 and 9

00 or 01 3 and 4 7 and 8 7 and 8 6 and 9

10 7 and 8 3 and 4 3 and 4 6 and 9Quad (10) 11 6 and 9 7 and 8 7 and 8 3 and 4

TO FRONT DACS

PCM right DAC uses

data from slot no.

SLOTS MAPPED

TO REAR DACS

Not supported

in this mode

Not supported

in this mode

MASTER

OR SLAVE

COMMENTS

Original definition (mas ter) Original definition (docking) Left/right surround channels Centre/LFE channels

DATA TO

S D0 PIN

Not supported

in this mode

7 and 8 3 and 4

BITCLK

DATA TO

I2S D1 PIN

Not supported

in this mode

SLAVE CODEC REGISTER ACCESS DEFINITIONS

Master Codec access is exactly as defined for AC’97. For s lave Codec access, the AC’97 Digital Controller must invali date the tag bits for Sl ot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0).

Slave Codecs disregard the Com mand Addres s and Com mand Dat a (Slot 0, bits 14 and 13) tag bit s when they see a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches t heir configuration. In a sense the Slave Codec ID fi eld funct ions as an al ternative Val id Comm and Addres s (f or Slave reads and writes) and Command Data (for S l ave writes) tag indicator.

Slave Codecs must monitor the Fram e Valid bit , and ignore the fram e (regardless of t he state of t he Slave Codec ID bits) if i t is not valid. AC’97 Digital Controllers should set the frame valid bit for a frame with a slave register acces s , even if no other bi ts in the out put t ag sl ot except t he Slave Codec ID bits are set.

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OUTPUT TAG SLOT (16-BITS)

BIT DESCRIPTION

15 14 13

12-3

1-0

Frame Valid Slot 1 Valid Command Address Bit (Master Codec onl y) Slot 2 Valid Command Data Bit (Master Codec only) Slot 3-12 Valid Bits as defined by AC’97 Reserved (Set to 0) 2-bit Codec ID field (00 reserved for Mas t er; 01, 10, 11 indicate Slave)

New definitions for Slave Codec Register Access

Table 9 Slave Codec Register Access Slot 0-Bit Definitions

CONTROL INTERFACE

A digital interface has been provi ded to control the W M9704Q and transfer data t o and from it. This serial interface is compatible with the Intel AC’97 specification as illustrated in Figure 7.

The main control interfac e functions are:

• Control of analogue gain and signal paths through the mixer.

• Bi-directional transfer of ADC and DAC words to and from AC’97 controll er.

• Selection of powerdown modes.

AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL

The WM9704Q incorporates a 5-pin digit al seri al int erfac e that link s i t t o the AC’97 controller. AC-link is a bi-directional, fi xed rate, serial PCM digital stream. It handles multiple input and output audio streams, as well as control register ac cesses empl oying a time division m ultiplexed (TDM) scheme. The AC-link architecture di vides each audio frame into 12 outgoi ng and 12 incoming data s treams, each with 20-bit sample resol ution. With a minim um required DAC and ADC resolution of 16-bits , AC’97 may also be implemented with 18 or 20-bit DAC/ADC resol ution, given the headroom that the AC-link architecture provi des. The WM9704Q provides support for 18-bit operation.

SLOT

NUMBER

0123456789101112

SYNC

CMD

PCM

SDATA_OUT

SDATA_IN

CODEC ID

TAG

STATUS

TAG

SLOTREQ 3-12

ADR

ADDR

DATA

STATUS

DATA

LEFT

PCM LEFT

RIGHT

PCM

RIGHT

LINE 1

DAC

LINE 1

ADC

CENTRE

Figure 8 AC’97 Standard Bi-directional Audio Frame

PCM

L SURR

MIC

RSRVD RSRVD RSRVD

ADC

PCM

R SURR

PCM

LFE

LINE 2

DAC

PCM L

(n+1)

LINE 2

ADC

HSET

DAC

PCM C

PCM R

(n+1)

HSET

ADCIOSTATUS

CTRL

(n+1)

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TAG PHASE DATA PHASE

20.8µS (48kHz)

SYNC

BIT_CLK

SDATA_OUT

END OF PREVIOUS

AUDIO FRAME

Figure 9 AC-link Audio Output Frame

12.288MHz

81.4nS

VALID

SLOT(1) SLOT(2) SLOT(12)

FRAME

TIME SLOT ’VALID’ BITS

(’1’ = TIME SLOT CONTAINS

VALID PCM DATA)

’0’

(ID1) (ID0)

19 0 19 0 19 0 19 0

SLOT (1) SLOT (2) SLOT (3) SLOT (12)

The datastreams currentl y defined by the AC’97 specificat i on i nclude:

PCM playback - 2 output slots 2-channel composit e P CM output stream PCM record data - 2 input slots 2-channel composite PCM input stream Control - 2 output slots Control register write port Status - 2 input slots Control register read port Optional dedicated microphone input -

1 input slot

Dedicated microphone input stream in support of stereo AEC and/or other voice appli cations.

Synchronisation of all AC-link data transactions is signalled by the WM9704Q controller. The WM9704Q drives the serial bi t clock onto AC-link, which the AC’97 cont roller then qualifies with a synchronisation signal t o construct audio frames .

SYNC, fixed at 48kHz, is derived by di viding down the serial clock (BIT _CLK). BIT_CLK, fixed at

12.288MHz, provides the necessary cloc king granularity t o support 12, 20-bit outgoing and incom ing time slots. AC-link serial data is t ransi tioned on eac h ris ing edge of BIT_CLK . The rec eiver of A C-link data, (WM9704Q for outgoing dat a and AC’97 cont roller for incoming data), samples each s erial bit on the falling edges of BIT_CLK.

The AC-link protocol provides for a special 16-bit tim e slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit positi on of slot 0 indicates that the c orresponding t im e s lot within the c urrent audi o fram e has been ass igned to a data stream, and contains valid data. If a slot is t agged invalid, it is the responsibilit y of the source of the data, (the WM9704Q for the input stream, AC’97 controller for the output stream), to stuff all bit positions with 0s during that slot’s active time.

SYNC remains high for a total duration of 16 BIT_CLKs at t he begi nni ng of each audio frame. The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder of

the audio frame where SYNC is low is defi ned as t he Data P hase. A ddit ionall y, for power savi ngs, al l clock, sync, and data signals can be halted. This requires that the WM9704Q be im plemented as a static design to all ow its register contents to remain intact when entering a power savings mode.

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AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)

The audio output frame data streams c orrespond to the m ultiplexed bundles of all di gital output dat a targeting the WM9704Q’s DAC inputs, and c ontrol regis ters. As brief ly ment ioned earlier, each audio output frame supports up t o 12 20-bit outgoing data t ime sl ots. S lot 0 i s a s pecial res erved tim e slot containing 16-bits, which are used for AC-link protocol infrastructure.

OUTPUT TAG SLOT (16-BITS)

Bit (15) Fram e Valid Bit (14) Sl ot 1 Valid Command Addres s bit (Pri mary Codec only) Bit (13) Sl ot 2 Valid Command Data bi t (Primary Codec only) Bit (12:3) Slot 3-12 Valid bits as defined by AC’97 Bit 2 Reserved (Set to 0) Bit (1:0) 2-bit Codec ID field (00 reserved for Primary; 01, 10, 11

New definitions for Secondary Codec Regi ster Access

Within sl ot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags t he validity for the entire audio frame. If t he Valid Frame bit is a 1, t hi s indicates that the current audio frame contains at least one time slot of valid data. The next 12-bit positions sampled by the W M9704Q indicate which of the corresponding 12 tim e slots contain valid data.

In this way data streams of differing sample rates can be transmitted across AC-link at its fixed 48kHz audio frame rate. Figure 9 illustrates the time slot based AC-link prot ocol.

indicate Secondary)

WM9704Q SAMPLES SYNC ASSERTION HERE

SYNC

WM9704Q SAMPLES FIRST SDATA_OUT BIT OF FRAME HERE

BIT_CLK

VALID

SLOT (1) SLOT (2)

SDATA_OUT

END OF PREVIOUS AUDIO FRAME

FRAME

Figure 10 Start of an Audio Output Frame

A new audio output frame begins with a low to high trans iti on of SY NC as s hown in Figure 10. SY NC is synchronous to the rising edge of BIT_CLK . On the im m ediat ely following falling edge of BI T_CLK, the WM9704Q samples the assertion of S YNC. This falling edge m arks the ti me when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK , AC’97 transitions SDATA_OUT i nto the first bit position of slot 0 (Vali d Frame bit). Eac h new bit position i s presented to AC-link on a rising edge of BIT_CLK, and subs equently sampled by the W M9704Q on the following falling edge of BIT_CLK. This sequence ensures that dat a transitions and subsequent sample points for bot h i ncoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert t o and from a fixed 48ks/s on the AC’97 controller. This requirement is necess ary to ensure that int eroperability between the AC’97 controller and the W M9704Q, among other things, can be guaranteed by definition for baseline specified AC’97 f eatures.

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions stuffed with 0s by the A C’97 controller. In the event that t here are less than 20 valid bits within an assigned and valid time s lot, the AC’97 controller always st uffs all trailing non-valid bit positions of the 20-bit slot with 0s.

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As an example, consider an 8-bit s ample stream that is being played out to one of t he W M9704Q’s DACs. The first 8 bit pos itions are presented to t he DAC (MSB justified) f ollowed by the next 12 bit positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the resolution of the implement ed DAC (16, 18 or 20-bit), no DC bias ing will be introduced by the least significant bits. When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data.

SLOT 1: COMMAND ADDRESS PORT

The command port is used to control features and monitor status for the WM9704Q functions including, but not lim ited to, mixer settings, and power managem ent (refer to the register s ection). The control interface architecture supports up to 64, 16-bit read/write regis ters, addres sable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid, odd register (01h, 03h, etc.) accesses are discouraged (if supported they should def ault to the preceding even byte boundary i.e. a read to 01h will return the 16-bit contents of 00h). The W M9704Q’s control register file is nonetheless readable as well as writeable to provide more robust testability.

Audio output frame slot 1 communicates control register address, and read/write command information to the WM9704Q.

COMMAND ADDRESS PORT BIT ASSIGNMENTS

Bit (19) Read/write command (1 = read, 0 = write) Bit (18:12) Control register index (64 16-bit locations, addressed on even

Bit (11:0) Reserved (stuffed with 0s)

The first bit (MSB) sam pled by the WM9704Q indic ates whether the current control transaction is a read or write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the s lot are reserved and must be stuffed with 0s by the AC’97 controller.

byte boundaries)

SLOT 2: COMMAND DATA PORT

The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (As indi cated by slot 1, bit 19).

Bit (19:4) Control register write data (stuffed with 0s if current operation is

Bit (3:0) Reserved (stuffed with 0s)

If the current command port operation is a read then the ent ire time slot m ust be stuffed with 0s by the AC’97 controller.

a read)

SLOT 3: PCM PLAYBACK LEFT CHANNEL

Audio output frame slot 3 is the composite digital audio left playbac k stream. In a typical Games Compatible PC this s lot is c omposed of s tandard PCM (.wav) output sam ples digital ly mixed (on the AC’97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC’97 controller must stuff all trailing non-valid bit positions within this time slot with 0s.

SLOT 4: PCM PLAYBACK RIGHT CHANNEL

Audio output frame slot 4 is the composite digi tal audio right playback stream. I n a typical Games Compatible PC this s lot is c omposed of s tandard PCM (.wav) output sam ples digital ly mixed (on the AC’97 controller or host processor) with music synthesis output samples.

If a sample stream of resolution less than 20-bit s is transferred, the AC’97 controller must stuff all trailing non-valid bit positi ons within this time s l ot with 0s.

SLOT 5: OPTIONAL MODEM LINE 1 CODEC

Slot 5 is not supported.

SLOTS 6 TO 9: SURROUND SOUND DATA

Audio output frame slots 6 to 9 are used to send surround s ound data to the extra DAC channels. These slots are supported by W M9704Q in Revi sion 2.1 6-c hannel mode and Quad m ode. Note t hat the data in the surround sound slot s m ay be applied to eit her the internal DACs, or sent out onto the GPIO pins as I

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S data, depending upon the mode and ID that has been selected.

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SLOT 10: OPTIONAL MODEM LINE2 CODEC

Slot 10 is not supported.

SLOT 11: HANDSET DAC

Slot 11 is not supported.

SLOT 12: GPIO CONTROL

Data in this slot is applied to the GPIO pins, if they have been enabled via the control regis ters. Note that only bits 11, 12 and 13 are s upport ed, all others are ignored.

AC-LINK AUDIO INPUT FRAME (SDATA_IN)

TAG PHASE DATA PHASE

20.8µS (48kHz)

SYNC

BIT_CLK

SDATA_IN

END OF PREVIOUS

AUDIO FRAME

12.288MHz

81.4nS

CODEC

SLOT(1) SLOT(2) SLOT(12)

READY

(’1’ = TIME SLOT CONTAINS

’0’ ’0’ ’0’ 19 0 19 0 19 0 19 0

TIME SLOT ’VALID’ BITS

VALID PCM DATA)

SLOT (1) SLOT (2) SLOT (3) SLOT (12)

Figure 11 AC-link Audio Input Frame

The audio input frame data stream s correspond to the multiplexed bundles of all digital input dat a targeting the AC’97 control ler. As is the case for audio out put frame, each AC-link audi o input fram e consists of 12, 20-bi t time slots.

Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol infrastructure.

Within slot 0 the first bit is a global bi t (SDATA_IN s lot 0, bit 15) which flags whether the W M9704Q is in the Codec Ready state or not. If the Codec Ready bit is a 0, this indi cates t hat the WM9704Q is not ready for normal operation. This condit ion is normal following the desertion of power on reset for example, while the WM9704Q’s voltage referenc es settle. W hen the AC-link Codec Ready indic ator bit is a 1, it indicates that t he AC-link and the WM9704Q control and s tatus registers are in a fully operational state. The AC’97 cont roller m ust f urther probe the Powerdown Control/St atus Register to determine exactly which subsec tions, if any, are ready.

Prior to any attempts at put ting t he WM9704Q into operation the AC’97 c ontroller s hould poll the f irst bit in the audio input frame (SDATA_IN sl ot 0, bit 15) for an indic ation that the W M9704Q has gone Codec Ready.

Once the WM9704Q is sam pled Codec Ready then the next 12 bit positi ons sampled by the AC’97 controller indicate which of t he corresponding 12 tim e slots are assi gned to input data streams, and that they contain valid data. Figure 11 illustrates the time slot based AC-link protocol.

There are several subsections within the WM9704Q that can independent ly go busy/ready. It is the responsibility of the W M9704Q controller to probe more deeply into the WM9704Q register file to determine which the WM9704Q subsections are actuall y ready.

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WM9704Q SAMPLES SYNC ASSERTION HERE

SYNC

AC’97 CONTROLLER SAMPLES FIRST SDATA_IN BIT OF FRAME HERE

BIT_CLK

CODEC

SLOT (1) SLOT (2)

SDATA_IN

END OF PREVIOUS AUDIO FRAME

READY

Figure 12 Start of an Audio Input Frame

A new audio input frame begins with a low to high transi tion of SYNC as shown in Figure 12. SY NC is synchronous to the rising edge of B IT_CLK. On the im m ediat ely following falling edge of BI T_CLK, AC’97 samples the assertion of SYNC. Thi s falling edge m arks the t ime when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, AC’97 transitions SDATA_IN into the firs t bit pos ition of slot 0 (“Codec Ready” bit ). Each new bit pos ition is present ed to AC-link on a rising edge of BI T_CLK, and subsequently sampl ed by the AC’97 Controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for bot h i ncoming and outgoing data streams are time aligned.

SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the WM9704Q. SDATA_IN should be sampled on the falling edges of BIT_CLK.

SLOT 1: STATUS ADDRESS PORT

The status port is used t o monitor status for the W M9704Q functions including, but not limited to, mixer settings, and power management.

Audio input frame slot 1 echoes the control register index, for histori cal reference, for t he data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged valid by the W M9704Q during slot 0).

STATUS ADDRESS PORT BIT ASSIGNMENTS:

Bit (19) RESERVED (stuffed with 0s) Bit (18:12) Control register index (echo of register i ndex for which data i s

being returned) Bit (11:2) Variable sample rate SLOTREQ bits. Bit (1:0) RESERVED (stuffed with 0s)

The first bit (MSB) generated by the WM9704Q is always stuffed with a 0. The following 7-bit positions communi cate the associated c ontrol register address. The next 10 bits s upport the AC’97 Rev 2.1 variable sample rate signalling protocol, and t he trailing 2 bit posit ions are stuf fed with 0s by AC’97.

SLOT 2: STATUS DATA PORT

The status data port delivers 16-bi t control register read data.

Bit (19:4) Control register read data (stuffed with 0s if tagged invalid

Bit (3:0) RESERVED (stuffed with 0s)

If slot 2 is tagged invalid by the WM9704Q, then the entire slot will be stuffed with 0s by the WM9704Q.

by WM9701)

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SLOT 3: PCM RECORD LEFT CHANNEL

Audio input frame slot 3 i s the left channel output of the WM9704Q’s input Mux, post-A DC. The WM9704Q’s ADCs c an be implemented to s upport 16, 18, or 20-bit resol ution. The WM9704Q

ships out its ADC output data (MSB f irst), and stuff s any trailing non-valid bit positions with 0s to fill out its 20-bit tim e slot.

SLOT 4: PCM RECORD RIGHT CHANNEL

Audio input frame slot 4 i s the right channel output of the WM9704Q’s input Mux, post-ADC. The WM9704Q’s ADCs c an be i mplemented to support 16, 18, or 20-bit resolution. The WM9704Q ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit

positions with 0s to fill out its 20-bit time slot.

SLOT 5: OPTIONAL MODEM LINE 1 CODEC

Slot 5 is not supported.

SLOT 10: OPTIONAL MODEM LINE 2 CODEC

Slot 10 is not supported.

SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA

Audio input frame slot 6 is an optional (post-ADC) third PCM system, input channel available for dedicated use by a desktop microphone. This optional AC’97 feature is not supported by the WM9704Q. This may be determ ined by the AC’97 controller i nterrogating the W M9704Q Vendor ID register.

SLOTS 7 TO 11: RESERVED

Audio input frame slots 7 to 11 are reserved for future use and are always s tuffed with 0s by AC ‘97.

SLOT 12:

GPIO functions support ed.

AC-LINK LOW POWER MODE

The AC-link signals can be plac ed in a low power mode. When the W M9704Q’s powerdown Register 26h, is programmed to the appropriat e value, both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage level.

BIT_CLK and SDATA_IN are trans itioned low immediately following the decode of the write to the Powerdown Register (26h) with PR4. When the AC’97 controller driver is at the point where it is ready to program the AC-link int o it s l ow power mode, slot s 1 and 2 are as s um ed t o be t he only valid stream in the audio output f rame. At this point in time it is assumed that all sources of audio input have also been neutralised.

The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the WM9704Q to this low power, halted mode.

Once the WM9704Q has been instructed to halt BIT_CLK , a special wake up prot ocol mus t be used to bring the AC-link to the active mode since normal audio output and input frames can not be communicated i n the absence of BIT_CLK.

WAKING UP THE AC-LINK

There are 2 methods for bringing the AC-link out of a l ow power, halted mode. Regardless of the method, it is the AC’97 controller that perform s the wake up task.

AC-link protocol provides f or a Col d WM9704Q Reset, and a Warm WM9704Q Reset. The current powerdown state would ultimately dict ate which form of WM9704Q reset is appropriate.

Unless a cold or register reset (a write to the reset register) is performed, wherein the WM9704Q registers are initialised to their default values, registers are required to keep state during all powerdown modes.

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Once powered down, re-activation of the AC-link vi a re-assertion of the SYNC signal must not occur for a minimum of 4 audio fram e times following the frame in which the powerdown was triggered. When AC-link powers up it i ndi cates readiness via the Codec Ready bi t (input slot 0, bit 15).

COLD WM9704Q RESET

A cold reset is achieved by asserting RESETB for the minimum specified time. By driving RESETB low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and all the WM9704Q control registers will be initialised t o t heir default power on reset values.

RESETB is an asynchronous WM9704Q input.

WARM WM9704Q RESET

A warm WM9704Q reset will re-activate the AC-link without altering the c urrent WM9704Q register values. A warm reset is signalled by driving SYNC high for a m inimum of 1µs in the absence of BIT_CLK.

Within norm al audio frames SYNC is a synchronous input. I n the absence of BIT_CLK, SY NC is treated as an asynchronous input used in the generation of a warm reset to the WM9704Q. The WM9704Q will not respond with the activation of B IT_CLK until S YNC has been s ampled low again by the WM9704Q. This will preclude the false detection of a new audio frame.

SERIAL INTERFACE REGISTER MAP DESCRIPTION

(See Table 24)

The serial interface bits perform cont rol functions described as f ollows. Note that the register m ap is fully specified by the AC’97 s pecif ication, and this des cripti on is si mply repeat ed below, with optional unsupported features omit ted.

RESET REGISTER (INDEX 00h)

Writing any value to t hi s register performs a register reset, which causes al l registers to revert to their default values. Reading this register returns the ID code of t he part, indic at ion of m odem s upport (not supported by the WM9704Q) and a code f or the type of 3D stereo enhancement.

BIT FUNCTION

ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9

SE4...SE0

Table 10 Reset Register Function

Note that the WM9704Q defaults to indic ate 18-bit c om patibilit y. However, a control bit m ay be set in the vendor-specific registers that changes bits ID6 and ID8 to be 0, indicating a 16-bit device. It is unlikely that this function will be required, however, as the MSB justification of t he ADC and DAC data means that a nominally 18-bit device should be fully compatible with controllers that only provide 16-bit support. Most PC type applications will only require 16-bit operation.

Dedicated Mic PCM in channel Modem line Codec support Bass and treble control Simulated stereo (mono to stereo) Headphone out support Loudness (bass boost) support 18-bit DAC resolution 20-bit DAC resolution 18-bit ADC resolution 20-bit ADC resolution 3D stereo enhancement tec hni que

VALUE ON

WM9704Q

0 0 0 0 0 0 1 0 1 0

11000

PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)

These registers manage the output signal volumes . Register 02h controls the stereo mas ter volume (both right and left channels), Register 04h c ontrols t he optional s tereo headphone out , and Register 06h controls the mono volume output. Each st ep corresponds to 1.5dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that c hannel i s set at -

∞dB.

ML5 through ML0 is for left channel level, ML5 through ML0 is f or the ri ght c hannel and MM5 through MM0 is for the mono out channel.

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Support for the MSB of the volume level i s not provided by the W M9704Q. If the MSB is written t o, then the WM9704Q detect s when that bit is set and sets all 4 LSB s to 1s. E xample: If the driver write s a 1xxxxx th e W M 9704Q interprets that as x11111. It will also respond when read with x11111 rather than 1xxxxx, the value writt en to i t. Th e dri ver c an us e thi s fe atur e to d etec t if support for t he 6th bit is there or not.

The default value of both the mono and t he stereo regist ers is 8000h (1000 0000 0000 0000), which corresponds to 0dB gain with mut e on.

MUTE MX4...MX0 FUNCTION

0 0 0000 0 0 0001 0 1 1111 1 x xxxx

Table 11 Volume Register Function

0dB attenuation

1.5dB attenuation

46.5dB attenuation

∞dB attenuation

MASTER TONE CONTROL REGISTERS (INDEX 08h)

Optional register for support of tone controls (bass and treble). The WM9704Q does not support bass and treble and writing to this register will have no effect, reading will result in all don’t care values.

PC BEEP REGISTER (INDEX 0Ah)

This controls the level for the PC-beep input. Each step corresponds to approximately 3dB of attenuation. The MSB of the regis ter is the mute bit. When this bit is set to 1 the level for that channel is set at -

WM9704Q defaults to t he PC-beep path being m uted, except during reset when the path i s open, so an external speaker should be provided within the PC to alert the user to power on self-test problems.

∞dB.

MUTE PV3...PV0 FUNCTION

0 0000 0 1111 1 xxxx

Table 12 PC-beep Register Function

0dB attenuation 45dB attenuation

∞dB attenuation

ANALOGUE MIXER INPUT GAIN REGISTERS (INDEX 0Ch - 18h)

This controls the gain/attenuation for each of the analogue inputs. Each step corresponds to approximately 1.5dB. The MSB of the regi ster is the mut e bit. When t his bit is set to 1 the level for

that channel is set at -∞dB . (See Table 13).

This has an extra bit that is for a 20dB boost. When bit 6 is s et to 1 t he 20dB boos t i s on. The default value is 8008, which corresponds to 0dB gai n with mute on.

The default value for the mono regis ters is 8008h, which corres ponds to 0dB gain with m ute on. The default value for stereo registers is 8808h, which corresponds to 0dB gain with mute on.

MUTE GX4...GX0 FUNCTION

0 00000 0 01000 0 11111 1 xxxxx

Table 13 Mixer Gain Control Register Function

+12dB gain 0dB gain

-34.5dB gain

∞dB gain

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RECORD SELECT CONTROL REGISTER (INDEX 1Ah)

Used to select the record source independently f or right and left (s ee Table 14). The default value i s 0000h, which corresponds to Mic in.

SR2 TO SR0 RIGHT RECORD SOURCE SL2 TO SL0 LEFT RECORD SOURCE

0 1 2 3 4 5 6 7

Table 14 Record Select Register Function

Mic

CD in (R)

Video in (R)

Aux in (R)

Line in (R)

Stereo mix (R)

Mono mix

Phone

0 1 2 3 4 5 6 7

RECORD GAIN REGISTERS (INDEX 1Ch AND 1Eh)

1Ch is for the stereo input and 1Eh i s for the optional special purpos e correlated audio Mic channel. Each step corresponds to 1. 5dB. 22.5dB corres ponds t o 0F0Fh and 000Fh respec tivel y. The MSB of the register is the m ute bit. When thi s bit is set to 1, t he l evel for that channel(s) is set at -

The default value is 8000h, which corresponds to 0dB gain with mute on.

MUTE GX3...GX0 FUNCTION

0 0 1

Table 15 Record Gain Register Function

1111 +22.5dB gain 0000 0dB gain

xxxxx -

∞dB gain

Mic

CD in (L)

Video in (L)

Aux in (L)

Line in (L)

Stereo mix (L)

Mono mix

Phone

∞dB.

GENERAL PURPOSE REGISTER (INDEX 20h)

This register is used to control several misc el l aneous functions of the WM9704Q. Below is a summary of each bit and its funct ion. Only the MIX, MS and LPBK bits are supported by

the WM9704Q. The MS bit controls the Mic s elector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-link, allowing for full system performance measurements. The f unction default value is 8000h, which is all off.

BIT FUNCTION

POP

ST 3D LD

LLBK

RLBK

MIX

LPBK

Table 16 General Purpose Register Function

PCM out path and mute, 0 = pre-3D, 1 = post -3D Yes, but fi xed at 1 Simulated stereo enhancement, on/off 1 = on No 3D stereo enhancement on/off, 1 = on Yes Loudness (bass boost) on/off, 1 = on No Local loop back - for modem, line codec No Remote loop back - for modem, line codec No Mono output select 0 = Mix, 1 = Mic Yes Mic select 0 = Mic1, 1 = Mic2 Yes ADC/DAC loopback mode Yes

WM9704Q SUPPORT

3D CONTROL REGISTER (INDEX 22h)

This register is used to control t he centre and/or depth of the 3D st ereo enhancement functi on built into of the AC ‘97 component. Only the depth bits DP0 to 3 have eff ect in the WM9704Q.

DP3…DP0 DEPTH

00% 1

8 Typical value

15 100%

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RESERVED REGISTER (INDEX 24h)

Not supported by the W M9704Q.

POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)

This read/write register is used t o program powerdown states and m oni tor s ubsys tem readines s. The lower half of this register is read only status, a 1 indicating that the subsection is ready. Ready is defined as the subsection able to perform in its nominal s tate. When this regist er is written the bit values that come in on AC-link will have no effect on read only bits 0 to 7.

When the AC-link Codec Ready indicator bit (SDATA_I N slot 0, bit 15) is a 1, it indicat es that the A Clink and the WM9704Q control and status registers are in a fully operational state. The AC’97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any, are ready.

READ BIT FUNCTION

REF

ANL DAC ADC

Table 17 Powerdown Status Register Function

The powerdown modes are as follows. The first three bi ts are to be used individually rather than i n combination with each other. The l ast bit PR3 can be used in combination with PR2 or by itself. PR0 and PR1 control the PCM ADCs and DACs onl y. PR6 is not supported by the WM9704Q.

WRITE BIT FUNCTION

PR0

PR1

PR2

PR3

PR4

PR5

PR6

EAPD

Table 18 Powerdown Control Register Function

VREFs up to nominal level Analogue mixers, etc ready DAC section ready to acc ept data ADC section ready to transmit data

PCM in ADCs and input Mux powerdown PCM out DACs powerdown Analogue mixer powerdown

(VREF still on) Analogue mixer powerdown (VREF off) Digital interface (AC-link) powerdown

(external clock off) Internal clock disabl e HP amp powerdown – not supported External amplifier powerdown

NORMAL

PR0 = 1

PR0 = 0 AND

ADC = 1

ADCs OFF

READY = 1

PR1 = 1 PR2 = 1 PR4 = 1

DAC = 1

DACs OFF

PR1

PR2 = 0 AND

ANL = 1

DEFAULT

PR0

PR1 = 0 AND

ANALOGUE

OFF PR2 OR

PR3

DIGITAL I/F

OFF PR4

WARM

RESET

SHUT OFF

CODA LINK

Figure 13 An Example of the WM9704Q Powerdown/Powerup Flow

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Figure 13 illustrates one example of a procedure to do a complete powerdown of the W M9704Q. From normal operation sequent i al writes to the Powerdown Register are performed to powerdown the WM9704Q a piece at a time. After everyt hing has been shut off (PR0 to PR3 set ), a final write (of PR4) can be executed to shut down the W M9704Q’s digital interface (AC-li nk).

The part will remain in sleep mode with all its registers holding t heir static values. To wake up the WM9704Q, the AC’97 controller will send a pulse on the s ync line issuing a warm reset. This will restart the W M9704Q’s digital interface (resetting PR4 to 0). The W M9704Q can also be woken up with a cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them to their default states . When a sec tion is powered back on, the Powerdown Control/S tatus Register (26h) should be read to verify that the section is ready (i.e. st able) before attempting any operation that requires it.

Alternatively if RESETB is held low, all PR bits are held set so the device is held powered off until RESETB is taken high again.

ADCs OFF

PR0

PR1 = 1

PR1 = 0 AND

DAC = 1

DACs OFF

PR2 = 1 PR4 = 1

ANALOGUE

PR1

PR2 = 0 AND

ANL = 1

OFF PR2

OR PR3

DIGITAL I/F

OFF PR4

WARM RESET

SHUT OFF

CODA LINK

Figure 14 The WM9704Q Powerdown/Flow with Analogue Still Alive

Figure 14 illustrates a state when all the mixers should work with the s tatic volume s ettings that are contained in their associated registers. This is used when the user is playing a CD (or external LINE_IN source) through WM9704Q to the speakers but has m os t of t he s yst em in low power m ode. The procedure for this follows the previous proc edure except that the analogue mixer is never shut down.

POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h)

Note that in order to go into ultimate low power mode, PR5 is required to be set which turns of f the oscillator circuit. As serting SYNC resets the P R5 bit and re-starts the osc illator in the same was as the AC link is restart ed.

Also when RESETB pin is asserted low, all PR bits are over-ridden and the entire device is powered off to ultra low power state for as long as RESETB = low. On releasing RESETB, the device is reset (all active) and powered up.

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REVISION 2.1 REGISTERS (INDEX 28h T0 58h)

These registers are specified as to use in Revision 2.1 of the AC’97 specification and have the following functions on the WM9704Q:

The Extended Audio ID register is a read only register that identif ies which extended audio features are supported (in addition to the original AC’97 features i dentified by reading the reset register at index 00h). A non-zero value indicates the feature is supported. The indication of support for 6-channel surround sound changes depending on whether the WM9704Q is conf igured in mode 00 or otherwise.

DATA BIT FUNCTION ANY MODE BUT 10 MODE 10

VRA DRA

VRM CDAC SDAC LDAC AMAP

ID1 ID0

Table 19 Extended Audio ID Register

Variable rate audio support Double rate audio support Variable rate Mic ADC support Centre DAC support Surround DAC support LFE DAC support Slot to front DAC m appi ng support Codec configuration – pin 45 value Codec configuration – pin 46 value

The Extended Audio Status and Control Regis ter is a read/write register that provides status and control of the extended audio features.

11 00

00 0 (unless I2S = 1) 1 when ID = 11 or I2S = 1 0 (unless I2S = 1) 1 0 (unless I2S = 1) 1 when ID = 11 or I2S = 1

Inverse of level at pin 45 Inverse of level at pin 45 Inverse of level at pin 46 Inverse of level at pin 46

DATA BIT FUNCTION READ/WRITE WM9704Q SUPPO RT

VRA DRA

VRM CDAC SDAC

LDAC

MADC

PRI PRJ

PRK

PRL

Table 20 Extended Audio Status and Control Register

Enables variable rate audio mode Enable double rate audio mode Enables variable rate Mic ADC Indicates centre DAC ready Indicates surround DAC ready Indicates LFE DAC ready Indicates Mic ADC ready Set to turn off centre DAC Set to turn off surround DA Cs Set to turn off LFE DACs Set to turn off Mic ADC

Read/write Yes Read/write No Read/write No

Read Yes Read Yes Read Yes

Read No Read/write Enable only Read/write Enable only Read/write Enable only Read/write No

These registers are read/write registers that are written to, to select al ternative sample rates for the audio PCM converters. Default is the 48ks/ s rate. Note that only Revision 2.1 recom mended rates are supported by the WM9704Q, selection of any other unsupported rates will cause the rate to default to the nearest support ed rate, and the supported rate value to be latched and so read back.

S mode ONLY supports 48ks/s rates, NOT variable rates .

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REGISTERS 36h AND 38h – 6 CHANNEL VOLUME CONTROL

These read/write registers control the out put volum e of the opti onal four PCM channel s. Note t hat as WM9704Q only supports 4 internal DACs, depending upon which ID has been selected via t he CID pins 45 and 46, these registers may or may not have effect . The fields behave the same as the master volume cont rol regi st er, which of fers att enuation but no gai n. If gain is required t hen t he PCM DAC mixer PGAs appropriate to each DAC should be used.

If Quad Mode is selected and ID = 10 or 11, then either 36h or 38h will control the level of the rear

GPIO FUNCTION

DAC outputs onto the line level pins 39 and 41. Surround data which is m apped from the surround data slots out onto the GPI O pins as I however, mute the data to all 0s.

Note that only the three GPIO pins are supported, GPIO 11 to 13. These pins are available to the user, unless used for I

S mode. GPIO mode over-ri des I2S function.

The GPIO Pin Configuration is a read/write regis ter that specifies whether a GPIO pin is configured for input (1) or for output (0), and is ac cessed via the s tandard slot 1 and 2 c ommand addres s/data protocols.

If a GPIO pin is implemented, the respective GCx bit should be read/writeable and s et t o 1. If a GPI O is not implement ed, then the respect ive GCx bit is read-only and set to 0. This informs the sof tware how many GPIO pins have been implem ented. It is up to the AC’97 Digital Controller to send t he desired GPIO pin value over output sl ot 12 in the outgoing stream of the AC-link before c onfiguring any of these bits for output. The default value after cold or regist er reset for t his regist er (3800h) is all pins configured as inputs.

S data, may not have it’s level adjusted. The mute bit will,

The GPIO Pin Polarity/Type is a read/write register that defines GPIO input polarity (0 = Low, 1 = High active) when a GPIO pin is configured as an Input. It defines GPIO output type (1 = CMOS, 0 = OPEN-DRAIN) when a GPIO pin is conf i gured as an output.

The default value after cold or register reset for this register (FFFFh) is all pins active high. Non-implemented GPI O pi ns always return 1s.

The GPIO Pin Sticky is a read/write register that defines GPIO Input Type (0 = Non-sticky, 1 = Sticky) when a GPIO pin is conf igured as an input. GP IO input s conf igured as s tic ky are cl eared by writing a 0 to the corresponding bit of t he GPIO pin status regist er 54h (see below), and by reset.

The default value after cold or register reset for this register (0000h) is all pins Non-sticky. Unimplemented GPI O pins al ways return 0s . S tic ky i s def ined as edge-s ensi tive, Non-s ti ck y as level sensitive.

The GPIO Pin Wake-up is a read/write regi st er that provi des a m as k f or determ i ning if an input GP IO change will generate a wake-up or GPIO_INT (0 = No, 1 = Yes). W hen t he A C-Link is powered down (Register 26h PR4 = 1 for primary codecs), a wake-up event will trigger t he assertion of SDA TA_IN. When AC-link is powered up, a wake-up event will appear as GPIO_INT = 1 on bit 0 of input s lot 12. GPIO_INT is also flagged when the link is active.

An AC-link wake-up interrupt is defined as a 0 to 1 transit ion on SDATA_IN when the AC-Link is powered down (Register 26h PR4 = 1). GPIO bits that have been program med as i nputs, s ticky and pin wake-up, upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause an AC-link wake-up event (transition of SDATA_IN from 0 to 1), if and only if the AC-link was powered down.

The default value after cold or register reset for this regi ster (0000h) defaults to all 0s specifying no wake-up event. Non-implemented GPIO pins always return 0s.

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The GPIO status is a read/write register that reflects the state of all GPIO pins (inputs and outputs) on slot 12. The value of all GPIO pin inputs and outputs co m es in f rom the c odec every f ram e on s lot 12, but is also available for readi ng as GPIO Pin Status via the s tandard slot 1 and 2 comm and address/data protocols. GPIO inputs configured as Sticky are cleared by writing a 0 to the corresponding bit of this regi ster 54h.

Bits corresponding to unim plemented GPIO pins s hould be forced to zero i n this register and input slot 12. GPIO bits that have been programmed as I nputs and Sticky, upon trans ition either (high-to low) or (low-to-high) depending on pin polarity, will cause the individual GPIO bit to go as serted 1, and remain asserted until a write of 0 to that bit. The normal way to set t he desired value of a GPIO output pin is to set the control bit in output slot 12.

The default value, if confi gured as an input, after c old or register reset f or this register is always the state of the GPIO pin.

Not supported in this m ode.

VENDOR RESERVED REGISTERS (INDEX 5Ah AND 7Ah)

These registers are vendor specif ic . Do not write t o thes e regis ters unles s t he Vendor ID regi st er has been checked first to ensure that the driver knows the source of the AC‘97 component. Values s tored in this register are used to provide vendor specific modes for the manufacturer.

BIT NAME DEFAULT ACTION WHEN SET TO 1

User bits

I2S

ADC no DAC

Rev 2.1 switch

S enable

Dual line modem Automute disable

0 0

AND

R2S

DLM

AMD

Table 22 Vendor Register 5Ah Bit Allocation and Default States

Select stereo mix into ADC as having no DAC signal

Closes Rev 2.1 switch when set (see fig 1) Enables I2S data and clock onto GPIO pi ns

43,44,48 Selects support for Line2 DAC and ADC slots Disables automute f unction on the front and

rear DACs

VENDOR SPECIFIC GAIN CONTROL REGISTERS – (INDEX 70h TO 74h)

These three registers control the gain and mute functi ons applied to the front and rear m ixer paths, and the rear channel DAC gains. These PG As are not accomm odated in the Intel spec ification, but are required in order to build a flexible quad surround sound device. The function is as per the other mixer PGAs. However, the default value of the register changes depending upon the MODE the device is operating in, as s hown in Table 23.

DEFAULT VALUE FOR REGISTER

MODE

Rev 2.1 (00) Rev 2.1 6-channel

(01) Quad (10)

Table 23 Vendor Specific PGA Default Values

REAR DAC –

REG 70H

8808 0808 8808 Closed 8808 0808 8808 Closed

8808 0808 0808 Open

FRONT MIXER –

REG 72H

REAR MIXER –

REG 74H

REV 2.1

SWITCH

VENDOR ID REGISTERS (INDEX 7Ch TO 7Eh)

This register is for spec ific vendor ident ificati on if so desired. The ID method is Micros oft’s Pl ug and Play Vendor ID code. The first character of that I D is F7 to F0, the sec ond character S 7 to S0, and the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field i s for the Vendor Revision number. In WM9704Q the vendor ID is set to W ML3 if MODE1 = 0, and W ML4 if MODE1 = 1.

Wolfson is a registered Microsoft Plug and Play vendor.

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The following table shows the function and address of the various control bits that are loaded through the serial interface during write operat i ons.

Reg Name D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0Default

00h Reset 02h Master volume 04h Headphone vol. 06h Master vol. m ono 0Ah PCBEEP vol. 0Ch Phone volume 0Eh Mic volume 10h Line in volume 12h CD volume 14h Video volume 16h Aux volume 18h Frnt PCM out

volume 1Ah Rec. select 1Ch Rec. gain 20h General purpose 22h 3D control 24h Reserved 26h Pwrdwn ctrl/stat 28h Ext’d audio ID 2Ah Ext’d audio

ctrl/stat 2Ch Front DAC rate 2Eh Rear DAC rate 30h LFE DAC rate 32h Audio ADC rate 36h 6ch vol. C,LFE 38h 6ch vol. L,R s urr 3Ch Ext’d mdm ID 3Eh Ext’d mdm stat

Line1 sample

40h

rate ADC/DAC

Line2 sample

42h

rate ADC/DAC

Line1 DAC/ADC

46h

level

Line2 DAC/ADC

48h

level

GPIO pin config

4Ch

GPIO pin type

4Eh

GPIO pin sticky

50h

GPIO wake-up

52h

GPIO pin status

54h

Misc. modem

56h

ctrl/stat 5Ah Vendor rsvd test 70h Rr PCM out vol. 72h Front mixer vol. 74h Rear mixer vol. 7Ah Vendor rsvd 7Ch Vendor ID1 7Eh Vendor ID2

Table 24 Serial Interface Register Map Description

X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6140h Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8000h Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8000h MuteXXXXXXXXXXMM4MM3MM2MM1MM08000h MuteXXXXXXXXXXPV3PV2PV2PV0X8000h MuteXXXXXXXXXXGN4GN3GN2GN1GN08008h MuteXXXXXXXX20dB X GN4 GN3 GN2 GN1 GN0 8008h Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

XXXXXSL2SL1SL0XXXXXSR2SR1SR00000h Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 GR0 8000h

POPST3DlDXXMIXMSLPBKXXXXXXX8000h

XXXXXXXXXXXXDP3DP2DP1DP00000h

XXXXXXXXXXXXXXXX0000h

APD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Fh

ID1 ID0 X X X X Amap Ldac Sdac Cdac X X VRM X DRA VRA 0281h

X PRL PRK PRJ PRI X Madc Ldac Sdac Cdac X X VRM X DRA VRA 0080h

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

Mute X X LFE4 LFE3 LFE2 LFE1 LFE0 Mute X X NT4 NT3 CNT2 CNT1 CNT0 0000h Mute X X LSR4 LSR3 LSR2 LSR1 LSR0 Mute X X SR4 SR3 RSR2 RSR1 RSR0 8080h

ID1ID0XXXXXXXXXID2CID1HSETLIN2LIN1x00xh

PRH PRG PRF PRE PD PRC PRB PRA DAC HADC DAC2 DC2 AC1 ADC1 MREF PIO 0100h

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

Sample rates written to 42h will alias onto 40h Not supported - set TX modem level s by writing to rear DAC PGA 04h Not supported - set TX modem level s by writing to rear DAC PGA 04h

00 11GC13GC12GC1111111111111FFFFh 00GP13GP12GP11000000000000000h 00GS13GS12GS11000000000000000h 00GI13GI12GI1100000000000000xh

CID2 CID1 CIDR MLNK X HSB2 HSB1 HSB0 X L2B2 L2B1 L2B0 X L1B2 L1B1 L1B0 0000h

ATST DTST AFTS DFTS RTST DDS AMD DLM I2S R2S AND HIM HIC TRM BB AEV 0000h

Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 0808h Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 0808h Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

XXXXXXXXXXXXXXXX0000h F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 574Dh T7 T6 T5 T4 T3 T2 T1 T0 Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0 4C04h

GW13 GW12 GW1

00000000000000Eh

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

Page 33

Production Data WM9704Q

RECOMMENDED EXTERNAL COMPONENTS

MODE OF

OPERATION

CONTROL

NOTES: 1. Pins 27, 29 and 31 are internally connected. It is recommended that capacitors only be

connected to one of

these pins.

2. C1 to C28 should be as close to WM9704Q as possible.

3. AGND and DGND should be connected as close to WM9704Q as possible.

MIXER

INPUTS

AVDD

AVSS

AC-LINK

DVDD

DGND

AVDD

DVDD1

DVDD2

C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17

DVSS1

DVSS2

PCBEEP

PHONE

AUXL

AUXR

VIDEOL

VIDEOR

CDL

CDGND

CDR

MIC1

MIC2

LINEINL

LINEINR

MODE0

MODE1

CID1

CID2

SDATAOUT

BITCLK

SDATAIN

SYNC

RESETB

WM9704Q

LNLVLOUTL

LNLVLOUTR

XTLOUT

XTLIN

C34

LINEOUTL LINEOUTR MONOOUT

AVDD1 AVDD2

AVSS1 AVSS2

VREF

VREFOUT

AFILT1

CAP1 CAP2

CX3D1 CX3D2

GPIO1 GPIO2 GPIO3

EAPD

C35

25 38

26 42

27 28 29 31 32

C21 C22

33 34

35 36 37 39 41

43 44 48 47

C3 C4

C23 C25

C27

C29

C30

C31

C32

C33

AGND

C18 C19 C20

C24 C26

AGND

C28

AGND

STEREO OUTPUT

MONO OUTPUT

LINE LEVEL STEREO

TO I2S DACs

AGND

DGND

Figure 15 External Components Diagram

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

Page 34

WM9704Q Production Data

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

C1 to C4 10nF De-coupling for DVDD and AVDD C5 to C17 470nF AC coupling capacitors for setting DC level of anal ogue i nputs to VCAP1.

C18 1µF C19 0.1µF C20 10µF C21 0.1µF C22 10µF C23 0.1µF C24 10µF C25 0.1µF C26 10µF C27 100nF 3D low pass f i l ter. This value sets nominal 100Hz. C28 47nF 3D high pass fil ter. This value sets nominal 1kHz. C29 to C33 10µF Output AC coupling caps to remove V RE F DC l evel from outputs. C34 and C35 22pF Optional capacitors for better crystal frequency stability. XT 24.576 MHz AC’97 master clock frequency. A bias resistor is not required, but if connected will not

Table 25 External Component Values

SUGGESTED

VALUE

DESCRIPTION

Value chosen to give corner frequenc y below 20Hz for min 10K input impedanc e. Reference de-coupling capacit ors for ADC, DAC, Mixer and CAP2 references .

Ceramic type or sim i l ar.

affect operation if value i s large (above 1MΩ).

RECOMMENDATIONS FOR 3.3V OPERATION

The device’s performance with AVDD = 3.3V is shown in Electrical Characteristics. In 3.3V analogue operation, mid-rail reference sc ales t o 1.5V . A ll A DC and DAC ref erences are 3/5

of their nominal 5V value. Input and output signals that are 1Vrms in 5V applications, scale to 660mVrms in 3.3V appli cations. If 1Vrms output i s required, the mi xer gain adjust PGAs need to be increased by 3 times 1. 5dB steps.

ths

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001

Page 35

Production Data WM9704Q

PACKAGE DIMENSIONS

FT: 48 PIN TQFP (7 x 7 x 1.4 mm)

DM003.B

2536

2437

E1 E

121

ccc

-C-

SEATING PLANE

Dimensions

Symbols

(mm)

MIN NOM MAX A A

----- ----- 1.60

0.05 ----- 0.15

1.35 1.40 1.45

b 0.17 0.22 0.27 c D D

0.09 ----- 0.20

9.00 BSC

7.00 BSC

E 9.00 BSC E

e L

0.45 0.60 0.75

7.00 BSC

0.50 BSC

3.5

Tolerances of Form and Position

ccc

0.08

REF: JEDEC.95, MS-026

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = BBC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

WOLFSON MICROELECTRONICS LTD PD Rev 2.3 January 2001