Datasheet WM9704CFT-V Datasheet (Wolfson)

WM9704M

AMC’97 Audio and Modem Codec

Production Data, January 2001, Rev 3.2

DESCRIPTION

WM9704M is a high quality audio c odec compliant with the
AC'97 Revision 2.1 specification. The WM9704M has a
proprietary mode which can meet the requirements of an
AMC’97 codec. It performs full duplex 18-bit codec functions
from 8 to 48ksamples/s and offers excellent quality with
high SNR. Features include 3D sound and line-level
outputs. Support is al so provided for variable sample rates
and master/slave mode operation.

In modem mode the devic e supports simultaneous modem
and stereo playback.

WM9704M is interchangeable with AC'97 Codecs from
Wolfson and other suppliers in the basic Revision 2.1 mode.
WM9704M is fully operable with 3.3V or 5V or mixed

3.3/5.0V supplies and is packaged in an indus try standard
48-pin TQFP package.

BLOCK DIAGRAM

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

KEY:

MONO

STEREO

3D

Σ

RECORD

MUX
AND

MUTE

Σ

CD (18,20)

LINEIN (23,24)

VIDEO (16,17)

AUX (14,15)
PHONE (13)

PCBEEP (12)

MIC[1] (21)
MIC[2] (22)

MUX

0dB/

20dB

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

Σ

Σ

Σ

FEATURES

• 4 DAC channels, stereo ADC

• S/N ratio > 95dB

• Variable rate audio and modem support

• Analogue 3D stereo enhancement

• Line level outputs

• Master/slave ID selection

• Low power implementation

• 3.3V or 5V operation

• 48-pin TQFP package

APPLICATIONS

• Simultaneous m odem operation and stereo playback

(35,36)
LINEOUT
(FRONT)

(39,41)
LINEOUT
(REAR)

(37) MONOOUT

(40) MODE1
(30) MODE0
(47) EAPD

(6) BITCLK
(10) SYNC
(8) SDATAIN
(5) SDATAOUT
(11) RESETB

(45) CID0
(46) CID1

(43,44,48)
GPIO[1:3]

(2) XTLIN
(3) XTLOUT

VOL/

MUTE

VOL/

MUTE

VOL

REV. 2.1
SWITCH

MUX

STEREO

STEREO

WM9704M

STEREO

REAR

DAC

FRONT

DAC

ADC

VOL/

MUTE

VOL/

MUTE

VOL/

MUTE

SRC

SRC

SRC

SERIAL
SERIAL

I/F
I/F

MASTER/

SLAVE

SELECT

GENERAL IO

SUPPORT

OSC

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: [phone]
Fax: [phone]
Email: [email protected]
http://www.wolfson.co.uk

Production Data datasheets contain final

specifications current on publication date.

Supply of products conforms to Wol fson
Microelectronics’ Term s and Conditions.

 2001 Wolfson Microelectronics Ltd.

WM9704M Production Data PIN CONFIGURATION ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM9704CFT/V 0 to 70oC 48-pin TQFP

GPIO3

EAPD

CID1

CID0

GPIO1

GPIO2

AVSS2

MONOOUT

AVDD2

LNLVLOUTL

MODE1

LNLVLOUTR

CDR

3747 46 45 44 43 42 41 40 39 3848

36

LINEOUTR
LINEOUTL

35
34

CX3D2

33

CX3D1

32

CAP2

31

CAP1

30

MODE0

29

AFILT1

28

VREFOUT
VREF

27

AVSS1

26
25

2316 17

MIC2

MIC1

AVDD1

24

LINEINL

LINEINR

DVDD1

XTLIN

XTLOUT

DVSS1

SDATAOUT

BITCLK
DVSS2

SDATAIN

DVDD2

SYNC
RESETB
PCBEEP

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15

18 19 20 21 22

CDL

AUXL

AUXR

PHONE

VIDEOL

CDGND

VIDEOR

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c onti nuously operat ing at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions s pecified

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.

As per specifications IPC/JEDEC J-STD-020A and JEDEC A113-B, this product requires specific storage conditions prior to
surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in
vacuum-sealed moisture barrier bags.

CONDITION MIN MAX

Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, T

A

Storage temperature
Package body temperature (s ol deri ng 10 seconds)
Package body temperature (s ol deri ng 2 minutes)

-0.3V +7V

-0.3V +7V
DVSS -0.3V DVDD +0.3V
AVSS -0.3V AVDD +0.3V

+240
+183

o

C

o

C

o

C

0oC+70

o

-65

C +150oC

Note:

1. The digital supply voltage (DVDD) must always be less than or equal to the analogue supply voltage (AVDD).

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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Production Data WM9704M

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital supply range
Analogue supply range
Digital ground
Analogue ground
Difference DVSS to AVSS
Analogue supply current
Digital supply current
Standby supply current (all P Rs set)
Analogue supply current
Digital supply current
Standby supply current (all P Rs set)

DVDD1, DVDD2 -10% 3.3 to 5.0 +10% V
AVDD1, AVDD2 -10% 3.3 to 5.0 +10% V

DVSS1, DVSS2 0 V
AVSS1, AVSS2 0 V

-0.3 0 +0.3 V
DVDD, AVDD = 5V 35 mA
DVDD, AVDD = 5V 25 mA
DVDD, AVDD = 5V 10 µA

DVDD, AVDD = 3.3V 22 mA
DVDD, AVDD = 3.3V 15 mA
DVDD, AVDD = 3.3V 6 µA

ELECTRICAL CHARACTERISTICS

Test Characteristics:

AVDD = 5V, GND = 0V …………..T
DVDD = 3.3V, GND = 0V …………..T

= 0oC to +70oC, unless otherwise stated

A

= 0oC to +70oC, unless otherwise stated

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Logic Levels (DVDD = 3.3 or 5.0V)

Input LOW level V
Input HIGH level V
Output LOW V
Output HIGH V

OL
OH

IL
IH

IOL = 2mA 0.1 x DVSS V
IOH = 2mA 0.9 x DVDD V

AVSS -0.3 0.8 V

2.0 AVDD +0.3 V

Analogue I/O Levels (Input signals on any inputs, Outputs on LINEOUT L, R and MONO)

Input level

Output level

Minimum input

impedance = 10k

AVSS

-100mV

Into 10kohm load AVSS

+100mV

Near rail to

rail

AVDD
+100mV

AVDD

-100mV

V

V

Reference Levels

Reference input/output CAP2
CAP2 impedance
Mixer reference VREF

2/5 AVDD AVDD/2 3/5 AVDD V

75 kohms

Buffered

V

CAP2

MIC reference VREFOUT

Buffered

V

CAP2

ADC reference CAP1

Buffered

V

CAP2

DAC reference AFILT1

Buffered

V

CAP2

MIDBUFF current sink

AVDD = 5V -5 -15 mA
(pins CAP1, AFILT2, VREF
and VREFOUT)

MIDBUFF current source

AVDD = 5V 5 15 mA
(pins CAP1, AFILT1, VREF
and VREFOUT)

MIDBUFF current source

AVDD = 3.3V 5 mA
(pins CAP1, AFILT1, VREF
and VREFOUT)

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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WM9704M Production Data

Test Characteristics:

AVDD = 5V, GND = 0V …………..T
DVDD = 3.3V, GND = 0V …………..T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DAC Circuit Specifications (AVDD = 5V) 48kHz sampling

SNR A-weighted (Note 1)
Full scale output voltage
THD
Frequency response
Transition band
Stop band
Out of band rejection
Spurious tone reduction
PSRR

ADC Circuit Specifications (AVDD = 5V) 48kHz sampling

SNR A-weighted (Note 1)
ADC input for full scal e out put
THD
Frequency response
Transition band
Stop band
Stop band rejection
PSRR

Mixer Circuit Specificati ons (AVDD = 5V) 48kHz sampling

SNR CD path A-weighted (Note 1)
SNR Other paths A-weighted

(Note 1)
Maximum input voltage
Maximum output voltage on

LINEOUT
THD
Frequency response (+/-1dB)
Input impedance (CD inputs )
Input impedance (other mixer

inputs)
Input impedance MIC inputs

PSRR

DAC Circuit Specifications (AVDD = 3.3V) 48kHz sampling

SNR A-weighted (Note 1)
Full scale output voltage
THD
Frequency response
Transition band
Stop band
Out of band rejection
Spurious tone reduction
PSRR

= 0oC to +70oC, unless otherwise stated

A

= 0oC to +70oC, unless otherwise stated

A

V

= 2.5V 1.0 Vrms

REF

-3dB output 74 90 %

20 to 20kHz 40 dB

V

= 2.5V 1.0 Vrms

REF

-6dBFS input 74 90 %

20 to 20kHz 40 dB

At any gain 10 15 kohm

At max gain 10 20 kohm

At 0db gain 100 kohm

At max gain 80 kohm

At 0db gain 10 15 kohm

20 to 20kHz 40 dB

V

= 1.65V 0.7 Vrms

REF

-3dBFSsp output 90 %

20 to 20kHz 40 dB

85 96 dB

20 19,200 Hz
19,200 28,800 Hz
28,800 Hz

-40 dB

-100 dB

75 85 dB

20 19,200 Hz
19,200 28,800 Hz
28,800 Hz

-74 dB

90 100 dB

85 95 dB

AVSS 1.0 AVDD Vrms

1.0 1.8 Vrms

74 90 %

20 20,000 Hz

96 dB

20 19,200 Hz
19,200 28,800 Hz
28,800 Hz

-40 dB

-100 dB

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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Production Data WM9704M

Test Characteristics:
AVDD = 5V, GND = 0V …………..T
DVDD = 3.3V, GND = 0V …………..T

= 0oC to +70oC, unless otherwise stated

A

= 0oC to +70oC, unless otherwise stated

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ADC Circuit Specifications (AVDD = 3.3V) 48kHz sampling

SNR A-weighted (Note 1)
ADC input for full scal e out put
THD
Frequency response
Transition band
Stop band
Stop band rejection
PSRR

V

= 1.65V 0.7 Vrms

REF

-9dBFS input 80 %
20 19,200 Hz

19,200 28,800 Hz
28,800 Hz

-74 dB

20 to 20kHz 40 dB

82 dB

Mixer Circuit Specificati ons (AVDD = 3.3V) 48kHz sampling

SNR CD path A-weighted

97 dB

(Note 1)
SNR Other paths A-weighted

92 dB

(Note 1)
Maximum input voltage
Maximum output voltage on

0.7 Vrms

0.7 Vrms

LINEOUT
THD
Frequency response (+/-1dB)
Input impedance (CD inputs )
Input impedance (other Mixer

inputs)
Input impedance MIC inputs

-3dBV input 90 %
20 20,000 Hz

At any gain 15 kohm

At max gain 20 kohm

At 0db gain 100 kohm

At max gain 80 kohm

At 0db gain 15 kohm

PSRR

20 to 20kHz 40 dB

Clock Frequency Range

Crystal clock
BIT_CLK frequency
SYNC frequency

24.576 MHz

12.288 MHz

48.0 kHz

Note:

1. SNR is the ratio of 0dB signal ampl i tude to noise floor with no signal, measured A-weighted over a 20Hz to 20kHz
bandwidth.

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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WM9704M Production Data PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1
2
3
4
5
6

7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

Note:

1. Pins 27, 29 and 31 have an internal connection.

DVDD1 Supply Digital positive supply

XTLIN Digital input Clock crystal connection or clock input (XTAL not used)

XTLOUT Digital output Clock crystal connection

DVSS1 Supply Digital ground supply

SDATAOUT Digital i nput Seri al data input

BITCLK Digi tal output (master)

Digital input (slave)

DVSS2 Supply Digital ground supply

SDATAIN Digital output Serial data output to AC’97 controller

DVDD2 Supply Digital positive supply

SYNC Digit al i nput Seri al i nt erface sync pulse from A C’97 c ontroller
RESETB Digital input NOT reset input (active low, resets regis ters)
PCBEEP Analogue input Mixer input, typically for PCBEEP signal

PHONE Analogue input Mixer input, typical l y f or P HONE signal

AUXL Analogue input Mixer input, typically for AUX signal

AUXR Analogue input Mixer input, typically for AUX signal

VIDEOL Analogue input Mixer input, typically for VIDEO s i gnal

VIDEOR Analogue input Mixer input, typically f or V IDEO signal

CDL Analogue input Mixer input, typically for CD signal

CDGND Analogue input CD input common mode reference (ground)

CDR Analogue input Mixer input, typically f or CD signal
MIC1 Analogue input Mixer input with extra gain if required
MIC2 Analogue input Mixer input with extra gain if required

LINEINL Anal ogue i nput Mixer input, typically for LINE signal
LINEINR Analogue input Mixer input, typically for LINE signal

AVDD1 Supply Analogue positive suppl y
AVSS1 Supply Analogue ground supply, chip substrat e

VREF(1) Analogue output Buffered CAP 2

VREFOUT Analogue output Reference for microphones; buffered CAP 2

AFILT1(1) Analogue output Buffered CAP2

MODE0 Digital input 6 channel support I

CAP1(1) Analogue output Buf f ered CAP2

CAP2 Analogue input Reference input/output; pulls to midrail if not driven

CX3D1 Analogue output Output pin f or 3D di fference signal
CX3D2 Analogue input Input pin for 3D dif ference signal

LINEOUTL Analogue output Main analogue output for left c hannel
LINEOUTR Analogue output Main analogue output for right channel
MONOOUT Analogue output Main mono output

AVDD2 Supply Analogue positive suppl y

LNLVLOUTL Anal ogue output Left channel line level output

MODE1 Digital input Mode select pin, internal pull down

LNLVLOUTR Analogue output Right channel line level output

AVSS2 Supply Analogue ground supply, chip substrat e

GPIO1 Programmable I/O GPIO or I
GPIO2 Programmable I/O GPIO or I

CID0 Digital input Master/slave ID selec t (internal pull-up)
CID1 Digital input Master/slave ID selec t (internal pull-up)

EAPD Digital output External amplifier power down/GPO

GPIO3 Programmable I/O GPIO

Serial interface cloc k output to AC’97 controller
or input from AC’97 mas ter codec

2

S enable

2

S

2

S

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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Production Data WM9704M

DETAILED TIMING DIAGRAMS

Test Characteristics:

AVDD = 5V, GND = 0V …………..T
DVDD = 3.3V, GND = 0V …………..T
All measurement s are taken at 10% to 90% VDD, unl ess otherwise stated.

AC-LINK LOW POWER MODE

= 0oC to +70oC, unless otherwise stated

A

= 0oC to +70oC, unless otherwise stated

A

COLD RESET

SYNC

SLOT 1 SLOT 2

BIT_CLK

SDATA_OUT

WRITE

TO 0X20

DATA PR4

t

S2_PDOWN

DON’T
CARE

SDATA_IN

Figure 1 AC-Link Powerdown Timing

PARAMETER SYMBOL MIN TYP MAX UNIT

End of slot 2 to BITCLK S DA T IN low

t

RST_LOW

t

S2_PDOWN

t

RST2CLK

1.0 µs

RESETB

BIT_CLK

Figure 2 Cold Reset Timing

PARAMETER SYMBOL MIN TYP MAX UNIT

RESETB active low pulse width t
RESETB inactive to BIT_CLK

RST_LOW

t

RST2_CLK

1.0 µs

162.8 ns

startup delay

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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WM9704M Production Data

WARM RESET

Figure 3 Warm Reset Timing

PARAMETER SYMBOL MIN TYP MAX UNIT

SYNC active high pulse width t
SYNC inactive to BIT_CLK

startup delay

CLOCK SPECIFICATIONS

SYNC

BIT_CLK

BIT_CLK

t

CLK_HIGH

t

CLK_PERIOD

t

SYNC_HIGH

t

SYNC_HIGH

SYNC_HIGH

t

SYNC2_CLK

t

SYNC2CLK

1.3 µs

162.4 ns

t

CLK_LOW

t

SYNC_LOW

SYNC

t

SYNC_PERIOD

Figure 4 Clock Specifications (50pF External Load)

PARAMETER SYMBOL MIN TYP MAX UNIT

BIT_CLK frequency
BIT_CLK period t
BIT_CLK output jitter
BIT_CLK high pulse width (Note 1) t
BIT_CLK low pulse width (Note 1) t
SYNC frequency
SYNC period t
SYNC high pulse width t
SYNC low pulse width t

CLK_PERIOD

CLK_HIGH
CLK_LOW

SYNC_PERIOD

SYNC_HIGH
SYNC_LOW

32.56 40.7 48.84 ns

32.56 40.7 48.84 ns

12.288 MHz

81.4 ns
750 ps

48.0 KHz

20.8 µs

1.3 µs

19.5 µs

Note: Worst case duty cycle restri cted to 40/60

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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Production Data WM9704M

DATA SETUP AND HOLD (50PF EXTERNAL LOAD)

t

SETUP

BIT_CLK

t

HOLD

SYNC

SDATA_OUT

Figure 5 Data Setup and Hold (50pF External Load)

PARAMETER SYMBOL MIN TYP MAX UNIT

Setup to falling edge of BIT_CLK t
Hold from falling edge of BI T_CLK t

SETUP

HOLD

15.0 ns

5.0 ns

Note: Setup and hold tim e parameters for SDATA_IN are with res pect to AC’97 Controller.

SIGNAL RISE AND FALL TIMES

t

BIT_CLK

t

rise

rise

CLK

SYNC

t

fall

CLK

t

fall

SYNC

SYNC

t

rise

DIN

t

fall

DIN

SDATA_IN

t

rise

DOUT

t

fall

DOUT

SDATA_OUT

Figure 6 Signal Rise and Fall Times (50pF external load)

PARAMETER SYMBOL MIN TYP MAX UNIT

BIT_CLK rise time trise
BIT_CLK fall time tfall
SYNC rise time trise
SYNC fall time tfall
SDATA_IN rise time trise
SDATA_IN fall time trise
SDATA_OUT rise time trise
SDATA_OUT fall time tfall

CLK

CLK

SYNC

SYNC

DIN
DIN

DOUT

DOUT

440ns
440ns
440ns
440ns
440ns
440ns
440ns
440ns

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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WM9704M Production Data SYSTEM INFORMATION

CD, VIDEO,

AUX, LINEIN

MIC2

MIC1

PCBEEP

RESET

AC’97

DIGITAL

CONTROLLER

BITCLK

SYNC

SDATAIN

SDATAOUT

CHIP

SELECT

CID0
CID1

{

Figure 7 WM9704M i n a Typical Application

22 21 12

11
6

WM9704M

10
8

5

45
46

(MODEM MODE)

23

XTAL

MODE0 = 1
MODE1 = 1

39, 41

GPIO [1:3]

35

36

13

37

484443

LNLVLOUTL/R

PHONE

MONOOUT

Tx

Rx

LINEOUTL/R
FRONT DATA

DAA

MODEM
DATA

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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Production Data WM9704M

DEVICE DESCRIPTION

INTRODUCTION

The WM9704M comprises a st ereo 18-bit Codec, (that is, 2 ADCs and 2 DACs) plus two additional
DACs. The additional pair of DAC channels are used to convert the Modem Tx data mapped from the
Line1 interface slot, at t he sample rate selected i n the Modem Rate register. Additi onally, a vendor
specific mode i s provided to allow dual line support for line1 and line2.

Alternatively, the WM9704M can be configured as a standard AC’97 Rev 2.1 device. In this m ode t he
device includes line level outputs and support for the variable rate audio sample rates spec ified in
Rev 2.1.

The WM9704M is fully com pliant with Rev 2.1 of the AC’97 specifi cation. The W M9704M comprises
a stereo 18-bit Codec, (that is, 2 A DCs and 2 DACs) plus t wo additional DACs. The WM9704M also
has a comprehensive analogue mixer with 4 sets of st ereo inputs, plus phone, 2 microphone, and
PC-beep inputs. Additionall y, on-chip reference c ircuits generate the necess ary bias voltages for the
device, and a bi-directional s eri al i nterface allows transfer of c ont rol data and DAC and ADC words to
and from the AC’97 controller. The W M9704M supports 18-bit resolution within the DA C and ADC
functions, but the AC’97 serial interface specification allows any word length up to 20-bits to be
written to, or read from, the A C’97 Codec. These words are MSB justified, and any LSBs not used
will simply default to 0. Normally it is anticipated that 16-bit words will be used in most PC type
systems. Therefore, for the DAC, 16-bit words will be downloaded into the Codec from t he controller,
along with padding of 0s to make the 16-bi t word up to 20-bit lengt h. In thi s c ase, the WM9704M will
process the 16-bit word along with 0 padding bits i n the 2 LSB loc ations (t o m ake 18-bit ). A t t he ADC
output, WM9704M will provide an 18-bit word, again with 0s in the two LS B locations (20-bit). The
AC’97 controller will then ignore the 4 LSBs of the 20-bit word. When the W M9704M is interrogated,
it responds indicating i t i s an 18-bit device.

The WM9704M has the ADC and DAC func tions implemented using oversampled, or ‘sigma-delta’
converters, and uses on-chi p di gi t al filters to convert thes e 1-bi t signals to and from t he 48ks/s 16/18­bit PCM words that the AC’97 controller requires. The digital parts of the device are powered
separately from the analogue to optimise performance, and 3.3V digital and 5V analogue supplies
may be used on the same devi ce to further optim ise performance. Digi tal IOs are 5V tolerant when
the analogue supplies are 5V, so the W M9704M may be connected to a controller running on 5V
supplies, but use 3.3V f or the digital section of W M9704M. WM9704M is als o capable of operating
with a 3.3V supply only (digital and analogue).

An internally generated midrail reference is provided at pin CAP2 which is used as the chip
reference. This pin should be heavily decoupled.

The WM9704M is not limited to PC-only applications. The ability to powerdown sections of the device
selectively, and the option t o choose alternative m aster clock, and henc e sample rates, m eans that
many alternative applicat i ons in areas such as telecomms, may be ant i cipated.

Additional features added to the Intel AC’97 specification, such as the EAPD (External Amplifier
Power Down) bit, internal connection of PC-beep t o the outputs in the case where the device is reset,
are supported, along with optional features such as variable sample rat e support.

OPERATIONAL MODES

The WM9704M is pin programmable to operate in the following modes :

MODE1

Table 1 Operating Modes

MODE0

PIN

0 0 2-channel
1 1 Modem mode

PIN

OPERATIONAL

MODE

RESULTING DEVICE BEHAVIOUR

Rev 2.1 compliant codec (2-channel mode)
Modem DAC mode

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

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WM9704M Production Data

MODEM MODE

In Modem mode the modem Tx data is mapped onto the rear DACs. Rear DAC sam ple rates are set
by the Modem Tx sample rate register 40h, and extended modem capability register 3Ch indicates
Line1 is supported. The following features are supported in Modem Mode:

• Vendor I D reads back WML4

• Headphone channel f lagged as ‘not supported’ (bit ID4 in register 00h)

• 4 channel s of DAC and 2 of ADC conversion availabl e, with all recommended Audio and

Modem sample rates supported via the audio sample rate regi sters 2Ch (front DACs),
40h (rear DACs) and 32h (ADCs in audio mode)

• ADC s amples are output onto both audio s l ots 3 & 4 and also line2/1 slot s 10 & 5
respectively

• Line1 Tx modem data is mapped onto the rear DA Cs as data and inverted data, so that t he
PAIR of rear DACs produce a differential Tx modem data output.

• Right audio ADC changes to use line1 sample rate 40h, when input mix selects PHONE
as its IP.

• Additional vendor specific mode DLM is available via bit DLM in register 5A h. Setting this bit
provides support for line2 as well as l i ne1 slots. Rear DACs are mapped onto line1 and line2
Tx modem data slots, and ADC Left and right outputs are m apped bot h onto normal audio
slots 3 and 4 and also onto the li ne1 and l i ne2 Rx m odem data slots. Modem rate register
40h is used for both DACs and the A DC's use their normal sample rate registers i.e. audio
registers, unless Right channel is selected as PHONE, in which case they too use regi ster
40h.

• If DLM bit i s set in register 5Ah, t hen l i ne1 Tx data is mapped onto the rear left DAC, and
Line2 Tx data is mapped onto the rear right DAC. Both rear DACs use the same sample rate
from register 40h (if 42h is written to, 40h will be updated inst ead)

• Left ADC always uses normal ADC audio rate regi ster, except in DLM mode when RPHONE
is selected, when it uses 40h

• GPI O capability supporting GPIO (11 to 13) is flagged as supported

• Master/slave ID0/1 are supported, with automatic re-mapping of the rear or LFE /center DAC

slot data onto the front DA Cs when ID 10 or 11 are selected

• Headphone/line level output pins 39 and 41 are used to output the rear DAC signals, with
volume controlled from register 04h. Rear mixer PGA is f i xed in MUTE condi tion.

• Wolfson 3D stereo enhancement supported

• Master vol ume control register maps to the location dependant on s el ected ID: (ID 00 or 01

uses master volume at register 02h, ID 10 uses 38h (surround volume) and ID11 uses 36h
(LFE, Center volume) In this case, bits 7 and 15 act as left and right mute.)

• Front DA C mute (reg18h) automatical l y de-muted, when ID is 1x, i.e. used as s urround DAC
or LFE/center, when surround or LFE/center master volume is de-muted.

• Rear DAC mute (reg70h) automatical l y de-muted when 04h volume is de-muted

• ADC’s always used record level from regis ter 1Ch

In order to achieve the above functionality, the following changes t o the Rev 2.1 compliant, or quad
mode, defaults are m ade:

• Rev 2.1 l egacy compliance switch i s opened (can be closed using REV2S W bit in regist er
5Ah)

• Rear channel mixer PGA default is now permanently muted, (unlikely that t he user wants to
send the analogue mix output onto the Tx modem line output)

• Tx modem level at the LNLVL pins still controlled from 04h rather than 46h or 48h (which
would normally be the modem A DC and DA C l e vel control registers)

• Rx ADC input levels are st ill controlled from the normal ADC record level regis t er 1Ch (rather
than 46h or 48h due to the difficult y i n re-al l ocating left and right channel gai n controls into
two different registers)

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REV 2.1 COMPLIANT 2-CHANNEL MODE

Features in this mode are as f ol l ows:

• Vendor I D reads back as WML3

• 2 channel s of ADC and DAC conversion provided, with all recommended Audio and Modem

sample rates support ed vi a t he audi o sample rate registers 2Ch and 32h

• Master/slave ID0/1 are supported

• Headphone/li ne level outputs duplicating the main outputs, are supported, with gain control

from register 04h

• Wolfson 3D stereo enhanced sound supported

• Master vol ume control register maps to the location dependant on s el ected ID: (ID 00 or 01

uses master volume at register 02h, ID 10 uses 38h (surround volume) and ID11 uses 36h
(LFE, Centre volume)

GPIO PINS

The AC’97 Rev 2.1 specificat ion allows for provision of programm able IO pins, up to 16 in number.
Within the 48-pin TQFP package used, provision has been made f or 3 pins to be us ed as GP IO pins .
These pins (numbers 43, 44, 48) are al so used as I

When used as GPIO pins, the pins 43, 44, 48 are mapped ont o the bits 11,12,13 in t he AC-link slot

12. These optional locations may be configured in any way: as input s or output s, s upporting interrupt

operation etc, offering maximum flexibility to the us er. The appropriate GPIO control registers are
supported to control these pi ns.

Configuration of these pins as GPIO is described in the Control Interface descripti on.

2

S output pins to support multi-channel operation.

3D STEREO ENHANCEMENT

This device contains a ‘stereo enhanc ement’ circuit, designed to optim ise the listening experience
when the device is used in a typical PC operating environment. That is, with a pair of speakers
placed either side of the m onitor with little s patial separation. This circuit creates a di fference si gnal
by differencing left and right channel playback data, then f ilters this difference si gnal using lowpass
and highpass filters whose time constants are s et using external capacitors connected to the CX3D
pins (33 and 34). Typically the values of 100nF and 47nF set highpass and lowpass poles at about
100Hz and 1kHz respectively. This f requency band corresponds to the range over which the ear is
most sensiti ve t o di rectional effects.

The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to
register 22h bits 3 to 0. Val ue 0h is ‘disable’, value Fh i s maximum effect. Typic ally a value of 8h is
optimum. The user interface would most typically use a slider type of control to allow the user to
adjust the level of enhancement to suit the program material. Bit D13 ‘3D’ in register 20h is the
overall 3D enable bit. The capability register 00h reads back the value 11000 in bits D14 to D10. This
corresponds to decimal 24, which is registered with Intel as ‘Wolfson Stereo Enhancement’.

Note that the external capacitors setting the filtering poles appli ed to the difference s ignal may be
adjusted in value, or even replaced with a direct connecti on between the pins. If such adjustm ents
are made, then the amount of difference signal fed back into the main signal paths may be
significant, and can cause large signals which may limit, distort, or overdrive signal paths or
speakers. Adjust these values with care, to selec t the preferred acoustic effect.

There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied
(if the signals are in phase and of the same amplitude).

Signals from the PCM DAC channels do not have s tereo enhancement applied. It is assumed that
these signals will already have been processed digitally with any required 3D-enhancement effect.
Applying the analogue 3D enhancement will corrupt this digital effect. This is equivalent to s etti ng the
POP bit in register 20h. As a result, the readback value of this bit is fixed as '1', and attempts to
change it will be ignored. POP bit is set to one and cannot be re-set.

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VARIABLE SAMPLE RATE SUPPORT

The DACs and ADCs on this devic e support all the recom mended s ample rat es spec ified i n the Intel
Rev 2.1 specification f or both audio and modem rates. Default rates are 48ks/ s. If alternat ive rates
are selected, the AC’97 i nterface continues to run at 48k words per second, but data is transf erred
across the link in bursts such that the net sam ple rate selected is achieved. It is up to the AC’97
Rev 2.1 compliant cont roller to ens ure that data is supplied t o the AC li nk, and recei ved from t he AC
link, at the appropriate rate.

The device supports ‘on demand’ s ampling. That is, when the DAC s ignal processing circuit s need
another sample, a sample request is sent to the cont roller which m ust res pond with a data sam ple in
the next frame it sends. For example, if a rate of 24ks/s is selected, on average the device will
request a sample from the controll er every other frame, for each of the stereo DACs. Note that if an
unsupported rate is written to one of the rate registers, the rate will default to the nearest rate
supported. The register will then respond when interrogated with the supported rate the device has
defaulted to.

ADCs are controlled similarly but with one difference: Normally the left and right channel ADCs
sample at the same rate.

AUDIO

SAMPLE RATE

8000 1F40 8400 20D0
11025 2B11 9000 2328
16000 3E80 9600 2580
22050 5622 10285.71 (72000/7) 282D
44100 AC44 12000 2EE0
48000 BB80 13714.28 (96000/7) 3592

Table 2 Variable Sample Rates Supported

The following table shows which registers c ont rol which DAC rates, versus Mode and ID selected

MODE ID FRONT DAC RATE REGISTER REAR DAC RATE REGISTER

00 and 01 2Ch

Rev 2.1 mode (00)

Modem mode (11)

Table 3 Variable Rate Register Location Versus Mode and ID

10 2Eh
11 2Ch (centre) and 30h (LFE)

00 and 01 2Ch

10 2Eh
11 2Ch (centre) and 30h (LFE)

CONTROL VALUE

D15 TO D0

MODEM

SAMPLE RATE

7200 1C20

8228.57 (57600/7) 2024

19200 4B00
24000 5DC0

40h

CONTROL VALUE

D15 TO D0

ADC RATE

REG

32h

32h (40h if

PHONE

IP selected)

GAIN CONTROL REGISTER LOCATION VERSUS MODE AND ID

Depending on what mode and ID the device is operated in, the vari ous gain control registers have
locations in the register map that may change.

In Modem mode, the rear volume is mapped always to location 46h, and the rear mixer is fixed
muted so analogue sources cannot be summed into t he Tx m odem signal.

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REV 2.1 MODE (00) M O DE M MODE (11)

PGA ID

Front DAC
PGA

Rear DAC
PGA

Front Mixer

Rear Mixer

Front
Volume

Rear
Volume

Table 4 Gain Control Register Location Versus Mode and ID

0x
10
11
0x
10
11
0x
10
11
0x
10
11
0x
10
11
0x
10
11

CONTROL

REG

18h

70h

72h Not -muted (bit15) 72h Not-muted (bit15)

74h Permanently muted 74h Permanently m uted

02h
38h
36h

04h

MUTE DEFAULT

Muted (bit15)
AND with 38h,7,15
AND with 36h,7,15

Muted (bit15)

and powered off

Muted (15)
muted (7 and 15)
muted (7 and 15)

Muted (bit15) Rev 2.1

switch enabled

CONTROL

REG

18h

70h AND with 04h, 15

02h
38h
36h

04h Muted (bit 15)

MUTE DEFAULT

Muted (bit15)
AND with 38h,7,15
AND with 36h,7,15

Muted (15)
muted (7 and 15)
muted (7 and 15)

MASTER/SLAVE ID0/1 SUPPORT

WM9704M supports operation as either a mast er or a slave codec. Configuration of the device as
either a master or as a sl ave, is s elect ed by tying the ID pins CID0 and CI D1, pins 45 and 46 on the
package.

Fundamentally, a device identi fied as a m aster (ID = 00) produc es BITCLK as an output, whereas a
slave (any other ID) must be provided with BITCLK as an input. This has the obvious impli cation t hat
if the master devic e on an AC link is disabled, the slave devices cannot function.

The AC’97 Rev 2.1 specificat ion defines t hat the I D pins have inverti ng sense, and are provided with
internal weak pull ups. Therefore, if no c onnections are made t o the CID0/1 pins, then the pi ns pull
‘hi’ and an ID = 00 is selected, i . e. ‘master’. External connects to ground will select other IDs.

PIN46 CID1 PIN45 CID0 ID SELECTED MASTER OR SLAVE BITCLK

NC NC 00 Master Output

NC Ground 01 Slave Input
Ground NC 10 Slave Input
Ground Ground 11 Slave Input

Table 5 ID Selection

WM9704M supports the AMAP f unction whereby selection of an ID will automatically map the data
from the interface onto the PCM DACs.

CODEC

ID

00 3 4
01 3 4

The codec ID is available to t he controller via registers 28h and 3c, bi ts D15 and D14

Table 6 Default Slot to DAC Mappings Based on Codec ID

AC–LINK FRAME DATA

USED FOR DACS

PCM left DAC uses

data from slot #

PCM right DAC uses

data from slot #

COMMENTS

Original definition (mas ter)
Original definition (docking)

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MODE ID

Rev 2.1

(00)

Table 7 Slot to DAC Mapping Based on Mode and Codec ID

00 or 01 3 and 4

10 7 and 8
11 6 and 9

00 or 01 3 and 4

10 7 and 8Modem (11)
11 6 and 9

SLAVE CODEC REGISTER ACCESS DEFINITIONS

Master Codec access is exactly as defined for AC’97. For slave Codec access, the AC’97 Digital
Controller must invali date the tag bits for Sl ot 1 and 2 Command Address and Data (Slot 0, bits 14
and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0).

Slave Codecs disregard the Com mand Addres s and Com mand Dat a (Slot 0, bits 14 and 13) tag bit s
when they see a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches t heir configuration. In a
sense the Slave Codec ID fi eld funct ions as an al ternative Val id Comm and Addres s (f or Slave reads
and writes) and Command Data (for S l ave writes) tag indicator.

Slave Codecs must monitor the Fram e Valid bit , and ignore the fram e (regardless of t he state of t he
Slave Codec ID bits) if i t is not valid. AC’97 Digital Controllers should set the frame valid bit for a
frame with a slave register acces s , even if no other bi ts in the out put t ag sl ot except t he Slave Codec
ID bits are set.

OUTPUT TAG SLOT (16-BITS)

BIT DESCRIPTION

15
14
13

12-3

2

1-0

New definitions for Slave Codec Register Access

Table 8 Slave Codec Register Access Slot 0-Bit Definitions

Frame Valid
Slot 1 Valid Command Address Bit (Master Codec onl y)
Slot 2 Valid Command Data Bit (Master Codec only)
Slot 3-12 Valid Bits as defined by AC’97
Reserved (Set to 0)
2-bit Codec ID field (00 reserved for Mas t er; 01, 10, 11 indicate Slave)

SLOTS MAPPED TO

FRONT DACS

SLOTS MAPPED TO REAR

DACS

Not supported

in this mode

5

(or 5 & 10 if DLM set)

CONTROL INTERFACE

A digital interface has been provided to cont rol the W M9704M and transfer data to and from i t. This
serial interface is c ompatible with the Intel AC’97 specification as illustrated in the System Diagram
(Figure 7).

The main control interfac e functions are:

• Control of analogue gain and signal paths through the mixer

• Bi-directional transfer of ADC and DAC words to and from AC’97 controll er

• Selection of powerdown modes

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AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL

The WM9704M incorporates a 5-pin digital serial interface t hat l inks it to t he AC’97 c ontroll er. A C-link
is a bi-directional, fi xed rate, serial PCM digital stream. It handl es multiple input and out put audio
streams, as well as control register acc esses employing a t ime division m ultiplexed (TDM) scheme.
The AC-link architecture di vides each audio frame into 12 outgoi ng and 12 incoming data stream s,
each with 20-bit sample resol ution. With a minim um required DAC and ADC resolution of 16-bits,
AC’97 may also be implemented with 18 or 20-bit DAC/ADC resoluti on, given the headroom that the
AC-link architecture provi des. The WM9704M provides support f or 18-bi t operation.

SLOT

NUMBER

0123456789101112

SYNC

CMD

CMD

SDATA_OUT

SDATA_IN

CODEC ID

TAG

STATUS

TAG

SLOTREQ 3-12

ADR

ADDR

STATUS

DATA

DATA

PCM
LEFT

PCM
LEFT

Figure 8 AC’97 Standard Bi-directional Audio Frame

TAG PHASE DATA PHASE

SYNC

12.288MHz

81.4nS

BIT_CLK

PCM

RIGHT

PCM

RIGHT

LINE 1

DAC

LINE 1

ADC

PCM

CENTRE

PCM

L SURR

MIC

RSRVD RSRVD RSRVD

ADC

20.8µS (48kHz)

PCM

R SURR

PCM
LFE

LINE 2

DAC

PCM L

(n+1)

LINE 2

ADC

HSET

DAC

CTRL

PCM C

PCM R

(n+1)

(n+1)

HSET

ADCIOSTATUS

IO

SDATA_OUT

END OF PREVIOUS

AUDIO FRAME

SLOT(1) SLOT(2) SLOT(12)

FRAME

TIME SLOT ’VALID’ BITS

(’1’ = TIME SLOT CONTAINS

VALID PCM DATA)

’0’

(ID1) (ID0)

19 0 19 0 19 0 19 0

SLOT (1) SLOT (2) SLOT (3) SLOT (12)

VALID

Figure 9 AC-link Audio Output Frame

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The datastreams currentl y defined by the AC’97 specificat i on i nclude:

PCM playback - 2 output slots 2-channel composite PCM output stream
PCM record data - 2 input slots 2-channel composite PCM input stream
Control - 2 output slots Control register write port
Status - 2 input slots Control register read port
Optional modem line c odec output -

1 output slot
Optional modem line c odec input -

1 input slot
Optional dedicated mic rophone i nput -

1 input slot

Synchronisation of all AC-link data transactions is signalled by the WM9704M controller. The
WM9704M drives the serial bit clock onto AC-link, which the AC’97 c ontroller then qualifies with a
synchronisation signal t o construct audio frames .

SYNC, fixed at 48kHz, is derived by di viding down the serial clock (BIT _CLK). BIT_CLK, fixed at

12.288MHz, provides the necessary cloc king granularity t o support 12, 20-bit outgoing and incom ing
time slots. AC-link serial data is t ransi tioned on eac h ris ing edge of BIT_CLK . The rec eiver of A C-link
data, (WM9704M for outgoing data and A C’97 controller for incom ing data), samples each serial bit
on the falling edges of BIT_CLK.

The AC-link protocol provides for a special 16-bit tim e slot (slot 0) wherein each bit conveys a valid
tag for its corresponding t im e sl ot within t he current audio f ram e. A “1” in a given bit posit ion of sl ot 0
indicates that the c orresponding t im e s lot within the c urrent audi o fram e has been ass igned to a data
stream, and contains valid dat a. I f a s lot is “tagged” invalid, it is t he respons ibility of the s ource of the
data, (the WM9704M for the input stream, AC’97 controller for the output stream), to stuff all bit
positions with 0s during that slot’s active time.

Modem line codec DAC input stream

Modem line codec ADC output stream
Dedicated microphone input stream in support

of stereo AEC and/or other voice applications.

SYNC remains high for a total duration of 16 BIT_CLKs at t he begi nni ng of each audio frame.
The portion of the audio frame where SYNC is high is def ined as the “Tag Phase”. The rem ainder of

the audio frame where SYNC is low is defi ned as the “Data Phase”. A dditionally, for power savings ,
all clock, sync, and data signal s can be halt ed. This requires that the W M9704M be i mplem ented as
a static design to all ow its register contents to remain intact when entering a power savings m ode.

AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)

The audio output frame data streams correspond t o the mult iplexed bundles of all digit al output data
targeting the WM9704M’s DAC inputs, and control registers. As brief ly ment ioned earlier, each audio
output frame supports up t o 12 20-bit outgoing data t ime sl ots. Slot 0 is a spec ial reserved time slot
containing 16-bits, which are used for AC-link protocol infrastructure.

OUTPUT TAG SLOT (16-BITS)

Bit (15) Fram e Valid
Bit (14) Sl ot 1 Valid Command Addres s bit (Pri mary Codec only)
Bit (13) Sl ot 2 Valid Command Data bi t (Primary Codec only)
Bit (12:3) Slot 3-12 Valid bits as defined by AC’97
Bit 2 Reserved (Set to 0)
Bit (1:0) 2-bit Codec ID field (00 reserved for Primary; 01, 10, 11

New definitions for Secondary Codec Regi ster Access

Within sl ot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags t he validity for the
entire audio frame. If t he “Valid Frame” bit is a 1, thi s indic ates that the current audio frame contai ns
at least one time slot of valid data. The next 12-bit positions sampled by the W M9704M indicate
which of the corresponding 12 tim e slots contain valid data.

indicate Secondary)

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In this way data streams of differing sample rates can be transmitted across AC-link at its fixed
48kHz audio frame rate. Figure 9 illustrates the time slot based AC-link prot ocol.

WM9704M SAMPLES
SYNC ASSERTION HERE

SYNC

WM9704M SAMPLES
FIRST SDATA_OUT
BIT OF FRAME HERE

BIT_CLK

VALID

SLOT (1) SLOT (2)

SDATA_OUT

END OF PREVIOUS AUDIO FRAME

FRAME

Figure 10 Start of an Audio Output Frame

A new audio output frame begins with a low to high trans iti on of SY NC as s hown in Figure 10. SY NC
is synchronous to the rising edge of BIT_CLK . On the im m ediat ely following falling edge of BI T_CLK,
the WM9704M samples the ass ertion of SYNC. This falling edge marks the tim e when both sides of
AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK , AC’97
transitions SDATA_OUT into the first bit posit ion of s lot 0 (“Valid Frame” bit). Each new bit pos it ion is
presented to AC-link on a risi ng edge of BIT_CLK, and subs equently sampled by the W M9704M on
the following falling edge of BIT_CLK. This sequence ensures that dat a transitions and subsequent
sample points for bot h i ncoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a f ixed
48ks/s on the AC’97 control ler.

This requirement is necessary t o ensure that interoperability between the AC’97 controller and the
WM9704M, among other things, can be guaranteed by definition for baseline specified AC’97
features.

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions
stuffed with 0s by the AC’97 controller.

In the event that there are less than 20 valid bits within an assigned and val id time slot, the AC’97
controller always stuffs al l trailing non-valid bit positions of the 20-bit slot with 0s.

As an example, consider an 8-bit s ample stream that is being played out to one of the W M9704M’s
DACs. The first 8 bit pos itions are presented to t he DAC (MSB justified) f ollowed by the next 12 bit
positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the
resolution of the implement ed DAC (16, 18 or 20-bit), no DC biasing will be introduced by the leas t
significant bits .

When mono audio s ample streams are output from the AC’97 controll er, it is necessary that BOTH
left and right sample stream time slots be filled with the same data.

SLOT 1: COMMAND ADDRESS PORT

The command port is us ed to cont rol features , and moni tor stat us (see Figure 12) f or the W M9704M
functions including, but not limited to, m ixer settings, and power management (refer to t he register
section). The control int erfac e archi tec ture s upports up to 64, 16-bit read/write regis ters , address able
on even byte boundaries. Only the even registers (00h, 02h, etc.) are val id, odd register (01h, 03h,
etc.) accesses are discouraged (if supported they should default to the preceding even byte
boundary - i.e. a read to 01h will return the 16-bit contents of 00h). The WM9704M’s c ontrol regis ter
file is nonetheless readable as well as writeable to provide more robust tes t abilit y.

Audio output frame slot 1 communicates control register address, and read/write command
information to the WM9704M.

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COMMAND ADDRESS PORT BIT ASSIGNMENTS

Bit (19) Read/write command (1 = read, 0 = write)
Bit (18:12) Control register index (64 16-bit locat i ons, addressed on even

Bit (11:0) Reserved (stuffed with 0s)

The first bit (MSB) sampl ed by the WM9704M indicates whether the current control transac tion is a
read or write operation. The following 7 bit positions communicate the targeted control register
address. The trailing 12 bit positions within the slot are reserved and must be st uffed with 0s by the
AC’97 controller.

SLOT 2: COMMAND DATA PORT

The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle. (As indi cated by slot 1, bit 19).

byte boundaries)

Bit (19:4) Control register write data (stuffed with 0s if current operation is

Bit (3:0) Reserved (stuffed with 0s)

If the current command port operation is a read then the entire t ime slot mus t be stuffed with 0s by
the AC’97 controller.

a read)

SLOT 3: PCM PLAYBACK LEFT CHANNEL

Audio output frame slot 3 is the composite digital audio lef t playback stream. In a typical ‘Games
Compatible’ PC this slot is compos ed of st andard PCM (.wav) output sam ples di gitally m ixed (on the
AC’97 controller or host processor) with music synthesis output samples. If a sample stream of
resolution less than 20-bits is transferred, the AC’97 controller must stuff all trailing non-valid bit
positions within this time slot with 0s.

SLOT 4: PCM PLAYBACK RIGHT CHANNEL

Audio output frame slot 4 is the composite digi tal audio right playback stream. In a typical ‘Games
Compatible’ PC this slot is compos ed of st andard PCM (.wav) output sam ples di gitally m ixed (on the
AC’97 controller or host processor) with music synthesis output samples.

If a sample stream of resolution less than 20-bit s is transferred, t he AC’97 controller must st uff all
trailing non-valid bit positi ons within this time s l ot with 0s.

SLOT 5: OPTIONAL MODEM LINE 1 CODEC

Audio output frame slot 5 contains the MSB justified modem line1 DAC input data. This optional
AC’97 feature is supported in WM9704M, but only in the m odem operation mode (sel ected with the
mode0/1 pins). If dat a is written to this location it is applied to the rear channel DA Cs if t he modem
mode is enabled. This may be determined by the AC’97 controller interrogating the WM9704M
Vendor ID registers; if modem mode is disabled, the device appears not to support modem . If the
mode is enabled, the m odem support flag is set .

SLOTS 6 TO 9: SURROUND SOUND DATA

Audio output frame slots 6 to 9 are used to send surround sound data to extra DAC channels. These
slots are supported by W M9704M in Revision 2.1 and modem modes. Note that the data in the
surround sound slots will only be applied to the front DAC. The slots used depend on t he Codec I D
configuration (see Table 7).

SLOT 10: OPTIONAL MODEM LINE2 CODEC

Audio output frame slot 10 cont ains MSB jus ti fied m odem Li ne2 DAC input data. Thi s opti onal AC’97
feature is supported by WM9704M, but only when register 5Ah DLM (Dual line modem) is set.

SLOT 11: HANDSET DAC

Slot 11 is not supported.

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SLOT 12 : GPIO CONTROL

Data in this slot is applied to the GPIO pins, if they have been enabled via the control regis ters.
Note that only bits 11, 12 and 13 are s upport ed, all others are ignored.

AC-LINK AUDIO INPUT FRAME (SDATA_IN)

TAG PHASE DATA PHASE

20.8µS (48kHz)

SYNC

BIT_CLK

SDATA_IN

END OF PREVIOUS

AUDIO FRAME

Figure 11 AC-link Audio Input Frame

12.288MHz

81.4nS

CODEC

SLOT(1) SLOT(2) SLOT(12)

READY

(’1’ = TIME SLOT CONTAINS

’0’ ’0’ ’0’ 19 0 19 0 19 0 19 0

TIME SLOT ’VALID’ BITS

VALID PCM DATA)

SLOT (1) SLOT (2) SLOT (3) SLOT (12)

The audio input frame data stream s correspond to the multiplexed bundles of all digital input data
targeting the AC’97 controller. As is the c ase for audio output frame, eac h AC-link audio input frame
consists of 12, 20-bi t time slots.

Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol
infrastructure.

Within slot 0 the first bit is a global bi t (SDATA_IN s lot 0, bit 15) which f lags whether the W M9704M
is in the “Codec Ready” state or not. If the “Codec Ready” bit is a 0, t his indic ates that the WM9704M
is not ready for normal operation. This condition is norm al following the desertion of power on reset
for example, while the WM9704M’s voltage references settle. When the AC-link “Codec Ready”
indicator bit is a 1, it indicates that the AC-l ink and the W M9704M control and st atus regist ers are in
a fully operational state. The AC’97 controller must further probe the Powerdown Control/Status
Register to determine exactl y which subsections, if any, are ready.

Prior to any attempts at put ting t he WM9704M into operation the AC’97 control ler should poll the firs t
bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indi cation that the W M9704M has gone
“Codec Ready”.

Once the WM9704M is sampl ed “Codec Ready” then the next 12 bit pos itions sam pled by the AC’97
controller indicate which of t he corresponding 12 tim e slots are assi gned to input data st reams, and
that they contain valid data. Figure 11 illustrates the time slot based AC-link protocol.

There are several subsections withi n the WM9704M that can independent ly go busy/ready. It is the
responsibility of the WM9704M controller to probe more deeply into the W M9704M register file to
determine which the WM9704M subsections are actually ready.

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WM9704M SAMPLES
SYNC ASSERTION HERE

SYNC

AC’97 CONTROLLER
SAMPLES FIRST SDATA_IN
BIT OF FRAME HERE

BIT_CLK

CODEC

SLOT (1) SLOT (2)

SDATA_IN

END OF PREVIOUS AUDIO FRAME

READY

Figure 12 Start of an Audio Input Frame

A new audio input frame begins with a low to high transi tion of SY NC as s hown in Figure 12. SYNC
is synchronous to the rising edge of BIT_CLK . On the im m ediat ely following falling edge of BI T_CLK,
AC’97 samples the assertion of SYNC. This falling edge mark s the tim e when both sides of A C-link
are aware of the start of a new audio frame. On the next rising of BIT_CLK, AC’97 transitions
SDATA_IN into the firs t bit pos ition of slot 0 (“Codec Ready” bit ). Each new bit pos ition is presented
to AC-link on a rising edge of BI T_CLK, and subsequently sampl ed by the AC’97 Controller on the
following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent
sample points for bot h i ncoming and outgoing data streams are time aligned.

SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0s by the WM9704M. SDATA_IN should be
sampled on the falling edges of BIT_CLK.

SLOT 1: STATUS ADDRESS PORT

The status port is used t o monitor status for the W M9704M functions including, but not l imited to,
mixer settings, and power management.

Audio input frame slot 1 echoes the control register index, for historical reference, for the data to
be returned in slot 2. (Ass uming that s lots 1 and 2 had been tagged “valid” by the W M9704M during
slot 0).

STATUS ADDRESS PORT BIT ASSIGNMENTS:

Bit (19) RESERVED (stuffed with 0s)
Bit (18:12) Control register index (echo of register index for which data is

being returned)
Bit (11:2) Variable sample rate SLOTREQ bits.
Bit (1:0) RESERVED (stuffed with 0s)

The first bit (MSB) generated by the WM9704M is always stuffed with a 0. The following 7 bit
positions communi cate the associated control register address. The next 10 bits support the AC’97
Rev 2.1 variable sample rate signalling protocol, and t he trailing 2 bit posit ions are stuf fed with 0s by
AC’97.

SLOT 2: STATUS DATA PORT

The status data port delivers 16-bi t control register read data.

Bit (19:4) Control register read data (stuffed with 0s if tagged “invalid” by

Bit (3:0) RESERVED (stuffed with 0s)

If slot 2 is tagged “invalid” by the WM9704M, then the entire slot will be stuffed with 0s by the
WM9704M.

WM9704M)

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SLOT 3: PCM RECORD LEFT CHANNEL

Audio input frame slot 3 i s the left channel output of the WM9704M’s input Mux, post-ADC.
The WM9704M’s ADCs can be im plement ed to support 16, 18, or 20-bit resoluti on. The WM9704M

ships out its ADC output data (MSB f irst), and stuff s any trailing non-valid bit positions with 0s to fill
out its 20-bit tim e slot.

SLOT 4: PCM RECORD RIGHT CHANNEL

Audio input frame slot 4 i s the right channel output of the WM9704M’s input Mux, post-ADC.
The WM9704M’s ADCs can be implemented to support 16, 18, or 20-bit resolution.
The WM9704M ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit

positions with 0s to fill out its 20-bit time slot.

SLOT 5: OPTIONAL MODEM LINE 1 CODEC

Audio input frame slot 5 contains MSB justified, modem A DC output data. When the device is in
Modem Mode (11), then right channel ADC data is output into this slot as well as onto the norm al
PCM right channel slot.

SLOT 10: OPTIONAL MODEM LINE 2 CODEC

Audio input frame slot 10 contains MSB just ified, modem ADC output data. When the device is in
Modem Mode (11), then left channel ADC dat a i s output into this slot as well as onto the normal PCM
left channel slot.

SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA

Audio input frame slot 6 is an optional (post-ADC) third PCM system, input channel available for
dedicated use by a desktop microphone. This optional AC’97 feature is not supported by the
WM9704M. This may be det ermined by the AC’97 cont roller interrogating the W M9704M Vendor ID
register.

SLOTS 7 TO 11: RESERVED

Audio input frame slots 7 to 12 are reserved for future use and are always s tuffed with 0s by AC ‘97.
Slot 10 is filled with lef t ADC data in modem mode.

SLOT 12:

GPIO functions support ed

AC-LINK LOW POWER MODE

The AC-link signals can be placed in a low power mode. When the WM9704M’s Powerdown Register
(26h), is programmed to the appropriat e value, both BIT_CLK and SDATA_I N will be brought to, and
held at a logic low voltage level.

BIT_CLK and SDATA_IN are trans itioned low immediately following the decode of t he write to the
Powerdown Register (26h) with PR4. When the AC’97 controller driver is at the point where it is
ready to program the AC-link int o it s l ow power mode, slot s 1 and 2 are as s um ed to be the only valid
stream in the audio output f rame. At this point in time it is as sumed that al l sources of audi o input
have also been neutralised.

The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the
WM9704M to this low power, “halted” mode.

Once the WM9704M has been inst ructed to halt BIT_CLK, a spec ial “wake up” protocol m ust be
used to bring the AC-link to t he active m ode since norm al audio output and input frames can not be
communicated i n the absence of BIT_CLK.

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WAKING UP THE AC-LINK

There are 2 methods for bringing the AC-link out of a low power, halted mode. Regardless of the
method, it is the AC’97 controller that perform s the wake up task.

AC-link protocol provides f or a “Cold WM9704M Reset”, and a “W a rm WM9704M Reset”.
The current powerdown state would ultimately dict ate which form of W M9704M reset is appropriate.

Unless a “cold” or “register” reset (a write to the Reset register) is performed, wherein the WM9704M
registers are initialised to their default values, registers are required to keep state during all
powerdown modes.

Once powered down, re-activation of the AC-link via re-ass ertion of the S YNC signal m ust not oc cur
for a minimum of 4 audio frame ti mes following the frame in which the powerdown was triggered.
When AC-link powers up it i ndi cates readiness via the Codec Ready bi t (input slot 0, bit 15).

COLD WM9704M RESET

A cold reset is achieved by asserting RESETB for the minimum specified time. By driving RESETB
low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and all the
WM9704M control registers will be initialised to their default power on reset values.

RESETB is an asynchronous WM9704M input.

WARM WM9704M RESET

A warm WM9704M reset will re-activate the AC-link without altering the current W M9704M register
values. A warm reset is signalled by driving SYNC high for a m inimum of 1µs in the absence of
BIT_CLK.

Within norm al audio frames SYNC is a synchronous input. I n the absence of BIT_CLK, SYNC is
treated as an asynchronous input used in the generation of a warm reset to t he WM9704M. The
WM9704M will not respond with the activation of BI T_CLK until SYNC has been s ampled low again
by the WM9704M. This will preclude the false detec t i on of a new audio frame.

SERIAL INTERFACE REGISTER MAP DESCRIPTION

(See Table 22)

The serial interface bits perform cont rol functions described as f ollows: Note that the register m ap is
fully specified by the AC’97 s pecif ication, and this des cripti on is si mply repeat ed below, with opt ional
unsupported features omit ted.

RESET REGISTER (INDEX 00H)

Writing any value to t hi s register performs a register reset, which causes al l registers to revert to their
default values. Reading this register returns the ID code of t he part, indic at ion of m odem s upport (not
supported by the WM9704M) and a code for the type of 3D stereo enhancement.

BIT FUNCTION

ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9

SE4...SE0

Table 9 Reset Register Function

Dedicated Mic PCM in channel
Modem line codec support
Bass and treble control
Simulated stereo (mono to stereo)
Headphone out support
Loudness (bass boost) support
18-bit DAC resolution
20-bit DAC resolution
18-bit ADC resolution
20-bit ADC resolution
3D stereo enhancement tec hni que

VALUE ON

WM9704M

0
0
0
0
0
0
1
0
1
0

11000

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Note that the WM9704M defaults t o indicat e 18-bit com pat ibility. However, a control bit m ay be set in
the vendor-specific regist ers that changes bits ID6 and ID8 to be ‘0’, indicati ng a 16-bit device. It is
unlikely that this function will be required, however, as the MSB justification of the ADC and DA C
data means that a nominally 18-bit device should be fully compatible with controllers that only
provide 16-bit support. Most PC type applications will only require 16-bit operation.

PLAY MASTER VOLUME REGISTERS (INDEX 02H, 04H AND 06H)

These registers manage the output si gnal volumes. Regi ster 02h controls t he stereo mast er volume
(both right and left channels), Register 04h c ontrols t he optional s tereo headphone out, and Regis ter
06h controls the mono volume output. Each step c orresponds to 1.5dB. The MSB of the regi ster is
the mute bit. When this bit is set to 1 the level for that c hannel i s set at -

ML5 through ML0 is for left channel level, ML5 through ML0 is for t he right c hannel and MM5 through
MM0 is for the mono out channel.

Support for the MSB of the volume level is not provided by the W M9704M. If the MSB is writt en to,
then the WM9704M detects when that bit is set and sets all 4 LSBs t o 1s. Example: If the driver
write s a 1xxxxx th e W M 9704M interprets that as x11111. It will also respond when read with x11111
rather than 1xxxxx, the value writt en to i t. Th e driv er ca n use this fea ture to de tec t if support for the
6th bit is there or not.

The default value of both the mono and the s tereo registers i s 8000h (1000 0000 0000 0000), which
corresponds to 0dB gain with mut e on.

MUTE MX4...MX0 FUNCTION

0 0 0000
0 0 0001
0 1 1111
1 x xxxx

Table 10 Volume Register Function

0dB attenuation

1.5dB attenuation

46.5dB attenuation

∞dB attenuation

∞dB.

MASTER TONE CONTROL REGISTERS (INDEX 08H)

Optional register for support of tone controls (bass and treble). The WM9704M does not support
bass and treble and writing to this register will have no effect, reading will res ult in all don’t care
values.

PC BEEP REGISTER (INDEX 0AH)

This controls the level for the PC-beep input. Each step corresponds to approximately 3dB of
attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that

channel is set at -∞dB.

WM9704M defaults to the PC-beep path being mut ed, except during res et when the path is open, so
an external speaker should be provided within the PC to alert the user to power on self-test
problems.

MUTE PV3...PV0 FUNCTION

0 0000
0 1111
1 xxxx

Table 11 PC-beep Register Function

0dB attenuation
45dB attenuation

∞dB attenuation

ANALOGUE MIXER INPUT GAIN REGISTERS (INDEX 0CH - 18H)

This controls the gain/attenuation for each of the analogue inputs. Each step corresponds to
approximately 1.5dB. The MSB of the regi ster is the mut e bit. When t his bit is set to 1 the level for
that channel is set at -

∞dB. (See Table 12).

REGISTER 0EH (MIC VOLUME REGISTER)

This has an extra bit that is for a 20dB boost. When bit 6 is set t o 1 the 20dB boost is on. The defaul t
value is 8008, which corresponds to 0dB gai n with mute on.

The default value for the mono regis ters is 8008h, which corres ponds to 0dB gain with mut e on. The
default value for stereo registers is 8808h, which corresponds to 0dB gain with mute on.

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WM9704M Production Data

MUTE GX4...GX0 FUNCTION

0 00000
0 01000
0 11111
1 xxxxx

Table 12 Mixer Gain Control Register Function

RECORD SELECT CONTROL REGISTER (INDEX 1AH)

Used to select the record source independently for right and left (see Table 13). The default value is
0000h, which corresponds to Mic in.

SR2 TO SR0 RIGHT RECORD SOURCE SL2 TO SL0 LEFT RECORD SOURCE

0
1
2
3
4
5
6
7

Table 13 Record Select Register Function

Mic
CD in (R)
Video in (R)
Aux in (R)
Line in (R)
Stereo mix (R)
Mono mix
Phone

+12dB gain
0dB gain

-34.5dB gain

-

∞dB gain

0
1
2
3
4
5
6
7

Mic
CD in (L)
Video in (L)
Aux in (L)
Line in (L)
Stereo mix (L)
Mono mix
Phone

RECORD GAIN REGISTERS (INDEX 1CH AND 1EH)

1Ch is for the stereo input and 1Eh i s for the optional special purpos e correlated audio Mic channel .
Each step corresponds to 1. 5dB. 22.5dB corres ponds t o 0F0Fh and 000Fh respec ti vely. The MSB of
the register is the m ute bit. When thi s bit is set to 1, t he l evel f or that channel(s) is set at -

The default value is 8000h, which corresponds to 0dB gain with mute on.

MUTE GX3...GX0 FUNCTION

0
0
1

Table 14 Record Gain Register Function

1111 +22.5dB gain
0000 0dB gain
xxxxx -

∞dB gain

∞dB.

GENERAL PURPOSE REGISTER (INDEX 20H)

This register is used to control several misc el l aneous functions of the WM9704M.
Below is a summary of each bit and its function. Only the MIX, MS and LPBK bits are supported by

the WM9704M. The MS bit controls the Mic selector. The LPBK bit enables loopback of the ADC
output to the DAC input without involving the AC-link, allowing for full system performance
measurements. The f unction default value is 8000h, which is all off.

BIT FUNCTION

POP

ST
3D
LD

LLBK

RLBK

MIX

MS

LPBK

Table 15 General Purpose Register Function

PCM out path and mute, 0 = pre-3D, 1 = post -3D Yes, but fixed at ‘1’
Simulated stereo enhancement, on/off 1 = on No
3D stereo enhancement on/off, 1 = on Yes
Loudness (bass boost) on/off, 1 = on No
Local loop back - for modem, line codec No
Remote loop back - for modem, line codec No
Mono output select 0 = Mix, 1 = Mic Yes
Mic select 0 = Mic1, 1 = Mic2 Yes
ADC/DAC loopback mode Yes

WM9704M

SUPPORT

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3D CONTROL REGISTER (INDEX 22H)

This register is used to control the c entre and/or depth of the 3D stereo enhancem ent function built
into of the AC ‘97 component. Only the depth bits DP0 to 3 have eff ect in the WM9704M.

DP3…DP0 DEPTH

00%
1

­8 Typical value

-

15 100%

RESERVED REGISTER (INDEX 24H)

This register was originally specified to control what sample rate AC’97 is sending or receiving
samples for the opti onal modem in and out. Not supported by the WM9704M.

POWERDOWN CONTROL/STATUS REGISTER (INDEX 26H)

This read/write register is used t o program powerdown states and m oni tor s ubsys tem readi ness . The
lower half of this register is read only status, a 1 indicating that the subsec tion is “ready”. Ready is
defined as the subsecti on able to perform in its nominal state. W hen this register i s written the bit
values that come in on AC-link will have no effect on read only bits 0 to 7.

When the AC-link “Codec Ready” indicator bit (SDATA_IN sl ot 0, bit 15) is a 1 it indicates that the
AC-link and the W M9704M control and status registers are in a fully operational state. The AC’97
controller must further probe this Powerdown Control/Status Register to determine exactly which
subsections, if any, are ready.

READ BIT FUNCTION

REF
ANL
DAC
ADC

Table 16 Powerdown Status Register Function

The powerdown modes are as follows. The first three bi ts are to be used individually rather than i n
combination with each other. The l ast bit PR3 can be used in combination with PR2 or by itself. PR0
and PR1 control the PCM ADCs and DACs onl y. PR6 is not supported by the WM9704M.

WRITE BIT FUNCTION

PR0
PR1
PR2

PR3
PR4

PR5
PR6

EAPD

Table 17 Powerdown Control Register Function

VREFs up to nominal level
Analogue mixers, etc ready
DAC section ready to acc ept data
ADC section ready to transmit data

PCM in ADCs and input Mux powerdown
PCM out DACs powerdown
Analogue mixer powerdown (VREF still

on)
Analogue mixer powerdown (VREF off)
Digital interface (AC-link) powerdown

(external clock off)
Internal clock disabl e
HP amp powerdown – not supported
External amplifier powerdown

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NORMAL

PR0 = 1

PR0 = 0 AND

ADC = 1

ADCs OFF

READY = 1

PR1 = 1 PR2 = 1 PR4 = 1

DAC = 1

DACs OFF

PR1

PR2 = 0 AND

ANL = 1

DEFAULT

PR0

PR1 = 0 AND

ANALOGUE

OFF PR2 OR

PR3

DIGITAL I/F

OFF PR4

WARM

RESET

COLD RESET

SHUT OFF

CODA LINK

Figure 13 An Example of the WM9704M Powerdown/Powerup Flow

Figure 13 illustrates one example procedure to do a com plete powerdown of the WM9704M. From
normal operation sequential writes to the Powerdown Register are performed to powerdown the
WM9704M a piece at a time. After everything has been shut off (P R0 to PR3 set), a final write (of
PR4) can be executed to shut down the W M9704M’s di gi tal interface (AC-link).

The part will remain in sleep mode with all its registers holding t heir static values. To wake up the
WM9704M, the AC’97 controller will send a pulse on the sync line issuing a warm reset. This will
restart the W M9704M’s digital interface (resetti ng PR4 to 0). The WM9704M can also be woken up
with a cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them
to their default states. When a section is powered back on, the Powerdown Control/Status register
(index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any
operation that requires it.

Alternatively if RESETB is held low, all PR bits are held set so the device is held powered off until
RESETB is taken high again.

ADCs OFF

PR0

PR1 = 1

PR1 = 0

AND

DAC = 1

DACs OFF

PR2 = 1 PR4 = 1

ANALOGUE

PR1

PR2 = 0 AND

OFF PR2 OR

ANL = 1

PR3

DIGITAL I/F

OFF PR4

WARM RESET

SHUT OFF

CODA LINK

Figure 14 The WM9704M Powerdown/Flow w i th Analogue Still Alive

Figure 14 illustrates a state when all the mixers should work with the s tatic volume s ettings that are
contained in their associated registers. This is used when the user c ould be pl aying a CD (or external
LINE_IN source) through WM9704M to the speakers but have most of the system in low power
mode. The procedure for this f ollows the previous except that the analogue m i xer is never shut down.

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POWERDOWN CONTROL/STATUS REGISTER (INDEX 26H)

Note that in order to go into ultim ate low power mode, PR5 is required to be s et which turns
off the oscillator circuit . Assert ing SYNC resets t he PR5 bit and re-starts the os cillator in the
same was as the AC link i s restarted.

Also when RESETB pin is asserted low, all PR bits are over-ridden and the entire device is
powered off to ultra low power state for as long as RESETB = low. On releasing RESETB,
the device is reset (all active) and powered up.

REV 2.1 REGISTERS (INDEX 28H T0 58H)

These registers are specif ied as to use in Rev 2.1 of the AC’97 specifi cation and have the following
functions on the WM9704M:

REGISTER 28H – EXTENDED AUDIO ID

The Extended Audio ID register is a read only register that identifies which extended audio features
are supported (in addition to the original AC’97 features identified by reading the res et register at
index 00h). A non-zero value indicates the feat ure i s supported.

DATA BIT FUNCTION VALUE

VRA
DRA

VRM
CDAC
SDAC
LDAC

AMAP

ID1
ID0

Table 18 Extended Audio Capability Register

Variable rate audio support
Double rate audio support
Variable rate Mic ADC support
Centre DAC support
Surround DAC support
LFE DAC support
Slot to front DAC m appi ng support
Codec configuration – pin 45 value
Codec configuration – pin 46 value

1
0
0

0
0 (unless I2S = 1)
0 (unless I2S = 1)

1

Inverse of level at pin 45
Inverse of level at pin 46

REGISTER 2AH - EXTENDED AUDIO STATUS AND CONTROL REGISTER

The Extended Audio Status and Control Regis ter is a read/write register that provides status and
control of the extended audio features.

DATA BIT FUNCTION READ/WRITE WM9704M SUPPORT

VRA
DRA

VRM
CDAC
SDAC

LDAC

MADC

PRI
PRJ
PRK
PRL

Table 19 Extended Audio Status and Control Register

Enables variable rate audio mode
Enable double rate audio mode
Enables variable rate Mic ADC
Indicates centre DAC ready
Indicates surround DAC ready
Indicates LFE DAC ready
Indicates Mic ADC ready
Set to turn off centre DAC
Set to turn off surround DA Cs
Set to turn off LFE DACs
Set to turn off Mic ADC

Read/write Yes
Read/write No
Read/write No

Read Yes
Read Yes
Read Yes

Read No
Read/write Enable only
Read/write Enable only
Read/write Enable only
Read/write No

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REGISTER 2CH TO 32H – AUDIO SAMPLE RATE CONTROL REGISTERS

These registers are read/write registers that are written t o, to select alternat ive sample rates for t he
audio PCM converters. Default is the 48ks/s rate. Note that only Rev 2.1 recommended rates are
supported by the WM9704M, selection of any other unsupported rates will cause the rate to default to
the nearest supported rate, and the supported rate value to be latched and so read bac k.

Register 2Ch is the front DAC rate register, but is als o used for centre channel data rate.

MODEM REGISTERS (INDEX 3CH TO 56H)

The contents of these regis ters control modem function.

REGISTER 3CH – EXTENDED MODEM ID

The extended modem ID is a read/write regis ter that primarily identif i es the enhanced codecs modem
AFE capabilities. The default value will depend on features and hardware configuration. Writing any
value to this register perform s a warm modem AFE reset (regi ster range 3C-56h), including GP IO
(register range 4C-54h). The warm reset causes all af fec ted regis ters to revert to t heir def ault val ues.
Note: for AMC ’97 parts the audio and modem AFE should be logically independent (writes to
register 0h resets audio only).

• LIN1 = 1 indi cates 1st line is s upport ed – set when WM9704M is in Modem mode 1 = 1

• LIN2 = 1 indi cates 2nd line is supported – supported on WM9704M when DLM is set

• HSE T = 1 i ndi cates handset DAC/ADC is supported – not supported on WM9704M

• CID1 = 1 indi cates that caller ID dec ode for line 1 is supported – not supported on WM9704M

• CID2 = 1 indi cates that caller ID dec ode for line 2 is supported – not supported on WM9704M

• ID1, ID0 is a 2-bit field which indicates the Codec configuration: Primary is 00; Secondary is

01, 10, or 11

REGISTER 3EH – EXTENDED MODEM STATUS/CONTROL

The Extended Modem Status and Control register functi ons similarly to the original AC’97 Power­down Control/Status register, located at index 26h. The (A)MC ’97 Codec m ust restrict m odem and
handset power-down control/status to this register since all of the functions are provided here.
Therefore, the (A)MC’97 Codec (and AC’97 Digit al Controller, of course) m ust ignore bits MDM and
PR7 in register 26h and use what is included here. When the GPIO section is powered down, all
outputs must be t ri-stated and input slot 12 should be marked inval id when the AC-link is active.
When slot 12 is invalid, regist er 54h (GPIO Pin Stat us Register) will report 0s. I n addition the Codec
should force SDATA_IN slot 12 to all 0s. Bits 7 to 0 are read only, 1 indicates modem AFE
subsystem readines s:

• GPI O = 1 i ndi cates GPIO ready

• MREF = 1 indicates Modem VREFs up to nominal level

• ADC1 = 1 indi cates Modem Line1 ADC ready

• DAC1 = 1 indi cates Modem Line1 DAC ready

• ADC2 = 1 indi cates Modem Line2 ADC ready – supported on WM9704M when in DLM is set

• DAC2 = 1 indi cates Modem Line2 DAC ready –supported on WM9704M when DLM is set

• HADC = 1 indicates Handset ADC ready – not supported on WM9704M

• HDAC = 1 indicates Handset DAC ready – not supported on WM9704M

Bits 15 to 8 are read/write and control modem AFE subsystem power-down. WM9704M
powerup/down functions are entirely controlled f rom register 26h. However, the following regis ters
are aliased onto the appropriate control bi t s in registers 26h.

• PRA = 1 i ndi cates GPIO power-down

• PRB = 1 i ndi cates Modem VREF off - no s eparate modem VREF on WM9704M, aliases

from PR3

• PRC = 1 indi cates Modem Line 1 ADC off – aliases from PR0

• PRD = 1 indi cates Modem Line 1 DAC off - ali ases from PR1

• PRE = 1 i ndicates Modem Line 2 ADC off – not supported on WM9704M

• PRF = 1 indi cates Modem Line 2 DAC off – not supported on WM9704M

• PRG = 1 indi cates Handset ADC off – not s upport ed on WM9704M

• PRH = 1 indicates Handset DAC off – not supported on WM9704M

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

30

Production Data WM9704M

Bits 7 to 0 are read only, 1 indicates modem AFE s ubsystem readines s. Bits 15 to 8 are read/write
and control modem AFE subsystem power-down. W riting ENA BLES (0) t o the above alias ed PR bits
is allowed and will write enable to appropriate PRN bit. However, writing DISABLES (1) is not
allowed.

REGISTER 40H – LINE1 ADC/DAC SAMPLE RATE

This read/write register 40h controls the modem DAC and A DC sample rate. This register is only
functional if Modem mode 1 = 1 is s elected from pins 30 and 40. The ADC will only use this s ample
rate if in addition, the input to the Rec ord Mux is selected, as Ri ght ADC is PHONE in regis ter 1Ah.
Note only the recommended s am ple rat es are s upported. If al ternat ive s am ple rat es are sel ect ed t he
rate will default to the nearest sample rate s upported, and that value will be read back.

REGISTER 46H TO 48H – LINE1 AND 2 DAC/ADC LEVEL

These registers are not supported i n WM9704M, register 04h being used to c ontrol TX modem level.

REGISTER 56H – MISCELLANEOUS MODEM AFE STATUS/CONTROL

This read/write register defines the loop back modes available for the modem line and handset
ADCs/DACs described in the Intel Specificat i on. Line1 ADC loopback mode 001 L1B0 is supported.

GPIO FUNCTION

Note that only the three GPIO pins are supported, GPIO 11 to 13.

REGISTER 4CH – GPIO PIN CONFIGURATION REGISTER

The GPIO Pin Configuration is a read/write register t hat specifies whether a GPI O pin is configured
for input (1) or for output (0), and is ac cessed via the s tandard slot 1 and 2 com mand address /data
protocols.

If a GPIO pin is im plemented, the respecti ve GCx bit s houl d be read/writeable and set to 1. If a GPIO
is not implement ed, then the respect ive GCx bit is read-only and set to 0. This informs the software
how many GPIO pins have been implem ented. It is up to t he AC’97 Digital Controller to send the
desired GPIO pin value over output sl ot 12 in the outgoing stream of the AC-link before conf iguring
any of these bits for output. The default value after cold or register res et for t his regis ter (3800h) is all
pins configured as inputs.

REGISTER 4EH – GPIO PINS POLARITY/TYPE

The GPIO Pin Polarity/Type is a read/write register that defines GPIO Input Polarity (0 = Low,
1 = High active) when a GPIO pin is configured as an Input. It defines GPIO Output Type
(1 = CMOS, 0 = OPEN-DRAIN) when a GPIO pin is conf i gured as an Output.

The default value after cold or register reset for this register (FFFFh) is all pins active high.
Non-implemented GPI O pi ns always return 1s.

REGISTER 50H – GPIO PIN STICKY CONTROL

The GPIO Pin Sticky is a read/write register that defines GPIO Input Type (0 = Non-sticky,
1 = Sticky) when a GPIO pin is conf igured as an input. GP IO input s c onfigured as s ti ck y are c leared
by writing a 0 to the corresponding bit of t he GPIO pin status regist er 54h (see below), and by reset.

The default value after cold or register reset for this register (0000h) is all pins Non-sticky.
Unimplemented GPI O pins al ways return 0s . S tic ky i s def ined as edge-s ens iti ve, Non-st ic ky as level
sensitive.

REGISTER 52H – GPIO PIN WAKE-UP CONTROL

The GPIO Pin Wake-up is a read/ write regist er that provides a m ask for det erm ining i f an input GPI O
change will generate a wake-up or GPIO_INT (0 = No, 1 = Yes). W hen t he AC-Link is powered down
(Register 26h PR4 = 1 for primary codecs), a wake-up event will trigger the assertion of SDATA_I N.
When AC-link is powered up, a wake-up event will appear as GPIO_INT = 1 on bit 0 of input slot 12.
GPIO_INT is also flagged when the link is active.

An AC-link wake-up Interrupt is defined as a 0 to 1 transition on SDATA_IN when the AC-Link is
powered down (Register 26h PR4 = 1). GPIO bits that have been program med as i nputs, s ticky and
pin wake-up, upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause
an AC-link wake-up event (transition of SDATA_IN from 0 to 1), if and only if the AC-link was
powered down.

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

31

WM9704M Production Data

The default value after cold or register reset for this regis ter (0000h) defaults to all 0s specifying no
wake-up event. Non-implemented GPIO pins always return 0s.

REGISTER 54H – GPIO PIN STATUS

The GPIO status is a read/write register that reflects the s tate of all GPIO pins (inputs and outputs)
on slot 12. The value of all GPIO pin inputs and outputs com es i n from t he codec every fram e on s lot
12, but is also available for readi ng as GPIO Pin Status via the st andard slot 1 and 2 comm and
address/data protocols. GPIO inputs configured as Sticky are cleared by writing a 0 to the
corresponding bit of this regi ster 54h.

Bits corresponding to unim plemented GPIO pins s hould be forced to zero in this register and input
slot 12. GPIO bits that have been programmed as Input s and Sticky, upon transit ion either (high-to
low) or (low-to-high) depending on pin polarity, will cause the individual GPIO bit to go ass erted 1,
and remain asserted until a write of 0 to that bit. The normal way to set t he desired value of a GPI O
output pin is to set the control bit in output slot 12.

The default value, if configured as an i nput, after cold or regi ster reset for thi s register is al ways the
state of the GPIO pin.

REGISTER 56H – MISCELLANEOUS MODEM AFE STATUS/CONTROL

This read/write register defines the loopback modes available for the modem line and handset
ADCs/DACs described in the Intel Specificat i on. Line1 ADC loopback mode 001 L1B0 is supported.

VENDOR RESERVED REGISTERS (INDEX 5AH AND 7AH)

These registers are vendor specif ic . Do not write t o thes e regis ters unles s t he Vendor ID regi st er has
been checked first to ensure that the driver knows the source of the AC‘97 component. Values st ored
in this register are used to provide vendor specific modes for the manufacturer.

BIT NAME DEFAULT ACTION WHEN SET TO 1

Test only bits – not normal use

AEV

BB

TRM

HIC

HIM

DDS

RTS
DFT
AFT
DTS
ATS

User bits

AND

R2S

I2S

DLM
ADS

Table 20 Vendor Register 5Ah Bit Allocation and Default States

ADC evaluation
BIASBOOST
TSTRECMUX

HALFICONV
MALFIMIX
Dither disable
RAM test mode
DAC FIT test
ADC FIR test
DAC test
ADC test

ADC no DAC

Rev 2.1 switch

2

S enable

I

Dual line modem
Automute disable

0
0
0

0
0
0
0
0
0
0
0

0

0
0

0
0

ADC evaluation mode selec t bit – do not use
Increases analogue bias current s by 50%
Enables record mux test mode; RECMUX outputs

summed into the front and rear DAC output path.
Halves to bias current to t he converters
Halves bias current to the mixer block
Disables ADC and DAC digital di ther – do not use
Digital test m ode – do not use
Digital test m ode – do not use
Digital test m ode – do not use
Digital test m ode – do not use
Digital test m ode – do not use

Select stereo mix into ADC as having no DAC
signal

Closes Rev 2.1 switch when set (see fig 1)
Enables I2S data and clock onto GPIO pi ns

43,44,48
Selects support for Line2 DAC and ADC slots
Disables automute f unction on the front and rear

DACs

Vendor specific Gain cont rol registers – (Index 70h to 74h). The function i s as per the other mixer
PGAs. However, the default value of the register changes depending upon the MODE the device is
operating in, as shown in Table 21.

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Production Data WM9704M

DEFAULT VALUE FOR REGISTER

MODE

Rev 2.1 (00) 8808 0808 8808 Closed
Modem (11) 0808 0808 0808 Open

Table 21 Vendor Specific PGA Default Values

REAR DAC – REG 70H

FRONT MIXER – REG

72H

REAR MIXER – REG 74H

REV 2.1
SWITCH

VENDOR ID REGISTERS (INDEX 7CH TO 7EH)

This register is for spec ific vendor ident ificati on if so desired. The ID method is Micros oft’s Pl ug and
Play Vendor ID code. The first character of that I D is F7 to F0, the sec ond character S 7 to S0, and
the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field i s for the
Vendor Revision number. In W M9704M the vendor ID is s et to W ML3 if MODE1 = 0, and W ML4 if
MODE1 = 1.

Wolfson is a registered Microsoft Plug and Play vendor.

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

33

WM9704M Production Data SERIAL INTERFACE REGISTER MAP

The following table shows the function and address of the various control bits t hat are loaded through
the serial interface during write operat i ons.

Reg Name

00h Reset
02h Master volume
04h Headphone vol.
06h Master vol. mono
0Ah PCBEEP vol.
0Ch Phone volume
0Eh Mic volume
10h Line in volume
12h CD volume
14h Video volume
16h Aux volume
18h Frnt PCM out

volume
1Ah Rec. sel ect
1Ch Rec. gain
20h General purpose
22h 3D control
24h Reserved
26h Pwrdwn ctrl/stat
28h Ext’d audio ID
2Ah Ext’d audio

ctrl/stat
2Ch Front DAC rate
2Eh Rear DAC rate
30h LFE DAC rat e
32h Audio ADC rate
36h 6ch vol. C, LFE
38h 6ch vol. L,R surr
3Ch Ext’d mdm ID
3Eh Ext’d mdm stat

Line1 sample

40h

rate ADC/DAC

Line2 sample

42h

rate ADC/DAC

Line1 DAC/ADC

46h

level

Line2 DAC/ADC

48h

level

GPIO pin config

4Ch

GPIO pin type

4Eh

GPIO pin sticky

50h

GPIO wake-up

52h

GPIO pin status

54h

Misc. modem

56h

ctrl/stat
5Ah Vendor rsvd t est
70h Rr PCM out vol.
72h Front m i xer vol.
74h Rear mi xer vol.
7Ah Vendor rsvd
7Ch Vendor ID1
7Eh Vendor ID2

Table 22 Serial Interface Register Map Description

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6140h
Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8000h
Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8000h
MuteXXXXXXXXXXMM4MM3MM2MM1MM08000h
MuteXXXXXXXXXXPV3PV2PV2PV0X8000h
MuteXXXXXXXXXXGN4GN3GN2GN1GN08008h
MuteXXXXXXXX20dB X GN4 GN3 GN2 GN1 GN0 8008h
Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h
Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h
Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h
Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h
Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

XXXXXSL2SL1SL0XXXXXSR2SR1SR00000h
Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 GR0 8000h
POPST3DlDXXMIXMSLPBKXXXXXXX8000h

XXXXXXXXXXXXDP3DP2DP1DP00000h

XXXXXXXXXXXXXXXX0000h

EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Fh

ID1 ID0 X X X X Amap Ldac Sdac Cdac X X VRM X DRA VRA 0281h

X PRL PRK PRJ PRI X Madc Ldac Sdac Cdac X X VRM X DRA VRA 0080h

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

Mute X X LFE4 LFE3 LFE2 LFE1 LFE0 Mute X X CNT4 CNT3 CNT2 CNT1 CNT0 0000h
Mute X X LSR4 LSR3 LSR2 LSR1 LSR0 Mute X X SR4 SR3 RSR2 RSR1 RSR0 8080h

ID1ID0XXXXXXXXXCID2CID1HSETLIN2LIN1x00xh

PRH PRG PRF PRE PD PRC PRB PRA DAC ADC DAC2 DC2 DAC1 ADC1 MREF GPIO 0100h

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

Not supported - set TX modem level s by writing to rear DAC PGA 04h
Not supported - set TX modem level s by writing to rear DAC PGA 04h

00GC13GC12GC1100000000000000Eh
11GP13GP12GP1111111111111FFFFh
00GS13GS12GS11000000000000000h
00
00GI13GI12GI1100000000000000xh

CID2 CID1 CIDR MLNK X HSB2 HSB1 HSB0 X L2B2 L2B1 L2B0 X L1B2 L1B1 L1B0 0000h

ATST DTST AFTS DFTS RTST DDS AMD DLM I2S R2S AND HIM HIC TRM BB AEV 0000h

Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 0808h
Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 0808h
Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

XXXXXXXXXXXXXXXX0000h

F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 574Dh
T7 T6 T5 T4 T3 T2 T1 T0 Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0 4C04h

GW13 GW12 GW11

Sample rates written to 42h will alias onto 40h

000000000000000h

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

34

Production Data WM9704M

RECOMMENDED EXTERNAL COMPONENTS

MODE OF

OPERATION

CONTROL

NOTES: 1. Pins 27, 29 and 31 are
internally connected.
It is recommended that
capacitors only be

connected to one of

these pins.

2. C1 to C28 should be as
close to WM9704M as
possible.

3. AGND and DGND should
be connected as close to

WM9704M as possible.

MIXER

INPUTS

AVDD

AVSS

AC-LINK

DVDD

C1

DGND

AVDD

1

DVDD1

9

DVDD2

C2

C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17

4
7

12
13
14
15
16
17
18
19
20
21
22
23
24

30
40
46
45

5
6

8
10
11

DVSS1
DVSS2

PCBEEP
PHONE
AUXL
AUXR
VIDEOL
VIDEOR
CDL
CDGND
CDR
MIC1
MIC2
LINEINL
LINEINR

MODE0
MODE1
CID1
CID2

SDATAOUT
BITCLK
SDATAIN
SYNC
RESETB

XTLIN

2

C34

VREFOUT

WM9704M

LINEOUTL
LINEOUTR
MONOOUT

LNLVLOUTL

LNLVLOUTR

XTLOUT

3

XT

AVDD1
AVDD2

AVSS1
AVSS2

AFILT1

CX3D1
CX3D2

GPIO1
GPIO2
GPIO3

EAPD

C35

VREF

CAP1
CAP2

25
38

26
42

27
28
29
31
32

C21 C22

33
34

35
36
37
39
41

43
44
48
47

C3 C4

C23 C25

+

C27

C29

+

++

C30

+

C31

+

C32

+

C33

+

AGND

C18 C19 C20

++

C24 C26

AGND

C28

AGND

STEREO OUTPUT

MONO OUTPUT

LINE LEVEL STEREO

TO I2S DACs

+

AGND

DGND

Figure 15 External Components Diagram

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

35

WM9704M Production Data

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

C1 to C4 10nF De-coupling for DVDD and AVDD

C5 to C17 470nF AC coupling capacitors for setti ng DC l evel of analogue inputs to VCAP1.

C18 1µF
C19 0.1µF
C20 10µF
C21 0.1µF
C22 10µF
C23 0.1µF
C24 10µF
C25 0.1µF
C26 10µF
C27 100nF 3D low pass f i l ter. This value sets nominal 100Hz.
C28 47nF 3D high pass filter. This value sets nominal 1kHz.

C29 to C33 10µF Output AC coupling caps to remove VREF DC level from outputs.

C34 and C35 22pF Optional capacitors for bett er crystal frequency stability.

XT 24.576 MHz AC’97 master clock frequency. A bias resistor is not required, but if connected will not

Table 23 External Component Values

SUGGESTED

VALUE

DESCRIPTION

Value chosen to give corner frequenc y below 20Hz for min 10K input impedanc e.
Reference de-coupling capacit ors for ADC, DAC, Mixer and CAP2 references.

Ceramic type or sim i l ar.

affect operation if value i s large (above 1MΩ).

RECOMMENDATIONS FOR 3.3V OPERATION

The device’s performance with AVDD = 3.3V is shown in Electrical Characteristics.
In 3.3V analogue operation, mid-rail reference scales to 1. 5V. All ADC and DAC ref erences are 3/ 5

of their nominal 5V value. Input and output signals that are 1Vrms in 5V applications, scale to
660mVrms in 3.3V applicat ions. If 1Vrm s output is requi red, the mixer gain adjust P GAs need to be
increased by 3 times 1. 5dB steps.

ths

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

36

Production Data WM9704M

PACKAGE DIMENSIONS

FT: 48 PIN TQFP (7 x 7 x 1.4 mm)

b

48

D1

D

DM003.B

e

2536

2437

E1 E

13

121

θ

c

A1

A A2

-C-

SEATING PLANE

C

ccc

Dimensions

Symbols

(mm)

MIN NOM MAX

A ----- ----- 1.60
A

1

A

2

b

0.05 ----- 0.15

1.35 1.40 1.45

0.17 0.22 0.27

c 0.09 ----- 0.20
D
D

1

9.00 BSC

7.00 BSC

E 9.00 BSC
E

1

e
L 0.45 0.60 0.75

θ

o

0

7.00 BSC

0.50 BSC

o

3.5

o

7

Tolerances of Form and Position

ccc

REF:

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MS-026, VARIATION = BBC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

JEDEC.95, MS-026

0.08

L

WOLFSON MICROELECTRONICS LTD PD Rev 3.2 January 2001

37