The WM8738 is a high performance stereo audio ADC
designed for consumer applications.
Stereo line-level audio inputs are provided, along with a
control input pin to allow operation of the audio interface in
either one of two industry standard modes. The device also
has a selectable digital high pass filter to remove residual
DC offsets.
Stereo 24-bit multi-bit sigma delta ADCs are provided, along
with oversampling digital interpolation filters. 24-bit digital
audio output word lengths and sampling rates from 32kHz
to 96kHz are supported.
The device is available in a small 14-pin SOIC package.
1. Digital input pins have Schmitt trigger input buffers and are 5V tolerant.
Digital positive supply
ADC digital data output
ADC audio interface data clock (5V tolerant)
Audio interface format selection (5V tolerant)
2
S
‘0’ = I
‘1’ = Left Justified
Reference de-coupling pin
Buffered reference decoupling pin
Right channel ADC input
Left channel ADC input
Analogue positive supply
Analogue ground supply and chip substrate
Digital highpass filter bypass; (5V tolerant)
‘0’ = Enabled
‘1’ = Bypassed
Data left/right word clock (5V tolerant)
Master clock input (5V tolerant)
Digital supply ground
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WM8738 Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
CONDITION
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Master Clock Frequency
Operating temperature range, TA
Storage temperature prior to soldering
Storage temperature after soldering
Notes
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply voltage must always be less than or equal to the analogue supply voltage.
of this device.
MIN MAX
-0.3V +4.2V
-0.3V +7.0V
DGND -0.3V +7.0V
AGND -0.3V AVDD +0.3V
37MHz
-25°C +85°C
30°C max / 85% RH max
-65°C +150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST
Digital supply range
Analogue supply range
Ground
Analogue supply current
Analogue supply current
Supply Current Low Power
Mode
Supply Current Low Power
Mode
Digital supply current
DVDD 3.0 3.6 V
AVDD 3.0 5.5 V
DGND,AGND 0
AVDD = 5.0V,
AVDD = 3.3V,
AVDD = 5.0V
AVDD = 3.3V
DVDD = 3.3V
CONDITIONS
(DVDD at 3.3V)
(DVDD at 3.3V)
(DVDD at 3.3V)
(DVDD at 3.3V)
AVDD = 5.0V or 3.3V
MIN TYP MAX UNIT
30
19
4
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mA
mA
µA
µA
mA
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WM8738 Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Logic Levels (TTL Levels)
Input LOW level VIL
Input HIGH level VIH
Output LOW VOL
Output HIGH VOH
Pull down resistance (FMT,
RPD
NOHP)
Analogue Reference Levels
Reference voltage V
Buffered reference voltage V
Potential divider output
CAP
REF
R
CAP
impedance
Input to ADC
Input Signal Level (0dB) V
RIN / VLIN
SNR (Note 1,2)
SNR (Note 1,2)
SNR (Note 1,2)
Dynamic Range (Note 2) DNR
Total Harmonic Distortion (THD)
(Note 4)
ADC channel separation
Power Supply Rejection Ratio
PSRR
Input Resistance 20 kΩ
Input Capacitance
Notes
1. Ratio of output level with 1kHz full scale input, to the output level with the input open circuited, measured ‘A’ weighted
over a 20Hz to 20kHz bandwidth using an Audio analyser.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. VREF and CAP de-coupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4. This data is measured, using an active filter on the device inputs.
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No ‘Auto-zero’ or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the r.m.s. values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
The WM8738 is an ADC designed for audio recording. It’s features, performance and low power
consumption make it ideal for recordable CD or DVD players, karaoke, MP3 players and mini-disc
players.
The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit highorder oversampling architecture delivering optimum performance with low power consumption. The
ADC includes a selectable digital high pass filter to remove unwanted DC components from the audio
signal. The device supports system clock inputs of 256, 384, 512fs or 768fs (fs is the sampling rate)
The output from the ADC is available on the digital audio interface in either I
data formats.
2
S or left justified audio
ADC
The line inputs are biased internally through the operational amplifier to V
The WM8738 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is
illustrated in Figure 3.
The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high
frequency noise.
The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any voltage greater than full scale will
possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with
AVDD.
ANALO G
INTEGRATOR
MULTI
BITS
.
CAP
TO ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface.
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter, selectable via pin NOHP.
NOHP = 0 Digital high pass filter enabled
NOHP = 1 Digital high pass filter bypassed
The high-pass filter response detailed in Digital Filter Characteristics. The operation of the high pass
filter removes residual DC offsets that are present on the audio signal.
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WM8738 Production Data
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the MCLK input pin.
In a system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the ADC.
The master clock for WM8738 supports audio sampling rates from 256fs to 768fs, where fs is the
audio sampling frequency LRCLK, typically 32kHz, 44.1kHz, 48kHz, or 96kHz. The master clock is
used to operate the digital filters and the noise shaping circuits.
The WM8738 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is
a greater than 32 clocks error the interface is disabled and maintains the output level at the last
sample. The master clock must be synchronised with LRCLK, although the WM8738 is tolerant of
phase variations or jitter on this clock. Table 1 shows the typical master clock frequency inputs for
the WM8738.
If MCLK is stopped for greater than 10us then the device will enter a low power mode where the
current taken from AVDD is greatly reduced. Note that when the device enters this mode the
references are powered down.
Table 1 shows the common MCLK frequencies for different sample rates.
SAMPLING
RATE
(LRCLK)
32kHz 8.192 12.288 16.384 24.576
44.1kHz 11.2896 16.9340 22.5792 33.8688
48kHz 12.288 18.432 24.576 36.864
96kHz 24.576 36.864 Unavailable Unavailable
Table 1 Master Clock Frequency Selection
Master Clock Frequency (MHz)
256fs 384fs 512fs 768fs
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WM8738 Production Data
DIGITAL AUDIO INTERFACES
The WM8738 has two data output formats, selectable via the FMT pin.
2
FMT = 0 ADC audio data output is I
FMT = 1 ADC audio data output is Left Justified
Both of these modes are MSB first.
The digital audio interface takes the data from the internal ADC digital filter. SDATO is the formatted
digital audio data stream output from the ADC digital filters with left and right channels multiplexed
together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on
the SDATO line. SDATO and LRCLK are synchronous with the BCLK signal with each data bit
transition signified by a low to high BCLK transition.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the ADC data is output on SDATO and changes on the same falling
edge of BCLK as LRCLK and may be sampled on the rising edge of BCLK. LRCLK is high during
the left samples and low during the right samples.
LRCLK
BCLK
S
1/fs
LEFT CHANNELRIGHT CHANNEL
SDATO
n321n-2n-1
LSBMSB
n321n-2n-1
LSBMSB
Figure 4 Left Justified Mode Timing Diagram
2
I
S MODE
In I2S mode, the MSB of the ADC data is output on SDATO and changes on the first falling edge of
BCLK following an LRCLK transition and may be sampled on the rising edge of BCLK. LRCLK is low
during the left samples and high during the right samples.
Figure 6 ADC Digital Filter Frequency Response Figure 7 ADC Digital Filter Ripple
ADC HIGH PASS FILTER
The WM8738 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the
following polynomial.
-1
H(z) =
0
-5
-10
Response (dB)
-15
00.00050.0010.00150.002
1 - z
1 - 0.9995z
-1
Frequency (Fs)
Figure 8 ADC Highpass Filter Response
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WM8738 Production Data
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD
Hardware
Control
DVDD
Audio Serial Data I/F
C
DVDD
1
R
R
1
+
C
2
DVDD
2
14
DGND
4
FMT
AVDD
AGND
LIN
9
10
8
WM8738
11
3
NOHP
13
MCLK
3
BCLK
12
LRCLK
2
SDATO
RIN
VREF
CAP
7
5
AVDD
+
C
C
4
3
AGND
C
5
R
1
C
6
C
7
R
4
C
8
6
C
9
C
11
C
C
10
AGND
12
AGND
+
+
Notes:
1. AGND and DGND should be connected as close to the WM8738 as possible.
, C3, C9 and C
2. C
2
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum
should be positioned as close to the WM8738 as possible.
11
performance.
Figure 9 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
C1 and C4 10µF
C2 and C3 0.1µF
C5 and C7 1µF Analogue input AC coupling caps
C6 and C8 4.7nF
R2 and R3 10kΩ
R1 and R4 680Ω
C9 0.1µF
C10 10µF
C11 0.1µF
C12 10µF
Table 3 External Components Description
SUGGESTED
VALUE
DESCRIPTION
De-coupling for DVDD and AVDD
De-coupling for DVDD and AVDD
Analogue input filtering (RC) capacitor
Current limiting resistors
Analogue input filtering (RC) resistor
Reference de-coupling capacitors for VREF pin
Reference de-coupling capacitors for CAP pin
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WM8738 Production Data
PACKAGE DIMENSIONS
D: 14 PIN SOIC 3.9mm Wide Body
e
14
D
A
B
0.10 (0.004)
DM001.C
8
H
E
71
L
o
h x 45
A1
-C-
SEATING PLANE
α
C
Symbols
Dimensions
(mm)
Dimensions
(Inches)
MINMAXMINMAX
A1.351.750.05320.0688
A10.100.250.00400.0098
B
0.330.510.01300.0200
C0.190.250.00750.0098
D
E
8.558.750.33670.3444
3.804.000.14970.1574
e1.27 BSC0.05 BSC
H
h
L0.401.270.01600.0500
αααα
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJE CT TO CHANGE WI THOUT NOT ICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
5.806.200.22840.2440
0.250.500.00990.0196
o
0
o
8
o
0
8
JEDEC.95, MS-012
o
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WM8738 Production Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (W M) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with W M’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
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property right of WM covering or relating to any combination, machine, or process in which such products or services might
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Resale of WM’s products or services with statements different from or beyond the parameters
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