Datasheet WM9701ACFT-V Datasheet (Wolfson)

WM9701A

Low Power AC’97 Multimedia Audio Codec

Production Data, January 2001, Rev 3.2

DESCRIPTION

The WM9701A is a high-qualit y stereo audio codec compli ant
with the Intel AC’97 Rev 1.03 specification. Forming the
analogue component PC audio solut ion, it performs f ull-duplex
18-bit codec functions at 48 ksamples/s and offers excellent
audio quality with high SNR.

In addition, the WM9701A provides a com prehensive analogue
mixer with 4 sets of stereo input s, plus phone, 2 microphone,
and PC-beep inputs. On-chip reference circuits generate the
necessary bias voltages f or the device, and a 5-pin digital bi­directional serial interface allows transfer of control data and
DAC and ADC words to and from the AC’97 controller.

The WM9701A is partic ularly suited to low power applications
such as notebook PCs.

BLOCK DIAGRAM

VOL/

MUTE

VOL/

MUTE

Σ

FEATURES

• 3.3V or 5V operation

• 18-bit stereo codec

• S/N ratio > 95dB

• Multiple stereo input mixer

• Mono and stereo volume control

• 48-pin TQFP package

• Power management features

• Very low standby power

APPLICATIONS

• Notebook PC

• PC sound cards

• Motherboards

VOL/

MUTE

(35,36) LINEOUT

KEY:

MONO

STEREO

VOL/

MUTE

VOL/

MUTE

VOL/

CD (18,20)

LINEIN (23,24)

VIDEO (16,17)

AUX (14,15)

PHONE (13)

PCBEEP (12)

MIC[1] (21)
MIC[2] (22)

MUX

0dB/
20dB

MUTE

VOL/

MUTE

VOL/

MUTE

Σ

RECORD

WOLFSON MICROELECTRONICS LTD.

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: [phone]
Fax: [phone]
Email: [email protected]
http://www.wolfson.co.uk

MUX
AND

MUTE

Σ

MUX

VOL/

MUTE

Σ

WM9701A

VOL

STEREO

DAC

STEREO

ADC

VOL/

MUTE

SERIAL

I/F

OSC

(37) MONOOUT

(6) BITCLK
(10) SYNC
(8) SDATAIN
(5) SDATAOUT
(11) RESETB

(2) XTLIN
(3) XTLOUT

Production Data datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolf son
Microelectronics’ Term s and Conditions.

 2001 Wolfson Microelectronics Ltd.

WM9701A Production Data

ORDERING INFORMATIONPIN CONFIGURATION

DEVICE TEMP. RANGE PACKAGE

WM9701ACFT/V 0o to 70oC 48-pin TQFP

DVDD1

XTLIN

XTLOUT

DVSS1

SDATAOUT

BITCLK

DVSS2

SDATIN

DVDD2

SYNC

RESETB

PCBEEP

NC

NC

1
2
3
4
5
6
7
8
9
10
11

12

AUXL

PHONE

NC

AUXR

NC

NC

NC

AVSS2

CDL

CDGND

VIDEOL

VIDEOR

NC

CDR

AVDD2

NC

NC

MONOOUT

3747 46 45 44 43 42 41 40 39 3848

242316 17 18 19 20 21 2213 14 15

MIC2

MIC1

LINEINL

LINEOUTR

36

LINEOUTL

35

NC

34

NC

33

CAP2

32
31

NC

30

NC
NC

29

VREFOUT

28

VREF

27

AVSS1

26

AVDD1

25

LINEINR

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be caus ed by cont inuous ly operati ng at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions specified

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.

As per specifications IPC/JEDEC J-STD-020A and JEDEC A113-B, this product requires specific storage conditions prior to
surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in
vacuum-sealed moisture barrier bags.

CONDITION MIN MAX

Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, T

A

Storage temperature
Package body temperature (s ol deri ng 10 seconds)
Package body temperature (s ol deri ng 2 minutes)

-0.3V +7V

-0.3V +7V
DVSS -0.3V DVDD +0.3V
AVSS -0.3V AVDD +0.3V

+240
+183

o

C

o

C

o

C

0oC+70

o

-65

C +150oC

Note:

1. The digital supply voltage (DVDD) must always be less than or equal to the analogue supply voltage (AVDD).

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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Production Data WM9701A

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital supply range
Analogue supply range
Digital ground
Analogue ground
Difference DVSS to AVSS
Analogue supply current
Digital supply current
Standby supply current (all P Rs set)
Analogue supply current
Digital supply current
Standby supply current (all P Rs set)

DVDD1, DVDD2 Note 1 -10% 3.3 to 5.0 +10% V
AVDD1, AVDD2 Note 1 -10% 3.3 to 5.0 +10% V

DVSS1, DVSS2 0 V
AVSS1, AVSS2 0 V

-0.3 0 +0.3 V
DVDD, AVDD = 5V 25 mA
DVDD, AVDD = 5V 10 mA
DVDD, AVDD = 5V 30 µA

DVDD, AVDD = 3.3V 15 mA
DVDD, AVDD = 3.3V 6 mA
DVDD, AVDD = 3.3V 20 µA

Note:

1. Both supplies should be powered on and off at the same time.

ELECTRICAL CHARACTERISTICS

Test Conditions:

AVDD = 5V, GND = 0V, DVDD = 3.3V, GND = 0V, T

PARAMETER SYM BOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Logic Levels (DVDD = 3.3 or 5.0V)

Input LOW level V
Input HIGH level V
Output LOW V
Output HIGH V

IL

IH
OL
OH

Analogue I/O Levels (Input Signals on any Inputs, Outputs on LINEOUT L, R and MONO)

Input level

Output level

Reference Levels

Reference input/output CAP2
CAP2 impedance
Mixer reference VREF

MIC reference VREFOUT

MIDBUFF current sink
(pins VREF and VREFOUT)

MIDBUFF current source
(pins VREF and VREFOUT)

MIDBUFF current source
(pins VREF and VREFOUT)

= 0oC to +70oC, unless otherwise stated.

A

AVSS -0.3 0.8 V

2.2 AVDD +0.3 V

0.1 ∗ VDD V

0.9 ∗ VDD V

Minimum input

impedance = 10k
Into 10kohm load AVSS

AVSS

-100mV

+100mV

Near rail to

rail

AVDD
+100mV

AVDD

-100mV

2/5 AVDD AVDD/2 3/5 AVDD V

75 kohms

Buffered

CAP2

Buffered

CAP2

AVDD = 5V -5 -15 mA

AVDD = 5V 5 15 mA

AVDD = 3.3V 5 mA

V

V

V

V

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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WM9701A Production Data

Test Conditions:

AVDD = 5V, GND = 0V, DVDD = 3.3V, GND = 0V, T

DAC Circuit Specifications 48kHz Sampling

SNR A-weighted (Note 1)

Full scale output voltage

THD
Frequency response
Transition band
Stop band
Out of band rejection
Spurious tone reduction
PSRR

ADC Circuit Specifications 48kHz Sampling

SNR A-weighted (Note 1)

ADC input for full scal e out put

THD
Frequency response
Transition band
Stop band
Stop band rejection
PSRR

Mixer Circuit Specificati ons 48kHz Sampling

SNR CD path A-weighted
(Note 1)

SNR Other paths A-weighted
(Note 1)

Maximum input voltage

Maximum output voltage on
LINEOUT

THD
Frequency response (+/-1dB)
Input impedance (CD inputs )
Input impedance (other mixer

inputs)
Input impedance MIC inputs

PSRR

Clock Frequency Range

Crystal clock
BIT_CLK frequency
SYNC frequency

= 0oC to +70oC, unless otherwise stated.

A

AVDD = 5V 85 96 dB

AVDD = 3.3V 93 dB

VREF = 2.5V 1.0 Vrms

= 1.65V 0.66 Vrms

VREF

-3dBFS input 74 (0.2%) 90 dB
20 19,200 Hz

19,200 28,800 Hz
28,800 Hz

-40 dB

-100 dB

20 to 20kHz 46 dB

AVDD = 5V 75 92 dB
AVDD = 3.3V 90 dB
VREF = 2.5V,

1.0 Vrms

AVDD = 5V

VREF

= 1.65V,

0.66 Vrms

AVDD = 3.3V

-6dBV input 74 90 dB
20 19,200 Hz

19,200 28,800 Hz
28,800 Hz

-74 (0.2%) dB

20 to 20kHz 40 dB

AVDD = 5V 90 95 dB

AVDD = 3.3V 93 dB

AVDD = 5V 85 95 dB

AVDD = 3.3V 93 dB

AVSS 1.0 AVDD Vrms

0.66

1.0 Vrms

0dBV input -74 (0.2%) -92 dB

20 20,000 Hz

At any gain 10 15 kohm

At max gain 10 20 kohm

At 0db gain 100 kohm

At max gain 80 kohm

At 0db gain 10 15 kohm

20 to 20kHz 40 dB

24.576 MHz

12.288 MHz

48.0 kHz

Note:

1. SNR is the ratio of 0dB ful l scale signal level to output le vel with no signal present, A-weighted and 20 - 20kHz bandwidth.

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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Production Data WM9701A

SERIAL INTERFACE

Test Conditions:

AVDD = 5V, GND = 0V, DVDD = 3.3V, GND = 0V, T
measurements are t aken at 10% to 90% VDD, unless otherwise stated.

All the following timing information is guaranteed, not tested.

AC-LINK LOW POWER MODE

= 0oC to +70oC, unless otherwise stated. All

A

COLD RESET

SYNC

SLOT 1 SLOT 2

BIT_CLK

SDATA_OUT

WRITE

TO 0X20

DATA PR4

t

S2_PDOWN

DON’T
CARE

SDATA_IN

Figure 1 AC-Link Power down Timing

PARAMETER SYMBOL MIN TYP MAX UNIT

End of slot 2 to BIT_CLK

t

S2_PDOWN

1.0 µs

SDATA_IN low

t

RST_LOW

t

RST2CLK

RESETB

BIT_CLK

Figure 2 Cold Reset Timing

PARAMETER SYMBOL MIN TYP MAX UNIT

RESETB active low pulse width t
RESETB inactive to BIT_CLK

RST_LOW

t

RST2CLK

1.0 µs

162.8 ns

startup delay

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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WM9701A Production Data

WARM RESET

Figure 3 Warm Reset Timing

SYNC active high pulse width t
SYNC inactive to BIT_CLK

startup delay

CLOCK SPECIFICATIONS

t

SYNC_HIGH

t

SYNC2CLK

SYNC

BIT_CLK

PARAMETER SYMBOL MIN TYP MAX UNIT

1.3 µs

BIT_CLK

t

CLK_HIGH

t

CLK_PERIOD

t

SYNC_HIGH

SYNC_HIGH

t

SYNC2CLK

162.4 ns

t

CLK_LOW

t

SYNC_LOW

SYNC

t

SYNC_PERIOD

Figure 4 Clock Specifications (50pF External Load)

Note: Worst case duty cycle restricted to 40/60.

PARAMETER SYMBOL MIN TYP MAX UNIT

BIT_CLK frequency
BIT_CLK period t
BIT_CLK output jitter
BIT_CLK high pulse width (Note

CLK_PERIOD

t

CLK_HIGH

32.56 40.7 48.84 ns

12.288 MHz

81.4 ns
750 ps

1 on page 4)
BIT_CLK low pulse width (Note

t

CLK_LOW

32.56 40.7 48.84 ns

1 on page 4)
SYNC frequency
SYNC period t
SYNC high pulse width t
SYNC low pulse width t

SYNC_PERIOD

SYNC_HIGH
SYNC_LOW

48.0 kHz

20.8 µs

1.3 µs

19.5 µs

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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Production Data WM9701A

DATA SETUP AND HOLD (50PF EXTERNAL LOAD)

t

SETU

P

BIT_CLK

SYNC/

SDATA_OUT

/SDATA_IN

Figure 5 Data Setup and Hold (50pF External Load)

Note: Setup and hold time parameters for SDATA_IN are with respect to AC’97 Controller.

PARAMETER SYMBOL MIN TYP MAX UNIT

Setup to falling edge of
BIT_CLK

Hold from falling edge of
BIT_CLK

SIGNAL RISE AND FALL TIMES

BIT_CLK

SYNC

t

t

rise

rise

t

rise

CLK

SYNC

DIN

t

t

HOL

D

t

fall

fall

t

t

SETUP

t

HOLD

fall

15.0 ns

5.0 ns

CLK

SYNC

DIN

SDATA_IN

t

rise

DOUT

t

fall

DOUT

SDATA_OUT

Figure 6 Signal Rise and Fall Times (50pF external load)

PARAMETER SYMBOL MIN TYP MAX UNIT

BIT_CLK rise time trise
BIT_CLK fall time tfall
SYNC rise time trise
SYNC fall time tfall
SDATA_IN rise time trise
SDATA_IN fall time trise
SDATA_OUT rise time trise
SDATA_OUT fall time tfall

CLK

CLK

SYNC

SYNC

DIN
DIN

DOUT

DOUT

26ns
26ns
26ns
26ns
26ns
26ns
26ns
26ns

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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WM9701A Production Data PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

DVDD1 Supply Digital positi ve s upply
XTLIN Digital input Clock crystal connection or clock input (XTAL not used)
XTLOUT Digital output Clock crystal connection
DVSS1 Supply Digital ground supply
SDATAOUT Digit al i nput Serial dat a i nput
BITCLK Digital output Serial interface clock output to AC’97 controller
DVSS2 Supply Digital ground supply
SDATAIN Digital output Serial dat a output to AC’97 controller
DVDD2 Supply Digital positi ve s upply
SYNC Digital i nput Serial interface sync pulse from AC’97 c ontroller
RESETB Digital input NOT reset input (active low, resets regis ters)
PCBEEP Analogue input Mixer input, typically for PCBEEP signal
PHONE Analogue input Mixer input, typically f or P HONE signal
AUXL Analogue input Mixer input, t ypi cally for AUX signal
AUXR Analogue input Mixer input, typic al l y f or AUX signal
VIDEOL Analogue input Mixer input, typically for VI DE O signal
VIDEOR Analogue input Mixer input, typically for VIDEO signal
CDL Analogue input Mixer input, typically for CD signal
CDGND Analogue input CD input common mode reference (ground)
CDR Analogue input Mixer input, typically for CD signal
MIC1 Analogue input Mixer input with extra gain if required
MIC2 Analogue input Mixer input with extra gain if required
LINEINL Analogue input Mixer input, t ypi cally for LINE signal
LINEINR Analogue input Mixer input, typically for LINE signal
AVDD1 Supply A nal ogue positive supply
AVSS1 Supply Analogue ground supply, chip substrate
VREF Analogue output Buffered CA P2, used as MIXER reference
VREFOUT Analogue output Reference for mi crophones; buffered CAP2
NC No internal connection
NC No internal connection
NC No internal connection
CAP2 Analogue input Referenc e i nput/output; pulls to midrail if not driven
NC No internal connection
NC No internal connection
LINEOUTL Analogue output Main analogue output for l ef t channel
LINEOUTR Analogue output Main analogue output for right channel
MONOOUT Analogue output Main mono output
AVDD2 Supply A nal ogue positive supply
NC No internal connection
NC No internal connection
NC No internal connection
AVSS2 Supply Analogue ground supply, chip substrate
NC No internal connection

NC
NC
NC
NC
NC

No internal connection
No internal connection
No internal connection
No internal connection
No internal connection

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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Production Data WM9701A

DEVICE DESCRIPTION

INTRODUCTION

WM9701A is full y compatible with Rev 1.03 of the AC’97 s pecification.
WM9701A compri ses a stereo 18-bit Codec, (that i s, 2 ADCs and 2 DACs) plus a comprehensive

analogue mixer with 4 sets of stereo inputs, plus phone, 2 microphone, and PC-beep inputs.
Additionally, on-chip reference generation circuits generate the necessary bias voltages for the
device, and a bi-directional s erial interface allows t ransfer of cont rol data and DAC and ADC words
to and from the AC’97 controller. WM9701A supports 18-bit resolution within the DAC and ADC
functions, but the A C’97 Codec serial interfac e specificat ion allows any word length up to 20-bi ts to
be written to, or read from, the A C’97 Codec. These words are MSB justified, and any LSBs not used
will simply default to 0. Normally it is anticipated that 16-bit words will be used in most PC type
systems. Therefore, for the DAC, 16-bit words will be downloaded into the Codec from the c ontroller,
along with padding of 0s to make t he 16-bit word up to 20-bit length. In t his case, W M9701A will
process the 16-bit word along with 0 padding bits i n the 2 LSB locations (to make 18-bit). A t the ADC
output, WM9701A will provide an 18-bit word, again with 0s in the two LSB loc ations (20-bit). The
AC’97 controller will then ignore the 4 LSBs of the 20-bit word. W hen W M9701A is interrogated, it
responds indicating it is an 18-bit device. However, a serial register c ontrolled mode is available t o
allow these flags to be changed, making the device appear to be a 16-bit devic e.

The WM9701A has the ADC and DA C functions impl emented using over sam pled, or ‘sigma-delta’
converters, and uses on-chip digital filters to convert these 1-bit signals to and from the 48ks/s
16/18-bit PCM words that the AC’97 controll er requires. The digital part s of the device are powered
separately from the analogue to optimise performance, and 3. 3V digital and 5V analogue supplies
may be used on the same devi ce to further optimise perf ormance. Digital levels are 5V tolerant when
the analogue supplies are 5V, so WM9701A may be connected to a controller running on 5V
supplies, but using 3.3V for the digital s ection of W M9701A. WM9701A i s also capable of operating
with a 3.3V supply only (digital and analogue).

An internally generated mid-rail reference is provided at pin CAP2 which is used as the chip
reference. This pin should be heavily decoupled.

The WM9701A is not limited to PC-only applications. The ability to power down sections of the
device selectively, and the option to choose alternative master clock, and hence sample rates,
means that many alternative applications in areas such as telecoms, m ay be anticipated. Internal
connection of Pc-beep to t he outputs in the case where the device is reset is supported.

CONTROL INTERFACE

A digital interface to c ontrol and transfer to and from the W M9701A has been provided. This serial
interface is compatible with the Intel AC’97 specification as illustrated in the ‘System Diagram’.

The main control interfac e functions are:

• Control of analogue gain and signal paths through the mixer.

• Bi-directional transf er of ADC and DAC words to and from AC’97 control l er.

• Selection of power down modes.

AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL

WM9701A incorporates a 5 pin digit al s erial i nterfac e that li nks it t o the A C’97 controller. AC-link is a
bi-directional, fixed rate, serial PCM digital stream. It handles multiple input, and output audio
streams, as well as control register acc esses empl oying a time divis ion multiplexed (TDM) schem e.
The AC-link architecture di vides each audio frame int o 12 outgoing and 12 incoming dat a streams,
each with 20-bit sample resol ution. With a minim um required DAC and ADC resolution of 16-bits,
AC’97 may also be implemented with 18 or 20-bit DAC/ADC res olution, given the headroom that t he
AC-link architecture provi des. WM9701A provides support for 18-bit operation.

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

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WM9701A Production Data

SLOT #

0123456789101112

SYNC

CMD

CMD

PCM

PCM

OUTGOING

STREAMS

INCOMING

STREAMS

TAG

ADR

DATA

LEFT

CMD

CMD

TAG

ADR

DATA

PCM
LEFT

RIGHT

PCM

RIGHT

OPT

RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD

MDM CDC

OPT

RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD

MDM CDC

DATA PHASE

TAG PHASE

Figure 7 AC’97 Standard Bi-directional Audio Frame

TAG PHASE DATA PHASE

SYNC

BIT_CLK

SDATA_OUT

END OF PREVIOUS

AUDIO FRAME

OUT

12.288MHz

VALID

SLOT(1)

SLOT(2) SLOT(12)

FRAME

(’1’ = TIME SLOT CONTAINS

81.4nS

’0’ ’0’ ’0’ 19 0 19 0 19 0 19 0

TIME SLOT ’VALID’ BITS

VALID PCM DATA)

SLOT (1) SLOT (2) SLOT (3) SLOT (12)

20.8µS (48kHz)

Figure 8 AC-link Audio Output Frame

The data streams current l y def i ned by t he AC’97 specification include:

PCM playback - 2 output slots 2 channel composite PCM output stream
PCM record data - 2 input slots 2 channel composite PCM input stream
Control 2 output slots Control register write port
Status 2 input slots Control register read port
Optional modem line Codec output - 1
output slot
Optional modem line Codec input - 1
input slot
Optional dedicated microphone input ­1 input slot

Modem line Codec DAC input st ream
(Not supported by WM9701A)
Modem line Codec ADC output st ream
(Not supported by WM9701A)
Dedicated microphone input stream in support of
stereo AEC, and/or other voice applications.
(Not supported by WM9701A)

Synchronisation of all AC-link data transactions is signalled by the W M9701A controller. W M9701A
drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a
synchronisation signal t o construct audio frames.

SYNC fixed at 48 kHz, is derived by dividi ng down the serial clock (BIT_CLK). BIT_CLK, fixed at

12.288 MHz, provides the necessary c l ocking granularity to support 12, 20-bit outgoing and incoming
time slots. AC-link serial data is trans itioned on each rising edge of BIT_CLK. The receiver of A C­link data, (WM9701A for out going data and the AC’97 controller for incom ing data), samples each
serial bit on the falling edges of BIT_CLK.

The AC-link protocol provides for a spec ial 16-bit tim e slot (slot 0) wherein each bit conveys a valid
tag for its corresponding time s lot within the c urrent audio frame. A 1 in a given bit pos ition of slot 0
indicates that the c orresponding time slot within the c urrent audio frame has been assigned to a data
stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the source of the
data, (WM9701A for t he i nput stream, AC’97 controller f or the out put s tream ); to s tuf f all bit posit ions
with 0s during that slot’s active time.

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Production Data WM9701A

SYNC remains high for a total duration of 16 BIT CLKs at the beginni ng of each audio frame.
The portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The rem ainder of

the audio frame where SYNC is low is defi ned as the “Data Phas e”. Additionally, f or power savings,
all clock, sync, and data signals can be halted. This requires that W M9701A be implement ed as a
static design to all ow its register contents to remain intact when entering a power savings mode.

AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)

The audio output frame data streams correspond t o the mul tiplexed bundles of al l digital out put data
targeting WM9701A’s DAC inputs , and control registers. As briefly mentioned earlier, each audio
output frame supports up to 12, 20-bit outgoing data time s lots. Slot 0 is a speci al reserved tim e sl ot
containing 16-bits, which are used for AC-link protocol infrast ruc ture.

Within slot 0 the firs t bit is a global bit (SDATA_OUT sl ot 0, bit 15) which flags the validity f or the
entire audio frame. If t he “Valid Frame” bit is a 1, this indicat es that t he current audio f rame c ontains
at least one time slot of valid dat a. The next 12-bit pos it ions sam pled by WM9701A indicate which of
the corresponding 12 time s l ots contain valid data.

In this way data streams of differing sampl e rates can be transmi tted across A C-link at it s fixed 48
kHz audio frame rate. Figure 8 illustrates t he time slot based AC-link protocol.

WM9701A SAMPLES SYNC ASSERTION

SYNC

BIT_CLK

WM9701A SAMPLES FIRST
SDATA_OUT BIT OF FRAME HERE

VALID

SLOT (1)

SDATA_OUT

FRAME

END OF PREVIOUS AUDIO FRAME

SLOT (2)

Figure 9 Start of an Audio Output Frame

A new audio output frame begins with a low to high t ransiti on of SYNC as s hown in Figure 9. S YNC
is synchronous to the rising edge of B I T_CLK . On the immediately following falling edge of BI T_CLK ,
WM9701A samples the ass ertion of SY NC. This f alling edge m arks the ti m e when bot h s ides of AC­link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, AC’97
transitions SDATA_OUT into the first bit position of slot 0 (“Valid Frame” bit). Each new bit position is
presented to AC-link on a rising edge of BIT_CLK , and subsequently sam pled by the W M9701A on
the following falling edge of BIT_CLK. This sequence ensures that dat a transitions and subsequent
sample points for bot h i ncoming and outgoing data stream s are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a
fixed 48 ks/s on the AC’97 control l er.

This requirement is necessary to ensure that interoperability between the AC’97 controller and
WM9701A, among other things, can be guaranteed by definition for baseline specified AC’97
features.

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions
stuffed with 0s by the AC’97 controller.

In the event that there are less than 20 valid bits within an as signed and valid time slot , the AC’97
controller always stuffs al l trailing non-valid bit positions of the 20-bit slot with 0s.

As an example, consider an 8-bit s ample stream that is being played out t o one of WM9701A’s
DACs. The first 8-bit pos itions are pres ented to the DAC (MSB justifi ed) followed by the next 12-bit ­positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the
resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least
significant bits .

When mono audio s ample stream s are output from t he AC’97 controller, it is necessary that B OTH
left and right sample stream time slots be filled with the s ame data.

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SLOT 1: COMMAND ADDRESS PORT

The command port is used to control features, and monit or stat us for W M9701A f unctions including,
but not limited to, mixer settings , and power management (refer to the regi ster s ection). The control
interface architecture supports up to 64, 16-bit read/write registers, addressable on even byte
boundaries. Only the even registers (00h, 02h, etc. ) are valid, odd regi ster (01h, 03h, etc. ) acces ses
are discouraged (if supported they s houl d default to the preceding even byte boundary - i.e. a read to
01h will return the 16-bit contents of 00h. WM9701A’s cont rol regis ter f il e is nonet heles s readabl e as
well as writeable to provide more robust testability.

Audio output frame slot 1 communicates control register address, and read/write command
information to WM9701A.

TAG PHASE DATA PHASE

SYNC

BIT_CLK

SDATA_IN

END OF PREVIOUS

AUDIO FRAME

12.288MHz

81.4nS

CODEC

SLOT(1) SLOT(2) SLOT(12)

READY

(’1’ = TIME SLOT CONTAINS

’0’ ’0’ ’0’ 19 0 19 0 19 0 19 0

TIME SLOT ’VALID’ BITS

VALID PCM DATA)

SLOT (1) SLOT (2) SLOT (3) SLOT (12)

20.8µS (48kHz)

Figure 10 AC-link Audio Input Frame

COMMAND ADDRESS PORT BIT ASSIGNMENTS

Bit(19) Read/write command (1 = read, 0 = write)
Bit(18:12) Control register index (64 16-bit locations, addressed

on even byte boundaries)

Bit(11:0) Reserved (stuffed with 0s)

The first bit (MSB) sam pled by W M9701A indi cates whether t he current cont rol transac tion is a read
or write operation. The following 7 bit positions communicate t he targeted control register address .
The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC’97
controller.

SLOT 2: COMMAND DATA PORT

The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle. (As indicated by slot 1, bit 19)

Bit(19:4) Control register write data (stuffed with 0s if current

operation is a read)

Bit(3:0) Reserved (stuffed with 0s)

If the current comm and port operation is a read then t he entire time sl ot must be s tuffed with 0s by
the AC’97 controller.

SLOT 3: PCM PLAYBACK LEFT CHANNEL

Audio output frame slot 3 is the composite digital audi o left playback stream. I n a typical ‘Games
Compatible’ PC this slot is com pos ed of s tandard P CM (.wav) output sam pl es di gital ly m ixed (on the
AC’97 controller or host processor) with music synthesis output samples. If a sample stream of
resolution less than 20-bits is transferred, the AC’97 controller must stuff all trailing non-valid bit
positions within this time slot with 0s.

SLOT 4: PCM PLAYBACK RIGHT CHANNEL

Audio output frame slot 4 is the com posite digital audio right playbac k stream. In a typic al ‘Games
Compatible’ PC this slot is com pos ed of s tandard P CM (.wav) output sam pl es di gital ly m ixed (on the
AC’97 controller or host processor) with music synthesis out put samples.

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If a sample stream of resolution less than 20-bits is transferred, the A C’97 controller must stuf f all
trailing non-valid bit positi ons within this time slot with 0s.

SLOT 5: OPTIONAL MODEM LINE CODEC

Audio output frame slot 5 contains the MSB justifi ed modem DAC input data. This optional AC’97
feature is not supported in WM9701A, and if data is written to t his loc ation it is ignored. Thi s m ay be
determined by the AC’97 controll er interrogating the WM9701A Vendor I D regi sters.

SLOTS 6-12: RESERVED

Audio output frame slot s 6-12 are reserved for future use and are always stuffed with 0s by the
AC’97 controller.

AC-LINK AUDIO INPUT FRAME (SDATA_IN)

The audio input frame data stream s correspond to the multi plexed bundles of all digital input data
targeting the AC’97 controller. As is the case f or audio output f rame, each AC-link audio input fram e
consists of 12, 20-bi t time slots.

Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol
infrastructure.

Within slot 0 the f irs t bit is a global bi t (SDA TA_I N sl ot 0, bit 15) which f lags whether WM9701A is in
the “Codec Ready” state or not. If t he “Codec Ready” bit is a 0, this indicates that WM9701A is not
ready for normal operation. This condition is normal foll owing the desertion of power on reset for
example, while WM9701A’s volt age references settl e. W hen the A C-link “Codec Ready” indicator bit
is a 1 it indicates that the AC-link and WM9701A control and status registers are in a fully
operational state. The AC’97 controller must further probe the power down Control/Status Register t o
determine exactly which subsec tions, if any, are ready.

Prior to any attempts at putti ng W M9701A into operat ion the AC’97 cont roller should poll t he first bi t
in the audio input frame (SDATA_IN slot 0, bit 15) for an indic ation that W M9701A has gone “Codec
Ready”.

Once WM9701A is s ampled “Codec Ready” then the next 12 bit positions sam pled by the AC’97
controller indicate which of t he corresponding 12 tim e slots are assigned to input data stream s, and
that they contain valid data. Figure 10 illustrates the time slot based AC-link protocol.

There are several subsections within WM9701A that can independently go busy/ready. It is the
responsibility of the W M9701A controller to probe more deeply into the WM9701A register file to
determine which W M9701A subsections are actually ready.

WM9701A samples SYNC assertion

SYNC

AC’97 Controller samples first
SDATA_IN bit of frame here

BIT_CLK

Codec

SDATA_IN

End of previous Audio Frame

Ready

Slot (1) Slot (2)

Figure 11 Start of an Audio Input Frame

A new audio input frame begins with a low to high transition of SYNC as shown in Figure 11. SYNC
is synchronous to the rising edge of B I T_CLK . On the immediately following falling edge of BI T_CLK ,
WM9701A samples the ass ertion of SY NC. This f alling edge m arks the ti m e when bot h s ides of AC­link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the A C’97
controller transitions SDATA_IN into the first bit position of slot 0 (valid frame bit). Each new bit
position is presented to A C-link on a rising edge of BIT_CLK, and subsequently sampled by the
AC’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data
transitions and subsequent sample points for both inc oming and outgoing data streams are time
aligned.

SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned tim e slots ) stuf fed with 0’s by W M9701A. SDATA _IN is s ampled on t he
falling edges of BIT_CLK .

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SLOT 1: STATUS ADDRESS PORT

The status port is used to monitor status for W M9701A functi ons including, but not limited to, mixer
settings, and power management.

Audio input frame slot 1 ec hoes the control regi ster index, for hist orical referenc e, for the data to be
returned in slot 2. (Ass uming that slots 1 and 2 had been tagged “valid” by WM9701A during slot 0).

STATUS ADDRESS PORT BIT ASSIGNMENTS:

Bit(19) RESERVED (stuffed with 0s)
Bit(18:12) Control register index (echo of regist er i ndex for which dat a i s

Bit(11:0) RESERVED (stuffed with 0s)

The first bit (MSB) generated by W M9701A is always stuff ed with a 0. The following 7 bit positions
communicate the associated control register address, and the trailing 12-bit positions are stuffed
with 0s by WM9701A.

SLOT 2: STATUS DATA PORT

The status data port delivers 16-bi t control register read data.

being returned)

Bit(19:4) Control regi ster read data (stuffed with 0s if t agged “invalid” by

Bit(3:0) RESERVED (stuffed with 0s)

If slot 2 is tagged “invalid” by WM9701A, t hen the entire slot will be stuffed with 0s by WM9701A.

WM9701)

SLOT 3: PCM RECORD LEFT CHANNEL

Audio input frame slot 3 i s the left channel output of WM9701A’s input Mux, post-ADC.
WM9701A’s ADCs can be implem ented to support 16, 18, or 20-bit resolution. WM9701A ships out

its ADC output data (MSB first), and stuf fs any trailing non-valid bit posit ions with 0s to f ill out its 20­bit time slot.

SLOT 4: PCM RECORD RIGHT CHANNEL

Audio input frame slot 4 i s the right channel output of WM9701A’s input Mux, post-ADC.
WM9701A’s ADCs can be implemented to support 16, 18, or 20-bit resolution.
WM9701A ships out its ADC output data (MSB first), and s tuffs any trailing non-valid bit positions

with 0s to fill out its 20-bit time slot.

SLOT 5: OPTIONAL MODEM LINE CODEC

Audio input frame slot 5 cont ains MSB jus tif ied m odem A DC output data. This opt ional f eature is not
supported by WM9701A. This may be determined by the AC’97 controller interrogating the
WM9701A Vendor ID register.

SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA

Audio input frame slot 6 is an optional (post-ADC) third PCM system input channel available for
dedicated use by a desktop m ic rophone. This opti onal AC’97 f eature is not supported by WM9701A.
This may be determined by t he AC’97 controller interrogating the WM9701A Vendor ID register.

SLOTS 7-12: RESERVED

Audio input frame slots 7-12 are reserved for future use and are always stuffed with 0s by
WM9701A.

AC-LINK LOW POWER MODE

The AC-link signals can be placed in a low power mode. W hen WM9701A’s power down Register
(26h), is programmed to the appropriat e value, both B IT_CLK and S DATA _IN will be brought t o, and
held at a logic low voltage level.

BIT_CLK and SDATA_IN are trans itioned low immediately following the dec ode of the write to the
power down Register (26h) with PR4. When the AC’97 c ontroller driver is at the point where it i s
ready to program the AC-link into its low power mode, slots 1 and 2 are assumed t o be the only val id

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stream in the audio output frame. At this point in time it is ass umed that all sources of audio input
have also been neutralised.

The AC’97 controller should also drive SYNC and SDATA_OUT low after program m ing WM9701A to
this low power, “halted” mode.

Once WM9701A has been instructed to hal t BIT_CLK , a speci al “wak e u p” protoc ol m ust be used t o
bring the AC-link to the active mode since normal audio output and input frames can not be
communicated i n the absence of BIT_CLK.

WAKING UP THE AC-LINK

There are 2 methods for bringing the AC-l ink out of a low power, halted mode. Regardless of the
method, it is the AC’97 controller that performs the wake up task.

AC-link protocol provides f or a “Cold WM9701A Reset”, and a “Warm WM9701A Reset ”.
The current power down state would ultimately dict ate which form of W M9701A reset is appropriate.

Unless a “cold” or “register” reset (a write to the Reset regi st er) is perf orm ed, wherein t he WM9701A
registers are initialised to their default values, regis ters are required to keep state during all power
down modes.

Once powered down, re-activation of the AC-link vi a re-asserti on of the SY NC signal m ust not oc cur
for a minimum of 4 audio frame times following the frame in which t he power down was triggered.
When AC-link powers up it i ndi cates readiness via the Codec Ready bit (input slot 0, bit 15).

COLD WM9701A RESET

A cold reset is achieved by asserting RESETB for the minimum specified time. By driving RESETB
low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and all
WM9701A control registers will be initialised t o t heir default power on reset values.

RESETB is an asynchronous WM9701A input.

WARM WM9701A RESET

A warm WM9701A reset will re-activate the AC-link without altering t he current WM9701A register
values. A warm reset is signaled by driving SYNC high for a minimum of 1µS in the absence of
BIT_CLK.

Within normal audio fram es SYNC is a synchronous W M9701A input. However, in the absence of
BIT_CLK, SYNC is treat ed as an asynchronous input used in the generation of a warm reset to
WM9701A. WM9701A will not respond with the activation of BIT_CLK unt il SYNC has been sam pled
low again by WM9701A. This will preclude the false detecti on of a new audio frame.

SERIAL INTERFACE REGISTER MAP DESCRIPTION

(See Table 10)
The serial interface bits perform control functions described as follows: The register map is fully

specified by the AC’97 specification, and this description is simply repeated below, with optional
unsupported features omit ted.

RESET REGISTER (INDEX 00h)

Writing any value to this regis ter performs a register reset, which causes all registers to revert to
their default values. Reading this register returns the ID code of the part, indication of modem
support (not supported by WM9701A) and a code for the type of 3D Stereo Enhancement (not
supported by WM9701A).

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The ID decodes the capabilities of WM9701A based on the following:

BIT FUNCTION VALUE ON WM9701A

ID0 Dedicated Mic PCM in c hannel
ID1 Modem line Codec s upport
ID2 Bass and trebl e control
ID3 Simulated stereo (mono to stereo)
ID4 Headphone out support
ID5 Loudness (bass boost) support
ID6 18-bit DAC resol ution
ID7 20-bit DAC resol ution
ID8 18-bit ADC resol ution
ID9 20-bit ADC resol ution

SE4....SE0No stereo enhancement

Table 1 Reset Register Function

Note that WM9701A defaults to indicat e 18-bit com pat ibility. However, a control bit m ay be set in t he
vendor - specific registers that changes bit s ID6 and ID8 to be ‘0’, indicating a 16-bit device. It is
unlikely that this function will be required, however, as the MSB justific ation of the ADC and DAC
data means that a nominally 18-bit device should be fully compatible with controllers that only
provide 16-bit support. (Most PC type applications will only require 16-bit operation).

PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)

These registers manage the out put s ignal vol um es. Register 02h c ontrols the s tereo m as ter volum e
(both right and left channels), Register 04h controls the optional stereo headphone out, and
Register 06h controls the mono volume output. Each step c orresponds to 1.5dB. The MSB of the

register is the mut e bi t. When this bit i s set to 1 the level for that c hannel is set at ­ML5 to ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5 to MM0 is

for the mono out channel.
Support for the MSB of the level is not provided by WM9701A. If the MSB is written to then

WM9701A detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes a
1xxxxx WM 9701A interprets that as x11111. It will also respond when read with x11111 rather than
1xxxxx, th e value writte n to it . The d river c an use this featu re to de tect if support for the 6t h bit is
there or not.

The default value of both the mono and t he stereo regis ters is 8000h (1000 0000 0000 0000), which
corresponds to 0dB gain with mut e on.

0
0
0
0
0
0
1
0
1
0

00000

∞dB.

MUTE MX4...MX0 FUNCTION

0 0 0000 0dB att enuation
0 0 0001 1.5dB at tenuation
0 1 1111 46.5dB at tenuation

1 x xxxx ∞dB attenuation

Table 2 Volume Register Function

MASTER TONE CONTROL REGISTERS (INDEX 08h)

Optional register for support of tone controls (bass and treble). W M9701A does not support bass
and treble and writing to this register will have no effect, reading will result in all don’t care values.

PC BEEP REGISTER (INDEX 0Ah)

This controls the level for the PC-beep input. Each step corresponds to approximately 3dB of
attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that
channel is set at -

WM9701A defaults t o the PC-beep path being muted, so an external s peaker should be provided
within the PC to alert the user to power on self -test problems.

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MUTE PV3...PV0 FUNCTION

0 0000 0dB attenuation
0 1111 45dB attenuation

1 xxxx ∞dB attenuation

Table 3 PC-beep Register Function

ANALOGUE MIXER INPUT GAIN REGISTERS (INDEX 0CH - 18h)

This controls the gain/attenuation for each of the analogue inputs. Each step corresponds to
approximately 1.5dB. The MSB of the register is the mute bit. W hen this bit is s et to 1 the level for

that channel is set at -∞dB.

REGISTER 0EH (MIC VOLUME REGISTER)

This has an extra bit that is for a 20dB boost. When bit 6 is set to 1 the 20dB boost is on. The default
value is 8008, which corresponds to 0dB gai n with mute on.

The default value for the mono registers is 8008h, which corresponds to 0dB gain with m ute on. The
default value for stereo registers is 8808h, which corresponds to 0dB gai n with mute on.

MUTE GX4...GX0 FUNCTION

0 00000 +12dB gain
0 01000 0dB gain
0 11111 -34.5dB gain

1 xxxxx -∞dB gain

Table 4 Mixer Gain Control Register Function

RECORD SELECT CONTROL REGISTER (INDEX 1Ah)

Used to select the record source independently for right and left. (see Table 5 for legend). The
default value is 0000h, which corresponds to Mic in.

SR2 -SR0 RIGHT

RECORD
SOURCE

0 Mic 0 Mic
1 CD in (R) 1 CD in (L)
2 Video in (R) 2 Video in (L)
3 Aux in (R) 3 Aux in (L)
4 Line in (R) 4 Line in (L)
5 Stereo mix (R) 5 Stereo mix (L)
6 Mono mix 6 Mono mix
7 Phone 7 Phone

Table 5 Record Select Register Function

SL2-SL0 LEFT RECORD SOURCE

RECORD GAIN REGISTERS (INDEX 1Ch AND 1Eh)

1Ch is for the stereo input and 1Eh i s for the optional spec ial purpos e correl ated audio Mic channel.
Each step corresponds to 1.5dB. 22.5dB corresponds to 0F0Fh and 000Fh respectively. The MSB of

the register is the m ute bit. When this bi t is set to 1 the level for that channel(s) is set at ­The default value is 8000h, which corresponds to 0dB gain with mute on.

MUTE GX3...GX0 FUNCTION

0 1111 +22.5dB gain
0 0000 0dB gain

1 xxxxx -∞dB gain

Table 6 Record Gain Register Function

∞dB.

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GENERAL PURPOSE REGISTER (INDEX 20h)

This register is used to control several miscel l aneous functions of the WM9701A.
Below is a summary of each bit and its f unction. Only the MIX, MS and LPBK bits are supported by

WM9701A. The MS bit controls the Mic select or. The LPBK bit enables loop bac k of the ADC output
to the DAC input without involving the AC-link, allowing for full syst em performanc e measurement s.
The function default value is 0000h which i s all off.

BIT FUNCTION WM9701A

SUPPORT

POP PCM out path and mute, 0 = pre 3D, 1 = post 3D No
ST Simulated stereo enhancement, on/off 1 = on No
3D 3D stereo enhancement on/off, 1 = on No
LD Loudness (bass boost) on/off, 1 = on No
LLBK Loc al l oop back - for modem, line Codec No
RLBK Remote loop bac k - for modem, line Codec No
MIX Mono output select 0 = Mix, 1 = Mic Yes
MS Mic select 0 = Mic1, 1 = Mic2 Yes
LPBK ADC/DAC/ loop back mode Yes

Table 7 General Purpose Register Function

3D CONTROL REGISTER (INDEX 22h)

This optional register is used to control the centre and/or depth of the 3D stereo enhancement
function built into of the AC’97 component. This feat ure i s not supported by the WM9701A.

MODEM SAMPLE RATE REGISTER (INDEX 24h)

This register controls what sample rate AC’97 is sending or receiving samples for the optional
Modem in and out. This feature is not supported by WM9701A.

POWER DOWN CONTROL/STATUS REGISTER (INDEX 26h)

This read/write register is used to program power down states and monitor subsystem readines s.
The lower half of this register is read only st atus , a 1 i ndic ating t hat the s ubsec ti on i s “ready”. Ready
is defined as the subsec tion able to perform in its nom inal st ate. W hen t his regis ter is written to the
bit values that come in on AC-link will have no effect on read only bits 0 to 7.

When the AC-link “Codec Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1 it indicates that the
AC-link and WM9701A control and status registers are in a fully operational state. The AC’97
controller must further probe this power down Control/Status Regi ster to determine exactly which
subsections, if any, are ready.

READ BIT FUNCTION

MDM Modem section ready – not supported
REF VREFs up to nominal level
ANL Analogue mixers, etc ready
DAC DAC section ready to accept data
ADC ADC secti on ready t o t ransmit data

Table 8 Power Down Status Register Function

The power down modes are as follows. The first three bits are to be used individuall y rather than in
combination with each other. The l ast bit P R3 can be us ed in c om binat ion with P R2 or by it sel f. P R0
and PR1 control the PCM ADCs and DACs only. PR7 independently c ontrols the optional m odem
ADC and DAC, not supported by WM9701A.

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WRITE BIT FUNCTION

PR0 PCM in ADCs and input Mux power down
PR1 PCM out DACs power down
PR2 Analogue mixer power down (VREF still on)
PR3 Analogue mixer power down (VREF off)
PR4 Digital interface (A C-Li nk) power down (external clock off)
PR5 Internal clock disable
PR6 HP amp power down - not supported
PR7 Modem ADC/DAC off - not supported

Table 9 Power Down Control Register Function

NORMAL

PR0 = 1

PR0 = 0 AND

ADC = 1

ADCs OFF

READY = 1

PR1 = 1 PR2 = 1 PR4 = 1

DAC = 1

DACs OFF

PR1

PR2 = 0 AND

ANL = 1

DEFAULT

PR0

PR1 = 0 AND

ANALOGUE

OFF PR2 OR

PR3

DIGITAL I/F

OFF PR4

WARM
RESET

COLD RESET

SHUT OFF

CODA LINK

Figure 12 An Example of WM9701A Power Down/Power up Flow

Figure 12 illustrates one example procedure to do a complete power down of WM9701A. From
normal operation sequential writes to the power down Register are performed to power down
WM9701A a piece at a time. After everything has been shut off, a final write (of PR4) can be
executed to shut down the WM9701A’s di gi tal interface (AC-link).

The part will remain in sleep mode with all its registers holding their static values. To wake up
WM9701A, the AC’97 cont roller will send a pulse on the sync line issuing a warm res et. This will
restart WM9701A’s digital interface (resetting PR4 to 0). W M9701A can also be woken up with a
cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them to
their default states. W hen a section is powered back on, the power down Control/Status regi ster
(index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any
operation that requires it.

Alternatively if RESETB is held low, all PR bits are held set so the device is held powered off until
RESETB is taken high again.

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ADCs OFF

PR0

PR1 = 1

PR1 = 0 AND

DAC = 1

DACs OFF

PR2 = 1 PR4 = 1

PR1

PR2 = 0 AND

ANL = 1

ANALOGUE

OFF PR2

OR PR3

DIGITAL I/F

OFF PR4

WARM RESET

SHUT OFF

CODA LINK

Figure 13 WM9701A Power Down/Flow with Analogue Still Alive

Figure 13 illustrates a state when all the mixers should work with the st atic volum e settings that are
contained in their associated registers. This is used when the user could be playing a CD (or
external LINE_IN source) through WM9701A to the s peakers but have most of the system in low
power mode. The procedure for this foll ows the previous except that the analogue mixer is never
shut down.

POWERDOWN CONTROL/STATUS REGISTER (INDEX 26H)

Also when RESETB pin is asserted low, all PR bits are over-ridden and the entire device is powered
off to ultra low power state for as long as RESETB = low. On releasing RESETB, the device is reset
(all active) and powered up.

RESERVED REGISTERS (INDEX 28h - 58h)

These registers are reserved by AC’97 and have no function on WM9701A.

VENDOR RESERVED REGISTERS (INDEX 5AH - 7Ah)

These are reserved for future use and are vendor specific. Do not write to thes e registers unless the
Vendor ID register has been checked firs t to ensure that the driver knows the sourc e of the AC’97
component. Values stored in this register are used to provi de test modes for the manufacturer.

VENDOR SPECIFIC GAIN CONTROL REGISTERS – (INDEX 70H TO 74H)

Not used in the WM9701A.

VENDOR ID REGISTERS (INDEX 7Ch - 7Eh)

This register is for specific vendor identificat ion if so des ired. The ID met hod is Microsoft ’s Plug and
Play Vendor ID code. The first character of that ID i s F7 to F0, the second charac ter S7 to S0 and
the third T7 to T0. These three charac ters are ASCII encoded. The REV7 to REV 0 field is for the
Vendor Revision number. In WM9701A the vendor ID is set to WML0.

Wolfson is a registered Microsoft Plug and Pl ay vendor.

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SERIAL INTERFACE REGISTER MAP

The following table shows the function and address of the various control bits that are loaded
through the serial interface duri ng write operat i ons.

Reg.

Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

Num.

00h

Reset X SE4 SE3 SE2 SE1 SEO ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0140h

02h

Master
Volume

06h

Master Vol.
Mono

0Ah

PCBEEP
Volume

OCh

Phone
Volume

OEh

Mic VolumeMuteXXXXXXXX20dBX GN4 GN3 GN2 GN1 GN0 8008h

10h

Line In
Volume

12h

CD Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

14h

Video
Volume

16h

Aux
Volume

18h

PCM Out
Vol.

1Ah

Record
Select

1Ch

Record
Gain

20h

General
Purpose

26H

Power­down
Ctrl/Stat

28h

ReservedXXXXXXXXXXXXXXXXX

5Ah

Vendor
Reserved

7Ah

Vendor
Reserved

7Ch

Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 574D

7Eh

Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7REV6REV5REV4REV3REV2REV1REV04COO

Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MM0 8000h

Mute X X X X X X X X X X MM4 MM3 MM2 MM1 MM0 8000h

Mute X X X X X X X X X X PV3 PV2 PV2 PV0 X 8000h

Mute X X X X X X X X X X GN4 GN3 GN2 GN1 GN0 8008h

Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

X X X X SL2 SL1 SL0 X X X X X SR2 SR1 SR0 0000h

Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 GR0 8000h

X X X X X X MIX MS LPBK X X X X X X X 0000h

X X PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Fh

XXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXX

Table 10 Serial Interface Register Map Description

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

21

WM9701A Production Data RECOMMENDED EXTERNAL COMPONENTS

INPUTS

AC-LINK

Notes:

1. C1 to C19 and C21 should be as
close to WM9701A as possible.

2. AGND and DGND should
be connected as close to
WM9701A as possible.

MIXER

DVDD

C1

DGND

AVDD

1

DVDD1

9

DVDD2

C2

C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17

4

DVSS1

7

DVSS2

12

PCBEEP

13

PHONE

14

AUXL

15

AUXR

16

VIDEOL

17

VIDEOR

18

CDL

19

CDGND

20

CDR

21

MIC1

22

MIC2

23

LINEINL

24

LINEINR

5

SDATAOUT

6

BITCLK

8

SDATAIN

10

SYNC

11

RESETB

XTLIN

2

C26

VREFOUT

LINEOUTL
LINEOUTR
MONOOUT

XTLOUT

3

XT

DGND

AVDD1
AVDD2

AVSS1
AVSS2

C27

CAP2
VREF

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

25
38

26
42

32
27

28

35
36
37

29
30

31
33

34
39
40

41
43
44
45
46

47
48

C3 C4

C23

+
+

C24
C25

+

AGND

C18 C19

STEREO OUTPUT

MONO OUTPUT

AGND

C20

C22

+

C21

+

Figure 14 External Components Diagram

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

22

Production Data WM9701A

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

C1 to C4 10nF De-coupling f or DVDD and AVDD
C5 to C17 470nF AC coupling capacitors for set ting DC level of analogue inputs.

C18 1µF
C19 0.1µF
C20 10µF
C21 0.1µF
C22 10µF
C23 to C25 10µF Output AC coupling caps to remove V RE F DC l evel from outputs.
C26 and C27 22pF Optional capac it ors for better crystal frequency stability.
XT 24.576 MHz AC’97 master clock frequency. A bias resistor is not required, but if connected will not

Table 11 External Component Recommendations

SUGGESTED

VALUE

DESCRIPTION

Value chosen to give corner frequenc y below 20Hz for minimum 10K input i mpedance.
Reference de-coupling capacit ors for ADC, DAC, Mixer and CAP2 references.

Ceramic type or sim i l ar.

affect operation if value i s large (above 1MΩ).

RECOMMENDATIONS FOR 3.3V OPERATION

The device’s performance with AVDD = 3.3V is shown in Electrical Characteristics.
In 3.3V analogue operation, mid-rail reference scales to 1.5V. All ADC and DAC references are

ths

of their nominal 5V value. I nput and output si gnals that are 1Vrm s in 5V appl ications, scale to

3/5
660mVrms in 3.3V applications . If 1Vrm s output is required, the m ixer gain adjust PGAs need to be
increased by 3 times 1. 5dB steps.

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

23

WM9701A Production Data PACKAGE DIMENSIONS

FT: 48 PIN TQFP (7 x 7 x 1.4 mm)

b

48

D1

D

DM003.B

e

2536

2437

E1 E

13

121

θ

c

A1

A

A2

-C-

SEATING PLANE

C

ccc

Dimensions

Symbols

(mm)

MIN NOM M AX
A
A

1

A

2

b
c
D
D

1

E
E

1

e
L

θ

----- ----- 1.60

0.05 ----- 0.15

1.35 1.40 1.45

0.17 0.22 0.27

0.09 ----- 0.20

9.00 BSC

7.00 BSC

9.00 BSC

7.00 BSC

0.50 BSC

0.45 0.60 0.75

o

0

3.5

o

7

o

Tolerances of Form and Position

ccc

REF:

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MS-026, VARIATION = BBC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

0.08

JEDEC.95, MS-026

L

WOLFSON MICROELECTRONICS LTD. PD Rev 3.2 January 2001

24