Atmel AT93C46-10PU, AT93C46-10SU, AT93C46-10TU, AT93C46W-10SU, AT93C46Y1-10YU Schematics

Features

•Low-voltage and Standard-voltage Operation

–2.7 (VCC = 2.7V to 5.5V)

–1.8 (VCC = 1.8V to 5.5V)

•User-selectable Internal Organization

–1K: 128 x 8 or 64 x 16

•Three-wire Serial Interface

•2 MHz Clock Rate (5V)

•Self-timed Write Cycle (10 ms max)

•High Reliability

–Endurance: 1 Million Write Cycles

–Data Retention: 100 Years

•Automotive Grade Devices Available

•8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP and 8-ball dBGA2 Packages

Description

The AT93C46 provides 1024 bits of serial electrically erasable programmable readonly memory (EEPROM), organized as 64 words of 16 bits each (when the ORG pin is connected to VCC), and 128 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT93C46 is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages.

The AT93C46 is enabled through the Chip Select pin (CS) and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the DO pin. The Write cycle is completely self-timed, and no separate Erase cycle is required before Write. The Write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.

The AT93C46 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.

Table 1. Pin Configurations

Pin Name	Function
CS	Chip Select
SK	Serial Data Clock
DI	Serial Data Input
DO	Serial Data Output
GND	Ground
VCC	Power Supply
ORG	Internal Organization
DC	Don’t Connect

	8-lead SOIC			8-lead dBGA2
				VCC			CS
CS	1	8	VCC		8	1
SK	2	7	DC	DC	7	2	SK
DI	3	6	ORG	ORG	6	3	D1
DO	4	5	GND	GND	5	4	D0

Bottom View

8-lead PDIP

CS		1	8		VCC
SK		2	7		DC
DI		3	6		ORG
DO		4	5		GND

8-lead Ultra Thin mini-MAP (MLP 2x3)

8-lead SOIC

Rotated (R)

(1K JEDEC Only)

DC		1	8		ORG
VCC		2	7		GND
CS		3	6		DO
SK		4	5		DI

VCC				CS		8-lead TSSOP
	8		1		CS	1	8	VCC
DC				SK
	7		2		SK	2	7	DC
ORG				DI
	6		3		DI	3	6	ORG
GND				DO
	5		4		DO	4	5	GND

Bottom View

Three-wire

Serial

EEPROM

1K (128 x 8 or 64 x 16)

AT93C46

Note: Not recommended for new design; please refer to AT93C46D datasheet.

5140B–SEEPR–2/07

1

Absolute Maximum Ratings*

......................................Operating Temperature

−55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

Storage Temperature .........................................

−65°C to +150°C

age to the device. This is a stress rating only, and

functional operation of the device at these or any

Voltage on Any Pin

other conditions beyond those indicated in the

with Respect to Ground ........................................

−1.0V to +7.0V

operational sections of this specification is not

Maximum Operating Voltage

6.25V

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

DC Output Current

5.0 mA

device reliability

Figure 1. Block Diagram

Note: When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the “x 16” organization is selected. The feature is not available on the 1.8V devices.

For the AT93C46, if “x 16” organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends using the AT93C46A device. For more details, see the AT93C46A datasheet.

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AT93C46

Table 2. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)

Symbol		Test Conditions	Max	Units	Conditions
COUT		Output Capacitance (DO)	5	pF	VOUT = 0V
CIN		Input Capacitance (CS, SK, DI)	5	pF	VIN = 0V
Note: 1.	This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics

Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, TAE = -40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted)

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

VCC1

Supply Voltage

1.8

5.5

V

VCC2

Supply Voltage

2.7

5.5

V

VCC3

Supply Voltage

4.5

5.5

V

ICC

Supply Current

VCC = 5.0V

READ at 1.0 MHz

0.5

2.0

mA

WRITE at 1.0 MHz

0.5

2.0

mA

ISB1

Standby Current

VCC = 1.8V

CS = 0V

0

0.1

µA

ISB2

Standby Current

VCC = 2.7V

CS = 0V

6.0

10.0

µA

ISB3

Standby Current

VCC = 5.0V

CS = 0V

17

30

µA

IIL

Input Leakage

VIN = 0V to VCC

0.1

1.0

µA

IOL

Output Leakage

VIN = 0V to VCC

0.1

1.0

µA

VIL1(1)

Input Low Voltage

2.7V ≤ VCC ≤ 5.5V

−0.6

0.8

V

V

IH1

(1)

Input High Voltage

2.0

V

CC

+ 1

VIL2(1)

Input Low Voltage

1.8V ≤ VCC ≤ 2.7V

−0.6

VCC x 0.3

V

V

IH2

(1)

Input High Voltage

V

CC

x 0.7

V

CC

+ 1

VOL1

Output Low Voltage

2.7V ≤ VCC

≤ 5.5V

IOL = 2.1 mA

0.4

V

VOH1

Output High Voltage

IOH = −0.4 mA

2.4

V

VOL2

Output Low Voltage

1.8V ≤ VCC

≤ 2.7V

IOL = 0.15 mA

0.2

V

VOH2

Output High Voltage

IOH = −100 µA

VCC – 0.2

V

Note:

1.

VIL min and VIH max are reference only and are not tested.

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5140B–SEEPR–2/07

Table 4. AC Characteristics

Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted)

Symbol	Parameter	Test Condition				Min	Typ	Max	Units
	SK Clock	4.5V ≤ VCC	≤ 5.5V			0		2
fSK	Frequency	2.7V ≤ VCC	≤ 5.5V			0		1	MHz
		1.8V ≤ VCC	≤ 5.5V			0		0.25
tSKH		4.5V ≤ VCC	≤ 5.5V			250
	SK High Time	2.7V ≤ VCC	≤ 5.5V			250			ns
		1.8V ≤ VCC	≤ 5.5V			1000
tSKL		4.5V ≤ VCC	≤ 5.5V			250
	SK Low Time	2.7V ≤ VCC	≤ 5.5V			250			ns
		1.8V ≤ VCC	≤ 5.5V			1000
tCS	Minimum CS	4.5V ≤ VCC	≤ 5.5V			250
	Low Time	2.7V ≤ VCC	≤ 5.5V			250			ns
		1.8V ≤ VCC	≤ 5.5V			1000
tCSS				4.5V ≤ VCC	≤ 5.5V	50
	CS Setup Time	Relative to SK		2.7V ≤ VCC	≤ 5.5V	50			ns
				1.8V ≤ VCC	≤ 5.5V	200
tDIS				4.5V ≤ VCC	≤ 5.5V	100
	DI Setup Time	Relative to SK		2.7V ≤ VCC	≤ 5.5V	100			ns
				1.8V ≤ VCC	≤ 5.5V	400
tCSH	CS Hold Time	Relative to SK				0			ns
tDIH				4.5V ≤ VCC	≤ 5.5V	100
	DI Hold Time	Relative to SK		2.7V ≤ VCC	≤ 5.5V	100			ns
				1.8V ≤ VCC	≤ 5.5V	400
tPD1	Output Delay to			4.5V ≤ VCC	≤ 5.5V			250
	“1”	AC Test		2.7V ≤ VCC	≤ 5.5V			250	ns
				1.8V ≤ VCC	≤ 5.5V			1000
tPD0	Output Delay to			4.5V ≤ VCC	≤ 5.5V			250
	“0”	AC Test		2.7V ≤ VCC	≤ 5.5V			250	ns
				1.8V ≤ VCC	≤ 5.5V			1000
tSV	CS to Status			4.5V ≤ VCC	≤ 5.5V			250
	Valid	AC Test		2.7V ≤ VCC	≤ 5.5V			250	ns
				1.8V ≤ VCC	≤ 5.5V			1000
tDF	CS to DO in High	AC Test		4.5V ≤ VCC	≤ 5.5V			100	ns
	Impedance	CS = VIL		2.7V ≤ VCC	≤ 5.5V			100
				1.8V ≤ VCC	≤ 5.5V			400
tWP	Write Cycle Time							10	ms
				4.5V ≤ VCC	≤ 5.5V	0.1	3		ms
Endurance(1)	5.0V, 25°C					1M			Write Cycles

Note: 1. This parameter is characterized and is not 100% tested.

4 AT93C46

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AT93C46

Table 5. Instruction Set for the AT93C46

		Op	Address			Data
Instruction	SB	Code	x 8	x 16	x 8		x 16	Comments
READ	1	10	A6 – A0	A5 – A0				Reads data stored in memory, at
								specified address
EWEN	1	00	11XXXXX	11XXXX				Write enable must precede all
								programming modes
ERASE	1	11	A6 – A0	A5 – A0				Erases memory location An – A0
WRITE	1	01	A6 – A0	A5 – A0	D7 – D0		D15 – D0	Writes memory location An – A0
ERAL	1	00	10XXXXX	10XXXX				Erases all memory locations. Valid
								only at VCC = 4.5V to 5.5V
WRAL	1	00	01XXXXX	01XXXX	D7 – D0		D15 – D0	Writes all memory locations. Valid
								only at VCC = 4.5V to 5.5V
EWDS	1	00	00XXXXX	00XXXX				Disables all programming instructions

Note: The Xs in the address field represent DON’T CARE values and must be clocked.

Functional

Description

The AT93C46 is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location.

READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.

ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part.

ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the selected memory location has been erased and the part is ready for another instruction.

WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle tWP starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Read/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed programming cycle tWP.

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5140B–SEEPR–2/07

ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.

WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%.

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.

Timing Diagrams

Figure 2. Synchronous Data Timing

s

Note: 1. This is the minimum SK period.

Table 6. Organization Key for Timing Diagrams

		AT93C46 (1K)
I/O	x 8		x 16
AN	A6		A5
DN	D7		D15

6 AT93C46

5140B–SEEPR–2/07