Apple MacBook 12'' Retina A1534 Schematics

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TABLE_TABLEOFCONTENTS_ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

87 6 5

4 21

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

11/21/2014

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

PRODUCT SAFETY REQUIREMENTS:

Schematic / PCB #’s

J92 MLB NEWARK - DVT

ALIASES RESOLVED

1 OF 75

<PART_DESCRIPTION>

<SCH_NUM>

<ECO_DESCRIPTION>

1 OF 130

SPI+SWD Debug Connector

J92_DEVMLB

61

37

07/23/2013

Temperature Sensing

J92_DEVMLB

55

36

09/12/2013

Voltage & Current Sensing

J92_DEVMLB

54

35

02/07/2014

SMBus Connections

J43_MLB

53

34

10/24/2012

SMC Project Support

J43_MLB

52

33

10/24/2012

SMC Shared Support

J92_DEVMLB

51

32

10/11/2013

SMC

J92_DEVMLB

50

31

10/11/2013

Keyboard & Trackpad Conn

J92_DEVMLB

48

30

03/26/2014

E85 FLEX CONNECTOR

DEV_MLB

47

29

04/17/2014

Host Port Micro

DEV_LIO

46

28

04/30/2014

High Speed MUXing

DEV_MLB

45

27

04/17/2014

Low Speed MUXing

J92_DEVMLB

44

26

07/08/2014

Camera 2 of 2

J92_DEVMLB

40

25

10/10/2013

Camera 1 of 2

J92_DEVMLB

39

24

07/24/2013

SSD Support

J92_DEVMLB

37

23

09/11/2013

WIFI/BT: MODULE

J72_MLB

35

22

11/13/2012

LPDDR3 DRAM Channel B (0-63)

(MASTER)

25

21

(MASTER)

LPDDR3 DRAM Channel A (0-63)

(MASTER)

23

20

(MASTER)

LPDDR3 VREF MARGINING

J92_DEVMLB

22

19

06/28/2013

Project Chipset Support

J92_DEVMLB

20

18

08/01/2013

Chipset Support

J92_DEVMLB

19

17

06/28/2013

CPU/PCH Merged XDP

J92_DEVMLB

18

16

09/16/2013

PCH GPIO/MISC/LPIO

J92_DEVMLB

16

15

08/14/2013

PCH PCIe/USB/LPC/SPI/SMBus

J92_DEVMLB

15

14

06/28/2013

PCH PM/PCI/GFX

J92_WILL

14

13

04/10/2013

PCH Audio/JTAG/SATA/CLK

J92_WILL

13

12

04/10/2013

PCH Decoupling

J92_DEVMLB

12

11

09/23/2013

CPU Decoupling

J92_DEVMLB

10

10/01/2013

CPU/PCH GROUNDS

J92_WILL

9

04/10/2013

CPU/PCH POWER

J92_DEVMLB

8

10/01/2013

CPU DDR3/LPDDR3 Interfaces

J92_LS_MLB

7

07/17/2013

CPU Misc/JTAG/CFG/RSVD

J92_WILL

6

04/10/2013

CPU GFX/DC_TEST

J92_WILL

5

04/10/2013

PD PARTS

J43_MLB

4

10/24/2012

J92 BOM Variants

J43_MLB

3

10/24/2012

BOM Configuration

J43_MLB

2

10/24/2012

MASTER

130

MASTER

75

Debug Support

07/15/2013

120

J92_DEVMLB

74

Reference

04/08/2014

118

J92_DEVMLB

73

Project Specific Constraints

09/11/2013

117

J92_DEVMLB

72

SMC Constraints

08/01/2013

116

J92_DEVMLB

71

Camera Constraints

11/16/2011

115

MASTER

70

NAND CONSTRAINTS

05/07/2013

114

J92_LS_MLB

69

Memory Constraints

04/17/2014

113

DEV_MLB

68

PCH Constraints 2

04/17/2014

112

DEV_MLB

67

PCH Constraints 1

07/08/2014

111

J92_DEVMLB

66

CPU Constraints

10/24/2012

110

J43_MLB

65

PCB Rule Definitions

10/24/2012

105

J41_MLB

64

Project FCT/NC/Aliases

07/08/2014

104

J92_DEVMLB

63

Func Test / No Test

07/08/2014

103

J92_DEVMLB

62

J92 Signal Aliases

(MASTER)

102

(MASTER)

61

Memory Signal Swaps

10/24/2012

100

J43_MLB

60

Power Aliases

02/12/2014

89

J92_DEVMLB

59

SSD SR, Power, & Debug

10/07/2013

88

J92_SSD

58

SSD NAND Flash & ROM

10/10/2013

87

J92_DEVMLB

57

SSD Controller (4 of 4)

02/11/2014

86

J92_SSD

56

SSD Controller (3 of 4)

10/10/2013

85

J92_DEVMLB

55

SSD Controller (2 of 4)

02/11/2014

84

J92_SSD

54

SSD Controller (1 of 4)

09/25/2013

83

J92_DEVMLB

53

eDP Display Connector

09/20/2013

81

J92_DEVMLB

52

Power Control

07/24/2013

80

J92_DEVMLB

51

Power FETs

04/04/2014

78

J92_DEVMLB

50

Misc Power Supplies

10/01/2013

77

J92_DEVMLB

49

LCD Backlight Driver

04/04/2014

76

J92_DEVMLB

48

1.05V S0 Power Supply

04/17/2014

75

DEV_MLB

47

5V & 3.3V Power Supplies

04/04/2014

74

J92_DEVMLB

46

LPDDR3 Supply

04/17/2014

73

DEV_MLB

45

CPU VR12.5 VCC Power Stage

10/09/2012

72

J43_MLB

44

CPU VR12.6 VCC Regulator IC

04/04/2014

71

J92_DEVMLB

43

PBus Supply & Battery Charger

02/04/2013

70

J92_WILL

42

3.3V G3Hot Regulator

10/24/2012

69

J43_MLB

41

Battery Connector

04/17/2014

67

CARA_J92

40

AUDIO: CONNECTORS

09/19/2013

64

J92_DEVMLB

39

Audio:Right Speaker Amps

820-00045

PCBF,MLB-NEWARK,J92

PCB1 CRITICAL

1

SCHEM,MLB-NEWARK,J92

SCH

051-00107

CRITICAL

09/19/2013

63

J92_DEVMLB

38

Audio:Left Speaker Amps

Contents

(.csa)

Date

SyncPage

Table of Contents

MASTER

1

MASTER

Contents

Date

(.csa)

Page Sync

WWW.AliSaler.Com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

CPU DRAM SPD Straps

Programmable Parts

BOM Groups

CFG 2

8GB

HYNIX

Module Parts

1

MICRON

Alternate Parts

00

SAMSUNG

1

2GB

0 1

0

CFG 0

1

10

1

CFG 3

4GB QDP

1

4GB DDP

DRAM Parts

CFG 1

VENDOR

CPU DRAM CFG Chart

0

ELPIDA

0

SIZE

SSD POP Parts

0

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:H,DRAM_TYPE:ELPIDA_8GB

DRAM:ELP_8GB

DRAM:HYN_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:H,DRAM_TYPE:HYNIX_8GB

DRAM:ELP_2GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_2GB

NXP alt for Diodes dual

376S1129

ALL

376S0855

338S00055

CRITICALSSD_CTRL

S1X:A2

1

IC,S1-X,CONTROLLER,A2,841(312)B,FCBGA

CRITICAL

S1X:A1

SSD_CTRL

1338S1288

IC,S1-X,CONTROLLER,A1,841(312)B,FCCSP

DRAM_TYPE:ELPIDA_4GB

CRITICAL

IC,SDRAM,LPDDR-1600,16GBIT,253B FBGA

333S0740 2

U2300,U2500

IC,SDRAM,LPDDR-1600,32GBIT,253B FBGA

333S0731 2

U2300,U2500

DRAM_TYPE:HYNIX_8GB

CRITICAL

IC,SDRAM,LPDDR-1600,16GBIT,253B FBGA

U2300,U2500

998-6454 2

DRAM_TYPE:ELPIDA_4GB_QDP

CRITICAL

IC,SDRAM,LPDDR-1600,8GBIT,253B FBGA

998-6453

U2300,U2500

2

DRAM_TYPE:ELPIDA_2GB

CRITICAL

2998-6486

U2300,U2500

DRAM_TYPE:HYNIX_2GB

CRITICAL

IC,SDRAM,LPDDR-1600,8GBIT,253B FBGA

IC,SDRAM,LPDDR-1600,16GBIT,253B FBGA

DRAM_TYPE:HYNIX_4GB_QDP

2

U2300,U2500

CRITICAL

333S00028

IC,SDRAM,LPDDR-1600,16GBIT,253B FBGA

DRAM_TYPE:HYNIX_4GB

2

U2300,U2500

CRITICAL

333S0730

Toshiba alt for Diodes dual

ALL

376S0855

376S00074

NXP alt for Diodes single

ALL

376S1089 376S1128

CRITICAL

2333S0741

IC,SDRAM,LPDDR-1600,32GBIT,253B FBGA

DRAM_TYPE:ELPIDA_8GB

U2300,U2500

J11/J13 MLB DYMAX ADHESIVE 29993-SC 0.4G

1 GLUE946-3892 CRITICAL

IC,CPU,BW,QGKZ,QS,E0,2/2,0.8,4.5W,.8,B1234

337S00054

CPU:0.8GHZ

1 U0500 CRITICAL

CRITICALU05001

CPU:1.1GHZ

337S00099

IC,CPU,BW,QH2Z,PRQ,F0,2/2,1.1,5W,.85,B1234

CRITICALU05001

CPU:1.2GHZ

337S00098

IC,CPU,BW,QH2V,PRQ,F0,2/2,1.2,5W,.9,B1234

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:ELPIDA_4GB

DRAM:ELP_4GB

DRAM:HYN_4GB_QDP

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB_QDP

128S0334

Kemet alt to Sanyo

ALL

128S0393

ALL

138S0648138S0703

Murata alt to Taiyo Yuden

372S0186

NXP alt to Diodes

ALL

372S0185

376S1053

Diodes alt to Fairchild

376S0604

ALL

IC,SMC12-B1,40MHZ/50DMIPS MCU,7X7,168BGA

U5000 CRITICAL338S1231

SMC:BLANK

1

DRAM:ELP_4GB_QDP

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB_QDP

DRAM:HYN_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:HYNIX_4GB

DRAM:HYN_2GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_2GB

XDP

MLB_DEBUG:PROD

XDP_CONN,XDP,HPMBB:SSP0,HPMVBUS:VDET

MLB_DEBUG:PVT

333S0733

CRITICAL

1

S1X_DRAM:ELPIDA

SSD_DRAM

IC,LPDDR2,128MX32,1.2V,ELPIDA 28NM,312B

685-00004

SSDRAM:A1_HYN

U8400

1

CRITICAL

POP,MLB,S1X-A1,HYN-4GBIT,X261

685-00003

SSDRAM:A1_ELP

CRITICAL

1

U8400

POP,MLB,S1X-A1,ELP-4GBIT,X261

SSDRAM:A0_HYN

339S0244

U8400

CRITICAL

1

POP,S1-X CONTROLLER+4GBITS HYN,841B,FCBGA

SSDRAM:A0_ELP

339S0243

CRITICAL

U8400

1

POP,S1-X CONTROLLER+4GBITS ELP,841B,FCBGA

1 U0500 CRITICAL

CPU:1.3GHZ

337S00097

IC,CPU,BW,QH2R,PRQ,F0,2/2,1.3,5W,.9,B1234

SSD_DRAM

IC,LPDDR2,128MX32,1.2V,HYNIX 29NM,312B

S1X_DRAM:HYNIX

333S0694 1

CRITICAL CRITICAL

1

870-00878

TAPE,CONDUCTIVE,SSD,REEL,X261

SSD_TAPE

IC,MCU,LPC11U37,128KB/12KB,TFBGA48

1 CRITICALU4600337S4638

HPM:BLANK

U6100

BOOTROM_MAC:BLANK

335S1010 CRITICAL1

64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO

SSDROM_MAC:BLANK

CRITICALU88001335S0966

IC,SPI SERIAL FLASH,64M BITS,1.8V,WLCSP

LABEL,BARCODE,2D,1D,CONFIG,MLB,X261

825-7995

LABEL

1

138S0941

ALL

Samsung alt to Murata

138S0789

TFT alt to Cyntec

ALL

107S0251107S0249

ALL

NDK alt to TXC

197S0588197S0591

197S0588

ALL

Epson alt to TXC

197S0590

333S0700

Hynix CAM DRAM alt to Elpida

ALL

333S0704

339S0243 339S0244

Elpida SSD DRAM alt to Hynix

ALL

128S0631

NEC alt to Sanyo

ALL

128S0351

335S0948 335S0966

Winbond alt to Macronix

ALL

128S00008

ALL

128S0380

NEC alt to Sanyo

ALL

Sanyo alt to NEC

311S0426

311S00007

311S0271

Samsung alt to Murata

ALL

311S00008 311S00018

311S0409

Diodes alt to NXP

ALL

740S00004

740S0134

ALL

Kemet alt to Sanyo

Polytronics alt to Wayon

740S00005

740S0190

ALL ALL

Sanyo alt to NEC

128S0296 128S0487

128S0487

ROHM alt to NEC

ALL

128S00012

AOS alt to Vishay

ALL

376S00007

376S1179

Kemet alt to Sanyo

ALL

128S0469

128S00025

376S1080

Diodes alt to OnSemi

ALL

376S0820 376S1194

Vishay alt to OnSemi

376S00036

ALL

333S0704

333S00016

Elpida new die CAM DRAM alt

333S0704

ALL

333S00030

Hynix new die CAM DRAM alt

XDP_CONN,XDP,HPMBB:SSP0,HPMVBUS:VDET

MLB_DEBUG:ENG

ALL

2.4G turbo CPU alt to 2.0G

337S00054337S00061

CPU:0.8GHZ

376S00037

Vishay alt to OnSemi

376S1193

ALL

128S0469

ALL

128S0374

NEC alt to Sanyo

SSDRAM:A1_ELP

ALL

Hynix SSD DRAM alt to Elpida

685-00003685-00004

U5000 CRITICAL

341S00031

SMC:PROG1

IC,SMC-B1,EXTERNAL (VXXXX) PROTO2A, J92

U61001

BOOTROM_WIN:BLANK

CRITICAL335S1009

64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO

SSDROM:PROG

341S00091

U8800 CRITICAL1

S1-X SSD BOOTROM, UI64

SSDROM_WIN:BLANK

CRITICALU88001335S0948

IC,SPI SERIAL FLASH,64M BITS,1.8V,WLBGA

CRITICALU6100

BOOTROM:PROG

1

341S00191

EFI ROM,MLB (VXXX) DVT,X261

U61001335S1029 CRITICAL

BOOTROM_MIC:BLANK

64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO

HPM:PROGU4600 CRITICAL1

341S00190

IC,HPM (VXXX) DVT,X261

CAM_FREQ:24M,CAM_XTAL:NO,EDP,RSMRST:SMC,PGOOD8:SLP_S4,SSD_LPSR:S3

MLB_MISC

ALTERNATE,COMMON,CCSAK,MLB_MISC,MLB_DEBUG:ENG,MLB_PROGPARTS,EQ:4CH

MLB_COMMON

SYNC_DATE=10/24/2012

SYNC_MASTER=J43_MLB

BOM Configuration

<SCH_NUM>

2 OF 130

2 OF 75

www.qdzbwx.com

WWW.AliSaler.Com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Partial & development BOMs

Common BOM

Top level BOM Variants

Programmable Parts

BOM Groups

ALTERNATE,CMN,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,NO CPU,EL 8GB,TOSH 256G,WIFI FCC,X261

939-00043

341S00198

WIFI ROM (PXXXX) DVT,WW2,X261

WIFI:ETSI

1 CRITICALU3580

BOOTROM:PROG,BT:PROG,SMC:PROG,SSDROM:PROG,HPM:PROG

MLB_PROGPARTS

341S00196

BT ROM (VXX) DVT,2MBIT,X261

CRITICALU35701 BT:PROG

341S00197

WIFI ROM (PXXXX) DVT,WW1,X261

WIFI:FCCU35801 CRITICAL

341S00199

WIFI ROM (PXXXX) DVT,WW3,X261

WIFI:APAC

U35801 CRITICAL

341S00200

WIFI ROM (PXXXX) DVT,IND,X261

WIFI:INDU35801 CRITICAL

685-00003

S1X:A2,S1X_DRAM:ELPIDA

POP,MLB,S1X-A2,ELP-4GBIT,X261

CMNPTS

CRITICAL

CMN1

685-00014

CMN PTS,PCBA,MLB-NEWARK,J92

685-00004

S1X:A2,S1X_DRAM:HYNIX

POP,MLB,S1X-A2,HYN-4GBIT,X261

685-00014

MLB_COMMON

CMN PTS,PCBA,MLB-NEWARK,J92

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 256G,WIFI IND,J92

639-6614

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 512G,WIFI IND,J92

639-6615

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 512G,WIFI IND,J92

639-6613

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 256G,WIFI IND,J92

639-6612

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 512G,WIFI IND,J92

639-6611

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 256G,WIFI IND,J92

639-6610

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 512G,WIFI IND,J92

639-6609

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 512G,WIFI IND,J92

639-6607

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 256G,WIFI IND,J92

639-6606

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI IND,J92

639-6608

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 512G,WIFI IND,J92

639-6605

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 512G,WIFI APAC,J92

639-6603

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:IND,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 256G,WIFI IND,J92

639-6604

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 256G,WIFI APAC,J92

639-6602

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 512G,WIFI APAC,J92

639-6601

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 256G,WIFI APAC,J92

639-6600

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 512G,WIFI APAC,J92

639-6599

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 512G,WIFI APAC,J92

639-6597

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI APAC,J92

639-6596

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 256G,WIFI APAC,J92

639-6598

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 512G,WIFI APAC,J92

639-6595

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 256G,WIFI APAC,J92

639-6594

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 512G,WIFI APAC,J92

639-6593

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:APAC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 256G,WIFI APAC,J92

639-6592

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 512G,WIFI ETSI,J92

639-6591

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 256G,WIFI ETSI,J92

639-6590

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 512G,WIFI ETSI,J92

639-6589

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 256G,WIFI ETSI,J92

639-6588

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 512G,WIFI ETSI,J92

639-6587

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 256G,WIFI ETSI,J92

639-6586

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 512G,WIFI ETSI,J92

639-6585

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI ETSI,J92

639-6584

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 512G,WIFI ETSI,J92

639-6583

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 256G,WIFI ETSI,J92

639-6582

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 512G,WIFI FCC,J92

639-6579

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 512G,WIFI ETSI,J92

639-6581

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:ETSI,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 256G,WIFI ETSI,J92

639-6580

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,TOSH 256G,WIFI FCC,J92

639-6578

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 256G,WIFI FCC,J92

639-6576

ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.3GHZ,EL 8GB,SAND 512G,WIFI FCC,J92

639-6577

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 512G,WIFI FCC,J92

639-6575

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 512G,WIFI FCC,J92

639-6573

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,TOSH 256G,WIFI FCC,J92

639-6574

ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI FCC,J92

639-6572

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_512GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 512G,WIFI FCC,J92

639-6571

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_512GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 512G,WIFI FCC,J92

639-6569

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:TOSH_256GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,TOSH 256G,WIFI FCC,J92

639-6570

ALTERNATE,CMN,CPU:1.1GHZ,DRAM:ELP_8GB,NAND:SAND_256GB_1Y_128GBIT,WIFI:FCC,SSDRAM:A1_ELP

PCBA,MLB,1.1GHZ,EL 8GB,SAND 256G,WIFI FCC,J92

639-6568

SYNC_MASTER=J43_MLB

J92 BOM Variants

SYNC_DATE=10/24/2012

<SCH_NUM>

3 OF 130

3 OF 75

WWW.AliSaler.Com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

CPU EMI CAN

860-00060

SSD EMI FENCE & CAN

860-00889

860-00864

860-2930

WIFI EMI CAN

CPU Heat Spreader Bosses

DRAM EMI CAN & SLOTs

E85 BTB Connector Boss

4.5OD1.85ID-1.5H

Z0403

1

4.5OD1.85ID-1.5H

Z0404

1

4.5OD1.85ID-1.5H

Z0405

1

OMIT_TABLE

SM

SHLD-J92-EMI-CAN-WIFI

SH0400

1

OMIT_TABLE

SM

SHLD-J92-EMI-CAN-CPU

SH0401

1

OMIT_TABLE

SM

SHLD-CAN-EMI-DRAM-X261

SH0402

1

TH-NSP

SL-1.1X0.4-1.6X0.9-NSP

SL0400

1

TH-NSP

SL-1.1X0.4-1.6X0.9-NSP

SL0401

1

STDOFF-3.3X1.8R0.859H-SM

Z0406

1

SHLD-FENCE-SSD-TOP-X261

SM

SH0403

1

SHLD-CAN-EMI-SSD-BTM-X261

SM

SH0404

1

SH04001 CRITICAL806-7064

CAN,EMI,WIFI,X261

CRITICAL1

806-00400

CAN,EMI,DRAM,TALL,X261

SH0402

CRITICAL1 SH0401

CAN,EMI,CPU,X261

806-00112

PD PARTS

SYNC_DATE=10/24/2012

SYNC_MASTER=J43_MLB

<SCH_NUM>

4 OF 130

4 OF 75

WWW.AliSaler.Com

OUT

OUT OUT OUT OUT OUT OUT OUT OUT

BI BI

DDI1_TXN[0]

DDI1_TXN[1]

DDI1_TXN[2]

DDI1_TXN[3]

DDI1_TXP[0]

DDI1_TXP[1]

DDI1_TXP[2]

DDI1_TXP[3]

DDI2_TXN[0]

DDI2_TXN[1]

DDI2_TXN[2]

DDI2_TXN[3]

DDI2_TXP[0]

DDI2_TXP[1]

DDI2_TXP[2]

DDI2_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

EDP_RCOMP

EDP_TXN0

EDP_TXN1

EDP_TXN2

EDP_TXN3

EDP_TXP0

EDP_TXP1

EDP_TXP2

EDP_TXP3

DDI

(1 OF 20)

EDP

(18 OF 20)

DAISY_CHAIN_NCTF_A44 DAISY_CHAIN_NCTF_C43 DAISY_CHAIN_NCTF_C45

DAISY_CHAIN_NCTF_D2

DAISY_CHAIN_NCTF_D44

DAISY_CHAIN_NCTF_F1

DAISY_CHAIN_NCTF_F3 DAISY_CHAIN_NCTF_F43

DAISY_CHAIN_NCTF_F45

DAISY_CHAIN_NCTF_H2 DAISY_CHAIN_NCTF_H44

RSVD_CB11 RSVD_H15

OUT

OUT OUT OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(MUXed with HDMI

NO_TEST

Internal panel

eDP Port Assignment:

TBT Sink 0

TBT Sink 1

if necessary)

DDI Port Assignments:

NO_TEST

exist between both TP’s on each corner.

Other corner test signals connected in

Each corner of CPU has two testpoints.

MCP Daisy-Chain Strategy:

daisy-chain fashion. Continuity should

63

53 66

53

66

53 66

BGA

OMIT_TABLE

CRITICAL

BROADWELL-MOBILE-Y-B

U0500

AD25

AD26

AG25

AG26

AC25

AC26

AE25

AE26

AD22

AG22

AD21

AG21

AC22

AE22

AC21

AE21

AG16 AE17

Y21

AP41

AD17

AG18

AD18

AA17

AC17

AE18

AC18

W17

BROADWELL-MOBILE-Y-B

BGA

CRITICAL

OMIT_TABLE

U0500

A44 C43 C45

D2 D44 F1

F3

F43

F45

H2

H44

CB11

H15

1/20W MF

1%

24.9

201

R0530

1

2

29 68

29

68

29 68

63

CPU GFX/DC_TEST

SYNC_DATE=04/10/2013SYNC_MASTER=J92_WILL

TP_MCP_DC_A44

TP_MCP_DC_H44

TP_ULX_SPARE1

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<0>

TP_ULX_SSP_SPARE

DP_INT_ML_C_P<3>

DP_INT_ML_C_P<2>

DP_INT_ML_C_P<1>

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<3>

DP_INT_ML_C_N<2>

DP_INT_ML_C_N<1>

DP_INT_ML_C_N<0>

MCP_EDP_RCOMP TP_EDP_DISP_UTIL

DP_INT_AUXCH_C_P

DP_INT_AUXCH_C_N

NC_DP_TBTSNK1_ML_CP<3>

NC_DP_TBTSNK1_ML_CP<2>

NC_DP_TBTSNK1_ML_CP<1>

NC_DP_TBTSNK1_ML_CP<0>

NC_DP_TBTSNK1_ML_CN<3>

NC_DP_TBTSNK1_ML_CN<2>

NC_DP_TBTSNK1_ML_CN<1>

NC_DP_TBTSNK1_ML_CN<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_N<0>

PPVCOMP_S0_CPU

TRUE

MCP_DC_H2_F3

TRUE

MCP_DC_F43_F45

TP_MCP_DC_F1

TP_MCP_DC_D2

TP_MCP_DC_C45

MCP_DC_C43_D44

TRUE

<SCH_NUM>

5 OF 130

5 OF 75

62

8

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(2 OF 20)

MISC

JTAG

THERMAL

PWR

DDR3

PROC_TRST*

PROC_TDO

PROC_TDI

PROC_TCK

PROCPWRGD

PROCHOT*

PREQ*

PRDY*

PECI

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PROC_TMS

BPM0*

CATERR*

PROC_DETECT*

SM_PG_CNTL1

SM_DRAMRST*

BI BI

BI

BI BI

NC NC

NC

NC NC

NC

NC NC

BI

OUT

NC

BI

OUT

IN

OUT

CFG[9]

CFG[8]

CFG[7]

CFG[5]

CFG[4]

CFG[3]

VSS

TD_IREF

RSVD_TP

RSVD

PROC_OPI_RCOMP

CFG[19]

CFG[15]

CFG[14]

CFG[13]

CFG[12]

CFG[10]

CFG[6]

CFG[16] CFG[17] CFG[18]

CFG[11]

CFG[0] CFG[1] CFG[2]

CFG_RCOMP

(19 OF 20)

RESERVED

NC NC NC NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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PAGE TITLE

SHEET

R

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

These can be placed close to J1800

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

TBD: Confirm w/ Intel which still apply for BDW-Y

and are only for debug access

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

(IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPD) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

.

(IPU)

(IPU) (IPU) (IPU) (IPU)

CRITICAL

OMIT_TABLE

BROADWELL-MOBILE-Y-B

BGA

U0500

CM39 CN38 CK36 CM37 CN36 CR35 CN34 CR34

CH39

CK42

CU40 CR41

CF41

CM41

CU36 CU38

CN40 CR39

CH41

CG42

AB2

BL14

CV7 CP7 CT7

NOSTUFF

1K

5%

201

1/20W

MF

R0640

1

2

NOSTUFF

1K

5%

201

1/20W MF

R0639

1

2

NOSTUFF

MF

1/20W

201

5%

1K

R0638

1

2

MF

1/20W 201

5%

1K

NOSTUFF

R0631

1

2

NOSTUFF

1K

5%

201

1/20W MF

R0630

1

2

6

16 66

6

16 66

16

66

16 66

6

16 66

16

66

6

16 66

6

16 66

6

16 66

16

66

16 66

MF

1/20W

49.9

201

1%

R0681

1

2

31 32 44

66

62

5%

1/20W

MF

201

R0610

1

2

201

5% MF

56

1/20W

R0611

12

32 66

31 64

66

PLACE_NEAR=U0500.CG42:12.7mm

10K

5%

1/20W

MF

201

R0620

1

2

16 66

16

66

16 66

12 16 66

16 66

PLACE_NEAR=U0500.CT7:12.7mm

100

1%

201

1/20W

MF

R0652

1

2

PLACE_NEAR=U0500.CP7:12.7mm

121

1%

201

1/20W

MF

R0651

1

2

PLACE_NEAR=U0500.CV7:12.7mm

MF

1/20W

201

200

1%

R0650

1

2

18

61

1%

49.9

1/20W

201

MF

R0680

1

2

OMIT_TABLE

BROADWELL-MOBILE-Y-B

CRITICAL

BGA

U0500

CV27 CT27

CP31 CN32 CV33 CU34 CT33 CP33 CR28 CN28 CR32 CU32

CP27 CU28 CV29 CT29 CM29 CU30 CN30 CV31

CR30

AB6

AJ22

AJ34

AK25

AL20

AL24

AP3 BJ40 BJ42

BT41 BT43

CK6

CL28

CL34

CL8

N18

P33

AA18

AL32

AL34

BJ14

BT15

CK13

Y18

W21

W33

Y33

Y34L40

AL26

AL28

1% 1/20W

201

MF

8.2K

R0685

1

2

1K

5%

201

1/20W MF

EDP

R0634

1

2

SYNC_DATE=04/10/2013SYNC_MASTER=J92_WILL

CPU Misc/JTAG/CFG/RSVD

CPU_SM_RCOMP<0>

CPU_PWRGD

CPU_PROCHOT_R_L

CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

CPU_CFG<1>

CPU_CFG<8>

CPU_CFG<10>

CPU_CFG<0>

CPU_CFG<4>

CPU_CFG_RCOMP

CPU_CFG<1>

CPU_CFG<0>

CPU_CFG<11>

CPU_CFG<18>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<6>

CPU_CFG<10>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_CFG<19>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<7>

CPU_CFG<9>

PP1V05_S0

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TCK

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_CPU_TMS

XDP_BPM_L<0>

CPU_PECI

CPU_CATERR_L

CPU_PROCHOT_L

TP_CPU_MEMVTT_PWR_EN_LSVDDQ

TP_CPU_MEM_RESET_L

TP_MCP_RSVD_Y18

TP_MCP_RSVD_AL32

TP_MCP_RSVD_BJ14 TP_MCP_RSVD_BT15

TP_MCP_RSVD_AA18

TP_MCP_RSVD_AL34

CPU_CFG<3>

MCP_RSVD_CK13

PCH_TD_IREF

CPU_OPI_RCOMP

CPU_CFG<8>

CPU_CFG<2>

CPU_CFG<9>

6 OF 75

6 OF 130

<SCH_NUM>

66

6

16 66

6

16 66

6

16 66

6

16 66

6

16 66

8

11 15 16

17 32 44 46 51 60

64

6

16 66

WWW.AliSaler.Com

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI BI

BI

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI

BI

BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI

(3 OF 20)

MEMORY CHANNEL A

SA_CAA5

SA_CAA0

NOTUSED

SA_CAB5

SA_CAB8

SA_CAB9

SA_DQSN1

SA_DQSN0

SA_DQ5 SA_DQ6

SA_CAB3

SA_DQ9

SM_VREF_DQ1

SM_VCCDDQG

SA_ODT0

SA_CAB0

SA_CAA6

SA_CAA7

SA_CAA1

SA_DQSP7

SA_DQSP6

SA_DQSP5

SA_DQSP4

SA_DQSP3

SA_DQSP2

SA_DQSP1

SA_DQSP0

SA_DQSN7

SA_DQSN6

SA_DQSN5

SA_DQSN4

SA_DQSN3

SA_DQSN2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ45

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ35

SA_DQ34

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ29

SA_DQ28

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ8

SA_DQ7

SA_CS1*

SA_CS0*

SA_CLK1

SA_CKE1

SA_CAA9

SA_CAB6

SA_CAA8

SA_DQ20

SA_DQ19 SA_CAB4

SM_VREF_DQ0

SM_VREF_CA

SA_CKE3

SA_CKE2

SA_CKE0

SA_CLK1*

SA_CAB2

SA_CAB7

SA_CAB1

SA_CLK0

SA_CLK0*

SA_DQ1

SA_DQ4

SA_DQ3

SA_DQ2

SA_DQ0

SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15

SA_CAA3

SA_CAA4

SA_CAA2

(4 OF 20)

MEMORY CHANNEL B

SB_CAA2

SB_CAB5

SB_CAB7

SB_CAA1

SB_CAA3

SB_CAA4

SB_CAB1

SB_CAB2

SB_DQ2

SB_DQ1

SB_ODT0

SB_CAB0

SB_CAA6

SB_CAA7

SB_CAB8

SB_CAB9

SB_DQSP7

SB_DQSP6

SB_DQSP5

SB_DQSP4

SB_DQSP3

SB_DQSP2

SB_DQSP1

SB_DQSP0

SB_DQSN7

SB_DQSN6

SB_DQSN5

SB_DQSN4

SB_DQSN3

SB_DQSN2

SB_DQSN1

SB_DQSN0

SB_DQ63

SB_DQ62

SB_DQ61

SB_DQ60

SB_DQ59

SB_DQ58

SB_DQ57

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ46

SB_DQ45

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ35

SB_DQ34

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ28

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ12

SB_DQ11

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ4

SB_CS1*

SB_CS0*

SB_CK1*

SB_CK1

SB_CK0*

SB_CK0

SB_CAA9

SB_CAA5

SB_CAB6

SB_CAB4

SB_CAA8

SB_CKE3

SB_CKE2

SB_DQ16

SB_DQ30

SB_DQ29

SB_CKE0 SB_CKE1

SB_CAB3

SB_DQ6

SB_DQ22 SB_DQ23

SB_DQ3

SB_DQ0

SB_DQ5

SB_DQ7

SB_CAA0

NOTUSED

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

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4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

61 69

61

69

61 69

20 61 69

61 69

61

20 61 69

20 69

61

20 61 69

61

20 61 69

61

61 69

20 61 69

61 69

20 69

21 64 69

21 69

21 64 69

21 69

21 64 69

21 61 69

61

21 61 69

61

21 61 69

61

61 64 69

61 69

21 61 69

61 69

61 64 69

61 69

21 61 69

61 69

BROADWELL-MOBILE-Y-B

CRITICAL

OMIT_TABLE

BGA

U0500

CE10 CG8 CG6

CC12

CH3

CB9

CE6

CF11

CH5

CG12

CG10

CF9

CB3

CC8

CE4

CE2

CB5

CF5

CC2

CF3

CE12

CE8

CH11 CH9 CA12 CA10

CG2

CG4

CC6

CC4

CA4 CA2

CT17 CV17

CP10 CM10 CN12 CV13 CV10 CT10 CT25 CP25 CN22 CP23

CN14

CN24 CV25 CV23 CT23 CN20 CN18 CT21 CT19 CP19 CP21

CP15

CV19 CV21

BU2 BW2 BW6 BU4 BW4 BT3 BU6 BT5

CN16

BN2 BR2 BN6 BN4 BR6 BR4 BM5

BM3 BT11 BU10

CR16

BW12 BW10

BW8

BU8 BU12

BT9

BN8

BR8 BN12 BN10

CM13

BR12 BR10 BM11

BM9

CV15 CT13 CP13

CU16 CR12 CR24 CR20 BV3 BP3 BV9 BP9

CT15 CU12 CU24 CU20 BV5 BP5 BV11 BP11

CA6

CC14

AP13

AU14

AT13

BGA

BROADWELL-MOBILE-Y-B

OMIT_TABLE

CRITICAL

U0500

AR6 AT5 AT3

AY5

BA8

AW2

AY3

AU2

AU6

AU4

AR2

BA6

AW8

AW10

AW12

BA10

AY11

AU8

BA12

AY9

AR4

AT9

AW4

AW6

AP9

AP11

BA2 BA4 AR8 AP5

AR10 AT11

BK3 BK5

BC6 BE2 BE4 BE6 BC2

BC4 BE10 BC10

BE8

BC8

BG6

BF11 BC12 BE12

BF9 BJ12 BG12

BJ8 BJ10

BG8 BG10

BJ2

BK9 BK11

AM1

AH2

AJ3

AM5

AM3

AJ1

AJ5

AH4

BJ4

AG3

AG1

AD2

AE3

AE1

AG5

AD4

AE5

AM9

AM7

BJ6

AH8

AJ9 AM11

AJ7 AJ11 AH10 AE11

AG7

AE7

AE9

BG2

AG11

AG9

AD8 AD10

BG4

BF3

BF5

BH5 BD5 BD11 BH11 AK2 AF2 AK8 AF8

BH3 BD3 BD9 BH9 AK4 AF4 AK10 AF10

AU10

19

61 64 69

61

69

61 69

20 61 69

61 69

21 61 69

61 69

SYNC_DATE=07/17/2013

SYNC_MASTER=J92_LS_MLB

CPU DDR3/LPDDR3 Interfaces

MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_CAB<6>

MEM_B_DQ<6>

MEM_A_DQS_N<4>

MEM_A_DQS_P<6>

MEM_B_DQ<38> MEM_B_DQ<39>

=MEM_A_BA<0>

MEM_B_DQ<40>

MEM_B_DQ<44>

MEM_B_DQ<36> MEM_B_DQ<37>

MEM_A_CKE<1>

=MEM_B_A<8>

MEM_A_CLK_P<0>

MEM_B_DQ<10>

MEM_B_DQ<14>

MEM_B_DQ<12>

=MEM_A_A<5>

TP_LPDDR3_RSVD1 TP_LPDDR3_RSVD2

=MEM_A_A<2>

=MEM_A_A<1>

=MEM_A_A<0>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<5> MEM_A_DQ<6>

=MEM_A_RAS_L

MEM_A_DQ<9>

CPU_DIMMB_VREFDQ TP_ULX_DDR_VCCDDQG

MEM_A_ODT<0>

=MEM_A_A<13>

MEM_A_CAA<6>

=MEM_A_A<11>

=MEM_A_A<9>

MEM_A_DQS_P<7>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CLK_P<1>

=MEM_A_A<14> =MEM_A_A<15>

MEM_A_DQ<19>

CPU_DIMMA_VREFDQ

CPU_DIMM_VREFCA

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CKE<0>

MEM_A_CLK_N<1>

=MEM_A_WE_L

=MEM_A_A<10>

=MEM_A_CAS_L

MEM_A_CLK_N<0>

MEM_A_DQ<1>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<0>

MEM_A_DQ<13> MEM_A_DQ<14>

=MEM_A_A<8>

=MEM_A_A<7>

=MEM_A_A<6>

MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

=MEM_B_A<6>

=MEM_B_A<2>

=MEM_B_A<10>

=MEM_B_A<9>

=MEM_B_CAS_L

=MEM_B_WE_L

MEM_B_DQ<1>

MEM_B_ODT<0>

=MEM_B_A<13>

MEM_B_CAA<6>

=MEM_B_A<11>

=MEM_B_A<1>

=MEM_B_A<0>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_DQ<9>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CLK_N<1> MEM_B_CLK_P<1>

MEM_B_CLK_N<0> MEM_B_CLK_P<0>

=MEM_B_A<14>

=MEM_B_BA<2>

MEM_B_CAB<6>

=MEM_B_BA<0>

=MEM_B_A<15>

MEM_B_CKE<3>

MEM_B_CKE<2>

MEM_B_CKE<0>

=MEM_B_RAS_L

MEM_B_DQ<3>

MEM_B_DQ<0>

MEM_B_DQ<7>

=MEM_B_A<5>

TP_LPDDR3_RSVD4

TP_LPDDR3_RSVD3

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<25>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<45>

MEM_B_DQ<41>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_CKE<1>

MEM_B_DQ<18>

MEM_B_DQ<15>

=MEM_A_BA<2>

MEM_B_DQ<13>

MEM_B_DQ<11>

MEM_B_DQ<8>

=MEM_B_A<7>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<2>

MEM_B_DQ<4> MEM_B_DQ<5>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<49>

MEM_B_DQ<48>

<SCH_NUM>

7 OF 130

7 OF 75

64

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OUT

IN

OUT

IN

OUT

BI

DCPSUS4

VCCOPIPLL VCCHDAPLL

DCPSUS3

DCPRTC

VCC1_05

VCCUSB2PLL

VCCTS1_5

VCCSUS3_3_RTC

VCCSUS3_3

VCCSPI

VCCSDIO

VCCRTC

VCCHDA

VCCCLK7 VCCCLK5 VCCCLK3

VCCCLK2

VCCCLK1

VCC3_3

VCC1_05_USB

DCPSUSBYP

DCPSUS1

VCCACLKPLL

VCCCLK4

VCCTS3_3

VCCASW

DCPSUS2

VCCDSW3_3

VCCUSB3PHY

VCCUSB3PLL

VCCSUS3_3

VCCCLK6

VCCSATA3PLL

VCC1_05_PHY

VCCPCIEPHY

VCCSATAPHY

OPIICC

USB2

GPIO/LCC USB3MISC

CORE

RTC

(13 OF 20)

SERIAL IO

SPI

HSIO

AZALIA/HDA

VRM/USB2/AZALIA

WPT LP POWER

SUS OSCILLATOR

THERMAL SENSOR

BRW ULX POWER

(12 OF 20)

RSVD

VCC RSVD

VSS

IST_TRIGGER

RSVD

VCCST

VCC

VDDQ

VIDSCLK

VR_EN VR_READY

RSVD

VIDALERT*

VIDSOUT VCCST_PWRGD

IVR_ERROR

RSVD_TP

PWR_DEBUG*

VSS

VCC_SENSE

VCCIO_OUT

RSVD

VCOMP_OUT

NC NC

NC

NC NC NC

NC NC

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

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4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0.

Max load: 300mA

???mA Max

R0800.2:

R0810.2:

R0802.2:

Max load: 300mA

32A Max

1.1A Max (LPDDR3: 1.2V)

1.4A Max (DDR3: 1.5-1.35V)

to avoid any extraneous connections.

NOTE: Aliases not used on CPU supply outputs

Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.

6.3V

10%

0.47UF

CERM-X5R 0201

C0897

1

2

PLACE_NEAR=U0500.AG13:6.35mm

0

0201

MF

1/20W

5%

R0896

12

BYPASS=U0500.V15::6.35mm

0201

10V X5R-CERM

10%

0.1UF

C0895

1

2

10V

X5R-CERM

0201

10%

0.1UF

BYPASS=U0500.AA15::6.35mm

C0892

1

2

X5R-CERM

BYPASS=U0500.AA15::6.35mm

10%

0.1UF

0201

10V

C0891

1

2

BYPASS=U0500.AA15::6.35mm

X5R

6.3V 0201

20%

1UF

C0890

1

2

201

5%

1/20W

MF

PLACE_NEAR=U0500.CH45:50.8mm

100

R0860

1

2

44 66

16 17

46

44

201

1/20W MF

PLACE_NEAR=U0500.CE40:2.54mm

130

1%

R0802

1

2

201

1/20W

MF

PLACE_NEAR=R0810.1:2.54mm

75

1%

R0800

1

2

201

5%

1/20W

MF

PLACE_NEAR=U0500.CD43:38.1mm

43

R0810

12

5%

0

0201

1/20W

MF

R0811

12

0201

5%

0

1/20W

MF

R0812

12

44 66

44

66

CRITICAL

OMIT_TABLE

BGA

BROADWELL-MOBILE-Y-B

U0500

V15

U16

AG14

U30

T21

AG13

AJ45

AG45

AH36

AJ16

T31

T17

AE13

W22

Y22

T27

A26

A28

A30

AK35

AE15

N1 T1 W14

AK23

AK31

AJ28

AL37

AL39

AL30

AJ26

AA1

AB14

AA13

W1

AK29

AK19

AA45

AB38

W45

AA15

T33

N45 T45

A32

A24 T25

U18

AL14

AC15

AJ32

AB36

AK17

AE45

AC45 AD36

T35

OMIT_TABLE

CRITICAL

BROADWELL-MOBILE-Y-B

BGA

U0500

CL26

CK27

CK40

CK25

AK33

AL16

AL22

CJ16

CJ28

CJ32

CK19

CK21

CK31

CL14

CL22

CM27

CM33

CK23

CJ22

AV45

AY45 BB45 BD45 BF45 BH45

BK45

BM45 BP45

BT45

BV41 BV43

BV45

BW40

BW42

BW44

BY41

BY43

BY45

CA40

CA42

CA44

CB41

CB43

CB45 CD45 CF45 CM45 CN44 CR43 CR45 CU44 CV43 CV45

CY13 CY15

CY17

CY19 CY21 CY23 CY25 CY27 CY29 CY31 CY33 CY36 CY38

CY40

CY42 CY44

CH45

BM43

AJ20

BU14

AR40

AP1 AV1

BA14

BB1 BC14 BE14

BF1

BK1

BP1

BV1

CB1

CF1

CL1

CM3

CR1

CT3

CW1

CY3

CD43 CD41 CE40

CE42 CF43

CF39

CJ20

16

BYPASS=U0500.AG13::6.35mm

0201

X5R

6.3V

20%

1UF

C0896

1

2

201

5%

1/20W

MF

10K

R0850

1

2

44 62

CPU/PCH POWER

SYNC_DATE=10/01/2013

SYNC_MASTER=J92_DEVMLB

CPU_VIDSCLK_R CPU_VIDSOUT_R

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PPVRTC_G3H

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP1V05_S5_PCH_VCCDSW

MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PP1V05_S5_PCH_VCCDSW_R

PP3V3_S5

PP3V3_S0

VOLTAGE=1.05V

PPVCOMP_S0_CPU

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

TP_PPVCCIO_S0_CPU

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

TP_MCP_DC_CY3

PP1V2_S3

TP_MCP_DC_CY44

MCP_DC_CV45

PPVCC_S0_CPU

CPU_VCCST_PWRGD

CPU_VIDALERT_R_L

PPVCC_S0_CPU

TP_MCP_DC_CW1

PP1V05_S0SW_PCH_USB3

PP1V05_S0SW_PCH_SATA

PP1V05_S0SW_PCH_PCIE

PP1V05_S0

CPU_VIDSOUT

PPVCC_S0_CPU

CPU_VIDALERT_L

CPU_PWR_DEBUG_L

PP1V05_S0

CPU_VCCSENSE_P

PP1V05_S0

PP1V05_S0SW_PCH_VCCSATA3PLL

PP3V3_SUS

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_SUS

PP1V05_S0

PP1V05_S0_PCH_VCC_ICC PP1V05_S0_PCH_VCCACLKPLL

PP1V05_SUS

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP3V3_SUS

PP1V5_S0

PP1V05_S0_PCH_VCCAPLL_OPI

PP1V05_SUS

PP1V05_S0_PCH_VCCAPLL_OPI

TP_MCP_RSVD_CJ22 TP_MCP_RSVD_CK23

TP_IST_TRIGGER

TP_IVR_ERROR

CPU_VR_EN CPU_VR_READY

CPU_VIDSCLK

PP3V3_SUS

PP3V3_S5

PP3V3_SUS

PP1V05_S0

PP1V05_SUS_PCH_VCCAOSCSUS

<SCH_NUM>

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VSS

VSS_SENSE

VSS

OUT

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

OMIT_TABLE

CRITICAL

BROADWELL-MOBILE-Y-B

U0500

AH29

AH30

AH31

AH32

AH33

AH34 AH44

AH6

AJ18

AJ24

AJ30 AJ37

AJ39

AK12 AK21 AK27

AK6

AM13

AM17

AM19

AM21 AM23 AM25 AM27 AM29 AM31 AM35

AM45

AN10 AN12 AN14

AN2 AN4

AN40 AN42 AN44

AN6

AN8

AP15

AP39

AP43

AP7

AR42

AT1

AT15 AT39 AT45

AT7

AU44 AV13 AV15 AV39 AW44

AY1

AY13 AY15 AY39

AY7

BA44

BB11 BB13 BB15

BB3

BB39

BB5 BB7 BB9

BC44 BD1

BD13 BD15 BD39

BD7

BE40 BE42

BE44

BF13 BF15 BF39

BF7

BG14 BG44 BH1

BH13 BH15 BH39 BH41 BH43

BH7

BJ44

BK13 BK15 BK39

BK7

BL10 BL12

BL2 BL4

BL40 BL42 BL44

BL6

BL8

BM1

BM13 BM39

BM7

BN44 BP13 CH1 CH15

CJ18 CJ24

CJ30

CL24

CL5

CN1

CU1

CV3

CV39 CV41 CW12 CW14 CW16 CW18

CRITICAL

OMIT_TABLE

BGA

BROADWELL-MOBILE-Y-B

U0500

AC32

AJ13

AK15

AK44

AM33

AV7

CA14

CH7

E16E20

E24

E28

E32 E36

F5 G16

G20

G24 N16

N20

N24 N28 N32 P35

R10

R16

R18

R2

R20

R22

R24 R26 R28

R30

R4

R44

R6 R8

CH43

T15

U22

U24

U26

U28 U32

U34

V17

V2

V40

44 66

PLACE_NEAR=U0500.CH43:50.8mm

201

MF

1/20W

100

5%

R0960

1

2

BGA

CRITICAL

OMIT_TABLE

BROADWELL-MOBILE-Y-B

U0500

A42

A6

AA11

AF36

BN14

BR14

BW14

CE14

CG14

CJ34

CK29

CK33

CL30

CL32

D4

D42

H42

J1

J3

J43

J45

L38

T13

W30

W32

W34

W35

Y12 Y14 Y16

Y19

Y2

Y24 Y28 Y32 Y40

Y42

Y44

BGA

OMIT_TABLE

CRITICAL

BROADWELL-MOBILE-Y-B

U0500

AG39

AM39

AR14

AW14

BP39

BP7

BR44

BT1

BT13

BT39

BT7

BU40 BU42

BU44

BV13 BV15 BV39

BV7

BY1

BY11 BY13 BY15

BY3

BY39

BY5 BY7 BY9

C16 C20 C24 C28 C32 C36

CA8

CB13 CB15 CB39

CB7

CC10

CC40 CC42 CC44

CD1

CD11

CD13 CD15

CD3

CD39

CD5

CD7

CD9

CE44

CF13 CF15

CF7

CG44 CH13 CJ26

CK10

CK3

CK38 CK44 CL12 CM15 CM17 CM19 CM21 CM23 CM25 CM31 CM35 CM43

CN26

CN42

CN8

CP17 CP29

CP3

CR14 CR18 CR22 CR26 CR37

CR8

CT31

CU14 CU18 CU22 CU26 CU42

CU8

CV35 CV37

CW20

CW22 CW24 CW26 CW28

CW30

CW32 CW34

CW5 CW8

CY10

CY7

D10 G28

G32

H10 H36

J16

J20

J24 J28

J32

L16

L2 L20

L24

L28

L32

OMIT_TABLE

CRITICAL

BGA

BROADWELL-MOBILE-Y-B

U0500

A10

A16

A20

A36

A40

AA19

AA21

AA22

AA24

AA25

AA26

AA28

AA29

AA3

AA30

AA32

AA33

AA34

AA35

AA37

AA39

AA5

AA7

AB12

AB15

AB16

AB40

AB44

AB8

AC1

AC11

AC13

AC19

AC24

AC28

AC3

AC35

AC37

AC41

AC43

AC5

AC7

AC9

AD12

AD14

AD16

AD19

AD24

AD28

AD32

AD44

AD6

AE16

AE19

AE24

AE28

AE32

AE35

AE37

AF12

AF14

AF16

AF44

AF6

AG19

AG24

AG28

AG32

AG35

AG37

AH12

AH14

AH15

AH16

AH17

AH19

AH20

AH21

AH22

AH23

AH25

AH26

AH27

AH28

AR12 AU12

AV11

AV3 AV5 AV9

BM15 BP15

CN5 CR5 CU5

H4

T19

T23

T29

U14

U20

V44

W16

W18

W19

W24

W28

CPU/PCH GROUNDS

SYNC_DATE=04/10/2013SYNC_MASTER=J92_WILL

CPU_VCCSENSE_N

<SCH_NUM>

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THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603

Apple implementation : 16x 10uF 0402 stuff, 12x 10uF 0402 nostuff

CPU VCC Decoupling

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

CPU VDDQ DECOUPLING

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

20% 4V

0402-1

X6S

10UF

NO STUFF

C1000

1

2

20%

6.3V CERM-X5R 0402-1

10UF

C1050

1

2

0402-1

20%

6.3V CERM-X5R

10UF

C1051

1

2

20%

6.3V

10UF

0402-1

CERM-X5R

C1052

1

2

20%

6.3V CERM-X5R 0402-1

10UF

C1053

1

2

20%

6.3V CERM-X5R 0402-1

10UF

C1054

1

2

20%

6.3V CERM-X5R 0402-1

10UF

C1055

1

2

20%

2.2UF

CERM

6.3V 402-LF

C1040

1

2

20%

2.2UF

CERM

6.3V 402-LF

C1041

1

2

20%

402-LF

CERM

6.3V

2.2UF

C1042

1

2

CERM 402-LF

2.2UF

20%

6.3V

C1043

1

2

0402-1

X6S

4V

20%

10UF

CRITICAL

C1001

1

2

20% X6S

4V

10UF

0402-1

CRITICAL

C1002

1

2

20% X6S

4V 0402-1

10UF

CRITICAL

C1003

1

2

X6S 0402-1

4V

20%

10UF

CRITICAL

C1004

1

2

0402-1

20% 4V X6S

10UF

NO STUFF

C1005

1

2

X6S

4V

20%

0402-1

10UF

NO STUFF

C1006

1

2

20% 4V X6S 0402-1

10UF

CRITICAL

C1007

1

2

20% 4V

10UF

X6S 0402-1

NO STUFF

C1008

1

2

0402-1

X6S

20% 4V

10UF

CRITICAL

C1009

1

2

4V

10UF

20% X6S

0402-1

C1011

1

2

10UF

20%

0402-1

4V X6S

C1012

1

2

10UF

20% 4V X6S

NO STUFF

0402-1

C1013

1

2

20%

0402-1

4V X6S

10UF

C1014

1

2

NO STUFF

10UF

20% 4V X6S 0402-1

C1015

1

2

20% 4V

10UF

0402-1

X6S

CRITICAL

C1016

1

2

0402-1

4V X6S

20%

10UF

NO STUFF

C1017

1

2

X6S

4V 0402-1

CRITICAL

20%

10UF

C1018

1

2

0402-1

4V

20% X6S

10UF

CRITICAL

C1019

1

2

10UF

4V X6S 0402-1

20%

CRITICAL

C1020

1

2

20%

0402-1

X6S

4V

10UF

NO STUFF

C1021

1

2

4V

20% X6S

0402-1

10UF

CRITICAL

C1022

1

2

X6S

20% 4V

0402-1

10UF

NO STUFF

C1025

1

2

4V

20% X6S

0402-1

10UF

C1026

1

2

0402-1

X6S

20% 4V

10UF

NO STUFF

C1027

1

2

20%

10UF

X6S

4V 0402-1

NO STUFF

C1028

1

2

20% X6S

4V 0402-1

NO STUFF

10UF

C1029

1

2

0402-1

20% X6S

4V

10UF

CRITICAL

C1023

1

2

CASE-B2S

CRITICAL

210UF

20%

2.5V POLY-TANT

C1031

1

2

CASE-B2S

CRITICAL

POLY-TANT

2.5V

20%

210UF

C1032

1

2

25V

12PF

CERM

5%

0201

C1030

1

2

CPU Decoupling

SYNC_DATE=10/01/2013

SYNC_MASTER=J92_DEVMLB

PP1V2_S3

PPVCC_S0_CPU

10 OF 130

<SCH_NUM>

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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH VCCSDIO BYPASS

(PCH 1.05V OPI PLL PWR)

PCH OPI VCCAPLL FILTER/BYPASS

(PCH 1.05V ACLK PLL PWR)

PCH VCCACLKPLL FILTER/BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SUSPEND RTC PWR)

(PCH 3.3V SUSPEND PWR)

PCH VCC3_3 BYPASS

PCH VCCA OSC FILTER/BYPASS (PCH 1.05V SUS VCCA OSC)

??mA Max

41mA Max

PCH VCCUSB3PLL FILTER/BYPASS

??mA Max

57mA Max

PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR)

(PCH 1.05V VCCCLK PWR)

PCH VCCCLK FILTER/BYPASS

??mA Max

(PCH 1.05V SATA PWR)

31mA Max

PCH VCCCLK BYPASS

PCH VCCSPI BYPASS

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

(PCH 3.3V/1.8V SDIO PWR)

PCH VCC BYPASS

(PCH 1.05V SUS USB3 PWR)

(PCH 1.05V SUS PWR)

PCH VCCSUS3_3 BYPASS

42mA Max

??mA Max

PCH VCCIO BYPASS

PCH VCC BYPASS

(PCH 1.05V CLK PWR)

(PCH 1.05V SUS PWR)

PCH VCCAIDLE BYPASS

(PCH 1.05V USB2 PWR)

(PCH 1.05V USB3 PWR)

PCH VCCHSIO BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR)

PCH VCCHSIO BYPASS

(PCH 3.3V SPI PWR)

(PCH 1.05V PCIe PWR)

(PCH 1.05V USB3 PLL PWR)

PCH VCC BYPASS

(PCH 3.3V THERMAL PWR)

(PCH 1.05V CORE PWR)

PCH VCCASW BYPASS

PCH VCCSATA3PLL FILTER/BYPASS

PCH VCC BYPASS

PCH VCCHSIO BYPASS

(PCH 1.05V ME CORE PWR)

??mA Max

(PCH 1.05V SATA3 PLL PWR)

(PCH 3.3V DSW PWR)

PCH VCCDSW3_3 BYPASS

20%

20UF

0402

X5R-CERM

4V

BYPASS=U0500.AK35::12.7mm

C1270

1

2

X5R

1UF

0201

6.3V

20%

BYPASS=U0500.AL30::6.35mm

C1220

1

2

X5R

1UF

0201

6.3V

20%

BYPASS=U0500.AK31::6.35mm

C1222

1

2

1UF

X5R

0201

BYPASS=U0500.AK23::6.35mm

6.3V

20%

C1224

1

2

BYPASS=U0500.AJ28::6.35mm

0201

1UF

X5R

6.3V

20%

C1225

1

2

X5R

1UF

0201

6.3V

20%

BYPASS=U0500.AL39::6.35mm

C1223

1

2

1UF

6.3V 0201

X5R

20%

BYPASS=U0500.AJ26::6.35mm

C1221

1

2

1UF

CERM-X6S 0201

4V

20%

BYPASS=U0500.U30::6.35mm

C1227

1

2

CERM-X6S

10UF

6.3V 0402

20%

BYPASS=U0500.U30::12.7mm

C1226

1

2

1UF

CERM-X6S 0201

BYPASS=U0500.U16::6.35mm

4V

20%

C1228

1

2

4V

CERM-X6S

20%

0201

1UF

BYPASS=U0500.AC45::6.35mm

C1262

1

2

20%

0201

CERM-X6S

1UF

BYPASS=U0500.AK35::6.35mm

4V

C1272

1

2

X5R-CERM

BYPASS=U0500.AK35::12.7mm

20%

20UF

0402

4V

C1271

1

2

NOSTUFF

X5R-CERM

20%

4V

BYPASS=U0500.T1::12.7mm

20UF

0402

C1250

1

2

6.3V

10%

BYPASS=U0500.W14::6.35mm

0.1UF

X6S 0201

C1251

1

2

1UF

0201

CERM-X6S

4V

20%

BYPASS=U0500.AL37::6.35mm

C1277

1

2

20%

0402

X5R-CERM

4V

20UF

BYPASS=U0500.AL37::12.7mm

C1276

1

2

X5R-CERM

0402

20UF

20%

4V

BYPASS=U0500.AL37::12.7mm

C1275

1

2

6.3V

BYPASS=U0500.A32::6.35mm

0.1UF

X6S

10%

0201

C1208

1

2

CERM-X6S

BYPASS=U0500.AK19::6.35mm

0201

4V

20%

1UF

C1282

1

2

NO STUFF

20%

X5R-CERM

0402

20UF

BYPASS=U0500.AK19::12.7mm

4V

C1281

1

2

NO STUFF

20%

0402

X5R-CERM

4V

20UF

BYPASS=U0500.AK19::12.7mm

C1280

1

2

BYPASS=U0500.AK29::6.35mm

CERM-X6S 0201

1UF

4V

20%

C1283

1

2

0201

CERM-X6S

1UF

20%

BYPASS=U0500.AK17::6.35mm

4V

C1284

1

2

NOSTUFF

20% 4V

0201

1UF

CERM-X6S

BYPASS=U0500.T35::6.35mm

C1297

1

2

BYPASS=U0500.T35::12.7mm

20%

20UF

0402

X5R-CERM

4V

C1296

1

2

20%

20UF

0402

X5R-CERM

4V

BYPASS=U0500.T35::12.7mm

C1295

1

2

BYPASS=U0500.U18::12.7mm

20%

20UF

6.3V 0402

CERM-X5R

C1204

1

2

20% 4V

0201

1UF

CERM-X6S

BYPASS=U0500.T33::6.35mm

NOSTUFF

C1292

1

2

20%

20UF

0402

X5R-CERM

4V

BYPASS=U0500.T33::12.7mm

NOSTUFF

C1291

1

2

20%

20UF

0402

X5R-CERM

4V

BYPASS=U0500.T33::12.7mm

NOSTUFF

C1290

1

2

20% 4V

0201

CERM-X6S

1UF

BYPASS=U0500.AG14::6.35mm

C1229

1

2

0201

CERM-X6S

1UF

4V

20%

BYPASS=U0500.AE13::6.35mm

C1264

1

2

10%

0.1UF

BYPASS=U0500.AA1::6.35mm

0201

X6S

6.3V

C1200

1

2

10% X6S

0.1UF

0201

6.3V

BYPASS=U0500.A24::6.35mm

C1202

1

2

1UF

BYPASS=U0500.N45::6.35mm

CERM-X6S

0201

4V

20%

C1261

1

2

20%

4V

0201

CERM-X6S

1UF

BYPASS=U0500.AB38::6.35mm

C1260

1

2

0201

20%

1UF

CERM-X6S

4V

BYPASS=U0500.T21::6.21mm

C1287

1

2

NO STUFF

BYPASS=U0500.T21::12.7mm

20%

0402

X5R-CERM

4V

20UF

C1286

1

2

NO STUFF

20%

0402

X5R-CERM

4V

20UF

BYPASS=U0500.T21::12.7mm

C1285

1

2

1UF

CERM-X6S

4V

20%

BYPASS=U0500.T31::6.35mm

0201

C1265

1

2

BYPASS=U0500.N1::6.35mm

0201

X6S

0.1UF

10%

6.3V

C1252

1

2

0201

6.3V

10% X6S

0.1UF

BYPASS=U0500.AB38::6.35mm

C1266

1

2

X6S 0201

6.3V

10%

0.1UF

BYPASS=U0500.AB38::6.35mm

C1267

1

2

0.1UF

0201

6.3V

10% X6S

BYPASS=U0500.N45::6.35mm

C1263

1

2

BYPASS=U0500.AC45::6.35mm

0201

6.3V

10% X6S

0.1UF

C1268

1

2

0201

6.3V

10% X6S

0.1UF

BYPASS=U0500.T27::6.35mm

C1216

1

2

0201

10%

0.1UF

X6S

6.3V

BYPASS=U0500.A28::6.35mm

C1215

1

2

X6S

0.1UF

10%

0201

6.3V

BYPASS=U0500.A30::12.7mm

C1212

1

2

0402

BYPASS=U0500.AK19::12.7mm

4V

X5R-CERM

20%

NO STUFF

20UF

C1289

1

2

NO STUFF

BYPASS=U0500.AK19::12.7mm

20UF

4V

X5R-CERM

0402

20%

C1288

1

2

BYPASS=U0500.AK35::12.7mm

4V

X5R-CERM

0402

20UF

20%

C1273

1

2

4V

0402

20UF

20%

BYPASS=U0500.AK35::12.7mm

X5R-CERM

C1274

1

2

20%

20UF

0402

X5R-CERM

4V

BYPASS=U0500.AL37::12.7mm

C1279

1

2

20%

20UF

0402

X5R-CERM

BYPASS=U0500.AL37::12.7mm

4V

C1278

1

2

NO STUFF

20UF

4V

X5R-CERM

0402

20%

BYPASS=U0500.T21::12.7mm

C1294

1

2

NO STUFF

BYPASS=U0500.T21::12.7mm

20UF

4V

X5R-CERM

0402

20%

C1293

1

2

603

0

5%

MF-LF

1/10W

R1280

12

603

1/10W MF-LF

5%

0

R1285

12

1/10W MF-LF

5%

0

603

R1290

12

BYPASS=U0500.W1::6.35mm

0201

CERM-X5R

10%

0.1UF

6.3V

C1210

1

2

20%

CERM

10V 402

0.1UF

BYPASS=U0500.AB36::6.35mm

C1214

1

2

1UF

0201

6.3V

20% X5R

BYPASS=U0500.AC15::6.35mm

C1206

1

2

BYPASS=U0500.Y22::12.7mm

CERM-X6S

10UF

6.3V

20%

0402

C1255

1

2

BYPASS=U0500.Y22::6.35mm

X6S

10%

6.3V 0201

0.1UF

C1257

1

2

2.2UH-240MA-0.221OHM

CRITICAL

0603

L1275

12

2.2UH-240MA-0.221OHM

CRITICAL

0603

L1295

12

1/16W

0

MF-LF

5%

402

R1275

12

0603

CRITICAL

2.2UH-240MA-0.221OHM

L1270

12

402

MF-LF

1/16W

5%

0

R1270

12

PCH Decoupling

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=09/23/2013

PP1V05_S0SW_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

PP1V05_S0SW_PCH_SATA

PP1V05_S0

PP3V3_SUS

PP1V05_S0_PCH_VCCACLKPLL_R

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0SW_PCH_PCIE

PP1V05_S0

PP3V3_SUS

PP3V3_S0

PP1V05_S0

PP1V05_S0SW_PCH_USB3

PP1V05_SUS

PP1V05_S0

PP1V05_S0SW_PCH_USB3

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0SW_PCH_SATA

PP1V5_S0

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0SW_PCH_VCCUSB3PLL

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCC_ICC

PP3V3_S0

PP3V3_S5

PP1V05_SUS

PP1V05_SUS_PCH_VCCAOSCSUS

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC_R

PP3V3_SUS

PP1V05_SUS

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCAPLL_OPI

MIN_NECK_WIDTH=0.075 MM

PP3V3_S0

11 OF 75

12 OF 130

<SCH_NUM>

8

12

8

11 51 60

6 8

11 15 16

17 32 44 46 51

60

8

11 14 15

18 27 28 29 46 51

60

8

51 60

6 8

11 15 16

17 32 44 46 51

60

6 8

11 15 16

17 32 44 46 51

60

8

11 14 15

18 27 28 29 46 51

60

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

6 8

11 15 16

17 32 44 46 51

60

6 8

11 15 16

17 32 44 46 51

60

8

11 51 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

6 8

11 15 16

17 32 44 46 51

60

8

11 51 60

8

12

8

11 51 60

8

17 40 46

60

8

14

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

8

13 15 16

17 22 33 37 46 47

51 59 60 73 75

8

11 12 16

46 48 51 60

8

11 14 15

18 27 28 29 46 51

60

8

11 12 16

46 48 51 60

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

WWW.AliSaler.Com

IN IN

OUT

IN

OUT

BI

NC

IN

OUT

OUT OUT

IN

OUT

IN

OUT

IN

(5 OF 20)

RTC

JTAG

AUDIO

SATA

HDA_SDI0/I2S0_RXD

INTVRMEN

RTCX2

PCH_TRST*

HDA_DOCK_EN*/I2S1_TXD HDA_DOCK_RST*/I2S1_SFRM

HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_SYNC/I2S0_SFRM

I2S1_SCLK

JTAGX

RSVD

SATA_IREF

SATA_RN0/PERN6_L3

SATA_RN1/PERN6_L2

SATA_RN2/PERN6_L1

SATA_RN3/PERN6_L0

SATA_RP0/PERP6_L3

SATA_RP1/PERP6_L2

SATA_RP2/PERP6_L1

SATA_RP3/PERP6_L0

SATA_TN0/PETN6_L3

SATA_TN1/PETN6_L2

SATA_TP0/PETP6_L3

SATA_TP1/PETP6_L2

SRTCRST*

RTCX1

PCH_TDI

PCH_TCK

RTCRST*

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA3GP/GPIO37

SATA2GP/GPIO36

SATA1GP/SATAPHY_PC/GPIO35

SATA0GP/GPIO34

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

RSVD

SATA_RCOMP

SATALED*

HDA_RST*/I2S_MCLK

HDA_BCLK/I2S0_SCLK

INTRUDER*

RSVD

PCH_TDO

PMTEST_RST

PCH_TMS

NC NC

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P3

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

CLKOUT_PCIE_N0

TESTLOW_AC33

DIFFCLK_BIASREF

CLKOUT_LPC_1

RSVD

XTAL24_OUT

XTAL24_IN

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P5

CLKOUT_PCIE_P4

CLKOUT_PCIE_N5

CLKOUT_PCIE_N4

CLKOUT_PCIE_N3

CLKOUT_LPC_0

TESTLOW_M15

TESTLOW_N14

TESTLOW_AD33

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P0

CLKOUT_ITPXDP_P CLKOUT_ITPXDP_N

CLOCK SIGNALS

(6 OF 20)

IN

OUT OUT

OUT

OUT OUT

IN

NC NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD)

(IPD-PLTRST#)

(IPD-PWROK)

1.5V -> 1.1V

(IPU)

(IPU - Flex IO strap only)

SATA Port assignments:

Unused

(IPD-PLTRST#)

16 68

01005

MF

1/32W

5%

100K

R1345

12

5% MF

100K

010051/32W

R1375

12

16

12 16

5% MF

1/32W 01005

100K

R1343

12

16 68

16

68

16

20K

1/20W 201

MF

5%

R1303

1

2

1UF

X5R

10% 10V

402

C1303

1

2

1%

1K

MF

1/20W

201

R1373

1

2

1/16W

1%

402

MF-LF

340

R1372

12

17

16 64

5% MF

100K

010051/32W

R1346

12

1/32W 01005

100K

MF5%

R1347

12

MF

5%

10K

NO STUFF

1/32W 01005

R1304

1

2

10V X5R

1UF

NO STUFF

0201-1

20%

C1304

1

2

29 62 64

68

29 62 64 68

12 29 62

25 68

12 24

40 68

PLACE_NEAR=U0500.J9:1.27mm

201

1/20W33MF5%

R1312

12

33

5% MF

1/32W 01005

PLACE_NEAR=U0500.L4:1.27mm

R1311

12

40 64 68

PLACE_NEAR=U0500.L6:1.27mm

MF

33

5%

1/32W 01005

R1310

12

46

330K

MF

1/20W

201

5%

R1302

1

2

1M

MF

1/20W 201

5%

R1301

1

2

1UF

X5R 402

10% 10V

C1300

1

2

5%

201

1/20W

MF

20K

R1300

1

2

6

16 66

PLACE_NEAR=U0500.L44:2.54mm

1%

3.01K

MF

1/20W 201

R1370

1

2

OMIT_TABLE

CRITICAL

BROADWELL-MOBILE-Y-B

BGA

U0500

L6

N5 N7

J9

L10

L8

N3

L4

N9

J5

H6

CL16

CK17

CL20

CL18

CK15

CM7

G26

C5

P17 R32

R34

A8

C9 C7

F29 H29 D33 L26

L42

L44

V36

T37

Y38

W37

V38

T39

W39

Y36

W43

T43

T41

AB42

AA43

V42

W41

AA41

C30

D6

CRITICAL

BGA

BROADWELL-MOBILE-Y-B

OMIT_TABLE

U0500

AG34

AE34

K15

L14

AD29

AD30

AE30

AC34

AE29

AG33

AC29

AC30

AG30

AD34

AG29

AE33

A38

B33

H25

P25

P27

D35

G30

BK41 BK43

AC33 AD33

M15

N14

AR44 AP45

12 22

22 68

22

68

40 68

54 64 66

12 54

1%

3.01K

MF

1/20W 201

PLACE_NEAR=U0500.A38:2.54mm

R1380

1

2

17 68

62 68

1/32W 01005

10K

MF5%

R1390

12

1/32W 01005

10K

MF5%

R1391

12

1/32W 01005

10K

MF5%

R1392

12

1/32W 01005

10K

MF5%

R1393

12

PLACE_NEAR=U0500.N3:1.27mm

MF 201

1/20W

33

5%

R1313

12

5% MF

1/32W 01005

100K

R1341

12

5% MF

100K

010051/32W

R1344

12

5% MF

100K

010051/32W

R1340

12

5% MF

100K

010051/32W

R1342

12

PCH Audio/JTAG/SATA/CLK

SYNC_DATE=04/10/2013SYNC_MASTER=J92_WILL

AP_CLKREQ_L

PP1V05_SUS

HDA_SDOUT

XDP_FW_PME_L

SSD_CLKREQ_L

PCH_UART_SSD_L_BT_H

PCIE_CLK100M_AP_N

PCH_SATALED_L

TBT_CLKREQ_L

FW_CLKREQ_L

CAMERA_CLKREQ_L

SD_CLKREQ_L

PCIE_CLK100M_AP_P

SYSCLK_CLK24M_SB

SYSCLK_CLK24M_SB_R

PP1V05_S0_PCH_VCCACLKPLL

HDA_SYNC

NC_PCIE_CLK100M_FWN NC_PCIE_CLK100M_FWP

FW_CLKREQ_L

PCH_TESTLOW1 PCH_TESTLOW2 PCH_TESTLOW3

PCH_DIFFCLK_BIASREF

TP_ITPXDP_CLK100MN

LPC_CLK24M_SMC_R TP_LPC_CLK24M_LPCPLUS_R

PCH_TESTLOW4

SD_CLKREQ_L

SSD_CLKREQ_L

PCIE_CLK100M_SSD_P

NC_PCIE_CLK100M_SDN

TP_ITPXDP_CLK100MP

NC_PCIE_CLK100M_SDP

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_CAMERA_P

PCIE_CLK100M_CAMERA_N

CAMERA_CLKREQ_L

HDA_RST_L

HDA_BIT_CLK

PPVRTC_G3H

PCIE_CLK100M_SSD_N

PP3V3_S0

AP_CLKREQ_L

XDP_PCH_TMS

PCH_PMTEST_RST

XDP_PCH_TDO

PCH_INTRUDER_L

HDA_BIT_CLK_R

HDA_RST_R_L

PCH_SATALED_L

PCH_SATA_RCOMP

NO_TEST=TRUE

NC_SATA2_R2DP

NO_TEST=TRUE

NC_SATA2_R2DN

XDP_FW_PME_L XDP_PCH_SATAPHY_PC XDP_PCH_UART_SSD_L_BT_H XDP_SSD_PCIE0_SEL_L

NO_TEST=TRUE

NC_SATA3_R2DP

NO_TEST=TRUE

NC_SATA3_R2DN

PCH_RTCRST_L

XDP_PCH_TCK XDP_PCH_TDI

PCH_CLK32K_PMIC

PCH_SRTCRST_L

NO_TEST=TRUE

NC_SATA1_R2DP

NO_TEST=TRUE

NC_SATA0_R2DP

NO_TEST=TRUE

NC_SATA1_R2DN

NO_TEST=TRUE

NC_SATA0_R2DN

NO_TEST=TRUE

NC_SATA3_D2RP

NO_TEST=TRUE

NC_SATA2_D2RP

NO_TEST=TRUE

NC_SATA1_D2RP

NO_TEST=TRUE

NC_SATA0_D2RP

NO_TEST=TRUE

NC_SATA3_D2RN

NO_TEST=TRUE

NC_SATA2_D2RN

NO_TEST=TRUE

NC_SATA1_D2RN

NO_TEST=TRUE

NC_SATA0_D2RN

PP1V05_S0SW_PCH_VCCSATA3PLL

PCH_JTAGX

TP_PCH_I2S1_SCLK

HDA_SYNC_R

HDA_SDOUT_R

NC_HDA_SDIN1

TP_PCH_I2S1_SFRM

TP_PCH_I2S1_TXD

XDP_CPUPCH_TRST_L

PCH_INTVRMEN

HDA_SDIN0

12 OF 75

<SCH_NUM>

13 OF 130

12 22

8

11 16 46

48 51 60

12 16

12 54

16 23

12

12 29 62

12

12 24

12

8

11

64

12

63

8

13 46 60

8

11 13 15 17

18 23 24 29 32 33

34 35 36 40 46 47 53 60 73 75

68

12

8

11

68

17 68

63

WWW.AliSaler.Com

IN

OUT

IN

OUT

SYSTEM POWER MANAGEMENT

(8 OF 20)

WAKE*

SUS_STAT*/GPIO61

SUSWARN*/SUSPWRDNACK/GPIO30

SUSCLK/GPIO62

SLP_WLAN*/GPIO29

SLP_SUS*

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_S0*

SLP_LAN*

SLP_A*

PWRBTN*

PLTRST*

DSWVRMEN

DPWROK

CLKRUN*/GPIO32

BATLOW*/GPIO72

ACPRESENT/GPIO31

SYS_PWROK

PCH_PWROK

RSMRST*

APWROK

SUSACK*

SYS_RESET*

OUT

BI

IN

OUT

PCI

DISPLAY

EDP

SIDEBAND

(9 OF 20)

GPIO55

GPIO54

GPIO53

GPIO52

GPIO51

EDP_HPD

DDPC_HPD

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPC_AUXP

DDPC_AUXN

DDPB_HPD

DDPB_CTRLDATA

DDPB_CTRLCLK

DDPB_AUXP

DDPB_AUXN

PME*

PIRQD*/GPIO80

EDP_BKLEN

PIRQC*/GPIO79

PIRQB*/GPIO78

PIRQA*/GPIO77

EDP_VDDEN

EDP_BKLCTL

OUT

BI BI

BI

OUT

IN

IN IN IN IN

OUT OUT OUT

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-PLTRST#)

(IPU)

(IPD-DeepSx)

(IPD-PLTRST#)

32

13 46

1/32W 01005

100K

MF5%

R1465

12

13 31 33

46 75

5% MF

10K

1/32W 01005

R1447

12

NO STUFF

010051/32W

10K

MF5%

R1444

12

15 16 18

46

16

31 46

17 31

13 46 51 52

13 31 46 52

BROADWELL-MOBILE-Y-B

BGA

OMIT_TABLE

CRITICAL

U0500

M17

J22

H17

B35

J7

G14

F9

M23

M21

F7

G18

K19G22

N22

H19

A18

D27

J18

D25

D19

B27

D8

A22

E26

F19

13 15 31 46

52

13 31 51 52

32 68

31

13 31

13 22

NO STUFF

100K

MF

1/32W 01005

5%

R1451

1

2

33 46

01005

1/32W

5% MF

330K

R1450

1

2

13 49

53 64

BROADWELL-MOBILE-Y-B

OMIT_TABLE

BGA

CRITICAL

U0500

Y26

W26

BP43 BN42

Y30

Y25

W25

BP41 BR40

Y29

BM41

BR42

W29

BN40

H33

L30

C39

F35

M29

K35 F31 J34 D38

B25

13 53

29 66

63

29

66

18

63

18

63

53

5%

1/32W 01005

100K

MF

R1446

12

1/32W 01005

MF5%

100K

R1445

12

1/32W

100K

MF5%

01005

R1442

12

01005

100K

5% MF

1/32W

R1443

12

1/32W 01005

100K

MF5%

R1441

12

0%

0.00

01005

1/32W

MF

NO STUFF

R1400

1

2

01005

100K

MF5%

1/32W

R1440

12

13 28 62

64

13 31

13 63

13 23 64

13 63

13 22

13 22 64

13 31

1/32W

10K

MF5%

01005

R1455

12

5% MF

10K

010051/32W

R1410

12

100K

1/32W 01005

MF5%

R1448

12

100K

1/32W 01005

MF5%

R1449

12

1/32W 01005

100K

MF5%

R1431

12

1/32W 01005

100K

MF5%

R1430

12

31 32

13 40

64

1/32W 01005

1.00K

MF5%

R1405

12

1/32W 01005

10K

MF5%

R1452

12

MF

100K

1/32W 01005

5%

R1460

12

01005

100K

MF5%

1/32W

R1461

12

1/32W

100K

5% MF

01005

R1462

12

1/32W 01005

100K

MF5%

R1464

12

1/32W

01005

100K

MF5%

R1463

12

13 16 31

SYNC_MASTER=J92_WILL SYNC_DATE=04/10/2013

PCH PM/PCI/GFX

PP3V3_S0

PM_SLP_S3_L

EDP_BKLT_EN EDP_PANEL_PWR

PCH_DSWVRMEN

PM_SLP_A_L

SMC_RUNTIME_SCI_L

SSD_BOOT

HDMITBTMUX_FLAG

HPM_I2C_INT_L

PM_SLP_A_L

PM_SLP_S5_L PM_SLP_S4_L

PM_SLP_SUS_L

PM_SLP_S0_L

PM_CLKRUN_L

PM_BATLOW_L PCIE_WAKE_L

PM_PWRBTN_L

PP3V3_S5

BT_LOW_PWR_L

EDP_BKLT_EN

ODD_PWR_EN_L

PM_SLP_S0_L

SMC_PCH_SUSACK_L

AP_PCIE_DEV_WAKE

DP_TBTSNK0_AUXCH_C_N

PLT_RESET_L PM_RSMRST_L

PM_PCH_SYS_PWROK

PM_BATLOW_L

PM_PWRBTN_L

PM_SYSRST_L

PM_CLKRUN_L

PM_DSW_PWRGD

TP_PCH_SLP_LAN_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_SUS_L

TP_PCH_SLP_WLAN_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PCIE_WAKE_L

BT_LOW_PWR_L

AP_PCIE_DEV_WAKE

AUD_PWR_EN

DP_INT_HPD

NC_DP_TBTSNK1_HPD

NC_DP_TBTSNK1_DDC_DATA

NC_DP_TBTSNK1_DDC_CLK

NC_DP_TBTSNK1_AUXCH_CP

NC_DP_TBTSNK1_AUXCH_CN

DP_TBTSNK0_HPD

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_DDC_CLK

NC_PCI_PME_L

SSD_BOOT

HDMITBTMUX_FLAG

SMC_RUNTIME_SCI_L

HPM_I2C_INT_L

EDP_PANEL_PWR

EDP_BKLT_PWM

PPVRTC_G3H

HDMITBTMUX_LATCH

AUD_PWR_EN

SMC_ADAPTER_EN

PM_PCH_APWROK

PM_PCH_PWROK

SMC_PCH_SUSWARN_L

ODD_PWR_EN_L HDMITBTMUX_LATCH

DP_TBTSNK0_AUXCH_C_P

14 OF 130

<SCH_NUM>

13 OF 75

8

11 12 15 17

18 23 24 29 32 33

34 35 36 40 46 47 53 60 73 75

13 31 46 52

13 49

13 53

13 31

13 23 64

13 63

13 28 62 64

13 46

13 31 51 52

13 15 31 46 52

13 46 51 52

13 31 33 46 75

13 31

13 22

13 16 31

8

11 15 16 17

22 33 37 46 47 51

59 60 73 75

13 22

13 63

31 62

13 22 64

63

8

12 46 60

13 63

13 40

64

31 62

WWW.AliSaler.Com

(7 OF 20)

LPC

SMBUS

SPI

C-LINK

LAD3

SPI_MOSI

LFRAME*

SPI_CLK

SPI_CS0*

SML0DATA

SPI_CS1*

CL_CLK

CL_DATA

CL_RST*

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML1ALERT*/PCHHOT*/GPIO73

SML1CLK/GPIO75

SML1DATA/GPIO74

SPI_CS2*

SPI_IO2

SPI_IO3

SPI_MISO

LAD0 LAD1 LAD2

OUT

IN IN IN IN

NC NC

OUT

IN

OUT

IN

OUT

IN

IN IN

OUT OUT

OUT

IN

OUT OUT

IN IN

OUT OUT

OUT

PCI-E

USB

(11 OF 20)

USB2P6

USB3RN1 USB3RP1

USB3TN1

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

USBRBIAS

USBRBIAS*

OC0*/GPIO40 OC1*/GPIO41 OC2*/GPIO42 OC3*/GPIO43

RSVD

USB3TP2

USB3TN2

USB3TP1

USB3RP2

USB3RN2

USB2P5

USB2P4

USB2P3

USB2P2

USB2P1

USB2P0

USB2N5

USB2N4

USB2N3

USB2N2

USB2N1

USB2N0

PETP5_L3

PETP5_L2

PETP5_L0

PETP4

PETP3

PETP2/USB3TP4

PETN5_L2

PETN4

PETN3

PETN1/USB3TN3

PERP5_L3

PERP5_L0

PERP3

PERP1/USB3RP3

PERN5_L3

PERN5_L0

PERN4

PERN3

PERN1/USB3RN3

PCIE_IREF

PERP4

PCIE_RCOMP

RSVD

PETN2/USB3TN4

PERP2/USB3RP4

PERN2/USB3RN4

PETP1/USB3TP3

PETN5_L0

USB2N6

USB2N7 USB2P7

USB2N8 USB2P8

USB2N9 USB2P9

PETN5_L3

IN

NC NC

IN

BI

IN

BI

OUT

BI

OUT

BI BI

BI

OUT

IN

BI

OUT

BI

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Thunderbolt lane 1

Unused

Reserved: Camera

SSD lane 2

(IPU/IPD)

(IPU)

(IPU/IPD)

(IPU)

SML1ALERT# pull-up not provided on this

Otherwise, 100k pull-up to 3.3V SUS required.

page, may be wire-ORed into other signals.

AirPort

(IPD)

Unused

Trackpad

IR

BT

Unused

Ext A (LS/FS/HS)

USB Port Assignments:

PCIe Port Assignments:

Unused

USB3 Port Assignments:

Ext B (LS/FS/HS)

SSD lane 3

Camera

SSD lane 1

SSD lane 0

Reserved: SD (HS)

Ext A (SS)

Thunderbolt lane 0

OMIT_TABLE

CRITICAL

BROADWELL-MOBILE-Y-B

BGA

U0500

D23

H23

K23

P13 M13 R14 K13

P15

K21

P21 B21

F21

P19 B19

H8

C14 A14

C26

H27

M27

K27

F27

J26

B23

D31

23 66

1/32W 01005

100K

MF5%

R1580

12

1/32W 01005

100K

MF5%

R1581

12

18 33

23 66

14

16 28 62 63 64

14 16 64

14 16

29 67

64 66

29 64 67

64 67

25 64 68

25 68

64 66

62 68

29 67

27 67

23 66

64 66

23 66

22 68

CRITICAL

OMIT_TABLE

BROADWELL-MOBILE-Y-B

BGA

U0500

E18 E22 H21 D21C41

F41

AF38

AH42

AD38

AH38

AF40

AD40

AE43

AF42

AE39

AJ43

AC39

AH40

AG41

AE41

AD42

AG43

BD41

BC40

AY41

AV41

AU40

AW40

BA42

BB41

BD43

BC42

AY43

AV43

AU42

AW42

BA40

BB43

AT41 AT43

F13

H13

W12

T9

Y10

AB10

W9

V8

V6

Y6

V4

Y4

V12

V10

Y8

AA9

W7

T7

T5

W5

T3

W3

AJ41

AM43

AM41

AK42

BG42

BF41

BG40

BF43

D13

B13

22 68

3.01K

1% MF

1/20W

201

PLACE_NEAR=U0500.F41:2.54mm

R1500

1

2

64 66

22.6

1% MF

1/20W 201

PLACE_NEAR=U0500.B13:2.54mm

R1570

1

2

64 67

64

66

64

22 67

64 67

23 66

26 64 67

31 68

010051/32W

5% MF

33

R1543

12

010051/32W

5% MF

33

R1542

12

23 66

010051/32W

5% MF

33

R1544

12

01005

MF

33

5%

1/32W

R1540

12

33

MF5%

1/20W

201

R1541

12

37 68

31

34 36 53 68 72

64 66

31 34 36 53 68 72

34 68

16 34 68

37 68

64 66

14 37

1/32W 01005

100K

MF5%

R1591

12

MF

1/32W 01005

1.00K

5%

R1549

12

1/32W 01005

100K

MF5%

R1590

12

MF

1/32W 01005

1.00K

5%

R1548

12

1/32W 01005

100K

MF5%

R1582

12

1/32W 01005

100K

MF5%

R1583

12

CPU

PCH PCIe/USB/LPC/SPI/SMBus

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=06/28/2013

USB3_EXTA_D2R_P

TP_USB_9P

USB3_EXTD_D2R_N

USB3_EXTD_R2D_C_P

USB3_EXTD_D2R_P USB3_EXTD_R2D_C_N

PCIE_TBT_D2R_P<0>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_AP_D2R_P

PCIE_SSD_D2R_P<3>

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<0>

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCIE_CAMERA_R2D_C_N PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_P

PCIE_CAMERA_D2R_N

PCIE_SSD_R2D_C_P<2>

TP_USB_8P

PCIE_SSD_R2D_C_N<3>

TP_USB_8N

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L

WOL_EN

SPI_IO<3> PCH_SMBALERT_L

SPI_IO<2>

XDP_USB_EXTD_OC_L

PP3V3_SUS PP3V3_SUS

PCH_USB_RBIAS

TP_USB_5N

NC_USB_CAMERAN

TP_USB_5P

NC_USB3_EXTB_R2D_CN NC_USB3_EXTB_R2D_CP

XDP_USB_EXTD_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTA_OC_L

TP_USB_9N

NC_USB_SDP

NC_USB_CAMERAP

NC_USB_SDN

NC_USB_EXTBN NC_USB_EXTBP

USB_EXTA_N USB_EXTA_P

NC_USB_IRN

USB_BT_P

USB_BT_N

NC_USB_TPADP

NC_USB_TPADN

NC_USB_IRP

USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_C_N

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_N<3>

PCIE_AP_D2R_N

PCIE_AP_R2D_C_N

SML_PCH_0_DATA

TP_SPI_CS1_L

NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

PCH_SMBALERT_L SMBUS_PCH_CLK

SMBUS_PCH_DATA

SML_PCH_0_CLK

PCH_SML1ALERT_L SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDATP_SPI_CS2_L

LPC_AD<0>

SPI_CLK_R SPI_CS0_R_L

SPI_MOSI_R SPI_MISO SPI_IO<2> SPI_IO<3>

LPC_AD_R<2> LPC_AD_R<3>

LPC_FRAME_R_L

LPC_AD<2>

LPC_AD<1>

LPC_AD<3>

WOL_EN

LPC_FRAME_L

PP1V05_S0SW_PCH_VCCUSB3PLL

PCH_PCIE_RCOMP

LPC_AD_R<1>

LPC_AD_R<0>

PCIE_SSD_R2D_C_P<3>

PCIE_AP_R2D_C_P

NC_USB3_EXTB_D2RP

NC_USB3_EXTB_D2RN

PCIE_SSD_R2D_C_P<0>

14 OF 75

15 OF 130

<SCH_NUM>

14 16 28 62

63 64

14 16 64

14 16

14

14 37

14

14 37

14 16

8

11 14 15 18

27 28 29 46 51 60

8

11 14 15 18

27 28 29 46 51 60

67

63

14

8

11

WWW.AliSaler.Com

IN

OUT

BI

NC NC

(10 OF 20)

GPIO

LPIO CPU/MISC

RSVD

PCH_OPI_RCOMP

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST*/GPIO2

GSPI0_MOSI/GPIO86

I2C1_SCL/GPIO7

I2C1_SDA/GPIO6

I2C0_SCL/GPIO5

I2C0_SDA/GPIO4

UART1_CTS*/GPIO3

SDIO_CLK/GPIO64

SPKR/GPIO81

SDIO_POWER_EN/GPIO70

SDIO_D2/GPIO68

SDIO_D1/GPIO67

SDIO_D0/GPIO66

SDIO_CMD/GPIO65

HSIOPC/PCIEPHY_PC/GPIO71

GPIO59

GPIO50

GPIO49

GPIO48

GPIO47

GPIO46

GPIO45

GPIO44

GPIO25

GPIO17

GPIO14

GPIO13

GPIO10

GPIO9

GPIO8

DEVSLP2/GPIO39

DEVSLP1/GPIO38

DEVSLP0/GPIO33

GPIO24

GPIO56

GPIO57

GPIO58

GPIO26

GPIO28

GPIO27

BMBUSY*/USB3PHY_PC/GPIO76

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

GPIO16

SDIO_D3/GPIO69

UART0_RTS*/GPIO93

GSPI0_CS*/GPIO83

THERMTRIP*

RCIN*/GPIO82

SERIRQ

UART0_TXD/GPIO92

UART0_RXD/GPIO91

GSPI_MOSI/GPIO90

GSPI1_MISO/GPIO89

GSPI1_CLK/GPIO88

GSPI1_CS*/GPIO87

GSPI0_MISO/GPIO85

GSPI0_CLK/GPIO84

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

IN

OUT

BI

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

(IPD-PLTRST#)

(IPD-RSMRST#)

(IPD-PLTRST#)

(IPD-DeepSx)

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Pull-up/down on chipset support page (depends on TBT controller)

(IPD)

(IPD-PLTRST#)

Requires connection to SMC via 1K series R

1/32W 01005

MF5%

10K

R1652

12

1/32W

MF5%

01005

47.0K

R1672

12

1/32W 01005

100K

MF5%

R1674

12

1/32W

MF5%

100K

01005

R1676

12

10K

1/32W

5% MF

01005

R1678

12

01005

100K

MF5%

1/32W

R1677

12

10K

MF5%

010051/32W

R1679

12

MF

5%

100K

1/32W 01005

R1639

1

2

5%

01005

MF

1/32W

1.00K

R1641

12

100K

5%

1/32W

MF

01005

R1621

1

2

13 15 16

18

29 62

15 63

15 31

BROADWELL-MOBILE-Y-B

OMIT_TABLE

BGA

CRITICAL

U0500

J30

E30

K31

J41

B17

E14

M19

K25

N26

H31

C22

F17

B15

K17

M25

L18

P23

L22

B29

K29

B31

F33

F25

F23

F15

D15

C18

D17

G34

D40

L36

K33

M31

L34

F37

H35

D29

R42

N36

M33

J37

J14

AB4

C34

AJ14 AL18

N34

H40

R40

R38

J39

P31

R36

E34

A34

CG40

N41

N43

M35

F39

N30

N39

P29

H38

1/32W

100K

MF5%

01005

R1609

12

1/32W

100K

MF 01005

5%

R1629

1

2

22

100K

5%

1/32W

MF

01005

R1691

1

2

13 15 16 18

5%

01005

100K

MF

1/32W

R1613

12

5% MF

1/20W

201

100K

RAMCFG3:H

R1631

1

2

1/32W

MF5%

47.0K

01005

R1673

12

47.0K

5% MF

1/32W 01005

R1675

12

47.0K

01005

5% MF

1/32W

R1668

12

1/32W 01005

47.0K

5% MF

R1669

12

47.0K

01005

5% MF

1/32W

R1670

12

010051/32W

MF5%

47.0K

R1671

12

1/32W

100K

MF5%

01005

R1608

12

15 63

5%

100K

1/20W 201

MF

RAMCFG2:H

R1636

1

2

15 63

MF

47.0K

1/32W5%01005

R1660

12

47.0K

MF5%

010051/32W

R1661

12

47.0K

1/32W

MF5%

01005

R1662

12

47.0K

5% MF

1/32W 01005

R1663

12

01005

5% MF

1/32W

100K

R1640

12

MF

5%

100K

01005

1/32W

SSD_LPSR:S3

R1634

1

2

13 31 46

52

5%

201

MF

100K

RAMCFG1:H

1/20W

R1635

1

2

5% MF

201

1/20W

RAMCFG0:H

100K

R1611

1

2

15 28 62 64

15 63

15

63

15 53 64

33

24

16

15 16 18

15 16

15 63

18

15 59 64

15 63

15 16

15 63

15 51

15 37

15 24 64

15 59 64

15 22 64

59

15 31 64

15 63

15 30 64

31 32 66

15 16

15 16 18

15 63

15 30

15 16

15 30 64

15 30 67

5%

1.00K

1/32W

MF

01005

R1650

1

2

15 30 67

5% MF

010051/32W

100K

R1610

12

5%

100K

010051/32W

MF

R1612

12

5% MF

100K

010051/32W

R1614

12

5% MF

100K

010051/32W

R1615

12

MF

010051/32W

100K

5%

R1616

12

100K

1/32W

MF

01005

5%

R1617

12

MF

100K

1/32W 01005

5%

R1618

12

100K

010051/32W

MF5%

R1619

12

5% MF

100K

010051/32W

SSD_LPSR:S0

R1620

12

MF

01005

100K

5%

1/32W

R1622

12

01005

100K

MF5%

1/32W

R1623

12

01005

100K

MF5%

1/32W

R1624

12

01005

100K

MF5%

1/32W

R1625

12

5%

01005

100K

MF

1/32W

R1626

12

010051/32W

100K

MF5%

R1627

12

5%

01005

MF

1/32W

100K

R1628

12

5%

100K

1/32W

MF

01005

R1630

12

5%

100K

1/32W

MF

01005

R1632

12

5%

100K

010051/32W

MF

R1633

12

MF

01005

5%

1/32W

100K

R1637

12

5%

010051/32W

100K

MF

R1638

12

5% MF

010051/32W

10K

R1694

12

1/32W 01005

100K

MF5%

R1693

12

PLACE_NEAR=U0500.AB4:2.54mm

201

1%

49.9

MF

1/20W

R1655

1

2

1/32W 01005

MF5%

100K

R1695

12

47K

201

1/20W

5% MF

R1664

12

47K

1/20W

MF5% 201

R1665

12

47K

5%

1/20W

MF 201

R1666

12

47K

201

1/20W

MF5%

R1667

12

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAMCFG_SLOT

PCH GPIO/MISC/LPIO

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=08/14/2013

PP3V3_S0

CAMERA_PWR_EN

SPIROM_USE_MLB

TPAD_SPI_IF_EN

TPAD_SPI_INT_L

TPAD_SPI_IF_EN

TPAD_USB_IF_EN

PCH_TBT_PCIE_RESET_L

SD_RESET_L

AUD_WAKE_L

XDP_LPCPLUS_GPIO

PP3V3_S5

LPC_SERIRQ

AP_S0IX_WAKE_SEL

SSD_SR_EN_L

PP3V3_SUS

XDP_JTAG_ISP_TDI

XDP_LPCPLUS_GPIO

I2C_PCH_1_SDA

JTAG_ISP_TDO

TPAD_SPI_MOSI

TPAD_SPI_CLK

AP_S0IX_WAKE_L

TPAD_SPI_MISO

I2C_PCH_1_SCL

TBT_CIO_PLUG_EVENT_L

PLT_RESET_L

CAMERA_RESET_L

PM_THRMTRIP_L

XDP_JTAG_ISP_TCK

JTAG_TBT_TMS_PCH PCH_PCIEPHY_PC

PCH_STRP_TOPBLK_SWP_L

XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG3 SPIROM_USE_MLB

AP_S0IX_WAKE_SEL

LCD_IRQ_L

SSD_SR_EN_L

TP_MEM_VDD_SEL_1V5_L

LCD_PSR_EN

PP1V05_S0

LCD_PSR_EN

ENET_MEDIA_SENSE LCD_IRQ_L

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG2

SD_PWR_EN

SMC_WAKE_SCI_L

XDP_PCH_GPIO17

I2C_PCH_1_SDA

PCH_UART1_D2R PCH_UART1_R2D

PCH_UART1_CTS_L

PCH_BT_UART_D2R

PCH_BT_UART_RTS_L

PCH_UART1_R2D

PCH_BT_UART_RTS_L

AP_S0IX_WAKE_L

PCH_BT_UART_CTS_L

PCH_TCO_TIMER_DISABLE

ENET_MEDIA_SENSE

PCH_OPI_COMP

TPAD_SPI_MISO

MIKEY_SPI_MOSI

LPC_SERIRQ

TPAD_SPI_MOSI

TPAD_SPI_CS_L

MIKEY_SPI_MISO

MIKEY_SPI_CLK

MIKEY_SPI_CS_L

MIKEY_SPI_MISO MIKEY_SPI_MOSI

PP3V3_S0

PCH_USB3PHY_PC

PCH_GPIO12

I2C_PCH_1_SCL

QR_SWITCH_EN

PCH_BT_UART_R2D

XDP_MLB_RAMCFG2

PCH_PCIEPHY_PC

PCH_BT_UART_R2D

CAMERA_PWR_EN

QR_SWITCH_EN

AP_RESET_L

PCH_UART1_CTS_L

JTAG_ISP_TDO

PCH_UART1_D2R

PCH_BT_UART_CTS_L

PCH_BT_UART_D2R

MIKEY_SPI_CS_L MIKEY_SPI_CLK

TPAD_SPI_CS_L

BT_PWRRST_L

XDP_MLB_RAMCFG1

JTAG_TBT_TMS_PCH

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

TBT_PWR_EN

PP3V3_SUS

SD_PWR_EN

PP3V3_SUS

XDP_SDCONN_STATE_CHANGE_L

AUD_WAKE_L

PP3V3_S0

SSD_PWR_EN

SSD_RESET_L

TBT_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

SSD_PWR_EN

PCH_GPIO12

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG0

PM_SLP_S4_L

PLT_RESET_L

PP3V3_S0

PCH_SATAPHY_PC

BT_PWRRST_L

XDP_PCH_GPIO17 SD_RESET_L SMC_WAKE_SCI_L TPAD_SPI_INT_L TPAD_USB_IF_EN

XDP_PCH_USB3PHY_PC

PP3V3_S0

TPAD_SPI_CLK

15 OF 75

16 OF 130

<SCH_NUM>

8

11 12 13

15 17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

15 24 64

15 37

15 30

15 16

8

11 13 16 17

22 33 37 46 47 51

59 60 73 75

15 31

15 22 64

15 59 64

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

15 28 34 64

15

15 30 67

15 22 64

15 30 67

15 28 34 64

15 63

6 8

11 16 17

32 44 46 51 60

15 63

15 53 64

15 16 18

15 28 34 64

15 64

15

15 23 64

15 23

15 64

15 23

15 22 64

15 23 64

15 63

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

16 51

15 63

15 28 34 64

15 23 64

15 16 18

15 51

15 23 64

15 28 62 64

15

15 64

15 23 64

15 63

15 30 64

15 63

15 16

15 63

8

11 14 15

18 27 28 29 46 51 60

15 63

8

11 14 15

18 27 28 29 46 51 60

15 16

15 63

8

11 12 13

15 17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

15 59 64

15 16 18

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

16 51

15 63

15 16

15 63

15 31 64

15 30 64

15 63

8

11 12 13

15 17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

www.qdzbwx.com

WWW.AliSaler.Com

IN

IN IN

IN

OUT

IN

OUT

IN

OUT OUT

IN

NC NC

IN IN

IN

OUT

IN

BI

IN

OUT

Y

NC NC

VCC

GND

A

NC

IN

NC

IN

PP

IN

PP

IN

BI

OUT

BI

OUT

IN

OUT

BI

OUT

IN

OUT

BI

PP

OUT

IN

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Extra BPM Probepoints

OBSDATA_A3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6

OBSFN_B0

PCH XDP Signals

OBSFN_A0 OBSFN_A1

DBR#/HOOK7

OBSDATA_B2 OBSDATA_D2

HOOK2

OBSDATA_C0

SSD_PCIEx_SEL_L straps are connected via 1K to common net. LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

support chipset debug.

OBSFN_C0 OBSFN_C1

OBSDATA_C1

OBSDATA_C3

OBSDATA_C2

OBSDATA_D0 OBSDATA_D1

OBSFN_D1

OBSDATA_D3

XDP_PRESENT#

TMS

TDI

OBSDATA_A0

OBSFN_B1

OBSDATA_A2

OBSDATA_B0

PWRGD/HOOK0

VCC_OBS_AB

HOOK3

HOOK1

SDA

TCK0

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to

OBSDATA_A1

SCL

OBSFN_D0

Merged (CPU/PCH) Micro2-XDP

TDI and TMS are terminated in CPU.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

Unused & MLB_RAMCFGx GPIOs have TPs.

OBSDATA_B3

OBSDATA_B1

TRSTn

TDO

PCH/XDP Signals

TCK1

518S0847

CPU JTAG Isolation

Non-XDP Signals

via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

These signals do not connect to XDP connector in this architecture, only accessible

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

6

66

13 15 18

6

66

6

66

6

66

6

66

6

66

6

66

13 31

46

12 16 68

17 66

6

66

12 16 68

12

16 68

5% MF

XDP

PLACE_NEAR=U0500.AG7:2.54mm

1/20W

201

1K

R1805

12

PLACE_NEAR=U0500.CM41:28mm

51

XDP

MF

1/20W

5% 201

R1813

21

5%

0

MF

1/20W

XDP

0201

R1804

12

PLACE_NEAR=U5000.K1:2.54mm

XDP

MF

1/20W

0

5%

0201

R1802

12

1K

201

PLACE_NEAR=U0500.BU14:2.54mm

MF5%

XDP

1/20W

R1800

12

6

66

XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

M-ST-SM1

J1800

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

61

62

6364

78 9

6

66

6

66

6

66

6

66

6

66

6

66

6

66

6

66

6

66

6

66

8

201

5%

150

MF

1/20W

R1830

1

2

PLACE_NEAR=U0500.CU38:28mm

XDP

51

MF

1/20W

5% 201

R1810

12

12 16 68

201

5%

1K

XDP

MF

1/20W

R1831

1

2

PLACE_NEAR=U0500.CK17:28mm

NO STUFF

51

MF

1/20W

5% 201

R1896

21

PLACE_NEAR=U0500.CK15:28mm

XDP

51

MF

1/20W

5% 201

R1892

21

PLACE_NEAR=U0500.CL20:28mm

XDP

51

MF

1/20W

5% 201

R1891

21

PLACE_NEAR=U0500.CL18:28mm

51

XDP

MF

1/20W

5% 201

R1890

21

PLACE_NEAR=U0500.CL16:28mm

201MF

NO STUFF

1/20W

1K

5%

R1899

12

PLACE_NEAR=J1800.58:28mm

XDP

MF

0

5%

0201

1/20W

R1835

12

12 16

6

12 16 66

6

66

6

66

6

16 66

0201

CERM-X5R

6.3V

10%

0.1UF

XDP

C1801

1

2

6

66

0.1UF

10%

CERM-X5R

XDP

6.3V 0201

C1800

1

2

6

66

6

66

CERM-X5R

0201

XDP

6.3V

0.1UF

10%

C1804

1

2

XDP

0.1UF

6.3V CERM-X5R 0201

10%

C1806

1

2

6

66

6

12 16 66

PLACE_NEAR=U0500.CM7:28mm

51

NO STUFF

MF

1/20W

5% 201

R1897

21

SOT891

74LVC1G07GF

U1845

2

3

1

5

6

4

0201

16V

0.1UF

10%

X5R-CERM

C1845

1

2

6

66

330K

MF

1/20W

5%

201

R1845

1

2

31 33 46

SM

P2MM

PP1802

1

P2MM

SM

PP1803

1

6

66

SM

P2MM

PP1804

1

SM

P2MM

PP1805

1

P2MM

SM

PP1806

1

P2MM

SM

PP1807

1

NOSTUFF

0201

1/20W

0

5% MF

R1832

1

2

15

12

12 64

12

15

12

15 18

15

18

15 18

15

14

14 16 28 62 63 64

14 16 64

15 18

P2MM

SM

PP1887

1

SHORT

201

NONENONENONE

OMIT

R1886

12

P2MM

SM

PP1884

1

P2MM

SM

PP1885

1

5% MF

1/20W

201

1K

R1883

12

NONENONE

SHORT

NONE

201

OMIT

R1882

12

201

NONE

SHORT

NONE NONE

OMIT

R1881

12

SM

P2MM

PP1880

1

P2MM

SM

PP1879

1

SM

P2MM

PP1875

1

P2MM

SM

PP1874

1

SM

P2MM

PP1873

1

15 51

12 23

15 51

14 16 28

62 63 64

14 16 64

PLACE_NEAR=J1800.55:28mm

CRITICAL

XDP

SOT563

DMN5L06VK-7

Q1840

3

5

4

PLACE_NEAR=J1800.55:28mm

CRITICAL

XDP

DMN5L06VK-7

SOT563

Q1840

6

2

1

SOT563

PLACE_NEAR=J1800.55:28mm

DMN5L06VK-7

XDP

CRITICAL

Q1842

3

5

4

SOT563

PLACE_NEAR=J1800.55:28mm

DMN5L06VK-7

XDP

CRITICAL

Q1842

6

2

1

6

66

14 34 68

14

34 68

6

16 66

6

66

8

17 46

6

66

6

66

6

66

SYNC_DATE=09/16/2013

CPU/PCH Merged XDP

SYNC_MASTER=J92_DEVMLB

XDP_CPU_VCCST_PWRGD XDP_CPU_PWRBTN_L

XDP_SYS_PWROK

XDP_CPU_TCK

XDP_JTAG_CPU_ISOL_L

XDP_PCH_TDO

XDP_PCH_TDI

XDP_PCH_TMS

XDP_CPUPCH_TRST_L

XDP_CPU_TMS

SMBUS_PCH_DATA

XDP_PCH_TCK

XDP_PCH_TMS

XDP_PCH_TDI

XDP_CPU_PRESENT_L

CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

XDP_USB_EXTB_OC_L

XDP_CPU_TDI

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_TRST_L

XDP_CPU_TDO

XDP_PCH_TDO

XDP_CPUPCH_TRST_L

CPU_VCCST_PWRGD

CPU_CFG<12>

PCH_JTAGX

SMBUS_PCH_CLK

CPU_CFG<5>

XDP_PCH_TCK

CPU_CFG<19>

CPU_CFG<11>

CPU_CFG<10>

XDP_CPUPCH_TRST_L

PLT_RESET_L

CPU_CFG<18>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<16>

CPU_CFG<17>

CPU_PWR_DEBUG_L

PM_PCH_SYS_PWROK

CPU_CFG<7>

CPU_CFG<2>

XDP_CPU_PREQ_L

PP1V05_S0

XDP_CPU_TDO

PCH_JTAGX

PP1V05_SUS

XDP_CPU_TCK

ALL_SYS_PWRGD

XDP_BPM_L<2> XDP_BPM_L<3>

XDP_BPM_L<5> XDP_BPM_L<6>

CPU_CFG<6>

CPU_CFG<4>

XDP_BPM_L<1>

CPU_CFG<3>

CPU_CFG<1>

XDP_BPM_L<4>

XDP_BPM_L<7>

PP5V_S0 PP3V3_S5

PM_PWRBTN_L

XDP_LPCPLUS_GPIO

XDP_FW_PME_L

XDP_SSD_PCIE0_SEL_L

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

XDP_PCH_SATAPHY_PC

XDP_PCH_GPIO17 XDP_PCH_USB3PHY_PC

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

XDP_PCH_UART_SSD_L_BT_H

PCH_USB3PHY_PC

PCH_SATAPHY_PC PCH_UART_SSD_L_BT_H

XDP_SDCONN_STATE_CHANGE_L

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

XDP_DBRESET_L

XDP_CPU_PRDY_L

XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2 XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG0

XDP_USB_EXTA_OC_L

XDP_CPURST_L

PP1V05_S0

XDP_BPM_L<0>

CPU_CFG<0>

16 OF 75

<SCH_NUM>

18 OF 130

12 16 68

12

16 68

12 16 68

6

12 16 66

6

12 16 66

12

16 68

6 8

11 15 16

17 32 44 46 51

60

6

16 66

12 16

8

11 12 46

48 51 60

6

16 66

17 25

30 39 40 44 45 47 49 51

60

8

11 13 15

17 22 33 37 46 47

51 59 60 73 75

66

6 8

11 15 16

17 32 44 46 51

60

WWW.AliSaler.Com

OUT

IN

BIIN

OUT

IN

NC

PAD

GND

VG3HOT

VDD

OE_12M_B

VIOE_12M_A

12M_B

12M_A

24M_B

24M_A

X1

X2

VIOE_24M_A VIOE_24M_B

THRM

32.768K

IN

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GreenCLK 24MHz Power Must be powered if any VDDIO is powered.

CAM XTAL Power

available ~3.3V power

NOTE: 30 PPM or better required for RTC accuracy

SSD XTAL Power

System 32kHz / 12MHz / 24MHz Clock Generator

Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5

VBAT and +V3.3A are

IPD = 9-50k

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

SMC controls strap enable to allow in-field control of strap setting.

PCH ME Disable Strap

to reduce VBAT draw.

internally ORed to

+V3.3A should be first

create VDD_RTC_OUT.

No bypass necessary

SB XTAL Power

PCH 24MHz Outputs

17 31 68

22

MF

201

5%

1/20W

PLACE_NEAR=U0500.K15:5.1mm

R1927

12

12 68

13 31 16

66

MF

XDP

1/20W

5%

0201

0

R1996

12

10K

MF 201

5% 1/20W

R1995

1

2

100K

MF 201

5% 1/20W

R1920

1

2

1K

MF 201

5% 1/20W

R1921

1

2

12 68

31

MF

1/20W

5%

201

10K

R1931

1

2

25V

0201

CERM-C0G

9PF

+/-0.5PF

C1926

12

25V

0201

CERM-C0G

9PF

+/-0.5PF

C1925

12

1/20W

MF

0201

0

5%

R1925

12

NO STUFF

5% 1/20W MF

1M

201

R1928

1

2

X5R-CERM

0.1UF

10% 16V

0201

C1924

1

2

10% 16V

0201

0.1UF

X5R-CERM

C1922

1

2

CRITICAL

24.000MHZ-20PPM-9.5PF-60OHM

1.60X1.20MM-SM

Y1925

24

13

SLG3AP3405

CRITICAL

TQFN

U1900

5 9

12 4

10

71114817

2

15

6

13

3

1

16

31

0201

10% 16V

X5R-CERM

0.1UF

C1923

1

2

X5R

20%

1UF

6.3V 0201

C1901

1

2

10% 16V X5R-CERM

0.1UF

0201

C1902

1

2

SOT563

DMN5L06VK-7

Q1920

6

2

1

DMN5L06VK-7

SOT563

Q1920

3

5

4

Chipset Support

SYNC_DATE=06/28/2013

SYNC_MASTER=J92_DEVMLB

SMC_CLK12M_EN

XDP_DBRESET_L

SYSCLK_CLK12M_SSD

SYSCLK_CLK24M_CAMERA

SYSCLK_CLK12M_SMC

SYSCLK_CLK32K_PMIC

SYSCLK_CLK24M_SB

PP3V3_S0

CPU_VCCST_PWRGD

HDA_SDOUT_R

PP1V05_S0

PP5V_S0

LPC_CLK24M_SMC_R

LPC_CLK24M_SMC

PM_SYSRST_L

MAKE_BASE=TRUE

LPC_CLK24M_SMC

PP3V3_G3H

SYSCLK_CLK24M_X2_R

SYSCLK_CLK24M_X1

PP1V8_S0SW_SSD_COLD

PP3V3_S5

PP1V2_CAM_XTALPCIEVDD

PP1V5_S0

SPI_DESCRIPTOR_OVERRIDE_L

PP1V5_S0

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

SYSCLK_CLK24M_X2

<SCH_NUM>

19 OF 130

17 OF 75

54 64

24 64

68

31 64

46 64

12

8

11 12 13

15 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

8

16 46

6 8

11 15 16 32

44 46 51 60

16 25 30 39 40 44 45 47 49 51 60

17 31 68

28 30 31 32 33 34 37 42 43 60

23 50 54 56 58 59 60 64

8

11 13 15

16 22 33 37 46 47

51 59 60 73 75

24

8

11

17 40

46 60

8

11 17 40

46 60

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OUT

IN

OUT

NC

08

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Platform Reset Connections

Unbuffered

RAM Configuration Straps

LPDDR3 Alias Support

Pull-downs for chip-down RAM systems

5%

201

1/20W

MF

10K

RAMCFG3:L

R2050

1

2

5%

201

1/20W

MF

10K

RAMCFG2:L

R2051

1

2

5%

201

1/20W

MF

10K

RAMCFG1:L

R2052

1

2

5%

201

1/20W

MF

10K

RAMCFG0:L

R2053

1

2

15 16

15

16

15 16

6

18

15 18

0

MF

1/20W

0201

5%

R2072

12

13 15 16 31

2.2K

MF

1/20W

201

5%

R2000

1

2

2.2K

MF

1/20W

201

5%

R2001

1

2

MF

1/20W

5%

100K

201

R2010

1

2

14 33

13

X5R-CERM 0201

10V

10%

0.1UF

C2020

1

2

CRITICAL

74LVC1G08

SOT891

U2020

2

1

35

6

4

4.7K

MF

1/20W

5%

201

R2020

1

2

29

28 33 64

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=08/01/2013

Project Chipset Support

PLT_RESET_L

TP_CPU_MEM_RESET_L

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

MAKE_BASE=TRUE

VOLTAGE=0.6V

MAKE_BASE=TRUE

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

PPVREF_S3_MEM_VREFDQ_B

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP3V3_S0

DP_TBTSNK0_DDC_DATA DP_TBTSNK0_DDC_CLK

PPVREF_S3_MEM_VREFCA PPVREF_S3_MEM_VREFCA

TP_MEM_VDD_SEL_1V5_L

TP_CPU_MEM_RESET_L

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG0

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFDQ_A

PP3V3_SUS

PCH_SML1ALERT_L

SMC_LRESET_L

DP_TBTSNK0_HPD

E85_TEST_MODE_HPD

PP3V3_S0

DP_E85SNK_HPD

<SCH_NUM>

20 OF 130

18 OF 75

6

18

15 18

18 19

20 21 69

18 19 20 69

18 19 21 69

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

13

18 19 20 21 69

18 19 21 69

18 19 20 69

8

11 14 15

27 28 29 46

51 60

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

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IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 (1.5V) 7.70mV per step

LPDDR3 (1.2V) ?.??mV per step

DDR3L (1.35V) 6.99mV per step

NOTE: CPU DAC output step sizes:

CPU-Based Margining

VRef Dividers

7

201

MF

1%

8.2K

1/20W

R2221

1

2

201

PLACE_NEAR=R2261.2:1mm

1%

8.2K

1/20W

MF

R2262

1

2

201

MF

1/20W

1%

24.9

R2260

12

5.1

1/20W

0201

1% MF

R2263

12

10%

0.022UF

0201

X5R-CERM

6.3V

C2260

1

2

201

1%

8.2K

1/20W MF

R2261

1

2

PLACE_NEAR=R2241.2:1mm

201

1%

8.2K

1/20W

MF

R2242

1

2

201

MF

1/20W

1%

24.9

R2240

12

201

10

MF

1/20W

1%

R2243

12

6.3V X5R-CERM 0201

0.022UF

10%

C2240

1

2

MF 201

8.2K

1% 1/20W

R2241

1

2

201

1/20W

MF

10

1%

R2223

12

PLACE_NEAR=R2221.2:1mm

1/20W

MF

201

1%

8.2K

R2222

1

2

24.9

201

MF

1/20W

1%

R2220

12

0.022UF

6.3V

10%

0201

X5R-CERM

C2220

1

2

LPDDR3 VREF MARGINING

SYNC_DATE=06/28/2013

SYNC_MASTER=J92_DEVMLB

PP1V2_S3

MEM_VREFDQ_A_RC

CPU_DIMMA_VREFDQ

MEM_VREFDQ_B_RC

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

MEM_VREFCA_A_RC

MIN_NECK_WIDTH=0.2 mm

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFCA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFDQ_A

<SCH_NUM>

22 OF 130

19 OF 75

8

10 20 21

46 52 59 60 69

18 21 69

18 20 21 69

18 20 69

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VDDCA_A/B VDDCA_A/B

VDDCA_A/B

VDD2_A/B

VSS_A/B

VDD1_A/B

VDDCA_A/B VDDCA_A/B

VDDCA_A/B

VDD2_A/B VDD2_A/B

VDD2_A/B

VDD2_A/B VDD2_A/B

VDD2_A/B

VDD2_A/B VDD2_A/B

VDD2_A/B

VDDQ_A/B

VDDQ_A/B VDDQ_A/B VDDQ_A/B

VDDQ_A/B VDDQ_A/B

VSS_A/B VSS_A/B

VDD1_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VDD1_A/B

SYM 2 OF 2

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

IN IN IN IN IN

IN

NC

NC NC NC NC

NC

NC NC

IN

BI BI

BI

IN

BI BI

CKE1_B

CS1_B*

CKE1_A

CS1_A*

CS0_B*

CKE0_B

CS0_A*

CKE0_A

CA9_B

CA8_B

DQ3_A

NC

VREFDQ_A

VREFCA_A

ZQ_A

DQS3_C_A

DQS3_T_A

DQS2_C_A

DQS2_T_A

DQS1_T_A DQS1_C_A

DQS0_T_A DQS0_C_A

DQ31_A

DQ30_A

DQ29_A

DQ28_A

DQ27_A

DQ26_A

DQ25_A

DQ24_A

DQ23_A

DQ22_A

DQ21_A

DQ20_A

DQ18_A DQ19_A

DQ17_A

DQ15_A DQ16_A

DQ13_A DQ14_A

DQ12_A

DQ11_A

DQ10_A

DQ8_A DQ9_A

DQ7_A

DQ6_A

DQ5_A

DQ4_A

DQ2_A

DQ0_A DQ1_A

DM3_A

DM2_A

DM1_A

DM0_A

ODT_A

NC

VREFDQ_B

VREFCA_B

ZQ_B

DQS3_C_B

DQS3_T_B

DQS2_C_B

DQS2_T_B

DQS1_C_B

DQS1_T_B

DQS0_C_B

DQS0_T_B

DQ31_B

DQ30_B

DQ29_B

DQ28_B

DQ26_B DQ27_B

DQ25_B

DQ24_B

DQ23_B

DQ22_B

DQ21_B

DQ20_B

DQ18_B DQ19_B

DQ17_B

DQ15_B DQ16_B

DQ14_B

DQ13_B

DQ12_B

DQ11_B

DQ10_B

DQ8_B DQ9_B

DQ7_B

DQ6_B

DQ5_B

DQ4_B

DQ3_B

DQ2_B

DQ1_B

DQ0_B

DM3_B

DM2_B

DM0_B DM1_B

ODT_B

CK_T_A

CA0_A

CA5_A

CK_C_BCK_C_A

CA1_A

CA3_A

CK_T_B

CA8_A

CA2_A

CA4_A

CA6_A

CA9_A

CA0_B CA1_B CA2_B CA3_B CA4_B CA5_B CA6_B CA7_BCA7_A

SYM 1 OF 2

DDR A

DDR B

IN IN

IN IN IN IN IN IN IN IN IN IN

IN IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BYPASS=U2300.R1::5mm

20%

6.3V

10UF

0402-2

CERM-X5R

C2341

1

2

BYPASS=U2300.A15::5mm

20%

6.3V

0402-2

CERM-X5R

10UF

C2340

1

2

BYPASS=U2300.A16::5mm

CERM-X5R

20%

0402-2

6.3V

10UF

C2342

1

2

10UF

BYPASS=U2300.T1::5mm

6.3V CERM-X5R 0402-2

20%

C2343

1

2

ELPIDA

32GB-LPDDR3X64

OMIT_TABLE

CRITICAL

BGA

U2300

R1 T1

B2 A15 A16 T16

H1

L1

T8 A11

U2

C3

U3 R15 H16 B17 C17

A7

A6

E1

K1

G2

A9

B9

N1 M2

U14 E17 G17 K17 L17 P17

M7

U7 M10 U10

M3

U11

U5 B12 C12 G12 K12 M12 A13

B1 C1

A3 B3 D3 A4 B4 C4 D4 M4 U4 A5

D1

E5 F5 G5 H5 J5 K5 L5 M5 A12 D12

F1

E12 F12 H12 L12 U12 N13 U13 A14 P14 G15

G1

H15 T15 U15 G16 R16 U16 D17 F17 J17 M17

M1

N17 R17 T17 E6 M6 U6 E7 R7 T7 A8

P1

E8 M8 R8 E9 U9 E10 E11 M11

A2 C2 D2

61

7

61 69

61

7

61 69

61

7

61 69

61

61 69

61

69

61 69

7

61 69

61

69

61 69

7

69

7

69

7

20 61 69

201

MF

1/20W

1%

243

R2300

1

2

X5R

6.3V 201

10%

0.047UF

C2311

1

2

X5R

6.3V

10%

0.047UF

201

C2310

1

2

61

X5R

6.3V

0.047UF

201

10%

C2331

1

2

X5R

6.3V

10%

0.047UF

201

C2330

1

2

201

MF

1/20W

1%

243

R2320

1

2

61

CRITICAL

OMIT_TABLE

32GB-LPDDR3X64

ELPIDA

BGA

U2300

B5 L2 C5 L3 D5 L4 B6 K2 C6 K3 C9 G3

D9 G4 B10 F2 C10 F3 D10 F4

C8 H2

B8 H3

C7 J3

D7 J4

D6 K4

B7 J2

N6 H14

P8 F13

P4 L14 P11 D14

N4 L15

T10 F16 R10 E13 P10 E14 N10 E15 T11 E16 R11 D13

T2 P15

R2 P16

P2 N14

N2 N15

T5 L16

T3 N16

R3 M13

P3 M14

N3 L13 N11 C13 N12 C14 P12 C15 T13 C16 R13 B13 P13 B14

R5 K13

T14 B15 R14 B16

P5 K14

N5 K15

T6 K16

R6 J15

P6 J16

T9 F14

R9 F15

N7 J13

P7 J14

N9 G13

P9 G14

R4 M15

T4 M16

R12 D15

T12 D16

A1 A17

C11 D11

D8E3 E4 H4

J12

M9

U1 U17

N8 H13

A10 J1

U8 H17

B11 E2

7

69

7

69

20%

BYPASS=U2300.A6::5mm

1.0UF

0201-1

X5R

6.3V

C2372

1

2

20%

6.3V

BYPASS=U2300.G2::5mm

CERM-X5R

0402-2

10UF

C2371

1

2

20%

6.3V

BYPASS=U2300.A9::5mm

CERM-X5R

0402-2

10UF

C2370

1

2

6.3V X5R 0201-1

1.0UF

20%

BYPASS=U2300.L1::5mm

C2353

1

2

6.3V CERM-X5R 0402-2

10UF

20%

BYPASS=U2300.A11::5mm

C2352

1

2

10UF

0402-2

CERM-X5R

6.3V

20%

BYPASS=U2300.U2::5mm

C2351

1

2

BYPASS=U2300.B17::5mm

CERM-X5R

10UF

0402-2

6.3V

20%

C2350

1

2

BYPASS=U2300.E17::5mm

20%

1.0UF

0201-1

X5R

6.3V

C2386

1

2

BYPASS=U2300.N1::5mm

20%

1.0UF

0201-1

X5R

6.3V

C2381

1

2

BYPASS=U2300.K17::5mm

20%

6.3V

CERM-X5R

0402-2

10UF

C2385

1

2

BYPASS=U2300.A13::5mm

20%

6.3V

CERM-X5R

0402-2

10UF

C2380

1

2

BYPASS=U2300.U5::5mm

20%

1.0UF

0201-1

X5R

6.3V

C2391

1

2

BYPASS=U2300.U10::5mm

20%

6.3V

CERM-X5R

0402-2

10UF

C2390

1

2

61 69

61

69

61 69

7

61 69

61

69

7

69

7

69

7

69

7

69

7

20 69

7

20 69

0201

25V

12PF

CERM

5%

C2344

1

2

5% CERM

12PF

25V 0201

C2354

1

2

NOSTUFF

25V

+/-0.1PF

3.3PF

C0G-CERM 0201

C2345

1

2

NOSTUFF

0201

C0G-CERM

3.3PF

+/-0.1PF 25V

C2355

1

2

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

LPDDR3 DRAM Channel A (0-63)

PP1V2_S3

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_CKE<3>

MEM_A_CS_L<1>

MEM_A_CS_L<0>MEM_A_CS_L<0>

MEM_A_CKE<2>

MEM_A_CAA<9>

MEM_A_CAA<8>

=MEM_A_DQ<35>

PPVREF_S3_MEM_VREFDQ_A

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

=MEM_A_DQ<53>

=MEM_A_DQ<52>

=MEM_A_DQ<51>

=MEM_A_DQ<49>

=MEM_A_DQ<47> =MEM_A_DQ<48>

=MEM_A_DQ<45> =MEM_A_DQ<46>

=MEM_A_DQ<44>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>

=MEM_A_DQ<34>

=MEM_A_DQ<32> =MEM_A_DQ<33>

MEM_A_ODT<0>

MEM_A_ZQ_A

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<3>

=MEM_A_DQS_N<1>

=MEM_A_DQS_P<1>

=MEM_A_DQS_N<0>

=MEM_A_DQS_P<0>

=MEM_A_DQ<31>

=MEM_A_DQ<30>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<26> =MEM_A_DQ<27>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<21>

=MEM_A_DQ<20>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<17>

=MEM_A_DQ<15> =MEM_A_DQ<16>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

=MEM_A_DQ<12>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<8>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQ<3>

MEM_A_DQ<33>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

MEM_A_ODT<0>

MEM_A_CLK_P<1>

MEM_A_CAB<5>

MEM_A_CLK_N<0>MEM_A_CLK_N<1>

MEM_A_CAB<1>

MEM_A_CAB<3>

MEM_A_CLK_P<0>

MEM_A_CAB<8>

MEM_A_CAB<2>

MEM_A_CAB<4>

MEM_A_CAB<6>

MEM_A_CAB<9>

MEM_A_CAA<0> MEM_A_CAA<1>

MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7>MEM_A_CAB<7>

=MEM_A_DQ<9>

MEM_A_CAB<0>

=MEM_A_DQ<50>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

=MEM_A_DQS_P<5>

PPVREF_S3_MEM_VREFCA

MEM_A_ZQ_B

PPVREF_S3_MEM_VREFCA PPVREF_S3_MEM_VREFDQ_A

MEM_A_CKE<0>

MEM_A_CAA<4>

MEM_A_CAA<3>

MEM_A_CAA<2>

PP1V2_S3

PP1V8_S3

20 OF 75

23 OF 130

<SCH_NUM>

8

10 19 20

21 46 52 59 60 69

8

10 19 20

21 46 52 59 60 69

7

20 69

7

20 69

18 19 20

69

7

20 61 69

18 19

20 21 69 18 19 20 21 69

18 19 20 69

8

10 19 20

21 46 52 59 60 69

21 46 50 52 59 60

www.qdzbwx.com

WWW.AliSaler.Com

VDDCA_A/B VDDCA_A/B

VDDCA_A/B

VDD2_A/B

VSS_A/B

VDD1_A/B

VDDCA_A/B VDDCA_A/B

VDDCA_A/B

VDD2_A/B VDD2_A/B

VDD2_A/B

VDD2_A/B VDD2_A/B

VDD2_A/B

VDD2_A/B VDD2_A/B

VDD2_A/B

VDDQ_A/B

VDDQ_A/B VDDQ_A/B VDDQ_A/B

VDDQ_A/B VDDQ_A/B

VSS_A/B VSS_A/B

VDD1_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B

VSS_A/B

VDD1_A/B

SYM 2 OF 2

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

IN IN IN IN IN

IN

NC

NC NC NC NC

NC

NC NC

IN

BI BI

BI

BI BI

CKE1_B

CS1_B*

CKE1_A

CS1_A*

CS0_B*

CKE0_B

CS0_A*

CKE0_A

CA9_B

CA8_B

DQ3_A

NC

VREFDQ_A

VREFCA_A

ZQ_A

DQS3_C_A

DQS3_T_A

DQS2_C_A

DQS2_T_A

DQS1_T_A DQS1_C_A

DQS0_T_A DQS0_C_A

DQ31_A

DQ30_A

DQ29_A

DQ28_A

DQ27_A

DQ26_A

DQ25_A

DQ24_A

DQ23_A

DQ22_A

DQ21_A

DQ20_A

DQ18_A DQ19_A

DQ17_A

DQ15_A DQ16_A

DQ13_A DQ14_A

DQ12_A

DQ11_A

DQ10_A

DQ8_A DQ9_A

DQ7_A

DQ6_A

DQ5_A

DQ4_A

DQ2_A

DQ0_A DQ1_A

DM3_A

DM2_A

DM1_A

DM0_A

ODT_A

NC

VREFDQ_B

VREFCA_B

ZQ_B

DQS3_C_B

DQS3_T_B

DQS2_C_B

DQS2_T_B

DQS1_C_B

DQS1_T_B

DQS0_C_B

DQS0_T_B

DQ31_B

DQ30_B

DQ29_B

DQ28_B

DQ26_B DQ27_B

DQ25_B

DQ24_B

DQ23_B

DQ22_B

DQ21_B

DQ20_B

DQ18_B DQ19_B

DQ17_B

DQ15_B DQ16_B

DQ14_B

DQ13_B

DQ12_B

DQ11_B

DQ10_B

DQ8_B DQ9_B

DQ7_B

DQ6_B

DQ5_B

DQ4_B

DQ3_B

DQ2_B

DQ1_B

DQ0_B

DM3_B

DM2_B

DM0_B DM1_B

ODT_B

CK_T_A

CA0_A

CA5_A

CK_C_BCK_C_A

CA1_A

CA3_A

CK_T_B

CA8_A

CA2_A

CA4_A

CA6_A

CA9_A

CA0_B CA1_B CA2_B CA3_B CA4_B CA5_B CA6_B CA7_BCA7_A

SYM 1 OF 2

DDR A

DDR B

IN IN

IN IN IN IN IN IN IN IN IN IN

IN IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

32GB-LPDDR3X64

ELPIDA

CRITICAL

OMIT_TABLE

U2500

R1 T1

B2 A15 A16 T16

H1

L1

T8 A11

U2

C3

U3 R15 H16 B17 C17

A7

A6

E1

K1

G2

A9

B9

N1 M2

U14 E17 G17 K17 L17 P17

M7

U7 M10 U10

M3

U11

U5 B12 C12 G12 K12 M12 A13

B1 C1

A3 B3 D3 A4 B4 C4 D4 M4 U4 A5

D1

E5 F5 G5 H5 J5 K5 L5 M5 A12 D12

F1

E12 F12 H12 L12 U12 N13 U13 A14 P14 G15

G1

H15 T15 U15 G16 R16 U16 D17 F17 J17 M17

M1

N17 R17 T17 E6 M6 U6 E7 R7 T7 A8

P1

E8 M8 R8 E9 U9 E10 E11 M11

A2 C2 D2

61

7

61 69

61

7

61 69

61

7

61 69

61

61 69

61 64

69

61 69

7

61 69

61

69

61 69

7

69

7

69

7

21 61 69

243

1%

1/20W

MF

201

R2500

1

2

0.047UF

10%

201

6.3V X5R

C2511

1

2

201

0.047UF

10%

6.3V X5R

C2510

1

2

61

10%

201

0.047UF

6.3V X5R

C2531

1

2

201

0.047UF

10%

6.3V X5R

C2530

1

2

243

1% 1/20W MF 201

R2520

1

2

61

BGA

CRITICAL

OMIT_TABLE

32GB-LPDDR3X64

ELPIDA

U2500

B5 L2 C5 L3 D5 L4 B6 K2 C6 K3 C9 G3

D9 G4 B10 F2 C10 F3 D10 F4

C8 H2

B8 H3

C7 J3

D7 J4

D6 K4

B7 J2

N6 H14

P8 F13

P4 L14 P11 D14

N4 L15

T10 F16 R10 E13 P10 E14 N10 E15 T11 E16 R11 D13

T2 P15

R2 P16

P2 N14

N2 N15

T5 L16

T3 N16

R3 M13

P3 M14

N3 L13 N11 C13 N12 C14 P12 C15 T13 C16 R13 B13 P13 B14

R5 K13

T14 B15 R14 B16

P5 K14

N5 K15

T6 K16

R6 J15

P6 J16

T9 F14

R9 F15

N7 J13

P7 J14

N9 G13

P9 G14

R4 M15

T4 M16

R12 D15

T12 D16

A1 A17

C11 D11

D8E3 E4 H4

J12

M9

U1 U17

N8 H13

A10 J1

U8 H17

B11 E2

7

64 69

7

64 69

61 64 69

61

69

61 64 69

61 69

7

61 69

61

69

7

69

7

64 69

7

69

7

69

7

21 64 69

7

21 64 69

0402-2

CERM-X5R

10UF

6.3V

20%

BYPASS=U2500.U10::5mm

C2590

1

2

CERM-X5R

0402-2

6.3V

20%

10UF

BYPASS=U2500.K17::5mm

C2585

1

2

0201-1

20%

1.0UF

6.3V X5R

BYPASS=U2500.U5::5mm

C2591

1

2

6.3V X5R 0201-1

20%

1.0UF

BYPASS=U2500.E17::5mm

C2586

1

2

CERM-X5R

20%

6.3V

0402-2

10UF

BYPASS=U2500.A13::5mm

C2580

1

2

10UF

0402-2

CERM-X5R

6.3V

20%

BYPASS=U2500.A9::5mm

C2570

1

2

0402-2

CERM-X5R

10UF

6.3V

20%

BYPASS=U2500.G2::5mm

C2571

1

2

20%

1.0UF

0201-1

X5R

6.3V

BYPASS=U2500.N1::5mm

C2581

1

2

0201-1

X5R

6.3V

1.0UF

20%

BYPASS=U2500.A6::5mm

C2572

1

2

BYPASS=U2500.B17::5mm

20%

10UF

6.3V

0402-2

CERM-X5R

C2550

1

2

BYPASS=U2500.U2::5mm

20%

10UF

6.3V

0402-2

CERM-X5R

C2551

1

2

1.0UF

BYPASS=U2500.L1::5mm

20%

6.3V 0201-1

X5R

C2553

1

2

0402-2

CERM-X5R

10UF

20%

6.3V

BYPASS=U2500.A15::5mm

C2540

1

2

CERM-X5R

10UF

0402-2

6.3V

20%

BYPASS=U2500.R1::5mm

C2541

1

2

BYPASS=U2500.A16::5mm

6.3V 0402-2

10UF

20% CERM-X5R

C2542

1

2

CERM-X5R 0402-2

20%

6.3V

10UF

BYPASS=U2500.T1::5mm

C2543

1

2

BYPASS=U2500.A11::5mm

10UF

20%

6.3V 0402-2

CERM-X5R

C2552

1

2

CERM

25V 0201

5%

12PF

C2544

1

2

0201

25V

12PF

CERM

5%

C2554

1

2

NOSTUFF

25V

+/-0.1PF

3.3PF

C0G-CERM 0201

C2545

1

2

NOSTUFF

0201

C0G-CERM

3.3PF

+/-0.1PF 25V

C2555

1

2

LPDDR3 DRAM Channel B (0-63)

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PP1V2_S3

MEM_B_CAB<3>

MEM_B_CAB<2>

MEM_B_CAB<1>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_CKE<3>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_CKE<2>

MEM_B_CAA<9>

MEM_B_CAA<8>

=MEM_B_DQ<35>

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFCA

MEM_B_ZQ_B

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<5> =MEM_B_DQS_N<5>

=MEM_B_DQS_P<4> =MEM_B_DQS_N<4>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<50> =MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQ<47> =MEM_B_DQ<48>

=MEM_B_DQ<45> =MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<40> =MEM_B_DQ<41>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<34>

=MEM_B_DQ<33>

MEM_B_ODT<0>

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFCA

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

=MEM_B_DQS_N<1>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<0>

=MEM_B_DQS_P<0>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<26> =MEM_B_DQ<27>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<20>

=MEM_B_DQ<18> =MEM_B_DQ<19>

=MEM_B_DQ<17>

=MEM_B_DQ<15> =MEM_B_DQ<16>

=MEM_B_DQ<14>

=MEM_B_DQ<13>

=MEM_B_DQ<12>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQ<8>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<3>

MEM_B_DQ<32>

=MEM_B_DQ<1>

=MEM_B_DQ<0>

MEM_B_ODT<0>

MEM_B_CLK_P<1>

MEM_B_CAB<5>

MEM_B_CLK_N<0>MEM_B_CLK_N<1>

MEM_B_CLK_P<0>

MEM_B_CAB<8>

MEM_B_CAB<4>

MEM_B_CAB<6>

MEM_B_CAB<9>

MEM_B_CAA<0>

MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7>MEM_B_CAB<7>

=MEM_B_DQ<23>

=MEM_B_DQ<32>

MEM_B_ZQ_A

MEM_B_CAA<1>

PP1V2_S3

MEM_B_CAB<0>

=MEM_B_DQ<9>

PP1V8_S3

<SCH_NUM>

25 OF 130

21 OF 75

8

10 19 20

21 46 52 59 60 69

7

21 64 69

7

21 64 69

18 19

21 69

18 19 20 21 69

18 19 21 69

18 19 20 21 69

7

21 61 69

8

10 19 20

21 46 52 59 60 69

8

10 19 20

21 46 52 59 60 69

20 46 50 52 59 60

WWW.AliSaler.Com

IN

OUT

IN

NC

IN

NC NC

NC

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

NC

BI

SYM_VER_2

GS

D

OUT

SK

DO

ORG

NC

DI CS

GND

THRM

PAD

VCC

NC

IN

WP*

HOLD*

SI/SIO0 SO/SIO1

CS*

SCLK

THRM

GND

VCC

PAD

NC

B0

GND

B1

1

VCC

A

VER 1

0

SEL

NC

BT_GPIO5

HSIC_RESUME_FAST_CTS_IN/JTAG_TCK

2G_CORE0_ANT

5G_CORE0_ANT

2G_CORE1_ANT

5G_CORE1_ANT

BT_GPIO3

HOST_WAKE_BT

SEC_OUT/JTAG_TDO

JTAG_TRST SEC_IN/JTAG_TDI

JTAG_TMS

HSIC_WLAN_STROBE

BT_REG_ON

HSIC_DEV_RDY

JTAG_SEL

WLAN_REG_ON

FAST_UART_TX WL_GPIO_8

FAST_UART_RX

FAST_RTS_OUT

WL_UART_TX

WL_GPIO_9

WLAN_PCIE_RDN0

WLAN_PCIE_RDP0

WLAN_PCIE_PME

WLAN_PCIE_CLKREQ

WLAN_PCIE_TDN0

WLAN_PCIE_TDP0

WLAN_PCIE_REFCLKP

WL_HOST_WAKE

WL_GPIO_13

WL_UART_RX

WLAN_PERST

WLAN_PCIE_REFCLKN

BT_PCM_IN

BT_USB_DN

BT_USB_DP

BT_UART_TXD

BT_UART_RXD

BT_UART_CTS*

BT_PCM_OUT

BT_PCM_SYNC

BT_PCM_CLK

BT_UART_RTS*

BATT_VCC

BATT_RF_VCC

BT_WAKE

ANT_SWITCH_CORE1

ANT_SWITCH_CORE0

BT_GPIO4

CLK32K_AP

VDDIO_1P8

HSIC_HOST_READY/PCIE_DEV_WAKE

HSIC_WLAN_DATA

SYM 1 OF 2

(2 OF 2)

THRM_PAD

GND

THRM_PAD

P2

P3

P1

GND

P2

P3

P1

GND

NC NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(FW changed to BT DEVICE WAKE)

(FW changed to BT HOST WAKE)

(GPIO5)

L PCIE_WAKE_L (B0)

(GPIO12)

(GPIO13)

(GPIO10)

(GPIO6)

SEL OUTPUT

(GPIO1)

(GPIO11)

PCIe Wake Muxing

H AP_S0IX_WAKE_L (B1)

(GPIO14) (GPIO15)

(GPIO2)

(GPIO4)

(GPIO3)

(GPIO0)

(AP_PCIE_WAKE_L)

(GPIO9)

(GPIO8) (GPIO7)

CRITICAL

20449-001E-01

F-ST-SM

J3510

234

1

31 64

20449-001E-01

CRITICAL

F-ST-SM

J3520

234

1

NO STUFF

0.2PF

+/-0.1PF

16V

NP0-C0G

01005

C3517

1

2

NO STUFF

16V NP0-C0G 01005

0.2PF

+/-0.1PF

C3516

1

2

16V

NP0-C0G

0.2PF

01005

+/-0.1PF

NO STUFF

C3527

1

2

NO STUFF

16V NP0-C0G 01005

0.2PF

+/-0.1PF

C3526

1

2

0.2PF

16V

NP0-C0G

01005

+/-0.1PF

NO STUFF

C3512

1

2

OMIT_TABLE

0.3PF

+/-0.1PF 16V NP0-C0G 01005

C3513

1

2

16V

NP0-C0G

01005

0.2PF

NO STUFF

+/-0.1PF

C3522

1

2

0.2PF

+/-0.1PF

01005

NP0-C0G

16V

OMIT_TABLE

C3520

1

2

CRITICAL

CERM

0.3PF

+/-0.5PF 16V

01005

C3523

1

2

0% MF

0.00

01005

CRITICAL

1/32W

R3510

12

MF

0%

CRITICAL

1/32W 01005

0.00

R3520

12

X5R-CERM1

6.3V 402

20%

4.7UF

C3500

1

2

X5R-CERM1 402

6.3V

20%

4.7UF

C3501

1

2

20%

10UF

603

X5R

6.3V

C3503

1

2

603

10UF

20% X5R

6.3V

C3502

1

2

1/20W MF

5%

100K

201

R3561

1

2

CERM-X5R

0201

10%

0.1UF

6.3V

C3560

1

2

15 64

13

15 64

5% MF

10K

201

1/20W

R3500

1

2

31 64 23

23

23 64

12

15

16V10%

0201

0.1UF

X5R-CERM

C3553

12

10%

0201X5R-CERM

16V

0.1UF

C3552

12

0.1UF

10%

0201

16V

X5R-CERM

C3551

12

0.1UF

16V10%

0201X5R-CERM

C3550

12

14 68

14

68

14 68

31 32

14 67

5%

100K

1/20W MF 201

R3571

1

2

100K

5% MF

201

1/20W

R3572

1

2

5%

100K

1/20W

MF

201

R3573

1

2

10%

0201

0.1UF

6.3V CERM-X5R

C3570

1

2

100K

MF 201

1% 1/20W

R3530

1

2

NO_XNET_CONNECTION=TRUE

DFN1006H4-3

DMN32D2LFB4

Q3530

3

1

2

30 31

33

OMIT_TABLE

AT93C66B-MAHM

UDFN

U3580

1

34

5

7

6

2

9

8

5%

10K

1/20W MF 201

R3580

1

2

6.3V

0.1UF

10%

0201

CERM-X5R

C3580

1

2

13 64

C0G

100PF

5%

0201

25V

C3554

12

12 68

5%

100PF

C0G25V

0201

C3555

12

512KBIT

MX25V512EZUI-13G

USON

OMIT_TABLE

U3570

1

4

7

6

5 2

9

8

3

1/20W

MF

1%

22

201

NO STUFF

R3550

12

201

MF

1%

22

1/20W

NO STUFF

R3551

12

MF

1/20W

5%

201

10K

R3501

1

2

MF

1/20W

5%

10K

201

R3502

1

2

201

MF

5% 1/20W

10K

R3503

1

2

201

5% MF

10K

1/20W

R3504

1

2

CRITICAL

DFN

PI5A3157B

U3560

34

2

5

6

1

0.2PF

16V

01005

NP0-C0G

+/-0.1PF

NO STUFF

C3525

1

2

OMIT_TABLE

0.00

1/32W

0% MF

01005

R3524

12

+/-0.1PF

01005

NP0-C0G

16V

2PF

C3515

1

2

OMIT_TABLE

0.00

1/32W 01005

0% MF

R3514

12

LBEE5UA1BL-717

LGA

CRITICAL

U3500

22 31

28 39

5 2

25

35

58

20

10

21

6

7

14

18

56

9 8

13 12

4

3

16

68

46

48 54

17

47 61 62

66 65

45

63 44

41

43 42

11

51

53

52

55

50 49

80

79

76

77

70

71

74

73

1

60

LBEE5UA1BL-717

LGA

CRITICAL

U3500

15 19

34 36 37 38 40 57 59 64 67 69

23

72 75 78

24 26 27 29 30 32 33

81 82

91 92 93 94 95 96 97 98 99

100

83

101 102 103 104 105 106 107 108 109 110

84

111 112 113

114 115 116 117 118 119 120

85

121 122 123 124 125 126 127 128 129 130

86

131 132 133 134 135 136 137 138 139 140

87

141 142 143 144 145 146 147 148 149 150

88

151 152 153 154 155 156 157 158 159 160

89

161 162 163 164 165 166 167 168 169 170

90

LLP

CRITICAL

LFD2H2G45ML5D911

U3510

246

1

3

5

LFD2H2G45ML5D911

LLP

CRITICAL

U3520

246

1

3

5

OMIT_TABLE

01005

1/32W

0.00

MF

0%

R3511

12

CRITICAL

1/32W

0.00

0% MF

01005

R3521

12

NO STUFF

0.2PF

01005

+/-0.1PF 16V NP0-C0G

C3510

1

2

13

5% CERM

12PF

25V 0201

C3505

1

2

25V

12PF

CERM

5%

0201

C3506

1

2

25V

12PF

CERM

5%

0201

C3507

1

2

25V

12PF

CERM

5%

0201

C3504

1

2

IND,FILM,0.4NH,+/-0.1NH,270MA,01005

152S1544

R3511

CRITICAL

1

IND,FILM,1.8NH,+/-0.1NH,270MA,01005

152S1720

C3520

CRITICAL

1

IND,FILM,2.4NH,+/-0.1NH,200MA,01005

152S1564 CRITICAL

R3524

1

152S1742

IND,FILM,1.6NH,+/-0.1NH,200MA,01005

C3513

CRITICAL

1

131S0259

CAP,7PF,+/-0.1PF,16V,01005

CRITICAL

R3514

1

WIFI/BT: MODULE

SYNC_MASTER=J72_MLB

SYNC_DATE=11/13/2012

PP3V3_S4

AP_PCIE_WAKE_L

RF_G_1_DIPLEXER

PCIE_AP_R2D_P

PCIE_CLK100M_AP_C_P

WLAN_ROM_CLK

BTROM_WP_L

WLAN_ROM_CS

WLAN_ROM_MOSI

USB_BT_P

USB_BT_N

SMC_PME_S4_WAKE_L

PCIE_AP_D2R_P

BTROM_HOLD_L

PCIE_AP_R2D_C_N

PCIE_AP_D2R_N

PCIE_CLK100M_AP_N

WLAN_ROM_MISO

AP_S0IX_WAKE_L

AP_S0IX_WAKE_SEL

PCIE_WAKE_L

PCIE_CLK100M_AP_P

WLAN_ROM_ORG

TP_JTAG_WLAN_TMS

SMC_BT_PWR_EN

JTAG_WLAN_SEL

WLAN_ROM_CLK WLAN_ROM_CS

WLAN_ROM_MISO

PCIE_AP_R2D_N

AP_CLKREQ_L

PCIE_AP_D2R_C_N

SMC_WIFI_EVENT_L

AP_RESET_L

PCIE_CLK100M_AP_C_N

BT_SPI_MISO

USB_BT_R_N

USB_BT_R_P

BT_UART_R2D

BT_UART_CTS_L

BT_SPI_MOSI

BT_UART_RTS_L

BT_GPIO4

PCIE_AP_R2D_C_P

PCIE_AP_D2R_C_P

BT_DEV_WAKE

SMC_WIFI_PWR_EN

RF_1_ANT

RF_0_ANT

RF_0_ANT_MATCH_T

RF_1_ANT_MATCH_T

RF_A_1_DIPLEXER

RF_A_0_DIPLEXER

BT_SPI_MISO

BT_SPI_MOSI

BT_SPI_CS_L BT_SPI_CLK

PP3V3_S4

RF_G_0_DIPLEXER

RF_G_0_MATCH

RF_A_0_MATCH

RF_G_1_MATCH

RF_A_1_MATCH

AP_PCIE_DEV_WAKE

BT_LOW_PWR_L

TP_JTAG_WLAN_TDO

JTAG_WLAN_TDI

TP_JTAG_WLAN_TCK

PP3V3_S5

WLAN_ROM_MOSI

TP_JTAG_WLAN_TRST

BT_UART_D2R

BT_SPI_CS_L

BT_SPI_CLK

<SCH_NUM>

35 OF 130

22 OF 75

22 23 28

29

30 32 33 50

51 60

64

73

68

22

68

22

67

22

68

64

73

73 73

73

22

22 23 28 29 30 32 33 50 51 60

73 73

73

8

11 13 15

16 17 33 37 46 47

51 59 60 73 75

22

WWW.AliSaler.Com

IN

OUT OUT

DIR2

A2

A1

DIR1

OE*

GND

B1 B2

VCCBVCCA

OUT

IN

SYM_VER_2

GS

D

OUT

OUT IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

OUT

IN

NC

08

NC

OUT

IN

D

SYM_VER_3

SG

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Bootloader Enable

BT UART CTS# Isolation

SEL OUTPUT

(PCH_UART_SSD_L_BT_H_RC)

L SSD (M) H BT (D)

PCH UART CTS# Isolation

SSD/PCH Level Shifter

PCH UART BT/SSD MUX

22 usec tau

14 66

14

66

14 66

X5R-CERM

16V

0201

GND_VOID=TRUE

0.1UF

10%

C3716

12

16V

0201X5R-CERM

GND_VOID=TRUE

10%

0.1UF

C3717

12

16V

0201X5R-CERM

GND_VOID=TRUE

0.1UF

10%

C3713

12

GND_VOID=TRUE

16V

0201X5R-CERM

0.1UF

10%

C3712

12

16V

GND_VOID=TRUE

0201X5R-CERM

0.1UF

10%

C3715

12

0201

GND_VOID=TRUE

X5R-CERM

16V

0.1UF

10%

C3714

12

16V

X5R-CERM 0201

GND_VOID=TRUE

0.1UF

10%

C3711

12

16V

GND_VOID=TRUE

0.1UF

10%

0201X5R-CERM

C3710

12

64 66

64

66

64 66

QFN

SN1203086RSWR

U3750

8 9

5 4

10

1

3

2

7

6

X5R-CERM

10%

0201

10V

BYPASS=U3750.9:7:5mm

0.1UF

C3750

1

2

54 59 64

54

59 64

13 64

DMN32D2LFB4

DFN1006H4-3

Q3700

3

1

2

54 59 64

0201

X5R-CERM

10V

10%

0.1UF

BYPASS=U3750.6:7:5mm

C3751

1

2

22

201

100K

MF

5% 1/20W

R3750

1

2

1/20W MF

100K

5%

201

R3751

1

2

MF

5%

201

1/20W

100K

R3752

1

2

100K

MF

1/20W 201

5%

R3753

1

2

PI3USB102EZLE

TQFN

CRITICAL

U3755

6

7

3

4

5

8

10

9

2

1

BYPASS=U3755.9:3:5mm

0.1UF

0201

X5R-CERM

10% 10V

C3755

1

2

15 64

22 64

SOT891

74LVC1G08

CRITICAL

U3756

2

1

35

6

4

X5R-CERM

10%

0.1UF

0201

10V

BYPASS=U3756.6::5mm

C3756

1

2

22 64

15 64

15

MF 201

5% 1/20W

330K

R3711

1

2

31 54

DMN32D2LFB4

DFN1006H4-3

Q3720

3

1

2

4.7K

5%

201

1/20W

MF

R3720

1

2

10K

1/20W

MF

5%

201

R3722

12

0201

10%

2.2NF

X5R-CERM

10V

C3722

1

2

12 16

10% 10V

X5R-CERM

2.2NF

0201

R3721

12

SSD Support

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=09/11/2013

PP1V8_S0SW_SSD_COLD

SMC_OOB1_D2R_L

SSD_UART_D2R

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<0>

PCH_BT_UART_RTS_L

BT_UART_CTS_L

PCH_UART_SSD_L_BT_H_RC

PCH_UART_SSD_L_BT_H

BT_UART_RTS_L

PCH_BT_UART_CTS_L

BT_UART_R2D

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_P<3>

PP3V3_S0

PCH_UART_SSD_L_BT_H_RC

PCH_BT_UART_R2D PCH_BT_UART_D2R

BT_UART_D2R

PP3V3_S4

S1X_DEBUG_UART_R2D

PCIE_SSD_R2D_N<2>

SSD_UART_BOOT_L

S1X_DEBUG_UART_D2R

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_N<3> PCIE_SSD_R2D_P<3>

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_N<3>

SSD_BOOT

SSD_UART_R2D

PP3V3_S0

<SCH_NUM>

37 OF 130

23 OF 75

17 50 54

56 58 59 60 64

23

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

23

22 23 28 29 30 32 33 50 51 60

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

WWW.AliSaler.Com

NC NC

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

BI BI BI

BI BI

OUT OUT OUT

IN

OUT

IN

OUT

SYM 1 OF 3

DEBUG_15

DEBUG_14

PWR_MODE

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03 DEBUG_04 DEBUG_05

DEBUG_09

PCIE_RDP0

DEBUG_06

DEBUG_00 DEBUG_01 DEBUG_02

DEBUG_07 DEBUG_08

DEBUG_10 DEBUG_11 DEBUG_12 DEBUG_13

DEBUG_16

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

I2C_CLK_DBG I2C_CLK_SENSOR I2C_DATA_DBG I2C_DATA_SENSOR

JTAG_TCK JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS UARTRTS

UARTRXD UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1 MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 3 OF 3

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00 DDR_AD01 DDR_AD02 DDR_AD03 DDR_AD04 DDR_AD05 DDR_AD06 DDR_AD07 DDR_AD08 DDR_AD09 DDR_AD10 DDR_AD11 DDR_AD12 DDR_AD13 DDR_AD14

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CS*

DDR_DM0 DDR_DM1

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

NC NC NC NC

NC

NC NC NC

NC NC NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PU = 25MHz

PD = 24MHz

L3901:1

PD = 1.35V

PU on PCH page

(=PP3V3_S0_CAMERA)

L3902:1

(=PP3V3_S0_CAMERA)

12

63

53

15 64

15

6.3V CERM-X5R 0201

0.1UF

10%

C3900

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C3924

1

2

0201-1

1.0UF

6.3V X5R

20%

C3923

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C3922

1

2

0201-1

1.0UF

6.3V X5R

20%

C3921

1

2

6.3V CERM-X5R 0201

0.1UF

10%

BYPASS=U3900.D6::2.54MM

C3910

1

2

BYPASS=U3900.D6::2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3951

1

2

100K

MF

1/20W

5%

201

R3901

1

2

17 64 68

25

68

25 68

MF 201

1/20W

5%

100K

CAM_XTAL:YES

R3906

1

2

MF 201

100K

5%

CAM_XTAL:NO

1/20W

R3907

1

2

201

100K

MF

5% 1/20W

CAM_FREQ:25M

R3904

1

2

PLACE_NEAR=U3900.M13:4MM

1.0UH-1.6A-55MOHM

1008

L3901

12

1008

1.0UH-1.6A-55MOHM

PLACE_NEAR=U3900.K13:4MM

L3902

12

4.7UF

BYPASS=U3900.K13::2.54MM

6.3V X5R 402

20%

C3912

1

2

PLACE_NEAR=U3900.M13:2.54MM

4.7UF

6.3V X5R 402

20%

C3915

1

2

22NH

0402

L3906

12

BYPASS=U3900.L7::2.54MM

CERM-X5R 0201

0.1UF

10%

6.3V

C3916

1

2

4.7UF

X5R 402

20%

6.3V

C3928

1

2

PLACE_NEAR=U3900.M14:2.54MM

6.3V

4.7UF

X5R 402

20%

C3926

1

2

6.3V

0.1UF

BYPASS=U3900.J1::2.54MM

0201

CERM-X5R

10%

C3919

1

2

BYPASS=U3900::5mm

6.3V CERM-X5R 0201

0.1UF

10%

C3937

1

2

CERM-X5R

BYPASS=U3900::5mm

6.3V 0201

0.1UF

10%

C3935

1

2

BYPASS=U3900::5mm

6.3V CERM-X5R 0201

0.1UF

10%

C3940

1

2

BYPASS=U3900::7mm

4.7UF

6.3V X5R 402

20%

C3942

1

2

BYPASS=U3900.F15::2.54MM

2.2UF

402-LF

CERM

6.3V

20%

C3941

1

2

BYPASS=U3900.G15::2.54MM

1UF

X5R 402

10V

10%

C3939

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C3960

1

2

BYPASS=U3900.J1::2.54MM

1000PF

16V

10%

0201

X7R-1

C3918

1

2

BYPASS=U3900::3mm

X7R-1 0201

1000PF

16V

10%

C3934

1

2

X7R-1 0201

BYPASS=U3900.L7::2.54MM

16V

1000PF

10%

C3917

1

2

0201

1000PF

10% 16V X7R-1

BYPASS=U3900::3mm

C3936

1

2

BYPASS=U3900.D7::2.54MM

16V

1000PF

0201

10% X7R-1

C3938

1

2

25 71

25

71

25 71

25 64 71

25 71

25 64 71

25 71

25

NO STUFF

MF

1/20W

100K

5%

201

R3910

1

2

100K

5% MF

1/20W 201

R3911

1

2

MF

1%

240

1/20W

201

R3912

12

1K

1/20W

5% MF

201

R3913

1

2

201

MF

5%

1/20W

1K

R3914

1

2

25 71

SM

XW3900

12

SM

XW3901

12

1/20W

5% MF

100K

201

R3990

1

2

6.3V

0.1UF

10% 0201

CERM-X5R

C3927

1

2

1.0UF

0201-1

X5R

20%

6.3V

C3930

1

2

25 71

1.0UF

0201-1

6.3V X5R

20%

C3932

1

2

6.3V CERM-X5R 0402-1

10UF

20%

C3931

1

2

6.3V CERM-X5R

10UF

20%

0402-1

C3933

1

2

4.7UF

6.3V X5R 402

20%

C3914

1

2

4.7UF

6.3V X5R 402

20%

C3913

1

2

0603

220-OHM-1.4A

L3903

12

0603

220-OHM-1.4A

L3904

12

BYPASS=U3900.L9::2.54MM

6.3V CERM-X5R 0201

10%

0.1UF

C3975

1

2

0.1UF

10%

6.3V

BYPASS=U3900.L9::2.54MM

CERM-X5R 0201

C3974

1

2

BYPASS=U3900.F9::2.54MM

16V

1000PF

X7R-1

10% 0201

C3973

1

2

BYPASS=U3900.F9::2.54MM

6.3V CERM-X5R 0201

10%

0.1UF

C3972

1

2

BYPASS=U3900.F6::2.54MM

0201

16V

1000PF

10% X7R-1

C3971

1

2

BYPASS=U3900.F6::2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3970

1

2

MF

5%

51K

1/20W 201

R3975

1

2

MF

1/20W

51K

5%

201

R3976

1

2

MF

100K

1/20W

5%

201

R3920

1

2

1/20W MF

5%

100K

201

R3921

1

2

25 71

5%

201

1/20W

MF

100K

R3991

1

2

5%

25V

0201

C0G

CAM_XTAL:NO

100PF

C3901

1

2

FBGA

CRITICAL

BCM15700A2KFEB4G

U3900

B11 C14 B14 A15 E11 E10 F11 F10 G11 G10 H11 H10 J10 K11 K10 L11 L10

R12 P12 P11 P10 P9 N11 N10 N9

D15 R10 C15

R9

C11

F13 E12 F12 D12 D11

R7

P7

R8

R6

P8

P6

P13

A7

B7

A10

B10

R14

B8

A8

C9

B9

N12

G12 E15 R13 H12

C13

C12

M10

J12

D13 D14

E13 E14

A12

A13

FBGA

CRITICAL

BCM15700A2KFEB4G

U3900

J1

A4 D4 G4 K4 N4

G5

N5

N7 N8 N6

L7

D7

C10

C7

D9

C8

D6

G14 M12

N13 P14 P15 R15

K15 L12 L13 L14 L15

M14 M15 N15

H14 H15 J13 J14 J15

M13 N14

K13 K14

F15

G15

F14

J11

F6 F7 F8 F9 L6 L5 L8 L9

B15

R11

M11 K12

A1 A6

G9 H5 H6 H7 H8 H9 J5 J6 J7 J8

B6

J9 K1 K5 K6 K7 K8 K9

A14

M9 N1

D1

P5 R1 R5

E9

D5 E5 G1 G6 G7 G8

B13

B12

FBGA

CRITICAL

BCM15700A2KFEB4G

U3900

L3 M4 N3 M3 M1 M2 P4 N2 P3 P2 J4 R2 L1 P1 R4

K3 L2 K2

H4

G2

H2

J3 L4

C1 C4

C2 E3 E4 D3 F3 F1 F4 F2 B5 C3 B1 B4 A5 C5 B2 B3

D2

A3

E2

A2

H3

R3

J2

G3

MF 201

1/20W

5%

100K

CAM_FREQ:24M

R3905

1

2

SYNC_MASTER=J92_DEVMLB

Camera 1 of 2

SYNC_DATE=07/24/2013

P1V35_CAM_SRVLXD_PHASE

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.35V

PP1V35_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

PP1V2_CAM_XTALPCIEVDD

VOLTAGE=1.2V

PP1V2_CAM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V8_CAM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

P1V2_CAM_SRVLXC_PHASE

VOLTAGE=1.35V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V35_DDR_CLK

MIN_LINE_WIDTH=0.6MM

PP0V675_CAM_VREF

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V2_CAM_PCIE_VDD_FLT

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

GND_CAM_PVSSC

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND_CAM_PVSSD

VOLTAGE=0V

PP1V35_CAM

GND_CAM_PVSSD

GND_CAM_PVSSC

PP1V35_CAM

PP1V2_CAM

PP1V2_CAM_XTALPCIEVDD

MEM_CAM_CLK_N

MEM_CAM_CLK_P

MEM_CAM_CAS_L

MEM_CAM_RAS_L

MEM_CAM_CKE

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5> MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_CS_L

MEM_CAM_DM<0> MEM_CAM_DM<1>

MEM_CAM_DQ<0> MEM_CAM_DQ<1> MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4> MEM_CAM_DQ<5> MEM_CAM_DQ<6>

MEM_CAM_DQ<8> MEM_CAM_DQ<9> MEM_CAM_DQ<10> MEM_CAM_DQ<11> MEM_CAM_DQ<12> MEM_CAM_DQ<13> MEM_CAM_DQ<14> MEM_CAM_DQ<15>

MEM_CAM_DQS_N<0>

MEM_CAM_DQS_N<1>

MEM_CAM_DQS_P<0>

MEM_CAM_DQS_P<1>

MEM_CAM_RESET_L

MEM_CAM_WE_L

MEM_CAM_ZQ_S2

CAM_PWR_SEL

TP_CAM_PCIE_WAKE_L

CAMERA_CLKREQ_L

TP_CAM_JTAG_SRST_L

TP_CAM_JTAG_TMS

TP_CAM_JTAG_TDO

PCIE_CLK100M_CAMERA_C_N

TP_CAM_LV_JTAG_TCK TP_CAM_LV_JTAG_TDI TP_CAM_LV_JTAG_TDO

PCIE_CAMERA_R2D_P

TP_CAM_LV_JTAG_TMS

TP_CAM_TEST_MODE0 TP_CAM_TEST_MODE1 TP_CAM_TEST_MODE2

TP_CAM_LV_JTAG_TRSTN

TP_CAM_RAMCFG0 TP_CAM_RAMCFG1 TP_CAM_RAMCFG2

TP_CAM_GPIO3 I2C_CAM_SMBDBG_CLK I2C_CAM_SCK I2C_CAM_SMBDBG_DAT I2C_CAM_SDA

TP_CAM_JTAG_TCK TP_CAM_JTAG_TDI

MIPI_CLK_P

PCIE_CAMERA_R2D_N

PCIE_CLK100M_CAMERA_C_P

CAMERA_RESET_L

PCIE_CAMERA_D2R_C_N

CAM_DEBUG_RESET_L

CAMERA_PWR_EN

CAM_UARTCTS

TP_CAM_UARTRTS

CAM_UARTRXD

TP_CAM_UARTTXD

CLK25M_CAM_CLKN

SYSCLK_CLK24M_CAMERA

MIPI_DATA_P

PCIE_CAMERA_D2R_C_P

CAM_XTAL_FREQ

CAM_XTAL_SEL

CAM_TEST_OUT

CAM_TEST_MODE

CAM_TEST_OUT

CAM_TEST_MODE

PP1V2_CAM_XTALPCIEVDD

P1V35_CAM_SRVLXD_PHASE

CAM_UARTRXD

CAM_UARTCTS

GND_CAM_PVSSD

I2C_CAM_SMBDBG_CLK

PP1V8_CAM

P1V2_CAM_SRVLXC_PHASE

GND_CAM_PVSSC

PP1V2_CAM_XTALPCIEVDD

PP1V2_CAM

I2C_CAM_SMBDBG_DAT

PP1V8_CAM

MIPI_CLK_N

MIPI_DATA_N

PP1V8_CAM

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V2_CAM_PCIE_PVDD_FLT

PP3V3_S0

CAM_XTAL_SEL

CAM_SENSOR_WAKE_L

MEM_CAM_DQ<7>

TP_CAM_JTAG_TRST_L

CAM_XTAL_FREQ

<SCH_NUM>

39 OF 130

24 OF 75

24

24 25 71

17 24

24

25

71

24

24 25 71

24

24 25 71

24

17 24

24

68

24

24 17 24

24

17 24

24

8

11

12 13 15 17

18

23 29

32 33 34 35 36

40 46

47 53 60 73

75

24 24

WWW.AliSaler.Com

OUT

IN

OUT

SYM_VER-1

A4

A14

DQSL*

DQL1

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML DMU

DQL5 DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NC NC NC NC NC

BI BI BI BI BI BI BI BI

BI BI

IN IN

BI BI BI BI BI BI BI BI

IN

IN IN IN

IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN IN

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

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4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

96.2 mA peak

77.2 mA nominal max

CAMERA SENSOR

24 68

14

64 68

14 64 68

10%

0.1UF

X5R-CERM 0201

16V

C4033

12

10%

0.1UF

X5R-CERM 0201

16V

C4032

12

10%

0.1UF

16V

0201X5R-CERM

C4031

12

10%

0.1UF

16V

0201X5R-CERM

C4030

12

14 68

24

68

24 68

BYPASS=U4000.H9::4mm

201

20% 4V CERM-X5R-1

0.47UF

C4004

1

2

20%

402

BYPASS=U4000.K2::4mm

X5R-CERM

2.2UF

10V

C4008

1

2

20%

402

BYPASS=U4000.D2::4mm

2.2UF

X5R-CERM

10V

C4006

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C4009

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U4000.R9::4mm

C4007

1

2

402

20%

0.1uF

10V

CERM

C4013

1

2

10% 0201

CERM-X5R

6.3V

0.1UF

C4005

1

2

24 71

24

71

24 71

0402-LF

FERR-120-OHM-1.5A

L4010

12

BYPASS=U4000.B2::4mm

20%

10UF

0402-1

CERM-X5R

6.3V

C4003

1

2

10UF

20%

0402-1

CERM-X5R

6.3V

BYPASS=U4000.A1::4mm

C4002

1

2

90-OHM-0.1A-0.7-2GHZ

TAM0605

CRITICAL

L4009

1

23

4

90-OHM-0.1A-0.7-2GHZ

TAM0605

CRITICAL

L4007

1

23

4

1K

MF

1/20W

201

1%

R4022

1

2

1K

MF

1/20W

201

1%

R4023

1

2

FBGA

4GB-DDR3L-256MX16

EDJ4216EFBG-GNL-F

CRITICAL

U4000

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

F3 G3

C7 B7

D7 C3 C8 C2 A7 A2 B8 A3

J1 J9 L1 L9 M7

K1

J3

T2

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

24 71

6.3V CERM-X5R 0201

0.1UF

10%

C4011

1

2

24 71

24

71

24 71

10%

0.1UF

0201

CERM-X5R

6.3V

C4010

1

2

24 71

24

71

24 71

24

24 64 71

24 71

201

1/20W MF

1%

84.5

R4020

1

2

24 71

24

71

24 71

24 64 71

24 71

5%

201

1/20W

MF

1K

R4002

1

2

201

1/20W MF

1%

240

R4004

1

2

10%

0.1UF

X5R-CERM 0201

16V

C4061

12

10%

0.1UF

X5R-CERM 0201

16V

C4062

12

53 71

53

71

53 71

24 71

24 68

12 68

SYNC_DATE=10/10/2013

SYNC_MASTER=J92_DEVMLB

Camera 2 of 2

MIPI_CLK_CONN_N

MEM_CAM_ODT

MIN_NECK_WIDTH=0.2 mm

PP5V_S0_ALSCAM_F

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

MIPI_DATA_CONN_N

VOLTAGE=0.675V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP0V675_MEM_CAM_VREFCA

MEM_CAM_ZQ_DDR

MEM_CAM_CKE

MEM_CAM_CLK_P

MEM_CAM_A<13>

MEM_CAM_A<5>

MEM_CAM_A<4>

PCIE_CLK100M_CAMERA_C_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_N

PCIE_CAMERA_D2R_C_N

MEM_CAM_WE_L

MEM_CAM_CS_L

MEM_CAM_CAS_L

MEM_CAM_RAS_L

MEM_CAM_BA<2>

MEM_CAM_BA<0>

MEM_CAM_A<12>

MEM_CAM_A<9> MEM_CAM_A<10>

MEM_CAM_A<7>

MEM_CAM_A<1>

MEM_CAM_DQ<13>

MEM_CAM_DQ<9>

MEM_CAM_DQS_P<1>

MEM_CAM_DM<1>

MEM_CAM_DQS_N<1>

MEM_CAM_DQ<15> MEM_CAM_DQ<8>

MEM_CAM_DQ<12>

MEM_CAM_DQ<14> MEM_CAM_DQ<11>

MEM_CAM_DQ<0>

MEM_CAM_DQ<3>

MEM_CAM_DQ<1>

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_N

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_P

PCIE_CAMERA_R2D_C_P

MEM_CAM_DM<0>

MEM_CAM_A<6>

MEM_CAM_A<0>

MEM_CAM_A<3>

MEM_CAM_RESET_L

PCIE_CLK100M_CAMERA_P

MEM_CAM_A<11>

MEM_CAM_BA<1>

MEM_CAM_DQ<10>

PP5V_S0

MIPI_CLK_N

MIPI_CLK_P

MIPI_DATA_N

MIPI_DATA_P

MIPI_DATA_CONN_P

MIPI_CLK_CONN_P

MEM_CAM_CLK_N

MEM_CAM_A<2>

MEM_CAM_A<8>

MEM_CAM_A<14>

PP1V35_CAM

PP0V675_CAM_VREF

MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<0>

MEM_CAM_DQ<7>

MEM_CAM_DQ<2>

MEM_CAM_DQ<6>

MEM_CAM_DQ<5>

MEM_CAM_DQ<4>

<SCH_NUM>

40 OF 130

25 OF 75

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71

16 17 30

39 40 44 45 47 49 51

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24 71

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IN

IA_P

OD_P OD_N

OC_N

OC_P

OB_N

OB_P

OA_N

OA_P

CROSS

EN

ID_P ID_N

IC_N

IC_P

IB_P IB_N

IA_N

VDD

VSS

NC

BI

BI BI

BI

NC NC

SBI

INB+

VCC

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

SAI

INB-

GND

THRM

ENB

PAD

IN IN

IN IN IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

IN

BI

BIIN

IN

BI BI

IN OUT

OUT

IN

BI

SYM_VER-1

BI BI

VCC

D

B

AY

OE*

C

GND

ENB

EPAD

GND

INB-

SAI

INA+

ENA

SBO

OUTB0+ OUTB0-

OUTB1-

OUTB1+

SAO

OUTA0-

OUTA0+

OUTA1-

OUTA1+

VCC

INB+

SBI

INA-

VER 2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Mode DX_EN DEBUG_A_EN DEBUG_B_EN DEBUG_FLIP_L SMC_SWD_EN HPM_SWD_EN INA DXDEBUG

Empty 0 X X Hi-Z Hi-Z

DP 0 X X Hi-Z AUX+/HPD 0 X 0

HPM SWD 0 X 1 1 X 1 OUTB1 SWD (HPM)

X 1 1 X 0 OUTB0 1 X 0 0 X OUTA0

1 X 1 0 X OUTA0

X 0 1

SMC SWD 0 1 X 0 1 X OUTA1 SWD (SMC)

Mojo 1 1 1 1 OUTB1 UART (SMC)

Empty 0 0 X X Hi-Z Hi-Z

Mode DX_EN M_EN M_SEL0 M_SEL1 INB Mission

0 X 0

Mode RFU_EN_L DEBUG_A_EN DEBUG_B_EN DEBUG_FLIP_L SMC_SWD_EN HPM_SWD_EN INB RFU

(DEBUG_A_EN)

X 0 1

No Debug 1 X X Hi-Z Hi-Z

(DEBUG_B_EN)

1=D

0=M

(DEBUG_FLIP_L)

Y=(C*B) + (!C*A)

1=D

0=M

0 X 1 X 0 0

X 0 0

0 X 1

Mojo 1 UART (SMC)

SMC SWD 1 1 X 1 1 X OUTA1 SWD (SMC)

X 1 0 X 0 OUTB0

HPM SWD 1 X 1 0 X 1 OUTB1 SWD (HPM)

Empty 1 X X Hi-Z Hi-Z

Mojo 0 UART (SMC)

USB (Host) 1 1 1 0 OUTA1 USB (PCH)

(DP_E85SNK_AUXCH_P) (DP_E85SNK_AUXCH_N)

Dx2

Dx1

HPM UART 1 1 0 1 OUTB0 UART (HPM)

USB (Device) 1 1 0 0 OUTA0 USB (HPM)

0.1UF

10%

0201

X5R-CERM

10V

C4400

1

2

28

10V

10%

0201

X5R-CERM

0.1UF

C4440

1

2

SIGNAL_MODEL=XBAR_1TO2

XFBGA

CBTL04043A1EX

CRITICAL

U4440

C1

F4

H1

G1

H2

G2

H3

G3

H4

G4

D2D3D4E1E2E3E4

D1

B1

A1

B2

A2

B4

A4

B3

A3

C4

F1

29 64 68

29 64

68

29 64 68

CRITICAL

SIGNAL_MODEL=TS3DS10224_EMPTY

QFN

TS3DS10224

U4450

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

1415

1211

21

13

10V 0201

0.1UF

10% X5R-CERM

C4450

1

2

28

TQFN

PI3USB102EZLE

CRITICAL

U4470

6

7

3

4

5

8

10

9

2

1

10%

0.1UF

0201

10V X5R-CERM

C4470

1

2

28

28 29

X5R-CERM

10V

0201

0.1UF

10%

C4490

1

2

TQFN

PI3USB102EZLE

CRITICAL

U4490

6

7

3

4

5

8

10

9

2

1

28

29 64

29 64 28

28

29

66

29 66

31 32 64 67

28

MF

1/20W

0201

5%

0

R4456

12

5%

0

0201

1/20W

MF

R4455

12

31 32 37

62

31 32 37 62

0201

5%01/20W

MF

R4466

12

0201

MF

1/20W

5%

0

R4465

12

28

14 64 67

14

64 67

CRITICAL

DLP0NS

90-OHM

L4405

12

34

5%

0

0201

1/20W

MF

R4410

12

MF

0201

0

5%

1/20W

R4411

12

29

SOT833

74LVC1G99

CRITICAL

U4465

2 3 5 6

4

1

8

7

0.1UF

X5R-CERM

10%

0201

10V

C4465

1

2

SIGNAL_MODEL=E85_USBMUX

CRITICAL

QFN

PI3DBS3224

U4400

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

1415

1211

21

13

1M

201

MF

1/20W

5%

R4412

1

2

Low Speed MUXing

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=07/08/2014

USB_BC1P2_N

E85LSMUX_DEBUG_A_EN

E85LSMUX_M_SEL0

SMC_DEBUGPRT_TX_L

USB_EXTA_F_N

PP3V3R3V0_AON

E85LSMUX_M_EN

E85_LS_MISSION_N

SMC_DEBUGPRT_RX_L

USB_HPM_R_N

E85LSMUX_M_SEL1

E85_LS_N<2>

E85_LS_P<2>

E85_LS_N<1>

E85_LS_P<1>

HPM_UART_TX

USB_HPM_R_P

USB_EXTA_F_P

E85_LS_RFUDEBUG_RX_DAT

DP_E85SNK_AUXCH_N

E85LSMUX_RFU_EN_L

HPM_SWCLK_R

E85LSMUX_HPM_SWD_EN

E85LSMUX_RFU_FLIP

E85_LS_RFU_AUXP_TX_CLK

E85LSMUX_DX_EN E85LSMUX_DX_FLIP

USB_BC1P2_P

HPM_SWCLK

HPM_SWDIO_R

E85LSMUX_SMC_SWD_EN

SMC_TMS

SMC_TCK

E85LSMUX_RFU_SEL_DEBUG

E85_RFU<1> E85_RFU<2>

SMC_SWDIO_R

SMC_SWCLK_R

E85_LS_RFU_AUXN_RX_DAT

HPM_SWDIO

DP_E85SNK_AUXCH_P

E85_LS_RFUDEBUG_TX_CLK

E85LSMUX_DEBUG_B_EN E85LSMUX_DEBUG_FLIP_L

E85_LS_MISSION_P

E85_LS_DXDEBUG_TX_CLK E85_LS_DXDEBUG_RX_DAT

HPM_UART_RX

USB_EXTA_N

USB_EXTA_P

<SCH_NUM>

44 OF 130

26 OF 75

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28 29 34

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67

68

WWW.AliSaler.Com

NC

NC NC

OUT OUT

IN IN

IN

OUT OUT

IN IN

IN

VER 3

D

SG

VER 3

D

SG

IA_P

OD_P OD_N

OC_N

OC_P

OB_N

OB_P

OA_N

OA_P

CROSS

EN

ID_P ID_N

IC_N

IC_P

IB_P IB_N

IA_N

VDD

VSS

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U4520 enabled if HS_EN high and

(E85HSMUX_DP_EN_L)

DP_EN_L low (DP mode) or USB_EN low (DCI mode).

DCI (Debug) 1 1 0 (ML2) (ML3) DCI-R2D DCI-D2R

NOTE: Invert HS_FLIP in DCI mode to put DCI-USB on USB3 pins. USB3 and DP not usable in DCI mode.

DPx4 (Passive) 1 0 0 ML2 ML3 ML1 ML0

USB3/DPx2 1 0 1 R2D D2R ML1 ML0

USB3 1 1 1 R2D D2R Hi-Z Hi-Z

Empty 0 X X Hi-Z Hi-Z Hi-Z Hi-Z

Mode HS_EN DP_EN_L USB_EN SSTx1 SSRx1 SSTx2 SSRx2

HS_FLIP swaps Tx1/2 and Rx1/2

Pins A1, A4, G1, G2, G3 & G4:

Pins B1, B4, H1, H2, H3 & H4:

29 68

29

68

29 68

29 67

29 68

14 67

29 68

28

DMN5L06VK-7

CRITICAL

SOT563

Q4530

6

2

1

SOT563

CRITICAL

DMN5L06VK-7

Q4530

3

5

4

100K

5%

201

1/20W

MF

R4530

1

2

0.1UF

0201

10% 10V

X5R-CERM

C4520

1

2

CKPLUS_WAIVE=PdifPr_badTermCKPLUS_WAIVE=PdifPr_badTerm

CKPLUS_WAIVE=NdifPr_badTermCKPLUS_WAIVE=NdifPr_badTerm

SIGNAL_MODEL=XBAR_2TO1

CKPLUS_WAIVE=PdifPr_badTerm

CKPLUS_WAIVE=NdifPr_badTerm

CKPLUS_WAIVE=PdifPr_badTermCKPLUS_WAIVE=PdifPr_badTerm

CKPLUS_WAIVE=NdifPr_badTermCKPLUS_WAIVE=NdifPr_badTerm

CKPLUS_WAIVE=PdifPr_badTerm

CKPLUS_WAIVE=NdifPr_badTerm

CRITICAL

CBTL04043A1EX

XFBGA

U4520

C1

F4

H1

G1

H2

G2

H3

G3

H4

G4

D2D3D4E1E2E3E4

D1

B1

A1

B2

A2

B4

A4

B3

A3

C4

F1

High Speed MUXing

SYNC_MASTER=DEV_MLB

SYNC_DATE=04/17/2014

PP3V3_SUS

E85HSMUX_USB_EN E85HSMUX_DP_EN

E85HSMUX_DP_EN_L

DP_E85SNK_ML_N<1> DP_E85SNK_ML_P<1>

DP_E85SNK_ML_N<0> DP_E85SNK_ML_P<0>

USB3_EXTD_D2R_N

USB3_EXTD_R2D_N USB3_EXTD_R2D_P

E85HSMUX_HS_EN

E85HSMUX_DPRDCI_EN

E85_HS_DP_ML0_N E85_HS_DP_ML0_P

E85_HS_DP_ML1_N E85_HS_DP_ML1_P

USB3_EXTD_D2R_P

<SCH_NUM>

45 OF 130

27 OF 75

8

11 14 15

18 28 29 46 51 60

28 29 50 62 64

28 29

WWW.AliSaler.Com

OUT BI

IN BI

BI BI

OUT

IN

RESET*/PIO0_0

PIO0_8/MISO0/CT16B0_MAT0

PIO0_6/USB_CONNECT*/SCK0 PIO0_7/CTS*

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 TDI/PIO0_11/AD0/CT32B0_MAT3 TMS/PIO0_12/AD1/CT32B1_CAP0 TDO/PIO0_13/AD2/CT32B1_MAT0

SWDIO/PIO0_15/AD4/CT32B1_MAT2

TRST*/PIO0_14/AD3/CT32B1_MAT1

PIO0_16/AD5/CT32B1_MAT3/WAKEUP PIO0_17/RTS*/CT32B0_CAP0/SCLK PIO0_18/RXD/CT32B0_MAT0

PIO0_20/CT16B1_CAP0

PIO0_19/TXD/CT32B0_MAT1

PIO0_21/CT16B1_MAT0/MOSI1

PIO0_23/AD7

PIO0_22/AD6/CT16B1_MAT1/MISO1

PIO1_13/DTR*/CT16B0_MAT0/TXD

PIO1_15/DCD*/CT16B0_MAT2/SCK1

PIO1_14/DSR*/CT16B0_MAT1/RXD

PIO1_16/RI*/CT16B0_CAP0

PIO1_19/DTR*/SSEL1

PIO1_20/DSR*/SCK1

PIO1_22/RI*/MOSI1

PIO1_21/DCD*/MISO1

PIO1_23/CT16B1_MAT1/SSEL1

PIO1_25/CT32B0_MAT1

PIO1_24/CT32B0_MAT0

PIO1_26/CT32B0_MAT2/RXD

PIO1_28/CT32B0_CAP0/SCLK PIO1_29/SCK0/CT32B0_CAP1

USB_DM

USB_DP

VDD

PIO1_5/CT32B1_CAP1

XTALOUT

XTALIN

PIO0_4/SCL

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_5/SDA

PIO0_3/USB_VBUS

PIO0_9/MOSI0/CT16B0_MAT1

PIO1_27/CT32B0_MAT3/TXD

PIO0_1_CLKOUT_CT32B0_MAT2_USB_FTOGGLE

VSS

IN

BI

IN

IN BI

IN

OUT

IN

OUT

IN

IN OUT OUT OUT

IN

OUT

P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7

INT*

ADDR

SCL SDA

RESET*

VCCI

VCCP

P1_1

P1_0

P1_3

P1_2

P1_4 P1_5 P1_6 P1_7

GND

NC

OUT

VER 3

D

SG

IN

OUT

VER 3

D

SG

OUT

VER 3

D

SG

OUT

IN

OUT

IN

VER 3

D

SG

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

indicates test-lio board.

Pull-down on PIO1_5

From MLB

Polarity swap is intentional, required to support low-speed USB on LPC11U37.

Pull-up in U4600

Allows HPM to monitor QR_SWITCH_EN

HPM SWITCH_EN Isolation

without creating leakage path.

outputs (connector unplug)

HPMBB:SSP0 - Use LPC SSP0 SPI controller (PoR)

G3H

SUS

AON AON

AON

AON AON

boots to counter internal 10-85uA pull-ups.

AON

Domain

AON AON

AON

AON AON

D+ V-Sense

D- V-Sense

Allows SAK to override HPM

S4

P1_7 in G3H domain for initial detection of G3H power.

All non-AON signals are open-drain to avoid leakage.

SUS

SSP/IOH Steering Resistors

4.7k pull-downs ensure signals are low when MCU

NOTE: Must be unstuffed before production!

For bring-up, allows default HPM SWD connection on RFU

Addr=0x40(Wr)/0x41(Rd)

Do not stuff if parasitic CC pull-down is active.

HPMBB:IOH - Use LPC I/O Handler for BB SPI (CYA)

PIO0_3 pull-down ensures MCU does not enter USB ISP mode when blank.

4.7K

MF

1/20W

2015%

R4646

12

NO STUFF

4.7K

MF

1/20W

2015%

R4644

12

201

4.7K

MF

1/20W

5%

R4643

12

5%

1/20W

4.7K

MF 201

R4642

12

1/20W

4.7K

MF 2015%

R4641

12

31 43 64

31

32

15 34 64

29 67

29 67 26

26

10% X5R-CERM

10V 0201

0.1UF

C4601

1

2

CKPLUS_WAIVE=NdifPr_badTerm

LPC11U37FET48-CP3316

OMIT_TABLE

TFBGA

CKPLUS_WAIVE=PdifPr_badTerm

CRITICAL

U4600

A6 A3 B3 B2

C2

F2 G4 E8 A5

F1 H2 G3 H3 H6 G7 F8 F7

B8 A8 A4 A2 B1 H1 G8 A7 H4 G6 A1 G2 G1 H7 D7

H8C1

E7

B6

D8

C8

C7

B7

G5

H5

B4

E2

B5

D2

D1 E1

29 64

28 29

34

29

28 29 34

26 28

28 29 64

4.7K

MF

1/20W

2015%

R4645

12

62

31 32

28 29

64

5%

201

1/20W

MF

10K

R4600

1

2

14 16 62 63

64

29

50

27 28 29

26 28

4.7K

MF

1/20W

2015%

R4647

12

4.7K

MF

1/20W

2015%

R4648

12

RFU_EN_PD

4.7K

MF

1/20W

2015%

R4649

12

NO STUFF

201

4.7K

MF

1/20W

5%

R4640

12

29

5%

201

1/20W

MF

1K

R4631

12

43 64

5% 201

1/20W

MF

100K

R4666

12

5% 201

1/20W

MF

100K

R4667

12

5% 201

1/20W

MF

100K

R4664

12

5% 201

1/20W

MF

100K

R4663

12

5% 201

1/20W

MF

100K

R4665

12

5% 201

1/20W

MF

100K

R4662

12

5% 201

1/20W

MF

100K

R4661

12

5% 201

1/20W

MF

100K

R4657

12

5% 201

1/20W

MF

100K

R4660

12

5% 201

1/20W

MF

100K

R4656

12

5% 201

1/20W

MF

100K

R4654

12

5% 201

1/20W

MF

100K

R4655

12

5% 201

1/20W

MF

100K

R4652

12

5% 201

1/20W

MF

100K

R4653

12

5% 201

1/20W

MF

100K

R4651

12

5% 201

1/20W

MF

100K

R4650

12

PCAL6416A

CRITICAL

VFBGA

U4650

B5

E2

A3 A1

C3 B1 C1 C2 D1 E1 D2

E3 E4 D3 E5 D4 D5 C5 C4

A2

A5 A4

B3

B4

X5R-CERM

10V

0201

0.1UF

10%

C4650

1

2

28 29 64

28

29

27 28 29 50 62 64

27 28

26 28

26 28 29

DMN5L06VK-7

SOT563

CRITICAL

Q4630

3

5

4

5%

0

0201

1/20W

MF

HPMVBUS:VDET

R4620

12

201

1/20W

MF

274K

1%

HPMVBUS:ADC

R4625

1

2

201

1/20W

MF

45.3K

1%

HPMVBUS:ADC

R4626

1

2

0.1UF

10% 10V X5R-CERM 0201

HPMVBUS:ADC

C4626

1

2

29

50

CRITICAL

DMN5L06VK-7

SOT563

Q4635

3

5

4

5%

201

1/20W MF

100K

R4670

1

2

50

1K

5%

201

1/20W

MF

R4630

12

DMN5L06VK-7

CRITICAL

SOT563

Q4630

6

2

1

28 29 64

28

29 64

5%

0

0201

1/20W

MF

HPMBB:SSP0

R4618

12

5%

0

0201

1/20W

MF

HPMBB:IOH

R4617

12

0201

5%01/20W

MF

HPMBB:SSP0

R4615

12

5%

0

0201

1/20W

MF

HPMBB:IOH

R4616

12

29 64

29

201

4.7K

MF

1/20W

5%

R4639

12

HPMBB:IOH

5%

0

0201

1/20W

MF

R4622

12

HPMBB:SSP0

5%

0

0201

1/20W

MF

R4621

12

1/20W

5%

0

0201

MF

HPMBB:IOH

R4623

12

5%

0

0201

1/20W

MF

HPMBB:SSP0

R4624

12

13 62 64

29

201

470K

MF

1/20W

5%

R4637

12

201

470K

MF

1/20W

5%

R4638

12

SOT563

CRITICAL

DMN5L06VK-7

Q4635

6

2

1

15 62 64

18

33 64

1.5K

NO_XNET_CONNECTION=TRUE

MF

1/20W

5%

201

R4610

1

2

0.1UF

X5R-CERM

10V 0201

10%

C4600

1

2

Host Port Micro

SYNC_DATE=04/30/2014

SYNC_MASTER=DEV_LIO

USB_HPM_N

E85_TEST_MODE_L

BBPD_CON_DET_L

HPM_PIO0_8

BBPD_IPU_EN

BBPD_VCONN_EN

E85LSMUX_RFU_EN_L HPM_SWCLK HPM_SWDIO

HPM_POWER_GATE_EN BBPD_PD_EN E85HSMUX_HS_EN E85LSMUX_DX_EN

BBPD_RPD_EN

HPM_PIO1_29

HPM_PIO0_3

PP3V3_G3H

BBPD_RX_L_TX_H

HPM_PIO1_29

PP3V3_S4

E85LSMUX_M_SEL0

E85LSMUX_HPM_SWD_EN

E85LSMUX_DEBUG_B_EN

E85HSMUX_USB_EN E85HSMUX_HS_FLIP

P5VOUT_EN_L EXPANDER_P1_7

HPM_PIO0_3

VBUSFET_VDET

BBPD_SPI_SCLK

BBPD_SPI_MISO

HPM_I2C_INT_L

HPM_PIO0_7

HPM_UART_RX

BBPD_DET2_B

BBPD_DET2_A

E85HSMUX_USB_EN E85HSMUX_HS_FLIP BBPD_PD_SEL_CC2

E85HSMUX_DP_EN_L

E85LSMUX_DEBUG_B_EN E85LSMUX_RFU_FLIP

E85LSMUX_M_EN E85LSMUX_DEBUG_A_EN

E85LSMUX_DX_FLIP E85LSMUX_DEBUG_FLIP_L E85LSMUX_HPM_SWD_EN E85LSMUX_SMC_SWD_EN

E85LSMUX_M_SEL0

I2C_HPM_SDA

I2C_HPM_SCL

PP3V3R3V0_AON

BBPD_SPI_MOSI

E85LSMUX_DX_EN

PPDCIN_G3H

TS_POWER_GATE_EN

HPM_POWER_GATE_EN

HPM_PIO1_29

E85LSMUX_DX_FLIP

E85LSMUX_RFU_FLIP

E85HSMUX_DP_EN_L

E85LSMUX_M_EN

E85LSMUX_DEBUG_FLIP_L

E85LSMUX_M_SEL1

HPM_UART_TX

XDP_USB_EXTA_OC_L

E85HSMUX_HS_EN

USB_HPM_P

GND

TS_HIPWR_EN

HPM_SWCLK

I2C_HPM_SDA

BBPD_PD_EN

BBPD_DET1_A BBPD_DET1_B

I2C_PCH_1_SDA

I2C_PCH_1_SCL

SMC_AID

HPM_SWDIO

P5VOUT_EN_L

TP_HPM_XTALOUT

PP3V3_G3H

P5VOUT_EN

E85LSMUX_RFU_EN_L

HPM_VBUS_VDET

E85LSMUX_DEBUG_A_EN

E85LSMUX_SMC_SWD_EN

BBPD_PD_SEL_CC2

E85LSMUX_M_SEL1

EXPANDER_P1_7

PP3V3_SUS

PP3V3R3V0_AON

BBPD_VCONN_EN

HPM_VBUSFET_EN

HPM_VBUSFET_OC_L

HPM_PIO0_3

HPM_RESET_L

VBUSFET_EN

HPM_VCFET_OC_L

I2C_HPM_SCL

HPM_SWITCH_EN_L

QR_SWITCH_EN

HPM_PIO0_8

HPM_PIO0_7

BBPD_IPU_EN

SMC_PME_S4_DARK_L

BBPD_RPD_EN DP_E85SNK_HPD

HPM_VBUSFET_EN

PP3V3R3V0_AON

<SCH_NUM>

46 OF 130

28 OF 75

29 62 64

28

29 64

28 29 64

26 28

28

28 29 64

27 28 29

26 28

28 29 64

28

17 28 30 31 32 33 34 37 42 43 60

28

22 23 29 30 32 33 50 51 60

26 28 29

26 28

27 28 29 50 62 64

28 29

28 50

28

28 29 34

26 28 29 34 41 43 60

29 35 43 60

28

26 28

27 28

26 28

28

50

17 28 30 31 32 33 34 37 42 43 60

26 28

28 29 64

28

8

11 14 15 18

27 29 46 51 60

26 28 29 34 41 43 60

28

26 28 29 34 41 43 60

WWW.AliSaler.Com

IN

OUT

D

SYM_VER_3

SG

IN

NC

08

BI

OUT

IN

IN IN

BI

OUT

BI

IN IN

IN

IN IN

IN

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

BI BI

OUT

BI

IN

BI BI BI

BI

OUT

G

S

D

OUT

IN

VBATVDDIO

VBUSOUT

GND

ID

D-

D+

VBUSIN

ENB

INTB VBUSDET

SDA SCL

DPH DNH

VCONN_EN

RD_EN

PD_EN

MOSI

DET1_A

DET2_A

CON_DET*

GND

VDD

IH_EN

SCLK

DET1_B

DET2_B

CC1

VCONN1_EN

CC2

VCONN2_EN

MISO

TX/RX*

PD_SEL_CC2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

USB VBUS & BC 1.2 Charger Detection

8.2V ZENER

Max Ids = 4.9A

E85 PCIe CLKREQ_L isolation

GND_VOID

24mA max output

TX level-shift and slew-rate control

35mohm max @ Vgs = -4.5V

516S1183

E85 B2B RECEPTACLE

E85 AC coupled signals

GND_VOID

0.1UF

0201X5R-CERM

10% 16V

TRUE

C4717

12

0201

16V10%

0.1UF

X5R-CERM

TRUE

C4715

12

X5R-CERM

16V10%

0.1UF

0201

TRUE

C4716

12

X5R-CERM

TRUE

10%

0.1UF

16V 0201

C4714

12

16V

X5R-CERM

0.1UF

10%

0201

C4721

12

16V 0201

10%

0.1UF

X5R-CERM

C4720

12

5

68

5

68

5

68

5

68

5

68

5

68

5

68

5

68

14 67

CRITICAL

4A-32V

0603

F4700

12

12 62

DMN32D2LFB4

DFN1006H4-3

Q4700

3

1

2

28

CRITICAL

74LVC1G08

SOT891

U4701

2

1

35

6

4

10% 10V

0201

X5R-CERM

0.1UF

C4701

1

2

1%

201

MF

1/20W

120

R4706

1

2

220

1%

201

1/20W

MF

CCSAK

R4705

1

2

0201

16V X7R-1

1000PF

10%

C4705

1

2

28

NO STUFF

100

1/20W

201

MF

1%

R4709

1

2

28

28 64

28

64

28 64

X5R-CERM

10% 10V

0201

0.1UF

C4700

1

2

60 64 68

50

64

50 64

26 64

27 28

27 28 50 62 64

15 62

62

12 62 64 68

62

30 31 32

14 67

16V 0201

0.1UF

10% X5R-CERM

C4722

12

16V 0201

10%

0.1UF

X5R-CERM

C4723

12

27 68

27

68

27 68

27 67

28

26 64

27 68

29 68

29 67

26 64 68

14 64 67

26 64 68

29 68

27 68

1/20W 0201

MF

0

TRUE

5%

C4712

12

1/20W 0201

0

5% MF

TRUE

C4713

12

0

1/20W 0201

MF

5%

TRUE

C4718

12

0201

1/20W

5% MF

0

TRUE

C4719

12

28 34

28

67

28 67

X5R-CERM

0201

0.1UF

10% 10V

C4780

1

2

26 29

26

66

26 66

13 66

NO_XNET_CONNECTION=TRUE

MF

1/20W 201

5%

100K

R4726

12

NO_XNET_CONNECTION=TRUE

100K

MF

5%

1/20W 201

R4725

12

28

MF

1%

201

1/20W

330K

R4755

1

2

1/20W

MF

201

1%

30K

R4756

1

2

X3DFN06032

GDZ8V2BLP3

CRITICAL

D4750

AK

CER-X5R 0201

16V

1UF

20%

C4755

1

2

SI8487DB

BGA

CRITICAL

Q4750

23

1

4

1/4W

MF

51.1

1%

0603

R4750

12

35V

10%

CRITICAL

0402

1.0UF

CERM-X5R

C4750

1

2

50V C0G

220PF

2%

0201

C4706

1

2

2%

220PF

C0G

50V 0201

C4707

1

2

0201X5R-CERM

10%

0.1UF

16V

C4710

12

0201

16V

0.1UF

10% X5R-CERM

C4711

12

18

5%

100K

1/20W

MF

201

R4727

1

2

26 28

PI3USB9281AGE

CSP

U4780

B5A2

A5A3

A1

A4

B4

C2

B3

B2

C1

C3

C5C4

B1

TRUE

AA21-S054VA1

F-ST-SM

CRITICAL

J4700

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354

5556

5758

6

78 9

STQFN

CCSAK

CRITICAL

SLG4AP645AV

U4700

10

1214

6 7 3 4

11

15

16 19

2

13

17

18

20

8

5

9

1

SYNC_DATE=04/17/2014

SYNC_MASTER=DEV_MLB

E85 FLEX CONNECTOR

PPDCIN_E85_SS

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=20V

PPVBUS_E85

USB3_EXTA_R2D_N

DP_E85SNK_ML_P<3> DP_E85SNK_ML_N<3>

E85_HS_DP_ML0_P

E85_TEST_MODE_L

=PCIE_E85_R2D_P

PCIE_CLK100M_TBT_N

PP1V05_S4SW

E85_HS_DP_ML0_N

E85_RFU<1>

E85_HS_DP_ML1_N E85_HS_DP_ML1_P

DP_E85SNK_ML_N<2> DP_E85SNK_ML_P<2>

E85_LS_P<2> E85_LS_N<2>

DP_E85SNK_AUXCH_P

PP5V1_S4SW_CC2 PCH_TBT_PCIE_RESET_L

E85_RFU<2>

=PCIE_E85_R2D_N

PCIE_CLK100M_TBT_P

=PCIE_E85_D2R_N

E85HSMUX_HS_FLIP

USB3_EXTA_R2D_P

E85_LS_N<1>

E85_LS_P<1>

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

SMC_ONOFF_L

PP5V1_S4SW_CC1

E85HSMUX_USB_EN

E85_TEST_MODE_HPD

=PCIE_E85_D2R_P

E85HSMUX_HS_EN

PP3V3_SUS

PDCIN_E85_SS_DIV

DP_E85SNK_ML_P<0>

DP_E85SNK_ML_N<2>

DP_E85SNK_ML_P<3>

USB_BC1P2_P

MAKE_BASE=TRUE

PPVBUS_E85

E85LSMUX_M_SEL0

TP_BC1P2_INTB VBUSFET_VDET

I2C_HPM_SDA I2C_HPM_SCL

USB_HPM_P USB_HPM_N

DP_E85SNK_AUXCH_N

USB3_EXTA_R2D_C_P

PP3V3_S4

DP_E85SNK_ML_P<2>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

PPDCIN_G3H

USB_BC1P2_N

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_N<2>

BBPD_SPI_MISO_BUF

USB3_EXTD_R2D_C_P

TBT_CLKREQ_L

PP3V3_S0

DP_E85SNK_ML_P<1>

BBPD_SPI_MISO

DP_TBTSNK0_ML_C_N<3>

USB_BC1P2_P

DP_E85SNK_ML_N<1>

USB3_EXTA_R2D_P

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_P<3>

USB3_EXTA_R2D_C_N

DP_E85SNK_ML_N<3>

DP_TBTSNK0_AUXCH_C_P

USB3_EXTD_R2D_C_N

DP_TBTSNK0_AUXCH_C_N

USB_BC1P2_N

MAKE_BASE=TRUE

TP_BC1P2_ID

PP3V3R3V0_AON

DP_E85SNK_ML_N<0>

BBPD_PD_SEL_CC2

BBPD_RX_L_TX_H BBPD_MISO_LS1V1

BBPD_VCONN2_EN

E85_CC2

BBPD_VCONN1_EN

E85_CC1

BBPD_DET2_B

BBPD_DET1_B

BBPD_SPI_SCLK

BBPD_IPU_EN

PP3V3R3V0_AON

BBPD_CON_DET_L

BBPD_DET2_A

BBPD_DET1_A

BBPD_SPI_MOSI

BBPD_PD_EN

BBPD_RPD_EN BBPD_VCONN_EN

USB3_EXTD_R2D_N

USB3_EXTD_R2D_P

USB3_EXTA_R2D_N

TP_BC1P2_VBUSOUT

<SCH_NUM>

47 OF 130

29 OF 75

29 50 60

28

62 64

50 60

8

11 14 15

18 27 28 29 46 51

60

8

11 14 15

18

27 28 29

46 51 60

29 68

26 29

29 50 60

22 23 28 30 32 33 50 51 60

29 68

28 35 43 60

8

11 12 13 15

17 18 23 24 32 33

34 35 36 40 46 47 53 60 73 75

29 67

29 68

26 29

26 28 29 34 41 43 60

64

26 28 29 34 41 43 60

29 67

WWW.AliSaler.Com

IN

OUT

IN

OUT

BI

IN

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

IPD ZIF CONNECTOR

Pinout reversed from flex

Bottom side contacts used

518S0854

SM

XW4801

12

BYPASS=J4801::1.5MM

5%

100PF

0201

C0G

25V

C4810

1

2

5%

100PF

0201

C0G

25V

BYPASS=J4801::1.5MM

C4811

1

2

5%

100PF

0201

C0G

25V

BYPASS=J4801::1.5MM

C4812

1

2

20%

402

10V

CERM

0.1uF

C4802

1

2

CRITICAL

FERR-120-OHM-1.5A

0402-LF

L4802

12

CRITICAL

FERR-120-OHM-1.5A

0402-LF

L4801

12

10V

0.1uF

402

20%

CERM

C4801

1

2

CRITICAL

FERR-120-OHM-1.5A

0402-LF

L4804

12

20% 402

0.1uF

10V

CERM

C4804

1

2

FERR-120-OHM-1.5A

0402-LF

CRITICAL

L4803

12

20%

402

0.1uF

10V

CERM

C4803

1

2

CRITICAL

0603

30-OHM-5A

L4800

12

20% 10V

0.1uF

402

CERM

C4800

1

2

15 64

22 31

33

15 67

MF

1/20W

201

15

1%

R4802

12

1%

201

15

MF

1/20W

R4801

21

CRITICAL

502250-8041

F-RT-SM

J4801

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

5

6

7

8

9

3A-6A-9V-0.05OHM

0603

CRITICAL

F4800

12

15 64

31 34

40 72

31 34 40 72

30 43

201

5% 1/20W MF

100K

R4870

1

2

29 30 31 32

30

31 32

15

1/20W

MF

1%

201

R4803

12

15 67

30 31

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=03/26/2014

Keyboard & Trackpad Conn

SMBUS_SMC_3_SDA

SMC_PME_S4_WAKE_L

TP_USB_TPADN

PP3V3_S4_TPAD_F

PP5V_S0_KBD_F

PP3V3_G3H_KBD_F

PP5V_S0_KBD_F

TPAD_SPI_CLK

SMC_LSOC_RST SMC_ONOFF_L SMC_LID

PP3V3_S4

PP5V_S4

PP5V_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S4_TPAD_F

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S0_KBD_F

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

PP3V3_S4_TPAD_F

PP3V3_G3H

VOLTAGE=3.3V

PP3V3_G3H_KBD_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

TPAD_SPI_MISO

PPBUS_G3H_TPAD_FLT

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.1MM VOLTAGE=8.7V

TPAD_SPI_MOSI

TPAD_SPI_MISO_R TPAD_SPI_MOSI_R TPAD_SPI_CLK_R TPAD_SPI_INT_L PP3V3_S4_TPAD_F TP_USB_TPADP PP5V_S4_TPAD_F SMBUS_SMC_3_SCL

SMC_LSOC_RST SMC_ONOFF_L

GND_ACTUATOR

MIN_NECK_WIDTH=0.1MM VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

TP_USB_VBUS_EN

SMC_LID

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.1MM

PPBUS_G3H_TPAD_FUSED

VOLTAGE=8.7V

TPAD_SPI_IF_EN

TPAD_SPI_CS_L

SMC_ACTUATOR_DISABLE_L

MAKE_BASE=TRUE

SMC_ACTUATOR_DISABLE_L

<SCH_NUM>

30 OF 75

48 OF 130

30

30 43

29 30

31 32

30 31 32

22 23 28 29 32 33 50 51 60

38 47 53 60 75

16 17 25 39 40 44 45 47 49 51 60

30

35 43 46 47 48 49 50 60

30

17 28 31 32 33 34 37 42 43 60 30

30

www.qdzbwx.com

WWW.AliSaler.Com

IN

BI BI BI BI

IN IN

IN BI OUT

IN OUT

BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT OUT OUT OUT

OUT

IN

OUT

OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

BI OUT

OUT

IN OUT

OUT

IN

OUT

IN

IN BI

OUT

OUT OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

IN

BI

IN

IN IN

OUT

IN

PN6

PL2

PE3

PE0 PD7

PC6 PC4 PC5 PJ5 PJ4

PB0 PB1

PC7

PN1

PE6

PE7

PK3

PB6 PB7

PD1

PD3

PB5

PG6

PM3

PJ3

PJ2

PJ1

PJ0

PH7

PH6

PH5

PH4

PH1

PH0

PG5

PG4

PF5

PF4

PF3

PF2

PF1

PF0

PA5/SSI0TX

PA4/SSI0RX

PA3/SSI0FSS

PK2

PK1

PK0

PD0

PD2

PB4

PE4

PE5

PD4

PD5

PD6

PE1

PE2

PL6

PL7

PA1/U0TX

PA0/U0RX

PQ7

PQ6

PQ5

PQ4

PQ3

PQ2

PQ1

PQ0

PP7

PP6

PP5

PP4

PP3

PP2

PP1

PP0

PG7

PG3

PG2

PG1

PF7

PF6

PA7

PA6

PB3/I2C0SDA

PB2/I2C0SCL

PM4

PL5

PL4

PM5

PL0

PL1

PK5

PN0

PN3

PK6

PM6 PM7

PK7 PN2

PH3

PN5

PN4

PJ6

PN7 PH2

PJ7

PA2/SSI0CLK

PG0

PM1

PM0

PM2

PL3

SYM 1 OF 2

PC2/TDI

PC3/SWO/TDO

PC1/SWDIO/TMS

PC0/SWCLK/TCK

VDDS

VREFA+

NC

PK4

HIB*

WAKE*

RST*

VDDC

VBAT

OSC1

OSC0

XOSC0 XOSC1

VDDC

VDDA

GND

GND GND

GND

GND GND

GND

GND GND GND GND

GNDA

VREFA-

SYM 2 OF 2

IN

NC

IN

OUT

IN OUT

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

If SMS interrupt is not used, pull up to SMC rail.

SMS Interrupt can be active high or low, rename net accordingly.

(OD)

Unused pins have "SMC_Pxx" names. Unused

(OD)

NOTE:

pins designed as outputs can be left floating, those designated as inputs require pull-ups.

(OD)

NOTE:

(OD)

(OD) (OD) (OD) (OD)

(OD)

PLACE_NEAR=U5000.A1:4MM

SM

XW5000

12

32 64

1M

5% 1/20W

201

MF

R5002

1

2

10%

0201

0.1UF

10V X5R-CERM

C5006

1

2

X5R-CERM 0201

0.1UF

10V

10%

C5005

1

2

0201

10V

0.1UF

10% X5R-CERM

C5009

1

2

0201

0.1UF

10V X5R-CERM

10%

C5008

1

2

0.1UF

X5R-CERM

10V

10%

0201

C5004

1

2

X5R-CERM 0201

10V

10%

0.1UF

C5003

1

2

X5R-CERM 0201

10% 10V

0.1UF

C5007

1

2

14 68

14

68

14 68

17 68

14 68

18

15

13

34 53 72

14 34 36 53 68 72

34 46 48 72

30 34 40 72

63

34 41 43 72

33 35

33

33 35

33

33 35

33

33 46

33

33 44

46

33

32

32 64

26 32 64 67

63

37 68

28 43 64

64

16 33 46

32

13 16

13 17

13 32

15 64

32

63

33

63

64

33

22 30 33

32 46

32 35 43 62

13 33 46 75

13 46 52

13 15 46 52

13 51 52

29 30 32

28 32

13

17

13 62

43 64

13 62

46 48 52

17

30-OHM-1.7A

0402

L5001

12

6

32 44 66

23

54

54 64

63 64

13 16 46

6

64 66

22 64

33 35

64

10V 0201

X5R-CERM

0.1UF

10%

PLACE_NEAR=U5000.K13:5MM

C5016

1

2

PLACE_NEAR=U5000.K13:5MM

10V

10%

0.1UF

0201

X5R-CERM

C5015

1

2

PLACE_NEAR=U5000.J1:5MM

10%

0.1UF

0201

10V X5R-CERM

C5013

1

2

0201-1

X5R

6.3V

20%

1.0UF

PLACE_NEAR=U5000.D6:5MM

C5010

1

2

10% 10V

0201

0.1UF

X5R-CERM

C5001

1

2

6.3V

1UF

20% X5R

0201

C5002

1

2

32

30

BYPASS=U5000.D2:D1:1MM

6.3V X5R 0201

1UF

20%

C5021

1

2

10V X5R-CERM 0201

0.01UF

10%

BYPASS=U5000.D2:D1:1MM

C5020

1

2

63

PLACE_NEAR=U5000.J1:5MM

0.1UF

10%

0201

10V X5R-CERM

C5011

1

2

X5R-CERM

10V 0201

0.1UF

10%

PLACE_NEAR=U5000.J6:5MM

C5012

1

2

PLACE_NEAR=U5000.J6:5MM

0201-1

X5R

6.3V

20%

1.0UF

C5014

1

2

0201-1

X5R

6.3V

1.0UF

20%

PLACE_NEAR=U5000.D6:5MM

C5017

1

2

32 33

32

15 32 66

64

17

64

BGA

OMIT_TABLE

TM4EA231H6ZXRI

U5000

L3 K5

N2 N3 L4 M4

N4 L5

E11 D11

D13 D12

A4 B4

E3 E4

M3 M2

N1

M1

B1

C1

D3

D4

A2

A1

C3

C2

G1

G2

G3

G4

B3

A3

C5

C4

L10 N11 N12 M11 K10 M10

N10

K8 N9 M9 L9 L8

M8 N8

N5 M5

L2 L1

K3 K2

K1 J3 J2 J4

D8 A8 B8 C8

A6

B6

C7

C6

H4 H3 H1 H2

B11

A12 B12

A13

C11

B13

D10

C12 C13

E12

E13

F10 G12

G11

G13

G10

H10

H13 H11

A5

B5

K4 A9

L12 M12 N13 L11

J10 H12

K6 J11 J12

K7

A7

L6

D2

D1

F1

M6

N6

L7

M7

N7

OMIT_TABLE

BGA

TM4EA231H6ZXRI

U5000

A10 D5

G5 G9 H5 H8 J5 J6 J7 J8 K9

D6 D9 E5 E8 E9 E10 F5 F9

F2 F4

L13

B7

F13 F12

B9 C9

B10

C10A11

F11

K13

E6 E7 F6 F7 F8 G6 G7 G8 H6 H7

F3

D7 H9 J1 J9

J13

E2

E1

M13

K11 K12

37 43 59

30

32

22 64

64

32

43 64

SYNC_DATE=10/11/2013

SYNC_MASTER=J92_DEVMLB

SMC

SMC_ACTUATOR_DISABLE_L

CPU_PECI_R

SMC_DSW_PWRGD

SMC_CPU_ISENSE

NC_SMC_LCDBKLT_ISENSE

NC_SMC_P3V3S5_ISENSE

NC_SMC_P1V05SUS_ISENSE

SMC_P1V2S3_ISENSE

NC_SMC_P1V1_S0_ISENSE

NC_SMC_PANEL_ISENSE

SMC_ACC_VSENSE

LPC_FRAME_L SMC_LRESET_L LPC_SERIRQ

SMC_WAKE_SCI_L

SMC_BT_PWR_EN

MIN_LINE_WIDTH=0.25MM

PP1V2_S5_SMC_VDDC

MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V

PMIC_PWRBTN_L

LPC_AD<3>

CPU_PROCHOT_L

SMC_DELAYED_PWRGD

SMC_PCH_SUSWARN_L

SMC_PROCHOT

SMC_DEBUGPRT_TX_L

SPI_SMC_MISO

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

SMC_PMIC_INT_L

SMC_ONOFF_L

NC_SMC_OSC1

NO_TEST=TRUE

NC_SMC_HIB_L

NO_TEST=TRUE

PP3V3_S5_SMC_VDDA

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM

SMC_PME_S4_WAKE_L

SMC_SENSOR_ALERT_L SMC_CBC_ON SMC_LID

PM_PWRBTN_L

NC_SMC_FAN_4_CTL

SMC_CHGR_INT_L

SMC_PECI_L

SMC_PCH_SUSACK_L

SMBUS_SMC_3_SDA NC_SMBUS_SMC_4_ASF_SCL

PM_THRMTRIP_L

TS_HIPWR_EN

SMC_CLK12M_EN

NC_SMC_SYS_LED

NC_SMC_ACCPWR_ISENSE

SMC_VCCIO_CPU_DIV2

SMC_DCIN_VSENSE

SMC_DCIN_ISENSE

NC_SMC_P1V05S0_VSENSE

SMC_PBUS_VSENSE

SMC_WIFI_PWR_EN

SMC_BMON_ISENSE

SMC_HS_COMPUTING_ISENSE NC_SMC_ACC_PWR_VSENSE

NC_SMC_P3V3S0_ISENSE

SMC_CPU_VSENSE

SMC_RESET_L

SMC_CLK32K_PMIC

SMC_TCK SMC_TMS

SMC_TDI

SMC_TDO

NC_SMC_XOSC1

NO_TEST=TRUE

SYSCLK_CLK12M_SMC

SMBUS_SMC_5_G3_SDA

PP3V0_S5_AVREF_SMC

GND_SMC_AVSS

NC_SMC_CAMERA_ISENSE

NC_SMC_WLAN_ISENSE

NC_SMC_1V8PWR_ISENSE

PM_CLKRUN_L LPC_PWRDWN_L SMC_RUNTIME_SCI_L

LPC_CLK24M_SMC

SMC_THRMTRIP

ALL_SYS_PWRGD

SPI_SMC_CLK

NC_SMC_FAN_0_CTL

PM_PCH_SYS_PWROK

S5_PWRGD

NC_SMC_PPBUS_TPAD_ISENSE

NC_SMC_GFX_THROTTLE_L

PM_SYSRST_L

NC_SMC_GFX_OVERTEMP

CPU_CATERR_L

SMC_RX_L

TP_SMC_PWRFAIL_WARN_L

SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL

SMBUS_SMC_0_S0_SCL

LPC_AD<2>

SPI_SMC_CS_L

NC_SMC_FAN_0_TACH

SPI_DESCRIPTOR_OVERRIDE_L

SPI_SMC_MOSI

SMC_DEBUGPRT_RX_L

SMC_SENSOR_PWR_EN

SMC_TX_L

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_2_G3_SDA

SMBUS_SMC_2_G3_SCL

LPC_AD<1>

LPC_AD<0>

NC_SMBUS_SMC_4_ASF_SDA

SMC_DP_HPD_L

SMC_PME_S4_DARK_L SMC_AID

SMBUS_SMC_3_SCL

NC_SYS_ONEWIRE

NC_SMC_FAN_1_CTL NC_SMC_FAN_1_TACH

SMC_WAKE_L

SMC_WIFI_EVENT_L

PP3V3_G3H

SMC_TOPBLK_SWP_L

NC_SMC_SYS_KBDLED

PM_BATLOW_L

MEM_EVENT_L SMC_ADAPTER_EN

SMC_OOB1_D2R_L SMC_OOB1_R2D_L

SMC_PM_RSMRST_L

SMC_PMIC_RSMRST_L

NC_SMC_OTHER_HI_ISENSE

NC_SMC_BMON_DISCRETE_ISENSE

SMBUS_SMC_1_S0_SDA

PM_SLP_S0_L

SMC_BC_ACOK

<SCH_NUM>

50 OF 130

31 OF 75

26 32 37 62

26 32

37 62

32

33

35

22 32

17 28 30 32 33 34 37 42 43 60

WWW.AliSaler.Com

IN

OUT

BI

IN

OUT

IN

BI

OUT

SYM_VER_2

GS

D

IN

OUT

IN

OUT

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Debug Power "Buttons"

To SMC

SMC12 PECI Support

From SMC

From/To CPU/PCH

5% 201

1/20W

MF

10K

R5170

12

100K

5% 201

1/20W

MF

R5171

12

2015%

1/20W

MF

10K

R5173

12

100K

1/20W

2015% MF

R5174

12

10K

201

1/20W

5% MF

R5177

12

201MF

1/20W

10K

5%

R5178

12

5% MF 201

10K

1/20W

R5179

12

201

10K

1/20W

MF5%

R5180

12

100K

2015% MF

1/20W

R5185

12

31 32

15 31 66

0603-ZERO-HGT

LF

PLACE_SIDE=TOP

SILK_PART=PWR_BTN

0

5% 1/10W

OMIT

R5115

1

2

6

31 44 66

31 64

100K

201

1/20W

5% MF

R5187

12

0603-ZERO-HGT

SILK_PART=PWR_BTN

LF

PLACE_SIDE=BOTTOM

OMIT

0

5%

1/10W

R5116

1

2

13 68

PLACE_NEAR=U0500.B27:5.1mm

201MF

1/20W

22

5%

R5112

12

31 64

5%

1/20W

20K

MF 201

R5175

12

5%

1/20W

20K

MF 201

R5176

12

1/20W

201MF5%

10K

R5186

12

1%

201

MF

1/20W

100K

R5197

1

2

100K

201

1% 1/20W MF

R5196

1

2

29 30 31

32

31

201

5% MF

1/20W

1.6K

NOSTUFF

R5153

1

2

0201

1/20W

0

MF

5%

R5152

12

201

330

MF

1/20W

5%

R5151

1

2

5% 201

10K

MF

1/20W

NO STUFF

R5114

12

100K

5% MF 201

1/20W

R5167

12

6 66

31

5%

201

1/20W

MF

43

R5134

12

1/20W

5%

100K

MF 201

R5191

12

CRITICAL

DFN1006H4-3

DMN32D2LFB4

Q5150

3

1

2

1/20W

5% 201

10K

MF

R5172

12

28 31 32

NOSTUFF

25V C0G 0201

47PF

5%

PLACE_NEAR=Q5150.2:5MM

C5134

1

2

47PF

25V

5%

PLACE_NEAR=Q5159.6:5MM

C0G

0201

C5131

1

2

100K

201

1/20W

5% MF

R5168

12

5% 201

100K

MF

1/20W

R5169

12

1/20W

5% MF

2.2K

201

R5192

12

RSMRST:DIRECT

5%

0

0201

1/20W

MF

R5130

12

RSMRST:SMC

0201

MF

1/20W

5%

0

R5131

1

2

RSMRST:SMC

0201

MF

1/20W

5%

0

R5132

1

2

46

31 31

13

DMN5L06VK-7

SOT563

Q5159

3

5

4

SOT563

DMN5L06VK-7

Q5159

6

2

1

SYNC_MASTER=J92_DEVMLB

SMC Shared Support

SYNC_DATE=10/11/2013

PM_RSMRST_L

SMC_PM_RSMRST_L

SMC_PMIC_RSMRST_L

PMIC_RSMRST_L

SMC_TX_L

SMC_ONOFF_L

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

SMC_AID

SMC_PECI_L

CPU_PECI_R

PP1V05_S0

SMC_PECI_L_R

SMC_CLK32K_PMIC

CPU_PECI

PM_CLK32K_SUSCLK_R

SMC_VCCIO_CPU_DIV2

SMC_ADAPTER_EN

SMC_TDO SMC_TDI

SMC_RX_L SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L

SMC_WIFI_EVENT_L SMC_PMIC_INT_L

SMC_LID

SMC_ONOFF_L

SMC_PME_S4_DARK_L

PP3V3_S0

PP3V3_S4

SMC_PME_S4_DARK_L

SMC_THRMTRIP

SMC_TMS

SMC_TCK

SMC_SENSOR_ALERT_L

MEM_EVENT_L

SMC_BC_ACOK

PM_THRMTRIP_L

SMC_THRMTRIP

SMC_PROCHOT

CPU_PROCHOT_L

PP1V05_S0

SMC_DELAYED_PWRGD

MAKE_BASE=TRUE

SMC_BC_ACOKSMC_BC_ACOK

PP3V3_G3H

<SCH_NUM>

51 OF 130

32 OF 75

31

28 31 32

28

31

6 8

11 15 16

17 32

44 46 51

60

31

13 31

31

26 31 64 67

22 31

31 46

30 31

29 30 31 32

28 31 32

8

11 12 13

15 17 18 23 24 29

33 34 35 36 40 46 47 53 60 73

75

22 23 28 29 30 33 50 51 60

31 32

26 31 37 62

31 33

31

31 32 35 43 62

6 8

11 15 16

17 32 44 46 51

60

31

31 32 35 43 62 31 32 35 43 62

17 28 30 31 33 34 37 42 43 60

WWW.AliSaler.Com

IN

OUT

IN

OUT

GND

OUT

NC4

NC0

NC3

IN

NC2

NC1

NC NC NC NC NC

Y

NC NC

VCC

GND

A

NCNC

OUT

IN

A

VCC

GND

Y

C

B

OUT

SYM_VER_2

GS

D

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

0 0 1 1.05V 0 1 1 1.05V 1 0 0 0.95V 1 1 1 1.05V

Truth table

Top-Block Swap

SMC AVREF Supply

ASPGD S0_L ULQ_L P1V05_SUS

22 30 31 33

22

30 31

33

5%

201

1/20W MF

100K

R5282

1

2

22 30 31 33

5%

201

1/20W

MF

1K

R5283

12

15 31

5%

201

1/20W

MF

1K

R5296

1

2

X5R

1.0UF

20%

6.3V

0201-1

C5265

1

2

6.3V

CERM-X5R

20%

10UF

0402-1

C5266

1

2

10V X5R-CERM

10% 0201

0.1UF

C5267

1

2

36

14 18

5%

201

1/20W

MF

NOSTUFF

100

R5211

12

5%

201

1/20W

MF

100

R5214

12

5%

201

1/20W

MF

100

R5213

12

NOSTUFF

5%

201

1/20W

MF

100

R5215

12

31 32

QFN

REF3330

CRITICAL

U5265

4

5

1

2

3 6 7

8

74LVC1G07GF

SOT891

CRITICAL

U5280

2

3

1

5

6

4

10% X5R-CERM

10V 0201

0.1UF

C5280

1

2

13 46 31

5%

201

1/20W MF

100K

R5280

1

2

13 31 46

75

16 31 46

5%

0

0201

1/20W

MF

NOSTUFF

R5250

12

CRITICAL

74LVC1G57

SOT891

U5250

3

1

6

2

5

4

0.1UF

10% 0201

10V X5R-CERM

C5250

1

2

48

DMN32D2LFB4

DFN1006H4-3

CRITICAL

Q5220

3

1

2

18 28 64

31

5%

201

1/20W MF

100K

R5220

1

2

SMC Project Support

SYNC_MASTER=J43_MLB

SYNC_DATE=10/24/2012

DP_E85SNK_HPD

SMC_DP_HPD_L

PP3V3_S4

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

SMC_P1V2S3_ISENSE

SMC_DSW_PWRGD

PCH_SML1ALERT_L

PM_DSW_PWRGD

PP3V3_S5

SMC_SENSOR_PWR_EN

SMC_CPU_ISENSE

MIN_NECK_WIDTH=0.2 MM

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 MM VOLTAGE=0V

NC_SMC_P3V3S5_ISENSE

NC_SMC_BMON_DISCRETE_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_BMON_DISCRETE_ISENSE

PP3V3_G3H

NC_SMC_P1V05SUS_ISENSE

VOLTAGE=3.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V0_S5_AVREF_SMC

NC_SMC_ACCPWR_ISENSE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

CPUTHMSNS_ALERT_L

NC_SMC_PANEL_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_OTHER_HI_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_P1V05SUS_ISENSE

MAKE_BASE=TRUE

SMC_P1V2S3_ISENSE

NC_SMC_CAMERA_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_P3V3S0_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_WLAN_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_PPBUS_TPAD_ISENSE

NC_SMC_1V8PWR_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ACCPWR_ISENSE

MAKE_BASE=TRUE

SMC_ACC_VSENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_HS_COMPUTING_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ACC_PWR_VSENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_P1V1_S0_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_CPU_VSENSE

SMC_SENSOR_PWR_EN

MAKE_BASE=TRUE

NC_SMC_P1V05S0_VSENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_P3V3S5_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

SMC_SENSOR_ALERT_LCPUBMONSNS_ALERT_L

NAND_OVERTMP_ALERT_L

NC_SMC_PANEL_ISENSE NC_SMC_P1V1_S0_ISENSE

SMC_CPU_ISENSE

SMC_BMON_ISENSE

SMC_HS_COMPUTING_ISENSE NC_SMC_ACC_PWR_VSENSE

NC_SMC_LCDBKLT_ISENSE

NC_SMC_OTHER_HI_ISENSE

SMC_P1V2S3_ISENSE

PP3V3_S0

SMC_TOPBLK_SWP_L

SMC_DCIN_VSENSE

SMC_ACC_VSENSE

PCH_STRP_TOPBLK_SWP_L

NC_SMC_CAMERA_ISENSE NC_SMC_P3V3S0_ISENSE NC_SMC_1V8PWR_ISENSE

SMC_PME_S4_WAKE_L SMC_PME_S4_WAKE_L

SMC_DCIN_ISENSE

NC_SMC_PPBUS_TPAD_ISENSE

NC_SMC_WLAN_ISENSE

SMC_CPU_VSENSE

NC_SMC_P1V05S0_VSENSE

ALL_SYS_PWRGD

PM_SLP_S0_L

P1V05_ULQ_L

PP3V3_S5

<SCH_NUM>

52 OF 130

33 OF 75

22 23 28 29

30 32 33 50 51 60

22 23 28 29 30 32 33 50 51 60

31 33 46

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

31 33 35 64

31 33 44

31 35

31 33

17 28 30 31 32 34 37 42 43 60

31 33

31

31 33

31 33 35

31 33

31

33 46

31 33

31 33 35

31 33

31 33 35

31 33 35 64

31 33

31 33 44

31 33

31 33 44

31 33 35

31 33

31 33 46

8

11 12 13 15

17 18 23 24 29 32

34 35 36 40 46 47 53 60 73 75

31 33 35

31 33

31 33 35

31 33

31 33 35

31 33

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

WWW.AliSaler.Com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Wildcat Point LP S0 I2C "1" Connections

J1800

(MASTER)

SMC

(Write: 0x98 Read: 0x99)

EMC1704-02: U5800

CPU Temp, Inlet, DDR, BMON THR

SMC "0" SMBus S0 Connections

(See Table)

U0500

(MASTER) (Write: 0x12 Read: 0x13)(MASTER)

U5000

(MASTER)

Battery

(MASTER)

U5000

SMC

J8300

SMC

(MASTER)

(Write: 0x88 Read: 0x89)

access PCH

SMLink 1 is slave port to

Samsung LGD Samsung LGD AUO

U5000

SMC

(MASTER)

Battery

J6950

Battery Charger

BANSURI - U7100

Trackpad

J4800

(See Table)

PMICs

(Write: 0x?? Read: 0x??)

RIO

J6799

U7400/U7600

Internal DP

SMC "2" SMBus S3 Connections

J43 J41

(* = Multiple options)

(MASTER)

U5000

(Write: 0x92 Read: 0x93)

J4002

ALS

HPA0033AI: U5880

NAND Temp Sense

(Write: 0x72 Read 0x73)

Wildcat Point LP S0 "SMLink 0" Connections

Wildcat Point LP S0 "SMLink 1" Connections

Internal DP

gated by EDP_PANEL_PWR

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

(Write: 0x90 Read: 0x91)

SMC "5" SMBus G3H Connections

S0 Pull-ups on PCH page 16

(MASTER)

U0500

Wildcat Point LP

Battery Manager - (Write: 0x16 Read: 0x17)

connector page and

Pullups are on eDP

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y * Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

HPM

U4600

(Write: 0x?? Read: 0X??)

(MASTER)

HPM

LPC11U37 - U4600

HPM Master Bus

(Write: 0x40 Read: 0x41)

I/O Expander

PCAL6516A - U5350

SMC "3" SMBus S0 Connections

XDP Connectors

U5000

SMC S0 "1" SMBus Connections

BC1.2 Detector

PI3USB9281 - U5680

(Write: 0x4A Read: 0x4B)

Wildcat Point LP S0 SMBus "0" Connections

4.7K

5% MF

1/20W 201

R5361

1

2

MF

201

5%

1/20W

4.7K

R5360

1

2

2.0K

1/20W

MF

201

5%

R5380

1

2

201

2.0K

5% 1/20W MF

R5381

1

2

201

MF

1/20W

5%

8.2K

R5310

1

2

201

MF

8.2K

1/20W

5%

R5311

1

2

1K

MF 201

1/20W

5%

R5301

1

2

1K

201

1/20W

MF

5%

R5300

1

2

2.0K

201

MF

5% 1/20W

R5391

1

2

5% MF

201

1/20W

2.0K

R5390

1

2

201

2.2K

5%

1/20W

MF

R5370

1

2

201

2.2K

MF

5% 1/20W

R5371

1

2

5%

201

1/20W

MF

2.0K

R5340

1

2

5%

201

1/20W MF

2.0K

R5341

1

2

SYNC_DATE=10/24/2012

SMBus Connections

SYNC_MASTER=J43_MLB

PP3V3_S0

I2C_HPM_SDA

MAKE_BASE=TRUE

I2C_HPM_SCL

MAKE_BASE=TRUE

I2C_HPM_SDA

I2C_HPM_SCL

SML_PCH_0_CLK

MAKE_BASE=TRUE

SML_PCH_0_DATA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_2_G3_SDA

MAKE_BASE=TRUE

SMBUS_PCH_DATA

PP3V3_S0

I2C_HPM_SCL

I2C_HPM_SDA

PP3V3R3V0_AON

SMBUS_PCH_CLK

I2C_PCH_1_SCL

MAKE_BASE=TRUE

I2C_PCH_1_SCL

MAKE_BASE=TRUE

I2C_PCH_1_SDA I2C_PCH_1_SDA

MAKE_BASE=TRUE

SMBUS_SMC_2_G3_SCL

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_PCH_CLK

SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_G3H

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

SMBUS_SMC_2_G3_SCL

SMBUS_SMC_3_SDA

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

PP3V3_S0

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_2_G3_SDA

34 OF 75

53 OF 130

<SCH_NUM>

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

28 29 34

14 68

14 31 34 36 53 68 72

31 34 46 48 72

14 16 34 68

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

28 29 34

26 28 29 41 43 60

14 16 34 68

15 28 34 64 15 28 34

64

15 28 34 64 15 28 34

64

31 34 46 48

72

14 31 34 36 53 68 72

14 16 34 68

30 31 34 40 72

31 34 41 43 72

31 34 53 72

14 31 34 36 53 68

72

14 31 34 36 53 68

72

14 31 34 36 53 68 72

17 28 30 31 32 33 34 37 42 43 60

30 31 34 40 72

31 34 46 48 72

30 31 34 40 72

31 34 41 43 72

31 34 53 72

31 34 41 43 72

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

31 34 53 72

14 31 34 36 53 68 72

31 34 46 48 72

WWW.AliSaler.Com

OUT

IN-

IN+ REF

V+

GND

OUT

IN

OUT

IN

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

V+

REFIN+

IN-

OUT

GND

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ACC Voltage Sense

present on IN+/- pins with INA output voltage decreasing

Max VOut: 3V at 21V Input

VCFR CPU Vcore Voltage Sense / Filter

Need to set gains for ULX

VD0R: DC-In Voltage Sense Enable & Filter

CHARGER BMON High Side Current Sense

RTHEVENIN = 19530 Ohms

Sense R is R7120, 20mOhm

ISL6259 Gain: 20x

DC-IN (AMON) Current Sense

EMC1704 Computing High Side Gain Stage

EDP Current :12A

ISL6259 Gain: 36x

from 3.3V with increasing discharge current.

In battery discharge scenario negative voltage will be

(For R and C)

With 100mA battery current, Will have 10.2mV difference

Scale: 2.5A / V

EDP Current: 3.5A

GAIN : 100X

MAX Vdiff : 24 mV

Scale: 2.78A / V

EDP Current: 310A

Max VOut: 3.3V at 9.167A

PLACEMENT_NOTEs:

RTHEVENIN = 4573 Ohms

VP0R: PBUS Voltage Sense Enable & Filter

Max VOut: 3V at 10.44V Input

going into sense pins of U5800. This will set the minumum current threshold at 0.100mA

GAIN: 500X

(500V/V)

Max VOut: 1.4V at 8.25A

POR VOLTAGE / CURRENT SENSORS : TO BE USED IN PRODUCTION

(100V/V)

IC0R : COMPUTING High Side Current Sense

Max VOut: 3V at 5.535V Input

31 33

Place close to SMC

PLACE_NEAR=U5000.B3:11mm

X5R 0201

20%

6.3V

0.22UF

C5455

1

2

PLACE_NEAR=U5000.B3:11mm

4.53K

MF

201

1%

1/20W

R5455

12

5%

201

1/20W

20K

MF

R5451

1

2

0201

CERM-X5R

0.1UF

10%

6.3V

BYPASS=U5450.3::5MM

C5450

1

2

INA214

SC70

PLACE_NEAR=R5450:5MM

CRITICAL

U5450

2

5

4

6

1

3

31 33

PLACE_NEAR=U5000.F1:11MM

10V

2.2NF

X5R-CERM 0201

10%

C5430

1

2

45.3K

MF

201

1%

1/20W

PLACE_NEAR=U5000.F1:11MM

R5430

12

43

31 33

10V

0201

X7R-CERM

10%

3300PF

PLACE_NEAR=U5000.F2:11MM

C5420

1

2

300K

MF

201

1%

1/20W

PLACE_NEAR=U5000.F2:11MM

R5420

12

43

31 32 43 62

31

33

64

1/20W

1%

201

MF

100K

R5411

1

2

PLACE_NEAR=Q7110.2:11MM

NTUD3169CZ

SOT-963

Q5410

6

3

2

5

1

4

201

1/20W

100K

MF

1%

R5401

1

2

MF

1%

1/20W

201

27.4K

PLACE_NEAR=U5000.E1:11MM

R5413

1

2

MF

1/20W

1%

PLACE_NEAR=U5000.E1:11MM

4.53K

201

R5414

1

2

6.3V

0.22UF

X5R 0201

20%

PLACE_NEAR=U5000.E1:11MM

C5414

1

2

1/20W

1%

201

MF

137K

R5412

1

2

31 33

PLACE_NEAR=F7140.2:11MM

NTUD3169CZ

SOT-963

Q5400

6

3

2

5

1

4

MF

201

1/20W

100K

1%

R5402

1

2

31 33

INA211

SC70

CRITICAL

PLACE_NEAR=R7150:5MM

CKPLUS_WAIVE=NdifPr_badTerm

U5460

2

5

4

6

1

3

1/20W

5%

201

MF

20K

R5463

1

2

6.3V CERM-X5R

0.1UF

0201

10%

C5461

1

2

27K

1/20W

MF

201

1%

R5461

1

2

36 73

201

MF

1%

1K

1/20W

R5462

1

2

36 73

SM

PLACE_NEAR=U5460.3:1mm

XW5460

12

PLACE_NEAR=U5000.E2:11MM

1% MF

68K

201

1/20W

R5403

1

2

PLACE_NEAR=U5000.E2:11MM

1%

1/20W

MF

201

27.4K

R5404

1

2

10%

6.3V

0.047UF

201

X5R

PLACE_NEAR=U5000.E2:11MM

C5404

1

2

0612

CYN

1W

1%

0.002

CRITICAL

R5450

123

4

31 33

0201

6.3V

0.22UF

20% X5R

PLACE_NEAR=U5000.A4:11MM

C5421

1

2

201

1/20W

MF

4.53K

1%

PLACE_NEAR=U5000.A4:11MM

R5421

12

SM

PLACE_NEAR=R7320.2:11MM

XW5420

12

PLACE_NEAR=L7850.2:11MM

SM

XW5421

12

84.5K

1/20W

1%

201

MF

R5422

1

2

100K

MF

201

1%

1/20W

R5423

1

2

31 33

X5R 201

0.047UF

6.3V

10%

C5423

1

2

Voltage & Current Sensing

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=02/07/2014

SMC_ACC_VSENSE

PP5V1_S4SW

PBUSVSENS_EN_L_DIV

GND_SMC_AVSS

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_G3H

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

PBUS_S0_VSENSE

ISNS_HS_GAIN_P

ISNS_HS_COMPUTING_P

GND_SMC_AVSS

PPBUS_G3H

SMC_PBUS_VSENSE

PBUSVSENS_EN_L

CHGR_BMON

GND_SMC_AVSS

SMC_DCIN_ISENSE

CHGR_AMON

SMC_BMON_ISENSE

GND_SMC_AVSS

SMC_BC_ACOK

SMC_SENSOR_PWR_EN

PPDCIN_G3H

PP3V3_S0

ISNS_HS_COMPUTING_IOUT

SMC_HS_COMPUTING_ISENSE

ISNS_HS_COMPUTING_N

SMC_DCIN_VSENSE

ISNS_HS_GAIN_N

PP3V3_S0

ISNS_HS_GAIN_OUT

DCIN_S5_VSENSE

DCINVSENS_EN_L

PDCINVSENS_EN_L_DIV

GND_SMC_AVSS

SMC_CPU_VSENSE

PPVCC_S0_CPU

ACC_VSENSE_IN

CPUVSENSE_IN

<SCH_NUM>

54 OF 130

35 OF 75

50 60

31 33

35

44 45 46 48 60

30 35 43 46 47 48 49 50 60

35 73

35

73

35 73

31 33 35

30 35 43 46 47 48 49 50 60

31 33 35

28 29 43 60

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

35 73

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

31 33 35

8

10 45 60

WWW.AliSaler.Com

NC

GND

V+

ADD0

ALERT

SCL

SDA

DUR_SEL

DP1

VDD

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

GPIO

THRM_PAD

GND

TH_SEL

SENSE-

SENSE+

DN2/DP3

DP2/DN3

DN1

OUT OUT

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

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4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Read Address: 0x99

Write Address: 0x98

NAND Temp Sensor

Place Q5560 between U2300 and U2500 on the Bot side

Placement note (DRAM Prox):

Place U5500 next to L7310/L7320 on the Top Side

Placement note: (CPU Prox)

Place Q5510 near L7130 on TOP side

Placement note (Charger Prox):

Place U5580 next to SSD Gumstick

POR THERMAL SENSORS : TO BE USED IN PRODUCTION

Place Q5530 next to J3501 on Bot side

Placement note (Wireless Prox):

Placement note: (NAND Prox)

CPU Proximity, Inlet ,DDR and BMON THR Sensor

100K

1/20W

5%

201

MF

R5506

1

2

1/20W

5%

0201

MF

0

R5505

1

2

0201

CERM-X5R

10%

0.1UF

6.3V

PLACE_NEAR=U5580.5:5mm

C5560

1

2

HPA00330AI

SOT563

U5580

4

3

2

1

6

5

QFN

EMC1704-2

CRITICAL

U5500

6

103

5

2

4

13

8

7

15

16

12

11

14

9

17

1

10V

2200PF

10%

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5500.2:5mm

PLACE_NEAR=U5500.3:5mm

X7R-CERM

0201

C5501

1

2

NOSTUFF

1/20W

10K

MF

5%

201

R5504

1

2

PLACE_NEAR=U5500.5:5mm

PLACE_NEAR=U5500.4:5mm

2200PF

10%

NO_XNET_CONNECTION=TRUE

10V

X7R-CERM

0201

C5502

1

2

10K

5%

1/20W

201

MF

NOSTUFF

R5503

1

2

35 73

CERM-X5R

6.3V

10% 0201

0.1UF

PLACE_NEAR=U5500.3:5mm

C5500

1

2

DFN1006H4-3

BC846BLP

Q5560

1

3

2

PLACE_NEAR=Q5560:3MM

5%

0201

C0G

25V

47PF

C5563

1

2

0201

47PF

PLACE_NEAR=Q5530:3MM

5% 25V C0G

C5530

1

2

DFN1006H4-3

BC846BLP

Q5530

1

3

2

25V

5%

0201

C0G

47PF

PLACE_NEAR=Q5510:3MM

C5511

1

2

BC846BLP

DFN1006H4-3

Q5510

1

3

2

33

5% MF

47

201

1/20W

PLACE_NEAR=U5500.2:5mm

R5500

12

33

14 31 34 36

53 68 72

14 31 34 36 53 68 72

Temperature Sensing

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=09/12/2013

PP3V3_S0

PP3V3_S0_CPUTHMSNS_R

VOLTAGE=3.3V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm

CPUTHMSNS_ALERT_L

CPUTHMSNS_DUR_SEL

ISNS_HS_GAIN_N

SMBUS_SMC_1_S0_SDA

ISNS_HS_GAIN_P

CPUBMONSNS_ALERT_L

CPUTHMSNS_ADDR_SEL

SMBUS_SMC_1_S0_SCL

PP3V3_S0

SMBUS_SMC_1_S0_SCL

NAND_OVERTMP_ALERT_L

INLET_THMSNS_D1_P

CPUTHMSNS_D2_N

SMBUS_SMC_1_S0_SDA

INLET_THMSNS_D1_N

CPUTHMSNS_D2_P

CPUTHMSNS_TH_SEL

<SCH_NUM>

55 OF 130

36 OF 75

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

14 31 34 36 53 68 72

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

73

14 31 34 36 53 68 72

73

WWW.AliSaler.Com

BI

IN

OUT

BI

VCC

D

B

AY

OE*

C

GND

BI

OUT

BI

OUT

NC

NC NC NC NC NC NC NC

VCC

NC

SIO3/HOLD*/

SIO2/W*/VPP/

CS*

GND/VSS

NC

SO/SIO1/

SI/SIO0/

NC

SCLK/C/CLK

NC

DQO/DI/IO0

DQ3/IO3

DQ2/WP/IO2

DQ1/DO/IO1

NC NC NC NC

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

516S00024

SPI ROM - Combo BGA Footprint (3 vendors)

Quad-IO Mode (Mode 0 & 3) supported. SPI Frequency: 50MHz for CPU, 20MHz for SMC.

Sam Card ROM Slave

(SPI_IO<0>)

BootROM SPI Bus Series Termination

SPI ROM Slave

(SWCLK)

(SWDIO)

(SPI_IO<1>)

SMC12 Master

CPU Master

SPI+SWD SAM Connector

201

1/20W

MF

1%

11

R6122

12

PLACE_NEAR=U0500.D31:50MM

1/20W

201

5% MF

11

R6112

12

14 68

31 68

31

68

31 68

201

5%

1/20W

MF

PLACE_NEAR=U5000.K10:12MM

22

R6117

12

201

5%

1/20W

MF

PLACE_NEAR=U5000.N9:12MM

22

R6115

12

201

5%

1/20W

MF

PLACE_NEAR=U5000.L10:12MM

22

R6116

12

201

5%

1/20W

MF

PLACE_NEAR=U5000.M9:12MM

22

R6114

12

PLACE_NEAR=U0500.B23:50MM

201

5%

1/20W

MF

11

R6113

12

201

PLACE_NEAR=U6100.3:12MM

1/20W

MF

1%

11

R6130

12

201

1/20W

PLACE_NEAR=U6100.7:12MM

MF

1%

11

R6131

12

14

PLACE_NEAR=J6100.9:5MM

MF

1/20W 0201

0

5%

R6133

1

2

PLACE_NEAR=J6100.7:5MM

5%

0

0201

1/20W MF

R6132

1

2

PLACE_NEAR=J6100.5:5MM

MF

1/20W 0201

0

5%

R6128

1

2

PLACE_NEAR=J6100.3:5MM

MF

1/20W 0201

0

5%

R6127

1

2

PLACE_NEAR=J6100.11:5MM

5%

0

0201

1/20W MF

R6126

1

2

0201

PLACE_NEAR=J6100.12:5MM

5%

0

1/20W MF

R6125

1

2

BYPASS=U6100::3mm

X5R-CERM

0.1UF

0201

10% 16V

C6100

1

2

CRITICAL

74LVC1G99

SOT833

PLACE_NEAR=U6100.1:12MM

U6101

2 3 5 6

4

1

8

7

16V

BYPASS=U6101::3mm

0201

X5R-CERM

10%

0.1UF

C6101

1

2

26 31 32

62

26 31 32 62

15 37

31 43 59

CRITICAL

DF40PC-12DP-0.4V-51

M-ST-SM

J6100

1

10

1112

1314

15

16

2

34 56 78 9

CRITICAL

WLBGA-COMBO-J92

3V-64MBIT

OMIT_TABLE

W25Q64FVBYIQ

U6100

A2

D2

1 2

11 12

3 4 5

6 7 8 9 10

C1

D1

C2

B1

B2

A1

PLACE_NEAR=U0500.H27:50MM

201

5%

1/20W

MF

11

R6110

12

14 68

PLACE_NEAR=U0500.C26:50MM

201

5%

1/20W

MF

11

R6111

12

14 68

201

PLACE_NEAR=U6100.2:12MM

1/20W

MF

1%

11

R6123

12

14 68

PLACE_NEAR=U6101.3:3MM

1/20W

MF

1%

201

11

R6120

12

201

1/20W

MF

1%

PLACE_NEAR=U6100.6:12MM

11

R6121

12

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=07/23/2013

SPI+SWD Debug Connector

SPI_MISO_R

SPI_IO<2>

SPI_CLK

SPI_MLB_CS_L

SPI_ALT_CLK

SPI_IO<3>

SPI_MISO

SPI_CLK_R

SPI_CS0_R_L

SPI_SMC_CLK

SPI_SMC_CS_L

SPI_SMC_MISO

SPI_SMC_MOSI

SPI_MOSI

SPI_MLB_IO<2>

SPI_ALT_CS_L

SPI_ALT_IO<2> SPI_ALT_MISO SPI_ALT_MOSI

SPI_MLB_CLK

SPI_MLB_IO<3>

SPI_MLB_MISO

SPI_MLB_CS_L

SPI_MLB_MOSI

PLACE_NEAR=U6100.5:12MM

SPIROM_USE_MLB

SPI_ALT_IO<3>

SPI_MLB_MISO

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_MLB_IO<3>

SPI_MLBROM_CS_L SPI_MLB_IO<2>

PP3V3_S5

SPI_CS0_L

SMC_TCK

SPI_ALT_IO<3>

SMC_TMS

SPI_ALT_IO<2>

SPIROM_USE_MLB

SPI_ALT_MISO

SPI_ALT_MOSI

PP3V3_G3H

SPI_ALT_CLK SPI_ALT_CS_L

SMC_RESET_L

SPI_MOSI_R

37 OF 75

61 OF 130

<SCH_NUM>

68

37 68

37

68

37

37 68

37

68

37 68

15 37

37

37 68

37 68 37 68

37

8

11 13 15

16 17 22 33 46 47

51 59 60 73 75

68

37

17 28 30 31 32 33 34 42 43 60

37

WWW.AliSaler.Com

OUT

GAIN_SLOT

OUTN

OUTP

GND

VDD

DIN

LRCLK

BCLK

SD_MODE*

IN

OUT

IN

GAIN_SLOT

OUTN

OUTP

GND

VDD

DIN

LRCLK

BCLK

SD_MODE*

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SPEAKER CONFIGS

APPLE P/N 353S4265

Left Speaker Amps

0

5%

MF

0201

1/20W

R6310

1

2

0805

POLY-TANT

6.3V

CRITICAL

20%

47UF

C6311

1

2

40 73

MAX98357BEWL

WLP

CRITICAL

U6310

C1

B1

B2

C2

C3

B3

A3A1

A2

NOSTUFF

1/20W

0

5%

MF 0201

R6311

1

2

38 39 40

38

39 40

38 39 40

POLY-TANT

CRITICAL 47UF

6.3V

20%

0805

C6321

1

2

38 39 40

0

LCHANNEL:1

0201

1/20W

MF

5%

R6320

1

2

BYPASS=U6320.A2:C2:3 MM

0.1UF

16V 0201

10% X5R-CERM

C6320

1

2

40 73

LCHANNEL:0

0

1/20W MF

5%

0201

R6321

1

2

38 39 40

1/20W

MF

0201

0

5%

R6312

12

1/20W

0

0201

5% MF

R6322

12

38 39 40

38

39 40

38 39 40

0

0201

MF

1/20W

5%

R6324

12

1/20W

5% MF

0

0201

R6325

12

NOSTUFF

5%

100PF

0201

C0G

25V

C6313

1

2

NOSTUFF

5%

100PF

25V C0G 0201

C6312

1

2

CRITICAL

MAX98357BEWL

WLP

U6320

C1

B1

B2

C2

C3

B3

A3A1

A2

1/20W

0201

5%

0

MF

R6315

12

0201

0

5%

MF

1/20W

R6314

12

NOSTUFF

100PF

5% 25V C0G 0201

C6322

1

2

NOSTUFF

100PF

5% 0201

C0G

25V

C6323

1

2

0201

1/20W

5%

0

MF

R6313

12

0201

5% MF

1/20W

0

R6323

12

10%

0.1UF

X5R-CERM

16V 0201

BYPASS=U6310.A2:C2:3 MM

C6310

1

2

Audio:Left Speaker Amps

SYNC_DATE=09/19/2013

SYNC_MASTER=J92_DEVMLB

LCHANNEL:0,RCHANNEL:4

EQ:4CH

EQ:2CH

LCHANNEL:1,RCHANNEL:3

MIN_LINE_WIDTH=0.40 mm

MIN_NECK_WIDTH=0.10 mm

SPKRAMP_LOUT2_N

MIN_LINE_WIDTH=0.40 mm

MIN_NECK_WIDTH=0.10 mm

SPKRAMP_LOUT2_P

SPKRAMP_LOUT1_P

MIN_NECK_WIDTH=0.10 mm

MIN_LINE_WIDTH=0.40 mm

MIN_NECK_WIDTH=0.10 mm

SPKRAMP_LOUT1_N

L_AMP2_GAIN

L_AMP1_GAIN

AUD_SCLK_A

AUD_LRCLK_A

PP5V_S4

AUD_SCLK_A

AUD_SDOUT_LEFT2

AUD_LRCLK_LEFT2

AUD_SDOUT_LEFT1

AUD_SDOUT_A

AUD_SCLKA_LEFT2

AUD_SPKRAMP_MODE

PP5V_S4

AUD_LRCLK_LEFT1

AUD_SCLKA_LEFT1

AUD_SPKRAMP_MODE_LEFT1

AUD_LRCLK_A

AUD_SDOUT_A

AUD_SPKRAMP_MODE

AUD_SPKRAMP_MODE_LEFT2

<SCH_NUM>

63 OF 130

38 OF 75

30 38 47

53 60 75

30 38 47 53 60 75

WWW.AliSaler.Com

IN

OUT

IN

GAIN_SLOT

OUTN

OUTP

GND

VDD

DIN

LRCLK

BCLK

SD_MODE*

GAIN_SLOT

OUTN

OUTP

GND

VDD

DIN

LRCLK

BCLK

SD_MODE*

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APPLE P/N 353S4265

Right Speaker Amps

38 39 40

38

39 40

100K

1/20W MF

5%

201

RCHANNEL:4

R6421

1

2

16V 0201

10% X5R-CERM

0.1UF

BYPASS=U6420.A2:C2:3 MM

C6420

1

2

RCHANNEL:3

100K

MF

5%

201

1/20W

R6420

1

2

6.3V

47UF

POLY-TANT

20%

0805

CRITICAL

C6421

1

2

NOSTUFF

100K

MF

5%

201

1/20W

R6411

1

2

38 39 40

40 73

40

73

16V

0.1UF

10% X5R-CERM

0201

BYPASS=U6410.A2:C2:3 MM

C6410

1

2

201

100K

MF

5%

1/20W

R6410

1

2

47UF

20% POLY-TANT

6.3V 0805

CRITICAL

C6411

1

2

5%

MF

0

0201

1/20W

R6414

12

5%

1/20W

MF

0

0201

R6415

12

5%

0

MF

0201

1/20W

R6422

12

5%

0

1/20W

MF

0201

R6425

12

0

5%

MF

0201

1/20W

R6424

12

38 39 40

38

39 40

NOSTUFF

0201

C0G

25V

100PF

5%

C6413

1

2

NOSTUFF

25V C0G 0201

100PF

5%

C6412

1

2

CRITICAL

WLP

MAX98357BEWL

U6410

C1

B1

B2

C2

C3

B3

A3A1

A2

MAX98357BEWL

CRITICAL

WLP

U6420

C1

B1

B2

C2

C3

B3

A3A1

A2

1/20W

MF

0

5%

0201

R6423

12

MF

5%

0

1/20W

0201

R6413

12

NOSTUFF

25V C0G 0201

5%

100PF

C6422

1

2

NOSTUFF

0201

C0G

25V

5%

100PF

C6423

1

2

38 39 40

5% MF

1/20W

0201

0

R6412

12

38 39 40

38

39 40

Audio:Right Speaker Amps

SYNC_DATE=09/19/2013

SYNC_MASTER=J92_DEVMLB

MIN_NECK_WIDTH=0.10 mm

SPKRAMP_ROUT1_P

MIN_LINE_WIDTH=0.40 mm

SPKRAMP_ROUT2_N

MIN_LINE_WIDTH=0.40 mm

MIN_NECK_WIDTH=0.10 mm

SPKRAMP_ROUT2_P

MIN_LINE_WIDTH=0.40 mm

MIN_NECK_WIDTH=0.10 mm

MIN_NECK_WIDTH=0.10 mm MIN_LINE_WIDTH=0.40 mm

SPKRAMP_ROUT1_N

AUD_LRCLK_A

AUD_SCLK_A

AUD_SDOUT_A

R_AMP1_GAIN

R_AMP2_GAIN

PP5V_S0

AUD_SDOUT_RIGHT1

AUD_LRCLK_RIGHT2

AUD_SCLK_RIGHT1AUD_SCLK_A

AUD_LRCLK_RIGHT1

AUD_SCLK_RIGHT2

AUD_SPKRAMP_MODE

AUD_SPKRAMP_MODE_RIGHT2

AUD_SPKRAMP_MODE

AUD_SDOUT_RIGHT2

PP5V_S0

AUD_SPKRAMP_MODE_RIGHT1

<SCH_NUM>

64 OF 130

39 OF 75

16 17 25

30 39 40 44 45 47 49

51 60

16 17 25 30 39 40 44 45 47 49 51 60

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NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LEFT SPEAKER CONN

518S00014

RIGHT SPEAKER CONN

MIC_BIAS (80%)

I2C_MIKEY_SDA/SCL

AUD_I2C_INT_L

SOUTHBRIDGE RESOURCE/PIN ALLOCATIONS

0X06 (6)

CONVERTER

CODEC INPUT SIGNAL PATHS

PIN COMPLEX

HP/LINE OUT

518S1034

RIO FLEX CONN

0X0D (13,V22,B,LEFT)

0X0D (13,B,RIGHT)

516S0899

PIN COMPLEX

CODEC OUTPUT SIGNAL PATHS

0X04 (4)

VOLUME 0X02 (2)

SB GPIO/INT

PCH SMBUS 0

MUTE CONTROL

MIKEY INTERRUPT

VREF

CONVERTER 0X02 (2)

GPIO 3

NET NAME AUD_IP_PERIPHERAL_DET

GPIO 16

AUD_IPHS_SWITCH_ENMIKEY ENABLE

FUNCTION

HEADSET MIC

PERIPHERAL/EXTRACTION DETECT

FUNCTION

0X0B (11)

MIKEY

SPEAKERS

0X06 (6)

MIKEY I2C BUS

N/A

0X09 (A)

GPIO_3

FUNCTION

GPIO 5

0X09 (9,A)

MIKEY

BUILT-IN MIC

0X04 (4)

N/A

DET ASSIGNMENT

38 73

AA07A-S010-VA1

CRITICAL

F-ST-SM

J6750

11

12

13 14

1

10

2 34 56 78 9

38 73

39

73

F-RT-SM

CRITICAL

502250-8027

J6799

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

4

5

6

7

8

9

F-RT-SM-A

CRITICAL

FF18-10A-R11AD-B-3H

J6751

11

12

1

10

2 3 4 5 6 7 8 9

39 73

39

73

SYNC_DATE=04/17/2014SYNC_MASTER=CARA_J92

AUDIO: CONNECTORS

AUD_LRCLK_A PP5V_S0

HDA_SDIN0

HDA_BIT_CLK HDA_SDOUT

HDA_SYNC

PP3V3_S0

HDA_RST_L

AUD_PWR_EN

SPKRAMP_LOUT1_P

SPKRAMP_ROUT1_P

SPKRAMP_ROUT1_N

SPKRAMP_ROUT2_P

SPKRAMP_ROUT2_NSPKRAMP_LOUT2_N

SPKRVNDR_R_ID

SPKRAMP_LOUT1_N

SPKRVNDR_L_ID

PP1V5_S0

SPKRVNDR_R_ID

SMBUS_SMC_3_SDA

SPKRAMP_LOUT2_P

AUD_SCLK_A

AUD_SDOUT_A

AUD_SPKRAMP_MODE

SMBUS_SMC_3_SCL

<SCH_NUM>

67 OF 130

40 OF 75

38 39

16 17

25 30 39 44 45 47 49 51

60

12 64 68

12 68

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 46 47 53 60 73 75

12 68

13 64

40

8

11 17 46

60

40

30 31 34 72

38 39

30 31 34 72

WWW.AliSaler.Com

IN

SYM_VER_2

GS

D

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Dim LED always lit when G3H rails are energized

Press switch to de-energize

G3H rails on battery-only

516-0343

Battery Connector

31 34 43

72

0

MF

1/20W

5%

NO STUFF

0201

R6950

1

2

DFN1006H4-3

DMN32D2LFB4

CRITICAL

Q6950

3

1

2

10K

MF

1/20W

5%

201

R6951

1

2

BATT-COMPRESSION-J92

ST-TH1

CRITICAL

J6950

1 2 3 4 5 6 7

31 34 43

72

CRITICAL

WHITE-140MCD-0.005A-2.7V 0402

D6900

A

K

MF

1/20W

5%

1M

201

R6952

1

2

CRITICAL

SOX-152HNT

SM

SW6900

12

CRITICAL

RCLAMP2402B

SC-75

D6950

3

1

2

10% 25V

0.1UF

402

X5R

C6950

1

2

X5R

1UF

16V 402

10%

C6951

1

2

SYNC_DATE=10/24/2012

Battery Connector

SYNC_MASTER=J43_MLB

PP3V3R3V0_AON

SMBUS_SMC_5_G3_SCL

PPVBAT_G3H_CONN

SMBUS_SMC_5_G3_SDA

SYS_DETECT_L

SYS_DETECT_LED

SYS_DETECT

<SCH_NUM>

69 OF 130

41 OF 75

26 28 29 34

43 60

43 46 60

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THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

87 6 5

4 3

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3.3V G3H VR - Bansuri

APN 152S1872

Vout = 1.25V * (1 + Ra / Rb)

Vout = 3.3V

300mA Max Output

(Switcher limit)

0603-1

35V X5R-CERM

10%

4.7UF

C7000

1

2

0603-1

35V X5R-CERM

10%

4.7UF

C7001

1

2

0603-1

35V X5R-CERM

4.7UF

10%

C7002

1

2

0201

0

5%

1/20W

MF

R7094

1

2

MF

1/20W

5%

10

201

R7090

1

2

10V 0402-7

X5R-CERM

20%

10UF

CRITICAL

C7097

1

2

5% CERM

12PF

25V 0201

C7096

1

2

33NF

CERM

10% 25V

402

C7094

1

2

10UF

20% X5R-CERM

0402-7

10V

CRITICAL

C7098

1

2

CRITICAL

10V

0402-7

X5R-CERM

20%

10UF

C7099

1

2

10UH-20%-0.85A-0.46OHM

CRITICAL

2520

L7095

12

SYNC_MASTER=J92_WILL SYNC_DATE=02/04/2013

3.3V G3Hot Regulator

PP3V3_G3H

PPVIN_G3H_P3V3G3H

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

P3V3G3H_SW

SWITCH_NODE=TRUE DIDT=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

P3V3G3H_BOOT_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

P3V3G3H_BOOT

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P3V3_G3H_REG_FB

<SCH_NUM>

70 OF 130

42 OF 75

17 28 30 31

32 33 34 37 43 60

43 60

43

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VDDA

VBAT

VCC_VR1

VR1_3P3

VR_AON

BOOT_VR2

BOOT_VR1

LX_VR2

PGOOD_VR2

HOST_RESET

LX_VR1

LX1 LX2

BOOT2

BOOT1

EN_VR2

LDO_3P0

FB_VR1 FB_VR2

LDO_5P0

AMON

ACOK

CBC_ON

CSOP

IRQ_L

PGND

PGND_VR2

PGND_VR1

AGND

P_IN

ACIN

GPIO1

GATE_Q1

GATE_Q3 GATE_Q4

GATE_Q2

POWER_GATE_EN

CSIP

CSIN

COMP

BGATE

BMON

CSON

HPWR_EN

PBUS PBUS

SMC_RST*

SMC_RST_IN

SCL

SDA

VDDP_2

VDDP_1

OUT

IN

OUT

IN

BI

S

G

D

NC

BG

TGR

TG

PGND

VIN

VSW

NC NC

NC

OUT

S2

D1

G2

G1

S1/D2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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D

A

C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

FROM ADAPTER

APN 376S1203

TO SYSTEM

APN 152S1914

APN 376S1179

(CHGR_PHASE)

(CHGR_BOOST_SW)

(CHGR_BGATE)

.

Charger PMIC - Bansuri

TO/FROM BATTERY

(CHGR_CSO_N)

(CHGR_CSO_P)

APN 376S1187

1% MF

1/20W 201

255K

R7111

1

2

10V X5R-CERM

10UF

20%

0402-7

C7103

1

2

10V

X5R-CERM

10UF

20%

0402-7

C7102

1

2

1%

750K

MF

1/20W 201

R7110

1

2

1.0UF

CERM-X6S

35V

10%

0402

C7122

1

2

NOSTUFF

0.047UF

201

10%

6.3V X5R

C7120

1

2

1

5%

201

1/20W

MF

R7122

12

20%

10UF

35V

CASE-D2-SM

TANT-POLY

CRITICAL

C7130

1

2

TANT-POLY

20%

CRITICAL

10UF

35V

CASE-D2-SM

C7131

1

2

0603

8AMP-32V-0.006OHM

CRITICAL

F7140

12

10%

0.01UF

0201

X5R-CERM

10V

C7111

1

2

0201

CER-X5R

25V

4700PF

10%

C7126

1

2

BYPASS=Q7130::1.5mm

10%

0.001UF

50V X7R-CERM 0402

C7137

1

2

1000PF

X7R-1

16V

0201

10%

C7145

1

2

0402

35V X5R-CERM

2.2UF

20%

C7135

1

2

0402

35V

20%

2.2UF

X5R-CERM

C7136

1

2

0402-1

25V X5R-CERM

2.2UF

20%

C7114

1

2

402

10%

X5R

25V

0.1UF

C7113

1

2

0.01UF

10% 25V X7R 402

C7112

1

2

45UF

20%

CASED12-SM

11V

POLY

CRITICAL

C7143

1

2

WCSP

CRITICAL

ISL95530HIZ-TR5655

OMIT_TABLE

U7100

D2

D3

B3G4D1

C4

F3

G3

B1 B7

G6 C6

E5

B5

C3

C2

G2

F2

C5

G5 D5

A2 A3 A5 A6

B2

D4

E3

G1

H1

H4

A1 A7

H6 E6 E7

G7

F6 F7

A4H5D6

D7

B6E2

E1

F1

F4

E4

F5H7B4

C1

C7

H3

H2

35

31 64

31 32

35 62

31 64

30

35

28 64

28 31 64

31 34 41 72

PIME062T-SM

CRITICAL

2UH-20%-9.3A-0.024OHM

L7130

1

2

0.047UF

X5R

16V

NOSTUFF

0201

10%

C7150

1

2

X7R-CERM-1

10% 25V

0402

0.1UF

C7127

1

2

SI7655DN

PWRPK-1212-8

CRITICAL

Q7155

5

4

123

X5R

0402-1

25V

1UF

10%

C7104

1

2

0402-1

25V X5R

10%

1UF

C7105

1

2

0402

0.33UF

25V

10%

X5R

C7116

1

2

2.2UF

25V X5R-CERM 0402-1

20%

C7144

1

2

0201

5%

1/20W

0

MF

R7127

12

1/20WMF0201

0

5%

R7125

12

CSD58879Q3D

CRITICAL

Q3D

Q7120

5

9

3

4

1

6 7 8

25V

0402-1

1UF

10%

X5R

C7101

1

2

1UF

10%

X5R

25V

0402-1

C7100

1

2

X5R

0402-1

10%

1UF

25V

C7106

1

2

1/20W

4.7

MF

201

5%

R7104

12

MF

1/20W

0201

0

5%

R7101

12

CRITICAL

1% 1/3W N/A

0.020 OHM

0603-COMBO

R7120

214

3

CRITICAL

0.010 OHM

1/3W

1%

N/A

0603-COMBO

R7150

21 43

MF

201

1

5%

1/20W

R7121

12

1

5%

1/20W

MF

201

R7151

12

1

MF

1/20W

5%

201

R7152

12

0402

0.47UF

X5R

25V

10%

C7128

1

2

25V X5R 0402

0.47UF

10%

C7129

1

2

100K

MF

1/20W

201

5%

R7160

1

2

31 37 59

10%

NOSTUFF

0201

25V X7R-CERM

1000PF

C7118

1

2

25V X5R-CERM

2.2UF

20%

0402-1

C7119

1

2

X7R-CERM-1 0402

10% 25V

0.1UF

C7125

1

2

16V

0.1UF

X5R-CERM

10%

0201

PLACE_NEAR=U7100.F5:2.54mm

C7110

1

2

PWRPAIR-3X3

CRITICAL

SIZ342JT

Q7110

2 3 4 10

1

8

9

5 6 7

1.0UF

CERM-X6S

35V

10%

0402

C7121

1

2

CER-X5R

35V

0201

0.1UF

10%

C7107

1

2

0402-1

20%

2.2UF

X5R-CERM

25V

C7117

1

2

0402-1

20% X5R-CERM

25V

2.2UF

C7146

1

2

MF

201

5%

10K

1/20W

R7161

1

2

0201

25V

12PF

CERM

5%

C7147

1

2

C0G-CERM

50V 0201

12PF

5%

C7109

1

2

IC,ISL95530B1T11,CHGR PMU,BANSURI,WCSP56

353S00347

U7100

1

CRITICAL

PBus Supply & Battery Charger

SYNC_DATE=04/04/2014

SYNC_MASTER=J92_DEVMLB

CHGR_BOOST_DH

TS_POWER_GATE_EN

SMBUS_SMC_5_G3_SCL

P3V3_G3H_REG_FB

TS_HOST_RST

MIN_LINE_WIDTH=0.6 mm

CHGR_LDO_P3V0

MIN_NECK_WIDTH=0.2 mm

CHGR_AMON

CHGR_PHASE2

MIN_LINE_WIDTH=0.6 mm

CHGR_BOOT2

MIN_NECK_WIDTH=0.2 mm

P3V3G3H_BOOT

CHGR_BUCK_DL

CHGR_BMON

CHGR_BOOT1_RC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

CHGR_CSI_R_N

P3V3G3H_SW

CHGR_CSO_R_P

MIN_LINE_WIDTH=0.6 mm

CHGR_LDO_P5V0

MIN_NECK_WIDTH=0.2 mm

SMC_BC_ACOK

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_BUCK_DL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_BOOT1

SMC_CBC_ON

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_BOOST_DH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_BOOST_DL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_BOOT2_RC

SMC_CHGR_INT_L

SMBUS_SMC_5_G3_SDA

CHGR_BOOST_DL

SMC_LSOC_RST

CHGR_CSI_R_P

CHGR_BUCK_DH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm VOLTAGE=8.6V

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CONN

SMC_RST_L

CHGR_LDO_P5V0

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_R

CHGR_CSO_R_N

SMC_RESET_L

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

CHGR_BGATE

CHGR_BUCK_DH

CHGR_ACIN

TS_HIPWR_EN

CHGR_CSI_P

CHGR_CSO_P

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.1 mm

PPVIN_G3H_P3V3G3H

PPBUS_G3H

PPVBAT_G3H_CHGR_REG

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_LDO_VDDA

CHGR_CSI_P

MIN_LINE_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm

CHGR_CSO_N

CHGR_CSI_N

PPDCIN_G3H

CHGR_COMP

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

CHGR_BOOST_SW

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_CHGR

CHGR_PHASE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

CHGR_CSI_N

PPVBAT_G3H_CONN

CHGR_LDO_VDDP

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3R3V0_AON

PP3V3_G3H

<SCH_NUM>

71 OF 130

43 OF 75

43

42

43

72

42

72

43

72

43

41 43 46

60

43

72

30 35 43 46 47 48 49 50 60

43

43 72

72

42 60

30 35 43 46 47 48 49 50 60

43 72

72

43 72

28 29 35 60

43 72

41 43 46 60

26 28 29 34 41 60

17 28 30 31 32 33 34 37 42 60

WWW.AliSaler.Com

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

NC NC

OUT OUT

IN IN

IN

OUT

IN

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(GND)

(CPUVR_ISUMP)

FCCM = 0: DCM FCCM = FLOATING: PS4

FCCM = 1: Forced CCM

8

66

8

66

8

66

8

6

31 32 66

PLACE_NEAR=U7200.32:2mm

201

1/20W

MF

54.9

1%

R7279

1

2

201

1/20W MF

130

1%

PLACE_NEAR=U7200.30:2mm

R7280

1

2

ISL95826AHRZ-_S2378

LLP

CRITICAL

U7200

31

6

25

7 8

18

3

12 11 10

14

15

9

19 21 24

5

2

28 27 26 20

22

23

13

32

30

29

33

16

17

4

1

8

62

45

5%

10

MF-LF

1/16W

402

R7202

12

X7R

0.22UF

PLACE_NEAR=U7200.17:2mm

0402

10% 25V

C7202

1

2

5%

1

MF-LF

1/16W

402

R7201

12

PLACE_NEAR=U7200.16:2mm

10V

1UF

402-1

X5R

10%

C7201

1

2

45

0.01UF

X7R-CERM 0201

10V

10%

C7210

1

2

X7R-CERM

0.01UF

0201

10V

10%

C7211

1

2

45

6.3V

CERM-X5R

0201

0.1UF

10%

C7213

1

2

201

1/20W MF

1%

6.04K

R7220

1

2

201

13.3K

1% MF

1/20W

R7221

1

2

31 33

102K

1% MF

1/20W 201

R7230

1

2

10V

1500PF

0201

X7R

10%

C7230

1

2

45

NO_XNET_CONNECTION=TRUE

201

220PF

X7R-CERM

10% 25V

C7214

1

2

201

1/20W

MF

845

1%

R7215

12

0201

820PF

X7R-CERM

10% 25V

C7215

12

47PF

5%

C0G

0201

25V

C7216

12

8

66

9

66

16V

330PF

X7R 0201

10%

C7260

1

2

0201

16V

330PF

X7R

10%

C7261

1

2

10V

CERM

1.2NF

+/-10%

0201-1

C7240

1

2

5%

100PF

0201

C0G

NO_XNET_CONNECTION=TRUE

25V

C7242

12

68PF

C0G

50V

0201

NO_XNET_CONNECTION=TRUE

5%

C7241

1

2

61.9K

NO_XNET_CONNECTION=TRUE

1% MF

1/20W

201

R7240

1

2

201

1/20W

MF

1K

1%

R7242

12

5%

0

0201

1/20W

MF

NO_XNET_CONNECTION=TRUE

R7243

12

9.31K

1/20W

MF

1%

201

R7235

12

1/20W

MF

1%

95.3K

201

R7236

1

2

100KOHM

0201

R7237

1

2

201

MF

1%

2K

NO_XNET_CONNECTION=TRUE

NOSTUFF

1/20W

R7250

12

NOSTUFF

0201

X7R

16V

330PF

10%

C7250

1

2

201

1.15K

1% MF

1/20W

R7241

12

201

215

1% MF

1/20W

R7210

12

201

1/20W MF

16.9K

1%

R7223

1

2

201

1/20W MF

1%

9.31K

R7222

1

2

SM

NO_XNET_CONNECTION=TRUE

XW7261

12

PLACE_NEAR=R7279.1:2mm

6.3V

CERM-X5R

0201

0.1UF

10%

C7278

1

2

CPU VR12.6 VCC Regulator IC

SYNC_MASTER=J43_MLB

SYNC_DATE=10/09/2012

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.9V

CPUVR_ISUMN

CPUVR_FB

CPUVR_ISEN2

CPU_RTN

CPU_PROCHOT_L

CPUVR_FB_RC

CPUVR_FCCM

CPUVR_SLOPE

PP1V05_S0

CPUVR_NTC_R

CPU_VCCSENSE_P_R

CPUVR_ISUMN_RC

CPUVR_COMP_RC

PP5V_S0

PPBUS_S5_HS_COMPUTING_ISNS

CPU_VR_READY

CPUVR_PWM2

CPU_VR_EN

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_VCCSENSE_P_RC

CPUVR_PWM1

CPUVR_PROG1

CPUVR_PROG3

CPUVR_PROG2

CPU_VIDSOUT CPU_VIDALERT_L CPU_VIDSCLK

CPUVR_COMP

CPUVR_FB2

CPUVR_ISUMN_R SMC_CPU_ISENSE

CPUVR_ISEN1

CPUVR_ISUMP

CPUVR_NTC

PP5V_S0_CPUVR_VDD

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.3 mm

<SCH_NUM>

72 OF 130

44 OF 75

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17 32 46 51 60

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IN

OUT

IN

OUT

IN

D

S

G

D

S

G

D

S

G

D

S

G

OUTOUT

THRM

PAD

PHASE

VCC

LGATE

BOOT

UGATE

FCCM

GND

PWM

THRM

PAD

PHASE

VCC

LGATE

BOOT

UGATE

FCCM

GND

PWM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

f = 700kHz

PHASE 1

Vout = 1.85V max

.

PHASE 2

353S3942

27A max load

152S1915

353S3942

NO_XNET_CONNECTION=TRUE

1.00

1% 1/20W MF-LF 0201

R7314

1

2

44

44 45

1/20W MF

1%

200K

201

NO_XNET_CONNECTION=TRUE

R7316

1

2

MF

1/20W

1K

1%

201

NO_XNET_CONNECTION=TRUE

R7315

1

2

44

44 45

NOSTUFF

OMIT

NONE NONE

NO_XNET_CONNECTION=TRUE

0201

NONE

R7317

12

44 45

NO_XNET_CONNECTION=TRUE

1%

1.00

MF-LF

1/20W 0201

R7324

1

2

NO_XNET_CONNECTION=TRUE

MF

1%

200K

201

1/20W

R7326

1

2

201

1K

MF

1%

NO_XNET_CONNECTION=TRUE

1/20W

R7325

1

2

44

0201

NONE NONE

NONE

NOSTUFF

OMIT

NO_XNET_CONNECTION=TRUE

R7327

12

44

44 45

1/16W

402

MF-LF

5%

2.2

R7311

21

0.22UF

16V

CERM

10%

402

C7311

12

1UF

0402

X6S-CERM

16V

10%

C7310

1

2

0402

16V

X6S-CERM

1UF

10%

C7320

1

2

44 45

MF-LF

5%

402

1/16W

2.2

R7321

12

402

16V

0.22UF

CERM

10%

C7321

12

PWRPAK-SM

CRITICAL

SISA18JN_GE3

Q7310

5

4

123

PWRPAK-SM

CRITICAL

SISA18JN_GE3

Q7320

5

4

123

CRITICAL

1%

0.00075

1W MF

0612-1

R7310

12 34

0.00075

CRITICAL

1W

1%

MF

0612-1

R7320

12 34

CRITICAL

PWRPAK-SM

SISA12JN_GE3

Q7311

5

4

123

CRITICAL

SISA12JN_GE3

PWRPAK-SM

Q7321

5

4

123

45 73 73

ISL6208D

DFN

CRITICAL

U7310

2

7

4

5

8

3

9

1

6

CRITICAL

DFN

ISL6208D

U7320

2

7

4

5

8

3

9

1

6

CRITICAL

PILE062T-SM

0.4UH-20%-14A-0.005OHM

L7320

12

CRITICAL

PILE062T-SM

0.4UH-20%-14A-0.005OHM

L7310

12

20%

CASED12-SM

11V

45UF

POLY

CRITICAL

C7370

1

2

CASED12-SM

CRITICAL

POLY

45UF

20% 11V

C7372

1

2

45UF

CASED12-SM

CRITICAL

POLY

20% 11V

C7323

1

2

0402-1

X5R

20%

2.2UF

25V

C7315

1

2

0402-1

X5R

20%

2.2UF

25V

C7325

1

2

SYNC_MASTER=DEV_MLB

CPU VR12.5 VCC Power Stage

SYNC_DATE=04/17/2014

CPUVR_ISNS1_P

CPUVR_ISUMP

PP5V_S0

CPUVR_ISNS1_N

DIDT=TRUE

CPUVR_UGATE2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

CPUVR_BOOT2

MIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

CPUVR_LGATE2 MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUVR_PHASE2

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

SWITCH_NODE=TRUE

CPUVR_PHASE1

PPVCC_S0_CPU_PH1

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.8V

CPUVR_BOOT1_RC

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT2_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPVCC_S0_CPU_PH2

CPUVR_BOOT1

MIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

CPUVR_LGATE1

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

CPUVR_UGATE1

MIN_NECK_WIDTH=0.2 MM

CPUVR_FCCM

CPUVR_PWM1

CPUVR_ISNS1_N

CPUVR_ISUMP

CPUVR_ISNS2_N

CPUVR_ISNS2_P

CPUVR_ISUMN

CPUVR_ISNS2_N

PP5V_S0

CPUVR_FCCM

CPUVR_PWM2

CPUVR_ISEN2

CPUVR_ISUMN

PPVCC_S0_CPU

CPUVR_ISEN1

PPBUS_S5_HS_COMPUTING_ISNS

<SCH_NUM>

73 OF 130

45 OF 75

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30 39

40 44 45 47 49

51 60

45 73

16 17 25 30 39 40 44 45 47 49 51 60

8

10 35 60

35

44 46 48 60

www.qdzbwx.com

WWW.AliSaler.Com

BG

TGR

TG

PGND

VIN

VSW

IN

NC NC NC NC

IN

OUT OUT

OUT

OUT OUT OUT

IN

NC

OUT

NC

IN

OUT

NC NC

IN

OUT OUT OUT

OUT OUT

OUT

NC

BI

IN

NC

OUT OUT

OUT

IN IN IN

IN

IN IN IN IN

NC

OUT

IN

NC

NC NC

NC

OUT

NC NC

IN IN IN IN

OUT

DPWROK

V1.05S

32KXTALOUT

DS3_VREN

BOOTSTRAP3

32KXTALIN

PCH32KHZCLK

EC32KHZCLK

1HZCLK

SH32KHZCLK

PGND3

GPIO2(SLP_S4*)

GPIO3(USB32_P0_PWREN_R)

V5_MODE V8_IMON

PGOOD2

LOWBATTSENSE

RADPNEG

RADPPOS

RBATTNEG

RBATTPOS

VDCSENSE

VREFBIAS

BATTID MBI

VPROGOTP

VINLDO3

VREF1.25V

V12_EN

VIN12

VREF

VOUT12

VIN LDO5V

SLAVEADDR

PWRBTNIN

V3.3DX_EN

CLOCK DATA

ACOK

VCCIN_PG

OVERTEMP

V2_MODE

V9_MODE

V4_MODE

VR_ON

V8_EN

V5_EN

BOOTSTRAP6

RDY

V2_EN

V4_EN

FB6

LX6

BOOTSTRAP7

FB7

VIN6

LX7

1.05A

VIN7

PGOOD5

PGOOD8

PGOOD4

PGOOD9

24MXTALIN

V3.3A_DSW

VBATTBKUP

24MXTALOUT

PCH24MHZCLK

SH8MHZCLK

V3.3A_RTC

ECCLK

ECCLKFRQ

ALL_SYS_PWRGD

SYS_PWROK

APWROK

AGND1

AGND2

AGND3

PGND12

DGND

PGND6

PGND7

PGND10

PGND11

RMON_GND

GND_K10

NC

GND_J10

GND_K8 GND_K9

GND_J8 GND_J9

GND_J7

GND_H10

GND_J6

GND_H9

GND_H8

GND_H7

GND_G10

GND_H6

GND_G9

GND_G8

GND_G7

GND_F10

GND_G6

GND_F7 GND_F8 GND_F9

GND_E10

GND_F6

GND_E9

GND_E8

GND_E7

GND_D7

EXT_TEMP_N

GPIO0(SATA_P0_PWR_EN)

GPIO1(V1.8U_EN)

EXT_CRITTEMP

EXT_TEMP_P

EXT_TEMPHOT

SYSTHERM3

SYSTHERM2

SYSTHERM1

SYSTHERM0

V8_SELECT

V8_MODE

V5_IMON

V4_IMON

V2_IMON

IMON_V9

VREF2.4V

ADC_EN

IMON_V10

VOUT11

FB11

IMON_CSP10 IMON_CSN10

DRVL10

VIN11

DDRID

CS10

VBST10 DRVH10

SW10

FB10

DDR_VTT_CTRL

VREG5

FB3

LX3

VIN3

V9_EN

GPIOVDD1

GPIOVDD2

V1.05M

V1.8S

V3.3M

V3.3S

ECVCC

BC_ACOK

VCCST_PWRGD

PCH_PWROK

RSMRST*_PWRGD

PMIC_INT*

SLP_S3* SLP_M*

SLP_S0*

EC_ONOFF*

PROCHOT*

EC_RST*

SLP_SUS*

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

V12 LDO (1.5V)

(RTC source)

(No coincell)

(24M unused)

(Float = 12 MHz)

(SH unused)

(DDR VTT LDO Off)

(From SMC)

(Float = 0x34/0x35)

- V11 LDO (V0.6Dx)

- V12 LDO (2.5V/1.5V)

- GPIOs

- Power Monitor Unit

- I2C

- 3V LDO

- 5V LDO

V10 (V1.2U VR)

- Power-up State Machine

- 32kHz / 24MHz

- V6 Converter (V3.3Dx_SSD)

- V3 Converter (V5Dx_WP)

- Emergency RESET Handler

- ADC

- Ref Sys

- EC RESET

- RTC Domain

- V7 Converter (V1.8U)

- Battery Detection

- Digital Block

- OTP

AGND_PMIC if not used

Alias sense pairs to

APN 152S1913

(OD)

BB: to 1.35M

(OD)

(SMC unused) (SH unused)

BB: to 12nF

(Cout)

f = ? kHz

(GND = 1.2Vout)

(24M unused)

4A max output

Vout = 1.2V

- Coin Cell Charger

TPS650811 (Walrus):

- V10 Controller (V1.2U)

- Interrupt Handler

(Cin)

(To PCH)

- AC/DC Detection

- Power Button

- Overtemp V12.6 Interface

APN 376S00012

(OD)

1/20W

201

MF

5%

10

R7460

12

5%

0

402

MF-LF 1/16W

R7425

12

Q3D

CRITICAL

CSD58889Q3D

Q7430

5

9

3

4

1

6 7 8

402

10% X5R

25V

0.1UF

C7425

12

1UH-20%-10.2A-0.014OHM

PIME052T-SM

CRITICAL

L7430

12

45UF

CRITICAL

20% 11V

CASED12-SM

POLY

C7430

1

2

13 31 52

13

31 33

75

13 51 52

13 33 46

32 46

16 31 33 46

13 46

13 16 31 46

8

16 17

48

31 48

52

48

31 32

64

12

13

48 64

48

31 34 48 72

52

48

64

201

MF

1% 1/20W

7.15K

R7430

1

2

48

46 48

48

59

52

13 15

31

46 52 52

48

PLACE_NEAR=U7400.D14:3mm

20% 16V

0603

X6S-CERM

10UF

C7400

1

2

1

402

5%

1/16W

MF-LF

R7400

12

X5R-CERM

0.1UF

10% 0201

PLACE_NEAR=U7400.F2:3mm

10V

C7401

1

2

20% 0402

PLACE_NEAR=U7400.C14:3mm

6.3V

10UF

CERM-X6S

C7402

1

2

PLACE_NEAR=U7400.A13:3mm

10UF

16V

X6S-CERM

20%

0603

C7405

1

2

PLACE_NEAR=U7400.B14:3mm

0402-1

25V X5R-CERM

20%

2.2UF

C7403

1

2

270UF

TANT

2V

20%

CRITICAL

CASE-B2-SM

C7440

1

2

270UF

TANT

2V

CRITICAL

20%

CASE-B2-SM

C7441

1

2

2.2UF

20%

0402-1

25V X5R-CERM

C7431

1

2

100KOHM

0201

NO_XNET_CONNECTION=TRUE

R7436

12

30.1K

1%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

R7440

12 1% MF

20K

201

1/20W

R7437

12

MF 201

1% 1/20W

84.5K

R7435

1

2

X5R

10%

0201

0.015UF

NO_XNET_CONNECTION=TRUE

6.3V

C7435

12

SM

XW7402

1

2

6.3V

10UF

20%

0402

CERM-X6S

C7410

1

2

0402

CERM-X6S

6.3V

10UF

20%

C7411

1

2

SM

XW7403

1

2

20% 0402-1

25V X5R-CERM

PLACE_NEAR=U7400.M1:3mm

2.2UF

C7406

1

2

31 33 46

1% 1/20W MF 201

1M

R7438

1

2

0201

1.24M

MF

1/20W

1%

R7439

1

2

31

0402

50V

10%

0.001UF

X7R-CERM

C7433

1

2

5% MF

201

1/20W

10K

R7450

1

2

5% MF

10K

1/20W

201

R7451

1

2

5%

201

MF

1/20W

10K

R7452

1

2

5% MF

201

10K

1/20W

R7453

1

2

MF

1/20W

201

10K

5%

R7454

1

2

1K

201

MF

5%

1/20W

R7455

1

2

17 64

PGOOD8:VREF3V3

MF

1/20W

5%

201

10K

R7456

1

2

0201

2.2UF

PLACE_NEAR=U7400.G2:3mm

X5R-CERM

6.3V

20%

C7404

1

2

CERM-X5R

0.47UF

10%

6.3V 0201

C7436

1

2

48

2.2UF

20% 25V X5R-CERM 0402-1

NOSTUFF

C7432

1

2

10UF

10V X5R-CERM

20%

0402-1

C7445

1

2

10V

X5R-CERM

20%

0402-1

10UF

C7444

1

2

46 48

64

46 48 64

46

48

64

46 48

64

1/20W

10K

5%

PGOOD8:SLP_S4

MF 201

R7457

1

2

52

SN650811

CRITICAL

BGA

U7400

L14

L12

P10 N10

M14

N14

D13

K5

F13

A2

H2

J11

M5

L10

B13

K14

A4

P3

P2

K2

N2

H5

J3

N7

A8

H1

N1

E6

M13

D12

C10

N9

L11

B12

D4

H4

H3

E4

L2

M11

F14

A10

P9

D7

E10

E7 E8 E9

F10

F6 F7 F8 F9

G10

G6 G7 G8 G9

H10

H6 H7 H8 H9

J10

J6 J7 J8 J9

K10

K8 K9

D9 K7 B8 C8

B11

D8

C1

B1

A3

C4

B14

L9

G12 G13 G14

A7 B7 C7

M6 N6 P6

P5

A1 A14 P1 P14

J5

M10

L13

H11

J1

N11

P11

N5

E12

E13

E14

A9B9C9M8N8

P8

K3

M7

H13

C6

B6

B10

M2

C13

F1

G1

D1

E1

A6

B4

D5

M12

M9

J4

L7

K6

H12

D10

L1

G11

F4 D3 E3 F3

G3

N3J2L3

F5

B2

E5

P7

K13

D6

L4

M3

F12

C2

C11

L5

D2

L6

C12

B3

D11 G5

H14

E11

K12

K1

K4

F11

G4

A13

N13 P13

A12

J12 J13 J14

A5 B5 C5

M4 N4 P4

D14

N12 P12

A11

K11

L8

C14

F2

G2

E2

M1

X7R-CERM

0.001UF

10% 50V

0402

C7446

1

2

PLACE_NEAR=C7440.1:1mm

SM

XW7401

1

2

SYNC_DATE=04/04/2014

LPDDR3 Supply

SYNC_MASTER=J92_DEVMLB

PP3V3_S5

PM_DSW_PWRGD

PP1V05_S0

SYSCLK_CLK32K_PMIC

P3V3S3_EN

PPBUS_G3H

P5VS0_BOOT

NC_PMIC_CLK32K_XTALIN PCH_CLK32K_PMIC

PM_SLP_S4_L P5VS0_EN

P3V3_S0_MODE

AGND_PMIC

P5V_S4_PGOOD

PPVBAT_G3H_CONN

AGND_PMIC

PPBUS_G3H

TP_PMIC_SYSTHERM_BIAS

AGND_PMIC

PP5V_G3H_LDO

PPBUS_G3H_PMIC_RC

PMIC_VREF1V25

P1V5S0_EN

PP1V8_S3

PMIC_VREF3V3

PP1V5_S0

PPBUS_G3H

PMIC_PWRBTN_L

P3V3S0_EN

SMBUS_SMC_2_G3_SCL SMBUS_SMC_2_G3_SDA

TP_CPUVR_OVERTEMP

P5V_S4_MODE

P1V05_SUS_MODE

P3V3_S5_MODE

PMIC_V8_EN

P3V3_S0_EN

P3V3SSD_BOOT

PMIC2_READY

P5V_S4_EN

P3V3_S5_EN

P3V3_SSD_REG_FB

P3V3SSD_PHASE

P1V8S3_BOOT

P1V8_S3_REG_FB

PPBUS_G3H

P1V8S3_PHASE

PPBUS_G3H

PP1V05_SUS

P3V3_S0_PGOOD

P1V1_S0_DLPN_PGOOD

S5_PWRGD

P1V05_SUS_PGOOD

AGND_PMIC

PP3V3_S5

TP_PMIC_VBATTBKUP

PPVRTC_G3H

ALL_SYS_PWRGD

PM_PCH_SYS_PWROK

PM_PCH_APWROK

VOLTAGE=0V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.6 MM

GND_RMON_PMIC1

PMIC2_THERMN

SAK_SSD_P3V3_NAND_EN

P1V8S3_EN

PMIC2_CRITTEMP

PMIC2_THERMP

PMIC2_PROCHOT

TP_PMIC_SYSTHERM3

TP_PMIC_SYSTHERM2

TP_PMIC_SYSTHERM1

TP_PMIC_SYSTHERM0

P3V3_S0_IMON

P3V3_S5_IMON

P5V_S4_IMON

P1V05_SUS_IMON

PMIC_VREF2V4

PMIC_ADC_EN

SMC_P1V2S3_ISENSE

ISNS_1V2_S3_P ISNS_1V2_S3_N

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

DDRREG_DRVL

GATE_NODE=TRUE

DDR_REG_ILIM

DDRREG_VBST

MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVH

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

DDRREG_LL

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_VDDQSNS

PP5V_G3H_LDO

P5V_S0_REG_FB

P5VS0_PHASE

P1V05_SUS_EN

PP1V8_S3

PP3V3_S0

PP3V3_SUS

CPU_VCCST_PWRGD

PM_PCH_PWROK

PMIC_RSMRST_L

SMC_PMIC_INT_L

PM_SLP_S3_L PM_SLP_A_L

PM_SLP_S0_L

TP_PMIC_PROCHOT_L

PM_SLP_SUS_L

PMIC_RSMRST_L

PP1V8_S3

PP3V3_S0

PPBUS_S5_HS_COMPUTING_ISNS

PM_SLP_S4_L

P1V1_S0_DLPN_PGOOD

PP5V_G3H_LDO

PP3V3_S5

PM_PCH_SYS_PWROK

PM_PCH_PWROK

ISNS_1V2_S3_RC

ALL_SYS_PWRGD

PM_PCH_APWROK

P1V05_SUS_IMON

GND_RMON_PMIC1

ISNS_1V2_S3_NTC

PMIC_VREF3V3

PM_DSW_PWRGD

PP3V3_SUS

PDDR_S3_PHASE_XW

SMC_P1V2S3_ISENSE

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST_RC

MIN_LINE_WIDTH=0.6 MM DIDT=TRUE

MIN_NECK_WIDTH=0.1 MM

PDDR_S3_PHASE

AGND_PMIC

VOLTAGE=8.7V

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

PPBUS_G3H_PMIC_RC

PPBUS_G3H

MIN_NECK_WIDTH=0.1 mm

PMIC_VREF2V4

MIN_LINE_WIDTH=0.2 mm

PMIC_VREF3V3

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

PMIC_VREF1V25

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

PP1V5_S0

PP1V2_S3

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_VDDQSNS_R

<SCH_NUM>

74 OF 130

46 OF 75

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46 60

30 35 43 46 47 48 49 50 60

47

50

30 35

43

46

47

48

49

50

60

50

30 35

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46

47

48

49

50

60

8

11 12 16

48

51 60

46 64

46 48 64

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11 13 15

16 17 22 33

37 46 47 51 59 60 73 75 8

12 13 60

46

73

46

60

47

20 21 46 50 52 59 60

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11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

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11 14 15 18

27 28 29 46 51 60

32 46

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15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

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13 15 31 46 52

46 64

46 60

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11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

13 16 31 46

13 46

16 31 33 46

13 46

46 48

46

46 48

13 33 46

8

11 14 15

18

27 28 29 46 51

60

31 33 46

46 48 64

46 30 35 43 46 47 48 49 50 60

46

46 48

46

8

11 17 40 46

60

8

10 19 20 21

52 59

60 69

www.qdzbwx.com

WWW.AliSaler.Com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

5V S0 - 2.9A

V2

V4

3.3V S0 - 1A

V5

3.3V S5 - 1.5A

3.3V SSD - 2A

V5

V6

Vout = 3.3V

V2

V6 V3 V4

F = ??? KHZ

Vout = 5.0V

5V S4 - 2.7A

V3

X5R-CERM

25V

0402-1

20%

2.2UF

C7541

1

2

0402-1

2.2UF

X5R-CERM

25V

20%

C7581

1

2

16V

PLACE_NEAR=L7560.2:1.5mm

X7R-1

1000PF

10%

0201

C7572

1

2

10% 16V X7R-1

1000PF

0201

C7583

1

2

1000PF

0201

10% 16V X7R-1

C7570

1

2

16V

10%

1000PF

0201

PLACE_NEAR=L7520.1:1.5mm

X7R-1

C7571

1

2

CRITICAL

2.2UH-20%-4.8A-0.105OHM

SM-PIME041B

L7520

12

20%

45UF

11V

POLY

CASED12-SM

CRITICAL

C7540

1

2

0805

POLY-TANT

6.3V

47UF

20%

C7553

1

2

0805

POLY-TANT

6.3V

47UF

20%

C7552

1

2

47UF

0805

6.3V POLY-TANT

20%

C7599

1

2

6.3V

47UF

20%

0805

POLY-TANT

C7597

1

2

47UF

POLY-TANT

6.3V

20%

0805

C7598

1

2

6.3V

20%

0805

POLY-TANT

47UF

C7596

1

2

0805

POLY-TANT

6.3V

47UF

20%

C7591

1

2

0805

POLY-TANT

6.3V

47UF

20%

C7593

1

2

20%

45UF

POLY

CASED12-SM

11V

CRITICAL

C7580

1

2

10%

4700PF

X7R 201

10V

C7560

1

2

10V

4700PF

X7R

10%

201

C7561

1

2

10V X7R

4700PF

10%

201

C7562

1

2

4700PF

10V X7R

10%

201

C7512

1

2

X7R

4700PF

10%

201

10V

C7520

1

2

20%

6.3V

POLY-TANT

0805

47UF

C7513

1

2

20%

47UF

6.3V 0805

POLY-TANT

C7510

1

2

CRITICAL

2.2UH-20%-4.8A-0.105OHM

SM-PIME041B

L7510

12

PIFE32251B

2.2UH-2.2A

CRITICAL

L7562

12

CRITICAL

2.2UH-2.2A

PIFE32251B

L7560

12

1000PF

X7R-1

10% 16V

0201

C7573

1

2

25V

0402-1

2.2UF

20%

X5R-CERM

C7542

1

2

0201

1000PF

10% X7R-1

16V

C7584

1

2

0402-1

25V X5R-CERM

2.2UF

20%

C7582

1

2

0201

X7R-1

1000PF

10% 16V

C7586

1

2

20%

2.2UF

0402-1

25V X5R-CERM

C7585

1

2

201

5% 1/20W MF

10

R7520

1

2

201

10

5% 1/20W MF

R7510

1

2

1/20W

10

5%

201

MF

R7562

1

2

MF

1/20W

5%

201

10

R7561

1

2

1/20W

5%

10

MF

201

R7560

1

2

2.2UF-20%-3.8A-0.083OHM

PIME041B-SM

CRITICAL

L7561

12

20%

6.3V

47UF

POLY-TANT 0805

C7567

1

2

POLY-TANT

20%

47UF

6.3V 0805

C7566

1

2

X5R-CERM 0402-1

20%

2.2UF

25V

NOSTUFF

C7587

1

2

X5R

25V

2.2UF

20%

0402-1

C7594

1

2

X5R

25V

2.2UF

20%

0402-1

C7592

1

2

20%

2.2UF

X5R-CERM

25V

0402-1

C7551

1

2

25V

2.2UF

20%

0402-1

X5R-CERM

C7550

1

2

25V X5R-CERM

2.2UF

20%

0402-1

C7543

1

2

20%

2.2UF

X5R-CERM

25V

NOSTUFF

0402-1

C7588

1

2

20%

2.2UF

X5R-CERM

25V

0402-1

C7589

1

2

X5R-CERM

25V

20%

0402-1

2.2UF

C7544

1

2

X5R-CERM

25V

20%

2.2UF

0402-1

C7511

1

2

2.2UF

20% 25V

X5R-CERM

0402-1

C7514

1

2

25V

2.2UF

20%

0402-1

X5R-CERM

NOSTUFF

C7569

1

2

25V X5R-CERM

2.2UF

20%

0402-1

C7595

1

2

25V X5R-CERM

2.2UF

20%

0402-1

C7568

1

2

25V X5R-CERM

2.2UF

20%

0402-1

C7590

1

2

0201

5% CERM

12PF

25V

C7563

1

2

25V

12PF

CERM

5%

0201

NOSTUFF

C7564

1

2

SYNC_DATE=04/17/2014

SYNC_MASTER=DEV_MLB

5V & 3.3V Power Supplies

MIN_NECK_WIDTH=0.1 mm

P3V3_S0_REG_FB

MIN_LINE_WIDTH=0.2 mm

P5VS0_BOOT

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P5V_S0_REG_FB

PP5V_S0

DIDT=TRUE

P5VS0_PHASE

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P5VS4_PHASE

PP5V_S4

MIN_LINE_WIDTH=0.2 mm

P5V_S4_REG_FB

MIN_NECK_WIDTH=0.1 mm

PP3V3_S5

P3V3SSD_PHASE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P3V3SSD_BOOT

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P3V3S5_BOOT

P3V3S5_PHASE

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

DIDT=TRUE

P3V3_S5_REG_FB

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P3V3S0_BOOT

P3V3S0_PHASE

DIDT=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P3V3_SSD_REG_FB

PP3V3_S0

PP3V3_S0SW_SSD

P5VS4_BOOT

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

PPBUS_G3H

47 OF 75

<SCH_NUM>

75 OF 130

48

46

16 17 25

30 39 40 44 45 49 51

60

46

48

30 38 53 60 75

48

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11 13 15

16 17 22 33 37 46 51

59 60 73 75

46

48

46

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 53 60

73 75

50 58 59 60

48

30 35 43 46 48 49 50 60

WWW.AliSaler.Com

BG

TGR

TG

PGND

VIN

VSW

IN

OUT

OUT OUT

IN IN OUT OUT

IN

OUT

IN

OUT

OUT OUT

IN

IN BI

IN

NC

NC NC NC

NC NC

NC

BOOTSTRAP5

BOOTSTRAP4

BOOTSTRAP2

BOOTSTRAP8

VIN2 VIN2

PGND2

LX2

PGND2

FB2

VOUT2

FB2

VIN4

PGND4

VIN4

LX4 LX4

VIN5

PGND4

FB4

VOUT4

VIN5

LX5

LX5 PGND5 PGND5

VIN8

VOUT5

FB5

VIN8

LX8

LX8 PGND8 PGND8

FB8

VOUT8

VBST9

SW9

ISP9 ISN9

DRVL9 PGND9

DRVH9

FB9

V4_IMON

PGOOD4

V5_EN V5_MODE PGOOD5 V5_IMON

V8_EN V8_MODE

V8_IMON

PGOOD8

V8SEL

V9_MODE

V9_EN

V9_ULQ

V9_IMON

PGOOD9

ILIMSET9

V4_MODE

V4_EN

V2_IMON

PGOOD2

V2_MODE

V2_EN

LX2

V2-V5A_DS3

V4-V3.3A-DSW

V5-V3.3DX

V8-V1.5S

V9-V1.05A

SYM 1 OF 2

VREF1.25V

VLDO3.3V

VINLDO3.3V

VIN

VCTRL0

AGND

VCTRL

AGND

GND

RDY

HOT

VLDO3.3V_EN

VDDIO VDDIO

TN

TP

VCTRL2

VIN5V

VIN3.3VA

LEDDRV2

LEDDRV1

SCL SDA

LEDDRV3 LEDDRV4

SLAVEADDR

CRITTEMP

IMON_EN

DEVICE CONTROL

SYM 2 OF 2

INTERNAL BIASING

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TPS650801 (Dolphin):

(Float = 0x34/0x35)

- 3V LDO

- Ref Sys

- V9 Controller (V1.05A)

- I2C

- Digital Block

- 5V LDO

- OTP

- V5 Converter (V3.3Dx)

Vout = 1.05V 5A Max Output f = ? kHz

- V4 Converter (V3.3A_DSW)

- V2 Converter (V5A_DS3)

- LED Drivers

- V8 Converter (V1.5S - UNUSED)

APN 152S1913

BB: to 12nF

V9 (V1.05A VR)

APN 376S00012

Q3D

CSD58889Q3D

CRITICAL

Q7630

5

9

3

4

1

6 7 8

CASED12-SM

CRITICAL

45UF

11V

POLY

20%

C7620

1

2

46

46 64

46

31 46

52

46

31 34 46 72

33

201

1%

1/20W

MF

8.66K

R7635

1

2

10% 10V

0.1UF

0201

X5R-CERM

PLACE_NEAR=U7600.A11:3mm

C7601

1

2

2.2UF

PLACE_NEAR=U7600.D9:3mm

6.3V 0201

X5R-CERM

20%

C7606

1

2

PLACE_NEAR=U7600.K1:3mm

1.0UF

20% X5R

6.3V

0201-1

C7602

1

2

402

MF-LF

1/16W

5%

10

R7602

1

2

PLACE_NEAR=U7600.K7:3mm

10UF

CERM-X6S

6.3V

20%

0402

C7603

1

2

PLACE_NEAR=U7600.J2:3mm

0201

10V

20%

1UF

X5R

C7604

1

2

PLACE_NEAR=U7600.G3:3mm

0201

10V

20%

1UF

X5R

C7605

1

2

CASE-B2-SM

20%

CRITICAL

2V TANT

270UF

C7648

1

2

CASE-B2-SM

CRITICAL

20%

2V

TANT

270UF

C7649

1

2

201

1/20W

20K

MF

1%

R7637

12

NO_XNET_CONNECTION=TRUE

100KOHM

0201

R7636

12

NO_XNET_CONNECTION=TRUE

31.6K

201

MF

1%

1/20W

R7640

12

201

121K

1/20W

1% MF

R7634

1

2

NO_XNET_CONNECTION=TRUE

10% X5R

0201

6.3V

0.015UF

C7634

12

SM

XW7600

1

2

SM

XW7601

1

2

PLACE_NEAR=U7600.B11:3mm

20%

10UF

0402

CERM-X6S

6.3V

C7607

1

2

0201

0.47UF

CERM-X5R

6.3V

10%

C7636

1

2

SM

XW7699

12

PLACE_NEAR=U7600.L9:3mm

20%

2.2UF

X5R-CERM

25V 0402-1

C7600

1

2

0402

20%

6.3V CERM-X6S

10UF

C7608

1

2

0402-1

20%

2.2UF

X5R-CERM

25V

C7624

1

2

X5R-CERM

20%

0402-1

10V

10UF

C7626

1

2

20% X5R-CERM

0402-1

10V

10UF

C7623

1

2

25V

12PF

CERM

5%

0201

C7647

1

2

SN650801

BGA

CRITICAL

U7600

L8

D11

H1

B6

B5 A2

L1 K2

J10

A1 B2

C9

C6

B3

C5

C4

L4 L5

G11 H11

D1 E1

A7 A8

L2 L3

J11 K11

B1 C1

A9 A10

A3

J4

H9

D3

D7

G2

A4

K5

C10

J5

G10

E9

G9

E3

C11

E2

B7

D10

C8 D2

B8

D4

C7

F2

B4

L6 L7

E11 F11

F1 G1

A5 A6

K3

J9

C2

B9

SN650801

BGA

CRITICAL

U7600

J1 K10 L11

H10

F9 H2

F4 F5 F6 F7 F8 G4 G5 G6 G7 G8

L10

H5 H6 H7

D5 D6 E4 E5 E6 E7 E8

K4

F3

K9 J7 K8 J6

H3

J8 H8 J3

F10

E10 K7

J2

G3

A11 B10

L9

K1

K6

D8

B11

H4

D9

0402

PLACE_NEAR=Q7630.1:1.5mm

CERM

5%

1000PF

25V

C7622

1

2

NOSTUFF

25V X5R-CERM

2.2UF

20%

0402-1

C7625

1

2

PLACE_NEAR=C7648.1:1mm

SM

XW7610

1

2

MF

201

5%

10

1/20W

R7641

12

0

5%

1/16W

MF-LF

402

R7630

1

2

0402

X7R-CERM

16V

10%

0.1UF

C7630

1

2

PIME052T-SM

1UH-20%-10.2A-0.014OHM

CRITICAL

L7630

12

SYNC_MASTER=J92_DEVMLB

1.05V S0 Power Supply

SYNC_DATE=04/04/2014

PMIC2_VREF1V25

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PMIC_VREF3V3

PPBUS_G3H

MIN_LINE_WIDTH=0.5 mm

PMIC2_VCTRL02

MIN_NECK_WIDTH=0.2 mm

AGND_PMIC

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PMIC2_VCTRL

PMIC2_READY

PMIC2_PROCHOT

AGND_PMIC

PMIC_VREF3V3

PMIC2_THERMN

PMIC2_THERMP

PMIC2_VCTRL02

PMIC2_VCTRL

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PMIC_VREF3V3_RC

TP_PMIC_LEDDRV2

TP_PMIC_LEDDRV1

SMBUS_SMC_2_G3_SCL SMBUS_SMC_2_G3_SDA

TP_PMIC_LEDDRV3 TP_PMIC_LEDDRV4

PMIC2_CRITTEMP

PMIC_ADC_EN

P3V3S0_BOOT

P3V3S5_BOOT

P5VS4_BOOT

PPBUS_G3H

P5VS4_PHASE

P5V_S4_REG_FB

PPBUS_G3H

P3V3S5_PHASE

PPBUS_G3H

P3V3_S5_REG_FB

P3V3S0_PHASE

PPBUS_G3H

P3V3_S0_REG_FB

MIN_LINE_WIDTH=0.5 mm

P1V05SUS_VBST

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05SUS_LL

ISNS_1V05_SUS_P ISNS_1V05_SUS_N

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P1V05SUS_DRVL

P1V05SUS_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

P1V05SUS_VDDQSNS

P3V3_S5_IMON

S5_PWRGD

P3V3_S0_EN P3V3_S0_MODE P3V3_S0_PGOOD P3V3_S0_IMON

MIN_NECK_WIDTH=0.095 mm

MIN_LINE_WIDTH=0.5 mm

AGND_PMIC

VOLTAGE=0V

P1V05_SUS_MODE

P1V05_SUS_EN

P1V05_ULQ_L

P1V05_SUS_IMON

P1V05_SUS_PGOOD

P1V05_SUS_ILIM

P3V3_S5_MODE

P3V3_S5_EN

P5V_S4_IMON

P5V_S4_PGOOD

P5V_S4_MODE

P5V_S4_EN

P1V05SUS_VDDQSNS_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

P1V05_SUS_PHASE_XW

AGND_PMIC

ISNS_1V05_SUS_NTC

ISNS_1V05_SUS_RC

P1V05_SUS_PHASE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P1V05SUS_BOOT_RC

MIN_LINE_WIDTH=0.5 mm

PP1V05_SUS

PPBUS_S5_HS_COMPUTING_ISNS

<SCH_NUM>

76 OF 130

48 OF 75

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46 47 48 49 50 60

48

46

48

64

48

46 48 64

46 48

48

47

30 35 43 46 47 48 49 50 60

47

30 35 43 46 47 48 49 50 60

47

30 35 43 46 47 48 49 50 60

47

30 35 43 46 47 48 49 50 60

47

73

64

46 48 64

8

11 12

16 46 51

60

35

44 45 46 60

WWW.AliSaler.Com

IN

OUT

IN

BI

NC NC

NC

SW

VDDD

VDDA

GD

SW

VSENSE_N

SD

GND_SW2

GNDD

GNDA

THRM

FB

SENSE_OUT

PWM_KEYB

SCL SDA

KEYB2

KEYB1

FB2

SW2

GND_SW

ISET_KEYB

EN

VSENSE_P

PAD

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(PPBUS_S0_BKLT_PWR_F)

(IPU)

(PPBUS_S0_BKLT_PWR_R)

(IPU)

C7715, C7716 SHOULD BE PLACED MIRRORED C7718, C7719 SHOULD BE PLACED MIRRORED

353S4292

BKLT:PROD - Stuffs 0 ohm series R for production

BOM options provided by this page:

Power aliases required by this page:

152S1893

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds

- =PP5V_S0_KBDLED (5V Keyboard Backlight Input)

- =PP5V_S0_BKLTCTRL (5V Backlight Driver Input)

- =PPVIN_S0_LCDBKLT (6-8.6V LCD Backlight Input)

Page Notes

603-HF

3AMP-32V-467

CRITICAL

F7700

12

CRITICAL

PIME061H-SM

15UH-20%-1.8A-0.258OHM

L7710

12

80.6K

1/16W MF-LF

1%

402

R7701

1

2

0201

16V X7R-1

1000PF

10%

C7700

1

2

402

1/16W

63.4K

1% MF-LF

R7702

1

2

SSOT6-HF

CRITICAL

FDC638APZ_SBMS001

Q7706

1

2

5

6

3

4

MF

1/20W

0201

0

5%

R7742

12

X5R

10V

402-1

1UF

10%

C7740

1

2

1UF

10V

10% 402-1

X5R

C7741

1

2

201

1M

MF

1/20W

5%

R7740

1

2

SM

XW7700

12

402

X5R

25V

0.1UF

10%

C7712

1

2

13

0.001UF

10%

402

CERM

50V

NOSTUFF

C7701

1

2

25V

4.7UF

10% X6S-CERM

0603-1

C7710

1

2

4.7UF

X6S-CERM

10%

0603-1

25V

C7711

1

2

25V

33PF

0201

NPO-C0G

NO STUFF

5%

C7742

1

2

73

PLACE_NEAR=L7710.2:3MM

CRITICAL

RB160M-60G

SOD-123

D7701

AK

0.001UF

402

10% 50V CERM

C7717

1

2

X5R

50V

CRITICAL

2.2UF

10%

0603

C7715

1

2

53

SM

XW7701

1

2

1.8K

MF

1/20W 201

5%

R7761

1

2

1.8K

MF

1/20W

201

5%

R7760

1

2

MF

1/20W

0201

0

5%

R7762

12

MF

1/20W

0201

0

5%

R7763

12

10K

MF

1/20W

201

5%

R7765

1

2

MF-LF

402

1/16W

0

5%

R7710

12

MF-LF

1/16W

402

0

5%

R7711

12

X5R

50V

10%

CRITICAL

2.2UF

0603

C7716

1

2

X5R

50V

10%

2.2UF

CRITICAL

0603

C7718

1

2

X5R

CRITICAL

2.2UF

10% 50V

0603

C7719

1

2

LLP

LP8548B1SQ-11

CRITICAL

U7701

17

21

8

4

7

232422

3

20

13 14

12

15

11

16

19

6

1

2

25

18

5

9

10

X5R

CRITICAL

50V

10%

2.2UF

0603

C7729

1

2

X5R

CRITICAL

2.2UF

10% 50V

0603

C7728

1

2

X5R

CRITICAL

2.2UF

10% 50V

0603

C7726

1

2

X5R

CRITICAL

2.2UF

10% 50V

0603

C7725

1

2

1W

1%

0.025

MTL-FILM

0612

CRITICAL

R7700

21 43

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=10/01/2013

LCD Backlight Driver

PPVOUT_S0_LCDBKLT

MIN_NECK_WIDTH=0.2 MM VOLTAGE=32V

MIN_LINE_WIDTH=0.5 MM

BKL_FB

BKLT_SDA_R

BKLT_SCL_R

PWM_KEYB

BKLT_EN_R

BKLT_SENSE_OUT

BKLT_SD

LCDBKLT_EN_L

PPBUS_G3H

EDP_BKLT_EN

GND_BKLT_SGND

PP5V_S0

I2C_BKLT_SCL

I2C_BKLT_SDA

GND_BKLT_SGND

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

PPLCDBKLT_VDDA

MIN_LINE_WIDTH=2 MM VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=12.6V

MIN_NECK_WIDTH=0.2 MM

PPBUS_SW_BKL

DIDT=TRUE

VOLTAGE=45V SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPBUS_S0_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=2 MM

PPLCDBKLT_VDDD

VOLTAGE=5V

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=2 MM

PPBUS_S0_LCDBKLT_FUSED

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=12.6V

PPBUS_SW_LCDBKLT_PWR

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

<SCH_NUM>

77 OF 130

49 OF 75

53

30 35 43

46 47 48 50

60

49

16 17 25 30 39 40 44 45 47 49 51 60

49

WWW.AliSaler.Com

IN

PAD

PVIN

VOS

FB

PG

THRM

AGND

PGND

AVIN

DEF

SS/TR

SW SW SW

EN

FSW

EN

VIN

GND

VOUT

IN

PAD

PVIN

VOS

FB

PG

THRM

AGND

PGND

AVIN

DEF

SS/TR

SW SW SW

EN

FSW

IN

VER 3

D

SG

VER 3

D

SG

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

ISET

ON

VOUT

OCFLAGB

VIN

GND

OUT

IN

G

SYM_VER_1

D

S

ISET

ON

VOUT

OCFLAGB

VIN

GND

IN

ISET

ON

VOUT

OCFLAGB

VIN

GND

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

f = 1.25 MHZ

VCONN Current Limiters

Pull-up in U4600

ILIM(max) = 1910 mA

APN 152S1888

353S4283

Vout = 0.8V * (1 + Ra / Rb)

1.05V S4 Switcher

2.5V SSD LDO

Vout = 1.051V 150mA Max Output

APN 152S1888

Freq = ? MHz

Max Current =

Vout = 1.794V

Max Current = 0.06A

Vnominal - 10%

1.1v OUTPUT VOLTAGE

Vout = 0.8 * (<Ra> + <Rb>)/<Rb> = 1.1V

1.1V SSD VR

<Ra>

<Rb>

F=1.25MHZ

Vnominal + 10%

Reserved

Vnominal

0

1

0 1 0

Vout = 1.1V

Freq = ? MHz

<Ra>

<Rb>

CORE_SHMOO<0>CORE_SHMOO<1>

<Rb>

Vout = 2.5V

f = 1.6MHZ

<Ra>

ILIM(min) = 1530 mA

Pull-up in U4600

ILIM(nom) = 335 mA ILIM(max) = 368.5 mA

ILIM(min) = 301.5 mA

ILIM(nom) = 1700 mA

VBUS Current Limiter/OVP IC

Max Current = 2.4A

1.8A Max Output

V7 (V1.8U VR)

Pull-up in U4600

Vout = 5.105V (5.337V max)

Vout = 0.8 * (1 + <Ra>/<Rb>) = 5.105V

E85 VBUS/VCONN 5V VR

10V

10%

X7R 201

4700PF

C7823

1

2

6.3V

POLY-TANT

20%

0805

47UF

CRITICAL

C7822

1

2

2.2UH-2.2A

PIFE32251B

CRITICAL

L7820

12

CASED12-SM

CRITICAL

45UF

20% 11V

POLY

C7890

1

2

59

BYPASS=U7870.B2::1mm

CERM

10%

6.3V

402

1UF

C7870

1

2

BYPASS=U7870.B2::1mm

1UF

402

6.3V CERM

10%

C7871

1

2

402

X5R

6.3V

2.2UF

10%

C7872

1

2

201

10K

1/20W

5% MF

R7891

1

2

20%

2.2UF

0402-1

X5R-CERM

25V

C7821

1

2

10% 16V

1000PF

X7R-1 0201

C7824

1

2

5%

10

MF

201

1/20W

R7820

1

2

10

5%

201

MF

1/20W

R7890

1

2

0402-1

25V X5R-CERM

2.2UF

20%

C7894

1

2

PIME041B

1.5UF-20%-4.9A-0.058OHM

CRITICAL

L7890

12

10

5% 1/20W MF 201

R7887

1

2

0201

10% 16V X5R-CERM

0.1UF

C7887

1

2

59

4700PF

10%

X7R 201

10V

C7883

1

2

MF

201

1%

42.2K

1/20W

R7892

1

2

1/20W

MF

1%

201

162K

R7893

1

2

54

6.3V

CRITICAL

0805

47UF

20%

POLY-TANT

C7827

1

2

0805

CRITICAL

20%

6.3V

47UF

POLY-TANT

C7826

1

2

QFN

TPS62130ARGT

CRITICAL

U7890

6

10

8

13

5

7

4

15

16

11

12

9

1 2 3

17

14

1/20W

201

MF

1%

357K

R7894

1

2

1/20W

1%

201

MF

357K

R7895

1

2

1/20W MF

5%

1K

201

R7896

1

2

10K

MF

5% 1/20W

201

R7897

1

2

SM

XW7890

12

20%

CRITICAL

2.0V POLY-TANT

330UF

CASE-B2-SM1

C7896

1

2

6.3V POLY-TANT

CRITICAL

47UF

0805

20%

C7891

1

2

0402-1

25V

2.2UF

X5R-CERM

20%

C7892

1

2

TLV70525PYFP

WCSP

CRITICAL

U7870

A2

A1

B2 B1

20% 25V

2.2UF

X5R-CERM 0402-1

C7820

1

2

X5R-CERM

0402-1

2.2UF

25V

20%

C7828

1

2

0402-1

20% 25V

2.2UF

X5R-CERM

C7825

1

2

0402-1

25V

2.2UF

X5R-CERM

20%

C7893

1

2

20%

CRITICAL

2.0V POLY-TANT

330UF

CASE-B2-SM1

C7895

1

2

16V X5R-CERM

10%

0201

0.1UF

C7847

1

2

SM

XW7800

12

CRITICAL

20%

2.2UF

0402-1

25V X5R-CERM

C7850

1

2

X5R-CERM

CRITICAL

20%

0402-1

2.2UF

25V

C7848

1

2

5%

MF 201

10

1/20W

R7847

2

1

28

CRITICAL

QFN

TPS62130ARGT

U7850

6

10

8

13

5

7

4

15

16

11

12

9

1 2

3

17

14

10% 10V

201

X7R

4700PF

C7853

1

2

MF

21K

201

1%

1/20W

R7851

1

2

201

MF

1%

1/20W

113K

R7850

1

2

1/20W

201

MF

5%

10

R7853

1

2

20%

6.3V

0805

POLY-TANT

47UF

CRITICAL

C7851

1

2

47UF

CRITICAL

0805

20%

6.3V POLY-TANT

C7852

1

2

X5R-CERM

20% 25V

0402-1

2.2UF

CRITICAL

C7849

1

2

X5R-CERM 0402-1

CRITICAL

25V

20%

2.2UF

C7854

1

2

PIFE32251B

2.2UH-2.2A

CRITICAL

L7850

12

MF

5%

201

10K

1/20W

R7856

1

2

CASED12-SM

45UF

11V

POLY

20%

CRITICAL

C7846

1

2

28

DMN5L06VK-7

SOT563

Q7890

6

2

1

SOT563

DMN5L06VK-7

Q7890

3

5

4

CRITICAL

POLY-TANT 0805

6.3V

47UF

20%

C7855

1

2

6.3V

20%

0805

47UF

POLY-TANT

CRITICAL

C7856

1

2

27 28 29

62 64

20% 10V

0402-4

CRITICAL

X5R-CERM

10UF

C7830

1

2

ISL8009B

DFN

CRITICAL

U7830

2

7

8

3

54

9

6

1

X5R-CERM

0402-4

10V

10UF

20%

CRITICAL

C7831

1

2

1/20W MF

1%

201

150K

R7833

1

2

0201

5% 50V C0G

22PF

C7832

1

2

PIFE20161T-SM

2.2UH-1.7A-0.197OHM

CRITICAL

L7830

12

47K

1/20W MF

1%

201

R7832

1

2

1/20W MF

10

5%

201

R7831

1

2

0402-4

20%

X5R-CERM

10V

10UF

CRITICAL

C7836

1

2

CRITICAL

10V

10UF

20% 0402-4

X5R-CERM

C7835

1

2

201

1/20W

MF

1%

634

R7886

1

2

10K

5% MF

1/20W

201

R7836

1

2

POLY-TANT 0805

47UF

20%

6.3V

CRITICAL

C7857

1

2

CSP

FPF2495UCX

CRITICAL

U7880

A2B2

C2

C1

C3

A1

B1

A3 B3

28

DFN1006H4-3

DMN32D2LFB4

NO STUFF

Q7850

3

1

2

100

5%

1/16W

402

NO STUFF

MF-LF

R7857

1

2

CRITICAL

CSP

FPF2495UCX

U7860

A2B2

C2

C1

C3

A1

B1

A3 B3

29 64

201

1/20W MF

1%

3.09K

R7865

1

2

FPF2495UCX

CSP

CRITICAL

U7865

A2B2

C2

C1

C3

A1

B1

A3 B3

29 64

1% MF

1/20W 201

3.09K

R7866

1

2

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=04/04/2014

Misc Power Supplies

VBUSFET_EN

P5V1R3V4_AGND

P5VOUT_DISCHARGE

P1V1_SSD_REG_FB

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.2 MM

PPBUS_G3H

P5VOUT_SS

PP5V1_S4SW

P5VOUT_PGOOD

P5VOUT_FB

P5VOUT_VOS

VBUSFET_ILIM

PP5V1_S4SW

BBPD_VCONN2_EN

PP5V1_S4SW

P5VOUT_PHASE

DIDT=TRUE

P1V05S4SW_FB_R

P1V8S3_BOOT

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

PPBUS_G3H

PP2V5_S0SW_SSD

PPBUS_G3H

P1V1SSD_SS

SAK_SSD_PP1V1_EN

P1V1SSD_PGOOD

PP1V8_S0SW_SSD_COLD

PVIN_S0_P1V1SSD_RC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

P1V1SSD_VOS

SSD_GPIO2_L SSD_GPIO1_L

SSD_CORE_SHMOO<0>

MIN_NECK_WIDTH=0.2 mm

P1V05S4SW_SW

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.4 mm

SAK_SSD_P2V5LDO_P3V3S1X_EN

PP3V3_S0SW_SSD

SSD_CORE_SHMOO<1>

PP1V05_S4SW

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

P1V1SSD_PHASE

MIN_LINE_WIDTH=0.5 MM

PP1V8_S3

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

P1V8_S3_REG_FB

E85HSMUX_USB_EN

P1V05S4SW_PGOOD

GND_P1V1SSD_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP1V1_S0SW_SSD

P1V8S3_PHASE

DIDT=TRUE

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.2 MM

PVIN_S4_P5VOUT_AIN

P5VOUT_EN

P5VOUT_EN_L

PP3V3_S0SW_SSD

P1V05S4SW_FB

PP3V3_S4

PPVBUS_E85

HPM_VBUSFET_OC_L

VCFET_ILIM1

BBPD_VCONN1_EN

HPM_VCFET_OC_L

VCFET_ILIM2

HPM_VCFET_OC_L

PP5V1_S4SW_CC2

PP5V1_S4SW_CC1

<SCH_NUM>

78 OF 130

50 OF 75

30 35 43

46 47

48 49 50 60

35 50 60

46

30 35 43 46 47 48 49 50 60

54 60

30 35 43 46 47 48 49 50 60

17 23 54 56

58 59

60 64

47 50 58 59 60

29 60

20 21 46 52 59 60

46

54 56 57 59 60

46

47 50 58 59 60

22 23 28 29 30 32 33 51 60

29 60

28 50

29 60

www.qdzbwx.com

WWW.AliSaler.Com

IN

GND

VOUT

ON

VIN

IN

S

D

ON S

D

VDD

GND

VDD

D

SON

CAP

S

D

ON S

D

VDD

GND

IN

S

D

ON S

D

VDD

GND

IN

GND

VOUT

ON

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3.3V S4 Switch

HSIO has turn-on requirement of

1.05V PCH SATA Switch

<65uS from EN to 95% (1.05V)

<0.1V/uS ramp rate and

<65uS from EN to 95% (1.05V)

Load Switch

1.05V S0 Switch

EDP: 0.564 A

Load Switch

3.3V SUS Switch

U8000

TPS22924C

Part

2A Max

Current

@ 2.5V

Current

25.8 mOhm Max

18.5 mOhm Typ

Load Switch

U8020

2A Max

TPS22924C Type R(on)

Part

@ 2.5V

SLG5AP1453V

9.8 mOhm Typ

U8006

@ 4V Vgs

R(on)

Current

HSIO has turn-on requirement of

@ 4V Vgs

R(on)

Type

Current

Part

U8005

TBD mOhm Max

SLG5AP1417V

9.8 mOhm Typ

6A Max

Load Switch

6A Max

9.8 mOhm Typ

SLG5AP1417V

TBD mOhm Max

Part

Current

Type R(on)

@ 4V Vgs

<0.1V/uS ramp rate and

Type

Part

TBD mOhm Max 6A Max

EDP: 0.802 A

EDP: 1.656 A

R(on)

Type

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

U8008

1.05V PCH PCIe Switch

TBD mOhm Max

SLG5AP1417V

9.8 mOhm Typ

6A Max

Load Switch

U8009

EDP: 0.472 A

@ 4V Vgs

R(on)

Type

Current

Part

1.05V PCH USB3 Switch

<0.1V/uS ramp rate and <65uS from EN to 95% (1.05V)

HSIO has turn-on requirement of

15

13 31 52

X5R

6.3V

1.0UF

20%

0201-1

C8000

1

2

CRITICAL

CSP

TPS22924

U8000

C1

C2

A2 B2

A1 B1

10% X5R

402

1UF

10V

C8006

1

2

52

CRITICAL

TDFN

SLG5AP1471V

U8005

2 3

8

95

7

1

TDFN

CRITICAL

SLG5AP1453V

U8006

73

8

25

1

201

10%

4700PF

X7R

10V

C8007

1

2

10% X5R

402

1UF

10V

C8008

1

2

SLG5AP1471V

TDFN

CRITICAL

U8008

2 3

8

95

7

1

15 16

10V

1UF

402

X5R

10%

C8009

1

2

10V

1UF

402

X5R

10%

C8005

1

2

TDFN

SLG5AP1471V

CRITICAL

U8009

2 3

8

95

7

1

15 16

13 46

52

0201-1

20%

1.0UF

6.3V X5R

C8020

1

2

CSP

TPS22924

CRITICAL

U8020

C1

C2

A2 B2

A1 B1

SYNC_MASTER=J92_DEVMLB

Power FETs

SYNC_DATE=07/24/2013

PP3V3_S5

P1V05S0_RAMP

PCH_USB3PHY_PC

PP5V_S0

PP1V05_S0SW_PCH_USB3

PP1V05_SUS

PM_SLP_SUS_L

PCH_SATAPHY_PC

PP5V_S0

PP1V05_S0SW_PCH_SATA

PP1V05_S0SW_PCH_PCIE

PP1V05_SUS

PP5V_S0

PCH_PCIEPHY_PC

P1V05S0_EN

PP1V05_S0

PP1V05_SUS

PP3V3_S5

PP3V3_S4

PP3V3_SUS

PM_SLP_S5_L

PP5V_S0

PP1V05_SUS

<SCH_NUM>

80 OF 130

51 OF 75

8

11 13

15 16

17

22 33 37

46 47 51

59 60 73

75

16 17 25 30 39 40 44 45 47 49 51 60

8

11 60

8

11 12 16 46

48 51

60

16 17 25 30 39 40 44 45 47 49 51 60

8

11 60

8

11 60

8

11 12 16 46

48 51

60

16 17 25 30 39 40 44 45 47 49 51 60

6 8

11 15 16 17

32 44 46 60

8

11 12 16 46

48 51 60

8

11 13 15

16

17 22 33

37 46 47 51

59 60 73 75

22 23 28 29 30 32 33 50 60

8

11 14 15 18

27 28 29 46 60

16 17 25 30 39 40 44 45 47 49 51 60

8

11 12 16 46

48 51

60

WWW.AliSaler.Com

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

0

S0 Enables

SUS & S4 Enables

LPDDR power down sequencing support

SMC_PM_G2_ENABLE

1

SMC_S4_WAKESRC_EN

PM_SLP_S3_LPM_SLP_S5_L

Deep Sleep (S4AC)

0

Deep Sleep (S4)

Battery Off (G3Hot)

Run (S0)

Deep Sleep (S5)

Sleep (S3)

Deep Sleep (S5AC)

Sleep (S3AC)

Battery Off (G3HotAC)

X 1

1

toggle 3Hz

0

1

0

1 1

1

1 0 0

1

0

0 0

0

1 1

1

SMC_ADAPTER_EN

0

1

0 0

0

1 1

0

1

0

1 1

0

0 0

1

0

1 1

0

1

0

State

S5 Power Good

S3 Enables

PM_SLP_S4_L

PM_SUS_EN

Mobile System Power State Table

13 46 51

52 13 46 51 52

13 31 51 52 13 31 51 52

31 46 48 52

13 15 31 46

46 52

30K

MF

1/20W

5%

201

NO STUFF

R8116

1

2

31 46 48

52

CERM-X5R

0.1UF

0201

10%

6.3V

C8184

1

2

MF

1/20W

5%

201

10K

R8184

1

2

1K

201

MF

1/20W

5%

R8183

1

2

0201

RB521ES-30

D8183

A

K

0201

RB521ES-30

D8181

A

K

20K

1/20W

5% MF

201

R8186

1

2

1/20W

2.0K

MF

5%

201

R8181

1

2

6.3V CERM-X5R

0.1UF

0201

10%

C8186

1

2

0201

RB521ES-30

D8182

A

K

30K

1/20W MF

5%

201

R8185

1

2

MF

1/20W

4.99K

1%

201

R8182

1

2

0.1UF

0201

6.3V

10% CERM-X5R

C8185

1

2

13 31 46

5% 1/20W MF

0

0201

R8187

1

2

NO STUFF

CERM-X5R 0201

6.3V

0.1UF

10%

C8187

1

2

46 52

51 52

PMEG1201AESF

SOD-962

NO STUFF

D8170

A

K

NO STUFF

0201

RB521ES-30

D8115

A

K

201

1K

NO STUFF

MF

1/20W

5%

R8115

1

2

0201

5% MF

1/20W

0

R8117

12

46

0201

NO STUFF

10%

0.1UF

6.3V CERM-X5R

C8116

1

2

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=09/20/2013

Power Control

P1V8S3_EN_D

PM_SLP_S4_L

MAKE_BASE=TRUE

S5_PWRGD

PP1V8_S3

PP1V2_S3

PM_SLP_S5_L

MAKE_BASE=TRUE

PM_SLP_SUS_L

PM_SLP_S5_L

S5_PWRGD

MAKE_BASE=TRUE

PM_SLP_SUS_L

P1V5S0_EN_D

P5VS0_EN

P3V3S0_EN P1V5S0_EN

P1V8S3_EN

P1V05S0_EN_D

P1V05S0_ENP1V05S0_EN

MAKE_BASE=TRUE

P5VS0_EN

MAKE_BASE=TRUE

P3V3S0_EN

PMIC_V8_EN

MAKE_BASE=TRUE

P1V8S3_EN

P1V5S0_EN

MAKE_BASE=TRUE

P3V3S0_EN_D

PM_SLP_S3_L

52 OF 75

<SCH_NUM>

81 OF 130

20 21 46 50

59 60

8

10 19 20 21

46 59 60 69

51 52

46 52

WWW.AliSaler.Com

IN

GND SHLD

IN IN

IN

BI

OUT

IN

BI

IN

BI

BI IN

OUT

NC

OUT

VIN

ON

GND

VOUT

GND

VDD

D

SON

CAP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R(on)

Type

Part

LCD PANEL INTERFACE (eDP) + Camera (MIPI)

Optional Sense R

goes here

U8320

Per NF request

LCD Panel HPD & AUX strapping

500mA Max

110 mOhm Max

TPS22904

@ 2.5V

Load Switch 75 mOhm Typ

Current

LCD IRQ not in J92 flex

518S00013

Pinout reversed from flex

Bottom side contacts used

13 53

4700PF

10V 201

10% X7R

C8309

1

2

X5R-CERM

10V

10%

0.1UF

0201

C8311

1

2

0402-7

20% 10V X5R-CERM

10UF

C8312

1

2

NO_XNET_CONNECTION=TRUE

1/20W

5%

201

MF

1M

R8302

1

2

5% MF

1M

NO_XNET_CONNECTION=TRUE

1/20W 201

R8303

1

2

1M

MF 201

5% 1/20W

R8301

1

2

0201-1

1.0UF

20%

6.3V X5R

C8310

1

2

CFPA342-0250F

CRITICAL

F-RT-SM-A

J8300

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

51

52

53

54

6

7

8

9

14 31 34

36 68 72

24

31 34 72

49

13 53

10% X5R-CERM0201

0.1UF

16V

C8320

12

10% X5R-CERM

16V

0.1UF

0201

C8321

12

10% X5R-CERM0201

16V

0.1UF

C8322

12

0.1UF

X5R-CERM

16V 0201

10%

C8323

12

0.1UF

0201X5R-CERM

10% 16V

C8324

12

X5R-CERM0201

10%

0.1UF

16V

C8326

12

0.1UF

10% 16V

0201X5R-CERM

C8325

12

X5R-CERM

16V

0.1UF

0201

10%

C8327

12

X5R-CERM

10%

0.1UF

0201

16V

C8328

12

0.1UF

10% 16V X5R-CERM0201

C8329

12

5

66

5

66

5

66

5

66

5

66

5

66

5

66

5

66

5

66

5

66

14 31 34 36

68 72

18PF

01005

CERM

5% 16V

C8301

1

2

100V

X7R-CERM

1000PF

0603

10%

C8300

1

2

13 64

24

31 34 72

49

15

64

25 71

2.0K

5% MF

1/20W

201

R8381

1

2

2.0K

1/20W MF 201

5%

R8380

1

2

10% X5R-CERM

1.0UF

6.3V 0201-1

C8316

1

2

26.7K

01005

MF

1/32W

1%

R8316

12

RB521ES-30

0201

D8318

AK

TPS22904

CRITICAL

CSP

U8310

B2

B1

A1

A2

1%

1.1K

1/32W

MF

01005

R8318

12

SLG5AP1443V

CRITICAL

TDFN

U8300

73

8

25

1

8.25K

MF

1/32W 01005

1%

R8315

12

1%

6.98K

MF

1/32W 01005

R8317

12

RB521ES-30

0201

D8317

AK

10% X5R-CERM

0201-1

1.0UF

6.3V

C8315

1

2

SYNC_MASTER=J92_DEVMLB

eDP Display Connector

SYNC_DATE=09/25/2013

PP3V3_S0

SMBUS_SMC_1_S0_SCL

MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50MM

PP3V3_S0SW_LCD

DP_INT_AUX_P

PP5V_S0_ALSCAM_F

EDP_PANEL_PWR

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_N<2>

DP_INT_HPD

PANEL_P5V_EN

I2C_CAM_SDA

EDP_PANEL_PWR

PPVOUT_S0_LCDBKLT

SMBUS_SMC_1_S0_SDA

DP_INT_ML_N<3>

DP_INT_ML_P<2>

MIPI_DATA_CONN_N

DP_INT_ML_P<0>

DP_INT_AUX_N

EDP_BKLT_PWM

MIPI_DATA_CONN_P

DP_INT_ML_N<2>

DP_INT_ML_P<1>

DP_INT_ML_N<0>

MIPI_CLK_CONN_P

I2C_CAM_SCK

I2C_BKLT_SDA

DP_INT_ML_N<0>

DP_INT_ML_N<1>

DP_INT_ML_P<3>

DP_INT_AUX_N

DP_INT_ML_C_N<0>

DP_INT_ML_C_N<3>

DP_INT_AUXCH_C_P

DP_INT_AUXCH_C_N

PP3V3_S0

DP_INT_AUX_N DP_INT_AUX_P

DP_INT_HPD

DP_INT_ML_C_P<2>

DP_INT_ML_P<3>

LCD_PWR_SLEW

LCD_IRQ_L

PANEL_P3V3_EN

DP_INT_ML_C_N<2>

MIPI_CLK_CONN_N

DP_INT_ML_C_P<3>

PP5V_S0SW_LCD

DP_INT_ML_C_P<0>

SMBUS_SMC_0_S0_SDA

PANEL_P5V_EN_D

SMBUS_SMC_0_S0_SCL

DP_INT_ML_P<1>

I2C_BKLT_SCL

PP5V_S0SW_LCD

PANEL_P3V3_EN_D

PP5V_S4

83 OF 130

53 OF 75

<SCH_NUM>

8

11 12 13

15

17 18 23

24 29 32 33

34 35 36 40

46 47 53 60

73 75

53 66

25

53 66

13 53

49

66

53 66

66

53 66

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

53 66

53 66 13 53

53 66

53 60

53 66

53 60

30 38 47 60 75

WWW.AliSaler.Com

IN

IN IN

OUT

IN

NC

IN

OUT

IN

RX0_P

PAVDD

XTALO

XTALI

RX1_N

RX0_N

RX1_P

RX2_P RX2_N

RX3_P

TX3_P

SLAVE_TAP_TCK

ATEST

AVDD

FUSE_VDD1 FUSE_VDD2 FUSE_VDD3

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10

GPIOHV0 GPIOHV1

GPIO_3_3_VDDIO

I2C_SCL I2C_SDA

MASTER_TAP_NRST

MASTER_TAP_TCK MASTER_TAP_TDI MASTER_TAP_TDO MASTER_TAP_TMS

NC

PCIE_CLKREQ*

PERST*

PFW*

POR_BYPASS

PVSS

REF_PAD_CLK_N

REF_PAD_CLK_P

RESREF

RX3_N

SLAVE_TAP_TMS

SPI_CSN

SPI_MISO SPI_MOSI SPI_SCLK

STBY_EN

TEST0 TEST1 TEST2 TEST3

TX3_N

UART0_RX UART0_TX UART1_RX UART1_TX

VIN_PFW*

VP

VREFIN0

VREFIN1 VREFOUT0 VREFOUT1

XTAL_BYPASS

TX0_P TX0_N

TX2_P TX2_N

VPTX

VPH

TX1_P TX1_N

SYM 3 OF 9

1

2

3

4

6

7

8

5

IN

OUT

IN

NC

IN

OUT OUT

IN

NC

NC NC NC

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

SSD NAND CONFIG Straps

(GPIO8)

SSD NAND Parts

1

**S1-X GPIO[10:1] IPD**

1X 1Y

8 (X56)

LITHO

64Gb

SANDISK

512GB

DENSITY

256GB

128GB

128Gb

4 (J92)

0

1

0

1

0

1

1 0

VENDOR TOSHIBA

1

(IPU)

NAND_VEND(GPIO3)

NAND_DENS0(GPIO4) NAND_DENS1(GPIO5)

1

NAND_DIE(GPIO7)

# NAND_CH

DIE SIZE

NAND_LITHO(GPIO6)

64

12 64 66

1% MF

200

201

1/20W

R8410

12

12 64 66

31

64

23 59 64

23 31

23 59 64

1.1K

201

5% MF

1/20W

R8440

12

0.1UF

10%

0201

X7R

6.3V

C8430

1

2

X5R

20%

6.3V 0201-1

1.0UF

C8432

1

2

6.3V

0.1UF

X7R

10%

0201

C8431

1

2

MF

1/20W

5%

10K

201

R8444

1

2

10K

1/20W

MF

5%

201

R8445

12

58

OMIT_TABLE

S1-X

BGA

U8400

G2

N8 P8

AA7 AB6 AB7

B3 F6

K6

C3 C2 H6 D3 G6 E3 J6 D2

AA8

Y5 Y4

F4 F5

G1 F1 F3 G3 F2

M6

V14

AB2

AB4

AB3

R10

V15 T15 U15 U14

J5

K5

T7

K3

J3

M3

L3

P3

N3

T3

R3

D1 E1

AD2

AD1 AC3 AB1

W5

L6 H4 G5 H5

R1

T1

N1

P1

L1

M1

J1

K1

Y1 Y2 H1 H2

AC4

U9 T9

R8 T8 U8

M9 N9 M10 N10

R9

N5 M5

59

12

17 54 64

59

50

10K

5% 1/20W MF 201

R8446

1

2

23 59 64

PLACE_NEAR=U8400.P8:3.0MM

0.22UF

20% X6S-CERM

6.3V 0201

C8434

1

2

1/20W MF

5%

100K

201

R8447

1

2

1/20W

5%

100K

MF 201

R8413

1

2

6.3V

0.1UF

GND_VOID=TRUE

CERM-X5R 0201

10%

C8410

12

CERM-X5R

GND_VOID=TRUE

6.3V

0.1UF

0201

10%

C8411

12

6.3V

10%

0201

0.1UF

CERM-X5R

GND_VOID=TRUE

C8413

12

6.3V

CERM-X5R

0.1UF

0201

10%

GND_VOID=TRUE

C8412

12

GND_VOID=TRUE

6.3V 0201

10% CERM-X5R

0.1UF

C8414

12

10%

0201

0.1UF

CERM-X5R

6.3V

GND_VOID=TRUE

C8415

12

0201CERM-X5R

6.3V

GND_VOID=TRUE

10%

0.1UF

C8417

12

10%

0.1UF

CERM-X5R

6.3V

GND_VOID=TRUE

0201

C8416

12

1/20W

1K

5% MF

201

NAND_DENS1

R8485

1

2

MF 201

1K

5% 1/20W

NAND_DENS0

R8484

1

2

NAND_LITHO

1K

201

MF

5% 1/20W

R8486

1

2

5% MF

201

1K

1/20W

NAND_DIE

R8487

1

2

5% 1/20W MF

1K

NAND_VEND

201

R8483

1

2

NAND:TOSH_128GB_1X_64GBIT

NAND_DENS0,NAND_DENS1,NAND_VEND,NAND_LITHO,NAND_DIE,NAND_TYPE:TOSH_128GB_1X_64GBIT

NAND:SAND_128GB_1X_64GBIT

NAND_DENS0,NAND_DENS1,NAND_LITHO,NAND_DIE,NAND_TYPE:SAND_128GB_1X_64GBIT

NAND_DENS1,NAND_TYPE:SAND_256GB_1Y_128GBIT

NAND:SAND_256GB_1Y_128GBIT

NAND_DENS0,NAND_DENS1,NAND_DIE,NAND_TYPE:SAND_128GB_1Y_64GBIT

NAND:SAND_128GB_1Y_64GBIT

NAND_DENS0,NAND_TYPE:SAND_512GB_1Y_128GBIT

NAND:SAND_512GB_1Y_128GBIT

SYNC_DATE=02/11/2014

SYNC_MASTER=J92_SSD

SSD Controller (1 of 4)

998-7360

NAND_TYPE:TOSH_128GB_1X_64GBIT

CRITICAL

NAND,19NM,64GX8,MLC,RAW,64G,2-CH,LGA60

U8801,U8810

2 2

NAND_TYPE:TOSH_128GB_1Y_64GBIT

CRITICAL

U8801,U8810

NAND,TOGGLE DDR2,2CH,64GB,1YNM,3.3V,LGA60

335S00004

U8801,U8810

NAND_TYPE:TOSH_512GB_1Y_128GBIT

CRITICAL

NAND,TOGGLE DDR2,2CH,256GB,1YNM,3.3V,LGA60

2335S1032

NAND_TYPE:SAND_128GB_1Y_64GBIT

335S1044 2

NAND,TOGGLE DDR2,2CH,64GB,1YNM,3.3V,LGA60

U8801,U8810

CRITICAL

NAND,TOGGLE DDR2,2CH,128GB,1YNM,3.3V,LGA60

NAND_TYPE:TOSH_256GB_1Y_128GBIT

335S1031

U8801,U8810

CRITICAL

2

CRITICAL

NAND_TYPE:SAND_256GB_1Y_128GBIT

U8801,U8810

NAND,TOGGLE DDR2,2CH,128GB,1YNM,3.3V,LGA60

2335S1041

NAND_TYPE:SAND_128GB_1X_64GBIT

998-7361

CRITICAL

U8801,U8810

NAND,19NM,64GX8,MLC,RAW,64G,2-CH,LGA60

2

U8801,U8810

335S1045

NAND_TYPE:SAND_512GB_1Y_128GBIT

CRITICAL

NAND,TOGGLE DDR2,2CH,256GB,1YNM,3.3V,LGA60

2

NAND:TOSH_256GB_1Y_128GBIT

NAND_VEND,NAND_DENS1,NAND_TYPE:TOSH_256GB_1Y_128GBIT

NAND_DENS0,NAND_DENS1,NAND_VEND,NAND_DIE,NAND_TYPE:TOSH_128GB_1Y_64GBIT

NAND:TOSH_128GB_1Y_64GBIT

NAND:TOSH_512GB_1Y_128GBIT

NAND_VEND,NAND_DENS0,NAND_TYPE:TOSH_512GB_1Y_128GBIT

S1X_DEBUG_UART_R2D

SSD_GPIO<5> SSD_GPIO<6> SSD_GPIO<7>

PP3V3_S0SW_S1X

PP1V1_S0SW_SSD

PP2V5_S0SW_SSD

PCIE_SSD_D2R_C_P<0>

=PCIE_SSD_R2D_P<2>

=PCIE_SSD_D2R_N<0>

PP1V8_S0SW_SSD_COLD

SSD_GPIO<4>

=PCIE_SSD_R2D_P<0> =PCIE_SSD_R2D_N<0>

PCIE_SSD_RESREF_R

SSD_CLKREQ_L

SAK_SSD_PCIE_RESET_L

MAKE_BASE=TRUE

SYSCLK_CLK12M_SSD

=PCIE_SSD_R2D_N<3>

PP1V8_S0SW_SSD_COLD

=PCIE_SSD_D2R_P<3>

=PCIE_SSD_D2R_N<2>

=PCIE_SSD_D2R_N<1>

=PCIE_SSD_D2R_P<1>

PCIE_CLK100M_SSD_N

PCIE_CLK100M_SSD_P

=PCIE_SSD_R2D_P<3>

=PCIE_SSD_R2D_N<2>

=PCIE_SSD_R2D_P<1> =PCIE_SSD_R2D_N<1>

PP1V1_S0SW_SSD

SSD_VIN_PWRFAIL_WARN_L

TP_SSD_JTAG_SLAVE_TMS

SSD_PWRFAIL_WARN_L

SSD_JTAG_MASTER_TMS

SSD_JTAG_MASTER_TDO

SSD_JTAG_MASTER_TDI

SSD_JTAG_MASTER_TCK

SSD_JTAG_MASTER_NRST

TP_SSD_JTAG_SLAVE_TCK

PP1V8_S0SW_SSD_COLD

PP3V3_S0SW_S1X

PCIE_SSD_D2R_C_N<1>

SSD_OSC_BYPASS

S1X_STBY_EN

PP1V8_S0SW_SSD_COLD

SMC_OOB1_R2D_L

SSD_SPI_MISO

PCIE_SSD_D2R_C_N<3>

SAK_SSD_COLD_BOOT_L

SSD_SPI_CS_L

SSD_SPI_SCLK

SSD_SPI_MOSI

SSD_UART_BOOT_L

SSD_I2C_SCL

SYSCLK_CLK12M_SSD

S1X_DEBUG_UART_D2R

SSD_I2C_SDA

SSD_GPIO<3>

SSD_CORE_SHMOO<0> SSD_CORE_SHMOO<1>

PCIE_SSD_D2R_C_P<3>

PCIE_SSD_D2R_C_N<2>

PCIE_SSD_D2R_C_P<2>

PCIE_SSD_D2R_C_P<1>

PCIE_SSD_D2R_C_N<0>

=PCIE_SSD_D2R_P<0>

=PCIE_SSD_D2R_N<3>

SMC_OOB1_D2R_L

=PCIE_SSD_D2R_P<2>

<SCH_NUM>

84 OF 130

54 OF 75

54 56 59

60

50 54 56 57 59 60

50 60

66

17 23 50 54 56 58 59 60

64

17 23 50 54 56 58

59 60 64

17 23 50 54 56 58 59 60 64

50 54 56 57 59 60

59

17 23 50 54 56 58 59 60

64

54 56 59 60

66

17 23 50 54 56 58 59 60 64

66

58

17 54 64

58

66

WWW.AliSaler.Com

NC

BI

OUT

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

ANI7_PPM_IN

ANI7_NWE

ANI7_NRE_P

ANI7_NRE_N

ANI7_NCE7

ANI7_NCE6

ANI7_NCE5

ANI7_NCE4

ANI7_NCE3

ANI7_NCE2

ANI7_NCE1

ANI7_NCE0

ANI7_IO7

ANI7_IO6

ANI7_IO5

ANI7_IO4

ANI7_IO3

ANI7_IO2

ANI7_IO1

ANI7_IO0

ANI7_DQS_P

ANI7_DQS_N

ANI7_CLE

ANI7_ALE

ANI6_PPM_OUT

ANI6_PPM_IN

ANI6_NWE

ANI6_NRE_P

ANI6_NRE_N

ANI6_NCE7

ANI6_NCE6

ANI6_NCE5

ANI6_NCE4

ANI6_NCE3

ANI6_NCE0

ANI6_IO7

ANI6_IO6

ANI6_IO5

ANI6_IO4

ANI6_IO3

ANI6_IO2

ANI6_CLE

ANI6_ALE

ANI5_PPM_OUT

ANI5_PPM_IN

ANI5_NWE

ANI5_NRE_P

ANI5_NCE4

ANI5_NCE2

ANI5_NCE0

ANI5_IO7

ANI5_IO5

ANI5_IO3

ANI5_IO1

ANI5_IO0

ANI5_DQS_P

ANI5_DQS_N

ANI5_CLE

ANI5_ALE

ANI4_PPM_OUT

ANI4_PPM_IN

ANI4_NWE

ANI4_NRE_P

ANI4_NRE_N

ANI4_NCE7

ANI4_NCE6

ANI4_NCE5

ANI4_NCE1

ANI4_NCE0

ANI4_IO6

ANI4_IO5

ANI4_IO2

ANI4_IO1

ANI4_IO0

ANI4_DQS_N

ANI4_CLE

ANI4_ALE

ANI6_NCE1 ANI6_NCE2

ANI4_NCE4

ANI4_IO4

ANI4_IO3

ANI4_IO7

ANI6_IO0

ANI4_NCE2 ANI4_NCE3

ANI5_NRE_N

ANI5_NCE7

ANI5_NCE6

ANI5_NCE5

ANI5_NCE3

ANI5_NCE1

ANI5_IO6

ANI5_IO4

ANI5_IO2

ANI4_DQS_P

ANI7_PPM_OUT

ANI6_IO1

ANI6_DQS_P

ANI6_DQS_N

4

SYM 2 OF 9

765

NC

NC NC NC NC

NC

NC NC

NC

NC NC

NC

NC NC NC

NC

NC NC

NC

OUT

BI

OUT

BI

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

BI

OUT

BI

OUT

BI

BI BI

BI

BI BI

BI

OUT

BI

OUT

NC

ANI0_DQS_P

ANI0_NCE0

ANI0_IO7

ANI0_NCE1

ANI0_IO5

ANI0_NCE5 ANI0_NCE6 ANI0_NCE7

ANI0_PPM_IN

ANI3_DQS_N

ANI2_PPM_OUTANI0_PPM_OUT

ANI1_ALE ANI1_CLE ANI1_DQS_N ANI1_DQS_P ANI1_IO0

ANI3_IO2

ANI3_IO1

ANI2_PPM_IN

ANI3_IO4

ANI3_IO3

ANI0_ALE ANI0_CLE ANI0_DQS_N

ANI0_IO0 ANI0_IO1 ANI0_IO2 ANI0_IO3 ANI0_IO4

ANI0_NRE_N ANI0_NRE_P ANI0_NWE

ANI1_IO1 ANI1_IO2 ANI1_IO3 ANI1_IO4 ANI1_IO5 ANI1_IO6 ANI1_IO7 ANI1_NCE0 ANI1_NCE1 ANI1_NCE2 ANI1_NCE3 ANI1_NCE4 ANI1_NCE5 ANI1_NCE6 ANI1_NCE7 ANI1_NRE_N ANI1_NRE_P ANI1_NWE ANI1_PPM_IN ANI1_PPM_OUT

ANI2_ALE

ANI2_CLE ANI2_DQS_N ANI2_DQS_P

ANI2_IO0

ANI2_IO1

ANI2_IO2

ANI2_IO3

ANI2_IO4

ANI2_IO5

ANI2_IO6

ANI2_IO7

ANI2_NCE0 ANI2_NCE1 ANI2_NCE2 ANI2_NCE3 ANI2_NCE4 ANI2_NCE5 ANI2_NCE6

ANI2_NCE7 ANI2_NRE_N ANI2_NRE_P

ANI2_NWE

ANI3_ALE ANI3_CLE

ANI3_DQS_P

ANI3_IO0

ANI3_IO5 ANI3_IO6

ANI3_IO7 ANI3_NCE0 ANI3_NCE1 ANI3_NCE2 ANI3_NCE3 ANI3_NCE4 ANI3_NCE5 ANI3_NCE6 ANI3_NCE7

ANI3_NRE_N ANI3_NRE_P

ANI3_NWE

ANI3_PPM_IN

ANI3_PPM_OUT

ANI0_NCE3

ANI0_NCE2

ANI0_IO6

ANI0_NCE4

13

20

SYM 1 OF 9

OUT

BI

OUT OUT

OUT

BI OUT

BI

BI BI

BI

NC

BI

OUT

BI BI

OUT OUT

BI

BI BI

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

58 70

58

70

58 70

S1-X

BGA

OMIT_TABLE

U8400

AE12 AF11 AH14 AJ14 AJ11 AJ16 AH11 AH16 AJ15 AH15 AJ12 AH12 AE16 AF15 AE15 AF14 AE14 AF13 AE13 AF12 AH13 AJ13 AF16 AE11 AD11

AF5 AE5 AH7 AJ7 AH5 AJ8 AH4 AH8 AJ9 AH9 AJ4 AJ5 AF9 AE9 AF8 AE8 AF7 AE7 AF6 AE6 AH6 AJ6 AD9 AF4 AE4

AF25 AF26 AE28 AE29 W29 AC29 AA28 AG26 AH26 AH25 AA29 AC28 AA25 AA26 AB25 AB26 AC25 AC26 AD25 AD26 AF27 AG27 W25 AE26 AE25

AD18 AF19 AH21 AJ21 AJ23 AH23 AH22 AJ22 AJ19 AH19 AJ18 AH18 AE23 AF22 AE22 AF21 AE21 AF20 AE20 AE19 AH20 AJ20 AF23 AF18 AE18

58 70

58

70

58 70

BGA

S1-X

OMIT_TABLE

U8400

F18 D19 B20 A20 B22 A23 B21 A22 A21 B18 A18 C18 E23 D22 E22 D21 E21 D20 E20 E19 B19 A19 D23 D18 E18

D25 D26 E28 E29 G28 J29 G29 L29 J28 B26 C26 B25 J25 J26 H25 H26 G25 G26 F25 F26 D27 C27 K25 E26 E25

E12 D11 B14 A14 A16 A11 B16 B11 A12 B12 B15 A15 E16 D15 E15 D14 E14 D13 E13 D12 B13 A13 D16 E11 F11

D5 E5 B6 A6 B4 A7 C4 B9 B8 A9 A4 A8 D9 E9 D8 E8 D7 E7 D6 E6 B5 A5 F9 D4 E4

58 70

58

70

58 70

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=10/10/2013

SSD Controller (2 of 4)

ANI1_NWE

ANI1_NRE_P

ANI1_ALE ANI1_CLE ANI1_DQS_N ANI1_DQS_P ANI1_IO<0>

ANI0_ALE ANI0_CLE ANI0_DQS_N ANI0_DQS_P ANI0_IO<0> ANI0_IO<1> ANI0_IO<2> ANI0_IO<3> ANI0_IO<4> ANI0_IO<5> ANI0_IO<6> ANI0_IO<7> ANI0_NCE<0> ANI0_NCE<1> ANI0_NCE<2> ANI0_NCE<3>

ANI0_NRE_N ANI0_NRE_P ANI0_NWE

ANI1_IO<1> ANI1_IO<2> ANI1_IO<3> ANI1_IO<4> ANI1_IO<5> ANI1_IO<6> ANI1_IO<7> ANI1_NCE<0> ANI1_NCE<1> ANI1_NCE<2> ANI1_NCE<3>

ANI6_NCE<2>

ANI6_NCE<1>

ANI6_ALE ANI6_CLE ANI6_DQS_N ANI6_DQS_P ANI6_IO<0> ANI6_IO<1> ANI6_IO<2> ANI6_IO<3> ANI6_IO<4> ANI6_IO<5> ANI6_IO<6> ANI6_IO<7> ANI6_NCE<0>

ANI6_NCE<3>

ANI6_NRE_N ANI6_NRE_P ANI6_NWE

ANI7_ALE ANI7_CLE ANI7_DQS_N ANI7_DQS_P ANI7_IO<0> ANI7_IO<1> ANI7_IO<2> ANI7_IO<3> ANI7_IO<4> ANI7_IO<5> ANI7_IO<6> ANI7_IO<7> ANI7_NCE<0> ANI7_NCE<1> ANI7_NCE<2> ANI7_NCE<3>

ANI7_NRE_N ANI7_NRE_P ANI7_NWE

ANI1_NRE_N

<SCH_NUM>

85 OF 130

55 OF 75

WWW.AliSaler.Com

DDR_ATO DDR_DTO0 DDR_DTO1 DDR_PHY_ZQ DDR_ZQ

AVSS

DDR_CKE0 DDR_CKE1

LPDDR2_DATA_VDDIO

PVDD_DIG

SENSE0 SENSE1

VDD2

VDDCA

VDDQ

VDD_DIG

VREF_CMD

VREF_DATA

LPDDR2_CMD_VDDIO

VDD1

1

2

5

6

7

SYM 4 OF 9

4

3

NC

1

SYM 5 OF 9

3

2

ZQ_RES_IN

TOP_VREF_1

TOP_VDDIO_PROB

DATA_VDDIO_PROB

CMD_VDDIO_PROB

BOT_VDDIO_PROB

BOTTOM_VREF_2

BOTTOM_VREF_1

ANI_TOP_VDDIOANI_BOT_VDDIO

TOP_VREF_2

NC NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

0.1UF

0201

X7R

6.3V

10%

C8640

1

2

PLACE_NEAR=U8400.V8:3.0MM

0.22UF

0201

6.3V X6S-CERM

20%

C8647

1

2

PLACE_NEAR=U8400.AA4:2.0MM

1K

201

1/20W MF

1%

R8600

1

2

BGA

S1-X

OMIT_TABLE

U8400

P7 M7 N7 R7

AD3

AA4 AA3

AE2 AE3 M23

V2

V8 W8 Y8 V5 V7 W6

N22 N24

T25 T27 U22 U24 U26 U28 R22

N26 N28 P23 P25 P27 R24 R26 T23

T14

P10 P9

A27 AA2 AF1 AJ27 R29 V4 AB28 AC1 AG1 AG29 C29 H28 R28 V3 W1

N6 P6

AA1 AE1 V1

AB29 AD29

P29 T29 V29 Y29

AF29 AH27 B27 D29 F29 H29 K29 M29

W2 R27

PLACE_NEAR=U8400.R27:5.0MM

0.1UF

X7R

10%

6.3V

0201

C8620

1

2

0.1UF

X7R

10%

0201

6.3V

C8654

1

2

20% X5R

0201-1

6.3V

1.0UF

C8644

1

2

10% X7R

6.3V 0201

0.1UF

C8657

1

2

PLACE_NEAR=U8400.W2:5.0MM

10% X7R

0201

0.1UF

6.3V

C8610

1

2

0.1UF

0201

6.3V X7R

10%

C8655

1

2

0.22UF

6.3V 0201

20% X6S-CERM

C8656

1

2

X6S 0402

6.3V

20%

4.7UF

C8645

1

2

6.3V X7R

0.1UF

10%

0201

C8658

1

2

1.0UF

6.3V

20% X5R

0201-1

C8648

1

2

X7R

10%

0201

0.1UF

6.3V

C8641

1

2

0201

6.3V X6S-CERM

0.22UF

20%

C8642

1

2

1.0UF

6.3V

20% X5R

0201-1

C8652

1

2

0201

6.3V

0.1UF

10% X7R

C8600

1

2

S1-X

BGA

OMIT_TABLE

U8400

AA22

AB9

AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AD10 AD17

AB11

AD24 AE10 AE17 AE24 AF10 AF17 AF24 AG10 AG17 AG24

AB13

AH10 AH17 AH24 AJ10 AJ17 AJ24

W22 Y23

AB15 AB17 AB19 AB21 AB23

AC8

A10 A17

D17 D24 E10 E17 E24 F10 F17 F24 G8 G10

A24

G12 G14 G16 G18 G20 G22 G24 H9 H11 H13

B10

H15 H17 H19 H21 H23 J8 J22 K7 K23 L7

B17

L22 H7

B24 C10 C17 C24 D10

AC7

AJ3 AJ25

Y7

V23

G7

A25 A3

G23

6.3V

10%

0.1UF

PLACE_NEAR=U8400.AA1:2.0MM

X7R 0201

C8653

1

2

6.3V 0201

20%

0.22UF

X6S-CERM

C8651

1

2

PLACE_NEAR=U8400.A25:2.0MM

0.1UF

10%

6.3V X7R 0201

C8650

1

2

PLACE_NEAR=U8400.AJ25:2.0MM

0.1UF

10%

6.3V X7R 0201

C8601

1

2

201

MF

1%

243

1/20W

R8630

12

0201

X6S-CERM

6.3V

20%

0.22UF

C8634

1

2

0.1UF

10%

0201

6.3V X7R

C8630

1

2

0.22UF

6.3V X6S-CERM

20%

0201

C8635

1

2

0.1UF

10%

0201

X7R

6.3V

C8631

1

2

1/20W

100K

201

5% MF

R8661

1

2

2.2UF

X6S

6.3V

20%

0402

C8649

1

2

100K

1/20W 201

5% MF

R8660

1

2

20%

2.2UF

X6S

6.3V 0402

C8636

1

2

0201

0.22UF

20% X6S-CERM

6.3V

C8632

1

2

0201

20% X6S-CERM

6.3V

0.22UF

C8633

1

2

PLACE_NEAR=U8400.W2:5.0MM

4.99K

0.1% 1/20W MF 0201

R8637

1

2

PLACE_NEAR=U8400.W2:5.0MM

0.1%

0201

1/20W MF

4.99K

R8636

1

2

PLACE_NEAR=U8400.R27:5.0MM

0201

MF

1/20W

0.1%

4.99K

R8651

1

2

0.22UF

0201

20%

6.3V X6S-CERM

C8643

1

2

PLACE_NEAR=U8400.R27:5.0MM

0201

1/20W

0.1%

4.99K

MF

R8650

1

2

3.0K

1/20W

0.1% MF

0201

R8634

1

2

3.0K

1/20W MF

0.1%

0201

R8639

1

2

0201

25V

12PF

CERM

5%

C8637

1

2

0201

5% CERM

12PF

25V

C8638

1

2

0201

25V

12PF

CERM

5%

C8659

1

2

25V 0201

C0G-CERM

3.3PF

+/-0.1PF

NOSTUFF

C8646

1

2

201

1/20W

240

1% MF

R8601

1

2

201

1/20W

240

1% MF

R8602

1

2

SSD Controller (3 of 4)

SYNC_MASTER=J92_SSD

SYNC_DATE=02/11/2014

DDR_VREF_DATA

PP1V2_S0SW_SSD_COLD

PP1V1_S0SW_SSD

LPDDR2_CKE0

PP3V3_S0SW_S1X

NO_TEST=TRUE

LPDDR2_CKE0

PP1V1_S0SW_SSD

PP1V2_S0SW_SSD_COLD

DDR_VREF_CMD

DDR_PHY_ZQ DDR_ZQ

PP1V2_S0SW_SSD_COLD

DDR_VREF_DATA

PP1V8_S0SW_SSD_COLD

ANI_VREF

PP1V8_S0SW_SSD_COLD PP1V8_S0SW_SSD_COLD

PP1V2_S0SW_SSD_COLD

ANI_VREF

S1X_ANI_CALIB

UNUSED_ANI_VREF

PP1V8_S0SW_SSD_COLD

PP1V2_S0SW_SSD_COLD

PP1V2_S0SW_SSD_HOT

PP1V8_S0SW_SSD_HOT

PP1V8_S0SW_SSD_COLD

<SCH_NUM>

86 OF 130

56 OF 75

56

56 59 60

50

54 56 57 59 60

50 54 56 57 59 60

56

54 59 60

56

50 54 56 57 59 60

56 59 60

56

56 59 60

56

17 23 50 54 56 58 59 60 64

56 58

17 23 50 54 56 58 59 60 64

56 59 60

56

58

17 23 50 54 56 58 59 60 64

56 59 60

59 60

17 23 50 54 56 58 59 60 64

WWW.AliSaler.Com

SYM 6 OF 9

PWR

VDDVDD

SYM 7 OF 9

VSSVSS

SYM 8 OF 9

VSS

SYM 9 OF 9

VSSVSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

0402

X6S

20%

6.3V

4.7UF

C8716

1

2

X5R

20%

1.0UF

6.3V 0201-1

C8712

1

2

6.3V X6S 0402

4.7UF

20%

C8717

1

2

0201-1

6.3V X5R

20%

1.0UF

C8713

1

2

20%

0201

6.3V X6S-CERM

0.22UF

C8706

1

2

0201

6.3V X6S-CERM

0.22UF

20%

C8707

1

2

0201

20%

6.3V X6S-CERM

0.22UF

C8702

1

2

0201

6.3V

20%

0.22UF

X6S-CERM

C8703

1

2

X6S-CERM 0201

20%

6.3V

0.22UF

C8708

1

2

X6S-CERM

6.3V

20%

0201

0.22UF

C8709

1

2

20% X6S

4V

10UF

0402-1

C8718

1

2

0201

6.3V

20%

0.22UF

X6S-CERM

C8704

1

2

0.1UF

X7R 0201

6.3V

10%

C8700

1

2

0.22UF

20%

6.3V X6S-CERM 0201

C8705

1

2

10%

6.3V X7R

0.1UF

0201

C8701

1

2

S1-X

BGA

OMIT_TABLE

U8400

AA10 AA12

J18 J20

K9 K11 K13 K15 K17 K19 K21 L10

AA14

L12 L14 L16 L18 L20 M11 M13 M15 M17 M19

AA16

M21 N12 N14 N16 N18 N20 P11 P13

P15 P17

AA18

P19 P21 R12 R14 R16 R18 R20 T11 T13 T17

AA20

T19 T21 U10 U12 U16 U18 U20 V9 V11 V13

J10

V17 V19 V21 W10 W12 W14 W16 W18 W20 Y9

J12

Y11 Y13 Y15 Y17 Y19 Y21

J14 J16

BGA

S1-X

OMIT_TABLE

U8400

A1 A2

AA11

B2 B7 B23 B28 B29 C1 C5 C6 C7 C8

AA13

C9 C11 C12 C13 C14 C15 C16 C19 C20 C21

AA15 AA17 AA19 AA21 AA23 AA24 AA27

AB5

A26

AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24

A28

AB27

AC2

AC5

AC6

AC9 AC11 AC13 AC15 AC17 AC19

A29

AC21 AC23 AC27

W4 AD4 AD5 AD6 AD7 AD8

AD12 AD13 AD14 AD15 AD16 AD19 AD20 AD21 AD22 AD23 AD27 AD28

W3 Y3 AE27 AF2 AF3 AF28 AG2 AG3 AG4

AA5

AG5 AG6 AG7 AG8 AG9 AG11 AG12 AG13 AG14 AG15

AA6

AG16 AG18 AG19 AG20 AG21 AG22 AG23 AG25 AG28 AH1

AA9

AH2 AH3 AH28 AH29 AJ1 AJ2 AJ26 AJ28 AJ29 B1

BGA

S1-X

OMIT_TABLE

U8400

C22 C23 C25 C28 D28

E2

E27

F7

F8 F12 F13 F14 F15 F16 F19 F20 F21 F22 F23 F27 F28

G4

G9 G11 G13 G15 G17 G19 G21 G27

H3

H8 H10 H12 H14 H16 H18 H20 H22 H24 H27

J2

J4

J7

J9 J11 J13 J15 J17 J19 J21

J23 J24 J27 K2 K4 K8 K10 K12 K14 K16 K18 K20 K22 K24 K26 K27 K28 L2 L4 L5 R5 L8 L9 L11 L13 L15 L17 L19 L21 L23 L24 L25 L26 L27 L28 M2 M4 T5 M8 M12 M14 M16 M18 M20 M22 M24 M25 M26 M27 M28 N2

20%

10UF

X6S

4V 0402-1

C8719

1

2

BGA

S1-X

OMIT_TABLE

U8400

N4 N11 N13 N15 N17 N19 N21 N23 N25 N27 N29

P2

P4

P5 P12 P14 P16 P18 P20 P22 P24 P26 P28

R2

R4

R6 R11 R13 R15 R17 R19 R21 R23 R25

T2

T4

T6 T10 T12 T16 T18 T20 T22 T24 T26 T28

U1

U2

U3

U4

U5 U6 U7 U11 U13 U17 U19 U21 U23 U25 U27 U29 V6 V10 V12 V16 V18 V20 V22 V24 V25 V26 V27 V28 W7 W9 W11 W13 W15 W17 W19 W21 W23 W24 W26 W27 W28 Y6 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24 Y25 Y26 Y27 Y28

0201

5% CERM

12PF

25V

C8722

1

2

0201

5% CERM

12PF

25V

C8723

1

2

0402

X6S

20%

4.7UF

6.3V

C8714

1

2

20%

0201-1

6.3V X5R

1.0UF

C8710

1

2

0402

X6S

20%

6.3V

4.7UF

C8715

1

2

6.3V 0201-1

20%

1.0UF

X5R

C8711

1

2

X6S

4V

20%

10UF

0402-1

C8720

1

2

4V

20%

10UF

X6S 0402-1

C8721

1

2

SYNC_DATE=10/10/2013

SYNC_MASTER=J92_DEVMLB

SSD Controller (4 of 4)

PP1V1_S0SW_SSD

<SCH_NUM>

87 OF 130

57 OF 75

50 54 56

59 60

WWW.AliSaler.Com

BI

IO3-0 IO4-0

WP*

CLE1

IO1-0

PPM0OUT

PPM0IN

IO7-1

RE0

ALE0 WE0*

DQS1*

DQS1

DQS0

PPM1OUT

IO0-0

IO5-0

IO7-0

PPM1IN

CE6*

CE4*

CE3*

CE2*

RE0*

CLE0

IO6-1

IO4-1 IO5-1

IO0-1

IO3-1

IO1-1 IO2-1

VREF

RE1

RE1*

WE1*

ALE1

CE1*

VCC

CE7*

IO6-0

VCCQ

GND

IO2-0

CE0*

DQS0*

VPP

CE5*

R/B*

NC

IN

BI BI

BI

NC

IN

BI

IN

BI

IN

SCL

GND

ADD0

ALERT

V+

SDA

NC

BI

OUT

IN

NC NC

NC

NC NC

NC

VSS

NC

DO/SO

DI/SI

HOLD*/RESET*

WP*

CS*

CLK/SCLK

VCC

NC

NC NC

BI

BI BI

BI

BI BI

BI

BI BI

BI

IO3-0 IO4-0

WP*

CLE1

IO1-0

PPM0OUT

PPM0IN

IO7-1

RE0

ALE0 WE0*

DQS1*

DQS1

DQS0

PPM1OUT

IO0-0

IO5-0

IO7-0

PPM1IN

CE6*

CE4*

CE3*

CE2*

RE0*

CLE0

IO6-1

IO4-1 IO5-1

IO0-1

IO3-1

IO1-1 IO2-1

VREF

RE1

RE1*

WE1*

ALE1

CE1*

VCC

CE7*

IO6-0

VCCQ

GND

IO2-0

CE0*

DQS0*

VPP

CE5*

R/B*

NC NC

BI

BI BI

IN

BI

IN

BI

BI BI

BI

BI BI

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NAND INTERFACE 6/1

NAND INTERFACE 0/7

55 70

LGA

OMIT_TABLE

NAND-XXNM-XGBX8-MLC-SSD-64G

U8810

J7

E7

N1

A1

L1 C1 J1 E1 H2 F2

L7

C7

M4 L3

B4 C3

D4

K4

OA0

OB8

OE8

OF0

N3

A3

N5

A5

M2

B2

M6

B6

L5

C5

K6

D6

K2

D2

J3

E3

G7 G1

G0 G5

H6

J5 H4

E5 F4

OA8

OC0

OD0

OF8

OB0

OC8

OD8

OE0

G3

G8

N7

A7

F6

6.3V

0201-1

1.0UF

X5R

20%

C8804

1

2

X6S-CERM

0.22UF

6.3V

20%

0201

C8805

1

2

55 70

55

70

55 70

0201

10% X7R

6.3V

0.1UF

C8806

1

2

0201

6.3V X7R

0.1UF

10%

C8807

1

2

10% X7R

6.3V

0.1UF

0201

C8808

1

2

55 70

55

70

55 70

20%

0201

6.3V

0.22UF

X6S-CERM

C8811

1

2

55 70

55

70

55 70

56 58

55 70

201

4.7K

5% 1/20W MF

R8821

1

2

201

4.7K

5% 1/20W MF

R8820

1

2

PLACE_NEAR=U8821.5:2.0MM

0201

10% 10V

0.01UF

X7R-CERM

C8821

1

2

PLACE_SIDE=TOP

SN1111039AIDPK

UQFN

U8821

4

3

2

1

6

5

54

201

MF

1/20W

5%

10K

R8802

1

2

54

X5R

6.3V

20%

0201-1

1.0UF

C8812

1

2

10V

20%

22UF

CER-X5R 0805

C8810

1

2

0201

25V

12PF

CERM

5%

C8813

1

2

0201

25V

12PF

CERM

5%

C8814

1

2

5% CERM

25V

12PF

0201

C8815

1

2

25V 0201

C0G-CERM

3.3PF

+/-0.1PF

NOSTUFF

C8816

1

2

54

201

1/20W

5%

10K

MF

R8803

1

2

201

MF

1/20W

5%

10K

R8804

1

2

CSP

OMIT_TABLE

64MB-SPI

W25Q64FWBYIG-MX25U6435F

U8800

C2 A3

D2 B3

B2

A1 B1

F1 F4

C1 D1 A4 B4 C4 D4

AA1 AA4

A2D3

C3

55 70

55

70

55 70

LGA

NAND-XXNM-XGBX8-MLC-SSD-64G

OMIT_TABLE

U8801

J7

E7

N1

A1

L1 C1 J1 E1 H2 F2

L7

C7

M4 L3

B4 C3

D4

K4

OA0

OB8

OE8

OF0

N3

A3

N5

A5

M2

B2

M6

B6

L5

C5

K6

D6

K2

D2

J3

E3

G7 G1

G0 G5

H6

J5 H4

E5 F4

OA8

OC0

OD0

OF8

OB0

OC8

OD8

OE0

G3

G8

N7

A7

F6

5% CERM

12PF

25V 0201

C8809

1

2

55 70

55

70

55 70

X7R

6.3V

0.1UF

10%

0201

C8800

1

2

6.3V

X6S-CERM

0.22UF

0201

20%

C8801

1

2

6.3V

20% X5R

0201-1

1.0UF

C8802

1

2

6.3V X6S

20%

2.2UF

0402

C8803

1

2

55 70

55

70

55 70

56 58

55 70

201

MF

47K

1/20W

5%

R8800

1

2

1K

1/20W MF

5%

201

R8801

1

2

55 70

55

70

55 70

SSD NAND Flash & ROM

SYNC_DATE=10/07/2013

SYNC_MASTER=J92_SSD

ANI1_IO<6>

ANI1_IO<1>

ANI6_IO<6>

ANI6_IO<5>

ANI6_IO<2>

ANI6_IO<0>

ANI6_IO<4>

SSD_I2C_SDA

PP1V8_S0SW_SSD_COLD

SSD_I2C_SCL

SSD_SPI_MOSI

PP1V8_S0SW_SSD_COLD

NAND_WP_L

SSD_SPI_MISO

SSD_SPI_SCLK SSD_SPI_CS_L

ANI1_IO<7>

ANI6_IO<7>

ANI1_IO<0>

ANI1_IO<2> ANI1_IO<3> ANI1_IO<4> ANI1_IO<5>

ANI6_IO<1>

ANI6_IO<3>

ANI_VREF

NAND_WP_L

NAND_RB_L

ANI1_NCE<2>

ANI6_NCE<0> ANI6_CLE ANI6_ALE ANI6_NWE

ANI6_NRE_N ANI6_NRE_P

ANI6_DQS_P ANI6_DQS_N

ANI1_NCE<0>

ANI1_ALE

ANI1_CLE

ANI1_NWE

ANI1_NRE_N ANI1_NRE_P

ANI1_DQS_P

ANI6_NCE<1> ANI1_NCE<1> ANI6_NCE<2>

ANI6_NCE<3> ANI1_NCE<3>

ANI1_DQS_N

NAND_RB_L

ANI7_NCE<2>

ANI0_DQS_N

ANI0_NCE<0>

ANI0_IO<2>

ANI0_IO<6>

ANI7_NCE<3>

ANI7_NCE<0>

ANI7_ALE ANI7_NWE

ANI7_NRE_P

ANI7_NRE_N

ANI_VREF

ANI7_IO<2>

ANI7_IO<1>

ANI7_IO<0>

ANI7_IO<5> ANI7_IO<6>

ANI0_CLE

ANI0_NRE_P

ANI0_NCE<1> ANI7_NCE<1> ANI0_NCE<2>

ANI0_NCE<3>

ANI0_IO<7>

ANI0_IO<5>

ANI0_IO<0>

ANI0_DQS_P

ANI7_DQS_P ANI7_DQS_N

ANI0_NWE

ANI0_ALE

ANI0_NRE_N

ANI7_IO<7>

ANI0_IO<1>

ANI7_CLE

ANI0_IO<4>

ANI0_IO<3>

SSD_SPI_WP_L SSD_SPI_SIO3

PP1V8_S0SW_SSD_COLD

PP3V3_S0SW_SSD

ANI7_IO<3> ANI7_IO<4>

PP3V3_S0SW_SSD

PP1V8_S0SW_SSD_COLD

<SCH_NUM>

88 OF 130

58 OF 75

17 23 50

54 56 58 59 60 64

17 23 50 54 56 58 59 60 64

58

17 23 50 54 56 58 59 60 64

47 50 58 59 60

17 23 50 54 56 58 59 60 64

WWW.AliSaler.Com

GPIO(20)

GPIO(19)

GPIO(18)

GPIO(8)

GPIO(9)

GPIO(10)

GPIO(7)

GPIO(6)

GPIO(5)

GPIO(4)

GPIO(17) GPIO(16)

GPIO(13) GPIO(12)

GND(11)

GPIO(15) GPIO(14)

VDD

GPIO(3)

GPI(2)

VER 1

OUT

IN

OUT

G

D

S

G

D

S

GND

VDD

D

SON

CAP

GND

VDD

D

SON

CAP

GND

VDD

D

SON

CAP

GND

VDD

D

SON

CAP

VIN

ON

GND

VOUT

IN

OUT

G

SYM_VER_1

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

LPDDR2 1.2V & 1.8V LOAD SWITCHES FOR SEQUENCING, SR SUPPORT

R (ON)

20 MOHM MAX

SSD 1.2V/1.8V HOT protection diode

S1X 3.3V Load Switch

SSD 1.1V Discharge FET

BTB DEBUG CONNECTOR

DISCHARGE

PART

65OHM TYP

CURRENT

85OHM MAX

SLG5AP1531V

SSD 3.3V Discharge FET

17 MOHM TYP

2.5A MAX

SILEGO GREEN PAK3 FOR POWER SEQUENCING, SR

1.0UF

20% X5R

0201-1

PLACE_NEAR=U8920.5:2.0MM

6.3V

C8950

1

2

PLACE_NEAR=U8903.5:2.0MM

X5R

6.3V 0201-1

20%

1.0UF

C8953

1

2

PLACE_NEAR=U8902.5:2.0MM

1.0UF

20% X5R

6.3V 0201-1

C8952

1

2

SLG46721V

OMIT_TABLE

STQFN

CRITICAL

U8990

11

2

10

12

13

14

15

16

17

181920

3 4 5 6 7

8

9

1

PLACE_NEAR=U8990.10:2.0MM

1/20W

100K

MF 201

5%

R8990

1

2

PLACE_NEAR=U8990.10:2.0MM

5% 1/20W MF

82K

201

R8991

1

2

PLACE_NEAR=U8990.10:2.0MM

10% 10V

0.01UF

X7R-CERM 0201

C8990

1

2

5% MF

201

1/20W

4.7K

R8918

1

2

54

50

15

15 64

15 64 50

59

54

DF40C-10DP-04V-51

M-ST-SM

CRITICAL

J8910

11

12

13 14

1

10

2

34 56 78 9

23 54 64

4.7K

1/20W

MF

5%

201

R8922

12

10K

5%

201

1/20W

MF

R8955

12

0201

0.01UF

10V

10% X7R-CERM

C8955

1

2

X5R 0201-1

6.3V

20%

NOSTUFF

1.0UF

C8954

1

2

201

5% MF

4.7K

1/20W

NOSTUFF

R8921

12

CRITICAL

BGA

SI8472DB

Q8950

4

1

23

SI8472DB

BGA

CRITICAL

Q8960

4

1

23

X7R-CERM 0201

10% 10V

0.01UF

C8965

1

2

201

1/20W

MF

5%

10K

R8965

12

CRITICAL

SLG5AP1531V

TDFN

U8903

73

8

25

1

SLG5AP1531V

CRITICAL

TDFN

U8920

73

8

25

1

0201-1

NOSTUFF

1.0UF

6.3V

20% X5R

C8970

1

2

SLG5AP1531V

TDFN

CRITICAL

U8901

73

8

25

1

NOSTUFF

20%

6.3V X5R 0201-1

1.0UF

C8971

1

2

SLG5AP1531V

TDFN

CRITICAL

U8902

73

8

25

1

1.0UF

0201-1

X5R

20%

NOSTUFF

6.3V

C8972

1

2

0.2

MF

1/6W

1%

0402

R8958

1

2

1/6W

1%

0.2

0402

MF

R8951

1

2

402

0.4

1% 1/6W MF

R8961

1

2

402

0.4

MF

1/6W

1%

R8968

1

2

NOSTUFF

SOD-962

PMEG1201AESF

D8900

AK

CRITICAL

TPS22904

CSP

U8999

B2

B1

A1

A2

PLACE_NEAR=U8920.1:2.0MM

0201

6.3V

10% X7R

0.1UF

C8975

1

2

PLACE_NEAR=U8901.5:2.0MM

20%

1.0UF

6.3V 0201-1

X5R

C8951

1

2

PLACE_NEAR=U8902.1:2.0MM

6.3V

0.1UF

0201

X7R

10%

C8976

1

2

6.3V X7R

10%

0.1UF

0201

PLACE_NEAR=U8901.1:2.0MM

C8977

1

2

PLACE_NEAR=U8903.1:2.0MM

10% X7R

6.3V

0.1UF

0201

C8978

1

2

31 37 43

46

DMN32D2LFB4

DFN1006H4-3

Q8990

3

1

2

201

10K

5%

1/20W

MF

R8992

1

2

IC,SLG4AP4547V,PWR RAIL SEQUENCER,STQFN-20

343S00030

U8990

1

CRITICAL

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=02/12/2014

SSD SR, Power, & Debug

PP3V3_S5

SAK_PP1V8_REF_P1V

PP3V3_S0SW_SSD

PP1V2_S3

SAK_SSD_SR_P1V8_EN

PP1V8_S0SW_SSD_HOT

SAK_SSD_PP1V1_EN

SSD_SR_EN_L

SAK_SSD_SR_P1V2_EN

SAK_SSD_P1V1_DISCHARGE_FB

SAK_SSD_P2V5LDO_P3V3S1X_EN

PP3V3_S0SW_S1X

PP1V8_S3

PP1V1_S0SW_SSD

PP1V2_S0SW_SSD_COLD

PP1V8_S3

PP3V3_S5

SAK_SSD_P3V3_DISCHARGE_FB

SSD_P1V2_COLD_SW_CAP

SSD_JTAG_MASTER_TDI SSD_JTAG_MASTER_TMS SSD_JTAG_MASTER_TCK

PP1V8_S0SW_SSD_COLD

SSD_JTAG_MASTER_NRST

SAK_SSD_P3V3_DISCHARGE

SAK_SSD_P3V3_DISCHARGE_FB

S1X_DEBUG_UART_R2D

SSD_UART_BOOT_L

SAK_SSD_P1V1_DISCHARGE

SAK_SSD_SR_P1V2_EN

PP1V2_S3

PP1V2_S0SW_SSD_HOT PP1V8_S0SW_SSD_HOT

SAK_SSD_P1V8_EN

SAK_SSD_P3V3_DISCHARGE_RC

SAK_SSD_P1V1_DISCHARGE

SAK_SSD_P1V1_DISCHARGE_FB

SAK_SSD_P1V1_DISCHARGE_RC

PP1V8_S0SW_SSD_COLD

PP3V3_S5

SAK_SSD_P2V5LDO_P3V3S1X_EN

SSD_P1V8_HOT_SW_CAP

PP3V3_S5

SSD_RESET_L

SAK_SSD_P1V2_EN

SSD_P1V2_HOT_SW_CAP

PP1V2_S0SW_SSD_HOT

SSD_P1V8_COLD_SW_CAP

PP1V8_S0SW_SSD_COLD

SAK_SSD_COLD_BOOT_L

SAK_SSD_SR_P1V8_EN

SSD_JTAG_MASTER_TDO

S1X_DEBUG_UART_D2R

SAK_SSD_P1V8_EN

SMC_RESET_L

SAK_SSD_PCIE_RESET_L

SSD_PWR_EN

SAK_SSD_P3V3_NAND_EN

PP3V3_S5

SAK_SSD_P1V2_EN

PAK_SMC_RESET

SAK_SSD_P3V3_DISCHARGE

PP1V8_S0SW_SSD_HOT

<SCH_NUM>

89 OF 130

59 OF 75

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

47 50 58 60

8

10 19 20

21 46 52 59 60 69

59 64

56 59 60

59 64

59

54 56 60

20 21 46 50 52 59 60

50 54 56 57 60

56 60

20 21 46 50 52 59 60

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

59

54

17 23 50 54 56 58 59 60 64

54

59

23 54 64

59

59 64

8

10 19 20 21

46 52 59 60 69

56 59 60 56 59 60

59 64

59

17 23 50 54 56 58 59 60 64

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

50 59

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

59 64 56 59 60

17 23 50 54 56 58 59 60 64

59 64

54

23 54 64

59 64

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

59 64

59

56 59 60

WWW.AliSaler.Com

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

"G3Hot" (Always-Present) Rails

5V Rails

3.3V Rails

? mA

2A max supply

SSD Rails

Digital Ground

1.8V/1.5V/1.2V/1.05V Rails

CPU "VCORE" RAILS

USB-C PWR (5.1V)

? mA

100 mA

29 64 68

SM

XWA001

12

29 64 68

SM

XWA002

12

SYNC_MASTER=J43_MLB

Power Aliases

SYNC_DATE=10/24/2012

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PPDCIN_G3H

PPBUS_G3H PPBUS_G3H

PP1V05_S4SW

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S4SW

PP1V05_SUS

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP1V05_SUS

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

PP1V05_S4SW

PP1V05_SUS

PP1V05_SUS PP1V05_SUS

PP1V05_SUS

PPBUS_G3H

PP1V8_S3

PP5V1_S4SW_CC1

PP5V1_S4SW

MIN_NECK_WIDTH=0.15 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V

PP3V3_S5

PP1V5_S0

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.3 mm

PP1V5_S0

PP3V3_S5 PP3V3_S5

PP3V3_S5

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.8V

PP1V8_S0SW_SSD_COLD

MIN_NECK_WIDTH=0.15 MM

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V2_S0SW_SSD_HOT

MIN_NECK_WIDTH=0.15 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP3V3_S0SW_S1XPP3V3_S0SW_S1X

MAKE_BASE=TRUE

PP2V5_S0SW_SSD

MIN_LINE_WIDTH=0.6 MM VOLTAGE=2.5V

MIN_NECK_WIDTH=0.15 MM

MIN_NECK_WIDTH=0.15 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP3V3_S0SW_SSDPP3V3_S0SW_SSD

PP3V3_S0SW_SSD

PP1V5_S0

PP1V2_S3

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PP1V05_S0

PP1V8_S0SW_SSD_COLD

PP1V1_S0SW_SSD

PP1V2_S0SW_SSD_HOT

PP1V8_S0SW_SSD_HOT

PP1V2_S0SW_SSD_COLD

PP1V1_S0SW_SSD

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.1V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0SW_SSD_HOT

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V2_S0SW_SSD_COLD

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PP1V8_S3

PP1V2_S3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM

MAKE_BASE=TRUE

VOLTAGE=1.2V

PP1V05_S0SW_PCH_USB3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0SW_PCH_SATA

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0SW_PCH_PCIE

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PPVBAT_G3H_CONN

PPVCC_S0_CPU

PP1V8_S3

PPVBAT_G3H_CONN

PP1V05_S0

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V8_S3

PP1V2_S3

PP1V05_S0SW_PCH_PCIE

PP1V05_S0SW_PCH_SATA

PP1V05_S0SW_PCH_USB3

PP1V5_S0

PP3V3_SUS

PP1V2_S3

PP2V5_S0SW_SSD

PP1V8_S0SW_SSD_COLD

PP1V05_S0SW_PCH_PCIE

PP1V8_S3

PP5V_S0

PP1V2_S3

PP2V5_S0SW_SSD

PP1V2_S0SW_SSD_HOT

PPVCC_S0_CPU

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.15 MM

PPVCC_S0_CPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP5V_S4

PP5V_S0

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.175 MM

PP5V1_S4SW

PP5V_S4

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_S4

PP3V3_S0

PP5V_S4

PP3V3_S5

PPDCIN_G3H

PP3V3_S5

E85_CC1

PP5V1_S4SW_CC1

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP5V1_S4SW_CC2

E85_CC2

PP5V1_S4SW_CC2

PP5V1_S4SW_CC1

MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V

PPVIN_G3H_P3V3G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PPVIN_G3H_P3V3G3H

PPBUS_S5_HS_COMPUTING_ISNS

PPVBUS_E85

MAKE_BASE=TRUE

VOLTAGE=20V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM

PPDCIN_G3H

MIN_NECK_WIDTH=0.1 MM VOLTAGE=20V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H

PP5V1_S4SW_CC2

PP1V2_S0SW_SSD_COLD

PP1V8_S0SW_SSD_COLD

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V8_S3

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP5V1_S4SW

VOLTAGE=5.1V

PP3V3_SUS

PP3V3_SUS PP3V3_SUS

PP3V3_SUS

PPBUS_S5_HS_COMPUTING_ISNS

MIN_NECK_WIDTH=0.2 MM

PPVRTC_G3H

VOLTAGE=3V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP5V_S0SW_LCD

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVRTC_G3H

PP5V_G3H_LDO

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_G3H_LDO

PP5V_S0SW_LCD

PP3V3R3V0_AON

PPBUS_G3H

PP3V3_G3H

PP3V3R3V0_AON

PP3V3R3V0_AON PP3V3R3V0_AON PP3V3R3V0_AON PP3V3R3V0_AON PP3V3R3V0_AON

PP3V3_S5

PPBUS_G3H

PPBUS_S5_HS_COMPUTING_ISNS PPBUS_S5_HS_COMPUTING_ISNS

PP3V3_G3H

PPVBUS_E85

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM

PP3V3R3V0_AON

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_G3H

PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H

PPBUS_G3H

PP3V3_SUS

PP3V3_S4 PP3V3_S4 PP3V3_S4

PP3V3_S4

PP3V3_S4 PP3V3_S4

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.6V

PPBUS_G3H

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_SUS

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_SUS

PP3V3_S0

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S0

PP3V3_S4

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM

MIN_NECK_WIDTH=0.075MM MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

GND

<SCH_NUM>

100 OF 130

60 OF 75

8

11 12 13

15 17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60

73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60

73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53

60 73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47

53 60 73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46

47 53 60 73 75

8

11 12 13 15

17 18 23 24 29 32 33 34 35 36 40

46 47 53 60 73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36

40 46 47 53 60 73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35

36 40 46 47 53 60 73 75

8

11 12 13 15

17 18 23 24 29 32

33 34

35 36 40 46 47 53 60 73 75

8

11 12 13 15

17 18 23 24 29 32

33

34 35 36 40 46 47 53 60 73

75

8

11 12 13 15

17 18 23 24 29

32

33 34 35 36 40 46 47 53 60 73

75

28 29 35 43 60

30 35 43 46 47 48 49 50 60

29 50 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

6 8

11 15 16 17

32 44 46 51 60

29 50 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

8

11 12 16

46 48 51 60

30 35 43 46 47 48 49 50 60

20 21 46 50 52 59 60

29 50 60

35 50 60

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

8

11 17 40

46 60

8

11 17 40

46 60

8

11 17 40

46 60

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75 8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

8

11 13 15

16 17 22 33 37 46

47 51 59 60 73 75

17 23 50 54 56 58

59 60 64

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

56 59 60

54 56 59 60

50 54 60

47 50 58 59 60

8

11 17 40

46 60

8

10 19 20

21 46 52 59 60 69

30 35 43 46 47 48 49 50 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

17 23 50 54 56 58

59 60 64

50 54 56 57 59 60

56 59 60

50 54 56 57 59 60

56 59 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

8

11 17 40

46 60

8

11 14 15

18 27 28 29 46 51

60

20 21 46 50 52 59 60

8

10 19 20

21 46 52 59 60 69

8

11 51 60

8

11 51 60

8

11 51 60

41

43 46 60

8

10 35 45

60

20 21 46 50 52 59 60

41 43 46 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

6 8

11 15 16 17

32 44 46 51 60

20 21 46 50 52 59 60

8

10 19 20

21 46 52 59 60 69

8

11 51 60

8

11 51 60

8

11 51 60

8

11 51 60

8

11 51 60

8

11 17 40

46 60

8

11 17 40

46 60

8

11 14 15

18 27 28 29 46 51 60

8

10 19 20

21 46 52 59 60 69

8

10 19 20

21 46 52 59 60 69

50 54 60

17 23 50 54 56 58

59 60 64

17 23 50 54 56 58 59 60 64

8

11 51 60

20

21 46 50 52 59 60

16 17 25 30 39 40 44 45 47 49 51 60

8

10 19 20

21 46 52 59 60 69

8

10 19 20

21 46 52 59 60 69

8

10 19 20

21 46 52 59 60 69

50 54 60

56 59 60

8

10 35 45

60

8

10 35 45

60

8

10 35 45

60

30 38

47 53 60 75

30 38 47 53 60 75

16 17 25 30 39 40 44 45 47 49 51 60

30 38 47 53 60 75

22 23 28 29 30 32 33 50 51 60

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

8

11 12 13

15 17 18 23 24 29

32 33 34 35 36 40 46 47 53 60

73 75

30 38 47 53 60 75

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

28 29 35 43 60

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

29 50 60

35 44 45 46 48 60

42 43 60 42 43 60

35 44 45 46 48 60

29 50 60

28 29 35 43 60

28 29 35 43 60 28 29 35

43 60

29 50 60

56 59 60

20 21 46 50 52 59 60

35 50 60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

8 11 14 15 18

27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

35 44 45 46 48 60

8

12 13 46 60

53 60

8

12 13

46 60

8

12 13 46 60

46 60 46

60

53 60

26 28 29 34 41 43

60

30 35 43 46 47 48

49 50 60

17 28 30 31 32 33 34 37 42 43 60

26 28 29 34 41 43 60

26 28 29 34 41 43

60

26 28 29 34 41 43 60

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

8

11 13 15

16 17 22 33 37 46 47

51 59 60 73 75

30 35 43 46 47 48 49 50 60

35 44 45 46 48 60

17 28 30 31 32 33

34 37 42

43 60

29 50 60

26 28 29 34 41 43 60

17 28 30 31 32 33 34 37 42 43 60

30 35 43 46 47 48 49 50 60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

22 23 28 29 30 32 33 50 51 60

30 35 43 46 47 48 49 50 60

30 35 43 46 47 48 49 50

60

8

11 14 15

18 27 28 29 46 51 60

8

11 14 15

18 27 28 29 46 51 60

8

11 12 13 15

17 18 23 24 29

32 33 34 35 36 40 46 47 53

60 73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60

73 75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53

60 73 75

8

11 12 13

15 17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 73

75

8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60

73 75

22 23 28 29 30 32 33 50 51 60

WWW.AliSaler.Com

IN

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IN IN IN

OUT OUT OUT OUT OUT OUT OUT OUT OUT

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IN IN IN

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IN IN IN

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IN IN IN

OUT

BIBI

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BI BI BI BI BI BI BI BI BI BI BI BI BI

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Memory Bit/Byte Swizzle

MAKE_BASEMAKE_BASE

LPDDR3 Command/Address

MAKE_BASE

7

20 69

7

20 69

7

20 69

7

20 61 69

7

20 61 69

20

69

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20 69

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21

69

21 69

21 64 69

7

21 61 69

7

21 64 69

21

69

21 69

7

21 61 69

21

69

21 69

7

21 61 69

7

20 61 69

7

61

7

61

7

20 61 69

7

21 61 69

7

61

7

61

7

21 61 69

7

69 20

20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

20 61 69

7

20 61 69

7

69 20

20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

69 20

7

20 61 69

7

20 61 69

7

20 61 69

7

20 61 69

7

69 20

7

69 20

7

69 20

21

7

21 61 69

21

7

21 61 69

7

21 61 69

21

7

69

7

69

7

69

7

69

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69

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69

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69

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69

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69

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69

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69

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7

69

7

69

7

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7

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69

7

69

7

69

7

69

7

69

7

21 61 69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

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69

7

69

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69

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69

7

69

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69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

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69

7

69

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69

7

69

7

64 69

7

69

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69

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69

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69

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69

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69

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69

7

69

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69

7

69

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7

69

7

69

7

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7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

69

7

21 61 69

7

21 61 69

7

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69

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64 69

7

64 69

7

69

7

69

7

69

7

69

7

69

7

69

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

Memory Signal Swaps

MEM_A_CAB<2>

TRUE

MEM_B_DQ<47>

TRUE

MEM_B_DQ<43>

TRUE

MEM_B_DQ<41>

TRUE

MEM_A_DQ<35>

TRUE

MEM_A_DQ<36>

MEM_B_ODT<0>

TRUE

MEM_B_CAB<3>

TRUE

MEM_B_DQ<18>

TRUE

MEM_A_DQ<4>

MEM_B_CAA<8>

TRUE

MEM_B_CAA<7>

TRUE

MEM_A_CAA<0>

TRUE

MEM_A_DQ<13>

TRUE

MEM_B_DQ<34>

TRUE

TP_LPDDR3_RSVD4

TRUE

TP_LPDDR3_RSVD2

TRUE

TP_LPDDR3_RSVD1

MAKE_BASE=TRUE

TP_CPU_MEMVTT_PWR_EN_LSVDDQ

MEM_A_CAA<1>

TRUE

MEM_A_CAA<4>

TRUE

MEM_A_CAA<8>

TRUE

MEM_A_CAB<0>

TRUE

MEM_A_CAA<9>

TRUE

MEM_A_CAB<1>

MEM_A_CAB<3>

TRUE TRUE

MEM_A_CAB<4>

MEM_A_CAB<6>

TRUE TRUE

MEM_A_CAB<7>

TRUE

MEM_A_CAB<8> MEM_A_CAB<9>

TRUE

MEM_A_ODT<0>

TRUE

MEM_B_CAA<0>

TRUE

MEM_B_CAA<1>

TRUE

MEM_B_CAA<2>

TRUE

MEM_B_CAA<3>

TRUE

MEM_B_CAA<4>

TRUE

MEM_B_CAA<5>

TRUE

MEM_B_CAA<6>

TRUE

MEM_B_CAA<9> MEM_B_CAB<0>

TRUE

MEM_B_CAB<4>

TRUE

MEM_B_CAB<8>

TRUE

MEM_B_CAB<9>

TRUE

MEM_B_CAB<1>

TRUE

MEM_B_CAB<2>

TRUE

TP_LPDDR3_RSVD3

MEM_A_CAB<5>

TRUE

MEM_B_CAB<7>

TRUE

MEM_B_CAB<6>

MEM_A_CAA<2>

TRUE

MEM_A_DQ<60>

TRUE

MEM_A_DQ<63>

TRUE

MEM_A_DQ<34>

TRUE

MEM_A_DQ<61>

TRUE

MEM_A_DQ<50>

TRUE

MEM_A_DQ<51>

TRUE

MEM_A_DQ<54>

TRUE

MEM_A_DQ<48>

TRUE

MEM_A_DQ<41>

TRUE

MEM_A_DQ<40>

TRUE

MEM_A_DQ<42>

TRUE

MEM_A_DQ<45>

TRUE

MEM_A_DQ<44>

TRUE

MEM_A_DQ<32>

TRUE

MEM_A_DQ<33>

TRUE

MEM_A_DQ<38>

TRUE

MEM_A_DQ<57>

TRUE

MEM_A_DQ<52>

TRUE

MEM_A_DQ<58>

TRUE

MEM_A_DQ<43>

TRUE

MEM_A_DQ<59>

TRUE

MEM_A_DQ<62>

MEM_A_DQ<39>

TRUE

MEM_B_DQ<53>

TRUE

MEM_B_DQ<50>

TRUE

MEM_B_DQ<51>

TRUE

MEM_B_DQ<35>

TRUE

MEM_B_DQ<39>

TRUE

MEM_B_DQ<37>

TRUE

MEM_B_DQ<40>

TRUE

MEM_B_DQ<44>

TRUE

MEM_B_DQ<45>

TRUE

MEM_B_DQ<32>

TRUE

MEM_B_DQ<38>

TRUE

MEM_B_DQ<33>

TRUE

MEM_B_DQ<36>

TRUE

MEM_A_DQ<37>

TRUE

MEM_A_DQ<12>

TRUE

MEM_A_DQ<8>

TRUE

MEM_A_DQ<15>

TRUE

MEM_A_DQ<0>

TRUE

MEM_A_DQ<6>

MEM_A_DQ<3>

TRUE

MEM_A_DQ<5>

TRUE

MEM_A_DQ<18>

TRUE

MEM_A_DQ<7>

TRUE

MEM_A_DQ<23>

TRUE

MEM_A_DQ<22>

TRUE

MEM_A_DQ<19>

TRUE

MEM_A_DQ<21>

MEM_A_DQ<24>

TRUE TRUE

MEM_A_DQ<29> MEM_A_DQ<26>

TRUE TRUE

MEM_A_DQ<28>

TRUE

MEM_A_DQ<25>

TRUE

MEM_A_DQ<31>

TRUE

MEM_A_DQ<27>

TRUE

MEM_A_DQ<14>

TRUE

MEM_A_DQ<2>

TRUE

MEM_A_DQ<1>

TRUE

MEM_B_DQ<13>

MEM_B_DQ<31>

TRUE

MEM_B_DQ<30>

TRUE

MEM_B_DQ<28>

TRUE

MEM_B_DQ<27>

TRUE

MEM_B_DQ<24>

TRUE

MEM_B_DQ<25>

TRUE

MEM_B_DQ<19>

TRUE

MEM_B_DQ<22>

TRUE

MEM_B_DQ<21>

TRUE

MEM_B_DQ<12>

TRUE

MEM_B_DQ<15>

TRUE

MEM_B_DQ<14>

MEM_A_DQS_N<3>

TRUE

MEM_A_DQS_P<7>

TRUE

MEM_A_DQS_P<4>

TRUE

MEM_A_DQS_P<3>

TRUE

MEM_A_DQS_N<2>

TRUE

MEM_A_DQS_P<2>

TRUE

MEM_A_DQS_N<1>

TRUE

MEM_A_DQS_P<1>

TRUE

MEM_A_DQS_N<0>

TRUE

MEM_A_DQS_P<0>

TRUE

MEM_A_DQS_N<7>

TRUE

MEM_A_DQS_N<6>

TRUE

MEM_A_DQS_P<6>

TRUE

MEM_A_DQS_N<5>

TRUE

MEM_A_DQS_P<5>

TRUE

MEM_A_DQS_N<4>

TRUE

MEM_A_DQ<46>

MEM_B_DQS_N<3>

TRUE

MEM_B_DQS_P<3>

TRUE

MEM_B_DQS_P<7>

TRUE

MEM_B_DQS_P<4>

TRUE

MEM_B_DQS_N<2>

TRUE

MEM_B_DQS_P<2>

TRUE

MEM_B_DQS_N<1>

TRUE

MEM_B_DQS_P<1>

TRUE

MEM_B_DQS_P<0>

TRUE

MEM_B_DQS_N<7>

TRUE

MEM_B_DQS_N<6>

TRUE

MEM_B_DQS_P<6>

TRUE

MEM_B_DQS_N<5>

TRUE

MEM_B_DQS_P<5>

TRUE

MEM_A_CAA<7>

MEM_A_CAA<6>

TRUE

MEM_A_CAA<5>

TRUE

MEM_A_DQ<20>

MEM_A_DQ<30>

TRUE

MEM_B_CAB<5>

TRUE

MEM_A_DQ<17>

TRUE

MEM_B_DQ<26>

TRUE

MEM_B_DQ<55>

TRUE

MEM_B_DQ<46>

TRUE

MEM_B_DQ<23>

MEM_B_DQS_N<0>

TRUE

MEM_A_DQ<10>

TRUE

MEM_A_DQ<9>

MEM_A_CAA<3>

TRUE

MEM_A_DQ<53>

TRUE

MEM_A_DQ<49>

TRUE

MEM_B_DQ<7>

TRUE

MEM_A_DQ<56>

TRUE

MEM_A_DQ<55>

TRUE

MEM_A_DQ<47>

MEM_A_DQ<11>

TRUE

MEM_B_DQ<8>

TRUE

MEM_B_DQ<17>

TRUE

MEM_B_DQ<20>

TRUE

MEM_B_DQ<29>

TRUE

MEM_B_DQ<2>

TRUE

MEM_B_DQ<4>

TRUE

MEM_B_DQ<1>

TRUE

MEM_B_DQ<5>

TRUE

MEM_B_DQ<0>

TRUE

MEM_B_DQ<6>

TRUE

MEM_B_DQ<58>

TRUE

MEM_B_DQ<56>

TRUE

MEM_B_DQ<61>

TRUE

MEM_B_DQ<63>

TRUE

MEM_B_DQ<59>

TRUE

MEM_B_DQ<57>

TRUE

MEM_B_DQ<60>

TRUE

MEM_B_DQ<49>

TRUE

MEM_B_DQ<52>

TRUE

MEM_B_DQ<54>

TRUE

MEM_B_DQ<10>

TRUE

MEM_A_DQ<16>

MEM_B_DQS_N<4>

TRUE

MEM_B_DQ<3>

TRUE

MEM_B_DQ<62>

TRUE

MEM_B_DQ<9>

TRUE

MEM_B_DQ<11>

TRUE

MEM_B_DQ<48>

TRUE

MEM_B_DQ<42>

TRUE

MEM_B_DQ<16>

=MEM_B_DQ<53>

=MEM_B_DQ<14>

=MEM_B_DQ<18>

=MEM_A_A<15>

=MEM_B_DQ<40>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_A_DQ<50>

=MEM_B_DQ<22>

=MEM_A_DQ<42>

=MEM_B_DQ<19> =MEM_B_DQ<20>

=MEM_B_DQ<54>

=MEM_B_DQ<29>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQ<28>

=MEM_A_A<5>

=MEM_A_DQ<23>

TP_LPDDR3_RSVD2

=MEM_A_A<1>

=MEM_B_DQ<50>

=MEM_B_DQ<48>

=MEM_B_DQ<10>

=MEM_B_DQ<16>

=MEM_B_DQ<60>

=MEM_A_DQ<57>

=MEM_B_DQ<51>

=MEM_A_DQ<46>

=MEM_A_DQ<10>

=MEM_B_DQ<17>

TP_LPDDR3_RSVD4

=MEM_A_DQ<1>

=MEM_A_DQ<16>

=MEM_A_DQ<45>

=MEM_A_DQ<44>

=MEM_A_DQ<43>

=MEM_B_DQ<26>

=MEM_B_DQ<23>

=MEM_A_A<6>

=MEM_A_A<9>

=MEM_B_A<10>

MEM_B_CAB<6>

=MEM_A_DQ<61>

=MEM_A_DQ<54>

=MEM_A_DQ<48>

=MEM_B_DQ<46>

=MEM_B_A<11>

=MEM_A_DQ<36>

=MEM_B_DQ<6>

=MEM_A_DQ<30>

=MEM_A_DQ<41>

=MEM_A_DQ<38>

=MEM_A_DQ<0>

=MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9>

=MEM_A_DQ<21>

MEM_B_DQ<32>

=MEM_B_DQS_P<7> =MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>

=MEM_B_DQS_N<5>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

=MEM_B_DQS_N<1>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<63> =MEM_B_DQS_P<0>

=MEM_B_DQ<62>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<55>

=MEM_B_DQ<49>

=MEM_B_DQ<43>

=MEM_B_DQ<41>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

=MEM_B_DQ<27>

=MEM_B_DQ<21>

=MEM_B_DQ<15>

=MEM_B_DQ<13>

=MEM_B_DQ<11>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<3>

=MEM_B_DQ<1>

=MEM_B_DQ<0>

=MEM_A_DQS_N<0> =MEM_A_DQS_P<1> =MEM_A_DQS_N<1> MEM_A_DQS_P<6> MEM_A_DQS_N<6> =MEM_A_DQS_P<3> =MEM_A_DQS_N<3> =MEM_A_DQS_P<4> =MEM_A_DQS_N<4> =MEM_A_DQS_P<5> =MEM_A_DQS_N<5> =MEM_A_DQS_P<6> =MEM_A_DQS_N<6> =MEM_A_DQS_P<7> =MEM_A_DQS_N<7>

=MEM_A_DQS_P<0>

=MEM_A_DQ<5>

=MEM_A_DQ<11>

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<17> =MEM_A_DQ<18> =MEM_A_DQ<19> =MEM_A_DQ<20>

=MEM_A_DQ<24> =MEM_A_DQ<25>

=MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQ<33> =MEM_A_DQ<34>

=MEM_A_DQ<40>

=MEM_A_DQ<49>

=MEM_A_DQ<51> =MEM_A_DQ<52> =MEM_A_DQ<53>

=MEM_A_DQ<55> =MEM_A_DQ<56>

=MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<60>

=MEM_A_DQ<62> =MEM_A_DQ<63>

TP_LPDDR3_RSVD3

MEM_B_ODT<0>

MEM_A_ODT<0>

=MEM_B_A<0>

=MEM_B_A<1>

=MEM_B_A<2>

=MEM_B_BA<0>

=MEM_B_WE_L =MEM_B_RAS_L

=MEM_B_CAS_L

=MEM_B_A<13>

=MEM_B_A<14>

=MEM_B_A<15>

=MEM_B_BA<2> MEM_B_CAA<6>

=MEM_B_A<7>

=MEM_B_A<6>

=MEM_B_A<9>

=MEM_B_A<5>

=MEM_A_A<0>

=MEM_A_A<10>

=MEM_A_A<2> MEM_A_CAB<6>

=MEM_A_BA<0>

=MEM_A_WE_L =MEM_A_RAS_L

=MEM_A_CAS_L

=MEM_A_A<13>

=MEM_A_A<7> =MEM_A_BA<2> MEM_A_CAA<6>

=MEM_A_A<14>

=MEM_B_DQ<52>

=MEM_B_DQ<61>

=MEM_A_DQ<37>

=MEM_B_DQ<35>

=MEM_A_DQ<22>

TP_LPDDR3_RSVD1

=MEM_A_DQ<6>

=MEM_A_DQ<4>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<12>

=MEM_A_DQ<47>

=MEM_B_DQ<34>

=MEM_B_DQ<36>

=MEM_A_DQ<31> =MEM_A_DQ<32>

TP_CPU_MEMVTT_PWR_EN_LSVDDQ

=MEM_A_DQ<26>

=MEM_B_DQ<24>

=MEM_A_A<8>

MEM_A_DQ<33>

=MEM_A_DQ<13>

=MEM_A_DQ<12>

=MEM_A_A<11>

=MEM_B_DQ<25>

=MEM_A_DQ<39>

=MEM_A_DQ<35>

=MEM_B_A<8>

=MEM_B_DQ<44> =MEM_B_DQ<45>

=MEM_B_DQ<47>

=MEM_B_DQ<42>

=MEM_A_DQ<3>

=MEM_B_DQ<7>

<SCH_NUM>

102 OF 130

61 OF 75

7

61

7

61

7

61

6

61

7

61

6

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IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAKE_BASE

27 28 29

50 62 64 27 28 29 50 62 64

J92 Signal Aliases

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=07/08/2014

TP_ULX_SSP_SPARE

CPU_VR_READY SMC_PCH_SUSWARN_L SMC_PCH_SUSACK_L SMC_BC_ACOK TP_ULX_SPARE1

QR_SWITCH_EN QR_SWITCH_EN

TRUE

SMC_PCH_SUSACK_L

TRUE

TP_LPC_CLK24M_LPCPLUS_R

CPU_VR_READY

TRUE

SMC_PCH_SUSWARN_L

TRUE

SMC_BC_ACOK

TP_ULX_SSP_SPARE

TRUE TRUE

TP_LPC_CLK24M_LPCPLUS_R HPM_I2C_INT_L

TRUE

HPM_I2C_INT_L

TRUE

TP_ULX_SPARE1

HPM_I2C_INT_L

SMC_TMS

TRUE

SMC_TMS

SMC_TCK SMC_TCK

TRUE

XDP_USB_EXTA_OC_L XDP_USB_EXTA_OC_L

TRUE

GND GND

TRUE

TP_HPM_XTALOUT TP_HPM_XTALOUT

TRUE

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_P

TRUE

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_N

TRUE

=PCIE_E85_D2R_P

PCIE_TBT_D2R_P<0>

TRUE

=PCIE_E85_R2D_P

PCIE_TBT_R2D_C_P<0>

TRUE

=PCIE_E85_D2R_N

PCIE_TBT_D2R_N<0>

TRUE

E85HSMUX_USB_EN

=PCIE_E85_R2D_N

PCIE_TBT_R2D_C_N<0>

TRUE

PCH_TBT_PCIE_RESET_L PCH_TBT_PCIE_RESET_L

TRUE

TBT_CLKREQ_L TBT_CLKREQ_L

TRUE

E85_TEST_MODE_L

TRUE

E85_TEST_MODE_L

MAKE_BASE=TRUE

E85HSMUX_USB_EN

<SCH_NUM>

103 OF 130

62 OF 75

5

62

8

44 62

13 31

62

13 31 62

31 32 35 43 62

5

62

15 28 62

64 15 28 62 64

13 31 62

12 62 68

8

44 62

13 31 62

31

32 35 43 62

5

62

12 62 68

13 28 62

64 13 28 62 64

5

62

13 28 62

64

26 31 32 37 62 26 31 32 37 62

14 16 28 62 63 64

28 62 28 62

12 29 62 64 68 12 29 62 64 68

29 14 68

15 29 62 15 29 62

12 29 62 12 29 62

28 29 62 64 28 29 62 64

WWW.AliSaler.Com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Nets with offpages not used on this project)

Unused nets with offpage

MAKE_BASE

NO_TEST

NO_TEST Nets

CPU/PCH

SMC

Func Test / No Test

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=07/08/2014

NC_SMC_FAN_1_CTL

TRUE TRUE

NC_SMC_FAN_1_CTL

TRUE

NC_SMC_FAN_1_TACH

TRUE

NC_SMC_FAN_1_TACH

TRUE TRUE

NC_SYS_ONEWIRENC_SYS_ONEWIRE

TRUE

NC_SMBUS_SMC_4_ASF_SDA

TRUE

NC_SMBUS_SMC_4_ASF_SDA

NC_SMBUS_SMC_4_ASF_SCL

TRUE TRUE

NC_SMBUS_SMC_4_ASF_SCL

NC_SMC_DEBUGPRT_EN_L

TRUETRUE

NC_SMC_DEBUGPRT_EN_L

NC_SMC_SYS_KBDLED

TRUETRUE

NC_SMC_SYS_KBDLED

NC_SMC_T25_EN_L

TRUE TRUE

NC_SMC_T25_EN_L

NC_SMC_GFX_THROTTLE_L

TRUE TRUE

NC_SMC_GFX_THROTTLE_L

NC_SMC_FAN_0_TACH

TRUE TRUE

NC_SMC_FAN_0_TACH

NC_SMC_SYS_LED

TRUE TRUE

NC_SMC_SYS_LED

TRUE TRUE

NC_DP_TBTSNK1_HPDNC_DP_TBTSNK1_HPD

NC_DP_TBTSNK1_AUXCH_CN

TRUETRUE

NC_DP_TBTSNK1_AUXCH_CN

NC_DP_TBTSNK1_AUXCH_CP

TRUETRUE

NC_DP_TBTSNK1_AUXCH_CP

NC_DP_TBTSNK1_DDC_DATA

TRUETRUE

NC_DP_TBTSNK1_DDC_DATA

NC_DP_TBTSNK1_DDC_CLK

TRUE TRUE

NC_DP_TBTSNK1_DDC_CLK

NC_DP_TBTSNK1_ML_CN<3..0>

TRUETRUE

=DP_TBTSNK1_ML_C_N<3..0>

NC_DP_TBTSNK1_ML_CP<3..0>

TRUETRUE

=DP_TBTSNK1_ML_C_P<3..0>

TRUETRUE

NC_PCIE_TBT_R2D_CP<1>

TRUETRUE

NC_PCIE_TBT_R2D_CN<1>

NC_CLINK_RESET_L

TRUE TRUE

NC_CLINK_RESET_L

NC_CLINK_DATA

TRUETRUE

NC_CLINK_DATA

NC_CLINK_CLK NC_CLINK_CLK

TRUETRUE

NC_PCI_PME_L

TRUE

NC_PCI_PME_L

TRUE

NC_USB_SDN

TRUETRUE

NC_USB_SDN

NC_USB_CAMERAN

TRUETRUE

NC_USB_CAMERAN

NC_HDA_SDIN1 NC_HDA_SDIN1

TRUETRUE

NC_USB_SDP

TRUE TRUE

NC_USB_SDP

NC_USB_CAMERAP

TRUETRUE

NC_USB_CAMERAP

NC_PCIE_TBT_R2D_CP<1> NC_PCIE_TBT_R2D_CN<1>

NC_PCIE_TBT_D2RP<1>

TRUETRUE

NC_PCIE_TBT_D2RP<1>

NC_PCIE_TBT_D2RN<1>

TRUE TRUE

NC_PCIE_TBT_D2RN<1>

NC_PCIE_CLK100M_SDP

TRUE TRUE

NC_PCIE_CLK100M_SDP

NC_PCIE_CLK100M_SDN

TRUE TRUE

NC_PCIE_CLK100M_SDN

SD_RESET_L SD_PWR_EN ENET_MEDIA_SENSE BT_PWRRST_L TPAD_USB_IF_EN

TBT_PWR_EN

PCH_GPIO12

JTAG_TBT_TMS_PCH

TBT_CIO_PLUG_EVENT_L

ODD_PWR_EN_L

HDMITBTMUX_LATCH

HDMITBTMUX_FLAG

LCD_PSR_EN

CAM_SENSOR_WAKE_L

XDP_USB_EXTA_OC_L

MIKEY_SPI_CS_L

AUD_WAKE_L

MIKEY_SPI_MISO

MIKEY_SPI_CLK

MIKEY_SPI_MOSI

<SCH_NUM>

104 OF 130

63 OF 75

31 63 31 63

31

63 31 63

31 63 64 31 63 64

31 63 31 63

63 63

31 63 31 63

63 63

31 63 31 63

13 63 13 63

5

63

14 63 14 63

14

63 14 63

14 63 14 63

13 63 13 63

14 63 14 63

12 63 12 63

14 63 14 63

63

63 63

12 63 12 63

15

13

15

24

14 16 28 62 64

15

WWW.AliSaler.Com

PP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Unused nets with offpage

(Nets with offpages not used on this project)

NO_TEST Nets

MAKE_BASE

NO_TEST

MAKE_BASE

NO_TEST

CPU/PCH

EE Chaz Probe Points

I770

SM

P2MM

PPA501

1

P2MM

SM

PPA502

1

P2MM

SM

PPA503

1

P2MM

SM

PPA504

1

P2MM

SM

PPA505

1

P2MM

SM

PPA506

1

SM

P2MM

PPA507

1

SM

P2MM

PPA509

1

SM

P2MM

PPA508

1

P2MM

SM

PPA510

1

P2MM

SM

PPA511

1

SM

P2MM

PPA513

1

P2MM

SM

PPA512

1

SM

P2MM

PPA514

1

SM

P2MM

PPA515

1

P2MM

SM

PPA519

1

SM

P2MM

PPA521

1

P2MM

SM

PPA520

1

P2MM

SM

PPA522

1

P2MM

SM

PPA523

1

SM

P2MM

PPA524

1

SM

P2MM

PPA529

1

P2MM

SM

PPA530

1

P2MM

SM

PPA531

1

SM

P2MM

PPA532

1

P2MM

SM

PPA533

1

SM

P2MM

PPA534

1

SM

P2MM

PPA535

1

SM

P2MM

PPA536

1

SM

P2MM

PPA537

1

P2MM

SM

PPA538

1

P2MM

SM

PPA539

1

P2MM

SM

PPA545

1

P2MM

SM

PPA546

1

P2MM

SM

PPA547

1

SM

P2MM

PPA548

1

P2MM

SM

PPA549

1

P2MM

SM

PPA550

1

SM

P2MM

PPA551

1

SM

P2MM

PPA552

1

SM

P2MM

PPA555

1

SM

P2MM

PPA556

1

P2MM

SM

PPA557

1

SM

P2MM

PPA558

1

SM

P2MM

PPA559

1

P2MM

SM

PPA560

1

SM

P2MM

PPA561

1

SM

P2MM

PPA562

1

P2MM

SM

PPA563

1

SM

P2MM

PPA564

1

SM

P2MM

PPA565

1

P2MM

SM

PPA566

1

SM

P2MM

PPA568

1

P2MM

SM

PPA569

1

SM

P2MM

PPA571

1

SM

P2MM

PPA570

1

SM

P2MM

PPA572

1

SM

P2MM

PPA573

1

P2MM

SM

PPA575

1

SM

P2MM

PPA576

1

SM

P2MM

PPA577

1

SM

P2MM

PPA578

1

P2MM

SM

PPA579

1

P2MM

SM

PPA592

1

P2MM

SM

PPA594

1

P2MM

SM

PPA595

1

P2MM

SM

PPA585

1

P2MM

SM

PPA596

1

P2MM

SM

PPA597

1

SM

P2MM

PPA586

1

P2MM

SM

PPA582

1

P2MM

SM

PPA581

1

P2MM

SM

PPA583

1

P2MM

SM

PPA584

1

SM

P2MM

PPA587

1

SM

P2MM

PPA516

1

SM

P2MM

PPA528

1

SM

P2MM

PPA527

1

P2MM

SM

PPA526

1

SM

P2MM

PPA525

1

SM

P2MM

PPA567

1

SM

P2MM

PPA574

1

SM

P2MM

PPA580

1

SM

P2MM

PPA588

1

SM

P2MM

PPA589

1

SM

P2MM

PPA590

1

P2MM

SM

PPA591

1

SM

P2MM

PPA593

1

0.15MM

SM

PPA5A0

1

SM

0.15MM

PPA5A1

1

SM

0.15MM

PPA5A2

1

SM

0.15MM

PPA5A3

1

SM

0.15MM

PPA5A4

1

SM

0.15MM

PPA5A5

1

SM

0.15MM

PPA5A6

1

SM

0.15MM

PPA5A7

1

SM

0.15MM

PPA5A8

1

SM

0.15MM

PPA5A9

1

SYNC_DATE=10/24/2012

SYNC_MASTER=J41_MLB

Project FCT/NC/Aliases

BBPD_VCONN_EN

USB_EXTA_N

BBPD_VCONN2_EN

BBPD_VCONN1_EN

BBPD_SPI_MOSI

BBPD_RX_L_TX_H

BBPD_RPD_EN

BBPD_PD_SEL_CC2

BBPD_PD_EN

BBPD_MISO_LS1V1

BBPD_IPU_EN

MEM_CAM_CS_L

PCH_BT_UART_CTS_L

TRUE TRUE

NC_PCIE_CLK100M_FWP

NC_USB3_EXTB_D2RP

MEM_B_CAA<0>

CPU_CATERR_L

TRUE TRUE

NC_SMC_FAN_4_CTL

PCIE_SSD_R2D_P<0..3>

MAKE_BASE=TRUE

=PCIE_SSD_R2D_P<0..3>

=PCIE_SSD_R2D_N<0..3>

SMC_BT_PWR_EN

MEM_B_CS_L<0>

CAMERA_PWR_EN

MAKE_BASE=TRUE

PP1V8_S0SW_SSD_COLD

PCIE_CAMERA_D2R_P

AGND_PMIC

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<0>

NC_USB_EXTBN

NC_USB_EXTBP

NC_USB_EXTBN

TRUETRUE

NC_USB_EXTBP

TRUETRUE

NC_USB_IRN

PMIC2_READY

SMC_CBC_ON

E85_LS_P<2>

USB_EXTA_P

MEM_CAM_A<8>

LCD_IRQ_L

E85HSMUX_USB_EN

PCH_UART1_D2R

XDP_USB_EXTB_OC_L

USB3_EXTA_D2R_N

AP_S0IX_WAKE_SEL

USB3_EXTA_D2R_P

I2C_PCH_1_SCL

DP_E85SNK_HPD

E85_LS_N<2>

E85_LS_N<1>

E85_LS_P<1>

E85_TEST_MODE_L

BT_DEV_WAKE

AP_PCIE_WAKE_L

E85_RFU<1>

E85_RFU<2>

E85_CC2

E85_CC1

HPM_I2C_INT_L

MAKE_BASE=TRUE

MCP_DC_CV45

TS_HIPWR_EN

MAKE_BASE=TRUE

TS_HIPWR_EN

TS_POWER_GATE_EN

MAKE_BASE=TRUE

TS_POWER_GATE_EN

SSD_PWR_EN

MAKE_BASE=TRUE

SSD_UART_BOOT_L

MAKE_BASE=TRUE

SSD_PWR_EN

SSD_UART_BOOT_L

TP_SMC_PWRFAIL_WARN_L

MAKE_BASE=TRUE

TP_SMC_PWRFAIL_WARN_L

SYSCLK_CLK32K_PMIC

MAKE_BASE=TRUE

SYSCLK_CLK32K_PMIC

P1V1_S0_DLPN_PGOOD P1V1_S0_DLPN_PGOOD

MAKE_BASE=TRUE

SYSCLK_CLK24M_CAMERA

MAKE_BASE=TRUE

SYSCLK_CLK24M_CAMERA

MAKE_BASE=TRUE

PCIE_SSD_R2D_N<0..3>

=PCIE_SSD_D2R_N<0..3>

PCIE_SSD_D2R_N<0..3>

MAKE_BASE=TRUE

=PCIE_SSD_D2R_P<0..3>

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<0..3>

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_N

MAKE_BASE=TRUE

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_P

MAKE_BASE=TRUE

S1X_DEBUG_UART_R2D

MAKE_BASE=TRUE

S1X_DEBUG_UART_R2D

PP1V8_S0SW_SSD_COLD

S1X_DEBUG_UART_D2R

MAKE_BASE=TRUE

S1X_DEBUG_UART_D2R

AGND_PMIC

AGND_PMIC AGND_PMIC AGND_PMIC

P3V3S3_EN

MAKE_BASE=TRUE

AP_S0IX_WAKE_L

AP_PCIE_DEV_WAKE

MEM_B_CLK_N<0>

SMC_CHGR_INT_L

NC_SYS_ONEWIRE

TRUETRUE

NC_PCIE_CLK100M_FWN

NC_PCIE_CLK100M_FWP NC_PCIE_CLK100M_FWN

SSD_SR_EN_L

XDP_USB_EXTA_OC_L

HDA_SDIN0

TRUE

NC_SYS_ONEWIRE

TRUE

NC_PMIC_CLK32K_XTALIN

TRUE

PCH_BT_UART_D2R

SYSCLK_CLK32K_PMIC

SYSCLK_CLK12M_SSD

NC_SMC_GFX_OVERTEMP

SSD_BOOT

BT_UART_CTS_L

PCH_UART1_R2D

PCIE_CLK100M_SSD_P

PCIE_CLK100M_TBT_P

SAK_SSD_SR_P1V2_EN

SAK_SSD_SR_P1V8_EN

SAK_SSD_P1V8_EN

SAK_SSD_P1V2_EN

TPAD_SPI_INT_L

SYSCLK_CLK12M_SMC

SYSCLK_CLK24M_CAMERA

SMC_OOB1_R2D_L

SMC_PROCHOT

SMC_SENSOR_PWR_EN

SMC_WIFI_PWR_EN

MEM_B_CLK_P<0>

EDP_BKLT_PWM

I2C_PCH_1_SDA

PCH_BT_UART_R2D

PCIE_CLK100M_SSD_N

PCIE_CAMERA_D2R_N

XDP_PCH_UART_SSD_L_BT_H

NC_USB3_EXTB_D2RN

TRUETRUE

NC_USB3_EXTB_D2RN

NC_USB3_EXTB_R2D_CP

TRUETRUE

NC_USB3_EXTB_R2D_CP

NC_USB3_EXTB_D2RP

TRUETRUE

NC_USB3_EXTB_R2D_CN

TRUETRUE

NC_USB3_EXTB_R2D_CN

TRUETRUE

NC_USB_IRP

NC_USB_TPADP

TRUETRUE

TRUE

NC_SMC_FAN_0_CTL

TRUE

NC_SMC_FAN_4_CTL

TPAD_SPI_CS_L

SMC_WAKE_SCI_L

PCIE_SSD_D2R_N<0>

PCIE_CLK100M_TBT_N

SMC_CLK32K_PMIC

QR_SWITCH_EN

AUD_PWR_EN

P1V05SUS_DRVH

MCP_DC_CV45

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_CAB<1>

MEM_B_CAA<3>

TRUE TRUE

NC_USB_TPADN

NC_SMC_FAN_0_CTL

NC_PMIC_CLK32K_XTALIN

TRUE

NC_SMC_GFX_OVERTEMP

TRUE

NC_USB_TPADN

NC_USB_TPADP

XDP_USB_EXTB_OC_L

NC_USB_IRP NC_USB_IRN

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_RX_L

TRUE

BT_UART_RTS_L

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<0>

MCP_RSVD_CK13

MAKE_BASE=TRUE

SMC_DEBUGPRT_TX_L

TRUE

SMC_DEBUGPRT_TX_L

TRUE

TP_ULX_DDR_VCCDDQGTP_ULX_DDR_VCCDDQG

MCP_RSVD_CK13

MEM_B_CAA<2>

P3V3S3_EN

<SCH_NUM>

105 OF 130

64 OF 75

28 29

14 26

67

29 50

28 29

29

28 29

24 25 71

15 23

12 64

14 64 67

21 61 69

6

31 66

31 64

23

66 54

54

22 31

7

21 69

15 24

17

23

50 54

56 58

59 60

64

14 25 68

46 48 64

14 64 66

14 64 67

14 64

67

14

64

67

14 64

46 48

31 43

26 29 68

14 26 67

24 25 71

15 53

27 28 29 50 62

15

14 16 64

14 29 67

15 22

14 29 67

15 28 34

18 28 33

26 29 68

28 29 62

22

26 29

29 60 68

13 28 62

28 31 43 64 28 31 43 64

28 43 64

15 59 64

23 54 59 64

15 59 64

23 54 59 64

31 64 31 64

17 46 64 17 46

64

46 64 46 64

17 24 64 68 17 24

64 68

23 66

54 14 64

66

54 14 64 66

12 54 64 66 12 54 64 66

12 54 64 66 12 54

64 66

23 54 59 64 23 54 59 64

17 23 50 54 56 58 59 60 64

23 54 59 64 23 54 59 64

46 48 64

46

64

15 22

13 22

7

21 69

31 43

31

63 64

12 64

15 59

14 16 28 62 63

12 40 68

31 63 64

46 64

15 23

17 46 64

17 54

31 64

13 23

22 23

15

12 54 64 66

12 29 62 68

59

15 30

17 31

17 24 64 68

31 54

31 32

31 33 35

22 31

7

21 69

13 53

15

28 34

15 23

12 54 64 66

14 25 68

12 16

14 64

67

14 64 67

14 64 67 14 64 67

14 64

67

31 64

15 30

15 31

14 64 66

12 29 62 68

31 32

15 28 62

13 40

48

8

64

7

21 69

7

21 69

21 61

69

21 61 69

14 64 67

31 64

46 64

31 64

14 64 67

14 16 64

14 64

26 31 32 64 67 26 31 32 64 67

22 23

7

61 69

7

61 69

7

61 69

26 31

32 64 67 26 31 32 64 67

7

64

7

64

6

64

21 61 69

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TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Single-ended Physical Constraints

Note: 80ohm copied from 85ohm (pending stack-up calcs)

Spacing Constraints

J92 Board-Specific Spacing & Physical Constraints

Differential Pair Physical Constraints

=STANDARD

70_OHM_DIFF

0.080 MM 0.080 MMISL8

Y

0.085 MM 0.085 MM

ISL6

Y

0.080 MM 0.080 MM

=STANDARD

70_OHM_DIFF

0.082 MM 0.082 MM

TOP,BOTTOM

Y

0.060 MM 0.100 MM 0.100 MM

70_OHM_DIFF

0.147 MM

0.081 MM

70_OHM_DIFF

Y

=STANDARD

0.080 MM 0.080 MM

ISL10

0.081 MM

=STANDARD

*

100 MM 100 MM

70_OHM_DIFF

=STANDARD=STANDARD

N

=STANDARD

100 MM100 MM

N*

=STANDARD =STANDARD

50_OHM_SE_RF

0.099 MM

Y

85_OHM_DIFF

TOP,BOTTOM

0.100 MM0.060 MM 0.100 MM

0.057 MM

ISL10

85_OHM_DIFF

Y

=STANDARD

0.057 MM 0.100 MM 0.100 MM

PCB Rule Definitions

SYNC_DATE=10/24/2012

SYNC_MASTER=J43_MLB

16.5

MM

NO_TYPE,BGA,MEM_TERM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

=DEFAULT=DEFAULT

*

=DEFAULT=DEFAULT=DEFAULTSTANDARD =DEFAULT

*

100 MM 100 MM

N

=STANDARD=STANDARD=STANDARD

27P4_OHM_SE

TOP,BOTTOM

0.144 MM0.144 MM

Y

40_OHM_SE

ISL8 0.073 MM0.073 MM

Y

40_OHM_SE

0.071 MM0.071 MM

ISL10

Y

40_OHM_SE

=STANDARD40_OHM_SE =STANDARD=STANDARD

*N

100 MM100 MM

0.090 MM0.090 MM

TOP,BOTTOM

Y

55_OHM_SE

50_OHM_SE =STANDARD =STANDARD=STANDARD

*N

100 MM 100 MM

0.095 MM0.095 MM

Y

50_OHM_SE

TOP,BOTTOM

100 MM

=STANDARD =STANDARD45_OHM_SE

*N

100 MM

=STANDARD

DEFAULT

Y

=45_OHM_SE =45_OHM_SE

ISL6,ISL8,ISL10

?*

1:1_SPACING

0.100 MM

?

TOP,BOTTOM

1x_DIELECTRIC

0.057 MM

?

1x_DIELECTRIC

ISL4,ISL9

0.054 MM

1x_DIELECTRIC?ISL5,ISL8

0.058 MM

?

0.051 MM

ISL6,ISL7

1x_DIELECTRIC

80_OHM_DIFF

=STANDARD =STANDARD=STANDARD

N*

100 MM 100 MM

80_OHM_DIFF

=STANDARD

Y

ISL8 0.060 MM 0.060 MM 0.100 MM 0.100 MM

80_OHM_DIFF

0.060 MM 0.100 MM

TOP,BOTTOM

Y

0.099 MM 0.100 MM

80_OHM_DIFF

0.100 MM

=STANDARD

Y

0.058 MM 0.058 MM

ISL6,ISL9,ISL11

0.100 MM

27P4_OHM_SE

0.134 MM

ISL6,ISL8,ISL10

Y

0.134 MM

ISL6 0.057 MM0.057 MM

Y

45_OHM_SE

0.058 MM0.058 MMISL8

Y

45_OHM_SE

0.057 MM0.057 MM

ISL10

Y

45_OHM_SE

0.120 MM

TOP,BOTTOM

Y

0.095 MM

*

=DEFAULT

?

STANDARD

?

0.075 MM

BGA_P075MM

*

P070MM_BGA

5 MM 0.075 MM0.070 MM

*

P070MM_BGA

BGA

*

DEFAULT

*

0.1 MM

?

BGA

BGA_P075MM

**

?

1x_DIELECTRIC

0.057 MM

ISL3,ISL10

1x_DIELECTRIC?ISL2,ISL11

0.057 MM

80_OHM_DIFF

=STANDARD

Y

ISL10

0.101 MM 0.101 MM0.056 MM 0.056 MM

0.060 MM0.060 MMISL8

Y

=STANDARD

85_OHM_DIFF

0.100 MM0.100 MM

0.058 MM0.058 MM

Y

=STANDARD

0.100 MM

85_OHM_DIFF

ISL6,ISL9,ISL11

0.100 MM

100 MM 100 MM

*N

85_OHM_DIFF

=STANDARD =STANDARD =STANDARD

0.260 MM0.310 MM

TOP,BOTTOM

Y

27P4_OHM_SE

0 MM

*

100 MM100 MM

10 MM

0 MM

Y

DEFAULT

ISL3,ISL4

Y

=45_OHM_SE

DEFAULT

=45_OHM_SE

TOP,BOTTOM

DEFAULT

=50_OHM_SE

Y

=50_OHM_SE

27P4_OHM_SE

ISL3,ISL4

Y

0.190 MM0.190 MM

Y

TOP,BOTTOM

50_OHM_SE_RF 0.225 MM 0.225 MM

100 MM

=STANDARD=STANDARD55_OHM_SE

*N

100 MM

=STANDARD

ISL6 0.070 MM0.070 MM

Y

40_OHM_SE

<SCH_NUM>

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TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1

NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

(FSB_CPURST_L)

CPU PCIE Spacing

PCIE Clock Spacing

PCH PCIE Spacing

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

Note: CPU_8MIL and CPU_ITP can be converted

back to TABLE_SPACING_RULE

once rdar://10308147 is resolved

Note: DisplayPort tables are on Page 113

DP

CPU Net Properties

PHYSICAL

NET_TYPE

SPACING

PCIe SSD

PCI-Express Interface Constraints

ELECTRICAL_CONSTRAINT_SET

CPU Signal Constraints

Note: 80ohm constraints are actually 85ohm

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206 I207

I208

I214

I215

CLK_PCIE_2OTHER

?*

=6x_DIELECTRIC

SYNC_DATE=07/08/2014

SYNC_MASTER=J92_DEVMLB

CPU Constraints

=STANDARD

=45_OHM_SE=45_OHM_SE =45_OHM_SE

CPU_45S

=STANDARD

*

=45_OHM_SE

=27P4_OHM_SE 0.100 MM=27P4_OHM_SE=27P4_OHM_SE

CPU_27P4S

*

0.100 MM

=27P4_OHM_SE

=STANDARD

CPU_AGTL

* ?

=80_OHM_DIFF =80_OHM_DIFFPCIE_80D

*

=80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF

CPU_COMP

CPU_COMP_2OTHER

**

CPU_COMP CPU_COMP

*

CPU_COMP_2SELF

=5x_DIELECTRIC

TOP,BOTTOM

?

PCIE_RX2OTHERRX

PCIE_2OTHER

**

PCIE_CPU_TX

PCIE_2OTHERHS

*_RX

PCIE_CPU_TX

*

**

CPU_8MIL_2ANY

CPU_8MIL

TOP,BOTTOM

CPU_AGTL

=2x_DIELECTRIC

?

=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

*

CLK_PCIE_80D

=80_OHM_DIFF

=80_OHM_DIFF=80_OHM_DIFF

=4x_DIELECTRIC

?*

CLK_PCIE_2SELF

*

8 MIL

?

CPU_8MIL_2ANY

CPU_ITP_2ANY

?*

=4x_DIELECTRIC

PCIE_2OTHERHS

=4x_DIELECTRIC

* ?

?*

=4x_DIELECTRIC

PCIE_RX2OTHERRX

TOP,BOTTOM

=7x_DIELECTRIC

?

PCIE_TX2RX

CLK_PCIE_2SELF

CLK_PCIECLK_PCIE

*

TOP,BOTTOM?=10x_DIELECTRICCLK_PCIE_2OTHER

=6x_DIELECTRIC

PCIE_TX2RX

* ?

?*

PCIE_TX2OTHERTX

=4x_DIELECTRIC

* ?

PCIE_RX2RX

=2.5x_DIELECTRIC

*

=2.5x_DIELECTRIC

PCIE_TX2TX

?

=5x_DIELECTRIC

PCIE_2OTHER

TOP,BOTTOM

=6x_DIELECTRIC

?

TOP,BOTTOM

PCIE_2OTHERHS

=7x_DIELECTRIC

?

TOP,BOTTOMPCIE_RX2TX

=5x_DIELECTRIC

TOP,BOTTOM

?

PCIE_TX2OTHERTX

?

=5x_DIELECTRIC

TOP,BOTTOMPCIE_TX2TX

PCIE_TX2TX

*

PCIE_PCH_TX PCIE_PCH_TX

PCIE_PCH_RXPCIE_PCH_RX

*

PCIE_RX2RX

PCIE_TX2OTHERTX

*_PCH_TX

PCIE_PCH_TX

*

*_PCH_RX

PCIE_RX2OTHERRX

*

PCIE_PCH_RX

PCIE_PCH_TX

*

*_RX

PCIE_2OTHERHS

*_TX

PCIE_2OTHERHS

*

PCIE_PCH_RX

*_TX

*

PCIE_2OTHERHS

PCIE_PCH_TX

PCIE_TX2RX

*

*_PCH_RX

PCIE_PCH_RX

PCIE_RX2TX

*

*_PCH_TX

PCIE_PCH_RX

PCIE_2OTHERHS

*

*_RX

*

PCIE_2OTHER

*

PCIE_PCH_TX

PCIE_2OTHER

**

PCIE_PCH_RX

*

PCIE_2OTHER

*

PCIE_CPU_RX

*_RX

PCIE_2OTHERHS

*

PCIE_CPU_RX

*

*_TX

PCIE_CPU_RX

PCIE_2OTHERHS

PCIE_TX2OTHERTX

*

PCIE_CPU_TX

*_CPU_TX

PCIE_CPU_RX

*

PCIE_RX2OTHERRX

*_CPU_RX

PCIE_CPU_RX

PCIE_RX2RX

*

PCIE_CPU_RX

PCIE_CPU_TX

PCIE_TX2TX

*

PCIE_CPU_TX

PCIE_2OTHER

?

*

=3x_DIELECTRIC

=6x_DIELECTRIC

?

PCIE_RX2TX

*

CLK_PCIE_2OTHER

*

CLK_PCIE

*

PCIE_2OTHERHS

*

*_TX

PCIE_CPU_TX

*_CPU_TX

PCIE_CPU_RX

PCIE_RX2TX

*

PCIE_CPU_TX

*_CPU_RX

*

PCIE_TX2RX

CPU_VCCSENSE

**

CPU_VCCSENSE_2OTHER

CPU_VCCSENSE_2SELF

=6x_DIELECTRIC

TOP,BOTTOM

?

CPU_COMP_2OTHER

?*

=6x_DIELECTRIC

TOP,BOTTOM?=6x_DIELECTRICCLK_PCIE_2SELF

?*

=4x_DIELECTRIC

CPU_VCCSENSE_2SELF

=6x_DIELECTRIC

TOP,BOTTOM

?

CPU_COMP_2SELF

=10x_DIELECTRIC

?

CPU_COMP_2OTHER

TOP,BOTTOM

?

=5x_DIELECTRIC

PCIE_RX2RX

=10x_DIELECTRIC

TOP,BOTTOM

?

CPU_VCCSENSE_2OTHER

CPU_ITP

CPU_ITP_2ANY

**

CPU_COMP_2SELF

?*

=4x_DIELECTRIC

?*

=6x_DIELECTRIC

CPU_VCCSENSE_2OTHER

CPU_VCCSENSE

*

CPU_VCCSENSE_2SELF

CPU_VCCSENSE

CLK_PCIECLK_PCIE_80D

PCIE_CLK100M_SSD

PCIE_CLK100M_SSD_N

CPU_ITPCPU_45S

XDP_CPU_PRDY_L

CPU_VIDALERT_L

CPU_45S

CPU_SVIDALERT_L

CPU_COMP

CPU_VIDSCLK

CPU_SVIDSCLK

CPU_45S

CPU_COMP

PCIE_80D

PCIE_CPU_TX

PCIE_SSD_R2D_P<3..0>

PCIE_SSD_R2D_C_N<3..0>

PCIE_80D

PCIE_CPU_TX

PCIE_CPU_SSD_R2D

DP_INT_ML

DP_80D

DP_TX

DP_INT_ML_P<3..0>

DP_80D

DP_TX

DP_INT_ML_C_P<3..0>

DP_TX

DP_80D

DP_TBTSNK1_ML_C_N<3..0>

PCIE_CPU_SSD_R2D

PCIE_SSD_R2D_C_P<3..0>

PCIE_CPU_TX

PCIE_80D

CPU_VIDSOUT

CPU_SVIDSOUT

CPU_45S

CPU_COMP

CPU_VCCSENSECPU_VALSENSE

CPU_27P4S

CPU_VCC_VALSENSE_N

DP_INT_AUXCH

DP_80D DP_AUX

DP_INT_AUX_CH_C_P

DP_INT_AUXCH_C_N

DP_AUXDP_80D

DP_INT_AUXCH

DP_AUXDP_80D

DP_INT_AUX_P

DP_80D DP_AUX

DP_INT_AUXCH_C_P

DP_INT_AUXCH

DP_80D DP_AUX

DP_INT_AUX_CH_C_N

DP_80D

DP_TX

DP_INT_ML_C_N<3..0>

DP_INT_ML

DP_80D

DP_TX

DP_INT_ML_N<3..0>

DP_AUX

DP_TBTSNK1_AUXCH_C_N

DP_80D

DP_AUXDP_80D

DP_TBT_AUXCH

DP_TBTSNK1_AUXCH_N

DP_AUXDP_80D

DP_TBTSNK1_AUXCH_C_P

DP_TX

DP_80D

DP_TBTSNK1_ML_C_P<3..0>

DP_TX

DP_TBT_ML

DP_80D

DP_TBTSNK1_ML_P<3..0>

DP_TX

DP_TBT_ML

DP_80D

DP_TBTSNK1_ML_N<3..0>

DP_AUXDP_80D

DP_TBTSNK0_AUXCH_C_N

CPU_VALSENSE CPU_VCCSENSE

CPU_AXG_VALSENSE_P

CPU_27P4S

DP_AUXDP_80D

DP_INT_AUX_N

PCIE_CPU_RX

PCIE_SSD_D2R_C_P<3..0>

PCIE_80D

PCIE_CPU_RX

PCIE_CPU_SSD_D2R

PCIE_SSD_D2R_P<3..0>

PCIE_80D

PCIE_CPU_RX

PCIE_CPU_SSD_D2R

PCIE_SSD_D2R_N<3..0> PCIE_CLK100M_SSD_P

CLK_PCIECLK_PCIE_80D

PCIE_CLK100M_SSD

CPU_PECI CPU_COMP

CPU_PECI

CPU_45S

PM_MEM_PWRGD CPU_AGTL

PM_MEM_PWRGD

CPU_45SPM_SYNC

CPU_AGTL

PM_SYNC

CPU_45S

XDP_DBRESET_L

CPU_ITP

CPU_ITPCPU_45S

XDP_CPU_PREQ_L

CPU_COMP

CPU_27P4S

EDP_COMP

CPU_COMP

CPU_27P4S

CPU_PEG_COMP

CPU_SM_RCOMP CPU_COMP

CPU_27P4S

CPU_SM_RCOMP<0>

CPU_SM_RCOMP CPU_COMP

CPU_SM_RCOMP<2>

CPU_27P4S

SENSE_1TO1_P2MM

CPU_VCCSENSE

CPU_VCCIOSENSE

CPU_VCCIOSENSE_P

CPU_VCCSENSECPU_VALSENSE

CPU_27P4S

CPU_VDDQ_SENSE_P

SENSE_1TO1_P2MM

CPU_VCCIOSENSE

CPU_VCCSENSE

CPU_VCCIOSENSE_N

CPU_VDDQ_SENSE_N

CPU_VALSENSE CPU_VCCSENSE

CPU_27P4S

CPU_AXG_VALSENSE_N

CPU_VCCSENSECPU_VALSENSE

CPU_27P4S

SENSE_1TO1_P2MM

CPU_VCCSENSE

CPU_AXG_SENSE

CPU_AXG_SENSE_N

SENSE_1TO1_P2MM

CPU_AXG_SENSE

CPU_VCCSENSE

CPU_AXG_SENSE_P

CPU_VCCSENSE_N

CPU_VCCSENSECPU_VCCSENSE

SENSE_1TO1_P2MM

CPU_CFG<19..4>

CPU_CFG CPU_ITPCPU_45S

CPU_45S

CPU_AGTL

CPU_VCCIO_SEL

CPU_45S

CPU_CATERR_L CPU_AGTL

CPU_CATERR_L

CPU_PWRGD

CPU_AGTL

CPU_PWRGD

CPU_45S

CPU_PROCHOT_L

CPU_AGTL

CPU_PROCHOT_L

CPU_45S

PM_THRMTRIP_L

CPU_8MIL

PM_THRMTRIP_L

CPU_45S

CLK_PCIECLK_PCIE_80D

ITPCPU_CLK100M

ITPCPU_CLK100M_P

ITPXDP_CLK100M_P

CLK_PCIE_80D

ITPCPU_CLK100M

CLK_PCIE

ITPCPU_CLK100M_N

CLK_PCIE_80D

ITPCPU_CLK100M

CLK_PCIECLK_PCIE_80D

ITPCPU_CLK100M

ITPXDP_CLK100M_N

CLK_PCIE

XDP_CPU_CLK100M_N

CLK_PCIE_80D

ITPCPU_CLK100M

CLK_PCIE_80D

ITPCPU_CLK100M

CLK_PCIE

XDP_CPU_CLK100M_P

CPU_ITP

XDP_CPU_TCK

CPU_45SXDP_TCK

XDP_BPM_L<7..2>

CPU_45S CPU_ITP

CPU_ITPCPU_45S

XDP_BPM_L<1..0>

XDP_BPM_L

XDP_OBSDATA_B<3..0>

CPU_45S CPU_ITP

CPU_CFG<2..0>

CPU_CFG CPU_ITPCPU_45S

DMI_CLK100M

CLK_PCIE

DMI_CLK100M_CPU_P

CLK_PCIE_80D

CPU_VCCSENSE CPU_VCCSENSE

SENSE_1TO1_P2MM

CPU_VCCSENSE_P

XDP_CPURST_L

CPU_ITPCPU_45S

XDP_TRST_L

XDP_CPUPCH_TRST_L

CPU_ITP

XDP_CPU_TDO

CPU_45SXDP_TDO

CPU_ITPCPU_45S

XDP_CPU_TDI

XDP_TDI

CLK_PCIECLK_PCIE_80D

DPLL_REF_CLK120M

DPLL_REF_CLKN

CLK_PCIECLK_PCIE_80D

DPLL_REF_CLK120M

DPLL_REF_CLKP

CLK_PCIE_80D CLK_PCIE

DMI_CLK100M_CPU_N

DMI_CLK100M

CPU_COMP

CPU_27P4S

CPU_SM_RCOMP

CPU_SM_RCOMP<1>

DP_E85SNK_AUXCH_P

DP_AUX

DP_TBT_AUXCH

DP_80D

PCIE_80D

PCIE_CPU_TX

PCIE_SSD_R2D_N<3..0>

CPU_27P4S

CPU_VCCSENSE

CPU_VCC_VALSENSE_P

CPU_VALSENSE

XDP_CPU_TMS

XDP_TMS CPU_ITPCPU_45S

CPU_CFG<3>

CPU_CFG3

CPU_45S CPU_ITP

DP_AUXDP_80D

DP_TBTSNK0_AUXCH_C_P

DP_AUX

DP_TBT_AUXCH

DP_80D

DP_TBTSNK1_AUXCH_P

DP_E85SNK_AUXCH_N

DP_AUX

DP_TBT_AUXCH

DP_80D

PCIE_CPU_RX

PCIE_80D

PCIE_SSD_D2R_C_N<3..0>

<SCH_NUM>

111 OF 130

66 OF 75

12 54 64

6

16

8

44

8

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23 64

14 23

53

5

53

14 23

8

44

5

53

5

53

5

53

13 29

53

54

14 64

12

54 64

6

32

16 17

6

16

6

9

44

6

16

6

31 64

6

31 32 44

15 31 32

6

16

6

16

6

16

6

16

8

44

16

6

12 16

6

16

6

16

6

26 29

23 64

6

16

6

16

13 29

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54

WWW.AliSaler.Com

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

I/O Port Host USB

USB EXTC nets (Left USB port)

PHYSICAL

USB EXTB nets (Left USB port)

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 3.0 Interface Constraints

SPACING

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

ELECTRICAL_CONSTRAINT_SET

SATA Interface Constraints

E85 Interface Constraints

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB 2.0 Interface Constraints

UART Interface Constraints

NET_TYPE

PCH Net Properties

I/O Port Device USB

Internal USB

I/O Port DCI

TP SPI

Note: 80ohm constraints are actually 85ohm

PCH Constraints 1

SYNC_MASTER=DEV_MLB

SYNC_DATE=04/17/2014

=4x_DIELECTRIC

* ?

E85_CC

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

USB_80D

=80_OHM_DIFF

*

=80_OHM_DIFF=80_OHM_DIFF

USB_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

*

=45_OHM_SE =45_OHM_SE=45_OHM_SE

*

UART_45S

=45_OHM_SE =45_OHM_SE =45_OHM_SE

=2x_DIELECTRIC

* ?

UART

*_PCH_RX

*

USB3_PCH_TX

USB3_TX2RX

=2x_DIELECTRIC

*USB ?

=6x_DIELECTRIC

?

TOP,BOTTOM

E85_CC

=4x_DIELECTRIC

E85_LS

?*

E85_LS_85D

=85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFFSATA_80D

*

=4x_DIELECTRIC

?*

SATA_ICOMP

*

USB3_PCH_RX USB3_PCH_RX

USB3_RX2RX

*_PCH_RX

*

USB3_PCH_RX

USB3_RX2OTHERRX

=5x_DIELECTRIC

?

USB3_RX2OTHERRX

TOP,BOTTOM

?

TOP,BOTTOMUSB3_TX2RX

=7x_DIELECTRIC

=2.5x_DIELECTRIC

USB3_TX2TX

?*

**

USB3_PCH_TX USB3_2OTHER

USB3_2OTHERHS

*_RX

*

USB3_PCH_RX

**

USB3_PCH_RX USB3_2OTHER

USB3_2OTHERHS

*_RX

*

USB3_PCH_TX

USB3_2OTHERHS

*_TX

*

USB3_PCH_TX

USB3_2OTHERHS

*_TX

*

USB3_PCH_RX

USB3_TX2OTHERTX

*_PCH_TX

*

USB3_PCH_TX

*_PCH_TX

*

USB3_PCH_RX

USB3_RX2TX

*

USB3_PCH_TX USB3_PCH_TX

USB3_TX2TX

=4x_DIELECTRIC

USB3_2OTHERHS

?*

?

USB3_2OTHER

*

=3x_DIELECTRIC

USB3_RX2TX

?

=6x_DIELECTRIC

*

USB3_RX2OTHERRX

?

=4x_DIELECTRIC

*

USB3_TX2OTHERTX

?

=4x_DIELECTRIC

*

USB3_RX2RX

?

=2.5x_DIELECTRIC

*

=5x_DIELECTRIC

?

USB3_2OTHER

TOP,BOTTOM

TOP,BOTTOM?=6x_DIELECTRIC

USB3_2OTHERHS

TOP,BOTTOM

?

USB3_RX2TX

=7x_DIELECTRIC

=5x_DIELECTRIC

?

USB3_TX2OTHERTX

TOP,BOTTOM

?

USB3_RX2RX

=5x_DIELECTRIC

TOP,BOTTOM

=5x_DIELECTRIC

?

USB3_TX2TX

TOP,BOTTOM

=4x_DIELECTRIC

USB ?

*

E85_HS

?

=6x_DIELECTRIC

USB3_TX2RX

?

=6x_DIELECTRIC

*

E85_LS

TOP,BOTTOM?=6x_DIELECTRIC

=STANDARD =STANDARD

PCH_USB_RBIAS

8 MIL

=STANDARD

8 MIL

*

=STANDARD

E85_HS

TOP,BOTTOM

=10x_DIELECTRIC

?

E85_HS_85D

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

*

=85_OHM_DIFF

USB_BT_R_N

USB_80D

USB

USB_BT_R_P

USB_80D

USB

USB_80D

USB_BT_P

USB_BT

USB

USB_80D

USB_BT_N

USB_BT

UART

SMC_DEBUGPRT_TX_L

UART_45S

UART

SMC_DEBUGPRT_RX_L

UART_45S

USB_80D

USB3_EXTD_R2D_C_N

USB3_PCH_TX

USB_80D

USB3_EXTD_R2D_C_P

USB3_PCH_TX

USB_80D

USB3_EXTD_R2D_P

USB3_PCH_TX USB3_PCH_TX

USB_80D

USB3_EXTD_R2D_N

USB3_PCH_RX

USB3_EXTD_D2R_N

USB_80D

USB3_PCH_RX

USB3_EXTD_D2R_P

USB3_EXTA_R2D_C_P

USB_80D

USB3_PCH_TX

USB3_EXTA_R2D_C_N

USB_80D

USB3_PCH_TX

USB3_EXTA_TX

USB_80D

USB3_PCH_TX

USB3_EXTA_R2D_N

USB3_EXTA_D2R_C_N

USB3_PCH_RX

USB_80D

USB3_EXTA_D2R_C_P

USB_80D

USB3_PCH_RX

USB3_EXTA_D2R_P

USB3_PCH_RX

USB_80D

USB3_EXTA_RX

USB

USB_85D

USB_EXTA_F_P

USB_85D

USB

USB_EXTA_F_N

USB

USB_85D

USB_HPM_R_P

USB

USB_HPM_R_N

USB_85D

USB_HPM_P

USB_HPM USB_85D

USB

USB_85DUSB_HPM

USB_HPM_N

USB

USB_TPAD

NC_USB_TPADP

USB_80D

USB_TPAD

NC_USB_TPADN

USB

USB_80D

USB

USB_BT_CONN_N

USB_80D

USB_BT

USB_BT_CONN_P

USB

USB_80D

USB_BT

SPI

TPAD_SPI_MISO

SPI_45S

USB_80D

USB3RPCIE_SD_R2D_C_P

USB3_SD_TX

USB3_PCH_TX

USB_80D

USB3RPCIE_SD_R2D_C_N

USB3_SD_TX

USB3_PCH_TX

USB_80D

USB3_PCH_TX

USB3_SD_R2D_P

PCH_DIFFCLK_UNUSED_

CLK_PCIE_80D CLK_PCIE

PCIE_CLK100M_PCH_P

USB3_SD_D2R_C_N

USB_80D

USB3_PCH_RX

USB_80D

USB3_SD_R2D_N

USB3_PCH_TX

PCH_DIFFCLK_UNUSED_

CLK_PCIECLK_PCIE_80D

PCH_CLK96M_DOT_P

CLK_PCIECLK_PCIE_80D

PCH_DIFFCLK_UNUSED_

PCH_CLK96M_DOT_N

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_80D

PCH_CLK100M_SATA_P

CLK_PCIE_80D CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCH_CLK100M_SATA_N

CLK_PCIE

CPU_45S

PCH_CLK14P3M_REFCLK

PCH_USB_RBIASPCH_USB_RBIAS

PCH_USB_RBIAS

USB3_PCH_RX

USB_80D

USB3_SD_D2R_C_P

USB_80D

USB3_SD_RX

USB3RPCIE_SD_D2R_N

USB3_PCH_RX

USB

USB_EXTB

USB_80D

NC_USB_EXTBN

USB

USB_80D

USB_EXTB

USB2_EXTB_F_P

USB_80D

USB_EXTB

USB

USB2_EXTB_F_N

USB3_EXTB_RX

USB3_PCH_RX

USB_80D

NC_USB3_EXTB_D2RP NC_USB3_EXTB_D2RN

USB3_EXTB_RX

USB_80D

USB3_PCH_RX

USB3_EXTB_R2D_P

USB3_EXTB_TX

USB_80D

USB3_PCH_TX

USB3_EXTB_TX

USB3_EXTB_R2D_N

USB3_PCH_TX

USB_80D

NC_USB3_EXTB_R2D_CP

USB_80D

USB3_PCH_TX

NC_USB3_EXTB_R2D_CN

USB3_PCH_TX

USB_80D

USB

USB_80D

USB_EXTC

USB2_EXTC_P

USB_EXTC

USB_80D

USB

USB2_EXTC_F_P

USB_80D

USB

USB_EXTC

USB2_EXTC_N

USB_EXTC

USB

USB_80D

USB2_EXTC_F_N

USB_80D

USB3_PCH_RX

USB3_EXTC_D2R_N

USB3_EXTC_RX

USB_80D

USB3_PCH_RX

USB3_EXTC_D2R_P

USB3_EXTC_RX

USB_80D

USB3_PCH_TX

USB3_EXTC_R2D_N

USB3_EXTC_TX

USB_80D

USB3_PCH_TX

USB3_EXTC_R2D_P

USB3_EXTC_TX

USB_80D

USB3_PCH_TX

USB3_EXTC_R2D_C_N

CLK_PCIE_80D CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCIE_CLK100M_PCH_N

USB_EXTB

USB_80D

USB

NC_USB_EXTBP

TPAD_SPI_CLK

SPI_45S

SPI

USB_80D

USB3_PCH_TX

USB3_EXTC_R2D_C_P

USB_80D

USB3_PCH_RX

USB3_SD_RX

USB3RPCIE_SD_D2R_P

SPI_45S

TPAD_SPI_MOSI

SPI

USB_80D

USB

USB_EXTA_N

USB_80D

USB

USB_EXTA_P

USB3_EXTA_D2R_N

USB_80D

USB3_PCH_RX

USB3_EXTA_RX

USB3_PCH_TX

USB3_EXTA_TX

USB_80D

USB3_EXTA_R2D_P

<SCH_NUM>

112 OF 130

67 OF 75

22

14 22

26

31 32 64

26 31 32 64

14 29

27 29

14 27

14 29

29

14 29 64

26

28 29

14 64

15 30

14

14 64

15 30

14 26 64

14 29 64

29

WWW.AliSaler.Com

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

HD Audio Interface Constraints

XDP Constraints

DisplayPort

NOTE: 25MHz system clocks very sensitive to noise.

ELECTRICAL_CONSTRAINT_SET

SIO Signal Constraints

SMBus Interface Constraints

SPI Interface Constraints

PHYSICAL

NET_TYPE

System Clock Signal Constraints

NET_TYPE

PCH Net Properties

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

Clock Net Properties

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

LPC Bus Constraints

NET_TYPE

E85 Net Properties

Note: 80ohm constraints are actually 85ohm

I385 I386

I387

I388

I389 I390

I391 I392

I393

I394 I395

I396

I397 I398

I399 I400

I401 I402

SYNC_DATE=04/17/2014

PCH Constraints 2

SYNC_MASTER=DEV_MLB

=45_OHM_SE=45_OHM_SE=45_OHM_SE

*

=STANDARD

=45_OHM_SE

=STANDARD

CLK_SLOW_45S

=STANDARD

=45_OHM_SE=45_OHM_SE =45_OHM_SE =45_OHM_SE

*

=STANDARD

LPC_45S

=STANDARD

=45_OHM_SE =45_OHM_SE

*

=STANDARD

=45_OHM_SE=45_OHM_SE

CLK_LPC_45S

CLK_LPC

?*

=4x_DIELECTRIC

SMB_45S_R_50S

TOP,BOTTOM =50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

SMB_45S_R_50S

=45_OHM_SE =45_OHM_SE

*

=STANDARD=STANDARD

=45_OHM_SE =45_OHM_SE

* ?

=4x_DIELECTRIC

CLK_SLOW

=45_OHM_SE

SPI_45S

*

=STANDARD=STANDARD

=45_OHM_SE=45_OHM_SE =45_OHM_SE

=45_OHM_SE=45_OHM_SE=45_OHM_SE

*

=STANDARD =STANDARD

CLK_SLOW_45S

=45_OHM_SE

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

*

=STANDARD =STANDARD

CLK_25M_45S

LPC * ?

=3x_DIELECTRIC

=STANDARD

=45_OHM_SE =45_OHM_SE=45_OHM_SE

HDA_45S

*

=45_OHM_SE

=STANDARD

*

=5x_DIELECTRIC

?

CLK_25M

SMB *

=2x_DIELECTRIC

?

?*

=2x_DIELECTRIC

HDA

* ?

CLK_SLOW

=2x_DIELECTRIC

*SPI ?

=4x_DIELECTRIC

=45_OHM_SE

=STANDARD

*

=45_OHM_SE

PCH_45S

=45_OHM_SE

=STANDARD

=45_OHM_SE

PCH_ITP

* ?

=2:1_SPACING

=80_OHM_DIFF=80_OHM_DIFF

*

=80_OHM_DIFF

DP_80D

=80_OHM_DIFF =80_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

DP_85D

*

DP_TX

*_TX

DP_2OTHERHS

*

DP_TX

*

DP_2OTHER

*_RX

*

DP_TX

DP_2OTHERHS

DP_2DP

DP_TXDP_TX

*

DP_AUX

* ?

=3x_DIELECTRIC

*

?

DP_2OTHER

*

?

DP_2OTHERHS

=4x_DIELECTRIC

?*

=3x_DIELECTRIC

DP_2DP

?

TOP,BOTTOM

DP_AUX

=4x_DIELECTRIC

?

TOP,BOTTOM

DP_2OTHERHS

=6x_DIELECTRIC

=4x_DIELECTRIC

?

TOP,BOTTOM

DP_2OTHER

=4x_DIELECTRIC

DP_2DP

?

TOP,BOTTOM

SYSCLK_CLK32K_RTCX1

CLK_SLOWCLK_SLOW_45S

SYSCLK_CLK32K_RTC

DP_85D

DP_TX

E85_HS_XBAR_R2D

DP_TBTSNK0_ML_C_N<1>

CLK_25M_45S

CLK25M_CAM_XTALP

CLK_25M

E85_CC

E85_CC1

E85_CC

E85_CC2

E85_LS_MISSION_N

E85_LS

E85_LS_85D

E85_LS_MISSION_P

E85_LS_85D

E85_LS

E85_LS_N<2..1>

E85_LS_85D

E85_LSE85_LS

E85_LS_P<2..1>

E85_LS E85_LS

E85_LS_85D

E85_HS_DP_ML0_N

DP_85D

DP_TX

E85_HS_DP_ML1_P

DP_TX

DP_85D

E85_HS_DP_ML1_N

DP_TX

DP_85D

DP_TX

DP_85D

E85_HS_DP_ML0_P

DP_E85SNK_ML_N<3..0>

DP_85D

DP_TX

DP_E85SNK_ML_P<3..0>

DP_85D

DP_TX

DP_TBTSNK0_ML_C_N<3..2>

E85_HS

DP_TX

DP_85D

DP_TBTSNK0_ML_C_P<3..2>

E85_HS

DP_TX

DP_85D

DP_TX

E85_HS_XBAR_R2D

DP_TBTSNK0_ML_C_P<1>

DP_TX

DP_85D

E85_HS_XBAR_D2R

DP_TBTSNK0_ML_C_P<0>

DP_TX

DP_85D

E85_HS_XBAR_D2R

DP_TBTSNK0_ML_C_N<0>

HDA_SYNC

HDA

HDA_45S

HDA_SYNC

HDA_45S

HDA

HDA_SYNC_R

HDA_45S

HDA_RST_R_L

HDA_RST_L

HDA

SPI_CLK_R

SPI_45S

SPI

SPI_CLK

LPC_FRAME_L

LPC_45S

LPC

LPC_FRAME_L

CLK_PCIE

PCIE_CLK100M_AP_P

CLK_PCIE_80D

PCIE_CLK100M_AP

PCIE_TBT_D2R_C_P<3..0>

PCIE_80D

PCIE_PCH_RX

PCIE_TBT_D2R

PCIE_TBT_D2R_P<3..0>

PCIE_80D

PCIE_PCH_RX

PCIE_TBT_R2D_C_N<3..0>

PCIE_PCH_TX

PCIE_80D

PCIE_PCH_TX

PCIE_AP_R2D_C_P

PCIE_80D

PCIE_AP_R2D_C_N

PCIE_PCH_TX

PCIE_80D

PCIE_AP_D2R_N

PCIE_80D

PCIE_AP_D2R PCIE_PCH_RX

PCIE_PCH_RX

PCIE_80D

PCIE_AP_D2R_C_N

PCIE_PCH_RX

PCIE_80D

PCIE_AP_D2R_C_P

PCIE_80D

PCIE_AP_D2R PCIE_PCH_RX

PCIE_AP_D2R_P

PCIE_CLK100M_TBT_P

CLK_PCIECLK_PCIE_80D

PCIE_CLK100M_TBT

PCIE_CLK100M_TBT_N

CLK_PCIE_80D CLK_PCIE

PCIE_CLK100M_TBT

PCIE_TBT_D2R_C_N<3..0>

PCIE_PCH_RX

PCIE_80D

PCIE_TBT_D2R_N<3..0>

PCIE_PCH_RX

PCIE_TBT_D2R PCIE_80D

PCIE_80D

PCIE_PCH_TX

PCIE_TBT_R2D_C_P<3..0>

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D

PCIE_PCH_TX

PCIE_80D

PCIE_TBT_R2D PCIE_80D

PCIE_PCH_TX

PCIE_TBT_R2D_P<3..0>

CLK_PCIE_80D CLK_PCIE

PCIE_CLK100M_AP_C_N

CLK_PCIE_80D CLK_PCIE

PCIE_CLK100M_AP_C_P

CLK_PCIE

PCIE_CLK100M_AP_N

CLK_PCIE_80D

PCIE_CLK100M_AP

SPI_45S

SPI_MLB_CS_L

SPI

PCIE_AP_R2D_P

PCIE_PCH_TX

PCIE_80D

PCIE_AP_R2D

PCIE_PCH_TX

PCIE_AP_R2D_N

PCIE_80D

PCIE_AP_R2D

SPI_45S

SPI

SPI_SMC_CS_L

DP_TBT_AUXCH

DP_AUXDP_80D

DP_AUX_CH_CONN_N

DP_TBT_AUXCH

DP_AUXDP_80D

DP_AUX_CH_CONN_P

DP_80D

DP_AUX_CH_C_P

DP_AUX

DP_TBT_AUXCH

DP_80D

DP_AUX_CH_C_N

DP_AUX

DP_TBT_AUXCH

DP_AUX

DP_AUX_CH_N

DP_80D

DP_TBT_ML

DP_80D

DP_TX

DP_ML_CONN_N<3..0>

DP_TBT_AUXCH

DP_AUX

DP_AUX_CH_P

DP_80D

DP_TBT_ML

DP_80D

DP_TX

DP_ML_CONN_P<3..0>

DP_ML_C_P<3..0>

DP_TBT_ML

DP_TX

DP_80D

DP_ML_C_N<3..0>

DP_TBT_ML

DP_TX

DP_80D

DP_TBT_ML

DP_ML_N<3..0>

DP_TX

DP_80D

PCIE_CLK100M_DBG

PCIE_CLK100M_DEBUG_N

CLK_PCIECLK_PCIE_80D

DP_TBT_ML

DP_ML_P<3..0>

DP_TX

DP_80D

CLK_PCIE

PCIE_CLK100M_CAMERA_C_N

CLK_PCIE_80D

PCIE_CLK100M_DBG

CLK_PCIECLK_PCIE_80D

PCIE_CLK100M_DEBUG_P

CLK_PCIE

PCIE_CLK100M_CAMERA_C_P

CLK_PCIE_80D

PCIE_CLK100M_CAM

PCIE_CLK100M_CAMERA_N

CLK_PCIE

PCIE_CLK100M_CAM

CLK_PCIE_80D

PCIE_CLK100M_CAMERA_P

CLK_PCIE

PCIE_CAMERA_D2R_C_N

PCIE_80D

PCIE_PCH_RX

PCIE_CAMERA_D2R_C_P

PCIE_PCH_RX

PCIE_80D

PCIE_PCH_RX

PCIE_80D

PCIE_CAMERA_D2R_N

PCIE_CAM

PCIE_CAMERA_D2R_P

PCIE_PCH_RX

PCIE_80D

PCIE_CAMERA_R2D_C_N

PCIE_PCH_TX

PCIE_80D

PCIE_CAM PCIE_80D

PCIE_PCH_TX

PCIE_CAMERA_R2D_N PCIE_CAMERA_R2D_C_P

PCIE_PCH_TX

PCIE_80D

PCIE_CAM PCIE_80D

PCIE_PCH_TX

PCIE_CAMERA_R2D_P

CLK_LPC

LPC_CLK33M

CLK_LPC_45S

LPC_CLK24M_LPCPLUS

CLK_LPC

CLK_LPC_45S

TP_LPC_CLK24M_LPCPLUS_R

LPC_AD

LPC_45S

LPC

LPC_AD<3..0>

LPCPLUS_RESET_L

LPC_45S

LPC

CLK_LPC_45S

CLK_LPC

LPC_CLK24M_SMC_R

SMB_45S_R_50S

SMB

SMBUS_PCH_CLK

SMB

SML_PCH_0_CLK

SMB_45S_R_50S

SMBUS_PCH_0_CLK

SMBUS_SMC_1_S0_SDA

SMB

SMB_45S_R_50S

SMBUS_SMC_1_S0_SDA

HDA_45S

HDA_SDOUT_R

HDA

SPI_SMC_MISO

SPI_45S

SPI

SPI_SMC_CLK

SPI_45S

SPI

SPI_CS0

SPI

SPI_CS0_R_L

SPI_45S

SPI_MISO

SPI_45S

SPI

SPI_MISO

SPI_45S

SPI

SPI_SMC_MOSI

SPI_45S

SPI_CS0_L

SPI

LPC_CLK33M

CLK_LPC

CLK_LPC_45S

LPC_CLK24M_SMC

SMB

SMB_45S_R_50S

SMBUS_SMC_1_S0_SCL

SMB_45S_R_50S

SMB

SMBUS_PCH_DATA

SMB_45S_R_50S

SMB

SML_PCH_0_DATA

SMBUS_PCH_0_DATA

XDP_TDI PCH_45S PCH_ITP

XDP_PCH_TDI

XDP_TDO PCH_ITPPCH_45S

XDP_PCH_TDO

SPI_45S

SPI

SPI_MLB_CLK

SPI

SPI_45S

SPI_MOSI

SPI

SPI_45S

SPI_MOSI

SPI_MOSI_R

SPI

SPI_45S

SPI_CLK

SMC_CLK32K

CLK_SLOWCLK_SLOW_45S

PM_CLK32K_SUSCLK_R

PM_SUS_CLK

CLK_SLOW_45S CLK_SLOW

XDP_PCH_TCK

PCH_45S PCH_ITPXDP_TCK

CLK_25M_45S

SYSCLK_CLK25M_X2

CLK_25M

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_XTAL

SYSCLK_CLK25M_X1

CLK_25M

SYSCLK_CLK25M_TBT_R

CLK_25M_45S

SYSCLK_CLK25M_TBT

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_TBT

CLK25M_CAM_XTALN

CLK_25M

CLK_25M_45S

CLK25M_CAM_XTALP_R

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_X2_R

CLK_25M_45S

CLK_25M

CLK_25M_45S

CLK_25M

SDCLK_CLK25M_X2

CLK_25M

SYSCLK_CLK25M_CAMERA

CLK_25M_45S

SYSCLK_CLK25M_SB

CLK_25M

CLK_25M_45S

SDCLK_CLK25M_X2_R

CLK_25M

CLK_25M_45S

CLK25M_CAM_CLKN

SYSCLK_CLK24M_CAMERA

CLK_25M

CLK_25M_45S

HDA_SDOUT

HDA

HDA_45S

HDA_SDOUT

HDA_45S

HDA

HDA_SDIN0

HDA_RST_L

HDA

HDA_45S

PCH_45S PCH_ITPXDP_TMS

XDP_PCH_TMS

SPI

SPI_45S

SPI_MLB_MISO

SPI_45S

SPI_MLB_MOSI

SPI

HDA_BIT_CLK

HDA_45S

HDA

CLK_25M_45S

CLK_25M

SDSCLK_CLK25M_X1

HDA_45S

HDA

HDA_BIT_CLK_R

<SCH_NUM>

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12 22

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WWW.AliSaler.Com

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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PAGE TITLE

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SIZE

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

Note: changed MEM_TERM physical rule to MEM_70D from MEM_73D temporarily

Memory to Power Spacing

NET_TYPE

PHYSICAL

Memory Net Properties

SPACING

Memory to GND Spacing

Memory Bus Spacing Group Assignments

Spacing Rule Sets

Memory Bus Constraints

I175

I176

=40_OHM_SE =40_OHM_SE

MEM_40S

=40_OHM_SE=40_OHM_SE

*

=40_OHM_SE

=8x_DIELECTRIC

?

*

MEM_DATA2OTHERMEM

?*

MEM_CMD2CMD

=3x_DIELECTRIC

*?

=3x_DIELECTRIC

MEM_CMD2CTRL

MEM_70D

MEM_TERM

MEM_70D

MEM_TERM

MEM_50SMEM_40S

**

MEM_2OTHER

MEM_A_DQS_2

**

MEM_2OTHER

MEM_A_DQS_3

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_7

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_6

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_5

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_4

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_2

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_3

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_1

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_0

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_6

*

MEM_2OTHERMEM

MEM_*_DATA_*

*

MEM_A_DATA_7

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_5

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_4

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_3

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_2

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_0

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_1

*

MEM_*MEM_*

MEM_2OTHERMEM

MEM_CMD2CMD

MEM_CMD MEM_CMD

*

MEM_B_DQS_5

MEM_B_DATA_5

*

MEM_DQS2OWNDATA

MEM_B_DQS_3

*

MEM_DQS2OWNDATA

MEM_B_DATA_3

MEM_B_DQS_1*MEM_B_DATA_1

MEM_DQS2OWNDATA

*

MEM_B_DQS_0

MEM_B_DATA_0

MEM_DQS2OWNDATA

MEM_B_DQS_4

*

MEM_DQS2OWNDATA

MEM_B_DATA_4

MEM_B_DQS_2*MEM_B_DATA_2

MEM_DQS2OWNDATA

**

MEM_2OTHER

MEM_A_DQS_5

**

MEM_2OTHER

MEM_A_DQS_6

**

MEM_2OTHER

MEM_A_DQS_7

**

MEM_2OTHER

MEM_B_DQS_0

**

MEM_2OTHER

MEM_B_DQS_1

**

MEM_2OTHER

MEM_B_DQS_2 MEM_B_DQS_3

*

MEM_2OTHER

*

**

MEM_2OTHER

MEM_A_DQS_1

**

MEM_2OTHER

MEM_B_DQS_5

MEM_2OTHER

**

MEM_A_DATA_0

*

MEM_*_DATA_*

MEM_DATA2SELF

=SAME

**

MEM_2OTHER

MEM_A_DQS_0MEM_A_DQS_0*MEM_A_DATA_0

MEM_DQS2OWNDATA

MEM_A_DQS_1

*

MEM_DQS2OWNDATA

MEM_A_DATA_1

*

MEM_A_DQS_3

MEM_DQS2OWNDATA

MEM_A_DATA_3

*

10000

MEM_2PWR

=2x_DIELECTRIC

=4x_DIELECTRIC

*?

MEM_2OTHERMEM

?*

=6x_DIELECTRIC

MEM_CLK2CLK

=3x_DIELECTRIC

*?

MEM_CTRL2CTRL

=3x_DIELECTRIC

*?

MEM_DQS2OWNDATA

MEM_2OTHER

**

MEM_CLK

*?

MEM_DATA2SELF

=2x_DIELECTRIC

*

=2x_DIELECTRIC

10000

MEM_2GND

MEM_2OTHER

*

MEM_CMD

* *

MEM_CTRL

*

MEM_2OTHER

MEM_CMD2CTRL

MEM_CMD

*

MEM_CTRL

*

MEM_DQS2OWNDATA

MEM_A_DQS_2

MEM_A_DATA_2

*

GND

MEM_*

MEM_2GND

*

MEM_*

MEM_PWR

MEM_2PWR

*

DEFAULTMEM_PWR

*

*?

MEM_2OTHER

=6x_DIELECTRIC

MEM_A_DATA_4

MEM_A_DQS_4

*

MEM_DQS2OWNDATA

MEM_A_DATA_5

MEM_A_DQS_5

*

MEM_DQS2OWNDATA

MEM_A_DQS_6*MEM_A_DATA_6

MEM_DQS2OWNDATA

MEM_A_DQS_7*MEM_A_DATA_7

MEM_DQS2OWNDATA

*

MEM_B_DQS_7

MEM_2OTHER

*

**

MEM_2OTHER

MEM_B_DQS_6

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_*_DATA_*

*

MEM_*

MEM_DATA2OTHERMEM

MEM_B_DQS_6

*

MEM_DQS2OWNDATA

MEM_B_DATA_6

*

MEM_B_DQS_7

MEM_DQS2OWNDATA

MEM_B_DATA_7

MEM_CLK

*

MEM_CLK2CLK

MEM_CLK

MEM_2OTHER

**

MEM_A_DQS_4

*

MEM_2OTHER

MEM_B_DQS_4

*

MEM_2OTHER

*

MEM_B_DATA_6

*

MEM_B_DATA_7

*

MEM_2OTHER

*

MEM_B_DATA_5

MEM_2OTHER

**

MEM_B_DATA_4

MEM_2OTHER

**

MEM_2OTHER

MEM_B_DATA_3

**

MEM_B_DATA_2

MEM_2OTHER

**

MEM_B_DATA_1

MEM_2OTHER

**

MEM_B_DATA_0

MEM_2OTHER

**

MEM_2OTHER

**

MEM_A_DATA_7

MEM_2OTHER

MEM_A_DATA_6

**

MEM_A_DATA_5

MEM_2OTHER

**

MEM_A_DATA_4

MEM_2OTHER

**

MEM_2OTHER

MEM_A_DATA_3

**

MEM_A_DATA_2

MEM_2OTHER

**

MEM_A_DATA_1

MEM_2OTHER

**

=50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

MEM_50S

*

=50_OHM_SE

=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF

MEM_70D

*

=70_OHM_DIFF

SYNC_MASTER=J92_LS_MLB

Memory Constraints

SYNC_DATE=05/07/2013

MEM_CTRL

MEM_40S

MEM_B_CS0

MEM_B_CS_L<0>

MEM_CTRL

MEM_40S

MEM_B_CS1

MEM_B_CS_L<1>

MEM_70D

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_70D

MEM_B_DQS6

MEM_B_DQS_6

MEM_B_DQS_N<6>

MEM_70D

MEM_B_DQS_7

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_70D

MEM_B_DQS_N<5>

MEM_B_DQS5

MEM_B_DQS_5

MEM_70D

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_B_DQS_6

MEM_B_DQS5

MEM_B_DQS_5

MEM_B_DQS_P<5>

MEM_70D

MEM_B_DQS_P<4>

MEM_B_DQS_4

MEM_B_DQS4

MEM_70D

MEM_B_DQS_N<4>

MEM_B_DQS4

MEM_B_DQS_4

MEM_70D

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_B_DQS_3

MEM_70D

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_B_DQS_3

MEM_70D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_B_DQS_2

MEM_70D

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_B_DQS_1

MEM_70D

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_B_DQS_2

MEM_70D

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_B_DQS_1

MEM_70D

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_B_DQS_0

MEM_B_DQS0

MEM_70D

MEM_B_DQS_P<0>

MEM_B_DQS_0

MEM_B_DQ_BYTE6

MEM_40S

MEM_B_DATA_6

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE7

MEM_40S

MEM_B_DQ<63..56>

MEM_B_DATA_7

MEM_B_DQ_BYTE5

MEM_40S

MEM_B_DQ<47..40>

MEM_B_DATA_5

MEM_40S

MEM_B_DQ<31..24>

MEM_B_DQ_BYTE3

MEM_B_DATA_3

MEM_B_DQ<39..32>

MEM_B_DATA_4

MEM_40S

MEM_B_DQ_BYTE4

MEM_40S

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1

MEM_B_DATA_1

MEM_40S

MEM_B_DQ<23..16>

MEM_B_DATA_2

MEM_B_DQ_BYTE2

MEM_40S

MEM_B_DQ_BYTE0

MEM_B_DATA_0

MEM_B_DQ<7..0>

MEM_CMD

MEM_B_CAA<9..0>

MEM_B_CMD0

MEM_40S MEM_40S MEM_CMD

MEM_B_CMD1

MEM_B_CAB<9..0>

MEM_40S MEM_CMD

MEM_B_CKE<3..2>

MEM_B_CKE1

MEM_40S MEM_CMD

MEM_B_CKE0

MEM_B_CKE<1..0>

MEM_B_ODT

MEM_40S

MEM_CTRL

MEM_B_ODT<0>

MEM_CTRL

MEM_40S

MEM_A_CS1

MEM_A_CS_L<1>

MEM_40S

MEM_CTRL

MEM_A_CS0

MEM_A_CS_L<0> MEM_A_ODT<0>

MEM_40S

MEM_CTRL

MEM_A_ODT

MEM_A_DQS_7

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_70D

MEM_A_DQS_7

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_70D

MEM_A_DQS_6

MEM_A_DQS_N<6>

MEM_70D

MEM_A_DQS6

MEM_A_DQS_5

MEM_A_DQS_N<5>

MEM_70D

MEM_A_DQS5

MEM_A_DQS_6

MEM_A_DQS_P<6>

MEM_70D

MEM_A_DQS6

MEM_A_DQS_5

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_70D

MEM_A_DQS_4

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_70D

MEM_A_DQS_4

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_70D

MEM_A_DQS_3

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_70D

MEM_A_DQS_2

MEM_A_DQS2

MEM_70D

MEM_A_DQS_N<2>

MEM_A_DQS_3

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_70D

MEM_A_DQS_1

MEM_A_DQS1

MEM_70D

MEM_A_DQS_N<1>

MEM_A_DQS_2

MEM_A_DQS2

MEM_70D

MEM_A_DQS_P<2>

MEM_A_DQS_1

MEM_A_DQS1

MEM_70D

MEM_A_DQS_P<1>

MEM_A_DQS_0

MEM_A_DQS0

MEM_70D

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_0

MEM_A_DQS0

MEM_70D

MEM_A_DATA_6

MEM_A_DQ_BYTE6

MEM_40S

MEM_A_DQ<55..48>

MEM_A_DATA_7

MEM_A_DQ_BYTE7

MEM_40S

MEM_A_DQ<63..56>

MEM_A_DQ<47..40>

MEM_A_DATA_5

MEM_A_DQ_BYTE5

MEM_40S

MEM_A_DQ<31..24>

MEM_A_DATA_3

MEM_A_DQ_BYTE3

MEM_40S

MEM_A_DQ<39..32>

MEM_A_DATA_4

MEM_A_DQ_BYTE4

MEM_40S

MEM_A_DQ<15..8>

MEM_A_DATA_1

MEM_A_DQ_BYTE1

MEM_40S

MEM_A_DQ<23..16>

MEM_A_DATA_2

MEM_A_DQ_BYTE2

MEM_40S

MEM_A_DQ<7..0>

MEM_A_DATA_0

MEM_A_DQ_BYTE0

MEM_40S

MEM_A_CMD0

MEM_CMD

MEM_A_CAA<9..0>

MEM_40S

MEM_A_CMD1

MEM_CMD

MEM_A_CAB<9..0>

MEM_40S

MEM_A_CKE1

MEM_A_CKE<3..2>

MEM_40S MEM_CMD

MEM_CMDMEM_40S

MEM_A_CKE<1..0>

MEM_A_CKE0

MEM_A_CLK0

MEM_CLKMEM_70D

MEM_A_CLK_P<0>

MEM_A_CLK0

MEM_A_CLK_N<0>

MEM_70D MEM_CLK

PPVREF_S3_MEM_VREFDQ_B

MEM_PWR

PPVREF_S3_MEM_VREFCA

MEM_PWR

PPVREF_S3_MEM_VREFDQ_A

MEM_PWR

PPVREF_S3_MEM_VREFCA

MEM_B_CLK1

MEM_CLKMEM_70D

MEM_B_CLK_N<1>

MEM_CLKMEM_70D

MEM_B_CLK0

MEM_B_CLK_P<0>

MEM_CLK

MEM_A_CLK1

MEM_A_CLK_N<1>

MEM_70D

MEM_A_CLK1

MEM_CLKMEM_70D

MEM_A_CLK_P<1>

MEM_B_CLK_P<1>

MEM_CLKMEM_70D

MEM_B_CLK1

MEM_CLKMEM_70D

MEM_B_CLK0

MEM_B_CLK_N<0>

PP1V2_S3

MEM_PWR

<SCH_NUM>

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WWW.AliSaler.Com

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5

4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NAND BUS CONSTRAINTS

DQS_P/N & NRE_P/N SHOULD MATCH +/- 100MIL FROM NWE

IO<7..0> AND ASSOCIATED DQS_P/N ROUTE ON SAME LAYER. NO MORE THAN 2 VIA TRANSITIONS.

IO<7..0> SIGNALS SHOULD MATCH +/- 50MIL FROM DQS_P/N

NAND:

DQS_P/N MAX LENGTH 3"

NCE<7..0>,ALE,CLE SHOULD MATCH +/- 250MIL FROM NWE

SPACING

NET_TYPE

PHYSICAL

NAND NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

NAND NET PROPERTIES

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

I243

I244

I245

I246

I247 I248

I249

I253

I254

I256

I257 I258

I259

I260

I261 I263 I264 I268

I269

I271

I275

I276

I277 I278

I279

I280 I281

I282

I284

I288

I289

I290 I291

I292

I293 I294

I297

I298

I299

I300 I301

I302

I303

I305 I307

I308 I309 I310 I311

I312

I313

I314 I317 I319

I321 I322

I323

I324

I325

I326

I327 I330 I332

I334

I335

I336

I337

I338

I339 I340 I344 I345

NAND CONSTRAINTS

SYNC_MASTER=MASTER

SYNC_DATE=11/16/2011

?

*

NAND_DQS 0.100 MM

?

NAND_CMD

*

0.100 MM

=45_OHM_SE =45_OHM_SE=45_OHM_SE

NAND_45S

=STANDARD =STANDARD

*

=45_OHM_SE

NAND_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

*

=85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF

?*

NAND_IO

0.100 MM

NAND_85D

DP_ANI3_DQS

NAND_DQS

ANI3_DQS_P

DP_ANI3_NRE

NAND_85D NAND_DQS

ANI3_NRE_N

ANI1_ALE NAND_CMD

ANI1_ALE

NAND_45S

ANI1_CLE NAND_CMD

ANI1_CLE

NAND_45S

DP_ANI2_DQS

NAND_85D NAND_DQS

ANI2_DQS_P

ANI2_IO NAND_IO

ANI2_IO<7..0>

NAND_45S

ANI2_NCE NAND_CMD

ANI2_NCE<3..0>

NAND_45S

ANI2_NWE NAND_CMD

ANI2_NWE

NAND_45S

DP_ANI2_NRE

NAND_85D NAND_DQS

ANI2_NRE_N

DP_ANI2_NRE

NAND_85D NAND_DQS

ANI2_NRE_P

ANI2_ALE NAND_CMD

ANI2_ALE

NAND_45S

ANI2_CLE NAND_CMD

ANI2_CLE

NAND_45S

DP_ANI3_DQS

NAND_85D NAND_DQS

ANI3_DQS_N

DP_ANI3_NRE

NAND_85D NAND_DQS

ANI3_NRE_P

ANI3_NWE NAND_CMD

ANI3_NWE

NAND_45S

ANI3_ALE NAND_CMD

ANI3_ALE

NAND_45S

ANI3_CLE NAND_CMD

ANI3_CLE

NAND_45S

ANI0_NWE NAND_CMD

ANI0_NWE

NAND_45S

DP_ANI0_NRE

NAND_85D NAND_DQS

ANI0_NRE_N

ANI0_IO NAND_IO

ANI0_IO<7..0>

NAND_45S

ANI0_NCE NAND_CMD

ANI0_NCE<3..0>

NAND_45S

ANI0_ALE NAND_CMD

ANI0_ALE

NAND_45S

ANI0_CLE NAND_CMD

ANI0_CLE

NAND_45S

DP_ANI0_NRE

NAND_85D NAND_DQS

ANI0_NRE_P

DP_ANI0_DQS

NAND_85D NAND_DQS

ANI0_DQS_N

DP_ANI0_DQS

NAND_85D NAND_DQS

ANI0_DQS_P

ANI1_IO NAND_IO

ANI1_IO<7..0>

NAND_45S

DP_ANI1_DQS

NAND_85D NAND_DQS

ANI1_DQS_P

DP_ANI1_NRE

NAND_85D NAND_DQS

ANI1_NRE_N

NAND_85D

DP_ANI1_NRE

NAND_DQS

ANI1_NRE_P

ANI1_NWE NAND_CMD

ANI1_NWE

NAND_45S

ANI1_NCE NAND_CMD

ANI1_NCE<3..0>

NAND_45S

ANI7_CLE NAND_CMD

ANI7_CLE

NAND_45S

ANI7_ALE NAND_CMD

ANI7_ALE

NAND_45S

ANI7_NCE NAND_CMD

ANI7_NCE<3..0>

NAND_45S

ANI7_NWE NAND_CMD

ANI7_NWE

NAND_45S

DP_ANI7_DQS

NAND_85D NAND_DQS

ANI7_DQS_N

DP_ANI7_DQS

NAND_85D NAND_DQS

ANI7_DQS_P

ANI6_CLE NAND_CMD

ANI6_CLE

NAND_45S

ANI6_ALE NAND_CMD

ANI6_ALE

NAND_45S

NAND_DQS

DP_ANI6_DQS

NAND_85D

ANI6_DQS_N

ANI6_IO NAND_IO

ANI6_IO<7..0>

NAND_45S

DP_ANI5_NRE

NAND_85D NAND_DQS

ANI5_NRE_P

DP_ANI5_DQS

NAND_85D NAND_DQS

ANI5_DQS_P

ANI4_CLE NAND_CMD

ANI4_CLE

NAND_45S

ANI4_ALE NAND_CMD

ANI4_ALE

NAND_45S

ANI4_NCE NAND_CMD

ANI4_NCE<3..0>

NAND_45S

DP_ANI4_NRE

NAND_85D NAND_DQS

ANI4_NRE_P

DP_ANI4_NRE

NAND_85D NAND_DQS

ANI4_NRE_N

DP_ANI4_DQS

NAND_85D NAND_DQS

ANI4_DQS_N

DP_ANI4_DQS

NAND_85D NAND_DQS

ANI4_DQS_P

ANI4_IO NAND_IO

ANI4_IO<7..0>

NAND_45S

ANI4_NWE NAND_CMD

ANI4_NWE

NAND_45S

ANI5_IO NAND_IO

ANI5_IO<7..0>

NAND_45S

ANI7_IO NAND_IO

ANI7_IO<7..0>

NAND_45S

DP_ANI7_NRE

NAND_85D NAND_DQS

ANI7_NRE_N

ANI5_CLE NAND_CMD

ANI5_CLE

NAND_45S

ANI5_ALE NAND_CMD

ANI5_ALE

NAND_45S

ANI5_NCE NAND_CMD

ANI5_NCE<3..0>

NAND_45S

DP_ANI5_DQS

NAND_85D NAND_DQS

ANI5_DQS_N

ANI5_NWE NAND_CMD

ANI5_NWE

NAND_45S

DP_ANI5_NRE

NAND_85D NAND_DQS

ANI5_NRE_N

DP_ANI7_NRE

NAND_85D NAND_DQS

ANI7_NRE_P

ANI6_NRE_P

DP_ANI6_NRE

NAND_85D NAND_DQS

DP_ANI2_DQS

NAND_85D NAND_DQS

ANI2_DQS_N

ANI3_IO NAND_IO

ANI3_IO<7..0>

NAND_45S

ANI3_NCE NAND_CMD

ANI3_NCE<3..0>

NAND_45S

DP_ANI1_DQS

NAND_85D NAND_DQS

ANI1_DQS_N

DP_ANI6_DQS

NAND_85D NAND_DQS

ANI6_DQS_P

ANI6_NRE_N

DP_ANI6_NRE

NAND_85D NAND_DQS

ANI6_NWE NAND_CMD

ANI6_NWE

NAND_45S

ANI6_NCE NAND_CMD

ANI6_NCE<3..0>

NAND_45S

<SCH_NUM>

115 OF 130

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55

58

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WWW.AliSaler.Com

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

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PAGE TITLE

SHEET

R

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Camera Net Properties

Memory Bus Spacing Group Assignments

MIPI Interface Constraints

ELECTRICAL_CONSTRAINT_SET

Spacing Rule Sets

Memory to Power Spacing

Memory to GND Spacing

SPACING

PHYSICAL

NET_TYPE

Memory Bus Constraints

I101

I102

I103 I104

I106

I107

I108

I109

I110

I127

I128

I129 I130

I131

I132

I133

I134

I145 I146

I147

I148

TOP,BOTTOM

=4x_DIELECTRIC

?

S2_DATA2SELF

Camera Constraints

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=08/01/2013

S2MEM_2OTHER

?

=10x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

S2MEM_2PWR?TOP,BOTTOM

TOP,BOTTOM

?

S2_CMD2CTRL

=4x_DIELECTRIC

?

TOP,BOTTOM

=10X_DIELECTRIC

MIPICLK_2OTHER

TOP,BOTTOM

?

=8X_DIELECTRIC

MIPI_2CLK

MIPI_2OTHER

TOP,BOTTOM

?

=6X_DIELECTRIC

TOP,BOTTOM

?

S2_DQS2OWNDATA =4x_DIELECTRIC

=4x_DIELECTRIC

TOP,BOTTOM

?

S2_CMD2CMD

S2_2OTHERMEM

?

=6x_DIELECTRIC

TOP,BOTTOM

S2MEM_2GND TOP,BOTTOM

=4x_DIELECTRIC

?

=4x_DIELECTRIC

TOP,BOTTOM

?

S2_CTRL2CTRL

=2x_DIELECTRIC

?*

S2_CMD2CMD

?*

S2_CTRL2CTRL

=2x_DIELECTRIC

*?

S2_CMD2CTRL

=2x_DIELECTRIC

S2_2OTHERMEM

=4x_DIELECTRIC

*?

=2x_DIELECTRIC

?*

S2_DQS2OWNDATA

?*

=2x_DIELECTRIC

S2MEM_2PWR

=2x_DIELECTRIC

S2_DATA2SELF

?*

S2_MEM_CMD

S2_MEM_CTRL

S2_CMD2CTRL

*

S2_MEM_DQS*

**

S2MEM_2OTHER

S2MEM_2OTHERS2_MEM_DATA*

**

=SAME

*

S2_DATA2SELF

S2_MEM_DATA*

S2MEM_2PWR

S2_MEM_*

S2_MEM_PWR

*

S2_MEM_PWR

**

DEFAULT

S2_MEM_DQS0

S2_DQS2OWNDATA

S2_MEM_DATA0

*

S2MEM_2OTHER

**

S2_MEM_CMD

S2MEM_2OTHER

S2_MEM_CTRL

**

S2_MEM_CLK

*

S2MEM_2OTHER

*

S2_MEM_CMD

S2_CMD2CMD

S2_MEM_CMD

*

S2_MEM_CTRL S2_MEM_CTRL

S2_CTRL2CTRL

*

S2_2OTHERMEM

*

S2_MEM_*S2_MEM_*

GND

S2MEM_2GND

S2_MEM_*

*

MIPI_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

S2_MEM_85D

=85_OHM_DIFF

=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

=45_OHM_SE

*

S2_MEM_45S =45_OHM_SE

*

CLK_MIPI

*

MIPICLK_2OTHER

*

MIPI_2CLK

CLK_MIPI

MIPI_DATA

**

MIPI_2OTHER

MIPI_DATA

MIPICLK_2OTHER

*

=7X_DIELECTRIC

?

MIPI_2CLK

*

=6X_DIELECTRIC

?

MIPI_2OTHER

?

*

=4X_DIELECTRIC

?*

S2MEM_2GND

=2x_DIELECTRIC =6x_DIELECTRIC

S2MEM_2OTHER

*?

S2_MEM_DQS1

S2_DQS2OWNDATA

S2_MEM_DATA1

*

CLK_MIPI

MIPI_CLK_CONN_P

MIPI_85D

S2_MEM_45S

S2_MEM_CTRL

S2_MEM_CMD

MEM_CAM_CAS_L

S2_MEM_CMD

MEM_CAM_BA<1>

S2_MEM_CMD S2_MEM_45S

S2_MEM_DQS0

S2_MEM_85D

MEM_CAM_DQS_N<0>

S2_MEM_DQS0

MEM_CAM_DQS_P<0>

S2_MEM_DQS0

S2_MEM_85D

S2_MEM_DATA0

MEM_CAM_DM<0>

S2_MEM_DATA_0

S2_MEM_45S

S2_MEM_CMD

S2_MEM_A

S2_MEM_45S

MEM_CAM_A<14..0>

S2_MEM_45S

S2_MEM_DATA_1

MEM_CAM_DM<1>

S2_MEM_DATA1

PP0V675_CAM_VREF

S2_MEM_PWR

CLK_MIPI

MIPI_CLK_CONN_N

MIPI_85D

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D

MEM_CAM_CLK_P

S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_ODT

S2_MEM_CTRL

MEM_CAM_CKE

S2_MEM_45S

S2_MEM_CNTL

S2_MEM_CTRL

S2_MEM_45SS2_MEM_CMD

MEM_CAM_RAS_L

S2_MEM_CMDS2_MEM_45SS2_MEM_CMD

MEM_CAM_WE_L

MIPI_CLK_P

CLK_MIPI

MIPI_CLK_S2

MIPI_85D

S2_MEM_DATA0

S2_MEM_45S

MEM_CAM_DQ<7..0>

S2_MEM_DATA_0

S2_MEM_CLK S2_MEM_85D S2_MEM_CLK

MEM_CAM_CLK_N

S2_MEM_45S

S2_MEM_CTRLS2_MEM_CNTL

MEM_CAM_CS_L

S2_MEM_CMDS2_MEM_CMD S2_MEM_45S

MEM_CAM_BA<0>

MEM_CAM_BA<2>

S2_MEM_CMDS2_MEM_45SS2_MEM_CMD

CLK_MIPI

MIPI_CLK_N

MIPI_CLK_S2

MIPI_85D

PP0V675_MEM_CAM_VREFCA

S2_MEM_PWR

S2_MEM_85D

S2_MEM_DQS1

MEM_CAM_DQS_N<1>

S2_MEM_DQS1

S2_MEM_DATA1

MEM_CAM_DQ<15..8>

S2_MEM_45S

S2_MEM_DATA_1

S2_MEM_PWR

PP1V35_CAM

S2_MEM_85D

S2_MEM_DQS1

MEM_CAM_DQS_P<1>

S2_MEM_DQS1

MIPI_DATA_CONN_N

MIPI_DATA

MIPI_85D

MIPI_DATA_CONN_P

MIPI_DATA

MIPI_85D

MIPI_DATA_N

MIPI_DATA

MIPI_DATA_S2 MIPI_85D

MIPI_DATA_S2

MIPI_DATA

MIPI_DATA_P

MIPI_85D

<SCH_NUM>

116 OF 130

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25 53

24 25

24 25 64

24 25

25 53

24 25

25

24 25

64

24 25

25

24 25

25 53

24 25

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TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

SMBus Charger Net Properties

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

SMC SMBus Net Properties

0.1 MM

*

=STANDARD

0.1 MM

=STANDARD

0.1 MM

=STANDARD

1TO1_DIFFPAIR

SMC Constraints

SYNC_MASTER=J92_DEVMLB

SYNC_DATE=09/11/2013

0.1 MM

*

2TO1_DIFFPAIR

0.2 MM

=STANDARD =STANDARD

0.1 MM

=STANDARD

SMBUS_SMC_0_S0_SDA

SMB_45S_R_50S

SMB

SMBUS_SMC_0_S0_SCL

SMB_45S_R_50S

SMB

SMBUS_SMC_1_S0_SCL

SMB

SMBUS_SMC_1_S0_SCL

SMB_45S_R_50S

SMB

SMBUS_SMC_3_SCL

SMB_45S_R_50S

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

SMB

SMB_45S_R_50S

SMB

SMBUS_SMC_5_G3_SCL

SMB_45S_R_50S

SMBUS_SMC_5_G3_SCL

SMB

SMBUS_SMC_5_G3_SDA

SMB_45S_R_50S

CHGR_CSI_R_P

1TO1_DIFFPAIR

CHGR_CSI_R_N

1TO1_DIFFPAIR

SENSE_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

SENSE_DIFFPAIR

CHGR_CSO_N

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

CHGR_CSO_R_N

1TO1_DIFFPAIR

SMBUS_SMC_2_G3_SDA

SMB_45S_R_50S

SMB

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_2_G3_SCL

SMBUS_SMC_2_S3_SCL

SMB_45S_R_50S

SMB

SMBUS_SMC_2_G3_SCL_R

SMB

SMB_45S_R_50S

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_2_G3_SDA_R

SMBUS_SMC_2_S3_SDA

SMB

SMB_45S_R_50S

SENSE_DIFFPAIR

CHGR_CSI_N

1TO1_DIFFPAIR

SENSE_DIFFPAIR

CHGR_CSI_P

1TO1_DIFFPAIR

SMBUS_SMC_1_S0_SDA

SMB

SMBUS_SMC_1_S0_SDA

SMB_45S_R_50S

<SCH_NUM>

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14

31 34 36 53 68

30 31 34 40

31 34 41 43

43

31 34 46 48

43

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

12

D

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

NET_TYPE

RF Interface Constraints

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPACING

J92 MLB Specific Net Properties

I346

I347

I348

I349

I350

I351

I352 I353

I354

I355

I356

I357

I358

I359

I370

I371

I372

I373

I374 I375

I376 I377

I378

I379 I380

I381 I382

I383

I384 I385

I386

I387

I388

I389

I390

I391

I392 I393

I394

I395

I396

I397

GND_P2MM

GND *

CPU_COMP

CPU_VCCSENSE

GND *

GND_P2MM

CLK_PCIE

*GND

GND_P2MM

=45_OHM_SE

=1TO1_DIFFPAIR

SENSE_1TO1_45S =1TO1_DIFFPAIR=1TO1_DIFFPAIR

*

=45_OHM_SE=45_OHM_SE

=1TO1_DIFFPAIR=1TO1_DIFFPAIR

=1TO1_DIFFPAIR

SPKR_DIFFPAIR

0.100 MM

=1TO1_DIFFPAIR

*

0.400 MM

=2:1_SPACING

?

THERM

*

PCIE*

GND_P2MM

GND *

*

LVDS*

GND

GND_P2MM

SATA*

SB_POWER PWR_P2MM

*

=1:1_SPACING

?*

SENSE

10000

0.20 MM

*

GND_P2MM

PWR_P2MM

0.20 MM

*

10000

0.15 MM

RF * ?

GND

GND_P2MM

SATA*

*

=45_OHM_SE

=1TO1_DIFFPAIR

SENSE_1TO1_P2MM

=1TO1_DIFFPAIR=1TO1_DIFFPAIR

0.200 MM

*

=50_OHM_SE_RF

=50_OHM_SE_RF=50_OHM_SE_RF=50_OHM_SE_RF

RF_50S

=STANDARD

*

=STANDARD

=1TO1_DIFFPAIR

*

=45_OHM_SE =45_OHM_SE

=1TO1_DIFFPAIR=1TO1_DIFFPAIRTHERM_1TO1_45S

=45_OHM_SE

=1TO1_DIFFPAIR

SENSE_1TO1_P3MM

0.300 MM

=1TO1_DIFFPAIR

*

=1TO1_DIFFPAIR

USB* GND_P2MM

*GND

PWR_P2MMSB_POWER

SATA*

*

PWR_P2MMCLK_PCIESB_POWER

*GND

=STANDARD

?

=2:1_SPACING

AUDIO

* ?

SYNC_DATE=04/08/2014

SYNC_MASTER=J92_DEVMLB

Project Specific Constraints

DP_TX

DP_EXT_ML

DP_80D

DP_EXT_ML_P<1..0>

USB3_PCH_TX

DPRUSB3_EXTA_R2D_N

USB_80D

USB3_EXTA_TX

RF_1_ANT_MATCH_T

RF_50S

RF

RF_1_ANT

RF

RF_50S

RF_G_1_MATCH

RF

RF_G_1_DIPLEXER

RF_50S

RF

RF_0_ANT

RF

RF_50S

RF_A_0_MATCH

RF_50S

RF

SPKR_OUT

SPKR_DIFFPAIR

AUDIO

SPKRAMP_LOUT2_P

USB3_PCH_RX

DPRUSB3_EXTA_D2R_N

USB3_EXTA_RX

USB_80D

PP3V3_S5

SB_POWER SB_POWER

PP3V3_S0

RF_A_0_DIPLEXER

RF_50S

RF

RF_G_0_DIPLEXER

RF

RF_50S

RF_G_0_MATCH

RF

RF_50S

SPKR_OUT

SPKR_DIFFPAIR

AUDIO

SPKRAMP_LOUT2_N

RF_A_1_MATCH

RF_50S

RF

RF_0_ANT_MATCH_T

RF

RF_50S

SENSE_1TO1_P3MM

SENSE

SENSE_DIFFPAIR

ISNS_1V2_S3_P

INLET_THMSNS_D1_N

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

SENSE_DIFFPAIR

INLET_THMSNS_D1_P

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_HS_GAIN_P

SENSE_DIFFPAIR

ISNS_LCDBKLT_P

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

ISNS_LCDBKLT_N

SENSE_1TO1_45S

SENSE

RF_A_1_DIPLEXER

RF

RF_50S

SPKR_DIFFPAIR

AUDIO

SPKR_OUT

SPKRAMP_LOUT1_N

SPKR_DIFFPAIR

AUDIO

SPKR_OUT

SPKRAMP_LOUT1_P

SPKR_OUT

AUDIO

SPKR_DIFFPAIR

SPKRAMP_ROUT2_P

SPKR_OUT

AUDIO

SPKR_DIFFPAIR

SPKRAMP_ROUT2_N

SPKR_OUT

SPKR_DIFFPAIR

SPKRAMP_ROUT1_N

AUDIO

SPKR_OUT

AUDIO

SPKR_DIFFPAIR

SPKRAMP_ROUT1_P

MAX98300_R_N

AUDIO

1TO1_DIFFPAIR

MAX98300_R_P

1TO1_DIFFPAIR

AUDIO

ISNS_HS_GAIN_N

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

CPUVR_ISNS2_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45S

CPUVR_ISNS2_P

SENSE_DIFFPAIR

SENSE

ISNS_HS_COMPUTING_N

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE

ISNS_HS_COMPUTING_P

SENSE_1TO1_45S

USB3_PCH_TX

DPRUSB3_EXTA_R2D_P

USB_80D

USB3_EXTA_TX

DP_TX

DP_EXT_ML

DP_80D

DP_EXT_ML_N<1..0>

USB3_PCH_RX

USB_80D

DPRUSB3_EXTA_D2R_P

USB3_EXTA_RX

USB_EXTA

USB

USB_80D

DPRUSB_EXTA_N

USB_80D

DPRUSB_EXTA_P

USB

USB_EXTA

DP_TX

DP_80D

DP_EXT_ML_C_N<1..0>

DP_TX

DP_80D

DP_EXT_ML_C_P<1..0>

CPUTHMSNS_D2_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

CPUTHMSNS_D2_N

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

CPUVR_ISNS1_N

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

CPUVR_ISNS1_P

SENSE_1TO1_P2MM

SENSE_DIFFPAIR

SENSE

ISNS_1V05_SUS_N

SENSE_1TO1_P2MM

SENSE_DIFFPAIR

ISNS_1V05_SUS_P

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_P3MM

ISNS_1V2_S3_N

SENSE

GND

<SCH_NUM>

118 OF 130

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38 40

8

11 13 15 16

17 22 33 37 46 47

51 59 60 75 8

11 12 13 15

17 18 23 24 29 32

33 34 35 36 40 46 47 53 60 75

22

38 40

22

46

36

35 36

49

22

38 40

39 40

35 36

45

35

36

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48

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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DRAWING NUMBER

REVISION

BRANCH

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Other Info:

Change List:

Kismet:

MobileMac HW Radar:

Schematic Design Wiki - <https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design>

<radar://component/497591> MobileMac HW | Task

<radar://component/497588> MobileMac HW | Layout

<radar://component/497585> MobileMac HW | New Bugs

<radar://component/497589> MobileMac HW | Architecture

Page Allocations - <radar:11791318> 2012 Schematic Page Allocations

Schematic Conventions - <https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions>

Useful Wiki Links:

<radar://component/497587> MobileMac HW | Schematic

<radar://component/497590> MobileMac HW | Investigation

<radar://component/XXXXXX> J92 HW EE SCHEMATIC | PROTO 0

<afp://kismet.apple.com/Kismet-Projects/J92/>

SYNC_DATE=07/15/2013

Reference

SYNC_MASTER=J92_DEVMLB

<SCH_NUM>

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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REVISION

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Power State Debug LEDs

5%

1/20W

MF

201

75K

RD096

1

2

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

PLACE_SIDE=TOP

DD096

A

K

GREEN-56MCD-2MA-2.65V

PLACE_SIDE=TOP

LTQH9G-SM

DD097

A

K

20K

1/20W

MF

5%

201

RD098

1

2

201

5%

1/20W

MF

20K

RD095

1

2

PLACE_SIDE=TOP

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

DD095

A

K

20K

MF

1/20W

5%

201

RD094

1

2

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=TOP

DD094

A

K

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

Debug Support

PP3V3_S5

DBGLED_S5

PP5V_S4

DBGLED_S0

PP3V3_S0

PM_SLP_S0_L

DBGLED_S0I

DBGLED_S4

<SCH_NUM>

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16 17 22 33 37 46

47 51 59 60 73

30 38 47 53 60

8

11 12 13

15 17 18 23

24 29 32 33 34 35 36 40 46 47

53 60 73

13 31 33 46

Apple MacBook 12'' Retina A1534 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual