Apple A1386 Schematics

TABLE_TABLEOFCONTENTS_ITEM

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

SCHEM,CORNHOLE,K19

Schematic / PCB #’s

PVT 04/24/2009

ALIASES RESOLVED

(.csa)

Date

SyncPage Contents

LAST_MODIFIED=Fri Apr 24 15:23:24 2009

TITLE=MLB

ABBREV=DRAWING

91

02/18/2008

103

MUXGFX

MCP Constraints 2

Date

SyncContents

(.csa)

Page

53

08/14/2008

46

SENSOR

Current & Voltage Sensing

(.csa)

Page

Date

Contents Sync

820-2523

1

CRITICAL

PCBF,CORNHOLE,K19

PCB

051-7892

SCH

1

CRITICAL

SCHEM,CORNHOLE,K19

DDR

1

12/05/2008

1

Table of Contents

92

02/18/2008

104

MUXGFX

Ethernet Constraints

93

02/18/2008

105

MUXGFX

FireWire Constraints

94

02/18/2008

106

MUXGFX

SMC Constraints

95

02/18/2008

107

MUXGFX

GPU (G96) CONSTRAINTS

96

02/21/2008

108

MUXGFX

Project Specific Constraints

97

01/22/2008

109

M99_MLB

PCB Rule Definitions

54

12/10/2008

47

YUN_K19_MLB

Current Sensing

55

12/22/2008

48

YUN_K19_MLB

Thermal Sensors

56

10/17/2007

49

M87_MLB

Fan Connectors

57

06/18/2008

50

AMASON_M98_MLB

WELLSPRING 1

58

01/05/2009

51

PWRSQNC

WELLSPRING 2

59

08/14/2008

52

SENSOR

Sudden Motion Sensor (SMS)

60

12/19/2008

53

DDR

DEBUG SENSORS AND ADC

61

07/01/2008

54

CHANG_M98_MLB

SPI ROM

62

03/16/2009

55

AUDIO

AUDIO: CODEC/REGULATOR

63

03/16/2009

56

AUDIO

AUDIO: LINE INPUT FILTER

65

03/16/2009

57

AUDIO

AUDIO: HEADPHONE FILTER

66

03/16/2009

58

AUDIO

AUDIO: SPEAKER AMP

67

03/16/2009

59

AUDIO

AUDIO: JACKS

68

03/16/2009

60

AUDIO

AUDIO: JACK TRANSLATORS

69

12/16/2008

61

YUN_K19_MLB

DC-In & Battery Connectors

70

12/10/2007

62

M99_MLB

PBus Supply & Battery Charger

71

10/17/2007

63

M87_MLB

IMVP6 CPU VCore Regulator

72

12/17/2008

64

PWRSQNC

5V / 3.3V Power Supply

73

12/05/2008

65

DDR

1.5V DDR3 Supply

75

11/14/2008

66

M98_MLB

MCP CORE REGULATOR

76

12/14/2007

67

M99_MLB

CPU VTT / 1V05 S0 Power Supply

77

12/14/2007

68

M99_MLB

Misc Power Supplies

78

12/17/2008

69

PWRSQNC

Power Control

79

12/05/2008

70

DDR

Power FETs

80

07/10/2008

71

MUXGFX

NV G96 PCI-E

81

07/10/2008

72

MUXGFX

NV G96 Core/FB Power

82

07/10/2008

73

MUXGFX

NV G96 Frame Buffer I/F

84

07/10/2008

74

MUXGFX

GDDR3 Frame Buffer A (Top)

85

07/10/2008

75

MUXGFX

GDDR3 Frame Buffer B (Top)

86

07/10/2008

76

MUXGFX

NV G96 GPIO/MIO/Misc

87

07/09/2008

77

MUXGFX

G96 GPIOs & Straps

88

07/10/2008

78

MUXGFX

NV G96 Video Interfaces

89

10/17/2007

79

M87_MLB

GPU (G96) CORE SUPPLY

90

12/19/2008

80

DDR

LVDS Display Connector

93

12/05/2008

81

AMASON_M98_MLB

Muxed Graphics Support

94

07/10/2008

82

MUXGFX

DisplayPort Connector

95

07/10/2008

83

MUXGFX

1.1V / 1V8 FB Power Supply

96

07/10/2008

84

MUXGFX

Graphics MUX (GMUX)

97

12/12/2008

85

DDR

LCD BACKLIGHT DRIVER

98

07/02/2008

86

YITE_M98_MLB

LCD Backlight Support

99

02/01/2008

87

MUXGFX

Misc Power Supplies

100

02/18/2008

88

MUXGFX

CPU/FSB Constraints

101

02/18/2008

89

MUXGFX

Memory Constraints

102

02/18/2008

90

MUXGFX

MCP Constraints 1

T18_MLB

2

12/12/2007

2

System Block Diagram

T18_MLB

3

12/12/2007

3

Power Block Diagram

N/A

4

N/A4

Power Block Diagram

DDR

5

12/18/2008

5

BOM Configuration

DDR

6

07/22/2008

6

JTAG Scan Chain

N/A

7

N/A7

Functional / ICT Test

(MASTER)

8

(MASTER)

8

Power Aliases

(MASTER)

9

(MASTER)

9

Signal Aliases

M98_MLB

10

11/12/2008

10

CPU FSB

M98_MLB

11

11/12/2008

11

CPU Power & Ground

M87_MLB

12

10/17/2007

12

CPU Decoupling & VID

M98_MLB

13

11/12/2008

13

eXtended Debug Port(MiniXDP)

T18_MLB

14

12/12/2008

14

MCP CPU Interface

T18_MLB

17

04/04/2008

17

MCP PCIe Interfaces

T18_MLB

18

12/12/2008

18

MCP Ethernet & Graphics

T18_MLB

19

12/12/2008

19

MCP PCI & LPC

T18_MLB

20

12/12/2008

20

MCP SATA & USB

T18_MLB

21

12/12/2008

21

MCP HDA & MISC

T18_MLB

22

12/12/2008

22

MCP Power & Ground

T18_MLB

23

03/31/2008

24

MCP79 A01 Silicon Support

T18_MLB

24

06/18/2008

25

MCP Standard Decoupling

AMASON_M98_MLB

25

06/18/2008

26

MCP Graphics Support

DDR

26

12/15/2008

28

SB Misc

DDR

27

12/05/2008

29

FSB/DDR3/FRAMEBUF Vref Margining

DDR

28

07/22/2008

31

DDR3 SO-DIMM Connector A

DDR

29

07/22/2008

32

DDR3 SO-DIMM Connector B

T18_MLB

30

12/12/2008

33

DDR3 Support

MUXGFX

31

12/08/2008

34

Right Clutch Connector

VEMURI

32

01/30/2009

35

SECUREDIGITAL CARD READER

SUMA_M98_MLB

33

07/01/2008

37

Ethernet PHY (RTL8211CL)

SUMA_M98_MLB

34

07/01/2008

38

Ethernet & AirPort Support

AMASON_M98_MLB

35

12/16/2008

39

Ethernet Connector

SENSOR

36

08/14/2008

41

FireWire LLC/PHY (FW643)

YUN_K19_MLB

37

12/22/2008

42

FireWire Port Power

SENSOR

38

08/14/2008

43

FireWire Ports

PWRSQNC

39

12/04/2008

45

SATA Connectors

M98_MLB

40

11/14/2008

46

External USB Connectors

PWRSQNC

41

12/04/2008

48

Front Flex Support

T18_MLB

42

12/12/2008

49

SMC

DDR

43

12/19/2008

50

SMC Support

CHANGZHANG

44

05/09/2008

51

LPC+SPI Debug Connector

DDR

45

12/19/2008

52

K19 SMBUS CONNECTIONS

A.0.0

SCHEM,MBP 15MLB

??

?

1

051-7892

97

?

T18_MLB

16

12/12/2008

16

MCP Memory Misc

T18_MLB

15

12/12/2008

15

MCP Memory Interface

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PG 9

PG 60

AmpAmp

Line In

U3700

Mini PCI-E

AirPort

PG 18

RGMII

HDMI OUT

DP OUT

LVDS OUT

PG 17

UP TO 20 LANES3

PG 16

PCI-E

DVI OUT

U1400

Boot ROM

PG 52

Bluetooth

7650 1

DIMM’s

SMB

CONN

PG 44

Connectors

CAMERA

PG 41

NVIDIA

HDA

PG 20

SMB

PG 24

FSB INTERFACE

PG 13

PG 38

RGB OUT

1.05V/3GHZ.

SATA

GPIOs

LPC Conn

Port80,serial

PG 14

Misc

PWR

BSB

Prt

B,0

SMC

ADC Fan

Ser

PG 43

J5100

FAN CONN AND CONTROL

TEMP SENSOR

SPI

PG 25,26

DIMM

J2900

DDR3-1067/1333MHZ

DDR2-800MHZ

800/1067/1333 MHz

MAIN

MEMORY

PG 18

PG 20

SPI

INTEL CPU

2.X OR 3.X GHZ

PENRYN

DC/BATT

J4900

PG 48,49

J5650,5600,5610,5611,5660,5720,5730,5750

POWER SENSE

PG 45

USB

TRACKPAD/

KEYBOARD

PG 40

USB

EXTERNAL

J3900,4635,4655

U6100

PG 39

SYNTH

Conn

ODD

E-NET

HD

PG 40

J4700

PG 40

U6600,6605,6610,6620

J4510

U1300

U1000

PG 12

J6950

U4900

J4710

PG 57

J4720

U6200

PG 53

PG 54

Amps

Speaker

Amp

E-NET

GB

PG 31

88E1116

Conn

PG 33

U3900 J3400

PG 28

POWER SUPPLY

XDP CONN

2 UDIMMs

64-Bit

FSB

Codec

Audio

HEADPHONE

PG 55 PG 56

PG 59

U6400 U6500U6301

SATA

PG 40

983

LPC

PG 19

PCI

PG 19

MCP79

PG 41

J6800,6801,6802,6803

Conns

(UP TO FOUR PORTS)

SATA

CLK

J4710

IR

CTRL

2

Line Out

TMDS OUT

4

(UP TO 12 DEVICES)

PG 17

J4520

Conn

PG 71

CONN

PG 71

LVDS CONN

J9000

DISPLAY PORT

J9400

SYNC_MASTER=T18_MLB

051-7892

97

2

A.0.0

SYNC_DATE=12/12/2007

System Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

M98 POWER SYSTEM ARCHITECTURE

(6A MAX CURRENT)

CPU_PWRGD

(PAGE 43)

EN_PSV

1.05V

CHGR_EN

(S5)

PP5V_S3

PP3V3_S5

PPVIN_G3H_P3V42G3H

V

PPBUS_G3H

DELAY

EN1

VOUT2

ALL_SYS_PWRGD

RST*

PGOOD

U7100

VIN

VR_PWRGD_CLKEN_L

V

SMC_CPU_VSENSE

GPUVCORE_PGOOD

EN_PSV

SMC_BATT_ISENSE

PPVBAT_G3H_CHGR_REG

D6905

8A FUSE

U5715

(9 TO 12.6V)

P3V3S3_EN

P5VS3_EN

LIO_S3_EN

A

V

PPVCORE_GPU_REG

U5705

(PAGE 42)

P17(BTN_OUT)

PM_WLAN_EN_L

PM_ENET_EN

WOW_EN

Q3801

PGOOD

(S5)

SMC_PM_G2_EN

U7859

PBUSVSENS_EN

(S0)

MCP79

(S0)

VIN

VOUT

Q3810

SLP_S5#(H17)

SLP_S3#(G17)

(PAGE 14~22)

BKLT_EN

VIN

U4900

VOUT

D6905

VOUT

SMC_GPU_VSENSE

U5498

PGOOD

(PAGE 78)

IMVP_VR_ON_R

SMC PWRGD

PM_GPUVCORE_EN

AC

A

ENABLES

Q5315

PBUSB_VSENSE

P5V_RT_EN

P60

A

3S2P

U1400

(PAGE 14~22)

U1400

RSMRST*

MCP79

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

VR_PWRGOOD_DELAY

S5

RUN2

VOUT1

EN2

ENA

RUN1

S3

EN/PSV

RESET*

(PAGE 10,11)

PWRGOOD

PLTRST*

PWRBTN#

SMC

U1000

CPU

U2850

VOUT2

PGOOD1,2

VOUT2

U2830

VIN

A

VOUT

VR_ON

VIN

P1V8FB_EN

VOUT

ADAPTER

(L/H)

VIN

RN5VD30A-F

U5000

ENABLE

SMC_RESET_L

IN

VIN

EN2

VIN

ENL

VREG3

EN0

VIN

VOUT1

Q7055

LIO_DCIN_ISENSE

SMC

Q3805

DELAY

P3V3S0_EN

(S0)

PM_ENET_EN_L

Q7920

(PAGE 61)

PP1V1_S0GPU_REG

U5400

PPBUS_G3H

P1V1GPU_EN

EN1

VOUT1

(R/H)

P3V3S5_EN

VLDOIN

VOUT2

PPVCORE_CPU_S0

CPUVCORE_IOUT

VOUT2

VIN

PP5V_S0 PP3V3_S0

PP1V5_S0_REG

V4

V3

V2

V1

U7870

RST*

VOUT1

PP1V8_GPU_REG

V4

U9701

(PAGE 84)

(PAGE 64)

SC417

U7400

VIN

1.103V(L/H)

1.8V(R/H)

TPS51124

U9500

(PAGE 82)

5V

3.3V

TPS51125

U7201

(PAGE 62)

CPU VCORE

ISL9504B

ISL6263B

U8900

GPU VCORE

3.425V G3HOT

LT3470

U6990

(PAGE 59)

PP3V42_G3H_REG

VOUT

TPS51117

U7600

(PAG 66)

PGOOD

CPUVTTS0_EN

PPCPUVTT_S0_REG

CPUVTTS0_PGOOD

ISL8009

U7750

(PAGE 66)

(8A MAX CURRENT)

PP5V_S5_REG

(5.5A MAX CURRENT)

PP3V3_S5_REG

PP5V_RT_REG

P5V_RT_PGOOD

P5V3V3_S5_PGOOD

Q7970

Q7930

PPVOUT_S0_LCDBKLT

GOSHAWK6P

LTC3407

U3850

(PAGE 33)

PP1V9_ENET_REG

PP1V2_ENET_REG

ENETAVDD_EN

P1V2ENET_EN

PPVIN_S0_DDRREG_LDO

1.8V

0.9V

TPS51116

(PAGE 63)

U7300

DDRREG_EN

DDRVTT_EN

PM_ENET_EN_L

WOL_EN

Q3800

PM_SLP_S3_L

P5VS0_EN

P5VRIGHT_EN

P1V8S0_EN

MCPDDR_EN

CPUVTTS0_EN

MCPCORES0_EN

P1V05S0_EN

MCP_CORE

1.1V

U7500

ISL6236

(PAGE 65)

MCPCPCORE_S0_REG

PP5V_RT_REG

PPVTT_S0_DDR_LDO

PPDDR_S3_REG

(12A MAX CURRENT)

P3V3ENET_EN_L

P3V3_ENET_FET

P3V3GPU_SS

PP3V3_S0_FET

PP3V3_S3_FET

Q7910

P5VS3_SS

PP5V_S3_FET

Q7900

P5VS0_SS

P1V05S0_PGOOD

P5VRIGHT_PGOOD MCPCORES0_PGOOD CPUVTTS0_PGOOD

P1V8S0_PGOOD

LTC2900

(PAGE 68)

PP1V05_S5_MCP

IMVP_VR_ON(P16)

PWRGD(P12)

RSMRST_OUT(P15)

99ms DLY

PM_RSMRST_L

SMC_RESET_L

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

U4900

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S5_L

(PAGE 60) PBUS SUPPLY/ BATTERY CHARGER

ISL6258A

U7000

DCIN(16.5V)

6A FUSE

BATT_POS_F

J6950

CHGR_BGATE

PPVBAT_G3H_CHGR_R

SMC_ADAPTER_EN

PM_SLP_S3_DELAY_L

(5A MAX CURRENT)

(25A MAX CURRENT)

PP5V_S0_FET

VRMPWRGD

VR_PWRGD_CLKEN

CK_PWRGD

PLT_RST_L

CPUPWRGD(GPIO49)

PWROK

MCP_PS_PWRGD

RSMRST_PWRGD

SMC_ONOFF_L

PM_PWRBTN_L

PWR_BUTTON(P90)

PLT_RST*

IMVP_VR_ON

RSMRST_IN(P13)

GPUVCORE_IOUT

(18A MAX CURRENT)

P3V3S3_SS

P1V5S0_PGOOD

S0PGOOD_PWROK

(PAGE 42)

P3V3S0_SS

PP3V3_S0GPU_FET

SYNC_MASTER=T18_MLB

051-7892

97

A.0.0

SYNC_DATE=12/12/2007

3

Power Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SYNC_MASTER=N/A

SYNC_DATE=N/A

4

97

A.0.0

051-7892

Power Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Development BOM

Module Parts

Bar Code Labels / EEE #’s

K19 BOM Groups

BOM Variants

KEMET ALT TO SANYOALL

128S0262128S0220

338S0554338S0714

Low Leakage G96 GPU

ALL

CYNTEC alt to YDS

ALL

107S0139 107S0075

138S0602

ALL

Murata alt to Samsung

138S0603

353S1294

ALL LMV2011,OPAMP. GBW

353S1681

152S0683

ALL

Maglayers alt to Dale/Vishay

152S0276

341S2366

ALL

Macronix alt to SST

341S2367

152S0867

Toko alt to Delta

152S1034

ALL

Delta alt to TDK Magnetics157S0055157S0058

Maglayers alt to Cyntec IND

ALL

152S0915 152S0796

ALL

ROHM ALT TO KEMET

127S0062 127S0108

152S0968 152S0966

Maglayer alt to Delta

ALL

CYNTEC alt to YDS

ALL

107S0138 107S0074

NXP alt to TI

311S0447 311S0406

ALL

K19_COMMON

ALTERNATE,COMMON,K19,K19_COMMON1,K19_COMMON2,K19_PROGPARTS

085-0736

K19 MLB DEVELOPMENT

K19_DEVEL_PVT

K19_COMMON1

BOOT_MODE_USER,DPMUX_EN_S0,DP_CA_DET_EG_PLD,DP_ESD,EG_PWRSEQ_HW,EXTRACT_BUFF

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

K19_PROGPARTS

BMON_PROD,LPCPLUS_NOT,NO_VREFMRGN

K19_PROD

K19_DEVEL_ENG

BMON_ENG,DEBUG_ADC,GMUX_JTAG,LPCPLUS,VREFMRGN,XDP_CONN

K19_DEVEL_PVT

BMON_PROD,LPCPLUS,NO_VREFMRGN,XDP_CONN

GMUX_1V8,GPUVID_1P00V,GPU_SS_INT,ISL6258A,MCP_B03,MCPSEQ_SMC,MIKEY,MUXGFX,SMC_DEBUG_YES,XDP

K19_COMMON2

K19_COMMON,DEVEL_BOM,EEE_6XT,CPU_3_06GHZ,FB_512_HYNIX

630-9970

PCBA,3.06GHZ,512HYN_VRAM,HB_AUDIO,K19

FB_256_SAMSUNG

VRAM4,VRAM_256_SAMSUNG

FB_512_SAMSUNG

VRAM4,VRAM_512_SAMSUNG

VRAM4,VRAM_512_HYNIX

FB_512_HYNIX

CRITICAL

EEE_6XN

[EEE:6XN]

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

1

EEE_6XP

[EEE:6XP]

826-4393 CRITICAL

[EEE:6XQ]

1

CRITICAL

EEE_6XQ

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

CRITICAL

1

EEE_6XR

[EEE:6XR]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEE:6XT]

EEE_6XT

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL

EEE_6XS

[EEE:6XS]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

337S3761

1

CRITICAL

U1000

IC,PDC,SLGLA,PRQ,2.66G,25W,1066,R0,3M,BGA

CPU_2_66GHZ

U1400

MCP_B03

338S0710 CRITICAL

IC,MCP79MXT-B3,35X35MM,BGA1437

1

CPU_3_06GHZ

U1000

1

CRITICAL337S3744

IC,PDC,SLGKH,QS,3.06G,35W,1066,E0,6M,BGA

CRITICAL

1

U1000

337S3682

IC,PDC,SLGEM,PRQ,2.80G,35W,1066,E0,6M,BGA

CPU_2_80GHZ

CRITICAL338S0694

U3700

1

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP

U4800

1

CRITICAL341S2384

IR,ENCORE II, CY7C63803-LQXC

1

U4100

CRITICAL338S0654

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

SMC_BLANK

CRITICAL

U4900

338S0563

1

IC,SMC,HS8/2117,9MMX9MM,TLP

341S2503

U5701

CRITICAL

IC,PSOC +W/USB,56PIN,MLF,K19

1

TPAD_PROG

SMC_PROG

1

U4900

IC,SMC,DEVELOPMENT,K19

341S2462 CRITICAL

1

U6100

BOOTROM_BLANK

335S0384 CRITICAL

IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

U6100

CRITICAL

IC,EFI ROM,DEVELOPMENT,K19

1

BOOTROM_PROG

341S2456

CRITICAL

4

U8400,U8450,U8500,U8550

VRAM_256_SAMSUNG

333S0507

IC,SGRAM,GDDR3,16Mx32,1000MHZ,136 FBGA

1

IC,GPU,55nm,NV G96-GS,BGA969,LF

U8000 CRITICAL

338S0554

CRITICAL

VRAM_256_HYNIX

4

333S0483

U8400,U8450,U8500,U8550

IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA

CRITICAL

1

085-0736

DEVEL_BOM

DEVEL

K19 MLB DEVELOPMENT

IC,SGRAM,GDDR3,32Mx32,800MHZ,136 FBGA

333S0511

VRAM_512_SAMSUNG

CRITICAL

4

U8400,U8450,U8500,U8550

CRITICAL

U8400,U8450,U8500,U8550

4

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

VRAM_512_HYNIX

333S0506

FB_256_HYNIX

VRAM4,VRAM_256_HYNIX

K19_COMMON,DEVEL_BOM,EEE_6XS,CPU_3_06GHZ,FB_512_SAMSUNG

630-9969

PCBA,3.06GHZ,512SAM_VRAM,HB_AUDIO,K19

K19_COMMON,DEVEL_BOM,EEE_6XR,CPU_2_80GHZ,FB_512_HYNIX

630-9968

PCBA,2.80GHZ,512HYN_VRAM,HB_AUDIO,K19

K19_COMMON,DEVEL_BOM,EEE_6XQ,CPU_2_80GHZ,FB_512_SAMSUNG

PCBA,2.80GHZ,512SAM_VRAM,HB_AUDIO,K19

630-9967

K19_COMMON,DEVEL_BOM,EEE_6XP,CPU_2_66GHZ,FB_256_HYNIX

PCBA,2.66GHZ,256HYN_VRAM,HB_AUDIO,K19

630-9966

K19_COMMON,DEVEL_BOM,EEE_6XN,CPU_2_66GHZ,FB_256_SAMSUNG

630-9965

PCBA,2.66GHZ,256SAM_VRAM,HB_AUDIO,K19

A.0.0

SYNC_DATE=12/18/2008

SYNC_MASTER=DDR

051-7892

97

5

BOM Configuration

IN

B1

OE*

VCCB

B2 B3 B4

GND

A4

A3

A2

A1

VCCA

OUT

GND

VCC

NCNC

YA

NC NC

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

or via level translator

U8000

GMUX CPLD Programming Port

TDO

From XDP connector

GPU

U9200

GMUX

MCP

U1400

From XDP connector

U1000

CPU

To XDP connector and/or level translator

XDP connector

TMS

TCK

TDI

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

6

10 13 88

JTAG_ALLDEV

NLSV4T244

UQFN

11

1

12

6

7

8

9

10

5

4

3

2

U0600

0.1UF

20%

402

10V CERM

JTAG_ALLDEV

2

1

C0601

JTAG_ALLDEV

402

CERM

10V

20%

0.1UF

2

1

C0602

402

MF-LF

1/16W

10K

5%

JTAG_ALLDEV

2

1

R0601

NOSTUFF

402

MF-LF

5%

1/16W

0

2

1

R0602

13

M-RT-SM

CRITICAL

1909782

GMUX_JTAG

6

5

4

3

2

1

8

7

J0600

PLACEMENT_NOTE=Place near pin U1000.AB3

XDP

0

5% 1/16W MF-LF

402

21

R0603

0

1/16W MF-LF

5%

402

XDP

PLACEMENT_NOTE=Place near pin U1400.F19

21

R0604

SOT886

74LVC1G07

PLACEMENT_NOTE=Place close to U0600

4

6

5

1

3

2

U0601

PLACEMENT_NOTE=Place close to U8000

402

10K

1/16W MF-LF

5%

NOSTUFF

21

R0605

402

MF-LF

1/16W

5%

10K

2

1

R0606

5%

MF-LF

1/16W

0

402

21

R0607

6

10 13 88

6

10 13 88

13

JTAG Scan Chain

SYNC_DATE=07/22/2008

SYNC_MASTER=DDR

6

97

A.0.0

051-7892

XDP_TDO

JTAG_GMUX_TDO

PP3V3_S0

XDP_TRST_L

XDP_TDO_CONN

XDP_TDI

XDP_TCK

XDP_TRST_L

PP3V3_S0GPU

GPU_JTAG_TMS

JTAG_MCP_TDO_CONN

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

JTAG_MCP_TCK

GPU_JTAG_TMS

JTAG_GMUX_TCK

XDP_TCK

JTAG_MCP_TRST_L

MAKE_BASE=TRUE

PPCPUVTT_S0

JTAG_GMUX_TDI

JTAG_GMUX_TMS

JTAG_MCP_TRST_L

JTAG_LVL_TRANS_EN_L

XDP_TMS

PP3V3_S0

JTAG_MCP_TMS

XDP_TMS

GPU_JTAG_TDI

JTAG_MCP_TDO

JTAG_MCP_TDI

MAKE_BASE=TRUE

JTAG_MCP_TCK

10 88

9

17 84

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6

10 13 88

8

69 70 76 77 79 81

6

76

6

76

6

76

6

13 21 76

6

76

84

6

10 13 88

6

13 21 76

7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

9

19 84

9

19 84

6

13 21 76

6

10 13 88

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

13 21

76

21

13 21

6

13 21 76

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Batt Signal Connector

Keyboard Connector

FUNC_TEST

Power Nets

Functional Test Points

DC Power Connector

3 TPs

SATA ODD Connectors

FUNC_TEST

LVDS Connector

2 TPs

5 TPs

FUNC_TEST

Fan Connectors

FUNC_TEST

3 TPs

ICT Test Points

NO_TEST

FUNC_TEST

KBD Backlight Conn.

SD Card Connector

NO_TEST properties are also on page9,26,43,50

Note.

3 TPs

6 TPs

5 TPs

FUNC_TEST

2 TPs

FUNC_TEST

6 TPs

Speaker Connectors

FUNC_TEST

4 TPs

3 TPs

IPD Flex Connector

6 TPs

4 TPs

FUNC_TEST

2 TPs

FUNC_TEST

3 TPs

FUNC_TEST

3 TPs

FUNC_TEST

SATA HDD Connector

FUNC_TEST

6 TPs

3 TPs

Battery Connector

2 TPs

NO_TEST

FUNC_TEST

10 TPs

Airport/BT/Camera Conn.

SYNC_DATE=N/A

SYNC_MASTER=N/A

Functional / ICT Test

7

97

A.0.0

051-7892

PPVOUT_S0_LCDBKLT

TRUE

FSB_ADS_L

TRUE

NC_ENET_PWRDWN_L

MAKE_BASE=TRUE

TRUE

NC_ENET_INTR_L

MAKE_BASE=TRUE

NC_USB_10P

TRUE

FAN_RT_PWM

PCIE_MINI_D2R_P

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PP3V3_S3_BT_F

TRUE

PP5V_S3_BTCAMERA_F

TRUE

PP5V_WLAN

TRUE

MINI_RESET_CONN_L

TRUE

MINI_CLKREQ_Q_L

TRUE

PCIE_CLK100M_MINI_CONN_N

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

PCIE_MINI_R2D_P

BKL_ISEN3

TRUE

BKL_ISEN1

TRUE

KBDLED_ANODE

WS_KBD20

TRUE

PCIE_WAKE_L

TRUE

PCIE_MINI_R2D_N

TRUE

PCIE_MINI_D2R_N

TRUE

WS_KBD21

TRUE

WS_KBD_ONOFF_L

TRUE

WS_CONTROL_KBD

TRUE

FSB_LOCK_L

TRUE

FSB_DSTB_L_P<3..0>

FSB_DINV_L<3..0>

TRUE

FSB_ADSTB_L<1..0>

NC_SB_A20GATE

NC_SATA_D_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RP

TRUE

MAKE_BASE=TRUE

NC_SB_A20GATE

FSB_DSTB_L_N<3..0>

TRUE

USB_BT_N

TRUE

USB_BT_P

TRUE

USB_CAMERA_N

TRUE

USB_CAMERA_P

TRUE TRUE

SATA_ODD_D2R_UF_N

NC_PCIE_CLK100M_PE6P

NC_PCIE_PE4_D2RN

NC_PCIE_PE4_R2D_CN

NC_PE4_PRSNT_L

NC_PCI_INTZ_L

NC_PCI_GNT1_L

NC_PCI_CLK0

NC_USB_10P

NC_AUD_LO1_N_L

NC_ENET_PWRDWN_L

NC_MEM_A_CLK2N

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK3P

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK4P

TRUE

PP3V3_S0

TRUE

PP3V3_S3

PP1V8R1V5_S3

TRUE

LED_RETURN_1

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PICKB_L

PP5V_S3_IR_R

TRUE

SATA_HDD_D2R_C_P

TRUE

IR_RX_OUT

SATA_ODD_D2R_UF_P

TRUE

DP_ML_C_P<3..0>

TRUE

FSB_HIT_L

FSB_D_L<63..0>

TRUE

PPVBAT_G3H_CONN

SMC_ODD_DETECT

TRUE

SATA_ODD_R2D_N

TRUE

PP18V5_DCIN_FUSE

TRUE

SMBUS_SMC_BSA_SCL

WS_KBD19

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMC_KDBLED_PRESENT_L

KBDLED_ANODE

TRUE

SYS_LED_ANODE_R

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_R2D_P

TRUE

PP5V_S0_HDD_FLT

TRUE

USB_CAMERA_CONN_N

TRUE

CONN_USB2_BT_P

TRUE

USB_CAMERA_CONN_P

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD16_NUM

WS_KBD12

TRUE

SATA_ODD_D2R_C_N

PP5V_SW_ODD

TRUE

SPKRCONN_S_OUT_P

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_L_OUT_N

BI_MIC_HI

TRUE

SPKRCONN_L_OUT_P

TRUE

BI_MIC_LO

TRUE

BI_MIC_SHIELD

TRUE

SD_WP

TRUE

SD_CD_L

SD_CMD

TRUE TRUE

SD_CLK

TRUE

SD_D<7..0>

TRUE

PSOC_F_CS_L

TRUE

SMBUS_SMC_A_S3_SCL

PSOC_MOSI

TRUE TRUE

PSOC_SCLK

PSOC_MISO

TRUE

Z2_KEY_ACT_L

TRUE TRUE

Z2_RESET

Z2_CLKIN

TRUE

Z2_HOST_INTN

TRUE

Z2_SCLK

TRUE

Z2_MISO

Z2_MOSI

TRUE

Z2_DEBUG3

TRUE

Z2_CS_L

PP18V5_S3

TRUE

PP3V3_S3_LDO

TRUE

BKL_ISEN6

BKL_ISEN5

TRUE

LED_RETURN_6

TRUE

LED_RETURN_4

TRUE

LED_RETURN_3

LED_RETURN_2

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_DATA_P<1>

TRUE

LVDS_CONN_A_CLK_F_P

TRUE

PPVOUT_S0_LCDBKLT

TRUE

PP3V3_SW_LCD

TRUE

SATA_ODD_D2R_C_P

Z2_BOOST_EN

TRUE

WS_KBD10

TRUE

PP3V42_G3H

TRUE

SMC_BIL_BUTTON_L

TRUE

PP18V5_S3

TRUE

WS_KBD6

TRUE

FSB_HITM_L

FSB_A_L<31..3>

TRUE

BKL_ISEN2

TRUE

LED_RETURN_5

TRUE

CONN_USB2_BT_N

SPKRCONN_S_OUT_N

TRUE

SATA_ODD_R2D_P

TRUE

WS_KBD15_CAP

TRUE

PP3V42_G3H

TRUE

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3..0>TP_PCI_C_BE_L<3..0>

TRUE

NC_PCI_CLK0

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK1

MAKE_BASE=TRUE

NC_PCI_CLK1

TRUE

NC_PCI_DEVSEL_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCI_FRAME_LNC_PCI_FRAME_L

TRUE

NC_PCI_GNT0_L

MAKE_BASE=TRUE

NC_PCI_GNT0_L

TRUE

NC_PCI_GNT1_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCI_INTW_LNC_PCI_INTW_L

TRUE

NC_PCI_INTX_L

MAKE_BASE=TRUE

NC_PCI_INTX_L

TRUE

NC_PCI_INTZ_L

MAKE_BASE=TRUE

TRUE

NC_PCI_IRDY_L

MAKE_BASE=TRUE

NC_PCI_IRDY_L

TRUE

MAKE_BASE=TRUE

NC_PCI_PERR_LNC_PCI_PERR_L

TRUE

NC_PCI_RESET1_L

MAKE_BASE=TRUE

NC_PCI_RESET1_L

TRUE

NC_PCI_SERR_L

MAKE_BASE=TRUE

NC_PCI_SERR_L

TRUE

NC_PCI_STOP_L

MAKE_BASE=TRUE

NC_PCI_STOP_L

TRUE

NC_PCI_TRDY_L

MAKE_BASE=TRUE

NC_PCI_TRDY_L

TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

TRUE

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5P

TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE4_D2RN

MAKE_BASE=TRUE

TRUE

NC_PE4_PRSNT_L

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

NC_PSOC_P1_3

TRUE

NC_PSOC_SDA

MAKE_BASE=TRUE

NC_PSOC_SDA

TRUE

NC_SATA_C_D2RP

MAKE_BASE=TRUE

NC_SATA_C_D2RP

TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CPNC_SATA_C_R2D_CP NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

NC_AUD_LO1_N_L

TRUE

MAKE_BASE=TRUE

NC_AUD_LO1_P_L

TRUE

MAKE_BASE=TRUE

NC_AUD_LO1_P_L

TRUE

MAKE_BASE=TRUE

NC_USB_10NNC_USB_10N

NC_ENET_INTR_L

TRUE

MAKE_BASE=TRUE

NC_LPC_DRQ0_LNC_LPC_DRQ0_L

NC_MEM_A_CKE<3..2>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK2N

NC_MEM_A_CLK3N

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK3N

NC_MEM_A_CLK4P

NC_MEM_A_CLK3P

TRUE

NC_MEM_A_CS_L<3>

MAKE_BASE=TRUE

NC_MEM_A_CS_L<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_ODT<3..2>TP_MEM_A_ODT<3..2>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CKE<2>NC_MEM_B_CKE<2>

TRUE

NC_MEM_B_CLK3P

MAKE_BASE=TRUE

NC_MEM_B_CLK3P

TRUE

NC_MEM_B_CLK4N

MAKE_BASE=TRUE

NC_MEM_B_CLK4N

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK4PNC_MEM_B_CLK4P

TRUE

NC_MEM_B_ODT<2>

MAKE_BASE=TRUE

NC_MEM_B_ODT<2>

TRUE

NC_MEM_B_CLK5N

MAKE_BASE=TRUE

NC_MEM_B_CLK5N

TRUE

MAKE_BASE=TRUE

NC_MLB_RAM_SIZENC_MLB_RAM_SIZE

TRUE

NC_P7_7

MAKE_BASE=TRUE

NC_P7_7

NC_PCI_AD<31..8>

MAKE_BASE=TRUE

TRUE

TP_PCI_AD<31..8>

NC_PCI_DEVSEL_L

WS_KBD22

TRUE

PP3V3_S0

TRUE

SATA_HDD_R2D_N

BKL_ISEN4

TRUE

LVDS_CONN_B_CLK_F_N

TRUE

LVDS_CONN_B_DATA_N<1>

TRUE

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_B_DATA_N<0>

TRUE

LVDS_CONN_A_DATA_N<2>

WS_KBD1

TRUE

WS_LEFT_OPTION_KBD

WS_KBD23

TRUE

LVDS_DDC_DATA

TRUE TRUE

LVDS_CONN_A_DATA_N<0>

TRUE

LVDS_CONN_A_DATA_P<0> LVDS_CONN_A_DATA_N<1>

TRUE TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_CONN_B_DATA_N<2>

TRUE

ADAPTER_SENSE

TP_MEM_A_CKE<3..2>

LVDS_DDC_CLK

TRUE

FAN_RT_TACH

FAN_LT_TACH

TRUE

FAN_LT_PWM

TRUE

WS_KBD13

TRUE

SMC_LID_R

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SDA

TRUE

WS_KBD5

TRUE

WS_KBD3

WS_KBD2

TRUE

WS_KBD8

TRUE

WS_KBD14

TRUE

GND

PP3V42_G3H

TRUE

PP3V3_S3

TRUE

WS_KBD9

TRUE

PPVCORE_S0_MCP_REG

TRUE

PP1V8R1V5_S0_FET

TRUE TRUE

PP1V8_S0

PP1V2R1V05_S5

TRUE

PPCPUVTT_S0

TRUE

PP0V9R0V75_S0_DDRVTT

TRUE

PPVCORE_S0_CPU

TRUE

WS_KBD11

TRUE

WS_KBD7

WS_KBD4

TRUE

WS_LEFT_SHIFT_KBD

TRUE

PP1V05_S0_MCP_PLL_UF PP5V_SW_ODD

TRUE

PP5V_S0_HDD_FLT

TRUE TRUE

BKL_VLDO

TRUE

PP5V_S3

TRUE

PP1V2R1V05_ENET

TRUE

PP3V3_ENET_PHY

TRUE

PPBUS_G3H

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V3_S3_LDO

PP4V5_AUDIO_ANALOG

TRUE TRUE

SMC_PM_G2_EN

TRUE

PM_SLP_S4_L

TRUE

PM_SLP_S3_L

TRUE

PP5V_S0

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

7

53 80 85

10 14 88

7

18

7

18

7

20

49

17 31 90

7

31 42 45 51 94

7

31 42 45 51 94

31

31 96

31 90 96

85

7

51

50

17 31

31 90 96

17 31 90

50

10 14 88

7

21

7

20

7

20

7

21

10 14 88

20 31 91

39 96

7

17

7

17

7

17

7

17

7

19

7

19

7

19

7

20

7

55

7

18

7

15

7

16

7

16

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

21 27 31 32 45 50 52 70

8 28 29 30 65 70

80 85

7

31 42 45 51 94

50 51

39

39 90

39 41

39 96

82 95

10 14 88

61 62

39 42

39 90

61

7

42 45 61 62 94

50

7

42 45 61 62 94

51

7

51

39

39 90

7

39

31 96

50

39 90

7

39 53

58 59 96

59 60

58 59 96

59 60

32

32 93

50 51

7

31 42 45 51 94

50 51

7

51

7

51

85

80 85

80 95

80 81 95

80 95

7

53 80 85

80

39 90

51

50

7 8

21

22 26

40 42

43

44

45 46 50 61 62 64 69

42 43 61

7

51

50

10 14 88

85

80 85

31 96

58 59 96

39 90

50

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

50

7

50

7

50

7

50

7

20

7

20

7

20

7

20

7

20

7

20

7

20

7

20

7

55

7

55

7

55

7

20

7

20

7

18

7

19

7

19

16

7

15

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

21

7

21

7

50

7

50

19

7

19

50

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

39 90

85

80 95

80 81 95

50

80 81

80 81 95

80 95

80 81 95

61

80 81

49

50

61

7

42 45 61 62 94

61

7

42 45 61 62 94

50

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 27 31 32 45 50 52 70

50

8

22 24 46 66

8

11 12 16 24 28 29 39 68 69 70

8

18 25 55 69 70 84 87

8

22 24 34 68

6 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

8

28 29 65 70

8

11 12 46 63

50

8

24 68

7

39 53

7

39

85

8 9

31 39 40 41 43 51 53 55 64

65 70 79

8

18 24 33 34 37

8

18 24 33 34

8

37 46 61 62 64 65 66 67 79 83

86

8

18 20 22 24 26 30 34 37 38 44

54 64 68 69 70 82 87 96

42 43

7

51

55

42 64 69

21 40 42 43 69 70

21 34 37 42 69 82 84

8

39 44

49 51 63

66 67 70

83 85

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"G3Hot" (Always-Present) Rails

241 mA max load

5V Rails

Chipset "VCore" Rails

4500 mA

"FW" (FireWire) Rails

190 mA

OR 0.75V

500 mA max supply

4771 mA

130 mA

1.8V/DDR 1.5V Rails

6600 MA

139 mA/ 0 mA

105 mA/241 mA

"GPU" Rails

500 mA

ENET Rails

1034 mA

1182 mA

3.3V-2.5V Rails

SYNC_MASTER=(MASTER)

Power Aliases

051-7892

A.0.0

97

8

SYNC_DATE=(MASTER)

PP1V1_S0GPU_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS_R

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPVCORE_GPU

MAKE_BASE=TRUE

PP1V8_GPUIFPX

MIN_NECK_WIDTH=0.2 mm

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0GPU_ISNS

VOLTAGE=1.05V

PP1V2R1V05_S5

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPVCORE_S0_CPU

PP5V_S0

PP5V_S0 PP5V_S0

PP5V_S0

VOLTAGE=5V

PP5V_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

PP3V3_S3

MIN_LINE_WIDTH=0.40MM

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

PPBUS_CPU_IMVP_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S5

PP1V8R1V5_S3 PP1V8R1V5_S3

MIN_LINE_WIDTH=0.8 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V8R1V5_S3

PP1V8R1V5_S0_FET

PPCPUVTT_S0

PP1V2R1V05_S5

PP3V3_S0

PP3V3_S3

PP5V_S3

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

PPBUS_CPU_IMVP_ISNS

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=16.5V

PPDCIN_G3H

PP3V42_G3H

PP5V_S3

PP5V_S3 PP5V_S3

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

PP1V1_S0GPU_REG

MAKE_BASE=TRUE

VOLTAGE=1.1V

PP1V1_S0GPU_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8R1V5_S0_FET

MAKE_BASE=TRUE

VOLTAGE=1.05V

PPCPUVTT_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0_MCP_SATA_AVDD

PP1V05_S0_MCP_PEX_AVDD PPCPUVTT_S0

PP1V1_S0GPU_REG

PP0V9R0V75_S0_DDRVTT

PP1V8R1V5_S0_FET

PP1V8R1V5_S3

PP3V3_S5

PP1V8R1V5_S0_FET

PPCPUVTT_S0

PP1V2R1V05_ENET

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_ENET_PHY

PPCPUVTT_S0

PPCPUVTT_S0 PPCPUVTT_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V

PP1V2R1V05_ENET

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PPCPUVTT_S0

PP5V_S3

PP3V3_FW_FWPHY

PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PEX_AVDD

PP3V3_S0

PP1V2_S0

PP1V2R1V05_ENET

PP3V3_ENET_PHY

PP1V2R1V05_ENET

PP3V3_ENET_PHY

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP1V2_S0

PP3V3_S0

PP1V2R1V05_ENET

PPBUS_G3H

PPDCIN_G3H

PP3V42_G3H

PP5V_S3

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8_S0GPU_ISNS_R

PP1V8_GPUIFPX

PP3V3_S0GPU

PPVTTDDR_S3

PP1V2R1V05_ENET

PPBUS_CPU_IMVP_ISNS

PP3V3_S5

PP1V8_S0

PP3V3_S0

PP1V05_S0_MCP_PLL_UF

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

PP5V_S3

PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS

PP1V8R1V5_S3

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

PP1V8_S0

PP1V8R1V5_S0_FET

PP1V1_S0GPU_REG

PP1V8_S0GPU_ISNS

PPVCORE_GPU

PPVP_FW

PP1V1_S0GPU_REG

PP3V3_S5

PP1V2R1V05_S5

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

PPVCORE_S0_MCP_REG

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V

PPVCORE_S0_CPU

PPVCORE_S0_MCP_REG

PP3V3_S0

PPBUS_G3H

PP5V_S3

PPDCIN_G3H

PP3V42_G3H

PPCPUVTT_S0

PP3V3_S0

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 mm

PP3V3_S5 PP3V3_S5

PPVP_FW

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPVP_FW

PP1V0_FW

PP3V3_FW_FWPHY

PP1V0_FW

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM VOLTAGE=1.8V

PP1V8_S0

PP3V3_S0

PPBUS_G3H

PP3V3_S5

PPBUS_G3H

PPVCORE_GPU

PP1V1_S0GPU_REG

PP3V3_S0GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM VOLTAGE=3.3V

PP3V3_S0GPU

PP3V3_S0

PP3V42_G3H

PP0V9R0V75_S0_DDRVTT

PP1V2R1V05_S5

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S5

PP3V42_G3H

PP5V_S3

PP3V3_S0

PPBUS_G3H

PP3V3_S0

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

PP1V2_S0

PP3V3_S0

PP3V3_S5

PP3V3_S0

PPCPUVTT_S0

PP1V8_S0

PP1V8R1V5_S3 PP1V8R1V5_S3

PP3V42_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.42V

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

PP5V_S3

MAKE_BASE=TRUE

VOLTAGE=0.9V

PP0V9R0V75_S0_DDRVTT

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=2 mm

PP0V9R0V75_S0_DDRVTT

PP3V3_S0

PP5V_S3

VOLTAGE=5.0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.17MM

PP3V3_S0GPU

PP3V3_S5

PP3V3_S3

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

PP3V3_S3

PP3V3_S5

PP1V8R1V5_S0_FET

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.17mm

MIN_LINE_WIDTH=0.6mm

PP3V3_S5

8

71 73 76 78 83

8

70 78

8

47 83

8

46 72 79

8

70 78

8 9

47 72 73 74 75

8 9

47 72 73 74 75

7 8

22 24 34 68

7 8

11 12 46 63

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85 7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51

63 66 67

70 83 85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

21 27 31 32 45 50 52 70

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

8

46 63

7 8

18 20 22

24 26 30 34 37 38 44 54 64 68

69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

28 29 30 65 70

7 8

28 29 30 65 70

7 8

28 29 30 65 70

7 8

11 12 16 24 28

29 39 68 69 70

7 8

11 12 16 24 28 29 39 68 69

70

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

7 8

22 24 34 68

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

21 27 31 32

45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31

32 45 50 52 70

7 8

21 27 31 32 45

50 52 70

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

37 46 61 62 64 65 66 67 79

83 86

8

46 63

8

61 62

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79 7 8 9

31 39 40 41 43 51 53 55

64 65 70 79 7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8

37 46 61

62 64 65 66 67 79 83 86

7 8

37 46 61 62 64 65 66 67 79

83 86

8

71 73 76 78 83

8

71 73 76 78 83

8

71 73 76 78 83

8

71 73 76 78 83

7 8

11 12 16 24 28 29 39 68 69

70

6 7 8 9

10 11 12

13 14 17 18 20 22 24 25 63 67

8

20 24

8

17 24

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

8

71 73 76 78 83

7 8

28 29 65 70

7 8

28 29 65 70

7 8

11 12 16 24 28 29 39 68 69

70

7 8

28 29 30 65 70

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

11 12 16 24 28

29 39 68 69 70

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

7 8

18 24 33 34 37

7 8

18 24 33 34

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67 6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

8

27 65

7 8

18 24 33 34 37

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

8

36 37 38

8

36 37 38

8

17 24

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18

19 21 22 24

25 28 29 37 39 43 45 47 48 49

51 55

59 60 63 68 69 70 77 80 81

82 84

85 96

8

84 87

7 8

18 24 33 34 37

7 8

18 24 33 34

7 8

18 24 33 34 37

7 8

18 24 33 34

7 8

18 24 33 34

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7

8

13 18 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77

80 81 82 84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7

8

13 18 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77

80 81 82 84

85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19

21 22 24 25 28 29 37 39 43 45

47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

8

84 87

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

18 24 33 34 37

7 8

37 46 61 62 64 65 66 67 79

83 86 7 8

37 46 61 62 64 65 66 67 79

83 86

8

61 62

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 7 8

13 18 19 21 22 24 25 28

29 37 39

43 45 47 48 49 51 55 59 60 63

68 69 70

77 80 81 82 84 85 96

8

47 83

8

47 83

8

70 78

6 8

69 70 76 77 79 81

8

27 65

7 8

18 24 33 34 37

8

46 63

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 25 55 69 70 84 87

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45

47 48 49 51 55 59 60 63 68 69

70 77

80 81 82 84 85 96

7 8

24 68

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

8 9

47 72 73 74 75

8 9

47 72 73 74 75

7 8

28 29 30 65 70

8

20 24

7 8

18 25 55 69 70 84 87

7 8

18 25 55 69 70 84 87

7 8

11 12 16 24 28 29 39 68

69 70

8

71 73 76 78 83

8 9

47 72 73 74 75

8 9

47 72 73 74 75

8

46 72 79

8 37 38

8

37 38

8

71 73 76 78 83

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

22 24 34 68

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

22 24 46 66

7 8

11

12 46 63

7 8

22 24 46 66

7 8

22

24 46 66

6 7 8

13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49

51 55 59 60 63 68 69 70 77 80

81

82 84 85 96

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8 9

31

39 40 41

43 51 53

55 64 65

70 79

8

61 62

7 8

21 22 26

40 42

43 44

45 46

50 61

62 64

69

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

11 12 46 63

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96 7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

8

37 38

8

37 38

8

36 37

8

36 37 38

8

36 37

8

36 37

7 8

18 25 55 69 70 84 87

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19

21 22 24 25 28 29 37 39 43 45

47 48 49 51 55 59 60 63 68 69

70 77 80 81 82 84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24

26

30 34 37 38 44 54 64 68 69 70

82 87 96

7 8

37 46 61 62 64 65 66 67 79

83 86

8

46 72 79

8

71 73 76 78 83

8

71 73 76 78 83

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

28 29 65 70

7 8

22 24 34 68

8

36 37 38

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 7

8

13 18 19 21 22 24 25 28 29

37

39 43 45 47 48 49 51 55 59 60

63

68 69 70 77 80 81

82

84

85 96

7 8

37 46 61 62 64 65 66 67 79

83 86

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

8

84 87

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87

96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

18 25 55 69 70 84 87

7 8

28 29 30 65 70

7 8

28

29 30 65 70

7 8

21 22 26 40

42 43 44 45 46 50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

37

46 61 62

64 65 66

67 79 83

86

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8

28 29 65 70

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

21 27 31 32

45

50 52 70

7 8

21 27 31 32 45 50 52 70

8

17 24

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

18 20 22 24

26

30 34 37 38 44 54 64 68 69 70

82 87 96

7 8

11 12 16 24 28 29 39 68 69

70

7 8

11 12 16 24 28 29 39 68 69

70

7 8

11 12 16 24 28 29 39 68 69

70

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TM Hole

MCP79 PCIe PRSNT# Straps

GPU signals

These need work. Add other PRSNT# straps if needed. .

CPU signals

TM Hole

Top GPU Right

TM Hole

Right CPU

Left CPU

ETHERNET ALIASES

Bosses

TOP MCP LEFT

TM Hole

Exist in MRB but not Intel designs. Here for CYA.

Frame Holes

Thermal Module Holes

If found to be necessary, will move to page14.csa

Extra FSB Pull-ups

Digital Ground

GMUX ALIASES

UNUSED EXPRESS CARD LANE

AUDIO ALIASES

3R2P5

1

ZT0940

1/16W

5%

402

MF-LF

47K

2

1

R0930

MF-LF

0

1/16W

5%

NO STUFF

402

21

R0925

17 37

SM

2 1

XW0901

1/16W MF-LF

10

1%

402

21

R0900

MF-LF

1/16W

1%

10

402

21

R0901

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0983

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0984

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0985

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0986

SL-3.1X2.7-6CIR-NSP

TH

1

ZT0950

3R2P5

1

ZT0960

3R2P5

1

ZT0990

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

1/16W

5%

MF-LF

0

402

21

R0926

17

84

NO STUFF

1/16W

5%

MF-LF

0

402

21

R0927

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0930

10 14 88

10 13 14 88

10 14 88

10 14 63 88

MF-LF

NO STUFF

1/16W

5%

402

62

2

1

R0960

220

NO STUFF

1/16W

5%

402

MF-LF

2

1

R0950

200

1/16W

5%

402

MF-LF

NO STUFF

2

1

R0970

402

150

NO STUFF

1/16W

1% MF-LF

2

1

R0980

150

1/16W

NO STUFF

MF-LF

402

1%

2

1

R0990

STDOFF-4.0OD3.0H-TH

1

ZT0934

STDOFF-4.0OD3.0H-TH

1

ZT0935

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0910

MF-LF

5%

1/16W

0

402

21

R0903

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0912

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0911

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0913

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0902

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0900

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0903

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0916

3R2P5

1

ZT0915

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0980

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0987

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0901

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0917

402

5%

22

1/16W MF-LF

2

1

R0931

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0914

4.0OD1.85H-M1.6X0.35

1

ZT0951

4.0OD1.5H-M1.6X0.35

1

ZT0952

4.0OD1.5H-M1.6X0.35

1

ZT0953

4.0OD1.85H-M1.6X0.35

1

ZT0954

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0904

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

051-7892

A.0.0

97

9

Signal Aliases

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

FW_PLUG_DET_L

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

NC_USB_EXTCN

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_MEM_B_A<15>

SMC_MCP_SAFE_MODE

USB_CARDREADER_N

NC_USB_EXCARDN

TP_MEM_B_A<15>

NC_USB_EXTCP

MAKE_BASE=TRUE

MCP_MII_PD MCP_MII_PD

GND

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

PM_SLP_RMGT_L

GND

PM_SLP_RMGT_L

TP_PCIE_CLK100M_EXCARD_P

TP_PCIE_EXCARD_D2R_N

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

FW_PLUG_DET_L

NC_USB_EXCARDP

NC_USB_EXTDP

NC_USB_MININ

USB_CARDREADER_P

NC_USB_EXTCN

TP_PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

TP_EXCARD_CLKREQ_L

MAKE_BASE=TRUE

TP_PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_N

DP_IG_HPD

GND

GPU_FB_B_VREF_DIV

DP_IG_ML_N<3>

MAKE_BASE=TRUE

PPCPUVTT_S0

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

GPU_FB_B_VREF_DIV

FSB_CPURST_L CPU_INTR CPU_NMI

CPU_DPRSTP_L

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<0..2>

FW643_WAKE_L

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_PRSNT_L

TP_PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_N

TP_EXCARD_CLKREQ_L

TP_PCIE_CLK100M_EXCARD_N

GND

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

NO_TEST=TRUE

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

PM_SLP_RMGT_L

PP5V_S3

PP5V_S3_AUDIO_AMP

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

RTL8211_CLK125

MAKE_BASE=TRUE

DP_IG_DDC_DATA

GND

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

GND

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

LCD_BKLT_EN

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

NC_USB_MINIP

NO_TEST=TRUE

USB_CARDREADER_P

MAKE_BASE=TRUE

NC_USB_MININ

NO_TEST=TRUE

GMUX_INT

MAKE_BASE=TRUE

NC_USB_EXTDP

NO_TEST=TRUE

TP_MEM_A_A<15>

JTAG_GMUX_TDI

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

NC_USB_EXTDN

NO_TEST=TRUE

NC_USB_EXTDN

MCP_MII_PD MCP_MII_PD

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

MCP_SPKR

MAKE_BASE=TRUE

GMUX_INT

GND

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

DP_IG_DDC_CLK

DP_IG_HPD

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

=MCP_HDMI_TXC_N

DP_IG_DDC_CLK

DP_IG_ML_P<2..0>

MAKE_BASE=TRUE

=MCP_HDMI_TXD_P<0..2>

TP_LVDS_MUX_SEL_EG

EG_RESET_L

MAKE_BASE=TRUE

EG_RESET_L

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

USB_CARDREADER_N

MAKE_BASE=TRUE

NC_USB_EXCARDP

NO_TEST=TRUE

NC_USB_MINIP

MAKE_BASE=TRUE

NC_USB_EXCARDN

NO_TEST=TRUE

=PEG_D2R_N<0..15> =PEG_R2D_C_P<0..15>

=PEG_D2R_P<0..15>

=PEG_R2D_C_N<0..15>

MEM_VTT_EN

TP_IMVP6_CLKEN_L

MAKE_BASE=TRUE

TP_IMVP6_CLKEN_L

CPU_VID<0..6>

MAKE_BASE=TRUE

CPU_BSEL<0..2>

MAKE_BASE=TRUE

MEM_VTT_EN

=MCP_BSEL<0..2>

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

DP_IG_ML_P<3>

MAKE_BASE=TRUE

IMVP6_VID<0..6>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXTCP

MAKE_BASE=TRUE

TP_MEM_A_A<15>

PM_ALL_GPU_PGOOD

EG_CLKREQ_OUT_L

PEG_PRSNT_L

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

MAKE_BASE=TRUE

JTAG_GMUX_TDO

JTAG_GMUX_TMS

MAKE_BASE=TRUE

JTAG_GMUX_TDI

TP_CPU_PECI_MCP

JTAG_GMUX_TDO

FW643_WAKE_L

MAKE_BASE=TRUE

GPU_FB_A_VREF_DIV

FSB_BREQ0_L

RTL8211_CLK125

MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS

JTAG_GMUX_TMS

DP_IG_DDC_DATA

NC_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_BKL_PWMNC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE

GND

NC_LVDS_IG_A_DATAP<3>

GND_CHASSIS_AUDIO_JACK

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.09MM

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

GND

9

19 37

71 90

9

14

9

20 91

9

29

42

9

20 32 96

9

20 91

9

29

9

20 91

9

18

9

18

9

33

9

21 34

9

21 34

9

17 90

9

17 90

9

17 90

9

19 37

9

20 91

9

20 91

9

20 91

9

20 32 96

9

20 91

9

17 90

9

17

9

17

9

17 90

9

18 81

9

27 75

81 90

6 7 8

10 11 12 13 14 17

18 20 22 24 25 63 67

9

18 90

9

27 75

9

18 90

9

18 90

18

9

36 37

9

17 90

9

17 90

9

17 90

9

17 90

9

17

9

17 90

9

17 90

9

17

9

17 90

9

33

9

33

9

21 34

7 8

31 39 40 41 43 51 53 55

64 65 70 79

58

9

33

9

18 77 81

9

27 74

71 90

9

84 86

9

18 84

9

20 91

9

20 32 96

9

20 91

9

18 84

9

20 91

9

28

6 9

19 84

9

18 84

9

20 91

9

20 91

9

18

9

18

9

18 84

9

18 84

21

9

18 84

9

69 83 84

9

18 77 81

9

18 81

9

84 86

18

9

18 77 81

81 90

18

9

84

9

71 84

9

71 84

9

84

9

20 32 96

9

20 91

9

20 91

9

20 91

17

9

26 65 70

9

63

9

63

11 88

10 88

9

26 65 70

14

71 90

81 90

63 88

9

20 91

9

28

9

69 83 84

81 90

6 9

17 84

6 9

19 84

6 9

19 84

9

14

6 9

17 84

9

36 37

9

27 74

8

47 72 73 74 75

6 9

19 84

9

18 77 81

9

18 90

9

18 90

9

18

9

18

9

18 90

9

18 90

9

18 90

9

18 90

59

9

18 90

9

18 90

9

18 90

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS

1/16W

1%

402

MF-LF

54.9

2

1

R1002

1/16W

5%

402

MF-LF

68

2

1

R1004

1/16W

1%

402

MF-LF

1K

2

1

R1005

1/16W

1%

402

MF-LF

2.0K

2

1

R1006

1/16W

1%

MF-LF

54.9

402

21

R1019

1/16W

1%

MF-LF

27.4

402

21

R1018

1/16W

1%

MF-LF

54.9

402

21

R1017

1/16W

1%

MF-LF

27.4

402

21

R1016

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

14 63 88

14 88

63

13 14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

88

9

88

9

88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

14 88

7

14 88

7

14 88

7

14 88

13 88

6

10 88

13 26

14 43 63 88

48 96

14 43 88

14 88

9

13 14 88

14 88

6

10 13 88

6

10 13 88

6

10 13 88

6

10 13 88

48 96

14 88

9

14 88

9

14 88

1/16W

5%

MF-LF

0

NOSTUFF

402

21

R1030

1/16W

5% MF-LF

1K

NOSTUFF

402

2

1

R1007

1/16W

1%

402

MF-LF

54.9

2

1

R1003

1/16W

1%

MF-LF

54.9

402

21

R1020

1/16W

1%

MF-LF

54.9

402

21

R1021

1/16W

1%

MF-LF

54.9

402

21

R1022

14 88

649

MF-LF

1/16W

1%

402

21

R1023

1/16W

5%

402

MF-LF

1K

NOSTUFF

2

1

R1012

16V

10% 402

X5R

0.1uF

NOSTUFF

2

1

C1000

1/16W

1%

MF-LF

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

402

21

R1024

FCBGA

PENRYN

OMIT

AB6

G2

AB5

C7

B25

A24

AB3

AA6

AC5

D5

A3

D3

D22

D2

F6

B2

V3

T2

N5

M4

G3

F4

F3

C1

L1

J3

K2

H2

K3

D21

AC1

AC2

H4

B4

C6

B3

C4

D20

E4

G6

A5

F21

H5

E1

C20

F1

G5

AC4

AD1

AD3

AD4

E2

A21

A22

V1

M1

H1

J1

N2

M3

K5

L4

L5

AA3

AB2

AA4

W3

V4

U2

J4

Y4

W5

W2

T3

T5

R4

U1

Y5

U4

A6

W6

R3

U5

Y2

R1

P1

P4

L2

P2

P5

N3

U1000

FCBGA

PENRYN

OMIT

C3

A26

AF1

AF26

C24

D25

C23

D7

D6

AE6

AD26

AF24

AA26

M26

H26

AE25

Y26

L26

J26

D24

B5

E5

AC20

U22

N24

H25

G24

K24

E23

AC23

AF22

AD23

AC22

E25

AD21

AE21

AC25

AF23

AE22

AD20

AC26

AB21

AB22

AA21

G25

AD24

AE24

AB25

AA24

AA23

W25

W24

Y23

W22

Y25

F23

U23

U25

T22

V23

V26

V24

AB24

Y22

N25

T25

G22

L25

R24

T24

P22

P23

P25

M23

L22

M24

L23

E26

R23

P26

K25

N22

H23

K22

F26

H22

J23

J24

F24

E22

Y1

AA1

U26

R26

C21

B23

B22

U1000

SYNC_DATE=11/12/2008

SYNC_MASTER=M98_MLB

97

051-7892

A.0.0

10

CPU FSB

FSB_A_L<14>

FSB_A_L<16>

FSB_A_L<18>

FSB_A_L<25>

PPCPUVTT_S0

TP_CPU_TEST6 TP_CPU_TEST7

CPU_TEST2

FSB_DSTB_L_P<1> FSB_DINV_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<25>

FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14>

FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<0>

FSB_D_L<32> FSB_D_L<1> FSB_D_L<2>

FSB_D_L<5>

FSB_D_L<16>

FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_DSTB_L_N<1>

CPU_GTLREF

TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

FSB_D_L<33>

FSB_D_L<34>

FSB_D_L<35>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<38>

FSB_D_L<39>

FSB_D_L<40>

FSB_D_L<41>

FSB_D_L<42>

FSB_D_L<43>

FSB_D_L<44>

FSB_D_L<45>

FSB_D_L<46>

FSB_D_L<47>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<2>

FSB_D_L<48>

FSB_D_L<49>

FSB_D_L<50>

FSB_D_L<51>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<54>

FSB_D_L<55>

FSB_D_L<56>

FSB_D_L<57>

FSB_D_L<58>

FSB_D_L<59>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<62>

FSB_D_L<63>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<3>

CPU_COMP<0>

CPU_COMP<1>

CPU_COMP<2>

CPU_COMP<3>

CPU_DPRSTP_L

CPU_DPSLP_L

FSB_DPWR_L

CPU_PWRGD

FSB_CPUSLP_L

CPU_PSI_L

FSB_D_L<17>

FSB_D_L<4>

FSB_D_L<3>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<10>

CPU_TEST1

FSB_REQ_L<1>

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L<6>

FSB_A_L<3> FSB_A_L<4>

FSB_REQ_L<0>

FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD4

TP_CPU_RSVD3

TP_CPU_RSVD2

TP_CPU_RSVD1

TP_CPU_RSVD0

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<17>

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26> FSB_A_L<27>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

CPU_THERMD_N

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8

PPCPUVTT_S0

XDP_TRST_L

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TCK

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

27 88 88

88

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6

10 13 88

6

10 13 88

6

10 13 88

6

10 88

6

10 13 88

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TBD A (Enhanced Deeper Sleep)

17.0 A (Design Target)

Ultra Low Voltage:

Standard Voltage:

44.0 A (Design Target)

27.4 A (Auto-Halt/Stop-Grant HFM)

TBD A (Deep Sleep SuperLFM)

TBD A (Deep Sleep HFM) TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

TBD A (Auto-Halt/Stop-Grant HFM) TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Deep Sleep HFM)

21.0 A (HFM)

TBD A (Sleep HFM)

9.4 A (Enhanced Deeper Sleep)

11.5 A (Deeper Sleep)

25.0 A (Deep Sleep HFM)

27.4 A (Sleep HFM)

25.5 A (SuperLFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)

TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deeper Sleep)

TBD A (Sleep SuperLFM)

TBD A (SuperLFM)

18.7 A (LFM)

23.0 A (Design Target)

Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

30.4 A (LFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

9

88

9

88

9

88

9

88

9

88

9

88

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

100

MF-LF 402

1% 1/16W

2

1

R1101

9

88

63 88

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

100

MF-LF 402

1% 1/16W

2

1

R1100

OMIT

PENRYN

FCBGA

AE7

AE2

AF3

AE3

AF4

AE5

AF5

AD6

AF7

N6

N21

M21

K21

J21

M6

K6

J6

W21

V21

T6

T21

R6

R21

V6

G21

C26

B26

AF20

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

B7

AE17

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

A20

AD12

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

A18

AC7

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

A17

AB9

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

A15

F20

F18

F17

F15

F14

F12

F10

F9

F7

E20

A13

E18

E17

E15

E13

E12

E10

E9

E7

D18

D17

A12

D15

D14

D12

D10

D9

C18

C17

C15

C13

C12

A10

C10

C9

B20

B18

B17

B15

B14

B12

B10

B9

A9

A7

U1000

OMIT

PENRYN

FCBGA

V25

V22

V5

V2

U24

U21

U6

U3

T26

T23

B8

T4

T1

R25

R22

R5

R2

P24

P21

P6

P3

B6

N26

N23

N4

N1

M25

M22

M5

M2

L24

L21

AF2

L6

L3

K26

K23

K4

K1

J25

J22

J5

J2

A23

H24

H21

H6

H3

G26

G23

G1

G4

F25

F22

A19

F2

F19

F16

F13

F11

F8

F5

E24

E21

E19

A16

E16

E14

E11

E8

E6

E3

D26

D23

D19

D16

A14

D13

D11

D8

D4

D1

C25

C22

C2

C19

C16

A11

C14

C11

C8

B1

AF25

A25

AF21

C5

AF19

AF16

AF13

AF11

AF8

AF6

A2

AE26

AE23

AE19

B24

AE16

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

B21

AD13

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

B19

AC11

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

B16

AB8

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

B13

AA5

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

B11

A8

A4

U1000

SYNC_DATE=11/12/2008

SYNC_MASTER=M98_MLB

CPU Power & Ground

051-7892

A.0.0

11 97

PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PP1V8R1V5_S0_FET

PPCPUVTT_S0

PPVCORE_S0_CPU

7 8

11 12 46 63

7 8

12 16 24 28 29 39 68 69

70

6 7 8 9

10 12 13 14 17 18 20 22

24 25 63 67

7 8

11 12 46 63

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1x 10uF, 1x 0.01uF

CPU VCORE HF AND BULK DECOUPLING

4x 330uF, 20x 22uF 0805

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1206

2.5V

20% D2T

POLY

470UF

CRITICAL

32

1

C1235

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1204

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1216

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1214

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1208

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1203

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1207

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1202

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1201

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1213

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1212

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1211

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1219

6.3V

20% 603

X5R-CERM

22UF

CRITICAL

2

1

C1200

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1210

10V

20%

402

CERM

0.1UF

2

1

C1236

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1205

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1209

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1215

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1217

10V

20%

402

CERM

0.1UF

2

1

C1237

10V

20%

402

CERM

0.1UF

2

1

C1238

10V

20%

402

CERM

0.1UF

2

1

C1239

10V

20%

402

CERM

0.1UF

2

1

C1240

10V

20%

402

CERM

0.1UF

2

1

C1241

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1218

16V

10%

402

CERM

0.01UF

PLACEMENT_NOTE=Place near CPU pin B26.

2

1

C1281

6.3V

20%

603

X5R

10uF

2

1

C1280

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1250

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1251

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1252

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1253

051-7892

SYNC_DATE=10/17/2007

A.0.0

12 97

SYNC_MASTER=M87_MLB

CPU Decoupling & VID

PPCPUVTT_S0

PPVCORE_S0_CPU

PP1V8R1V5_S0_FET

6 7 8 9

10 11 13 14 17 18 20

22 24 25 63 67

7 8

11 46 63

7 8

11 16 24 28 29 39 68 69

70

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TCK0

OBSDATA_A3

OBSDATA_A1

OBSFN_C0

OBSDATA_C0 OBSDATA_C1

OBSDATA_C3

Mini-XDP Connector

VCC_OBS_CD

DBR#/HOOK7

Please avoid any obstructions on even-numbered side of J1300

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

TDO

TDI

RESET#/HOOK6

OBSFN_D0

SCL

SDA

TRSTn

HOOK3

HOOK2

HOOK1

TMS

OBSDATA_D0

TCK1

OBSDATA_B2

PWRGD/HOOK0

OBSFN_D1

OBSDATA_B3

XDP_PRESENT#

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSFN_B0

OBSDATA_C2

OBSFN_C1

Direction of XDP module

998-1571

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSDATA_A2

OBSDATA_A0

OBSFN_A1

OBSFN_A0

Use with 920-0620 adapter board to support CPU, MCP debugging.

MCP79-specific pinout

10 14 88

1/16W

5%

402

MF-LF

1K

XDP

21

R1399

21 28 29 45 91

1/16W

1%

402

MF-LF

54.9

XDP

2

1

R1315

16V

10%

402

X5R

0.1uF

XDP

2

1

C1300

16V

10%

402

X5R

0.1uF

XDP

2

1

C1301

10 88

6

10 88

9

10 14 88

1/16W

5%

402

MF-LF

1K

XDP

PLACEMENT_NOTE=Place close to CPU to minimize stub.

21

R1303

10 88

6

21 76

6

21

6

21

19 91

6

21 76

6

14 88

6

10 88

6

10 88

6

10 88

10 26

19

F-ST-SM

LTH-030-01-G-D-NOPEGS

CRITICAL XDP_CONN

9

8 7

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1300

eXtended Debug Port(MiniXDP)

97

A.0.0

13

SYNC_MASTER=M98_MLB

051-7892

SYNC_DATE=11/12/2008

TP_XDP_OBSFN_B0

XDP_BPM_L<3>

PP3V3_S0 PPCPUVTT_S0

TP_XDP_OBSDATA_B2

MCP_DEBUG<2>

JTAG_MCP_TDI

MCP_DEBUG<4>

MCP_DEBUG<6> MCP_DEBUG<7>

XDP_CPURST_L XDP_DBRESET_L

MCP_DEBUG<0>

XDP_TCK

SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_OBS20

TP_XDP_OBSDATA_B3

XDP_PWRGD

TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1

TP_XDP_OBSFN_B1

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_BPM_L<5>

JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L

MCP_DEBUG<1>

MCP_DEBUG<3>

JTAG_MCP_TMS

MCP_DEBUG<5>

FSB_CLK_ITP_P FSB_CLK_ITP_N

XDP_TDI

XDP_TRST_L

XDP_TDO_CONN

XDP_TMS

CPU_PWRGD

FSB_CPURST_L

6 7 8

18 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96 6 7 8 9

10 11 12 14 17 18 20

22 24 25 63 67

88

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

IN

BI BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Loop-back clock for delay matching.

(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)

20 mA 29 mA 15 mA

206 mA270 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

9

10 88

9

10 13 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

9

10 88

7

10 88

7

10 88

7

10 88

13 88

10 88

9

10 88

9

10 88

10 13 88

10 88

9

10 63 88

9

10 43 63 88

10 43 88

10 88

49.9

1/16W

1%

402

MF-LF

2

1

R1436

1/16W

1%

402

MF-LF

49.9

2

1

R1431

49.9

MF-LF

402

1%

1/16W

2

1

R1430

49.9

1/16W

1%

402

MF-LF

2

1

R1435

NO STUFF

1K

402

5% 1/16W MF-LF

2

1

R1422

1K

NO STUFF

402

MF-LF

5%

1/16W

2

1

R1421

1K

5%

402

MF-LF

NO STUFF

1/16W

2

1

R1420

1/16W

402

MF-LF

62

5%

2

1

R1415

1/16W

402

MF-LF

54.9

1%

2

1

R1410

NO STUFF

150

1/16W 402

MF-LF

5%

2

1

R1440

OMIT

(1 OF 11)

MCP79-TOPO-B

BGA

AH27 AG28 AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42

AB41

AC41

H38

AC35

AC33

AC39

AA33

AC38

AH43

AJ41

E41

AG41

AC43

AF42

AH42

AH39

AD40

AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32

AN33

AN32

AA40

AD39

J41

N35

V35

V41

U41

P42

Y42

M43

H39

J40

K41

Y41

H42

H43

L41

H41

K42

H40

M40

N40

N41

P41

V42

M42

L42

J37

J38

J39

N38

N36

L38

L39

L37

Y39

R38

R37

R39

P35

R35

R34

N33

N34

U37

R33

W41

W38

U34

U33

U35

U36

U38

AA35

AA38

AA34

AA36

Y40

W34

W33

AA37

W35

T43

R41

T41

T42

T39

R42

W42

Y43

AM43 AM42

F42 D42 F41

AL32

AE40

AA41

AD43

AK35

AE36

AD42

AB35

AE35

AE37

AC37

AE34

AE38

AN35

AR39

AN34

AL35

AL38

AJ34

AC34

AN37

AL34

AL37

AJ38

AJ36

AJ37

AJ35

AN36

AJ33

AF41

AL33

AG33

AL39

AN38

AG34

AG38

AG37

AE33

AG39

AG35

AF35

AM39 AM40

AL41 AK42

AL43 AL42

G42 G41

AJ40

AK41

U1400

1/16W 402

MF-LF

62

5%

2

1

R1416

A.0.0

SYNC_DATE=12/12/2008

MCP CPU Interface

051-7892

9714

SYNC_MASTER=T18_MLB

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_BREQ0_L

FSB_BNR_L

FSB_CLK_MCP_N

FSB_BREQ1_L

FSB_REQ_L<4>

FSB_ADS_L

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<34>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32>

FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_DINV_L<3>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_DPWR_L

FSB_RS_L<1>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

FSB_TRDY_L

CPU_PROCHOT_L

=MCP_BSEL<0>

FSB_RS_L<2>

=MCP_BSEL<1>

FSB_CLK_MCP_P

CPU_PWRGD

FSB_DSTB_L_P<0>

FSB_DSTB_L_P<1>

FSB_DINV_L<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<0>

FSB_DINV_L<2>

FSB_DSTB_L_P<2> FSB_DSTB_L_N<2>

FSB_DSTB_L_P<3>

FSB_A_L<4>

FSB_DSTB_L_N<3>

FSB_A_L<3>

FSB_A_L<5>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<6> FSB_A_L<7>

FSB_A_L<12>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<11>

FSB_A_L<15> FSB_A_L<16>

FSB_A_L<19>

FSB_A_L<17> FSB_A_L<18>

FSB_A_L<20> FSB_A_L<21>

FSB_A_L<35>

FSB_A_L<33>

FSB_ADSTB_L<0>

FSB_REQ_L<0>

FSB_LOCK_L

FSB_HIT_L FSB_HITM_L

CPU_FERR_L

PM_THRMTRIP_L

TP_CPU_PECI_MCP

MCP_CPU_COMP_GND

FSB_D_L<0> FSB_D_L<1>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<4> FSB_D_L<5> FSB_D_L<6>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<9>

FSB_D_L<15>

FSB_D_L<17> FSB_D_L<18>

FSB_D_L<16>

FSB_D_L<19> FSB_D_L<20> FSB_D_L<21>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40> FSB_D_L<41>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47>

FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59>

FSB_D_L<63>

FSB_BPRI_L FSB_DEFER_L

FSB_CLK_ITP_P FSB_CLK_ITP_N

CPU_A20M_L

CPU_NMI

CPU_INTR

CPU_SMI_L

FSB_CPURST_L FSB_CPUSLP_L

CPU_DPSLP_L

CPU_STPCLK_L CPU_DPRSTP_L

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_ADSTB_L<1>

CPU_IGNNE_L CPU_INIT_L

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<0>

PP1V05_S0_MCP_PLL_FSB

FSB_A_L<10>

=MCP_BSEL<2>

FSB_DBSY_L FSB_DRDY_L

FSB_REQ_L<1>

PPCPUVTT_S0

88

24

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

OMIT

MCP79-TOPO-B

(2 OF 11)

BGA

AR17

AV17

AP15 AV15

AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39

AN5

AU5 AR10 AN13 AN27 AW29 AV35 AR34

AT37 AU37 AW39

AL8

AL9

AP9

AN9

AV39

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5 AN10

AR5

AR37

AU6

AV5

AU7

AU8

AW9 AP11

AW6

AY5

AU9

AV9

AR38

AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25

AV38

AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31

AW38

AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31

AR35 AP35

AT15 AR18

AW33 AV33

BA24 AY24

BB20 BC20

AU23 AT23

AP17

AP23 AP19 AW17

AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19

AR23 AU15 AN23 AW21 AN19

AT19 AR19

U1400

28 89

29 89

OMIT

(3 OF 11)

MCP79-TOPO-B

BGA

BA16

AW16

BB13 AY15

AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43

AT5 BA2

AY7 BA11 BB34 BB38 AY43 AR42

AW42 AW41 AT40

AT4

AT3

AV2

AV3

AT41

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

AP41

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

AN40

BA9 BB10 BB12 AW12

BB8

BB9 AY12 BA12 BC32 AW32

AU40

BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40

AU41

BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40

AR41 AP42

BB14 BB16

BA42 BB42

BB22 BA22

BA19 AY19

AY31 BB30

BA15

BB29 BB18 BB17

BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25

BA29 BA14 AW28 BC28 BA17

BB25 BA18

U1400

29 89

97

051-7892

A.0.0

15

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2008

MCP Memory Interface

MEM_B_DQ<23>

MEM_A_CKE<1> MEM_A_CKE<0>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

NC_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<8> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<13> MEM_A_A<12>

MEM_A_A<14>

MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DQ<0> MEM_A_DM<7>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12>

MEM_A_DQ<16>

MEM_A_DQ<21> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<17>

MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22>

MEM_A_DQ<26>

MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<35> MEM_A_DQ<34>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<33>

MEM_A_DQ<41>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<40> MEM_A_DQ<39>

MEM_A_DQ<42>

MEM_A_DQ<47> MEM_A_DQ<46>

MEM_A_DQ<43>

MEM_A_DQ<45> MEM_A_DQ<44>

MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<52>

MEM_A_DQ<48>

MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<61> MEM_A_DQ<60>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_ODT<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<60> MEM_B_DQ<59>

MEM_B_DQ<62>

MEM_B_DQ<58>

MEM_B_DQ<61>

MEM_B_DQ<57>

MEM_B_DQ<53>

MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<49>

MEM_B_DQ<51> MEM_B_DQ<50>

MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<42> MEM_B_DQ<41>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<36> MEM_B_DQ<35>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<31> MEM_B_DQ<30>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<22>

MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24>

MEM_B_DQ<17>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<18>

MEM_B_DQ<21>

MEM_B_DQ<16>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<11> MEM_B_DQ<10>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<3>

MEM_B_DQ<6>

MEM_B_DQ<2>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<1>

MEM_B_DM<6> MEM_B_DM<5>

MEM_B_DQ<0> MEM_B_DM<7>

MEM_B_DM<4> MEM_B_DM<3>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DQ<40>

MEM_B_DQS_P<7>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>

MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>

TP_MEM_B_CLK2P

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CS_L<1> MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_ODT<1> MEM_B_ODT<0>

MEM_B_CKE<0>

MEM_B_CKE<1>

7

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

4771 mA (A01, DDR3)

17 mA 12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA

TP or NC for DDR2.

39 mA

87 mA (A01)

1%

40.2

1/16W

402

MF-LF

2

1

R1610

MF-LF

402

1%

1/16W

40.2

2

1

R1611

OMIT

(4 OF 11)

MCP79-TOPO-B

BGA

BC29

AN16

AM29

AM27

AM25

AM31

AL30

BC25

AW24

AW19

AY26

AM23

AY25

AU18

AM15

AY18

AY17

AV20

BC17

AW27

AU22

AU20

AM21

AV24

AY29

AT21

AU24

AN18

AU16

AP18

AP22

AW15

AR24

AM19

AR20

AR16

AV16

AP24

AP20

AN22

AP16

AT17

AN24

AN20

AM17

T28

T27 U28 U27

AY32

BC13

AY16

AN15

AN17

AN41 AM41

BA13

BC16

AR15

AU17

BA41 BB41

AY23 BA23

BA20 AY20

AU33 AU34

BB24 BC24

BA21 BB21

BA31

BA30

AN25

AV23

W5

V34

V10

U22

U20

U18

T9

T7

T6

T38

T37

T35

T34

T33

T26

T24

AK11

T20

T18

T10

R5

R43

R40

R36

P7

P40

P4

P37

P34

P33

P10

N8

N39

M9

M7

M6

M5

M38

K7

H31

G32

G30

F24

D34

BC9

AY9

BC21

F28

AU10

AR36

AP30

AT25

AP12

AM28

AK7

AH35

AG24

AF24

AE20

AD22

AB7

AB22

AA39

AA22

U1400

30

MCP Memory Misc

16 97

A.0.0

051-7892

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

NC_MEM_B_CLK4N

NC_MEM_B_CLK4P

MCP_MEM_RESET_L

MCP_MEM_COMP_VDD MCP_MEM_COMP_GND

NC_MEM_A_ODT<2> NC_MEM_A_ODT<3>

NC_MEM_A_CKE<3>

NC_MEM_A_CKE<2>

NC_MEM_A_CLK3N

TP_MEM_A_CS_L<2> NC_MEM_A_CS_L<3>

TP_MEM_A_CLK5N NC_MEM_A_CLK4P

NC_MEM_A_CLK3P

TP_MEM_A_CLK4N

TP_MEM_A_CLK5P

PP1V05_S0_MCP_PLL_CORE

PP1V8R1V5_S0_FET

TP_MEM_B_CKE<3>

NC_MEM_B_CKE<2>

TP_MEM_B_ODT<3>

NC_MEM_B_ODT<2>

TP_MEM_B_CS_L<3>

TP_MEM_B_CS_L<2>

TP_MEM_B_CLK3N

NC_MEM_B_CLK3P

NC_MEM_B_CLK5N

TP_MEM_B_CLK5P

PP1V8R1V5_S0_FET

7

89

7

24

7 8

11 12 16 24 28 29 39 68 69

70

7

7 8

11 12 16 24 28 29 39 68

69 70

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Int PU (S5)

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU

84 mA (A01)

Int PU

57 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

OMIT

MCP79-TOPO-B

(5 OF 11)

BGA

K11

A11

M19

M17

M18

M16

L18

L16

B10

M15

C10

E8

D9

D5

F17

N14 M14

L14 K14

J13 H13

G13 F13

J11 J10

B6 C6

A7 B7

B8 A8

D8 C8

H7 G7

F9 E9

H9 G9

K9 J9

G11 F11

H3 H2

G3 H4

F3 F4

E2 F2

D2 E1

C1 D1

B3 B2

A4 A3

C4 B4

M2 M1

M4 M3

L4 L3

K2 K3

J2 J3

H1 J1

C5 D4

L11 L10

J5 J4

J7 J6

G5 H5

C3 D3

E4 E3

E5 F5

E6 F6

D7 C7

N5 N4

N7 N6

N9 P9

N11 N10

L7 L6

L9 L8

F7 E7

E11 D11

C9

T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

P13

N13

M13

U12

T12

N12

R12

P12

M12

AB12

AA12

W12

V12

AD12

AC12

Y12

U1400

9

71 90

9

7

31 90

7

31 90

9

37

7

31

36 90

9

90

9

90

31

9

31 90

36 90

9

90

9

90

31 90

9

90

9

90

9

2.37K

402

MF-LF

1% 1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

2

1

R1710

26 37

84

6 9

84

32

SYNC_MASTER=T18_MLB

MCP PCIe Interfaces

17 97

A.0.0

051-7892

SYNC_DATE=04/04/2008

PP1V05_S0_MCP_PEX_AVDD

=PEG_D2R_P<0>

=PEG_D2R_N<2>

PP1V05_S0_MCP_PLL_PEX

PPCPUVTT_S0

=PEG_D2R_N<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6>

PCIE_MINI_PRSNT_L

NC_PCIE_PE4_R2D_CN

TP_PCIE_PE4_R2D_CP

TP_PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_N

TP_PCIE_EXCARD_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P

TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P

NC_PCIE_CLK100M_PE5N

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE4N

NC_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PEG_CLK100M_N

PEG_CLK100M_P

PCIE_CLK100M_MINI_P

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14> =PEG_R2D_C_P<15>

=PEG_R2D_C_N<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<13>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<9> =PEG_R2D_C_P<10>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_N<4> =PEG_R2D_C_P<5>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<0>

MCP_PEX_CLK_COMP

NC_PCIE_PE4_D2RN

TP_PCIE_PE4_D2RP

TP_PCIE_EXCARD_D2R_N

PCIE_MINI_D2R_N

PCIE_FW_D2R_P

TP_PCIE_EXCARD_D2R_P

PCIE_FW_D2R_N

PCIE_WAKE_L

PCIE_MINI_D2R_P

PEG_PRSNT_L

=PEG_D2R_N<13> =PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_D2R_N<14>

=PEG_D2R_N<15>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<13>

=PEG_D2R_N<11>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_P<8>

=PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_N<8>

=PEG_D2R_N<9>

=PEG_D2R_N<5>

=PEG_D2R_P<7>

=PEG_D2R_N<6>

=PEG_D2R_N<7>

=PEG_D2R_P<3>

=PEG_D2R_P<5>

=PEG_D2R_N<3>

=PEG_D2R_N<4>

=PEG_D2R_P<1> =PEG_D2R_N<1>

PCIE_FW_PRSNT_L

FW_CLKREQ_L

TP_PCIE_CLK100M_EXCARD_P

TP_EXCARD_CLKREQ_L TP_PCIE_EXCARD_PRSNT_L

MINI_CLKREQ_L

TP_PE4_CLKREQ_L NC_PE4_PRSNT_L

AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L

CARDREADER_RESET JTAG_GMUX_TDO

8

17 24

8

17 24 24

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

7

90

7

60

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

IN OUT

IN IN IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable: Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1 0

MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_DDC_CLK

TP_DP_IG_AUX_CHP/N

TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0>

MCP Signal

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_DDC_DATA

TMDS_IG_HPD

=MCP_HDMI_HPD DP_IG_AUX_CH_P/N

8 mA 8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_IFPx at 1.8V

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_ML_P/N<0>

Interface Mode

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

level-shifters.

NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used): In MCP79 these pins have undocumented internal

24

33 92

34 92

33 92

25 90

9

84

9

84

9

81 90

9

84

9

81

25 90

49.9

402

MF-LF

1/16W

1%

2

1

R1810

1%

402

49.9

MF-LF

1/16W

2

1

R1811

77 81 82 84

25

9

18

9

18

9

18

OMIT

MCP79-TOPO-B

(6 OF 11)

BGA

D38

C38

C37

A35

E36

A36

D36

B36 C36

D25

C25

C24

B24

C26

D24

A24

E24

B23

C23

C22

A23

G23

C21

D21

J22

A41

B38

C39

B39

A40

A39 B40

M26

M27

T25

K32

J32

M28 M29

V23

U23

T23

K24

J24

E28

F23

J23

B22

C27 B27

B26

F40

E37

G39

N30 M30

L30 K30

L29 K29

J29 H29

L31 K31

G31

E32

B34 C34

D33 C33

D32 C32

B32 A32

B35 C35

F31

C31

J30

J33 H33

F33 G33

G35 F35

D35 E35

J31

B15

E16

D43 C43

E31

B30

A31

D31

C30

B31

E23

U1400

MF-LF

5% 1/16W

402

10K

2

1

R1850

MF-LF

1/16W

100K

5%

402

2

1

R1861

100K

1/16W

5%

MF-LF

402

2

1

R1860

44

1/16W MF-LF

402

47K

5%

2

1

R1820

33 92

84 90

33 92

84 90

9

90

9

90

9

90

9

90

84 90

33 92

84 90

9

90

9

90

81

9

77 81

9

77 81

25 90

33 92

25 90

33 92

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2008

051-7892

A.0.0

9718

DP_CA_DET

PP1V05_ENET_MCP_PLL_MAC

PPCPUVTT_S0

PP3V3_S0_MCP_VPLL

PP1V8_S0

PP3V3_S0_MCP_DAC

PP1V2R1V05_ENET

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

NC_LVDS_IG_BKL_PWM

NC_MCP_CLK27M_XTALOUT

LPCPLUS_GPIO

=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2>

GMUX_INT

LVDS_IG_A_CLK_N

NC_MCP_CLK27M_XTALIN

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

NC_MCP_RGB_DAC_RSET NC_MCP_RGB_DAC_VREF

NC_MCP_TV_DAC_VREF

DP_IG_AUX_CH_P DP_IG_AUX_CH_N

DP_IG_HPD

MCP_HDMI_RSET MCP_HDMI_VPROBE

ENET_MDIO

MCP_CLK25M_BUF0_R

MCP_DDC_DATA0

MCP_DDC_CLK0

NC_MCP_RGB_RED NC_MCP_RGB_GREEN NC_MCP_RGB_BLUE

NC_MCP_RGB_HSYNC NC_MCP_RGB_VSYNC

NC_CRT_IG_R_C_PR NC_CRT_IG_G_Y_Y

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1>

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA_N<2>

NC_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKN

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2> NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAN<3>

DP_IG_DDC_DATA

DP_IG_DDC_CLK

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

NC_MCP_TV_DAC_RSET

ENET_RXD<0>

NC_ENET_INTR_L

ENET_RXD<3>

ENET_RX_CTRL

ENET_CLK125M_RXCLK

ENET_RXD<2>

ENET_RXD<1>

ENET_RESET_L

ENET_MDC

NC_ENET_PWRDWN_L

MCP_MII_PD MCP_MII_PD MCP_MII_PD

NC_CRT_IG_B_COMP_PB NC_CRT_IG_HSYNC

NC_CRT_IG_VSYNC

MCP_MII_VREF

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

PP3V3_ENET_PHY

NC_LVDS_IG_A_DATAN<3>

PP3V3_S0

PP3V3_ENET_PHY

PP3V3_S5

24

6 7 8 9

10 11 12 13 14 17 20

22 24 25 63 67

25

7 8

25 55 69 70 84 87

25

7 8

24 33 34 37

92

25

7

7 8

18 24 33 34

6 7 8

13 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

7 8

18 24 33 34

7 8

20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

OUT

BI BI BI BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

42 44 84 91

26 84 91

42 44 84 91

OMIT

(7 OF 11)

MCP79-TOPO-B

BGA

Y3

Y2

AA7

R11

R10

T4

U9

T3

V9

T2

T1

AB9

Y1

AA10

N1

N2

N3

P2

P3

U11

R4

U10

R3

Y4

AA9

AD11

R9

R8

R7

R6

W10

AA11

AA6

AA3

AA2

AC8

AC7

AB2

AC6

AB3

U7

T5

AE11

U6

U1

U5

U2

W11

U3

W9

V2

W8

V3

AC4

W7

W4

W6

W3

Y5

AA5

AA1

AC11

AC10

AC9

AE10

AC3

AE6

AE5

AE12

AD4

AE2 AE1

AE9

AD5

AD1

AD2

AD3

Y27

Y26

Y25

Y24

Y22

Y20

Y19

Y18

Y17

Y16

W43

W40

W36

W24

W22

W20

V7

V40

V4

V37

V33

V28

V27

V26

V24

V22

V20

V18

V17

V16

U8

U4

U39

U26

U24

AD34

AD33

AD28

AD27

AD26

AD25

AD24

AD20

AD19

AD18

AD17

AD16

AC5

AB33

AC40

AC36

AC22

AB40

AB4

AB37

AB34

AB28

AB27

AB26

AB25

AB24

AB23

AB21

AB20

H34

AB18

U1400

42 44

42 44 26 91

42 44

PLACEMENT_NOTE=Place close to pin R8

MF-LF 402

1/16W

5%

22

2

1

R1910

402

MF-LF1/16W

5%

8.2K

21

R1989

402

MF-LF1/16W

5%

8.2K

21

R1991

402

MF-LF1/16W

5%

8.2K

21

R1990

402

MF-LF1/16W

5%

8.2K

21

R1994

8.2K

5%

1/16W MF-LF

402

21

R1992

19

MF-LF 402

1/16W

5%

10K

2

1

R1961

1/16W MF-LF

402

22

5%

21

R1960

5%

1/16W MF-LF22402

21

R1950

5%

1/16W MF-LF22402

21

R1951

22

5%

1/16W MF-LF

402

21

R1952

402

MF-LF1/16W

5%

22

21

R1953

26

9

37

19

19 37

13

13 91

60

6 9

84

6 9

84

051-7892

A.0.0

9719

MCP PCI & LPC

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

NC_PCI_AD<27>

NC_PCI_AD<29>

NC_PCI_AD<28>

NC_PCI_AD<10>

NC_PCI_INTW_L NC_PCI_INTX_L TP_PCI_INTY_L NC_PCI_INTZ_L

FW_PLUG_DET_L

LPC_PWRDWN_L

NC_PCI_TRDY_L

NC_LPC_DRQ0_L LPC_SERIRQ

MCP_DEBUG<4>

MCP_DEBUG<0>

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<5> MCP_DEBUG<6>

NC_PCI_AD<9>

NC_PCI_AD<8>

MCP_DEBUG<7>

NC_PCI_AD<11>

NC_PCI_AD<14>

NC_PCI_AD<13>

NC_PCI_AD<12>

NC_PCI_AD<15> NC_PCI_AD<16> NC_PCI_AD<17>

NC_PCI_AD<20>

NC_PCI_AD<19>

NC_PCI_AD<18>

NC_PCI_AD<21> NC_PCI_AD<22>

NC_PCI_AD<25>

NC_PCI_AD<23>

NC_PCI_AD<26>

NC_PCI_AD<31>

NC_PCI_GNT0_L

NC_PCI_C_BE_L<2>

NC_PCI_C_BE_L<0>

NC_PCI_C_BE_L<3>

NC_PCI_IRDY_L

NC_PCI_FRAME_L

NC_PCI_DEVSEL_L

TP_PCI_PAR

NC_PCI_SERR_L NC_PCI_STOP_L

MEM_VTT_EN_R NC_PCI_RESET1_L

PCI_CLK33M_MCP_R

NC_PCI_CLK1

NC_PCI_CLK0

PCI_CLK33M_MCP

LPC_FRAME_R_L

LPC_AD_R<1>

LPC_AD_R<0>

LPC_RESET_L

LPC_CLK33M_SMC_R

LPC_AD_R<3>

LPC_AD_R<2>

NC_PCI_AD<30>

NC_PCI_AD<24>

PM_CLKRUN_L

JTAG_GMUX_TMS JTAG_GMUX_TDI MCP_RS232_SOUT_L

NC_PCI_GNT1_L

NC_PCI_C_BE_L<1>

NC_PCI_PERR_L

AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L

PM_LATRIGGER_L

FW_PWR_EN

PCI_REQ0_L PCI_REQ1_L

FW_PWR_EN

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

MCP_RS232_SIN_L

PP3V3_S0

7

91

7

91

7

19 91

19 37

19 91

19

6 7 8

13 18 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

BI BI

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT OUT

IN

OUT OUT

IN IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ExpressCard

SD Card Reader

External C

Minimum 1.025V for Gen2 support

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

84 mA (A01)

Minimum 1.025V for Gen2 support

19 mA (A01)

External B

IR

Bluetooth

Camera

External A

External D

AirPort (PCIe Mini-Card)

Geyser Trackpad/Keyboard

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

127 mA (A01, AVDD0 & 1)

43 mA (A01, DVDD0 & 1)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

40 91

9

91

9

91

9

91

9

91

7

31 91

7

31 91

41 91

50 91

7

31 91

7

31 91

40 91

9

91

9

91

9

91

9

91

MF-LF

1% 1/16W

402

2.49K

2

1

R2010

806

MF-LF

1%

1/16W

402

2

1

R2060

5%

8.2K

MF-LF

1/16W 402

2

1

R2053

1/16W MF-LF

402

5%

8.2K

2

1

R2052

5%

8.2K

1/16W 402

MF-LF

2

1

R2051

8.2K

402

MF-LF

1/16W

5%

2

1

R2050

OMIT

MCP79-TOPO-B

(8 OF 11)

BGA

A27

H21

J21

K21

L21

H25 J25

K25 L25

D27 E27

F27 G27

J26 J27

K27 L27

F29 G29

A28 B28

C28 D28

K23 L23

F25 G25

C29 D29

AE3

E12

AP3 AP2

AN2

AN3

AN1 AM1

AM3

AM2

AM4 AL3

AK3

AL4

AK2 AJ3

AJ1

AJ2

AJ11 AJ10

AK9

AJ9

AJ7 AJ6

AJ4

AJ5

L28

AE16

AH19

AH17

AG19

AG17

AG16

AF19

AM14

AM13

AL14

AN14

AL13

AN12

AM12

AM11

AL12

AK13

AK12

AN11

AJ12

AH24

AH22

AH20

AH18

AG40

AG36

AG26

AG22

AG20

AG18

AF40

AF37

AF34

AF33

AF28

AF27

AF26

AF22

AF20

AF18

AF17

AF16

AD6

AE4

AE39

AE24

AE22

AD38

AD37

AD35

U1400

39 90

9

32 96

9

32 96

SYNC_MASTER=T18_MLB

MCP SATA & USB

051-7892

A.0.0

9720

SYNC_DATE=12/12/2008

TP_SATA_C_D2RN

SATA_HDD_D2R_P

SATA_ODD_R2D_C_P

MCP_USB_RBIAS_GND

USB_CARDREADER_N

USB_CARDREADER_P

NC_USB_10N

NC_USB_10P

NC_USB_EXTCN

NC_USB_EXTCP

USB_EXTB_N

NC_USB_EXCARDN

NC_USB_EXCARDP

USB_EXTB_P

USB_BT_N

USB_BT_P

USB_TPAD_N

USB_IR_N

USB_IR_P

USB_TPAD_P

NC_USB_EXTDN

NC_USB_EXTDP

USB_EXTA_N

NC_USB_MININ

NC_USB_MINIP

USB_EXTA_P

MCP_SATA_TERMP

TP_MCP_SATALED_L

TP_SATA_F_D2RN TP_SATA_F_D2RP

TP_SATA_E_R2D_CP

NC_SATA_D_D2RN NC_SATA_D_D2RP

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

NC_SATA_C_R2D_CN

NC_SATA_C_D2RP

NC_SATA_C_R2D_CP

SATA_ODD_D2R_N SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_HDD_R2D_C_P

USB_CAMERA_P USB_CAMERA_N

USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

TP_SATA_F_R2D_CN

TP_SATA_F_R2D_CP

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

PP3V3_S0_MCP_PLL_USB

PP1V05_S0_MCP_PLL_SATA

PPCPUVTT_S0

GND

PP1V05_S0_MCP_SATA_AVDD

GND

PP3V3_S5

91

7

90

7

40

43

24

6 7 8 9

10 11 12 13 14 17 18

22 24 25 63 67

8

24

7 8

18 22 24 26 30 34 37 38 44

54 64 68 69 70 82 87 96

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID* LLB*

PWRBTN* RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

automatic recovery.

Connects to SMC for

USER mode: Normal

recovery

SAFE mode: For ROMSIP

(MXM_OK for MXM systems)

Int PU (S5)

Int PU

SPI1 option. Rev B01 will.

NOTE: MCP79 rev A01 does not support

Int PU (S5)

Int PD

Int PU

1

0 1 0

LPC_FRAME# 0 0 1 1

default, LPC+ debug card pulls

R1961 and R2160 selects SPI0 ROM by

BIOS Boot Select

HDA_SDOUTI/F

SPI1

SPI0

LPC

NOTE: MCP79 does not support FWH, only

Frequency

SPI Frequency Select

1 MHz

NOTE: Straps not provided on this page.

31 MHz

Frequency

BUF_SIO_CLK Frequency

14.31818 MHz

1

0

SPI_DO

SPI_CLK

0 1

1

0

24 MHz

HDA_SYNC

1 0

LPC ROMs. So Apple designs will

0

42 MHz 25 MHz

Int PU Int PU Int PU (S5)

Int PU

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

LPC_FRAME# high for SPI1 ROM override.

not use LPC for BootROM override.

PCI

For EMI Reduction on HDA interface

HDA Output Caps

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

7 mA (A01)

37 mA (A01)

20 mA 17 mA

Int PU (S5) Int PU (S5)

(MGPIO3)

(MGPIO2)

44 91

7

34 37 42 69 82 84

7

40 42 43 69 70

13 28 29 45 91

45 60 85 91

13 28 29 45 91

45 60 85 91

21 66

48 96

21 66

21 31 34

48 96

9

34

63 88

42

55 91

MF-LF

1/16W

1%

402

49.9K

2

1

R2121

1%

49.9K

MF-LF

402

1/16W

2

1

R2120

1K

MF-LF

1% 1/16W

402

2

1

R2190

26 91

42

MF-LF

402

5%

22

1/16W

21

R2170

MF-LF

5%

1/16W

402

22

21

R2171

5%

22

MF-LF

1/16W

402

21

R2173

402

5%

10K

MF-LF

1/16W

2

1

R2163

MF-LF

8.2K

5% 1/16W

402

2

1

R2160

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

2

1

R2180

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

2

1

R2181

402

5%

22

1/16W MF-LF

21

R2172

44

49.9

MF-LF

1/16W

1%

402

2

1

R2110

402

1/16W MF-LF

5%

10K

2

1

R2150

6

13

6

13

6

13 76

6

13 76

6

10PF

50V

5%

402

CERM

2

1

C2171

50V

10PF

5%

402

CERM

2

1

C2173

50V

10PF

5%

402

CERM

2

1

C2170

50V

10PF

5%

402

CERM

2

1

C2172

OMIT

(9 OF 11)

MCP79-TOPO-B

BGA

B19

B16

A19

A16

B11 C11

K22

B18

C13

B14

C15

C14 D13

F21

K19 G21

L19

M23

H17

G17 J17

C19

C20

D16

D20

C16

E20

L22

AE17

AE18

K16

J16

M21

M20

L20

M24

M25

L13

J18

J19

F19

E19

G19

B20

L15

F15

J15

J14

G15

K15

A15

L17

K17

E15

L24

L26

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

39

21 60

26 26

34 37 42 43

21 28 29 42

402

1/16W MF-LF

5%

100K

2

1

R2147

10K

5% 1/16W

402

MF-LF

2

1

R2142

402

1/16W MF-LF

5%

10K

2

1

R2141

22K

5% MF-LF

1/16W 402

2

1

R2157

22K

5% MF-LF

1/16W 402

2

1

R2156

402

1/16W

22K

5% MF-LF

2

1

R2155

402

MF-LF

5% 1/16W

100K

2

1

R2151

1/16W MF-LF

5%

100K

402

1

2

R2154

MF-LF 402

1/16W

5%

10K

2

1

R2143

10K

5% MF-LF

1/16W 402

2

1

R2140

9

21 42 43

26

42

26

44 91

MCP HDA & MISC

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

21 97

A.0.0

051-7892

MCP_GPIO_4 AUD_I2C_INT_L

MCP_VID<0>

TP_MLB_RAM_VENDOR

PM_SLP_S3_L PM_SLP_RMGT_L

HDA_BIT_CLK_R

HDA_SDOUT_R

MCP_THMDIODE_N

MCP_THMDIODE_P

HDA_RST_R_L

MCP_HDA_PULLDN_COMP

NC_MLB_RAM_SIZE

MCP_VID<2>

MCP_VID<1>

SMC_RUNTIME_SCI_L

ARB_DETECT

SMC_IG_THROTTLE_L

ODD_PWR_EN_L

MEM_EVENT_L

SMC_WAKE_SCI_L

TP_MCP_KBDRSTIN_L

MCP_TEST_MODE_EN

TP_MCP_BUF_SIO_CLK

MCP_CPUVDD_EN

SMBUS_MCP_0_DATA

SMBUS_MCP_0_CLK

MCP_SPKR

HDA_SYNC_R

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

JTAG_MCP_TRST_L

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

JTAG_MCP_TMS

MCP_CPU_VLD

JTAG_MCP_TDI JTAG_MCP_TDO

RTC_RST_L

MCP_PS_PWRGD

PM_RSMRST_L

SM_INTRUDER_L

TP_MCP_LID_L PM_BATLOW_L

PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L

PM_DPRSLPVR

PM_SLP_S4_L

HDA_SDIN0

SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN

SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R

PM_CLK32K_SUSCLK_R

PP3V3_S0

SPIROM_USE_MLB

NC_SB_A20GATE

SMC_ADAPTER_EN

PP1V05_S0_MCP_PLL_NV

ARB_DETECT

SMC_IG_THROTTLE_L

AP_PWR_EN

PP3V3_S3

AUD_I2C_INT_L

MCP_GPIO_4

MCP_VID<0>

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V42_G3H

PP3V3_S0

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

MCP_VID<2>

MCP_VID<1>

HDA_SYNC

PP3V3_S0

MEM_EVENT_L

PP3V3_S0

21

21 91

91

7

21

21 91

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43

45 47 48 49 51 55 59 60 63 68

69 70 77 80

81 82 84 85 96

7

24

21

21 42 43

21 31 34

7 8

27 31 32 45 50 52 70

21 60

21

21 66

7 8

22 26 40 42 43 44 45 46

50 61 62 64 69

6 7 8

13 18 19 21 22 24 25

28 29 37 39 43 45 47 48 49

51 55 59 60 63 68 69 70 77

80 81 82 84 85 96

21 91

21 66

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

21 28 29 42

6 7 8

13 18 19 21 22 24 25

28 29 37 39 43 45 47 48 49

51 55 59 60 63 68 69 70 77

80 81 82 84 85 96

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1182 mA (A01)

450 mA (A01)

16 mA

10 uA (G3)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

80 uA (S0)

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

250 mA

1139 mA

43 mA

105 mA (A01)

266 mA (A01)

OMIT

(11 OF 11)

MCP79-TOPO-B

BGA

T22

AH16

Y11

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AD7

AN26

AB16

AB17

Y38

Y37

Y35

Y34

Y33

Y28

M37

M35

M34

M10

L5

L43

L40

AU1

K8

K40

K4

K37

K26

K18

K12

K10

J8

J12

G40

AN8

H23

AW35

H15

H11

G8

G6

G43

G4

G34

AW20

G24

G22

BC12

G16

G14

G12

G10

F8

F32

F16

F12

E33

E29

E25

E21

E17

E13

D6

D37

D30

D26

D23

D22

D19

D18

D15

D14

D10

C2

BC5

AY14

BC41

BC37

BC33

L35

AY6

AW31

BA4

BA1

AV40

AY41

AY38

AY37

AY34

AY33

AY30

AV12

AY10

AW43

AR43

G20

AW11

AV7

AV4

AV36

AV32

AV28

F20

G28

AU4

AU38

AU36

AR30

AU32

AP33

AU28

AU12

L12

AY22

AY21

AT9

AT7

AT6

AT33

AT29

AT13

AR12

AT10

AR40

AR32

AR28

AW23

AP7

AP40

AP4

AP37

AP36

AP34

AP32

AP28

AU14

AP14

AU26

AP10

Y7

AN4

AN39

AN30

AN28

AP26

AM9

AM7

AM6

AM5

AM38

AM37

AM35

AM34

AM30

AM26

AM24

AM22

AM20

AM18

AM16

AM10

AL5

AL40

AL36

AK40

AK4

AK37

AK34

AK33

AK10

AJ8

AJ39

AH38

AH37

AH34

AH33

AH26

U1400

OMIT

(10 OF 11)

BGA

MCP79-TOPO-B

AG32

W32

V32

U32

T32

AA32

Y32

P32

N32

N31

M33

M32

M31

L34

L33

L32

K35

K34

K33

J36

J35

J34

H37

H35

G38

G37

G36

F39

F38

F37

E40

E39

E38

D41

D40

D39

C42

C41

C40

B42

B41

AC32

AB32

AL31

AD32

AK32

AK31

AJ32

AH32

AE32

AF32

P31

R32

AA16

AF12

W25

Y23

W23

W21

AA24

AH9

AH7

AH6

AH5

AH4

AH3

AH21

Y21

AH25

W28

AA23

AH2

W26

AH11

AH10

AH1

AG9

AG8

AG5

AG7

AG6

AA21

AG4

AG3

AG25

AG23

AG21

AG12

AG11

AG10

AA20

AF9

AH23

AF7

AF4

AF3

AF25

AF23

AF21

AF2

AH12

AA19

AF11

AF10

AE28

AE27

AE26

AE25

AE23

AE21

AE19

U25

AA18

V25

W27

AD23

AD21

AC28

AC27

AC26

AC25

AC24

AC23

AA17

AC21

AC20

AC19

AC18

AC17

AC16

AA28

AA27

AA26

AA25

V21

U21

T21

A20

K28

J28

H27

G26

K20

J20

H19

G18

Y9

AA8

AB11

Y10

AD9

AB10

AE8

AD10

U1400

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

051-7892

A.0.0

9722

MCP Power & Ground

PPCPUVTT_S0

PPVCORE_S0_MCP_REG

PP3V3_S5

PP3V42_G3H

PP3V3_S0

PP1V2R1V05_S5

6 7 8 9

10 11 12 13 14 17 18 20

24 25 63 67

7 8

24 46 66

7 8

18 20 24 26 30 34 37 38 44

54 64 68 69

70 82 87 96

7 8

21 26 40 42 43 44 45 46

50 61 62 64 69

6 7 8

13 18 19 21 24 25 28 29

37 39 43 45

47 48 49 51 55 59 60 63 68 69

70 77 80 81

82 84 85 96

7 8

24 34 68

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

23 97

A.0.0

051-7892

MCP79 A01 Silicon Support

SYNC_MASTER=T18_MLB

SYNC_DATE=03/31/2008

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

(No IG vs. EG data)

MCP SATA (DVDD) Power

43 mA (A01)

270 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

19 mA (A01)

450 mA (A01)

57 mA (A01)

127 mA (A01)

206 mA (A01)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

105 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

MCP 3.3V Ethernet Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP 1.05V AUX Power

Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 5x 2.2uF 0402 (11 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

4771 mA (A01, DDR3)

333 mA (A01)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

5 mA (A01)

562 mA (A01)

Apple: 7x 2.2uF 0402 (15.4 uF)

131 mA (A01)

MCP 1.05V RMGT Power

MCP PCIE (DVDD) Power

MCP Core Power

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

4.7UF

X5R 402

20%

4V

2

1

C2582

4.7UF

X5R 402

20%

4V

2

1

C2588

4.7UF

X5R 402

20%

4V

2

1

C2584

4.7UF

X5R 402

20%

4V

2

1

C2586

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2555

4.7UF

X5R 402

20%

4V

2

1

C2502

1UF

X5R 402-1

10% 10V

2

1

C2507

1UF

X5R

10% 10V

402-1

2

1

C2506

1UF

402-1

10V

10% X5R

2

1

C2505

1UF

X5R 402-1

10% 10V

2

1

C2504

CERM 402

20% 10V

0.1UF

2

1

C2511

0.1UF

CERM 402

20% 10V

2

1

C2510

0.1UF

CERM 402

20% 10V

2

1

C2509

0.1UF

CERM 402

20% 10V

2

1

C2508

0.1UF

CERM 402

20% 10V

2

1

C2513

0.1UF

CERM

20% 10V

402

2

1

C2512

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2536

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2535

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2534

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2533

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2532

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2531

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2530

1UF

X5R 402-1

10% 10V

2

1

C2517

1UF

X5R 402-1

10% 10V

2

1

C2516

4.7UF

X5R 402

20%

4V

2

1

C2515

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2572

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2571

4.7UF

X5R 402

20%

4V

2

1

C2520

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2570

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2574

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2573

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2576

CERM

20%

6.3V 402-LF

2.2UF

2

1

C2575

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2553

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2552

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2551

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2550

0.1UF

CERM 402

20% 10V

2

1

C2549

0.1UF

CERM 402

20% 10V

2

1

C2548

0.1UF

CERM 402

20% 10V

2

1

C2547

0.1UF

CERM 402

20% 10V

2

1

C2546

0.1UF

CERM 402

20% 10V

2

1

C2545

0.1UF

CERM 402

20% 10V

2

1

C2544

0.1UF

CERM 402

20% 10V

2

1

C2543

0.1UF

CERM 402

20% 10V

2

1

C2542

0.1UF

CERM 402

20% 10V

2

1

C2541

4.7UF

X5R 402

20%

4V

2

1

C2540

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2562

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2564

4.7UF

X5R 402

20%

4V

2

1

C2580

30-OHM-5A

0603

21

L2570

30-OHM-5A

0603

21

L2575

0402

30-OHM-1.7A

21

L2582

30-OHM-1.7A

0402

21

L2584

30-OHM-1.7A

0402

21

L2588

30-OHM-1.7A

0402

21

L2586

30-OHM-1.7A

0402

21

L2555

4.7UF

X5R 402

20%

4V

2

1

C2500

4.7UF

X5R 402

20%

4V

2

1

C2501

0.1uF

CERM 402

20% 10V

2

1

C2526

0.1uF

CERM 402

20% 10V

2

1

C2525

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2560

0.1UF

CERM 402

20% 10V

2

1

C2589

0.1UF

CERM 402

20% 10V

2

1

C2590

4.7UF

X5R 402

20%

4V

2

1

C2595

30-OHM-1.7A

0402

21

L2595

1.47K

MF-LF

402

1%

1/16W

2

1

R2590

0.1UF

CERM 402

20% 10V

2

1

C2591

1.47K

MF-LF

402

1%

1/16W

2

1

R2591

18

0.1uF

CERM 402

20% 10V

2

1

C2521

CERM 402

20% 10V

0.1uF

2

1

C2518

0.1uF

CERM 402

20% 10V

2

1

C2519

10V 402

CERM

0.1UF

20%

2

1

C2583

0.1UF

CERM 402

20% 10V

2

1

C2585

0.1UF

CERM 402

20% 10V

2

1

C2587

0.1UF

CERM 402

20% 10V

2

1

C2596

0.1uF

CERM 402

20% 10V

2

1

C2529

4.7uF

X5R 402

20%

4V

2

1

C2528

30-OHM-1.7A

0402

21

L2580

0.1UF

CERM

20% 10V

402

2

1

C2581

4.7UF

X5R 402

20%

4V

2

1

C2503

97

051-7892

A.0.0

24

MCP Standard Decoupling

SYNC_MASTER=T18_MLB

SYNC_DATE=06/18/2008

PP1V2R1V05_ENET

PPCPUVTT_S0

PP1V2R1V05_S5

PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_CORE

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_ENET_MCP_PLL_MAC

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V2R1V05_ENET

PP3V3_ENET_PHY

MCP_MII_VREF

PP3V3_S0

PP3V3_S5

PP1V8R1V5_S0_FET

PP3V3_S0

PP3V3_ENET_PHY

PP1V05_S0_MCP_PEX_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPCPUVTT_S0

PP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPCPUVTT_S0

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

PPVCORE_S0_MCP_REG

PPCPUVTT_S0

7 8

18 24 33 34 37

6 7 8 9

10 11 12 13 14 17

18 20 22 24 25 63 67

7 8

22 34 68

7 8

68

21

16

20

18

7 8

18 24 33 34 37

7 8

18 24 33 34

6 7 8

13 18 19 21

22 24 25 28 29 37 39 43 45

47 48 49 51 55 59 60 63 68

69 70 77 80 81 82 84 85

96

6 7 8

13 18 19 21

22 24 25 28 29 37 39 43 45

47 48 49 51 55 59 60 63 68

69 70 77 80 81 82 84 85

96

7 8

18 20 22 26 30

34 37 38 44 54 64 68 69 70

82 87 96

7 8

11 12 16 28 29

39 68 69 70

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

18 24 33 34

8

17

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

8

20

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

14

17

7 8

22 46 66

6 7 8 9

10 11 12 13 14 17

18 20 22 24 25 63 67

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

95 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

190 mA (A01, 1.8V)

16 mA (A01)

Apple: ???

16 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

NO STUFF

0.1UF

CERM

402

20% 10V

2

1

C2620

NO STUFF

1K

MF-LF 402

1% 1/16W

2

1

R2630

NO STUFF

0.1UF

CERM

402

20% 10V

2

1

C2630

4.7UF

X5R 402

20%

4V

2

1

C2615

4.7UF

CERM

603

20%

6.3V 2

1

C2640

30-OHM-1.7A

0402

21

L2640

0.1uF

CERM 402

20% 10V

2

1

C2641

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2616

0

MF-LF 402

5% 1/16W

2

1

R2651

1K

MF-LF 402

1% 1/16W

2

1

R2620

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2610

051-7892

A.0.0

9725

MCP Graphics Support

SYNC_MASTER=AMASON_M98_MLB

SYNC_DATE=06/18/2008

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_RED

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NC_MCP_RGB_RED NC_MCP_RGB_GREEN

NC_CRT_IG_B_COMP_PB

NC_MCP_CLK27M_XTALIN NC_MCP_CLK27M_XTALOUT

MCP_IFPAB_VPROBE

NC_MCP_TV_DAC_RSET NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

NC_MCP_RGB_DAC_VREF

MCP_HDMI_VPROBE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE NC_MCP_RGB_HSYNC NC_MCP_RGB_VSYNC

NC_MCP_RGB_BLUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

NC_CRT_IG_R_C_PR

NC_MCP_RGB_DAC_RSET

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNCNC_CRT_IG_VSYNC

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_YNC_CRT_IG_G_Y_Y

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

PP1V8_S0

MCP_HDMI_RSET

PP3V3_S0

MCP_IFPAB_RSET

PPCPUVTT_S0

PP3V3_S0_MCP_VPLL

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_DAC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

18 25

18 25 90

18 25

18 25 90

18 25

18 90

18 25 90

18 25 90 18 25 90

18 25

18 25 90

18 25

18 90

18 25

18 25 90

18 25

18 25 90 18 25 90

18 25 90

18 25 90 18 25 90

18 25

7 8

18 55 69 70 84 87

18 90

6 7 8

13 18 19 21 22 24 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

18 90

6 7 8 9

10 11 12 13 14 17 18

20 22 24 63 67

18

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

OUTY

B

A

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

but results in MCP79 ROMSIP sequence happening after CPU powers up.

Reset Button

10K pull-up to 3.3V S0 inside MCP

Platform Reset Connections

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization.

RTC Power Sources

LPC Reset (Unbuffered)

PCIE Reset (Unbuffered)

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

MCP S0 PWRGD & CPU_VLD

MCP 25MHz Crystal

RTC Crystal

10 13 21

12pF

CERM

402

5%

50V

21

C2810

12pF

CERM

402

5%

50V

21

C2811

0

MF-LF

5%

1/16W

402

21

R2810

NO STUFF

MF-LF

402

5%

1/16W

10M

2

1

R2811

19 84 91

XDP

0

MF-LF

402

5%

1/16W

21

R2896

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2883

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2881

0

MF-LF

402

5%

1/16W

21

R2890

SILK_PART=FP SYS RESET

OMIT

0

MF-LF

402

5%

1/16W

2

1

R2897

44

42

21

17 26 37

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2826

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2825

19 91

12pF

CERM

402

5%

50V

21

C2815

12pF

CERM

402

5%

50V

21

C2816

CRITICAL

25.0000M

SM-3.2X2.5MM

31

42

Y2815

0

MF-LF

402

5%

1/16W

21

R2815

NO STUFF

1M

MF-LF

402

5%

1/16W

2

1

R2816

21

42 91

PLACEMENT_NOTE=Place close to U1400

22

MF-LF

402

5%

1/16W

21

R2829

21 91

33

MF-LF

402

5%

1/16W

21

R2899

NO STUFF

1UF

X5R 402

10% 10V

2

1

C2899

17 26 37

9

65 70

33

MF-LF

402

5%

1/16W

21

R2870

19

42

44 91

42 91

32.768K

7X1.5X1.4-SM

CRITICAL

41

Y2810

0

5% 1/16W MF-LF

402

21

R2891

27

MF-LF

1/16W

5%

402

0

21

R2893

86

31

1/16W

5%

402

MF-LF

0

21

R2894

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2827

84

26 84

21

63

42 69

MCPSEQ_MIX

0

MF-LF

402

5%

1/16W

21

R2851

MCPSEQ_SMC

0.1UF

CERM 402

20% 10V

2

1

C2850

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_SMC

0

MF-LF

402

5%

1/16W

21

R2850

21

MCPSEQ_SMC

0

MF-LF

402

5%

1/16W

21

R2853

21

MCPSEQ_MIX

0

MF-LF

402

5%

1/16W

21

R2852

MCPSEQ_SMC

TC7SZ08AFEAPE

SOT665

4

5

3

1

2

U2850

402

16V X5R

0.1UF

10%

2

1

C2801

6.3V 402

20%

4.7UF

X5R

2

1

C2802

X5R

4.7UF

402

20%

6.3V

2

1

C2803

402

0

5% 1/16W MF-LF

21

R2895

32

051-7892

26

A.0.0

97

SB Misc

SYNC_MASTER=DDR

SYNC_DATE=12/15/2008

PP3V42_G3H

PCIE_RESET_L

PP3V42_G3H

RTC_CLK32K_XTALOUT_R

LPC_RESET_L

MINI_RESET_L

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT_R

PP3V3_S5

MCP_PS_PWRGD

MCP_CPU_VLD

MCP_CPUVDD_EN

MAKE_BASE=TRUE

GMUX_PCIE_RESET_L

PM_CLK32K_SUSCLK_R

LPC_CLK33M_SMC_R

PCA9557D_RESET_L

MEM_VTT_EN

LPC_CLK33M_GMUX

PM_CLK32K_SUSCLK

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

SMC_LRESET_L

DEBUG_RESET_L

PM_SYSRST_L

PM_SYSRST_DEBOUNCE_L

XDP_DBRESET_L

S0_AND_IMVP_PGOOD

VR_PWRGOOD_DELAY

GMUX_PCIE_RESET_L

MEM_VTT_EN_R

ALL_SYS_PWRGD

BKLT_PLT_RST_L

CARDREADER_PLT_RST_L

MAKE_BASE=TRUE

PCIE_RESET_L

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7 8

18 20 22 24 30 34 37 38

44 54 64 68 69 70 82 87 96

26 84

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Place close to U8400, U8450

Place close to J3200.126

Place close to J3100.126

MEM A VREF CA

DAC channel A B A B C D

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV

Place close to J3200.1

MEM B VREF CA

FRAME BUFFER VREF

CPU FSB VREF

- =PP3V3_S5_VREFMRGN

- =I2C_VREFDACS_SCL

BOM options provided by this page:

Place close to U8500, U8550

Place close to U1000.AD26

Page Notes

- =I2C_VREFDACS_SDA

10mA max load

- =PPVTT_S3_DDR_BUF

- =PP3V3_S3_VREFMRGN

ADDR=0x98(WR)/0x99(RD)

Place close to J3100.1

ADDR=0x30(WR)/0x31(RD)

Power aliases required by this page:

Required zero ohm resistors when no VREF margining circuit stuffed

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

VREFMRGN

NO_VREFMRGN

Signal aliases required by this page:

(per DAC LSB)

MEM A VREF DQ MEM B VREF DQ

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA

Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF

9

74

1/16W

1%

402

MF-LF

49.9

VREFMRGN

21

R2916

10 88

10V

20% 402

CERM

0.1UF

VREFMRGN

2

1

C2902

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2914

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2913

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2903

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2915

9

75

1/16W

1%

402

MF-LF

49.9

VREFMRGN

21

R2917

UCSP

MAX4253

VREFMRGN

B4

B1

C4

C1

C2

C3

U2902

UCSP

MAX4253

VREFMRGN

B4

B1

A4

A1

A2

A3

U2903

UCSP

MAX4253

VREFMRGN

B4

B1

A4

A1

A2

A3

U2902

UCSP

MAX4253

VREFMRGN

B4

B1

C4

C1

C2

C3

U2903

UCSP

MAX4253

VREFMRGN

B4

B1

A4

A1

A2

A3

U2904

UCSP

MAX4253

VREFMRGN

B4

B1

C4

C1

C2

C3

U2904

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2905

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2909

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2911

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2902

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2901

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2904

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2906

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2910

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2907

QFN

PCA9557

VREFMRGN

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2901

10V

20%

402

CERM

0.1UF

VREFMRGN

2

1

C2904

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2912

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2908

26

27 39 42 45 94

MSOP

DAC5574

VREFMRGN

5

4

2

1

8

7

6

3

10

9

U2900

27 39 42 45 94

10V

20% 402

CERM

0.1UF

VREFMRGN

2

1

C2901

6.3V

20% 402-LF

CERM

2.2UF

VREFMRGN

2

1

C2900

10V

20%

402

CERM

0.1UF

VREFMRGN

2

1

C2905

10V

20%

402

CERM

0.1UF

VREFMRGN

2

1

C2903

SYNC_DATE=12/05/2008

27 97

A.0.0

051-7892

SYNC_MASTER=DDR

FSB/DDR3/FRAMEBUF Vref Margining

R2905

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

NO_VREFMRGN

R2911

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

NO_VREFMRGN

R2909

1

116S0004 CRITICAL

NO_VREFMRGN

RES,MTL FILM,0,5%,0402,SM,LF

R2903

1

116S0004 CRITICAL

NO_VREFMRGN

RES,MTL FILM,0,5%,0402,SM,LF

VREFMRGN_CPUFSB_EN

SMBUS_SMC_MGMT_SDA

VREFMRGN_FRAMEBUF_EN

VREFMRGN_DQ_SODIMM

PPVTTDDR_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_FRAMEBUF_EN

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

PCA9557D_RESET_L

VREFMRGN_DQ_SODIMMA_EN

SMBUS_SMC_MGMT_SCL

VREFMRGN_CA_SODIMMB_EN

CPU_GTLREF

GPU_FB_B_VREF_DIV

GPU_FB_A_VREF_DIV

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

PP3V3_S3

VREFMRGN_CPUFSB

VREFMRGN_DQ_SODIMMB_BUF

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

27

8

65

28

27

7 8

21 31 32 45 50 52 70

28

29

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

516-0196

SPD ADDR=0xA0(WR)/0xA1(RD)

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

"Factory" (top) slot

- =I2C_SODIMMA_SDA

- =PP0V75_S0_MEM_VTT_A

- =I2C_SODIMMA_SCL

- =PP1V5_S3_MEM_A

BOM options provided by this page:

(NONE)

F-RT-THB

DDR3-SODIMM-DUAL-M97-3

113

204203

196195

190189

185

184

179

178

173

172

168167

162161

156155

151

150

145

144

139

138

134133

128127

126

199

100

99

9493

8887

8281

124123

118117

112111

106105

7675

125

200 202201

197

121

114

110

120

116

122

77

198

186 188

169 171

152 154

135 137

194

192

182

180

193

191

183

181

176

174

166

164

177

175

165

163

160

158

148

146

159

157

149

147

142

140

132

130

143

141

131

129

187

170

153

136

7473

104

102

103

101

115

79

108

109

85

89

86

90

91 92

95 96

78 80

119

83 84

107

97 98

J3100

15 89

10V

20%

402

CERM

0.1UF

2

1

C3131

6.3V

20%

402-LF

CERM

2.2UF

2

1

C3130

15 89

29 30

15 89

F-RT-THB

DDR3-SODIMM-DUAL-M97-3

CRITICAL

2625

2019

1413

9

7271

6665

61

60

8

55

54

49

48

4443

3837

3231

3

21

30

62 64

45 47

27 29

10 12

23

21

18

16

6

4

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

63

46

28

11

J3100

15 89

9

15 89

10V

20% 402

CERM

0.1UF

2

1

C3136

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3135

15 89

21 29 42

13 21 29 45 91

15 89

1/16W

5%

402

MF-LF

10K

2

1

R3141

1/16W

5%

402

MF-LF

10K

2

1

R3140

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3140

6.3V

20%

603

X5R

10UF

2

1

C3100

6.3V

20%

603

X5R

10UF

2

1

C3101

10V

20% 402

CERM

0.1UF

2

1

C3110

10V

20% 402

CERM

0.1UF

2

1

C3111

10V

20% 402

CERM

0.1UF

2

1

C3112

10V

20% 402

CERM

0.1UF

2

1

C3113

10V

20% 402

CERM

0.1UF

2

1

C3114

10V

20% 402

CERM

0.1UF

2

1

C3115

10V

20% 402

CERM

0.1UF

2

1

C3116

10V

20% 402

CERM

0.1UF

2

1

C3117

10V

20% 402

CERM

0.1UF

2

1

C3118

10V

20% 402

CERM

0.1UF

2

1

C3119

10V

20% 402

CERM

0.1UF

2

1

C3120

10V

20% 402

CERM

0.1UF

2

1

C3121

10V

20% 402

CERM

0.1UF

2

1

C3122

10V

20% 402

CERM

0.1UF

2

1

C3123

28 97

A.0.0

051-7892

DDR3 SO-DIMM Connector A

SYNC_DATE=07/22/2008

SYNC_MASTER=DDR

MEM_A_BA<2>

MEM_A_DQ<60>

MEM_A_DQ<58> MEM_A_DQ<59>

MEM_A_SA<0>

PP1V8R1V5_S0_FET

MEM_A_DQ<3> MEM_A_DQ<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DM<0>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQ<11> MEM_A_DQ<14>

MEM_A_DQ<18>

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MEM_A_DQ<23> MEM_A_DQ<19>

MEM_A_DQ<30>

MEM_A_DQ<24>

MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_DQ<6> MEM_A_DQ<7>

MEM_A_DQ<8> MEM_A_DQ<12>

MEM_A_DM<1> MEM_RESET_L

MEM_A_DQ<15> MEM_A_DQ<10>

MEM_A_DQ<21> MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17> MEM_A_DQ<22>

MEM_A_DQ<29> MEM_A_DQ<28>

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MEM_A_DQ<26> MEM_A_DQ<31>

MEM_A_DQ<4>

MEM_A_DM<3>

MEM_A_DQ<16>

PP3V3_S0

MEM_A_CKE<1>

TP_MEM_A_A<15> MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_ODT<0>

MEM_A_ODT<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<36> MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38> MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<47>

MEM_A_DQS_N<5>

MEM_A_CKE<0>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_BA<0>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<13> MEM_A_CS_L<1>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<44> MEM_A_DQ<41>

MEM_A_DQ<46>

MEM_A_DQS_P<5>

MEM_A_DQ<43>

MEM_A_DQ<48> MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_EVENT_L

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

MEM_A_DQ<45>

MEM_A_DM<5>

MEM_A_DQ<42>

MEM_A_DQ<52> MEM_A_DQ<51>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<61>

MEM_A_DM<7>

MEM_A_CLK_N<0>

MEM_A_DQ<35>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

PP0V9R0V75_S0_DDRVTT

MEM_A_SA<1>

MEM_A_A<10>

MEM_A_DQ<32>

MEM_A_A<5>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6>

MEM_A_DQ<27> MEM_A_DQ<25>

PP1V8R1V5_S3

MEM_A_CS_L<0>

MEM_A_BA<1>

7 8

11 12 16 24 29 39 68 69

70

27

6 7 8

13 18 19

21 22 24 25 29 37 39 43

45 47 48 49 51

55 59 60 63 68 69 70 77

80 81 82 84 85

96

27

7 8

29 65 70

7 8

29 30 65 70

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Power aliases required by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

BOM options provided by this page:

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

Page Notes

516s0704

SPD ADDR=0xA2(WR)/0xA3(RD)

- =PP1V5_S0_MEM_B

"Expansion" (bottom) slot

(NONE)

Signal aliases required by this page:

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

15 89

21 28 42

13 21 28 45 91

10V

20%

402

CERM

0.1UF

2

1

C3231

15 89

6.3V

20%

402-LF

CERM

2.2UF

2

1

C3230

1/16W

5%

402

MF-LF

10K

2

1

R3241

1/16W

5%

402

MF-LF

10K

2

1

R3240

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3240

6.3V

20%

603

X5R

10UF

2

1

C3200

6.3V

20%

603

X5R

10UF

2

1

C3201

10V

20% 402

CERM

0.1UF

2

1

C3210

10V

20% 402

CERM

0.1UF

2

1

C3211

10V

20% 402

CERM

0.1UF

2

1

C3212

10V

20% 402

CERM

0.1UF

2

1

C3213

15 89

10V

20% 402

CERM

0.1UF

2

1

C3214

10V

20% 402

CERM

0.1UF

2

1

C3215

10V

20% 402

CERM

0.1UF

2

1

C3216

10V

20% 402

CERM

0.1UF

2

1

C3217

10V

20% 402

CERM

0.1UF

2

1

C3218

10V

20% 402

CERM

0.1UF

2

1

C3219

10V

20% 402

CERM

0.1UF

2

1

C3220

10V

20% 402

CERM

0.1UF

2

1

C3221

10V

20% 402

CERM

0.1UF

2

1

C3222

10V

20% 402

CERM

0.1UF

2

1

C3223

15 89

F-RT-BGA3

DDR3-SODIMM

113

204203

212211

210209

208207

206205

196195

190189

185

184

179

178

173

172

168167

162161

156155

151

150

145

144

139

138

134133

128127

126

199

100

99

9493

8887

8281

124123

118117

112111

106105

7675

125

200 202201

197

121

114

110

120

116

122

77

198

186 188

169 171

152 154

135 137

194

192

182

180

193

191

183

181

176

174

166

164

177

175

165

163

160

158

148

146

159

157

149

147

142

140

132

130

143

141

131

129

187

170

153

136

7473

104

102

103

101

115

79

108

109

85

89

86

90

91 92

95 96

78 80

119

83 84

107

97 98

J3200

15 89

28 30

15 89

F-RT-BGA3

DDR3-SODIMM

CRITICAL

2625

2019

1413

9

7271

6665

61

60

8

55

54

49

48

4443

3837

3231

3

21

30

62 64

45 47

27 29

10 12

23

21

18

16

6

4

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

63

46

28

11

J3200

15 89

9

15 89

10V

20% 402

CERM

0.1UF

2

1

C3236

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3235

15 89

DDR3 SO-DIMM Connector B

SYNC_DATE=07/22/2008

051-7892

A.0.0

9729

SYNC_MASTER=DDR

PP1V8R1V5_S0_FET

MEM_B_DQ<9>

MEM_B_DQ<18> MEM_B_DQ<22>

MEM_B_DQ<4>

MEM_B_DQ<23>

MEM_B_DQ<19>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<16>

MEM_B_DQ<20>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DM<1>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_RESET_L

MEM_B_DM<3>

MEM_B_DQ<25>

MEM_B_DQ<29>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<5>

MEM_B_DQ<21> MEM_B_DQ<17>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<8>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_DM<0>

MEM_B_DQ<0> MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<3>

MEM_B_DQ<2>

PP3V3_S0

MEM_B_DQ<59>

MEM_B_DQ<63>

MEM_B_SA<0>

MEM_B_SA<1>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DM<7>

MEM_B_CAS_L

MEM_B_DQS_P<4>

MEM_B_DQ<35>

MEM_B_CLK_N<0>

MEM_B_A<10>

MEM_B_DQ<52> MEM_B_DQ<51>

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK

PP0V9R0V75_S0_DDRVTT

MEM_EVENT_L

MEM_B_DQ<58>

MEM_B_DQS_N<7> MEM_B_DQS_P<7>

MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQ<50>

MEM_B_DQ<53>

MEM_B_DM<6>

MEM_B_DQ<54>

MEM_B_DQ<48>

MEM_B_DQ<46>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<41>

MEM_B_DQ<34>

MEM_B_DQ<32> MEM_B_DQ<37>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_DQS_N<5>

MEM_B_DQ<44> MEM_B_DQ<45>

MEM_B_DQ<39>

MEM_B_DM<4>

MEM_B_DQ<36>

MEM_B_DQ<33>

PP0V75_S3_MEM_VREFCA_B

MEM_B_ODT<1>

MEM_B_CS_L<0> MEM_B_ODT<0>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

TP_MEM_B_A<15>

MEM_B_CKE<1>

MEM_B_DM<5>

MEM_B_DQS_N<4>

MEM_B_DQ<40>

MEM_B_DQ<55>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8> MEM_B_A<5>

MEM_B_A<3> MEM_B_A<1>

PP1V8R1V5_S3

MEM_B_CKE<0>

MEM_B_DQ<24>

MEM_B_DQ<38>

MEM_B_DQ<49>

MEM_B_DQ<62>

MEM_B_DM<2>

MEM_B_CLK_N<1>

7 8

11 12 16 24 28 39 68 69

70

27

6 7 8

13 18 19 21

22 24 25 28 37 39 43 45 47

48 49 51 55 59 60

63 68 69 70 77 80 81 82 84

85 96

7 8

28 65 70

27

7 8

28 30 65 70

D

Q2

SG

Q1

B

C

E

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

must be high before 1.5V starts to

3.3V S5 is used because MEM_RESET

rise to avoid glitch on MEM_RESET_L.

CRITICAL

DMB53D0UDW

SOT-363

12

4 6

3

5

Q3305

5% 1/16W MF-LF

402

100K

2

1

R3305

28 29

5%

402

MF-LF

1/16W

10K

2

1

R3300

10V

0.1UF

20% CERM

402

2

1

C3300

402

1/16W

20K

5%

MF-LF

2

1

R3301

402

0

1/16W MF-LF

5%

12

R3309

16

5% 1/16W MF-LF

402

1K

2

1

R3310

051-7892

A.0.0

9730

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2008

DDR3 Support

PP1V8R1V5_S3

MEM_RESET_L

MEM_RESET_RC_L

MEM_RESET

PP3V3_S5

MCP_MEM_RESET_L

7 8

28 29 65 70

7 8

18 20 22 24 26 34 37 38 44

54 64 68 69 70 82 87 96