Apple A1386 Schematics

TABLE_TABLEOFCONTENTS_ITEM

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

SCHEM,CORNHOLE,K19

Schematic / PCB #’s

PVT 04/24/2009

ALIASES RESOLVED

(.csa)

Date

SyncPage Contents

LAST_MODIFIED=Fri Apr 24 15:23:24 2009

TITLE=MLB

ABBREV=DRAWING

91

02/18/2008

103

MUXGFX

MCP Constraints 2

Date

SyncContents

(.csa)

Page

53

08/14/2008

46

SENSOR

Current & Voltage Sensing

(.csa)

Page

Date

Contents Sync

820-2523

1

CRITICAL

PCBF,CORNHOLE,K19

PCB

051-7892

SCH

1

CRITICAL

SCHEM,CORNHOLE,K19

DDR

1

12/05/2008

1

Table of Contents

92

02/18/2008

104

MUXGFX

Ethernet Constraints

93

02/18/2008

105

MUXGFX

FireWire Constraints

94

02/18/2008

106

MUXGFX

SMC Constraints

95

02/18/2008

107

MUXGFX

GPU (G96) CONSTRAINTS

96

02/21/2008

108

MUXGFX

Project Specific Constraints

97

01/22/2008

109

M99_MLB

PCB Rule Definitions

54

12/10/2008

47

YUN_K19_MLB

Current Sensing

55

12/22/2008

48

YUN_K19_MLB

Thermal Sensors

56

10/17/2007

49

M87_MLB

Fan Connectors

57

06/18/2008

50

AMASON_M98_MLB

WELLSPRING 1

58

01/05/2009

51

PWRSQNC

WELLSPRING 2

59

08/14/2008

52

SENSOR

Sudden Motion Sensor (SMS)

60

12/19/2008

53

DDR

DEBUG SENSORS AND ADC

61

07/01/2008

54

CHANG_M98_MLB

SPI ROM

62

03/16/2009

55

AUDIO

AUDIO: CODEC/REGULATOR

63

03/16/2009

56

AUDIO

AUDIO: LINE INPUT FILTER

65

03/16/2009

57

AUDIO

AUDIO: HEADPHONE FILTER

66

03/16/2009

58

AUDIO

AUDIO: SPEAKER AMP

67

03/16/2009

59

AUDIO

AUDIO: JACKS

68

03/16/2009

60

AUDIO

AUDIO: JACK TRANSLATORS

69

12/16/2008

61

YUN_K19_MLB

DC-In & Battery Connectors

70

12/10/2007

62

M99_MLB

PBus Supply & Battery Charger

71

10/17/2007

63

M87_MLB

IMVP6 CPU VCore Regulator

72

12/17/2008

64

PWRSQNC

5V / 3.3V Power Supply

73

12/05/2008

65

DDR

1.5V DDR3 Supply

75

11/14/2008

66

M98_MLB

MCP CORE REGULATOR

76

12/14/2007

67

M99_MLB

CPU VTT / 1V05 S0 Power Supply

77

12/14/2007

68

M99_MLB

Misc Power Supplies

78

12/17/2008

69

PWRSQNC

Power Control

79

12/05/2008

70

DDR

Power FETs

80

07/10/2008

71

MUXGFX

NV G96 PCI-E

81

07/10/2008

72

MUXGFX

NV G96 Core/FB Power

82

07/10/2008

73

MUXGFX

NV G96 Frame Buffer I/F

84

07/10/2008

74

MUXGFX

GDDR3 Frame Buffer A (Top)

85

07/10/2008

75

MUXGFX

GDDR3 Frame Buffer B (Top)

86

07/10/2008

76

MUXGFX

NV G96 GPIO/MIO/Misc

87

07/09/2008

77

MUXGFX

G96 GPIOs & Straps

88

07/10/2008

78

MUXGFX

NV G96 Video Interfaces

89

10/17/2007

79

M87_MLB

GPU (G96) CORE SUPPLY

90

12/19/2008

80

DDR

LVDS Display Connector

93

12/05/2008

81

AMASON_M98_MLB

Muxed Graphics Support

94

07/10/2008

82

MUXGFX

DisplayPort Connector

95

07/10/2008

83

MUXGFX

1.1V / 1V8 FB Power Supply

96

07/10/2008

84

MUXGFX

Graphics MUX (GMUX)

97

12/12/2008

85

DDR

LCD BACKLIGHT DRIVER

98

07/02/2008

86

YITE_M98_MLB

LCD Backlight Support

99

02/01/2008

87

MUXGFX

Misc Power Supplies

100

02/18/2008

88

MUXGFX

CPU/FSB Constraints

101

02/18/2008

89

MUXGFX

Memory Constraints

102

02/18/2008

90

MUXGFX

MCP Constraints 1

T18_MLB

2

12/12/2007

2

System Block Diagram

T18_MLB

3

12/12/2007

3

Power Block Diagram

N/A

4

N/A4

Power Block Diagram

DDR

5

12/18/2008

5

BOM Configuration

DDR

6

07/22/2008

6

JTAG Scan Chain

N/A

7

N/A7

Functional / ICT Test

(MASTER)

8

(MASTER)

8

Power Aliases

(MASTER)

9

(MASTER)

9

Signal Aliases

M98_MLB

10

11/12/2008

10

CPU FSB

M98_MLB

11

11/12/2008

11

CPU Power & Ground

M87_MLB

12

10/17/2007

12

CPU Decoupling & VID

M98_MLB

13

11/12/2008

13

eXtended Debug Port(MiniXDP)

T18_MLB

14

12/12/2008

14

MCP CPU Interface

T18_MLB

17

04/04/2008

17

MCP PCIe Interfaces

T18_MLB

18

12/12/2008

18

MCP Ethernet & Graphics

T18_MLB

19

12/12/2008

19

MCP PCI & LPC

T18_MLB

20

12/12/2008

20

MCP SATA & USB

T18_MLB

21

12/12/2008

21

MCP HDA & MISC

T18_MLB

22

12/12/2008

22

MCP Power & Ground

T18_MLB

23

03/31/2008

24

MCP79 A01 Silicon Support

T18_MLB

24

06/18/2008

25

MCP Standard Decoupling

AMASON_M98_MLB

25

06/18/2008

26

MCP Graphics Support

DDR

26

12/15/2008

28

SB Misc

DDR

27

12/05/2008

29

FSB/DDR3/FRAMEBUF Vref Margining

DDR

28

07/22/2008

31

DDR3 SO-DIMM Connector A

DDR

29

07/22/2008

32

DDR3 SO-DIMM Connector B

T18_MLB

30

12/12/2008

33

DDR3 Support

MUXGFX

31

12/08/2008

34

Right Clutch Connector

VEMURI

32

01/30/2009

35

SECUREDIGITAL CARD READER

SUMA_M98_MLB

33

07/01/2008

37

Ethernet PHY (RTL8211CL)

SUMA_M98_MLB

34

07/01/2008

38

Ethernet & AirPort Support

AMASON_M98_MLB

35

12/16/2008

39

Ethernet Connector

SENSOR

36

08/14/2008

41

FireWire LLC/PHY (FW643)

YUN_K19_MLB

37

12/22/2008

42

FireWire Port Power

SENSOR

38

08/14/2008

43

FireWire Ports

PWRSQNC

39

12/04/2008

45

SATA Connectors

M98_MLB

40

11/14/2008

46

External USB Connectors

PWRSQNC

41

12/04/2008

48

Front Flex Support

T18_MLB

42

12/12/2008

49

SMC

DDR

43

12/19/2008

50

SMC Support

CHANGZHANG

44

05/09/2008

51

LPC+SPI Debug Connector

DDR

45

12/19/2008

52

K19 SMBUS CONNECTIONS

A.0.0

SCHEM,MBP 15MLB

??

?

1

051-7892

97

?

T18_MLB

16

12/12/2008

16

MCP Memory Misc

T18_MLB

15

12/12/2008

15

MCP Memory Interface

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PG 9

PG 60

AmpAmp

Line In

U3700

Mini PCI-E

AirPort

PG 18

RGMII

HDMI OUT

DP OUT

LVDS OUT

PG 17

UP TO 20 LANES3

PG 16

PCI-E

DVI OUT

U1400

Boot ROM

PG 52

Bluetooth

7650 1

DIMM’s

SMB

CONN

PG 44

Connectors

CAMERA

PG 41

NVIDIA

HDA

PG 20

SMB

PG 24

FSB INTERFACE

PG 13

PG 38

RGB OUT

1.05V/3GHZ.

SATA

GPIOs

LPC Conn

Port80,serial

PG 14

Misc

PWR

BSB

Prt

B,0

SMC

ADC Fan

Ser

PG 43

J5100

FAN CONN AND CONTROL

TEMP SENSOR

SPI

PG 25,26

DIMM

J2900

DDR3-1067/1333MHZ

DDR2-800MHZ

800/1067/1333 MHz

MAIN

MEMORY

PG 18

PG 20

SPI

INTEL CPU

2.X OR 3.X GHZ

PENRYN

DC/BATT

J4900

PG 48,49

J5650,5600,5610,5611,5660,5720,5730,5750

POWER SENSE

PG 45

USB

TRACKPAD/

KEYBOARD

PG 40

USB

EXTERNAL

J3900,4635,4655

U6100

PG 39

SYNTH

Conn

ODD

E-NET

HD

PG 40

J4700

PG 40

U6600,6605,6610,6620

J4510

U1300

U1000

PG 12

J6950

U4900

J4710

PG 57

J4720

U6200

PG 53

PG 54

Amps

Speaker

Amp

E-NET

GB

PG 31

88E1116

Conn

PG 33

U3900 J3400

PG 28

POWER SUPPLY

XDP CONN

2 UDIMMs

64-Bit

FSB

Codec

Audio

HEADPHONE

PG 55 PG 56

PG 59

U6400 U6500U6301

SATA

PG 40

983

LPC

PG 19

PCI

PG 19

MCP79

PG 41

J6800,6801,6802,6803

Conns

(UP TO FOUR PORTS)

SATA

CLK

J4710

IR

CTRL

2

Line Out

TMDS OUT

4

(UP TO 12 DEVICES)

PG 17

J4520

Conn

PG 71

CONN

PG 71

LVDS CONN

J9000

DISPLAY PORT

J9400

SYNC_MASTER=T18_MLB

051-7892

97

2

A.0.0

SYNC_DATE=12/12/2007

System Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

M98 POWER SYSTEM ARCHITECTURE

(6A MAX CURRENT)

CPU_PWRGD

(PAGE 43)

EN_PSV

1.05V

CHGR_EN

(S5)

PP5V_S3

PP3V3_S5

PPVIN_G3H_P3V42G3H

V

PPBUS_G3H

DELAY

EN1

VOUT2

ALL_SYS_PWRGD

RST*

PGOOD

U7100

VIN

VR_PWRGD_CLKEN_L

V

SMC_CPU_VSENSE

GPUVCORE_PGOOD

EN_PSV

SMC_BATT_ISENSE

PPVBAT_G3H_CHGR_REG

D6905

8A FUSE

U5715

(9 TO 12.6V)

P3V3S3_EN

P5VS3_EN

LIO_S3_EN

A

V

PPVCORE_GPU_REG

U5705

(PAGE 42)

P17(BTN_OUT)

PM_WLAN_EN_L

PM_ENET_EN

WOW_EN

Q3801

PGOOD

(S5)

SMC_PM_G2_EN

U7859

PBUSVSENS_EN

(S0)

MCP79

(S0)

VIN

VOUT

Q3810

SLP_S5#(H17)

SLP_S3#(G17)

(PAGE 14~22)

BKLT_EN

VIN

U4900

VOUT

D6905

VOUT

SMC_GPU_VSENSE

U5498

PGOOD

(PAGE 78)

IMVP_VR_ON_R

SMC PWRGD

PM_GPUVCORE_EN

AC

A

ENABLES

Q5315

PBUSB_VSENSE

P5V_RT_EN

P60

A

3S2P

U1400

(PAGE 14~22)

U1400

RSMRST*

MCP79

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

VR_PWRGOOD_DELAY

S5

RUN2

VOUT1

EN2

ENA

RUN1

S3

EN/PSV

RESET*

(PAGE 10,11)

PWRGOOD

PLTRST*

PWRBTN#

SMC

U1000

CPU

U2850

VOUT2

PGOOD1,2

VOUT2

U2830

VIN

A

VOUT

VR_ON

VIN

P1V8FB_EN

VOUT

ADAPTER

(L/H)

VIN

RN5VD30A-F

U5000

ENABLE

SMC_RESET_L

IN

VIN

EN2

VIN

ENL

VREG3

EN0

VIN

VOUT1

Q7055

LIO_DCIN_ISENSE

SMC

Q3805

DELAY

P3V3S0_EN

(S0)

PM_ENET_EN_L

Q7920

(PAGE 61)

PP1V1_S0GPU_REG

U5400

PPBUS_G3H

P1V1GPU_EN

EN1

VOUT1

(R/H)

P3V3S5_EN

VLDOIN

VOUT2

PPVCORE_CPU_S0

CPUVCORE_IOUT

VOUT2

VIN

PP5V_S0 PP3V3_S0

PP1V5_S0_REG

V4

V3

V2

V1

U7870

RST*

VOUT1

PP1V8_GPU_REG

V4

U9701

(PAGE 84)

(PAGE 64)

SC417

U7400

VIN

1.103V(L/H)

1.8V(R/H)

TPS51124

U9500

(PAGE 82)

5V

3.3V

TPS51125

U7201

(PAGE 62)

CPU VCORE

ISL9504B

ISL6263B

U8900

GPU VCORE

3.425V G3HOT

LT3470

U6990

(PAGE 59)

PP3V42_G3H_REG

VOUT

TPS51117

U7600

(PAG 66)

PGOOD

CPUVTTS0_EN

PPCPUVTT_S0_REG

CPUVTTS0_PGOOD

ISL8009

U7750

(PAGE 66)

(8A MAX CURRENT)

PP5V_S5_REG

(5.5A MAX CURRENT)

PP3V3_S5_REG

PP5V_RT_REG

P5V_RT_PGOOD

P5V3V3_S5_PGOOD

Q7970

Q7930

PPVOUT_S0_LCDBKLT

GOSHAWK6P

LTC3407

U3850

(PAGE 33)

PP1V9_ENET_REG

PP1V2_ENET_REG

ENETAVDD_EN

P1V2ENET_EN

PPVIN_S0_DDRREG_LDO

1.8V

0.9V

TPS51116

(PAGE 63)

U7300

DDRREG_EN

DDRVTT_EN

PM_ENET_EN_L

WOL_EN

Q3800

PM_SLP_S3_L

P5VS0_EN

P5VRIGHT_EN

P1V8S0_EN

MCPDDR_EN

CPUVTTS0_EN

MCPCORES0_EN

P1V05S0_EN

MCP_CORE

1.1V

U7500

ISL6236

(PAGE 65)

MCPCPCORE_S0_REG

PP5V_RT_REG

PPVTT_S0_DDR_LDO

PPDDR_S3_REG

(12A MAX CURRENT)

P3V3ENET_EN_L

P3V3_ENET_FET

P3V3GPU_SS

PP3V3_S0_FET

PP3V3_S3_FET

Q7910

P5VS3_SS

PP5V_S3_FET

Q7900

P5VS0_SS

P1V05S0_PGOOD

P5VRIGHT_PGOOD MCPCORES0_PGOOD CPUVTTS0_PGOOD

P1V8S0_PGOOD

LTC2900

(PAGE 68)

PP1V05_S5_MCP

IMVP_VR_ON(P16)

PWRGD(P12)

RSMRST_OUT(P15)

99ms DLY

PM_RSMRST_L

SMC_RESET_L

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

U4900

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S5_L

(PAGE 60) PBUS SUPPLY/ BATTERY CHARGER

ISL6258A

U7000

DCIN(16.5V)

6A FUSE

BATT_POS_F

J6950

CHGR_BGATE

PPVBAT_G3H_CHGR_R

SMC_ADAPTER_EN

PM_SLP_S3_DELAY_L

(5A MAX CURRENT)

(25A MAX CURRENT)

PP5V_S0_FET

VRMPWRGD

VR_PWRGD_CLKEN

CK_PWRGD

PLT_RST_L

CPUPWRGD(GPIO49)

PWROK

MCP_PS_PWRGD

RSMRST_PWRGD

SMC_ONOFF_L

PM_PWRBTN_L

PWR_BUTTON(P90)

PLT_RST*

IMVP_VR_ON

RSMRST_IN(P13)

GPUVCORE_IOUT

(18A MAX CURRENT)

P3V3S3_SS

P1V5S0_PGOOD

S0PGOOD_PWROK

(PAGE 42)

P3V3S0_SS

PP3V3_S0GPU_FET

SYNC_MASTER=T18_MLB

051-7892

97

A.0.0

SYNC_DATE=12/12/2007

3

Power Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SYNC_MASTER=N/A

SYNC_DATE=N/A

4

97

A.0.0

051-7892

Power Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Development BOM

Module Parts

Bar Code Labels / EEE #’s

K19 BOM Groups

BOM Variants

KEMET ALT TO SANYOALL

128S0262128S0220

338S0554338S0714

Low Leakage G96 GPU

ALL

CYNTEC alt to YDS

ALL

107S0139 107S0075

138S0602

ALL

Murata alt to Samsung

138S0603

353S1294

ALL LMV2011,OPAMP. GBW

353S1681

152S0683

ALL

Maglayers alt to Dale/Vishay

152S0276

341S2366

ALL

Macronix alt to SST

341S2367

152S0867

Toko alt to Delta

152S1034

ALL

Delta alt to TDK Magnetics157S0055157S0058

Maglayers alt to Cyntec IND

ALL

152S0915 152S0796

ALL

ROHM ALT TO KEMET

127S0062 127S0108

152S0968 152S0966

Maglayer alt to Delta

ALL

CYNTEC alt to YDS

ALL

107S0138 107S0074

NXP alt to TI

311S0447 311S0406

ALL

K19_COMMON

ALTERNATE,COMMON,K19,K19_COMMON1,K19_COMMON2,K19_PROGPARTS

085-0736

K19 MLB DEVELOPMENT

K19_DEVEL_PVT

K19_COMMON1

BOOT_MODE_USER,DPMUX_EN_S0,DP_CA_DET_EG_PLD,DP_ESD,EG_PWRSEQ_HW,EXTRACT_BUFF

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

K19_PROGPARTS

BMON_PROD,LPCPLUS_NOT,NO_VREFMRGN

K19_PROD

K19_DEVEL_ENG

BMON_ENG,DEBUG_ADC,GMUX_JTAG,LPCPLUS,VREFMRGN,XDP_CONN

K19_DEVEL_PVT

BMON_PROD,LPCPLUS,NO_VREFMRGN,XDP_CONN

GMUX_1V8,GPUVID_1P00V,GPU_SS_INT,ISL6258A,MCP_B03,MCPSEQ_SMC,MIKEY,MUXGFX,SMC_DEBUG_YES,XDP

K19_COMMON2

K19_COMMON,DEVEL_BOM,EEE_6XT,CPU_3_06GHZ,FB_512_HYNIX

630-9970

PCBA,3.06GHZ,512HYN_VRAM,HB_AUDIO,K19

FB_256_SAMSUNG

VRAM4,VRAM_256_SAMSUNG

FB_512_SAMSUNG

VRAM4,VRAM_512_SAMSUNG

VRAM4,VRAM_512_HYNIX

FB_512_HYNIX

CRITICAL

EEE_6XN

[EEE:6XN]

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

1

EEE_6XP

[EEE:6XP]

826-4393 CRITICAL

[EEE:6XQ]

1

CRITICAL

EEE_6XQ

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

CRITICAL

1

EEE_6XR

[EEE:6XR]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEE:6XT]

EEE_6XT

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL

EEE_6XS

[EEE:6XS]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

337S3761

1

CRITICAL

U1000

IC,PDC,SLGLA,PRQ,2.66G,25W,1066,R0,3M,BGA

CPU_2_66GHZ

U1400

MCP_B03

338S0710 CRITICAL

IC,MCP79MXT-B3,35X35MM,BGA1437

1

CPU_3_06GHZ

U1000

1

CRITICAL337S3744

IC,PDC,SLGKH,QS,3.06G,35W,1066,E0,6M,BGA

CRITICAL

1

U1000

337S3682

IC,PDC,SLGEM,PRQ,2.80G,35W,1066,E0,6M,BGA

CPU_2_80GHZ

CRITICAL338S0694

U3700

1

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP

U4800

1

CRITICAL341S2384

IR,ENCORE II, CY7C63803-LQXC

1

U4100

CRITICAL338S0654

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

SMC_BLANK

CRITICAL

U4900

338S0563

1

IC,SMC,HS8/2117,9MMX9MM,TLP

341S2503

U5701

CRITICAL

IC,PSOC +W/USB,56PIN,MLF,K19

1

TPAD_PROG

SMC_PROG

1

U4900

IC,SMC,DEVELOPMENT,K19

341S2462 CRITICAL

1

U6100

BOOTROM_BLANK

335S0384 CRITICAL

IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

U6100

CRITICAL

IC,EFI ROM,DEVELOPMENT,K19

1

BOOTROM_PROG

341S2456

CRITICAL

4

U8400,U8450,U8500,U8550

VRAM_256_SAMSUNG

333S0507

IC,SGRAM,GDDR3,16Mx32,1000MHZ,136 FBGA

1

IC,GPU,55nm,NV G96-GS,BGA969,LF

U8000 CRITICAL

338S0554

CRITICAL

VRAM_256_HYNIX

4

333S0483

U8400,U8450,U8500,U8550

IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA

CRITICAL

1

085-0736

DEVEL_BOM

DEVEL

K19 MLB DEVELOPMENT

IC,SGRAM,GDDR3,32Mx32,800MHZ,136 FBGA

333S0511

VRAM_512_SAMSUNG

CRITICAL

4

U8400,U8450,U8500,U8550

CRITICAL

U8400,U8450,U8500,U8550

4

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

VRAM_512_HYNIX

333S0506

FB_256_HYNIX

VRAM4,VRAM_256_HYNIX

K19_COMMON,DEVEL_BOM,EEE_6XS,CPU_3_06GHZ,FB_512_SAMSUNG

630-9969

PCBA,3.06GHZ,512SAM_VRAM,HB_AUDIO,K19

K19_COMMON,DEVEL_BOM,EEE_6XR,CPU_2_80GHZ,FB_512_HYNIX

630-9968

PCBA,2.80GHZ,512HYN_VRAM,HB_AUDIO,K19

K19_COMMON,DEVEL_BOM,EEE_6XQ,CPU_2_80GHZ,FB_512_SAMSUNG

PCBA,2.80GHZ,512SAM_VRAM,HB_AUDIO,K19

630-9967

K19_COMMON,DEVEL_BOM,EEE_6XP,CPU_2_66GHZ,FB_256_HYNIX

PCBA,2.66GHZ,256HYN_VRAM,HB_AUDIO,K19

630-9966

K19_COMMON,DEVEL_BOM,EEE_6XN,CPU_2_66GHZ,FB_256_SAMSUNG

630-9965

PCBA,2.66GHZ,256SAM_VRAM,HB_AUDIO,K19

A.0.0

SYNC_DATE=12/18/2008

SYNC_MASTER=DDR

051-7892

97

5

BOM Configuration

IN

B1

OE*

VCCB

B2 B3 B4

GND

A4

A3

A2

A1

VCCA

OUT

GND

VCC

NCNC

YA

NC NC

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

or via level translator

U8000

GMUX CPLD Programming Port

TDO

From XDP connector

GPU

U9200

GMUX

MCP

U1400

From XDP connector

U1000

CPU

To XDP connector and/or level translator

XDP connector

TMS

TCK

TDI

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

6

10 13 88

JTAG_ALLDEV

NLSV4T244

UQFN

11

1

12

6

7

8

9

10

5

4

3

2

U0600

0.1UF

20%

402

10V CERM

JTAG_ALLDEV

2

1

C0601

JTAG_ALLDEV

402

CERM

10V

20%

0.1UF

2

1

C0602

402

MF-LF

1/16W

10K

5%

JTAG_ALLDEV

2

1

R0601

NOSTUFF

402

MF-LF

5%

1/16W

0

2

1

R0602

13

M-RT-SM

CRITICAL

1909782

GMUX_JTAG

6

5

4

3

2

1

8

7

J0600

PLACEMENT_NOTE=Place near pin U1000.AB3

XDP

0

5% 1/16W MF-LF

402

21

R0603

0

1/16W MF-LF

5%

402

XDP

PLACEMENT_NOTE=Place near pin U1400.F19

21

R0604

SOT886

74LVC1G07

PLACEMENT_NOTE=Place close to U0600

4

6

5

1

3

2

U0601

PLACEMENT_NOTE=Place close to U8000

402

10K

1/16W MF-LF

5%

NOSTUFF

21

R0605

402

MF-LF

1/16W

5%

10K

2

1

R0606

5%

MF-LF

1/16W

0

402

21

R0607

6

10 13 88

6

10 13 88

13

JTAG Scan Chain

SYNC_DATE=07/22/2008

SYNC_MASTER=DDR

6

97

A.0.0

051-7892

XDP_TDO

JTAG_GMUX_TDO

PP3V3_S0

XDP_TRST_L

XDP_TDO_CONN

XDP_TDI

XDP_TCK

XDP_TRST_L

PP3V3_S0GPU

GPU_JTAG_TMS

JTAG_MCP_TDO_CONN

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

JTAG_MCP_TCK

GPU_JTAG_TMS

JTAG_GMUX_TCK

XDP_TCK

JTAG_MCP_TRST_L

MAKE_BASE=TRUE

PPCPUVTT_S0

JTAG_GMUX_TDI

JTAG_GMUX_TMS

JTAG_MCP_TRST_L

JTAG_LVL_TRANS_EN_L

XDP_TMS

PP3V3_S0

JTAG_MCP_TMS

XDP_TMS

GPU_JTAG_TDI

JTAG_MCP_TDO

JTAG_MCP_TDI

MAKE_BASE=TRUE

JTAG_MCP_TCK

10 88

9

17 84

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6

10 13 88

8

69 70 76 77 79 81

6

76

6

76

6

76

6

13 21 76

6

76

84

6

10 13 88

6

13 21 76

7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

9

19 84

9

19 84

6

13 21 76

6

10 13 88

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

13 21

76

21

13 21

6

13 21 76

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Batt Signal Connector

Keyboard Connector

FUNC_TEST

Power Nets

Functional Test Points

DC Power Connector

3 TPs

SATA ODD Connectors

FUNC_TEST

LVDS Connector

2 TPs

5 TPs

FUNC_TEST

Fan Connectors

FUNC_TEST

3 TPs

ICT Test Points

NO_TEST

FUNC_TEST

KBD Backlight Conn.

SD Card Connector

NO_TEST properties are also on page9,26,43,50

Note.

3 TPs

6 TPs

5 TPs

FUNC_TEST

2 TPs

FUNC_TEST

6 TPs

Speaker Connectors

FUNC_TEST

4 TPs

3 TPs

IPD Flex Connector

6 TPs

4 TPs

FUNC_TEST

2 TPs

FUNC_TEST

3 TPs

FUNC_TEST

3 TPs

FUNC_TEST

SATA HDD Connector

FUNC_TEST

6 TPs

3 TPs

Battery Connector

2 TPs

NO_TEST

FUNC_TEST

10 TPs

Airport/BT/Camera Conn.

SYNC_DATE=N/A

SYNC_MASTER=N/A

Functional / ICT Test

7

97

A.0.0

051-7892

PPVOUT_S0_LCDBKLT

TRUE

FSB_ADS_L

TRUE

NC_ENET_PWRDWN_L

MAKE_BASE=TRUE

TRUE

NC_ENET_INTR_L

MAKE_BASE=TRUE

NC_USB_10P

TRUE

FAN_RT_PWM

PCIE_MINI_D2R_P

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PP3V3_S3_BT_F

TRUE

PP5V_S3_BTCAMERA_F

TRUE

PP5V_WLAN

TRUE

MINI_RESET_CONN_L

TRUE

MINI_CLKREQ_Q_L

TRUE

PCIE_CLK100M_MINI_CONN_N

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

PCIE_MINI_R2D_P

BKL_ISEN3

TRUE

BKL_ISEN1

TRUE

KBDLED_ANODE

WS_KBD20

TRUE

PCIE_WAKE_L

TRUE

PCIE_MINI_R2D_N

TRUE

PCIE_MINI_D2R_N

TRUE

WS_KBD21

TRUE

WS_KBD_ONOFF_L

TRUE

WS_CONTROL_KBD

TRUE

FSB_LOCK_L

TRUE

FSB_DSTB_L_P<3..0>

FSB_DINV_L<3..0>

TRUE

FSB_ADSTB_L<1..0>

NC_SB_A20GATE

NC_SATA_D_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RP

TRUE

MAKE_BASE=TRUE

NC_SB_A20GATE

FSB_DSTB_L_N<3..0>

TRUE

USB_BT_N

TRUE

USB_BT_P

TRUE

USB_CAMERA_N

TRUE

USB_CAMERA_P

TRUE TRUE

SATA_ODD_D2R_UF_N

NC_PCIE_CLK100M_PE6P

NC_PCIE_PE4_D2RN

NC_PCIE_PE4_R2D_CN

NC_PE4_PRSNT_L

NC_PCI_INTZ_L

NC_PCI_GNT1_L

NC_PCI_CLK0

NC_USB_10P

NC_AUD_LO1_N_L

NC_ENET_PWRDWN_L

NC_MEM_A_CLK2N

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK3P

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK4P

TRUE

PP3V3_S0

TRUE

PP3V3_S3

PP1V8R1V5_S3

TRUE

LED_RETURN_1

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PICKB_L

PP5V_S3_IR_R

TRUE

SATA_HDD_D2R_C_P

TRUE

IR_RX_OUT

SATA_ODD_D2R_UF_P

TRUE

DP_ML_C_P<3..0>

TRUE

FSB_HIT_L

FSB_D_L<63..0>

TRUE

PPVBAT_G3H_CONN

SMC_ODD_DETECT

TRUE

SATA_ODD_R2D_N

TRUE

PP18V5_DCIN_FUSE

TRUE

SMBUS_SMC_BSA_SCL

WS_KBD19

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMC_KDBLED_PRESENT_L

KBDLED_ANODE

TRUE

SYS_LED_ANODE_R

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_R2D_P

TRUE

PP5V_S0_HDD_FLT

TRUE

USB_CAMERA_CONN_N

TRUE

CONN_USB2_BT_P

TRUE

USB_CAMERA_CONN_P

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD16_NUM

WS_KBD12

TRUE

SATA_ODD_D2R_C_N

PP5V_SW_ODD

TRUE

SPKRCONN_S_OUT_P

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_L_OUT_N

BI_MIC_HI

TRUE

SPKRCONN_L_OUT_P

TRUE

BI_MIC_LO

TRUE

BI_MIC_SHIELD

TRUE

SD_WP

TRUE

SD_CD_L

SD_CMD

TRUE TRUE

SD_CLK

TRUE

SD_D<7..0>

TRUE

PSOC_F_CS_L

TRUE

SMBUS_SMC_A_S3_SCL

PSOC_MOSI

TRUE TRUE

PSOC_SCLK

PSOC_MISO

TRUE

Z2_KEY_ACT_L

TRUE TRUE

Z2_RESET

Z2_CLKIN

TRUE

Z2_HOST_INTN

TRUE

Z2_SCLK

TRUE

Z2_MISO

Z2_MOSI

TRUE

Z2_DEBUG3

TRUE

Z2_CS_L

PP18V5_S3

TRUE

PP3V3_S3_LDO

TRUE

BKL_ISEN6

BKL_ISEN5

TRUE

LED_RETURN_6

TRUE

LED_RETURN_4

TRUE

LED_RETURN_3

LED_RETURN_2

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_DATA_P<1>

TRUE

LVDS_CONN_A_CLK_F_P

TRUE

PPVOUT_S0_LCDBKLT

TRUE

PP3V3_SW_LCD

TRUE

SATA_ODD_D2R_C_P

Z2_BOOST_EN

TRUE

WS_KBD10

TRUE

PP3V42_G3H

TRUE

SMC_BIL_BUTTON_L

TRUE

PP18V5_S3

TRUE

WS_KBD6

TRUE

FSB_HITM_L

FSB_A_L<31..3>

TRUE

BKL_ISEN2

TRUE

LED_RETURN_5

TRUE

CONN_USB2_BT_N

SPKRCONN_S_OUT_N

TRUE

SATA_ODD_R2D_P

TRUE

WS_KBD15_CAP

TRUE

PP3V42_G3H

TRUE

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3..0>TP_PCI_C_BE_L<3..0>

TRUE

NC_PCI_CLK0

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK1

MAKE_BASE=TRUE

NC_PCI_CLK1

TRUE

NC_PCI_DEVSEL_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCI_FRAME_LNC_PCI_FRAME_L

TRUE

NC_PCI_GNT0_L

MAKE_BASE=TRUE

NC_PCI_GNT0_L

TRUE

NC_PCI_GNT1_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCI_INTW_LNC_PCI_INTW_L

TRUE

NC_PCI_INTX_L

MAKE_BASE=TRUE

NC_PCI_INTX_L

TRUE

NC_PCI_INTZ_L

MAKE_BASE=TRUE

TRUE

NC_PCI_IRDY_L

MAKE_BASE=TRUE

NC_PCI_IRDY_L

TRUE

MAKE_BASE=TRUE

NC_PCI_PERR_LNC_PCI_PERR_L

TRUE

NC_PCI_RESET1_L

MAKE_BASE=TRUE

NC_PCI_RESET1_L

TRUE

NC_PCI_SERR_L

MAKE_BASE=TRUE

NC_PCI_SERR_L

TRUE

NC_PCI_STOP_L

MAKE_BASE=TRUE

NC_PCI_STOP_L

TRUE

NC_PCI_TRDY_L

MAKE_BASE=TRUE

NC_PCI_TRDY_L

TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

TRUE

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5P

TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE4_D2RN

MAKE_BASE=TRUE

TRUE

NC_PE4_PRSNT_L

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

NC_PSOC_P1_3

TRUE

NC_PSOC_SDA

MAKE_BASE=TRUE

NC_PSOC_SDA

TRUE

NC_SATA_C_D2RP

MAKE_BASE=TRUE

NC_SATA_C_D2RP

TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CPNC_SATA_C_R2D_CP NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

NC_AUD_LO1_N_L

TRUE

MAKE_BASE=TRUE

NC_AUD_LO1_P_L

TRUE

MAKE_BASE=TRUE

NC_AUD_LO1_P_L

TRUE

MAKE_BASE=TRUE

NC_USB_10NNC_USB_10N

NC_ENET_INTR_L

TRUE

MAKE_BASE=TRUE

NC_LPC_DRQ0_LNC_LPC_DRQ0_L

NC_MEM_A_CKE<3..2>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK2N

NC_MEM_A_CLK3N

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK3N

NC_MEM_A_CLK4P

NC_MEM_A_CLK3P

TRUE

NC_MEM_A_CS_L<3>

MAKE_BASE=TRUE

NC_MEM_A_CS_L<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_ODT<3..2>TP_MEM_A_ODT<3..2>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CKE<2>NC_MEM_B_CKE<2>

TRUE

NC_MEM_B_CLK3P

MAKE_BASE=TRUE

NC_MEM_B_CLK3P

TRUE

NC_MEM_B_CLK4N

MAKE_BASE=TRUE

NC_MEM_B_CLK4N

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK4PNC_MEM_B_CLK4P

TRUE

NC_MEM_B_ODT<2>

MAKE_BASE=TRUE

NC_MEM_B_ODT<2>

TRUE

NC_MEM_B_CLK5N

MAKE_BASE=TRUE

NC_MEM_B_CLK5N

TRUE

MAKE_BASE=TRUE

NC_MLB_RAM_SIZENC_MLB_RAM_SIZE

TRUE

NC_P7_7

MAKE_BASE=TRUE

NC_P7_7

NC_PCI_AD<31..8>

MAKE_BASE=TRUE

TRUE

TP_PCI_AD<31..8>

NC_PCI_DEVSEL_L

WS_KBD22

TRUE

PP3V3_S0

TRUE

SATA_HDD_R2D_N

BKL_ISEN4

TRUE

LVDS_CONN_B_CLK_F_N

TRUE

LVDS_CONN_B_DATA_N<1>

TRUE

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_B_DATA_N<0>

TRUE

LVDS_CONN_A_DATA_N<2>

WS_KBD1

TRUE

WS_LEFT_OPTION_KBD

WS_KBD23

TRUE

LVDS_DDC_DATA

TRUE TRUE

LVDS_CONN_A_DATA_N<0>

TRUE

LVDS_CONN_A_DATA_P<0> LVDS_CONN_A_DATA_N<1>

TRUE TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_CONN_B_DATA_N<2>

TRUE

ADAPTER_SENSE

TP_MEM_A_CKE<3..2>

LVDS_DDC_CLK

TRUE

FAN_RT_TACH

FAN_LT_TACH

TRUE

FAN_LT_PWM

TRUE

WS_KBD13

TRUE

SMC_LID_R

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SDA

TRUE

WS_KBD5

TRUE

WS_KBD3

WS_KBD2

TRUE

WS_KBD8

TRUE

WS_KBD14

TRUE

GND

PP3V42_G3H

TRUE

PP3V3_S3

TRUE

WS_KBD9

TRUE

PPVCORE_S0_MCP_REG

TRUE

PP1V8R1V5_S0_FET

TRUE TRUE

PP1V8_S0

PP1V2R1V05_S5

TRUE

PPCPUVTT_S0

TRUE

PP0V9R0V75_S0_DDRVTT

TRUE

PPVCORE_S0_CPU

TRUE

WS_KBD11

TRUE

WS_KBD7

WS_KBD4

TRUE

WS_LEFT_SHIFT_KBD

TRUE

PP1V05_S0_MCP_PLL_UF PP5V_SW_ODD

TRUE

PP5V_S0_HDD_FLT

TRUE TRUE

BKL_VLDO

TRUE

PP5V_S3

TRUE

PP1V2R1V05_ENET

TRUE

PP3V3_ENET_PHY

TRUE

PPBUS_G3H

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V3_S3_LDO

PP4V5_AUDIO_ANALOG

TRUE TRUE

SMC_PM_G2_EN

TRUE

PM_SLP_S4_L

TRUE

PM_SLP_S3_L

TRUE

PP5V_S0

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

7

53 80 85

10 14 88

7

18

7

18

7

20

49

17 31 90

7

31 42 45 51 94

7

31 42 45 51 94

31

31 96

31 90 96

85

7

51

50

17 31

31 90 96

17 31 90

50

10 14 88

7

21

7

20

7

20

7

21

10 14 88

20 31 91

39 96

7

17

7

17

7

17

7

17

7

19

7

19

7

19

7

20

7

55

7

18

7

15

7

16

7

16

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

21 27 31 32 45 50 52 70

8 28 29 30 65 70

80 85

7

31 42 45 51 94

50 51

39

39 90

39 41

39 96

82 95

10 14 88

61 62

39 42

39 90

61

7

42 45 61 62 94

50

7

42 45 61 62 94

51

7

51

39

39 90

7

39

31 96

50

39 90

7

39 53

58 59 96

59 60

58 59 96

59 60

32

32 93

50 51

7

31 42 45 51 94

50 51

7

51

7

51

85

80 85

80 95

80 81 95

80 95

7

53 80 85

80

39 90

51

50

7 8

21

22 26

40 42

43

44

45 46 50 61 62 64 69

42 43 61

7

51

50

10 14 88

85

80 85

31 96

58 59 96

39 90

50

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

19

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

17

7

50

7

50

7

50

7

50

7

20

7

20

7

20

7

20

7

20

7

20

7

20

7

20

7

55

7

55

7

55

7

20

7

20

7

18

7

19

7

19

16

7

15

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

16

7

21

7

21

7

50

7

50

19

7

19

50

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

39 90

85

80 95

80 81 95

50

80 81

80 81 95

80 95

80 81 95

61

80 81

49

50

61

7

42 45 61 62 94

61

7

42 45 61 62 94

50

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 27 31 32 45 50 52 70

50

8

22 24 46 66

8

11 12 16 24 28 29 39 68 69 70

8

18 25 55 69 70 84 87

8

22 24 34 68

6 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

8

28 29 65 70

8

11 12 46 63

50

8

24 68

7

39 53

7

39

85

8 9

31 39 40 41 43 51 53 55 64

65 70 79

8

18 24 33 34 37

8

18 24 33 34

8

37 46 61 62 64 65 66 67 79 83

86

8

18 20 22 24 26 30 34 37 38 44

54 64 68 69 70 82 87 96

42 43

7

51

55

42 64 69

21 40 42 43 69 70

21 34 37 42 69 82 84

8

39 44

49 51 63

66 67 70

83 85

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"G3Hot" (Always-Present) Rails

241 mA max load

5V Rails

Chipset "VCore" Rails

4500 mA

"FW" (FireWire) Rails

190 mA

OR 0.75V

500 mA max supply

4771 mA

130 mA

1.8V/DDR 1.5V Rails

6600 MA

139 mA/ 0 mA

105 mA/241 mA

"GPU" Rails

500 mA

ENET Rails

1034 mA

1182 mA

3.3V-2.5V Rails

SYNC_MASTER=(MASTER)

Power Aliases

051-7892

A.0.0

97

8

SYNC_DATE=(MASTER)

PP1V1_S0GPU_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS_R

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPVCORE_GPU

MAKE_BASE=TRUE

PP1V8_GPUIFPX

MIN_NECK_WIDTH=0.2 mm

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0GPU_ISNS

VOLTAGE=1.05V

PP1V2R1V05_S5

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPVCORE_S0_CPU

PP5V_S0

PP5V_S0 PP5V_S0

PP5V_S0

VOLTAGE=5V

PP5V_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

PP3V3_S3

MIN_LINE_WIDTH=0.40MM

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

PPBUS_CPU_IMVP_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S5

PP1V8R1V5_S3 PP1V8R1V5_S3

MIN_LINE_WIDTH=0.8 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V8R1V5_S3

PP1V8R1V5_S0_FET

PPCPUVTT_S0

PP1V2R1V05_S5

PP3V3_S0

PP3V3_S3

PP5V_S3

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

PPBUS_CPU_IMVP_ISNS

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=16.5V

PPDCIN_G3H

PP3V42_G3H

PP5V_S3

PP5V_S3 PP5V_S3

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

PP1V1_S0GPU_REG

MAKE_BASE=TRUE

VOLTAGE=1.1V

PP1V1_S0GPU_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8R1V5_S0_FET

MAKE_BASE=TRUE

VOLTAGE=1.05V

PPCPUVTT_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0_MCP_SATA_AVDD

PP1V05_S0_MCP_PEX_AVDD PPCPUVTT_S0

PP1V1_S0GPU_REG

PP0V9R0V75_S0_DDRVTT

PP1V8R1V5_S0_FET

PP1V8R1V5_S3

PP3V3_S5

PP1V8R1V5_S0_FET

PPCPUVTT_S0

PP1V2R1V05_ENET

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_ENET_PHY

PPCPUVTT_S0

PPCPUVTT_S0 PPCPUVTT_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V

PP1V2R1V05_ENET

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PPCPUVTT_S0

PP5V_S3

PP3V3_FW_FWPHY

PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PEX_AVDD

PP3V3_S0

PP1V2_S0

PP1V2R1V05_ENET

PP3V3_ENET_PHY

PP1V2R1V05_ENET

PP3V3_ENET_PHY

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP1V2_S0

PP3V3_S0

PP1V2R1V05_ENET

PPBUS_G3H

PPDCIN_G3H

PP3V42_G3H

PP5V_S3

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8_S0GPU_ISNS_R

PP1V8_GPUIFPX

PP3V3_S0GPU

PPVTTDDR_S3

PP1V2R1V05_ENET

PPBUS_CPU_IMVP_ISNS

PP3V3_S5

PP1V8_S0

PP3V3_S0

PP1V05_S0_MCP_PLL_UF

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

PP5V_S3

PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS

PP1V8R1V5_S3

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

PP1V8_S0

PP1V8R1V5_S0_FET

PP1V1_S0GPU_REG

PP1V8_S0GPU_ISNS

PPVCORE_GPU

PPVP_FW

PP1V1_S0GPU_REG

PP3V3_S5

PP1V2R1V05_S5

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

PPVCORE_S0_MCP_REG

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V

PPVCORE_S0_CPU

PPVCORE_S0_MCP_REG

PP3V3_S0

PPBUS_G3H

PP5V_S3

PPDCIN_G3H

PP3V42_G3H

PPCPUVTT_S0

PP3V3_S0

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 mm

PP3V3_S5 PP3V3_S5

PPVP_FW

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPVP_FW

PP1V0_FW

PP3V3_FW_FWPHY

PP1V0_FW

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM VOLTAGE=1.8V

PP1V8_S0

PP3V3_S0

PPBUS_G3H

PP3V3_S5

PPBUS_G3H

PPVCORE_GPU

PP1V1_S0GPU_REG

PP3V3_S0GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM VOLTAGE=3.3V

PP3V3_S0GPU

PP3V3_S0

PP3V42_G3H

PP0V9R0V75_S0_DDRVTT

PP1V2R1V05_S5

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S5

PP3V42_G3H

PP5V_S3

PP3V3_S0

PPBUS_G3H

PP3V3_S0

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

PP1V2_S0

PP3V3_S0

PP3V3_S5

PP3V3_S0

PPCPUVTT_S0

PP1V8_S0

PP1V8R1V5_S3 PP1V8R1V5_S3

PP3V42_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.42V

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

PP5V_S3

MAKE_BASE=TRUE

VOLTAGE=0.9V

PP0V9R0V75_S0_DDRVTT

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=2 mm

PP0V9R0V75_S0_DDRVTT

PP3V3_S0

PP5V_S3

VOLTAGE=5.0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.17MM

PP3V3_S0GPU

PP3V3_S5

PP3V3_S3

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

PP3V3_S3

PP3V3_S5

PP1V8R1V5_S0_FET

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.17mm

MIN_LINE_WIDTH=0.6mm

PP3V3_S5

8

71 73 76 78 83

8

70 78

8

47 83

8

46 72 79

8

70 78

8 9

47 72 73 74 75

8 9

47 72 73 74 75

7 8

22 24 34 68

7 8

11 12 46 63

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85 7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51

63 66 67

70 83 85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

39 44 49 51 63 66 67 70 83

85

7 8

21 27 31 32 45 50 52 70

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

8

46 63

7 8

18 20 22

24 26 30 34 37 38 44 54 64 68

69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

28 29 30 65 70

7 8

28 29 30 65 70

7 8

28 29 30 65 70

7 8

11 12 16 24 28

29 39 68 69 70

7 8

11 12 16 24 28 29 39 68 69

70

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

7 8

22 24 34 68

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

21 27 31 32

45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31

32 45 50 52 70

7 8

21 27 31 32 45

50 52 70

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

37 46 61 62 64 65 66 67 79

83 86

8

46 63

8

61 62

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79 7 8 9

31 39 40 41 43 51 53 55

64 65 70 79 7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8

37 46 61

62 64 65 66 67 79 83 86

7 8

37 46 61 62 64 65 66 67 79

83 86

8

71 73 76 78 83

8

71 73 76 78 83

8

71 73 76 78 83

8

71 73 76 78 83

7 8

11 12 16 24 28 29 39 68 69

70

6 7 8 9

10 11 12

13 14 17 18 20 22 24 25 63 67

8

20 24

8

17 24

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

8

71 73 76 78 83

7 8

28 29 65 70

7 8

28 29 65 70

7 8

11 12 16 24 28 29 39 68 69

70

7 8

28 29 30 65 70

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

11 12 16 24 28

29 39 68 69 70

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

7 8

18 24 33 34 37

7 8

18 24 33 34

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67 6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

8

27 65

7 8

18 24 33 34 37

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

8

36 37 38

8

36 37 38

8

17 24

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18

19 21 22 24

25 28 29 37 39 43 45 47 48 49

51 55

59 60 63 68 69 70 77 80 81

82 84

85 96

8

84 87

7 8

18 24 33 34 37

7 8

18 24 33 34

7 8

18 24 33 34 37

7 8

18 24 33 34

7 8

18 24 33 34

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7

8

13 18 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77

80 81 82 84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7

8

13 18 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77

80 81 82 84

85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19

21 22 24 25 28 29 37 39 43 45

47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

8

84 87

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

18 24 33 34 37

7 8

37 46 61 62 64 65 66 67 79

83 86 7 8

37 46 61 62 64 65 66 67 79

83 86

8

61 62

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 7 8

13 18 19 21 22 24 25 28

29 37 39

43 45 47 48 49 51 55 59 60 63

68 69 70

77 80 81 82 84 85 96

8

47 83

8

47 83

8

70 78

6 8

69 70 76 77 79 81

8

27 65

7 8

18 24 33 34 37

8

46 63

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 25 55 69 70 84 87

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45

47 48 49 51 55 59 60 63 68 69

70 77

80 81 82 84 85 96

7 8

24 68

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

8 9

47 72 73 74 75

8 9

47 72 73 74 75

7 8

28 29 30 65 70

8

20 24

7 8

18 25 55 69 70 84 87

7 8

18 25 55 69 70 84 87

7 8

11 12 16 24 28 29 39 68

69 70

8

71 73 76 78 83

8 9

47 72 73 74 75

8 9

47 72 73 74 75

8

46 72 79

8 37 38

8

37 38

8

71 73 76 78 83

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

22 24 34 68

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

22 24 46 66

7 8

11

12 46 63

7 8

22 24 46 66

7 8

22

24 46 66

6 7 8

13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49

51 55 59 60 63 68 69 70 77 80

81

82 84 85 96

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8 9

31

39 40 41

43 51 53

55 64 65

70 79

8

61 62

7 8

21 22 26

40 42

43 44

45 46

50 61

62 64

69

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

11 12 46 63

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96 7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

8

37 38

8

37 38

8

36 37

8

36 37 38

8

36 37

8

36 37

7 8

18 25 55 69 70 84 87

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19

21 22 24 25 28 29 37 39 43 45

47 48 49 51 55 59 60 63 68 69

70 77 80 81 82 84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

37 46 61 62 64 65 66 67 79

83 86

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24

26

30 34 37 38 44 54 64 68 69 70

82 87 96

7 8

37 46 61 62 64 65 66 67 79

83 86

8

46 72 79

8

71 73 76 78 83

8

71 73 76 78 83

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

28 29 65 70

7 8

22 24 34 68

8

36 37 38

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 7

8

13 18 19 21 22 24 25 28 29

37

39 43 45 47 48 49 51 55 59 60

63

68 69 70 77 80 81

82

84

85 96

7 8

37 46 61 62 64 65 66 67 79

83 86

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

8

84 87

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87

96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

18 25 55 69 70 84 87

7 8

28 29 30 65 70

7 8

28

29 30 65 70

7 8

21 22 26 40

42 43 44 45 46 50 61 62 64 69

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

37

46 61 62

64 65 66

67 79 83

86

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8

28 29 65 70

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

21 27 31 32

45

50 52 70

7 8

21 27 31 32 45 50 52 70

8

17 24

7 8

21 27 31 32 45 50 52 70

7 8

21 27 31 32 45 50 52 70

7 8

18 20 22 24

26

30 34 37 38 44 54 64 68 69 70

82 87 96

7 8

11 12 16 24 28 29 39 68 69

70

7 8

11 12 16 24 28 29 39 68 69

70

7 8

11 12 16 24 28 29 39 68 69

70

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TM Hole

MCP79 PCIe PRSNT# Straps

GPU signals

These need work. Add other PRSNT# straps if needed. .

CPU signals

TM Hole

Top GPU Right

TM Hole

Right CPU

Left CPU

ETHERNET ALIASES

Bosses

TOP MCP LEFT

TM Hole

Exist in MRB but not Intel designs. Here for CYA.

Frame Holes

Thermal Module Holes

If found to be necessary, will move to page14.csa

Extra FSB Pull-ups

Digital Ground

GMUX ALIASES

UNUSED EXPRESS CARD LANE

AUDIO ALIASES

3R2P5

1

ZT0940

1/16W

5%

402

MF-LF

47K

2

1

R0930

MF-LF

0

1/16W

5%

NO STUFF

402

21

R0925

17 37

SM

2 1

XW0901

1/16W MF-LF

10

1%

402

21

R0900

MF-LF

1/16W

1%

10

402

21

R0901

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0983

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0984

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0985

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0986

SL-3.1X2.7-6CIR-NSP

TH

1

ZT0950

3R2P5

1

ZT0960

3R2P5

1

ZT0990

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

1/16W

5%

MF-LF

0

402

21

R0926

17

84

NO STUFF

1/16W

5%

MF-LF

0

402

21

R0927

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0930

10 14 88

10 13 14 88

10 14 88

10 14 63 88

MF-LF

NO STUFF

1/16W

5%

402

62

2

1

R0960

220

NO STUFF

1/16W

5%

402

MF-LF

2

1

R0950

200

1/16W

5%

402

MF-LF

NO STUFF

2

1

R0970

402

150

NO STUFF

1/16W

1% MF-LF

2

1

R0980

150

1/16W

NO STUFF

MF-LF

402

1%

2

1

R0990

STDOFF-4.0OD3.0H-TH

1

ZT0934

STDOFF-4.0OD3.0H-TH

1

ZT0935

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0910

MF-LF

5%

1/16W

0

402

21

R0903

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0912

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0911

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0913

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0902

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0900

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0903

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0916

3R2P5

1

ZT0915

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0980

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0987

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0901

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0917

402

5%

22

1/16W MF-LF

2

1

R0931

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0914

4.0OD1.85H-M1.6X0.35

1

ZT0951

4.0OD1.5H-M1.6X0.35

1

ZT0952

4.0OD1.5H-M1.6X0.35

1

ZT0953

4.0OD1.85H-M1.6X0.35

1

ZT0954

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0904

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

051-7892

A.0.0

97

9

Signal Aliases

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

FW_PLUG_DET_L

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

NC_USB_EXTCN

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_MEM_B_A<15>

SMC_MCP_SAFE_MODE

USB_CARDREADER_N

NC_USB_EXCARDN

TP_MEM_B_A<15>

NC_USB_EXTCP

MAKE_BASE=TRUE

MCP_MII_PD MCP_MII_PD

GND

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

PM_SLP_RMGT_L

GND

PM_SLP_RMGT_L

TP_PCIE_CLK100M_EXCARD_P

TP_PCIE_EXCARD_D2R_N

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

FW_PLUG_DET_L

NC_USB_EXCARDP

NC_USB_EXTDP

NC_USB_MININ

USB_CARDREADER_P

NC_USB_EXTCN

TP_PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

TP_EXCARD_CLKREQ_L

MAKE_BASE=TRUE

TP_PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_N

DP_IG_HPD

GND

GPU_FB_B_VREF_DIV

DP_IG_ML_N<3>

MAKE_BASE=TRUE

PPCPUVTT_S0

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

GPU_FB_B_VREF_DIV

FSB_CPURST_L CPU_INTR CPU_NMI

CPU_DPRSTP_L

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<0..2>

FW643_WAKE_L

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_PRSNT_L

TP_PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_N

TP_EXCARD_CLKREQ_L

TP_PCIE_CLK100M_EXCARD_N

GND

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

NO_TEST=TRUE

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

PM_SLP_RMGT_L

PP5V_S3

PP5V_S3_AUDIO_AMP

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

RTL8211_CLK125

MAKE_BASE=TRUE

DP_IG_DDC_DATA

GND

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

GND

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

LCD_BKLT_EN

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

NC_USB_MINIP

NO_TEST=TRUE

USB_CARDREADER_P

MAKE_BASE=TRUE

NC_USB_MININ

NO_TEST=TRUE

GMUX_INT

MAKE_BASE=TRUE

NC_USB_EXTDP

NO_TEST=TRUE

TP_MEM_A_A<15>

JTAG_GMUX_TDI

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

NC_USB_EXTDN

NO_TEST=TRUE

NC_USB_EXTDN

MCP_MII_PD MCP_MII_PD

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

MCP_SPKR

MAKE_BASE=TRUE

GMUX_INT

GND

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

DP_IG_DDC_CLK

DP_IG_HPD

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

=MCP_HDMI_TXC_N

DP_IG_DDC_CLK

DP_IG_ML_P<2..0>

MAKE_BASE=TRUE

=MCP_HDMI_TXD_P<0..2>

TP_LVDS_MUX_SEL_EG

EG_RESET_L

MAKE_BASE=TRUE

EG_RESET_L

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

USB_CARDREADER_N

MAKE_BASE=TRUE

NC_USB_EXCARDP

NO_TEST=TRUE

NC_USB_MINIP

MAKE_BASE=TRUE

NC_USB_EXCARDN

NO_TEST=TRUE

=PEG_D2R_N<0..15> =PEG_R2D_C_P<0..15>

=PEG_D2R_P<0..15>

=PEG_R2D_C_N<0..15>

MEM_VTT_EN

TP_IMVP6_CLKEN_L

MAKE_BASE=TRUE

TP_IMVP6_CLKEN_L

CPU_VID<0..6>

MAKE_BASE=TRUE

CPU_BSEL<0..2>

MAKE_BASE=TRUE

MEM_VTT_EN

=MCP_BSEL<0..2>

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

DP_IG_ML_P<3>

MAKE_BASE=TRUE

IMVP6_VID<0..6>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXTCP

MAKE_BASE=TRUE

TP_MEM_A_A<15>

PM_ALL_GPU_PGOOD

EG_CLKREQ_OUT_L

PEG_PRSNT_L

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

MAKE_BASE=TRUE

JTAG_GMUX_TDO

JTAG_GMUX_TMS

MAKE_BASE=TRUE

JTAG_GMUX_TDI

TP_CPU_PECI_MCP

JTAG_GMUX_TDO

FW643_WAKE_L

MAKE_BASE=TRUE

GPU_FB_A_VREF_DIV

FSB_BREQ0_L

RTL8211_CLK125

MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS

JTAG_GMUX_TMS

DP_IG_DDC_DATA

NC_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_BKL_PWMNC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE

GND

NC_LVDS_IG_A_DATAP<3>

GND_CHASSIS_AUDIO_JACK

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.09MM

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

GND

9

19 37

71 90

9

14

9

20 91

9

29

42

9

20 32 96

9

20 91

9

29

9

20 91

9

18

9

18

9

33

9

21 34

9

21 34

9

17 90

9

17 90

9

17 90

9

19 37

9

20 91

9

20 91

9

20 91

9

20 32 96

9

20 91

9

17 90

9

17

9

17

9

17 90

9

18 81

9

27 75

81 90

6 7 8

10 11 12 13 14 17

18 20 22 24 25 63 67

9

18 90

9

27 75

9

18 90

9

18 90

18

9

36 37

9

17 90

9

17 90

9

17 90

9

17 90

9

17

9

17 90

9

17 90

9

17

9

17 90

9

33

9

33

9

21 34

7 8

31 39 40 41 43 51 53 55

64 65 70 79

58

9

33

9

18 77 81

9

27 74

71 90

9

84 86

9

18 84

9

20 91

9

20 32 96

9

20 91

9

18 84

9

20 91

9

28

6 9

19 84

9

18 84

9

20 91

9

20 91

9

18

9

18

9

18 84

9

18 84

21

9

18 84

9

69 83 84

9

18 77 81

9

18 81

9

84 86

18

9

18 77 81

81 90

18

9

84

9

71 84

9

71 84

9

84

9

20 32 96

9

20 91

9

20 91

9

20 91

17

9

26 65 70

9

63

9

63

11 88

10 88

9

26 65 70

14

71 90

81 90

63 88

9

20 91

9

28

9

69 83 84

81 90

6 9

17 84

6 9

19 84

6 9

19 84

9

14

6 9

17 84

9

36 37

9

27 74

8

47 72 73 74 75

6 9

19 84

9

18 77 81

9

18 90

9

18 90

9

18

9

18

9

18 90

9

18 90

9

18 90

9

18 90

59

9

18 90

9

18 90

9

18 90

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS

1/16W

1%

402

MF-LF

54.9

2

1

R1002

1/16W

5%

402

MF-LF

68

2

1

R1004

1/16W

1%

402

MF-LF

1K

2

1

R1005

1/16W

1%

402

MF-LF

2.0K

2

1

R1006

1/16W

1%

MF-LF

54.9

402

21

R1019

1/16W

1%

MF-LF

27.4

402

21

R1018

1/16W

1%

MF-LF

54.9

402

21

R1017

1/16W

1%

MF-LF

27.4

402

21

R1016

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

14 63 88

14 88

63

13 14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

88

9

88

9

88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

14 88

7

14 88

7

14 88

7

14 88

13 88

6

10 88

13 26

14 43 63 88

48 96

14 43 88

14 88

9

13 14 88

14 88

6

10 13 88

6

10 13 88

6

10 13 88

6

10 13 88

48 96

14 88

9

14 88

9

14 88

1/16W

5%

MF-LF

0

NOSTUFF

402

21

R1030

1/16W

5% MF-LF

1K

NOSTUFF

402

2

1

R1007

1/16W

1%

402

MF-LF

54.9

2

1

R1003

1/16W

1%

MF-LF

54.9

402

21

R1020

1/16W

1%

MF-LF

54.9

402

21

R1021

1/16W

1%

MF-LF

54.9

402

21

R1022

14 88

649

MF-LF

1/16W

1%

402

21

R1023

1/16W

5%

402

MF-LF

1K

NOSTUFF

2

1

R1012

16V

10% 402

X5R

0.1uF

NOSTUFF

2

1

C1000

1/16W

1%

MF-LF

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

402

21

R1024

FCBGA

PENRYN

OMIT

AB6

G2

AB5

C7

B25

A24

AB3

AA6

AC5

D5

A3

D3

D22

D2

F6

B2

V3

T2

N5

M4

G3

F4

F3

C1

L1

J3

K2

H2

K3

D21

AC1

AC2

H4

B4

C6

B3

C4

D20

E4

G6

A5

F21

H5

E1

C20

F1

G5

AC4

AD1

AD3

AD4

E2

A21

A22

V1

M1

H1

J1

N2

M3

K5

L4

L5

AA3

AB2

AA4

W3

V4

U2

J4

Y4

W5

W2

T3

T5

R4

U1

Y5

U4

A6

W6

R3

U5

Y2

R1

P1

P4

L2

P2

P5

N3

U1000

FCBGA

PENRYN

OMIT

C3

A26

AF1

AF26

C24

D25

C23

D7

D6

AE6

AD26

AF24

AA26

M26

H26

AE25

Y26

L26

J26

D24

B5

E5

AC20

U22

N24

H25

G24

K24

E23

AC23

AF22

AD23

AC22

E25

AD21

AE21

AC25

AF23

AE22

AD20

AC26

AB21

AB22

AA21

G25

AD24

AE24

AB25

AA24

AA23

W25

W24

Y23

W22

Y25

F23

U23

U25

T22

V23

V26

V24

AB24

Y22

N25

T25

G22

L25

R24

T24

P22

P23

P25

M23

L22

M24

L23

E26

R23

P26

K25

N22

H23

K22

F26

H22

J23

J24

F24

E22

Y1

AA1

U26

R26

C21

B23

B22

U1000

SYNC_DATE=11/12/2008

SYNC_MASTER=M98_MLB

97

051-7892

A.0.0

10

CPU FSB

FSB_A_L<14>

FSB_A_L<16>

FSB_A_L<18>

FSB_A_L<25>

PPCPUVTT_S0

TP_CPU_TEST6 TP_CPU_TEST7

CPU_TEST2

FSB_DSTB_L_P<1> FSB_DINV_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<25>

FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14>

FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<0>

FSB_D_L<32> FSB_D_L<1> FSB_D_L<2>

FSB_D_L<5>

FSB_D_L<16>

FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_DSTB_L_N<1>

CPU_GTLREF

TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

FSB_D_L<33>

FSB_D_L<34>

FSB_D_L<35>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<38>

FSB_D_L<39>

FSB_D_L<40>

FSB_D_L<41>

FSB_D_L<42>

FSB_D_L<43>

FSB_D_L<44>

FSB_D_L<45>

FSB_D_L<46>

FSB_D_L<47>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<2>

FSB_D_L<48>

FSB_D_L<49>

FSB_D_L<50>

FSB_D_L<51>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<54>

FSB_D_L<55>

FSB_D_L<56>

FSB_D_L<57>

FSB_D_L<58>

FSB_D_L<59>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<62>

FSB_D_L<63>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<3>

CPU_COMP<0>

CPU_COMP<1>

CPU_COMP<2>

CPU_COMP<3>

CPU_DPRSTP_L

CPU_DPSLP_L

FSB_DPWR_L

CPU_PWRGD

FSB_CPUSLP_L

CPU_PSI_L

FSB_D_L<17>

FSB_D_L<4>

FSB_D_L<3>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<10>

CPU_TEST1

FSB_REQ_L<1>

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L<6>

FSB_A_L<3> FSB_A_L<4>

FSB_REQ_L<0>

FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD4

TP_CPU_RSVD3

TP_CPU_RSVD2

TP_CPU_RSVD1

TP_CPU_RSVD0

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<17>

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26> FSB_A_L<27>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

CPU_THERMD_N

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8

PPCPUVTT_S0

XDP_TRST_L

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TCK

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

27 88 88

88

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6

10 13 88

6

10 13 88

6

10 13 88

6

10 88

6

10 13 88

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TBD A (Enhanced Deeper Sleep)

17.0 A (Design Target)

Ultra Low Voltage:

Standard Voltage:

44.0 A (Design Target)

27.4 A (Auto-Halt/Stop-Grant HFM)

TBD A (Deep Sleep SuperLFM)

TBD A (Deep Sleep HFM) TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)

TBD A (Auto-Halt/Stop-Grant HFM) TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Deep Sleep HFM)

21.0 A (HFM)

TBD A (Sleep HFM)

9.4 A (Enhanced Deeper Sleep)

11.5 A (Deeper Sleep)

25.0 A (Deep Sleep HFM)

27.4 A (Sleep HFM)

25.5 A (SuperLFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)

TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deeper Sleep)

TBD A (Sleep SuperLFM)

TBD A (SuperLFM)

18.7 A (LFM)

23.0 A (Design Target)

Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

30.4 A (LFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

9

88

9

88

9

88

9

88

9

88

9

88

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

100

MF-LF 402

1% 1/16W

2

1

R1101

9

88

63 88

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

100

MF-LF 402

1% 1/16W

2

1

R1100

OMIT

PENRYN

FCBGA

AE7

AE2

AF3

AE3

AF4

AE5

AF5

AD6

AF7

N6

N21

M21

K21

J21

M6

K6

J6

W21

V21

T6

T21

R6

R21

V6

G21

C26

B26

AF20

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

B7

AE17

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

A20

AD12

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

A18

AC7

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

A17

AB9

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

A15

F20

F18

F17

F15

F14

F12

F10

F9

F7

E20

A13

E18

E17

E15

E13

E12

E10

E9

E7

D18

D17

A12

D15

D14

D12

D10

D9

C18

C17

C15

C13

C12

A10

C10

C9

B20

B18

B17

B15

B14

B12

B10

B9

A9

A7

U1000

OMIT

PENRYN

FCBGA

V25

V22

V5

V2

U24

U21

U6

U3

T26

T23

B8

T4

T1

R25

R22

R5

R2

P24

P21

P6

P3

B6

N26

N23

N4

N1

M25

M22

M5

M2

L24

L21

AF2

L6

L3

K26

K23

K4

K1

J25

J22

J5

J2

A23

H24

H21

H6

H3

G26

G23

G1

G4

F25

F22

A19

F2

F19

F16

F13

F11

F8

F5

E24

E21

E19

A16

E16

E14

E11

E8

E6

E3

D26

D23

D19

D16

A14

D13

D11

D8

D4

D1

C25

C22

C2

C19

C16

A11

C14

C11

C8

B1

AF25

A25

AF21

C5

AF19

AF16

AF13

AF11

AF8

AF6

A2

AE26

AE23

AE19

B24

AE16

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

B21

AD13

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

B19

AC11

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

B16

AB8

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

B13

AA5

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

B11

A8

A4

U1000

SYNC_DATE=11/12/2008

SYNC_MASTER=M98_MLB

CPU Power & Ground

051-7892

A.0.0

11 97

PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PP1V8R1V5_S0_FET

PPCPUVTT_S0

PPVCORE_S0_CPU

7 8

11 12 46 63

7 8

12 16 24 28 29 39 68 69

70

6 7 8 9

10 12 13 14 17 18 20 22

24 25 63 67

7 8

11 12 46 63

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1x 10uF, 1x 0.01uF

CPU VCORE HF AND BULK DECOUPLING

4x 330uF, 20x 22uF 0805

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1206

2.5V

20% D2T

POLY

470UF

CRITICAL

32

1

C1235

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1204

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1216

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1214

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1208

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1203

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1207

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1202

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1201

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1213

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1212

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1211

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1219

6.3V

20% 603

X5R-CERM

22UF

CRITICAL

2

1

C1200

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1210

10V

20%

402

CERM

0.1UF

2

1

C1236

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1205

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1209

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1215

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1217

10V

20%

402

CERM

0.1UF

2

1

C1237

10V

20%

402

CERM

0.1UF

2

1

C1238

10V

20%

402

CERM

0.1UF

2

1

C1239

10V

20%

402

CERM

0.1UF

2

1

C1240

10V

20%

402

CERM

0.1UF

2

1

C1241

6.3V

20% X5R-CERM

22UF

CRITICAL

603

2

1

C1218

16V

10%

402

CERM

0.01UF

PLACEMENT_NOTE=Place near CPU pin B26.

2

1

C1281

6.3V

20%

603

X5R

10uF

2

1

C1280

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1250

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1251

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1252

2.0V

20%

D2T-SM2

POLY-TANT

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

32

1

C1253

051-7892

SYNC_DATE=10/17/2007

A.0.0

12 97

SYNC_MASTER=M87_MLB

CPU Decoupling & VID

PPCPUVTT_S0

PPVCORE_S0_CPU

PP1V8R1V5_S0_FET

6 7 8 9

10 11 13 14 17 18 20

22 24 25 63 67

7 8

11 46 63

7 8

11 16 24 28 29 39 68 69

70

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TCK0

OBSDATA_A3

OBSDATA_A1

OBSFN_C0

OBSDATA_C0 OBSDATA_C1

OBSDATA_C3

Mini-XDP Connector

VCC_OBS_CD

DBR#/HOOK7

Please avoid any obstructions on even-numbered side of J1300

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

TDO

TDI

RESET#/HOOK6

OBSFN_D0

SCL

SDA

TRSTn

HOOK3

HOOK2

HOOK1

TMS

OBSDATA_D0

TCK1

OBSDATA_B2

PWRGD/HOOK0

OBSFN_D1

OBSDATA_B3

XDP_PRESENT#

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSFN_B0

OBSDATA_C2

OBSFN_C1

Direction of XDP module

998-1571

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSDATA_A2

OBSDATA_A0

OBSFN_A1

OBSFN_A0

Use with 920-0620 adapter board to support CPU, MCP debugging.

MCP79-specific pinout

10 14 88

1/16W

5%

402

MF-LF

1K

XDP

21

R1399

21 28 29 45 91

1/16W

1%

402

MF-LF

54.9

XDP

2

1

R1315

16V

10%

402

X5R

0.1uF

XDP

2

1

C1300

16V

10%

402

X5R

0.1uF

XDP

2

1

C1301

10 88

6

10 88

9

10 14 88

1/16W

5%

402

MF-LF

1K

XDP

PLACEMENT_NOTE=Place close to CPU to minimize stub.

21

R1303

10 88

6

21 76

6

21

6

21

19 91

6

21 76

6

14 88

6

10 88

6

10 88

6

10 88

10 26

19

F-ST-SM

LTH-030-01-G-D-NOPEGS

CRITICAL XDP_CONN

9

8 7

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1300

eXtended Debug Port(MiniXDP)

97

A.0.0

13

SYNC_MASTER=M98_MLB

051-7892

SYNC_DATE=11/12/2008

TP_XDP_OBSFN_B0

XDP_BPM_L<3>

PP3V3_S0 PPCPUVTT_S0

TP_XDP_OBSDATA_B2

MCP_DEBUG<2>

JTAG_MCP_TDI

MCP_DEBUG<4>

MCP_DEBUG<6> MCP_DEBUG<7>

XDP_CPURST_L XDP_DBRESET_L

MCP_DEBUG<0>

XDP_TCK

SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_OBS20

TP_XDP_OBSDATA_B3

XDP_PWRGD

TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1

TP_XDP_OBSFN_B1

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_BPM_L<5>

JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L

MCP_DEBUG<1>

MCP_DEBUG<3>

JTAG_MCP_TMS

MCP_DEBUG<5>

FSB_CLK_ITP_P FSB_CLK_ITP_N

XDP_TDI

XDP_TRST_L

XDP_TDO_CONN

XDP_TMS

CPU_PWRGD

FSB_CPURST_L

6 7 8

18 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96 6 7 8 9

10 11 12 14 17 18 20

22 24 25 63 67

88

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

IN

BI BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Loop-back clock for delay matching.

(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)

20 mA 29 mA 15 mA

206 mA270 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

9

10 88

9

10 13 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

9

10 88

7

10 88

7

10 88

7

10 88

13 88

10 88

9

10 88

9

10 88

10 13 88

10 88

9

10 63 88

9

10 43 63 88

10 43 88

10 88

49.9

1/16W

1%

402

MF-LF

2

1

R1436

1/16W

1%

402

MF-LF

49.9

2

1

R1431

49.9

MF-LF

402

1%

1/16W

2

1

R1430

49.9

1/16W

1%

402

MF-LF

2

1

R1435

NO STUFF

1K

402

5% 1/16W MF-LF

2

1

R1422

1K

NO STUFF

402

MF-LF

5%

1/16W

2

1

R1421

1K

5%

402

MF-LF

NO STUFF

1/16W

2

1

R1420

1/16W

402

MF-LF

62

5%

2

1

R1415

1/16W

402

MF-LF

54.9

1%

2

1

R1410

NO STUFF

150

1/16W 402

MF-LF

5%

2

1

R1440

OMIT

(1 OF 11)

MCP79-TOPO-B

BGA

AH27 AG28 AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42

AB41

AC41

H38

AC35

AC33

AC39

AA33

AC38

AH43

AJ41

E41

AG41

AC43

AF42

AH42

AH39

AD40

AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32

AN33

AN32

AA40

AD39

J41

N35

V35

V41

U41

P42

Y42

M43

H39

J40

K41

Y41

H42

H43

L41

H41

K42

H40

M40

N40

N41

P41

V42

M42

L42

J37

J38

J39

N38

N36

L38

L39

L37

Y39

R38

R37

R39

P35

R35

R34

N33

N34

U37

R33

W41

W38

U34

U33

U35

U36

U38

AA35

AA38

AA34

AA36

Y40

W34

W33

AA37

W35

T43

R41

T41

T42

T39

R42

W42

Y43

AM43 AM42

F42 D42 F41

AL32

AE40

AA41

AD43

AK35

AE36

AD42

AB35

AE35

AE37

AC37

AE34

AE38

AN35

AR39

AN34

AL35

AL38

AJ34

AC34

AN37

AL34

AL37

AJ38

AJ36

AJ37

AJ35

AN36

AJ33

AF41

AL33

AG33

AL39

AN38

AG34

AG38

AG37

AE33

AG39

AG35

AF35

AM39 AM40

AL41 AK42

AL43 AL42

G42 G41

AJ40

AK41

U1400

1/16W 402

MF-LF

62

5%

2

1

R1416

A.0.0

SYNC_DATE=12/12/2008

MCP CPU Interface

051-7892

9714

SYNC_MASTER=T18_MLB

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_BREQ0_L

FSB_BNR_L

FSB_CLK_MCP_N

FSB_BREQ1_L

FSB_REQ_L<4>

FSB_ADS_L

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<34>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32>

FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_DINV_L<3>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_DPWR_L

FSB_RS_L<1>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

FSB_TRDY_L

CPU_PROCHOT_L

=MCP_BSEL<0>

FSB_RS_L<2>

=MCP_BSEL<1>

FSB_CLK_MCP_P

CPU_PWRGD

FSB_DSTB_L_P<0>

FSB_DSTB_L_P<1>

FSB_DINV_L<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<0>

FSB_DINV_L<2>

FSB_DSTB_L_P<2> FSB_DSTB_L_N<2>

FSB_DSTB_L_P<3>

FSB_A_L<4>

FSB_DSTB_L_N<3>

FSB_A_L<3>

FSB_A_L<5>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<6> FSB_A_L<7>

FSB_A_L<12>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<11>

FSB_A_L<15> FSB_A_L<16>

FSB_A_L<19>

FSB_A_L<17> FSB_A_L<18>

FSB_A_L<20> FSB_A_L<21>

FSB_A_L<35>

FSB_A_L<33>

FSB_ADSTB_L<0>

FSB_REQ_L<0>

FSB_LOCK_L

FSB_HIT_L FSB_HITM_L

CPU_FERR_L

PM_THRMTRIP_L

TP_CPU_PECI_MCP

MCP_CPU_COMP_GND

FSB_D_L<0> FSB_D_L<1>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<4> FSB_D_L<5> FSB_D_L<6>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<9>

FSB_D_L<15>

FSB_D_L<17> FSB_D_L<18>

FSB_D_L<16>

FSB_D_L<19> FSB_D_L<20> FSB_D_L<21>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40> FSB_D_L<41>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47>

FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59>

FSB_D_L<63>

FSB_BPRI_L FSB_DEFER_L

FSB_CLK_ITP_P FSB_CLK_ITP_N

CPU_A20M_L

CPU_NMI

CPU_INTR

CPU_SMI_L

FSB_CPURST_L FSB_CPUSLP_L

CPU_DPSLP_L

CPU_STPCLK_L CPU_DPRSTP_L

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_ADSTB_L<1>

CPU_IGNNE_L CPU_INIT_L

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<0>

PP1V05_S0_MCP_PLL_FSB

FSB_A_L<10>

=MCP_BSEL<2>

FSB_DBSY_L FSB_DRDY_L

FSB_REQ_L<1>

PPCPUVTT_S0

88

24

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

OMIT

MCP79-TOPO-B

(2 OF 11)

BGA

AR17

AV17

AP15 AV15

AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39

AN5

AU5 AR10 AN13 AN27 AW29 AV35 AR34

AT37 AU37 AW39

AL8

AL9

AP9

AN9

AV39

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5 AN10

AR5

AR37

AU6

AV5

AU7

AU8

AW9 AP11

AW6

AY5

AU9

AV9

AR38

AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25

AV38

AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31

AW38

AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31

AR35 AP35

AT15 AR18

AW33 AV33

BA24 AY24

BB20 BC20

AU23 AT23

AP17

AP23 AP19 AW17

AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19

AR23 AU15 AN23 AW21 AN19

AT19 AR19

U1400

28 89

29 89

OMIT

(3 OF 11)

MCP79-TOPO-B

BGA

BA16

AW16

BB13 AY15

AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43

AT5 BA2

AY7 BA11 BB34 BB38 AY43 AR42

AW42 AW41 AT40

AT4

AT3

AV2

AV3

AT41

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

AP41

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

AN40

BA9 BB10 BB12 AW12

BB8

BB9 AY12 BA12 BC32 AW32

AU40

BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40

AU41

BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40

AR41 AP42

BB14 BB16

BA42 BB42

BB22 BA22

BA19 AY19

AY31 BB30

BA15

BB29 BB18 BB17

BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25

BA29 BA14 AW28 BC28 BA17

BB25 BA18

U1400

29 89

97

051-7892

A.0.0

15

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2008

MCP Memory Interface

MEM_B_DQ<23>

MEM_A_CKE<1> MEM_A_CKE<0>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

NC_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<8> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<13> MEM_A_A<12>

MEM_A_A<14>

MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DQ<0> MEM_A_DM<7>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12>

MEM_A_DQ<16>

MEM_A_DQ<21> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<17>

MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22>

MEM_A_DQ<26>

MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<35> MEM_A_DQ<34>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<33>

MEM_A_DQ<41>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<40> MEM_A_DQ<39>

MEM_A_DQ<42>

MEM_A_DQ<47> MEM_A_DQ<46>

MEM_A_DQ<43>

MEM_A_DQ<45> MEM_A_DQ<44>

MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<52>

MEM_A_DQ<48>

MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<61> MEM_A_DQ<60>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_ODT<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<60> MEM_B_DQ<59>

MEM_B_DQ<62>

MEM_B_DQ<58>

MEM_B_DQ<61>

MEM_B_DQ<57>

MEM_B_DQ<53>

MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<49>

MEM_B_DQ<51> MEM_B_DQ<50>

MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<42> MEM_B_DQ<41>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<36> MEM_B_DQ<35>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<31> MEM_B_DQ<30>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<22>

MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24>

MEM_B_DQ<17>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<18>

MEM_B_DQ<21>

MEM_B_DQ<16>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<11> MEM_B_DQ<10>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<3>

MEM_B_DQ<6>

MEM_B_DQ<2>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<1>

MEM_B_DM<6> MEM_B_DM<5>

MEM_B_DQ<0> MEM_B_DM<7>

MEM_B_DM<4> MEM_B_DM<3>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DQ<40>

MEM_B_DQS_P<7>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>

MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>

TP_MEM_B_CLK2P

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CS_L<1> MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_ODT<1> MEM_B_ODT<0>

MEM_B_CKE<0>

MEM_B_CKE<1>

7

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

4771 mA (A01, DDR3)

17 mA 12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA

TP or NC for DDR2.

39 mA

87 mA (A01)

1%

40.2

1/16W

402

MF-LF

2

1

R1610

MF-LF

402

1%

1/16W

40.2

2

1

R1611

OMIT

(4 OF 11)

MCP79-TOPO-B

BGA

BC29

AN16

AM29

AM27

AM25

AM31

AL30

BC25

AW24

AW19

AY26

AM23

AY25

AU18

AM15

AY18

AY17

AV20

BC17

AW27

AU22

AU20

AM21

AV24

AY29

AT21

AU24

AN18

AU16

AP18

AP22

AW15

AR24

AM19

AR20

AR16

AV16

AP24

AP20

AN22

AP16

AT17

AN24

AN20

AM17

T28

T27 U28 U27

AY32

BC13

AY16

AN15

AN17

AN41 AM41

BA13

BC16

AR15

AU17

BA41 BB41

AY23 BA23

BA20 AY20

AU33 AU34

BB24 BC24

BA21 BB21

BA31

BA30

AN25

AV23

W5

V34

V10

U22

U20

U18

T9

T7

T6

T38

T37

T35

T34

T33

T26

T24

AK11

T20

T18

T10

R5

R43

R40

R36

P7

P40

P4

P37

P34

P33

P10

N8

N39

M9

M7

M6

M5

M38

K7

H31

G32

G30

F24

D34

BC9

AY9

BC21

F28

AU10

AR36

AP30

AT25

AP12

AM28

AK7

AH35

AG24

AF24

AE20

AD22

AB7

AB22

AA39

AA22

U1400

30

MCP Memory Misc

16 97

A.0.0

051-7892

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

NC_MEM_B_CLK4N

NC_MEM_B_CLK4P

MCP_MEM_RESET_L

MCP_MEM_COMP_VDD MCP_MEM_COMP_GND

NC_MEM_A_ODT<2> NC_MEM_A_ODT<3>

NC_MEM_A_CKE<3>

NC_MEM_A_CKE<2>

NC_MEM_A_CLK3N

TP_MEM_A_CS_L<2> NC_MEM_A_CS_L<3>

TP_MEM_A_CLK5N NC_MEM_A_CLK4P

NC_MEM_A_CLK3P

TP_MEM_A_CLK4N

TP_MEM_A_CLK5P

PP1V05_S0_MCP_PLL_CORE

PP1V8R1V5_S0_FET

TP_MEM_B_CKE<3>

NC_MEM_B_CKE<2>

TP_MEM_B_ODT<3>

NC_MEM_B_ODT<2>

TP_MEM_B_CS_L<3>

TP_MEM_B_CS_L<2>

TP_MEM_B_CLK3N

NC_MEM_B_CLK3P

NC_MEM_B_CLK5N

TP_MEM_B_CLK5P

PP1V8R1V5_S0_FET

7

89

7

24

7 8

11 12 16 24 28 29 39 68 69

70

7

7 8

11 12 16 24 28 29 39 68

69 70

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Int PU (S5)

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU

84 mA (A01)

Int PU

57 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

OMIT

MCP79-TOPO-B

(5 OF 11)

BGA

K11

A11

M19

M17

M18

M16

L18

L16

B10

M15

C10

E8

D9

D5

F17

N14 M14

L14 K14

J13 H13

G13 F13

J11 J10

B6 C6

A7 B7

B8 A8

D8 C8

H7 G7

F9 E9

H9 G9

K9 J9

G11 F11

H3 H2

G3 H4

F3 F4

E2 F2

D2 E1

C1 D1

B3 B2

A4 A3

C4 B4

M2 M1

M4 M3

L4 L3

K2 K3

J2 J3

H1 J1

C5 D4

L11 L10

J5 J4

J7 J6

G5 H5

C3 D3

E4 E3

E5 F5

E6 F6

D7 C7

N5 N4

N7 N6

N9 P9

N11 N10

L7 L6

L9 L8

F7 E7

E11 D11

C9

T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

P13

N13

M13

U12

T12

N12

R12

P12

M12

AB12

AA12

W12

V12

AD12

AC12

Y12

U1400

9

71 90

9

7

31 90

7

31 90

9

37

7

31

36 90

9

90

9

90

31

9

31 90

36 90

9

90

9

90

31 90

9

90

9

90

9

2.37K

402

MF-LF

1% 1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

2

1

R1710

26 37

84

6 9

84

32

SYNC_MASTER=T18_MLB

MCP PCIe Interfaces

17 97

A.0.0

051-7892

SYNC_DATE=04/04/2008

PP1V05_S0_MCP_PEX_AVDD

=PEG_D2R_P<0>

=PEG_D2R_N<2>

PP1V05_S0_MCP_PLL_PEX

PPCPUVTT_S0

=PEG_D2R_N<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6>

PCIE_MINI_PRSNT_L

NC_PCIE_PE4_R2D_CN

TP_PCIE_PE4_R2D_CP

TP_PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_N

TP_PCIE_EXCARD_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P

TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P

NC_PCIE_CLK100M_PE5N

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE4N

NC_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PEG_CLK100M_N

PEG_CLK100M_P

PCIE_CLK100M_MINI_P

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14> =PEG_R2D_C_P<15>

=PEG_R2D_C_N<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<13>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<9> =PEG_R2D_C_P<10>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_N<4> =PEG_R2D_C_P<5>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<0>

MCP_PEX_CLK_COMP

NC_PCIE_PE4_D2RN

TP_PCIE_PE4_D2RP

TP_PCIE_EXCARD_D2R_N

PCIE_MINI_D2R_N

PCIE_FW_D2R_P

TP_PCIE_EXCARD_D2R_P

PCIE_FW_D2R_N

PCIE_WAKE_L

PCIE_MINI_D2R_P

PEG_PRSNT_L

=PEG_D2R_N<13> =PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_D2R_N<14>

=PEG_D2R_N<15>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<13>

=PEG_D2R_N<11>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_P<8>

=PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_N<8>

=PEG_D2R_N<9>

=PEG_D2R_N<5>

=PEG_D2R_P<7>

=PEG_D2R_N<6>

=PEG_D2R_N<7>

=PEG_D2R_P<3>

=PEG_D2R_P<5>

=PEG_D2R_N<3>

=PEG_D2R_N<4>

=PEG_D2R_P<1> =PEG_D2R_N<1>

PCIE_FW_PRSNT_L

FW_CLKREQ_L

TP_PCIE_CLK100M_EXCARD_P

TP_EXCARD_CLKREQ_L TP_PCIE_EXCARD_PRSNT_L

MINI_CLKREQ_L

TP_PE4_CLKREQ_L NC_PE4_PRSNT_L

AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L

CARDREADER_RESET JTAG_GMUX_TDO

8

17 24

8

17 24 24

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

7

90

7

60

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

IN OUT

IN IN IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable: Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1 0

MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_DDC_CLK

TP_DP_IG_AUX_CHP/N

TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0>

MCP Signal

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_DDC_DATA

TMDS_IG_HPD

=MCP_HDMI_HPD DP_IG_AUX_CH_P/N

8 mA 8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_IFPx at 1.8V

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_ML_P/N<0>

Interface Mode

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

level-shifters.

NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used): In MCP79 these pins have undocumented internal

24

33 92

34 92

33 92

25 90

9

84

9

84

9

81 90

9

84

9

81

25 90

49.9

402

MF-LF

1/16W

1%

2

1

R1810

1%

402

49.9

MF-LF

1/16W

2

1

R1811

77 81 82 84

25

9

18

9

18

9

18

OMIT

MCP79-TOPO-B

(6 OF 11)

BGA

D38

C38

C37

A35

E36

A36

D36

B36 C36

D25

C25

C24

B24

C26

D24

A24

E24

B23

C23

C22

A23

G23

C21

D21

J22

A41

B38

C39

B39

A40

A39 B40

M26

M27

T25

K32

J32

M28 M29

V23

U23

T23

K24

J24

E28

F23

J23

B22

C27 B27

B26

F40

E37

G39

N30 M30

L30 K30

L29 K29

J29 H29

L31 K31

G31

E32

B34 C34

D33 C33

D32 C32

B32 A32

B35 C35

F31

C31

J30

J33 H33

F33 G33

G35 F35

D35 E35

J31

B15

E16

D43 C43

E31

B30

A31

D31

C30

B31

E23

U1400

MF-LF

5% 1/16W

402

10K

2

1

R1850

MF-LF

1/16W

100K

5%

402

2

1

R1861

100K

1/16W

5%

MF-LF

402

2

1

R1860

44

1/16W MF-LF

402

47K

5%

2

1

R1820

33 92

84 90

33 92

84 90

9

90

9

90

9

90

9

90

84 90

33 92

84 90

9

90

9

90

81

9

77 81

9

77 81

25 90

33 92

25 90

33 92

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2008

051-7892

A.0.0

9718

DP_CA_DET

PP1V05_ENET_MCP_PLL_MAC

PPCPUVTT_S0

PP3V3_S0_MCP_VPLL

PP1V8_S0

PP3V3_S0_MCP_DAC

PP1V2R1V05_ENET

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

NC_LVDS_IG_BKL_PWM

NC_MCP_CLK27M_XTALOUT

LPCPLUS_GPIO

=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2>

GMUX_INT

LVDS_IG_A_CLK_N

NC_MCP_CLK27M_XTALIN

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

NC_MCP_RGB_DAC_RSET NC_MCP_RGB_DAC_VREF

NC_MCP_TV_DAC_VREF

DP_IG_AUX_CH_P DP_IG_AUX_CH_N

DP_IG_HPD

MCP_HDMI_RSET MCP_HDMI_VPROBE

ENET_MDIO

MCP_CLK25M_BUF0_R

MCP_DDC_DATA0

MCP_DDC_CLK0

NC_MCP_RGB_RED NC_MCP_RGB_GREEN NC_MCP_RGB_BLUE

NC_MCP_RGB_HSYNC NC_MCP_RGB_VSYNC

NC_CRT_IG_R_C_PR NC_CRT_IG_G_Y_Y

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1>

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA_N<2>

NC_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKN

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2> NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAN<3>

DP_IG_DDC_DATA

DP_IG_DDC_CLK

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

NC_MCP_TV_DAC_RSET

ENET_RXD<0>

NC_ENET_INTR_L

ENET_RXD<3>

ENET_RX_CTRL

ENET_CLK125M_RXCLK

ENET_RXD<2>

ENET_RXD<1>

ENET_RESET_L

ENET_MDC

NC_ENET_PWRDWN_L

MCP_MII_PD MCP_MII_PD MCP_MII_PD

NC_CRT_IG_B_COMP_PB NC_CRT_IG_HSYNC

NC_CRT_IG_VSYNC

MCP_MII_VREF

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

PP3V3_ENET_PHY

NC_LVDS_IG_A_DATAN<3>

PP3V3_S0

PP3V3_ENET_PHY

PP3V3_S5

24

6 7 8 9

10 11 12 13 14 17 20

22 24 25 63 67

25

7 8

25 55 69 70 84 87

25

7 8

24 33 34 37

92

25

7

7 8

18 24 33 34

6 7 8

13 19 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

7 8

18 24 33 34

7 8

20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

OUT

BI BI BI BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

42 44 84 91

26 84 91

42 44 84 91

OMIT

(7 OF 11)

MCP79-TOPO-B

BGA

Y3

Y2

AA7

R11

R10

T4

U9

T3

V9

T2

T1

AB9

Y1

AA10

N1

N2

N3

P2

P3

U11

R4

U10

R3

Y4

AA9

AD11

R9

R8

R7

R6

W10

AA11

AA6

AA3

AA2

AC8

AC7

AB2

AC6

AB3

U7

T5

AE11

U6

U1

U5

U2

W11

U3

W9

V2

W8

V3

AC4

W7

W4

W6

W3

Y5

AA5

AA1

AC11

AC10

AC9

AE10

AC3

AE6

AE5

AE12

AD4

AE2 AE1

AE9

AD5

AD1

AD2

AD3

Y27

Y26

Y25

Y24

Y22

Y20

Y19

Y18

Y17

Y16

W43

W40

W36

W24

W22

W20

V7

V40

V4

V37

V33

V28

V27

V26

V24

V22

V20

V18

V17

V16

U8

U4

U39

U26

U24

AD34

AD33

AD28

AD27

AD26

AD25

AD24

AD20

AD19

AD18

AD17

AD16

AC5

AB33

AC40

AC36

AC22

AB40

AB4

AB37

AB34

AB28

AB27

AB26

AB25

AB24

AB23

AB21

AB20

H34

AB18

U1400

42 44

42 44 26 91

42 44

PLACEMENT_NOTE=Place close to pin R8

MF-LF 402

1/16W

5%

22

2

1

R1910

402

MF-LF1/16W

5%

8.2K

21

R1989

402

MF-LF1/16W

5%

8.2K

21

R1991

402

MF-LF1/16W

5%

8.2K

21

R1990

402

MF-LF1/16W

5%

8.2K

21

R1994

8.2K

5%

1/16W MF-LF

402

21

R1992

19

MF-LF 402

1/16W

5%

10K

2

1

R1961

1/16W MF-LF

402

22

5%

21

R1960

5%

1/16W MF-LF22402

21

R1950

5%

1/16W MF-LF22402

21

R1951

22

5%

1/16W MF-LF

402

21

R1952

402

MF-LF1/16W

5%

22

21

R1953

26

9

37

19

19 37

13

13 91

60

6 9

84

6 9

84

051-7892

A.0.0

9719

MCP PCI & LPC

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

NC_PCI_AD<27>

NC_PCI_AD<29>

NC_PCI_AD<28>

NC_PCI_AD<10>

NC_PCI_INTW_L NC_PCI_INTX_L TP_PCI_INTY_L NC_PCI_INTZ_L

FW_PLUG_DET_L

LPC_PWRDWN_L

NC_PCI_TRDY_L

NC_LPC_DRQ0_L LPC_SERIRQ

MCP_DEBUG<4>

MCP_DEBUG<0>

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<5> MCP_DEBUG<6>

NC_PCI_AD<9>

NC_PCI_AD<8>

MCP_DEBUG<7>

NC_PCI_AD<11>

NC_PCI_AD<14>

NC_PCI_AD<13>

NC_PCI_AD<12>

NC_PCI_AD<15> NC_PCI_AD<16> NC_PCI_AD<17>

NC_PCI_AD<20>

NC_PCI_AD<19>

NC_PCI_AD<18>

NC_PCI_AD<21> NC_PCI_AD<22>

NC_PCI_AD<25>

NC_PCI_AD<23>

NC_PCI_AD<26>

NC_PCI_AD<31>

NC_PCI_GNT0_L

NC_PCI_C_BE_L<2>

NC_PCI_C_BE_L<0>

NC_PCI_C_BE_L<3>

NC_PCI_IRDY_L

NC_PCI_FRAME_L

NC_PCI_DEVSEL_L

TP_PCI_PAR

NC_PCI_SERR_L NC_PCI_STOP_L

MEM_VTT_EN_R NC_PCI_RESET1_L

PCI_CLK33M_MCP_R

NC_PCI_CLK1

NC_PCI_CLK0

PCI_CLK33M_MCP

LPC_FRAME_R_L

LPC_AD_R<1>

LPC_AD_R<0>

LPC_RESET_L

LPC_CLK33M_SMC_R

LPC_AD_R<3>

LPC_AD_R<2>

NC_PCI_AD<30>

NC_PCI_AD<24>

PM_CLKRUN_L

JTAG_GMUX_TMS JTAG_GMUX_TDI MCP_RS232_SOUT_L

NC_PCI_GNT1_L

NC_PCI_C_BE_L<1>

NC_PCI_PERR_L

AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L

PM_LATRIGGER_L

FW_PWR_EN

PCI_REQ0_L PCI_REQ1_L

FW_PWR_EN

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

MCP_RS232_SIN_L

PP3V3_S0

7

91

7

91

7

19 91

19 37

19 91

19

6 7 8

13 18 21 22 24 25 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

BI BI

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT OUT

IN

OUT OUT

IN IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ExpressCard

SD Card Reader

External C

Minimum 1.025V for Gen2 support

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

84 mA (A01)

Minimum 1.025V for Gen2 support

19 mA (A01)

External B

IR

Bluetooth

Camera

External A

External D

AirPort (PCIe Mini-Card)

Geyser Trackpad/Keyboard

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

127 mA (A01, AVDD0 & 1)

43 mA (A01, DVDD0 & 1)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

40 91

9

91

9

91

9

91

9

91

7

31 91

7

31 91

41 91

50 91

7

31 91

7

31 91

40 91

9

91

9

91

9

91

9

91

MF-LF

1% 1/16W

402

2.49K

2

1

R2010

806

MF-LF

1%

1/16W

402

2

1

R2060

5%

8.2K

MF-LF

1/16W 402

2

1

R2053

1/16W MF-LF

402

5%

8.2K

2

1

R2052

5%

8.2K

1/16W 402

MF-LF

2

1

R2051

8.2K

402

MF-LF

1/16W

5%

2

1

R2050

OMIT

MCP79-TOPO-B

(8 OF 11)

BGA

A27

H21

J21

K21

L21

H25 J25

K25 L25

D27 E27

F27 G27

J26 J27

K27 L27

F29 G29

A28 B28

C28 D28

K23 L23

F25 G25

C29 D29

AE3

E12

AP3 AP2

AN2

AN3

AN1 AM1

AM3

AM2

AM4 AL3

AK3

AL4

AK2 AJ3

AJ1

AJ2

AJ11 AJ10

AK9

AJ9

AJ7 AJ6

AJ4

AJ5

L28

AE16

AH19

AH17

AG19

AG17

AG16

AF19

AM14

AM13

AL14

AN14

AL13

AN12

AM12

AM11

AL12

AK13

AK12

AN11

AJ12

AH24

AH22

AH20

AH18

AG40

AG36

AG26

AG22

AG20

AG18

AF40

AF37

AF34

AF33

AF28

AF27

AF26

AF22

AF20

AF18

AF17

AF16

AD6

AE4

AE39

AE24

AE22

AD38

AD37

AD35

U1400

39 90

9

32 96

9

32 96

SYNC_MASTER=T18_MLB

MCP SATA & USB

051-7892

A.0.0

9720

SYNC_DATE=12/12/2008

TP_SATA_C_D2RN

SATA_HDD_D2R_P

SATA_ODD_R2D_C_P

MCP_USB_RBIAS_GND

USB_CARDREADER_N

USB_CARDREADER_P

NC_USB_10N

NC_USB_10P

NC_USB_EXTCN

NC_USB_EXTCP

USB_EXTB_N

NC_USB_EXCARDN

NC_USB_EXCARDP

USB_EXTB_P

USB_BT_N

USB_BT_P

USB_TPAD_N

USB_IR_N

USB_IR_P

USB_TPAD_P

NC_USB_EXTDN

NC_USB_EXTDP

USB_EXTA_N

NC_USB_MININ

NC_USB_MINIP

USB_EXTA_P

MCP_SATA_TERMP

TP_MCP_SATALED_L

TP_SATA_F_D2RN TP_SATA_F_D2RP

TP_SATA_E_R2D_CP

NC_SATA_D_D2RN NC_SATA_D_D2RP

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

NC_SATA_C_R2D_CN

NC_SATA_C_D2RP

NC_SATA_C_R2D_CP

SATA_ODD_D2R_N SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_HDD_R2D_C_P

USB_CAMERA_P USB_CAMERA_N

USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

TP_SATA_F_R2D_CN

TP_SATA_F_R2D_CP

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

PP3V3_S0_MCP_PLL_USB

PP1V05_S0_MCP_PLL_SATA

PPCPUVTT_S0

GND

PP1V05_S0_MCP_SATA_AVDD

GND

PP3V3_S5

91

7

90

7

40

43

24

6 7 8 9

10 11 12 13 14 17 18

22 24 25 63 67

8

24

7 8

18 22 24 26 30 34 37 38 44

54 64 68 69 70 82 87 96

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID* LLB*

PWRBTN* RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

automatic recovery.

Connects to SMC for

USER mode: Normal

recovery

SAFE mode: For ROMSIP

(MXM_OK for MXM systems)

Int PU (S5)

Int PU

SPI1 option. Rev B01 will.

NOTE: MCP79 rev A01 does not support

Int PU (S5)

Int PD

Int PU

1

0 1 0

LPC_FRAME# 0 0 1 1

default, LPC+ debug card pulls

R1961 and R2160 selects SPI0 ROM by

BIOS Boot Select

HDA_SDOUTI/F

SPI1

SPI0

LPC

NOTE: MCP79 does not support FWH, only

Frequency

SPI Frequency Select

1 MHz

NOTE: Straps not provided on this page.

31 MHz

Frequency

BUF_SIO_CLK Frequency

14.31818 MHz

1

0

SPI_DO

SPI_CLK

0 1

1

0

24 MHz

HDA_SYNC

1 0

LPC ROMs. So Apple designs will

0

42 MHz 25 MHz

Int PU Int PU Int PU (S5)

Int PU

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

LPC_FRAME# high for SPI1 ROM override.

not use LPC for BootROM override.

PCI

For EMI Reduction on HDA interface

HDA Output Caps

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

7 mA (A01)

37 mA (A01)

20 mA 17 mA

Int PU (S5) Int PU (S5)

(MGPIO3)

(MGPIO2)

44 91

7

34 37 42 69 82 84

7

40 42 43 69 70

13 28 29 45 91

45 60 85 91

13 28 29 45 91

45 60 85 91

21 66

48 96

21 66

21 31 34

48 96

9

34

63 88

42

55 91

MF-LF

1/16W

1%

402

49.9K

2

1

R2121

1%

49.9K

MF-LF

402

1/16W

2

1

R2120

1K

MF-LF

1% 1/16W

402

2

1

R2190

26 91

42

MF-LF

402

5%

22

1/16W

21

R2170

MF-LF

5%

1/16W

402

22

21

R2171

5%

22

MF-LF

1/16W

402

21

R2173

402

5%

10K

MF-LF

1/16W

2

1

R2163

MF-LF

8.2K

5% 1/16W

402

2

1

R2160

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

2

1

R2180

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

2

1

R2181

402

5%

22

1/16W MF-LF

21

R2172

44

49.9

MF-LF

1/16W

1%

402

2

1

R2110

402

1/16W MF-LF

5%

10K

2

1

R2150

6

13

6

13

6

13 76

6

13 76

6

10PF

50V

5%

402

CERM

2

1

C2171

50V

10PF

5%

402

CERM

2

1

C2173

50V

10PF

5%

402

CERM

2

1

C2170

50V

10PF

5%

402

CERM

2

1

C2172

OMIT

(9 OF 11)

MCP79-TOPO-B

BGA

B19

B16

A19

A16

B11 C11

K22

B18

C13

B14

C15

C14 D13

F21

K19 G21

L19

M23

H17

G17 J17

C19

C20

D16

D20

C16

E20

L22

AE17

AE18

K16

J16

M21

M20

L20

M24

M25

L13

J18

J19

F19

E19

G19

B20

L15

F15

J15

J14

G15

K15

A15

L17

K17

E15

L24

L26

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

39

21 60

26 26

34 37 42 43

21 28 29 42

402

1/16W MF-LF

5%

100K

2

1

R2147

10K

5% 1/16W

402

MF-LF

2

1

R2142

402

1/16W MF-LF

5%

10K

2

1

R2141

22K

5% MF-LF

1/16W 402

2

1

R2157

22K

5% MF-LF

1/16W 402

2

1

R2156

402

1/16W

22K

5% MF-LF

2

1

R2155

402

MF-LF

5% 1/16W

100K

2

1

R2151

1/16W MF-LF

5%

100K

402

1

2

R2154

MF-LF 402

1/16W

5%

10K

2

1

R2143

10K

5% MF-LF

1/16W 402

2

1

R2140

9

21 42 43

26

42

26

44 91

MCP HDA & MISC

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

21 97

A.0.0

051-7892

MCP_GPIO_4 AUD_I2C_INT_L

MCP_VID<0>

TP_MLB_RAM_VENDOR

PM_SLP_S3_L PM_SLP_RMGT_L

HDA_BIT_CLK_R

HDA_SDOUT_R

MCP_THMDIODE_N

MCP_THMDIODE_P

HDA_RST_R_L

MCP_HDA_PULLDN_COMP

NC_MLB_RAM_SIZE

MCP_VID<2>

MCP_VID<1>

SMC_RUNTIME_SCI_L

ARB_DETECT

SMC_IG_THROTTLE_L

ODD_PWR_EN_L

MEM_EVENT_L

SMC_WAKE_SCI_L

TP_MCP_KBDRSTIN_L

MCP_TEST_MODE_EN

TP_MCP_BUF_SIO_CLK

MCP_CPUVDD_EN

SMBUS_MCP_0_DATA

SMBUS_MCP_0_CLK

MCP_SPKR

HDA_SYNC_R

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

JTAG_MCP_TRST_L

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

JTAG_MCP_TMS

MCP_CPU_VLD

JTAG_MCP_TDI JTAG_MCP_TDO

RTC_RST_L

MCP_PS_PWRGD

PM_RSMRST_L

SM_INTRUDER_L

TP_MCP_LID_L PM_BATLOW_L

PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L

PM_DPRSLPVR

PM_SLP_S4_L

HDA_SDIN0

SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN

SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R

PM_CLK32K_SUSCLK_R

PP3V3_S0

SPIROM_USE_MLB

NC_SB_A20GATE

SMC_ADAPTER_EN

PP1V05_S0_MCP_PLL_NV

ARB_DETECT

SMC_IG_THROTTLE_L

AP_PWR_EN

PP3V3_S3

AUD_I2C_INT_L

MCP_GPIO_4

MCP_VID<0>

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V42_G3H

PP3V3_S0

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

MCP_VID<2>

MCP_VID<1>

HDA_SYNC

PP3V3_S0

MEM_EVENT_L

PP3V3_S0

21

21 91

91

7

21

21 91

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43

45 47 48 49 51 55 59 60 63 68

69 70 77 80

81 82 84 85 96

7

24

21

21 42 43

21 31 34

7 8

27 31 32 45 50 52 70

21 60

21

21 66

7 8

22 26 40 42 43 44 45 46

50 61 62 64 69

6 7 8

13 18 19 21 22 24 25

28 29 37 39 43 45 47 48 49

51 55 59 60 63 68 69 70 77

80 81 82 84 85 96

21 91

21 66

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

21 28 29 42

6 7 8

13 18 19 21 22 24 25

28 29 37 39 43 45 47 48 49

51 55 59 60 63 68 69 70 77

80 81 82 84 85 96

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1182 mA (A01)

450 mA (A01)

16 mA

10 uA (G3)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

80 uA (S0)

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

250 mA

1139 mA

43 mA

105 mA (A01)

266 mA (A01)

OMIT

(11 OF 11)

MCP79-TOPO-B

BGA

T22

AH16

Y11

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AD7

AN26

AB16

AB17

Y38

Y37

Y35

Y34

Y33

Y28

M37

M35

M34

M10

L5

L43

L40

AU1

K8

K40

K4

K37

K26

K18

K12

K10

J8

J12

G40

AN8

H23

AW35

H15

H11

G8

G6

G43

G4

G34

AW20

G24

G22

BC12

G16

G14

G12

G10

F8

F32

F16

F12

E33

E29

E25

E21

E17

E13

D6

D37

D30

D26

D23

D22

D19

D18

D15

D14

D10

C2

BC5

AY14

BC41

BC37

BC33

L35

AY6

AW31

BA4

BA1

AV40

AY41

AY38

AY37

AY34

AY33

AY30

AV12

AY10

AW43

AR43

G20

AW11

AV7

AV4

AV36

AV32

AV28

F20

G28

AU4

AU38

AU36

AR30

AU32

AP33

AU28

AU12

L12

AY22

AY21

AT9

AT7

AT6

AT33

AT29

AT13

AR12

AT10

AR40

AR32

AR28

AW23

AP7

AP40

AP4

AP37

AP36

AP34

AP32

AP28

AU14

AP14

AU26

AP10

Y7

AN4

AN39

AN30

AN28

AP26

AM9

AM7

AM6

AM5

AM38

AM37

AM35

AM34

AM30

AM26

AM24

AM22

AM20

AM18

AM16

AM10

AL5

AL40

AL36

AK40

AK4

AK37

AK34

AK33

AK10

AJ8

AJ39

AH38

AH37

AH34

AH33

AH26

U1400

OMIT

(10 OF 11)

BGA

MCP79-TOPO-B

AG32

W32

V32

U32

T32

AA32

Y32

P32

N32

N31

M33

M32

M31

L34

L33

L32

K35

K34

K33

J36

J35

J34

H37

H35

G38

G37

G36

F39

F38

F37

E40

E39

E38

D41

D40

D39

C42

C41

C40

B42

B41

AC32

AB32

AL31

AD32

AK32

AK31

AJ32

AH32

AE32

AF32

P31

R32

AA16

AF12

W25

Y23

W23

W21

AA24

AH9

AH7

AH6

AH5

AH4

AH3

AH21

Y21

AH25

W28

AA23

AH2

W26

AH11

AH10

AH1

AG9

AG8

AG5

AG7

AG6

AA21

AG4

AG3

AG25

AG23

AG21

AG12

AG11

AG10

AA20

AF9

AH23

AF7

AF4

AF3

AF25

AF23

AF21

AF2

AH12

AA19

AF11

AF10

AE28

AE27

AE26

AE25

AE23

AE21

AE19

U25

AA18

V25

W27

AD23

AD21

AC28

AC27

AC26

AC25

AC24

AC23

AA17

AC21

AC20

AC19

AC18

AC17

AC16

AA28

AA27

AA26

AA25

V21

U21

T21

A20

K28

J28

H27

G26

K20

J20

H19

G18

Y9

AA8

AB11

Y10

AD9

AB10

AE8

AD10

U1400

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

051-7892

A.0.0

9722

MCP Power & Ground

PPCPUVTT_S0

PPVCORE_S0_MCP_REG

PP3V3_S5

PP3V42_G3H

PP3V3_S0

PP1V2R1V05_S5

6 7 8 9

10 11 12 13 14 17 18 20

24 25 63 67

7 8

24 46 66

7 8

18 20 24 26 30 34 37 38 44

54 64 68 69

70 82 87 96

7 8

21 26 40 42 43 44 45 46

50 61 62 64 69

6 7 8

13 18 19 21 24 25 28 29

37 39 43 45

47 48 49 51 55 59 60 63 68 69

70 77 80 81

82 84 85 96

7 8

24 34 68

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

23 97

A.0.0

051-7892

MCP79 A01 Silicon Support

SYNC_MASTER=T18_MLB

SYNC_DATE=03/31/2008

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

(No IG vs. EG data)

MCP SATA (DVDD) Power

43 mA (A01)

270 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

19 mA (A01)

450 mA (A01)

57 mA (A01)

127 mA (A01)

206 mA (A01)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

105 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

MCP 3.3V Ethernet Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP 1.05V AUX Power

Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 5x 2.2uF 0402 (11 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

4771 mA (A01, DDR3)

333 mA (A01)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

5 mA (A01)

562 mA (A01)

Apple: 7x 2.2uF 0402 (15.4 uF)

131 mA (A01)

MCP 1.05V RMGT Power

MCP PCIE (DVDD) Power

MCP Core Power

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

4.7UF

X5R 402

20%

4V

2

1

C2582

4.7UF

X5R 402

20%

4V

2

1

C2588

4.7UF

X5R 402

20%

4V

2

1

C2584

4.7UF

X5R 402

20%

4V

2

1

C2586

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2555

4.7UF

X5R 402

20%

4V

2

1

C2502

1UF

X5R 402-1

10% 10V

2

1

C2507

1UF

X5R

10% 10V

402-1

2

1

C2506

1UF

402-1

10V

10% X5R

2

1

C2505

1UF

X5R 402-1

10% 10V

2

1

C2504

CERM 402

20% 10V

0.1UF

2

1

C2511

0.1UF

CERM 402

20% 10V

2

1

C2510

0.1UF

CERM 402

20% 10V

2

1

C2509

0.1UF

CERM 402

20% 10V

2

1

C2508

0.1UF

CERM 402

20% 10V

2

1

C2513

0.1UF

CERM

20% 10V

402

2

1

C2512

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2536

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2535

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2534

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2533

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2532

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2531

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2530

1UF

X5R 402-1

10% 10V

2

1

C2517

1UF

X5R 402-1

10% 10V

2

1

C2516

4.7UF

X5R 402

20%

4V

2

1

C2515

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2572

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2571

4.7UF

X5R 402

20%

4V

2

1

C2520

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2570

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2574

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2573

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2576

CERM

20%

6.3V 402-LF

2.2UF

2

1

C2575

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2553

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2552

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2551

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2550

0.1UF

CERM 402

20% 10V

2

1

C2549

0.1UF

CERM 402

20% 10V

2

1

C2548

0.1UF

CERM 402

20% 10V

2

1

C2547

0.1UF

CERM 402

20% 10V

2

1

C2546

0.1UF

CERM 402

20% 10V

2

1

C2545

0.1UF

CERM 402

20% 10V

2

1

C2544

0.1UF

CERM 402

20% 10V

2

1

C2543

0.1UF

CERM 402

20% 10V

2

1

C2542

0.1UF

CERM 402

20% 10V

2

1

C2541

4.7UF

X5R 402

20%

4V

2

1

C2540

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2562

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2564

4.7UF

X5R 402

20%

4V

2

1

C2580

30-OHM-5A

0603

21

L2570

30-OHM-5A

0603

21

L2575

0402

30-OHM-1.7A

21

L2582

30-OHM-1.7A

0402

21

L2584

30-OHM-1.7A

0402

21

L2588

30-OHM-1.7A

0402

21

L2586

30-OHM-1.7A

0402

21

L2555

4.7UF

X5R 402

20%

4V

2

1

C2500

4.7UF

X5R 402

20%

4V

2

1

C2501

0.1uF

CERM 402

20% 10V

2

1

C2526

0.1uF

CERM 402

20% 10V

2

1

C2525

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2560

0.1UF

CERM 402

20% 10V

2

1

C2589

0.1UF

CERM 402

20% 10V

2

1

C2590

4.7UF

X5R 402

20%

4V

2

1

C2595

30-OHM-1.7A

0402

21

L2595

1.47K

MF-LF

402

1%

1/16W

2

1

R2590

0.1UF

CERM 402

20% 10V

2

1

C2591

1.47K

MF-LF

402

1%

1/16W

2

1

R2591

18

0.1uF

CERM 402

20% 10V

2

1

C2521

CERM 402

20% 10V

0.1uF

2

1

C2518

0.1uF

CERM 402

20% 10V

2

1

C2519

10V 402

CERM

0.1UF

20%

2

1

C2583

0.1UF

CERM 402

20% 10V

2

1

C2585

0.1UF

CERM 402

20% 10V

2

1

C2587

0.1UF

CERM 402

20% 10V

2

1

C2596

0.1uF

CERM 402

20% 10V

2

1

C2529

4.7uF

X5R 402

20%

4V

2

1

C2528

30-OHM-1.7A

0402

21

L2580

0.1UF

CERM

20% 10V

402

2

1

C2581

4.7UF

X5R 402

20%

4V

2

1

C2503

97

051-7892

A.0.0

24

MCP Standard Decoupling

SYNC_MASTER=T18_MLB

SYNC_DATE=06/18/2008

PP1V2R1V05_ENET

PPCPUVTT_S0

PP1V2R1V05_S5

PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_CORE

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_ENET_MCP_PLL_MAC

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V2R1V05_ENET

PP3V3_ENET_PHY

MCP_MII_VREF

PP3V3_S0

PP3V3_S5

PP1V8R1V5_S0_FET

PP3V3_S0

PP3V3_ENET_PHY

PP1V05_S0_MCP_PEX_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPCPUVTT_S0

PP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPCPUVTT_S0

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

PPVCORE_S0_MCP_REG

PPCPUVTT_S0

7 8

18 24 33 34 37

6 7 8 9

10 11 12 13 14 17

18 20 22 24 25 63 67

7 8

22 34 68

7 8

68

21

16

20

18

7 8

18 24 33 34 37

7 8

18 24 33 34

6 7 8

13 18 19 21

22 24 25 28 29 37 39 43 45

47 48 49 51 55 59 60 63 68

69 70 77 80 81 82 84 85

96

6 7 8

13 18 19 21

22 24 25 28 29 37 39 43 45

47 48 49 51 55 59 60 63 68

69 70 77 80 81 82 84 85

96

7 8

18 20 22 26 30

34 37 38 44 54 64 68 69 70

82 87 96

7 8

11 12 16 28 29

39 68 69 70

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

7 8

18 24 33 34

8

17

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

8

20

6 7 8 9

10 11 12 13 14 17 18

20 22 24 25 63 67

14

17

7 8

22 46 66

6 7 8 9

10 11 12 13 14 17

18 20 22 24 25 63 67

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

95 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

190 mA (A01, 1.8V)

16 mA (A01)

Apple: ???

16 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

NO STUFF

0.1UF

CERM

402

20% 10V

2

1

C2620

NO STUFF

1K

MF-LF 402

1% 1/16W

2

1

R2630

NO STUFF

0.1UF

CERM

402

20% 10V

2

1

C2630

4.7UF

X5R 402

20%

4V

2

1

C2615

4.7UF

CERM

603

20%

6.3V 2

1

C2640

30-OHM-1.7A

0402

21

L2640

0.1uF

CERM 402

20% 10V

2

1

C2641

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2616

0

MF-LF 402

5% 1/16W

2

1

R2651

1K

MF-LF 402

1% 1/16W

2

1

R2620

2.2UF

CERM 402-LF

20%

6.3V

2

1

C2610

051-7892

A.0.0

9725

MCP Graphics Support

SYNC_MASTER=AMASON_M98_MLB

SYNC_DATE=06/18/2008

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_RED

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NC_MCP_RGB_RED NC_MCP_RGB_GREEN

NC_CRT_IG_B_COMP_PB

NC_MCP_CLK27M_XTALIN NC_MCP_CLK27M_XTALOUT

MCP_IFPAB_VPROBE

NC_MCP_TV_DAC_RSET NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

NC_MCP_RGB_DAC_VREF

MCP_HDMI_VPROBE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE NC_MCP_RGB_HSYNC NC_MCP_RGB_VSYNC

NC_MCP_RGB_BLUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

NC_CRT_IG_R_C_PR

NC_MCP_RGB_DAC_RSET

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNCNC_CRT_IG_VSYNC

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_YNC_CRT_IG_G_Y_Y

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

PP1V8_S0

MCP_HDMI_RSET

PP3V3_S0

MCP_IFPAB_RSET

PPCPUVTT_S0

PP3V3_S0_MCP_VPLL

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_DAC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

18 25

18 25 90

18 25

18 25 90

18 25

18 90

18 25 90

18 25 90 18 25 90

18 25

18 25 90

18 25

18 90

18 25

18 25 90

18 25

18 25 90 18 25 90

18 25 90

18 25 90 18 25 90

18 25

7 8

18 55 69 70 84 87

18 90

6 7 8

13 18 19 21 22 24 28 29

37 39 43 45 47 48 49 51 55 59

60 63 68 69 70 77 80 81 82 84

85 96

18 90

6 7 8 9

10 11 12 13 14 17 18

20 22 24 63 67

18

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

OUTY

B

A

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

but results in MCP79 ROMSIP sequence happening after CPU powers up.

Reset Button

10K pull-up to 3.3V S0 inside MCP

Platform Reset Connections

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization.

RTC Power Sources

LPC Reset (Unbuffered)

PCIE Reset (Unbuffered)

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

MCP S0 PWRGD & CPU_VLD

MCP 25MHz Crystal

RTC Crystal

10 13 21

12pF

CERM

402

5%

50V

21

C2810

12pF

CERM

402

5%

50V

21

C2811

0

MF-LF

5%

1/16W

402

21

R2810

NO STUFF

MF-LF

402

5%

1/16W

10M

2

1

R2811

19 84 91

XDP

0

MF-LF

402

5%

1/16W

21

R2896

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2883

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2881

0

MF-LF

402

5%

1/16W

21

R2890

SILK_PART=FP SYS RESET

OMIT

0

MF-LF

402

5%

1/16W

2

1

R2897

44

42

21

17 26 37

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2826

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2825

19 91

12pF

CERM

402

5%

50V

21

C2815

12pF

CERM

402

5%

50V

21

C2816

CRITICAL

25.0000M

SM-3.2X2.5MM

31

42

Y2815

0

MF-LF

402

5%

1/16W

21

R2815

NO STUFF

1M

MF-LF

402

5%

1/16W

2

1

R2816

21

42 91

PLACEMENT_NOTE=Place close to U1400

22

MF-LF

402

5%

1/16W

21

R2829

21 91

33

MF-LF

402

5%

1/16W

21

R2899

NO STUFF

1UF

X5R 402

10% 10V

2

1

C2899

17 26 37

9

65 70

33

MF-LF

402

5%

1/16W

21

R2870

19

42

44 91

42 91

32.768K

7X1.5X1.4-SM

CRITICAL

41

Y2810

0

5% 1/16W MF-LF

402

21

R2891

27

MF-LF

1/16W

5%

402

0

21

R2893

86

31

1/16W

5%

402

MF-LF

0

21

R2894

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

402

5%

1/16W

21

R2827

84

26 84

21

63

42 69

MCPSEQ_MIX

0

MF-LF

402

5%

1/16W

21

R2851

MCPSEQ_SMC

0.1UF

CERM 402

20% 10V

2

1

C2850

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_SMC

0

MF-LF

402

5%

1/16W

21

R2850

21

MCPSEQ_SMC

0

MF-LF

402

5%

1/16W

21

R2853

21

MCPSEQ_MIX

0

MF-LF

402

5%

1/16W

21

R2852

MCPSEQ_SMC

TC7SZ08AFEAPE

SOT665

4

5

3

1

2

U2850

402

16V X5R

0.1UF

10%

2

1

C2801

6.3V 402

20%

4.7UF

X5R

2

1

C2802

X5R

4.7UF

402

20%

6.3V

2

1

C2803

402

0

5% 1/16W MF-LF

21

R2895

32

051-7892

26

A.0.0

97

SB Misc

SYNC_MASTER=DDR

SYNC_DATE=12/15/2008

PP3V42_G3H

PCIE_RESET_L

PP3V42_G3H

RTC_CLK32K_XTALOUT_R

LPC_RESET_L

MINI_RESET_L

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT_R

PP3V3_S5

MCP_PS_PWRGD

MCP_CPU_VLD

MCP_CPUVDD_EN

MAKE_BASE=TRUE

GMUX_PCIE_RESET_L

PM_CLK32K_SUSCLK_R

LPC_CLK33M_SMC_R

PCA9557D_RESET_L

MEM_VTT_EN

LPC_CLK33M_GMUX

PM_CLK32K_SUSCLK

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

SMC_LRESET_L

DEBUG_RESET_L

PM_SYSRST_L

PM_SYSRST_DEBOUNCE_L

XDP_DBRESET_L

S0_AND_IMVP_PGOOD

VR_PWRGOOD_DELAY

GMUX_PCIE_RESET_L

MEM_VTT_EN_R

ALL_SYS_PWRGD

BKLT_PLT_RST_L

CARDREADER_PLT_RST_L

MAKE_BASE=TRUE

PCIE_RESET_L

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7 8

18 20 22 24 30 34 37 38

44 54 64 68 69 70 82 87 96

26 84

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Place close to U8400, U8450

Place close to J3200.126

Place close to J3100.126

MEM A VREF CA

DAC channel A B A B C D

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV

Place close to J3200.1

MEM B VREF CA

FRAME BUFFER VREF

CPU FSB VREF

- =PP3V3_S5_VREFMRGN

- =I2C_VREFDACS_SCL

BOM options provided by this page:

Place close to U8500, U8550

Place close to U1000.AD26

Page Notes

- =I2C_VREFDACS_SDA

10mA max load

- =PPVTT_S3_DDR_BUF

- =PP3V3_S3_VREFMRGN

ADDR=0x98(WR)/0x99(RD)

Place close to J3100.1

ADDR=0x30(WR)/0x31(RD)

Power aliases required by this page:

Required zero ohm resistors when no VREF margining circuit stuffed

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

VREFMRGN

NO_VREFMRGN

Signal aliases required by this page:

(per DAC LSB)

MEM A VREF DQ MEM B VREF DQ

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA

Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF

9

74

1/16W

1%

402

MF-LF

49.9

VREFMRGN

21

R2916

10 88

10V

20% 402

CERM

0.1UF

VREFMRGN

2

1

C2902

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2914

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2913

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2903

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2915

9

75

1/16W

1%

402

MF-LF

49.9

VREFMRGN

21

R2917

UCSP

MAX4253

VREFMRGN

B4

B1

C4

C1

C2

C3

U2902

UCSP

MAX4253

VREFMRGN

B4

B1

A4

A1

A2

A3

U2903

UCSP

MAX4253

VREFMRGN

B4

B1

A4

A1

A2

A3

U2902

UCSP

MAX4253

VREFMRGN

B4

B1

C4

C1

C2

C3

U2903

UCSP

MAX4253

VREFMRGN

B4

B1

A4

A1

A2

A3

U2904

UCSP

MAX4253

VREFMRGN

B4

B1

C4

C1

C2

C3

U2904

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2905

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2909

1/16W

1%

402

MF-LF

200

VREFMRGN

21

R2911

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2902

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2901

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2904

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2906

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2910

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2907

QFN

PCA9557

VREFMRGN

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2901

10V

20%

402

CERM

0.1UF

VREFMRGN

2

1

C2904

1/16W

1%

402

MF-LF

100

VREFMRGN

21

R2912

1/16W

5%

402

MF-LF

100K

VREFMRGN

21

R2908

26

27 39 42 45 94

MSOP

DAC5574

VREFMRGN

5

4

2

1

8

7

6

3

10

9

U2900

27 39 42 45 94

10V

20% 402

CERM

0.1UF

VREFMRGN

2

1

C2901

6.3V

20% 402-LF

CERM

2.2UF

VREFMRGN

2

1

C2900

10V

20%

402

CERM

0.1UF

VREFMRGN

2

1

C2905

10V

20%

402

CERM

0.1UF

VREFMRGN

2

1

C2903

SYNC_DATE=12/05/2008

27 97

A.0.0

051-7892

SYNC_MASTER=DDR

FSB/DDR3/FRAMEBUF Vref Margining

R2905

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

NO_VREFMRGN

R2911

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

NO_VREFMRGN

R2909

1

116S0004 CRITICAL

NO_VREFMRGN

RES,MTL FILM,0,5%,0402,SM,LF

R2903

1

116S0004 CRITICAL

NO_VREFMRGN

RES,MTL FILM,0,5%,0402,SM,LF

VREFMRGN_CPUFSB_EN

SMBUS_SMC_MGMT_SDA

VREFMRGN_FRAMEBUF_EN

VREFMRGN_DQ_SODIMM

PPVTTDDR_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_FRAMEBUF_EN

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

PCA9557D_RESET_L

VREFMRGN_DQ_SODIMMA_EN

SMBUS_SMC_MGMT_SCL

VREFMRGN_CA_SODIMMB_EN

CPU_GTLREF

GPU_FB_B_VREF_DIV

GPU_FB_A_VREF_DIV

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

PP3V3_S3

VREFMRGN_CPUFSB

VREFMRGN_DQ_SODIMMB_BUF

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

27

8

65

28

27

7 8

21 31 32 45 50 52 70

28

29

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

516-0196

SPD ADDR=0xA0(WR)/0xA1(RD)

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

"Factory" (top) slot

- =I2C_SODIMMA_SDA

- =PP0V75_S0_MEM_VTT_A

- =I2C_SODIMMA_SCL

- =PP1V5_S3_MEM_A

BOM options provided by this page:

(NONE)

F-RT-THB

DDR3-SODIMM-DUAL-M97-3

113

204203

196195

190189

185

184

179

178

173

172

168167

162161

156155

151

150

145

144

139

138

134133

128127

126

199

100

99

9493

8887

8281

124123

118117

112111

106105

7675

125

200 202201

197

121

114

110

120

116

122

77

198

186 188

169 171

152 154

135 137

194

192

182

180

193

191

183

181

176

174

166

164

177

175

165

163

160

158

148

146

159

157

149

147

142

140

132

130

143

141

131

129

187

170

153

136

7473

104

102

103

101

115

79

108

109

85

89

86

90

91 92

95 96

78 80

119

83 84

107

97 98

J3100

15 89

10V

20%

402

CERM

0.1UF

2

1

C3131

6.3V

20%

402-LF

CERM

2.2UF

2

1

C3130

15 89

29 30

15 89

F-RT-THB

DDR3-SODIMM-DUAL-M97-3

CRITICAL

2625

2019

1413

9

7271

6665

61

60

8

55

54

49

48

4443

3837

3231

3

21

30

62 64

45 47

27 29

10 12

23

21

18

16

6

4

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

63

46

28

11

J3100

15 89

9

15 89

10V

20% 402

CERM

0.1UF

2

1

C3136

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3135

15 89

21 29 42

13 21 29 45 91

15 89

1/16W

5%

402

MF-LF

10K

2

1

R3141

1/16W

5%

402

MF-LF

10K

2

1

R3140

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3140

6.3V

20%

603

X5R

10UF

2

1

C3100

6.3V

20%

603

X5R

10UF

2

1

C3101

10V

20% 402

CERM

0.1UF

2

1

C3110

10V

20% 402

CERM

0.1UF

2

1

C3111

10V

20% 402

CERM

0.1UF

2

1

C3112

10V

20% 402

CERM

0.1UF

2

1

C3113

10V

20% 402

CERM

0.1UF

2

1

C3114

10V

20% 402

CERM

0.1UF

2

1

C3115

10V

20% 402

CERM

0.1UF

2

1

C3116

10V

20% 402

CERM

0.1UF

2

1

C3117

10V

20% 402

CERM

0.1UF

2

1

C3118

10V

20% 402

CERM

0.1UF

2

1

C3119

10V

20% 402

CERM

0.1UF

2

1

C3120

10V

20% 402

CERM

0.1UF

2

1

C3121

10V

20% 402

CERM

0.1UF

2

1

C3122

10V

20% 402

CERM

0.1UF

2

1

C3123

28 97

A.0.0

051-7892

DDR3 SO-DIMM Connector A

SYNC_DATE=07/22/2008

SYNC_MASTER=DDR

MEM_A_BA<2>

MEM_A_DQ<60>

MEM_A_DQ<58> MEM_A_DQ<59>

MEM_A_SA<0>

PP1V8R1V5_S0_FET

MEM_A_DQ<3> MEM_A_DQ<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DM<0>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQ<11> MEM_A_DQ<14>

MEM_A_DQ<18>

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MEM_A_DQ<23> MEM_A_DQ<19>

MEM_A_DQ<30>

MEM_A_DQ<24>

MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_DQ<6> MEM_A_DQ<7>

MEM_A_DQ<8> MEM_A_DQ<12>

MEM_A_DM<1> MEM_RESET_L

MEM_A_DQ<15> MEM_A_DQ<10>

MEM_A_DQ<21> MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17> MEM_A_DQ<22>

MEM_A_DQ<29> MEM_A_DQ<28>

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MEM_A_DQ<26> MEM_A_DQ<31>

MEM_A_DQ<4>

MEM_A_DM<3>

MEM_A_DQ<16>

PP3V3_S0

MEM_A_CKE<1>

TP_MEM_A_A<15> MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_ODT<0>

MEM_A_ODT<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<36> MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38> MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<47>

MEM_A_DQS_N<5>

MEM_A_CKE<0>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_BA<0>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<13> MEM_A_CS_L<1>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<44> MEM_A_DQ<41>

MEM_A_DQ<46>

MEM_A_DQS_P<5>

MEM_A_DQ<43>

MEM_A_DQ<48> MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_EVENT_L

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

MEM_A_DQ<45>

MEM_A_DM<5>

MEM_A_DQ<42>

MEM_A_DQ<52> MEM_A_DQ<51>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<61>

MEM_A_DM<7>

MEM_A_CLK_N<0>

MEM_A_DQ<35>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

PP0V9R0V75_S0_DDRVTT

MEM_A_SA<1>

MEM_A_A<10>

MEM_A_DQ<32>

MEM_A_A<5>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6>

MEM_A_DQ<27> MEM_A_DQ<25>

PP1V8R1V5_S3

MEM_A_CS_L<0>

MEM_A_BA<1>

7 8

11 12 16 24 29 39 68 69

70

27

6 7 8

13 18 19

21 22 24 25 29 37 39 43

45 47 48 49 51

55 59 60 63 68 69 70 77

80 81 82 84 85

96

27

7 8

29 65 70

7 8

29 30 65 70

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Power aliases required by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

BOM options provided by this page:

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

Page Notes

516s0704

SPD ADDR=0xA2(WR)/0xA3(RD)

- =PP1V5_S0_MEM_B

"Expansion" (bottom) slot

(NONE)

Signal aliases required by this page:

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

15 89

21 28 42

13 21 28 45 91

10V

20%

402

CERM

0.1UF

2

1

C3231

15 89

6.3V

20%

402-LF

CERM

2.2UF

2

1

C3230

1/16W

5%

402

MF-LF

10K

2

1

R3241

1/16W

5%

402

MF-LF

10K

2

1

R3240

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3240

6.3V

20%

603

X5R

10UF

2

1

C3200

6.3V

20%

603

X5R

10UF

2

1

C3201

10V

20% 402

CERM

0.1UF

2

1

C3210

10V

20% 402

CERM

0.1UF

2

1

C3211

10V

20% 402

CERM

0.1UF

2

1

C3212

10V

20% 402

CERM

0.1UF

2

1

C3213

15 89

10V

20% 402

CERM

0.1UF

2

1

C3214

10V

20% 402

CERM

0.1UF

2

1

C3215

10V

20% 402

CERM

0.1UF

2

1

C3216

10V

20% 402

CERM

0.1UF

2

1

C3217

10V

20% 402

CERM

0.1UF

2

1

C3218

10V

20% 402

CERM

0.1UF

2

1

C3219

10V

20% 402

CERM

0.1UF

2

1

C3220

10V

20% 402

CERM

0.1UF

2

1

C3221

10V

20% 402

CERM

0.1UF

2

1

C3222

10V

20% 402

CERM

0.1UF

2

1

C3223

15 89

F-RT-BGA3

DDR3-SODIMM

113

204203

212211

210209

208207

206205

196195

190189

185

184

179

178

173

172

168167

162161

156155

151

150

145

144

139

138

134133

128127

126

199

100

99

9493

8887

8281

124123

118117

112111

106105

7675

125

200 202201

197

121

114

110

120

116

122

77

198

186 188

169 171

152 154

135 137

194

192

182

180

193

191

183

181

176

174

166

164

177

175

165

163

160

158

148

146

159

157

149

147

142

140

132

130

143

141

131

129

187

170

153

136

7473

104

102

103

101

115

79

108

109

85

89

86

90

91 92

95 96

78 80

119

83 84

107

97 98

J3200

15 89

28 30

15 89

F-RT-BGA3

DDR3-SODIMM

CRITICAL

2625

2019

1413

9

7271

6665

61

60

8

55

54

49

48

4443

3837

3231

3

21

30

62 64

45 47

27 29

10 12

23

21

18

16

6

4

70

68

17

58

56

69

67

59

57

52

50

42

40

15

53

51

41

39

36

34

24

22

35

33

7

5

63

46

28

11

J3200

15 89

9

15 89

10V

20% 402

CERM

0.1UF

2

1

C3236

6.3V

20% 402-LF

CERM

2.2UF

2

1

C3235

15 89

DDR3 SO-DIMM Connector B

SYNC_DATE=07/22/2008

051-7892

A.0.0

9729

SYNC_MASTER=DDR

PP1V8R1V5_S0_FET

MEM_B_DQ<9>

MEM_B_DQ<18> MEM_B_DQ<22>

MEM_B_DQ<4>

MEM_B_DQ<23>

MEM_B_DQ<19>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<16>

MEM_B_DQ<20>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DM<1>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_RESET_L

MEM_B_DM<3>

MEM_B_DQ<25>

MEM_B_DQ<29>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<5>

MEM_B_DQ<21> MEM_B_DQ<17>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<8>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_DM<0>

MEM_B_DQ<0> MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<3>

MEM_B_DQ<2>

PP3V3_S0

MEM_B_DQ<59>

MEM_B_DQ<63>

MEM_B_SA<0>

MEM_B_SA<1>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DM<7>

MEM_B_CAS_L

MEM_B_DQS_P<4>

MEM_B_DQ<35>

MEM_B_CLK_N<0>

MEM_B_A<10>

MEM_B_DQ<52> MEM_B_DQ<51>

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK

PP0V9R0V75_S0_DDRVTT

MEM_EVENT_L

MEM_B_DQ<58>

MEM_B_DQS_N<7> MEM_B_DQS_P<7>

MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQ<50>

MEM_B_DQ<53>

MEM_B_DM<6>

MEM_B_DQ<54>

MEM_B_DQ<48>

MEM_B_DQ<46>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<41>

MEM_B_DQ<34>

MEM_B_DQ<32> MEM_B_DQ<37>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_DQS_N<5>

MEM_B_DQ<44> MEM_B_DQ<45>

MEM_B_DQ<39>

MEM_B_DM<4>

MEM_B_DQ<36>

MEM_B_DQ<33>

PP0V75_S3_MEM_VREFCA_B

MEM_B_ODT<1>

MEM_B_CS_L<0> MEM_B_ODT<0>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

TP_MEM_B_A<15>

MEM_B_CKE<1>

MEM_B_DM<5>

MEM_B_DQS_N<4>

MEM_B_DQ<40>

MEM_B_DQ<55>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8> MEM_B_A<5>

MEM_B_A<3> MEM_B_A<1>

PP1V8R1V5_S3

MEM_B_CKE<0>

MEM_B_DQ<24>

MEM_B_DQ<38>

MEM_B_DQ<49>

MEM_B_DQ<62>

MEM_B_DM<2>

MEM_B_CLK_N<1>

7 8

11 12 16 24 28 39 68 69

70

27

6 7 8

13 18 19 21

22 24 25 28 37 39 43 45 47

48 49 51 55 59 60

63 68 69 70 77 80 81 82 84

85 96

7 8

28 65 70

27

7 8

28 30 65 70

D

Q2

SG

Q1

B

C

E

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

must be high before 1.5V starts to

3.3V S5 is used because MEM_RESET

rise to avoid glitch on MEM_RESET_L.

CRITICAL

DMB53D0UDW

SOT-363

12

4 6

3

5

Q3305

5% 1/16W MF-LF

402

100K

2

1

R3305

28 29

5%

402

MF-LF

1/16W

10K

2

1

R3300

10V

0.1UF

20% CERM

402

2

1

C3300

402

1/16W

20K

5%

MF-LF

2

1

R3301

402

0

1/16W MF-LF

5%

12

R3309

16

5% 1/16W MF-LF

402

1K

2

1

R3310

051-7892

A.0.0

9730

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2008

DDR3 Support

PP1V8R1V5_S3

MEM_RESET_L

MEM_RESET_RC_L

MEM_RESET

PP3V3_S5

MCP_MEM_RESET_L

7 8

28 29 65 70

7 8

18 20 22 24 26 34 37 38 44

54 64 68 69 70 82 87 96

OUT

IN

BI

NC

IN

BI

OUT OUT

Y

B

A

IN

NC

SYM_VER-1

D

S G

D

S G

OUT

IN

OUT OUT

D

GS

S

G

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

14 mOhm @4.5V

TPCP8102

5V S3 WLAN FET

Part Type Rds(on) Loading

0.8 A (EDP)

P-Channel

(C3420 & C3421)

PLACEMENT_NOTEs:

BLUETOOTH

750 mA nominal max

AIRPORT

ALS CAMERA

518S0610

206 mA nominal max

275 mA peak

1000 mA peak

7

17

F-RT-SM

20347-325E-12

CRITICAL

9

8

7

6

5

4

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3401

0402-LF

FERR-120-OHM-1.5A

PLACEMENT_NOTE=Place close to J3401.

2 1

L3405

34

7

42 45 51 94

7

42 45 51 94

PLACEMENT_NOTE=Place close to J3401.

FERR-120-OHM-1.5A

0402-LF

2 1

L3404

0.1uF

402

CERM

10V

20%

2

1

C3452

PLACEMENT_NOTE=Place close to J3401.

0.1uF

402

X5R

16V

10%

21

C3430

17 90

PLACEMENT_NOTE=Place close to J3401.

10% 16V X5R 402

0.1uF

21

C3431

17 90

7

20 91

7

20 91

Place close to Q3450.

20% 10V

CERM

402

0.1uF

2

1

C3421

7

20 91

7

20 91

7

17 90

7

17 90

TC7SZ08AFEAPE

SOT665

4

5

3

1

2

U3401

26

SOT-553

74LVC1G17DRL

4

5

13

2

U3402

Place close to Q3450.

20% 10V X5R 805

10UF

2

1

C3420

402

MF-LF

1/16W

5%

33K

2

1

R3453

1/16W

402

MF-LF

5%

62K

2

1

R3454

10%

6.3V CERM 402

1UF

2

1

C3453

CRITICAL

DLP11S

90-OHM-100MA

PLACE_NEAR=J3401.8,2mm

4 3

21

L3401

CRITICAL

PLACEMENT_NOTE=Place close to J3401.

90-OHM DLP0NS

4 3

21

L3402

CRITICAL

PLACEMENT_NOTE=Place close to J3401.

90-OHM DLP0NS

4 3

21

L3403

SSM6N15FEAPE

SOT563

1

2

6

Q3401

SSM6N15FEAPE

SOT563

4

5

3

Q3401

17

21 34

53 96

SOD-VESM-HF

SSM3K15FV

2

1

3

Q3455

1

5%

402

1/16W MF-LF

21

R3455

CERM

402

20% 10V

0.1uF

2

1

C3462

0402-LF

FERR-120-OHM-1.5A

2 1

L3406

CRITICAL

TPCP8102

23V1K-SM

321

4

8765

Q3450

SM

21

XW3450

SM

2

1

XW3451

SM

2

1

XW3452

10% 16V X5R 402

0.1UF

21

C3450

10% 16V X5R 402

0.033UF

2

1

C3451

100K

1/16W MF-LF

5%

402

21

R3450

402

MF-LF

1/16W

5%

10K

2

1

R3451

0.1uF

402

CERM

10V

20%

2

1

C3422

Right Clutch Connector

31 97

A.0.0

051-7892

SYNC_MASTER=MUXGFX

SYNC_DATE=12/08/2008

PP5V_WLAN_F

MIN_LINE_WIDTH=1 mm VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

PP5V_WLAN_R

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

ISNS_AIRPORT_N

ISNS_AIRPORT_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_MINI_CONN_P

PCIE_MINI_R2D_N

PP3V3_S3_BT_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_BTCAMERA_F

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

PP5V_S3

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm VOLTAGE=5V

PP5V_WLAN

MINI_RESET_CONN_L

PCIE_MINI_D2R_P PCIE_MINI_D2R_N

PCIE_WAKE_L

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

USB_CAMERA_CONN_N

USB_CAMERA_CONN_P

CONN_USB2_BT_N

CONN_USB2_BT_P

USB_CAMERA_P

USB_CAMERA_N

USB_BT_P

USB_BT_N

PCIE_MINI_R2D_C_P

WLAN_SMIT_DISCHRG

PCIE_CLK100M_MINI_CONN_N

PCIE_CLK100M_MINI_P

PP3V3_S3

WLAN_SMIT_RC

PM_WLAN_EN_L

MINI_CLKREQ_Q_L

MINI_CLKREQ_L

AP_PWR_EN

PCIE_MINI_PRSNT_L

PCIE_MINI_R2D_P

PCIE_MINI_R2D_C_N

WLAN_SMIT_BUF

MINI_RESET_L

PP5V_S3

P5VWLAN_SS

53

7

96

7

90

96

7

7 8

21 27 31 32 45 50 52 70

7

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7

96

7 8

21 27 31 32 45 50 52 70

7

90

96

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

BI BI

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW CARD_DETECT_GND

DAT6 DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

CLK CMD

DAT0

SHLD_PIN

SHLD_PIN SHLD_PIN

SHLD_PIN

X2

DP

CS

PMOSO

D1

VDD5V

D0

SK

DI

DO

D4

D2

D5

DM

GPIO2

D7

X1

GPIO3

GPIO1

VDD18O

AVDD

EXTRSTZ*

D3

DVDD

TESTMOD

CLK

D6

RREF

SD_CDZ

XD_CDZ

XD_CE XD_WEZ XD_RBZ XD_WPZ

MS_INS

SD_WP

SD_CMD

PDMOD

MS_BS

GND

NC

NC NC NC NC NC

NC NC

D

SG

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

MAX CURRENT = 250MA

IPU/

IPD/

/IPU

IPD/

/IPD

IPD/

/IPD

IPD/

IPU/ IPU/

IPU/

IPD/

NC = DISABLE (DEFAULT)

IPD/

10K LOW = POWER SAVING MODE ENABLE

PDMOD: POWER DOWN MODES

(PDMOD)

10K HIGH = REMOTE WAKE UP ENABLE

MF-LF 402

1/16W

5%

0

2

1

R3502

X5R

20%

603

6.3V

10UF

2

1

C3500

402

10V

20%

0.1UF

CERM

2

1

C3501

NO STUFF

402

MF-LF

1M

5%

1/16W

21

R3503

10V CERM

20%

0.1UF

402

2

1

C3505

10V

20% CERM

0.1UF

402

2

1

C3506

603

20% CERM1

6.3V

2.2UF

2

1

C3507

0.1UF

20% CERM

402

10V

2

1

C3508

0.1UF

CERM 402

10V

20%

2

1

C3502

0.1UF

CERM 402

20% 10V

2

1

C3503

402

0.1UF

10V CERM

20%

2

1

C3504

9

20 96

9

20 96

50V

CERM

5%

33PF

402

21

C3511

12.000M-100PPM

8X4.5X1.4-SM

CRITICAL

21

Y3500

402

50V

33PF

CERM

5%

21

C3512

OMIT

F-RT-TH

SD-CARD-K19

16

6

3

4

20

19

18

17

13

12

11

10

9

8

7

2

5

1

14 15

J3500

0.22UH

0805-1

21

L3500

LQFP

GL137A

45

42

44

31

1

14

13

25

4

17

19

3 41

23

10

36

2

24 33

46

47

48

342716

12

9

5

18

352615

8

21

7

22

38

32

30

28

29

37

43

40

20

39

11

6

U3500

6.3V X5R 603

10UF

20%

2

1

C3514

5% MF-LF

402

39K

1/16W

2

1

R3505

402

CERM

NO STUFF

0.1UF

20% 10V

2

1

C3513

715

1% 1/16W MF-LF 402

2

1

R3506

MF-LF

1/16W

10K

5%

402

2

1

R3507

1/16W

5%

10K

NO STUFF

402

MF-LF

2

1

R3508

5%

402

MF-LF

1/16W

10K

NO STUFF

2

1

R3509

5%

402

MF-LF

1/16W

10K

2

1

R3510

MF-LF

1/16W

0

5%

402

21

R3511

10K

5% MF-LF

402

1/16W

2

1

R3512

10K

1/16W MF-LF

5%

402

NO STUFF

2

1

R3513

402

MF-LF

1/16W

5%

0

21

R3504

402-1

CERM

50V

NO STUFF

5%

10PF

2

1

C3515

SSM6N15FEAPE

SOT563

4

5

3

Q3500

SSM6N15FEAPE

SOT563

1

2

6

Q3500

17

26

CONN,SD CARD READER,OPTN B

CRITICAL

J3500

1

516-0225

32 97

SYNC_DATE=01/30/2009

SYNC_MASTER=VEMURI

SECUREDIGITAL CARD READER

A.0.0

051-7892

CARDREADER_PLT_RST_L

CARDREADER_PLT_RST

CARDREADER_RESET

SD_CLK

PP3V3_S3_CARDREADER_DVDD

CARDREADER_GPIO2CARDREADER_GPIO1

MIN_NECK_WIDTH=0.20MM

PP3V3_S3

MIN_LINE_WIDTH=0.40MM

VOLTAGE=3.3V

PP3V3_S3_CARDREADER_DVDD

CARDREADER_PDMOD

SD_CMD

SD_WP

SD_CD_L

CARDREADER_RREF

SD_D<6>

SD_CLK_R

CARDREADER_TEST_MOD

SD_D<3>

CARDREADER_RESET_L

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

VOLTAGE=3.3V

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

PP3V3_S3_CARDREADER_AVDD

PP1V8_S3_CARDREADER

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=1.8V

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

PP3V3_S3_CARDREADER_DVDD

CARDREADER_GPIO1

CARDREADER_XTAL1

SD_D<7>

CARDREADER_GPIO2

SD_D<5>

SD_D<2>

SD_D<4>

SD_D<0> SD_D<1>

PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE

PP3V3_SW_SD_PWR

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

USB_CARDREADER_P

CARDREADER_XTAL2

USB_CARDREADER_N

7

93

32

32 32

7 8

21 27 31 45 50 52 70

32

7

93

7

93

7

93

32

7

93

32

7

93

7

93

7

93

7

93

7

93

IN IN IN IN

IN

BI

IN

BI

BI BI

OUT

OUT OUT OUT OUT

OUT

IN

TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1 CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]

MDI+[2]

MDI+[3]

MDI+[1] MDI-[1]

ENSWREG

TXD[1]

TXD[0]

RXD[3]/AN1

RXD[1]/TXDLY

TXC

MDI-[3]

LED1/PHYAD1

LED2/RXDLY

LED0/PHYAD0

RXD[2]/AN0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENCE

RGMII/MII

MEDIA DEPENDENT

MANAGEMENT

CLOCK

RESET

LED

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE R3796 CLOSE TO U1400, PIN D24

Alias to GND for external 1.05V supply.

Alias to =PP3V3_ENET_PHY for internal switcher.

WF: Marvell numbers, update for Realtek

If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

PHYAD = 01 (PHY Address 00001)

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T) ( 7mA typ - Energy Detect)

(19mA typ - Energy Detect)

(43mA typ - 1000base-T)

If internal switcher is not used, VDDREG and REGOUT can float.

Configuration Settings:

Hence, RC (R3725 and C3725) are made NOSTUFF.

ENET_RESET_L is not asserted when WOL is active.

per RealTek request.

Reserved for EMI

TXDLY = 0 (No TXCLK Delay)

AN[1:0] = 11 (Full auto-negotiation) RXDLY = 0 (RXCLK transitions with data)

1/16W

5%

402

MF-LF

0

21

R3724

10V

20% 402

CERM

0.1UF

NO STUFF

2

1

C3725

1/16W

1%

402

MF-LF

2.49K

2

1

R3730

1/16W

5%

402

MF-LF

4.7K

NO STUFF

2

1

R3725

1/16W

5%

402

MF-LF

10K

2

1

R3720

0402-LF

FERR-120-OHM-1.5A

CRITICAL

2

1

L3705

16V

10%

402

X5R

0.1UF

2

1

C3705

16V

10%

402

X5R

0.1UF

2

1

C3706

16V

10% 402

X5R

0.1UF

2

1

C3700

16V

10% 402

X5R

0.1UF

2

1

C3701

16V

10% 402

X5R

0.1UF

2

1

C3702

18 92

34 92

35 92

1/16W

5% 402

MF-LF

22

21

R3790

1/16W

5% 402

MF-LF

22

21

R3791

1/16W

5% 402

MF-LF

22

21

R3792

1/16W

5% 402

MF-LF

22

21

R3793

1/16W

5% 402

MF-LF

22

21

R3794

1/16W

5% 402

MF-LF

22

21

R3795

18 92

1/16W

5%

402

MF-LF

4.7K

2

1

R3755

1/16W

5%

402

MF-LF

4.7K

2

1

R3756

1/16W

5%

402

MF-LF

4.7K

2

1

R3752

1/16W

5%

402

MF-LF

4.7K

2

1

R3757

1/16W

5%

402

MF-LF

4.7K

2

1

R3750

1/16W

5%

402

MF-LF

4.7K

2

1

R3751

16V

10% 402

X5R

0.1UF

2

1

C3715

16V

10% 402

X5R

0.1UF

2

1

C3716

0402-LF

FERR-120-OHM-1.5A

CRITICAL

2

1

L3715

16V

10%

402

X5R

0.1UF

2

1

C3711

16V

10%

402

X5R

0.1UF

2

1

C3710

16V

10% 402

X5R

0.1UF

2

1

C3714

50V

5%

402

CERM

10PF

2

1

C3790

1/16W

5%

402 MF-LF

22

21

R3796

18 92

TQFP

RTL8211CLGR

OMIT

45

44

26

25

24

23

27

22

18

17

16

14

13

19

46

48

29

31

11 12

8 9

4 5

1 2

30

38

35

34

473320

7

3

39

372115

36

28

32

43

42

41

6

40

10

U3700

051-7892

9733

A.0.0

SYNC_MASTER=SUMA_M98_MLB

Ethernet PHY (RTL8211CL)

SYNC_DATE=07/01/2008

RTL8211_PHYRST_L

RTL8211_RSET

TP_RTL8211_CKXTAL2

GND

ENET_RESET_L

ENET_CLK125M_RXCLK

ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>

ENET_RX_CTRL

TP_PP3V3_ENET_PHY_VDDREG

NC_RTL8211_REGOUT

ENET_MDI_N<0>

ENET_RXD_R<2>

RTL8211_PHYAD0

RTL8211_RXDLY

RTL8211_PHYAD1

ENET_MDI_N<3>

ENET_RXD_R<1>

ENET_RXD_R<3>

ENET_TXD<0> ENET_TXD<1>

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENET_MDI_P<2> ENET_MDI_N<2>

ENET_RXCTL_R

ENET_MDC

RTL8211_CLK125

RTL8211_CLK25M_CKXTAL1

ENET_MDI_P<0>

ENET_RXD_R<0>

ENET_TXD<3>

ENET_MDIO

ENET_CLK125M_RXCLK_R

PP1V2R1V05_ENET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V

PP1V05_ENET_PHYAVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V

PP3V3_ENET_PHYAVDD

ENET_TXD<2>

PP3V3_ENET_PHY

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_CLK125M_TXCLK_R

9

92

9

92

7 8

18 24 34 37

7 8

18 24 34

G

DS

IN

OUT

D

SG

IN

D

S G

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1.8V Vgs

ARB for alternate power options.

=P3V3ENET_EN. Nets separated on

Recommend aliasing PM_SLP_RMGT_L and

1.05V ENET FET

WLAN Enable Generation

Recommend aliasing PM_SLP_RMGT_L and

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

RTL8211 25MHz Clock

=P1V05ENET_EN. Nets separated on

I(max) = 1.7A (85C)

3.3V ENET FET

Rds(on) = 90mOhm max

MOBILE:

@ 2.5V Vgs:

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

Non-ARB:

Pull-up is with power FET.

SOT-23-HF

NTR4101P

CRITICAL

2

1

3

Q3810

16V

10%

402

CERM

0.01UF

2 1

C3810

16V

10%

402

X5R

0.033UF

2

1

C3811

1/16W

5%

402

MF-LF

100K

21

R3810

18 92

1/16W

5%

402

MF-LF

22

PLACEMENT_NOTE=Place close to U1400

21

R3895

33 92

16V

10% 402

CERM

0.01UF

2

1

C3841

10V

20%

402

CERM

0.1UF

2

1

C3840

31

SOT563

SSM6N15FEAPE

4

5

3

Q3805

21 37 42 43

SOT563

SSM6N15FEAPE

1

2

6

Q3801

21 31

7

21 37 42 69 82 84

SOT563

SSM6N15FEAPE

1

2

6

Q3805

SOT563

SSM6N15FEAPE

1

2

6

Q3841

1/16W

1%

402

MF-LF

69.8K

2

1

R3842

SOT23

SI2312BDS

CRITICAL

2

1

3

Q3840

1/16W

5%

402

MF-LF

10K

2

1

R3800

SOT563

SSM6N15FEAPE

4

5

3

Q3801

9

21 34

SOT563

SSM6N15FEAPE

4

5

3

Q3841

9

21 34

1/16W

1%

402

MF-LF

10K

21

R3841

1/16W

5%

402

MF-LF

100K

21

R3840

SYNC_DATE=07/01/2008

SYNC_MASTER=SUMA_M98_MLB

34 97

A.0.0

051-7892

Ethernet & AirPort Support

PM_WLAN_EN_L

P3V3ENET_EN_L

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

P3V3ENET_SS

PP3V3_ENET_PHY

PP3V3_S5

AP_PWR_EN

AC_OR_S0_L

SMC_ADAPTER_EN

PM_SLP_S3_L

PM_SLP_RMGT_L

P1V05ENET_EN_L

P1V05ENET_SS

PP3V3_S5

P1V05ENET_EN_L_RC

PP1V2R1V05_ENET

PP1V2R1V05_S5

7 8

18 24 33

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 87 96

7 8

18 24 33 37

7 8

22 24 68

BI

RX

TX

BI

RX

TX

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOM options provided by this page:

Power aliases required by this page: (NONE)

Page Notes

Place one of 0.1uf cap close to each centertap pin of transformer

(NONE)

Transformers should be

(NONE)

Signal aliases required by this page:

514-0636

sides of the board

mirrored on opposite

33 92

CRITICAL

TLA-6T213HF

SM

9

8

76

5

4

3

2

12

11

10

1

T3900

1/16W

5%

402

MF-LF

75

2

1

R3900

1/16W

5%

402

MF-LF

75

2

1

R3901

1/16W

5% 402

MF-LF

75

2

1

R3902

1/16W

5% MF-LF

75

402

2

1

R3903

2KV

10%

1206

CERM

1000PF

CRITICAL

21

C3908

33 92

0.1UF

10% 16V

402

X5R

2

1

C3906

16V

10% 402

X5R

0.1UF

2

1

C3904

16V

10% 402

X5R

0.1UF

2

1

C3902

SM

TLA-6T213HF

CRITICAL

9

8

76

5

4

3

2

12

11

10

1

T3901

16V

10% 402

X5R

0.1UF

2

1

C3900

F-RT-TH

CRITICAL

RJ45-M97-3

9

8

7

6

5

4

3

2

12

11

10

1

J3900

CRITICAL

402-1

10PF

50V

5% CERM

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

2

1

C3910

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

2

1

C3941

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

2

1

C3940

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

402-1

10PF

CERM

5% 50V

2

1

C3931

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

2

1

C3930

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

2

1

C3921

CRITICAL

CERM

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

5% 50V

402-1

2

1

C3920

33 92

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

2

1

C3911

33 92

A.0.0

35

051-7892

97

Ethernet Connector

SYNC_DATE=12/16/2008

SYNC_MASTER=AMASON_M98_MLB

ENET_MDI_N<0>

ENETCONN_CTAP

ENET_MDI_N<2>

ENET_MDI_P<0>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENETCONN_P<0> ENETCONN_N<0>

ENETCONN_N<1>

ENET_MDI_N<3>

ENET_CTAP0

ENETCONN_N<3>

ENET_MDI_P<2>

ENET_CTAP3

ENET_CTAP2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

ENET_BOB_SMITH_CAP

ENET_MDI_N<1>

ENET_CTAP1

ENETCONN_N<2>

ENETCONN_P<1>

ENETCONN_P<3>

ENETCONN_P<2>

96

DS2

ATBUSH ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620* JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK SCIFDAIN SCIFDOUT

SCIFMC

SCL SDA

SE SM

TDO

TPA1N

TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P

TPBIAS0 TPBIAS1 TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC NC NC

NC

IN IN

IN

OUT

IN IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

IN

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

135 mA

(IPD) NT-21

(IPD) NT-18

NT-6

NT-2 (IPU)

NT-1 (IPU)

NT-13

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-3 (IPU)

NAND tree order.

NOTE: NT-xx notes show

110 mA Digital Core

(IPU)

NT-15 (IPD)

(IPD) NT-11

(IPU) NT-8

(IPD)

138 mA

7 mA I/O

114 mA FireWire PHY

0 mA VReg PWR

17 mA PCIe SerDes25 mA PCIe SerDes

NT-4 (IPU)

(OD)

NT-16 (IPD)

NT-17

NT-5

NT-14 (IPD)

NT-OUT

(Reserved)

NT-9

(IPD) NT-19 (IPD) NT-20

(IPU)

NT-12 (IPD)

NT-10 (IPD)

NT-7

(IPD)

R4170

1

2

1/16W

1%

402

MF-LF

191

C4162

1

2

6.3V

10% 402

CERM-X5R

0.33UF

R4162

1

2

MF-LF

1/16W

5%

402

470K

U4100

B13 A13 A11

A10

L13

L2

F12 E12 E13

D12

K13

D1

J2

K1

J12 J13

N8 N7 N5 N6

N4

B11

N9 N10

D13

L8

G2 G1 H1 F2

N12 M11

M13 N13

M4 N2 M1 M3

B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4

B7 C3 A2

B10

N1

E1 D2

H13

A1

B1

M12N3N11

B12

C13E2E10H2H12K2L1

C1

C12F1G12J1L3

L11M2A12D5D6D8L5

L10L6L9

K12

L12

B2

D4

F7

F8

F10

G4G6G7

G8

G10

H4

H6D7H7

H8

H10

J4J5J9

J10

K4K5K7D9K8K9L7

K6

K10

D10

E4E5E9F4F6

C2

G13

F13

BGA

FW643

CRITICAL

OMIT

C4151

1 2

50V

5%

402

CERM

22PF

C4150

1 2

50V

5%

402

CERM

22PF

R4160

1

2

1/16W

1%

402

MF-LF

200K

R4150

1 2

1/16W

1%

402

MF-LF

412

R4163

1

2

1/16W

5%

402

MF-LF

10K

R4164

1

2

1/16W

5%

402

MF-LF

10K

R4165

1

2

1/16W

5%

402

MF-LF

10K

FW643_LDO

C4176

1 2 16V10%

402X5R

0.1UF

PLACEMENT_NOTE=Place C4176 close to U4000

C4175

1 2 16V10%

402X5R

0.1UF

PLACEMENT_NOTE=Place C4175 close to U4000

R4166

1

2

1/16W

5%

402

MF-LF

10K

C4171

1 2 16V10%

402X5R

0.1UF

PLACEMENT_NOTE=Place C4171 close to U1400

C4170

1 2 16V10%

402X5R

0.1UF

PLACEMENT_NOTE=Place C4170 close to U1400

C4130

1

2

6.3V

10%

402

CERM

1UF

C4131

1

2

6.3V

10%

402

CERM

1UF

C4100

1

2

6.3V 402

CERM

1UF

10%

C4101

1

2

6.3V

10% 402

CERM

1UF

C4132

1

2

6.3V

10%

402

CERM

1UF

C4102

1

2

6.3V

10% 402

CERM

1UF

C4103

1

2

CERM

6.3V

10% 402

1UF

C4135

1

2

6.3V

10% 402

CERM

1UF

C4136

1

2

6.3V

10% 402

CERM

1UF

C4104

1

2

6.3V

10% 402

CERM

1UF

C4110

1

2

6.3V

10% 402

CERM

1UF

C4105

1

2

6.3V

10% 402

CERM

1UF

C4106

1

2

6.3V

10% 402

CERM

1UF

C4120

1

2

6.3V

10%

402

CERM

1UF

C4121

1

2

6.3V

10%

402

CERM

1UF

C4122

1

2

6.3V

10%

402

CERM

1UF

C4123

1

2

6.3V

10%

402

CERM

1UF

C4124

1

2

6.3V

10%

402

CERM

1UF

C4141

1

2

10V

20% 402

CERM

0.1UF

C4111

1

2

6.3V

10% 402

CERM

1UF

C4140

1

2

6.3V

10% 402

CERM

1UF

17 90

9

37

R4161

1

2

1/16W

1%

402

MF-LF

2.94K

38

38 93

38

38 93

38

37 38

38

L4130

1 2

0402-LF

120-OHM-0.3A-EMI

L4135

1 2

0402-LF

120-OHM-0.3A-EMI

37

L4110

1 2

0402-LF

120-OHM-0.3A-EMI

Y4150

2 4

1 3

24.576MHZ

SM-3.2X2.5MM

CRITICAL

R4100

1 2

402

MF-LF

1/16W

0.2

1%

OMIT

114S0557

1

R4100

CRITICAL

RES,0.475 ohm,1%,1/16W,0402

FireWire LLC/PHY (FW643)

SYNC_MASTER=SENSOR

36 97

4.12.0

051-7892

SYNC_DATE=08/14/2008

FW_CLK24P576M_XI

FW_CLKREQ_PHY_L

TP_FW643_SCIFDAIN

FW643_SCL

TP_FW643_MODE_A TP_FW643_CE

TP_FW643_JASI_EN

TP_FW643_TCK

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_FW_D2R_C_P

PCIE_FW_D2R_C_N

TP_FW643_TDO

FW643_TPCPS

TP_FW643_NAND_TREE

TP_FW643_SE

PP1V0_FW_FWPHY_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_FW_FWPHY_VDDA

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_R2D_P

PCIE_FW_R2D_C_P

PCIE_FW_R2D_N

PCIE_FW_R2D_C_N

NC_FW0_TPAN NC_FW0_TPAP

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_FW_FWPHY_VP25

NC_FW0_TPBP

FW_P1_TPBIAS

FWPHY_DS1

PP3V3_FW_FWPHY

FWPHY_DS0

FWPHY_DS2

FW643_REXT FW_CLK24P576M_XO_R

NC_FW2_TPBIAS

NC_FW0_TPBIAS

NC_FW2_TPBP

FW_PORT1_TPB_P

FW_PORT1_TPB_N

NC_FW0_TPBN

NC_FW2_TPAP

NC_FW2_TPAN

FW_PORT1_TPA_N FW_PORT1_TPA_P

TP_FW643_VBUF

TP_FW643_SM

TP_FW643_SCIFCLK

TP_FW643_FW620_L

TP_FW643_AVREG

TP_FW643_TDI

TP_FW643_TMS

TP_FW643_OCR10_CTL

PPVP_FW_CPS

FW_CLK24P576M_XO

PP3V3_FW_FWPHY

TP_FW643_SCIFMC

TP_FW643_SCIFDOUT

FW643_VAUX_DETECT

FW643_TRST_L

TP_FW643_VAUX_ENABLE

FW643_REGCTL

FW_RESET_L

TP_FW643_SDA

FW643_WAKE_L

FW643_PU_RST_L

NC_FW2_TPBN

FW643_R0

PP1V0_FW

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

PP1V0_FW_R

90

8

36 37 38

38

8

36 37 38

8

37

D

SG

IN

D

SG

V-

V+

E

Q2

C

BD

Q1

GS

G

D

S

G

D

S

IN

G

DS

D

SG

D

SG

D

SG

D

S

G

IN

D

SG

D

SG

OUT

IN

OUT

IN

G

D

S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT OF

SIZE

D

1.05V FW FET

Enables port power when machine is running or on AC.

Rds(on) = 90mOhm max

(NONE)

PP1V05_FW PGOOD/FW_RESET_L

I(max) = 1.7A (85C)

@ 2.5V Vgs:

3.3V FW FET

FireWire Port Power Switch

2.91V when late Vg event and port power is off

3.08V when port power is on

FWLATEVG Hysteresis:

BOM options provided by this page:

Signal aliases required by this page:

- =PPVP_FW_SUMNODE (power passthru summation node)

- =PP3V3_FW_LATEVG_ACTIVE

- =PPBUS_S5_FWPWRSW (system supply for bus power)

Power aliases required by this page:

Page Notes

Late-VG Event Detection

CERM 402

0.1UF

20% 10V

2

1

C4210

MF-LF

200K

402

1%

1/16W

21

R4210

10K

MF-LF

402

5%

1/16W

2

1

R4211

100pF

CERM

402

5%

50V

2

1

C4211

1/16W MF-LF 402

1%

10K

2

1

R4212

MF-LF

1% 1/16W

402

80.6K

2

1

R4213

SOI-HF

NDS9407

CRITICAL

3 2 1

4

8 7 6 5

Q4260

10%

0.1UF

X5R

25V 402

2

1

C4260

SSM6N15FEAPE

SOT563

4

5

3

Q4261

21 34 42 43

7 21 34 42 69 82 84

SOT563

SSM6N15FEAPE

1

2

6

Q4261

5%

10K

MF-LF

402

1/16W

2 1

R4265

NOSTUFF

100

1%

402

1/16W MF-LF

21

R4263

470K

5% 1/16W MF-LF 402

2

1

R4260

MF-LF 402

330K

5% 1/16W

2

1

R4261

NOSTUFF

402-1

X5R

1UF

10% 10V

2

1

C4263

LMC7211

SM-HF

2

5

1

3

4

U4210

SOT-563

DMB54D0UV

CRITICAL

1 2

46

3

5

Q4262

MINISMDC110H24

1.1A-24V

CRITICAL

21

F4260

CRS08-1.5A-30V

CRITICAL

SM

21

D4260

CRITICAL

BC847CDXV6TXG SOT563

1

6

2

Q4270

CRITICAL

SOT563

BC847CDXV6TXG

4

3

5

Q4270

330K

1/16W 402

5% MF-LF

2

1

R4270

56K

MF-LF 402

5% 1/16W

2

1

R4271

5%

402

MF-LF

100K

1/16W

2

1

R4274

12K

402

MF-LF

1/16W

5%

2

1

R4273

1/16W

1K

5%

402

MF-LF

2

1

R4272

CRITICAL

DMB53D0UV

SOT-563

1

2

6

Q4275

CRITICAL

DMB53D0UV

SOT-563

4

3

5

Q4275

DMB53D0UV

SOT-563

CRITICAL

1

2

6

Q4299

402

5%

MF-LF

1/16W

10K

21

R4283

17 26

6.3V

1UF

10%

CERM

402

2

1

C4281

SOT-563

DMB53D0UV

CRITICAL

4

3

5

Q4299

10K

1/16W

1%

MF-LF

402

21

R4280

402

100K

5% MF-LF

1/16W

2

1

R4281

10K

5%

402

MF-LF

1/16W

2

1

R4290

100K

MF-LF

402

5%

1/16W

21

R4291

16V

10%

402

X5R

0.033UF

2

1

C4290

NTR4101P

SOT-23-HF

CRITICAL

2

1

3

Q4291

10% 16V

402

CERM

0.01UF

2 1

C4291

SSM6N15FEAPE

SOT563

4

5

3

Q4290

SSM6N15FEAPE

SOT563

4

5

3

Q4293

1/16W

10K

MF-LF

402

5%

2

1

R4295

1/16W

402

100K

MF-LF

5%

21

R4296

220K

1/16W MF-LF

402

5%

21

R4297

SSM6N15FEAPE

SOT563

1

2

6

Q4293

NOSTUFF

0.068UF

CERM 402

10% 10V

2

1

C4295

CRITICAL

SI2312BDS

SOT23

2

1

3

Q4295

36 37

SSM6N15FEAPE

SOT563

1

2

6

Q4264

SOT563

SSM6N15FEAPE

4

5

3

Q4264

9 17

17

16V X5R 402

0.1UF

10%

2

1

C4270

36 38

9 19 37

36

19 37

0.1UF

CERM

20% 10V

402

2

1

C4296

402

1K

5% MF-LF

1/16W

2

1

R4275

19 37

DMB53D0UV

CRITICAL

SOT-563

4

3

5

Q4276

CRITICAL

DMB53D0UV

SOT-563

1

2

6

Q4276

402

5% 1/16W MF-LF

100K

2

1

R4276

NOSTUFF

0.1UF

10% 16V X5R 402

2

1

C4276

10K

MF-LF

5%

1/16W

402

2

1

R4277

FireWire Port Power

SYNC_MASTER=YUN_K19_MLB

SYNC_DATE=12/22/2008

9737

051-7892

A.0.0

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_FW_FWPWRSW_D

MIN_LINE_WIDTH=0.5 mm

PPBUS_FW_FWPWRSW_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_G3H

LATEVG_FAULT_EVENT_PNP

LATEVG_FAULT_EVENT

LATEVG_EVENT

SMC_ADAPTER_EN

P1V05_FW_EN_L

FW_PLUG_DET_L

FW_WAKE

PP3V3_FW_FWPHY

FW643_WAKE_L

FW_PWR_EN

PP3V3_S5

P2V4_FWLATEVG_RC

LATEVG_RETRY_RC

FWLATEGV_3V_REF

FWPWR_EN_L_DIV

PPVP_FW

PP3V3_S0

PP1V0_FW

FW_RESET_L

P1V0_RESET_GATE

P1V0_FW_RC

PP3V3_FW_FWPHY

PM_SLP_S3_L

FWPWR_EN_L

PCIE_RESET_L

PP2V4_FW_LATEVG

FW_PLUG_DET_L

FW_PWR_EN

FW_P1_TPBIAS

FW_DET_EMIT

FW_P1_TPBIAS_R

FW_PLUG_DET

PP1V2R1V05_ENET

FW_DET_MIRROR

FW_PWR_EN_L

PP3V3_S0

P3V3FW_SS

P3V3FW_EN_L

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

FW_CLKREQ_L

PP1V2R1V05_ENET

PP1V0_FW

P1V05FW_SS

P1V05_FW_EN_L_RC

PP3V3_FW_FWPHY

FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

FW_CLKREQ_PHY_L

FW_PWR_EN

PP3V3_S5

FW_PWR_EN

7 8 46 61 62 64 65 66 67 79 83 86

9 19 37

8 36 37 38

9 36

7 8 18 20 22

24 26 30 34

37 38 44 54

64 68 69 70

82 87 96

8 38

6 7 8 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

8 36 37

8 36 37 38

7 8 18 24 33 34 37

6 7 8 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

7 8 18 24 33 34 37

8 36 37

8 36 37 38

36

37

19 37 7 8 18 20 22 24 26

30 34 37 38 44 54 64

68 69 70 82 87 96

19 37

SC/NC

TPA+

TPA(R)

VG

VPTPB+

TPB(R)

TPB-

TPA-

CHASSIS

GND

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

constrained on this page. It is

provide the appropriate constraints

Configures PHY for:

"Snapback" & "Late VG" Protection

NOTE: This page is expected to contain

- 1-port Portable Power Class (0)

- Port "1" Bilingual (1394B)

Power aliases required by this page:

Page Notes

for snap-back diodes

Late-VG Protection Power

PP2V4_FWLATEVG needs to be biased to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin

assumed that FireWire PHY page will

to apply to entire TPA/TPB XNets.

Termination

FW spec calls out 0.33uF

Place close to FireWire PHY

TI PHYs require 1uF even though

- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

514S0605

beta-only device, there is no DC path between them (to avoid ground offset issue)

BREF should be hard-connected to logic ground for speed signaling and connection

appropriate connectors and/or to

NOTE: FireWire TPA/TPB pairs are NOT

Cable Power

(GND_FW_PORT1_VG)

(FW_PORT1_BREF)

AREF needs to be isolated from all

INPUT

NC

TPB<R>

TPB-

TPA-

TPA+

ESD and late-VG rail

(Common to all ports)

(NONE)

OUTPUT

BILINGUAL

- =GND_CHASSIS_FW_EMI_R

(NONE)

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple

the necessary aliases to map the FireWire TPA/TPB pairs to their

- =GND_CHASSIS_FW_PORT1

PORT 1

Signal aliases required by this page:

BOM options provided by this page:

properly terminate unused signals.

R4390 should be 390 Ohms max for a 3.3V rail

FireWire PHY Config Straps

NC

VP

TPB+

VG

TPA<R>

When a bilingual device is connected to a

Note: Trace PPVP_FW_PORT1 must handle up to 5A

local grounds per 1394b spec

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

2

1

R4363

4.99K

MF-LF

402

1%

1/16W

2

1

R4364

SIGNAL_MODEL=EMPTY

56.2

MF-LF 402

1% 1/16W

2

1

R4362

220pF

CERM 402

5% 25V

2

1

C4364

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

2

1

R4361

0.33UF

CERM-X5R 402

10%

6.3V

2

1

C4360

SIGNAL_MODEL=EMPTY

56.2

MF-LF 402

1% 1/16W

2

1

R4360

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

0.1uF

X7R

603-1

10% 50V

2

1

C4319

1M

MF-LF 402

5% 1/16W

2

1

R4319

0.01UF

X7R 402

10% 50V

2

1

C4314

CRITICAL

FERR-250-OHM

SM

21

L4310

0.01uF

X7R 402

10% 50V

2

1

C4310

CRITICAL

BAV99DW-X-G

SOT-363

6

2

1

DP4310

0.01uF

X7R 402

10% 50V

2

1

C4311

CRITICAL

BAV99DW-X-G

SOT-363

3

5

4

DP4310

CRITICAL

BAV99DW-X-G

SOT-363

6

2

1

DP4311

CRITICAL

BAV99DW-X-G

SOT-363

3

5

4

DP4311

0.01uF

X7R 402

10% 50V

2

1

C4313

0.01uF

X7R 402

10% 50V

2

1

C4312

332

MF-LF

402

1%

1/16W

21

R4390

CRITICAL

MMBZ5227BLT1H

SOT23

3

1

D4390

CRITICAL

1394B-M97

F-RT-TH

9

8 7 6

5 4

3

2

13

12

11

10

1

J4310

10K

MF-LF

402

1%

1/16W

2

1

R4381

10K

MF-LF

402

1%

1/16W

2

1

R4382

10K

MF-LF

402

1%

1/16W

2

1

R4380

BSS8402DW

SOT-363

4

5

3

Q4300

BSS8402DW

SOT-363

1

2

6

Q4300

330K

MF-LF

402

5%

1/16W

2

1

R4312

470K

MF-LF

402

5%

1/16W

2

1

R4311

SYNC_DATE=08/14/2008

SYNC_MASTER=SENSOR

FireWire Ports

051-7892

A.0.0

38 97

PPVP_FW_PORT1_F

VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

FW_PORT1_TPA_P

FW_PORT1_AREF

PP2V4_FW_LATEVG

PPVP_FW_CPS

VOLTAGE=12.6V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

FW_P1_TPBIAS

FW_PORT1_TPB_P

MAKE_BASE=TRUE

NC_FW0_TPBN

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW0_TPBIAS NC_FW2_TPBIAS NC_FW0_TPAN

NC_FW2_TPAP

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPBN

NC_FW2_TPBN

FW_PORT1_TPB_P

NC_FW0_TPBP

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

PP2V4_FW_LATEVG

VOLTAGE=2.4V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

FW_PORT1_TPB_C

FW_PORT1_TPB_N

PP3V3_S5

PPVP_FW

FW_PORT1_TPA_P

FWPHY_DS1

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS2

FWPHY_DS1

FWPHY_DS0

PP3V3_FW_FWPHY

NC_FW0_TPBP

MAKE_BASE=TRUE

NC_FW2_TPAN

NC_FW0_TPAP

NC_FW2_TPBN

MAKE_BASE=TRUE

NC_FW2_TPBP NC_FW2_TPBP

MAKE_BASE=TRUE

FW_PORT1_TPA_N

PPVP_FW_CPS

PPVP_FW

PP3V3_FW_FWPHY

CPS_EN_L

CPS_EN_L_DIV

FW_PORT1_TPB_N

FW_PORT1_TPB_P

FW_PORT1_TPA_N

36 38 93

37 38

36 38

36 37

36 38 93

36 38

36 38 93

36 38

36 38 93

36 38

36 38 93

36 38

36 38 93

36 38

36 38 93

37 38

36 38 93

7 8

18 20 22 24 26 30 34 37

44 54 64 68 69 70 82 87 96

8

37 38

36 38 93

36 38

8

36 37 38

36 38 93

36 38

36 38 93

36 38

36 38 36 38

36 38 93

36 38

8

37 38

8

36 37 38 36 38 93

36 38 93

OUT

IN

BI

S

G

D

OUT

IN

SYM_VER-1

OUT

IN

D

SG

D

SG

SYM_VER-1

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Indicates disc presence

516S0687

516S0616

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

SATA ODD Port

SATA HDD Port

ODD Power Control

ensure the drive is unpowered in S3/S5.

10% 50V

0.001UF

CERM 402

2

1

C4531

4.7

402

1/16W

MF-LF

5%

2 1

R4531

7

41

27 42 45 94

CRITICAL

TPCP8102

23V1K-SM

321

4

8765

Q4590

10% CERM

6.3V 402

1UF

2

1

C4503

FERR-220-OHM

0402

21

L4502

SM

2

1

XW4503

SM

21

XW4504

SM

21

XW4505

SM

21

XW4500

SM

2

1

XW4502

SM

2

1

XW4501

7

42

MF-LF

402

5%

1/16W

33K

2

1

R4590

F-ST-SM

54722-0164

CRITICAL

9

87

65

43

2

1615

1413

1211

10

1

J4500

21

PLACEMENT_NOTE=Place FL4520 close to J4500

CRITICAL

90-OHM-100MA

DLP11S

43

2 1

FL4520

CRITICAL

90-OHM-100MA

DLP11S

PLACEMENT_NOTE=Place FL4525 close to J4500

4 3

21

FL4525

20 90

SOT563

SSM6N15FEAPE

4

5

3

Q4596

100K

MF-LF

5%

1/16W

402

2

1

R4597

SSM6N15FEAPE

SOT563

1

2

6

Q4596

100K

MF-LF

5%

1/16W

402

2

1

R4596

100K

MF-LF

402

5%

1/16W

21

R4595

0.068UF

CERM 402

10% 10V

2

1

C4595

10%

0.01UF

CERM

402

16V

21

C4596

0.01UF

CERM

40210% 16V

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

21

C4521

0.01UF

CERM

40210% 16V

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

21

C4520

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

CERM

10% 16V

0.01UF

402

21

C4526

0.01UF

40210%16V

CERM

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

21

C4525

0603

FERR-70-OHM-4A

CRITICAL

21

L4500

0.1UF

20% 10V CERM 402

2

1

C4501

CRITICAL

90-OHM-100MA

DLP11S

43

2 1

FL4501

402

0.1UF

CERM

20% 10V

2

1

C4502

DLP11S

CRITICAL

90-OHM-100MA

4 3

21

FL4502

20 90

0.01UF

CERM

40210% 16V

21

C4516

0.01UF

40210%16V

CERM

21

C4510

0.01UF

40210%16V

CERM

21

C4511

0.01UF

CERM

40210% 16V

21

C4515

53 96

54722-0224

F-ST-SM

9

87 65 43

2221 20

2

19

1817 1615 1413 1211 10

1

J4501

MF-LF

1/16W

5%

10

402

2 1

R4532

0.1UF

16V

10%

402

X7R-CERM

2

1

C4532

051-7892

A.0.0

9739

SATA Connectors

SYNC_MASTER=PWRSQNC

SYNC_DATE=12/04/2008

PP5V_S0

PP5V_S0_HDD_R

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm VOLTAGE=5V

ISNS_HDD_N

ISNS_HDD_P

PP5V_SW_ODD_R

VOLTAGE=5V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm

ISNS_ODD_P

ISNS_ODD_N

PP5V_SW_ODD

VOLTAGE=5V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm

ODD_PWR_SS

PP5V_S0

IR_RX_OUT

SATA_HDD_D2R_C_N

PP5V_S3

SYS_LED_ANODE

PP3V3_S0

ODD_PWR_EN_L

SATA_HDD_D2R_UF_N

SATA_HDD_R2D_UF_P

SATA_ODD_D2R_UF_N

PP3V3_S0

ODD_PWR_EN

SATA_ODD_D2R_N

SATA_ODD_R2D_UF_P

ODD_PWR_EN_LS5V_L

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_P

SATA_ODD_R2D_N

SATA_ODD_R2D_P

SATA_ODD_D2R_P

SATA_HDD_D2R_C_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_HDD_R2D_UF_N

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

SMC_ODD_DETECT

SATA_HDD_R2D_N

SATA_HDD_R2D_P

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm VOLTAGE=5V

PP5V_S0_HDD_FLT

PP5V_S3_IR_R

SYS_LED_ANODE_R

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

PP1V8R1V5_S0_FET

VOLTAGE=1.5V MIN_NECK_WIDTH=0.3mm

MIN_LINE_WIDTH=0.6mm

PP1V5_S0_HDD_FLT

PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

PLACEMENT_NOTE=Place FL4501 close to J4501

PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=Place C4516 close to J4501

PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510

PLACEMENT_NOTE=Place C4515 next to C4516

7 8

39 44 49 51 63 66 67 70

83 85

7

53

7 8

39 44 49 51 63 66 67 70

83 85

7

90

7 8 9

31 40 41 43 51 53 55 64

65 70 79

43

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

96

7

96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

96

7

96

7

90

7

90

7

90

96

7

90

7

90

7

7 7

7 8

11 12 16 24 28 29 68

69 70

OUT

BI

SYM_VER-1

IN OUT

IN

SYM_VER-1

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1 OC2*

IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

514-0606

We can add protection to 5V if we want, but leaving NC for now

Place L4600 and L4605 at connector pin

Left USB Port B

Port Power Switch

SEL=1 Choose USB

SEL=0 Choose SMC

Left USB Port A

USB/SMC Debug Mux

0603

FERR-220-OHM-2.5A

CRITICAL

21

L4605

6.3V

20%

CASE-B2-SM

POLY-TANT

100UF

CRITICAL

2

1

C4696

6.3V

20% 603

X5R

10UF

2

1

C4695

10V

20%

402

CERM

0.1UF

2

1

C4691

20

20 91

10V

20%

402

CERM

0.1UF

SMC_DEBUG_YES

2

1

C4650

1/16W

5%

402

MF-LF

10K

2

1

R4650

DLP11S

90-OHM-100MA

CRITICAL

4 3

21

L4600

42 43 44

42

1/16W

5%

402

MF-LF

0

SMC_DEBUG_NO

21

R4651

1/16W

5%

402

MF-LF

0

SMC_DEBUG_NO

21

R4652

16V

20% 402

CERM

0.01uF

2

1

C4605

16V

20% 402

CERM

0.01uF

2

1

C4615

0603

FERR-220-OHM-2.5A

CRITICAL

21

L4615

DLP11S

90-OHM-100MA

CRITICAL

4 3

21

L4610

6.3V

20%

603

X5R

10UF

2

1

C4617

6.3V

20%

CASE-B2-SM

POLY-TANT

100UF

CRITICAL

2

1

C4616

20 91

20

SLP1210N6

RCLAMP0502N

CRITICAL

6

32 45

1

D4600

SLP1210N6

RCLAMP0502N

CRITICAL

6

32 45

1

D4610

6.3V

20%

603

X5R

10UF

2

1

C4690

F-RT-TH-M97-4

USB

CRITICAL

8

7

6

5

4

3

2

1

J4600

F-RT-TH-M97-4

USB

CRITICAL

8

7

6

5

4

3

2

1

J4610

MSOP

TPS2064DGN

CRITICAL

9

6

7

5

8

2

1

4

3

Q4690

1/16W

5%

402

MF-LF

5.1K

2

1

R4690

10V

10%

402

X5R

0.47UF

2

1

C4692

TQFN

PI3USB102ZLE

CRITICAL

SMC_DEBUG_YES

SIGNAL_MODEL=USB_MUX

1 2

9

10

8

5 4

3

7 6

U4650

SYNC_MASTER=M98_MLB

External USB Connectors

051-7892

A.0.0

9740

SYNC_DATE=11/14/2008

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_A_F

USB2_LT1_N

USB2_LT1_P

USB_EXTB_OC_L

USB_EXTA_N

USB_EXTA_P

SMC_RX_L SMC_TX_L

PP3V42_G3H

USB_PWR_EN

PP5V_S3

PM_SLP_S4_L

USB_EXTB_N

USB_EXTB_P

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_A_ILIM

USB_EXTA_OC_L

USB_DEBUGPRT_EN_L

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

USB_LT2_N

USB_LT2_P

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_B_F

96

7 8

21 22 26 42

43 44 45 46 50 61

62 64 69

7 8 9

31 39 41 43 51 53 55 64

65 70 79

7

21 42 43 69 70

96

BI BI

VCC

P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK

P1.5/SMOSI

P1.6/SMISO

P0.0

P0.1 INT0/P0.2 INT1/P0.3

TIO1/P0.6

NC

TIO0/P0.5

INT2/P0.4

VSSPAD

THRML

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

IR SUPPORT

20 91

10V

10% 402-1

X5R

1UF

2

1

C4803

CRITICAL

OMIT

QFN

CY7C63803-LQXC

11

14

1

2

25

19

18

17

16

15

13

12

6

7

24

23

22

21

20

10

9

8

3

4

5

U4800

16V 402

0.1UF

10% X7R-CERM

2

1

C4801

50V

10%

402

CERM

0.001UF

2

1

C4804

1/16W

5%

402

MF-LF

100

21

R4800

7

39

Front Flex Support

051-7892

A.0.0

9741

SYNC_DATE=12/04/2008

SYNC_MASTER=PWRSQNC

IR_RX_OUT_RC

IR_RX_OUT

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_P

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_N

IR_VREF_FILTER

PP5V_S3

P/N 338S0633

7 8 9

31 39 40 43 51 53 55 64

65 70 79

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT

IN

OUT

BI

IN

OUT

BI OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(OC) (OC)

(OC)

(OC) (OC)

(DEBUG_SW_2)

(DEBUG_SW_1)

(OC)

(OC) (OC)

(OC)

(See below)

SMC_PB3: SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

those designated as inputs require pull-ups.

NOTE: Unused pins have "SMC_Pxx" names. Unused

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

NOTE: P94 and P95 are shorted, P95 could be spare.

pins designed as outputs can be left floating,

22UF

805

CERM

20%

6.3V

2

1

C4902

19 44

43 44

43 50

10% 402

CERM-X5R

0.47UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

6.3V 2

1

C4907

10V 402

0.1UF

CERM

20%

2

1

C4903

10V 402

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

0.1UF

CERM

20%

2

1

C4920

402

MF-LF

5%

1/16W

4.7

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

21

R4999

10V 402

0.1UF

CERM

20%

2

1

C4904

SM

2 1

XW4900

21

63

10V 402

0.1UF

CERM

20%

2

1

C4905

21

69

26 69

43

10V 402

0.1UF

CERM

20%

2

1

C4906

46

47

46

43 47

43

43 61 62

40 42 43 44

7

64 69

27 39 45 94

402

1/16W

5%

MF-LF

10K

2

1

R4909

44

402

1/16W

5%

10K

MF-LF

2

1

R4901

402

10K

MF-LF

5% 1/16W

2

1

R4902

402

1/16W

5% MF-LF

0

NO STUFF

2

1

R4903

402

1/16W

5% MF-LF

10K

2

1

R4998

40

61

21

7

39

43

21

43

49

43

49

52

43 47

52

43 46

43 47

43 44

43

43 44

43 50 61

7

45 61 62 94

7

45 61 62 94

7

31 45 51 94

7

31 45 51 94

45 48 94

43

43 47

40 42 43 44

43

77

19 44

21 28 29

26

44

21

19 44

77

52

21 34 37 43

7

43 61

43

9

43

H8S2117

OMIT

LGA-HF

F1

F4

G4

H4

G1

H2

G3

J4

C6

B5

A6

D5

C7

B6

A7

L12

N13

M13

N12

N11

L10

M11

N10

H12

J11

J10

K13

J12

K11

K12

L13

E4

F3

G2

C3

C1

B2

C2

A1

B4

A5

D4

D6

D7

D8

A8

B7

C8

D9

A9

E10

F13

E12

E13

F11

D12

E11

D13

D10

C12

C13

D11

B13

A12

A13

B12

U4900

H8S2117

OMIT

LGA-HF

C4

B3

A4

J2

F2

E2

L6

M7

N6

K6

K7

K8

N7

M8

M4

L4

N4

M5

L5

M6

N5

K5

K4

J1

K2

J3

K1

L7

K9

N8

M9

L8

K10

N9

M10

J13

H11

G12

G10

H13

F12

G13

G11

A11

C11

B10

C10

A10

B9

C9

B8

L2

K3

L1

N2

M2

M3

N1

N3

U4900

H8S2117

OMIT

LGA-HF

A3

C5

B11

F10

L3

D2

E1

H10

M1

B1

D3

E3

E5

H1

D1

A2

H3

L9

L11

M12

U4900

19 44 84 91

26

26 91

51

45 48 53 78 94

7

21 34 37 69 82 84

7

21 40 42 43 69 70

7

21 40 42 43 69 70

26 91

45 48 53 78 94

27 39 45 94

43

SYNC_DATE=12/12/2008

SYNC_MASTER=T18_MLB

051-7892

A.0.0

9742

SMC

SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L

SMC_RESET_L

SMC_NMI

SMC_VCL

PP3V42_G3H

SMC_KBC_MDE

SMC_MD1

SMC_TRST_L

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

SMC_EXTAL

SMC_XTAL

PM_CLK32K_SUSCLK

SMBUS_SMC_B_S0_SCL

SMC_PA5

MEM_EVENT_L

SMC_PA0

SMC_PA1 PM_SYSRST_L USB_DEBUGPRT_EN_L

SYS_ONEWIRE PM_BATLOW_L

SMC_RUNTIME_SCI_L SMC_ODD_DETECT

SMC_IG_THROTTLE_L SMC_EXCARD_CP

SMC_EXCARD_OC_L SMC_GFX_OVERTEMP_L

SMC_FAN_0_CTL SMC_FAN_1_CTL NC_SMC_FAN_2_CTL NC_SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH NC_SMC_FAN_2_TACH NC_SMC_FAN_3_TACH

SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_GPU_1V8_ISENSE SMC_MCP_CORE_ISENSE SMC_MCP_DDR_ISENSE SMC_MCP_VSENSE SMC_CPU_HI_ISENSE

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS

SMC_SYS_LED SMC_LID

SMC_MCP_SAFE_MODE

SMS_INT_L SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL SMBUS_SMC_B_S0_SDA

SMC_PROCHOT SMC_THRMTRIP SMC_PH2 NC_ALS_GAIN

RSMRST_PWRGD

PM_RSMRST_L IMVP_VR_ON

SMC_PROCHOT_3_3_L

NC_EXCARD_PWR_EN TP_SMC_RSTGATE_L ALL_SYS_PWRGD

PM_PWRBTN_L NC_ESTARLDO_EN

TP_SMC_P24

SMC_BMON_MUX_SEL

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

LPC_CLK33M_SMC LPC_SERIRQ

TP_SMC_P41 SMBUS_SMC_MGMT_SDA SMS_PWRDN

SMC_GFX_THROTTLE_L SMC_SYS_KBDLED

SMC_TX_L SMC_RX_L SMBUS_SMC_0_S0_SCL

SMC_PM_G2_EN

SMC_ADAPTER_EN

SMC_BIL_BUTTON_L SMC_CPU_ISENSE

SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_CPU_FSB_ISENSE

SMC_WAKE_SCI_L

SMC_TX_L SMC_RX_L SMBUS_SMC_MGMT_SCL

SMC_ONOFF_L SMC_BC_ACOK

PM_SLP_S4_L

SMBUS_SMC_0_S0_SDA

SMC_LRESET_L

LPC_PWRDWN_L

PM_CLKRUN_L

7 8

21 22 26 40 43 44 45 46

50 61 62 64 69

43 46 47

7

43

21 43

43

43 46

43

D

S G

CD

GND

NC

OUT

IN

OUT

IN

OUT

BI

OUT

IN

D

S G

GND

OUT

IN

OUT

IN

02

D

SG

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SMC Reset "Button" / Brownout Detect

Debug Power "Button"

TO SMC

Place R5015,R5001 on bottom side

System (Sleep) LED Circuit

SMC Crystal Circuit

SMC AVREF Supply

SMC FSB to 3.3V Level Shifting

NC

TO CPU

402

20%

CERM

10V

0.1uF

2

1

C5000

SOT563

SSM6N15FEAPE

4

5

3

Q5059

0.47UF

6.3V CERM-X5R

10%

402

2

1

C5020

0.01UF

CERM 402

10% 16V

2

1

C5026

20%

6.3V

10uF

X5R 603

2

1

C5025

0

MF-LF

402

5%

1/16W

21

R5095

10K

MF-LF

4025%

1/16W

21

R5070

100K

MF-LF

4025%

1/16W

21

R5071

10K

MF-LF

402

1/16W

5%

21

R5072

10K

4025%

MF-LF1/16W

21

R5073

100K

402

MF-LF1/16W

5%

21

R5074

10K

5%

MF-LF

402

1/16W

21

R5077

10K

MF-LF

4025%

1/16W

21

R5078

10K

MF-LF

4025%

1/16W

21

R5079

10K

MF-LF

4025%

1/16W

21

R5080

10K

MF-LF

4025%

1/16W

21

R5085

10K

MF-LF

4025%

1/16W

21

R5086

10K

MF-LF

4025%

1/16W

21

R5088

NCP303LSN

CRITICAL

SOT23-5-HF

1

4

2

3

5

U5000

100K

MF-LF

4025%

1/16W

21

R5090

42 44

42

10 14 88

OMIT

MF-LF

5%

603

1/10W

0

SILK_PART=SMC_RST

2

1

R5001

SILK_PART=PWR_BTN

0

MF-LF 603

5% 1/10W

OMIT

2

1

R5015

MF-LF

402

3.3K

5%

1/16W

21

R5062

10 14 63 88

42

SSM6N15FEAPE

SOT563

1

2

6

Q5059

100K

1/16W

4025%

MF-LF

21

R5091

100K

MF-LF

402

1/16W

5%

21

R5092

SOT23-3

CRITICAL

REF3333

21

3

VR5020

42 20

1K

MF-LF 402

5% 1/16W

2

1

R5000

10K

MF-LF

4025%

1/16W

21

R5089

MF-LF

4025%

1/16W

10K

21

R5081

1/16W

0

5%

402

MF-LF

21

R5010

20.00MHZ

CRITICAL

5X3.2-SM

2

1

Y5010

CERM

402

5%

50V

15pF

21

C5011

15pF

CERM

5%

50V 402

21

C5010

470K

MF-LF

402

1/16W

5%

21

R5087

SN74LVC1G02

SOT553-5

4

5

3

2

1

U5001

SSM6N15FEAPE

SOT563

4

5

3

Q5032

1/16W

20

1% MF-LF

402

2

1

R5030

523

MF-LF

402

1%

1/16W

2

1

R5031

402

1/16W

1%

MF-LF

1.47K

2

1

R5032

42

10K

MF-LF

4025%

1/16W

21

R5093

SOT-563

DMB54D0UV

1 2463

5

Q5030

39

DMB53D0UV

SOT-563

1

2

6

Q5060

DMB53D0UV

SOT-563

4

3

5

Q5060

MF-LF

10K

402

5% 1/16W

2

1

R5060

402

100K

5% 1/16W MF-LF

2

1

R5061

100K

5%

MF-LF

402

1/16W

21

R5076

42 43 50

402

0.01UF

10% 16V

CERM

2

1

C5001

SYNC_DATE=12/19/2008

SYNC_MASTER=DDR

SMC Support

051-7892

43 97

A.0.0

353S1912

Intersil ISL60002-33

353S1381

ALL

PP3V42_G3H

SMC_RESET_L

SMC_MANUAL_RST_L

PM_THRMTRIP_L

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

NO_TEST=TRUE

TP_SMC_P41

NC_ALS_GAIN

NC_EXCARD_PWR_EN

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

TP_SMC_P41

MAKE_BASE=TRUE

NC_ALS_GAIN

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

SMC_IG_THROTTLE_L

SMC_MCP_VSENSE

SMC_EXCARD_OC_L

SMS_INT_L

MAKE_BASE=TRUE

SMC_BC_ACOK

PP3V42_G3H

MAKE_BASE=TRUE

NC_EXCARD_PWR_EN

NO_TEST=TRUE

SMS_INT_L

TP_SMC_P24

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

SMC_ONOFF_L

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_ESTARLDO_EN

NO_TEST=TRUE

NC_SMC_FAN_3_CTL

SMC_THRMTRIP

SMC_PROCHOT

SMC_EXCARD_CP

SMC_ADAPTER_EN

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_XTAL_R

EXCARD_OC_L

SMC_TDI

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_2_CTL

SMC_CASE_OPEN

PM_SLP_S4_L

SMC_PA5

PM_SLP_S4_L

SMC_BIL_BUTTON_L

PP3V3_S0

SMS_INT_L

SMC_BC_ACOK

SYS_LED_ANODE

SYS_LED_L

SMC_PA0

NC_ESTARLDO_EN

CPU_PROCHOT_L

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_2_TACH

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_EXTAL

SMC_TPAD_RST

SMC_ONOFF_L

SMC_TPAD_RST_L

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP5V_S3

SYS_LED_ILIM

SYS_LED_L_VDIV

SMC_XTAL

SMC_SYS_LED

SMC_BMON_MUX_SEL

TP_SMC_P24

SMC_BC_ACOK

SMC_PROCHOT_3_3_L

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

SMC_CPU_FSB_ISENSE SMC_GPU_1V8_ISENSE

TP_SMC_RSTGATE_L

CPU_PROCHOT_L_R

CPU_PROCHOT_BUF

PP3V3_S0

SMC_TCK

SMC_TDO

SMC_TMS

SMC_BS_ALRT_L

SMC_RX_L

SMC_TX_L

SMC_PH2

SMC_LID

SMC_ONOFF_L

SMC_PA1

SMC_CPU_HI_ISENSE

PP3V42_G3H

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

42 43

42 43 47

42 43

42 43 47

21 42 43

42 43 46

42 43

42 43 61 62

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

42 43

21 42 43

42 43

42

21 34 37 42

42 43 46

42 44

42 43 42 43

42

7

21 40 42 43 69 70

42

7

21 40 42 43 69 70

7

42 61

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

42 43

42 43 61 62

42

42 43

42 43 42 43

42 43

42

42 43 50

50

42 46 47

7

42

7 8 9

31 39 40 41 51 53 55 64

65 70 79

42

42 43 46

42 43

42 43 61 62

42 43 46

42 43 47

42 43 46

42 43 47

42 43

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

42 44

42

40 42 44

42

42 50 61

42 43 50

42

42 43 46

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

IN

BI

IN OUT OUT OUT

BI BI

IN OUT IN OUT OUT IN OUT IN

OUT OUT OUT

OUT

IN

OUT

IN

OUT

IN

OUT OUT

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

BI

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Pull-up on debug card

LPC+SPI Connector

SPI MUX BYPASS

SEL LOW OUTPUTS TO M (FRANKCARD ROM)

SEL HIGH OUTPUTS TO D (ON BOARD ROM)

Alternate SPI ROM Support

516S0573

44

19 42

42 43

LPCPLUS

CRITICAL

55909-0374

M-ST-SM

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J5100

19 42 84 91

44

19 42 84 91

19 42

42 43

26

42 43

42

40 42 43

18

42

44

44 54

54

26 91

1/16W

5%

402

MF-LF

20K

2

1

R5144

44

44 54

10V

20%

402

CERM

0.1UF

LPCPLUS

2

1

C5114

TQFN

PI3USB102ZLE

CRITICAL

LPCPLUS

1 2

9

10

8

5 4

3

7 6

U5110

19 42 84 91

10V

20% 402

CERM

0.1UF

LPCPLUS

2

1

C5124

TQFN

PI3USB102ZLE

CRITICAL

LPCPLUS

1 2

9

10

8

5 4

3

7 6

U5120

1/16W

5%

402

MF-LF

10K

2

1

R5190

21 91

21 44 91

19 42 84 91

21 44 91

1/16W

5%

402

MF-LF

0

LPCPLUS_NOT

PLACEMENT_NOTE=PLACE NEXT TO U1400

21

R5146

1/16W

5%

402

MF-LF

0

LPCPLUS_NOT

21

R5157

1/16W

5%

402

MF-LF

0

LPCPLUS_NOT

21

R5156

1/16W

5%

402

MF-LF

0

LPCPLUS_NOT

21

R5158

21 44 91

1/16W

5%

402

MF-LF

10K

2

1

R5191

21 44

21 44 91

44 54

21 44

1/16W

5%

402

MF-LF

100K

2

1

R5140

44

LPC+SPI Debug Connector

A.0.0

9744

051-7892

SYNC_DATE=05/09/2008

SYNC_MASTER=CHANGZHANG

SMC_TRST_L

DEBUG_RESET_L

LPC_FRAME_L

SPI_ALT_MOSI

LPC_AD<1>

LPC_AD<0>

SMC_MD1

SMC_TDO

SMC_TMS

PM_CLKRUN_L

SPI_ALT_MISO

LPCPLUS_GPIO

SMC_RX_L

SMC_NMI

SMC_RESET_L

SMC_TCK

SMC_TDI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_ALT_CS_L

SPI_ALT_CLK

SPIROM_USE_MLB

LPC_AD<3>

LPC_AD<2>

LPC_CLK33M_LPCPLUS

PP5V_S0

PP3V42_G3H

SPI_MOSI_MUX

SPI_MLB_CS_L

SPIROM_USE_MLB

SPI_CS0_R_L

SPI_ALT_MISO

PP3V42_G3H

SPI_CLK_R

SPI_MOSI_R

SPI_ALT_CLK SPI_ALT_MOSI

SPI_ALT_CS_L

SPI_MISO_MUX

PP3V3_S5

SPI_MISO

SPI_MOSI_R

SPI_CLK_R

SPI_MISO

SPI_CLK_MUX

SPI_MISO_MUX

SPI_MOSI_MUX

PP3V3_S5

SPI_CLK_MUX

MAKE_BASE=TRUE

SPIROM_USE_MLB

PP3V42_G3H

SMC_TX_L

7 8

39 49 51 63 66 67 70 83

85

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 87 96

21

44

7 8

21 22 26 40

42 43 44 45 46 50

61 62 64 69

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(WRITE: 0x58 READ: 0x59)

LED BACKLIGHT

U9701

SMC "0" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

GPU Temp (Int)

(Write: 0x98 Read: 0x99)

(WRITE: 0X72 READ: 0X73)

Mikey

U6860

(MASTER)

SMC "A" SMBus Connections

(Write: 0x72 Read: 0x73)

SMC

U4900 J5800

TRACKPAD

GPU Temp (Ext)

U4900

(MASTER?)

U2300

SMC

ALS

J3401

(MASTER)

SO-DIMM "A"

U2300

MCP79

(Write: 0x90 Read: 0x91)

SMC "B" SMBus Connections

(Write: 0xA2 Read: 0xA3)

SO-DIMM "B"

J3200

J3100

(MASTER)

(Write: 0x98 Read: 0x99)

EMC1413: U5570

(WRITE: 0XD8 READ: 0XD9)

EMC1413: U5550

Battery

(Write: 0x12 Read: 0x13)

(See Table)

J6955

ISL6258A - U7000

U2900

(Write: 0x98 Read: 0x99)

U4900

Battery LED Driver - (Write: 0x36 Read: 0x37)

(MASTER)

SMC

Battery Temp - (Write: 0x90 Read: 0x91)

(MASTER)

SMC

Sensor ADCs

(Write: 0x10 Read: 0x11)

U5930

(MASTER)

EMC1413: U5500

CPU Temp

MCP TEMP

(Write: 0x9E Read: 0x9F)

GT216: U8000

MCP79

MCP79 SMBus "1" Connections

U2901

SMC

U4900

SMC "Battery A" SMBus Connections

SMC "Management" SMBus Connections

Battery

MCP79 SMBus "0" Connections

(Write: 0xA0 Read: 0xA1)

Battery Manager - (Write: 0x16 Read: 0x17)

Battery Charger

The bus formerly known as "Battery B"

Vref DACs

Margin Control

(Write: 0x30 Read: 0x31)

(Write: 0xXX Read: 0xXX)

J4501

HDD Margin Control

3.3K

MF-LF 402

5% 1/16W

2

1

R5261

3.3K

402

5% 1/16W MF-LF

2

1

R5260

2.61K

1% 1/16W MF-LF

402

2

1

R5280

2.61K

1% 1/16W MF-LF 402

2

1

R5281

2.2K

MF-LF

402

5%

1/16W

2

1

R5270

2.2K

MF-LF 402

5% 1/16W

2

1

R5271

2.0K

MF-LF

402

5%

1/16W

2

1

R5230

MF-LF 402

1/16W

2.0K

5%

2

1

R5231

1.6K

402

5%

1/16W MF-LF

2

1

R5290

MF-LF 402

5% 1/16W

1.6K

2

1

R5291

1/16W

402

MF-LF

5%

1.6K

2

1

R5250

1/16W

5%

402

MF-LF

1.6K

2

1

R5251

1.6K

5%

MF-LF

402

1/16W

2

1

R5200

1.6K

MF-LF 402

5% 1/16W

2

1

R5201

SYNC_MASTER=DDR

SYNC_DATE=12/19/2008

A.0.0

45 97

051-7892

K19 SMBUS CONNECTIONS

PP3V42_G3H

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_BSA_SCL

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

PP3V3_S3

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

SMBUS_MCP_0_CLK

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_MGMT_SDA

PP3V3_S0

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_B_S0_SDASMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

SMBUS_SMC_0_S0_SDA

PP3V3_S0

SMBUS_MCP_0_DATA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SDA

PP3V3_S3

PP3V3_S0

SMBUS_MCP_1_CLK

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

SMBUS_MCP_1_DATA

SMBUS_MCP_1_CLK

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

MAKE_BASE=TRUE

SMBUS_MCP_0_CLK

MAKE_BASE=TRUE

PP3V3_S0

SMBUS_MCP_1_DATA

7 8

21 22 26 40 42 43 44 46

50 61 62 64 69

27 39 42 45

94

7

42 45

61 62 94

42 45 48 53 78 94

27

39 42

45 94

7 8

21 27 31 32 45 50 52 70

27 39 42 45

94

27 39 42 45

94

27

39 42

45

94

13 21 28 29 45 91

42 45 48 53 78 94

27 39 42 45

94

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

42

45 48

53

78

94

42

45 48

53 78 94

42 45 48 53

78 94

7

31 42 45

51 94

42 45 48 94

42

45 48

94

42 45 48 94

42 45 48 53

78 94

27 39 42 45 94

7

42 45 61

62 94

7

42 45 61

62 94

27 39 42 45

94

27 39 42 45

94

7

42 45 61

62 94

7

42 45 61

62 94

7

42 45

61 62 94

42

45 48

94

42 45 48 94

7

31 42 45

51 94

7

31 42 45

51 94

42 45 48 53 78 94

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

13 21 28 29 45 91

42 45 48 53 78 94

7

31

42 45 51

94

7

31

42 45 51

94

7

31 42 45

51 94

7 8

21 27 31 32 45 50 52 70

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

21 45 60 85 91

13 21 28 29 45 91

21 45 60 85 91

42 45 48 94

42 45 48 53 78 94

13 21 28 29 45 91

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

21 45 60 85 91

OUT

N-CHN

S

D

G

P-CHN

G

D

S

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

IN

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Enables PBUS VSense divider when high.

INA213 has gain of 50V/V

MCP Voltage Sense / Filter

Place short near U8000 center

CPU VCore Load Side Current Sense / Filter

Place short near U1000 center

DCIN Current Sense Filter

Place RC close to SMC

PBUS Voltage Sense & Filter

Rthevanin = 4573 ohms

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388

GPU Voltage Sense / Filter

CPU VCore High Side Current Sensor

Place RC close to SMC

CPU Voltage Sense / Filter

REGULATOR SIDE:

LOAD SIDE:

Monitors battery discharge

Place RC close to SMC

BMON Current Sense - Entire circuit must be near SMC (U4900)

current from battery to PBUS

100K

MF-LF

402

5%

1/16W

2

1

R5315

42

27.4K

MF-LF

402

1%

1/16W

2

1

R5385

0.22UF

X5R 402

20%

6.3V

2

1

C5385

5.49K

MF-LF

402

1%

1/16W

2

1

R5386

FDG6332CG

SC70-6

1

2

6

Q5315

FDG6332CG

SC70-6

4

5

3

Q5315

6.19K

MF-LF

402

1%

1/16W

21

R5331

63

100K

MF-LF

402

5%

1/16W

2

1

R5316

0.22UF

X5R 402

20%

6.3V

2

1

C5399

PLACEMENT_NOTE=Place near U1400 center

SM

21

XW5399

4.53K

MF-LF

402

1%

1/16W

21

R5399

42 43

17.4K

MF-LF

402

1%

1/16W

2

1

R5332

INA210

SC70

3

1

6

4

5

2

U5388

0.001

MF

1206

1%

0.5W

CRITICAL

432

1

R5388

42 43

0.22UF

X5R 402

20%

6.3V

2

1

C5335

4.53K

MF-LF

402

1%

1/16W

21

R5335

7 8

37 46 61 62

64 65 66 67 79

83 86

8

63

0.1UF

CERM 402

20% 10V

2

1

C5388

BMON_ENG

0.1uF

CERM 402

20% 10V

2

1

C5369

42

0.22UF

X5R 402

20%

6.3V

2

1

C5390

42 43

4.53K

MF-LF

402

1%

1/16W

21

R5391

BMON_ENG

100K

MF-LF 402

5% 1/16W

2

1

R5371

BMON_ENG

NC7SB3157P6XG

SC70

5

6

2

1

3 4

U5313

BMON_PROD

0

MF-LF

402

5%

1/16W

2 1

R5330

62

BMON_ENG

INA213

SC70

3

1

6

4

5

2

U5303

BMON_ENG

0.1uF

CERM 402

20% 10V

2

1

C5318

62 96

42

0.22UF

X5R 402

20%

6.3V

2

1

C5359

4.53K

MF-LF

402

1%

1/16W

21

R5359

42

0.22UF

X5R 402

20%

6.3V

2

1

C5380

4.53K

MF-LF

402

1%

1/16W

21

R5380

62

42

0.22UF

X5R 402

20%

6.3V

2

1

C5330

SM

21

XW5359

42

4.53K

MF-LF

402

1%

1/16W

21

R5309

0.22UF

X5R 402

20%

6.3V

2

1

C5309

SM

21

XW5309

Current & Voltage Sensing

SYNC_MASTER=SENSOR

SYNC_DATE=08/14/2008

46 97

A.0.0

051-7892

PPBUS_CPU_IMVP_ISNS

GND_SMC_AVSS

BMON_INA_OUT

CHGR_CSO_R_N

PPVCORE_S0_MCP_REG

PP3V42_G3H

SMC_BMON_MUX_SEL

SMC_BATT_ISENSE

PPVCORE_GPU

IMVP6_IMON

GND_SMC_AVSS

PM_SLP_S3_L_R

CPUVSENSE_IN

ISNS_CPU_P

GND_SMC_AVSS

SMC_PBUS_VSENSE

PBUSVSENS_EN_DIV

PPBUS_G3H_VSENSE

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm

PBUSVSENS_EN_L

GND_SMC_AVSS

SMC_CPU_HI_ISENSE

PPBUS_G3H

GND_SMC_AVSS

SMC_DCIN_ISENSE

CHGR_AMON

CPUVCORE_HISIDE_IOUT

GPUVSENSE_IN

PPBUS_G3H

PPVCORE_S0_CPU

SMC_CPU_ISENSE

SMC_MCP_VSENSE

SMC_CPU_VSENSE

SMC_GPU_VSENSE

MCPVSENSE_IN

BMON_AMUX_OUT

PP3V42_G3H

ISNS_CPU_N

CHGR_CSO_R_P

CHGR_BMON

42 43 46 47

7 8

22 24 66

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

8

72 79

42 43 46 47

69 70

96

42 43 46 47

7 8

37 46 61 62 64 65 66 67

79 83 86

42 43 46 47

7 8

11 12 63

7 8

21 22 26 40 42

43 44 45 46 50 61 62 64 69

96

IN

THRM

V-

V+

THRM

V-

V+

THRM

V-

V+

THRM

V-

V+

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU FSB 1.05V Current Sense

MCP VCore Current Sense Filter

MCP MEM VDD Current Sense

Place RC close to SMC

1.05V CPU Current Sense Filter

Place RC close to SMC

NC

Gain: 274x

Place RC close to SMC

Gain: 274x

MCP MEM VDD Current Sense Filter

Place RC close to SMC

GPU VCore Current Sense Filter

GPU VCore Current Sense

NC

1.4X GAIN FOR SENSING CURRENT UP TO 25 AMPS

GPU 1.8V Current Sense Filter

dual package opamp U5410

GPU 1.8V Current Sense

GPU VCore Current Sense and GPU 1.8V Current Sense share

NC

dual package opamp U5440

MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share

MCP VCore Current Sense

1/16W

1%

402

MF-LF

4.53K

21

R5475

118

1% 1/16W MF-LF 402

2

1

R5443

70

SOD

2SA2154MFV-YAE

2

3

1

Q5441

1/16W

5%

402

0

MF-LF

2

1

R5441

1/16W

5%

402

MF-LF

0

21

R5442

16V

10%

402

X5R

0.1UF

21

C5441

66

DFN

OPA2330

8

4

9

1

2

3

U5410

CRITICAL

OPA2330

DFN

8

4

9

7

6

5

U5410

DFN

OPA2330

8

4

9

7

6

5

U5440

CRITICAL

OPA2330

DFN

8

4

9

1

2

3

U5440

42 43

6.3V

20% 402

X5R

0.22UF

2

1

C5490

1/16W

1%

402

MF-LF

4.53K

21

R5440

42 43

X5R 402

20%

6.3V

0.22UF

2

1

C5470

4.53K

MF-LF

402

1%

1/16W

21

R5470

42 43

6.3V

20% 402

X5R

0.22UF

2

1

C5435

1/16W

1%

402

MF-LF

4.53K

21

R5495

2.87K

1/16W

1%

402

MF-LF

21

R5493

1/16W

1%

402

MF-LF

10K

21

R5491

1/16W

1%

402

MF-LF

4.02K

21

R5498

6.3V

20% 402

X5R

0.22UF

2

1

C5465

50V

10%

402

CERM

470PF

21

C5498

79

42 43

1/16W

1%

402

MF-LF

3.65K

21

R5415

1/16W

1%

402

MF-LF

4.53K

21

R5465

1/4W

1%

1206

MF

0.002

CRITICAL

432

1

R5413

1%

402

SIGNAL_MODEL=EMPTY

1M

1/16W MF-LF

21

R5411

50V

10%

402

CERM

470PF

SIGNAL_MODEL=EMPTY

21

C5411

10V

20% 402

CERM

0.1UF

2

1

C5410

1/16W

1%

402

MF-LF

1M

SIGNAL_MODEL=EMPTY

2

1

R5412

1%

402

MF-LF

3.65K

1/16W

21

R5414

50V

10%

402

CERM

470PF

SIGNAL_MODEL=EMPTY

2

1

C5412

8

83

8 9

72 73 74 75

10V

20% CERM

0.1UF

402

2

1

C5440

42

50V

10%

402

CERM

470PF

SIGNAL_MODEL=EMPTY

21

C5432

1/16W

1%

402

MF-LF

1M

SIGNAL_MODEL=EMPTY

21

R5432

1%

402

MF-LF

1/16W

3.65K

21

R5431

1%

1/16W

402

MF-LF

3.65K

21

R5436

1/16W

1%

402

MF-LF

1M

SIGNAL_MODEL=EMPTY

2

1

R5437

6.3V

20% 402

X5R

0.22UF

2

1

C5475

10%

402

CERM

50V

470PF

SIGNAL_MODEL=EMPTY

2

1

C5472

SYNC_DATE=12/10/2008

Current Sensing

47 97

A.0.0

051-7892

SYNC_MASTER=YUN_K19_MLB

P1V5_S0_SENSE_C

CPUVTTISNS_R_P

CPUVTTISNS_R_N

GND_SMC_AVSS

PP3V3_S0

GPUVCORE_IOUT

PP1V8_S0GPU_ISNS_R

P1V8GPUISNS_R_P

P1V8_S0GPU_IOUT

P1V8GPUISNS_R_N

GPUISENS_P

GPUISENS_N

GFXIMVP6_IMON

SMC_GPU_ISENSE

SMC_MCP_DDR_ISENSE

P1V8GPU_N

P1V8GPU_P

GND_SMC_AVSS

PP1V8_S0GPU_ISNS

SMC_CPU_FSB_ISENSE

GND_SMC_AVSS

SMC_GPU_1V8_ISENSE

P1V5_S0_SENSE_E

P1V5_S0_SENSE_B

MCPCORES0_IMON

CPUVTT_ISNS_N

CPUVTT_ISNS_P

SMC_MCP_CORE_ISENSE

GND_SMC_AVSS

CPU1V05_S0_IOUT

PP3V3_S0

P1V5_S0_SENSE

P1V5_S0_SENSE_AMP

P1V5_S0_KELVIN

96

42 43 46 47

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

96

42 43 46 47

67 96

42 43 46 47

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Placement note:

Detect GPU Die Temperature

Detect Left Heat Pipe Temperature

Place on top side under left heat pipe near CPU

to IC pins as possible

Placement note:

Place U5550 near GPU

Detect Right Fin Stack Temperature

Keep 2 caps as close

Placement note:

Place U5500 near MCP

close to right fin stack

Place Q5501 on bottom side

Detect CPU Die Temperature

Place Q5502 near battery

Placement note:

Detect Battery Charger Temperature

CPU Proximity/CPU Die/Right Fin Stack

to IC pins as possible

Keep 2 caps as close

Placement note:

and close to left fin stack

Place U5570 under CPU

Note: EMC1413 can perform Beta

Compensation for External Diode 1 only

charger circuit

GPU Proximity/GPU Die/Left Heat Pipe

Detect MCP Die Temperature

MCP Proximity/MCP Die/Battery Charger Proximity

402

CERM

10V

20%

0.1uF

2

1

C5500

47

5%

MF-LF

402

1/16W

21

R5500

42 45 48 94

402

CERM

10%

SIGNAL_MODEL=EMPTY

0.0022uF

50V

2

1

C5511

MF-LF

402

1/16W

15.0K

1%

2

1

R5501

5% MF-LF

402

1/16W

10K

2

1

R5502

402

1/16W MF-LF

5%

10K

2

1

R5572

BC846BMXXH

SOT732-3

2

3

1

Q5501

10 96

21 96

42 45 53 78 94

1/16W

402

MF-LF

10K

1%

2

1

R5551

402

MF-LF

1/16W

10K

5%

2

1

R5552

10V

20% 402

CERM

0.1uF

2

1

C5550

1/16W

5%

402

MF-LF

47

21

R5550

50V

10%

402

CERM

0.0022uF

SIGNAL_MODEL=EMPTY

2

1

C5551

SIGNAL_MODEL=EMPTY

50V

10%

402

CERM

0.0022uF

2

1

C5552

76 77 96

SOT732-3

BC846BMXXH

2

3

1

Q5503

SIGNAL_MODEL=EMPTY

50V

10%

CERM

402

0.0022uF

2

1

C5521

SOT732-3

BC846BMXXH

2

3

1

Q5502

EMC1413

CRITICAL

DFN

1

11

7

9

10

6

4

2

5

3 8

U5570

DFN

EMC1413

CRITICAL

1

11

7

9

10

6

4

2

5

3 8

U5500

EMC1413

CRITICAL

DFN

1

11

7

9

10

6

4

2

5

3 8

U5550

1/16W

402

MF-LF

10K

1%

2

1

R5571

42 45 48 94

10V

20% 402

CERM

0.1uF

2

1

C5570

1/16W

5%

402

MF-LF

47

21

R5570

SIGNAL_MODEL=EMPTY

0.0022uF

50V

CERM

402

10%

2

1

C5590

10% 50V

402

CERM

0.0022UF

SIGNAL_MODEL=EMPTY

2

1

C5580

Thermal Sensors

SYNC_MASTER=YUN_K19_MLB

051-7892

A.0.0

9748

SYNC_DATE=12/22/2008

MCPTHMSNS_D_P

MCPTHMSNS_D_N

MCP_THMDIODE_N

MCP_THMDIODE_P

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_S0_REMTHMSNS_R

MIN_LINE_WIDTH=0.38 mm

SMBUS_SMC_B_S0_SCL

REMTHMSNS_ALERT_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

CPUTHMSNS_THM_L

SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

REMTHMSNS_THM_L

PP3V3_S0

GPUTHMSNS_D_N

CPUTHMSNS_ALERT_L

GPUTHMSNS_ALERT_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=3.3V

PP3V3_S0_GPUTHMSNS_R

GPUTHMSNS_D_P

SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL

GPU_TDIODE_N

GPU_TDIODE_P

GPUTHMSNS_THM_L

PP3V3_S0

CPU_THERMD_N

CPU_THERMD_P

PP3V3_S0

96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

G

S D

G

S D

IN

OUT OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0369

Right Fan

Left Fan

518S0369

47K

MF-LF

402

5%

1/16W

2

1

R5650

47K

MF-LF

402

5%

1/16W

21

R5655

47K

MF-LF

402

5%

1/16W

2

1

R5660

47K

MF-LF

402

5%

1/16W

21

R5665

100K

MF-LF

402

5%

1/16W

2

1

R5651

2N7002DW-X-G

SOT-363

4

5

3

Q5660

100K

MF-LF

402

5%

1/16W

2

1

R5661

2N7002DW-X-G

SOT-363

1

2

6

Q5660

CRITICAL

78171-0004

M-RT-SM

4

3

2

1

6

5

J5650

CRITICAL

78171-0004

M-RT-SM

4

3

2

1

6

5

J5660

42

42 42

42

Fan Connectors

A.0.0

051-7892

9749

SYNC_MASTER=M87_MLB

SYNC_DATE=10/17/2007

FAN_LT_PWM

SMC_FAN_1_CTL

SMC_FAN_1_TACH

SMC_FAN_0_CTL

FAN_RT_PWM

PP5V_S0

FAN_RT_TACH

PP3V3_S0

FAN_LT_TACH

PP5V_S0 PP3V3_S0

SMC_FAN_0_TACH

7 7

7 8

39 44 49 51 63 66 67 70

83 85

7

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77

80 81 82 84 85 96

7

7 8

39 44 49 51 63 66 67 70

83 85

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77

80 81 82 84 85 96

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

Y

C

B

A

IN

OUT

IN

Y

B

A

Y

B

A

Y

B

A

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

U5701 CHIP DECOUPLING

TO MLB CONNECTOR

ISSP DATA

ISSP CLOCK

PSOC PROGRAMMING CONNECTOR

APN 518S0430

PSOC USB CONTROLLER

KEYBOARD SCANNER

TEST POINTS ARE FOR ON BOARD PROGRAMMING

VDD PIN 49

CLOSE TO U5701

VDD PIN 22

CLOSE TO U5701

VOUT

ISOLATION CIRCUIT

USB INTERFACES TO MLB

TPAD BUTTONS DISABLE

PLACE THESE COMPONENTS CLOSE TO J5800

TMP102

KEYBOARD CONNECTOR

WHEN THE LID IS CLOSED

LID CLOSE => SMC_LID_LC < 0.50V

APN 518S0637

75.2E-6 W

294E-6 W

96E-6 W

0.72E-3 W

36E-3 W

16.32E-6 W

0.255E-6 W

0.0255 V

0.204 V

0.6 V

0.012 V

0.021 V

0.0188 V

POWERV_SNS

4.7 OHM

1.5 OHM

0.2 OHM

10 OHM

2.55 KOHM

R_SNS

10UA 80UA 60MA MAX 60MA MAX

8MA (TYP)

14MA (MAX)

4MA (MAX)

CURRENT

VIN

VDD

V+

PIN NAME

IC

3V3 LDO

PSOC

18V BOOSTER

PLACE C5701, C5702 & C5703

ISSP SCLK/I2C SCL

PLACE C5704, C5705 & C5706

SPI HOST TO Z2

APN 337S2983

ISSP SDATA/I2C SDA

THE TPAD BUTTONS WILL BE DISABLE

LID OPEN => SMC_LID_LC ~ 3.42V

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

APN 311S0406

SMC_MANUAL_RESET LOGIC

TRACKPAD PICK BUTTONS

SOD-VESM-HF

SSM3K15FV

2

1

3

Q5701

16V

10%

402

X7R-CERM

0.1UF

2

1

C5758

1/16W

5%

402

MF-LF

33K

2

1

R5771

1/16W

5%

402

MF-LF

33K

2

1

R5770

1/16W

5%

402

MF-LF

33K

2

1

R5769

6.3V

20% 603

X5R

4.7UF

2

1

C5706

16V

10% 402

X7R-CERM

0.1UF

2

1

C5705

50V

5% 402

CERM

100PF

2

1

C5704

16V

10% 402

X7R-CERM

0.1UF

2

1

C5703

50V

5% 402

CERM

100PF

2

1

C5702

6.3V

20% 603

X5R

4.7UF

2

1

C5701

24

MF-LF

402

5%

1/16W

21

R5702

CRITICAL

MLF

CY8C24794

OMIT

50194922

57

23

24

11 32 12 31 13 30 14 29

3 40 4 39 5 38 6 37 7 36 8 35 9 34

10 33

554456

43

1 42 2 41

15281627172618

25

51485247534654

45

21

20

U5701

24

MF-LF

402

5%

1/16W

21

R5701

SC70

SN74LVC1G10

CRITICAL

5

4

6

3

1

2

U5703

1/16W

5%

402

MF-LF

1.5

21

R5704

42 43 61

10V

20% 402

CERM

0.1UF

PLACEMENT_NOTE=NEAR J5713

2

1

C5710

1/16W

5%

402

MF-LF

1K

21

R5710

1/16W

1%

402

MF-LF

470

21

R5714

1/16W

1%

402

MF-LF

10K

21

R5715

F-RT-SM1

FH19C-4S-0.5SH25

TPAD_DEBUG

4

3

2

1

6

5

J5702

F-RT-SM

FF14-30A-R11B-B-3H

9 8 7 6 5 4

30

3

29 28 27 26 25 24 23 22 21 20

2

19 18 17 16 15 14 13 12 11 10

1

32

31

J5713

SOT665

TC7SZ08AFEAPE

CRITICAL

4

5

3

1

2

U5726

SOT665

TC7SZ08AFEAPE

CRITICAL

4

5

3

1

2

U5727

SOT665

TC7SZ08AFEAPE

CRITICAL

4

5

3

1

2

U5725

10V

20%

402

CERM

0.1UF

2 1

C5725

50 97

051-7892

SYNC_MASTER=AMASON_M98_MLB

A.0.0

SYNC_DATE=06/18/2008

WELLSPRING 1

PP3V3_S3

WS_KBD9

WS_KBD13

WS_KBD16_NUM

WS_KBD22

PP3V42_G3H

WS_LEFT_OPTION_KBD

WS_LEFT_SHIFT_KBD

SMC_ONOFF_L

PP3V3_S3

PP3V42_G3H

PP3V3_S3

WS_KBD4 WS_KBD5

ISSP_SDATA_P1_0

NC_P7_7

PP3V3_S3_PSOC

WS_KBD22

WS_KBD21

WS_KBD20

WS_KBD19

WS_KBD2

Z2_CS_L

PICKB_L

Z2_SCLK

PSOC_SCLK

ISSP_SCLK_P1_1

Z2_HOST_INTN

WS_KBD18

WS_KBD16N

WS_KBD7

Z2_KEY_ACT_L

WS_KBD13

NC_PSOC_P1_3

WS_KBD3

WS_KBD9

WS_KBD10

WS_KBD12

WS_KBD14

WS_KBD15_C

PP3V3_S3

WS_KBD11

TP_PSOC_SCL

NC_PSOC_SDA

WS_KBD8

WS_KBD7

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

WS_KBD_ONOFF_L PP3V42_G3H WS_LEFT_SHIFT_KBD

WS_KBD23

WS_KBD19

WS_KBD20

WS_KBD21

WS_KBD10

WS_KBD11

WS_KBD14

WS_KBD17

WS_KBD18

WS_KBD6

WS_KBD5

WS_KBD4

WS_KBD3

WS_KBD2

WS_KBD1

WS_KBD8

WS_LEFT_SHIFT_KEY

WS_KBD16N

WS_KBD17

BUTTON_DISABLE

SMC_LID

WS_CONTROL_KBD

WS_CONTROL_KEY

PSOC_MOSI

WS_KBD12

WS_KBD15_C

BUTTON_DISABLE

WS_KBD23

WS_LEFT_OPTION_KEY

SMC_TPAD_RST_L

WS_LEFT_OPTION_KEY

WS_LEFT_OPTION_KBD

PP3V3_S3

WS_LEFT_SHIFT_KBD

WS_LEFT_SHIFT_KEY

PP3V42_G3H

WS_CONTROL_KBD

WS_KBD15_CAP

WS_KBD1

ISSP_SDATA_P1_0

ISSP_SCLK_P1_1

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD NET_SPACING_TYPE=USB NET_PHYSICAL_TYPE=USB_90D

USB_TPAD_R_N

DIFFERENTIAL_PAIR=USB2_TPAD NET_SPACING_TYPE=USB NET_PHYSICAL_TYPE=USB_90D

USB_TPAD_P

DIFFERENTIAL_PAIR=USB2_TPAD

USB_TPAD_N

DIFFERENTIAL_PAIR=USB2_TPAD

PP3V3_S3_PSOC

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

Z2_CLKIN

WS_KBD6

Z2_RESET

TP_BOOT_CFG1

TP_P4_5

PSOC_MISO

Z2_MISO

Z2_MOSI

PSOC_F_CS_L

Z2_DEBUG3

WS_CONTROL_KEY

7 8

21 27 31 32 45 50 52 70

7

50

7

50

7

50

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7

50

7

50

42 43

7 8

21 27 31 32 45 50 52

70

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 27 31 32 45 50 52 70

7

50

7

50

7

50

7

50 7 50 7 50 7 50

7

50

7

51

7

51

7

51

7

51

50

7

51

7

50

7

50

7

51

7

50

7

50

7

50

7

50

7

50

7

50

7 8

21 27 31 32 45 50 52 70

7

50

7

50

7

50

7

50

7

50

7

7 8

21 22 26 40 42 43 44

45 46 50 61 62 64 69 7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

51

7

50

7

50

43

50

7

50

7 8

21 27 31 32 45 50 52 70

7

50

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7

50

7

50

20 91

50

7

51

7

50

7

51

7

51

7

51

7

51

7

51

7

51

50

VDD

VOUT

GND

CE

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3V3 LDO FOR IPD

IPD FLEX CONNECTOR

APN 516S0689

Keyboard LED Driver

To detect Keyboard backlight, SMC will

LOW = keyboard backlight present

HIGH= keyboard backlight not present

APN 353S1364

J5815 pin 1 is grounded on keyboard backlight flex

BOM OPTION: KBDLED_YES

R5853 ALWAYS PRESENT

APN 371S0313

- POWER CONSUMPTION

- DROOP LINE REGULATION

BOOSTER DESIGN CONSIDERATION:

- R5812,R5813,C5818 MODIFIED

- STARTUP TIME LESS THAN 2MS

- 100-300 KHZ CLEAN SPECTRUM

- RIPPLE TO MEET ERS

APN 152S0504

BOOSTER +18.5VDC FOR SENSORS

APN 518S0612

KBD BACKLIGHT CONNECTOR

tristate SMC_SYS_KBDLED:

APN 353S1401

M-ST-SM

55560-0228

CRITICAL

9

8 7

6 5

4 3

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J5800

10% 16V

603

X5R

2.2UF

2

1

C5853

MLF

MM3243DRRE

CRITICAL

3

2

4

1

VR5802

1%

1/6W

402-HF

MF

0.2

21

R5836

16V

10% X7R-CERM

0.1UF

402

2

1

C5838

6.3V

20%

603

X5R

4.7UF

2

1

C5854

1/16W

1%

402

MF-LF

10

21

R5873

1/16W

5%

402

MF-LF

4.7K

2

1

R5854

1/16W

5%

402

MF-LF

470K

2

1

R5853

DFN

LT3491

CRITICAL

1

7

3

5

2

6

4

U5850

5%

1/16W

402

MF-LF

10K

NO STUFF

2

1

R5852

10V

10%

402-1

X5R

1UF

2

1

C5850

1/16W

1%

402

MF-LF

10

2

1

R5855

1098AS-SM

10UH-0.58A-0.35OHM

CRITICAL

21

L5850

35V

10%

603

X5R

1UF

2

1

C5855

F-RT-SM

FF18-4A-R11AD-B-3H

CRITICAL

4

3

2

1

J5815

1/16W

5%

402

MF-LF

0

21

R5806

1/16W

1%

402

MF-LF

1M

2

1

R5812

50V

5% 402

CERM

39PF

2

1

C5818

B0520WSXG

SOD-323

21

D5802

25V

10%

603-1

X5R

1UF

2

1

C5819

1/16W

1%

402

MF-LF

71.5K

2

1

R5813

1/16W

1%

402

MF-LF

100K

2

1

R5811

3.3UH-870MA

CRITICAL

VLF3010AT-SM-HF

21

L5801

5%

402

MF-LF

1/16W

0

21

R5805

CRITICAL

TPS61045

QFN

2

9

8

7

1

6

4

3 5

U5805

2.2UF

603

16V

10% X5R

2

1

C5817

X7R-CERM

0.1UF

16V

10% 402

2

1

C5816

WELLSPRING 2

SYNC_MASTER=PWRSQNC

SYNC_DATE=01/05/2009

9751

051-7892

A.0.0

PP3V3_S3_LDO

PP3V3_S3_LDO_R

Z2_CLKIN

PP3V3_S3_LDO

0.20MM

0.50MM

BOOST_FB

SMC_SYS_KBDLED

PP5V_S3

PP3V3_S0

SMC_KDBLED_PRESENT_L

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

KBDLED_ANODE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

KBDLED_SW

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

KBDLED_CAP

PP5V_S0

PP18V5_S3_SW

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP18V5_S3

Z2_RESET

PSOC_F_CS_L

PICKB_L

PSOC_MISO

PSOC_MOSI

PSOC_SCLK

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

0.20MM

0.50MM

PP18V5_S3

Z2_KEY_ACT_L

Z2_CS_L

Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

BOOST_SW

SWITCH_NODE=TRUE

Z2_BOOST_EN

PP5V_S3_VR

0.50MM

0.20MM

INPUT_SW

PP5V_S3

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP5V_S3_BOOSTER

7

51

7

50

7

51

42

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 55 59

60 63 68 69 70 77 80 81 82

84 85 96

7

51

7

51

7

7 8

39 44 49 63 66 67 70 83

85

7

51

7

50

7

50

7

50

7

50

7

50

7

50

7

31 42 45

94

7

31 42 45

94

7

51

7

50

7

50

7

50

7

50

7

50

7

50

7

51

7

50

7

51

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

OUT

FS PD ST

RES RES

GND

NC

NC NC

NC

NC NC

VOUTX

VOUTY

VOUTZ

VDD

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

+Y

+X

Front of system

Desired orientation when

Circle indicates pin 1 location when placed

+Z (up)

placed on board top-side:

in correct orientation

NC

Analog SMS

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

42

0.01UF

CERM 402

10% 16V

2

1

C5925

0.01UF

CERM 402

10% 16V

2

1

C5924

0.01UF

CERM 402

10% 16V

2

1

C5923

10K

MF-LF

402

5%

1/16W

2

1

R5921

CRITICAL

AP344ALH

LGA

8

10

12

14

2

4

15

5

16

13

11

9

6

3

7

1

U5920

10K

MF-LF 402

5% 1/16W

2

1

R5922

42 52

10UF

X5R 603

20% 4V

2

1

C5926

0.1UF

X5R 402

10% 16V

2

1

C5922

42

SYNC_MASTER=SENSOR

52 97

A.0.0

051-7892

Sudden Motion Sensor (SMS)

SYNC_DATE=08/14/2008

PP3V3_S3

SMS_PWRDN

SMS_SELFTEST

SMS_PWRDN

MAKE_BASE=TRUE

SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS

7 8

21 27 31 32 45 50 70

42 52

COM

GND

THRM

DVDDAVDD

AD0 AD1

SDA SCL

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

VREF

REFCOMP

PAD

BI

IN

V+

REFIN+

IN-

OUT

GND

IN

THRM

V-

V+

IN

THRM

V-

V+

IN

THRM

V-

V+

THRM

V-

V+

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

GAIN: 273X

GAIN: 200X

LSB: 0.001V

ADC RANGE: 0V TO 4.096V

I2C ADDRESS: 0X10 / 0X11

GAIN: 1239X

GAIN: 561X

DIVIDER: ~ 2/5

DIVIDER: ~ 1/22

GAIN: 845X

DIVIDER: ~ 2/5

QFN

LTC2309

DEBUG_ADC

7

25

17 16

8

2019181110

9

21

6

5

4

3

2

1

24

23

22

13

12

15

14

U6000

42 45 48 78 94

DEBUG_ADC

402

1% 1/16W MF-LF

412

21

R6060

2.2UF

X5R

DEBUG_ADC

6.3V

10% 402

PLACEMENT_NOTE=PLACE RC NEAR U6000

2

1

C6074

226K

1/16W

DEBUG_ADC

402

MF-LF

1%

21

R6074

42 45 48 78 94

85 96

402

10V

20%

0.1UF

DEBUG_ADC

CERM

2

1

C6050

2.2UF

X5R

DEBUG_ADC

6.3V 402

10%

PLACEMENT_NOTE=PLACE RC NEAR U6000

2

1

C6082

DEBUG_ADC

226K

MF-LF

1/16W

402

1%

21

R6082

PLACEMENT_NOTE=PLACE NEAR D9701

SM

21

XW6080

DEBUG_ADC

10UF

X5R 603

20%

6.3V

2

1

C6005

402

MF-LF

1/16W

DEBUG_ADC

1M

1%

2

1

R6080

47.0K

DEBUG_ADC

1/16W MF-LF

1%

402

2

1

R6081

DEBUG_ADC

SC70

INA210

3

1

6

4

5

2

U6050

PLACEMENT_NOTE=PLACE CLOSE TO U4900

402

DEBUG_ADC

0

MF-LF

5%

1/16W

21

R6001

0

402

DEBUG_ADC

MF-LF

5%

1/16W

PLACEMENT_NOTE=PLACE CLOSE TO U4900

21

R6002

DEBUG_ADC

20%

6.3V X5R 603

10UF

2

1

C6003

DEBUG_ADC 10UF

X5R 603

20%

6.3V

2

1

C6001

SM

PLACEMENT_NOTE=PLACE NEAR Q3450

21

XW6010

PLACEMENT_NOTE=PLACE NEAR Q4590

SM

21

XW6020

1%

402

MF-LF

1/16W

1M

DEBUG_ADC

2

1

R6010

681K

MF-LF

1/16W

1%

402

DEBUG_ADC

2

1

R6011

226K

402

1% 1/16W MF-LF

DEBUG_ADC

21

R6012

2.2UF

X5R 402

10%

6.3V

DEBUG_ADC

PLACEMENT_NOTE=PLACE RC NEAR U6000

2

1

C6012

2.2UF

X5R

10%

402

DEBUG_ADC

PLACEMENT_NOTE=PLACE RC NEAR U6000

6.3V

2

1

C6022

226K

1/16W

1%

MF-LF

402

DEBUG_ADC

21

R6022

DEBUG_ADC

1M

MF-LF 402

1/16W

1%

2

1

R6020

681K

MF-LF 402

1% 1/16W

DEBUG_ADC

2

1

R6021

DEBUG_ADC

0.1UF

CERM 402

20% 10V

2

1

C6002

31 96

50V

10%

CERM

402

470PF

DEBUG_ADC

2

1

C6032

MF-LF 402

1% 1/16W

DEBUG_ADC

301K

2

1

R6032

470PF

CERM

10% 50V

402

DEBUG_ADC

21

C6033

243

1/16W

402

MF-LF

1%

DEBUG_ADC

21

R6031

243

402

1%

MF-LF

1/16W

DEBUG_ADC

21

R6030

1%

1/16W

402

MF-LF

DEBUG_ADC

301K

21

R6033

DFN

OPA2330

DEBUG_ADC

8

4

9

1

2

3

U6030

20% CERM

402

10V

DEBUG_ADC

0.1UF

2

1

C6030

31 96

PLACEMENT_NOTE=PLACE RC NEAR U6000

10% 402

DEBUG_ADC

2.2UF

X5R

6.3V

2

1

C6034

DEBUG_ADC

MF-LF

1%

402

1/16W

226K

21

R6034

DEBUG_ADC

0.1UF

CERM 402

20% 10V

2

1

C6004

PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC

2.2UF

X5R

6.3V

10%

402

2

1

C6044

DEBUG_ADC

226K

MF-LF

1/16W

402

1%

21

R6044

DFN

OPA2330

8

4

9

7

6

5

U6030

DEBUG_ADC

1%

1M

1/16W MF-LF

402

21

R6043

402

50V

470PF

CERM

10%

DEBUG_ADC

21

C6043

DEBUG_ADC

1M

1% 1/16W MF-LF 402

2

1

R6042

DEBUG_ADC

10%

470PF

50V

CERM

402

2

1

C6042

DEBUG_ADC

1%

3.65K

1/16W MF-LF

402

21

R6040

DEBUG_ADC

3.65K

1/16W

1%

MF-LF

402

21

R6041

65 96

2.2UF

X5R

10%

PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC

6.3V 402

2

1

C6054

2.2UF

X5R

DEBUG_ADC

402

10%

6.3V

PLACEMENT_NOTE=PLACE RC NEAR U6000

2

1

C6064

DEBUG_ADC

0.1UF

CERM 402

20% 10V

2

1

C6000

226K

DEBUG_ADC

1/16W

1%

402

MF-LF

21

R6054

DEBUG_ADC

0.1UF

CERM 402

10V

20%

2

1

C6040

226K

DEBUG_ADC

402

1% 1/16W MF-LF

21

R6064

280K

1/16W MF-LF

402

1%

DEBUG_ADC

21

R6053

DEBUG_ADC

470PF

10%

402

CERM

50V

21

C6053

280K

DEBUG_ADC

MF-LF 402

1% 1/16W

2

1

R6052

DEBUG_ADC

470PF

CERM

10% 50V

402

2

1

C6052

DEBUG_ADC

MF-LF

402

1%

1/16W

348K

21

R6063

50V 402

10%

CERM

470PF

DEBUG_ADC

21

C6063

DEBUG_ADC

MF-LF 402

1% 1/16W

348K

2

1

R6062

10% 50V

DEBUG_ADC

470PF

CERM

402

2

1

C6062

2.2UF

DEBUG_ADC

20%

6.3V CERM 402-LF

2

1

C6006

39 96

OPA2330

DFN

DEBUG_ADC

8

4

9

1

2

3

U6040

DFN

OPA2330

8

4

9

7

6

5

U6040

499

402

MF-LF

1/16W

1%

DEBUG_ADC

21

R6051

499

402

MF-LF

1/16W

1%

DEBUG_ADC

21

R6050

DEBUG_ADC

402

1/16W MF-LF

1%

412

21

R6061

051-7892

A.0.0

9753

SYNC_DATE=12/19/2008

SYNC_MASTER=DDR

DEBUG SENSORS AND ADC

ISNS_HDD_IOUT

ISNS_HDD_N

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

ISNS_AIRPORT_P

ADC_CH6

PP5V_WLAN_F_DIV

ADC_CH0

PP5V_SW_ODD_DIV

ADC_CH1

ADC_CH3

PPVOUT_S0_LCDBKLT_XW

ADC_CH5

ISNS_ODD_R_N

PPVOUT_S0_LCDBKLT

ISNS_AIRPORT_N

ADC_CH3

PP5V_SW_ODD_XW

PP5V_SW_ODD

ISNS_ODD_N

ISNS_ODD_P

ISNS_ODD_R_P

ADC_CH4

PP5V_WLAN_F_XW

ADC_CH5

ADC_CH4

ADC_CH0

ADC_REFCOMP

PP5V_S3PP5V_S3

PP5V_WLAN_F

ADC_CH6 ADC_CH7

ADC_CH2

ADC_VREF

ISNS_ODD_IOUT

ADC_SDA ADC_SCL

ADC_CH2

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

ISNS_AIRPORT_IOUT

ADC_CH7

ISNS_HDD_R_N

ISNS_HDD_R_P

ISNS_HDD_P

ISNS_AIRPORT_R_N

PPVOUT_S0_LCDBKLT_DIV

ISNS_LCDBKLT_IOUT

ISNS_AIRPORT_R_P

ISNS_1V5_S3_IOUT

PP5V_S3

ISNS_1V5_S3_R_P

ISNS_1V5_S3_P

ISNS_1V5_S3_R_N

ISNS_1V5_S3_N

PP5V_S3

53

53 53

53

96

7

80 85

53

7

39

96

53

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

31

53

96

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

96

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

IN

OUT

ININ

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SPI_CLK

SPI_MOSI

Frequency

MCP79 SPI Frequency Select

0

1

0

1

0

1

0

1

31 MHz

25 MHz

1 MHz

42 MHz

44

1/16W

5%

402

MF-LF

10K

NO STUFF

2

1

R6191

1/16W

5%

402

MF-LF

0

PLACEMENT_NOTE=PLACE CLOSE TO U6100

21

R6105

44

PLACEMENT_NOTE=PLACE CLOSE TO U6100

0

MF-LF

402

5%

1/16W

21

R6152

44 44

1/16W

5%

402

MF-LF

0

PLACEMENT_NOTE=PLACE CLOSE TO U6100

21

R6150

1/16W

5%

402

MF-LF

10K

NO STUFF

2

1

R6190

SOP

MX25L3205DM2I-12G

32MBIT

CRITICAL

OMIT

3

8

2

5

6

7

4

1

U6100

1/16W

5%

402

MF-LF

3.3K

2

1

R6100

1/16W

5%

402

MF-LF

3.3K

2

1

R6101

10V

20%

402

CERM

0.1UF

2

1

C6100

SYNC_DATE=07/01/2008

SYNC_MASTER=CHANG_M98_MLB

SPI ROM

051-7892

A.0.0

9754

SPI_MISO_MUX

SPI_CLK_MUX

SPI_CLK

SPI_MLB_CS_L

SPI_WP_L SPI_HOLD_L

PP3V3_S5

SPI_MISO_R

SPI_MOSI

SPI_MOSI_MUX

with R6190, R6191, R5190 and R5191

Any of the 4 frequencies can be selected

25MHz is selected with R5190 and R5191

91

7 8

18 20 22 24 26 30 34 37

38 44 64 68 69 70 82 87 96

91

IN

OUT

IN

OUT

OUT OUT

OUT

IN

IN IN IN IN

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

/SPDIF_OUT2

IN

OUT

IN

OUT

IN

OUT

OUT OUT

BP

NC

SHDN*

IN OUT

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2234

APPLE P/N 353S2355

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS

NOTES ON CODEC I/O

NC

SE FSINPUT= 1.22VRMS

DIFF FSINPUT= 2.45VRMS

AUDIO CODEC

NC

NC NC

20%

10UF

X5R 603-1

6.3V

CRITICAL

2

1

C6221

SM

21

XW6201

402-LF

2.2UF

CERM

20%

6.3V

CRITICAL

2

1

C6222

6.3V

402-LF

CERM

20%

2.2UF

CRITICAL

2

1

C6223

10UF

CRITICAL

X5R

603-1

20%

6.3V

2

1

C6220

CRITICAL

20% 16V

0603-SM

1UF

TANT

2

1

C6224

CRITICAL

402

20% 4V

4.7UF

X5R

2

1

C6210

21 91

60

58

57

58

60

56

60

20% 603

X5R

6.3V

10UF

CRITICAL

2

1

C6213

QFN

CS4206ACNZC

CRITICAL

27

1

3

44 41

9

28

29

24

46

25

49

10

48

47

13

5

8

11

19 20

18 17

16

32 33

36 37

31 30

35 34

23

21 22

39

40

38

15

14

12

2

45

42

43

4

7

6

26

U6201

56

CRITICAL

0402

FERR-220-OHM

21

L6200

2.21K

MF-LF

402

1%

1/16W

21

R6200

402

10% 16V X5R

0.1UF

2

1

C6215

402

0.1UF

X5R

16V

10%

2

1

C6211

0.1UF

402

10% 16V X5R

2

1

C6214

1% 1/16W

2.67K

402

MF-LF

2

1

R6210

402

MF-LF

100K

5% 1/16W

2

1

R6213

39

MF-LF

5%

1/16W

402

21

R6211

X5R 402

16V

10%

0.1UF

2

1

C6218

2012-LLP

16V

20% TANT-POLY

10UF

CRITICAL

2

1

C6217

TANT-POLY

20% 16V

2012-LLP

10UF

CRITICAL

2

1

C6219

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51

55 59 60 63 68 69 70 77 80

81 82 84 85 96

59

7

55

7 8

18 25 69 70 84 87

7

55

59

7

55

59

1UF

10% 10V X5R

CRITICAL

402-1

2

1

C6216

16V

0.1UF

10%

X7R-CERM

402

21

C6202

58

SM

21

XW6200

0

MF-LF

402

5%

1/16W

NOSTUFF

21

R6201

0402

FERR-220-OHM

CRITICAL

21

L6201

39

MF-LF

402

5%

1/16W

21

R6212

MAX8840-4.5V

UDFN

CRITICAL

3

6

5

1

2

4

U6200

5%

402

MF-LF

1/16W

K19

10K

2

1

R6218

402

10K

5% 1/16W MF-LF

K19I

2

1

R6219

402-1

10V X5R

1UF

10%

2

1

C6200

10V

CRITICAL

402-1

X5R

1UF

10%

2

1

C6201

1UF

10% X5R

10V

CRITICAL

402-1

2

1

C6203

10UF

CRITICAL

CASE-B2-SM

16V POLY-TANT

20%

2

1

C6225

AUDIO: CODEC/REGULATOR

051-7892

A.0.0

9755

GND_AUDIO_CODEC

VOLTAGE=0V

4V5_REG_IN

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

VOLTAGE=5V

4V5_REG_EN

PP5V_S3

4V5_NR

CS4206_FP

CS4206_FLYP CS4206_FLYC

CS4206_FLYN

GND_AUDIO_HP_AMP

AUD_LO1_P_R

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

AUD_HP_PORT_REF

NC_AUD_LO1_N_L

AUD_SDI_R

PP4V5_AUDIO_ANALOG PP3V3_S0

CS4206_FN

AUD_SPDIF_IN

CS4206_VREF_ADC

NC_AUD_LO1_P_L

HDA_SDIN0

VBIAS_DAC

AUD_LO2_P_L

AUD_MIC_INP_R

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM

VOLTAGE=0V

GND_AUDIO_HP_AMP

AUD_LO2_N_R

MIN_LINE_WIDTH=0.30MM

AUD_HP_PORT_L

MIN_NECK_WIDTH=0.20MM

PP3V3_S0

AUD_LO2_N_L

AUD_LO1_N_R

AUD_LO2_P_R

PP1V8_S0

AUD_HP_PORT_R

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

GND_AUDIO_CODEC

GND_AUDIO_HP_AMP

PP5V_S3

PP4V5_AUDIO_ANALOG

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM

VOLTAGE=4.5V

AUD_GPIO_1

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM

PP1V8_S0_AUDIO_DIG

VOLTAGE=1.8V

HDA_SDOUT HDA_RST_L

AUD_SPDIF_OUT

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM

TP_AUD_GPIO_0

AUD_LI_P_L

PP3V3_S0

AUD_LI_P_R

AUD_MIC_INN_R

HDA_SYNC

AUD_SPDIF_OUT_CHIP

MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

MIN_LINE_WIDTH=0.5MM

GND_AUDIO_CODEC

CS4206_VCOM

HDA_BIT_CLK

AUD_CODEC_MICBIAS

AUD_LI_REF

AUD_MIC_INP_L

TP_AUD_DMIC_CLK

AUD_MIC_INN_L

AUD_GPIO_3 AUD_SENSE_A

TP_AUD_GPIO_2

55 56 60

55 57 59

7

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70

77 80 81 82 84 85 96

7

55 57 59

55 56 60

55 57 59

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

55 56 60

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS

VIN = 2VRMS, CODEC VIN = 1.21 VRMS

NET RIN = 20K OHMS FC = 8 HZ

59

55

CRITICAL

3.3UF

CERM-X5R

805-1

10% 10V

21

C6301

CRITICAL

3.3UF

10% 10V

CERM-X5R

805-1

21

C6302

3.3UF

CRITICAL

CERM-X5R

805-1

10% 10V

21

C6311

CRITICAL

3.3UF

CERM-X5R

805-1

10% 10V

21

C6312

CRITICAL NOSTUFF

15PF

CERM 402

5% 50V

2

1

C6303

CRITICAL NOSTUFF

15PF

CERM 402

5% 50V

2

1

C6313

55 60

402

MF-LF

1%

6.04K

1/16W

21

R6301

MF-LF

6.04K

402

1/16W

1%

21

R6311

16.5K

402

MF-LF

1/16W

1%

2

1

R6312

16.5K

402

MF-LF

1/16W

1%

2

1

R6302

1/16W MF-LF

1%

10

402

2

1

R6300

AUDIO: LINE INPUT FILTER

A.0.0

9756

051-7892

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_REF

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_GND

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_P_R

AUD_LI_L_DIV

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_R

GND_AUDIO_CODEC

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_L

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

59

2.21K

MF-LF 402

1% 1/16W

2

1

R6502

2.21K

MF-LF 402

1% 1/16W

2

1

R6512

0.1UF

CRITICAL

X7R-CERM

402

10% 16V

2

1

C6500

402

39

MF-LF

5%

1/16W

2

1

R6500

CRITICAL

16V

10%

402

X7R-CERM

0.1UF

2

1

C6510

39

MF-LF

402

5%

1/16W

2

1

R6510

NO STUFF CRITICAL

0.0022UF

CERM

402

10% 50V

2

1

C6501

NO STUFF CRITICAL

0.0022UF

CERM

402

10% 50V

2

1

C6511

59

0

MF-LF

603

5%

1/10W

21

R6501

0

MF-LF

603

5%

1/10W

21

R6511

55

55 59

55

AUDIO: HEADPHONE FILTER

SYNC_MASTER=AUDIO

SYNC_DATE=03/16/2009

9757

051-7892

A.0.0

GND_AUDIO_HP_AMP

AUD_HP_PORT_R

AUD_HP_ZOBEL_R

AUD_HP_ZOBEL_L

AUD_HP_R

AUD_HP_PORT_L

AUD_HP_L

IN

OUT

IN

OUT

IN

OUT

IN

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SPEAKER CHECKPOINTS

PLACE C6630 CLOSE TO VDD PIN

3X MONO SPEAKER AMPLIFIERS (SSM2315)

APN: 353S2500

GAIN = 6DB

PLACE C6620 CLOSE TO VDD PIN

1ST ORDER FC (L&R) = 120 HZ +/- 30% 1ST ORDER FC (SUB) = 58HZ +/- 30%

PLACE C6610 CLOSE TO VDD PIN

100K

1/16W

402

MF-LF

5%

2

1

R6601

CRITICAL

0.033UF

X5R 402

10% 16V

21

C6610

CRITICAL

0402

FERR-1000-OHM

21

L6601

55

CRITICAL

FERR-1000-OHM

0402

21

L6610

7

59 96

7

59 96

7

59 96

CRITICAL

X5R

16V

0.033UF

402

10%

21

C6611

X5R

0.1UF

402

16V

10%

CRITICAL

2

1

C6613

20%

6.3V

CASE-A4

TANT-POLY

CRITICAL

47UF

2

1

C6622

CRITICAL

10% 16V

402

X5R

0.1UF

2

1

C6623

402

0.033UF

X5R

10% 16V

CRITICAL

21

C6620

CRITICAL

FERR-1000-OHM

0402

21

L6620

55

0

402

5% 1/16W MF-LF

2 1

R6620

1/16W

0

MF-LF

402

5%

2 1

R6621

1/16W MF-LF

5%

402

0

2 1

R6611

7

59 96

1/16W

5%

402

MF-LF

0

2 1

R6610

47UF

TANT-POLY

20%

CASE-A4

CRITICAL

6.3V

2

1

C6612

TANT

CASE-AL1

20%

6.3V

100UF

CRITICAL

2

1

C6632

CRITICAL

0.068UF

CERM

402

10% 10V

21

C6630

CRITICAL

FERR-1000-OHM

0402

21

L6630

55

7

59 96

7

59 96

MF-LF

0

402

5% 1/16W

2 1

R6630

0

MF-LF

402

5% 1/16W

2 1

R6631

CRITICAL

FERR-1000-OHM

0402

21

L6611

55

0.033UF

X5R

10% 16V

402

CRITICAL

21

C6621

CRITICAL

0402

FERR-1000-OHM

21

L6621

55

0.068UF

CERM

402

10% 10V

CRITICAL

21

C6631

CRITICAL

FERR-1000-OHM

0402

21

L6631

55

CRITICAL

0.1UF

X5R 402

10% 16V

2

1

C6633

SSM2315

CRITICAL

WLCSP

B1C2B2

C3 A3

A1

C1

B3

A2

U6610

CRITICAL

SSM2315

WLCSP

B1C2B2

C3 A3

A1

C1

B3

A2

U6620

SSM2315

WLCSP

CRITICAL

B1C2B2

C3 A3

A1

C1

B3

A2

U6630

AUDIO: SPEAKER AMP

SYNC_DATE=03/16/2009

58 97

SYNC_MASTER=AUDIO

A.0.0

051-7892

PP5V_S3_AUDIO_AMP

SPKRAMP_R_OUT_P

SSM2315R_N

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L_OUT_N

SSM2315L_P

AUD_LO2_P_L

NO_TEST=TRUE

AUD_SPKRAMP_INP_L

SSM2315L_N

AUD_SPKRAMP_SHUTDOWN_L

NO_TEST=TRUE

AUD_SPKRAMP_INN_L

SPKRAMP_L_OUT_P SPKRAMP_L_OUT_N

NO_TEST=TRUE

AUD_SPKRAMP_INP_R

PP5V_S3_AUDIO_AMP

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_L_OUT_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRCONN_S_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_S_OUT_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L_OUT_P

SSM2315S_P

NO_TEST=TRUE

AUD_SPKRAMP_INP_SUB

SSM2315R_P

SPKRAMP_R_OUT_N

PP5V_S3_AUDIO_AMP

SPKRAMP_S_OUT_P SPKRAMP_S_OUT_N

AUD_SPKRAMP_SHUTDOWN_L

SSM2315S_N

AUD_LO2_N_R

AUD_SPKRAMP_INN_SUB NO_TEST=TRUE

AUD_LO2_P_R

AUD_GPIO_3

AUD_LO1_N_R

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_OUT_N

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRCONN_S_OUT_N

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_S_OUT_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_R_OUT_N

AUD_LO1_P_R

AUD_LO2_N_L

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_L_OUT_N

AUD_SPKRAMP_SHUTDOWN_L

AUD_SPKRAMP_INN_R

NO_TEST=TRUE

9

58

58 96

58

58 96

9

58

58 96

9

58

58 96

58

58 96

58

IN IN

OUT

OUT OUT OUT

IN

PINS

SHELL

SHIELD

POF

A - VDD B - GND

C - VOUT

OPERATING VOLTAGE 3.3

AUDIO

SWITCH

LEFT

RIGHT

GROUND

DETECT FOR PLUG TYPE

OUT

RIGHT

MIC

AUDIO

GND

LEFT

SWITCH

DETECT

B - VCC

POF

SHIELD

SHELL

PINS

C - GND

A - VIN

OPERATING VOLTAGE 3.3

BI

OUT

BI

OUT

IN

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AUDIO JACK 1 LO/HP JACK, SPDIF TX

APN: 514-0671

SPEAKER CONNECTOR

MIC CONNECTOR

GND PATCH

APN: 518S0519

APN: 518S0521

AUDIO JACK 2 LINE IN JACK, SPDIF RX

APN: 514-0635

APN: 518S0520

7

58 96

7

58 96

7

58 96

7

58 96

1/16W

5%

MF-LF

4.7

402

21

R6749

10% X5R

1UF

10V 402-1

2

1

C6750

FERR-220-OHM

0402

CRITICAL

21

L6751

CRITICAL

6.8V-100PF

402

2

1

DZ6701

402

6.8V-100PF

CRITICAL

2

1

DZ6751

402

6.8V-100PF

CRITICAL

2

1

DZ6758

0402

FERR-220-OHM

CRITICAL

21

L6758

402

CRITICAL

6.8V-100PF

2

1

DZ6700

402

6.8V-100PF

CRITICAL

2

1

DZ6706

402

6.8V-100PF

CRITICAL

2

1

DZ6704

402

6.8V-100PF

CRITICAL

2

1

DZ6754

55 57

0402

FERR-1000-OHM

CRITICAL

21

L6702

0402

CRITICAL

FERR-1000-OHM

21

L6703

402

6.8V-100PF

CRITICAL

2

1

DZ6703

7

60

7

60

7

60

FERR-1000-OHM

0402

CRITICAL

21

L6705

0402

FERR-1000-OHM

CRITICAL

21

L6752

10% 402

X5R

0.1UF

16V

2

1

C6700

M-RT-SM

78171-0004

CRITICAL

4

3

2

1

6

5

J6782

M-RT-SM

78171-0003

CRITICAL

3

2

1

5

4

J6780

M-RT-SM

78171-0002

CRITICAL

2

1

4

3

J6781

7

58 96

7

58 96

6.3V

20%

2.2UF

402-LF

CERM

2

1

C6701

1/16W

5%

402

MF-LF

0

21

R6701

FERR-1000-OHM

0402

CRITICAL

21

L6754

F-RT-TH5

AUDIO-RCVR-M97

8

6

2

3

1

9

12

11

10

4

7

5

J6750

50V

5%

402

CERM

33PF

CRITICAL

NOSTUFF

2

1

C6782

50V

5%

402

CERM

33PF

CRITICAL

NOSTUFF

2

1

C6781

50V

5% 402

CERM

33PF

CRITICAL

NOSTUFF

2

1

C6784

50V

5%

402

CERM

33PF

CRITICAL

NOSTUFF

2

1

C6783

60

0402

FERR-1000-OHM

CRITICAL

21

L6756

60

F-RT-TH

SPDIF-TXRX-K24

2

3

6

1

9

8

7

13

12

11

10

4

5

J6700

55

402

6.8V-100PF

CRITICAL

2

1

DZ6756

SM

21

XW6702

SM

21

XW6701

FERR-220-OHM

0402

CRITICAL

21

L6707

50V

5%

402

CERM

100PF

2

1

C6756

55

56

60

55

57

0603

FERR-220-OHM-2.5A

CRITICAL

21

L6701

FERR-220-OHM

0402

CRITICAL

21

L6704

CRITICAL

FERR-220-OHM

0402

21

L6706

60

1/16W

402

MF-LF

10K

5%

21

R6700

CERM

50V

5%

402

100PF

2

1

C6705

A.0.0

AUDIO: JACKS

051-7892

SYNC_MASTER=AUDIO

9759

SYNC_DATE=03/16/2009

AUD_HP_PORT_REF

GND_AUDIO_HP_AMP

AUD_HP_R

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_SLEEVE

AUD_CONNJ1_RING

HS_MIC_LO

AUD_SPDIF_OUT

AUD_HP_L

AUD_CONNJ1_TIP

AUD_CONNJ1_TIPDET

AUD_J1_SLEEVEDET_R

HS_MIC_HI

AUD_CONNJ1_SLEEVE2

PP3V3_S0

GND_CHASSIS_AUDIO_JACK

MIN_NECK_WIDTH=0.10 MM VOLTAGE=0V

MIN_LINE_WIDTH=0.30 mm

GND_CHASSIS_AUDIO_JACK

BI_MIC_HI

AUD_J2_TIPDET_R

SPKRCONN_S_OUT_P

SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N

SPKRCONN_S_OUT_N

AUD_LI_L

AUD_LI_R

AUD_LI_GND

PP3V3_S0

SPKRCONN_L_OUT_N

SPKRCONN_L_OUT_P

AUD_J1_TIPDET_R

BI_MIC_SHIELD

BI_MIC_LO

GND_CHASSIS_AUDIO_JACK

AUD_SPDIF_IN

AUD_CONNJ2_SLEEVE

AUD_CONNJ2_SLEEVEDET

AUD_CONNJ2_TIPDET

AUD_CONNJ2_RING

AUD_CONNJ2_TIP

AUD_J2_OPT_OUT

6 7 8

13 18 19

21 22 24 25 28 29 37 39

43 45 47 48 49

51 55 59 60 63 68 69 70

77 80 81 82 84

85 96

9

59

9

59

56

6 7 8

13 18 19 21 22

24 25 28 29 37

39 43 45 47

48 49 51 55 59

60 63 68 69

70 77 80 81 82

84 85 96

9

59

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

D

G S

OUT

IN

OUT

IN

OUT

IN

BI

IN

OUT

VDD

GND

MR*

RST*

D

SG

D

SG

IN

GND THM

ENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASS

INT*

SCL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PIN COMPLEX

0X0D (13,V22,B,LEFT)

DET ASSIGNMENT

0X0C (B)

N/A

0X09 (A)

0X09 (9,A) 0X0B (11)

0X0D (13,B,RIGHT)

N/A

PORT B RIGHT(BUILT-IN MIC)

0X03 (03)

PORT B LEFT(HEADSET MIC)

DRC MIKEY

HP=80HZ, LP=8.82KHZ

CONVERTER

0X0F (15)

FUNCTION LINE IN SPDIF IN BUILT-IN MIC

EXTRACTION NOTIFICATION

APN:353S2401

HEADSET MIC

APN:376S0612

NC

PLACE L6800/C6800 CLOSE TO U6800

0X02 (2)

NC

SUB SPDIF OUT

FUNCTION

SATELLITES

HP/LINE OUT

CODEC INPUT SIGNAL PATHS

VOLUME

N/A

0X02 (2) 0X04 (4) 0X03 (3)

0X08 (8)

0X05 (5) 0X07 (7) 0X06 (6) 0X06 (6)

PIN COMPLEX

N/A

VREF

MIKEY

MIC_BIAS (80%)

MIKEY

N/A

DET ASSIGNMENT

CONVERTER

0X10 (16)

0X0C (12,C)

PORT C DETECT (LINE-IN)

APN:353S2256

PULLUPS ON MCP PAGE

0X0C (12,C)

N/A

0X04 (4)

CODEC OUTPUT SIGNAL PATHS

HP=80HZ

GPIO_3

N/A

MUTE CONTROL

GPIO_3

0X0A (10)

APN:376S0613

NC

PORT B DETECT(SPDIF DELEGATE)

PORT A DETECT (HEADPHONES)

10V

20%

402

CERM

0.1UF

2

1

C6801

1/16W

5%

402

MF-LF

47K

21

R6802

1/16W

5%

402

MF-LF

220K

2

1

R6801

59 60

39.2K

1/16W

1%

402

MF-LF

2

1

R6806

1/16W

5%

402

MF-LF

220K

21

R6803

1/16W

5%

402

MF-LF

220K

2

1

R6804

16V

10%

402

CERM

0.01UF

2

1

C6802

55 60

59 60

1/16W

1%

402

MF-LF

10K

2

1

R6813

10V

20%

402

CERM

0.1UF

2

1

C6811

1/16W

5%

402

MF-LF

270K

2

1

R6811

1/16W

5%

402

MF-LF

47K

21

R6812

59

MF-LF

1/16W

1%

402

20.0K

2

1

R6805

SOT563

SSM6N15FEAPE

4

5

3

Q6800

SOT563

SSM6N15FEAPE

1

2

6

Q6800

SOT563

SSM6N15FEAPE

4

5

3

Q6801

SOT563

SSM6N15FEAPE

1

2

6

Q6801

SOD-VESM-HF

SSM3K15FV

2

1

3

Q6802

55 60

402-1

MF

2.4K

1/16W

1%

21

R6851

CERM

CRITICAL

50V

5%

402

27PF

2

1

C6854

0.1UF

CRITICAL

25V

10%

402

X5R

21

C6850

50V

10%

402

CERM

0.001UF

CRITICAL

2

1

C6853

100K

1/16W

5%

402

MF-LF

2

1

R6852

SM

21

XW6851

55

7

59

7

59

7

59

CRITICAL

6.3V

20%

402

TANT

2.2UF

2

1

C6852

FERR-1000-OHM

0402

21

L6851

FERR-1000-OHM

0402

21

L6850

59

1/16W

5%

402

MF-LF

2.2K

MIKEY

2

1

R6882

50V

5%

402

MIKEY

CERM

27PF CRITICAL

2

1

C6885

25V

10%

402X7R

0.0082UF

MIKEY

CRITICAL

2

1

C6884

1/16W

5%

402

MF-LF

100K

MIKEY

2

1

R6883

25V

10%

402

X5R

CRITICAL

MIKEY

0.1UF

21

C6883

SM

21

XW6880

55

MIKEY

1/16W

1%

402

MF-LF

1K

2

1

R6881

MIKEY

1/16W

5%

402

MF-LF

100K

2

1

R6880

16V

10%

402

CERM

0.01UF

MIKEY

2

1

C6881

MIKEY

0402

FERR-1000-OHM

CRITICAL

21

L6880

6.3V

20%

603 X5R

10UF

MIKEY

CRITICAL

2

1

C6880

6.3V

20% 402

TANT

2.2UF

CRITICAL

MIKEY

2

1

C6882

21

21 45 85 91

19

MIKEY

1/16W

5%

402

MF-LF

2.2K

21

R6884

25V

10%

402

X5R

0.1UF

CRITICAL

MIKEY

21

C6886

55

CRITICAL

25V

10%

402

X5R

0.1UF

21

C6851

402

100

1/16W

1%

MF-LF

21

R6850

402-1

1%

1/16W

MF

2.4K

21

R6853

17

SC-70-1

TPS3801E18DCK

EXTRACT_DEBOUNCE

4

35

21

U6860

SOT563

SSM6N15FEAPE

EXTRACT_BUFF

1

2

6

Q6803

1/16W

5%

402

MF-LF

100

21

R6861

10V

20%

402

CERM

0.1UF

2

1

C6861

0402

FERR-1000-OHM

CRITICAL

21

L6862

220K

MF-LF

402

5%

1/16W

EXTRACT_BUFF

21

R6864

1/16W

5%

402

MF-LF

100K

EXTRACT_BUFF

21

R6865

SOT563

SSM6N15FEAPE

EXTRACT_BUFF

4

5

3

Q6803

EXTRACT_BUFF

10V

20% CERM

0.1UF

402

2

1

C6860

EXTRACT_BUFF

1/16W

5%

402

MF-LF

15K

21

R6860

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51

55 59 60 63 68 69 70 77 80

81 82 84 85 96

DRC

CD3275

MIKEY

11

5

6

1

7

4

9

8

2

10

3

U6880

AUDIO: JACK TRANSLATORS

SYNC_MASTER=AUDIO

051-7892

60 97

A.0.0

SYNC_DATE=03/16/2009

AUD_PORTB_DET_L

AUD_SENSE_A

AUD_J1_SLEEVEDET_R

AUD_OUTJACK_INSERT_L

SMBUS_MCP_1_DATA AUD_I2C_INT_L AUD_IPHS_SWITCH_EN

GND_AUDIO_CODEC

BI_MIC_HI_F

BI_MIC_LO_F

PP3V3_S0

AUD_J1_TIPDET_INV

AUD_PERPH_DET_R

PP3V3_S0_AUDIO_F

MIN_LINE_WIDTH=0.1MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM PP3V3_S0_AUDIO_F

GND_AUDIO_CODEC

AUD_J1_TIPDET_R

AUD_MIC_INP_R

SMBUS_MCP_1_CLK

PP3V3_S0_HS_RX

MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.1MM

GND_AUDIO_CODEC

AUD_MIC_INP_L

AUD_SENSE_A

BI_MIC_HI

AUD_MIC_INN_R

GND_AUDIO_CODEC

AUD_MIC_INN_L

HS_MIC_HI

AUD_PORTA_DET_L

AUD_J1_DET_RC

AUD_J1_SLEEVEDET_R

AUD_J1_TIPDET_R

TIPDET_FILT

GND_AUDIO_CODEC

AUD_IP_PERIPHERAL_DET

AUD_J1_TIPDET_R

PP3V3_S0

PP3V3_S0_AUDIO_F

AUD_INJACK_INSERT_L

AUD_J2_DET_RC

GND_AUDIO_CODEC

AUD_J2_TIPDET_R

BI_MIC_LO

GND_AUDIO_CODEC

BI_MIC_SHIELD

AUD_CODEC_MICBIAS

GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

AUD_J1_SLEEVEDET_INV

PP3V3_S0_AUDIO_F

HS_MIC_LO

HS_MIC_BIAS HS_SW_DET

HS_RX_BP

MIC_BIAS_FILT

HS_MIC_HI_RC

59 60

55 56 60

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

60

55 56 60

59 60

55 56 60

59 60

60

55 56 60

60

BI

NC

VCC

EXTINT

NC

GND

Y

B

A

IN

P3 P4 P5 P6 P7 P8

P1 P2

P9

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

OUT

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

OUT

NC

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

NC

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

connected.

send transients onto ADAPTER_SENSE when AC is

PWR

SIG

GND

PWR

GND

250mA max output

Vout = 3.425

(Switcher limit)

NC

516S0523

<Ra>

NC

BATTERY CONNECTOR

518-0358

TO SMC

BIL CONNECTOR

MagSafe DC Power Jack

1-Wire OverVoltage Protection

The chassis ground will otherwise float and can

1206-2

CRITICAL

6AMP-24V

21

F6905

PLACEMENT_NOTE=Place near L6900

50V

20% CERM

603

0.01UF

2

1

C6905

42

47

MF-LF

5%

1/8W

805

21

R6905

25V

10%

10UF

805

X5R

2

1

C6990

33UH

CDPH4D19FHF-SM

CRITICAL

21

L6995

5%

402

CERM

50V

22pF

2

1

C6995

200K

MF-LF 402

1/16W

1%

2

1

R6996

MF-LF 402

1% 1/16W

348K

2

1

R6995

22UF

X5R-CERM 603

20%

6.3V

2

1

C6999

HN2D01JEAPE

SOT665

2

4

5

3

1

D6905

X5R

6.3V

20%

402

0.22UF

2

1

C6994

M-RT-SM

78048-0573

CRITICAL

5

4

3

2

1

J6900

CRITICAL

MAX9940

SC70-5

1

3

4

2

5

U6900

402

10V

PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

CERM

20%

0.1UF

2

1

C6908

SOT665

TC7SZ08AFEAPE

4

5

3

1

2

U6901

42 43 62

RCLAMP2402B

SC-75

NO STUFF

CRITICAL

2

1

3

D6900

SC-75

RCLAMP2402B

CRITICAL

2

1

3

D6950

10K

5%

MF-LF

1/16W

402

2

1

R6950

25V X5R

0.1UF

10%

402

2

1

C6950

BAT-K19

CRITICAL

M-RT-TH

9

8

7

6

5

4

3

2

1

13

12

11

10

J6950

CERM

0.001UF

50V

402

10%

2

1

C6954

5%

402

47PF

CERM

50V

2

1

C6953

402

5%

50V

47PF

CERM

2

1

C6952

CRITICAL

CPB6312-0101F

F-ST-SM

9

8 7

6 5

4 3

2

16 15

14 13

12 11

10

1

J6955

X5R

25V

402

0.1UF

10%

2

1

C6951

0.001UF

CERM

402

10% 50V

2

1

C6955

MF-LF

100

1/16W

402

5%

2 1

R6961

42 43 50

CRITICAL

DFN

LT3470A

6

9

48

7

5

1

3

2

U6990

7

42 43

7

42 45 61 62

94

7

42 45

61

62 94

402

MF-LF

1/16W

5%

2.0K

2

1

R6929

SYNC_DATE=12/16/2008

SYNC_MASTER=YUN_K19_MLB

A.0.0

051-7892

9761

DC-In & Battery Connectors

ADAPTER_SENSE

SMC_BIL_BUTTON_L

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

PP3V42_G3H

SMC_BC_ACOK

SMC_LID_R

SMC_LID

SYS_DETECT_L

SMBUS_SMC_BSA_SCL

PPBUS_G3H

SMBUS_SMC_BSA_SDA

PP3V42_G3H

PPVBAT_G3H_CONN

GND

PPDCIN_G3H

PP18V5_DCIN_FUSE

MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V

PPDCIN_G3H

SMC_BC_ACOK_VCC

SYS_ONEWIRE

P3V42G3H_BOOST

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.3 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

PPDCIN_S5_P3V42G3H

VOLTAGE=18.5V

P3V42G3H_FB

PP3V42_G3H

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

DIDT=TRUE

7

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

7

42 45 61 62 94

7 8

37 46 62 64 65 66 67 79

83 86

7 42 45 61 62 94

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7

62

8

61 62

7

8

61 62

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF ACIN

SDA

VHST SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

NC

OUT

IN BI

OUT

GND

VCC

D

S G

D

S G

D

G

S

D

G

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

152S0542

Max Current = 8.5A

(CHGR_AGATE)

Inrush Limiter

ACIN pin threshold

(L7030 limit)

Reverse-Current Protection

3S Battery Default

2S Battery Default

32V/V

30mA max load

f = 400 kHz

(OD)

20V/V

R7075 clamps CHGR_AMON when charger is

TO SYSTEM

not powered to counter TL331 bias current.

VREF = 3.2V, < 300uA

Divider sets ACIN

is 3.2V, +/- 50mV

Input impedance of ~40K meets

threshold at 13.07V

(CHGR_CSO_P)

(CHGR_DCIN)

FROM ADAPTER

sparkitecture requirements

1%

402

MF-LF

1/16W

9.31K

2

1

R7011

16V

10%

402

X5R

0.033UF

2

1

C7042

50V

10% 402

CERM

470PF

2

1

C7016

3.01K

1/16W

1%

402

MF-LF

2

1

R7016

50V

10%

402

CERM

0.001UF

2

1

C7015

1/16W

1%

402

MF-LF

56.2K

2

1

R7015

402-1

10V

10% X5R

1UF

2

1

C7002

1UF

X5R

10% 10V

402-1

2

1

C7000

1/16W

5%

402

MF-LF

4.7

21

R7001

1SS418

SOD-723-HF

2

1

D7005

MF-LF

1/16W

1%

402

30.1K

2

1

R7010

0.1UF

25V

10% 402

X5R

2

1

C7060

470K

1/16W

5%

402

MF-LF

2

1

R7060

1/16W

1%

402

MF-LF

1.82K

2

1

R7071

1/16W

1%

402

MF-LF

57.6K

2

1

R7070

CERM

0.01uF

16V

10%

402

2

1

C7057

0.1UF

16V

10% 402

X5R

2

1

C7056

SM

21

XW7000

ISL6258A

CRITICAL

QFN

OMIT

4

8

12

20

19

7

24

13

29

10

11

23

22

21

5

2

18 17

28 27

25

15

16

9

26

6

1

14

3

U7000

402-1

1UF

10V

10% X5R

2

1

C7001

10% 25V

402

X5R

0.1UF

2

1

C7021

0.1UF

X5R 402

25V

10%

2

1

C7022

10V 402

0.047UF

10% CERM

2

1

C7020

0.1UF

25V

10% 402

X5R

2

1

C7035

LFPAK-HF

CRITICAL

RJK0305DPB

321

4

5

Q7035

MF-LF

1/16W

5%

402

10

21

R7022

402

MF-LF

1/16W

10

5%

21

R7021

25V

20%

CASE-D2-SM

POLY-TANT

22UF

CRITICAL

2

1

C7030

CRITICAL

25V

20%

CASE-D2-SM

22UF

POLY-TANT

2

1

C7031

25V

10%

603-1

X5R

1UF

2

1

C7032

CASE-D2-SM

POLY-TANT

25V

CRITICAL

20%

22UF

2

1

C7040

8AMP-24V

CRITICAL

1206-2

2

1

F7040

MF-LF

402

1/16W

5%

10

21

R7051

MF-LF

5%

1/16W

402

10

21

R7052

25V

10%

603-1

X5R

1UF

2

1

C7033

SOD-723-HF

1SS418

NOSTUFF

21

D7040

1/16W

5%

402

MF-LF

62K

2

1

R7066

1/16W

5%

402

MF-LF

100K

2

1

R7065

25V

10%

603-1

X5R

1UF

2

1

C7055

1/16W

330K

402

MF-LF

5%

2

1

R7061

402

25V

10% X5R

0.1UF

2

1

C7005

46

46 62

7

42 45 61 94

7

42 45 61 94

0.01UF

16V

10%

402

CERM

2

1

C7011

0.1uF

16V

10%

402

X5R

2

1

C7070

0.1uF

16V

10% 402

X5R

2

1

C7050

0.001UF

50V

10% CERM

402

2

1

C7026

42 43 61

0612-1

MF

0.5% 1W

CRITICAL

0.01

4 3

2 1

R7050

1W MF 0612-1

CRITICAL

0.5%

0.02

432

1

R7020

SOT23-5

TL331

2

5

4

3

1

U7070

FDA1254F-SM

CRITICAL

4.7UH-10.2A

3

2

1

L7030

SOT563

SSM6N15FEAPE

4

5

3

Q7074

1/16W

5%

402

MF-LF

1M

2

1

R7074

SOT563

SSM6N15FEAPE

1

2

6

Q7074

50V

10%

402

X7R

0.001UF

2

1

C7034

0.001UF

50V

10%

402

X7R

2

1

C7041

SO-8

CRITICAL

SI7137DP

321

4

5

Q7055

CRITICAL

SOI

HAT1128R01

321

4

8765

Q7060

CRITICAL

HAT1128R01

SOI

321

4

8765

Q7065

RJK0305DPB

CRITICAL

LFPAK-HF

321

4

5

Q7030

CRITICAL

ISL6258

353S1811

1

IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L

U7000

051-7892

SYNC_MASTER=M99_MLB

PBus Supply & Battery Charger

SYNC_DATE=12/10/2007

A.0.0

9762

IC,ISL6258A,BAT CHARGER,4X4MM,QFN28

U7000

1

353S1832 ISL6258ACRITICAL

CHGR_PHASE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PPDCIN_S5_FET_CHGR

CHGR_UGATE

DIDT=TRUE

CHGR_ACIN

CHGR_VNEG

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=5.1V

PP5V1_CHGR_VDD

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

CHGR_ICOMP CHGR_VCOMP

PPDCIN_S5_CHGR_R

MIN_LINE_WIDTH=0.6 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

CHGR_CSI_R_N

MIN_LINE_WIDTH=0.3 mm

CHGR_SGATE_DIV

MIN_NECK_WIDTH=0.3 mm

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm

CHGR_AMON

SGATE_P0V1_VREF

AMON_CLAMP

PP5V1_CHGR_VDD

CHGR_VCOMP_R

CHGR_VNEG_R

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

PPVBAT_G3H_CONN

MIN_NECK_WIDTH=0.4 mm

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

CHGR_SGATE

PPBUS_G3H

CHGR_CSO_N

PPDCIN_S5_INRUSH

MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.2 mm

GND_CHGR_AGND

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

CHGR_CSO_P

CHGR_CSO_R_P

CHGR_BMON

CHGR_CSI_P

CHGR_AGATE

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

CHGR_BGATE

TP_CHGR_TRKL

CHGR_LGATE

DIDT=TRUE

CHGR_CSO_R_N

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

PPVBAT_G3H_CHGR_R

SMC_BC_ACOK

CHGR_AMON

CHGR_BOOT

PPDCIN_G3H

CHGR_CSI_N

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_REG

CHGR_CSI_R_P

CHGR_DCIN

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

62

96

46 62

62

7

61

7 8

21 22 26 40 42 43 44 45 46

50 61 62 64 69

7 8

37 46 61 64 65 66 67 79 83

86

94

46 96

94

46

96

8

61

94

96

IN

OUT IN OUT

IN

OUT OUT

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

S

G

D

G

S

G

D

G

S

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

These caps are for Q7100

Place R7131 Between L7100,L7101 and CPU

DCM

(PGD_IN)

(IMVP6_NTC)

These caps are for Q7102

(IMVP6_VW)

(IMVP6_COMP)

(GND)

(IMVP6_VO)

10

0

1

CCM

(IMVP6_VSUM)

LAYOUT NOTE:

(ISL9504A)

(GND)

PSI*

CCM

Mode

(IMVP6_VO)

1

0

spot of reg circuit.

Place R7126 in hot

(GND_IMVP6_SGND)

Operation

44A MAX CURRENT

(GND_IMVP6_SGND)

(IMVP6_FB)

1-Phase DCM

2-Phase

1

DPRSTP*

1-Phase0 1 1 1-Phase

DPRSLPVR

0

(IMVP6_ISEN1)

(IMVP6_PHASE2)

(IMVP6_ISEN2)

(IMVP6_PHASE1)

10K

MF-LF

402

1%

1/16W

21

R7100

0.22UF

CERM

402

10% 10V

21

C7103

SM

2 1

XW7104

0.22UF

X5R 603

20% 25V

2

1

C7115

9

10 14 88

21 88

10

9

63

26

SM

2 1

XW7102

1/16W

10K

MF-LF

402

1%

21

R7105

0.22UF

CERM

402

10% 10V

21

C7104

0.22UF

603

20% 25V X5R

2

1

C7127

10

MF-LF

402

1%

1/16W

21

R7120

10

MF-LF

402

1%

1/16W

21

R7112

10V

10% X5R

1UF

402-1

2

1

C7126

10

MF-LF

402

1%

1/16W

21

R7121

X5R 402

16V

10%

0.1uF

2

1

C7130

499

MF-LF

402

1%

1/16W

21

R7119

0.001UF

CERM

402

10% 50V

2

1

C7107

6.81K

MF-LF 402

1% 1/16W

2

1

R7110

4.7UF

X5R-CERM 402

20%

6.3V

2

1

C7135

0.01uF

CERM

402

10% 16V

2

1

C7110

1K

MF-LF

402

1%

1/16W

2

1

R7113

1K

MF-LF 402

1% 1/16W

2

1

R7109

220PF

X7R-CERM

402

10% 50V

2

1

C7113

97.6K

MF-LF

402

1%

1/16W

2

1

R7114

1

MF-LF 402

5% 1/16W

2

1

R7104

1

MF-LF 402

5% 1/16W

2

1

R7107

NO STUFF

0.001uF

CERM

402

10% 50V

2

1

C7116

1%

4.42K

1/16W MF-LF

402

21

R7117

180pF

CERM 402

5% 50V

2

1

C7129

1K

MF-LF 402

1% 1/16W

2

1

R7118

2.61K

MF-LF

402

1%

1/16W

2

1

R7130

MF-LF

1% 1/16W

402

11K

2

1

R7115

0.22UF

CERM-X5R

402

10%

6.3V 2

1

C7128

0.068UF

CERM 402

10% 10V

2

1

C7134

MF-LF

402

5%

1/16W

0

21

R7122

0.01UF

CERM

402

10% 16V

2

1

C7131

16V CERM

10%

NO STUFF

0.01uF

402

2

1

C7132

0

MF-LF

402

5%

1/16W

21

R7123

0.01uF

CERM

402

10% 16V

2

1

C7133

0.22UF

X5R 402

20%

6.3V

2

1

C7121

SM

21

XW7100

3.65K

MF-LF 603

1% 1/10W

2

1

R7101

3.65K

MF-LF 603

1% 1/10W

2

1

R7106

MPCG1040-SM

0.36UH-26A-1.05MOHM

CRITICAL

21

L7100

MPCG1040-SM

0.36UH-26A-1.05MOHM

CRITICAL

21

L7101

0.1UF

X5R 402

10% 16V

2

1

C7196

9

88

9

88

9

88

9

88

9

88

9

88

9

88

0.001UF

CERM 402

10% 50V

2

1

C7106

470PF

CERM 402

10% 50V

2

1

C7114

255

MF-LF

402

1%

1/16W

2

1

R7111

0.015UF

X7R 402

10% 16V

2

1

C7105

13.3K

MF-LF 402

1% 1/16W

2

1

R7116

1UF

X5R

10% 25V

603-1

2

1

C7109

CRITICAL

10KOHM-5%

0603-LF

2

1

R7131

147K

MF-LF 402

1% 1/16W

2

1

R7108

1/16W

4.02K

MF-LF

402

1%

2

1

R7127

10K

MF-LF 402

5% 1/16W

2

1

R7197

SM

21

XW7103

SM

21

XW7101

63

11 88

470K

402

CRITICAL

2

1

R7126

0

MF-LF

402

5%

1/16W

21

R7198

10 14 43 88

MF-LF 402

5%

68

1/16W

2

1

R7199

ISL9504BCRZ

QFN

9

19

14

5

44

18

20

43 42 41 40 39 38 37

13

22

27

35

49

7

15

4

31

2

28

34

1

29

33

8

6

25

30

32

23

24

3

21

12 11

16

46 45

17

10

47

26

36

48

U7100

S1

IRF6710

CRITICAL

3

4 6

5

2

1

Q7100

IRF6795

CRITICAL

DIRECTFET-MX

43

5

7621

Q7103

IRF6710

S1

CRITICAL

3

4 6

5

2

1

Q7102

CRITICAL

IRF6795

DIRECTFET-MX

43

5

7621

Q7101

CRITICAL

20%

68UF

POLY-TANT

16V

CASE-D2E-SM

2

1

C7117

20%

68UF

POLY-TANT

16V

CASE-D2E-SM

CRITICAL

2

1

C7153

CRITICAL

20%

68UF

POLY-TANT

16V

CASE-D2E-SM

2

1

C7155

1UF

X5R 603-1

10% 25V

2

1

C7154

46

I848I849

0

MF-LF

402

5%

1/16W

21

R7160

0.001UF

X7R 402

50V

10%

2

1

C7108

0.001UF

X7R 402

10% 50V

2

1

C7152

0.001UF

X7R 402

10% 50V

2

1

C7156

0.001UF

X7R 402

10% 50V

2

1

C7157

IMVP6 CPU VCore Regulator

SYNC_MASTER=M87_MLB

051-7892

A.0.0

63 97

SYNC_DATE=10/17/2007

PPVIN_S5_IMVP6_VIN

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

PP5V_S0

IMVP6_ISEN1

IMVP6_UGATE2

DIDT=TRUE

IMVP6_LGATE2

DIDT=TRUE

IMVP6_LGATE1

VR_PWRGOOD_DELAY

IMVP_DPRSLPVR CPU_PSI_L IMVP6_IMON

IMVP6_BOOT2

IMVP6_VSUM2

CPU_PROCHOT_L

IMVP6_SOFT

IMVP6_VDIFF

IMVP6_VSEN_P

IMVP6_FB

IMVP_VR_ON_R

PP5V_S0_IMVP6_VDD

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_VID<5>

IMVP6_VID<3>

IMVP6_VR_TT_L IMVP6_NTC

IMVP6_RBIAS

IMVP6_COMP_RC

IMVP6_COMP IMVP6_VW

IMVP6_FB2

PP3V3_S0

PPCPUVTT_S0

IMVP6_VID<2>

CPU_DPRSTP_L

TP_IMVP6_CLKEN_L

IMVP6_NTC_R

IMVP6_VW

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_LGATE2

IMVP6_VO2

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO2

IMVP_VR_ON

IMVP6_VDIFF_RC

IMVP_VR_ON_R

IMVP6_VSEN_P

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_ISEN1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_UGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_VSUM1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_OCSET

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VO

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DFB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_RBIAS

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VDIFF

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_FB2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_PHASE1

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_BOOT1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_LGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_VO1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_VO1

CPU_VCCSENSE_N

CPU_VCCSENSE_P

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_UGATE2

IMVP6_BOOT2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_PHASE2

PM_DPRSLPVR

IMVP6_COMP

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_SOFT

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VO_R

IMVP6_FB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DROOP

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VID<6>

IMVP6_BOOT1

IMVP6_OCSET

IMVP6_PHASE1

DIDT=TRUE

IMVP6_PHASE2

DIDT=TRUE

PPVCORE_S0_CPU

IMVP6_VSUM1

IMVP6_VO

IMVP6_ISEN2

DIDT=TRUE

IMVP6_UGATE1

IMVP6_DROOP

IMVP6_DFB

IMVP6_VSUM

IMVP6_VID<1>

IMVP6_VID<4>

PP3V3_S0_IMVP6_3V3

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

IMVP6_VSEN_N

IMVP6_ISEN2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_VSUM2

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

PPBUS_CPU_IMVP_ISNS

IMVP6_VSEN_N

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_VID<0>

MIN_NECK_WIDTH=0.20 MM

GND_IMVP6_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.50 MM

7 8

39 44 49 51

66 67 70 83 85

63

88

63

63 88

63

6 7 8

13 18 19 21

22 24 25 28 29 37

39 43 45 47 48 49

51 55 59 60 68 69

70 77 80 81 82 84

85 96

6 7 8 9

10 11 12

13 14 17 18 20 22

24 25 67

63

42 63

63 88

63

7 8

11 12 46

63

63 88

63

8

46

63 88

OUT

Q1

Q2

SW

DRVH1

SKIPSEL

VBST1

GND

THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREF

VIN

TONSEL

D

SG

D

SG

D

SG

G

D

S

G

D

S

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

5.5A max output

(L7260 limit)

Vout = 3.3V

f=460KHz

M99 differences from last sync on 11/01/07 to M88 MLB:

.

4. Added R7200, R7220,R7221, R7260,R7261, C7201.

(P3V3S5_V02)

One master PGOOD for both 5V and 3V3

1. L7260 changed from M88 MLB inductors to 152S0693.

2. Q7220 changed to 372S0512. Q7225 changed to 376S0511.

(P5VS5_VO1)

Vout = 5.0V

f=365KHz

(Q7220 limit)

3. U7200 changed to 353S2087.

10.5A max output

25V

10%

603-1

X5R

1UF

2

1

C7200

IHLP2525CZ

4.7UH-5.5A

CRITICAL

21

L7260

25V

1UF

10% 603-1

X5R

2

1

C7241

10% 50V

603-1

X7R

0.1UF

2

1

C7264

603

X5R

20%

6.3V

10UF

2

1

C7290

603-1

50V

10% X7R

0.1UF

2

1

C7224

330UF

CASE-D3L-SM1

CRITICAL

20%

POLY-TANT

6.3V

2

1

C7252

805

10V

20% X5R

10UF

2

1

C7250

CRITICAL

20%

150UF-.025-OHM

CASE-B2-SM

TANT

6.3V

2

1

C7292

POLY-TANT

CASE-D2-SM

25V

20%

CRITICAL

22UF

2

1

C7240

25V

10%

603-1

X5R

1UF

2

1

C7281

25V

20%

CASE-D2-SM

POLY-TANT

22UF

CRITICAL

2

1

C7280

X5R

6.3V

20%

603

10UF

2

1

C7203

6.3V 603

X5R

10UF

20%

2

1

C7205

75K

1/16W

1%

402

MF-LF

2

1

R7206

66 67 68 69

SM

PLACEMENT_NOTE=Place XW7260 next to L7260.

2

1

XW7260

PLACEMENT_NOTE=Place XW7220 next to L7220.

SM

2

1

XW7220

NO STUFF

25V

5% 402

CERM

220PF

2

1

C7208

SM

PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.

21

XW7200

CRITICAL

FDMS9600S

MLP

10

7

6 5

8

1

9 4 3 2

Q7260

TPS51125

QFN

17

8

3

724

16

52

18

922

4

25

14

23

1120

15

61

13

1219

1021

U7201

0.22UF

10% 10V CERM 402

2

1

C7201

PATH=I621

1/16W

1%

402

MF-LF

6.49K

2

1

R7260

1/16W

1%

402

MF-LF

10K

2

1

R7261

1/16W

5%

402

MF-LF

15K

PATH=I623

2

1

R7220

1/16W

1%

402

MF-LF

10K

2

1

R7221

SOT563

SSM6N15FEAPE

4

5

3

Q7211

SSM6N15FEAPE

SOT563

1

2

6

Q7210

SOT563

SSM6N15FEAPE

4

5

3

Q7210

1/16W

5%

402

MF-LF

10K

2

1

R7210

1/16W

5%

402

MF-LF

10

NO STUFF

2

1

R7222

CERM

402

50V

5%

NO STUFF

100PF

2

1

C7222

1/16W

5%

402

MF-LF

10

NO STUFF

2

1

R7262

50V

5%

402

CERM

100PF

NO STUFF

2

1

C7262

1/16W

5%

402

MF-LF

0

2 1

R7264

1/16W MF-LF

5%

0

402

2 1

R7224

0.001UF

CERM

50V

10%

402

2

1

C7243

0.001UF

CERM

50V 402

10%

2

1

C7282

10% CERM

50V 402

0.001UF

2

1

C7251

0.001UF

50V

10%

402

CERM

2

1

C7291

402

100K

5% 1/16W MF-LF

2

1

R7273

CRITICAL

4.7UH-13A-15MOHM

PCMB104E4R7-SM

21

L7220

MF-LF

1% 1/16W

402

86.6K

2

1

R7200

PWRFLAT-SM

STL11NH3LL

CRITICAL

3 2 1

4

5

Q7220

PWRFLAT-SM

CRITICAL

STL15N3LLH5

3 2 1

4

5

Q7225

SYNC_DATE=12/17/2008

051-7892

A.0.0

9764

SYNC_MASTER=PWRSQNC

5V / 3.3V Power Supply

Cyntec alternate to MagLayers

ALL

152S0693152S0778

DIDT=TRUE

P5VS5_LL

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_VFB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

GND_P5VP3V3_SGND

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

P5VS5_DRVL

DIDT=TRUE

PPBUS_G3H

P5VS5_DRVH

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

PP5V_S3

P5VS3_EN_L

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P3V3S5_LL

SWITCH_NODE=TRUE

P5VP3V3_VREF

P5VP3V3_VREG3

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P3V3S5_VBST

P5VS5_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

P3V3S5_DRVL

P5VP3V3_VREG5

P3V3S5_ENTRIP

P3V3_S5_REG_XW

P5V_S5_REG_XW

P5VS3_EN

P3V3S5_EN_L

PP3V42_G3H

P5VS5_RC

P3V3S5_RC

P5VS5_VBST_R

P3V3S5_VBST_R

5V3V3_REG_EN

SMC_PM_G2_EN

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_DRVH

GATE_NODE=TRUE

PP3V3_S5

P3V3S5_VFB

P5VS5_ENTRIP

S0_PWR_PGOOD

7 8

37 46 61 62 65 66 67 79

83 86

7 8 9

31 39 40 41 43 51 53 55

65 70 79

69

7 8

21 22 26 40 42 43 44 45

46 50 61 62 69

7

42 69

7 8

18 20

22 24 26

30 34 37

38 44 54

68 69 70

82 87 96

MODE

VDDQSNS

COMP

NC0 NC1

VTTSNS

VTT

VTTREF

PGOOD

S3 S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN IN OUT

NC NC

S

D

G

OUT

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 1.5V

VTT Enable

<Rb>

VDDQ/VTTREF Enable VDDQ PGOOD

(DDRREG_FB)

<Ra>

f = 400 kHz

(Q7335 limit)

15A max output

Vout = VDDQSNS/2

10mA max load

(DDRREG_VBST)

(DDRREG_DRVL)

(DDRREG_CSGND)

(DDRREG_VDDQSNS)

(DDRREG_DRVH)

Vout = VTTREF

Vout = 0.75V * (1 + Ra / Rb)

(DDRREG_LL)

0.1UF

X7R

603-1

10% 50V

21

C7325

1/16W

15.0K

MF-LF 402

1%

2

1

R7320

15.0K

MF-LF 402

1% 1/16W

2

1

R7321

1UF

X5R 603-1

10% 25V

2

1

C7332

100PF

CERM

NO STUFF

402

5%

50V

2

1

C7320

CRITICAL

TPS51116

QFN

2

5

1

24

23

8

9

22

15

14

25

11

10

13

18

12

7

4

20

3

19

21

17

16

6

U7300

402-1

10V

10% X5R

1UF

2

1

C7305

4.7

MF-LF

402

5%

1/16W

21

R7305

CRITICAL

22UF

X5R-CERM 603

20%

6.3V

2

1

C7361

22UF

X5R-CERM

603

20%

6.3V

CRITICAL

2

1

C7360

SM

21

XW7360

SM

PLACEMENT_NOTE=Place next to Q7335

21

XW7335

0.033UF

X5R 402

10% 16V

2

1

C7350

9

26 70

603

4.7UF

CERM

20%

6.3V 2

1

C7300

69

10K

MF-LF

402

1%

1/16W

2

1

R7310

69

CRITICAL

22UF

POLY-TANT

CASE-D2-SM

20% 25V

2

1

C7330

22UF

CASE-D2-SM

POLY-TANT

20% 25V

CRITICAL

2

1

C7331

1.0UH-13A-5.6MOHM

CRITICAL

PCMB065T-SM

21

L7330

PLACEMENT_NOTE=Place next to C7345

SM

2

1

XW7345

10UF

X5R 603

20%

6.3V

2

1

C7355

SM

2

1

XW7300

CASE-B4-SM

270UF

CRITICAL

TANT

2V

20%

2

1

C7341

CASE-B4-SM

CRITICAL

20%

270UF

TANT

2V

2

1

C7340

10UF

X5R 603

20%

6.3V

2

1

C7345

0.001UF

X7R 402

10% 50V

2

1

C7333

0.001UF

X7R 402

10% 50V

2

1

C7346

CRITICAL

PWRPK-1212-8-HF

SI7110DN

321

4

5

Q7330

53 96

CRITICAL

SI7108DN

PWRPK-1212-8-HF

321

4

5

Q7335

SM

2

1

XW7331

SM

2

1

XW7332

SM

21

XW7330

SYNC_MASTER=DDR

A.0.0

9765

051-7892

SYNC_DATE=12/05/2008

1.5V DDR3 Supply

MEM_VTT_EN

MIN_LINE_WIDTH=0.6 mm

PP5V_S3_DDRREG_V5FILT

MIN_NECK_WIDTH=0.17 mm VOLTAGE=5V

PP5V_S3

DDRREG_DRVL

MIN_NECK_WIDTH=0.17 mm

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_VDDQSNS

DDRREG_FB

TP_DDRREG_PGOOD

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DDRREG_LL

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

GND_DDRREG_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

PPBUS_G3H

PPVTTDDR_S3

DDRREG_CS

DDRREG_EN

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_CSGND

DDRREG_VTTSNS

PP1V8R1V5_S3

PP0V9R0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm

MIN_NECK_WIDTH=0.17 mm

ISNS_1V5_S3_N

PP1V8R1V5_S3

ISNS_1V5_S3_P

PPDDR_S3_REG_R

MIN_LINE_WIDTH=0.8 MM

MIN_NECK_WIDTH=0.1 MM

VOLTAGE=1.5V

7 8 9

31 39 40 41 43 51 53 55

64 70 79

7 8

37 46

61 62 64 66

67 79 83 86

8

27

7 8

28 29 30 65 70

7 8

28 29 70

7 8

28 29 30 65 70

IN

OUT

OCSET

ICOMP

RBIAS

LGATE

THRM_PAD

FDE

IMON

PVCC

PHASE

UGATE

BOOT

VDD

VSS

VIN

VO

VSEN

VDIFF

FB

COMP

VW

SOFT

PGND

ISN

ISP

RTN

PGOOD

AF_EN

VR_ON

OFFSET1

OFFSET0

VID2

VID1

VID0

D

S

G

D

S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(MCPCORES0_VO)

(MCPCORES0_VW)

(MCPCORES0_RTN)

CONNECT SENSE LINES TO CLOSEST

(MCPCORES0_ISN)

(Q7560 Limit)

MAX CURRENT: 15.5A

101 0.80V 110 0.75V

(MCPCORES0_UGATE)

MCPCORE AND GND BALL OF MCP

PLACE XW NEAR THE MCP,

f = 300 kHz

(MCPCORES0_VDIFF)

(MCPCORES0_FB)

(MCPCORES0_COMP)

(MCPCORES0_VSEN)

(MCPCORES0_ICOMP)

VID<2:0> VOLTAGE

001 1.00V 010 0.95V 011 0.90V 100 0.85V

111 0.70V

(MCPCORES0_PHASE)

000 1.05V

(MCPCORES0_LGATE)

CRITICAL

1.0UH-17A-5M-OHM

HAHF651R0AP-SM

21

L7560

SM

OMIT

21

XW7563

OMIT

SM

21

XW7562

21

20

1/16W MF-LF

1%

402

21

R7568

20

1/16W MF-LF

402

1%

21

R7566

402

X7R

10% 50V

0.001UF

2

1

C7570

1/16W MF-LF

1%

402

100

2

1

R7563

1/16W

1%

402

MF-LF

20.0K

2

1

R7582

1/16W

1%

402

MF-LF

20.0K

2

1

R7583

5%

1/16W

402

MF-LF

0

21

R7592

1/16W MF-LF

NOSTUFF

402

20.0K

1%

2

1

R7580

1%

402

NOSTUFF

1/16W MF-LF

20.0K

2

1

R7581

402

0

1/16W

5%

MF-LF

21

R7591

16V

10%

402

X7R-CERM

0.1UF

2

1

C7576

150K

1%

402

MF-LF

1/16W

2

1

R7572

69

64 67

68

69

0

5%

402

MF-LF

1/16W

21

R7590

1K

1/16W

5%

402

MF-LF

2

1

R7561

QFN

ISL6263D

4

15

8

29

12

14

27

26

25

7

16

18

33

2

9

1

22

1931

20

24

23

3

21

13 11

28

10

32

6

5

17

30

U7500

SM

21

XW7561

MF-LF 402

1% 1/16W

47.0K

2

1

R7575

10K

MF-LF 402

1% 1/16W

2

1

R7573

1%

11.3K

1/16W MF-LF

402

21

R7569

0

MF-LF

603

1/10W

5%

21

R7565

CRITICAL

MICROFET3X3

FDMC8678S

321

4

5

Q7565

CERM-X7R

10V

5%

603

0.22UF

21

C7564

POWER33-SM

CRITICAL

FDMC8676

321

4

5

Q7560

402

10% 16V

1UF

X5R

2

1

C7550

MF-LF

2.2

1/10W

5%

603

21

R7560

1UF

402

X5R

16V

10%

2

1

C7562

MF-LF

1/16W

1%

402

100

21

R7578

1/16W

1%

402

MF-LF

2.21K

21

R7579

1/16W

1%

402

MF-LF

133K

21

R7577

50V

5%

402-1

CERM

68PF

21

C7580

50V

10%

402

CERM

560PF

21

C7581

1%

100

1/16W 402

MF-LF

2

1

R7571

50V

10%

402

CERM

560PF

21

C7582

10% 50V

402

X7R

0.001UF

2

1

C7579

402

1/16W

1% MF-LF

6.98K

2

1

R7576

5%

1

603

NO STUFF

MF-LF

1/10W

2

1

R7589

50V

10%

0.001UF

NO STUFF

X7R 402

2

1

C7589

20% 603

4V

X5R

10UF

2

1

C7566

CASE-B4-SM

20%

CRITICAL

2V TANT

270UF

2

1

C7568

50V 402

X7R

0.001UF

10%

2

1

C7569

CASE-B4-SM

20%

CRITICAL

2V TANT

270UF

2

1

C7565

10UF

4V

20% X5R

603

2

1

C7567

25V

10%

603-1

X5R

1UF

2

1

C7561

CASE-D2E-SM

16V

POLY-TANT

68UF

20%

CRITICAL

2

1

C7560

50V

10%

402

X7R

0.001UF

2

1

C7563

402

MF-LF

1/16W

100

1%

21

R7500

47PF

CERM

5%

50V 402

2

1

C7573

402

CERM

5% 50V

47PF

2

1

C7575

0

MF-LF

402

1/16W

5%

21

R7593

CASE-D2E-SM

16V

POLY-TANT

68UF

20%

CRITICAL

2

1

C7540

CRITICAL

0.001

MF-1

1% 1W

0612

4 3

2 1

R7525

MCP CORE REGULATOR

SYNC_DATE=11/14/2008

66 97

A.0.0

051-7892

SYNC_MASTER=M98_MLB

PPBUS_G3H

MCP_VID0_R

MCP_VID2_R

MCPCORES0_FDE

MCPCORES0_SOFT

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MCPCORES0_UGATE

5V_S0_MCPREG_VIN

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

MCPCORES0_IMON_R

0.25 MM

0.2 MM

MCPCORES0_BOOT

MCP_VID<2>

MCP_VID<1>

MCP_VID<0>

MCPCORES0_RSEN_P

MCPCORES0_EN

S0_PWR_PGOOD

MCPCORES0_RSEN_N

PPVCORE_S0_MCP_REG

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

0.25 MM

0.2 MM

MCPCORES0_BOOT_R

MCPCORES0_IMON

PP5V_S0

MCPCORES0_RBIAS

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V

PPMCPCORE_S0_R

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_LGATE

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

SWITCHNODE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE DIDT=TRUE

MCPCORES0_PHASE

MCPCORE_SNUBBER

MCPCORES0_ISN

MCPCORES0_VSEN

MCPCORES0_FB

GND_MCPCORES0_AGND

VOLTAGE=0V MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm

MCPCORES0_COMP

MCPCORES0_VDIFF

MCP_VID1_R

MCPCORES0_OS0 MCPCORES0_OS1

MCPCORES0_VW

MCPCORES0_RTN

MCPCORES0_ICOMP

MCPCORES0_VO

MCPCORES0_OCSET

MCPCORES0_ISP_R

MCPCORES0_ISP

PPVCORE_S0_MCP_REG

7 8

37 46 61 62 64 65 67 79

83 86

7 8

22 24 46 66

7 8

22 24 46 66

47

7 8

39 44 49 51

63 67 70 83 85

7 8

22 24 46 66

Q1

Q2

SW

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

8A max output (Q7660 limit?)

<Ra>

(=PPCPUVTT_S0_REG)

(GND)

(CPUVTTS0_VFB)

M99 differences from last sync on 12/03/07 to T18 MLB:

1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.

Vout = 1.052V

<Rb>

f = 360 kHz

Vout = 0.75V * (1 + Ra / Rb)

6.3V

20%

603

X5R

10UF

2

1

C7665

25V

10% 603-1

X5R

1UF

2

1

C7695

1% 1/16W MF-LF

8.06K

402

2

1

R7670

1/16W

1%

402

MF-LF

20.0K

2

1

R7671

NO STUFF

5%

100PF

50V

CERM

402

2

1

C7670

CRITICAL

330UF

2.0V

20%

B2-SM

POLY-TANT

2

1

C7660

CRITICAL

2.2UH-8.0A

PCMB065T-SM

21

L7660

10%

0.1UF

50V

603-1

X7R

2

1

C7680

25V

POLY-TANT

22UF

CASE-D2-SM

20%

CRITICAL

2

1

C7690

MLP

FDMS9600S

CRITICAL

10

7

6 5

8

1

9 4 3 2

Q7660

SM

PLACEMENT_NOTE=Place XW7665 next to L7660

2

1

XW7665

1/16W

1%

402

MF-LF

200

21

R7601

SM

21

XW7600

8.87K

1% 1/16W MF-LF 402

2

1

R7685

64 66 68 69

69

QFN

CRITICAL

TPS51117RGY_QFN14

3

5

14

4

10

11

2

1568

12

7

1

9

13

U7600

16V

10%

603

X5R

2.2UF

2

1

C7601

1UF

10V X5R 402-1

10%

2

1

C7600

1/16W MF-LF

402

1%

226K

2

1

R7679

MF

1W

1%

0612

0.002

43

21

R7660

67 97

051-7892

SYNC_DATE=12/14/2007

A.0.0

SYNC_MASTER=M99_MLB

CPU VTT / 1V05 S0 Power Supply

CPUVTT_ISNS_P

CPUVTT_ISNS_N

CPUVTTS0_TON

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PPCPUFSB_ISNS

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_LL

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

PP5V_S0_CPUVTTS0_V5FILT

PP5V_S0

PPCPUVTT_S0

CPUVTTS0_VSNS

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_DRVL

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

S0_PWR_PGOOD

CPUVTTS0_DRVH

MIN_NECK_WIDTH=0.2MM

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_EN

PPBUS_G3H

CPUVTTS0_VBST

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_CPUVTTS0_SGND

CPUVTTS0_TRIP

CPUVTTS0_VFB

47 96

7 8

39 44 49 51 63 66 70 83

85

6 7 8 9

10 11 12 13 14 17 18 20

22 24 25 63

7 8

37 46 61 62 64 65 66 79

83 86

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

SS

IN0 IN1

THRML_PAD

EN FB

BIAS

OUT0 OUT1

GND

PG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

<Ra>

VOUT = 0.8V * (1 + RA / RB)

MCP 1.05V S5 (AUXC) SUPPLY

<Ra>

<Rb>

Vout = 1.053V

FREQ = 1.6MHZ

Vout = 1.05V

VOUT = 0.8V * (1 + RA / RB)

MAX CURRENT = 0.5A

MAX CURRENT = 0.8A

1.05V S0 PLL LDO

<Rb>

69

100

5% 1/16W MF-LF

402

21

R7743

CERM

1UF

10%

6.3V 402

2

1

C7741

6.3V

10%

1UF

402

CERM

2

1

C7740

CRITICAL

6.3V

20%

805

CERM

22UF

2

1

C7750

50V

5%

402

CERM

47PF

2

1

C7776

IHLP1616BZ-SM

2.2UH-3.25A

1V05S5_SW

CRITICAL

21

L7770

MF-LF 402

806K

1% 1/16W

2

1

R7781

255K

MF-LF 402

1% 1/16W

2

1

R7780

CERM

6.3V

20% 805

22UF

CRITICAL

2

1

C7771

CRITICAL

DFN

ISL8009B

1

6

9

4 5

3

8

7

2

U7750

SON

CRITICAL

TPS74701

11

7 3

10

9

2

1

6

85

4

U7740

50V

10%

CERM

0.0022UF

NOSTUFF

402

2

1

C7743

MF-LF

1/16W

1%

1.37K

402

2

1

R7744

MF-LF

1/16W

1%

402

4.42K

2

1

R7745

402

4V

20% X5R

4.7UF

2

1

C7742

MF-LF

402

1/16W

5%

0

21

R7746

68 97

A.0.0

051-7892

SYNC_DATE=12/14/2007

SYNC_MASTER=M99_MLB

Misc Power Supplies

PP1V8R1V5_S0_FET

PP1V05_S0_MCP_PLL_UF

P1V05S0_PGOOD

S0_PWR_PGOOD

PP3V3_S0

P1V05S0_LDO_SS

PP3V3_S0_MCP_PLL_VLDO_BIAS

P1V05S0_LDO_FB

DIDT=TRUE

PM_G2_P1V05S5_EN

PP1V2R1V05_S5

PP3V3_S5

1V05S5_FB

P1V05_S5_PGOOD

7 8

11 12 16 24 28 29 39 69

70

7 8

24

64 66 67 69

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 69 70 77 80 81 82 84

85 96

7 8

22 24 34

7 8

18 20 22 24 26 30 34 37

38 44 54 64 69 70 82 87 96

69

OUT

IN

OUT

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

OUT

IN

D

G S

IN

OUT

IN

OUT

SENSE

CT

VDD

GND

RESET*

MR*

OUT

Y

B

A

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.3V 1,05V S5 ENABLE

APN: 353S2310

V4MON THRESHOLD IS 0.6V

NC

V3MON THRESHOLD IS 0.6V

V2MON THRESHOLD IS 2.866V

1) 1.1V

GPUVCORE ENABLE

3) GPUVcore

S5 rail PWRGD

up in the following order:

(PM_S4_STATE_L)

TPS3808 MR* HAS INTERNAL PULLUP

3.3V,5V S3 ENABLE

0

PM_SLP_S3_L

1

0

00

PM_SLP_S4_L

1

0

1

0

1

Battery Off (G3Hot)

Soft-Off (S5)

State

Run (S0)

PM_ALL_GFX_PGOOD

EG PM_ALL_GPU_PGOOD

IG high

Other S0 RAILS

1.1V GPU ENABLE

Sleep (S3)

SMC_PM_G2_ENABLE

G96 GPU requires rails to come

(PM_SLP_S3_L)

Unused PGOOD signal

EXT GPU PWRGD Pullup

BOMOPTION: EG

4) GDDR3 1.8V

2) GPU_3.3V

S0 ENABLE

Graphic MEM ENABLE

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

place XW0402 if needed to save trace space for pin 7,8

69 83 84

16V

20%

402

CERM

0.022UF

NO STUFF

PLACEMENT_NOTE=near U9500

2

1

C7850

PLACEMENT_NOTE=near U9500

EG_PWRSEQ_HW

0

MF-LF

402

5%

1/16W

2 1

R7852

EG_PWRSEQ_HW

10K

1/16W

5%

402

MF-LF

21

R7851

1/16W

5%

402

MF-LF

100K

EG_PWRSEQ_HW

21

R7850

84

1/16W

5%

402

MF-LF

100K

2

1

R7853

1/16W

5%

402

MF-LF

10K

2

1

R7892

69 79 84

PLACEMENT_NOTE=near U8900

CERM

16V

10% 402

0.01UF

2

1

C7861

1/16W

402

MF-LF

0

PLACEMENT_NOTE=near U8900

5%

EG_PWRSEQ_HW

21

R7864

1/16W

5%

402

MF-LF

EG_PWRSEQ_HW

100K

21

R7863

7

21 40 42 43 69 70

65 69

1/16W

5%

402

MF-LF

100K

PLACEMENT_NOTE=near U1400

2

1

R7810

7

21 40 42 43 69 70

69 70 83 84

1/16W

5%

402

MF-LF

0

PLACEMENT_NOTE=near U7880

NO STUFF

21

R7891

64 66 67 68 69

SOT563

SSM6N15FEAPE

EG_PWRSEQ_HW

1

2

6

Q7850

SSM6N15FEAPE

EG_PWRSEQ_HW

SOT563

4

5

3

Q7850

SOT563

SSM6N15FEAPE

EG_PWRSEQ_HW

1

2

6

Q7861

SOT563

SSM6N15FEAPE

EG_PWRSEQ_HW

4

5

3

Q7861

64

68 69

64 66 67 68 69

CERM-X5R

6.3V

10%

402

0.47UF

PLACEMENT_NOTE=near U7750

2

1

C7801

402

1/16W

5%

MF-LF

100K

2 1

R7802

0.068UF

10V

10%

402

CERM

NO STUFF

PLACEMENT_NOTE=near U7201

2

1

C7802

1/16W

5%

402

5.1K

PLACEMENT_NOTE=near U7750

MF-LF

2 1

R7801

SOD-VESM-HF

SSM3K15FV

2

1

3

Q7800

1/16W

5%

402

MF-LF

100K

PLACEMENT_NOTE=near U4900

2

1

R7858

7

42 64

46 69 70

69 70

67 69

69 87

66 69

64 66 67 68 69

MF-LF 402

PLACEMENT_NOTE=nearU7700

5%

1/16W

10K

2

1

R7883

PLACEMENT_NOTE=nearQ7971

1/16W 402

MF-LF

0

5%

2

1

R7882

402

PLACEMENT_NOTE=nearU7600

1/16W

5%

MF-LF

33K

2

1

R7881

5%

402

MF-LF

100K

1/16W

2

1

R7890

1/16W

5%

402

MF-LF

PLACEMENT_NOTE=near U1400

100K

2

1

R7879

7

21 34 37 42 82 84

PLACEMENT_NOTE=nearU7700

0.47UF

10% 402

6.3V CERM-X5R

2

1

C7883

10%

6.3V 402

0.47UF

CERM-X5R

NO STUFF

PLACEMENT_NOTE=nearQ7971

2

1

C7882

6.3V

10% 402

CERM-X5R

0.47UF

PLACEMENT_NOTE=nearQ7600

2

1

C7881

6.3V

10% 402

PLACEMENT_NOTE=nearU7500

CERM-X5R

0.47UF

2

1

C7880

64 69

1/16W

5%

402

MF-LF

5.1K

PLACEMENT_NOTE=near U7300

2

1

R7811

6.3V

10%

402

CERM-X5R

0.47UF

PLACEMENT_NOTE=near U7300

2

1

C7810

1/16W

5%

402

MF-LF

0

PLACEMENT_NOTE=near U7201

2

1

R7812

6.3V

10% 402

CERM-X5R

0.47UF

NO STUFF

PLACEMENT_NOTE=near U7201

2

1

C7812

0

402

1/16W

5%

MF-LF

PLACEMENT_NOTE=near U7880

2

1

R7894

100K

1/16W

5%

402

MF-LF

2

1

R7840

10V

20%

402

CERM

0.1uF

2

1

C7840

TPS3808G33DBVRG4

SOT23-6

6

5 1

3

2

4

U7840

0.001UF

50V

20% 402

CERM

2

1

C7841

1/16W

5%

402

MF-LF

100K

EG_PWRSEQ_HW

PLACEMENT_NOTE=near U7972

2

1

R7889

9

69 83 84

70 84

1/16W

5%

402

MF-LF

0

EG_PWRSEQ_HW

2

1

R7888

1/16W

5%

402

MF-LF

100

21

R7878

SOT665

TC7SZ08AFEAPE

4

5

3

1

2

U7880

10V

20% 402

CERM

0.1uF

2

1

C7870

TDFN

ISL88042IRTEZ

7

2

6

5

3

9

8

1

4

U7870

0.47UF

CERM-X5R 402

10%

6.3V

NO STUFF

2

1

C7884

69 70

0

MF-LF

1/16W

5%

402

2

1

R7884

PLACEMENT_NOTE=nearU7500

22K

MF-LF

402

5%

1/16W

2

1

R7880

64 66 67 68 69

26 42

16V

20%

402

CERM

0.022UF

NO STUFF

PLACEMENT_NOTE=near U9500

2

1

C7869

10V

20% 402

CERM

0.1UF

2

1

C7889

PLACEMENT_NOTE=near U9500

1/16W

5%

402

MF-LF

0

EG_PWRSEQ_HW

21

R7869

EG_PWRSEQ_HW

1/16W

5%

402

MF-LF

100K

21

R7868

Power Control

SYNC_MASTER=PWRSQNC

SYNC_DATE=12/17/2008

9769

A.0.0

051-7892

S0_PWR_PGOOD

PM_SLP_S3_L_R

MAKE_BASE=TRUE

P1V8_S0GPU_EN

S0_PWR_PGOOD

MAKE_BASE=TRUE

PP3V3_S5

S0_PWR_PGOOD

PM_SLP_S3_L_R

P1V2R1V8S0_EN

MAKE_BASE=TRUE

P3V3S0_EN

GPUVCORE_EN

PP1V8_S0

P3V3S5_EN_L

CPUVTTS0_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

MCPDDR_EN

MAKE_BASE=TRUE

P3V3S0_EN P1V2R1V8S0_EN

PM_SLP_S3_L_R

P1V05_S5_PGOOD

PM_G2_P1V05S5_EN

MAKE_BASE=TRUE

GPU_S0_EN_L

MCPCORES0_EN

P1V8_S0GPU_EN_RC

GPUVCORE_PGOOD

PP1V8R1V5_S0_FET

PP3V3_S0

CPUVTTS0_EN

MCPDDR_EN

PM_ALL_GPU_PGOOD

GPU_S0_EN_L

MAKE_BASE=TRUE

PM_ALL_GPU_PGOODPM_ALL_GPU_PGOOD

PP3V3_S0

P3V3GPU_EN

P1V1GPU_PGOOD

PP3V3_S5

EXTGPU_PWR_EN

ALL_GFX_PGOOD_R

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

P5VS3_EN

ALL_SYS_PWRGD

PP3V3_S5

PP3V3_S0

MAKE_BASE=TRUE

PM_G2_P1V05S5_EN

GPUVCORE_EN_RC

PP3V42_G3H

PP3V3_S0GPU

CT

RSMRST_PWRGD

PM_SLP_S4_L

DDRREG_EN

P5VS3_EN

GPU_S0_EN_L

MAKE_BASE=TRUE

PM_SLP_S4_L

P1V8_S0GPU_EN

P1V1_GPU_EN

PM_SLP_S3_L

P1V1_GPU_EN_RC

PP3V42_G3H

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

PP3V3_S0GPU

MAKE_BASE=TRUE

GPUVCORE_EN

PP3V3_S0

S0_PWR_PGOOD

MAKE_BASE=TRUE

P1V1_GPU_EN

MCPCORES0_EN

MAKE_BASE=TRUE

46 69 70

64

66

67

68

69

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 87 96

69 87

69 70

7 8

18 25 55 70 84 87

67 69

69 70

68

69

79

7 8

11 12 16 24 28 29 39 68

70

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

9

69 83 84

69

9

69 83 84

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

83

7 8

18 20 22 24 26

30 34 37 38

44 54 64 68 69 70

82 87 96

65 69

64 69

7 8

18 20 22 24 26 30 34 37 38

44 54 64 68 69 70 82 87 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

68 69

7 8

21 22 26 40 42 43 44 45

46 50 61 62 64 69

6 8

69 70

76 77 79 81

42

69

7 8

21 22 26

40 42 43 44

45 46 50 61

62 64 69

65 69 65 69

6 8

69 70 76 77 79 81

69 79

84

6 7 8

13 18

19 21 22 24

25 28 29 37

39 43 45 47

48 49 51 55

59 60 63 68

69 70 77 80 81 82

84 85 96

64 66 67 68 69

69 83 84

66 69

IN

D

SG

D

SG

IN

D

SG

D

SG

IN

D

SG

D

SG

D

G S

SGD

IN

D

SG

D

SG

D

S

G

D

S

KELVIN

NC

GND

SENSE

G

OUT

IN

D

G S

S

G

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LOADING

5.0V S0 FET

3.3V S3 FET

1.8V GPU FET

RDS(ON)

FDC606P

P-TYPECHANNEL

MOSFET

0.087 A (EDP)

5.0V S0 FET

26 MOHM @4.5V

1.7 A (EDP)

MCP79 DDR FETs

will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp

P-TYPE

48 mOhm @4.5V

3.3V GPU FET

BOM_OPTION

RDS(ON)

CHANNEL

MOSFET

LOADING

3.3V GPU FET

EG

FDC606P

P-TYPE

1.1 A (EDP)

26 mOhm @4.5V

LOADING

RDS(ON)

CHANNEL

Rome SenseFET

6.3 mOhm @4.5V

N-TYPE

1.5V S0 FET

3.3V S3 FET

on VTT rail, which pulls all CKE signals low through VTT termination resistors.

81mW max power

90mA max load @ 0.9V

LOADING

RDS(ON)

P-TYPE

3.3V S0 FET

RDS(ON)

CHANNEL

LOADING

MOSFET

FDC638PMOSFET

3.3V S0 FET

2.9 A (EDP)

26 mOhm @4.5V

FDC606P

1.8V Vgs

MOSFET

5.4 A (EDP)

1.5V S0 FET

In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low before rail is turned off, and remains low until after rail turns back on or DIMMs

MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep.

CHANNEL

9

26 65

SSM6N15FEAPE

SOT563

4

5

3

Q7975

100K

MF-LF

402

5%

1/16W

2

1

R7976

NO STUFF

0.001UF

CERM

402

20% 50V

2

1

C7976

SSM6N15FEAPE

SOT563

1

2

6

Q7975

10

MF-LF

402

5%

1/16W

2

1

R7975

10V X5R

402-1

1UF

10%

2

1

C7971

16V

10%

402

CERM

0.01UF

21

C7970

1/16W MF-LF

1K

5%

402

21

R7970

5%

MF-LF

51K

402

1/16W

2

1

R7972

69 84

0.1UF

CERM

402

20% 10V

2

1

C7902

0.068UF

CERM 402

10% 10V

2

1

C7903

SSM6N15FEAPE

SOT563

1

2

6

Q7971

47K

MF-LF

402

5%

1/16W

21

R7971

10K

MF-LF

402

5%

1/16W

21

R7901

100K

MF-LF

402

5%

1/16W

2

1

R7903

SOT563

SSM6N15FEAPE

4

5

3

Q7971

69

0.01UF

CERM

402

10% 16V

21

C7910

0.033UF

X5R 402

10% 16V

2

1

C7911

47K

MF-LF

402

5%

1/16W

21

R7910

10K

MF-LF

5%

1/16W

402

2

1

R7912

0.01UF

CERM

402

10% 16V

21

C7930

0.033UF

X5R 402

10% 16V

2

1

C7931

47K

MF-LF

402

5%

1/16W

21

R7930

100K

402

5% 1/16W MF-LF

2

1

R7932

7

21 40 42 43 69

69

SSM6N15FEAPE

SOT563

1

2

6

Q7912

SSM6N15FEAPE

SOT563

4

5

3

Q7912

SM

FDC638P_G

CRITICAL

4

3

6 5 2 1

Q7910

SOD-VESM-HF

SSM3K15FV

2

1

3

Q7972

CRITICAL

FDC606P_G

SOT-6

4

3

6521

Q7930

SOT-6

FDC606P_G

CRITICAL

4

3

6521

Q7970

69 83 84

SOT563

SSM6N15FEAPE

4

5

3

Q7941

69.8K

402

1% 1/16W MF-LF

2

1

R7942

10K

MF-LF

402

1%

1/16W

21

R7941

100K

MF-LF

402

5%

1/16W

21

R7940

SSM6N15FEAPE

SOT563

1

2

6

Q7941

CERM

402

20% 10V

0.1UF

2

1

C7940

CRITICAL

SI2312BDS

SOT23

2

1

3

Q7940

0.01UF

CERM 402

10% 16V

2

1

C7941

CRITICAL

ROME

DFN

7 321

8

6

5

4

9

Q7901

47

46 69

SOD-VESM-HF

SSM3K15FV

2

1

3

Q7955

47K

1/16W MF-LF

402

5%

2

1

R7952

5%

1/16W

402

47K

MF-LF

21

R7950

X5R

16V

10%

402

0.033UF

2

1

C7951

16V

CERM

402

10%

0.01UF

21

C7950

CRITICAL

TPCP8102

23V1K-SM

321

4

8765

Q7950

SYNC_MASTER=DDR

SYNC_DATE=12/05/2008

Power FETs

A.0.0

70

051-7892

97

P3V3GPU_EN_L

PM_SLP_S4_L

P3V3GPU_SS

PP1V8R1V5_S0_FET

PP1V8R1V5_S3

MCPDDR_EN

PP5V_S3

MCPDDR_EN_L_RC

P1V8_S0GPU_EN

P3V3S0_EN

VTTCLAMP_L

PP3V3_S5

P3V3S0_SS

PP5V_S3

VTTCLAMP_EN

MEM_VTT_EN

PP0V9R0V75_S0_DDRVTT

PP3V3_S0

P3V3S3_SS

P1V8GPU_SS

P1V8GPU_EN_L

P1V8GPU_EN_L_RC

MCPDDR_SS

P1V5_S0_SENSE

P1V5_S0_KELVIN

PP5V_S3

P3V3GPU_EN

PP3V3_S0GPU

PM_SLP_S3_L_R

P3V3S0_EN_L

P5V0S0_EN_L

P3V3S3_EN_L

PP1V8_S0

PP1V8_GPUIFPX

PP3V3_S3

MCPDDR_EN_L

PP3V3_S5

P5V0S0_SS

PP5V_S0

PP5V_S3

7 8

11 12 16 24 28 29 39 68 69

7 8

28 29 30 65

7 8 9

31 39 40 41

43 51 53 55 64 65 70 79

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 87 96

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

7 8

28 29 65

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 77 80 81 82 84

85 96

7 8 9

31 39 40 41 43

51 53 55 64 65 70 79

6 8

69 76 77 79 81

7 8

18 25 55 69 84 87

8

78

7 8

21 27 31 32 45 50 52

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 87

96

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 87 96

7 8

39 44 49 51 63 66 67 83 85

7 8 9

31 39 40 41 43 51 53 55

64 65 70 79

OUT

GND_SENSE

VDD_SENSE

PEX_IOVDDQ23

PEX_IOVDDQ25

PEX_IOVDD5

PEX_IOVDDQ1 PEX_IOVDDQ2

PEX_PLLVDD

PEX_IOVDDQ22

PEX_IOVDDQ6

PEX_IOVDD2 PEX_IOVDD3 PEX_IOVDD4

PEX_IOVDDQ9

PEX_IOVDDQ15 PEX_IOVDDQ16 PEX_IOVDDQ17

PEX_IOVDDQ19 PEX_IOVDDQ20 PEX_IOVDDQ21

PEX_IOVDD1

PEX_IOVDDQ14

PEX_IOVDDQ13

PEX_IOVDDQ12

PEX_IOVDDQ8

PEX_IOVDDQ7

PEX_IOVDDQ5

PEX_IOVDDQ4

PEX_IOVDDQ11

PEX_IOVDDQ24

PEX_IOVDDQ18

PEX_IOVDDQ3

PEX_IOVDDQ10

NC

SYMBOL 2 OF 9

PEX_RFU2

PEX_TX2

PEX_TX3

PEX_TX3*

PEX_TX4

PEX_TX4*

PEX_TX5*

PEX_TX6*

PEX_RFU1

PEX_RX5

PEX_RX3*

PEX_RX4

PEX_RX0

PEX_RX1

PEX_RX0*

PEX_RX9 PEX_RX9*

PEX_RX4*

PEX_RX5*

PEX_RX10

PEX_TX13*

PEX_TX1

PEX_TX7

PEX_TX10

PEX_TX10*

PEX_TX11

PEX_TX11*

PEX_TX12

PEX_TX12*

PEX_TX13

PEX_TX14

PEX_TX14*

PEX_TX15*

PEX_TX9*

PEX_TX8*

PEX_TX2*

PEX_TX1*

PEX_TX0*

PEX_RX15*

PEX_RX12*

PEX_RX11*

PEX_RX10*

PEX_RX8*

PEX_RX7*

PEX_RX6*

PEX_RX2*

PEX_TX0

PEX_TX9

PEX_TX5

PEX_TX6

PEX_TX8

PEX_TX15

PEX_RX3

PEX_RX6

PEX_RX7

PEX_RX8

PEX_RX11

PEX_RX12

PEX_RX2

PEX_RX1*

PEX_RX15

PEX_RX14*

PEX_RX14

PEX_RX13 PEX_RX13*

PEX_TSTCLK_OUT*

PEX_TSTCLK_OUT

PEX_TERMP

PEX_CLKREQ*

PEX_RST*

PEX_REFCLK*

PEX_REFCLK

PEX_TX7*

SYMBOL 1 OF 9

NC NC

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

1500mA

(NONE)

- =PP1V2_GPU_PEX_IOVDD

(NONE)

180mA

250mA

- =PP1V2_GPU_PEX_IOVDDQ

PEX 1.1V Current = 2A

Signal aliases required by this page:

BOM options provided by this page:

- =PP1V2_GPU_PEX_PLLXVDD

9

90

40216VX5R10%

0.1uF

21

C8081

40216VX5R10%

0.1uF

21

C8082

9

90

9

90

40216VX5R10%

0.1uF

21

C8079

40216VX5R10%

0.1uF

21

C8080

9

90

9

90

40216VX5R10%

0.1uF

21

C8077

40216VX5R10%

0.1uF

21

C8078

9

90

9

90

40216VX5R10%

0.1uF

21

C8075

40216VX5R10%

0.1uF

21

C8076

9

90

9

90

402X5R16V10%

0.1uF

21

C8073

402X5R16V10%

0.1uF

21

C8074

9

90

0.1uF

402X5R16V10%

21

C8020

9

90

402X5R16V10%

0.1uF

21

C8071

402X5R16V10%

0.1uF

21

C8072

9

90

9

90

40216VX5R10%

0.1uF

21

C8069

40216VX5R10%

0.1uF

21

C8070

9

90

9

90

40216VX5R10%

0.1uF

21

C8067

16V10%

0.1uF

402X5R

21

C8021

40216VX5R10%

0.1uF

21

C8068

9

90

9

90

402X5R16V10%

0.1uF

21

C8065

40216VX5R10%

0.1uF

21

C8066

9

90

9

90

402X5R16V10%

0.1uF

21

C8063

402X5R16V10%

0.1uF

21

C8064

9

90

16V10% 402X5R

0.1uF

21

C8050

9

90

402X5R16V10%

0.1uF

21

C8061

402X5R16V

0.1uF

10%

21

C8062

9

90

9

90

40216VX5R10%

0.1uF

21

C8059

40216VX5R10%

0.1uF

21

C8060

9

90

9

90

40216VX5R10%

0.1uF

21

C8057

0.1uF

16V 402X5R10%

21

C8051

40216VX5R10%

0.1uF

21

C8058

16V10% 402X5R

0.1uF

21

C8048

16V10% 402X5R

0.1uF

21

C8049

16V10% 402X5R

0.1uF

21

C8046

4.7UF

20%

6.3V 603

CERM

2

1

C8001

1UF

10%

402

CERM

6.3V

2

1

C8003

CERM

20%

402

10V

0.1UF

2

1

C8004

16V10% 402X5R

0.1uF

21

C8047

0.1UF

CERM 402

20% 10V

2

1

C8005

4.7UF

20% CERM

6.3V 603

2

1

C8016

603

20%

4.7UF

CERM

6.3V 2

1

C8015

CERM-X5R

22UF

6.3V 805

20%

2

1

C8000

16V 402X5R10%

0.1uF

21

C8044

402

CERM

6.3V

10%

1UF

2

1

C8002

6.3V

20% 805

CERM-X5R

22UF

2

1

C8006

603

6.3V

4.7UF

CERM

20%

2

1

C8007

6.3V

10% 402

CERM

1UF

2

1

C8008

1UF

10%

6.3V CERM 402

2

1

C8009

10V

20%

0.1UF

CERM 402

2

1

C8010

10V CERM 402

0.1UF

20%

2

1

C8011

0.1UF

402

CERM

10V

20%

2

1

C8017

10% X5R 40216V

0.1uF

21

C8045

0603

10NH-600MA

21

L8015

16V10% 402X5R

0.1uF

21

C8042

NB9P-GS

BGA

OMIT

AD20

AG14

AG23

AG22

AG18

AG17

AG16

AG15

AG13

AL16

AK26

AK23

AK20

AK18

AJ27

AG12

AJ25

AJ24

AJ22

AJ21

AJ19

AJ15

AJ14

AG26

AG25

AG24

AG11

AK27

AK24

AK21

AK17

AK16

AB7

V6

U7

R7

P7

P6

A2

M7

F7

E35

E7

AL7

AK15

D35

AJ5

AG6

AF6

AD6

H32

AD19

U8000

OMIT

NB9P-GS

BGA

AM26

AL26

AK25

AL25

AM25

AM24

AM23

AL23

AK22

AL22

AM22

AM21

AM20

AL20

AK19

AL19

AP32

AN32

AM32

AM31

AM30

AM29

AL29

AK29

AK28

AL28

AM28

AM27

AM19

AM18

AM17

AL17

AJ18

AJ17

AG21

AN26

AP26

AR26

AR25

AP25

AN25

AN23

AP23

AR23

AR22

AP22

AN22

AN20

AP20

AR20

AR19

AP34

AR34

AR32

AR31

AP31

AN31

AN29

AP29

AR29

AR28

AP28

AN28

AP19

AN19

AN17

AP17

AM16

AG20

AG19

AR17

AR16

AR13

U8000

2.49K

MF-LF

402

1%

1/16W

21

R8050

1/16W

1%

402

MF-LF

200

21

R8060

1/16W MF-LF

402

0

5%

21

R8020

16V10% 402X5R

0.1uF

21

C8043

16V10% 402X5R

0.1uF

21

C8040

16V10% 402X5R

0.1uF

21

C8041

16V10% 402

0.1uF

X5R

21

C8038

X5R16V10% 402

0.1uF

21

C8039

16V10% 402X5R

0.1uF

21

C8036

402X5R

0.1uF

16V10%

21

C8037

16V10% 402X5R

0.1uF

21

C8034

0.1uF

16V10% 402X5R

21

C8035

16V10% 402X5R

0.1uF

21

C8032

16V10% 402X5R

0.1uF

21

C8033

16V10% 402X5R

0.1uF

21

C8030

16V10% 402X5R

0.1uF

21

C8031

16V10% 402X5R

0.1uF

21

C8028

16V10% 402X5R

0.1uF

21

C8029

16V10% 402X5R

0.1uF

21

C8026

16V10% 402X5R

0.1uF

21

C8027

16V10% 402X5R

0.1uF

21

C8024

16V10% 402X5R

0.1uF

21

C8025

0.1uF

16V10% X5R 402

21

C8022

16V10% 402X5R

0.1uF

21

C8023

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

17 90

9

84

16V X5R 40210%

0.1uF

21

C8055

16V X5R 40210%

0.1uF

21

C8056

9

90

9

90

9

90

9

90

402X5R16V10%

0.1uF

21

C8085

402X5R16V10%

0.1uF

21

C8086

9

90

9

90

40216VX5R10%

0.1uF

21

C8083

402X5R16V10%

0.1uF

21

C8084

9

90

A.0.0

051-7892

SYNC_DATE=07/10/2008

71 97

NV G96 PCI-E

SYNC_MASTER=MUXGFX

GPU_RESET_R_L

EG_RESET_L

PEG_R2D_N<12>

PEG_R2D_P<13> PEG_R2D_N<13>

PEG_R2D_N<14>

PP1V1_S0GPU_REG PP1V1_S0GPU_REG

PEG_R2D_C_P<10>

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 mm

PP1V1_GPU_PEX_PLLVDD_F

MIN_NECK_WIDTH=0.25 mm

PEG_R2D_C_P<3>

PEG_R2D_N<7>

PEG_R2D_N<10>

PEG_R2D_N<11>

PEG_R2D_C_P<12>

PEG_R2D_N<15>

PEG_R2D_C_P<6>

PEG_R2D_P<11>

GPU_GND_SENSE

PEG_R2D_N<0>

PEG_R2D_N<1>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_R2D_C_N<13>

PEG_R2D_C_N<8>

PEG_R2D_C_P<8>

PEG_R2D_C_P<7>

PEG_R2D_C_N<6>

PEG_R2D_C_P<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_N<1>

PEG_D2R_P<1>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_N<3>

PEG_D2R_P<3>

PEG_D2R_N<4>

PEG_D2R_P<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_N<6>

PEG_D2R_P<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<9>

PEG_D2R_N<14>

PEG_D2R_P<13>

PEG_D2R_N<12>

PEG_D2R_N<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_N<13>

PEG_D2R_P<15>

PEG_D2R_N<15>

PEG_R2D_P<2> PEG_R2D_N<2>

PEG_R2D_C_P<4>

PEG_D2R_C_N<5>

PEG_D2R_C_N<6>

PEG_R2D_N<3>

PEG_R2D_P<4>

PEG_R2D_N<9>

PEG_R2D_P<10>

PEG_D2R_C_P<1>

PEG_D2R_C_P<7> PEG_D2R_C_N<7>

PEG_D2R_C_P<10>

PEG_D2R_C_P<11> PEG_D2R_C_N<11>

PEG_D2R_C_P<12> PEG_D2R_C_N<12>

PEG_D2R_C_N<9>

PEG_D2R_C_N<8>

PEG_R2D_N<8>

PEG_R2D_N<6>

PEG_D2R_C_P<9>

PEG_D2R_C_P<5>

PEG_D2R_C_P<6>

PEG_D2R_C_P<8>

PEG_R2D_P<3>

PEG_R2D_P<6>

PEG_R2D_P<7>

PEG_R2D_P<8>

PEG_R2D_P<15>

PEG_R2D_P<14>

NO_TEST=TRUE

NC_GPU_DFM

PEG_R2D_C_N<5>

PEG_R2D_C_N<7>

PEG_R2D_C_N<1>

PEG_R2D_N<5>

PEG_R2D_P<5>

PEG_R2D_N<4>

PEG_R2D_P<9>

PEG_R2D_C_N<10>

PEG_R2D_C_N<9>

PEG_R2D_C_P<11>

PEG_R2D_C_N<12>

PEG_R2D_P<12>

PEG_D2R_C_N<4>

PEG_D2R_C_P<4>

PEG_D2R_C_N<3>

PEG_D2R_C_P<3>

PEG_D2R_C_N<2>

PEG_D2R_C_P<2>

PEG_D2R_C_N<1>

PEG_D2R_C_N<0>

PEG_D2R_C_P<0>

GPU_VDD_SENSE

PEG_D2R_C_N<10>

PEG_D2R_P<10>

PEG_D2R_C_N<14>

PEX_TSTCLK_P

PEG_D2R_C_P<14>

PEG_D2R_C_N<13>

PEG_D2R_C_P<13>

PEX_TSTCLK_N

PEX_TERMP_PD

PEG_D2R_C_P<15> PEG_D2R_C_N<15>

PEG_R2D_C_P<13>

TP_PEX_CLKREQ_L

PEG_R2D_C_N<11>

PEG_R2D_C_P<9>

PEG_R2D_C_P<1>

PEG_R2D_C_N<0>

PEG_R2D_C_P<0>

PEG_R2D_C_P<15>

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

PEG_R2D_C_N<15>

PEG_CLK100M_N

PEG_CLK100M_P

PP1V1_S0GPU_REG

90

8

71 73 76 78 83

8

71 73 76 78 83

90

79

90

90 90

90

79

90

8

71 73 76 78 83

VDD VDD

SYMBOL 9 OF 9

SYMBOL 7 OF 9

FBVDDQ FBVDDQ

SYMBOL 8 OF 9

GNDGND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

???A @ ???/???MHz Core/Mem Clk for VDD

???A @ ???MHz 1.8V GDDR3

Page Notes

Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF

Signal aliases required by this page:

BOM options provided by this page:

- =PP1V8_GPU_FBVDDQ

(NONE)

- =PPVCORE_GPU

Power aliases required by this page:

6.3V

402

X5R-CERM

20%

4.7UF

2

1

C8101

402

6.3V X5R-CERM

20%

4.7UF

2

1

C8100

402

6.3V X5R-CERM

20%

4.7UF

2

1

C8102

10%

0.47UF

6.3V

402

CERM-X5R

2

1

C8107

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8112

0.1UF

CERM 402

10V

20%

2

1

C8117

402

CERM-X5R

10%

6.3V

0.47UF

2

1

C8106

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8105

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8110

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8111

10V

0.1UF

402

20%

CERM

2

1

C8116

CERM 402

20%

0.1UF

10V

2

1

C8115

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8104

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8109

0.1UF

CERM 402

10V

20%

2

1

C8114

402

CERM

10V

20%

0.1UF

2

1

C8113

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8108

402

CERM-X5R

10%

0.47UF

6.3V

2

1

C8103

402

CERM-X5R

10%

6.3V

0.47UF

2

1

C8160

CERM-X5R

402

0.47UF

6.3V

10%

2

1

C8166

CERM

402

10V

20%

0.1UF

2

1

C8159

4.7UF

603

20%

CERM

6.3V 2

1

C8151

CERM

402

10V

20%

0.1UF

2

1

C8158

CERM

402

0.1UF

20% 10V

2

1

C8165

CERM

402

0.1UF

20% 10V

2

1

C8164

4.7UF

603

20%

6.3V CERM

2

1

C8150

CERM

402

10V

0.1UF

20%

2

1

C8157

402

CERM

10V

20%

0.1UF

2

1

C8163

402

0.1UF

CERM

20% 10V

2

1

C8162

CERM

402

20%

0.1UF

10V

2

1

C8156

10V

20%

CERM 402

0.1UF

2

1

C8122

10V

20%

402

0.1UF

CERM

2

1

C8121

10V

20%

CERM 402

0.1UF

2

1

C8120

20%

0.1UF

10V CERM 402

2

1

C8119

0.1UF

10V

20%

402

CERM

2

1

C8118

402

CERM-X5R

10%

6.3V

0.47UF

2

1

C8161

0.47UF

402

6.3V

10%

CERM-X5R

2

1

C8167

0.47UF

CERM-X5R

10%

6.3V

402

2

1

C8169

CERM-X5R

0.47UF

10%

6.3V

402

2

1

C8168

0.47UF

CERM-X5R

10%

6.3V

402

2

1

C8171

0.47UF

CERM-X5R

10%

6.3V

402

2

1

C8170

NB9P-GS

OMIT

BGA

AC19

AC18

AC17

AC16

AC15

AC14

AC13

AC12

AC11

AB25

L19

AB23

AB21

AB19

AB17

AB15

AB13

AB11

Y24

Y22

Y20

L18

Y18

Y16

Y14

Y12

W25

W24

W23

W22

W21

AD24

L17

W19

W18

W17

W16

W15

W14

W13

W12

W11

V25

L16

V23

V21

V19

V17

V15

V13

V11

T24

T22

T20

L15

T18

T16

T14

T12

R25

R24

R23

R22

R21

R20

L14

R19

R18

R17

R16

R15

R14

R13

R12

R11

P25

L13

P23

P21

P19

P17

P15

P13

P11

M24

M22

M20

L12

M18

M16

M14

M12

L25

L24

L23

L22

W20

AD22

L21

AD18

AD16

AD14

AD12

AC25

AC24

AC23

AC22

AC21

AC20

L20

L11

U8000

NB9P-GS

OMIT

BGA

AJ28

AE27

AD27

AC27

AB29

AB27

AA31

AA29

AA27

Y27

W27

V34

V29

V27

U29

U27

T27

R27

P27

N27

J29

J24

J23

J22

J21

J20

J17

J16

J15

J14

H29

G22

G18

G17

G9

G8

E21

B18

U8000

NB9P-GS

BGA

V22

V20

V18

V16

V14

V12

V9

V5

V2

U25

B30

U24

U23

U22

U21

U20

U19

U18

U17

U16

U15

B27

U14

U13

U12

U11

T25

T23

T21

T19

T17

T15

B24

T13

T11

R34

R31

R5

R2

P24

P22

P20

P18

B21

P16

P14

P12

N25

N24

N23

N22

N21

N20

N19

B15

N18

N17

N16

N15

N14

N13

N12

N11

M34

M31

B12

M25

M23

M21

M19

M17

M15

M13

M11

M5

M2

B9

L9

J34

J31

J5

J2

F34

F31

F5

F2

E30

B6

AP30

AP27

E27

AP24

AP21

AP18

AP15

AP12

AP9

AP6

AP3

AN34

AN2

E24

AL30

AL27

AL24

AL21

AL18

AL15

AL12

AL9

AL6

AK34

E18

AK31

AP33

AK5

AK2

AG34

AG31

AG5

AG2

AE25

AE24

E15

AE23

AE22

AE21

AE20

AE19

AE18

AE17

AE16

AE15

AE14

E12

AE13

AE12

AE11

AD34

AD31

AD25

AD23

AD21

AD17

AD15

E9

AD13

AD11

AD5

AD2

AC9

AB24

AB22

AB20

AB18

AB16

E6

AB14

AB12

AA34

AA25

AA24

AA23

AA22

AA21

AA20

AA19

C34

AA18

AA17

AA16

AA15

AA14

AA13

AA12

AA11

AA5

AA2

C2

Y25

Y23

Y21

Y19

Y17

Y15

Y13

Y11

V31

V24

B33

B3

U8000

9772

051-7892

A.0.0

SYNC_DATE=07/10/2008

NV G96 Core/FB Power

SYNC_MASTER=MUXGFX

PPVCORE_GPU

PP1V8_S0GPU_ISNS

8 46

79

8 9

47 73 74 75

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

BI BI BI BI BI BI BI BI

IN IN IN IN IN IN

IN

OUT

OUT OUT OUT OUT

OUT

BI

IN IN IN IN IN IN IN IN

OUT OUT OUT

OUT

OUT OUT OUT

D

SG

IN

OUT OUT

OUT

FBC_D8

FBC_CMD2 FBC_CMD3

FBC_RFU0 FBC_RFU1*

FBC_RFU7*

FBC_RFU6

FBC_RFU5*

FBC_RFU4

FBC_RFU3*

FBC_RFU2

FBC_D63

FBC_D62

FBC_D21

FBC_D24 FBC_D25 FBC_D26

FBC_D0

FBC_D2

FBC_CMD1

FBC_CMD0

FBC_D5

FBC_D3 FBC_D4

FBC_D6 FBC_D7

FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20

FBC_D23

FBC_D28

FBC_D31

FBC_D34

FBC_D32 FBC_D33

FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55

FBC_CMD26

FBC_CMD25

FBC_CMD24

FBC_CMD23

FBC_CMD22

FBC_CMD20

FBC_CMD19

FBC_CMD17

FBC_CMD16

FBC_CMD14

FBC_CMD13

FBC_CMD11

FBC_CMD10

FBC_CMD9

FBC_CMD8

FBC_CMD7

FBC_CMD6

FBC_CMD5

FBC_CMD4

FBC_CMD21

FBC_CMD18

FBC_CMD15

FBC_CMD12

FBC_D1

FBC_D58

FBC_D57

FBC_D56

FBC_D27

FBC_D29 FBC_D30

FBC_D35

FBC_D22

FBC_CLK0*

FBC_CLK0

FBC_CLK1

FBC_CLK1*

FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

FBC_DQS_WP1

FBC_DQS_WP0

FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

FB_DLLAVDD1

FBC_DEBUG

FB_PLLAVDD1

FB_VREF

FBC_CMD28

FBC_CMD27

FBC_CMD30

FBC_CMD29

FBC_D61

FBC_D60

FBC_D59

SYMBOL 4 OF 9

FBA_D62

FBA_D60

FBA_D59

FBA_D57

FBA_D55

FBA_D52

FBA_D48

FBA_D43

FBA_D39

FBA_D36

FBA_D34

FBA_D32

FBA_D30

FBA_D28

FBA_D27

FBA_D26

FBA_D25

FBA_CMD0

FBA_CMD7

FBA_CMD9

FBA_D5

FBA_CMD1

FBA_D0 FBA_D1

FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6

FBA_CMD8

FBA_CMD10 FBA_CMD11

FBA_CMD15

FBA_CMD14

FBA_CMD13

FBA_CMD12

FBA_D14 FBA_D15

FBA_D17

FBA_D20

FBA_D23 FBA_D24

FBA_D33

FBA_D35

FBA_D38

FBA_D40 FBA_D41 FBA_D42

FBA_D44 FBA_D45 FBA_D46 FBA_D47

FBA_D49 FBA_D50 FBA_D51

FBA_D53 FBA_D54

FBA_D56

FBA_CMD24

FBA_CMD23

FBA_CMD22

FBA_CMD21

FBA_CMD20

FBA_CMD19

FBA_CMD18

FBA_CMD17

FBA_CMD16

FBA_D22

FBA_D19

FBA_D16

FBA_CMD25

FBA_D31

FBA_D18

FBA_D3

FBA_D11

FBA_D10

FBA_D9

FBA_D8

FBA_D7

FBA_D6

FBA_D4

FBA_D2

FBA_D37

FBA_D21

FBA_D29

FBA_DQM5 FBA_DQM6

FBA_DQS_RN0

FBA_DQM7

FBA_DQS_RN2

FBA_DQS_RN1

FBA_DQS_RN4

FBA_DQS_RN3

FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1

FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6

FB_DLLAVDD0

FBA_DQS_WP7

FBA_DEBUG

FB_PLLAVDD0

FB_CAL_PU_GND

FB_CAL_PD_VDDQ

FB_CAL_TERM_GND

FBA_CLK1*

FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4

FBA_CLK0*

FBA_CLK1

FBA_CLK0

FBA_CMD30

FBA_DQM0

FBA_DQS_WP3

FBA_DQS_WP2

FBA_D58

FBA_D63

FBA_D61

FBA_RFU7*

FBA_RFU1*

FBA_RFU3* FBA_RFU4 FBA_RFU5* FBA_RFU6

FBA_RFU2

FBA_RFU0

FBA_D13

FBA_D12

FBA_CMD29

FBA_CMD28

FBA_CMD27

FBA_CMD26

SYMBOL 3 OF 9

NC

NC NC

NC NC NC NC NC NC

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

(NONE)

- =PP1V8_GPU_FBIO

(NONE)

BOM options provided by this page:

- =PP1V2_GPU_FBPLLAVDD

74 95

74

74 95

77

74 95

75 95

74

74 95

402

20%

0.1UF

10V CERM

2

1

C8201

74 95

75 95

77

75

75 95

75

75 95

1/16W

10K

5%

MF-LF 402

2

1

R8200

75 95

10K

402

MF-LF

1/16W

5%

2

1

R8250

1%

33.2

402

MF-LF

1/16W

PLACEMENT_NOTE=Place close to U8000.

2

1

R8291

NO STUFF

402

X5R

10%

0.1uF

16V

2

1

C8296

1%

1/16W

402

MF-LF

1.07K

2

1

R8295

FERR-220-OHM

0402

21

L8200

48.7

PLACEMENT_NOTE=Place close to U8000.

1% 1/16W MF-LF

402

2

1

R8290

6.3V CERM

1UF

10%

402

2

1

C8200

402

5% 1/16W MF-LF

10K

2

1

R8201

10K

402

MF-LF

1/16W

5%

2

1

R8251

74 95

75 95

NO STUFF

SOT563

SSM6N15FEAPE

1

2

6

Q8295

2.49K

1% 1/16W MF-LF

402

2

1

R8296

NO STUFF

1/16W MF-LF

402

1%

1.02K

2

1

R8297

74 75 76 77

74 95 75 95

74 95

77

75 95

77

OMIT

NB9P-GS

BGA

G28

G27

G25

G24

G15

G14

G12

G11

A32

D32

B26

E26

C14

D14

A10

E10

A31

D31

A26

F26

B14

E14

B10

D9

A34

D34

D28

D27

A16

D15

D10

F11

G19

C13

B11

F12

B35

B34

C32

B32

E8

C31

B31

C29

B29

E32

F32

D33

C33

E31

D30

F9

F29

E29

A29

A28

B28

C28

C26

D25

B25

A25

F8

D29

F28

E28

F27

F25

E25

D26

D24

D16

B16

D8

A17

C16

A14

B13

A13

D13

F13

F14

E16

F16

F10

F15

F17

E13

D12

C10

C11

C8

A8

B8

A11

E11

D11

F20

G21

E20

B23

D21

A23

A20

F21

B20

C23

F22

C19

F18

D19

E19

D20

D22

A19

D18

B22

C20

E22

C25

F24

B17

C22

A22

F23

F19

B19

C17

E23

D23

D17

E17

J27

J18

J19

U8000

PLACEMENT_NOTE=Place close to U8000.

40.2

1%

MF-LF

402

1/16W

2

1

R8292

402

CERM

10V

20%

0.1UF

2

1

C8202

402

CERM

10V

0.1UF

20%

2

1

C8291

402

CERM

10V

0.1UF

20%

2

1

C8290

402

MF-LF

1/16W

1%

60.4

2

1

R8293

MF-LF

60.4

1/16W

1%

402

2

1

R8294

OMIT

BGA

NB9P-GS

AH29

AG29

AE29

AD29

M29

L29

R29

P29

AJ34

AJ32

AC33

AE31

H35

J32

L34

N31

AJ35

AJ31

AC34

AD32

G35

H31

L35

N32

AL34

AL32

AF35

AF32

H34

J30

P32

P30

T30

P34

P33

L30

AJ33

AL35

AM34

AH34

M30

AH32

AH35

AH33

AM35

AH30

AJ30

AK30

AL31

AM33

AL33

M32

AK32

AN33

AB32

AC35

AE34

AE33

AE35

AF34

AF33

AE32

L31

AE30

AC32

AD30

AF30

AF31

AG32

AH31

AG30

G33

E34

N30

E33

K34

G34

K33

K35

H33

G31

F30

H30

G32

P31

K32

G30

K30

K31

N33

L32

L33

N34

P35

N35

R32

R30

T34

W30

W33

W35

AB34

AB35

W29

Y32

T33

AB33

AB30

U33

U30

U35

V30

W34

Y35

U34

U31

Y31

U32

Y33

AA32

AA30

W32

Y34

Y30

AB31

T35

W31

V32

AC30

AC31

T31

T32

AF27

AG27

M27

L27

K27

U8000

FERR-220-OHM

0402

21

L8290

6.3V CERM

1UF

10%

402

2

1

C8292

A.0.0

051-7892

9773

SYNC_DATE=07/10/2008

SYNC_MASTER=MUXGFX

NV G96 Frame Buffer I/F

FB_A_MA<9> FB_A_MA<6> FB_A_LMA<2> FB_A_MA<8> FB_A_LMA<3> FB_A_MA<1>

FB_B_DQ<62> FB_B_DQ<63>

GPU_FB_VREF

FBC_DEBUG

FB_B_DQ<42>

NC_FBA_CMD29

FB_A_DQ<48> FB_A_DQ<49>

FB_A_WDQS<6>

FB_A_WDQS<4>

FB_A_DQ<40>

FB_A_DQ<45>

FB_A_DQ<11>

FB_A_DQ<62>

FB_A_DQ<60>

FB_A_DQ<59>

FB_A_DQ<57>

FB_A_DQ<55>

FB_A_DQ<52>

FB_A_DQ<43>

FB_A_DQ<39>

FB_A_DQ<36>

FB_A_DQ<34>

FB_A_DQ<32>

FB_A_DQ<30>

FB_A_DQ<28>

FB_A_DQ<27>

FB_A_DQ<26>

FB_A_DQ<25>

FB_A_LMA<4>

NC_FB_A_CS1_L

FB_A_MA<11>

FB_A_DQ<5>

FB_A_RAS_L

FB_A_DQ<0> FB_A_DQ<1>

FB_A_LMA<5> FB_A_BA<1> FB_A_UMA<2> FB_A_UMA<4> FB_A_UMA<3>

FB_A_CS0_L

FB_A_CAS_L FB_A_WE_L

FB_A_DRAM_RST

FB_A_MA<12>

FB_A_UMA<5>

FB_A_BA<0>

FB_A_DQ<14> FB_A_DQ<15>

FB_A_DQ<17>

FB_A_DQ<20>

FB_A_DQ<23> FB_A_DQ<24>

FB_A_DQ<33>

FB_A_DQ<35>

FB_A_DQ<38>

FB_A_DQ<41> FB_A_DQ<42>

FB_A_DQ<44>

FB_A_DQ<46> FB_A_DQ<47>

FB_A_DQ<50> FB_A_DQ<51>

FB_A_DQ<53> FB_A_DQ<54>

FB_A_DQ<56>

FB_A_MA<0>

FB_A_MA<10>

FB_A_MA<7>

FB_A_DQ<22>

FB_A_DQ<19>

FB_A_DQ<16>

FB_A_DQ<31>

FB_A_DQ<18>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<8>

FB_A_DQ<7>

FB_A_DQ<6>

FB_A_DQ<4>

FB_A_DQ<2>

FB_A_DQ<37>

FB_A_DQ<21>

FB_A_DQ<29>

FB_A_DQM_L<5> FB_A_DQM_L<6>

FB_A_RDQS<0>

FB_A_DQM_L<7>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A_RDQS<4>

FB_A_RDQS<3>

FB_A_RDQS<5> FB_A_RDQS<6> FB_A_RDQS<7>

FB_A_WDQS<0> FB_A_WDQS<1>

FB_A_WDQS<5>

FB_A_WDQS<7>

FBA_DEBUG

FBCAL_PU_GND

FBCAL_PD_VDDQ

FBCAL_TERM_GND

FB_A_CLK_N<1>

FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3> FB_A_DQM_L<4>

FB_A_CLK_N<0> FB_A_CLK_P<1>

FB_A_CLK_P<0>

NC_FBA_CMD30

FB_A_DQM_L<0>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_DQ<58>

FB_A_DQ<63>

FB_A_DQ<61>

FB_A_DQ<13>

FB_A_DQ<12>

NC_FBA_CMD28

FB_A_BA<2>

FB_B_CKE

FB_B_CLK_P<0>

FB_B_CLK_N<1>

FB_B_DQ<12>

PP1V8_S0GPU_ISNS

FB_B_WDQS<7>

FB_B_MA<8>

FB_B_DQ<26>

FB_B_DQ<5>

FB_B_DQ<3> FB_B_DQ<4>

FB_B_DQ<6> FB_B_DQ<7>

FB_B_DQ<9>

FB_B_DQ<8>

FB_B_DQ<10> FB_B_DQ<11>

FB_B_DQ<13> FB_B_DQ<14> FB_B_DQ<15> FB_B_DQ<16> FB_B_DQ<17> FB_B_DQ<18> FB_B_DQ<19> FB_B_DQ<20> FB_B_DQ<21> FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<24>

FB_B_DQ<27> FB_B_DQ<28> FB_B_DQ<29>

FB_B_DQ<34>

FB_B_DQ<33>

FB_B_DQ<37>

FB_B_DQ<43>

FB_B_DQ<58>

FB_B_BA<2>

NC_FBB_MA<13>

FB_B_MA<1>

FB_B_LMA<3>

FB_B_LMA<2>

FB_B_MA<10>

FB_B_MA<7>

FB_B_MA<12>

FB_B_UMA<5>

FB_B_WE_L

FB_B_CAS_L

FB_B_MA<11>

FB_B_CS0_L

NC_FB_B_CS1_L

FB_B_UMA<3>

FB_B_UMA<4>

FB_B_UMA<2>

FB_B_BA<1>

FB_B_LMA<5>

FB_B_DRAM_RST

FB_B_BA<0>

FB_B_DQ<0> FB_B_DQ<1> FB_B_DQ<2>

FB_B_DQ<61>

FB_B_RAS_L

FB_B_LMA<4>

FB_B_DQ<59>

FB_B_DQ<57>

FB_B_DQ<55>

FB_B_DQ<52>

FB_VREF_UNTERM

FB_B_DQ<36>

FB_B_DQ<60>

FB_B_DQ<53>

FB_B_DQ<30> FB_B_DQ<31> FB_B_DQ<32>

FB_B_DQ<45>

FB_B_DQ<44>

FB_B_CLK_N<0> FB_B_CLK_P<1>

FB_B_DQM_L<5>

FB_B_RDQS<0> FB_B_RDQS<1> FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<4>

FB_B_RDQS<6>

FB_B_WDQS<2>

FB_B_WDQS<4>

FB_B_WDQS<3>

FB_B_WDQS<5> FB_B_WDQS<6>

FB_B_DQ<25>

NC_FBC_CMD28 NC_FBC_CMD29 NC_FBC_CMD30

FB_B_MA<6>

FB_B_MA<9>

FB_B_MA<0>

FB_B_WDQS<1>

FB_B_RDQS<5>

FB_B_DQ<47>

FB_B_DQ<46>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_DQ<50>

FB_B_DQ<35>

FB_B_DQM_L<4>

FB_B_DQM_L<3>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_DQ<48> FB_B_DQ<49>

FB_B_DQ<54>

FB_B_DQ<41>

FB_B_DQ<40>

FB_B_DQ<39>

FB_B_DQ<38>

FB_B_DQ<56>

FB_B_DQ<51>

PP1V1_S0GPU_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

GPU_FB_VREF_UNTERM_L

NC_FBA_MA<13>

FB_A_DQ<3>

FB_A_CKE

FB_B_WDQS<0>

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2 MM

PP1V1_GPU_FBPLLAVDD0_F

MIN_NECK_WIDTH=0.2 MM

FB_B_RDQS<7>

VOLTAGE=1.1V

PP1V1_GPU_FBPLLAVDD1_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V1_S0GPU_REG

PP1V8_S0GPU_ISNS

77

8 9

47 72 73

74 75

77

8

71 73 76 78 83

8

71 73 76 78 83

8 9

47 72 73 74 75

IN

BI

BI BI

BI

BI BI BI

BI

BI BI BI

BI

IN

IN IN IN

OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

D

SG

D

SG

D

SG

D

SG

IN IN

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

BI BI

BI

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

U8400.J12

Connect to designated pin, then GND Connect to designated pin, then GND

BOM options provided by this page:

(NONE)

U8400.J1 U8400.J1

U8400.J12

VRAM4

Signal aliases required by this page:

- =PP1V8_S0_FB_VDD

Power aliases required by this page:

Page Notes

- =PP1V8_S0_FB_VREFA

1/16W MF-LF

402

1%

549

2

1

R8430

402

MF-LF

1/16W

1%

1.33K

2

1

R8431

10%

0.1uF

X5R 402

16V

2

1

C8403

0.1uF

402

X5R

10% 16V

2

1

C8402

0.1uF

16V X5R 402

10%

2

1

C8404

0.1uF

X5R 402

10% 16V

2

1

C8401

10%

0.1uF

16V X5R 402

2

1

C8422

402

X5R

16V

10%

0.1uF

2

1

C8423

402

0.1uF

16V

10% X5R

2

1

C8424

X5R 402

16V

0.1uF

10%

2

1

C8425

402

0.1uF

X5R

10% 16V

2

1

C8426

100

402

1/16W

5%

MF-LF

2

1

R8449

MF-LF

243

402

1%

1/16W

2

1

R8448

VRAM4

MF-LF

1/16W 402

121

1%

2

1

R8445

1/16W

1%

402

MF-LF

243

2

1

R8446

0.1uF

10% 16V X5R 402

2

1

C8421

0.1uF

X5R 402

10% 16V

2

1

C8415

X5R 402

16V

10%

0.1uF

2

1

C8410

MF-LF

1/16W

402

1K

5%

2

1

R8440

1/16W

243

MF-LF

1%

402

2

1

R8447

VRAM4

1/16W

402

MF-LF

121

1%

2

1

R8444

1/16W

VRAM4

MF-LF

1%

121

402

2

1

R8443

VRAM4

1/16W

402

MF-LF

121

1%

2

1

R8442

73 95

73 74 95

73 74

73 95

73 74

73 74 95

73 95

73 74 95

73 95

73 74 95

73 95

73 74 95

73 74

73 74 95

73 95

73 74

73 95

73 74 95

73 95

73 74 95

5%

1K

1/16W

402

MF-LF

2

1

R8490

MF-LF

VRAM4

1/16W

121

1%

402

2

1

R8492

402

16V X5R

0.1uF

10%

2

1

C8471

16V

10%

402

X5R

0.1uF

2

1

C8472

1/16W

1%

402

MF-LF

243

2

1

R8498

5% 1/16W

402

MF-LF

100

2

1

R8499

VRAM4

1%

121

MF-LF 402

1/16W

2

1

R8493

VRAM4

121

1/16W 402

1%

MF-LF

2

1

R8495

MF-LF

1/16W

402

121

1%

VRAM4

2

1

R8494

MF-LF

1%

402

1/16W

243

2

1

R8497

MF-LF

402

1%

1/16W

243

2

1

R8496

16V

10%

402

X5R

0.1uF

2

1

C8473

16V

10%

402

X5R

0.1uF

2

1

C8474

10% 16V

402

X5R

0.1uF

2

1

C8475

16V

10%

402

X5R

0.1uF

2

1

C8476

X5R

16V

10%

402

0.1uF

2

1

C8451

402

16V

10%

0.1uF

X5R

2

1

C8452

0.1uF

16V

10%

402

X5R

2

1

C8460

16V

10%

0.1uF

X5R 402

2

1

C8453

16V

10%

402

X5R

0.1uF

2

1

C8465

16V

10%

402

X5R

0.1uF

2

1

C8454

73 95

10UF

20%

603

6.3V X5R

2

1

C8400

X5R 603

10UF

20%

6.3V 2

1

C8420

10UF

603

X5R

6.3V

20%

2

1

C8450

10UF

603

X5R

6.3V

20%

2

1

C8470

CERM

0.01UF

402

10% 16V

2

1

C8446

0.01UF

402

16V

10%

CERM

2

1

C8496

1%

402

MF-LF

1/16W

931

2

1

R8432

16V

10%

0.01uF

402

CERM

2

1

C8481

931

1/16W

1%

MF-LF

402

2

1

R8482

549

402

MF-LF

1%

1/16W

2

1

R8480

1.33K

1%

MF-LF

1/16W

402

2

1

R8481

73 74 75 76 77

SOT563

SSM6N15FEAPE

1

2

6

Q8400

SOT563

SSM6N15FEAPE

1

2

6

Q8450

402

931

MF-LF

1%

1/16W

2

1

R8435

1%

MF-LF

402

1/16W

549

2

1

R8433

MF-LF

1%

402

1/16W

1.33K

2

1

R8434

10% 16V

0.01UF

402

CERM

2

1

C8431

SOT563

SSM6N15FEAPE

4

5

3

Q8400

CERM

0.01uF

16V

10%

402

2

1

C8482

931

1%

402

MF-LF

1/16W

2

1

R8485

549

MF-LF

402

1%

1/16W

2

1

R8483

1.33K

1%

1/16W

402

MF-LF

2

1

R8484

SOT563

SSM6N15FEAPE

4

5

3

Q8450

73 74 95 73 74 95

CRITICAL

32MX32-900MHZ-MFH

K4J10324QD-HC11

BGA

OMIT

A4

H4

P2

P11

D11

D2

V4

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

J3

L9

K11

H11

K9

U8450

K4J10324QD-HC11

BGA

32MX32-900MHZ-MFH

CRITICAL

OMIT

A4

H4

P2

P11

D11

D2

V4

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

J3

L9

K11

H11

K9

U8400

32MX32-900MHZ-MFH

K4J10324QD-HC11

BGA

CRITICAL

OMIT

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8400

K4J10324QD-HC11

32MX32-900MHZ-MFH

OMIT

BGA

CRITICAL

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8450

73 95

0.01UF

10%

402

CERM

16V

2

1

C8432

GDDR3 Frame Buffer A (Top)

051-7892

SYNC_DATE=07/10/2008

SYNC_MASTER=MUXGFX

74 97

A.0.0

FB_A_RDQS<6> FB_A_RDQS<4>

FB_A_WDQS<7> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<4>

FB_A_BA<0> FB_A_BA<1> FB_A_BA<2>

FB_A1_SEN

FB_A_MA<1>

FB_A_UMA<5>

FB_A_CKE

FB_A_MA<9>

FB_A_DQ<60> FB_A_DQ<57> FB_A_DQ<56>

FB_A_DQ<59> FB_A_DQ<58> FB_A_DQ<63>

FB_A_DQ<61>

FB_A_DQ<40>

FB_A_DQ<62>

FB_A_DQ<44>

FB_A_DQ<47>

FB_A_DQ<33>

FB_A_DQ<32>

FB_A_DQ<36> FB_A_DQ<37>

FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<34>

PP1V8_S0GPU_ISNS

FB_A_MA<11>FB_A_MA<11>

FB_A_MA<10>

FB_A_MA<9>

FB_A_MA<8>

FB_A_MA<7>

FB_A_MA<6>

FB_A_LMA<5>

FB_A_LMA<4>

FB_A_LMA<3>

FB_A_CKE

FB_A_CS0_L

FB_A_DQ<16>

FB_A_DQ<19>

FB_A_DQ<21>

FB_A_DQ<22>

FB_A_DQ<20>

FB_A_DQ<26>

FB_A_DQ<25>

FB_A_DQ<27>

FB_A_DQ<17>

FB_A_DQ<6> FB_A_DQ<7>

FB_A_DQ<8> FB_A_DQ<11>

FB_A_DQ<9>

FB_A_DQ<10>

FB_A_DQ<14>

FB_A_DQ<4>

FB_A_DQ<15>

FB_A_DQ<0>

FB_A_DQ<3>

FB_A_DQ<2>

FB_A_CLK_N<0>

FB_A_DQM_L<0>

FB_A_BA<2>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<2>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_WDQS<3>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A0_SEN

FB_A_DQ<13>

FB_A_DQ<23>

FB_A_DQ<18>

FB_A_DQ<1>

FB_A_DQ<12>

FB_A_DQM_L<1>

FB_A_DQM_L<2>

FB_A_DQM_L<3>

FB_A_CAS_L

FB_A_WE_L

FB_A0_ZQ

FB_A_RAS_L

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_DRAM_RST

FB_A_LMA<2>

FB_A_MA<1>

FB_A_MA<0>

FB_A_MA<12>

FB_A_DQ<24>

FB_A_DQ<29>

FB_A_DQ<30>

FB_VREF_UNTERM

PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS

GPU_FB_A_VREF_DIV

FB_A0_VREF_UNTERM_L

FB_A_DQM_L<4>

FB_A_DQM_L<6>

FB_A_DQM_L<5>

FB_A_DRAM_RST

FB_A_RDQS<7>

FB_A2_VREF FB_A3_VREF

VOLTAGE=0.9V

FB_A_CLK1_TERM

GPU_FB_A_VREF_DIV

FB_A1_VREF

FB_A2_VREF_UNTERM_L

FB_A0_VREF

VOLTAGE=0.9V

FB_A_CLK0_TERM

FB_A1_VREF_UNTERM_L

FB_A3_VREF_UNTERM_L

FB_A_DQ<35>

FB_A_MA<7>

FB_A_RDQS<5>

FB_A_DQM_L<7>

FB_VREF_UNTERM

FB_A_UMA<2>

FB_A_UMA<4>

FB_A_DQ<31> FB_A_DQ<28>

FB_A0_MF

FB_A_DQ<5>

FB_A1_MF

FB_A_DQ<43> FB_A_DQ<41> FB_A_DQ<54>

FB_A_MA<10>

FB_A_UMA<3>

FB_A_MA<0>

FB_A_MA<6>

FB_A_MA<8>

FB_A_DQ<46> FB_A_DQ<45> FB_A_DQ<42>

FB_A_DQ<55>

FB_A_DQ<50> FB_A_DQ<48>

FB_A_DQ<53> FB_A_DQ<52>

FB_A_DQ<51>

FB_A_DQ<49>

FB_A1_ZQ

FB_A_RAS_L

FB_A_CAS_L

FB_A_WE_L

FB_A_CS0_L

FB_A_CLK_N<1>

FB_A_CLK_P<1>

FB_A_MA<12>

FB_A_CLK_P<0>

PP1V8_S0GPU_ISNS

8 9

47 72 73 74 75

8 9

47 72 73 74

75

8 9

47 72 73 74 75

9

27 74

9

27 74

8 9

47 72 73 74

75

IN

IN IN

IN

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI BI BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

BI BI BI BI

BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

D

SG

D

SG

D

SG

D

SG

ININ

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ7

DQ10 DQ11 DQ12 DQ13

DQ15 DQ16

DQ18 DQ19

DQ21

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

A3 A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5 A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0 VDD1

VDD4

VDD3

VDD2

VSS6 VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0 VSSA1

VDDA0 VDDA1

VDD7

VDD6

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21

VSSQ0

VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19

VREF0 VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

VRAM4

Connect to designated pin, then GND

U8500.J12

U8500.J1

U8500.J12

(NONE)

U8500.J1

Connect to designated pin, then GND

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V8_S0_FB_VDD

Power aliases required by this page:

Page Notes

- =PP1V8_S0_FB_VREF_B

0.1uF

16V

10% X5R

402

2

1

C8503

16V

10%

402

X5R

0.1uF

2

1

C8502

0.1uF

16V

402

X5R

10%

2

1

C8504

0.1uF

402

16V

10% X5R

2

1

C8501

16V

10%

402

X5R

0.1uF

2

1

C8522

16V

10%

402

X5R

0.1uF

2

1

C8523

16V

10%

402

X5R

0.1uF

2

1

C8524

16V

10%

402

X5R

0.1uF

2

1

C8525

10% X5R

0.1uF

402

16V

2

1

C8526

1/16W

5%

402

MF-LF

100

2

1

R8549

1/16W

1%

402

MF-LF

243

2

1

R8548

402

16V

10% X5R

0.1uF

2

1

C8521

16V

10%

402

X5R

0.1uF

2

1

C8515

16V

10%

402

X5R

0.1uF

2

1

C8510

73 95

73 75 95

73 75

73 95

73 75

73 75 95

73 95

73 75 95

73 95

73 75 95

73 95

73 75 95

73 75

73 75 95

73 95

73 75

73 95

73 75 95

73 95

73 75 95

X5R 402

10% 16V

0.1uF

2

1

C8571

X5R 402

10% 16V

0.1uF

2

1

C8572

1%

243

MF-LF

402

1/16W

2

1

R8598

100

402

1/16W MF-LF

5%

2

1

R8599

10%

402

X5R

16V

0.1uF

2

1

C8573

16V

10%

402

X5R

0.1uF

2

1

C8574

16V X5R 402

10%

0.1uF

2

1

C8575

X5R 402

10% 16V

0.1uF

2

1

C8576

0.1uF

X5R 402

10% 16V

2

1

C8551

0.1uF

X5R 402

10% 16V

2

1

C8552

16V

10%

402

X5R

0.1uF

2

1

C8560

16V

10%

402

X5R

0.1uF

2

1

C8553

16V

10%

402

X5R

0.1uF

2

1

C8565

0.1uF

X5R 402

10% 16V

2

1

C8554

73 95

10UF

603

X5R

6.3V

20%

2

1

C8500

10UF

603

X5R

6.3V

20%

2

1

C8520

10UF

603

20%

6.3V X5R

2

1

C8550

10UF

603

X5R

6.3V

20%

2

1

C8570

MF-LF

1/16W

402

1%

243

2

1

R8546

1/16W 402

MF-LF

1%

243

2

1

R8547

121

VRAM4

1/16W

1%

MF-LF

402

2

1

R8544

VRAM4

MF-LF 402

1% 1/16W

121

2

1

R8545

VRAM4

402

MF-LF

121

1%

1/16W

2

1

R8542

402

5%

MF-LF

1/16W

1K

2

1

R8540

VRAM4

MF-LF

1%

121

402

1/16W

2

1

R8543

1%

1/16W

402

MF-LF

243

2

1

R8596

1/16W 402

MF-LF

1%

243

2

1

R8597

402

VRAM4

MF-LF

121

1% 1/16W

2

1

R8595

VRAM4

402

1%

121

MF-LF

1/16W

2

1

R8594

402

121

VRAM4

1%

MF-LF

1/16W

2

1

R8592

MF-LF

1%

VRAM4

1/16W

121

402

2

1

R8593

402

1/16W

1K

5%

MF-LF

2

1

R8590

16V

10%

402

0.01UF

CERM

2

1

C8596

0.01UF

CERM

402

10% 16V

2

1

C8546

402

1/16W

1%

MF-LF

1.33K

2

1

R8531

1%

402

MF-LF

1/16W

931

2

1

R8532

10% 16V

402

CERM

0.01uF

2

1

C8531

1/16W

1%

402

MF-LF

549

2

1

R8530

MF-LF

1%

1/16W

402

1.33K

2

1

R8581

1/16W

1%

MF-LF

402

931

2

1

R8582

402

1/16W

1%

549

MF-LF

2

1

R8580

10%

402

CERM

0.01uF

16V

2

1

C8581

73 74 75 76 77

SSM6N15FEAPE

SOT563

1

2

6

Q8500

SSM6N15FEAPE

SOT563

1

2

6

Q8550

CERM

0.01uF

402

10% 16V

2

1

C8532

1/16W

1%

402

MF-LF

931

2

1

R8535

MF-LF

402

1%

1/16W

549

2

1

R8533

1% 1/16W MF-LF

402

1.33K

2

1

R8534

SSM6N15FEAPE

SOT563

4

5

3

Q8500

16V

0.01uF

CERM 402

10%

2

1

C8582

1/16W

1%

MF-LF

402

931

2

1

R8585

1/16W

1%

402

MF-LF

549

2

1

R8583

MF-LF

1%

1/16W

402

1.33K

2

1

R8584

SSM6N15FEAPE

SOT563

4

5

3

Q8550

73 75 95 73 75 95

OMIT

CRITICAL

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFH

A4

H4

P2

P11

D11

D2

V4

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

J3

L9

K11

H11

K9

U8550

K4J10324QD-HC11

32MX32-900MHZ-MFH

OMIT

CRITICAL

BGA

A4

H4

P2

P11

D11

D2

V4

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

J3

L9

K11

H11

K9

U8500

K4J10324QD-HC11

32MX32-900MHZ-MFH

BGA

CRITICAL

OMIT

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8500

BGA

32MX32-900MHZ-MFH

K4J10324QD-HC11

CRITICAL

OMIT

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8550

75 97

A.0.0

051-7892

SYNC_MASTER=MUXGFX

SYNC_DATE=07/10/2008

GDDR3 Frame Buffer B (Top)

FB_B2_VREF_UNTERM_L

FB_B_UMA<2>

FB_B_CLK_P<1>

FB_B_DQ<63> FB_B_DQ<59>

FB_B_DQ<57>

FB_B_DQ<36>

FB_B_DQ<32>

FB_B_MA<11>

FB_B_MA<6>

PP1V8_S0GPU_ISNS

FB_B_BA<1>

FB_B_MA<0> FB_B_MA<1>

FB_B_MA<10>

FB_B_MA<9>

FB_B_WDQS<5>

FB_B_WDQS<7>

FB_B_BA<2>

FB_B_WDQS<4>

FB_B_RAS_L

FB_B1_ZQ

FB_B1_SEN

FB_B_RDQS<6> FB_B_RDQS<5> FB_B_RDQS<4> FB_B_RDQS<7>

FB_B_WDQS<6>

FB_B_BA<1>

FB_B_DQ<51>

FB_B_DQM_L<5>

FB_B_DQM_L<7>

FB_B_DQ<49> FB_B_DQ<50>

FB_B_DQM_L<6>

FB_B_BA<0>

FB_B_WE_L FB_B_CAS_L

FB_B_CS0_L

FB_B_MA<10>

FB_B_UMA<5>

FB_B0_VREF_UNTERM_L

FB_B0_VREF FB_B1_VREF

FB_B3_VREFFB_B2_VREF

FB_B3_VREF_UNTERM_L

FB_VREF_UNTERM

FB_B_CLK1_TERM

VOLTAGE=0.9V

FB_B1_VREF_UNTERM_L

VOLTAGE=0.9V

FB_B_CLK0_TERM

PP1V8_S0GPU_ISNS

FB_B_DQ<48>

FB_B_DQM_L<4>

PP1V8_S0GPU_ISNS

GPU_FB_B_VREF_DIV

PP1V8_S0GPU_ISNS

GPU_FB_B_VREF_DIV

FB_VREF_UNTERM

FB_B_DQM_L<0>

FB_B_MA<8>

FB_B_LMA<2>

FB_B_MA<7>

FB_B_MA<6>

FB_B_MA<9>

FB_B_LMA<4> FB_B_LMA<5>

FB_B_DQ<7>

FB_B_LMA<3>

FB_B_DQ<1>FB_B_CAS_L

FB_B_MA<11>

FB_B_CLK_N<0>

FB_B_DQM_L<1>

FB_B_DQ<19>

FB_B_DQ<16>

FB_B_DQ<21>

FB_B_DQ<6>

FB_B_DQ<10>

FB_B_DQ<8>

FB_B_DQ<12>

FB_B_DQM_L<2> FB_B_DQM_L<3>

FB_B_DQ<9>

FB_B_DQ<5>

FB_B_RDQS<0>

FB_B_DRAM_RST

FB_B_RDQS<2>

FB_B0_MF

FB_B_DQ<2>

FB_B_DQ<0>

FB_B_DQ<4>

FB_B_DQ<3>

FB_B_DQ<14>

FB_B_DQ<13>

FB_B_DQ<11>

FB_B_DQ<15>

FB_B_DQ<17>

FB_B_DQ<23>

FB_B_DQ<18>

FB_B_DQ<20> FB_B_DQ<22>

FB_B_DQ<24>

FB_B_DQ<29> FB_B_DQ<30>

FB_B_DQ<25>

FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<31> FB_B_DQ<28>

FB_B_BA<2>

FB_B_BA<0>

FB_B_WDQS<3>

FB_B_WDQS<2>

FB_B_WDQS<1>

FB_B0_ZQ

FB_B0_SEN

FB_B_WDQS<0>

FB_B_RDQS<3>

FB_B_RDQS<1>

FB_B_RAS_L

FB_B_CKE FB_B_MA<12>

FB_B_CLK_P<0>

FB_B_CS0_L FB_B_WE_L

FB_B_CKE FB_B_MA<12>

FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<33>

FB_B_DQ<46>

FB_B_DQ<43>

FB_B_DQ<45>

FB_B_DQ<44>

FB_B_DQ<47>

FB_B_DQ<42>

FB_B_DQ<41>

FB_B_DQ<52>

FB_B_DQ<53> FB_B_DQ<55> FB_B_DQ<54>

FB_B_DQ<40>

FB_B_MA<7>

FB_B1_MF

FB_B_MA<0>

FB_B_UMA<4>

FB_B_MA<1>

FB_B_UMA<3>

FB_B_CLK_N<1>

FB_B_MA<8>

FB_B_DQ<37> FB_B_DQ<38> FB_B_DQ<39>

FB_B_DQ<56>

FB_B_DQ<60>

FB_B_DQ<61>

FB_B_DQ<62>

FB_B_DQ<58>

FB_B_DRAM_RST

8 9

47 72 73 74 75

8 9

47 72 73 74

75

8 9

47 72 73 74

75

9

27 75

8 9

47 72 73 74 75

9

27 75

HDA_BCLK

HDA_SYNC

HDA_SDO

HDA_RST*

SPDIF

BUFRST*

JTAG_TMS

MIOA_CLKIN

MIOA_CLKOUT

JTAG_TCK

GPIO20

GPIO23

HDA_SDI

MIOA_D8

MIOA_D10

MIOA_D9

JTAG_TDI

GPIO2

GPIO11

GPIO7

GPIO5

GPIO4

GPIO3

GPIO1

GPIO0

MIOB_VDDQ_4

MIOB_VDDQ_2

GPIO21

GPIO18

GPIO15 GPIO16 GPIO17

GPIO9

GPIO10

GPIO12 GPIO13 GPIO14

GPIO19

JTAG_TDO

JTAG_TRST*

MIOA_CTL3

MIOA_D7

MIOA_D6

MIOA_D5

MIOA_D4

MIOA_D3

MIOA_D2

MIOA_D1

MIOA_DE

MIOB_CAL_PD_VDDQ

GPIO6

GPIO8

MIOA_D11 MIOA_D12 MIOA_D13

MIOB_D9

MIOB_D8

MIOB_D7

MIOB_D5 MIOB_D6

MIOB_D3

MIOB_D0

MIOB_DE

MIOB_CLKOUT*

MIOB_CTL3

MIOB_CLKOUT

MIOB_CLKIN

MIOB_D11 MIOB_D12 MIOB_D13 MIOB_D14

MIOB_D16 MIOB_D17

MIOB_D15

MIOB_HSYNC MIOB_VSYNC

THERMDP THERMDN

PGOOD_OUT*

XTAL_IN XTAL_OUT

XTAL_OUTBUFF

MIOB_D10

MIOB_D4

MIOB_D2

MIOB_D1

MIOA_VSYNC

MIOA_HSYNC

MIOA_D14

MIOA_CLKOUT*

MIOA_D0

MIOB_CAL_PU_GND

MIOB_VDDQ_3

MIOA_VDDQ_3 MIOA_VDDQ_4

MIOA_VDDQ_2

GPIO22

RFU1

ROM_CS* ROM_SCLK

ROM_SO

STRAP_REF_3V3 STRAP_REF_MIOB

VDD33_5

VDD33_1 VDD33_2 VDD33_3 VDD33_4

RFU1_GND

RFU0

RFU0_GND

ROM_SI

MIOA_VDDQ_1

MIOB_VDDQ_1

MIOA_CAL_PU_GND

MIOA_CAL_PD_VDDQ

MIOA_VREF MIOB_VREF

TESTMODE

SP_PLLVDD

PLLVDD

VID_PLLVDD

XTAL_SSIN

SYMBOL 6 OF 9

BI BI

BI

BI BI

OUT OUT OUT OUT OUT

OUT

IN IN

IN

OUT

IN

OUT

IN

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

110mA

- =PP3V3_GPI_MIO

(IPD)

(NONE)

BOM options provided by this page:

(NONE)

- =PP1V2_GPU_H_PLLVDD

- =PP3V3_GPU_VDD33

Page Notes

Power aliases required by this page:

- =PP1V2_GPU_PLLVDD

- =PP1V2_GPU_VID_PLLVDD

Signal aliases required by this page:

Typically <??mA

65mA

25mA

50mA

40.2K

1% 1/16W MF-LF 402

2

1

R8697

0.47UF

6.3V CERM-X5R

10%

402

2

1

C8601

6.3V

402

CERM-X5R

10%

0.47UF

2

1

C8602

10%

X5R

16V

402

0.1uF

2

1

C8636

CERM

4.7UF

603

6.3V

20%

2

1

C8635

0402

FERR-220-OHM

21

L8635

FERR-220-OHM

0402

21

L8640

0.1uF

10%

402

X5R

16V

2

1

C8617

402

5%

10K

1/16W MF-LF

2

1

R8616

5%

10K

402

1/16W MF-LF

2

1

R8617

1/16W

402

1%

49.9

MF-LF

2

1

R8620

1/16W

49.9

1%

402

MF-LF

2

1

R8622

49.9

1% 1/16W MF-LF 402

2

1

R8621

0.1uF

10%

402

X5R

16V

2

1

C8619

10K

5%

MF-LF 402

1/16W

2

1

R8618

5%

10K

1/16W MF-LF 402

2

1

R8619

CERM

10%

1UF

402

6.3V 2

1

C8611

402

6.3V

1UF

10%

CERM

2

1

C8610

1/16W

49.9

1%

MF-LF 402

2

1

R8623

10%

X5R 402

16V

0.1uF

2

1

C8631

4.7UF

603

CERM

6.3V

20%

2

1

C8630

FERR-220-OHM

0402

21

L8630

4.7UF

603

CERM

6.3V

20%

2

1

C8633

0.1uF

10%

X5R

16V

402

2

1

C8641

CERM

603

6.3V

20%

4.7UF

2

1

C8640

603

20%

6.3V CERM

4.7UF

2

1

C8643

6.3V CERM

603

4.7UF

20%

2

1

C8637

CERM-X5R

0.47UF

6.3V

10%

402

2

1

C8600

BGA

OMIT

NB9P-GS

D2

D1

B2

B1

AD9

J13

J12

J11

J10

J9

B5 B4

AP35

M9

N9

A5

AF9

C4

D3

D4

C3

K9

J26

AK14

J25

AE9

C5

W2

AF1

Y9

W9

AB9

AA9

W1

Y5

AC3

AC2

AC1

AC4

AB1

AB2

AB3

Y3

V7

W7

W5

Y6

W6

U6

AE2

AE3

Y2

Y1

W3

W4

V4

AE1

AA6

AA7

L3

N5

U9

T9

R9

P9

N3

N2

U1

U4

T1

T2

T3

P3

P2

P1

N6

T6

R6

U3

U2

P4

N1

P5

T4

R4

N4

T5

U5

AP16

AR14

AN16

AN14

AP14

A7

B7

C7

D6

D7

J7

H6

H5

H4

H1

H2

H3

M6

L6

K6

L5

K3

L7

M4

L4

L2

L1

J6

J4

H7

K5

K4

K2

K1

A4

U8000

40.2K

1% 1/16W MF-LF 402

2

1

R8696

5%

10K

402

MF-LF

1/16W

2

1

R8660

16V CERM-X5R 402

0.022UF

10%

2

1

C8691

402

0.022UF

10% 16V CERM-X5R

2

1

C8693

402

20% 10V CERM

0.1UF

2

1

C8695

402

16V

10% CERM-X5R

0.022UF

2

1

C8690

402

16V

10% CERM-X5R

0.022UF

2

1

C8692

0.1UF

20% 10V

402

CERM

2

1

C8694

402

CERM-X5R

6.3V

10%

0.47UF

2

1

C8697

402

CERM-X5R

6.3V

10%

0.47UF

2

1

C8696

10%

6.3V

1UF

CERM 402

2

1

C8698

77

77 81

77

77 79

73 74 75 77

77

77 83

77

77 84

77

6

13 21

6

13 21

77

48 77 96

77

77 95

A.0.0

051-7892

97

SYNC_DATE=07/10/2008

76

NV G96 GPIO/MIO/Misc

SYNC_MASTER=MUXGFX

GPU_MIOB_VREF

GPU_MIOA_PU_GND

PP1V1_S0GPU_REG

GPU_MIOB_PU_GND

GPU_MIOA_PD_VDDQ GPU_MIOB_PD_VDDQ

PP1V1_S0GPU_REG

PP3V3_S0GPU

GPU_MIOA_VREF

DP_EG_HPD

NC_GPU_GPIO_0

GPU_VCORE_VID0

FB_VREF_UNTERM

SMC_GFX_THROTTLE_R_L

SMC_GFX_OVERTEMP_R_L

GPIO7_FBVDD_ALTVO

GPU_GPIO_6

TP_GPU_GSTATE<0>

EG_BKLT_EN

EG_LCD_PWR_EN

TP_LVDS_EG_BKL_PWM

GPU_GPIO_16

NC_GPU_MIOA_CLKOUT_P

NC_GPU_MIOA_VSYNC

NC_GPU_MIOA_HSYNC

NC_GPU_MIOA_D<14>

NC_GPU_MIOA_D<13>

NC_GPU_MIOA_D<12>

NC_GPU_MIOA_D<11>

NC_GPU_MIOA_D<10>

TP_GPU_MIOA_D<8>

TP_GPU_MIOA_D<5>

TP_GPU_MIOA_D<4>

NC_GPU_MIOA_CLKOUT_N

TP_GPU_MIOA_D<6>

TP_GPU_MIOA_D<3>

TP_GPU_MIOA_D<2>

TP_GPU_MIOA_D<0>

TP_GPU_MIOA_DE

NC_GPU_MIOB_CLKOUT_P

NC_GPU_MIOB_D<9>

NC_GPU_MIOB_D<8>

NC_GPU_MIOB_D<7>

NC_GPU_MIOB_D<6>

NC_GPU_MIOB_D<5>

NC_GPU_MIOB_D<4>

NC_GPU_MIOB_D<3>

NC_GPU_MIOB_D<2>

NC_GPU_MIOB_D<1>

NC_GPU_MIOB_D<0>

NC_GPU_MIOB_DE

NC_GPU_MIOB_CTL3

NC_GPU_MIOB_CLKOUT_N

NC_CPU_HDA_SYNC

NC_CPU_HDA_RST_L

TP_GPU_BUFRST_L

NC_CPU_HDA_SD0

NC_CPU_HDA_SDI

NC_GPU_GPIO_17

JTAG_MCP_TCK GPU_JTAG_TDI

NC_GPU_MIOA_CLKIN

NC_GPU_MIOB_CLKIN

GPU_STRAP<2>

GPU_STRAP<0>

NC_GPU_MIOB_D<12>

NC_GPU_MIOB_D<11>

GPU_TESTMODE_PD

GPU_MIOA_PD_VDDQ GPU_MIOA_PU_GND

GPU_MIOB_PD_VDDQ GPU_MIOB_PU_GND

NC_GPU_MIOB_D<13>

NC_GPU_MIOB_D<10>

TP_GPU_MIOA_D<7>

TP_GPU_MIOA_D<9>

TP_GPU_MIOA_D<1>

NC_GPU_MIOA_CTL3

TP_GPU_JTAG_TDO

NC_GPU_GPIO_18

NC_GPU_GPIO_15

TP_GPU_VCORE_VID3

GPU_VCORE_VID2

GPU_VCORE_VID1

NC_GPU_SPDIF

NC_CPU_HDA_BCLK

NC_GPU_GPIO_23

NC_GPU_GPIO_22

NC_GPU_GPIO_21

NC_GPU_GPIO_20

NC_GPU_GPIO_19

TP_GPU_PGOOD_OUT_L

GPU_TDIODE_N

GPU_TDIODE_P

GPU_STRAP<1>

NC_GPU_MIOB_D<14>

NC_GPU_MIOB_HSYNC NC_GPU_MIOB_VSYNC

PP3V3_S0GPU

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

PP1V1_GPU_H_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm

PP1V1_GPU_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.2V

PP1V1_GPU_VID_PLLVDD_F

GPU_XTALOUT

GPU_CLK27M_SS

GPU_XTALOUTBUFF

GPU_CLK27M

PP3V3_S0GPU

GPU_STRAP_REF_MIOB_PD

GPU_STRAP_REF_3V3_PD

GPU_ROM_SO

GPU_ROM_SI

GPU_ROM_SCLK

NC_GPU_ROM_CS_L

PP3V3_S0GPU

JTAG_MCP_TRST_L

GPU_JTAG_TMS

76

8

71 73 76 78 83

8

71 73 76 78 83

76

8

71 73 76 78 83

6 8

69 70 76 77 79 81

76

6 8

69 70 76

77 79 81

6 8

69 70 76 77 79 81

77

6 8

69 70 76 77 79 81

OUT

IN

NC

D

GS

IN

BI

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(I2CS requires pullups even if not used)

I2CS ties into SMBus connection page

RAMCFG[0]

TVMODE[1]

G96 HDCP ROM APN is 341S2272, blank device is 335S0574.

GPU 27MHz Crystal

D 1101 PU 30k

4 0100 PD 25k 5 0101 PD 30k

7 0111 PD 45k

THERM

Native Func

ROM_SCLK ROM_SI STRAP 2 STRAP 1 STRAP 0

6 0110 PD 35k

Config Straps

RAMCFG[3]

F 1111 PU 45k

RAMCFG[2]

B 1011 PU 20k

XCLK_277

GP

HPDE

GP

Unused Clocks

Unused signals

DVI_MODE0

G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.

GPIOs

HPDF

Isolation FETs for DP MUX inputs

PWR_CTL1

HDMI_DETECT1

HDMI_DETECT0

PEX_PLLEN_TERM100

PCI_DEVID[0] 3GIO_PADCFG[0] USER[0]

TVMODE[0]

Strapping Bit 0

PCI_DEVID[1]

SLOT_CLK_CFG

Strapping Bit 1

USER[1]

ROM_SO

HPDC

Renamed signals

Unused I2C Buses

PWR_CTL0

AC_DET

FAN_PWM

VID1

RAMCFG[1]

Native Func

E 1110 PU 35k

C 1100 PU 25k

8 1000 PU 5k

USER[2]

3GIO_PADCFG[2]

PCI_DEVID[4]

SLI_SYNC

MEM_VREF

GPIOs

PCI_DEVID[2]

Strap S1/S2 Bit[3:0] PU/PD Rval

3GIO_PADCFG[1]

TVMODE[2]

Strapping Bit 3

VID0

SUB_VENDOR

SWAPRDY_A

HPDD

DVI_MODE1

VID2/MEM_VID

LCD0_BL_EN

LCD0_VDD

LCD0_BL_PWM

3 0011 PD 20k

2 0010 PD 15k

1 0001 PD 10k

0 0000 PD 5k

3GIO_PADCFG[3]

PCI_DEVID[3]

Strapping Bit 2

A 1010 PU 15k

9 1001 PU 10k

USER[3]

Strapping Pin

Physical

Strap S1/S2 Bit[3:0] PU/PD Rval

1/16W MF-LF

GPU_SS_INT

10K

5%

402

2

1

R8781

MF-LF

1/16W

5%

402

10K

2

1

R8780

76 77 79

76 77

76 77 95

5%

402

1/16W MF-LF

0

21

R8783

50V 402

CERM

5%

12pF

21

C8780

CERM

402

5%

12pF

50V

21

C8781

27MHZ

SM-2

CRITICAL

31

42

Y8780

NO STUFF

MF-LF

1/16W

402

5%

10M

2

1

R8782

1%

1/16W

45.3K

OMIT

402

MF-LF

2

1

R8708

1/16W

2.0K

5%

402

MF-LF

2

1

R8710

15.0K

MF-LF

1/16W

1%

402

2

1

R8712

402

1/16W

2.0K

NO STUFF

MF-LF

5%

2

1

R8702

OMIT

MF-LF

402

5%

2.0K

1/16W

2

1

R8707

NO STUFF

1/16W

402

1%

MF-LF

4.99K

2

1

R8709

4.99K

NO STUFF

1% 1/16W MF-LF

402

2

1

R8711

MF-LF

10K

402

1%

1/16W

2

1

R8704

45.3K

1/16W

1%

MF-LF

402

2

1

R8706

402

1%

MF-LF

45.3K

1/16W

2

1

R8701

402

NO STUFF

10K

1%

MF-LF

1/16W

2

1

R8703

MF-LF

402

1/16W

10K

1%

NO STUFF

2

1

R8705

DP_CA_DET_EG_FET

SOD-VESM-HF

SSM3K15FV

2

1

3

Q8742

DP_CA_DET_EG_FET

100K

1% 1/16W MF-LF

402

2

1

R8742

18 81 82 84

76 77 81

MF-LF

5%

402

4.7K

1/16W

2

1

R8750

1/16W

5%

4.7K

MF-LF

402

2

1

R8751

1/16W

5%

4.7K

402

MF-LF

2

1

R8752

1/16W

5%

4.7K

MF-LF

402

2

1

R8753

77 78 81

9

18 81

77 78 81

9

18 81

76

DP_CA_DET_EG_PLD

402

0

MF-LF

1/16W

5%

21

R8743

84

MF-LF

4025%01/16W

21

R8798

MF-LF

4025%01/16W

21

R8799

42

76 77 79

402

MF-LF

1/16W

2.2K

5%

2

1

R8797

402

MF-LF

1/16W

2.2K

5%

2

1

R8796

76 77 84

76 77 83

73 74 75 76 77

10K

MF-LF

402

1/16W

5%

2

1

R8792

10K

1/16W

5%

MF-LF

402

2

1

R8793

1/16W

10K

402

MF-LF

5%

2

1

R8794

402

NO STUFF

1/16W MF-LF

5%

10K

2

1

R8795

114S0368

RES,MTL FILM,1/16W,35.7K,1,0402,SMD,LF

VRAM_512_HYNIX

R8708

1

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

114S0378

R8708

1

VRAM_512_SAMSUNG

R8708

VRAM_256_SAMSUNG

114S0343

1

RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF

VRAM_1024_SAMSUNG

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

R8707

1

114S0378

114S0361

R8707

VRAM_1024_QIMONDA

1

RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF

VRAM_512_QIMONDA

114S0361

1

R8708

RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF

G96 GPIOs & Straps

SYNC_MASTER=MUXGFX

A.0.0

051-7892

SYNC_DATE=07/09/2008

9777

R8708

114S0331

RES,MTL FILM,1/16W,15.0K,1,0402,SMD,LF

1

VRAM_256_HYNIX

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

TP_GPU_VCORE_VID3

MAKE_BASE=TRUE

PP3V3_S0GPU

GPU_VCORE_VID2

GPU_VCORE_VID1

EG_LCD_PWR_EN

GPU_GPIO_6

SMC_GFX_OVERTEMP_R_L

GPIO7_FBVDD_ALTVO

FB_VREF_UNTERM

GPIO7_FBVDD_ALTVO

EG_BKLT_EN

EG_LCD_PWR_EN

NC_GPU_GPIO_15

DP_EG_HPD

SMC_GFX_THROTTLE_R_L

DP_IG_DDC_DATA

FB_VREF_UNTERM

MAKE_BASE=TRUE

GPU_VCORE_VID0

GPU_XTALOUT

SMC_GFX_THROTTLE_R_L

SMC_GFX_OVERTEMP_R_L

SMC_GFX_THROTTLE_L

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

NC_GPU_GPIO_0

MAKE_BASE=TRUE

DP_EG_HPD

TP_LVDS_EG_BKL_PWM

MAKE_BASE=TRUE

EG_LCD_PWR_EN

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

MAKE_BASE=TRUE

TP_LVDS_EG_BKL_PWM

GPU_ROM_SCLK

GPU_ROM_SO

GPU_GPIO_16

NC_GPU_GPIO_17

NC_GPU_GPIO_18

MAKE_BASE=TRUE

NC_GPU_GPIO_19

PP3V3_S0GPU

NC_GPU_GPIO_22

MAKE_BASE=TRUE

FB_VREF_UNTERM

DP_IG_DDC_CLK

PP3V3_S0

MAKE_BASE=TRUE

GPIO7_FBVDD_ALTVO

SMC_GFX_OVERTEMP_L

TP_GPU_VCORE_VID3

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

NC_GPU_GPIO_23

MAKE_BASE=TRUE

TP_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CLKIN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CC_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CC_SCL NC_GPU_I2CC_SCL

DP_EG_DDC_DATA

LVDS_EG_DDC_DATA

LVDS_EG_DDC_CLK

GPU_TDIODE_P

GPU_XTALOUT

GPU_CLK27M

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_HDA_SYNC

NO_TEST=TRUE

NC_CPU_HDA_SD0

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_HDA_SDI

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBA_CMD28

NC_FBB_MA<13>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBC_CMD28

NC_FBA_CMD29

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_LVDS_EG_B_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_EG_B_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_P<3>

NC_GPU_GPIO_23

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_22

NC_GPU_GPIO_20

EG_DP_CA_DET

DP_CA_DET_EG

DP_CA_DET

GPU_STRAP<0>

NC_GPU_GPIO_19

EG_DP_CA_DET

MAKE_BASE=TRUE

NC_GPU_GPIO_15

GPU_ROM_SI

MAKE_BASE=TRUE

NC_GPU_GPIO_21

MAKE_BASE=TRUE

NC_GPU_GPIO_18

MAKE_BASE=TRUE

NC_GPU_GPIO_17

NC_GPU_GPIO_20

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_D<14..10>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_N<3>

TP_LVDS_EG_B_CLK_P

MAKE_BASE=TRUE

NC_FBC_CMD29

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_EG_DDC_DATA

NC_GPU_I2CD_SCL

NC_GPU_I2CE_SCL

NC_GPU_I2CE_SDA

NC_FB_B_CS1_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FB_A_CS1_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_CS_L

NO_TEST=TRUE

NC_FBC_CMD30

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_EG_DDC_CLK

MAKE_BASE=TRUE

DP_EG_DDC_CLK

GPU_CLK27M

NC_GPU_I2CC_SDA

NC_LVDS_EG_B_DATA_N<3>

NC_LVDS_EG_B_DATA_P<3>

TP_LVDS_EG_B_CLK_P

TP_LVDS_EG_B_CLK_N

NC_FBA_MA<13>

NC_FBB_MA<13>

NC_FBC_CMD30

NC_GPU_ROM_CS_L

NC_LVDS_EG_A_DATA_P<3>

NC_FBA_CMD29

NC_FBC_CMD29

NC_FBA_CMD30

NC_GPU_I2CD_SDA

NC_LVDS_EG_A_DATA_N<3>

NC_FB_B_CS1_L

NC_FB_A_CS1_L

GPU_CLK27M_SS

MAKE_BASE=TRUE

LVDS_EG_DDC_CLK

NC_CPU_HDA_SDI

NO_TEST=TRUE

NC_GPU_SPDIF

MAKE_BASE=TRUE

NC_GPU_SPDIF

MAKE_BASE=TRUE

NC_FBA_CMD30

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_HDA_RST_L

NO_TEST=TRUE

NC_CPU_HDA_RST_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_HDA_BCLK

NC_CPU_HDA_SYNC

NC_CPU_HDA_SD0

NC_FBC_CMD28

NC_FBA_CMD28

NC_FBA_MA<13>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_VSYNC

NC_GPU_MIOA_HSYNC

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CTL3 NC_GPU_MIOA_CTL3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CLKOUT_N NC_GPU_MIOA_CLKOUT_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_CLKOUT_P NC_GPU_MIOA_CLKOUT_P

NC_GPU_MIOA_CLKIN

GPU_MIOA_D<14..10>

GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

GPU_CLK27M_SS

MAKE_BASE=TRUE

GPU_CLK27M

MAKE_BASE=TRUE

GPU_XTALOUT

MAKE_BASE=TRUE

GPU_TDIODE_P

MAKE_BASE=TRUE

GPU_TDIODE_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CD_SDA

NC_GPU_MIOB_CLKIN

NC_GPU_MIOB_CTL3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_DE NC_GPU_MIOB_DE

NC_GPU_MIOB_CLKOUT_N

NC_GPU_MIOB_CLKOUT_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_HSYNC NC_GPU_MIOB_HSYNC

NC_GPU_MIOB_VSYNC

GPU_MIOB_D<14..0>

GPU_CLK27M_SS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKOUT_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_D<14..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKOUT_P

GPU_TDIODE_N

MAKE_BASE=TRUE

LVDS_EG_DDC_DATA

GPU_CLK27M_XTALOUT_R

GPU_XTALOUTBUFF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_VSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_CTL3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CD_SCL

PP3V3_S0GPU

DP_EG_DDC_CLK

DP_EG_DDC_DATA

PP3V3_S0GPU

GPU_STRAP<2>

GPU_STRAP<1>

NC_GPU_GPIO_21

GPU_VCORE_VID0

TP_GPU_GSTATE<0>

EG_BKLT_EN

NC_GPU_GPIO_0

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CH_SDA

NC_GPU_I2CH_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CE_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CE_SCL

NC_GPU_I2CH_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CH_SCL

76 77

6 8

69 70 76 77 79 81

76 77

79

76 77

79

76 77

84

76

76 77

83

76 77

81

76 77

73 74

75

76

77

76 77

76 77 84

76 77

76

76 77

6 8

69 70 76 77 79 81

76 77

73 74 75 76 77

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 80 81 82

84 85 96

76 77 83

76 77

76

76 77

77 78

77 78 77 78

77 78 81

48 76 77 96

76 77

76 77 95

76 77

73 77

77 78

76 77

77

76 77

77

76 77

76

77 78

73 77

77 78 81

77 78

73 77

76 77

73 77

77 78 81

77 78

73 77

76 77

77 78

73 77

77 78

73 77

76 77 95

77 78 81

76 77

73 77

76 77 76 77

76 77

73 77

76 77

76 77 76 77

76 77

76 77 95

76 77

48 76 77 96

77 78

76 77

76 77 76 77

76 77

76 77 95

76

76 77

48 76 77 96

77 78 81

76

76 77

77 78

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

6 8

69 70 76 77 79 81

76 77

79

76 77

84

76 77

77 78

OUT OUT

OUT

OUT OUT OUT

IFPB_TXC*

I2CD_SDA

I2CB_SCL

I2CS_SDA

I2CS_SCL

I2CC_SCL I2CC_SDA

IFPEF_RSET

I2CA_SDA

DACB_RSET

DACC_VSYNC

DACC_HSYNC

DACC_BLUE

DACC_GREEN

DACC_RED

DACB_CSYNC

DACB_BLUE

DACB_GREEN

DACB_RED

DACA_VSYNC

DACA_RED

IFPF_L0*

IFPF_L0

IFPF_AUX*

IFPF_AUX

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_AUX

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L0*

IFPD_AUX*

IFPC_L3*

IFPC_L2*

IFPC_L0*

IFPC_AUX*

IFPB_TXD7*

IFPB_TXD7

IFPB_TXD6*

IFPB_TXD5

IFPB_TXD4*

IFPA_TXD2*

IFPA_TXD2

DACC_VREF DACC_RSET

DACC_VDD

DACB_VDD

DACA_VDD

DACA_VREF DACA_RSET

DACA_HSYNC

DACA_GREEN

DACA_BLUE

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L3

IFPF_L2*

IFPF_L3*

IFPE_AUX*

IFPD_L0

IFPD_L1

IFPD_L1*

IFPC_L3

IFPC_L2

IFPC_L1

IFPC_L0

IFPB_TXD6

IFPB_TXD4

IFPB_TXC

IFPA_TXD3*

IFPA_TXD3

IFPA_TXD1

IFPA_TXD1*

IFPA_TXD0

IFPA_TXD0*

IFPA_TXC*

IFPA_TXC

I2CA_SCL

IFPCD_RSET

IFPC_AUX

I2CE_SDA

I2CE_SCL

I2CD_SCL

I2CB_SDA

I2CH_SCL

IFPC_L1*

I2CH_SDA

IFPD_AUX

IFPB_TXD5*

IFPEF_PLLVDD

IFPAB_PLLVDD IFPAB_RSET

IFPF_IOVDD

IFPE_IOVDD

IFPD_IOVDD

IFPC_IOVDD

IFPB_IOVDD

IFPA_IOVDD

DACB_VREF

IFPCD_PLLVDD

SYMBOL 5 OF 9

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

NC NC

NC NC NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC

NC NC NC

NC NC

NC NC NC

NC

NC NC NC

NC NCNC

NC

BI BI

OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

?mA peak for all pairs

80mA peak

Place at AJ8

160mA peak

(NONE)

?mA peak per diff pair

?mA peak for all pairs

?mA peak per diff pair

Place at AG9

I2CS addr fixed at 0x9E,0x9F

Place at AK8

- =PP1V8_GPU_IFPX

(NONE)

I2CS addr fixed at 0x9E,0x9F

Power inputs must be pulled down if not used

Sum of peak currents: 240mA

I2CS must be pulled up if not used.

I2CS must be pulled up if not used

Place at AG10

BOM options provided by this page:

Signal aliases required by this page:

- =PP3V3_GPU_IFPCD_IOVDD

Power aliases required by this page:

Page Notes

402

1%

1K

1/16W MF-LF

2

1

R8850

0402

FERR-220-OHM

21

L8805

402

10V

CERM

0.1UF

20%

2

1

C8806

FERR-220-OHM

0402

21

L8815

77

84 95

603

6.3V CERM

20%

4.7UF

2

1

C8805

5%

10K

MF-LF

1/16W 402

2

1

R8852

5%

10K

1/16W 402

MF-LF

2

1

R8853

5%

10K

1/16W MF-LF 402

2

1

R8854

6.3V

4.7UF

CERM

603

20%

2

1

C8815

CERM

402

10V

0.1UF

20%

2

1

C8801

603

6.3V CERM

20%

4.7UF

2

1

C8800

0402

FERR-220-OHM

21

L8800

402

CERM

10V

20%

0.1UF

2

1

C8803

402

0.1UF

CERM

10V

20%

2

1

C8813

20% 10V

402

CERM

0.1UF

2

1

C8811

4.7UF

20%

CERM

603

6.3V 2

1

C8810

0402

FERR-220-OHM

21

L8810

20% 10V

402

CERM

0.1UF

2

1

C8816

BGA

NB9P-GS

OMIT

AH3

AH2

AH1

AJ1

AJ2

AJ3

AL3

AL2

AD7

AF2

AF3

AL1

AJ6

AE5

AE6

AF5

AF4

AG4

AH4

AH5

AH6

AE7

AD4

AE4

AR4

AR5

AP5

AN5

AN7

AP7

AR7

AR8

AK8

AN4

AP4

AK7

AJ9

AR2

AP1

AM4

AM3

AM5

AL5

AM6

AM7

AJ8

AN3

AP2

AP11

AN11

AR10

AR11

AN10

AP10

AP8

AN8

AN13

AP13

AG10

AJ11

AK9

AL11

AK11

AL10

AK10

AM9

AM10

AL8

AM8

AM12

AM11

AG9

E1

E2

G6

F6

E5

D5

G5

F4

E4

E3

G2

G3

G4

G1

AM2

AK6

AG7

AH7

AK4

AM1

AL4 AJ4

AC5

AC6

AB6

AA4 AB4

AB5

Y4

AL13

AK12

AJ12

AK13

AM15

AM13

AM14 AL14

U8000

402

1K

1% 1/16W MF-LF

2

1

R8855

81 95

1/16W MF-LF

10K

5%

402

2

1

R8857

402

1/16W

10K

MF-LF

5%

2

1

R8856

77

77 81

77

77 81

42 45 48 53 94

77

1K

NO STUFF

MF-LF 402

1/16W

5%

2

1

R8860

1/16W MF-LF 402

5%

1K

2

1

R8861

402

1%

1K

MF-LF

1/16W

2

1

R8851

SYNC_DATE=07/10/2008

78 97

051-7892

A.0.0

SYNC_MASTER=MUXGFX

NV G96 Video Interfaces

GPU_DACA_VDD

GPU_IFPEF_RSET

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V8_GPU_IFPAB_IOVDD_F

PP1V8_GPU_IFPEF_PLLVDD_F

NC_GPU_I2CC_SCL

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_IFPAB_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm

PP1V1_GPU_IFPEF_IOVDD_F

GPU_DACB_VDD

PP1V8_GPUIFPX

DP_EG_AUX_CH_P DP_EG_AUX_CH_N

LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2> NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>

DP_EG_ML_N<2> DP_EG_ML_P<3>

DP_EG_ML_N<1>

DP_EG_ML_P<1>

GPU_IFPAB_RSET

GPU_IFPCD_RSET

PP1V8_GPU_IFPEF_PLLVDD_F

LVDS_EG_A_CLK_P

LVDS_EG_A_DATA_N<2>

DP_EG_ML_P<2>

PP1V1_S0GPU_REG

PP1V8_GPU_IFPCD_PLLVDD_F GPU_IFPCD_RSET

GPU_IFPEF_RSET

GPU_IFPAB_RSET

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0>

NC_LVDS_EG_A_DATA_N<3>

NC_LVDS_EG_A_DATA_P<3>

LVDS_EG_A_DATA_P<2>

TP_LVDS_EG_B_CLK_P

PP1V8_GPU_IFPCD_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

SMBUS_SMC_0_S0_SDA

NC_GPU_I2CC_SDA

NC_GPU_I2CH_SDA

DP_EG_DDC_DATA

DP_EG_DDC_CLK

NC_GPU_I2CD_SDA

NC_GPU_I2CD_SCL

NC_GPU_I2CE_SDA

NC_GPU_I2CE_SCL

PP1V1_GPU_IFPCD_IOVDD_F

LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_P<0>

DP_EG_ML_N<0>

DP_EG_ML_P<0>

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_P<1>

PP1V1_GPU_IFPEF_IOVDD_F

DP_EG_ML_N<3>

GPU_DACC_VDD

MIN_LINE_WIDTH=0.4 mm

PP1V1_GPU_IFPCD_IOVDD_F

VOLTAGE=1.1V

MIN_NECK_WIDTH=0.1 mm

LVDS_EG_B_DATA_N<0>

TP_LVDS_EG_B_CLK_N

LVDS_EG_DDC_DATA

NC_GPU_I2CH_SCL

SMBUS_SMC_0_S0_SCL

LVDS_EG_DDC_CLK

78

8

70

78

8

71 73 76 83

78

PVCC

THRM_PAD

FDE

PGOOD

AF_EN

VR_ON

IMON

VID4

VID3

VID2

VID1

VID0

LGATE

PGND

PHASE

UGATE

BOOT

VSS

VIN

ISP

VO

ISN

ICOMP

RTN

VSEN

VDIFF

FB

COMP

VW

OCSET

SOFT

VDD

RBIAS

OUT

G

D

S

G

D

S

IN

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

K19

K19 Default Vcore Setpoints

K19

0

0.92700V

Other VID states may not be valid

Max perfBalanced

GPU VCore Setpoints

Max Batt

Voltage

VID0VID1VID2VID3

-

0.90125V

1.00425V

1

1 0

1

1 1

30A max output (L8920 limit)

(GFXIMVP6_AGND)

GPU VCore Regulator

(PPVCORE_GPU_REG)

Vout = 0.90V - 1.00V

4.99K

1/16W MF-LF

1%

402

2

1

R8951

374K

1%

402

MF-LF

1/16W

2

1

R8950

5%

PLACEMENT_NOTE=Place R8920 at U8900

1/16W

20

MF-LF

402

21

R8908

1/16W

5%

402

MF-LF

20

PLACEMENT_NOTE=Place R8908 at U8900

21

R8920

10K

MF-LF

402

5%

1/16W

2

1

R8907

10K

1/16W MF-LF 402

5%

2

1

R8910

CERM

50V

10%

402

560PF

21

C8951

2.21K

402

1/16W

1% MF-LF

2

1

R8953

5%

402-1

68PF

50V CERM

2

1

C8952

50V

5%

402

CERM

180PF

2 1

C8950

50V CERM 402

10%

0.001UF

2

1

C8920

QFN

CRITICAL

ISL6263C

4

15

8

29

12

14

27

26

25

24

23

7

16

18

33

2

9

1

22

19

31

20

3

21

13 11

28

10

32

6

5

17

30

U8900

SM

21

XW8900

50V

10%

402

CERM

680pF

2

1

C8953

MF-LF

1/16W

402

1%

7.15K

2

1

R8909

50V

10%

402

X7R

0.001UF

2

1

C8922

402

0.001UF

50V

10% CERM

2

1

C8923

69

0.001UF

50V

10% 402

CERM

2

1

C8921

1/16W

1%

402

MF-LF

10

21

R8904

1/16W

1%

402

MF-LF

150K

12

R8905

0.033UF

16V

10%

402

X5R

2 1

C8904

1UF

402-1

10% 10V X5R

2

1

C8901

1/16W

5%

402

MF-LF

1

21

R8911

6.3V

20%

X5R-CERM

402

4.7UF

2

1

C8902

0.01uF

16V

10%

402

CERM

2

1

C8903

16V

10%

402

X5R

0.1uF

2

1

C8972

68PF

50V

5%

402-1

CERM

21

C8971

402

MF-LF

9.76K

1%

1/16W

1

2

R8902

1/16W

1%

402

MF-LF

5.11K

2

1

R8901

1%

8.66K

1/16W MF-LF

402

21

R8900

CRITICAL

CSD58857Q5

MLP5X6-LFPAK-Q5

321

4

5

Q8951

16V

10%

603

X7R

0.22UF

2

1

C8956

CRITICAL

0.6UH-30A-1.5MOHM

MPL104-SM

21

L8920

6.3V

20%

603

X5R

10UF

2

1

C8965

10UF

6.3V

20% 603

X5R

2

1

C8966

2.0V

20% D2T-SM2

POLY-TANT

330UF

CRITICAL

3 2

1

C8943

1/16W

5%

402

MF-LF

1K

2

1

R8930

CRITICAL

CSD58856Q5A

MLP5X6-LFPAK-Q5A

321

4

5

Q8950

25V

20%

CASE-D2-SM

POLY-TANT

22UF

CRITICAL

2

1

C8930

25V

10% 603-1

X5R

1UF

2

1

C8932

25V

10%

603-1

X5R

1UF

2

1

C8933

1K

1/16W

1%

402

MF-LF

2

1

R8903

5%

402

COG

330PF

50V

2

1

C8906

D2T-SM2

2.0V

20%

POLY-TANT

330UF

CRITICAL

32

1

C8942

6.3V

20%

603

X5R

10UF

2

1

C8968

10%

4.7UF

X5R-CERM

6.3V 603

2

1

C8967

25V

20%

CASE-D2-SM

POLY-TANT

22UF

CRITICAL

2

1

C8931

69 84

1%

0.001

1W MF-1 0612

CRITICAL

43

21

R8940

50V

10% X7R

402

0.001UF

2

1

C8934

50V

10% 402

X7R

0.001UF

2

1

C8969

100

1% 1/16W MF-LF

402

2

1

R8924

MF-LF

100

1%

1/16W

402

2 1

R8925

76 77

5% 1/16W MF-LF

0

402

21

R8994

76 77

402

5%

0

1/16W MF-LF

21

R8990

1/16W MF-LF

402

0

5%

2 1

R8986

402

GPUVID1_0

1/16W MF-LF

2.2K

5%

R8985

GPUVID2_0

2.2K

MF-LF

5%

402

1/16W

R8983

1/16W

402

MF-LF

5%

2.2K

GPUVID0_1

2

1

R8987

5%

MF-LF

1/16W

GPUVID1_1

402

2.2K

R8984

1/16W 402

MF-LF

0

5%

2

1

R8988

1/16W MF-LF

GPUVID2_1

5%

402

2.2K

2

1

R8982

1/16W

5%

MF-LF

402

0

R8980

GPU (G96) CORE SUPPLY

SYNC_MASTER=M87_MLB

A.0.0

051-7892

9779

SYNC_DATE=10/17/2007

GPUVID2_0,GPUVID1_1,GPUVID0_1

GPUVID_1P00V

GPUVID2_1,GPUVID1_1,GPUVID0_1

GPUVID_0P90V

GND_GFXIMVP6_AGND

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

GFXIMVP6_FDE

GFXIMVP6_VSEN_P

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSEN_N

MIN_NECK_WIDTH=0.2MM

GPUVCORE_PGOOD

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_PHASE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_LGATE

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

PPBUS_G3H

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_UGATE

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

GFXIMVP6_VSUM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VIN

PPVCORE_GPU

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PPVCORE_GPU_REG_R

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

GFXIMVP6_PHASE_VSUM

PP5V_S3

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_BOOT

MIN_NECK_WIDTH=0.2MM

GPU_VDD_SENSE

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.20 mm VOLTAGE=1.25V

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

PP3V3_S0GPU

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_RBIAS

GFXIMVP6_VID0

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_COMP

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_FB

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VID1

GFXIMVP6_AF_EN

GFXIMVP6_DFB

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

PPVCORE_GPU

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VDIFF

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DROOP

GFXIMVP6_VID3

GPUVCORE_EN

GFXIMVP6_VID4

GFXIMVP6_SOFT

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GPU_GND_SENSE

MIN_LINE_WIDTH=0.25 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.20 mm

GFXIMVP6_VID2

GFXIMVP6_IMON

GFXIMVP6_VW

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S5_GFXIMVP6_PVCC

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S5_GFXIMVP6_VDD

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF_RC

MIN_NECK_WIDTH=0.3MM

GPU_VCORE_VID2

GPU_VCORE_VID1

GFXIMVP6_VID1 GFXIMVP6_VID2

GFXIMVP6_VID4

GFXIMVP6_VID3

PP3V3_S0GPU

GFXIMVP6_VID0

GPU_VCORE_VID0

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_OCSET

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

96

7 8

37 46 61 62 64 65 66 67 83

86

8

46 72 79

7 8 9 31 39 40

41 43 51

53 55 64

65 70

71

6 8

69 70 76

77 79

81

79

8

46 72 79

79

71

79

47

79

6 8

69 70 76 77 79 81

79

IN

SYM_VER-1

NC

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LCD (LVDS) INTERFACE

518S0651

Place close to the connector

no-panel case (development).

Panel has 2K pull-ups

100K pull-ups are for

X7R 402

10% 50V

0.001UF

2

1

C9010

0.1UF

X5R 402

10% 16V

2

1

C9001

SM

FERR-250-OHM

CRITICAL

21

L9000

MF-LF

1/16W

5%

10K

402

2

1

R9094

100K

MF-LF

5% 1/16W

402

2

1

R9011

MF-LF

402

5%

1/16W

100K

2

1

R9010

84

90-OHM-100MA

CRITICAL

DLP11S

4 3

21

L9010

DLP11S

CRITICAL

90-OHM-100MA

4 3

21

L9011

CRITICAL

20474-040E-11

F-RT-SM

9

8

7

6

5

44

43

42

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9000

0.001UF

X7R 402

10% 50V

2

1

C9002

0.1UF

X5R

16V 402

10%

2

1

C9009

CRITICAL

FPF1009

MFET-2X2

5

4

3

2

7

1

6

U9000

0.1UF

10% X5R

16V 402

2

1

C9011

10UF

20%

6.3V X5R 603

2

1

C9012

051-7892

A.0.0

9780

SYNC_MASTER=DDR

SYNC_DATE=12/19/2008

LVDS Display Connector

LCD_PWR_EN

PP3V3_S0

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD_UF

LVDS_CONN_B_CLK_F_N

LVDS_CONN_A_CLK_N

LVDS_CONN_B_CLK_N

LVDS_CONN_B_CLK_P

LVDS_CONN_A_CLK_P

PPVOUT_S0_LCDBKLT

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_DATA_P<2>

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_A_CLK_F_P

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_B_CLK_F_P LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1

LVDS_DDC_CLK LVDS_DDC_DATA

LVDS_CONN_A_CLK_F_N

PP3V3_S0

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

7

95

81 95

7

53 85

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

7

95

7

81 95

7

81 95

7

81 95

7

95

7

85

7

85

7

85

7

85

7

85

7

85

7

81

7

81

7

95

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

7

IN IN

IN

BI

IN

OUT

OUT OUT

OUT

BI

IN

BI

IN

IN IN

BI BI

IN

OUT

BI

IN

XSD*

HPD_1

DIN1_0-

DIN1_1+

DIN1_2-

DAUX1+

DIN1_3+

DDC_DAT2

DAUX2-

DDC_CLK2

HPD_2

GPU_SEL

TST0

DIN1_2+

DIN1_1-

DOUT_0-

DOUT_1+ DDC_CLK1 DDC_DAT1

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-

DIN2_1+

DDC_AUX_SEL

DIN2_1-

AUX+ AUX-

HPDIN

DIN2_2+ DIN2_2-

DIN2_3+ DIN2_3-

DAUX2+

DIN2_0-

DIN2_0+

DIN1_0+

DAUX1-

DOUT_1-

DOUT_0+ DIN1_3-

VDD

GND

OUT

VCC

C1

C2

C3

C4

A1 B1

A2 B2

A3 B3

A4 B4

GND

THRM

IN

OUT

IN

BI

BI BI

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

LVDS DDC MUX

LVDS Transmitter Termination

All emulated LVDS outputs require this termination

LO=PORT1 HI=PORT2

DisplayPort Mux

HI=DDC

LO=AUX_CH

(All 24 resistors)

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

18 77

9

18 77

9

18

82 95

18 77 81 82 84

0.1uF

X5R 40210% 16V

21

C9330

0.1uF

X5R 40210% 16V

21

C9331

18 90

MUXGFX

10V

20% 402

CERM

0.1UF

2

1

C9320

78 95

0.1uF

X5R 40210% 16V

21

C9335

X5R10% 402

0.1uF

16V

21

C9336

78 95

77 78

76 77

77 78

81 82 84

84

MUXGFX

10V

20% 402

CERM

0.1UF

2

1

C9321

SIGNAL_MODEL=DPMUX

CRITICAL

BGA

CBTL06141EE

MUXGFX

B7

J4

A2

G2

J1

H3

J2

A1

H7H4G8C8B3

F2 F1

E2 E1

D2 D1

B2 B1

F8 F9

E8 E9

D8 D9

B8 B9

A8 A9

B6 A6

B5 A5

B4 A4

J5

J8

H5

H8

C2

H6 J6

H9 J9

H2 H1

U9320

81 82 84

18 77 81 82 84

QFN1

SN74LV4066A

14

15

7

12

6

5

13

10

9

3

2

11

8

4

1

U9370

84

7

80

77 78

18

77 78

18

7

80

20%

0.1UF

402

CERM

10V

2

1

C9370

20K

402

MF-LF

1/16W

5%

2

1

R9373

5%

1/16W

402

MF-LF

20K

2

1

R9372

84

1%

10K

MF-LF

402

1/16W

DPMUX_EN_S0&DPMUX_EN_PLD

2

1

R9302

5%

0

MF-LF

402

1/16W

DPMUX_EN_PLD

21

R9303

DPMUX_EN_HPD

1%

10K

1/16W

402

MF-LF

2

1

R9301

84 95

PLACEMENT_NOTE=Place at U9600

1%

MF-LF

402

1/16W

270

OMIT

21

R9357

PLACEMENT_NOTE=Place at U9600

1%

GMUX_2V5

133

402

1/16W MF-LF

SIGNAL_MODEL=EMPTY

2

1

R9356

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9352

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9355

PLACEMENT_NOTE=Place at U9600

133

402

1/16W MF-LF

1%

SIGNAL_MODEL=EMPTY

GMUX_2V5

2

1

R9351

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9350

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9347

PLACEMENT_NOTE=Place at U9600

1%

GMUX_2V5

133

402

1/16W MF-LF

SIGNAL_MODEL=EMPTY

2

1

R9346

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9342

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9345

PLACEMENT_NOTE=Place at U9600

133

402

1/16W MF-LF

1%

SIGNAL_MODEL=EMPTY

GMUX_2V5

2

1

R9341

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9340

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

OMIT

21

R9337

PLACEMENT_NOTE=Place at U9600

133

402

1/16W MF-LF

1%

SIGNAL_MODEL=EMPTY

GMUX_2V5

2

1

R9336

PLACEMENT_NOTE=Place at U9600

270

1% 1/16W MF-LF

402

OMIT

21

R9332

PLACEMENT_NOTE=Place at U9600

270

1% 1/16W MF-LF

402

OMIT

21

R9335

PLACEMENT_NOTE=Place at U9600

133

402

1/16W MF-LF

1%

SIGNAL_MODEL=EMPTY

GMUX_2V5

2

1

R9331

PLACEMENT_NOTE=Place at U9600

270

1% 1/16W MF-LF

402

OMIT

21

R9330

PLACEMENT_NOTE=Place at U9600

270

1% 1/16W MF-LF

402

OMIT

21

R9327

PLACEMENT_NOTE=Place at U9600

133

1/16W MF-LF 402

1%

SIGNAL_MODEL=EMPTY

GMUX_2V5

2

1

R9326

84 95

OMIT

PLACEMENT_NOTE=Place at U9600

MF-LF

402

270

1/16W

1%

21

R9322

PLACEMENT_NOTE=Place at U9600

270

402

1/16W MF-LF

1%

OMIT

21

R9325

PLACEMENT_NOTE=Place at U9600

133

1/16W MF-LF

1%

402

SIGNAL_MODEL=EMPTY

GMUX_2V5

2

1

R9321

PLACEMENT_NOTE=Place at U9600

402

MF-LF

1/16W

1%

270

OMIT

21

R9320

DPMUX_EN_HPD

402

CERM-X5R

6.3V

10%

1UF

2

1

C9301

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

7

80 95

5%

100K

1/16W

402

MF-LF

2

1

R9305

5%

100K

1/16W

402

MF-LF

2

1

R9304

MF-LF

402

1/16W

1K

5%

2

1

R9306

PLACEMENT_NOTE=Place at U9320

1K

5%

MF-LF

402

1/16W

MUXGFX

21

R9307

5% MF-LF

1/16W 402

20K

2

1

R9371

5%

20K

MF-LF

402

1/16W

2

1

R9370

16

114S0517

R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357

GMUX_2V5

RES,MTL FILM,270 OHM,1%,1/16W,0402,SMD,L

16

R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357

GMUX_1V8114S0174

RES,MTL FILM,1/16W,357 OHM,1,0402,SMD,LF

Muxed Graphics Support

SYNC_DATE=12/05/2008

051-7892

A.0.0

9781

SYNC_MASTER=AMASON_M98_MLB

LVDS_B_DATA_N<2>

LVDS_A_DATA_P<1>

LVDS_B_CLK_P

LVDS_CONN_A_CLK_P

DP_EG_HPD

LVDS_B_DATA_P<2>

DP_EG_AUX_CH_P DP_EG_AUX_CH_N

DP_MUX_SEL_EG

PP3V3_S0

DP_MUX_EN

DP_MUX_XSD_L

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_DATA_P<1>

DP_IG_ML_N<3>

DP_IG_ML_P<3>

DP_EG_ML_P<1>

DP_CA_DET

DP_HOTPLUG_DET

MAKE_BASE=TRUE

LVDS_EG_DDC_DATA

LVDS_DDC_DATA

LVDS_DDC_SEL_IG

LVDS_A_DATA_N<1>

LVDS_B_DATA_N<1>

LVDS_A_CLK_N

DP_EG_AUX_CH_C_P

DP_IG_AUX_CH_C_P

DP_ML_N<0>

DP_ML_P<1> DP_ML_N<1>

DP_EG_ML_P<0> DP_EG_ML_N<0>

PP3V3_S0

LVDS_EG_DDC_CLK

LVDS_IG_DDC_CLK

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<2>

LVDS_DDC_SEL_EG

LVDS_IG_DDC_DATA

LVDS_DDC_CLK

LVDS_A_CLK_P

PP3V3_S0GPU

DP_ML_P<0>

DP_HPD_R

DP_IG_ML_P<0>

DP_IG_ML_P<1>

DP_IG_ML_P<2>

PP3V3_S0

DP_HOTPLUG_DET

DP_EG_ML_N<2>

DP_EG_ML_N<1>

DP_IG_DDC_CLK

DP_IG_AUX_CH_C_N

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_B_CLK_P

LVDS_CONN_B_CLK_N

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_CLK_N

LVDS_A_DATA_N<2>

LVDS_A_DATA_P<2>

LVDS_A_DATA_N<0>

LVDS_A_DATA_P<0>

LVDS_CONN_A_CLK_N

DP_ML_P<3>

DP_ML_N<2>

DP_ML_N<3>

DP_AUX_CH_C_P DP_AUX_CH_C_N

MAKE_BASE=TRUE

DP_CA_DET

DP_EG_ML_P<3>

DP_IG_ML_N<2>

DP_IG_ML_N<1>

DP_IG_ML_N<0>

DP_ML_P<2>

DP_EG_DDC_DATA

DP_EG_DDC_CLK

DP_EG_AUX_CH_C_N

DP_EG_ML_N<3>

DP_EG_ML_P<2>

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

6 7 8

13 18 19 21 22 24 25

28 29 37 39 43 45 47 48 49 51

55 59 60 63 68 69 70 77 80

81 82 84 85 96

95

96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 8

69 70 76 77 79

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

96

95

BI

IN

IO NC NC

IO

GND

OUT

IO NC NC

IO

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P ML_LANE3N

ML_LANE2N

CONFIG1 CONFIG2

BOT ROW TOP ROW

TH PINS SM PINS

SHIELD PINS

IO NC NC

IO

GND

IO NC NC

IO

GND

IN

G

D

S

G

D

S

SYM_VER-2

OUT

G

D

S

G

D

S

BI

IN

OC*

OUT

EN

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(CA) has 100k

DP to DVI/HDMI Cable Adapter

pull-up to DP_PWR.

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

Port Power Switch

81 95

100K

MF-LF

402

5%

1/16W

2

1

R9421

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

109

12

3

D9411

0.1uF

X5R 40210% 16V

21

C9415

0.1uF

X5R 40210% 16V

21

C9414

18 77 81 84

0.1uF

X5R 40210% 16V

21

C9411

0.1uF

X5R 40210% 16V

21

C9410

100K

MF-LF

402

5%

1/16W

2

1

R9420

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

109

12

3

D9410

DP_ESD

CRITICAL

RCLAMP0504F

SC70-6-1

52

6

4

3

1

D9400

CRITICAL

DSPLYPRT-M97-1

F-RT-THSM

19

10 12

15 17

9 11

3 5

22 21

2

14 13

8 7

1

20

6

4

16 18

J9400

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

76

45

3

D9411

1M

MF-LF 402

5% 1/16W

2

1

R9425

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

76

45

3

D9410

0.1uF

X5R 40210% 16V

21

C9417

0.1uF

X5R 40210% 16V

21

C9416

0.1uF

X5R 40210% 16V

21

C9413

0.1uF

X5R 40210% 16V

21

C9412

81 95

0.01UF

CERM 603

20% 50V

2

1

C9400

FERR-120-OHM-3A

0603

21

L9400

81 95

2N7002DW-X-G

SOT-363

4

5

3

Q9440

2N7002DW-X-G

SOT-363

1

2

6

Q9440

100K

MF-LF

402

5%

1/16W

2

1

R9443

100K

MF-LF

402

5%

1/16W

2

1

R9442

12-OHM-100MA

TCM1210-4SM

4

3 2

1

FL9403

12-OHM-100MA

TCM1210-4SM

4

32

1

FL9402

12-OHM-100MA

TCM1210-4SM

4

32

1

FL9401

12-OHM-100MA

TCM1210-4SM

4

32

1

FL9400

NO STUFF

0

MF-LF

4025%

1/16W

21

R9403

NO STUFF

0

MF-LF

4025%

1/16W

21

R9413

NO STUFF

0

MF-LF

4025%

1/16W

21

R9402

NO STUFF

0

MF-LF

4025%

1/16W

21

R9432

NO STUFF

0

MF-LF

4025%

1/16W

21

R9401

NO STUFF

0

MF-LF

4025%

1/16W

21

R9431

NO STUFF

0

MF-LF

4025%

1/16W

21

R9400

NO STUFF

0

MF-LF

4025%

1/16W

21

R9430

81 84

2N7002DW-X-G

SOT-363

1

2

6

Q9441

2N7002DW-X-G

SOT-363

4

5

3

Q9441

1M

MF-LF

402

5%

1/16W

2

1

R9422

10K

MF-LF

402

5%

1/16W

2

1

R9445

10K

MF-LF

402

5%

1/16W

2

1

R9444

100K

MF-LF

402

5%

1/16W

2

1

R9423

81 95

7

21 34 37 42 69 84

10UF

X5R 603

20%

6.3V

2

1

C9480

0.1UF

CERM 402

20% 10V

2

1

C9481

CRITICAL

22UF

X5R-CERM 603

20%

6.3V

2

1

C9486

CRITICAL

TPS2051B

SOT23

1

3

5

2

4

U9480

0.1UF

CERM

402

20% 10V

2

1

C9485

82 97

A.0.0

051-7892

SYNC_DATE=07/10/2008

SYNC_MASTER=MUXGFX

DisplayPort Connector

DP_ML_CONN_N<2>

DP_ML_CONN_N<1>

DP_ML_CONN_P<1>

DP_ML_CONN_P<0> DP_ML_CONN_N<0>

PP3V3_S0_DPILIM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

DP_AUX_CH_C_N

DP_ML_CONN_P<3>

DP_AUX_CH_C_P

PP3V3_S5

PM_SLP_S3_L

TP_DPPWR_OC_L

DP_HOTPLUG_DET

DP_HPD_L_Q

PP3V3_S0

DP_ML_C_P<0>

DP_ML_C_N<1>

DP_ML_C_P<2>

DP_ML_C_N<2>

DP_ML_C_P<3>

DP_ML_C_N<3>

DP_ML_P<3>

DP_ML_N<2>

DP_ML_P<2>

DP_ML_N<1>

DP_ML_P<1>

DP_ML_N<0>

DP_ML_P<0>

DP_CA_DET_L_Q

DP_CA_DET

DP_ML_N<3> DP_ML_CONN_N<3>

DP_ML_CONN_P<2>

PP3V3_S0

DP_ML_C_N<0>

DP_ML_C_P<1>

DP_HPD_Q

PP3V3_S0_DPPWR

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

DP_CA_DET_Q

HDMI_CEC

95

7 8

18 20 22 24 26 30 34

37 38 44 54 64 68 69 70 87

96

6 7 8

13 18 19 21 22

24 25 28 29 37 39 43

45 47 48 49 51 55 59

60 63 68 69 70 77 80

81 82 84 85 96

7

95

7

95

95 95

95

6 7 8

13 18 19 21 22 24

25 28 29 37 39 43 45 47

48 49 51 55 59 60 63 68

69 70 77 80 81 82 84 85

96

95

7

95

IN OUT

IN

OUT

Q1

Q2

SW

BOOT1 UGATE1 PHASE1 LGATE1 OUT1

VCC

REFIN2

ILIM2

OUT2

SKIP*

POK2

EN2

UGATE2 PHASE2

BOOT2

LGATE2

PGND

GND

SECFB

PVCC

EN1

ILIM1

FB1

BYP

LDOREFIN

LDO

VIN

VREF3

EN_LDO

TON

REF

POK1

THRM_PAD

D

GS

NC

D

S

G

D

S

G

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(=PP1V8FB_S0_REG)

(Q9510 limit)

6A max output

(Q9560 limit)

10.5A max output

(Rb should be between 10K and 100K)

(Internal 10-ohm path from PVCC to VCC)

Vout = 0.7V * (1 + Ra / Rb)

f = 300 kHz

(SGND)

Vout = 1.8V

<Ra>

f = 400 kHz

Vout = 1.103V

<Rb>

<Ra>

<Rb>

6.3V

20%

603

X5R

10UF

2

1

C9565

25V

10%

603-1

X5R

1UF

2

1

C9595

0.1UF

603-1

X7R

50V

10%

2

1

C9530

25V

10% 603-1

X5R

1UF

2

1

C9545

402

MF-LF

1/16W

1%

5.76K

2

1

R9520

10K

MF-LF

1/16W

1%

402

2

1

R9521

6.3V

20%

603

X5R

10UF

2

1

C9515

1/16W

1%

402

MF-LF

280K

2

1

R9535

1/16W

1%

402

MF-LF

130K

2

1

R9585

PCMB053T

3.3UH-3.5A

CRITICAL

21

L9510

2.0V

20% B2-SM

POLY-TANT

330UF

CRITICAL

2

1

C9510

2.5V

20%

CASE-B2-SM2

POLY-TANT

220UF

CRITICAL

2

1

C9560

69 84

69

69 70 84

9

69 84

MMD06CZ-SM

2.2UH-14A

CRITICAL

21

L9560

50V

10%

603-1

X7R

0.1UF

2

1

C9580

CRITICAL

25V

20%

CASE-D2-SM

POLY-TANT

22UF

2

1

C9540

25V

20%

CASE-D2-SM

POLY-TANT

22UF

CRITICAL

2

1

C9590

MLP

FDMS9600S

CRITICAL

10

7

6 5

8

1

9 4 3 2

Q9560

SM

PLACEMENT_NOTE=Place next to C7665

2 1

XW9565

50V

5%

402

CERM

100PF

NO STUFF

2

1

C9520

PLACEMENT_NOTE=Place XW9515 next to C7615

SM

21

XW9515

ISL6236

OMIT

QFN

563

2615

2

33

29

20

32

1

19

28

13

2516

22

3010

2318

8

7

3112

21

11

4

2714

9

2417

U9500

25V

10%

805

X5R

10UF

2

1

C9500

SM

21

XW9500

10V

20%

402

CERM

0.1UF

2

1

C9585

1/16W

1%

402

MF-LF

127K

2

1

R9564

1%

402

MF-LF

14.0K

1/16W

2

1

R9563

10V

10%

402-1

X5R

1UF

2

1

C9503

10V

10%

402-1

X5R

1UF

2

1

C9501

1/16W

1%

402

MF-LF

78.7K

2

1

R9562

SSM3K15FV

SOD-VESM-HF

2

1

3

Q9565

10%

0.0022UF

CERM

50V 402

2

1

C9561

1/16W

5%

402

MF-LF

4.7

2 1

R9500

PWRPK-1212-8

SI7904BDN

CRITICAL

3

4

5

Q9510

CRITICAL

SI7904BDN

PWRPK-1212-8

1

2

6

Q9510

10V

10%

402-1

X5R

1UF

2

1

C9504

1.1V / 1V8 FB Power Supply

SYNC_DATE=07/10/2008

SYNC_MASTER=MUXGFX

051-7892

A.0.0

9783

U9500

1

353S2312 CRITICAL

IC,ISL6236,DUAL PWM CTRL,QFN32

PPBUS_G3H

GPIO7_FBVDD_ALTVO

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

GND_P1V1P1V8_SGND

GPU_P1V8_REFIN

PP1V1_S0GPU_REG

P1V1GPU_PGOOD

GPUFB_VID_L

P1V8FB_DRVH

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GATE_NODE=TRUE

P1V1GPU_VBST

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP5V_S0GPU_VREF

PM_ALL_GPU_PGOOD

P1V8_GPU_VSNS

PP1V8_S0GPU_ISNS_R

P1V8FB_TRIP

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V8FB_VBST

P1V1GPU_TRIP

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=5V

PP5V_S0GPU_P1V1P1V8_VCC

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V8FB_LL

SWITCH_NODE=TRUE

DIDT=TRUE

P1V8_S0GPU_EN

PP5V_S0

VOLTAGE=2V

PP2V_S0GPU_P1V8_REF

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V1GPU_DRVL

GATE_NODE=TRUE

DIDT=TRUE

PVIN_S0GPU_P1V1

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V8FB_DRVL

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V1GPU_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V1GPU_LL

SWITCH_NODE=TRUE

DIDT=TRUE

P1V1S0_VSNS

P1V1GPU_VFB

P1V1_GPU_EN

7 8

37 46 61 62 64 65 66 67

79 86

76 77

8

71 73

76 78

8

47

7 8

39 44 49 51 63 66 67 70 85

IN

OUT

IN

OUT

D

S G

IN

IN IN

IN

OUT

IN

IN OUT

IN

D

S G

IN IN

IN

IN IN

IN

PT17B

PT17A

PT16B

PT16A

PT15A

PT14B

PT4B

PT4A

PT3B

PT3A

PR10B

PR10A

PT32A

PT20B

PT19B

PT19A

PB15B PB16A PB16B

PR11B PR12A

PR13B

PR14B PR15A PR15B PR16A PR16B

CFG0

GND

GNDIO0

GNDIO1

GNDIO2

GNDIO3

GNDIO4

GNDIO5

GNDIO6

GNDIO7

LRC_GNDPLL

LRC_VCCPLL

PB2A PB2B PB14A PB14B PB15A

PB17A PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB30A PB30B PB31A PB31B PB32A PB32B

PL2A PL2B PL10A PL10B PL11A PL11B PL12A PL12B PL13A PL13B PL14A PL14B PL15A PL15B PL16A PL16B PL18A PL18B PL19A PL19B PL32A PL32B

PR2A PR2B

PR11A

PR12B PR13A

PR14A

PR18A PR18B PR30A PR30B

PT2A PT2B

PT14A

PT15B

PT18B

PT20A

PT32B

TCK TDI TDO TMS TOE

ULC_GNDPLL

ULC_VCCPLL

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCJ

PT18A

VCC

IN

IN OUT

IN

BI BI

BI

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

GMUX CPLD

BANK7 BANK6

(OD)

BANK3 BANK2 BANK1

(All 14 resistors)

PM_SLP_S3_L Isolation

LVDS Receiver Termination

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

GMUX_JTAG_TCK Inversion

BANK5

(OD)

Required Pullups

Required Pulldowns

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

The MAKE BASE properties for these signals are on the POWER CONTROL page.

BANK0

BANK4

7

21 34 37 42 69 82

78 84 95

81 82

18 77 81 82

81 95

4V

20%

402

X5R

4.7UF

2

1

C9600

81 95

84

81 95

1/16W

1%

402

MF-LF

10K

2

1

R9670

81 95

SOT563

SSM6N15FEAPE

4

5

3

Q9670

17

1/16W

5% 402

MF-LF

100K

21

R9693

1/16W

5% 402

MF-LF

20K

21

R9692

1/16W

5% 402

MF-LF

100K

NO STUFF

21

R9691

1/16W

5% 402

MF-LF

10K

21

R9683

1/16W

5% 402

MF-LF

10K

21

R9682

9

69 83

1/16W

5% 402

MF-LF

4.7K

21

R9690

1/16W

5% 402

MF-LF

10K

21

R9681

1/16W

5% 402

MF-LF

1K

21

R9680

10V

20%

402

CERM

0.1UF

2

1

C9630

10V

20%

402

CERM

0.1UF

2

1

C9631

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9666

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9665

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9664

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9663

84

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9656

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9662

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9661

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9660

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9655

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9651

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9652

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9653

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9654

1/16W

1% 402

MF-LF

100

PLACEMENT_NOTE=Place at U9200

SIGNAL_MODEL=EMPTY

21

R9650

84

1/16W

5% 402

MF-LF

10K

21

R9695

1/16W

1%

402

MF-LF

10K

NO STUFF

SILK_PART=GMUX_RST

PLACEMENT_NOTE=Place on top side at U9200

2

1

R9679

69

69 70

69 83

69 79

69 70 83

26

10V

20%

402

CERM

0.1UF

NO STUFF

2

1

C9694

10V

20%

402

CERM

0.1UF

NO STUFF

2

1

C9693

1/16W

5% 402

MF-LF

0

EG_PWRSEQ_HW

21

R9630

1/16W

5% 402

MF-LF

0

EG_PWRSEQ_GMUX

21

R9631

1/16W

5% 402

MF-LF

0

EG_PWRSEQ_GMUX

21

R9632

10V

20%

402

CERM

0.1UF

NO STUFF

2

1

C9692

10V

20%

402

CERM

0.1UF

NO STUFF

2

1

C9691

1/16W

5% 402

MF-LF

0

EG_PWRSEQ_GMUX

21

R9634

1/16W

5% 402

MF-LF

0

EG_PWRSEQ_GMUX

21

R9633

18 84 90

1/16W

5% 402

MF-LF

100K

21

R9694

0402

FERR-220-OHM

21

L9627

0402

FERR-220-OHM

21

L9631

9

18 84 90

SOT563

SSM6N15FEAPE

1

2

6

Q9670

18 84 90

CRITICAL

OMIT

XP28

CSBGA-HF

K12

F2

C3M1N5M3M9

M12

F13

C14

A12

B7

B5

M8

J14

J2

C11

P8

N11

J13

J3

C4

B11

A4

B4

K2

L12

K13

L13

K14

A5

C5

B3

A1

A13

B13

A3

A2

B12

A11

A10

B10

C10

A9

B9

A8

C9

C8

A7

A6

C7

B6

N13

N14

B14

A14

M13

L14

J12

H14

H12

H13

G13

G12

G14

F14

F12

E12

E14

D14

D13

D12

P1

N1

B2

B1

L2

K3

L3

L1

H3

H1

G3

H2

G2

F3

G1

F1

E3

D2

E1

D1

D3

C2

P14

N12

P13

P12

M10

P10

N2

P2

N9

P9

N8

N7

M7

P7

M6

P6

M5

P5

M4

N3

N4

P4

P11

M11

E2C1M2P3N6

N10

M14

E13

C13

C12

C6

B8

J1

K1

U9600

18 84 90

26

9

18 84

19 26 91

19 42 44 91

1/16W

1%

402

MF-LF

10K

NO STUFF

2

1

R9647

19 42 44 91

80

77

9

84

9

71 84

81 84

81

10V

20%

402

CERM

0.1UF

2

1

C9604

10V

20%

402

CERM

0.1UF

2

1

C9605

81 84

84 85

9

86

6 9

19

6 9

17

6 9

19

1/16W

1%

402

MF-LF

10K

NO STUFF

2

1

R9641

20% 10V

402

CERM

0.1UF

2

1

C9606

10V

20%

402

CERM

0.1UF

2

1

C9607

10V

20%

402

CERM

0.1UF

2

1

C9608

10V

20%

402

CERM

0.1UF

2

1

C9609

10V

20%

402

CERM

0.1UF

2

1

C9610

10V

20%

402

CERM

0.1UF

2

1

C9611

10V

20%

402

CERM

0.1UF

2

1

C9621

10V

20%

402

CERM

0.1UF

2

1

C9622

10V

20%

402

CERM

0.1UF

2

1

C9612

10V

20%

402

CERM

0.1UF

2

1

C9613

1/16W

1%

402

MF-LF

10K

NO STUFF

2

1

R9646

10V

20%

402

CERM

0.1UF

2

1

C9623

10V

20%

402

CERM

0.1UF

2

1

C9624

10V

20%

402

CERM

0.1UF

2

1

C9614

10V

20%

402

CERM

0.1UF

2

1

C9625

10V

20%

402

CERM

0.1UF

2

1

C9615

10V

20%

402

CERM

0.1UF

2

1

C9616

10V

20%

402

CERM

0.1UF

2

1

C9626

10V

20% 402

CERM

0.1UF

2

1

C9627

10V

20%

402

CERM

0.1UF

2

1

C9617

1/16W

1%

402

MF-LF

10K

2

1

R9640

10V

20%

402

CERM

0.1UF

2

1

C9628

10V

20%

402

CERM

0.1UF

2

1

C9629

76 77

9

18

76 77

9

18

78 84 95

1/16W

1%

402

MF-LF

10K

2

1

R9645

78 84 95

1

U9600

CRITICAL

336S0025

IC,XP2-5,HF,CPLD,BLANK

GMUX_5K_BLANK

IC,CPLD,LATTICE,132CSBGA,K19

341S2479

GMUX_PROG

CRITICAL

U9600

1

84 97

A.0.0

051-7892

SYNC_DATE=07/10/2008

SYNC_MASTER=MUXGFX

Graphics MUX (GMUX)

PP1V8_S0

LCD_BKLT_PWM

EG_CLKREQ_IN_L

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

LVDS_EG_A_DATA_N<0>

DP_MUX_EN

LVDS_DDC_SEL_IG

LVDS_DDC_SEL_EG

LCD_BKLT_EN

GMUX_TOE GMUX_CFG0

LCD_BKLT_PWM

DP_MUX_SEL_EG

EG_RAIL3_EN EG_RAIL4_EN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S0_LRC_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S0_ULC_F

GMUX_INT

EG_RAIL4_EN

EXTGPU_PWR_EN

GMUX_DEBUG_RESET_L

DP_MUX_SEL_EG

LVDS_DDC_SEL_IG

LVDS_DDC_SEL_EG

EG_RESET_L

JTAG_GMUX_TCK

EG_CLKREQ_OUT_L

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<1>

LVDS_EG_B_DATA_P<2>

GMUX_DEBUG_RESET_L

LVDS_EG_B_DATA_N<2>

PP3V3_S0

EG_RESET_L EG_RAIL1_EN

JTAG_GMUX_TDI JTAG_GMUX_TDO JTAG_GMUX_TMS

EG_CLKREQ_OUT_L

P1V1_GPU_EN

GPUVCORE_EN

PM_ALL_GPU_PGOOD EG_CLKREQ_IN_L

LVDS_IG_A_DATA_N<0>

LVDS_IG_B_DATA_N<1>

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<1>

LVDS_IG_B_DATA_N<2>

LVDS_EG_A_DATA_N<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<0>

LVDS_A_DATA_P<0>

LVDS_B_CLK_N

LVDS_B_CLK_P

LVDS_A_CLK_N

GMUX_PM_SLP_S3_L

LVDS_IG_B_DATA_N<1>

LVDS_IG_A_DATA_N<0>

GMUX_INT

P1V8_S0GPU_EN

P3V3GPU_EN

JTAG_GMUX_TCK

DP_CA_DET_EG

LVDS_EG_A_DATA_P<0>

LVDS_EG_B_DATA_N<0>LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<1>LVDS_EG_B_DATA_P<1>

LVDS_EG_A_CLK_NLVDS_EG_A_CLK_P

LVDS_EG_A_DATA_P<0>

LVDS_EG_A_DATA_N<1>LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<2>LVDS_EG_A_DATA_P<2>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>LVDS_IG_B_DATA_P<0>

LVDS_IG_A_DATA_N<2>LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1>

LVDS_IG_B_DATA_P<1>

LVDS_IG_A_CLK_P LVDS_IG_A_DATA_P<0>

LVDS_B_DATA_N<1>

LVDS_A_DATA_P<2>

TP_GMUX_PT32A

DP_HOTPLUG_DET

GMUX_JTAG_TCK_L

JTAG_GMUX_TCK

MAKE_BASE=TRUE

GMUX_PM_SLP_S3_L

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<1> LVDS_A_DATA_N<1>

GMUX_PM_SLP_S3_L

TP_GMUX_PT32B

DP_CA_DET

LVDS_B_DATA_P<2>

TP_GMUX_PT20A TP_GMUX_PT20B

LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_IG_PANEL_PWR EG_LCD_PWR_EN

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_N<2> LVDS_EG_B_DATA_P<0>

LVDS_EG_A_DATA_P<1>

LVDS_EG_A_DATA_P<2>

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_N<0>

LVDS_EG_B_DATA_N<2>

LVDS_EG_B_DATA_P<1>

EG_BKLT_EN

LVDS_IG_BKL_ON

LCD_PWR_EN LPC_AD<0> LPC_AD<1> LPC_AD<2>

EG_RAIL2_EN

LPC_AD<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_P<2>

LPC_FRAME_L

LPC_CLK33M_GMUX

LPC_RESET_L

GMUX_PCIE_RESET_L

LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<0>

TP_GMUX_PL10B

LVDS_IG_A_DATA_P<1>

TP_LVDS_MUX_SEL_EG

LVDS_IG_A_CLK_N

LVDS_IG_B_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<2>

PM_SLP_S3_L

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

TP_GMUX_PL18B_VSYNC

PP3V3_S0

TP_GMUX_PL10A

LVDS_A_CLK_P

PP3V3_S0

PP1V2_S0

PP3V3_S0

7 8

18 25 55

69 70 87

84 85

84

9

18 84

84

81 84

9

71 84

6

84

9

84

78 84 95

84

78 84 95

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 85 96

18 84 90

78 84 95

6

84

78 84 95 78 84 95

78 84 95

78 84 95 78 84 95

18 84 90

18 84 90 18 84 90

18 84 90

6

84

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81 82

84 85 96

8

87

6 7 8

13 18

19 21 22 24

25 28 29 37

39 43 45 47

48 49 51 55

59 60 63 68

69 70 77 80

81 82 84 85

96

OUT

NC

ALSI

ALSO

ADR

IF_SEL

PWM

EN

FAULT

THRM

GND_L

GND_SW

OUT6

VIN

VDDIO VLDO

FB

SW

OUT1

OUT2

OUT4

OUT5

OUT7

OUT3SCLK

SDA

GND_S

PAD

NC

IN

OUT

G

S

D

S

G

N-CHN

P-CHN

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE XW9700 CLOSE TO C9712 AND C9713

*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.

R9704 SHOULD BE 47K IF RC FILTER IS USED

* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

IF_SEL=1 FOR SMBUS

MF-LF

0

5%

1/16W

402

21

R9757

805

25V

10% X5R

10UF

CRITICAL

2

1

C9712

X5R

10%

0.1UF

402

25V

2

1

C9713

IHLP2525CZ-SM

22UH-2.5A

CRITICAL

21

L9701

402

X7R-CERM

220PF

10% 50V

2

1

C9796

2.2UF

X7R 1210

10% 100V

2

1

C9799

2.2UF

X7R 1210

10% 100V

2

1

C9797

CRITICAL

RB160M-60G

SOD-123

21

D9701

10.2

TF

402

0.1%

1/16W

21

R9722

10.2

TF

402

0.1%

1/16W

21

R9721

10.2

TF

402

0.1%

1/16W

21

R9720

7

80

7

80

0

MF-LF

5%

1/16W

402

21

R9753

7

80

7

80

7

80

7

80

10.2

TF

402

0.1%

1/16W

21

R9718

10.2

TF

402

0.1%

1/16W

21

R9719

10.2

TF

402

0.1%

1/16W

21

R9717

100K

MF-LF 402

1%

1/16W

21

R9715

402

1%

MF-LF

1/16W

301K

21

R9731

NO STUFF

X5R 402

10% 25V

0.1UF

2

1

C9723

1UF

X5R 603-1

10% 25V

2

1

C9710

402

X5R

10%

0.1UF

16V

2

1

C9711

SM

21

XW9710

OMIT

LLP

LP8543SQX

CRITICAL

22

23

8

25

24

11

10

2

19

18

17

16

14

13

12

3

1

9

15

21

7

4

6

5

20

U9701

MF-LF

402

5%

1/16W

100K

2

1

R9716

0.01UF

CERM 402

10% 16V

2

1

C9714

NO STUFF

402

0

MF-LF

5% 1/16W

2

1

R9703

5%

0

MF-LF 402

1/16W

2

1

R9702

84

0

MF-LF

402

5%

1/16W

21

R9704

NO STUFF

50V

33PF

CERM 402

5%

2

1

C9704

53 96

NO STUFF

MF-LF

1/16W

100K

5%

402

2

1

R9714

100K

1% 1/16W MF-LF

402

21

R9735

402

0

1/16W

5%

MF-LF

21

R9701

NTZD3155C

SOT-563-HF

CRITICAL

1

4

2

5

6

3

Q9701

SM

21

XW9720

SM

2

1

XW9721

SM

2

1

XW9722

85

SYNC_MASTER=DDR

SYNC_DATE=12/12/2008

LCD BACKLIGHT DRIVER

97

A.0.0

051-7892

IC,LP8543,WHT LED BKLT,PROD

CRITICAL

U9701

1

353S2670

PPBUS_S0_LCDBKLT_PWR

PPVIN_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=6V

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP5V_S0

PPVIN_BKL_R

BKL_VLDO

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

SWITCH_NODE=TRUE

PPBUS_S0_LCDBKLT_PWR_SW

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

BKLT_EN

BKL_SGND

BKL_IF_SEL

BKL_SDA

PPVOUT_S0_LCDBKLT

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

BKLT_EN

BKL_ISEN4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN5 BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

TP_BKL_FAULT

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

SMBUS_MCP_1_CLK

SMBUS_MCP_1_DATA

PPBUS_S0_LCDBKLT_PWR

LCD_BKLT_PWM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN2

BKLT_EN_R

BKL_VLDO_EN_L

PP3V3_S0

LVDS_BKL_PWM_RC

BKL_SCL

85 86

7 8

39 44 49 51 63 66 67 70 83

7

85

7

53 80

85

7

21 45 60 91

85 86

7

6 7 8

13 18 19 21 22 24 25 28

29 37 39 43 45 47 48 49 51 55

59 60 63 68 69 70 77 80 81

82 84 96

OUT

IN

D

SG

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

43 mOhm @4.5V

LOADING 0.4 A (EDP)

P-TYPE

PPBUS S0 LCDBkLT FET

FDC638APZ

RDS(ON)

MOSFET

.

CHANNEL

0402-HF

CRITICAL

2AMP-32V

21

F9800

85

1/16W

1%

402

MF-LF

301K

2

1

R9808

MF-LF

1/16W

1%

402

147K

2

1

R9809

16V

10%

402

X5R

0.1UF

2

1

C9802

7 8

37 46 61 62 64 65 66 67

79 83

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

4

3

6521

Q9806

1/16W

5%

402

MF-LF

4.7K

2

1

R9840

SSM6N15FEAPE

SOT563

4

5

3

Q9807

SOT563

SSM6N15FEAPE

1

2

6

Q9807

9

84 86

26

SYNC_DATE=07/02/2008

SYNC_MASTER=YITE_M98_MLB

LCD Backlight Support

86 97

A.0.0

051-7892

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_FUSED

LCD_BKLT_EN

BKLT_EN_L

BKLT_PLT_RST_L

PPBUS_S0_LCDBKLT_EN_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_PWR

PPBUS_S0_LCDBKLT_EN_DIV

LCD_BKLT_EN

PPBUS_G3H

9

84 86

IN

VIN

MODE

RUN1

VFB1 VFB2

SW2SW1

RUN2

THRM

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(Switcher limit) f = 2.25 MHz

1.8V/1.2V S0 SWITCHER

Vout = 0.6V * (1 + Ra/Rb)

(Switcher limit)

<Ra>

<Rb>

f = 2.25 MHz

0.6A max output

Vout = 1.2V

<Ra>

0.6A max output

Vout = 1.8V

69

CRITICAL

PCAA031B-SM

2.2UH-1.2A

21

L9900

PCAA031B-SM

2.2UH-1.2A

CRITICAL

21

L9980

237K

MF-LF 402

1% 1/16W

2

1

R9901

10PF

50V

5%

402

CERM

2

1

C9901

475K

1/16W

1% MF-LF

402

2

1

R9900

1/16W

280K

1%

402

MF-LF

2

1

R9983

CERM

50V

5%

10PF

402

2

1

C9982

1% MF-LF

280K

1/16W 402

2

1

R9982

CRITICAL

LTC3419

DFN

5

81

9

64

72

3

U9900

603

6.3V

20% X5R

10UF

2

1

C9985

10UF

X5R

20%

6.3V 603

2

1

C9905

6.3V

20% X5R

10UF

603

2

1

C9900

SYNC_DATE=02/01/2008

SYNC_MASTER=MUXGFX

Misc Power Supplies

051-7892

A.0.0

9787

PP3V3_S5

PP1V8_S0

P1V2S0_VFB

P1V2S0_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

P1V8S0_SW

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P2V5S0_VFB

P1V2R1V8S0_EN

PP1V2_S0

7 8

18 20 22 24 26 30 34 37

38 44 54 64 68 69 70 82 96

7 8

18 25 55 69 70 84

8

84

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

FSB 1X signals shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 2X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.

FSB 4X signals / groups shown in signal table on right.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

FSB (Front-Side Bus) Constraints CPU / FSB Net Properties

(CPU_VCCSENSE) (CPU_VCCSENSE)

(FSB_CPURST_L)

(See above)

Signals

NET_TYPE

SPACING

FSB 1X Signals

FSB 4X Signal Groups

FSB 2X

PHYSICAL

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SR DG recommends at least 25 mils, >50 mils preferred

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

Most CPU signals with impedance requirements are 55-ohm single-ended.

FSB Clock Constraints

Some signals require 27.4-ohm single-ended impedance.

MCP FSB COMP Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

Design Guide recommends each strobe/signal group is routed on the same layer.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Intel Design Guide recommends FSB signals be routed only on internal layers.

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

ELECTRICAL_CONSTRAINT_SET

88 97

A.0.0

051-7892

CPU/FSB Constraints

SYNC_MASTER=MUXGFX

SYNC_DATE=02/18/2008

CPU_AGTL

?

TOP,BOTTOM

=2x_DIELECTRIC

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=50_OHM_SE

FSB_DSTB_50S

=1:1_DIFFPAIR=1:1_DIFFPAIR

*

TOP,BOTTOM

FSB_ADSTB

?

=4x_DIELECTRIC

=50_OHM_SE

*

=STANDARD

FSB_50S

=50_OHM_SE =50_OHM_SE

=STANDARD

=50_OHM_SE

TOP,BOTTOM

?

FSB_DATA

=4x_DIELECTRIC

TOP,BOTTOM

FSB_DSTB

?

=5x_DIELECTRIC

FSB_ADDR

TOP,BOTTOM

?

=3x_DIELECTRIC

FSB_1X

TOP,BOTTOM

?

=3x_DIELECTRIC

FSB_DATA

* ?

=2x_DIELECTRIC

?

FSB_DSTB

*

=3x_DIELECTRIC

=STANDARD

*

FSB_ADDR

?

=STANDARDFSB_1X

?*

FSB_ADSTB

?*

=2x_DIELECTRIC

=3x_DIELECTRIC

?

CLK_FSB

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB_100D

8 MIL

* ?

MCP_FSB_COMP

=50_OHM_SE

MCP_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE

*

=STANDARD =STANDARD

*

CPU_VCCSENSE

?

25 MIL

CPU_GTLREF

* ?

CPU_ITP

* ?

=2:1_SPACING

?

CPU_COMP

*

25 MIL

8 MIL

CPU_8MIL

?*

CPU_AGTL

?*

=STANDARD

=27P4_OHM_SE

*

=27P4_OHM_SE =27P4_OHM_SE

7 MIL7 MIL

CPU_27P4S

*

=STANDARD =STANDARD

CPU_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE =50_OHM_SE

=4x_DIELECTRICCLK_FSB

?

TOP,BOTTOM

FSB_50S

FSB_DATA

FSB_DATA_GROUP0

FSB_DINV_L<0>

FSB_50S

FSB_1XFSB_1X

FSB_LOCK_L

CPU_50S

CPU_AGTL

CPU_ASYNC

CPU_A20M_L

FSB_50S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB1

FSB_DSTB_L_N<1>

FSB_50S

FSB_ADSTB

FSB_ADSTB0

FSB_ADSTB_L<0>

CPU_50S

CPU_8MIL

CPU_VID<6..0>

CPU_50S

CPU_8MIL

IMVP6_VID<6..0>

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_N

CPU_27P4S

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSE_N

CPU_27P4S

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSE_P

CPU_50S CPU_ITP

XDP_CPURST_L

CPU_50S CPU_ITP

XDP_BPM_L5

XDP_BPM_L<5>

CPU_50S CPU_ITP

XDP_BPM_L

XDP_BPM_L<4..0>

CPU_50S CPU_ITP

XDP_TRST_L

CPU_50S CPU_ITPXDP_TCK

XDP_TCK

CPU_50S CPU_ITPXDP_TMS

XDP_TMS

CPU_50S CPU_ITPXDP_TDO

XDP_TDO

CPU_50S CPU_ITPXDP_TDI

XDP_TDI

CPU_27P4S

CPU_COMPCPU_COMP

CPU_COMP<0>

CPU_50S

CPU_COMPCPU_COMP

CPU_COMP<1>

CPU_27P4S

CPU_COMPCPU_COMP

CPU_COMP<2>

CPU_50S

CPU_COMPCPU_COMP

CPU_COMP<3>

CPU_50S

CPU_GTLREFCPU_GTLREF

CPU_GTLREF

CPU_50S

CPU_AGTL

IMVP_DPRSLPVR

CPU_50S

CPU_AGTL

PM_DPRSLPVR

CPU_50S

CPU_IERR_L

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

FSB_CLK_MCP_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

FSB_CLK_MCP_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP

FSB_CLK_ITP_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP

FSB_CLK_ITP_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU

FSB_CLK_CPU_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU

FSB_CLK_CPU_P

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_GND

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_VCC

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_GND

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_VDD

CPU_50S

CPU_AGTL

CPU_ASYNC

FSB_DPWR_L

CPU_50S

CPU_AGTLCPU_DPRSTP_L

CPU_DPRSTP_L

CPU_50S

CPU_AGTL

CPU_FROM_SB

CPU_DPSLP_L

CPU_50S

CPU_AGTLFSB_CPUSLP_L

FSB_CPUSLP_L

CPU_50S

CPU_8MIL

PM_THRMTRIP_L

CPU_50S

CPU_AGTL

CPU_ASYNC

CPU_STPCLK_L

CPU_50S

CPU_AGTL

CPU_ASYNC

CPU_SMI_L

CPU_50S

CPU_AGTL

CPU_PWRGD

CPU_50S

CPU_AGTL

CPU_PROCHOT_L

CPU_50S

CPU_AGTL

CPU_ASYNC_R

CPU_NMI

CPU_50S

CPU_AGTL

CPU_ASYNC_R

CPU_INTR

CPU_50S

CPU_AGTL

CPU_INIT_L

CPU_50S

CPU_AGTL

CPU_ASYNC

CPU_IGNNE_L

CPU_50S

CPU_8MIL

CPU_FERR_L

CPU_50S

CPU_AGTLCPU_BSEL

CPU_BSEL<2..0>

FSB_50S

FSB_1XFSB_1X

FSB_TRDY_L

FSB_50S

FSB_1XFSB_1X

FSB_RS_L<2..0>

FSB_50S

FSB_1X

FSB_CPURST_L

FSB_50S

FSB_1XFSB_1X

FSB_HITM_L

FSB_50S

FSB_1XFSB_1X

FSB_HIT_L

FSB_50S

FSB_1XFSB_1X

FSB_DRDY_L

FSB_50S

FSB_1XFSB_1X

FSB_DEFER_L

FSB_50S

FSB_1XFSB_1X

FSB_DBSY_L

FSB_50S

FSB_1XFSB_1X

FSB_BPRI_L

FSB_50S

FSB_1XFSB_1X

FSB_BNR_L

FSB_50S

FSB_1X

FSB_BREQ1_L

FSB_50S

FSB_1X

FSB_BREQ0_L

FSB_50S

FSB_1XFSB_1X

FSB_ADS_L

FSB_50S

FSB_ADSTB

FSB_ADSTB1

FSB_ADSTB_L<1>

FSB_50S

FSB_ADDR

FSB_ADDR_GROUP1

FSB_A_L<35..17>

FSB_50S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_REQ_L<4..0>

FSB_50S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_A_L<16..3>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB3

FSB_DSTB_L_N<3>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB3

FSB_DSTB_L_P<3>

FSB_50S

FSB_DATA

FSB_DATA_GROUP3

FSB_DINV_L<3>

FSB_50S

FSB_DATA

FSB_DATA_GROUP3

FSB_D_L<63..48>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB2

FSB_DSTB_L_N<2>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB2

FSB_DSTB_L_P<2>

FSB_50S

FSB_DATA

FSB_DATA_GROUP2

FSB_DINV_L<2>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB1

FSB_DSTB_L_P<1>

FSB_50S

FSB_DATA

FSB_DATA_GROUP1

FSB_DINV_L<1>

FSB_50S

FSB_DATA

FSB_DATA_GROUP1

FSB_D_L<31..16>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB0

FSB_DSTB_L_N<0>

FSB_DSTB_50S FSB_DSTB

FSB_DSTB0

FSB_DSTB_L_P<0>

FSB_50S

FSB_DATA

FSB_DATA_GROUP0

FSB_D_L<15..0>

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

9

11

9

63

11 63

13

10 13

6

10 13

6

10 13

6

10 13

6

10

6

10 13

10

10 27

63

21 63

10

14

13 14

10 14

14

10 14

9

10 14 63

10 14

10 14 43

10 14

10 13 14

10 14 43 63

9

10 14

9

10 14

9

10

10 14

9

10 13 14

7

10 14

7

10 14

14

9

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Memory Net Properties

DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

NET_TYPE

SPACING

PHYSICAL

Memory Bus Constraints

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MCP MEM COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DDR3:

DDR2:

ELECTRICAL_CONSTRAINT_SET

*

MEM_DATA2MEM

MEM_DATA

MEM_CLK

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

*

MEM_CMD

MEM_CMD2MEM

MEM_CTRL

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

?

=3:1_SPACING

MEM_DQS2MEM

*

25 MIL

MEM_2OTHER

* ?

MEM_DATA2MEM =3:1_SPACING

* ?

MEM_CMD2MEM

* ?

=3:1_SPACING

*

MEM_DATA2DATA

?

=1.5:1_SPACING

MEM_CTRL2MEM

* ?

=2.5:1_SPACING

MEM_CLK2MEM

* ?

=4:1_SPACING

MEM_CTRL2CTRL

=2:1_SPACING

* ?

=1.5:1_SPACING

MEM_CMD2CMD

* ?

MEM_40S_VDD

=40_OHM_SE=40_OHM_SE=40_OHM_SE

=STANDARD

*

=STANDARD

=40_OHM_SE

MEM_40S

=STANDARD

*

=STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=70_OHM_DIFF=70_OHM_DIFF

*

=70_OHM_DIFF=70_OHM_DIFF

=70_OHM_DIFF

MEM_70D_VDD

=70_OHM_DIFF

=70_OHM_DIFF =70_OHM_DIFF

*

=70_OHM_DIFF =70_OHM_DIFF

MEM_70D

MEM_CMDMEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

SYNC_DATE=02/18/2008

SYNC_MASTER=MUXGFX

Memory Constraints

89 97

A.0.0

051-7892

MCP_MEM_COMP

8 MIL

* ?

=STANDARD

7 MIL7 MIL

Y

MCP_MEM_COMP

*

=STANDARD =STANDARD

MEM_DQSMEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2MEM

MEM_CLK

*

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL

MEM_DATA

*

MEM_DATA2MEM

MEM_CTRL

MEM_DATA2MEM

MEM_DATA

*

MEM_DQS

MEM_DATA

MEM_DATA2DATA

MEM_DATA

*

MEM_DATA2MEM

MEM_DATA

*

MEM_CMD

MEM_2OTHER

MEM_CLK

**

MEM_2OTHER

MEM_CTRL

* *

MEM_2OTHER

MEM_DQS

**

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_DATA

* *

MEM_CLK MEM_CLK

MEM_CLK2MEM

*

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

*

MEM_CMD

MEM_CLK2MEM

MEM_CLK

*

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_CKE<3..0>

MEM_70D_VDD

MEM_CLK

MEM_A_CLK

MEM_A_CLK_P<5..0>

MEM_40S_VDD

MEM_CTRL

MEM_A_CNTL

MEM_A_CKE<3..0>

MEM_70D_VDD

MEM_CLK

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_40S_VDD

MEM_CTRL

MEM_A_CNTL

MEM_A_ODT<3..0>

MEM_40S_VDD

MEM_CTRL

MEM_A_CNTL

MEM_A_CS_L<3..0>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_A_DM<2>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DM<3>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_A_DM<4>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_A_DM<5>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DM<6>

MEM_70D MEM_DQS

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_A_DM<1>

MEM_70D MEM_DQS

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_70D MEM_DQS

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_70D MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_70D MEM_DQS

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_70D MEM_DQS

MEM_A_DQS2

MEM_A_DQS_N<2>

MEM_70D MEM_DQS

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_70D MEM_DQS

MEM_A_DQS3

MEM_A_DQS_N<3>

MEM_70D MEM_DQS

MEM_A_DQS5

MEM_A_DQS_N<5>

MEM_70D MEM_DQS

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_70D MEM_DQS

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_70D MEM_DQS

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_A_BA<2..0>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE0

MEM_A_DM<0>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_A_CAS_L

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_A_DQ<39..32>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_A_DQ<47..40>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_B_WE_L

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DM<0>

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_B_BA<2..0>

MEM_70D MEM_DQS

MEM_B_DQS6

MEM_B_DQS_N<6>

MEM_70D MEM_DQS

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DM<7>

MEM_70D MEM_DQS

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_70D MEM_DQS

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_70D MEM_DQS

MEM_B_DQS4

MEM_B_DQS_N<4>

MEM_70D MEM_DQS

MEM_B_DQS5

MEM_B_DQS_N<5>

MEM_70D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_70D MEM_DQS

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_70D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_N<2>

MEM_70D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_70D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_70D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_70D MEM_DQS

MEM_B_DQS0

MEM_B_DQS_N<0>

MEM_70D MEM_DQS

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_70D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DM<6>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DM<5>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DM<3>

MEM_70D MEM_DQS

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_B_DM<4>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DM<2>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DM<1>

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_ODT<3..0>

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_CS_L<3..0>

MEM_70D_VDD

MEM_CLK

MEM_B_CLK

MEM_B_CLK_N<5..0>

MEM_70D_VDD

MEM_CLK

MEM_B_CLK

MEM_B_CLK_P<5..0>

MCP_MEM_COMP MCP_MEM_COMPMCP_MEM_COMP

MCP_MEM_COMP_VDD

MCP_MEM_COMP MCP_MEM_COMPMCP_MEM_COMP

MCP_MEM_COMP_GND

MEM_70D MEM_DQS

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_70D MEM_DQS

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_B_CAS_L

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_B_RAS_L

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_B_A<14..0>

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_A_A<14..0>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE7

MEM_A_DM<7>

MEM_70D MEM_DQS

MEM_A_DQS0

MEM_A_DQS_P<0>

MEM_70D MEM_DQS

MEM_A_DQS6

MEM_A_DQS_N<6>

15 29

15 28

15 29

16

15 28

15 29

15 28

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SATA Interface Constraints

- 75-ohm from output of three-pole filter to connector (if possible).

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

NET_TYPE

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

Digital Video Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

R/G/B signals should be matched as close as possible and < 10 inches.

- 50-ohm from first to second termination resistor.

- 37.5-ohm from MCP to first termination resistor.

CRT signal single-ended impedence varies by location:

Analog Video Signal Constraints

PCI-Express

MCP Constraints 1

SYNC_DATE=02/18/2008

SYNC_MASTER=MUXGFX

051-7892

A.0.0

9790

13.1 MM

=90_OHM_DIFF

*

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

PCIE_90D

* ?

MCP_PEX_COMP

8 MIL

=4:1_SPACING

CRT

* ?

=STANDARD

CRT_2CRT

?*

MCP_DAC_COMP

* ?

=2:1_SPACING

=100_OHM_DIFF

*

=100_OHM_DIFF

DP_100D

=100_OHM_DIFF=100_OHM_DIFF

TOP,BOTTOM

=4x_DIELECTRIC

?

DISPLAYPORT

?*

CRT_2CLK

50 MIL

SATA

?

TOP,BOTTOM

=3x_DIELECTRIC

SATA_100D

=100_OHM_DIFF

*

=100_OHM_DIFF

* ?

SATA_TERMP

8 MIL

=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

=3x_DIELECTRIC

* ?

DISPLAYPORT

?

=4x_DIELECTRIC

SATA

*

* ?

CRT_2SWITCHER

250 MIL

CRT_SYNC

?*

16 MIL

*

Y 20 MIL 20 MIL =STANDARD

=STANDARD =STANDARD

MCP_DV_COMP

?*

LVDS

=3x_DIELECTRIC

=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

CLK_PCIE_100D

=100_OHM_DIFF

PCIE

=4X_DIELECTRIC

TOP,BOTTOM

?

CRT_2CRT

*

CRTCRT

=50_OHM_SE

CRT_50S

=50_OHM_SE

=STANDARD

*

=STANDARD

=50_OHM_SE=50_OHM_SE

CLK_PCIE

* ?

20 MIL

* ?

=3X_DIELECTRIC

PCIE

?

LVDS

=4x_DIELECTRIC

TOP,BOTTOM

CLK_PCIE_100D

CLK_PCIE

TP_PCIE_CLK100M_EXCARD_N

DP_100D

DISPLAYPORTTMDS_IG_TXC

TMDS_IG_TXC_P

LVDS_100D

LVDS

LVDS_IG_A_CLK

LVDS_IG_A_CLK_P

DP_100D

DISPLAYPORTTMDS_IG_TXC

TMDS_IG_TXC_N

MCP_PEX_COMP

MCP_PEX_CLK_COMP

CLK_PCIE_100D

CLK_PCIE

MCP_PE3_REFCLK

TP_PCIE_CLK100M_EXCARD_P

PCIE_90D PCIE

PCIE_EXCARD_R2D_P

PCIE_90D PCIE

PCIE_EXCARD_R2D_N

PCIE_90D PCIE

PEG_R2D_P<15..0>

PCIE_90D PCIE

PEG_D2R_N<15..0>

PCIE_90D PCIE

PCIE_MINI_D2R_N

PCIE_90D PCIE

PCIE_MINI_D2R

PCIE_MINI_D2R_P

PCIE_90D PCIE

PEG_R2D_C_N<15..0>

PCIE_90D PCIE

PCIE_MINI_R2D_P

PCIE_90D PCIE

PEG_R2D

PEG_R2D_C_P<15..0>

PCIE_90D PCIE

PEG_D2R_C_P<15..0>

PCIE_90D PCIE

PEG_D2R

PEG_D2R_P<15..0>

PCIE_90D PCIE

PEG_R2D_N<15..0>

PCIE_90D PCIE

PCIE_FW_R2D_N

PCIE_90D PCIE

PCIE_FW_R2D

PCIE_FW_R2D_C_P

PCIE_90D PCIE

PCIE_FW_D2R

PCIE_FW_D2R_P

PCIE_90D PCIE

PCIE_FW_D2R_N

PCIE_90D PCIE

PCIE_FW_D2R_C_N

PCIE_90D PCIE

PCIE_EXCARD_D2R

TP_PCIE_EXCARD_D2R_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_FW_N

CLK_PCIE_100D

CLK_PCIE

MCP_PE2_REFCLK

PCIE_CLK100M_FW_P

CLK_PCIE_100D

CLK_PCIE

MCP_PE1_REFCLK

PCIE_CLK100M_MINI_P

PCIE_90D PCIE

PCIE_FW_D2R_C_P

PCIE_90D PCIE

PCIE_FW_R2D_P

PCIE_90D PCIE

PCIE_MINI_R2D_C_N

CRT_50S

CRT

CRT_RED

NC_CRT_IG_R_C_PR

CRT_50S

CRT

CRT_GREEN

NC_CRT_IG_G_Y_Y

CRT_50S

CRT

CRT_BLUE

NC_CRT_IG_B_COMP_PB

CRT_50S

CRT_SYNCCRT_SYNC

NC_CRT_IG_VSYNC

MCP_DAC_COMPMCP_DAC_RSET

NC_MCP_TV_DAC_RSET

MCP_DAC_COMPMCP_DAC_VREF

NC_MCP_TV_DAC_VREF

DP_100D

DISPLAYPORTTMDS_IG_TXD

TMDS_IG_TXD_N<2..0>

DP_100D

DISPLAYPORT

DP_ML

DP_IG_ML_P<3..0>

MCP_DV_COMP

MCP_HDMI_RSET

LVDS_100D

LVDS

LVDS_IG_A_CLK

LVDS_IG_A_CLK_N

PCIE_90D PCIE

PCIE_MINI_R2D

PCIE_MINI_R2D_C_P

PCIE_90D PCIE

PCIE_MINI_R2D_N

CRT_50S

CRT_SYNCCRT_SYNC

NC_CRT_IG_HSYNC

MCP_DV_COMP

MCP_HDMI_VPROBE

PCIE_90D PCIE

PEG_D2R_C_N<15..0>

PCIE_90D PCIE

PCIE_FW_R2D_C_N

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_N

LVDS_100D

LVDS

LVDS_IG_B_CLK

NC_LVDS_IG_B_CLKP

LVDS_100D

LVDS

LVDS_IG_B_DATA

LVDS_IG_B_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_IG_B_DATA

LVDS_IG_B_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_IG_A_DATA

LVDS_IG_A_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_IG_A_DATA

LVDS_IG_A_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_IG_A_DATA3

NC_LVDS_IG_A_DATAN<3>

LVDS_100D

LVDS

LVDS_IG_A_DATA3

NC_LVDS_IG_A_DATAP<3>

LVDS_100D

LVDS

LVDS_IG_B_DATA3

NC_LVDS_IG_B_DATAN<3>

LVDS_100D

LVDS

LVDS_IG_B_DATA3

NC_LVDS_IG_B_DATAP<3>

LVDS_100D

LVDS

LVDS_IG_B_CLK

NC_LVDS_IG_B_CLKN

DP_100D

DISPLAYPORT

DP_AUX_CH

DP_IG_AUX_CH_P

SATA_TERMP

MCP_SATA_TERMP

SATA_100D

SATA

SATA_ODD_D2R_C_N

SATA_100D

SATA

SATA_ODD_D2R_C_P

SATA_100D

SATASATA_ODD_D2R

SATA_ODD_D2R_P

SATA_100D

SATA

SATA_ODD_D2R_N

SATA_100D

SATA

SATA_ODD_R2D_P

SATA_100D

SATA

SATA_ODD_R2D_N

SATA_100D

SATA

SATA_ODD_R2D_C_N

SATA_100D

SATA

SATA_HDD_D2R_C_N

SATA_100D

SATASATA_ODD_R2D

SATA_ODD_R2D_C_P

SATA_100D

SATA

SATA_HDD_D2R_N

SATA_100D

SATA

SATA_HDD_D2R_C_P

SATA_100D

SATASATA_HDD_D2R

SATA_HDD_D2R_P

SATA_100D

SATA

SATA_HDD_R2D_P

SATA_100D

SATA

SATA_HDD_R2D_N

SATA_100D

SATASATA_HDD_R2D

SATA_HDD_R2D_C_P

SATA_100D

SATA

SATA_HDD_R2D_C_N

MCP_IFPAB_VPROBE

MCP_DV_COMP

MCP_IFPAB_RSET

CLK_PCIE_100D

CLK_PCIE

PEG_CLK100M_N

CLK_PCIE_100D

CLK_PCIE

MCP_PE0_REFCLK

PEG_CLK100M_P

PCIE_90D PCIE

TP_PCIE_EXCARD_D2R_N

PCIE_90D PCIE

PCIE_EXCARD_R2D

TP_PCIE_EXCARD_R2D_C_P

PCIE_90D PCIE

TP_PCIE_EXCARD_R2D_C_N

DP_100D

DISPLAYPORTTMDS_IG_TXD

TMDS_IG_TXD_P<2..0>

DP_100D

DISPLAYPORT

DP_ML

DP_IG_ML_N<3..0>

DP_100D

DISPLAYPORT

DP_AUX_CH

DP_IG_AUX_CH_N

9

17

18 84

17

9

17

96

71

9

71

7

17 31

7

17 31

9

71

7

31 96

9

71

9

71

36

17 36

36

9

17

17 36

17 31

36

17 31

18 25

9

81

18 25

18 84

17 31

7

31 96

18 25

71

17 36

17 31

9

18

18 84

9

18

9

18

9

18

9

18

9

18

18 81

20

7

39

7

39

20 39

7

39

7

39

20 39

7

39

20 39

7

39

20 39

7

39

7

39

20 39

18 25

17 71

9

17

9

17

9

17

9

81

18 81

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

SMBus Interface Constraints

HD Audio Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

SIO Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PHYSICAL

NET_TYPE

SPACING

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

LPC Bus Constraints

PCI Bus Constraints

ELECTRICAL_CONSTRAINT_SET

=STANDARDPCI

?*

=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

LPC_55S

*

=STANDARD

=4x_DIELECTRIC

TOP,BOTTOM

?

USB

8 MIL

?

CLK_SLOW

*

MCP_HDA_COMP

8 MIL

* ?

?*

HDA

=2x_DIELECTRIC

=55_OHM_SE=55_OHM_SE=55_OHM_SE

SMB_55S

=STANDARD=STANDARD

*

=55_OHM_SE

=90_OHM_DIFF

*

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

USB_90D

*

=STANDARD=STANDARD

=STANDARD =STANDARD

8 MIL8 MIL

MCP_USB_RBIAS

=2x_DIELECTRIC

USB

?*

SMB

* ?

=2x_DIELECTRIC

=STANDARD

=55_OHM_SE

*

CLK_PCI_55S

=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

CLK_LPC_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD

6 MIL

LPC

?*

CLK_LPC

8 MIL

* ?

MCP Constraints 2

SYNC_DATE=02/18/2008

SYNC_MASTER=MUXGFX

91 97

A.0.0

051-7892

=55_OHM_SE

SPI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

=STANDARD =STANDARD

8 MIL

?

SPI

*

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

HDA_55S

=STANDARD =STANDARD

*

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

CLK_SLOW_55S

=STANDARD=STANDARD

=55_OHM_SE

PCI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD

*

=STANDARD

8 MIL

CLK_PCI

?*

CLK_SLOW_55S CLK_SLOW

PM_CLK32K_SUSCLK

SPI_55S

SPI

SPI_MOSI

SPI_MOSI_R

SPI_55S

SPI

SPI_MOSI

SPI_55S

SPI

SPI_MISO

SPI_55S

SPI

SPI_MISO_R

SPI_55S

SPI

SPI_CS0

SPI_CS0_R_L

USB_90D

USB

USB_EXTC

NC_USB_EXTCP

USB_90D

USB

NC_USB_EXTCN

SPI_55S

SPI

SPI_CS0_L

HDA_55S

HDA

HDA_RST_L

HDA_55S

HDA

HDA_SDIN0

HDA_55S

HDA

HDA_SDOUT

USB_90D

USB

NC_USB_EXCARDN

MCP_USB_RBIASMCP_USB_RBIAS

MCP_USB_RBIAS_GND

SMB_55S

SMB

SMBUS_MCP_0_DATA

HDA_55S

HDA

HDA_BIT_CLK

SMB_55S

SMB

SMBUS_MCP_0_CLK

CLK_SLOW_55S CLK_SLOW

MCP_SUS_CLK

PM_CLK32K_SUSCLK_R

SPI_55S

SPI

SPI_CLK

SPI_55S

SPI

SPI_CLK

SPI_CLK_R

PCI_55S

PCI

PCI_AD

PCI_AD<31..25>

PCI_55S

PCI

PCI_CNTL

PCI_DEVSEL_L

PCI_55S

PCI

PCI_AD

PCI_AD<23..8>

PCI_55S

PCI

MCP_DEBUG

MCP_DEBUG<7..0>

HDA_55S

HDA

HDA_SDIN_CODEC

HDA_55S

HDA

HDA_SYNC_R

HDA_55S

HDA

HDA_RST_L

HDA_RST_R_L

HDA_55S

HDA

HDA_BIT_CLK_R

HDA_55S

HDA

HDA_SYNC

USB_90D

USB

USB_EXCARD

NC_USB_EXCARDP

USB_90D

USB

USB_EXTB_N

USB_90D

USB

USB_EXTB

USB_EXTB_P

USB_90D

USB

USB_IR_N

USB_90D

USB

USB_IR

USB_IR_P

USB_90D

USB

USB_TPAD_N

USB_90D

USB

USB_TPAD

USB_TPAD_P

USB_90D

USB

USB_BT_N

USB_90D

USB

USB_BT

USB_BT_P

USB_90D

USB

USB_CAMERA_N

USB_90D

USB

USB_CAMERA

USB_CAMERA_P

USB_90D

USB

NC_USB_EXTDN

USB_90D

USB

USB_EXTD

NC_USB_EXTDP

USB_90D

USB

NC_USB_MININ

USB_90D

USB

USB_MINI

NC_USB_MINIP

USB_90D

USB

USB_EXTA_MUXED_N

USB_90D

USB

USB_EXTA_MUXED_P

USB_90D

USB

USB_EXTA_N

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_LPCPLUS

USB_90D

USB

USB_EXTA

USB_EXTA_P

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_SMC

CLK_LPC_55S

CLK_LPC

MCP_LPC_CLK0

LPC_CLK33M_SMC_R

LPC_55S

LPC

LPC_RESET_L

LPC_55S

LPC

LPC_AD

LPC_AD<3..0>

LPC_55S

LPC

LPC_FRAME_L

CLK_PCI_55S

CLK_PCI

MCP_PCI_CLK2

PCI_CLK33M_MCP_R

CLK_PCI_55S

CLK_PCI

PCI_CLK33M_MCP

PCI_55S

PCI

PCI_INTY_L

PCI_55S

PCI

PCI_INTZ_L

PCI_55S

PCI

PCI_INTW_L

PCI_55S

PCI

PCI_INTX_L

PCI_55S

PCI

PCI_GNT1_L

PCI_55S

PCI

PCI_GNT0_L

PCI_55S

PCI

PCI_REQ1_L

PCI_55S

PCI

PCI_CNTL

PCI_FRAME_L

PCI_55S

PCI

PCI_REQ0_L

PCI_55S

PCI

PCI_CNTL

PCI_TRDY_L

PCI_55S

PCI

PCI_CNTL

PCI_SERR_L

PCI_55S

PCI

PCI_CNTL

PCI_STOP_L

PCI_55S

PCI

PCI_CNTL

PCI_PERR_L

PCI_55S

PCI

PCI_CNTL

PCI_IRDY_L

PCI_55S

PCI

PCI_AD

PCI_PAR

PCI_55S

PCI

PCI_C_BE_L

PCI_C_BE_L<3..0>

PCI_55S

PCI

PCI_AD24

PCI_AD<24>

HDA_55S

HDA

HDA_SDOUT_R

MCP_HDA_COMP

MCP_HDA_PULLDN_COMP

SMB_55S

SMB

SMBUS_MCP_1_CLK

SMB_55S

SMB

SMBUS_MCP_1_DATA

26 42

21 44

54

21 44

54

21 44

9

20

9

20

21 55

9

20

13 21 28 29 45

21 55

13 21 28 29 45

21 26

54

21 44

13 19

21

21 55

9

20

20 40

20 41

20 50

7

20 31

7

20 31

7

20 31

7

20 31

9

20

9

20

9

20

9

20

20 40

26 44

20 40

26 42

19 26

19 26 84

19 42 44 84

19

21

21 45 60 85

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

88E1116R (Ethernet PHY) Constraints

PHYSICAL

NET_TYPE

MCP RGMII (Ethernet) Constraints

SPACING

ENET_MDI

* ?

25 MIL

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF

ENET_MDI_100D

*

=STANDARD=STANDARD

ENET_MII_55S

=55_OHM_SE

=55_OHM_SE =55_OHM_SE =55_OHM_SE

MCP_MII_COMP

*

=STANDARD

7.5 MIL

=STANDARD=STANDARD

=STANDARD

7.5 MIL

MCP_BUF0_CLK

?*

=3:1_SPACING

12 MIL

ENET_MII

* ?

051-7892

A.0.0

9792

Ethernet Constraints

SYNC_MASTER=MUXGFX

SYNC_DATE=02/18/2008

MCP_MII_COMP_VDD

MCP_MII_COMP MCP_MII_COMP

ENET_RXD_R<3..0>

ENET_MIIENET_MII_55S

ENET_CLK125M_RXCLK

ENET_RXCLK

ENET_MIIENET_MII_55S

ENET_CLK125M_RXCLK_R

ENET_MIIENET_MII_55S

MCP_CLK25M_BUF0_R

MCP_CLK25M_BUF0

MCP_BUF0_CLKENET_MII_55S

MCP_MII_COMP_GND

MCP_MII_COMP MCP_MII_COMP

ENET_RX_CTRL

ENET_RXD ENET_MIIENET_MII_55S

ENET_CLK125M_TXCLK

ENET_TXCLK

ENET_MIIENET_MII_55S

ENET_TXD<3..1>

ENET_TXD ENET_MIIENET_MII_55S

ENET_TXD<0>

ENET_TXD0

ENET_MIIENET_MII_55S

ENET_RESET_L

ENET_MIIENET_MII_55S

ENET_TX_CTRL

ENET_TXD ENET_MIIENET_MII_55S

ENET_MDI_N<3..0>

ENET_MDI

ENET_MDI_100D

ENET_MDI_P<3..0>

ENET_MDI ENET_MDI

ENET_MDI_100D

ENET_RXD<3..1>

ENET_RXD_STRAP

ENET_MIIENET_MII_55S

ENET_RXD<0>

ENET_RXD ENET_MIIENET_MII_55S

ENET_MDIO

ENET_MIIENET_MII_55S

ENET_PWRDWN_L

ENET_MIIENET_MII_55S

ENET_MDC

ENET_MDC ENET_MIIENET_MII_55S

ENET_INTR_L

ENET_MIIENET_MII_55S

RTL8211_CLK25M_CKXTAL1

MCP_BUF0_CLKENET_MII_55S

18

33

18 33

33

18 34

18

18 33

33 35

18 33

33 34

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

FireWire Net Properties

SPACING

NET_TYPE

FireWire Interface Constraints

PHYSICAL

Port 2 Not Used

ELECTRICAL_CONSTRAINT_SET

SD CARD INTERFACE CONSTRAINTS

ELECTRICAL_CONSTRAINT_SET

SD CARD NET PROPERTIES

SPACING

NET_TYPE

PHYSICAL

I23

I24

I25

I26

I27

I28

I29

I30

I31

I32

*

SD_55S

=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

*

?

=3X_DIELECTRIC

SD_INTERFACE

051-7892

A.0.0

9793

FireWire Constraints

SYNC_MASTER=MUXGFX

SYNC_DATE=02/18/2008

*

=3:1_SPACING

?

FW_TP

=110_OHM_DIFF=110_OHM_DIFF

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

SD_D<0>

SD_55S

SD_DATA

SD_INTERFACE

SD_INTERFACESD_55S

SD_CLK

SD_INTERFACESD_55S

SD_CMD

SD_D<7>

SD_55S

SD_DATA

SD_INTERFACE

SD_D<6>

SD_55S

SD_DATA

SD_INTERFACE

SD_DATA

SD_D<1>

SD_INTERFACESD_55S

SD_DATA

SD_D<2>

SD_55S SD_INTERFACE

SD_D<3>

SD_55S

SD_DATA

SD_INTERFACE

SD_D<4>

SD_55S

SD_DATA

SD_INTERFACE

SD_D<5>

SD_DATA

SD_55S SD_INTERFACE

FW_110D

FW_TP

FW_P1_TPA

FW_PORT1_TPA_P

FW_110D

FW_TP

FW_P1_TPA

FW_PORT1_TPA_N

FW_110D

FW_TP

FW_P1_TPB

FW_PORT1_TPB_P

FW_110D

FW_TP

FW_P1_TPB

FW_PORT1_TPB_N

FW_110D

FW_TP

FW_P0_TPB

NC_FW0_TPBN

FW_110D

FW_TP

FW_P0_TPB

NC_FW0_TPBP

FW_110D

FW_TP

FW_P0_TPA

NC_FW0_TPAN

FW_110D

FW_TP

FW_P0_TPA

NC_FW0_TPAP

7

32

7

32

7

32

7

32

7

32

7

32

7

32

7

32

7

32

7

32

36 38

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

SYNC_DATE=02/18/2008

SYNC_MASTER=MUXGFX

SMC Constraints

94 97

A.0.0

051-7892

1TO1_DIFFPAIR

=STANDARD =STANDARD

*

0.1 MM0.1 MM

=STANDARD=STANDARD

1TO1_DIFFPAIR

CHGR_CSO_N

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI_N

SMB_55S

SMB

SMBUS_SMC_A_S3_SCL

SMB_55S

SMB

SMBUS_SMC_A_S3_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMB_55S

SMB

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMB_55S

SMB

SMBUS_SMC_BSA_SCL

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMB_55S

SMB

SMBUS_SMC_0_S0_SCL

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMB_55S

SMB

SMBUS_SMC_B_S0_SCL

62

7

31 42 45 51

7

31 42 45 51

7

42 45 61 62

27 39 42 45

7

42 45 61 62

42 45 48 53 78

42 45 48

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

G96 Net Properties

Digital Video Signal Constraints

GDDR3 FB C/D Net Properties

ELECTRICAL_CONSTRAINT_SET

(CK505_DOT96)

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

SPACING

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

MUXGFX Net Properties

PHYSICAL

NET_TYPE

SPACING

PHYSICAL

GDDR3 FB A/B Net Properties

NET_TYPE

PHYSICAL

SPACING

NET_TYPE

SPACING

From T18 MXM:

NET_TYPE

PHYSICAL

GDDR3 Frame Buffer Signal Constraints

ELECTRICAL_CONSTRAINT_SET

I138

I139

I142

I143

I144

I145

I148

I149

I152

I153

I155

I157

I158

I159

I160

I161

I182

I183

I184

I185

I190

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

I204I205

=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF

DP_100D

=100_OHM_DIFF =100_OHM_DIFF

=2.5:1_SPACING

*

GDDR3_DQS

?

=80_OHM_DIFF=80_OHM_DIFF

*

GDDR3_80D

=80_OHM_DIFF

0.095 MM

=80_OHM_DIFF

DISPLAYPORT

?*

=3x_DIELECTRIC

?

TOP,BOTTOM

DISPLAYPORT

=4x_DIELECTRIC

=3x_DIELECTRIC

LVDS

* ?

*

GDDR3_CMD

?

=2.5:1_SPACING

GDDR3_CLK

?

*

=2.5:1_SPACING

=STANDARD=STANDARD

*

GDDR3_40SE =40_OHM_SE

=40_OHM_SE

0.095 MM

GDDR3_DATA

*

?

=2.5:1_SPACING

12.7 MM

=40_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

GDDR3_40R55SE

*

0.095 MM

=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

TOP,BOTTOM

?

LVDS

=4x_DIELECTRIC

051-7892

A.0.0

9795

SYNC_DATE=02/18/2008

SYNC_MASTER=MUXGFX

GPU (G96) CONSTRAINTS

LVDS_100D

LVDS

LVDS_CONN_B_CLK_F_P

LVDS_100D

LVDS

LVDS_CONN_A_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_CONN_B_CLK_F_N

LVDS_100D

LVDS

LVDS_CONN_A_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_CONN_B_CLK_N

DP_100D

DISPLAYPORT

DP_ML_CONN_N<3..0>

DP_100D

DISPLAYPORT

DP_ML

DP_ML_CONN_P<3..0>

DP_100D

DISPLAYPORT

DP_ML

DP_ML_C_P<3..0>

DP_100D

DISPLAYPORT

DP_ML

DP_ML_P<3..0>

LVDS_100D

LVDS

LVDS_CONN_B_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_CONN_B_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_CONN_A_CLK_N

LVDS_100D

LVDS

LVDS_CONN_A_CLK_F_P

LVDS_100D

LVDS

LVDS_CONN_A_CLK_F_N

DP_100D

DISPLAYPORT

DP_AUX_CH

DP_AUX_CH_C_N

DP_100D

DISPLAYPORT

DP_AUX_CH

DP_AUX_CH_C_P

GDDR3_80D GDDR3_CLK

FB_B_CLK_P<0>

FB_C_CLK_P

GDDR3_40R55SE

GDDR3_CMD

FB_A_BA<2..0>

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_A_MA<12..6>

FB_AB_CMD

GDDR3_80D GDDR3_CLK

FB_A_CLK_P

FB_A_CLK_P<0>

GDDR3_80D GDDR3_CLK

FB_B_CLK_N<0>

GDDR3_80D GDDR3_CLK

FB_B_CLK_P<1>

FB_D_CLK_P

GDDR3_80D GDDR3_CLK

FB_B_CLK_N<1>

GDDR3_40R55SE

GDDR3_CMDFB_CD_CMD

FB_B_MA<1..0>

GDDR3_CMDFB_CD_CMD

FB_B_RAS_L

GDDR3_40R55SE

GDDR3_CMD

FB_B_WE_L

FB_CD_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_B_UCKE

FB_CD_CMD_PD

LVDS_100D

LVDS

LVDS_B_CLK

LVDS_B_CLK_N

LVDS_100D

LVDS

LVDS_A_DATA

LVDS_A_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_A_DATA

LVDS_A_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_A_CLK

LVDS_A_CLK_N

DP_100D

DISPLAYPORT

DP_ML_N<3..0>

DP_100D

DISPLAYPORT

DP_ML_C_N<3..0>

LVDS_100D

LVDS

LVDS_CONN_A_CLK_P

LVDS_100D

LVDS

LVDS_B_DATA

LVDS_B_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_B_DATA

LVDS_B_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_B_CLK

LVDS_B_CLK_P

LVDS_100D

LVDS

LVDS_A_CLK

LVDS_A_CLK_P

LVDS_100D

LVDS

LVDS_EG_A_CLK

LVDS_EG_A_CLK_N

LVDS

LVDS_EG_A_DATA

LVDS_EG_A_DATA_P<2..0>

LVDS_100D

LVDS_EG_A_CLK_P

LVDS_100D

LVDS

LVDS_EG_A_CLK

DP_100D

DISPLAYPORT

DP_ML

DP_EG_ML_P<3..0>

DP_100D

DISPLAYPORT

DP_AUX_CH

DP_EG_AUX_CH_P

LVDS_EG_B_DATA

LVDS_EG_B_DATA_P<2..0>

LVDS_100D

LVDS

DP_100D

DISPLAYPORT

DP_EG_AUX_CH_C_N

DP_100D

DISPLAYPORT

DP_EG_AUX_CH_C_P

DP_100D

DP_AUX_CH

DP_EG_AUX_CH_N

DISPLAYPORT

GDDR3_80D GDDR3_CLK

FB_A_CLK_N<1>

GDDR3_CLK

FB_B_CLK_P

FB_A_CLK_P<1>

GDDR3_80D

GDDR3_40R55SE

GDDR3_CMDFB_AB_CMD

FB_A_MA<1..0>

GDDR3_40R55SE

GDDR3_CMDFB_AB_CMD

FB_A_RAS_L

GDDR3_CMDFB_AB_CMD

FB_A_CAS_L

GDDR3_40R55SE

FB_B_DRAM_RST

GDDR3_40R55SE

FB_CD_CMD_PD

GDDR3_CMD

FB_B_LMA<5..2>

GDDR3_CMD

GDDR3_40SE

FB_C_CMD

FB_B_UMA<5..2>

GDDR3_CMD

GDDR3_40SE

FB_D_CMD

FB_B_WDQS<0>

GDDR3_DQS

GDDR3_40SEFB_C_WDQS0

FB_B_WDQS<1>

GDDR3_DQS

GDDR3_40SEFB_C_WDQS1

FB_B_WDQS<3>

GDDR3_DQS

GDDR3_40SEFB_C_WDQS3

FB_B_WDQS<2>

GDDR3_DQS

GDDR3_40SEFB_C_WDQS2

FB_B_RDQS<1>

GDDR3_DQS

GDDR3_40SEFB_C_RDQS1

FB_B_RDQS<0>

GDDR3_DQS

GDDR3_40SEFB_C_RDQS0

FB_B_RDQS<3>

GDDR3_DQS

GDDR3_40SEFB_C_RDQS3

FB_B_DQ<7..0>

GDDR3_DATAGDDR3_40SE

FB_C_DQ_BYTE0

FB_B_DQ<23..16>

GDDR3_DATAGDDR3_40SE

FB_C_DQ_BYTE2

FB_B_DQM_L<0>

GDDR3_DATAGDDR3_40SE

FB_C_DQM0

FB_B_DQ<31..24>

GDDR3_DATAGDDR3_40SE

FB_C_DQ_BYTE3

FB_B_DQM_L<2>

GDDR3_DATAGDDR3_40SE

FB_C_DQM2

FB_B_DQM_L<1>

GDDR3_DATAGDDR3_40SE

FB_C_DQM1

FB_B_WDQS<4>

GDDR3_DQS

GDDR3_40SEFB_D_WDQS0

FB_B_WDQS<7>

GDDR3_DQS

GDDR3_40SEFB_D_WDQS3

FB_B_WDQS<6>

GDDR3_DQS

GDDR3_40SEFB_D_WDQS2

FB_B_RDQS<5>

GDDR3_DQS

FB_D_RDQS1 GDDR3_40SE

FB_B_DQM_L<6>

GDDR3_DATA

FB_D_DQM2

GDDR3_40SE

FB_B_DQM_L<5>

GDDR3_DATA

FB_D_DQM1

GDDR3_40SE

FB_B_DQM_L<7>

GDDR3_DATAGDDR3_40SE

FB_D_DQM3

FB_B_RDQS<7>

GDDR3_DQS

FB_D_RDQS3 GDDR3_40SE

FB_B_RDQS<6>

GDDR3_DQS

FB_D_RDQS2 GDDR3_40SE

FB_B_DQ<47..40>

GDDR3_DATAGDDR3_40SE

FB_D_DQ_BYTE1

FB_B_DQ<39..32>

GDDR3_DATAGDDR3_40SE

FB_D_DQ_BYTE0

FB_B_DQ<55..48>

GDDR3_DATA

FB_D_DQ_BYTE2

GDDR3_40SE

FB_B_DQ<63..56>

GDDR3_DATAGDDR3_40SE

FB_D_DQ_BYTE3

FB_B_DQM_L<4>

GDDR3_DATAGDDR3_40SE

FB_D_DQM0

FB_B_RDQS<2>

GDDR3_DQS

GDDR3_40SEFB_C_RDQS2

FB_B_DQ<15..8>

GDDR3_DATAGDDR3_40SE

FB_C_DQ_BYTE1

FB_B_DQM_L<3>

GDDR3_DATAGDDR3_40SE

FB_C_DQM3

FB_B_WDQS<5>

GDDR3_DQS

GDDR3_40SEFB_D_WDQS1

FB_B_RDQS<4>

GDDR3_DQS

FB_D_RDQS0 GDDR3_40SE

FB_B_LCS0_L

GDDR3_CMD

GDDR3_40R55SE

FB_CD_CS0

FB_B_LCKE

GDDR3_40R55SE

GDDR3_CMD

FB_CD_CMD_PD

GDDR3_CMDFB_CD_CMD

FB_B_CAS_L

GDDR3_40R55SE

GDDR3_CMDFB_CD_CMD

FB_B_BA<2..0>

GDDR3_40R55SE

GDDR3_CMDFB_CD_CMD

FB_B_MA<12..6>

GDDR3_CMD

FB_A_WE_L

FB_AB_CMD

GDDR3_40R55SE

FB_A_DRAM_RST

GDDR3_CMD

GDDR3_40R55SE

FB_AB_CMD_PD

FB_A_WDQS<0>

FB_A_WDQS0

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS<2>

FB_A_WDQS2

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS3

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS<3>

FB_A_RDQS<1>

FB_A_RDQS1

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<0>

FB_A_RDQS0

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS2

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<2> FB_A_RDQS<3>

FB_A_RDQS3

GDDR3_DQS

GDDR3_40SE

FB_A_DQ<7..0>

FB_A_DQ_BYTE0

GDDR3_DATAGDDR3_40SE

FB_A_DQ_BYTE3

GDDR3_DATAGDDR3_40SE

FB_A_DQ<31..24>

FB_A_DQ<23..16>

FB_A_DQ_BYTE2

GDDR3_DATAGDDR3_40SE

FB_A_DQ<15..8>

FB_A_DQ_BYTE1

GDDR3_DATAGDDR3_40SE

FB_A_DQM_L<0>

FB_A_DQM0

GDDR3_DATAGDDR3_40SE

FB_A_WDQS<4>

FB_B_WDQS0

GDDR3_DQS

GDDR3_40SE

FB_A_DQM_L<3>

FB_A_DQM3

GDDR3_DATAGDDR3_40SE

FB_A_DQM_L<1>

FB_A_DQM1

GDDR3_DATAGDDR3_40SE

FB_A_DQM_L<2>

FB_A_DQM2

GDDR3_DATAGDDR3_40SE

FB_B_WDQS1

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS<5> FB_A_WDQS<6>

FB_B_WDQS2

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS<7>

FB_B_WDQS3

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<4>

FB_B_RDQS0

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<5>

FB_B_RDQS1

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<7>

FB_B_RDQS3

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<6>

FB_B_RDQS2

GDDR3_DQS

GDDR3_40SE

FB_B_DQ_BYTE1

GDDR3_DATAGDDR3_40SE

FB_A_DQ<47..40>

FB_B_DQ_BYTE2

GDDR3_DATAGDDR3_40SE

FB_A_DQ<55..48>

FB_B_DQM0

GDDR3_DATAGDDR3_40SE

FB_A_DQM_L<4>

FB_B_DQM2

GDDR3_DATAGDDR3_40SE

FB_A_DQM_L<6> FB_A_DQM_L<7>

FB_B_DQM3

GDDR3_DATAGDDR3_40SE

FB_A_WDQS<1>

FB_A_WDQS1

GDDR3_DQS

GDDR3_40SE

FB_B_DQ_BYTE0

GDDR3_DATAGDDR3_40SE

FB_A_DQ<39..32>

FB_B_DQ_BYTE3

GDDR3_DATAGDDR3_40SE

FB_A_DQ<63..56>

FB_B_DQM1

GDDR3_DATAGDDR3_40SE

FB_A_DQM_L<5>

CLK_SLOW_55S CLK_SLOW

GPU_CLK27M

LVDS_100D

LVDS

LVDS_EG_B_DATA

LVDS_EG_B_DATA_N<2..0>

GDDR3_80D GDDR3_CLK

FB_A_CLK_N<0>

FB_A_CMD

GDDR3_CMD

GDDR3_40SE

FB_A_LMA<5..2> FB_A_UMA<5..2>

FB_B_CMD

GDDR3_CMD

GDDR3_40SE

FB_A_LCS0_L

GDDR3_CMD

GDDR3_40R55SE

FB_AB_CS0

GDDR3_40R55SE

GDDR3_CMD

FB_AB_CMD_PD

FB_A_LCKE

GDDR3_40R55SE

FB_A_UCKE

GDDR3_CMD

FB_AB_CMD_PD

CLK_SLOW_55S CLK_SLOW

CK505_CLK27MSS

GPU_CLK27M_SS

LVDS_100D

LVDS

LVDS_EG_A_DATA

LVDS_EG_A_DATA_N<2..0>

DP_100D

DP_ML

DP_EG_ML_N<3..0>

DISPLAYPORT

LVDS_CONN_B_CLK_P

LVDS

LVDS_100D

7

80

7

80 81

7

80

7

80 81

82

7

82

81 82

7

80 81

7

80 81

7

80

7

80

81 82

73 75

73 74

73 75

81 84

81 82

82

80 81

81 84

78 84

78 81

78 84

81

78 81

73 74

73 75

73 74

76 77

78 84

73 74

76 77

78 84

78 81

80 81

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

K19 Specific Net PropertiesK19 Specific Net Properties

Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).

Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island.

(USB_EXTD) (USB_EXTD)

(USB_CAMERA)

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

PGA CONSTRAINT RELAXATIONS

(USB_CAMERA)

(USB_EXTA)

(PCIE_EXCARD)

(PCIE_MINI)

PHYSICAL

NET_TYPE

SPACINGSPACING

NET_TYPE

PHYSICAL

(USB_EXTA)

Memory Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

Graphics ,SATA Constraint Relaxations

I124

I125

I126

I127

I128

I129

I130

I133

I134

I135

I136

I137

I138

I139

I140

I141

I142

I143

I144

I145

I146

I147

I150

I151

I152

I153

I156

I157

I158

I159

I160

I161

I162

I163

I164

I165

I166

I167

I168

I169

I170

I171

I172

I173

I174

I175

I176

I177

I178

I179

I180

I181

I182

I183

I184

I185

I186

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210 I211

I212

I213

I214

I215

I216

I217

I218

I219

I220

I221

I222

I223 I224

I225

I226

I227 I228

GND

*

CLK_FSB

GND_P2MM

*

0.09 MM

5.8 MM

MEM_70D

PCIE_90D

100 MIL0.09 MM

*

MCP_MEM_COMP

0.1 MM

500 MIL

TOP

MCP_USB_RBIAS

0.1 MMTOP

500 MIL

GND

GND_P2MM

*

MEM_CMD

CPU_VCCSENSE

*

GND

GND_P2MM

500 MILUSB_90D 0.09 MM

*

MCP_DV_COMP

0.1 MM

500 MIL

TOP

0.1 MM

500 MIL

MCP_MII_COMP

TOP

*

0.09 MM 100 MIL

MEM_70D_VDD

*

MEM_40S_VDD

0.09 MM

5.8 MM

MEM_40S

*

0.09 MM

5.8 MM

FSB_DSTB GND_P2MM

*

FSB_DSTB

CPU_COMP

GND

GND_P2MM

*

BOTTOM

6.35 MMMEM_70D

0.127 MM

GND

*

LVDS

GND_P2MM

PWR_P2MM

*

SB_POWER

USB

*

PWR_P2MMSB_POWER

SATA

PWR_P2MM

*

CLK_PCIE SB_POWER

GND_P2MM

*

PCIE

GND

GND_P2MM

*

SATA

GND

GND_P2MM

*

GNDUSB

GND_P2MM

*

CLK_PCIE

GND

ENET_MDI

*

GND

GND_P2MM

*

GND

MEM_DATA

GND_P2MM

GND

MEM_CTRL

*

GND_P2MM

GND

MEM_CLK

*

1000

0.20 MM

*

PWR_P2MM

*

GND_P2MM

MEM_DQS

GND

?

*

=2:1_SPACING

AUDIO

CPU_GTLREF

GND

GND_P2MM

*

PGA

PGA_50SE

FSB_DSTB_50S

BGA

100_DIFF_BGA

SATA_100D

BGA

100_DIFF_BGA

DP_100D

BGA

100_DIFF_BGA

LVDS_100D

FSB_DSTB

PGA_CPU

PGA

*

FSB_ADDR

*

PGA_CPU

PGA

FSB_ADSTB

PGA_CPU

*

PGA

FSB_1X

PGA_CPU

*

PGA

CPU_8MIL

PGA_CPU

*

PGA

CPU_AGTL

PGA

*

PGA_CPU

PGA

*

FSB_DATA

PGA_CPU

PGA

PGA_50SE

CPU_50S

PGA_50SE

PGA

FSB_50S

PGA_50SE

=50_OHM_SE

=1:1_DIFFPAIR

0.073 MM

* Y

=50_OHM_SE

0.073 MM

ISL3,ISL10

N

MEM_70D_VDD

MCP_DV_COMP

250 MIL

*

0.25 MM

CPU_27P4S

100 MIL0.23 MM

BOTTOM

ISL4,ISL9

MEM_40S

MEM_40S_VDD

ISL3,ISL10

N

MEM_70D

ISL4,ISL9

DIFFPAIR

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

=STANDARD

GND

?

*

GND_P2MM

1000

*

0.20 MM

=STANDARDPP1V8_MEM

*

?

25 MILS

*

?

ENETCONN

?

THERM

*

=2:1_SPACING

*

?

SENSE

=2:1_SPACING

THERM_1TO1_55S

=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

SENSE_1TO1_55S

=55_OHM_SE

=1:1_DIFFPAIR

=55_OHM_SE

*

=1:1_DIFFPAIR

=55_OHM_SE

Project Specific Constraints

SYNC_DATE=02/21/2008

SYNC_MASTER=MUXGFX

96 97

A.0.0

051-7892

USB_LT2_N

USB

USB_90D

ENETCONN_N<3..0>

ENETCONN

ENET_MDI_100D

SATA_ODD_R2D_UF_P

SATA

SATA_100D

SATA_HDD_D2R_UF_P

SATA

SATA_100D

SATA_HDD_R2D_UF_N

SATA

SATA_100D

SATA_HDD_D2R_UF_N

SATA

SATA_100D

USB2_EXTA_MUXED_P

USB_90D

USB

SATA_ODD_D2R_UF_N

SATA

SATA_100D

THERM_1TO1_55S

CPU_THERMD_P

CPU_THERMD_DP

THERM

GFXIMVP6_VSEN_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

PCIE_MINI_R2D_N

PCIEPCIE_90D

PCIE_MINI_R2D_P

PCIEPCIE_90D

PCIE_EXCARD_R2D_N

PCIEPCIE_90D

PCIE_CLK100M_MINI_CONN_P

CLK_PCIE

CLK_PCIE_100D

SATA_HDD_R2D_UF_P

SATA

SATA_100D

THERM

THERM_1TO1_55S

CPU_THERMD_N

PCIE_EXCARD_R2D_P

PCIEPCIE_90D

AUDIO

DIFFPAIR

SPKRAMP_S_OUT_P

USB2_LT1_P

USB

USB_90D

USB

USB_90D

USB_CAMERA_CONN_P

PCIE_CLK100M_MINI_CONN_N

CLK_PCIE

CLK_PCIE_100D

CHGR_CSI_R_P

1TO1_DIFFPAIR

CHGR_CSI_R_N

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

CHGR_CSO_R_N

1TO1_DIFFPAIR

USB2_EXTA_MUXED_N

USB_90D

USB

USB_90D

USB2_LT1_N

USB

USB_90D

USB_TPAD_R_P

USB

USB_90D

USB_CAMERA_CONN_N

USB

USB_90D

CONN_USB2_BT_P

USB_CARDREADER

USB_90D

USB

USB_CARDREADER_P

USB

USB_90D

USB_CARDREADER_N

USB

USB_90D

USB_TPAD_R_N

GFXIMVP6_VSEN_N

SENSE

SENSE_1TO1_55S

THERM_1TO1_55S

CPUTHMSNS_D2_N

THERM

SENSE

SENSE_1TO1_55S

GPUISENS_N

SATA_ODD_D2R_UF_P

SATA

SATA_100D

SATA_ODD_R2D_UF_N

SATA

SATA_100D

ENETCONN_P<3..0>

ENETCONN

ENET_MDI_100D

ISNS_1V5_S3_N

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_N

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_R_N

SENSE_1TO1_55S

SENSE

ISNS_ODD_R_N

CPUVTT_ISNS_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

SENSE_DIFFPAIR

SENSE

ISNS_1V5_S3_R_P

SENSE_1TO1_55S

ISNS_AIRPORT_R_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_1V5_S3_P

SENSE

SENSE_1TO1_55S

ISNS_1V5_S3_R_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

PP3V3_S0

SB_POWER

SENSE_DIFFPAIR

SENSE

P1V8GPU_P

SENSE_1TO1_55S

SENSE

CPUVTT_ISNS_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

GPUISENS_P

CPUVTTISNS_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

THERM_1TO1_55S

THERM

GPU_TDIODE_N

THERM

GPU_THERMD_DP

GPU_TDIODE_P

THERM_1TO1_55S

THERM

GPUTHMSNS_D_N

THERM_1TO1_55S

GPUTHMSNS_D_P

GPUTHMSNS_D_DP

THERM

CPUTHMSNS_D2_DP

THERM

THERM_1TO1_55S

CPUTHMSNS_D2_P

THERM

MCPTHMSNS_D_DP THERM_1TO1_55S

MCPTHMSNS_D_P

THERM_1TO1_55S

MCPTHMSNS_D_N

THERM

MCP_THMDIODE_N

THERM

THERM_1TO1_55S

CPUVTTISNS_R_N

SENSE

SENSE_1TO1_55S

THERM

MCP_THMDIODE_P

THERM_1TO1_55S

MCP_THERMD_DP

SENSE

SENSE_1TO1_55S

ISNS_HDD_N

DISPLAYPORT

DP_100D

DP_IG_AUX_CH_C_P

DISPLAYPORT

DP_100D

DP_IG_AUX_CH_C_N

DIFFPAIR

AUDIO

SPK_OUT

SPKRCONN_L_OUT_P

AUDIO

DIFFPAIR

SPKRCONN_L_OUT_N

DIFFPAIR

SPK_OUT

AUDIO

SPKRCONN_S_OUT_P

SPK_OUT

AUDIO

DIFFPAIR

SPKRCONN_R_OUT_P

DIFFPAIR

AUDIO

SPKRCONN_R_OUT_N

AUDIO

DIFFPAIR

SPKRAMP_L_OUT_N

AUDIO

DIFFPAIR

SPKRAMP_R_OUT_N

AUDIO

DIFFPAIR

SPKRAMP_L_OUT_P

USB

USB_90D

CONN_USB2_BT_N USB_LT2_P

USB

USB_90D

AUDIO

DIFFPAIR

SPKRCONN_S_OUT_N

AUDIO

DIFFPAIR

SPKRAMP_R_OUT_P

AUDIO

DIFFPAIR

SPKRAMP_S_OUT_N

SENSE

SENSE_1TO1_55S

ISNS_ODD_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_ODD_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_ODD_R_P

SENSE

SENSE_1TO1_55S

ISNS_HDD_P

SENSE_DIFFPAIR

SENSE

ISNS_HDD_R_P

SENSE_1TO1_55S SENSE_1TO1_55S

ISNS_HDD_R_N

SENSE

P1V8GPU_N

SENSE

SENSE_1TO1_55S

ISNS_CPU_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_CPU_N

SENSE

PP3V3_S5

SB_POWER

P1V8GPUISNS_R_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

P1V8GPUISNS_R_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

GND

40

35

39

40

7

39

10 48

79

7

31 90

7

31 90

90

7

31

39

10 48

90

58

40

7

31

7

31

62

46 62

40

50

7

31

7

31

9

20 32

9

20 32

50

79

48

47

7

39

35

53 65

53 85

53

47 67

53

53 65

53

6 7 8

13 18 19 21 22 24

25 28 29 37 39 43 45 47

48 49 51 55 59 60 63 68

69 70 77 80 81 82 84 85

47

47 67

47

48 76 77

48

21 48

47

21 48

39 53

81

7

58 59

7

58 59

7

58 59

7

58 59

7

58 59

58

7

31

40

7

58 59

58

39 53

53

39 53

53

47

46

7 8

18 20 22 24 26 30 34

37 38 44 54 64 68 69 70

82 87

47

31 53

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

K19 Board-Specific Spacing & Physical Constraints

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

NOTE:From T18 MLB, changed to reflect M99 stackup.

0.095 MM

TOP,BOTTOM

0.165 MM

Y

40_OHM_SE

2.5:1_SPACING

0.25 MM

*

?

0.15 MM

*

?

1.5:1_SPACING

0.4 MM

4:1_SPACING

*

?

0.3 MM

3:1_SPACING

*

?

0.280 MM

*

4X_DIELECTRIC

?

3X_DIELECTRIC

0.210 MM

* ?

CLK_SLOW

*

BGA_P2MM

BGA

BGA_P2MM

BGA

CLK_PCIE

*

0.1 MM

DEFAULT

?

=DEFAULTSTANDARD

*

?

0.140 MM

?*

2X_DIELECTRIC

0.170 MM

0.150 MM 0.150 MM

TOP,BOTTOM

Y

70_OHM_DIFF

0.095 MM

0.150 MM0.150 MM

0.170 MM

Y

70_OHM_DIFF

ISL2,ISL11

0.170 MM

=STANDARD

*

70_OHM_DIFF

N

=STANDARD

=STANDARD=STANDARD=STANDARD

=STANDARD

N*

90_OHM_DIFF

0.102 MM

ISL3,ISL4

90_OHM_DIFF

Y

0.102 MM

0.220 MM 0.220 MM

0.102 MM 0.102 MM

0.220 MM

ISL9,ISL10

90_OHM_DIFF

Y

0.220 MM

0.115 MM

90_OHM_DIFF

ISL2,ISL11

Y

0.115 MM

0.230 MM 0.230 MM

0.115 MM

90_OHM_DIFF

TOP,BOTTOM

Y

0.230 MM0.230 MM

0.095 MM

=STANDARD =STANDARD

100_OHM_DIFF

* N

=STANDARD=STANDARD

=STANDARD

0.080 MM

Y

ISL3,ISL4

100_OHM_DIFF

0.200 MM0.200 MM

0.080 MM

0.200 MM

0.080 MM

0.200 MM

Y

100_OHM_DIFF

ISL9,ISL10

0.080 MM

0.095 MM0.310 MM

27P4_OHM_SE

Y

TOP,BOTTOM

0.160 MM0.160 MM

0.175 MM0.175 MM

Y

70_OHM_DIFF

ISL3,ISL4

0.077 MM

0.330 MM

Y

0.077 MM

110_OHM_DIFF

0.330 MM

ISL9,ISL10

0.089 MM

Y

100_OHM_DIFF

ISL2,ISL11

0.220 MM 0.220 MM

0.089 MM

0.089 MM 0.089 MM

TOP,BOTTOM

100_OHM_DIFF

Y

0.220 MM0.220 MM

0.330 MM

0.077 MM

ISL3,ISL4

0.077 MM

110_OHM_DIFF

0.330 MM

Y

=STANDARD

=STANDARD =STANDARD

110_OHM_DIFF

*

=STANDARD

N

=STANDARD

0.250 MM0.250 MM

27P4_OHM_SE

Y*

=STANDARD

5X_DIELECTRIC

0.350 MM

* ?

0.160 MM0.160 MM

0.175 MM 0.175 MM

Y

70_OHM_DIFF

ISL9,ISL10

0.135 MM

=STANDARD

0.135 MM

=STANDARD

*

40_OHM_SE

Y

0.180 MM0.180 MM

0.125 MM0.125 MM

Y

ISL3,ISL4

80_OHM_DIFF

0.180 MM 0.180 MM

0.125 MM0.125 MM

80_OHM_DIFF

Y

ISL9,ISL10

0.140 MM

0.190 MM0.190 MM

0.140 MM

80_OHM_DIFF

ISL2,ISL11

Y

0.190 MM 0.190 MM

0.140 MM

80_OHM_DIFF

TOP,BOTTOM

Y

0.095 MM

=STANDARD

N

=STANDARD

80_OHM_DIFF

*

=STANDARD

0.077 MM

ISL2,ISL11

110_OHM_DIFF

Y

0.330 MM 0.330 MM

0.077 MM

Y

110_OHM_DIFF

TOP,BOTTOM

0.077 MM 0.077 MM

0.330 MM 0.330 MM

0.075 MM

0.125 MM 0.125 MM

Y

ISL9,ISL10

0.075 MM

100_DIFF_BGA

0.075 MM

0.125 MM 0.125 MM

ISL3,ISL4

Y

0.075 MM

100_DIFF_BGA

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF

100_DIFF_BGA

Y

TOP,BOTTOM

50_OHM_SE

0.095 MM0.110 MM

=STANDARD=STANDARD

0.090 MM

* Y

50_OHM_SE =STANDARD

0.090 MM

*

2:1_SPACING

0.2 MM

?

0.18 MM

*

?

1.8:1_SPACING

=DEFAULTBGA_P1MM

?

*

CLK_FSB

BGA

BGA_P2MM

*

BGA

*

BGA_P2MM

MEM_CLK

BGA

BGA_P1MM

* *

0.090 MM

55_OHM_SE

TOP,BOTTOM

Y

0.090 MM

?

*

=DEFAULTBGA_P2MM

*

=DEFAULT

?

BGA_P3MM

FSB_DSTB BGA_P3MMFSB_DSTB

BGA

PGA_CPU

*

0.073 MM

?

0.076 MM

=STANDARD

*

=STANDARD

55_OHM_SE

Y

0.076 MM

=STANDARD

97 97

A.0.0

051-7892

SYNC_MASTER=M99_MLB

SYNC_DATE=01/22/2008

PCB Rule Definitions

=STANDARD =STANDARD

0.1 MM 0.1 MM

Y*

1:1_DIFFPAIR

=STANDARD

=DEFAULT =DEFAULT

*

=DEFAULT

STANDARD

Y

10 MM

=DEFAULT

33.6 MM

=50_OHM_SE

0 MM

DEFAULT

0 MM

* Y

=50_OHM_SE

NO_TYPE,BGA,PGA

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

15.5.1

MM

Apple A1386 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual