Apple A1370 Schematic Rev2.5.0

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

K78 MLB SCHEMATIC

Schematic / PCB #’s

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

PRODUCT SAFETY REQUIREMENTS:

04/08/11

1 OF 74

051-8871

2.5.0

1 OF 109

2011-04-08

High Side Current Sensing

54

12/13/2010

45

K21_MLB

Voltage & Load Side Current Sensing

53

12/13/2010

44

K21_MLB

SMBus Connections

52

12/13/2010

43

K21_MLB

LPC+SPI Debug Connector

51

12/13/2010

42

K21_MLB

SMC Support

50

12/13/2010

41

K21_MLB

SMC

49

12/13/2010

40

K21_MLB

LIO CONNECTORS

47

N/A

39 N/A

External USB Connectors

46

12/13/2010

38

K21_MLB

SATA CONNECTOR

45

12/13/2010

37

K21_MLB

X21 WIRELESS CONNECTOR

40

12/13/2010

36

K21_MLB

T29 Power Support

38

12/13/2010

35

K21_MLB

T29 Host (2 of 2)

37

12/13/2010

34

K21_MLB

T29 Host (1 of 2)

36

12/13/2010

33

K21_MLB

DDR3 DRAM Channel B (32-63)

34

12/13/2010

32

K21_MLB

FSB/DDR3/FRAMEBUF Vref Margining

33

12/13/2010

31

K21_MLB

DDR3 DRAM CHANNEL B (32-63)

32

12/13/2010

30

K21_MLB

DDR3 DRAM CHANNEL B (0-31)

31

12/13/2010

29

K21_MLB

DDR3 DRAM CHANNEL A (32-63)

30

12/13/2010

28

K21_MLB

DDR3 DRAM CHANNEL A (0-31)

29

12/13/2010

27

K21_MLB

CPU Memory S3 Support

28

12/13/2010

26

K21_MLB

Clock (CK505) and Chipset Support

27

11/30/2010

25

K21_MLB

USB HUBS

26

12/13/2010

24

K21_MLB

CPU & PCH XDP

25

12/13/2010

23

K21_MLB

PCH DECOUPLING

24

12/13/2010

22

K21_MLB

PCH GROUNDS

23

12/13/2010

21

K21_MLB

PCH POWER

22

12/13/2010

20

K21_MLB

PCH MISC

21

12/13/2010

19

K21_MLB

PCH PCI/FLASHCACHE/USB

20

12/13/2010

18

K21_MLB

PCH DMI/FDI/GRAPHICS

19

12/13/2010

17

K21_MLB

PCH SATA/PCIE/CLK/LPC/SPI

18

12/13/2010

16

K21_MLB

CPU DECOUPLING-II

17

12/13/2010

15

K21_MLB

CPU DECOUPLING-I

16

12/13/2010

14

K21_MLB

CPU GROUNDS

14

12/13/2010

13

K21_MLB

CPU POWER

13

12/13/2010

12

K21_MLB

CPU DDR3 INTERFACES

12

12/13/2010

11

K21_MLB

CPU CLOCK/MISC/JTAG

11

12/13/2010

10

K21_MLB

CPU DMI/PEG/FDI/RSVD

10

12/13/2010

9

K21_MLB

Signal Aliases

9

05/15/2010

8

K91_MLB

Power Aliases

8

05/15/2010

7

K91_MLB

Functional Test / No Test

7

(02/16/2010)

6 (K99_MLB)

BOM Configuration

5

11/16/2010

5

K21_MLB

K78 BOM Variants

4

11/16/2010

4

K21_MLB

Power Block Diagram

3

19/01/2011

3

System Block Diagram

2

12/11/2009

2 K6_MLB

PCB Rule Definitions

CONSTRAINTS

04/06/2011

74

109

Project Specific Constraints

CONSTRAINTS

04/06/2011

73

108

SMC Constraints

CONSTRAINTS

04/06/2011

72

106

T29 Constraints

CONSTRAINTS

04/06/2011

71

105

Ethernet/FW Constraints

CONSTRAINTS

04/06/2011

70

104

PCH Constraints 2

CONSTRAINTS

04/06/2011

69

103

PCH Constraints 1

CONSTRAINTS

04/06/2011

68

102

Memory Constraints

CONSTRAINTS

04/06/2011

67

101

CPU Constraints

CONSTRAINTS

04/06/2011

66

100

LCD Backlight Driver

K21_MLB

12/13/2010

65

97

DisplayPort/T29 A Connector

K21_MLB

12/13/2010

64

94

DisplayPort/T29 A MUXing

K21_MLB

12/13/2010

63

93

Internal DisplayPort Connector

K21_MLB

12/13/2010

62

90

Power Control 1/ENABLE

K21_MLB

12/13/2010

61

79

Power FETs

K21_MLB

12/13/2010

60

78

Misc Power Supplies

K21_MLB

12/13/2010

59

77

CPU VCCIO (1.05V) Power Supply

K21_MLB

12/13/2010

58

76

CPU IMVP7 & AXG VCore Output

K21_MLB

12/13/2010

57

75

CPU IMVP7 & AXG VCore Regulator

K21_MLB

12/13/2010

56

74

1.5V DDR3 Supply

K21_MLB

12/13/2010

55

73

5V / 3.3V Power Supply

K21_MLB

11/30/2010

54

72

System Agent Supply

K21_MLB

12/13/2010

53

71

PBus Supply & Battery Charger

K21_MLB

11/30/2010

52

70

DC-In & Battery Connectors

K21_MLB

11/11/2010

51

69

AUDI0: SPEAKER AMP

K21_MLB

12/13/2010

50

62

SPI ROM

K21_MLB

12/13/2010

49

61

IPD / KBD Backlight

K21_MLB

12/13/2010

48

57

Fan

K21_MLB

12/13/2010

47

56

Table of Contents

1

MASTER

1 MASTER

Thermal Sensors

K21_MLB

12/13/2010

46

55

SCHEM,MLB,K78

051-8871

1

SCH

CRITICAL

PCBF,MLB,K78

820-3024

1

PCB

CRITICAL

LAST_MODIFIED=Fri Apr 8 10:21:51 2011

ABBREV=DRAWING

TITLE=MLB

Page

Contents

(.csa)

Date

Sync

Contents

Date

Page

(.csa)

Sync

SCHEM,MLB,K78

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DISPLAY

CONN

PG 16

INTEL PCH

JTAG

U6620

PG 10

PG 29,30

SANDYBRIDGE SFF

DMI

PG 19

USB

J4700

PG 11

LINE IN

PG 8

FILTER

AMP

FILTER

HEADPHONE

LINE INSPEAKER

SPEAKER

LEFT

USB

XDP CONN

PCIE

0

DDR3-1066/1333MHZ

SERIAL

SMB_B/0

ADC

FAN0

PG 52

J5100

JTAG

J2500

XDP CONN

RIGHT

64-Bit

PG 16

MISC

CTRL

DP OUT

3

PG 23

DMI

PM_SLP S3/S4

PORT

MEMORY

U3100,3230

SPI

PG 9

64-Bit

BOOTROM

J5700

EXT

USBUSB

CAM

10

PG 24

HUB-2

USB

U2650

5 1

U1800

U2600

USB

PG 24

PWR

B

A

U1000

PG 9

MEMORY

LID

J6903

RIGHT

SMB_A

U4900

MEMORY

U6100

PG 15

GPIO

PG 11

J4610

PCH

PG 23

J4001

T29

1

U9390

DISPLAY PORT+

MUX

J9400

DP

U3600

T29 ROUTER

PG 9

LVDS OUT

PG 16

I2C

SPK

J6702

PG 9

CONN

PG 10

U6201

J6700

JACK

HEADPHONE/

HDA

J4702

CONN

4

FDI

PG 9

FDI

PG 10

CPU

1.6 GHZ

PG 17

SMB

PG 16

CLOCK

PCI

PG 18PG 16

PG16

PG 17PG 17

PG 18

13

EDP OUT

TMDS OUT

RGB OUT

PG 27,38

PG 25

9

HDA

67 2

PG 52-60

POWER CIRCUITRY

TEMP SENSOR

1G/2GB

SATA

RTC

BUFFER

PG 17

12

8

DVI OUT

U2700

J4501

J9000

PCIE

1G/2GB

U2900,U3030

EDP

LPC

INTERNAL

SPEAKER

EFFECT

PG 51

HALL

J6955

SMC

SMB_BSA

DDR3-1066/1333MHZ

CONN

WIRELESS

X21

11

PG 36

HDMI OUT

COUGAR POINT

0

HUB-1

J4600

EXT USB

CONN

PG 37

PG 38

PG 39

PG 40

PG 42

VOLTAGE/CURRENT SENSOR

PG 45

FAN CONN

PG 46

U7000

CHARGER

J5600

CONN

PG 47

CONN

LPC+SPI

PG 48

IPD FLEX

U6210

SPEAKER

AMP

PG 49

CONN

PG 50

EXT USB

LEFT

J4610

PG 51

SYSTEM

CLOCK

SSD

CONN

PCIE

PG 34,35

PG 62

CONN

PG 63

PG 64

PG 5

LIO BOARD

PG 6

LEFT I/O CONN

PG 16

AUDIO CODEC

CAMERA+ALS

PG 7

INTEL CPU

SYNC_DATE=12/11/2009

System Block Diagram

SYNC_MASTER=K6_MLB

2 OF 109

2.5.0

051-8871

2 OF 74

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

K78/K21 POWER SYSTEM ARCHITECTURE

PPVIN_S5_P5VP3V3

EN2

TPS51980

PP3V3_SUS_FET

PPDCIN_G3H_OR_PBUS

AC

2S3P

(6 TO 8.4V)

PPVBATT_G3H_CONN

14-1

P5VS3_PGOOD

P5V_3V3_SUS_EN

P3V3S3_EN

PG 17

P5VS3_EN

P3V3S3_EN

DDRREG_EN

DELAY

RC

SLP_S4#(H4)

(PAGE 17~21)

P5VS0_EN

P3V3S5_PGOOD

P1V8S0_PGOOD

CPUIMVP_AXG_PGOOD

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

ALL_SYS_PWRGD

10-3

8

14

P5VS3_PGOOD

PP1V05_S0_LDO.

PP1V5S0_EN

EN

TPS72015

U7780

(PAGE 60)

Q7840

VIN

2

R5400

PP5V_S0_CPUVCCIOS0.

1.05V

22

25-1

(PAGE 59)

P3V3S5_PGOOD

VIN

PPVCCSA_S0_REG

23

PPVTT_S0_DDR_LDO

VOUT1

27

DDRREG_PGOOD

U7801

16

VOUT

9

14-1

Q9706

13-1

P3V3S5_EN

U7201

(PAGE 55)

PP5V_S3_REG

PP5V_SUS_FET

Q7810

U7740

CPU_VCCSA_VID<1>

23-1

V

U7100

PVCCSA_PGOOD

PP3V3_S5

PP3V3_S5_REG

S3

PP5V_S0_FET

10-4

PP1V05_S0_VMON

A

SMC_BATT_ISENSE

PPVBAT_G3H

15

CPUVCCIOS0_EN

ISL6259HRTZ

T29BST_EN_UVLO

EN/UVLO

DELAY

RC

CPUVCCIOS0_EN

21

P3V3S0_EN

14-1

PPBUS_SW_LCDBKLT_PWR

Q3880

PBUSVSENS_EN

(PAGE 36)

(PAGE 60)

PM_SLP_S3_L

RC

14

14-1

BKLT_PLT_RST_L

7

13

P5VS3_EN

PG62

13-2

LCD_BKLT_EN

P5V_3V3_SUS_EN

PG62

15

VIN

PG 17

VOUT2

P5V_3V3_SUS_EN

Q7820

(PAGE 66)

U9701

F7040

24

DELAY

R7978

SMC_RESET_L

F6905 6A FUSE

SMC_CPU_VSENSE

22-1

V

U7960

ISL88042IRTEZ

V3MON

V2MON

R7962

VDD

4

6

V4MON

(PAGE 62)

PP1V5_S3RS0_VMON

PP5V_S0_VMON

PPVCORE_S0_CPU_REG

25

U1800

RESET*

S5_PWRGD

SLP_S5_L(P95)

SMC

25

15

P17(BTN_OUT)

A

26

12

PLT_RERST_L

PM_DSW_PWRGD

CPUIMVP_VR_ON

Q7860

SLP_S3#(F4)

1V05_S0_LDO_EN

P1V8S0_EN

P1V5S0_EN

PVCCSA_EN

U3890

LT3957

T29_A_HV_EN

PP15V_T29_REG

LP8550

VIN

5V

(R/H)

VOUT1

VOUT

SLP_SUS#

(L/H)

29

PM_RSMRST_L

PM_PWRBTN_L

PM_MEM_PWRGD

CPU_PWRGD

30

10

P15

(PAGE 17~21)

RSMRST#

SYS_RERST#

COUGAR-POINT

PWRBTN#

SYSRST(PA2)

PROCPWRGD

RES*

PLTRST#

DRAMPWROK

SM_DRAMPWROK

UNCOREPWRGOOD

4

PP1V05_T29_FET

T29_PWR_EN

SMC POWER

SN0903048

R5330

R5320

ENABLE

PP3V42_G3H_REG

PGOOD

3.425V G3HOT

VOUT

VCC

U7400

U7600

EN

21

D6905

R6920

(PCH)

26-1

RSMRST_IN(P13)

PWRGD(P12)

(PAGE 41)

SLP_S3_L(P93)

SLP_S4_L(P94)

9

PM_SLP_S5_L

PGOOD

VIN

(PAGE 56)

EN

VCC

PVCCSA_EN

Q7830

PGOOD

PPVIN_G3H_P3V42G3H

VOUT

PBUS SUPPLY/

R6905

J6900

EN1

Q7055

7

11

PG 17

PG61

EN

VOUT

VIN

F9700

&&

PG62

13

PG62

PBUSVSENS_EN

PM_SLP_S4_L

SMC

U4900

6

U7940

RC

DELAY

PM_SLP_SUS_L

(PAGE 41)

P60

(PCH)

COUGAR-POINT

U1800

PM_SLP_S3_R_L

P5VS0_EN

22

21

19

17

DELAY

RC

DELAY

RC

DELAY

SMC_RESET_L

PP3V3_S0_VMON

Q5300

PP3V3_S3_FET

18

U7770

TPS720105

EN

ISL8014A

TPS22924

U7720

PP3V3_S0

P1V8_S0_EN

17

U3810

14

P3V3S0_EN

T29_PWR_EN

19

(PAGE 36)

PM_SYSRST_L

PM_DSW_PWRGD

28

CHGR_BGATE

SMC_DCIN_ISENSE

VIN

4

U7000

1

PPVBAT_G3H_CHGR_R

(PAGE 53)

DCIN(14.5V)

ADAPTER

IN

J6950

BATTERY CHARGER

R7020

R7050

1

3

LT3470A

U6990

U5010

(PAGE 42)

CPU

5

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

CPUIMVP_VR_ON

PM_SYSRST_L

4

PM_PWRBTN_L

PWR_BUTTON(P90)

SMC_ONOFF_L

99ms DLY

PM_RSMRST_L

6-1

PM_SLP_S4_L

PM_SLP_S3_L

PM_SLP_S5_L

SMC_PM_G2_EN

P3V3S5_EN

3.3V

PPVOUT_SW_LCDBKLT

SMC_PBUS_VSENSE

EN

TPS720105

(PAGE 60)

PP1V05_SUS_LDO

VOUT

ISL95870

(PAGE 52)

(PAGE 9~15)

VR_ON

10-1

SLP_S5#(E4)

16-1

VOUT2

SMC_RESET_L

22

10-2

16

PP3V3_T29_FET

EN

PP1V5_S0_REG

PP1V5_S3RS0_FET

U2850

U1000

PM_PCH_PWRGD

R7140

P1V5CPU_EN

PGOOD

ISL95870A

(PAGE 54)

PGOOD

VID1

MAX15092GTL

CPU VCORE

VLDOIN

PGOODG

CPUIMVP_AXG_PGOOD

1.5V

0.75V

TPS51916

U7300

CPUIMVP_PGOOD

SMC_GFX_VSENSE

PPVCORE_S0_AXG_REG

26

R7350

A

(PAGE 60)

1V05_S0_LDO_EN

PP1V8_S0_REG

A

CPUVCCIOS0_PGOOD

(PAGE 57)

S5

PP5V_S0_VCCSA

DPWROK

TPS22924

U3816/U3815

(PAGE 36)

EN

R7640

SMC_CPU_FSB_ISENSE

PPCPUVCCIO_S0_REG

PPDDR_S3_REG

DDRVTT_EN

DDRREG_EN

PPBUS_G3H

A

U4900

P1V8S0_PGOOD

Power Block Diagram

SYNC_DATE=19/01/2011

3 OF 109

2.5.0

051-8871

3 OF 74

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEEE #’s

BOM Variants

Sub-BOMs

LABEL,LIO,K99

825-7563 CRITICAL

1

EEEE:DK9L

[EEEE_DK9L]

LABEL,LIO,K99

825-7563 CRITICAL

1

[EEEE_DLCL]

EEEE:DLCL

LABEL,LIO,K99

825-7563

[EEEE_DLCQ]

CRITICAL

1

EEEE:DLCQ

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCR]

EEEE:DLCR

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCT]

EEEE:DLCT

SYNC_MASTER=K21_MLB

SYNC_DATE=11/16/2010

K78 BOM Variants

LABEL,LIO,K99

825-7563 CRITICAL

1

[EEEE_DLCM]

EEEE:DLCM

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCN]

EEEE:DLCN

LABEL,LIO,K99

825-7563 CRITICAL

1

[EEEE_DLCP]

EEEE:DLCP

639-1808

PCBA,MLB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DK9L,DDR3:HYNIX_2GB

639-1990

PCBA,MLB,1.6GHZ,SA 2GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCT,DDR3:SAMSUNG_2GB

639-1987

PCBA,MLB,1.6GHZ,MI 2GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCP,DDR3:MICRON_2GB

639-1999

PCBA,MLB,1.6GHZ,SA 4GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLD6,DDR3:SAMSUNG_4GB

639-1995

PCBA,MLB,1.6GHZ,EL 4GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLD1,DDR3:ELPIDA_4GB

639-1998

PCBA,MLB,1.5GHZ,HY 2GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLD4,DDR3:HYNIX_2GB

PCBA,MLB,1.5GHZ,HY 4GB,K78

639-1991

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCV,DDR3:HYNIX_4GB

639-1986

PCBA,MLB,1.5GHZ,SA 2GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCN,DDR3:SAMSUNG_2GB

639-1985

PCBA,MLB,1.5GHZ,SA 4GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCM,DDR3:SAMSUNG_4GB

PCBA,MLB,1.5GHZ,MI 2GB,K78

639-1992

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCW,DDR3:MICRON_2GB

639-1993

PCBA,MLB,1.5GHZ,EL 4GB,K78

K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCY,DDR3:ELPIDA_4GB

PCBA,MLB,1.4GHZ,HY 2GB,K78

639-1994

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD0,DDR3:HYNIX_2GB

PCBA,MLB,1.4GHZ,HY 4GB,K78

639-1988

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLCQ,DDR3:HYNIX_4GB

639-1997

PCBA,MLB,1.4GHZ,SA 2GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD3,DDR3:SAMSUNG_2GB

639-1984

PCBA,MLB,1.4GHZ,SA 4GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLCL,DDR3:SAMSUNG_4GB

607-8084

K78_COMMON

CMN PTS,PCBA,MLB,K78

639-2000

PCBA,MLB,1.4GHZ,MI 2GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD5,DDR3:MICRON_2GB

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCV]

EEEE:DLCV

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD0]

EEEE:DLD0

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD2]

EEEE:DLD2

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD4]

EEEE:DLD4

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD6]

EEEE:DLD6

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD5]

EEEE:DLD5

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD3]

EEEE:DLD3

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLD1]

EEEE:DLD1

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCY]

EEEE:DLCY

LABEL,LIO,K99

825-7563

1

CRITICAL

[EEEE_DLCW]

EEEE:DLCW

639-1989

PCBA,MLB,1.6GHZ,HY 4GB,K78

K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCR,DDR3:HYNIX_4GB

DEVEL_BOM

K78 MLB DEVELOPMENT BOM

1

DEVEL

CRITICAL085-2714

K78_CMNPTS

CMN PTS,PCBA,MLB,K78

CRITICAL

1

607-8084

CMNPTS

639-1996

PCBA,MLB,1.4GHZ,EL 4GB,K78

K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD2,DDR3:ELPIDA_4GB

085-2714

K78 MLB DEVELOPMENT BOM

K78_DEVEL:ENG

4 OF 109

2.5.0

051-8871

4 OF 74

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_ALT_ITEM

Programmable Parts

K78 BOM GROUPS

Module Parts

DRAM CFG CHART

MICRON

ELPIDA

SAMSUNG

VENDOR

2GB

SIZE

HYNIX

4GB

0

1

CFG 2

1

0

CFG 1

1

0

CFG 0

B

A

1

DIE REV

0

CFG 3

1

0

Alternate Parts

FDMS0349 alt to RJK0305DPB

376S0617

ALL

376S1018

376S0972 376S0612

ALL

Rohm alt to Toshiba

Murata alt to Samsung

138S0691

ALL

138S0676

Panasonic alt to Cyntec

104S0011

ALL

104S0035

152S1295

ALL

152S1462

Toko alt to NEC inductor

128S0333

ALL

128S0294

Sanyo alt to Sanyo/Frederick

337S4093

EARLY 1.4GHZ CPU SAMPLES

ALL

337S4101

IC,T29-MCU,K78

T29MCU:PROG

1

U9330

CRITICAL341T0355

U3690

335S0550

T29ROM:BLANK

1

CRITICAL

EEPROM,32KBIT,2X3QFN

377S0107

ONsemi alt to Semtech

377S0066

ALL

138S0671

Taiyo alt to Murata

138S0673

ALL

BOOTROM_PROG,SMC_PROG,T29ROM:PROG,T29MCU:PROG

K78_PROGPARTS K78_DEVEL:ENG

BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

LPCPLUS,XDP_CONN,XDP_PCH

K78_DEVEL:PVT

DEVEL_BOM,SMC_DEBUG_YES,XDP

K78_DEBUG:ENG

K78_DEBUG:PVT

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT

K78_DEBUG:PROD

BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

DDR3:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB

DDR3:SAMSUNG_2GB

DRAM_CFG0:H,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB

DDR3:ELPIDA_4GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB

DDR3:SAMSUNG_4GB

K78_MISC

PCH:B3,CPUMEM_S0,HUB1_2NONREM,HUB2_2NONREM,T29:YES,SDRVI2C:MCU,SDRV_PD,KB_BL

U1000 CPU:1.3GHZ

SNB,QALV,QS,J1,1.3,17W,2+2,1.05,3M,BGA

337S4098 CRITICAL

1

ALTERNATE,COMMON,K78_MISC,K78_DEBUG:ENG,K78_PROGPARTS,USBHUB_2513B,T29BST:Y,EDP

K78_COMMON

SNB,QAM1,QS,J1,1.6,17W,2+2,1.1,4M,BGA

337S4101

1

U1000

CRITICAL

CPU:1.6GHZ

COUGAR POINT,B3,SLJ4K,PRQ,BD82QS67

U1800

PCH:B3

337S4091

1

CRITICAL

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

U2900,U2910,U2920,U2930

CRITICAL

4

DRAM_TYPE:HYNIX_2GB

333S0585

DRAM_TYPE:HYNIX_2GB

333S0585

U3000,U3010,U3020,U3030

CRITICAL

4

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

CRITICAL

U2900,U2910,U2920,U2930

333S0586

DRAM_TYPE:HYNIX_4GB

4

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

U3200,U3210,U3220,U3230

4

333S0586

DRAM_TYPE:HYNIX_4GB

CRITICAL

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

CRITICAL

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

CRITICAL

U3200,U3210,U3220,U3230

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

U3100,U3110,U3120,U3130

CRITICAL

4

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

4

333S0589

DRAM_TYPE:ELPIDA_4GB

CRITICAL

U2900,U2910,U2920,U2930

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

4

333S0589

DRAM_TYPE:ELPIDA_4GB

U3200,U3210,U3220,U3230

CRITICAL

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

4

333S0589

DRAM_TYPE:ELPIDA_4GB

CRITICAL

U3100,U3110,U3120,U3130

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,C-DIE,ELPIDA

4

333S0589

DRAM_TYPE:ELPIDA_4GB

CRITICAL

U3000,U3010,U3020,U3030

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

1

607-6811

CRITICAL

J6955

IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28

1

353S2929

CRITICAL

U7000

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB

DDR3:HYNIX_4GB

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB

DDR3:MICRON_2GB

IC,T29, FCBGA,PRQ 8x9MM

338S0976

1

U3600

T29:YES

CRITICAL

COUGAR POINT,SLHAG,PRQ,BD82QS67

PCH:B2

U1800

CRITICAL

1

337S4080

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,T-DIE,HYNIX

U3100,U3110,U3120,U3130

CRITICAL

333S0585

4

DRAM_TYPE:HYNIX_2GB

CRITICAL

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

U3100,U3110,U3120,U3130

CRITICAL

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

U3200,U3210,U3220,U3230

CRITICAL

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

U3000,U3010,U3020,U3030

CRITICAL

U2900,U2910,U2920,U2930

4

333S0588

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

4

CRITICAL

333S0587

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_2GB

U3200,U3210,U3220,U3230

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,G-DIE,SAMSUNG

CRITICAL

U3100,U3110,U3120,U3130

4

333S0587

DRAM_TYPE:SAMSUNG_2GB

U3000,U3010,U3020,U3030

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

4

333S0587

CRITICAL

DRAM_TYPE:SAMSUNG_2GB

4

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

U2900,U2910,U2920,U2930

333S0587

CRITICAL

DRAM_TYPE:SAMSUNG_2GB

U3100,U3110,U3120,U3130

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,B-DIE,HYNIX

CRITICAL

4

333S0586

DRAM_TYPE:HYNIX_4GB

U3000,U3010,U3020,U3030

CRITICAL

4

333S0586

DRAM_TYPE:HYNIX_4GB

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

333S0585

CRITICAL

U3200,U3210,U3220,U3230

4

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

DRAM_TYPE:HYNIX_2GB

SNB,QAM3,QS,J1,1.4,17W,2+2,1.05,3M,BGA

337S4099

CPU:1.4GHZ

1

CRITICAL

U1000

SNB,QAM2,QS,J1,1.5,17W,2+2,1.1,4M,BGA

337S4100

1

U1000

CRITICAL

CPU:1.5GHZ

341T0354

1

T29ROM:PROG

U3690

IC,T29-ROM,K78

CRITICAL

337S3997

1

U9330

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

T29MCU:BLANK

CRITICAL

338S0895

U4900

1

IC,SMC,RENESAS,H8S/2117RP,9MM,TLP,HF

CRITICAL

SMC_BLANK

341T0349 CRITICAL

U6100

1

BOOTROM_PROG

IC,EFI ROM,K21 K78

U6100

CRITICAL335S0809

1

BOOTROM_BLANK

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

Diodes alt to Toshiba

ALL

376S0859376S0977

376S0855 376S0613

ALL

Diodes alt to Toshiba

341T0350

1

IC,SMC,K78

CRITICAL

U4900

SMC_PROG

U6100

CRITICAL335S0803

1

BOOTROM_BLANK

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8

ALL

371S0652

NXP alt to NXP

371S0679

138S0679 138S0678

ALL

Murata/Samsung alt to Taiyo

ALL

NXP ALT TO PERICOM

353S3055353S3312

152S1085

Toko alt to Cyntec

152S1307

ALL

337S4100337S4092

EARLY 1.5GHZ CPU SAMPLES

ALL

FDMC0202S alt to RJK03E0DNS

376S0895376S0874

SYNC_DATE=11/16/2010

BOM Configuration

SYNC_MASTER=K21_MLB

ALL

376S0826 376S0917

RJK0332DPB alt to FDMS0355

ALL

514-0744 998-3941

mDP connector alt

5 OF 109

2.5.0

051-8871

5 OF 74

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

J9000: Internal DP Connector

(Need to add 27 GND TPs)

J5100: LPC+SPI Connector

J6955: HALL EFFECT Connector

FUNC_TEST

J5715: KB BKLT Connector

FUNC_TEST

(Need to add 2 GND TPs)

FUNC_TEST

Misc Voltages & Control Signals

(Need to add 5 GND TPs)

(Need 3 TPs)

(Need 4 TPs)

(Need to add 3 GND TPs)

(Need to add 5 GND TPs)

(Need 5 TPs)

(Need 6 TPs)

(Need to add 8 GND TPs)

FUNC_TEST

J4001: AirPort / BT Connector

FUNC_TEST

J4700: LIO Connector

J6903: Speaker Connector

J5700: IPD Flex Connector

FUNC_TEST

(Need to add 5 GND TPs)

(Need to add 6 GND TPs)

(Need to add 5 GND TPs)

(Need to add 6 GND TPs)

FUNC_TEST

J5600: Fan Connector

FUNC_TEST

(Need to add 1 GND TP)

FUNC_TEST

(Need 2 TPs) (Need 2 TPs)

FUNC_TEST

Functional Test Points

NO_TEST

NO_TEST Nets

(Need 4 TPs)

FUNC_TEST

J6900: DC-In Connector

J4501: SATA SSD Connector

J6950 and 1 for shield)

(Need to add 4 GND TPs near

J6950: Battery Connector

FUNC_TEST

I499

I500

I501 I502

I503

I504 I505

I506

I566 I567

I568

I569

I570

I571

SYNC_DATE=(02/16/2010)

SYNC_MASTER=(K99_MLB)

Functional Test / No Test

TP_CLINK_RESET_L

TP_CLINK_DATA

TRUE

I2C_TCON_SDA_R

TRUE

PP3V3_SW_LCD

TRUE

SMC_BC_ACOK

TRUE

SYS_ONEWIRE

=PP3V3R1V5_S0_AUDIO

TRUE

PP0V75_S0_DDRVTT

TRUE

PP15V_T29

TRUE

PP3V3_T29

TRUE

PP1V05_T29

PP1V05_S0

TRUE

PP1V05_S0_PCH_VCCADPLL

TRUE

PPVCORE_S0_CPU

TRUE

PPVCORE_S0_AXG

TRUE

PP1V5_S3_CPU_VCCDQ

TRUE

PP1V05_S0_CPU_VCCPQE

TRUE

PP1V8_S0_CPU_VCCPLL_R

TRUE

PP1V05_SUS

TRUE

PPVCCSA_S0_CPU

TRUE

PPVTTDDR_S3

PP1V5_S0

TRUE

PP1V5_S3RS0

TRUE

=PP3V42_G3H_HALL

TRUE

SMC_LID_R

TRUE

KBDLED_ANODE

TRUE

KBDLED_FB

TRUE

PPBUS_G3H

TRUE

PPVIN_SW_T29BST

TRUE

PP3V42_G3H

TRUE

PPVRTC_G3H

TRUE

PP5V_SUS

TRUE

PP3V3_SUS

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP1V5_S3

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

WIFI_EVENT_L

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_AP_R2D_N

TRUE

LED_RETURN_1

TRUE

I2C_TCON_SCL_R

=PP3V3_S3_BT

TRUE

=PP3V3_S0_AUDIO

TRUE

HDA_SYNC

TRUE

HDA_RST_L

SPKRAMP_R_P_OUT

TRUE

SPKRAMP_R_N_OUT

TRUE

=PP5V_S0_FAN

TRUE

PP5V_TPAD_FILT

TRUE

SMC_PME_S4_WAKE_L

TRUE

FAN_RT_PWM

TRUE

=PP3V42_G3H_TPAD

TRUE

AP_CLKREQ_Q_L

TRUE

PP3V3_S0_HDD_R

TRUE

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_D2R_C_N

TRUE

SMC_HDD_TEMP_CTL_CONN

TRUE

SATA_HDD_R2D_P

TRUE

SATA_HDD_R2D_N

TRUE

MAKE_BASE=TRUE

NC_PCI_CLK33M_OUT3

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

MAKE_BASE=TRUE

TRUE

NC_CLINK_DATA

TRUE MAKE_BASE=TRUE

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

NC_CLINK_CLK

NC_CLINK_RESET_L

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN2

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN3

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

NC_PCH_LVDS_VBG

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_DATA

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_CLK

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

TRUE

NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

TRUE MAKE_BASE=TRUE

NC_CRT_IG_GREEN

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_RED

TRUE MAKE_BASE=TRUE

NC_SDVO_INTN

TRUE MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTP

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_D<0..1>

TRUE MAKE_BASE=TRUE

NC_TP_XDPPCH_HOOK3

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_B<0..1>

MAKE_BASE=TRUE

TRUE

NC_TP_XDPPCH_HOOK2

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_A<0..1>

NC_TP_XDP_PCH_HOOK4

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_HOOK5

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<9>

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<1>

TRUE

MAKE_BASE=TRUE

TRUE

NC_SMC_BS_ALRT_L

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

PCH_VSS_NCTF<29>

TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<17>

TRUE

NC_PCH_TP1

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

NC_PCH_TP3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP4

TRUE

PCH_VSS_NCTF<15>

MAKE_BASE=TRUE

TRUE

NC_PCH_TP5

MAKE_BASE=TRUE

TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

MAKE_BASE=TRUE

NC_PCH_TP8

TRUE

NC_PCH_TP9

TRUE

MAKE_BASE=TRUE

NC_PCH_TP10

TRUE

MAKE_BASE=TRUE

NC_PCH_TP12

TRUE

MAKE_BASE=TRUE

NC_PCH_TP13

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

NC_PCH_TP15

TRUE

MAKE_BASE=TRUE

NC_PCH_TP16

TRUE

MAKE_BASE=TRUE

NC_PCH_TP18

TRUE

MAKE_BASE=TRUE

NC_PCH_TP17

TRUE

NC_SATA_E_D2RP

TRUE MAKE_BASE=TRUE

NC_SATA_E_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_E_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RN

NC_SATA_D_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RN

MAKE_BASE=TRUE

NC_PSOC_P1_3

TRUE

NC_PCIE_CLK100M_PE7P

TRUE MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CN

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5P

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<15..4>

TRUE

MAKE_BASE=TRUE

NC_CPU_RSVD<8..27>

NC_CPU_RSVD<30..45>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_CPU_THERMDC

TRUE

MAKE_BASE=TRUE

NC_EDP_AUXN

TRUE

MAKE_BASE=TRUE

NC_CPU_THERMDA

TRUE

MAKE_BASE=TRUE

NC_EDP_TXN<0..3>

TRUE

MAKE_BASE=TRUE

NC_EDP_AUXP

TRUE

MAKE_BASE=TRUE

NC_EDP_TXP<0..3>

TRUE

PCIE_WAKE_L

USB_BT_N

TRUE

USB_BT_P

TRUE

FAN_RT_TACH

TRUE

SMC_ONOFF_L

TRUE

=I2C_TPAD_SDA

TRUE

USB_TPAD_CONN_N

USB_TPAD_CONN_P

TRUE

SMC_TPAD_RST_L

TRUE

SMC_LID

TRUE

=PP18V5_DCIN_CONN =PP5V_S3_LIO_CONN

TRUE

=SMBUS_BATT_SCL

TRUE

PP3V3_WLAN_F

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_AP_P

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_N

TRUE

AP_RESET_CONN_L

TRUE

=PP3V3_S5_LPCPLUS

TRUE

SPI_ALT_MOSI

TRUE

LPC_FRAME_L

TRUE

SPI_ALT_MISO

TRUE

SMC_TMS

TRUE

PM_CLKRUN_L

TRUE

LPCPLUS_RESET_L

TRUE

SMC_TDO

TRUE

SMC_TRST_L

TRUE

SMC_TX_L

TRUE

SMC_MD1

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CS_L

TRUE

LPC_PWRDWN_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

SMC_RESET_L

TRUE

SMC_RX_L

TRUE

SMC_NMI

TRUE

LPCPLUS_GPIO

TRUE

=PP5V_S0_LPCPLUS

TRUE

LPC_AD<3..0>

AUD_IP_PERIPHERAL_DET

TRUE

AUD_IPHS_SWITCH_EN

TRUE

AUD_I2C_INT_L

TRUE

SPKRAMP_INR_N

AUD_GPIO_3

TRUE

USB_EXTD_N

SPKRAMP_INR_P

TRUE

USB_EXTD_P

TRUE

USB_CAMERA_P

TRUE

USB_CAMERA_N

TRUE

HDA_SDOUT

TRUE

HDA_SDIN0

TRUE

HDA_BIT_CLK

USB_EXTD_OC_L

TRUE

=USB_PWR_EN

TRUE

=I2C_LIO_SDA

TRUE

=I2C_MIKEY_SCL

TRUE

=I2C_LIO_SCL

TRUE

=I2C_MIKEY_SDA

=PP3V42_G3H_ONEWIRE

TRUE

PPDCIN_G3H

TRUE

PP5V_S5

TRUE

LED_RETURN_5

TRUE

LED_RETURN_4

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

DP_INT_HPD_CONN

TRUE

DP_INT_AUX_CH_C_N

TRUE

DP_INT_AUX_CH_C_P

TRUE

DP_INT_ML_F_P<0>

TRUE

DP_INT_ML_F_N<0>

TRUE

DP_INT_ML_F_P<1>

LED_RETURN_6

TRUE

DP_INT_ML_F_N<1>

TRUE

TP_EDP_TX_P<0..3>

TP_EDP_AUX_P

TP_EDP_TX_N<0..3>

TP_CPU_THERMDA

TP_EDP_AUX_N

TP_CPU_THERMDC

TP_CPU_RSVD<30..45>

TP_CPU_RSVD<8..27>

=PEG_R2D_C_P<15..4>

=PEG_D2R_P<15..4>

=PEG_R2D_C_N<15..4>

=PEG_D2R_N<15..4>

TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE7N

TP_SATA_B_R2D_CN

TP_PCIE_CLK100M_PE7P

TP_PSOC_P1_3 TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_B_R2D_CP

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_D_D2RP

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RP

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_PCH_TP17

TP_PCH_TP18

TP_PCH_TP16 TP_PCH_TP15

TP_PCH_TP14

TP_PCH_TP13 TP_PCH_TP12

TP_PCH_TP10 TP_PCH_TP9

TP_PCH_TP8 TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5 TP_PCH_TP4

TP_PCH_TP3

TP_PCH_TP2 TP_PCH_TP1

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_BKL_PWM

SMC_BS_ALRT_L

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2 TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO64_CLKOUTFLEX0

TP_XDP_PCH_HOOK5

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_A<0..1>

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK3 TP_XDP_PCH_OBSFN_D<0..1>

TP_SDVO_STALLP

TP_SDVO_INTN TP_SDVO_INTP

TP_SDVO_STALLN

TP_SDVO_TVCLKINN

TP_SDVO_TVCLKINP

TP_CRT_IG_BLUE

TP_CRT_IG_DDC_DATA

TP_LVDS_IG_CTRL_DATA

TP_HDA_SDIN3

TP_PCI_PME_L

TP_CLINK_CLK

TP_PCI_CLK33M_OUT3

TP_PCIE_CLK100M_PEBN

TP_PCIE_CLK100M_PEBP

TP_HDA_SDIN2

TP_HDA_SDIN1

TP_PCH_LVDS_VBG

TP_LVDS_IG_CTRL_CLK

TP_CRT_IG_VSYNC

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TP_CRT_IG_GREEN

TP_CRT_IG_HSYNC

TRUE

=I2C_TPAD_SCL

TRUE

PP3V3_TPAD_CONN

TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..4>

TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..4>

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE4N

TRUE

MAKE_BASE=TRUE

NC_PEG_D2RP<15..4>

TRUE

SMC_HDD_OOB_TEMP_CONN

TRUE

PP3V3_S5

TRUE

PP1V8_S0

PPVOUT_SW_LCDBKLT

TRUE

PPVBAT_G3H_CONN

TRUE

SYS_DETECT_L

TRUE

=SMBUS_BATT_SDA

TRUE

7 OF 109

2.5.0

051-8871

6 OF 74

16

62

39 40 41

39 40

7

39

7

35

7

67

7

51

48

7

51

7

35

7

73

7

67

7

36 40

36 69

62 65

62

7

36

7

39

16 39 69

50 51 73

7

47

48

40 41 48

47

7

48

36

37

37 68

37

37 68

69

6

69

6

69

17 36

24 36 68

47

40 41 48

43 48

48 73

41 48

40 41 48 51

7

51

7

51

43 51

36

16 36 69

36

7

42

16 40 42 69

42

40 41 42

17 40 42

25 42

40 41 42

40 42

38 40 41 42

40 42

25 42 69

19 42 49

42

16 40 42

42

17 40 42

40 41 42

40 41 42 52

38 40 41 42

40 42

19 42

7

42

16 40 42 69

18 39

19 39

18 39

39 50 73

39 50

24 39 68

39 50 73

24 39 68

18 39 68

16 39 69

24 39

38 39 61

39 43

7

39

7

62 65

62

62 69

62 65

62 69

9

16

8

16

23

17

16

18

16

18

16

17

43 48

48

16

37

7

73

7

62 65

51 52

51

43 51

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

5V Rails

1.8V/1.5V/1.2V/1.05V Rails

T29 Rails (off when no cable)

"G3Hot" (Always-Present) Rails

2A max supply

3.3V Rails

? mA

Chipset "VCore" Rails

1V05 S0 LDO

SYNC_DATE=05/15/2010

Power Aliases

SYNC_MASTER=K91_MLB

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S3

VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_USB_HUB

=PP3V3_S3_PCH_GPIO

=PP3V3_S3_1V5S3ISNS =PP3V3_S3_DBGLEDS

=PP3V3_S3_FET

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_VREFMRGN

=PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_DP_DDC =PP3V3_S0_FAN

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM

=PP5V_S5_LDO

=PP3V3_S0_FET

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_HS_COMPUTING_ISNS

=PP3V3_S0_P3V3T29FET

=PP3V3_S0_P1V8S0

=PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_VCC3_3_CLK =PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH_VCCSSC

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PP1V05_S0_CPU_VCCIO

=PP3V3_S3_WLANISNS

=PP3V3_S3_WLAN

=PP3V3_S5_SMC

=PPDCIN_S5_CHGR

=PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC

=PP3V3_S0_P1V5S0

=PP3V3_S0_PCH_STRAPS

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCCADAC

=PP1V5_S0_REG

=PP3V3_SUS_PWRCTL

=PP3V3_SUS_GPIO

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_S0_BKLTISNS

=PP3V3_S0_P1V05S0LDO

=PP3V3_S0_T29PWRCTL =PP3V3_S0_DPSDRVA

=PP3V3_S0_VMON

=PP3V3_S0_HDDISNS

=PP3V3_S0_HDD

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_PCH

=PP3V3_S0_SB_PM

=PP3V3_S0_RSTBUF

=PP3V3_S0_PWRCTL

=PP3V3_S0_CPU_VCCIO_SEL

=PP0V75_S0_MEM_VTT_B

MIN_LINE_WIDTH=2 mm

MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V

=PPVTT_S0_VTTCLAMP

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

=PP5V_S5_TPAD

=PPVRTC_G3_OUT

=PP5V_S5_P1V5DDRFET

=PP5V_SUS_PCH

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP5V_SUS

=PPVRTC_G3_PCH

=PP3V42_G3H_ONEWIRE

=PP5V_S0_FAN

=PP5V_S0_BKL

=PP5V_S3_REG

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S5_PCH

=PP1V05_S0_PCH_VCCASW

=PPVIN_S0_DDRREG_LDO

=PP1V5_S3_P1V5S3RS0_FET

=PP3V3_S5_SMCBATLOW

=PP3V3_S4_SMC

=PP3V3_S3_P3V3S3FET

=PPVBAT_G3_SYSCLK

=PPVIN_S5_SMCVREF

=PP3V42_G3H_TPAD

=PPVIN_S0_CPUIMVP

=PP18V5_DCIN_CONN

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A

=PP1V5_S3_MEMRESET

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3RS0

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

PP1V5_S3

=PP1V05_T29_FET

=PPVIN_S5_P5VP3V3

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

=PPVCCIO_S0_CPUIMVP

=PP3V3_S5_P3V3SUSFET

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

=PP1V5_S3_CPU_VCCDQ

=PPGFXVCORE_S0_VSENSE

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE

=PP1V05_S0_LDO

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_T29_RTR

=PP3V3_T29_FET

=PP3V3_T29_PCH_GPIO

=PP3V3_T29_RTR

=PP15V_T29_REG

=PP1V05_S0_P1V05T29FET

=PPVCCIO_S0_SMC

=PPVCCIO_S0_XDP

=PP1V05_S0_PCH_VCCDMI_FDI

=PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_VMON

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH

=PP5V_SUS_FET

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPVIN_SW_T29BST

=PPBUS_S0_VSENSE

=PPBUS_S0_LCDBKLT

=PP5V_S0_FET

=PP3V3_S5_USB_RESET

=PP3V3_S5_ROM

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_LCD

=PP0V75_S0_MEM_VTT_A

=PP1V05_SUS_PCH_JTAG

=PPCPUVCCIO_S0_REG

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_REG

=PPBUS_G3H

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S5_REG

=PP3V3_S0_P3V3S0FET

=PP3V3_S5_XDP

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_REG

=PPVIN_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 MM

PPVCCSA_S0_CPU

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=0.9V

PPVIN_SW_T29BST

VOLTAGE=12.8V

VOLTAGE=3.3V

PP3V3_T29

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.25V MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPVCORE_S0_AXG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0_CPU_VCCPQE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V

PP1V8_S0_CPU_VCCPLL_R

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

=PPVCORE_S0_CPU_REG

=PPVDDIO_T29_CLK

=PP1V5_S3_CPU_VCCDDR =PP1V5_S3RS0_VMON

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_T29

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

=PPHV_SW_DPAPWRSW

VOLTAGE=17.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP15V_T29

=PP1V05_SUS_LDO

=PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG

=PP5V_S3_MEMRESET

=PP5V_S3_P5VS0FET

=PP5V_S3_RTUSB

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=5V

=PP5V_S3_LIO_CONN

=PP5V_S0_CPUVCCIOS0

=PP5V_S0_CPUIMVP

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=5V

=PP5V_S0_LPCPLUS

=PP5V_S0_VCCSA =PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_KBDLED

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_P1V5S0

=PPVDDIO_S0_SBCLK

=PP1V8_S0_P1V05S0LDO

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0

=PPDDR_S3_REG

=PP1V5_S3RS0_FET

VOLTAGE=3V

MIN_LINE_WIDTH=0.2 MM

PPVRTC_G3H

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP3V42_G3H

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V

MIN_LINE_WIDTH=0.3 MM

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_CHGR

=PP3V42_G3H_HALL

MAKE_BASE=TRUE

PPVTTDDR_S3

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3R1V5_S0_PCH_VCCSUSHDA

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=2 mm

=PP3V3R1V5_S0_AUDIO

=PPVIN_S0_CPUAXG

=PPVIN_S0_VCCSAS0

=PP3V3_SUS_FET

=PPVIN_S0_CPUVCCIOS0

=PPVIN_S3_DDRREG

=PP3V3_S5_TPAD

=PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S5_PCH_VCC_SPI

=PP3V3_SUS_PCH_VCCSUS_GPIO =PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_P1V05SUSLDO

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PPDCIN_G3H

MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V

=PPDCIN_S5_VSENSE

=PP3V3_S3_BT

=PP3V3_S3_MEMRESET

=PP3V3_SUS_PCH

=PP3V3_S4_DPAPWRSW

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.50MM

PP3V3_SUS

VOLTAGE=3.3V

=PP3V3_SUS_SMC

=PP3V3_S3_BMON_ISNS

=PP3V3_S3_USB_RESET

=PPVCCSA_S0_REG

=PPVCCSA_S0_CPU

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP1V05_S0_PCH_V_PROC_IO

=PP5V_S5_P5VSUSFET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S5

=PP3V3_S0_SYSCLKGEN

=PP3V3_S0_T29I2C

=PP3V3_S0_XDP

=PP3V3_S0_IMVPISNS

8 OF 109

2.5.0

051-8871

7 OF 74

6

43

8

24

18 19

45

51

60

43

31

44

6

39

46

8

47

6

73

54

60

65

45

35

59

16 19 22

18

22 20 22

20 22

16 20 22

20 22

6

20

9

10 12 14

45

36

40 41

52

43

41

59

16 17 19

20 22

22

59

61

16 17 18 19

20 22

45

59

35

63

61

45

37

43

25

61

12

32

6

26

6

55

31 55

48

25

60

22

6

16 17 20

6

39

6

47

65

54

16 20 22

17 19

20 22

55

60

41

60

25

41

6

48

56 57

6

51 29 30 32

27 28 32

26

6

67

6

67

35

54

6

51

56

60

12 14

12 15

44

9

12 15

57

9

12 14

44

59

20

34

35

16 19

33 34 35

8

35

40

23

20

20 22

20

20 22

61

17

20 22

16 22

60

45

8

35

44

65

60

24

49

25

62

32

23

58

14

59

52

26

54

60

23

6

42

51

45

6

35

6

57

25

10 12 15 26

61

6

35

64

6

59

50

55

26

60

38

6

51

58

56

6

42

53

22

61

48

18 20 22

20

59

25

59

6

55

60

6

38

43

61

52

6

51

6

16 20 22

6

39

57

53

60

58

55

48

20 22

25

61

20 22

20

59

6

44

6

36

26

22

64

6

73

6

41

45

24

53

12 15

20

20 22

60

6

25

43

23

44

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

870-1938 870-1938

870-2015

4x 860-1327

T29 DP Ports

CPU signals

SSD Boss

860-1327860-1327

T29_A_BIAS caps

Unused USB ports

T29 Aliases

DP_A_BIAS caps

SATA Aliases

Unused SATA ODD Signals

UNUSED SDCARD USB Aliases

LVDS Aliases

T29_A_BIAS caps

T29 JTAG

Unused PGOOD signal

806-1176

X21 Boss

CPU Heat Sink Mounting Bosses

DisplayPort PCB Stiffener

870-1940

USB/SD Card Pogo

EMI I/O Pogo Pins

860-1327

998-2691

DisplayPort Pogo

Fan Boss

T29 Can Slots

(Provides PCB support for small finger above J9400)

Digital Ground

60

55

33

19 23

19

21

R0917

NO STUFF

0

5%

MF

1/20W

201

21

R0918

201

1/20W

MF

0

NO STUFF

5%

16 68

43

21

R0910

0.5%

1W MF

0.01

CRITICAL

0612-1

45 73

1

Z0910

STDOFF-4.5OD1.8H-SM

1

Z0912

STDOFF-4.5OD1.8H-SM

1

Z0913

STDOFF-4.5OD1.8H-SM

1

Z0911

STDOFF-4.5OD1.8H-SM

1

Z0915

STDOFF-4.5OD1.9H-SM

1

ZS0906

SM

CRITICAL

POGO-2.0OD-3.6H-K86-K87

1

Z0914

STDOFF-4.5OD1.9H-SM

1

Z0905

STDOFF-4.5OD1.8H-SM

1

ZS0905

POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

1

MT0900

SM-SP

STIFFENER-K16-K99

NO STUFF

2

1

C0964

201

10%

0.01UF

X5R

10V

2

1

C0962

0.01UF

201

10%

X5R

10V

21

R0960

5%

1/8W

805

MF-LF

0

T29BST:N

2

1

C0960

0.01UF

10% 10V X5R 201

2

1

R0920

2.2K

5%

1/20W

MF

201

2

1

R0921

2.2K

1/20W

201

MF

5%

2

1

R0922

201

MF

1/20W

5%

2.2K

2

1

R0923

2.2K

5%

MF

201

1/20W

2

1

R0924

2.2K

5%

1/20W

MF

201

2

1

R0925

2.2K

5%

1/20W

MF

201

2

1

R0908

100K

1/20W

MF

201

5%

2

1

R0915

5%

1/20W

10K

MF

201

2

1

R0916

1/20W

201

MF

5%

10K

2

1

C0906

SIGNAL_MODEL=EMPTY

10%

0.01UF

201

10V X5R

21

R0926

SIGNAL_MODEL=EMPTY

201

51

5%

1/20W

MF

2

1

C0907

10V

10%

0.01UF

201

X5R

SIGNAL_=EMPTY

21

R0927

201

SIGNAL_MODEL=EMPTY

51

1/20W

5%

MF

2

1

C0908

SIGNAL_MODEL=EMPTY

X5R

0.01UF

10V

10%

201

2

1

C0905

0.01UF

201

X5R

10V

10%

SIGNAL_MODEL=EMPTY

2

1

C0901

SIGNAL_MODEL=EMPTY

X5R

0.01UF

10% 10V

201

2

1

C0902

SIGNAL_MODEL=EMPTY

0.01UF

10V

201

10%

X5R

2

1

C0903

SIGNAL_MODEL=EMPTY

10V

201

10%

X5R

0.01UF

2

1

C0904

SIGNAL_MODEL=EMPTY

0.01UF

10V

201

10%

X5R

21

R0931

201

MF

1/20W

5%

51

SIGNAL_MODEL=EMPTY

21

R0932

SIGNAL_MODEL=EMPTY

51

5%

1/20W

201

MF

21

R0933

SIGNAL_MODEL=EMPTY

1/20W

5%

51

201

MF

21

R0934

SIGNAL_MODEL=EMPTY

5%

1/20W

MF

51

201

24 68

1

ZS0904

POGO-2.0OD-2.95H-K86-K87

CRITICAL

SM

1

ZS0907

1.4DIA-SHORT-SILVER-K99

CRITICAL

SM

2

1

R0902

10K

5% MF

1/20W

201

2

1

R0901

10K

1/20W

5% MF

201

2

1

R0909

MF

1/20W

5%

100K

201

21

R0990

0

201

1/20W

5%

MF

1

SL0901

TH-NSP

SL-1.1X0.4-1.4x0.7

1

SL0902

TH-NSP

SL-1.1X0.4-1.4x0.7

SYNC_DATE=05/15/2010

Signal Aliases

SYNC_MASTER=K91_MLB

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.075MM

ISNS_LCDBKLT_N

=USB_HUB1_OCS4

=USB_HUB2_OCS4

MAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWR

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_SW_BKL

NC_PEG_CLK100MP

MAKE_BASE=TRUE

DPLL_REF_CLKN

MAKE_BASE=TRUE

DPLL_REF_CLK_N

DPLL_REF_CLKP

MAKE_BASE=TRUE

DPLL_REF_CLK_P

TP_PCH_CLKOUT_DPP

TP_PCH_CLKOUT_DPN

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

PEG_CLK100M_N

PEG_CLK100M_P

TP_MEM_A_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

NC_MEM_A_CKE<1>

MAKE_BASE=TRUE

NC_MEM_A_ODT<1>

MAKE_BASE=TRUE

NC_PEG_CLK100MN

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_P

DP_IG_ML_N<3..0>

TP_DP_IG_B_MLP<3..0>

DP_IG_ML_P<3..0>

=DDRVTT_EN

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_N

PEG_D2R_N<3..0>

PCIE_T29_D2R_P<3..0>

MAKE_BASE=TRUE

PEG_D2R_P<3..0>

=PPBUS_SW_BKL

NC_USB_HUB2_OCS4

MAKE_BASE=TRUE

USB_SDCARD_N

USB_SDCARD_P

=PP3V3_S3_USB_HUB

USB_T29A_N USB_T29A_P

MAKE_BASE=TRUE

NC_USB_HUB1_OCS4

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MEM_A_A<15>

NC_MEM_B_ODT<1>

MAKE_BASE=TRUE

NC_MEM_B_CS_L<1>

MAKE_BASE=TRUE

MEM_A_CLK_N<1>

MAKE_BASE=TRUE

DP_EXTA_ML_C_P<3..0>

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA

TP_DP_IG_D_CTRL_CLK

=PP3V3_S0_DP_DDC

DP_IG_B_HPD

MAKE_BASE=TRUE

MEMVTT_EN

DP_EXTA_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_EXTA_DDC_CLK

MAKE_BASE=TRUE

PCIE_T29_R2D_C_P<3..0>

MAKE_BASE=TRUE

PCIE_T29_R2D_C_N<3..0>

=PEG_D2R_P<3..0>

TP_DP_IG_B_MLN<3..0>

DP_IG_B_AUX_P

DP_IG_B_AUX_N

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

T29_A_BIAS

PCIE_T29_D2R_N<3..0>

MAKE_BASE=TRUE

=PEG_R2D_C_N<3..0>

=PEG_R2D_C_P<3..0>

=PEG_D2R_N<3..0>

TP_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK

DP_IG_B_DDC_DATA

MAKE_BASE=TRUE

DP_EXTA_HPD

T29_A_BIAS_D2RP1

T29_A_BIAS_D2RN1

DP_A_BIAS_P_0DP_A_BIAS_P_2

T29_A_RSVD_P

T29_A_RSVD_N

P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

DP_IG_C_CTRL_CLK

TP_DP_IG_C_CTRL_DATA

TP_DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

DP_IG_C_CTRL_DATA

T29_A_BIAS_R

DP_IG_B_DDC_CLK

T29_A_BIAS_R2DP0

T29_A_BIAS_R2DN0

T29_A_BIAS_R2DP1

T29_A_BIAS_R2DN1

T29_A_BIAS_R

DP_EXTA_AUXCH_C_N

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_P

MEM_B_CLK_P<1>

PCIE_EXCARD_D2R_P

NC_PCIE_EXCARD_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_EXCARDP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_EXCARDN

NC_PCIE_EXCARD_R2D_CN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RN

DDRREG_PGOOD

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

DP_A_BIAS_N_2

MEM_A_CLK_P<1>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

ISNS_LCDBKLT_P

DP_A_BIAS_N_0

MAKE_BASE=TRUE

DP_IG_D_CTRL_DATA

PEG_R2D_C_N<3..0>

PEG_R2D_C_P<3..0>

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

LVDS_IG_B_CLK_N

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

LVDS_IG_B_DATA_P<0..3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

LVDS_IG_B_DATA_N<0..3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

LCD_BKLT_PWM

LVDS_IG_A_DATA_N<3>

NC_LVDS_IG_A_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

LCD_IG_PWR_EN

LVDS_IG_BKL_ON

LCD_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCP

NC_SATA_ODD_D2RP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

DP_T29SNK0_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_T29SNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

TP_DP_IG_C_MLP<3..0>

DP_T29SNK0_AUXCH_C_P

MAKE_BASE=TRUE

TP_DP_IG_C_AUXP

DP_T29SNK0_AUXCH_C_N

MAKE_BASE=TRUE

TP_DP_IG_C_AUXN

TP_DP_IG_C_HPD

MAKE_BASE=TRUE

DP_T29SNK0_HPD

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

DP_IG_D_HPD

LVDS_IG_B_CLK_P

TP_DP_IG_D_HPD

NC_MEM_A_CS_L<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKN<1>

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

NC_MEM_B_CKE<1>

=PPVIN_SW_T29BST

MEM_B_ODT<1>

MEM_A_ODT<1>

MEM_B_A<15>

MEM_B_CS_L<1>

=PP15V_T29_REG

MEM_B_CLK_N<1>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_B_CKE<1>

JTAG_T29_TDIJTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TCK

MAKE_BASE=TRUE

JTAG_T29_TDOJTAG_ISP_TDO

MAKE_BASE=TRUE

JTAG_T29_TCK

JTAG_T29_TCK_R

9 OF 109

2.5.0

051-8871

8 OF 74

24

65

10 66

10 66 16

16

16 69

16

68

17

68

26 55

16

66

33 69

66

65

7 8

24

7 8

24

24 68

11 67

63 69

63

17

7 8

17

26

63 69

63

33 69

9

17

68

63 64

33 69

9

17

63

64

63 63

63 68

17

8

64

8

64

17

63

8

64

8

64

8

64

8

64

63 69

11 67

16

63 63

66

6

68

6

68

17 65

68

17 62

17 65

33 71

33 71 17

17 33

17

68

17

7

35

11 67

7

35

11 67

IN IN IN IN

IN

OUT

IN

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

IN

IN IN IN IN IN IN

IN

IN IN

OUT

OUT OUT OUT OUT

IN IN

IN

IN IN

NC

EDP_TX_3

EDP_TX_0 EDP_TX_1 EDP_TX_2

EDP_TX_2* EDP_TX_3*

EDP_TX_0* EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

VCC_VAL_SENSE

CFG_17

CFG_16

CFG_15

CFG_10 CFG_11 CFG_12 CFG_13 CFG_14

CFG_5 CFG_6 CFG_7 CFG_8 CFG_9

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4

RSVD_28 RSVD_29

RSVD_30

RSVD_32

RSVD_31

RSVD_34

RSVD_33

RSVD_35 RSVD_36 RSVD_37 RSVD_38

RSVD_40

RSVD_39

RSVD_42 RSVD_43

RSVD_41

RSVD_44

RSVD_45

DC_TEST_A4 DC_TEST_C4

DC_TEST_D1

DC_TEST_D3

DC_TEST_A58

DC_TEST_C59

DC_TEST_A59

DC_TEST_C61

DC_TEST_A61

DC_TEST_D61

DC_TEST_BE61

DC_TEST_BD61

DC_TEST_BG61

DC_TEST_BE59

DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BE3

DC_TEST_BG3

DC_TEST_BE1 DC_TEST_BD1

DC_TEST_BG1

VCC_DIE_SENSE

RSVD_7

RSVD_6

RSVD_8 RSVD_9 RSVD_10

RSVD_12

RSVD_11

RSVD_13 RSVD_14 RSVD_15

RSVD_17

RSVD_16

RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22

RSVD_24

RSVD_23

RSVD_25

RSVD_27

RSVD_26

RESERVED

(5 OF 9)

OUT OUT

NC

IN

D

G S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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8 7 5 4 2 1

to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.

NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.

to low voltage signals for the processor

even if internal Graphics is disabled since they are

Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating shared with other interfaces.

Note. VOLTAGE=0V

Note. VOLTAGE=1.25V

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

NOTE: Intel validation sense lines per

Note. VOLTAGE=0V

FOR SANDYBRIDGE PROCESSOR

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

Note. VOLTAGE=1.05V

This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core

Therefore, an inverting level shifter is required on the motherboard

NOTE: The EDP_HPD processor input is a low voltage active low signal.

FIXME: Pin should be EDP_HPD*

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

If HPD is disabled while eDP interface is still enabled,

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

These can be Placed close to J2500 and Only for debug access

This signal can be left as no-connect if entire eDP interface is disabled.

(refer to latest Processor EDS for DC specifications).

to convert the active high signal from Embedded DisplayPort sink device

17 66

8

6

8

6

8

6

8

6

8

6

8

6

21

R1010

24.9

201

1%

1/20W

MF

PLACE_NEAR=U1000.G3:12.7MM

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

9

23

17 66

A15

C15

F14

E14

F17

G17

K15

K17

C17

B18

H19

G19

F21

E21

D23

D24

J4

K4

D9

D8

F10

G10

M10

K10

H13

G13

J14

K13

C23

A23

G22

F22

B10

C9

A11

C11

D13

D12

B14

C13

D17

D16

A19

C19

D21

D19

B22

C21

K7

K6

E5

F6

H8

H6

B6

C5

A8

C8

G8

F8

J21

K19

H22

K22

G4

G1

G3

U11

AC9

AC8

Y2

AA3

V4

T4

W6

W7

AG8

AC12

AA6

AA7

W1

W3

W11

W10

U7

U6

AA10

AA11

AE7

AE6

AE11

AE10

AC4

AA4

AC3

AC1

AD2

AG11

AF3

AG4 AF4

R2

T3

N4

P4

M8

M7

K1

K3

P10

P11

P1

P3

P6

P7

M2

N3

U1000

MOBILE-2C-35W

BGA

CRITICAL

OMIT_TABLE

SANDY-BRIDGE

K45

K43

H43

F48

H45

W14

U14

P13

N50

N42

M14

M13

L47

L45

L42

K48

K24

H48

BG7

BG26

BG22

BF23

BE7

BE26

BE24

BE22

BD26

BD25

BD22

BD21

BB21 BB19

BA22

BA19

AY22

AY21

AV19

AU21

AU19

AT49

AT21

AM15

AM14

AH2 AG13

D61

D3 D1

C61

C59

C4

BG61 BG59 BG58 BG4 BG3

BG1

BE61 BE59

BE3

BE1

BD61

BD1

A61

A59

A58

A4

H51

A55

H49

C55

C53

A51

D53

B54

L53

D52

F51

L51

G53

F53

K53

K49

C51

B50

U1000

SANDY-BRIDGE

MOBILE-2C-35W

OMIT_TABLE

CRITICAL

BGA

46 73

2

1

R1044

EDP

1K

5%

MF-LF

1/16W

402

9

23 66

2

1

R1064

201

MF

1/20W

1%

49.9

NOSTUFF

2

1

R1070

PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM

201

MF

1/20W

1%

49.9

NOSTUFF

2

1

R1065

NOSTUFF

49.9

1%

1/20W

MF

201

PLACE_NEAR=U1000.K43:50.8MM

PLACE_SIDE=BOTTOM

2

1

R1071

PLACE_NEAR=U1000.K45:50.8MM

PLACE_SIDE=BOTTOM

NOSTUFF

49.9

1% 1/20W MF 201

21

R1021

1/20W

5%

0

MF

201

NOSTUFF

2

1

R1020

NOSTUFF

1K

1% 1/20W MF 201

21

R1030

PLACE_NEAR=U1000.AF3:12.7MM

MF

201

1/20W

1%

24.9

2

1

R1045

5%

1K

MF-LF

1/16W

402

2

1

R1046

NOSTUFF

1K

5%

MF-LF

1/16W

402

2

1

R1047

5%

1K

NOSTUFF

MF-LF

1/16W

402

2

1

R1042

NOSTUFF

1K

5%

MF-LF

1/16W

402

2

1

R1040

5%

1K

NOSTUFF

1/16W MF-LF

402

2

1

R1041

1K

MF-LF

1/16W

5%

402

NOSTUFF

2

1

R1043

NOSTUFF

MF-LF

1/16W

1K

402

5%

2

1

R1049

5%

1K

NOSTUFF

MF-LF

1/16W

402

2

1

R1031

201

1K

MF

1/20W

5%

PLACE_NEAR=U1000.AG11:12.7MM

2

1

3

Q1031

SOD-VESM-HF

SSM3K15FV

CPU DMI/PEG/FDI/RSVD

EDP_HPD_L

CPU_CFG<16> CPU_CFG<3>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

FDI_DATA_P<1>

=PP1V05_S0_CPU_VCCIO

CPU_CFG<1>

CPU_CFG<6>

CPU_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_A

CPU_AXG_VALSENSE_N

CPU_VCC_VALSENSE_N

=PPVCORE_S0_CPU_VCCAXG

CPU_AXG_VALSENSE_P

CPU_VCC_VALSENSE_P

=PPVCORE_S0_CPU

CPU_CFG<4>

CPU_THERMD_N

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<3>

CPU_CFG<1>

CPU_CFG<0>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<12>

CPU_CFG<11>

CPU_CFG<10>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>

=PP1V05_S0_CPU_VCCIO

CPU_THERMD_P

TP_CPU_VCC_DIE_SENSE

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE1_BG1

CPU_DC_TEST_C4_BE3_BG3

TP_CPU_DC_TEST_BG4

TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_D61

CPU_DC_TEST_C61_A61

CPU_DC_TEST_C59_A59

TP_CPU_DC_TEST_A58

TP_CPU_DC_TEST_D1

CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_A4

CPU_MEM_VREFDQ_A

=PP1V05_S0_CPU_VCCIO

CPU_CFG<2>

DP_INT_HPD

=PEG_R2D_C_P<15>

=PEG_R2D_C_P<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<1>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_P<13>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<9> =PEG_D2R_P<10>

=PEG_D2R_P<8>

=PEG_D2R_P<7>

=PEG_D2R_P<5> =PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2> =PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_P<0>

=PEG_D2R_N<15>

=PEG_D2R_N<13> =PEG_D2R_N<14>

=PEG_D2R_N<11> =PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_N<6> =PEG_D2R_N<7>

=PEG_D2R_N<5>

=PEG_D2R_N<4>

=PEG_D2R_N<1> =PEG_D2R_N<2>

CPU_PEG_COMP DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<2>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<2>

DMI_N2S_N<1>

FDI_DATA_N<2>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<5>

FDI_DATA_P<2>

FDI_DATA_P<0>

FDI_DATA_N<6> FDI_DATA_N<7>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

FDI_DATA_P<7>

FDI_DATA_P<6>

FDI_DATA_P<4> FDI_DATA_P<5>

FDI_DATA_P<3>

FDI_LSYNC<0>

DMI_N2S_N<3>

FDI_LSYNC<1>

EDP_HPD_L

EDP_COMP

DP_INT_AUX_CH_N DP_INT_AUX_CH_P

DP_INT_ML_N<1>

DP_INT_ML_N<0>

TP_EDP_TX_N<3>

TP_EDP_TX_N<2>

TP_EDP_TX_P<2>

DP_INT_ML_P<1>

DP_INT_ML_P<0>

TP_EDP_TX_P<3>

=PEG_R2D_C_N<14> =PEG_R2D_C_N<15>

FDI_DATA_N<0> FDI_DATA_N<1>

=PEG_D2R_N<3>

=PEG_D2R_N<0>

=PEG_R2D_C_N<11> =PEG_R2D_C_N<12>

=PEG_R2D_C_N<6>

CPU_CFG<5> CPU_CFG<4>

CPU_CFG<7>

CPU_CFG<2>

CPU_CFG<0>

10 OF 109

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051-8871

9 OF 74

9

23

9

23 66

7 9

10 12 14

9

23 66

9

23 66

9

27 28 29 30 31 67

7

12

15

7

12 14

7 9

10 12 14

9

7 9

10 12 14

62

66

9

66

62 69

6

62 69

6

9

23 66

9

23 66

9

23 66

9

23 66

9

23 66

BI BI BI BI BI

IN

OUT

IN IN

OUT

BI

NC

OUT

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN IN

IN

OUT

IN IN

IN

OUT

IN

IN IN

IN

OUT

BI BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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8 7 5 4 2 1

(IPU) (IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

23 66

17 26 66

19 23 66

26

16 66

18

19 66

41 56 66

19 40 66

66

B46

J58

L55

D45

L59

M60

L56

BG43

BE43

BF44

AT30

BE45

D44

C45

F49

C57

N55

N53

C48

A48

AG1

AG3

K58

C49

J61

J59

H60

G59

G55

E59

E55

G58

N58

N59

H2

J3

U1000

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

2

1

R1101

62

5% 1/20W MF 201

2

1

R1104

201

MF

1/20W

5%

51

NOSTUFF

2

1

R1100

1K

5%

1/20W

MF

201

NOSTUFF

2

1

R1102

NOSTUFF

1K

5% 1/20W MF 201

21

R1103

201

MF

1/20W

5%

56

2

1

R1120

200

1%

1/20W

MF

201

21

R1121

1%

1/20W

MF

201

130

2

1

R1114

1%

MF

1/20W

200

201

2

1

R1113

1% 1/20W

201

MF

25.5

2

1

R1112

140

1% 1/20W MF 201

2

1

R1111

10K

201

MF

1/20W

5%

2

1

R1126

75

1%

1/20W

MF

201

21

R1125

43.2

1% MF

1/20W

201

2

1

R1115

1/20W MF

4.99K

1%

201

NOSTUFF

8

66

8

66

23 66

16 66

17 66

23 25

23 25 66

23 66

CPU CLOCK/MISC/JTAG

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

PLT_RESET_LS1V1_L

=MEM_RESET_L

CPU_PWRGD

PM_MEM_PWRGD_R

CPU_SM_RCOMP<0>

CPU_SM_RCOMP<2>

XDP_BPM_L<1>

PM_MEM_PWRGD

=PP1V5_S3_CPU_VCCDDR

CPU_PROCHOT_R_L

CPU_PROCHOT_L

CPU_CATERR_L

XDP_CPU_PREQ_L

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

CPU_PECI

CPU_RESET_L

=PP1V05_S0_CPU_VCCIO

CPU_SM_RCOMP<1>

PM_THRMTRIP_L

CPU_PROC_SEL_L

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_CPU_TDO

PM_SYNC

=PP1V05_S0_CPU_VCCIO

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_PRDY_L

DPLL_REF_CLKP DPLL_REF_CLKN

11 OF 109

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66

7

12 15 26

7 9

10 12 14

66

7 9

10 12 14

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

OUT OUT

OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SA_MA_14 SA_MA_15

SA_MA_12 SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5 SA_DQS_6

SA_DQS_3 SA_DQS_4

SA_DQS_2

SA_DQS_0 SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0* SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0 SA_BS_1 SA_BS_2

SA_DQ_62 SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50 SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42 SA_DQ_43

SA_DQ_41

SA_DQ_39 SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34 SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29 SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24 SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19 SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_11 SA_DQ_12

SA_DQ_9 SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12 SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7 SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0 SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34 SB_DQ_35

SB_DQ_33

SB_DQ_31 SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26 SB_DQ_27 SB_DQ_28

SB_DQ_24 SB_DQ_25

SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8 SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4 SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40 SB_DQ_41 SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

OUT OUT

OUT

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

27 67

28 67

27 28 32 67

29 67

30 67

29 30 32 67

27 28 32 67

27 67

28 67

27 67

28 67

27 28 32 67

8

67

29 30 32 67

29 67

30 67

29 67

30 67

29 30 32 67

8

67

AT41

BD39

BA41

AY40

AV32

AY32

AT32

BB32

AU34

AT34

BD35

BE35

AU26

AY28

AW41

BC30

BA30

BE37

BB34

BG35

AK55

AK54

AT55

AT56

AY51

AV51

AV45

AW45

AT17

AU17

AV11

AY11

AR8

AR10

AL11

AJ11

AP6

AR11

AL7

AK56

AG55

AN52

AN55

AL8

AG53

AG56

AN53

AN57

AP52

AP56

AT54

AV54

AP53

AP50

AJ8

AV56

BA55

BB55

BA53

AU49

BB49

AY53

BB51

AV49

BA49

AJ10

AY48

AT48

AR45

BC45

BC48

AW48

AR43

BA45

BB17

BB14

AL6

AU14

BA14

AR19

AY17

AR14

AV14

AY13

BB9

BA9

BA7

AP11

BB11

BA13

BB7

BC7

AU13

AT13

AP8

AR6

AV9

AU6

AJ6

AG6

BC41

BB40

BB26

AY26

AU40

AT40

AV36

AU36

BE39

BA28

BF36

BD37

U1000

SANDY-BRIDGE

MOBILE-2C-35W

CRITICAL

BGA

OMIT_TABLE

BD45

BF40

BG47

AT43

BE28

BE30

BD29

BG30

AV30

BD30

AU30

BD33

AU22

AT26

BD46

AV28

AT28

BD43

BE33

BF32

AK59

AK61

AT60

AR59

BA59

BA61

BG51

BE51

BD17

BD18

BG11

BE11

AV3

AV1

AL3

AM2

AT2

AU4

AR1

AH60

AF61

AL59

AM60

AN4

AG59

AG58

AL58

AK58

AR58

AN58

AU61

AU59

AN59

AN61

AK3

AU58

AW58

AW59

BA58

BG54

BE54

AY60

BC59

BE57

BF56

AK4

BE53

BD54

BE49

BD49

BF52

BD53

BF48

BD50

BF19

BG18

AR4

BG14

BE14

BE21

BE18

BE17

BF16

BE13

BD14

BD10

BF8

AN3

BF12

BD13

BD9

BE9

BA3

AY2

AR3

AU3

BA4

AV4

AL1

AL4

BE47

BE41

BF27

AR22

BB36

BA36

AY34

BA34

AV43

AT22

BD42

BG39

U1000

MOBILE-2C-35W

SANDY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

8

67

SYNC_DATE=12/13/2010

CPU DDR3 INTERFACES

MEM_B_DQ<27>

MEM_B_A<7>

MEM_A_DQ<46>

MEM_B_RAS_L MEM_B_WE_L

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_DQ<63> MEM_B_BA<0>

MEM_B_DQ<62>

MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQ<58> MEM_B_DQ<59>

MEM_B_DQ<57>

MEM_B_DQ<55> MEM_B_DQ<56>

MEM_B_DQ<53> MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<50> MEM_B_DQ<51>

MEM_B_DQ<48> MEM_B_DQ<49>

MEM_B_DQ<47>

MEM_B_DQ<45> MEM_B_DQ<46>

MEM_B_DQ<43> MEM_B_DQ<44>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<38> MEM_B_DQ<39>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<26>

MEM_B_DQ<29> MEM_B_DQ<30>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36> MEM_B_DQ<37>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>

MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<14> MEM_B_A<15>

MEM_A_DQS_P<1>

MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<26>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<31>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<41>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<44> MEM_A_DQ<45>

MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L

MEM_A_DQS_N<5> MEM_A_DQS_N<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<7>

MEM_A_A<0>

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<14> MEM_A_A<15>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_CLK_P<0>

MEM_A_DQS_N<7>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_CKE<0>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<15>

MEM_A_CLK_P<0>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_A<1>

MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<0>

MEM_A_CLK_N<0>

MEM_A_CLK_N<1> MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_ODT<1>

MEM_A_CLK_P<1> MEM_B_CLK_P<1>

MEM_B_CLK_N<1> MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_ODT<1>

12 OF 109

2.5.0

051-8871

11 OF 74

OUT OUT

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1 VCCPQE_2

VIDALERT*

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

VAXG_1 VAXG_2

VAXG_4

VAXG_3

VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25

VAXG_28

VAXG_26 VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31 VAXG_32

VAXG_35

VAXG_34

VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43

VAXG_45

VAXG_44

VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=1.25V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Fixed at 1.05V

(IPU)

(NOT controlled by VCCIO_SEL)

For Future Compatibility

(IPU)

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

56 66

58 66

53

56 66

53

AN17

G43

C44

B43

A44

AN22

AM25

W17

W16

AN16

BC22

AN48

AN45

AN42

AN20

AM47

AM43

AM21

AM17

AM16

AL48

AL45

AL26

AL22

AL20

AL16

AL15

AL14

AK51

AK50

AJ47

AJ43

AJ25

AJ21

AJ17

AJ15

AJ14

AG51

AG50

AG48

AG21

AG20

AG17

AG16

AG15

AF46

AF20

AF18

AF16

AE15

AE14

AD21

AD18

AD16

AC13

AB20

AB17

AA15

AA14

F43

N38

N34

N30

N26

L40

L36

L33

L28

L25

K42

K39

K37

K35

K34

K32

K29

K27

K26

J42

J40

J38

J37

J35

J34

J32

J29

J28

J26

J25

H40

H38

H37

H35

H34

H32

H29

H28

H26

H25

G42

F42

F38

F37

F34

F32

F28

F26

F25

E38

E37

E34

E32

E28

E26

D42

D39

D37

D34

D32

D27

C42

C39

C37

C34

C32

C27

C26

A42

A39

A38

A35

A34

A31

A29

A26

U1000

BGA

CRITICAL

OMIT_TABLE

MOBILE-2C-35W

SANDY-BRIDGE

G45

BA43

BC43

BG33

BB28

BA40

AW26

AV41

AR40

AR36

AR34

AR32

AR30

AR28

AR26

AN38

AN34

AN30

AM40

AM36

AM33

AL42

AL38

AL34

AL30

AJ40

AJ36

AJ33

AJ28

W20

D49

D48

V21

V18

V17

V16

U15

U10

R21

R18

R16

P20

P17

N22

N20

N16

L21

L17

BC4

BC1

BB3

AN26

AM28

Y61

Y48

W61

W56

W55

W53

W52

W51

W50

V59

V58

V56

V55

V53

V52

V51

V50

V48

V47

U46

T61

T59

T58

T48

F45

P61

P56

P55

P53

P52

P51

P50

P48

P47

N45

AE46

AD59

AD58

AD56

AD55

AD53

AD52

AD51

AD50

AD48

AD47

AC61

AB59

AB58

AB56

AB55

AB53

AB52

AB51

AB50

AB47

AA46

AY43

U1000

SANDY-BRIDGE

MOBILE-2C-35W

BGA

CRITICAL

OMIT_TABLE

21

R1311

MF05%

1/20W

201

21

R1312

MF05%

1/20W

201

21

R1310

43

201

1/20W

5% MF

2

1

R1302

PLACE_NEAR=U1000.C44:2.54mm

201

MF

1/20W

1%

130

2

1

R1320

10K

1/20W

5%

MF

201

2

1

R1300

201

MF

1/20W

1%

75

PLACE_NEAR=R1310.2:2.54mm

2

1

R1370

PLACE_NEAR=U1000.F45:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

100

1% 1/20W MF 201

2

1

R1371

PLACE_SIDE=BOTTOM

NOSTUFF

100

1%

1/20W

MF

201

PLACE_NEAR=U1000.G45:50.8mm

2

1

R1382

PLACE_NEAR=U1000.U10:50.8mm

201

MF

1/20W

1%

100

2

1

R1380

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.BC43:50.8mm

100

1%

1/20W

MF

201

2

1

R1381

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.BA43:50.8mm

201

1/20W

1%

100

MF

2

1

R1314

201

MF

5%

1/20W

10K

2

1

R1313

201

MF

5% 1/20W

10K

2

1

R1330

SM_VREF_EXT

5%

201

MF

1/20W

100

PLACE_NEAR=U1000.AY43:2.54mm

2

1

R1331

SM_VREF_EXT

100

1/20W

MF

201

5%

PLACE_NEAR=U1000.AY43:2.54mm

2

1

C1330

10% 16V X5R-CERM 0201

0.1UF

SM_VREF_EXT

PLACE_NEAR=U1000.AY43:2.54mm

2

1

R1362

PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=BOTTOM

201

MF

1/20W

1%

100

NOSTUFF

2

1

R1360

PLACE_NEAR=U1000.F43:50.8mm

NOSTUFF

100

1%

1/20W

MF

201

PLACE_SIDE=BOTTOM

2

1

R1361

100

1%

1/20W

MF

201

PLACE_NEAR=U1000.G43:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

2

1

R1363

201

MF

1/20W

1%

100

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AN17:50.8mm

SYNC_DATE=12/13/2010

CPU POWER

SYNC_MASTER=K21_MLB

CPU_AXG_SENSE_N

=PP1V8_S0_CPU_VCCPLL_R

CPU_AXG_SENSE_P

=PP3V3_S0_CPU_VCCIO_SEL

=PP1V05_S0_CPU_VCCIO

CPU_VCCSENSE_N

CPU_VCCIOSENSE_N

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VCCIOSENSE_P

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU_VCCAXG

CPU_DDR_VREF

VOLTAGE=0.75V

CPU_DDR_VREF

=PP1V5_S3_CPU_VCCDDR

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>

CPU_VDDQ_SENSE_N

=PP1V5_S3_CPU_VCCDDR

CPU_VDDQ_SENSE_P

CPU_VCCSASENSE

=PPVCCSA_S0_CPU

=PP1V05_S0_CPU_VCCIO

CPU_VIDALERT_L

CPU_VIDALERT_L_R

CPU_VIDSOUT

CPU_VIDSCLK

CPU_VCCIO_SEL

CPU_VIDSOUT_R

CPU_VIDSCLK_R

=PP1V05_S0_CPU_VCCPQE

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PPVCORE_S0_CPU

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

13 OF 109

2.5.0

051-8871

12 OF 74

7

14

7

7 9

12 14

7 9

10 12 14

7 9

12 15

12

7

10 12 15 26

7

10 12 15 26

7

12 15

7 9

10 12 14

7

14

7

15

7

12 15

7 9

12 14

7 9

12 15

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

(9 OF 9)

VSS

(8 OF 9)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Y59

Y58

Y47

Y4

W8

W46

W21

W18

W15

W13

V61

V20

U8

U13

T56

T55

T53

T52

T51

T50

T47

T1

R46

R4

R20

R17

P9

P59

P58

P21

P18

P16

P14

E61

E1

D59

C58

C3

BG57

BG5

BE58

BE4

BD59

BD3

BC61

A57

A5

N61

N56

N52

N51

N48

N47

N43

N40

N36

N33

N28

N25

N21

N17

N1

M6

M58

M4

M15

M11

L61

L48

L43

L38

L34

L30

L26

L22

L20

L16

K8

K51

K21

K11

J55

J49

J1

H58

H53

H4

H21

H17

H14

H10

G61

G6

G51

G48

F55

F40

F35

F29

F19

F15

F13

E40

E35

E3

E29

E25

D6

D58

D54

D50

D46

D43

D40

D4

D35

D29

D26

D22

D18

D14

D10

C40

C35

C29

BG53

BG49

BG45

BG41

BG37

BG28

BG24

BG21

BG17

BG13

U1000

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

BG9

BE5

BD8

BD56

BD52

BD48

BD44

BD40

BD36

BD32

BD27

BD23

BD19

BD16

BD12

BC57

BC5 BC13

BB53

BA51

BA48

BA32

BA26

BA21

BA17

BA11

BA1

AY9

AY58

AY55

AY49

AY45

AY41

AY4

AY36

AY30

AY19

AY14

AW7

AW61

AW43

AW13

AV55

AV48

AV40

AV34

AV22

AV21

AV17

AU7

AU51

AU32

AU28

AU11

AU1

AT58

AT52

AT45

AT4

AT36

AT19

AT14

AR7

AR61

AR48

AR41

AR21

AR17

AR13

AP7

AP55

AP51

AP10

AN54

AN50

AN47

AN43

AN40

AN36

AN33

AN28

AN25

AN21

AN1

AM58

AM48

AM45

AM42

AM4

AM38

AM34

AM30

AM26

AM22

AM20

AM13

AL61

AL47

AL43

AL40

AL36

AL33

AL28

AL25

AL21

AL17

AL13

AL10

AK52

AK1

AJ7

AJ48

AJ45

AJ42

AJ38

AJ34

AJ30

AJ26

AJ22

AJ20

AJ16

AJ13

AH58

AH4

AG7

AG61

AG52

AG47

AG18

AG14

AG10

AF59

AF58

AF56

AF55

AF53

AF52

AF51

AF50

AF48

AF47

AF21

AF17

AF1

AE8

AE13

AD61

AD4

AD20

AD17

AC6

AC46

AC14

AC10

AB61

AB48

AB21

AB18

AB16

AA8

AA56

AA55

AA53

AA52

AA51

AA50

AA13

AA1

A9

A53

A49

A45

A40

A37

A33

A28

A25

A21

A17

A13

U1000

OMIT_TABLE

CRITICAL

MOBILE-2C-35W

SANDY-BRIDGE

BGA

CPU GROUNDS

14 OF 109

2.5.0

051-8871

13 OF 74

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1640-C1645):

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

CPU VCCIO/VCCPQ DECOUPLING

PLACEMENT_NOTE (C1655-C1666):

CPU VCCPLL Low pass filter

Processor Load Line : -2.9 mOhms

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Note:The smallest 10mOhm available in the library are 0805s

PLACEMENT_NOTE (C1667-C1679):

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

CPU VCORE DECOUPLING

PLACEMENT_NOTE (C1646-C1671):

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

CPU VCCPLL DECOUPLING

PLACEMENT_NOTE (C1672-C1681):

PLACEMENT_NOTE (C1684-C167F):

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

21

R1601

0.010

MF

0603

1%

1/4W

2

1

C160Y

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

1UF

X5R 402

10% 10V

2

1

C1607

2.2UF

X5R 402

4V

20%

CRITICAL

2

1

C1608

CRITICAL

2.2UF

X5R 402

4V

20%

2

1

C1609

CRITICAL

2.2UF

X5R 402

20% 4V

2

1

C1610

CRITICAL

2.2UF

X5R 402

20% 4V

2

1

C1698

X5R 402

10% 10V

1UF

2

1

C1611

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1612

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1613

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1614

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1615

CRITICAL

2.2UF

402

20% 4V X5R

2

1

C1699

1UF

X5R 402

10% 10V

2

1

C161E

10UF

6.3V

20%

Place near U1000 on bottom side

CERM-X5R 0402-1

2

1

C162A

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C162B

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C162C

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C162D

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

2

1

C169A

1UF

X5R 402

10% 10V

2

1

C162E

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C167A

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C167B

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V 2

1

C167C

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

2

1

C167D

20% 2V

CASE-B2-SM

TANT

270UF

2

1

C1680

2V CASE-B2-SM

TANT

20%

270UF

2

1

C169B

1UF

X5R 402

10% 10V

2

1

C1657

X5R 402

4V

20%

22UF

CRITICAL

2

1

C1658

X5R

4V

20%

402

22UF

CRITICAL

2

1

C1659

CRITICAL

4V

20%

402

X5R

22UF

2

1

C1660

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1661

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1662

20% 4V

402

X5R

22UF

CRITICAL

2

1

C1663

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1664

20% 4V

402

X5R

22UF

CRITICAL

2

1

C1665

4V

20%

402

X5R

22UF

CRITICAL

2

1

C1666

X5R

4V

20%

402

22UF

CRITICAL

2

1

C1681

20% CASE-B2-SM

270UF

2V TANT

2

1

C1682

TANT

20% 2V

CASE-B2-SM

270UF

2

1

C1683

CASE-B2-SM

2V

20% TANT

270UF

2

1

C167E

270UF

TANT CASE-B2-SM

20% 2V

2

1

C167G

270UF

TANT CASE-B2-SM

20% 2V

2

1

C167H

270UF

TANT CASE-B2-SM

20% 2V

2

1

C160Z

2V

20% TANT

PLACE_NEAR=U1000.BC2:5mm

CASE-B2-SM

270UF

2

1

C1679

CASE-B2-SM

2V

20% TANT

270UF

2

1

C169C

1UF

X5R 402

10% 10V

2

1

C1684

X5R

10% 10V

402

1UF

Place on bottom side of U1000

2

1

C1685

Place on bottom side of U100.

1UF

X5R 402

10% 10V

2

1

C1686

Place on bottom side of U1000

X5R 402

10% 10V

1UF

2

1

C1655

CRITICAL

4V

20%

402

X5R

22UF

Place close to U1000 on top side.

2

1

C1656

22UF

4V

20%

402

X5R

CRITICAL

2

1

C1687

Place on bottom side of U1000

1UF

X5R 402

10% 10V

2

1

C1688

1UF

X5R 402

10% 10V

2

1

C1689

1UF

X5R 402

10% 10V

2

1

C167F

1UF

X5R 402

10% 10V

2

1

C1600

2.2UF

X5R

20% 4V

402

CRITICAL

2

1

C1601

2.2UF

X5R

20% 4V

402

CRITICAL

2

1

C1602

2.2UF

20% 4V

402

X5R

CRITICAL

2

1

C1603

402

20% X5R

4V

CRITICAL

2.2UF

2

1

C1604

X5R

4V

20%

402

2.2UF

CRITICAL

2

1

C1605

X5R 402

4V

20%

CRITICAL

2.2UF

2

1

C1606

CRITICAL

2.2UF

402

20% X5R

4V

2

1

C169D

1UF

X5R 402

10% 10V

2

1

C169E

1UF

X5R 402

10% 10V

2

1

C169F

1UF

X5R 402

10% 10V

2

1

C161A

1UF

X5R 402

10% 10V

2

1

C161B

1UF

X5R 402

10% 10V

2

1

C161C

1UF

X5R 402

10% 10V

2

1

C161D

1UF

X5R 402

10% 10V

2

1

C1690

1UF

X5R 402

10% 10V

2

1

C1691

1UF

X5R 402

10% 10V

2

1

C1692

1UF

X5R 402

10% 10V

2

1

C1693

1UF

X5R 402

10% 10V

2

1

C1697

1UF

X5R 402

10% 10V

2

1

C1694

1UF

X5R 402

10% 10V

2

1

C1695

1UF

X5R 402

10% 10V

2

1

C1696

1UF

X5R 402

10% 10V

2

1

C161F

Place near U1000 on bottom side

10UF

CERM-X5R

20%

6.3V 0402-1

21

R1600

0

402

5%

MF-LF

1/16W

2

1

C160X

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

1UF

X5R 402

10% 10V

Place near U1000 on top side

CPU DECOUPLING-I

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_CPU_VCCPLL_R

16 OF 109

2.5.0

051-8871

14 OF 74

7 9

10 12

7 9

12

7

12

7

12

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

VAXG DECOUPLING

PLACEMENT_NOTE (C1700-C1710):

Graphics Load Line : -3.9 mOhms

PLACEMENT_NOTE (C1717-C1722):

PLACEMENT_NOTE (C1711-C1716):

PLACEMENT_NOTE (C1738-C1747):

PLACEMENT_NOTE (C1758-C1762):

CPU VCCSA DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

CPU VDDQ/VCCDQ DECOUPLING

PLACEMENT_NOTE (C1723-C1724):

21

R1702

0603

0.010

1%

1/4W

MF

2

1

C1740

Place on bottom side of U1000

402

X5R

10V

10%

1UF

2

1

C1756

CASE-B2-SM

270UF

TANT

20% 2V

2

1

C1768

CASE-B2-SM

20% 2V TANT

270UF

2

1

C1711

CRITICAL

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1712

CRITICAL

10UF

20%

6.3V

0402-1

CERM-X5R

2

1

C1713

CRITICAL

6.3V

10UF

20%

0402-1

CERM-X5R

2

1

C1714

CRITICAL

10UF

CERM-X5R

20%

0402-1

6.3V

2

1

C1715

CRITICAL

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1716

CRITICAL

0402-1

20%

6.3V CERM-X5R

10UF

2

1

C1748

Place close to U1000 on bottom side

10UF

20%

CERM-X5R

6.3V

0402-1

2

1

C1717

6.3V

22UF

20%

CRITICAL

X5R-CERM1 0603

2

1

C1749

6.3V

Place close to U1000 on bottom side

10UF

CERM-X5R

20%

0402-1

2

1

C1751

0402-1

20%

6.3V CERM-X5R

10UF

Place close to U1000 on bottom side

2

1

C1752

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1753

0402-1

20%

6.3V CERM-X5R

10UF

Place close to U1000 on bottom side

2

1

C1755

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1763

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1764

0402-1

10UF

CERM-X5R

6.3V

20%

2

1

C1765

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1718

20%

6.3V

22UF

CRITICAL

X5R-CERM1 0603

2

1

C1766

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1767

0402-1

20%

6.3V CERM-X5R

10UF

2

1

C1723

270UF

20% 2V TANT CASE-B2-SM

2

1

C1724

270UF

20% 2V TANT CASE-B2-SM

2

1

C1725

270UF

20% 2V TANT CASE-B2-SM

2

1

C1754

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1750

6.3V

20%

Place close to U1000 on bottom side

10UF

CERM-X5R 0402-1

2

1

C1719

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1741

10V

10%

1UF

402

X5R

Place on bottom side of U1000

2

1

C1742

1UF

X5R 402

10% 10V

2

1

C1743

10V

402

1UF

10%

X5R

2

1

C1744

X5R

1UF

10% 10V

402

2

1

C1720

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1721

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1722

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

2

1

C1745

1UF

402

10V X5R

10%

2

1

C1746

10% 10V X5R

1UF

402

2

1

C1747

1UF

10%

X5R 402

10V

2

1

C1700

Place on bottom side of U1000

402

CRITICAL

10V X5R

10%

1UF

2

1

C1701

1UF

10%

CRITICAL

402

10V

Place on bottom side of U100.

X5R

2

1

C1702

CRITICAL

X5R 402

10V

10%

1UF

Place on bottom side of U1000

2

1

C1704

CRITICAL

1UF

402

10%

X5R

10V

2

1

C1705

1UF

CRITICAL

10% 10V

402

X5R

2

1

C1706

CRITICAL

10V

10%

1UF

X5R 402

2

1

C1757

X5R

10% 10V

402

1UF

2

1

C1707

402

CRITICAL

1UF

10% 10V X5R

2

1

C1708

CRITICAL

1UF

402

X5R

10V

10%

2

1

C1709

CRITICAL

1UF

10% 10V X5R 402

2

1

C1758

402

10V

10%

1UF

Place on bottom side of U1000

X5R

2

1

C1759

1UF

Place on bottom side of U100.

10V

402

X5R

10%

2

1

C1760

Place on bottom side of U1000

402

10V

10%

1UF

X5R

2

1

C1761

1UF

Place on bottom side of U1000

10V

402

10%

X5R

2

1

C1762

402

1UF

10%

X5R

10V

2

1

C1710

CRITICAL

1UF

402

X5R

10% 10V

2

1

C1703

CRITICAL

10V

10%

402

1UF

X5R

Place on bottom side of U1000

2

1

C1738

1UF

10V

Place on bottom side of U1000

10%

X5R 402

2

1

C1739

1UF

402

X5R

Place on bottom side of U100.

10V

10%

SYNC_MASTER=K21_MLB

CPU DECOUPLING-II

SYNC_DATE=12/13/2010

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

17 OF 109

2.5.0

051-8871

15 OF 74

7

12

7

12

7

10 12 26

7 9

12

IN

OUT

IN

BI

IN

IN OUT OUT

IN

IN OUT OUT

OUT OUT

OUT

IN

IN IN

IN

OUT

BI

OUT

BI

IN

IN OUT OUT

OUT

BI

IN

OUT OUT

IN

OUT

OUT OUT

NC

IN

IN OUT OUT

OUT

SRTCRST*

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0 HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1 RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

SATA1RXP SATA1TXN

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5TXN SATA5TXP

SATAICOMPO SATAICOMPI

SATALED*

SATA0GP/GPIO21 SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

RTC

IHDA

JTAG

SPI

SATA

LPC

(1 OF 10)

SMBDATA

SML0CLK

SML0ALERT*/GPIO60

SML0DATA

SML1ALERT*/PCHHOT*/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PETP1

PERP2

PERN2

PERP3 PETN3

PERN4

PETP3

PERP4 PETN4

PERN5

PETP4

PERP5 PETN5 PETP5

PERN6 PERP6

PETP6

PETN6

PERN7 PERP7 PETN7

PERN8

PETP7

PETN8

PERP8

PETP8

SMBALERT*/GPIO11

SMBCLK

PERN1

PETN1

CLKOUT_PCIE0P

CLKOUT_PCIE0N

PERP1

PETN2 PETP2

PERN3

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1*/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ*/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7*/GPIO46

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CL_DATA1

CL_CLK1

CL_RST1*

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_SATA_P

CLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLK

FLEX CLOCK

LINK

CNTRL

SMBUS

PCI-E*

(2 OF 10)

IN

OUT

IN

OUT

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.5V -> 1.1V

DOES THIS NEED LENGTH MATCH???

PLACE THIS RESISTOR NEAR THE PCH PIN

(IPU)

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

Pullup needed for SPI_DESCRIPTOR_OVERRIDE_L? PD needed for BCM_MEDIA_SENSE?

25 69

6

39 69

42 69

6

40 42

37 68

6

36 69

6

36 69

6

36 69

6

36 69

10 66

8

69

8

69

8

25 68

43 69

8

43 69

16 33

16 36

16

8

69

8

69

16 35

16

23

33 69

25 69

8

68

8

68

8

68

8

68

19

A23

N1

W8

Y2

AB6

AB8

AD12

Y4

W10

AB10 AB12

AJ1

AJ3

AC1

AC3

AH6

AH8

AE1

AE3

AG1

AG3

AD6

AD8

AF10

AH4

AF12

AL1

AL3

AD2

AD4

AR1

AR3

AN8

AN6

R1

AU1

AU3

AN1

AN3

M2

C19

A19

F19

F37

H40

M15

M12

U12

M17

C21

K22

H37

K37

A35

C35

B36

D36

F35

M35

K35

H35

K40

C37

C39

A39

A37

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

W51

W49

AC49

C11

D12

C9

A9

K12

H22

F10

F17

H12

J49

BB40

BB37

BF37

BB35

BF35

BD33

AY33

AY30

AY40

AY37

BD37

AY35

BD35

BF33

BB33

BB30

BL43

BL41

BK40

BL39

BL37

BK36

BL35

BL33

BJ43

BJ41

BH40

BJ39

BJ37

BH36

BJ35

BJ33

C4

R8

H4

J3

K8

M19

B8

T4

U8

M4

J51

G49

D48

H50

AF42

AF40

AF46

AF44

W46

W44

AB46

AB44

AB42

AB40

Y50

Y48

AA51

AA49

AD42

AD40

AE51

AE49

AD50

AD48

AR10

AR12

AN12

AN10

AY24

BB24

AK6

AK8

E51

AY26

BB26

K24

M24

BF17

BD17

M8

J1

L3

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

16

2

1

R1876

10K

MF

201

5%

1/20W

21

R1811

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.H37:1.27mm

21

R1810

PLACE_NEAR=U1800.H35:1.27mm

33

MF

201

5%

1/20W

21

R1813

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.K37:1.27mm

21

R1812

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.F35:1.27mm

2

1

R1842

1/20W

MF

5%

201

10K

2

1

R1834

10K

201

5%

1/20W

MF

2

1

R1844

10K

5%

1/20W

201

MF

2

1

R1833

NOSTUFF

10K

5%

201

MF

1/20W

2

1

R1847

MF

201

5%

1/20W

10K

2

1

R1849

10K

5%

NOSTUFF

1/20W

201

MF

2

1

R1845

MF

1/20W

5%

10K

201

2

1

R1846

10K

201

1/20W

5% MF

2

1

R1848

1/20W

201

MF

10K

5%

2

1

R1866

NOSTUFF

10K

MF

201

5%

1/20W

40

2

1

R1800

330K

5%

201

MF

1/20W

21

R1880

0

MF

201

5%

1/20W

NOSTUFF

PLACE_NEAR=R1813.1:2.54mm

2

1

R1853

10K

MF 201

5% 1/20W

2

1

R1855

1/20W

5%

201

MF

10K

2

1

R1854

1/20W

5%

201

MF

10K

21

R1888

NOSTUFF

0

MF

201

5%

1/20W

19 40

21

R1841

0

5%

1/20W

MF

201

NOSTUFF

21

R1840

0

5%

1/20W

MF

201

NOSTUFF

6

39 69

6

39 69

6

39 69

6

39 69

2

1

R1850

10K

MF

201

5%

1/20W

2

1

R1851

1/20W

5%

201

MF

10K

21

R1860

5%

1/20W

MF

201

33

6

40

42 69

6

40

42 69

21

R1864

201

MF

1/20W

5%

33

6

40

42 69

21

R1861

5%

1/20W

MF

201

33

6

40

42 69

21

R1862

201

MF

1/20W

5%

33

6

40

42 69

21

R1863

5%

1/20W

MF

201

33

2

1

R1820

10K

MF 201

5% 1/20W

2

1

R1830

MF

PLACE_NEAR=U1800.AB10:2.54mm

37.4

201

1%

1/20W

2

1

R1899

10K

MF

201

5%

1/20W

2

1

R1877

1/20W

5%

201

MF

4.7K

2

1

R1878

5%

1/20W

4.7K

201

MF

2

1

R1831

PLACE_NEAR=U1800.AF12:2.54mm

49.9

MF

201

1%

1/20W

2

1

R1832

PLACE_NEAR=U1800.AH4:2.54mm

750

MF

201

1%

1/20W

2

1

R1803

20K

MF 201

5% 1/20W

2

1

R1802

MF

5%

1/20W

20K

201

2

1

R1801

1M

MF 201

5% 1/20W

2

1

C1803

6.3V

20%

1.0UF

X5R 0201-MUR

2

1

C1802

6.3V X5R

0201-MUR

20%

1.0UF

2

1

R1871

201

MF

1/20W

5%

10K

2

1

R1870

10K

1/20W

MF

201

5%

21

R1885

1/20W

1%201 MF

604

PLACE_NEAR=U1800.W49:5.1mm

2

1

R1886

PLACE_NEAR=R1885.1:2.54mm

1K

MF 201

1% 1/20W

2

1

R1890

PLACE_NEAR=U1800.W49:2.54mm

90.9

MF

201

1%

1/20W

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

PCH SATA/PCIE/CLK/LPC/SPI

PCH_INTVRMEN_L

PCH_INTRUDER_L

SPI_MOSI_R

PCH_SPKR

SMC_SCI_L

HDA_SYNC_R

TP_SATA_B_D2RN TP_SATA_B_D2RP

SATA_HDD_D2R_P

LPC_SERIRQ

TP_SATA_B_R2D_CP

PCH_SATA3RBIAS

PCH_SATA3COMP

PCH_SATAICOMP

SPI_MISO

PCIECLKRQ5_L_GPIO44

HDA_SDOUT_R

JTAG_T29_TMS ENET_MEDIA_SENSE

TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

PCH_SATALED_L

TP_SATA_E_R2D_CP

TP_SATA_D_R2D_CN

PCH_SRTCRST_L

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

RTC_RESET_L

PCH_INTRUDER_L PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_RST_R_L

HDA_SDIN0 TP_HDA_SDIN1 TP_HDA_SDIN2

XDP_PCH_TCK

SPI_CS0_R_L

SPI_CLK_R

SYSCLK_CLK32K_RTC

SATA_HDD_D2R_N

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN

TP_SATA_F_D2RN

DP_AUXCH_ISOL SATARDRVR_EN

HDA_SDOUT_R

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_RST_R_L

HDA_RST_L

ITPCPU_CLK100M_N

ITPXDP_CLK100M_P ITPCPU_CLK100M_P

HDA_SDOUT_R

TP_HDA_SDIN3

XDP_PCH_TMS

XDP_PCH_TDO

TP_SPI_CS1_L

HDA_BIT_CLK_R

TP_SATA_D_R2D_CP

TP_SATA_D_D2RP

=PP3V3_S0_PCH

=PP1V05_S0_PCH_VCCIO_SATA

ENET_MEDIA_SENSE

=PP1V05_S0_PCH

SPI_DESCRIPTOR_OVERRIDE_L

PCH_GPIO11

XDP_PCH_TDI

PCH_SRTCRST_L

=PP1V05_S0_PCH_VCCDIFFCLK

DP_AUXCH_ISOL

SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_D_D2RN

TP_SATA_B_R2D_CN

T29_PWR_EN_PCH

TP_LPC_DREQ0_L

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO64_CLKOUTFLEX0

PCH_XCLK_RCOMP

PCH_CLK33M_PCIIN

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLKIN_GNDP1

PCH_CLKIN_GNDN1

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

TP_PCH_CLKOUT_DPP

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

PEG_CLK100M_P

PEG_CLK100M_N

PEG_CLKREQ_L

TP_CLINK_RESET_L

TP_CLINK_CLK TP_CLINK_DATA

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

PCH_GPIO46

TP_PCIE_CLK100M_PE7P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE6N

PEG_B_CLKRQ_L_GPIO56

TP_PCIE_CLK100M_PEBP

TP_PCIE_CLK100M_PEBN

PCIECLKRQ5_L_GPIO44

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE5N

T29_CLKREQ_L

PCIE_CLK100M_T29_P

PCIE_CLK100M_T29_N

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

PCIECLKRQ2_L_GPIO20

TP_PCIE_CLK100M_PE2P

TP_PCIE_CLK100M_PE2N

AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIECLKRQ0_L_GPIO73

NC_PCIE_3_D2RN

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

NC_PCIE_1_D2RP

TP_PCIE_CLK100M_PE0N TP_PCIE_CLK100M_PE0P

NC_PCIE_1_R2D_CN

NC_PCIE_1_D2RN

SMBUS_PCH_CLK

PCH_GPIO11

NC_PCIE_8_R2D_CP

NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN

NC_PCIE_7_R2D_CP NC_PCIE_8_D2RN

NC_PCIE_7_R2D_CN

NC_PCIE_7_D2RP

NC_PCIE_7_D2RN

NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP

NC_PCIE_6_D2RP

NC_PCIE_6_D2RN

NC_PCIE_5_R2D_CP

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RP

PCIE_EXCARD_R2D_C_P NC_PCIE_5_D2RN

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

NC_PCIE_3_R2D_CP PCIE_EXCARD_D2R_N

NC_PCIE_3_R2D_CN

NC_PCIE_3_D2RP

PCIE_AP_D2R_N PCIE_AP_D2R_P

NC_PCIE_1_R2D_CP

SML_PCH_1_DATA

SML_PCH_1_CLK

SML_PCH_1_ALERT_L

SML_PCH_0_DATA

SML_PCH_0_ALERT_L SML_PCH_0_CLK

SMBUS_PCH_DATA

PCH_CLK14P3M_REFCLK

SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_SB

SML_PCH_0_ALERT_L

=PP3V3_SUS_GPIO

SML_PCH_1_ALERT_L

=PP3V3_S0_PCH_STRAPS

SATARDRVR_EN

PCIECLKRQ0_L_GPIO73

PEG_B_CLKRQ_L_GPIO56

=PPVRTC_G3_PCH

RTC_RESET_L

LPC_R_AD<0>

LPC_AD<0>

LPC_R_AD<1>

LPC_AD<1>

LPC_R_AD<2>

LPC_AD<2>

LPC_R_AD<3>

LPC_AD<3>

LPC_FRAME_R_L

LPC_FRAME_L

SATA_ODD_D2R_N

JTAG_T29_TMS PCH_SPKR AP_CLKREQ_L PCH_SATALED_L EXCARD_CLKREQ_L

=PP3V3_T29_PCH_GPIO

T29_CLKREQ_L PEG_CLKREQ_L

=PP3V3_S0_PCH_STRAPS

PCIECLKRQ2_L_GPIO20

WOL_EN TP_PCIE_CLK100M_PE7N

ITPXDP_CLK100M_N

=PP3V3_SUS_GPIO

HDA_SYNC_R

=PP3V3R1V5_S0_PCH_VCCSUSHDA

HDA_SDOUT_R

18 OF 109

2.5.0

051-8871

16 OF 74

16

16 69

6

68

16

16 69

6

16

6

16

16 69

6

16 23 63

16 23

16 69

10 66

16 23 66 10 66

16 69

6

16 69

6

7

19 22

7

20 22

16

7

22

16

7

20 22

16 23 63

6

16 23 66

19

6

16

6

16

6

16

69

16

7

16 17 18 19

16

7

16 17 19

16 23

16

7

17 20

16

16 33

16

16 36

16

7

19

16 35

16

7

16 17 19

16

19

6

16 23 66

7

16 17 18 19

16 69

7

20 22

16 69

IN

OUT

OUT OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

ACPRESENT/GPIO31

SUSWARN*/SUSPWRDNACK/GPIO30

DPWROK

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

RSMRST*

APWROK

PWRBTN*

SLP_S3*

DMI_IRCOMP

DMI0TXN

DMI2RXN

DRAMPWROK

FDI_RXN6 FDI_RXN7

FDI_RXP0

FDI_RXP3

FDI_RXP1 FDI_RXP2

FDI_RXP5

FDI_RXP4

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI_LSYNC1

WAKE*

CLKRUN*/GPIO32

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S5*/GPIO63

SLP_S4*

SLP_A*

SLP_LAN*/GPIO29

PMSYNCH

DSWVRMEN

SLP_SUS*

SUSACK*

DMI2TXN

DMI1TXN

DMI0TXP

DMI3TXN

DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

SYS_RESET*

SYS_PWROK

PWROK

BATLOW*/GPIO72

RI*

FDI_RXN0 FDI_RXN1

FDI_RXN3

FDI_RXN2

FDI_RXN4 FDI_RXN5

DMI0RXN

DMI3RXN

FDI_RXP6

DMI2RBIAS

DMI1RXN

FDI

DMI

SYSTEM POWER

MANAGEMENT

(3 OF 10)

L_VDD_EN

L_DDC_DATA

L_DDC_CLK

L_CTRL_DATA

L_CTRL_CLK

L_BKLTEN

L_BKLTCTL

LVD_VREFL

LVD_VREFH

LVD_VBG

LVD_IBG

LVDSB_DATA_3*

LVDSB_DATA_2*

LVDSB_DATA_1*

LVDSB_DATA_0*

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

LVDSB_DATA0

LVDSB_CLK* LVDSB_CLK

LVDSA_DATA_3*

LVDSA_DATA_2*

LVDSA_DATA_1*

LVDSA_DATA_0*

LVDSA_DATA3

LVDSA_DATA2

LVDSA_DATA1

LVDSA_DATA0

LVDSA_CLK* LVDSA_CLK

SDVO_TVCLKINP

SDVO_TVCLKINN

SDVO_STALLP

SDVO_STALLN

SDVO_INTP

SDVO_INTN

SDVO_CTRLDATA

SDVO_CTRLCLK

DDPB_AUXN DDPB_AUXP

DDPB_0N

DDPB_HPD

DDPB_0P DDPB_1N DDPB_1P

DDPB_2P

DDPB_2N

DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_1P

DDPC_0P DDPC_1N

DDPC_2P

DDPC_2N

DDPC_3P

DDPC_3N

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXP

DDPD_AUXN

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N

DDPD_3N

DDPD_2P

DDPD_3P

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC

DAC_IREF

CRT_VSYNC

CRT_IRTN

LVDS

CRT

DIGITAL DISPLAY INTERFACE

(4 OF 10)

NC NC

NC

NC NC

NC NC NC

NC

NC NC

OUT OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Set to Vcc when High

.

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low

9

66

9

66

9

66

9

66

9

66

9

66

6

17 36

6

17 40 42

41

40 61

26 40 48 61

26 40 61

10 26 66

61

17 23 40

17 41

25

40

23 25

25 40

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

10 66

6

40 42

40 41 61

17

19 25

17

D8L1

M10

C13

D3

F15

G6

A15

F6

K10

D4

A7

C7

B20

F12

M22

K19

BB8

BD10

BL9

BB12

BB15

BL11

BF12

BL15

BJ13

BF10

BJ9

AY12

AY15

BJ11

BD12

BJ15

BL13

BH8

BK12

BB10

BK8

BH12

F22

B12

A21

BF19 BD19

AY17

BB17

BJ17

BL17

AY19

BB19

BL19

BJ19

BK20

AY22

BB22

BJ23

BL23

BF22

BD22

BJ21

BL21

T2

H10

G3

H19

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

AU42

AU40

AR49

AR51

AT48

AT50

R44

W42

AH50

AJ51

AL49

AM50

AH48

AJ49

AL51

AM48

AH46 AH44

AK40

AN44

AN49

AR46

AK42

AN46

AN51

AR44

AK44 AK46

AG49

AG51

AH40

AH42

M42

K46

L51

M40

R42

M44

L49

BK44

U42

M48

AU44

AU46

BJ45

BL45

BL47

BJ47

BD42

BF42

BG49

BG51

BE46

U44

T50

AU49

AU51

BE51

BE49

BF45

BF46

BD50

BD48

BC51

BC49

AY42

AW49

AW51

BA51

BA49

BB46

BB44

AY46

AY44

AY50

AY48

R51

N51

U46

T48

M50

R46

N49

R49

M46

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

2 1

R1986

0

MF

201

5%

1/20W

2

1

R1984

10K

MF

201

5%

1/20W

NOSTUFF

2

1

R1925

201

1K

1/20W

1% MF

2

1

R1985

1K

MF 201

1% 1/20W

2

1

R1905

10K

MF

201

5%

1/20W

2

1

R1900

PLACE_NEAR=U1800.BF19:12.7mm

49.9

MF 201

1% 1/20W

2

1

R1920

750

MF 201

1% 1/20W

PLACE_NEAR=U1800.BK20:2.54mm

2

1

R1909

100K

MF 201

5% 1/20W

2

1

R1915

390K

MF

201

5%

1/20W

2

1

R1983

1/20W

5%

201

MF

10K

2

1

R1982

MF

201

1/20W

10K

5%

2

1

R1991

MF

1/20W

5%

8.2K

201

2

1

R1951

PLACE_NEAR=U1800.R51:2.54mm

1K

MF 201

5% 1/20W

8

2

1

R1955

201

1/20W

100K

5% MF

63

PCH DMI/FDI/GRAPHICS

TP_DP_IG_D_MLP<1>

FDI_DATA_N<5>

FDI_DATA_N<4>

FDI_DATA_N<3>

PM_CLKRUN_L

PM_PWRBTN_L

PM_SLP_SUS_L

PCH_DSWVRMEN

=PP3V3_S0_PCH_STRAPS

PCH_DMI_COMP

=PP1V05_S0_PCH_VCCIO_PCIE

=T29_WAKE_L

MAKE_BASE=TRUE

PCIE_WAKE_L

PCH_SUSACK_L

FDI_FSYNC<0>

FDI_LSYNC<0> FDI_LSYNC<1>

PM_CLKRUN_L

PM_CLK32K_SUSCLK_R PM_SLP_S5_L PM_SLP_S4_L

PCH_SUSACK_L

FDI_DATA_P<1>

LVDS_IG_BKL_PWM

PM_PCH_SYS_PWROK

FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6>

FDI_INT

FDI_DATA_P<2>

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

DP_IG_B_DDC_DATA

DP_IG_B_DDC_CLK

DP_IG_B_AUX_N DP_IG_B_AUX_P

TP_DP_IG_B_MLN<0>

DP_IG_B_HPD

TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUXN TP_DP_IG_C_AUXP TP_DP_IG_C_HPD

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXP

TP_DP_IG_D_AUXN

TP_DP_IG_D_HPD TP_DP_IG_D_MLN<0>

TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLP<3>

TP_CRT_IG_BLUE TP_CRT_IG_GREEN TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK TP_CRT_IG_DDC_DATA

TP_CRT_IG_HSYNC

PCH_DAC_IREF

TP_CRT_IG_VSYNC

=PPVRTC_G3_PCH

FDI_FSYNC<1>

LPC_PWRDWN_L

PM_DSW_PWRGD

PM_BATLOW_L

PCH_DMI2RBIAS

PM_SYNC GPIO29_SLP_LAN_L

FDI_DATA_P<7>

FDI_DATA_P<3>

FDI_DATA_N<2>

FDI_DATA_N<1>

FDI_DATA_N<0>

FDI_DATA_N<7>

FDI_DATA_N<6>

FDI_DATA_P<0>

SMC_ADAPTER_EN

PCH_SUSWARN_L

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<0>

PM_RSMRST_L

PM_PCH_APWROK

PM_PWRBTN_L

DMI_N2S_N<2>

PM_MEM_PWRGD

DMI_S2N_N<2>

DMI_S2N_P<0>

DMI_S2N_N<3>

PM_SYSRST_L

PM_PCH_PWROK

DMI_N2S_N<0>

DMI_N2S_N<3>

DMI_N2S_N<1>

=PP3V3_S5_PCH

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

TP_PM_SLP_A_L

PM_SLP_S3_L

DMI_S2N_P<2>

DMI_S2N_P<1>

PCH_RI_L

DMI_N2S_P<3>

DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_P<3>

=PP3V3_SUS_GPIO

GPIO29_SLP_LAN_L PM_BATLOW_L

=PP3V3_SUS_GPIO

PCH_SUSWARN_L

=PP3V3_SUS_GPIO

PCIE_WAKE_L

PCH_SUSWARN_L

19 OF 109

2.5.0

051-8871

17 OF 74

9

66

9

66

9

66

6

17 40 42

17 23 40

61

7

16 19

17

9

66

9

66

9

66

9

66

9

66

6

8

6

7

16 20

17

9

66

9

66

9

66

9

66

9

66

9

66

9

66

9

66

7

19

7

16 17 18 19

17

17 41

7

16 17 18 19

17

7

16 17 18 19

6

17 36

17

IN

BI BI

IN IN

TP20

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

TP7

TP6

TP5

TP4

TP3

TP2

TP1

RSVD_BE3 RSVD_BE1 RSVD_AU8 RSVD_BJ7

RSVD_BH3

RSVD_BA3

RSVD_AU6

RSVD_AW1

RSVD_AW3

RSVD_AY6 RSVD_AY2 RSVD_AY4

RSVD_BC1

RSVD_BC3

RSVD_BG1 RSVD_BG3 RSVD_BE6

RSVD_BF7

RSVD_BH4

RSVD_BJ4 RSVD_BJ5 RSVD_BK6

DF_TVS

RSVD_AY8

RSVD_BL5

RSVD_BB6

RSVD_BD2 RSVD_BD4

RSVD_BF6

RSVD_BA1

USBP0N

USBP1N

USBP0P

USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11P

USBP11N

USBP12N USBP12P

USBP13P

USBP13N

USBRBIAS*

USBRBIAS

TP22

TP21

TP23 TP24 TP41 TP42

TP25 TP26 TP27 TP28 TP29

TP31

TP30

TP32 TP33 TP34 TP35 TP36 TP37 TP38

TP40

TP39

PIRQB*

PIRQA*

PIRQC*

REQ1*/GPIO50

PIRQD*

REQ2*/GPIO52 REQ3*/GPIO54

GNT1*/GPIO51 GNT2*/GPIO53

PIRQE*/GPIO2

GNT3*/GPIO55

PIRQH*/GPIO5

PIRQG*/GPIO4

PIRQF*/GPIO3

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2 CLKOUT_PCI3

CLKOUT_PCI1

CLKOUT_PCI4

OC1*/GPIO40

OC0*/GPIO59

OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

TP

RSVD

PCI

USB

(5 OF 10)

NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC NC

NC

NC NC

NC

NC NC

NC

BI BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ON AP_PWR_EN IF ISOLATION RESISTOR R2090 IS UNSTUFFED

NOTE: PULLUP IS REQUIRED

FIXME: NEED INTEL APPROVAL OF NC ON TPS

PUs TO S0 INSTEAD?

USB HUB 1

Unused

USB HUB 2

Unused

Camera

Unused

6

39

6

39 68

6

39 68

63

6

39

C33 A33

A29

C29

K28

M28

B32

D32

F26

H26

B28

D28

K26

M26

F28

H28

A27

C27

A25

C25

K33

M33

F30

H30

F33

H33

A31

C31

H24

F24

AR42

AR40

AN40

AN42

BH16

BB42

BH49

BD30

BK16

BD28

AY28

BD26

BF30

BF28

BB28

BF26

BL29

BL31

BL27

BH20

BL25

BJ29

BJ31

BJ27

BJ25

K30

W40

BL7

BJ48

AD46

BK24

AD44

D24

B24

AD10

AT2

AT4

AM4

E3

M30

D20

BH24

BL5

BK6

BJ7

BJ5

BJ4

BH4

BH3

BG3

BG1

BF7

BF6

BE6

BE3 BE1

BD4

BD2

BC3 BC1

BB6

BA3

BA1

AY8

AY6

AY4

AY2

AW3 AW1

AU8

AU6

F46

K44

G46

H2

F7

F40

F45

C41

A47

C45

C47

C48

D49

H15

C23

B16

A11

D16

A13

A17

C17

D44

H42

F42

BC7

G45

J43

H48

E49

G51

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

2

1

R2054

1/20W

5%

201

MF

10K

NOSTUFF

2

1

R2053

1/20W

5%

201

MF

10K

NOSTUFF

2

1

R2052

10K

MF

201

5%

1/20W

NOSTUFF

2

1

R2068

10K

1/20W

5%

201

MF

2

1

R2069

1/20W

5%

201

MF

10K

2

1

R2065

1/20W

5%

201

MF

10K

2

1

R2067

1/20W

5%

201

MF

10K

2

1

R2064

5%

201

MF

10K

1/20W

2

1

R2062

1/20W

5%

201

MF

10K

2

1

R2061

1/20W

5%

201

MF

10K

2

1

R2060

1/20W

5%

201

MF

10K

2

1

R2081

1/20W

5%

201

MF

2.2K

2

1

R2070

1/20W

1%

201

MF

22.6

PLACE_NEAR=U1800.C33:2.54mm

2 1

R2015

NOSTUFF

1/20W

5%

10K

201 MF

2 1

R2031

1/20W

5% MF

10K

201

2 1

R2030

5%201 MF

10K

1/20W

2 1

R2018

1/20W

5%201 MF

10K

2 1

R2017

1/20W

5%201 MF

10K

2 1

R2016

1/20W

5%201 MF

10K

2 1

R2013

1/20W

5%201 MF

10K

2 1

R2012

1/20W

5%201 MF

10K

2 1

R2011

1/20W

5%201 MF

10K

2 1

R2010

1/20W

5%201 MF

10K

2 1

R2090

0

5% MF

1/20W

201

21

R2080

201

5% MF

1/20W

1K

24 68

25 26

25

25 69

25

SYNC_DATE=12/13/2010

PCH PCI/FLASHCACHE/USB

SYNC_MASTER=K21_MLB

PCH_GPIO59_OC0_L

USB_HUB_SOFT_RESET_L

ENET_PWR_EN

PCH_GPIO14_OC7_L

PCH_GPIO43_OC4_L SDCONN_STATE_CHANGE PCH_GPIO10_OC6_L

PCH_PCI_GNT1_L

PCH_PCI_GNT2_L

T29_MCU_INT_L

=PP3V3_S0_PCH_GPIO

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

PCH_DF_TVS

TP_PM_TEST_RST_L

USB_HUB1_UP_N

NC_USB_1N

USB_HUB1_UP_P

NC_USB_1P NC_USB_2N

NC_USB_2P NC_USB_3N

NC_USB_3P NC_USB_4N

NC_USB_4P NC_USB_5N

NC_USB_5P NC_USB_6N

NC_USB_6P NC_USB_7N

NC_USB_7P

USB_HUB2_UP_P USB_CAMERA_N

USB_CAMERA_P NC_USB_10N

NC_USB_10P

NC_USB_11P

NC_USB_11N

NC_USB_12N NC_USB_12P

NC_USB_13P

NC_USB_13N

PCH_USB_RBIAS

PCI_INTB_L

PCI_INTA_L

PCI_INTC_L

JTAG_GMUX_TMS

PCI_INTD_L

T29_A_HV_EN_L PCI_REQ3_L

PCH_PCI_GNT1_L PCH_PCI_GNT2_L

PCI_INTE_L

PCH_PCI_GNT3_L

AUD_I2C_INT_L

AUD_IP_PERIPHERAL_DET

TP_PCI_PME_L

LPC_CLK33M_SMC_R

PLT_RESET_L

TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

SDCONN_STATE_RST_L

USB_HUB2_UP_N

PCH_PCI_GNT3_L

=PP3V3_S3_PCH_GPIO =PP3V3_SUS_GPIO

AP_PWR_EN

20 OF 109

2.5.0

051-8871

18 OF 74

23

23 24

23

18

7

68

18

6

23

18

7

19

7

16 17 19

36 61

OUT

BI

IN

OUT

IN

BI

IN

INIT3_3V*

PROCPWRGD THRMTRIP*

RCIN*

PECI

TACH1/GPIO1 TACH2/GPIO6

BMBUSY*/GPIO0

TACH7/GPIO71

TACH6/GPIO70

GPIO57

TACH4/GPIO68

SDATAOUT1/GPIO48 SATA5GP/GPIO49

SDATAOUT0/GPIO39

SLOAD/GPIO38

SATA2GP/GPIO36

GPIO35

GPIO28

GPIO27

SCLOCK/GPIO22 GPIO24/MEM_LED

TACH0/GPIO17

GPIO8 LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

A20GATE

SATA4GP/GPIO16

GPIO15

STP_PCI*/GPIO34

TACH5/GPIO69

SATA3GP/GPIO37

VSS_NCTF_A4

VSS_NCTF_A48

VSS_NCTF_A5

VSS_NCTF_A49

VSS_NCTF_BH51

VSS_NCTF_A51 VSS_NCTF_BH1

VSS_NCTF_BJ3

VSS_NCTF_BJ1

VSS_NCTF_BJ49

VSS_NCTF_BL1

VSS_NCTF_BJ51

VSS_NCTF_BL3 VSS_NCTF_BL4

VSS_NCTF_BL48

VSS_NCTF_BL51

VSS_NCTF_BL49

VSS_NCTF_C3 VSS_NCTF_C49 VSS_NCTF_C51

VSS_NCTF_D51

VSS_NCTF_D1

VSS_NCTF_E1

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

NCTF

GPIO

CPU

MISC

(6 OF 10)

Y

A

B

08

Y

A

B

08

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

GPIO[68:71] have 15K-45K internal PUs

ALL RSVD TPs NC-ed per INTEL approval

(IPU)

This has internal pull up and should not pulled low.

(NC-ed per Intel chklist)

(PU necessary?)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(PUs necessary?)

(PU necessary?)

10 23 66

19 23 26

6

42

19 23

19

19 23

19

8

19 23

8

19

6

19 42 49

10 66

16 19 40

19 40 41

E1

D51

D1

C51

C49

C3

BL51

BL49

BL48

BL4

BL3

BL1

BJ51

BJ49

BJ3

BJ1

BH51

BH1

A51

A5

A49

A48

A4

AH10

AK12

AH12

AK10

BC9

A41

D40

A43

K42

A45

C43

B40

B44

R3

N3

U1

U10

W3

AA1

AA3

M6

W6

U6 AU10

AU12

U40

C5 R6

H17

K17

W12

G1

C15

K15

K6

W1 U3

U1800

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

2

1

R2186

10K

MF

201

5%

1/20W

2

1

R2185

10K

MF

201

5%

1/20W

2

1

R2184

1/20W

5%

201

MF

10K

2

1

R2115

1/20W

5%

201

MF

10K

2

1

R2114

10K

MF

201

5%

1/20W

2

1

R2172

1/20W

5%

201

MF

10K

DRAM_CFG3:H

2

1

R2173

MF

1/20W

5%

201

10K

DRAM_CFG2:H

2

1

R2174

1/20W

5%

201

MF

10K

DRAM_CFG1:H

2

1

R2160

10K

MF

201

5%

1/20W

2

1

R2175

10K

MF

201

5%

1/20W

DRAM_CFG0:H

2

1

R2113

1/20W

5%

201

MF

10K

2

1

R2112

10K

MF

201

5%

1/20W

2

1

R2194

1/20W

5%

201

MF

10K

2

1

R2193

1/20W

5%

201

MF

100K

2

1

R2192

10K

MF

201

5%

1/20W

2

1

R2191

1/20W

201

MF

10K

5%

2

1

R2130

NOSTUFF

1K

MF

201

5%

1/20W

2

1

R2197

NOSTUFF

10K

MF

201

5%

1/20W

2

1

R2110

NOSTUFF

10K

MF

201

5%

1/20W

2

1

R2196

1/20W

5%

201

MF

10K

2

1

R2198

1/20W

5%

201

MF

10K

2

1

R2111

1/20W

5% MF

20K

201

2

1

R2190

100K

5%

1/20W

MF

201

2

1

R2150

10K

MF

201

5%

1/20W

2

1

R2155

1/20W

5%

201

MF

10K

21

R2140

201MF1/20W

5%

0

21

R2156

1/20W

5%

201

MF

390

21

R2170

MF

201

5%

1/20W

NOSTUFF

43

2

1

R2199

1/20W

5%

201

MF

10K

2

1

R2165

201

1K

MF

1/20W

5%

DRAM_CFG0:L

2

1

R2164

201

5%

1/20W

MF

1K

DRAM_CFG1:L

2

1

R2163

DRAM_CFG2:L

201

1K

5% 1/20W MF

2

1

R2162

201

1K

MF

1/20W

5%

DRAM_CFG3:L

3

8

4

6

5

U2150

74LVC2G08GT

SOT833

7

8

4

2

1

U2150

74LVC2G08GT

SOT833

16

19 23

35

6

39

2

1

C2152

0.1UF

10% 0201

X5R-CERM

16V

2

1

R2195

NOSTUFF

10K

201

MF

5%

1/20W

2 1

R2152

0

201

5% MF

1/20W

PCH MISC

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

MLB_RAM_CFG1

T29_PWR_EN

AUD_IPHS_SWITCH_EN_PCH

AUD_IPHS_SWITCH_EN_PCH_R

MLB_RAM_CFG2

MLB_RAM_CFG3

MLB_RAM_CFG1

PCH_GPIO46

WOL_EN

=PP3V3_SUS_GPIO

ENET_LOW_PWR

T29_SW_RESET_L

PCH_INIT3V3_L

MLB_RAM_CFG2

PCH_GPIO12

FW_PWR_EN

MLB_RAM_CFG3

MLB_RAM_CFG0

SMC_IG_THROTTLE_L FW_PME_L

PCH_INIT3V3_L

T29_PWR_EN_PCH

SPIROM_USE_MLB

=PP3V3_S0_PCH

JTAG_ISP_TCK

PCH_GPIO36_SATA2GP

PCH_GPIO35

ENET_LOW_PWR

PM_PCH_PWROK

AUD_IPHS_SWITCH_EN

ISOLATE_CPU_MEM_L

ODD_PWR_EN_L

LPCPLUS_GPIO

AUD_IPHS_SWITCH_EN_PCH

PCH_GPIO15

NC_GPIO8

SMC_RUNTIME_SCI_L

GMUX_INT

PCH_GPIO12

=PP3V3_S5_PCH

=PP3V3_T29_PCH_GPIO

SMC_SCI_L

PCH_GPIO24

SMC_SCI_L

T29_SW_RESET_L

JTAG_ISP_TDO JTAG_ISP_TDI

=PP3V3_SUS_GPIO

ODD_PWR_EN_L

MLB_RAM_CFG3 MLB_RAM_CFG2 MLB_RAM_CFG1

=PP3V3_S0_PCH_STRAPS

MLB_RAM_CFG0

FW_PME_L

=PP3V3_S3_PCH_GPIO

=PP3V3_S0_PCH_STRAPS

SMC_RUNTIME_SCI_L

PM_THRMTRIP_L

CPU_PWRGD

PCH_PROCPWRGD PM_THRMTRIP_L_R

PCH_RCIN_L

PCH_PECI CPU_PECI

=PP3V3_S0_PCH

PCH_A20GATE

JTAG_ISP_TCK

GMUX_INT

SPIROM_USE_MLB

PCH_GPIO24

ISOLATE_CPU_MEM_L

JTAG_ISP_TDO

FW_PWR_EN

=PP3V3_S0_PCH_STRAPS

SMC_IG_THROTTLE_L

MLB_RAM_CFG0

PCH_GPIO36_SATA2GP

=PP3V3_T29_PCH_GPIO

JTAG_ISP_TDI

21 OF 109

2.5.0

051-8871

19 OF 74

19

16

7

16 17 18 19

19 23

19 35

19

7

16 19 22

19 23

23

19 23

17 19 25

23

19

7

17

7

16 19

16 19 40

19

19 35

8

19

7

16 17 18 19

19

7

16 17 19

19

7

18

7

16 17 19

19 40 41

41

7

16 19 22

8

19 23

19

6

19 42 49

19

19 23 26

8

19

7

16 17 19

19 23

19

19 23

7

16 19

8

19

NC

VCCTX_LVDS_AG37

VSSALVDS_AC33

VCCALVDS_AG33

VCCALVDS_AF33

VSSADAC

VCCADAC

VCCDFTERM_AL13

VCCDFTERM_AK15

VCCSPI

VCCDFTERM_AJ15

VCCDFTERM_AJ13

VCCDMI_AM23

VCCCLKDMI

VCCVRM_AW21

VCCVRM_AU21

VCC3_3_U37

VCC3_3_T39

VCCTX_LVDS_AJ37

VCCTX_LVDS_AG39

VCCDMI_AU15 VCCDMI_AW16

VCCIO_AK21

VCCAFDIPLL_AP13 VCCAFDIPLL_AP15

VCCVRM_AW18

VCCVRM_AU19

VCCIO_AW34

VCC3_3_BK28

VCCIO_AU35

VCCIO_AU29

VCCIO_AU27

VCCIO_AU25

VCCIO_AU23

VCCIO_AR27 VCCIO_AR29

VCCIO_AR25

VCCIO_AR23

VCCIO_AR15 VCCIO_AT13

VCCIO_AM21

VCCAPLLEXP

VCCCORE_AM33 VCCCORE_AM35

VCCCORE_AK33

VCCCORE_AK31

VCCCORE_AK29

VCCCORE_AJ29 VCCCORE_AJ31

VCCCORE_AJ27

VCCCORE_AJ25

VCCCORE_AJ23

VCCCORE_AG27 VCCCORE_AJ21

VCCCORE_AG25

VCCCORE_AG23

VCCCORE_AG21

VCCCORE_AF21 VCCCORE_AF23

VCCCORE_AE23

VCCCORE_AE21

VCCCORE_AB21

VCCTX_LVDS_AF37

VSSALVDS_AE33

VCCCORE_AC23

VCCCORE_AC21

VCCCORE_AB23

(7 OF 10)

VCC CORE

VCCIO

FDI

NAND/SPI

DMI

HVCMOS

LVDS

CRT

NC

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_V37 VCC3_3_V39

VCCAPLLDMI2

VCCIO_AP27

DCPSUS_V13

DCPSUS_AR33 DCPSUS_AU33

VCCASW_AB27

VCCASW_AB31

VCCASW_AB29

VCCASW_AC27 VCCASW_AC29 VCCASW_AC31 VCCASW_AE27 VCCASW_AE29 VCCASW_AE31

VCCASW_V21

VCCASW_U21

VCCASW_V23 VCCASW_V25 VCCASW_Y21

VCCASW_Y25

VCCASW_Y23

VCCASW_Y27 VCCASW_Y29 VCCASW_Y31

DCPRTC_R15 DCPRTC_U15

VCCVRM_AC39

VCCADPLLA VCCADPLLB

VCCIO_AJ17

VCCDIFFCLKN_AC37 VCCDIFFCLKN_AE37 VCCDIFFCLKN_AE39

VCCSSC DCPSST

V_PROC_IO

VCCRTC

VCCSUSHDA

VCCASW_V19

VCCASW_R19

VCCASW_U19

VCCIO_AC15

VCCIO_AC13

VCCIO_AB15

VCCVRM_AF17

VCCVRM_AE19

VCCAPLLSATA

VCCIO_AF15

VCCIO_AG15

VCCIO_AG13

VCCIO_AA13

VCC3_3_AF6

VCC3_3_R40

VCC3_3_AC19

VCC3_3_AB19

VCCSUS3_3_U35

VCCSUS3_3_U33

VCCSUS3_3_R35

VCCSUS3_3_R33

V5REF

VCCSUS3_3_AM27

DCPSUS_AU31

V5REF_SUS

VCCIO_N18

VCCSUS3_3_N27

VCCSUS3_3_U29

VCCSUS3_3_U27

VCCSUS3_3_R29

VCCSUS3_3_R27

VCCIO_U25

VCCIO_U23

VCCIO_R25

VCCIO_R23

PCI/GPIO/LPC

SATA

CLOCK/MISC

USB

FUSE

HDA

RTC CPU

(8 OF 10)

NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VCCACLK pin left as NC per DG

AL24 left as NC per DG

1.44 A Max, 474mA Idle

55mA Max, 5mA Idle

VCCAPLLDMI2 pin left as NC per DG

(PCH DPLLA PWR)

(PCH DPLLB PWR)

69 mA

VCCAFDIPLL pin left as NC per DG

PCH VCCADPLLA Filter

68 mA

VCCAPLLSATA pin left as NC per DG

NC-ed per DG

PCH VCCADPLLB Filter

PCH output, for decoupling only

10 mA Max, 1mA Idle

2

1

C2232

0.1UF

16V X5R-CERM 0201

10%

PLACE_NEAR=U1800.N16:2.54mm

2

1

C2231

CERM

6.3V

10%

402

1UF

PLACE_NEAR=U1800.N16:2.54mm

2

1

C2222

10% 0201

X5R-CERM

16V

PLACE_NEAR=U1800.U17:2.54mm

0.1UF

2

1

C2210

10% 0201

X5R-CERM

16V

PLACE_NEAR=U1800.R15:2.54mm

0.1UF

21

R2260

1/16W

5%

402

MF-LF

0

21

R2265

1/16W

5%

402

MF-LF

0

2

1

C2233

0.1UF

16V X5R-CERM 0201

10%

PLACE_NEAR=U1800.N16:2.54mm

2

1

C2261

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.BF40:2.54MM

2

1

C2266

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.BF40:2.54MM

2

1

C2260

16V X5R-CERM 0201

10%

0.1UF

2

1

C2265

16V X5R-CERM 0201

10%

0.1UF

AE33

AC33

V50

AW21

AW18

AU21

AU19

AJ37

AG39

AG37

AF37

Y19

AW34

AU35

AU29

AU27

AU25

AU23

AT13

AR29

AR27

AR25

AR23

AR15

AM21

AK21

AW16

AU15

AM23

AL13

AK15

AJ15

AJ13

AM35

AM33

AK33

AK31

AK29

AJ31

AJ29

AJ27

AJ25

AJ23

AJ21

AG27

AG25

AG23

AG21

AF23

AF21

AE23

AE21

AC23

AC21

AB23

AB21

AP39

AP19

AG33

AF33

AP15

AP13

U51

U37

T39

BK28

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

AF17

AE19

AC39

V31

U35

U33

U29

U27

R35

R33

R29

R27

N27

AM27

AC35

N16

U25

U23

R25

R23

N18

AP27

AJ17

AG15

AG13

AF15

AC15

AC13

AB15

AA13

R12

AE39

AE37

AC37

Y31

Y29

Y27

Y25

Y23

Y21

V25

V23

V21

V19

U21

U19 R19

AE31

AE29

AE27

AC31

AC29

AC27

AB31

AB29

AB27

AM2

AW31

BD40

BF40

AC51

V39

V37

R40

AF6

AC19

AB19

AM17

M37

N36

R10

V13

AU33

AU31

AR33

U17

U15

R15

U1800

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

PCH POWER

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLB

PP1V05_S0_PCH_VCCADPLLA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLA

=PP3V3_S5_PCH_VCCDSW

TP_PPVOUT_PCH_DCPSUSBYP

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP1V05_S0_PCH_VCCIO_CLK

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

=PP1V8R1V5_S0_PCH_VCCVRM

PP1V05_S0_PCH_VCCADPLLB

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_PCH_VCCSSC

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP5V_S0_PCH_V5REF

=PP3V3_SUS_PCH_VCCSUS

=PP5V_SUS_PCH_V5REFSUS

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0_PCH_VCCIO_USB

=PP3V3_S0_PCH_VCC3_3_PCI

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCDMI_FDI

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_PLLPCIE TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V8R1V5_S0_PCH_VCCVRM

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V8_S0_PCH_VCC_DFTERM

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCADPLL

22 OF 109

2.5.0

051-8871

20 OF 74

20

7

22

7

20 22

7

20

7

20 22

7

16 22

7

22

7

22

7

20 22

7

16 20 22

7

20

7

16 20 22

7

22

7

22

7

22

7

22

7

22

7

22

7

22

7

20

7

22

7

22

7

22

7

22

7

22

7

20

22

7

18 22

22

7

20 22

7

16 22

7

16 17

7

VSS_G7

VSS_BA7

VSS_B46

VSS_B42

VSS_B38

VSS_B34

VSS_B30

VSS_B26

VSS_B22

VSS_B18

VSS_B14

VSS_B10

VSS_B6

VSS_AY10

VSS_AW45

VSS_AW43

VSS_AW41

VSS_AW39

VSS_AW36

VSS_AW29

VSS_AW27

VSS_AW25

VSS_AW23

VSS_AW13

VSS_AW11

VSS_AW9

VSS_AW7

VSS_AV50

VSS_AV48

VSS_AV4

VSS_AV2

VSS_AU37

VSS_AU17

VSS_AT45

VSS_AT43

VSS_AT41

VSS_AT39

VSS_AT11

VSS_AT9

VSS_AT7

VSS_AR37

VSS_AR35

VSS_AR31

VSS_AR21

VSS_AR19

VSS_AR17

VSS_AR8

VSS_AR6

VSS_AP50

VSS_AP48

VSS_AP45

VSS_AP43

VSS_AP41

VSS_AP37

VSS_AP35

VSS_AP33

VSS_AP31

VSS_AP29

VSS_AP25

VSS_AP23

VSS_AP21

VSS_AP17

VSS_AP11

VSS_AP9

VSS_AP7

VSS_AP4

VSS_AP2

VSS_AM37

VSS_AM31

VSS_AM29

VSS_AM25

VSS_AM19

VSS_AM15

VSS_AL45

VSS_AL43

VSS_AL41

VSS_AL39

VSS_AL11

VSS_AL9

VSS_AL7

VSS_AK50

VSS_AK48

VSS_AK37

VSS_AK35

VSS_AK27

VSS_AK25

VSS_AK23

VSS_AK19

VSS_AK17

VSS_AK4

VSS_AK2

VSS_AJ45

VSS_AJ43

VSS_AJ41

VSS_AJ39

VSS_AJ35

VSS_AJ33

VSS_AJ19

VSS_AJ11

VSS_AJ9

VSS_AJ7

VSS_AH2

VSS_AG45

VSS_AG43

VSS_AG41

VSS_AG35

VSS_AG31

VSS_AG29

VSS_AG19

VSS_AG17

VSS_AG11

VSS_AG9

VSS_AG7

VSS_AF50

VSS_AF48

VSS_AF35

VSS_AF31

VSS_AF29

VSS_AF27

VSS_AF25

VSS_AF19

VSS_AF8

VSS_AF4

VSS_AF2

VSS_AE45

VSS_AE43

VSS_AE41

VSS_AE35

VSS_AE25

VSS_AE17

VSS_AE15

VSS_AE13

VSS_AE11

VSS_AE9

VSS_AE7

VSS_AC45

VSS_AC43

VSS_AC41

VSS_AC25

VSS_AC17

VSS_AC11

VSS_AC9

VSS_AC7

VSS_AB50

VSS_AB48

VSS_AB37

VSS_AB35

VSS_AB33

VSS_AB25

VSS_AB17

VSS_AB4

VSS_AB2

VSS_AA45

VSS_AA43

VSS_AA39

VSS_AA11

VSS_AA9

VSS_AA7

VSS_BB48 VSS_BA31 VSS_BA34 VSS_BA36 VSS_BA39 VSS_BA41 VSS_BA43 VSS_BA45

VSS_BB4 VSS_BB2

VSS_BA11 VSS_BA13 VSS_BA16 VSS_BA18 VSS_BA21 VSS_BA23 VSS_BA25 VSS_BA27 VSS_BA29 VSS_BA9

VSS_AA41

VSS

(9 OF 10)

VSS_G9

VSS_F50

VSS_F48

VSS_F4

VSS_F2

VSS_D46

VSS_D42

VSS_D38

VSS_D34

VSS_D30

VSS_D26

VSS_D22

VSS_D18

VSS_BK46

VSS_BK42

VSS_BK38

VSS_BK34

VSS_BK32

VSS_BK30

VSS_BK26

VSS_D14

VSS_D10

VSS_D6

VSS_BK22

VSS_BK18

VSS_BK14

VSS_BK10

VSS_BH48

VSS_BH46

VSS_BH44

VSS_BH42

VSS_BH38

VSS_BH34

VSS_BH32

VSS_BH30

VSS_BH28

VSS_BH26

VSS_BH22

VSS_BH18

VSS_BH14

VSS_BH10

VSS_BF50

VSS_BF48

VSS_BH6

VSS_BF24

VSS_BF15

VSS_BE45

VSS_BE43

VSS_BE41

VSS_BE39

VSS_BE36

VSS_BE34

VSS_BF4

VSS_BF2

VSS_BE31

VSS_BE29

VSS_BE27

VSS_BE25

VSS_BE23

VSS_BE21

VSS_BE18

VSS_BE16

VSS_BE13

VSS_BE11

VSS_BE9

VSS_BD24

VSS_BD15

VSS_BC45

VSS_BC43

VSS_BC41

VSS_BC39

VSS_BC36

VSS_BE7

VSS_BC31

VSS_BC29

VSS_BC27

VSS_BC25

VSS_BC23

VSS_BC21

VSS_BC18

VSS_BC16

VSS_BC13

VSS_BC11

VSS_BB50

VSS_Y37

VSS_Y35

VSS_Y33

VSS_V45

VSS_V43

VSS_V41

VSS_V35

VSS_V33

VSS_V29

VSS_V27

VSS_V48 VSS_Y15 VSS_Y17

VSS_V7

VSS_V4

VSS_V2

VSS_U49

VSS_U31

VSS_T45

VSS_V9 VSS_V11 VSS_V15 VSS_V17

VSS_T43

VSS_T11

VSS_T9

VSS_T7

VSS_R37

VSS_R31

VSS_R21

VSS_R17

VSS_T13 VSS_T41

VSS_P50

VSS_N45

VSS_N43

VSS_N41

VSS_N39

VSS_N34

VSS_N31

VSS_N29

VSS_P2

VSS_P4 VSS_P48

VSS_N13

VSS_N11

VSS_N9

VSS_N7

VSS_L45

VSS_L43

VSS_L41

VSS_N21 VSS_N23 VSS_N25

VSS_L29

VSS_L27

VSS_L25

VSS_L23

VSS_L21

VSS_L18

VSS_L31 VSS_L34 VSS_L36 VSS_L39

VSS_L16

VSS_L9

VSS_L7

VSS_K50

VSS_K48

VSS_K4

VSS_K2

VSS_J45

VSS_L11 VSS_L13

VSS_J41

VSS_J29

VSS_J27

VSS_J25

VSS_J23

VSS_J21

VSS_J18

VSS_J34 VSS_J36 VSS_J39

VSS_J9

VSS_J7

VSS_G43

VSS_G41

VSS_G39

VSS_G36

VSS_G34

VSS_J11 VSS_J13 VSS_J16

VSS_G25

VSS_G23

VSS_G21

VSS_G18

VSS_G16

VSS_G13

VSS_G11

VSS_G27 VSS_G29 VSS_G31

VSS_J31

VSS_BC34

VSS

(10 OF 10)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

G7

BB48

BB4 BB2BA9

BA7

BA45

BA43

BA41

BA39

BA36

BA34

BA31

BA29

BA27

BA25

BA23

BA21

BA18

BA16

BA13

BA11

B6

B46

B42

B38

B34

B30

B26

B22

B18

B14

B10

AY10

AW9

AW7

AW45

AW43

AW41

AW39

AW36

AW29

AW27

AW25

AW23

AW13

AW11

AV50

AV48

AV4

AV2

AU37

AU17

AT9

AT7

AT45

AT43

AT41

AT39

AT11

AR8

AR6

AR37

AR35

AR31

AR21

AR19

AR17

AP9

AP7

AP50

AP48

AP45

AP43

AP41

AP4

AP37

AP35

AP33

AP31

AP29

AP25

AP23

AP21

AP2

AP17

AP11

AM37

AM31

AM29

AM25

AM19

AM15

AL9

AL7

AL45

AL43

AL41

AL39

AL11

AK50

AK48

AK4

AK37

AK35

AK27

AK25

AK23

AK2

AK19

AK17

AJ9

AJ7

AJ45

AJ43

AJ41

AJ39

AJ35

AJ33

AJ19

AJ11

AH2

AG9

AG7

AG45

AG43

AG41

AG35

AG31

AG29

AG19

AG17

AG11

AF8

AF50

AF48

AF4

AF35

AF31

AF29

AF27

AF25

AF2

AF19

AE9

AE7

AE45

AE43

AE41

AE35

AE25

AE17

AE15

AE13

AE11

AC9

AC7

AC45

AC43

AC41

AC25

AC17

AC11

AB50

AB48

AB4

AB37

AB35

AB33

AB25

AB2

AB17

AA9

AA7

AA45

AA43

AA41

AA39

AA11

U1800

FCBGA

COUGAR-POINT

MOBILE-SFF

OMIT_TABLE

Y37

Y35

Y33

Y17

Y15

V9

V7

V48

V45

V43

V41

V4

V35

V33

V29

V27

V2

V17

V15

V11

U49

U31

T9

T7

T45

T43

T41

T13

T11

R37

R31

R21

R17

P50

P48

P4

P2

N9

N7

N45

N43

N41

N39

N34

N31

N29

N25

N23

N21

N13

N11

L9

L7

L45

L43

L41

L39

L36

L34

L31

L29

L27

L25

L23

L21

L18

L16

L13

L11

K50

K48

K4

K2

J9

J7

J45

J41

J39

J36

J34

J31

J29

J27

J25

J23

J21

J18

J16

J13

J11

G9

G43

G41

G39

G36

G34

G31

G29

G27

G25

G23

G21

G18

G16

G13

G11

F50

F48

F4

F2

D6

D46

D42

D38

D34

D30

D26

D22

D18

D14

D10

BK46

BK42

BK38

BK34

BK32

BK30

BK26

BK22

BK18

BK14

BK10

BH6

BH48

BH46

BH44

BH42

BH38

BH34

BH32

BH30

BH28

BH26

BH22

BH18

BH14

BH10

BF50

BF48

BF4

BF24

BF2

BF15

BE9

BE7

BE45

BE43

BE41

BE39

BE36

BE34

BE31

BE29

BE27

BE25

BE23

BE21

BE18

BE16

BE13

BE11

BD24

BD15

BC45

BC43

BC41

BC39

BC36

BC34

BC31

BC29

BC27

BC25

BC23

BC21

BC18

BC16

BC13

BC11

BB50

U1800

FCBGA

COUGAR-POINT

MOBILE-SFF

OMIT_TABLE

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

PCH GROUNDS

23 OF 109

2.5.0

051-8871

21 OF 74

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

PAGE TITLE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)

(PCH Reference for 5V Tolerance on USB)

(PCH HD Audio 3.3V/1.5V PWR)

(PCH USB 1.05V PWR)

PCH VCCIO BYPASS

PCH VCCCORE BYPASS

(PCH SUSPEND USB 3.3V PWR)

(PCH 1.05V CORE PWR)

<1 MA

1 mA

PCH VCCSUS3_3 BYPASS

<1 MA S0-S5

PCH V5REF_SUS Filter & Follower

NEED PWR CONSTRAINT

PCH VCCIO BYPASS

1 mA S0-S5

(PCH Reference for 5V Tolerance on PCI)

PCH V5REF Filter & Follower

PCH VCCSUSHDA BYPASS

NEED PWR CONSTRAINT

2

1

C2439

PLACE_NEAR=U1800.N36:2.54mm

X5R 402

10V

10%

1UF

2 1

R2405

100

MF

201

5%

1/20W

2

1

C2438

0.1UF

CERM

402

20% 10V

PLACE_NEAR=U1800.M37:2.54mm

6

1

D2400

BAT54DW-X-G

SOT-363

2 1

R2404

10

MF

5%

1/20W

201

3

4

D2400

BAT54DW-X-G

SOT-363

2

1

C2423

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.AF6:2.54mm

2

1

C2440

PLACE_NEAR=U1800.AJ15:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2441

PLACE_NEAR=U1800.V31:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2419

PLACE_NEAR=U1800.AM23:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2421

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.BK28:2.54mm

2

1

C2413

PLACE_NEAR=U1800.U27:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2417

PLACE_NEAR=U1800.AM17:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2416

PLACE_NEAR=U1800.AM17:2.54mm

4.7UF

X5R 402

20%

6.3V

2

1

C2484

PLACE_NEAR=U1800.R27:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2485

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.R40:2.54mm

2

1

C2463

PLACE_NEAR=U1800.AU25:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2475

PLACE_NEAR=U1800.AC35:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2434

PLACE_NEAR=U1800.AE37:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2469

PLACE_NEAR=U1800.AJ17:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2414

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

2

1

C2401

PLACE_NEAR=U1800.AU25:2.54mm

10UF

CERM-X5R

0402

20%

6.3V

2

1

C2452

PLACE_NEAR=U1800.AC13:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2499

PLACE_NEAR=U1800.R12:2.54mm

0.1UF

X5R-CERM

0201

10% 16V

2

1

C2442

PLACE_NEAR=U1800.Y19:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2486

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.AC19:2.54mm

2

1

C2444

PLACE_NEAR=U1800.AG13:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2446

PLACE_NEAR=U1800.U23:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2424

0.1UF

X5R-CERM 0201

10% 16V

PLACE_NEAR=U1800.T39:2.54mm

2

1

C2460

PLACE_NEAR=U1800.AK33:2.54mm

10UF

CERM-X5R

0402

20%

6.3V

2

1

C2482

PLACE_NEAR=U1800.AF23:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2481

PLACE_NEAR=U1800.AC21:2.54mm

1UF

X5R 0201

20%

6.3V 2

1

C2483

PLACE_NEAR=U1800.AJ25:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2407

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

2

1

C2429

PLACE_NEAR=U1800.AU25:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2420

X5R-CERM1

0603

22UF

6.3V

PLACE_NEAR=U1800.AC27:2.54mm

20%

2

1

C2496

1UF

PLACE_NEAR=U1800.AC27:2.54mm

X5R 0201

20%

6.3V

2

1

C2456

PLACE_NEAR=U1800.AC27:2.54mm

1UF

X5R 0201

20%

6.3V

2

1

C2426

PLACE_NEAR=U1800.AC27:2.54mm

1UF

X5R 0201

20%

6.3V

21

R2415

1

MF

201

5%

1/20W

2

1

C2411

PLACE_NEAR=U1800.AP39:2.54mm

10UF

CERM-X5R 0402-1

20%

6.3V

2

1

C2430

PLACE_NEAR=U1800.AM17:2.54mm

0.1UF

X5R-CERM 0201

10% 16V

2

1

C2428

22UF

20%

6.3V 0603

X5R-CERM1

PLACE_NEAR=U1800.AC27:2.54mm

21

R2450

0

MF

201

5%

1/20W

2

1

C2455

PLACE_NEAR=U1800.U51:2.54mm

0.01UF

X5R-CERM

0201

10% 16V

2

1

C2451

X5R-CERM

PLACE_NEAR=U1800.U51:2.54mm

0.1UF

0201

10% 16V

21

R2451

1/16W

5%

MF-LF

1

402

2

1

C2454

PLACE_NEAR=U1800.V37:2.54mm

6.3V

20% 0201

X5R

1UF

21

L2451

0603

10UH-0.12A-0.36OHM

2

1

C2476

PLACE_NEAR=U1800.U33:2.54mm

1UF

X5R 0201

20%

6.3V

21

L2406

10UH-0.12A-0.36OHM

0603

2

1

C2450

PLACE_NEAR=U1800.U51:2.54mm

10UF

CERM-X5R

0402

20%

6.3V

2

1

C2453

PLACE_NEAR=U1800.V37:2.54mm

10UF

CERM-X5R

0402-1

20%

6.3V

PCH DECOUPLING

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_VCCASW

PP3V3_S0_PCH_VCCA_DAC_F

VOLTAGE=3.3V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCCLKDMI_R

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S5_PCH_VCCDSW

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP1V05_S0_PCH_VCCIO_USB

=PP5V_SUS_PCH

=PP3V3_SUS_PCH

=PP5V_S0_PCH_V5REF

=PP3V3_S0_PCH =PP5V_S0_PCH

PP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_S5_PCH_VCC_SPI

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH

=PP3V3_S0_PCH_VCC3_3_SATA

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCC_CORE

=PP3V3_S0_PCH_VCC3_3_GPIO

PP5V_SUS_PCH_V5REFSUS

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

PP3V3_S0_PCH_VCC3_3_CLK_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCC3_3_CLK_R

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_PCH_VCCIO

24 OF 109

2.5.0

051-8871

22 OF 74

5

2

20

7

20

7

20

7

20

7

16 20

7

18 20

7

20

7

16 20

7

20

7

20

7

20

7

16 19

7

20

7

20

7

20

7

16 20

7

20

7

16

7

20

7

20

7

20

7

20

7

20

7

20

IN

IN IN

IN

IN IN IN IN

IN IN IN

OUT

IN

OUT OUT

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN

IN IN

NC

BI

IN

IN IN

BI

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT NOTE:

TMS

OBSDATA_C1

DESIGN NOTE:

TRSTn

TDI

OBSDATA_C3

OBSFN_D0

PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST*

TERM NEAR CPU

TERM NEAR PCH

TDO

ODT AVAILABLE ON JTAG

HOOK1

OBSFN_B0

OBSFN_D1

OBSDATA_D2

OBSDATA_B0

SCL

OBSDATA_D3

XDP_PRESENT#

HOOK2

SDA

OBSDATA_B1

OBSFN_C0

TCK1

PLACEMENT NOTE:

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_B3

PWRGD/HOOK0

HOOK3

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

OBSFN_B1

SNB XDP CONN

PLACE TDO TERM NEAR

PLACE TCK/TDI/TMS/TRST*

OBSFN_A0

OBSDATA_D1

OBSDATA_D0

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

OBSDATA_A2

OBSDATA_A3

OBSFN_A1 OBSFN_C1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

OBSDATA_A0

OBSDATA_A1

TCK0

PCH XDP CONN

PLACE TDO TERM NEAR

PLACEMENT NOTE:

VCC_OBS_AB

OBSDATA_B2

OBSDATA_C0

OBSDATA_C2

Even pins should be facing edge of the board

1K series R on PCH Support P. 28

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

SCL

SDA

TCK1 TCK0

XDP_PRESENT#

TMS

TDI

TRSTn

TDO

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1

OBSDATA_D0

OBSFN_D1

OBSFN_D0

OBSDATA_C3

OBSDATA_C2

OBSDATA_C1

OBSDATA_C0

OBSFN_C1

OBSFN_C0

Use with 920-0782 Adapter Flex to support chipset debug

NOTE: This is not the standard XDP pinout

PCH MICRO2-XDP CONNECTOR

Use with 920-0782 Adapter Flex to support chipset debug

NOTE: This is not the standard XDP pinout

PROCESSOR MICRO2-XDP CONNECTOR

998-2516

9

10 25

10 66

9

66

10 66

9

66

9

66

9

66

21

R2501

201

1/20W

MF

PLACE_NEAR=U1000.B50:2.54MM

XDP

5%

1K

9

23 66

9

66

19

16

21

R2579

XDP

PLACE_NEAR=U1800.AA3:2.54MM

1/20W

201

MF

0

5%

8

19

9

66

25

16 23

9

66

21

R2580

PLACE_NEAR=U1800.A17:2.54MM

5%

MF

201

XDP

1/20W

0

18

16 23

9

66

18 24

2

1

R2556

201

1/20W

MF

51

XDP

5%

PLACE_NEAR=U1800.M17:2.54MM

23 43

10 23 25 66

2

1

C2580

0.1UF

16V

10%

XDP

X5R 402

2

1

C2581

10%

0.1UF

16V X5R

XDP

402

19

21

R2502

201

XDP

1/20W

MF

0

5%

PLACE_NEAR=U4900.D10:2.54MM

17 23 40

21

R2585

201

1/20W

XDP

MF

0

5%

PLACE_NEAR=U4900.D10:2.54MM

17 23 40

21

R2504

910

XDP

5%

1/16W

MF-LF

402

17 25

18

21

R2584

PLACE_NEAR=J2550.39:2.54MM

1K

XDP

5% MF-LF

1/16W

402

25 40 51 61

21

R2581

201

1/20W

MF

XDP

0

5%

PLACE_NEAR=U1800.B16:2.54MM

18

10 23 66

10 23 25 66

21

R2582

PLACE_NEAR=U1800.H4:2.54MM

201

5%

MF

1/20W

0

XDP

18

21

R2578

PLACE_NEAR=U1800.G1:2.54MM

5%

0

XDP

MF

1/20W

201

19 26

21

R2586

PLACE_NEAR=U1800.A13:2.54MM

XDP

1/20W

201

MF

0

5%

21

R2587

MF

201

1/20W

5%

0

XDP

PLACE_NEAR=U1800.D16:2.54MM

18

9

10 23 66

16 66

21

R2515

201

1/20W

MF

0

PLACE_NEAR=R1841.1:2.54MM

XDP

5%

21

R2516

201

XDP

1/20W

MF

PLACE_NEAR=R1840.1:2.54MM

5%

0

21

R2505

1/20W

201

MF

XDP

1K

5%

PLACE_NEAR=R1125.1:2.54MM

16 63

2

1

R2550

PLACE_NEAR=J2550.52:2.54MM.

MF-LF

51

1/16W

5%

402

XDP

10 23 66

2

1

R2551

51

PLACE_NEAR=U1800.U12:2.54MM

201

1/20W

MF

XDP

5%

2

1

R2552

201

1/20W

MF

PLACE_NEAR=U1800.M15:2.54MM

5%

XDP

51

21

R2560

XDP_CPU:BPM

5%

0

MF-LF

1/16W

402

21

R2561

5%

1/16W

402

XDP_CPU:BPM

MF-LF

0

21

R2562

XDP_CPU:BPM

5%

MF-LF

1/16W

0

402

21

R2563

XDP_CPU:BPM

0

5%

MF-LF

1/16W

402

21

R2564

5%

XDP_CPU:CFG

0

MF-LF

1/16W

402

10 23 66

21

R2566

1/16W

402

5%

0

XDP_CPU:CFG

MF-LF

21

R2567

MF-LF

XDP_CPU:CFG

0

5%

1/16W

402

21

R2565

XDP_CPU:CFG

0

5%

MF-LF

1/16W

402

2

1

R2540

402

NOSTUFF

1/16W MF-LF

1K

5%

2

1

C2500

16V

10%

X5R

XDP

0.1UF

402

9

8 7

64 63

62

61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J2500

XDP_CONN CRITICAL

DF40RC-60DP-0.4V

M-ST-SM

9

8 7

64 63

62

61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J2550

DF40RC-60DP-0.4V

M-ST-SM

XDP_CONN CRITICAL

19

9

23 66

2

1

C2501

10%

XDP

0.1UF

X5R

16V

402

9

66

10 66

9

66

9

66

9

66

9

66

23 43

10 23 66

21

R2500

1/20W

PLACE_NEAR=U1000.B46:1MM

XDP

201

MF

1K

5%

9

66

10 19 66

9

66

2

1

R2510

PLACE_NEAR=J2500.52:2.54MM

51

5%

XDP

MF-LF

1/16W

402

2

1

R2511

5%

51

XDP

PLACE_NEAR=U1000.M60

MF-LF

1/16W

402

2

1

R2512

51

5%

XDP

PLACE_NEAR=U1000.L55:2.54MM

MF-LF

1/16W

402

2

1

R2513

201

1/20W

MF

51

XDP

5%

PLACE_NEAR=U1000.J58:2.54MM

2

1

R2514

201

MF

1/20W

5%

PLACE_NEAR=U1000.L56:2.54MM

XDP

51

10 66

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

CPU & PCH XDP

PCH_GPIO59_OC0_L

USB_HUB_SOFT_RESET_L

XDP_PCH_ENET_PWR_EN

ALL_SYS_PWRGD

SDCONN_STATE_CHANGE

SDCONN_STATE_RST_L

XDP_PCH_SDCONN_DET_L

XDP_BPM_L<6>

CPU_PWRGD

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

=PPVCCIO_S0_XDP

XDP_BPM_L<4>

PM_PWRBTN_L

=PP1V05_SUS_PCH_JTAG

PM_PCH_SYS_PWROK

XDP_CPU_TRST_L

XDP_CPU_TDO

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_CPU_TMS

XDP_PCH_TDO

CPU_CFG<0>

=PP3V3_S0_XDP

=SMBUS_XDP_SCL

XDP_CPU_PWRBTN_L

XDP_CPU_TDI XDP_CPU_TMS

XDP_BPM_L<0>

CPU_CFG<1>

CPU_CFG<7>

XDP_CPU_TDO XDP_CPU_TRST_L

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

PCH_GPIO43_OC4_L

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_B<0>

XDP_PCH_TMS

XDP_DBRESET_L

TP_XDP_PCH_TRST_L XDP_PCH_TDI

XDP_PCH_TDO

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_D<1>

TP_XDP_PCH_HOOK5

CPU_CFG<5>

XDP_CPU_PWRGD

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_BPM_L<3>

CPU_CFG<10> CPU_CFG<11>

XDP_BPM_L<2>

XDP_VR_READY

PM_PWRBTN_L

CPU_CFG<14>

XDP_BPM_L<1>

ENET_PWR_EN

XDP_PCH_SDCONN_STATE_RST_L

XDP_PCH_PWRBTN_L

AUD_IPHS_SWITCH_EN_PCH

CPU_CFG<6>

XDP_CPU_TDI

XDP_CPU_TCK

XDP_PCH_TDI XDP_PCH_TMS XDP_PCH_TCK

CPU_CFG<12>

=SMBUS_XDP_SDA

CPU_RESET_L

CPU_CFG<16>

CPU_CFG<0>

XDP_DBRESET_L

XDP_CPURST_L

CPU_CFG<4>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<3>

XDP_CPU_TCK

XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>

XDP_PCH_USB_HUB_SOFT_RST_L

XDP_PCH_GPIO59_OC0_L

XDP_PCH_S5_PWRGD

TP_XDPPCH_HOOK2

XDP_PCH_TCK

XDPPCH_PLTRST_L

XDP_PCH_AUD_IPHS_SWITCH_EN

JTAG_ISP_TCK

PCH_GPIO36_SATA2GP

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

=PPVCCIO_S0_XDP

CPU_CFG<17>

CPU_CFG<2>

XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N

ENET_LOW_PWR

TP_XDP_PCH_OBSFN_D<0>

SMC_IG_THROTTLE_L

PCH_GPIO15

=PP3V3_S5_XDP

SATARDRVR_EN

DP_AUXCH_ISOL

PCH_GPIO35

XDP_PCH_ISOLATE_CPU_MEM_L

ISOLATE_CPU_MEM_L

XDP_CPU_CFG<0>

CPU_CFG<15>

CPU_CFG<13>

25 OF 109

2.5.0

051-8871

23 OF 74

7

23

7

10 23 66

16 23

7

6

10 23 66

16 23

66

6

7

23

66

6

7