Apple A1369 Schematic

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DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

07/23/2010

SCHEM,MLB,K16

Schematic / PCB #’s

1 OF 74

051-8467

3.3.0

1 OF 110

2010-07-23

(MASTER)

38

(MASTER)

48

SecureDigital Card Reader

(MASTER)

37

(MASTER)

47

Left I/O (LIO) Connector

K99_MLB

36

03/01/2010

46

External USB Connectors

K99_MLB

35

04/08/2010

45

SATA CONNECTOR

K99_MLB

34

04/08/2010

40

X21 WIRELESS CONNECTOR

K99_MLB

33

04/08/2010

39

FSB/DDR3 Vref Margining

K99_MLB

32

04/08/2010

37

Memory Active Termination

K99_MLB

31

04/08/2010

36

DDR BYPASSING 2

K99_MLB

30

04/08/2010

35

DDR BYPASSING 1

K99_MLB

29

04/08/2010

34

DDR3 DRAM Channel B (32-63)

K99_MLB

28

04/08/2010

33

DDR3 DRAM Channel B (0-31)

K99_MLB

27

04/08/2010

32

DDR3 DRAM Channel A (32-63)

K99_MLB

26

04/08/2010

31

DDR3 DRAM Channel A (0-31)

(K99_MLB)

25

(02/11/2010)

28

SB Misc

K99_MLB

24

04/08/2010

26

MCP Graphics Support

K99_MLB

23

04/08/2010

25

MCP Standard Decoupling

K99_MLB

22

04/08/2010

24

MCP89 GFX Core Rail Gating

K99_MLB

21

04/08/2010

23

MCP89 Memory Rail Gating

K99_MLB

20

04/08/2010

20

MCP Power & Ground

K99_MLB

19

04/08/2010

19

MCP HDA, LPC & MISC

K99_MLB

18

04/08/2010

18

MCP SATA, USB & Ethernet

K99_MLB

17

04/08/2010

17

MCP Graphics

K99_MLB

16

04/08/2010

16

MCP PCIe Interfaces

K99_MLB

15

04/08/2010

15

MCP Memory Interface

K99_MLB

14

04/08/2010

14

MCP CPU Interface

K99_MLB

13

03/01/2010

13

eXtended Debug Port (Micro-XDP)

(K99_MLB)

12

(02/11/2010)

12

CPU Decoupling & VID

K99_MLB

11

04/08/2010

11

CPU Power & Ground

K99_MLB

10

04/08/2010

10

CPU FSB

(MASTER)

9

(MASTER)

9

Signal Aliases

(K99_MLB)

8

(02/11/2010)

8

Power Aliases

(K99_MLB)

7

(02/16/2010)

7

Functional Test / No Test

N/A

6

N/A

6

Revision History

N/A

5

N/A

5

K16 BOM Variants

K6_MLB

4

12/11/2009

4

BOM Configuration

MARTIN.YEH

3

2/25/2010

3

Power Block Diagram

ALAN.DAI

2

02/26/2010

2

System Block Diagram

74

K16_MLB

06/01/2010

Acoustic Cap BOM Config Tables

110

73

K99_MLB

04/08/2010

K99 RULE DEFINITIONS

109

72

T27_MLB

09/08/2009

K16/K99 Specific Constraints

108

71

K99_MLB

04/08/2010

SMC Constraints

106

70

K99_MLB

04/08/2010

Ethernet Constraints

104

69

K99_MLB

04/08/2010

MCP Constraints 2

103

68

K99_MLB

04/08/2010

MCP Constraints 1

102

67

K99_MLB

04/08/2010

Memory Constraints

101

66

K99_MLB

04/08/2010

CPU/FSB Constraints

100

65

K99_MLB

05/18/2010

Additional CPU/GPU Decoupling

99

64

K99_MLB

04/08/2010

LCD Backlight Support

98

63

(K99_MLB)

(03/01/2010)

LCD Backlight Driver

97

62

K16_MLB

06/01/2010

DisplayPort Connector

94

61

K99_MLB

04/08/2010

External DisplayPort Support

93

60

K99_MLB

07/23/2010

Internal DisplayPort Connector

90

59

K99_MLB

04/08/2010

Power FETs

79

58

K99_MLB

04/08/2010

Power Sequencing

78

57

K99_MLB

04/08/2010

Misc Power Supplies

77

56

(K99_MLB)

(03/01/2010)

CPUVTT (1.05V) Power Supply

76

55

(K99_MLB)

(02/11/2010)

MCP VCore Regulator

75

54

(K99_MLB)

(02/16/2010)

IMVP6 CPU VCore Regulator

74

53

K16_MLB

06/01/2010

1.5V/1.35V LVDDR3 Supply

73

52

K99_MLB

04/08/2010

5V / 3.3V Power Supply

72

51

(K99_MLB)

(02/16/2010)

PBus Supply & Battery Charger

70

50

(MASTER)

(MASTER)

DC-In & Battery Connectors

69

49

K99_MLB

04/08/2010

AUDI0: SPEAKER AMP

66

48

K99_MLB

04/08/2010

SPI ROM

61

47

K99_MLB

04/08/2010

WELLSPRING 1

57

46

K99_MLB

04/08/2010

Fan

56

45

K99_MLB

04/08/2010

Thermal Sensors

55

44

K99_MLB

04/08/2010

Current Sensing

54

43

K99_MLB

04/08/2010

Voltage & Current Sensing

53

42

K99_MLB

07/23/2010

K16/K99 SMus Connections

52

41

K99_MLB

04/08/2010

LPC+SPI Debug Connector

51

40

(K99_MLB)

(03/01/2010)

SMC Support

50

1051-8467 CRITICALSCH

SCHEM,MLB,K16

Sync

(.csa)

Date

Page

ContentsContents

(.csa)

Page

Date

Sync

39

K16_MLB

06/01/2010

SMC

49

820-2838 1

PCBF,MLB,K16

PCB CRITICAL

N/A

1

N/A

1

Table of Contents

SCHEM,MLB,K16

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

64-BIT
800MHZ

FSB

BASE FREQ.=200MHZ

64-BIT

64-BIT

DDR3-1066/1333MHZ

DDR3-1066/1333MHZ

BOOTROM

J1300

1.2 GHZ

U6100

SPI

SPKUSB

TMDS OUT

PANEL

LVDS OUT

(UP TO 8 DEVICES)

USB_7

PG 14

LPC+SPI

CONN

TRACKPAD

(IPD)

SMC

AUDIO CODEC

PG 17

UP TO 2 PORTS

USB_4

SATA_A0

USB_5

USB_0

USB_6

USB_2

PG 17

PG 18

J5700

SPEAKER

AMPS

LIO FLEX CONN

U6201

J4700

EXT

PG 18

HDA

PE1[0,1]:X1,X1 GEN1,UP TO 2 LANES

AIRPORT+

Y2810

BLUETOOTH

25MHZ

X4 DP LINK

SATA 2.0 3GBIT/S

PG 24

24.5X24.5MM

0.6MM PITCH
FCPBGA

1244P

FLAT

PG 60

DP0[3:0]

S3/S4

J6955

U6610

CTRL CONN

CHARGER,BATT CONN

SMS

PG 47

VOLTAGE/CURRENT SENSOR

PG 50,51

XDP CONN

SATA

U5515.U5535

J6950,U7000

CPU/MCP TEMP SENSOR

PENRYN

PG 16

PCI-E

J4501

SSD

INTERNAL

CONN

PG 6

SPEAKER

U6620

AMPS

LEFT

SPEAKER

J6700

HEADPHONE/

LINE IN

JACK

HEADPHONE

FILTER

PG 8

LINE IN

FILTER

PG 11

EXT USB

PG 6

LEFT

J4702

CAMERA+

CONN

ALS

J4610

I2C
MIKEY CAMERA

HDA

PG 36

USB

I2C

PG 49

PG 50

SPEAKER

J4600

U4800

PG 46

SD CARD

PG 50

HALL EFFECT

J4800

FAN CONN

U5920

SMB_A

SYS_LED

PM_SLP

LID

SMSFAN0ADC

SMB_B/0SMB_BSA

SERIAL
PORT

PG 40

MEMORY

U3300,3400

128MX8

PG 25,26

1GB

U3100,U3200

MEMORY

128MX8

USB 2.0

RGMII

PG 17

PE0[4,5]:X2,X1 GEN2,UP TO 2 LANES

SMB

DVI OUT

HDMI OUT

A

PG 9

PG 13

J5100

PG 37

1GB

SUPPORT GEN3,6.0GB/S

CTRL

LIO

POWER SUPPLY

RIGHT

CONN

CONN

CONN

SIL+

J6903

PG 35

PG 37

SD CARD

DP1[1:0]

PG 45

J5600

PG 42,43

PG 44

PG 52-57

CONN

PG 38

U4900

U1000

EXT USB

X2 DP LINK

DISPLAY

PG 62

J9400

CONN

DISPLAY

CONN

EXTERNAL

J9000

RGB OUT

SATA

PWR

PG 15

CONN

PG 34

RTC XTAL

PG 18

MCP

PG 24

Y2815

MISC

PG 18

PCIE GEN1

PE1_0

J4001

CONN

PG 33

LIO BOARD

PG 5

PG 18

PG 10

CONN

J6702

PG 9

PG 10

LPC

PG 18

LAN

GPIOs

FSB INTERFACE

MAIN

MEMORY

PG 18

B

PG 48

PG 27,28

SPI

32.768KHZ

NVIDIA
MCP89U

PG 12

INTEL CPU

System Block Diagram

SYNC_MASTER=ALAN.DAI SYNC_DATE=02/26/2010

2 OF 110

3.3.0

051-8467

2 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IN

BATTERY CHARGER

R7050

Q7080

PP18V5_DCIN_CONN

PBUS SUPPLY/

SLP_S3_L(P93)

VIN

PP4V5_AUDIO_ANALOG

V

SMC_BATT_ISENSE

01

PPVBAT_G3H_CHGR_R

P3V3S3_EN

CHGR_BGATE

EN2

Q7055

PPVBAT_G3H_CONN

PM_WLAN_EN_L

PM_SLP_S3_L

P1V5S0_EN

MCPCORES0_EN

RC

DELAY

16-4

Q7890,Q7891

DDRVTT_EN

S5

Q7930

MCPPLLDO_PGOOD

PP1V05_S0_MCP_PLL_REG

TPS74701

1.05V

U7740

ISL8009B

U7710

1.5V

PP1V5_S0_REG

ISL8009B

U7750

P3V3S0_EN

P5V3V3_PGOOD

PP0V9_S5_REG

VOUT1

(1A MAX CURRENT)

(25A MAX CURRENT)

PPMCPCORE_S0_R

(13A MAX CURRENT)

PP0V75_S0_REG

14

TPS51116

U7300

VOUT2

VOUT1

TPS51980

(5.3A MAX

(5.6A MAX CURRENT)

CURRENT)

Q7910

PP3V3_S5_REG

3.3V

LP8545

ENA

PPVOUT_SW_LCDBKLT

VOUT

U9701

02

(S5)

P16

U7400

02

VR_PWRGOOD_DELAY

SMC_CPU_ISENSE

PGOOD

TPS51982

VIN

CPU VCORE

(28A MAX CURRENT)

PPVCORE_S0_CPU

(11.5A MAX CURRENT)

(60MA MAX CURRENT)

PP3V42_G3H_REG

U6990

02

3.425V G3HOT
LT3470

VOUT

PBUS_G3H_VSENSE

V

VIN

CPUVTT

(1.05V)

ISL95870

U7600

06-1

PPVBAT_G3H_CHGR_REG

IMVP_VR_ON_R

PPBUS_G3H

PM_SLP_S3_L

U7840

P5VS3_EN_L

ISL6259

ENABLES

MAX8840

MCP89

DELAY

RC

DELAY

RC

CPUVTTS0_EN

16-5

16-6

AP_PWR_EN

Q7890

(9 TO 12.6V)

3S2P

PM_SLP_S3_L

U1400

PM_SLP_S4_L

MCP89

11

15

DELAY

RC

11-2

RC
DELAY

11-3

11-1

J6950

PBUSVSENSE_EN

DELAY

RC

P3V3S0_EN

(S0)

(S0)

16-2

16-1

16-1

04-1

=DDRREG_EN

=DDTVTT_EN

S3

MCPCORES0_EN

0.75V

02

VIN

EN

VIN

02

1.5V

P5VS3_EN_L

BKLT_EN

U4900

SMC

P60

A

ADAPTER

AC

6A FUSE

01

A

VOUT

Q7085

P3V3S5_EN_L

25

02

U7500

VOUT

20

PP1V5_S3_REG

VIN

VOUT

R7525

05

VIN

EN1

(RT)

5V

VREG3

VR_ON

28

PP3V3_S0_FET

PP3V3_S0
PP1V5_S0
PP1V05_S0

V2

V1

RST*

P1V5S0_PGOOD

P5V3V3_PGOOD

MCPCORES0_PGOOD

SLP_S5_L
SLP_S4_L
SLP_S3_L

09

ALL_SYS_PWRGD

05

SMC_ONOFF_L

RSMRST_PWRGD

SLP_S4_L(P94)

SLP_S5_L(P95)

U4900

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

99ms DLY

26

EN

U6200

VOUT

4.5V AUDIO

24

07

17

Q7940

P5VS0_EN

PP5V_S0_FET

SMC

29

U1000

CPU

U1400

PWRGD

CPUVTTS0_EN

02

EN_PSV

ENABLE

PP1V05_S0

03

RN5VD30A-F

SMC PWRGD

U5010

04

RST*

P17(BTN_OUT)

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

PLT_RST*

CPU_RESET#

PWRBTN*

PLTRST*

RESET*

CPUPWRGD(GPIO49)

PWRGOOD

RSMRST*

IMVP_VR_ON_R

PM_PWRBTN_L
SMC_RESET_L

25

PM_RSMRST_L

32

10

FSB_CPURST_L

30

CPU_PWRGD

LPC_RESET_L

31

13

PP5V_S3_REG

PGOOD1,2

ISL88042

V3

16

21

Q5315

EN

P5VS0_EN

DCIN(16.5V)

DDRREG_EN

SMC_DCIN_ISENSE

(S0)

F6905

R7020

VIN

(S5)

U7000

8A FUSE

F7040

VOUT

PBUS_VSENSE

PGOOD

SMC_CPU_VSENSE

CPUVTTS0_PGOOD

VOUT

PPBUS_G3H

VOUT2

VIN

04

U7201

SMC_ADAPTER_EN

ISL9563B

S0PGOOD_RST_L

P3V3S3_EN

PPMCPCORE_S0_REG

MCP_CORE

MCPMEM_GATE

Q2300

MCP_PS_PWRGD

U2850

CPUVTTS0_PGOOD

18

P3V3_S3_WLAN

PM_WLAN_EN_L

Q4050

PP3V3_S3_FET

PP1V5R1V35_SW_MCP

SMC_PM_G2_EN

CHGR_EN

U7870

K16 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H_OR_PBUS

Power Block Diagram

SYNC_MASTER=MARTIN.YEH

SYNC_DATE=2/25/2010

3 OF 110

3.3.0

051-8467

3 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

K16 BOM Variants on following page

ELPIDA

1

DRAM CFG CHART

HYNIX

SAMSUNG

Alternate Parts

Programmable Parts

4GB

2GB

SIZE

CFG 2

1

0

B

A

DIE REV

CFG 3

1

0

1

1

MICRON

CFG 0 CFG 1

VENDOR

0

1

0

0

0

Module Parts

BOM Groups

CRITICAL

ISL6259_SCREENED:YES

353S2929

1

U7000

ISL6259_SCREENED:NO

IC,ISL6259,BATCHARGER,4X4MM,QFN28

CRITICAL353S2392

1

U7000

DRAM_TYPE:MICRON_4GB

CRITICAL333S0557

4

MICRON,LVDDR3,2GBIT,9X11.5

DRAM_TYPE:MICRON_4GB

U3300,U3310,U3320,U3330

CRITICAL333S0557

4

MICRON,LVDDR3,2GBIT,9X11.5

U3400,U3410,U3420,U3430

333S0556

4

CRITICAL

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

U3200,U3210,U3220,U3230

DRAM_TYPE:MICRON_4GB

333S0557

4

MICRON,LVDDR3,2GBIT,9X11.5

U3100,U3110,U3120,U3130

CRITICAL

4

MICRON,LVDDR3,2GBIT,9X11.5

U3300,U3310,U3320,U3330

333S0556

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

CRITICAL

4

CRITICAL

4

333S0556

U3100,U3110,U3120,U3130

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

333S0556 CRITICAL

4

333S0555

4

HYNIX,LVDDR3,2GBIT,9X11.1

CRITICAL

U3400,U3410,U3420,U3430

333S0555

4

HYNIX,LVDDR3,2GBIT,9X11.1

U3200,U3210,U3220,U3230

CRITICAL

333S0555

4

U3300,U3310,U3320,U3330

HYNIX,LVDDR3,2GBIT,9X11.1

CRITICAL

333S0555 CRITICAL

HYNIX,LVDDR3,2GBIT,9X11.1

4

U3100,U3110,U3120,U3130

333S0566

U3100,U3110,U3120,U31304CRITICAL
U3200,U3210,U3220,U32304CRITICAL
U3300,U3310,U3320,U3330

CRITICAL

4

4

CRITICAL

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DRAM_TYPE:ELPIDA_2GB

U3400,U3410,U3420,U3430

4

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DRAM_TYPE:ELPIDA_2GB

4

U3200,U3210,U3220,U3230

DRAM_TYPE:ELPIDA_2GB

CRITICAL

U3100,U3110,U3120,U3130

333S0565

DRAM_TYPE:MICRON_2GB

333S0554

4

U3300,U3310,U3320,U3330

333S0554 CRITICAL

U3400,U3410,U3420,U3430

4

DRAM_TYPE:SAMSUNG_2GB

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

333S0553 CRITICAL
333S0554

U3100,U3110,U3120,U3130

CRITICAL4DRAM_TYPE:MICRON_2GB

DRAM_TYPE:MICRON_2GB

CRITICAL333S0554

4

U3200,U3210,U3220,U3230

U3300,U3310,U3320,U3330

333S0553

DRAM_TYPE:SAMSUNG_2GB

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

4

333S0553 CRITICAL

DRAM_TYPE:SAMSUNG_2GB

U3200,U3210,U3220,U3230

4

CRITICAL333S0553

DRAM_TYPE:SAMSUNG_2GB

4

4

CRITICAL

DRAM_TYPE:HYNIX_2GB

333S0552

DRAM_TYPE:HYNIX_2GB

HYNIX,LVDDR3,1GBIT,7.5X11.0

333S0552

4

CRITICAL

DRAM_TYPE:HYNIX_2GB

4

333S0552

333S0552

DRAM_TYPE:HYNIX_2GB

U3100,U3110,U3120,U3130

CRITICAL

4

337S3938

MCP89U:A03

IC,MCP89U-A03,24.5MMX24.5MM,1244FCBGA

1

CRITICAL

U1400

U1400

1

MCP89U:A02

337S3868

CRITICAL

1

337S3820

MCP89U:A01U1400

353S2988

ALL

138S0638138S0681

TAIYO YUDEN AS ALTERNATE

MAGLAYERS AS ALTERNATE

376S0926

TAIYO AS ALTERNATE

TAIYO AS ALTERNATE

CYNTEC AS ALTERNATE

CYNTEC/DALE AS ALTERNATES

TPS71725 ALTERNATE FOR U2590

MAGLAYERS AS ALTERNATE

FAIRCHILD AS ALTERNATE

MAGLAYERS AS ALTERNATE

ON SEMI AS ALTERNATE

155S0578 155S0367

152S0874

152S0586

IC,SMC,HS8/2117,9X9MM,TLP,HF

MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF,MU_CAP_22UF

BOOTROM:BLANK

DDR3:MICRON_4GB

DDR3:SAMSUNG_4GB

DDR3:HYNIX_4GB

CAPS:MU
CAPS:TY

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

CRITICAL335S0610

U6100

1

U4900

CRITICAL

1

SMC:BLANK

338S0563

152S0516

ALL

152S0847

ALL

353S2987

HVDDLDO:FIXED

ALL

107S0075107S0139

ALL

138S0673138S0671

ALL

104S0018104S0023

ALL

ALL

376S0610

ALL

155S0329155S0457

ALL

377S0066377S0107

ALL

SYNC_DATE=12/11/2009

SYNC_MASTER=K6_MLB

BOM Configuration

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:MICRON_4GB

U3300,U3310,U3320,U3330

ELPIDA,LVDDR3,1GBIT,7.5X10.6

4

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

CRITICAL

U3400,U3410,U3420,U3430

ELPIDA,LVDDR3,2GBIT,7.5X10.6

ELPIDA,LVDDR3,2GBIT,7.5X10.6

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DRAM_TYPE:ELPIDA_4GB
DRAM_TYPE:ELPIDA_4GB
DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:MICRON_4GB

U3400,U3410,U3420,U3430

IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28

333S0557

333S0566

333S0565

333S0565

CAPS:SS

SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF,SS_CAP_22UF

K16_COMMON

K16_MISC

K16_PROGPARTS

BOOTROM:UNLOCKED,SMC:PROG

LPCPLUS

K16_DEVEL:PVT

K16_DEVEL:ENG

DEVEL_BOM,SMC_DEBUG:YES,XDP

K16_DEBUG:ENG

K16_DEBUG:PROD

K16_DEBUG:PVT

DDR3:HYNIX_2GB

DDR3:MICRON_2GB

DDR3:SAMSUNG_2GB

DDR3:ELPIDA_2GB
DDR3:ELPIDA_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:ELPIDA_4GB

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

IC,MCP89U-A01,24.5MMX24.5MM,1244FCBGA

IC,MCP89U-A02,24.5MMX24.5MM,1244FCBGA

HYNIX,LVDDR3,1GBIT,7.5X11.0

HYNIX,LVDDR3,1GBIT,7.5X11.0

HYNIX,LVDDR3,1GBIT,7.5X11.0

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

333S0566

BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

U3100,U3110,U3120,U3130

U3400,U3410,U3420,U3430

DRAM_TYPE:ELPIDA_2GB

ELPIDA,LVDDR3,2GBIT,7.5X10.6

4

333S0566

4

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DP_ESD,DP_PWR:SMC,VFRQ:SLPS3,HVDDLDO:FIXED,MCPHVDD:P2V5,MCPPLL_R:REG,S0PGOOD_BJT,ISL6259_SCREENED:YES,DPI2C:SMC

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

U3200,U3210,U3220,U3230

U3400,U3410,U3420,U3430

MICRON,LVDDR3,1GBIT,8X11.5

MICRON,LVDDR3,1GBIT,8X11.5

MICRON,LVDDR3,1GBIT,8X11.5

MICRON,LVDDR3,1GBIT,8X11.5

333S0565

TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF,TY_CAP_22UF

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB

COMMON,ALTERNATE,PROJ:K16,K16_MISC,MCP89U:A03,K16_DEBUG:ENG,K16_PROGPARTS,SPI:41MHZ,LVDDR3:YES,WLAN_PCTL:HW,IPD_5V:S5_INT,IPD_3V3:S5

BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,MCPPLL_LDO,S3_S0_LED

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB

DRAM_CFG0:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_2GB

DRAM_CFG0:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB

DRAM_CFG0:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB

DRAM_CFG0:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

U3200,U3210,U3220,U3230

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:MICRON_2GB

U3300,U3310,U3320,U3330

4 OF 110

3.3.0

051-8467

4 OF 74

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

SAMSUNG

MURATA

TAIYO YUDEN

K16-Specific BOM Tables

Sub-BOMs

Bar Code Labels / EEE #’s

BOM Variants

CRITICAL

[EEEE_DCXL]

EEEE:DCXL

1825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCWT]

EEEE:DCWT

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

825-7557

[EEEE_DCWR]

EEEE:DCWR

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

[EEEE_DCXM]

EEEE:DCXM

1 CRITICAL825-7557

EEEE:DCWN

825-7557

[EEEE_DCWN]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

825-7557

EEEE:DCX3

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX3]

1

825-7557 1

[EEEE_DCWW]

EEEE:DCWW

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:DCWP

825-7557

[EEEE_DCWP]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX0]

825-7557

EEEE:DCX0

1 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX1]

825-7557

EEEE:DCX1

1 CRITICAL

825-7557

[EEEE_DCWX]

EEEE:DCWX

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

CRITICAL

EEEE:DCX2

[EEEE_DCX2]

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

1

825-7557

EEEE:DCX4

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX4]

1 CRITICAL

[EEEE_DCX5]

EEEE:DCX5

1 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCWQ]

EEEE:DCWQ

1 CRITICAL

[EEEE_DCXK]

EEEE:DCXK

1 CRITICAL825-7557

1

EEEE:DCXC

CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCXC]

639-1092

PCBA,MLB,2.13GHZ HY 2GB,MU CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXJ,CAPS:MU,DDR3:HYNIX_2GB

PCBA,MLB,2.13GHZ HY 4GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX2,CAPS:TY,DDR3:HYNIX_4GB

639-1079

PCBA,MLB,2.13GHZ HY 4GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWX,CAPS:SS,DDR3:HYNIX_4GB

639-1075

PCBA,MLB,2.13GHZ HY 2GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX8,CAPS:TY,DDR3:HYNIX_2GB

639-1085

639-1082

PCBA,MLB,2.13GHZ,HY 2GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX5,CAPS:SS,DDR3:HYNIX_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWQ,CAPS:MU,DDR3:HYNIX_2GB

639-1070

PCBA,MLB,1.86GHZ HY 2GB,MU CAP,K16

PCBA,MLB,1.86GHZ HY 2GB,TY CAP,K16

639-1096

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXN,CAPS:TY,DDR3:HYNIX_2GB
K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXV,CAPS:MU,DDR3:HYNIX_4GB

639-1101

PCBA,MLB,1.86GHZ HY 4GB,MU CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXQ,CAPS:SS,DDR3:HYNIX_4GB

639-1098

PCBA,MLB,1.86GHZ HY 4GB,SS CAP,K16

639-1068

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWN,CAPS:TY,DDR3:HYNIX_4GB

PCBA,MLB,1.86GHZ HY 4GB,TY CAP,K16

639-1083

PCBA,MLB,1.86GHZ MI 2GB,MU CAP,K16

639-1090

PCBA,MLB,1.86GHZ MI 2GB,TY CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXG,CAPS:TY,DDR3:MICRON_2GB

639-1067

PCBA,MLB,1.86GHZ MI 4GB,SS CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWM,CAPS:SS,DDR3:MICRON_4GB

639-1088

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXD,CAPS:MU,DDR3:MICRON_4GB

PCBA,MLB,1.86GHZ MI 4GB,TY CAP,K16

639-1077

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWR,CAPS:TY,DDR3:SAMSUNG_2GB

639-1071

PCBA,MLB,1.86GHZ SA 2GB,TY CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXM,CAPS:SS,DDR3:SAMSUNG_2GB

PCBA,MLB,1.86GHZ SA 2GB,SS CAP,K16

639-1095

PCBA,MLB,1.86GHZ SA 2GB,MU CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX3,CAPS:MU,DDR3:SAMSUNG_2GB

639-1080

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXP,CAPS:MU,DDR3:SAMSUNG_4GB

639-1097

PCBA,MLB,1.86GHZ SA 4GB,MU CAP,K16

639-1099

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXR,CAPS:MU,DDR3:MICRON_2GB

PCBA,MLB,2.13GHZ MI 2GB,MU CAP,K16

639-1093

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXK,CAPS:SS,DDR3:MICRON_4GB

PCBA,MLB,2.13GHZ MI 4GB,SS CAP,K16
PCBA,MLB,2.13GHZ MI 4GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWY,CAPS:TY,DDR3:MICRON_4GB

EEEE:DCX8

1 CRITICAL

[EEEE_DCX8]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557

EEEE:DCX6

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

[EEEE_DCX6]

EEEE:DCXG

825-7557

[EEEE_DCXG]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

[EEEE_DCXD]

EEEE:DCXD

1825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX7,CAPS:SS,DDR3:SAMSUNG_4GB

639-1084

PCBA,MLB,1.86GHZ SA 4GB,SS CAP,K16
PCBA,MLB,1.86GHZ SA 4GB,TY CAP,K16

639-1091

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXH,CAPS:TY,DDR3:SAMSUNG_4GB

EEEE:DCX7

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

[EEEE_DCX7]

825-7557

PCBA,MLB,2.13GHZ MI 4GB,MU CAP,K16

639-1100

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXT,CAPS:MU,DDR3:MICRON_4GB

PCBA,MLB,2.13GHZ MI 2GB,TY CAP,K16

639-1069

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWP,CAPS:TY,DDR3:MICRON_2GB

639-1087

PCBA,MLB,2.13GHZ MI 2GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXC,CAPS:SS,DDR3:MICRON_2GB

EEEE:DCXJ

[EEEE_DCXJ]

1 CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXH

1

[EEEE_DCXH]

CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXF

1 CRITICAL825-7557

[EEEE_DCXF]

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXN

[EEEE_DCXN]

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

EEEE:DCWM

[EEEE_DCWM]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL825-7557 1

825-7557

[EEEE_DCWV]

EEEE:DCWV

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

1

[EEEE_DCWY]

EEEE:DCWY

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCX9

1 CRITICAL

[EEEE_DCX9]

825-7557

PCBA,MLB,2.13GHZ HY 4GB,MU CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXF,CAPS:MU,DDR3:HYNIX_4GB

639-1089

639-1078

PCBA,MLB,1.86GHZ MI 2GB,SS CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX1,CAPS:SS,DDR3:MICRON_2GB

639-0837

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXW,CAPS:SS,DDR3:HYNIX_2GB

PCBA,MLB,1.86GHZ,HY 2GB,SS CAP,K16

K16 BOM Variants

SYNC_DATE=N/A

SYNC_MASTER=N/A

825-7557
825-7557

1

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

PCBA,MLB,1.86GHZ MI 4GB,MU CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX6,CAPS:MU,DDR3:MICRON_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX0,CAPS:TY,DDR3:MICRON_4GB

639-1076

CPU:2.13GHZ

CRITICAL1 U1000

PDC,SLGEQ,PRQ,2.13,17W,1066,ED,6M,BGA

337S3758

CRITICAL1337S3751 U1000

CPU:1.86GHZ

PDC,SLGAB,PRQ,1.86,17W,1066,ED,6M,BGA

U49001 SMC:PROGCRITICAL

IC ASSY,SMC EXTERNAL,K16

341T0276
341T0275

IC ASSY,EFI UNLOCKED,K16

BOOTROM:UNLOCKED

U61001 CRITICAL

CRITICAL1 U6100

BOOTROM:LOCKED

341S2785

IC EFI ROM,PVT,LOCKED,K16

085-1327 1

DEVEL_BOM

CRITICALDEVEL

K16 MLB DEVELOPMENT BOM

607-6915 CRITICAL1

CMN PTS,PCBA,MLB,K16

CMNPTS

K16_CMNPTS

138S0634 CRITICAL

TY_CAP_2_2UF

1 C4807

CAP, 2.2UF, 6.3V, 20%, 0402CAP, 2.2UF, 6.3V, 20%, 0402

138S0633 CRITICAL

MU_CAP_2_2UF

1 C4807138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

1

SS_CAP_2_2UF

639-1072

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWT,CAPS:SS,DDR3:SAMSUNG_2GB

PCBA,MLB,2.13GHZ SA 2GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX9,CAPS:TY,DDR3:SAMSUNG_2GB

639-1074

PCBA,MLB,2.13GHZ SA 2GB,MU CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWW,CAPS:MU,DDR3:SAMSUNG_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWV,CAPS:MU,DDR3:SAMSUNG_4GB

639-1073

PCBA,MLB,2.13GHZ SA 4GB,SS CAP,K16

639-1081

PCBA,MLB,2.13GHZ SA 4GB,TY CAP,K16

639-1094

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 CRITICAL1

[EEEE_DCXP]

EEEE:DCXP

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 1

[EEEE_DCXQ]

EEEE:DCXQ

CRITICAL

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCXR]

EEEE:DCXR

825-7557 CRITICAL1

EEEE:DCXT

[EEEE_DCXT]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXV

[EEEE_DCXV]

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

EEEE:DCXW

[EEEE_DCXW]

PCBA,MLB,1.86GHZ EL 2GB,SS CAP,K16

639-1451

PCBA,MLB,1.86GHZ EL 2GB,TY CAP,K16

639-1455

PCBA,MLB,2.13GHZ EL 2GB,SS CAP,K16

639-1454

PCBA,MLB,2.13GHZ EL 2GB,MU CAP,K16

639-1453

PCBA,MLB,1.86GHZ EL 2GB,MU CAP,K16

639-1450

639-1452

PCBA,MLB,2.13GHZ EL 2GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG50,CAPS:TY,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG52,CAPS:SS,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG51,CAPS:MU,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG53,CAPS:TY,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG4Y,CAPS:SS,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG4W,CAPS:MU,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXL,CAPS:TY,DDR3:SAMSUNG_4GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX4,CAPS:SS,DDR3:SAMSUNG_4GB

PCBA,MLB,2.13GHZ SA 2GB,TY CAP,K16
PCBA,MLB,2.13GHZ SA 4GB,MU CAP,K16

639-1086

CRITICALC4807

EEEE:DG4Y

[EEEE_DG4Y]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 1 CRITICAL

EEEE:DG4W

[EEEE_DG4W]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 CRITICAL1

EEEE:DG53

[EEEE_DG53]

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DG52

[EEEE_DG52]

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DG51

[EEEE_DG51]

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DG50

[EEEE_DG50]

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

1 CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG5P]

EEEE:DG5P

CRITICAL1825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG5W]

EEEE:DG5W

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

[EEEE_DG5T]

EEEE:DG5T

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

[EEEE_DG5V]

EEEE:DG5V

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

[EEEE_DG5Q]

EEEE:DG5Q

1 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557

[EEEE_DG5R]

EEEE:DG5R

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG5P,CAPS:MU,DDR3:ELPIDA_4GB

PCBA,MLB,1.86GHZ EL 4GB,MU CAP,K16

639-1458

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG5W,CAPS:SS,DDR3:ELPIDA_4GB

PCBA,MLB,1.86GHZ EL 4GB,SS CAP,K16

639-1463

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG5T,CAPS:TY,DDR3:ELPIDA_4GB

PCBA,MLB,1.86GHZ EL 4GB,TY CAP,K16

639-1460

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG5R,CAPS:TY,DDR3:ELPIDA_4GB

639-1461

PCBA,MLB,2.13GHZ EL 4GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG5Q,CAPS:MU,DDR3:ELPIDA_4GB

PCBA,MLB,2.13GHZ EL 4GB,MU CAP,K16

639-1462

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG5V,CAPS:SS,DDR3:ELPIDA_4GB

PCBA,MLB,2.13GHZ EL 4GB,SS CAP,K16

639-1459

K16_COMMON

CMN PTS,PCBA,MLB,K16

607-6915

K16_DEVEL:ENG

085-1327

K16 MLB DEVELOPMENT BOM

5 OF 110

3.3.0

051-8467

5 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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D

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8 7 5 4 2 1

7803283 - Changed 5V S3 regulator output from 5.02V to 5.12V nominal (pg. 72).
7809760 - Stuffed C9799 and clarified tables/BOMOPTIONs around these parts (pg. 97).

Proto 1 (ECO #0000884508, v2.0.0, P4 change #212783, 03/31/2010)

7796658 - Changed OMITs to OMIT_TABLEs (pp. 10-11, 14-20, 26, 31-36, 49, 61).

7796658 - Added alternates for two caps per GSM and removed unused alternates (pg. 4).

BOM:

BOM:

v2.1.0 (P4 change #??????, ??/??/2010)

v1.4.0 (P4 change #212757, 03/31/2010)

7761747 - Documented SMBus addresses for panel (pg. 52).
SD Card:
7800415 - Changed SD Card discharge R to more standard value (pg. 48).
Power Supplies:

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

7798399 - Consolidated 100pF caps (pp. 74, 75).

7809733 - Changed strapping to select 62.5MHz SPI bus frequency (pg. 4).

7796631 - Added XDP connection to SMBus aliases page (pp. 13, 52).
7808530 - Changed SMC ’MGMT’ SMBus pull-ups from 4.7K to 2K (pg. 52).

MCP SPI:

7788138 - Added feedback divider and BOM tables for more HVDD LDOs (pp. 4, 25).

7787883 - Added support for DP HPD wake / S4 state (pp. 4, 7, 8, 19, 49, 50, 78, 94).

7798425 - R/C value changes for 3.42V G3Hot power supply (pg. 69).

7796631 - Sorted BOM variants for easier verification (pg. 5).

7796683 - Stuffed RC on backlight driver PWM input (pg. 97).

7796658 - Changed RCs on some SMC analog inputs (pg. 54).

7796661 - Set up primary & alternate for power supply FET (pp. 4, 72).

7796648 - Changed DP and LCD power from PP3V3_S3 to PP3V3_S5 (pp. 8, 90).

7796626 - Changed port switch from TPS2052B to TPS2069 (pg. 46).

7742015 - Added RC to DDC pass FETs to avoid glitch (pp. 7, 93).

7761747 - Added resistors to connect TCON to SMC or MCP SMBus (pp. 4, 52, 90).

v1.1.0 (P4 change #211399, 03/24/2010)

v1.2.0 (P4 change #211839, 03/26/2010)

7787883 - Added PLACE_NEAR property on R5022 to avoid stub (pg. 50).

7787897 - Property/page fixes to reduce CheckPlus warnings/errors (pp. 7, 8, 12, 17, 74, 93, 108).

7769139 - Unstuffed SMS circuit (pg. 4).

7765466 - Added S3 pull-up to SMS_INT_L to prevent leakage path (pp. 50, 59).

SMC:

SMBus:

USB:

MCP:

SMC:

SMS:

General:

7761747 - Added TCON I2C nets to FUNC_TEST list for J9000 (pg. 7).

7796631 - Cosmetic clean-up (pg. 76).

7761747 - Added isolation FET and unstuffed series R’s on TCON I2C for now (pp. 4, 90, 108).

7796658 - Changed backlight driver back to non-E00 version (pp. 4, 97).

7796654 - Consolidated SSM6N15FE to SSM6N37FE (pg. 48).

7798445 - R value changes for 0.9V S5 power supply (pg. 77).

7800179 - R value changes for CPU VCore power supply (pg. 74).

7798399 - R/C value changes for 5V/3.3V power supply (pg. 72).

7796661 - Removed alternate FET, made some FETs primary to other APN (pp. 4, 72, 73, 76).

v1.3.0 (P4 change #212050, 03/26/2010)

7796658 - Changed backlight driver to E00 version (pg. 97).
BOM:

SMBus:

General:

SMBus:

Power Supply:

Power:

Proto 0 (ECO #0000876215, v1.0.0, P4 change #210266, 03/16/2010)

Revision History

Revision History

SYNC_MASTER=N/A

SYNC_DATE=N/A

6 OF 110

3.3.0

051-8467

6 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(Need to add 5 GND TPs)

FUNC_TEST

Misc Voltages & Control Signals

(Need to add 27 GND TPs)

(Need 5 TPs)

(Need 4 TPs)

J6950 and 1 for shield)

(Need to add 4 GND TPs near

J9000: Internal DP Connector

(Need to add 6 GND TPs)

(Need to add 5 GND TPs)

(Need to add 6 GND TPs)

(Need to add 2 GND TPs)

(Need to add 6 GND TPs)

(Need to add 6 GND TPs)

(Need 2 TPs)

J5100: LPC+SPI Connector

J4800: SD Card Connector

(Need to add 5 GND TPs)

FUNC_TEST

FUNC_TEST

(Need 5 TPs)

J4001: AirPort / BT Connector

FUNC_TEST

FUNC_TEST

J6950: Battery Connector

J6903: Speaker Connector

FUNC_TEST

J6900: DC-In Connector

(Need 6 TPs)

J5700: IPD Flex Connector

J5600: Fan Connector

FUNC_TEST

FUNC_TEST

(Need to add 1 GND TP)

J4700: LIO Connector

J4501: SATA SSD Connector

FUNC_TEST

(Need 2 TPs)
(Need 2 TPs)

FUNC_TEST

FUNC_TEST

FUNC_TEST

Functional Test Points

NO_TEST

NO_TEST Nets

FSB Signals (Covered via CPU/MCP JTAG)

Functional Test / No Test

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(02/16/2010)

=I2C_TCON_SDA

TRUE

=I2C_TCON_SCL

TRUE

TRUE

DP_INT_ML_F_N<1>

TRUE

LED_RETURN_6

DP_INT_ML_F_P<1>

TRUE

DP_INT_ML_F_N<0>

TRUE

DP_INT_ML_F_P<0>

TRUE

DP_INT_AUX_CH_C_P

TRUE

DP_INT_AUX_CH_C_N

TRUE

DP_INT_HPD_CONN

TRUE

LED_RETURN_1

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LED_RETURN_4

TRUE

LED_RETURN_5

TRUE

PM_SLP_S3_L

TRUE

PM_SLP_S4_L

TRUE

SMC_PM_G2_EN

TRUE

PPVCORE_S0_MCP

TRUE

PPVCORE_S0_CPU

TRUE

PP0V9_S5

TRUE

PP0V9_ENET

TRUE

PP1V05_S0_MCP_PLL_UF

TRUE

PP1V05_S0

TRUE

PP1V5_S0

TRUE

PP3V3_ENET

TRUE

PP1V5R1V35_S3

TRUE

PP3V3_S0

TRUE

PP3V3_S0_HDD_R

TRUE

PP3V3_WLAN_F

TRUE

PP3V3_S3

TRUE

PP3V3_SW_DPPWR

TRUE

PP3V3_S5

TRUE

PP5V_S0

TRUE

PP3V42_G3H

TRUE

PP5V_S3

TRUE

PP5V_S3_RTUSB_A_F

TRUE

PPBUS_G3H_ISNS

TRUE

PPBUS_G3H

TRUE

PPDCIN_S5_S5

TRUE

PPVOUT_SW_LCDBKLT

TRUE

SMC_HDD_TEMP_CTL

TRUE

SATA_HDD_R2D_P

TRUE

SMC_HDD_OOB_TEMP

TRUE

SATA_HDD_R2D_N

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

PP3V3_S0_HDD_R

TRUE

TRUE

=PP1V8R1V5_S0_AUDIO

=PP3V3_S0_AUDIO

TRUE

TRUE

=PP3V42_G3H_ONEWIRE

=I2C_MIKEY_SDA

TRUE

=I2C_LIO_SCL

TRUE

=I2C_MIKEY_SCL

TRUE

=I2C_LIO_SDA

TRUE

SMC_LID

TRUE

=USB_PWR_EN

TRUE

SYS_ONEWIRE

TRUE

SMC_BC_ACOK

TRUE

TRUE

HDA_SYNC

TRUE

USB_EXTD_OC_L
HDA_RST_L

TRUE

HDA_BIT_CLK

TRUE

HDA_SDIN0

TRUE

HDA_SDOUT

TRUE

USB_CAMERA_N

TRUE

USB_CAMERA_P

TRUE

USB_EXTD_P

TRUE

TRUE

SPKRAMP_INR_P
USB_EXTD_N

TRUE

TRUE

AUD_GPIO_3

TRUE

SPKRAMP_INR_N

TRUE

AUD_I2C_INT_L

TRUE

AUD_IPHS_SWITCH_EN

TRUE

AUD_IP_PERIPHERAL_DET

LPC_AD<3..0>

TRUE

=PP5V_S0_LPCPLUS

TRUE

SD_WP

TRUE

SD_CD_L

TRUE

SD_CMD

TRUE

SD_D<7..0>

TRUE

LPCPLUS_GPIO

TRUE

SMC_NMI

TRUE

SMC_RX_L

TRUE

SMC_RESET_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

LPC_PWRDWN_L

TRUE

SPI_ALT_CS_L

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CLK

TRUE

SPIROM_USE_MLB

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SMC_MD1

TRUE

SMC_TX_L

TRUE

SMC_TRST_L

TRUE

SMC_TDO

TRUE

LPCPLUS_RESET_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

TRUE

SPI_ALT_MOSI

TRUE

=PP3V3_S5_LPCPLUS

TRUE

SD_CLK

TRUE

PP3V3_SW_SD_PWR

TRUE

=PP3V3_S3_BT

TRUE

AP_CLKREQ_Q_L

TRUE

AP_RESET_CONN_L

TRUE

PCIE_WAKE_L

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_AP_R2D_N

TRUE

WIFI_EVENT_L

TRUE

PP3V3_WLAN_F

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

PPVBAT_G3H_CONN

TRUE

SPKRAMP_R_P_OUT

TRUE

SPKRAMP_R_N_OUT

TRUE

=PP5V_S3_LIO_CONN

TRUE

=PP18V5_DCIN_CONN

TRUE

SMC_LID

TRUE

SMC_TPAD_RST_L

TRUE

=PP5V_S3_TPAD

TRUE

=PP3V42_G3H_TPAD

TRUE

=PP3V3_S3_TPAD

TRUE

USB_TPAD_CONN_P

TRUE

USB_TPAD_CONN_N

TRUE

=I2C_TPAD_SDA

TRUE

SMC_ONOFF_L

TRUE

=I2C_TPAD_SCL

TRUE

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE

TRUE

PP5V_S0

PP3V3_SW_LCD

TRUE

PPVOUT_SW_LCDBKLT

TRUE

USB_BT_P

TRUE

USB_BT_N

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_ADS_L

TRUE

FSB_A_L<35..3>

TRUE

FSB_LOCK_L

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_D_L<63..0>

TRUE

FSB_DINV_L<3..0>

TRUE

FSB_HIT_L

TRUE
TRUE

FSB_HITM_L

FSB_REQ_L<4..0>

TRUE

FSB_DSTB_L_P<3..0>

TRUE

7 OF 110

3.3.0

051-8467

7 OF 74

42 60

42 60

60 72

60 63

60 72

60 72

60 72

60 72

60 72

60

60 63

60 63

60 63

60 63

60 63

19 39 40 58

19 39 58

39 58

8

43

8

43

8

8

8

8

58

8

58 72

8

8

72

8

58 72

7

35

7

34 40

8

62

8

58 72

7 8

58

8

8

36

8

8

43 50

8

7

43 60 63

35 39

35 68

35 39

35 68

35 68

35 68

7

35

8

37

8

37

8

37

37 42

37 42

37 42

37 42

7

37 39 40 47

36 37 58

37 39

9

37 39 40

19 37 69

18 37

19 37 69

19 37 69

19 37 69

19 37 69

18 37 69

18 37 69

18 37 69

37 49 72

18 37 69

37 49

37 49 72

19 37

19 37

17 37

19 39 41 69

8

41

38

38

38 70

38 70

19 41

39 41

36 39 40 41

39 40 41 51

39 40 41

39 40 41

19 39 41

41 69

19 39 41

41 69

19 41 48

25 41 69

39 41

36 39 40 41

39 41

39 40 41

25 41

19 39 41

39 40 41

41 69

19 39 41 69

41 69

8

41

38 70

38

8

34

34

34

16 34

16 34 68

16 34 68

16 34 68

16 34 68

34 68

34 68

34 39 40

7

34 40

42 71

50

42 71

50 51

49 50

49 50

8

50

8

50

7

37 39 40 47

40 47

8

57

8

47

8

47

47 72

47 72

42 47

39 40 47

42 47

46

46

7 8

58

60

7

43 60 63

18 34 69

18 34 69

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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R

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SHEET

PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

"S5" Rails

3.30 A

0 mA

"G3Hot" (Always-Present) Rails

0.064

0.100 A

300mA

"S3" Rails

11.30 A

5.40 A

300mA

4250 mA

(OR 0.675V)

(OR 0.675V)

23.8 A

1.20 A

18 A

9.40 A

0.210 A

105 mA/241 mA

0.290 A

1.07 A + S3 + S0

"S0" Rails

1.274 A

"ENET" Rails

(OR 1.35V)

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(02/11/2010)

Power Aliases

=PP3V3_S5_P0V9ENETFET

=PP3V3_S5_P3V3S3FET

=PP3V42_G3H_SMCUSBMUX

=PPVIN_S5_SMCVREF

=PPDDR_S3_REG

=PPBUS_S0_LCDBKLT

=PPVIN_S0_MCPCORE

=PP3V3_S5_LPCPLUS

=PP5V_S3_AUDIO_AMP

PP3V3_G3_RTC

=PPVIN_S5_CPU_IMVP

VOLTAGE=8.4V
MAKE_BASE=TRUE

PPBUS_G3H_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V

PPDCIN_S5_S5

MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

=PPVIN_S3_DDRREG

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM

=PPVIN_S5_P5VP3V3

VOLTAGE=8.4V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

=PPBUS_G3H

=PPBUS_5V_S5

=PPVIN_S0_CPUVTTS0

=PPBUS_G3H_R_IN

=PP3V42_G3H_TPAD

=PP3V3_S5_MCPPWRGD

=PP3V3_S5_MCP

=PP3V3_S5_SMC

=PP3V42_G3H_CHGR
=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_REG

=PPBUS_G3H_R_OUT

=PP3V3_S0_FET

MAKE_BASE=TRUE

PP5V_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

=PP5V_S0_FET

MIN_LINE_WIDTH=0.6 MM

PP1V5_S0

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 mm

=PP1V5_S0_CPU

=PP1V8R1V5_S0_AUDIO

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_CPU

=PP1V5R1V35_S3_MCP_MEM

=PP3V3_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

=PPVIN_S0_DDRREG_LDO

=PP1V5R1V35_S0_MCPDDRFET
=PPLVDDR_S3_MEM_A

=PP5V_S3_LIO_CONN

=PP5V_S3_TPAD

=PP5V_S3_SYSLED

=PP5V_S3_REG

=PP5V_S3_MCPDDRFET
=PP5V_S3_RTUSB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_ENET

=PP3V3_S3_WLANISNS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_SMS

=PP1V05_S0_MCP_M2CLK_DLL
=PP1V05_S0_MCP_DP0_VDD
=PP1V05_S0_MCP_PE_DVDD
=PP1V05_S0_MCP_SATA_DVDD

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_DPCONN

=PP3V3_S0_PWRCTL

=PP3V3_S0_P1V5S0

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_IMVP

=PP3V3_S0_FAN

=PP3V3_S0_MCPTHMSNS

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_CSREGISNS
=PP3V3_S0_MCPCOREISNS

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

=PP3V3_S0_HDD

=PP3V3_S0_HDDISNS

=PP3V3_S0_BKLTISNS

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_DEBUGROM
=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_SMC

=PP3V3_S0_AUDIO

=PP18V5_DCIN_CONN

=PP1V05_SW_MCP_FSB

=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_MCP_FSB

=PP1V05_S0_XDP

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_PLL_UF

=PP5V_S0_MCPFSBFET

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP

=PP3V3_S0_MCP_HVDD

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_XDP

=PP5V_S0_BKL
=PP5VR3V3_S0_DPCADET

=PP1V5_S0_REG

=PPCPUVTT_S0_REG

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

=PP1V05_S0_MCP_PLL_OR

=PPVTT_S0_DDR_LDO

=PPMCPCORE_S0_REG

=PPVCORE_S0_CPU_REG

=PPDDRVTT_S0_MEM_B

=PPDDRVTT_S0_MEM_A

=PPVCORE_S0_MCPGFXFET

=PPVCORE_S0_MCP

=PPVCORE_S0_CPU

=PP3V3R1V5_S0_MCP_HDA

=PP1V5_S0_MCP_PLL_VLDO

=PP5V_S0_CPUVTTS0

=PP5V_S0_MCPREG

=PP5V_S0_CPU_IMVP

=PP5V_S0_LPCPLUS
=PP5V_S0_FAN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=0.75V

PPDDRVTT_S0

VOLTAGE=1.05V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_MCP

=PP0V9_ENET_MCP_RMGT

=PP3V3_S5_P0V9S5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP0V9_ENET

MAKE_BASE=TRUE

VOLTAGE=0.9V

=PP0V9_ENET_FET

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_SMBUS_SMC_MGMT
=PP3V3_S5_ROM

=PP0V9_S5_MCP_VDD_AUXC
=PP0V9_ENET_P0V9ENETFET

=PP3V3_S5_TPAD
=PP3V3_SMC_PME

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S5

PP0V9_S5

VOLTAGE=0.9V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

=PP3V3_S3_DBGLEDS

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

MIN_NECK_WIDTH=0.25 mm

=PP3V3_S3_FET

=PP0V9_S5_REG

=PP3V3_S5_REG

=PP3V3_ENET_FET_R

PPDDRVREF_S3

VOLTAGE=0.75V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

=PPLVDDR_S3_MEM_B

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm

PP1V5R1V35_S3

MAKE_BASE=TRUE

=PP5V_S3_P5VS0FET

=PP5V_S3_DDRREG

=PP3V3_S3_CARDREADER

=PP3V3_S3_MCP_GPIO
=PP3V3_S3_VREFMRGN
=PP3V3_S3_BT
=PP3V3_S3_WLAN

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_TPAD

=PP3V3_S3_PDCISENS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S3

=PPVTT_S3_DDR_BUF

=PP3V42_G3H_ONEWIRE

=PP3V3_S0_LCD

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_P3V3S0FET

=PP3V3_S5_VMON

=PP3V3_S5_MCP_GPIO

8 OF 110

3.3.0

051-8467

8 OF 74

59

59

36

40

53

64

55

7

41

49

19 20 23

54

7

7

51

53

7

52

7

43 50 51

57

56

44

7

47

25

20 23

39 40

51 58

58

42

44

50

44

59

7

58 59

7

58 72

11 12

7

37

7

58

10 11 12

15

23

18 20 23

53

21

26 27 30

7

50

7

57

40

52

21

36

7

43

42

15 23

17 24

20 23

20 23

63

62

58

57

57

54

46

45

45

44

44

44

7

58 72

35

43

43

42

42

42

41

42

40

7

37

7

50

20 23

23

57

14 20 23

13

7

23

22

23

20 23

20 23

17 18 19

13

63

62

57

56

7

43

57

53

55

54

32

32

22

20 23

11 12 65

19 23

57

56

55

54

7

41

46

7

43

20 23

57 58

7

59

59

42

48

20 23

59

47

40

7

58 72

7

50

7

59

57

52 58

9

28 29 31

7

72

59

53

38

19

33

7

34

34

43

7

47

53

7

33 53

7

37

60

62

59

58

18 19

OUT
OUT
OUT
OUT

OUT
OUT

BI

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT

BI

BI

BI

BI

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DisplayPort Pogo

806-1176

Digital Ground

(Provides PCB support for small finger above J9400)

DisplayPort PCB Stiffener

USB/SD Card Pogo

CPU Aliases

DisplayPort Aliases

External DisplayPort Signals

Internal DisplayPort Signals

MCPCOREISNS Signals

Charger Signal

LVDS Aliases

Unused PCI-E Lanes

PCI-E Aliases

Unused SATA ODD Signals

SATA Aliases

Unused USB Ports

USB Aliases

Misc MCP89 Aliases

CPU Heat Sink Mounting Bosses

870-1938

Fan Boss

860-1327

EMI I/O Pogo Pins

X21 Boss

860-1327

4x 860-1327

860-1327

SSD Boss

4x 860-1327

MCP Heat Sink Mounting Bosses

Plated Board Slot

Ethernet Aliases

870-1938

18 70

18 70

18 70

18 70

18 70

18 70

18 70

18

1/20W

5%

201

MF

10K

R0981

10K

1/20W

5%

201

MF

R0980

7

37 39 40 51

PLACE_NEAR=U7980.A1:5MM

0

MF-LF

402

5%

1/16W

R0911

8

18

1/20W

10K

MF

201

5%

R0982

R0984

1/20W

5%

201

MF

10K

MF

10K

201

5%
1/20W

R0983

10K

MF
201

5%
1/20W

R0985

SM

CRITICAL

POGO-2.0OD-3.6H-K86-K87

ZS0905

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

ZS0906

STDOFF-4.5OD1.9H-SM

Z0915

STDOFF-4.5OD1.8H-SM

Z0910

STDOFF-4.5OD1.8H-SM

Z0911

STDOFF-4.5OD1.8H-SM

Z0912

STDOFF-4.5OD1.8H-SM

Z0913

STDOFF-4.5OD1.8H-SM

Z0905

STDOFF-4.5OD1.9H-SM

Z0914

18 68

18 68

18 68

18 68

17 68

17 68

17 68

17 68

17

17

17

61

17

17 68

17 68

61

61

17 68

17 68

62 72

62 72

60 72

60 72

62 72

62 72

61

61

60 72

60 72

60

62

62

17

9

17 60

17

17

17

63

9

17 60

64

18 69

18 69

18 69

18 69

16 68

16 68

16

16

16

16

16

17

17

17

17

17

17

17

17

10 66

14

14

16

15 67

15 67

15 67

15 67

15 67

15 67

19

55

55

44

44

STDOFF-4.5OD1.8H-SM

Z0909

STDOFF-4.5OD1.8H-SM

Z0907

STDOFF-4.5OD1.8H-SM

Z0906

STDOFF-4.5OD1.8H-SM

Z0908

SL-2.3X3.9-2.9X4.5

TH-NSP

SL0900

Signal Aliases

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

ENET_RX_CTRL
ENET_MDIO

ENET_CLKREQ_L

DP_IG_ML1_P<2..3>

LCD_IG_PWR_EN

MAKE_BASE=TRUE

CPU_PECI_MCP

CPU_BSEL<0:2>

MAKE_BASE=TRUE

DP_IG_ML0_P<0..3>
DP_IG_ML0_N<0..3>

DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N

DP_IG_HPD0

DP_CA_DET

DP_AUX_CH_C_N
DP_AUX_CH_C_P

DP_IG_ML1_P<0..1>
DP_IG_ML1_N<0..1>

DP_IG_ML1_N<2..3>

DP_IG_AUX_CH1_P

DP_IG_HPD1

DP_IG_AUX_CH1_N

ENET_RXD_PD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

ENET_RXCLK_PD

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET_FET

=PP3V3_ENET_FET

MAKE_BASE=TRUE

SMC_BC_ACOK

=CHGR_ACOK

TP_DP_INT_MLP<2..3>

MAKE_BASE=TRUE

TP_DP_INT_MLN<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ENET_CLKREQ_L

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

ENET_ENERGY_DET

MCP_RGMII_VREF

ENET_CLK125M_RXCLK

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

=PP3V3_ENET_FET_R

LCD_BKLT_EN

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_INT_HPD

DP_INT_AUX_CH_N

MAKE_BASE=TRUE

DP_INT_AUX_CH_P

MAKE_BASE=TRUE

DP_INT_ML_N<0..1>

MAKE_BASE=TRUE

DP_INT_ML_P<0..1>

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_P

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_N

MAKE_BASE=TRUE

DP_EXT_HPD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_CA_DET

MAKE_BASE=TRUE

DP_EXT_AUX_CH_N

DP_EXT_AUX_CH_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_ML_N<0..3>

MAKE_BASE=TRUE

DP_EXT_ML_P<0..3>

=MCP_BSEL<0:2>

MAKE_BASE=TRUE

MCPCORES0_VO

MAKE_BASE=TRUE

MCPCORES0_ISP_R

=MCPCOREISNS_N
=MCPCOREISNS_P

NC_LVDS_IG_A_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_LVDS_DDC_DATA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_LVDS_DDC_CLK

NO_TEST=TRUE

NC_PEG_R2DCP<5:4>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2DCN<5:4>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<5:4>

NO_TEST=TRUE

NC_PEG_D2RP<5:4>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_CLK100MP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_CLK100MN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PEG_CLKREQ_L

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

NO_TEST=TRUE

NC_USB_MINIP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_MININ

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXTCN

NO_TEST=TRUE

NC_USB_EXTCP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREFTP_MCP_RGB_DAC_VREF

TP_MEM_A_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKN<1>

TP_MEM_A_A<15>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5

MAKE_BASE=TRUE

=MCP_IFPA_TXC_P

=MCP_IFPA_TXD_P<0..3>

=MCP_IFPA_TXC_N

=MCP_IFPB_TXC_N

=MCP_IFPB_TXC_P

=MCP_IFPA_TXD_N<0..3>

=MCP_IFPB_TXD_N<0..3>

=MCP_IFPB_TXD_P<0..3>

=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

=PEG_D2R_P<5:4>

=PEG_D2R_N<5:4>

=PEG_R2D_C_P<5:4>

=PEG_R2D_C_N<5:4>

PEG_CLK100M_P

PEG_CLKREQ_L

SATA_ODD_R2D_C_P

PEG_CLK100M_N

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P
SATA_ODD_D2R_N

USB_MINI_P
USB_MINI_N

USB_EXTC_N

USB_EXTC_P

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_A<15>

MEM_A_A<15>

MCP_MEM_VDD_SEL_1V5

LCD_IG_BKLT_EN

LCD_IG_PWR_EN

LCD_IG_BKLT_PWM

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.1 mm

VOLTAGE=0V

GND

SM-SP

MT0900

STIFFENER-K16-K99

NO STUFF

9 OF 110

3.3.0

051-8467

9 OF 74

121

2

1 2

1

2

1

2

1

2

1

2

1 1

1

1

1 1

1

1 1

1

1

1

1

1

1

59

17

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN

IN

IN
IN

IN

IN

OUT

BI
BI
BI
BI

OUT

IN
IN

A6*

BR0*

BPM0*

DBR*

DEFER*

DBSY*

A7*

A15*

A14*

REQ2*

A17*
A18*

PREQ*

IERR*

BPRI*

BNR*

A4*

TRST*

LINT1

TEST2

TEST4

A16*

A20M*

A3*

A30*
A31*
A32*

A34*
A35*

A5*

A8*

ADSTB0*

ADSTB1*

BCLK1

BPM2*
BPM3*

FERR*

HIT*

HITM*

IGNNE*

LINT0

RSVD7

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

TEST1

TEST3

TEST5
TEST6

PROCHOT*

REQ0*
REQ1*

REQ3*
REQ4*

SMI*

TCK

TDO

THERMTRIP*

THRMDA
THRMDC

TMS

PRDY*

BPM1*

RS2*

RS1*

RS0*

RESET*

DRDY*

ADS*

A19*
A20*
A21*

A23*

A22*

A24*
A25*
A26*
A27*
A28*
A29*

A33*

STPCLK*

A13*

A12*

A11*

BCLK0

TDI

TRDY*

LOCK*

INIT*

A10*

A9*

(1 OF 8)

XDP/ITP SIGNALS

ADDR GROUP0ADDR GROUP1

THERMAL

H CLK

ICH

CONTROL

D11*

D7*

D6*

D5*

D4*

D3*

D17*

D16*

DINV0*

DSTBP0*

DSTBN0*

D10*

D2*

SLP*

PWRGOOD

PSI*

GTLREF

DSTBP3*

DSTBP2*

DSTBN3*

DSTBN2*

DSTBN1*

DPWR*

DPSLP*

DPRSTP*

DINV3*

DINV2*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D53*

D52*

D51*

D50*

D49*

D48*

D47*

D46*

D45*

D44*

D43*

D42*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

D31*

D30*

D26*

D25*

D24*

D23*

D22*

D21*

D20*

D13*

D12*

D1*

D0*

COMP3

COMP2

COMP1

COMP0

BSEL2

BSEL1

BSEL0

D27*

D29*

D8*

DINV1*

DSTBP1*

D28*

D14*
D15*

D9*

D19*

D18*

D41*

(2 OF 8)

DATA GRP 3

DATA GRP1

MISC

DATA GRP 0

DATA GRP 2

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE_NEARs:

C1014.1:

R1006.1:

R1005.2:

PLACE_NEARs:

R1020.1:
R1021.1:
R1022.1:
R1023.1:

CPU JTAG Support

54.9

1%

201

1/20W

MF

R1000

68

5%

201

1/20W

MF

R1002

U1000.AW43:12.7 mm

1%

1K

201

1/20W
MF

R1005

1%

U1000.AW43:12.7 mm

2K

201

1/20W
MF

R1006

54.9

1%

U1000.AF2:12.7 mm

201

1/20W

MF

R1023

27.4

1%

U1000.AE1:12.7 mm

201

1/20W
MF

R1022

54.9

1%

U1000.AD44:12.7 mm

201

1/20W

MF

R1021

27.4

1%

U1000.AE43:12.7 mm

201

1/20W
MF

R1020

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

14 54 66

14 66

14 66

14 66

13 14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

9

66

9

66

9

66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

14 66

14 66

14 66

14 66

14 66

14 66

7

14 66

7

14 66

7

14 66

13 66

13 66

13 66

13 66

13 66

13 66

10 13 66

14 40 66

45 72

14 40 66

14 66

13 14 66

14 66

14 66

14 66

14 66

10 13 66

10 13 66

10 13 66

10 13 66

45 72

14 66

14 66

14 66

14 66

14 66

14 66

14 66

NO STUFF

5%

0

201

1/20W

MF

R1010

NO STUFF

1K

5%

201

1/20W

MF

R1011

54.9

1%

201

1/20W

MF

R1001

1%

54.9

201

1/20W

MF

R1090

1%

54.9

201

1/20W

MF

R1091

1%

54.9

201

1/20W

MF

R1093

7

14 66

7

14 66

7

14 66

7

14 66

MF

54.9

1%

201

1/20W

R1094

NO STUFF

1K

5%

201

1/20W
MF

R1012

U1000.AE41:12.7 mm

NO STUFF

X5R

10%

0.1UF

201

6.3V

C1014

1/20W

1%

54.9

PLACE_NEAR=J1300.52:12.7 mm

201

MF

R1092

13 25

14 66

14 66

NEED_TP=TRUE
NEED_TP=TRUE

OMIT_TABLE

BGA

PENRYN-SFF

CDC-QKWH-QS-1.2-10W-800-R0-1M

U1000

OMIT_TABLE

CDC-QKWH-QS-1.2-10W-800-R0-1M

BGA

PENRYN-SFF

U1000

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

CPU FSB

CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L

CPU_COMP<0>

XDP_TMS

FSB_A_L<23>

FSB_A_L<7>

FSB_REQ_L<3>
FSB_REQ_L<4>

CPU_INTR

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_BREQ0_L

CPU_IERR_L

FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L

XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_TDI

CPU_THERMD_N

PM_THRMTRIP_L

CPU_PROCHOT_L

XDP_BPM_L<5>

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_ADS_L
FSB_BNR_L

TP_CPU_PSI_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

XDP_TDO

XDP_TCK

FSB_CPURST_L

CPU_INIT_L

FSB_BPRI_L

TP_CPU_RSVD_J9
TP_CPU_RSVD_F4

TP_CPU_RSVD_V2
TP_CPU_RSVD_Y2
TP_CPU_RSVD_AG5

CPU_TEST1

FSB_D_L<19>

FSB_D_L<18>

CPU_FERR_L

FSB_D_L<11>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<17>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<0>

FSB_D_L<10>

FSB_D_L<2>

FSB_DSTB_L_N<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<1>

FSB_D_L<0>

CPU_COMP<1>

CPU_BSEL<2>

FSB_D_L<27>

FSB_D_L<29>

FSB_D_L<8>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

FSB_D_L<28>

FSB_D_L<14>
FSB_D_L<15>

FSB_D_L<9>

FSB_REQ_L<2>

CPU_A20M_L

FSB_A_L<34>

FSB_ADSTB_L<1>

CPU_IGNNE_L

FSB_REQ_L<1>

CPU_STPCLK_L

FSB_A_L<17>

FSB_A_L<12>

FSB_ADSTB_L<0>

FSB_A_L<27>

FSB_A_L<32>
FSB_A_L<33>

FSB_A_L<11>

FSB_A_L<28>

CPU_NMI
CPU_SMI_L

FSB_A_L<4>

FSB_A_L<15>
FSB_A_L<16>

FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>

FSB_A_L<29>
FSB_A_L<30>

FSB_A_L<35>

FSB_A_L<13>

FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<14>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<22>

FSB_DINV_L<0>

FSB_D_L<16>

CPU_COMP<3>

CPU_COMP<2>

FSB_A_L<10>

FSB_REQ_L<0>

FSB_A_L<3>

CPU_BSEL<1>

CPU_TEST2

CPU_BSEL<0>

=PP1V05_S0_CPU

XDP_TDO

XDP_TDI

TP_CPU_RSVD_AL5

CPU_GTLREF

FSB_RS_L<0>

FSB_LOCK_L

CPU_TEST4

FSB_HITM_L

FSB_HIT_L

XDP_BPM_L<3>

XDP_TRST_L

CPU_THERMD_P

XDP_TMS

XDP_TRST_L

XDP_TCK

FSB_A_L<18>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<24>

FSB_A_L<31>

TP_CPU_RSVD_H8

XDP_DBRESET_L

CPU_TEST4

CPU_TEST1
CPU_TEST2

TP_CPU_TEST5
TP_CPU_TEST6

TP_CPU_TEST3

10 OF 110

3.3.0

051-8467

10 OF 74

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1

2

1 2

1 2

1 2

1 2

1

2

2

1

1 2

T4

M2

AY8

J7

N5

J1

AA1

AB2

AE5

U1

AN1
AK4

AV2

B40

L5

J5V4

AV8

C5

D40

AE41

AC1

C7

P2

AJ1
AL1
AM2

AP2
AR1

W1

AB4

Y4

AN5

C35

BA5
AY2

D4

H2
F2

F10

C9

J9
F4
H8
V2
Y2
AG5
AL5

E37

C43

AY10
AC43

D38

R1
R5

P4
W5

E5

AV4

AU1

B10

BB34
BD34

AW5

AV10

BA7

K4

H4

K2

G5

F38

M4

AG1
AT4
AK2

AH2

AT2

AF4
AJ5
AH4
AM4
AP4
AR5

AU5

F8

AA5

AD4

AD2

A35

AW7

L1

N1

D8

AC5

T2

T40

E41

G39

H44

H40

J43

V40

P44

P40

J41

K40

N41

E43

D10

E7

BD10

AW43

AY38

AL43

AY40

AK44

U43

C41

B8

G7

BC37

AJ41

AU43

BA35

BB40

BA41

BC39

BC35

AT40

AY36

BB38

BA37

AR41

AW41

AU41

AV40

AT44

AV38

AL41

AN41

AP40

AG43

AK40

AM40

AM44

AH44

AF44

AG41

AJ43

AF40

AH40

AR43

AP44

T44

Y44

AD40

AB40

AA41

U41

N43

W41

R41

G41

M40

G43

F40

AF2

AE1

AD44

AE43

B38

C37

A37

AC41

Y40

L41

R43

W43

AA43

M44
L43

K44

AB44

V44

AN43

66

66

10

66

66

66

10

8

11 12

10 13 66

10 13 66

33 66

10

10 13 66

10 13 66

10 13 66

10

10

10

VCCA

VID

VCC

VCC

VCCP

(3 OF 8)

VSSSENSE

VCCSENSE

VCC VCC

(7 OF 8)

VCCP VCCP

(8 OF 8)

VSS VSS

(6 OF 8)

VSSVSS

(4 OF 8)

VSSVSS

(5 OF 8)

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

18 A (CULV Design Target)

17.6 A (CULV ICC_Max)

4500 mA (before VCC stable)
2500 mA (after VCC stable)

(CPU INTERNAL PLL POWER 1.5V)

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

BGA

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

OMIT_TABLE

U1000

BGA

PENRYN-SFF

CDC-QKWH-QS-1.2-10W-800-R0-1M

OMIT_TABLE

U1000

54 66

PLACE_NEAR=U1000.BD12:25.4 mm

100

1%
1/20W
MF
201

R1100

PLACE_NEAR=U1000.BC13:25.4 mm

100

1%
1/20W
MF
201

R1101

54 66

12 54 66

12 54 66

12 54 66

12 54 66

12 54 66

12 54 66

12 54 66

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

CPU Power & Ground

=PPVCORE_S0_CPU

CPU_VID<1>
CPU_VID<2>

CPU_VID<6>

CPU_VID<5>

CPU_VID<3>

=PPVCORE_S0_CPU

CPU_VID<4>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0>

11 OF 110

3.3.0

051-8467

11 OF 74

T32
R33
P32

AP32

AR33

AE33

N33

H32

AT30

AT28

AM30

AM26

AP26

AF30

F32

AF32

AT34

F28

T26

AD28

AH28

AV26

B34

D34

N37

L37

AK38

BD8

BC7

BB10

BB8

BC5

M32

K32

V32
U33

AC33
AB32
AA33

Y32

AH32

AL33

AV32
AU33
AT32

BD32
BB32

B26
B30
B28
H26
F26
D26
H28
H30

F30
D30
D28
M26
K26
M28
M30
K28
K30
V26

P26
V28
V30
T28
T30
P28

P30
AD26
AB26

Y26

AB30
Y28
Y30
AK26
AH26
AF26
AK28
AK30

AH30
AF28

AP28
AP30
AM28

AY26

AT26
AY28

AV28
AV30

BB26
BD28

K38
J37
W37
V38

R37
P38
AC37
AB38
AA37

AG37
AF38

AJ37

U37

BD26

AY30

AN33
AM32

AK32
AJ33

AG33

W33

J33

AD32

L33

G33

BB4
AY4

BD12

BC13

AB28

AD30

AY32

BB14

BD14

AP14

BB18

BB16

K16
K18

D24

AF24

AF22

AH24

AK24

BB28

BD30

T22
T24

M18

AH22

AY20

BB30

B24
B22
H22
H24
F22

D22

K22

AD22
AD24

AB24

Y22
Y24

AK22

M22
M24

AB22

AP22
AP24
AM22
AM24
AY22
AY24
AV22
AV24
AT22
AT24
BD22
BD24
BB22
BB24

B20
B18
B16
H20
F20
D20
H16
H18
F16
F18
D18
D16
M20

K20
M16

T20
P20
V16
V18
T16
T18
P16
P18
AD20
AB20
Y20
AD16
AD18
AB16
AB18
Y16
Y18
AK20
AK16
AK18
AH20
AF20
AH16
AH18
AF16
AF18
AP20
AM20
AP16
AP18
AM16
AM18

AV20
AT20
AY16
AY18
AV16
AV18
AT16
AT18
BD20
BB20
BD16
BD18

AM14
AY14
AV14
AT14

V20

K24
V22
V24

P22
P24

F24

AC11

K36

G35

H36

F34

AK14
AJ11

AN37

B12

B14

AN35

AE35

AJ35

AK36

AC35

U35

V36

W35

J35

N35

AE37

L35

P36

AB36

AA35

AF36

AG35

AP36

AL35

C13

H12
H14
G11

F12
F14
E11
E13
D14
D12
K10
N11
N13
M14

L13
K12
K14
J11
J13
V10
P10
W11
W13
V12

U11
U13
T14
R11

R13
P12
P14
AB10
AD14

AB12
AB14
AA11
AA13
Y14
AK10
AF10
AK12

AH14
AG11
AG13
AF12
AF14
AE11
AE13
AP10
AR11
AR13

AN11
AN13
AL11
AL13
AU11
AU13
N7
N9
L7
L9

W9
U7
U9
R7
R9
AC7
AC9
AA7
AA9
AJ7

AE7
AE9
AR7
AR9
AN7
AN9
AL7
AL9
A33
A13

AG7
AG9

G13

L11

V14

AC13

AJ13

AP12

W7

AJ9

C33

E33

R35

E35
D32

F36

B32

AL37

AP38

AK6

AF6

AP6

AT8

AT6

AU9

AV6

AU7

AW9

AY6

AM8

AF8

AH8

Y8

AL3

AU3

A7

A5

A9

A11

A15

A19

A17

A25

A23

A21

A29

A27

A31

A41

A39

BA1

AW1

E1

G1

BA3

BB2

BC3

BD4

AW3

AN3

AR3

AE3

AA3

AC3

R3

U3

W3

J3

L3

N3

D2

E3

G3

B4

C3

BA9

BB6

BC9

BD6

AP8

AH6

Y6

AK8

AM6

AJ3
AG3

AW35

G25

G23

G21

C25
C23
C21

BA29

BA27

BA31
BC27
BC29

BC31

AU29

AU27

AW27
AW29

AW31
AU31

AL29

AN29
AL27

AN31
AL31
AN27

AR27
AR29

AE27
AE29
AR31

AG27
AG29

AE31
AJ27
AJ29

AJ31
AG31

AA29

AC29
AA27

AC27

AA31

AC31

R27
R29

R31
U27
U29

U31

W29

J29
W31
W27

J27

L29

N27
N29
L27

L31
J31

N31

E27
E29

G29

G27

E31

C27
G31

BA33
C31
C29

BB36
BC33

AV34
AU35
BD36

AW33

AY34

AV36

AP34
AM34

AB42

AR37

AE39

AG39

AH38

Y38

AA39

P42

AD42

Y42
AK42
AH42
AF42

AM42
AY42

B42

AM36

AR35

AH34

AH36

AK34

Y34

AB34

AD34

AF34

Y36

AD36

P34

T34

V34

T36

K34

M34

M36

H34

D36

B36

BA39

BC41

BD40

BD38

AT38

AU39

AU37

AW39

AW37

AL39

AM38

AN39

AR39

AJ39

AC39

R39

T38

W39

J39

L39

M38

N39

E39

G37

H38

C39

BA43

BB42

AY44

AV44

AT42

AV42

V42

M42

F44

D44

K42

T42

AP42

H42

D42

F42

U39

AD38

AT36

N21
N23

W25

J23

AN25

AN23

AN21

AR25

AR23

L21
L23

M10

E15

G15

C11

C15

BA17

BC17

AU19

AU17

AW19

AW17

AE17

L15

AB8

AB6

AD8

AD6

P8

P6

T8

T6

V8

V6

U5

K8

K6

M8

M6

D6

E9

F6

G9

H6

B6

BA13

BA11

BB12

BC11

BA15

BC15

AT12

AV12

AW13

AW11

AY12

AU15

AW15

AT10

AM12

AL15

AN15

AR15

AM10

AH12

AE15

AG15

AJ15

AH10

Y12

AD12

AA15

AC15

Y10

AD10

T12

R15

U15

W15

T10

M12

J15

N15

H10

BA19

BC19

AG19

U17

G19

G17

AU21

AA25

U21

AR19

AG17

AJ19

AJ17

AA19

AA17

AC19

AC17

R19

R17

U19

W19

W17

J19

J17

L19

L17

N19

N17

E19

E17

C17

C19

BA25

BA23

BA21

BC25

BC23

BC21

AU25

AU23

AW25

AL25

AL23

AL21

AE21

AG25

AJ21

AA23

AA21

AC25

AC23

AC21

R25

R23

R21

U25

U23

W23

W21

J25

J21

L25

E21

AR17

N25

AL19

AL17

AN19

AN17

AE19

E25

E23

AW23

AW21

AG23

AG21

AJ25

AJ23

AE23
AE25
AR21

1

2

1

2

8

11 12 65

8

11 12 65

8

12

8

10 11 12

8

10 11 12

IN

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LAYOUT NOTE:

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

PLACE ON OPPOSITE SIDE OF CPU

CPU VCORE VID CONNECTIONS

VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE:

PLACE C1281 NEAR PIN B34 OF U1000

PLACE C1291-C1296 CLOSE TO FSB DATA PINS

PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS

PLACE C1290 CLOSE TO CPU

1x 270uF, 12x 2.2uF

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

LAYOUT NOTE:

4x 270uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402

CPU VCORE HF AND BULK DECOUPLING

PLACE ON SAME SIDE AS CPU

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

LAYOUT NOTE:

10UF

603

X5R

6.3V

20% 20%

6.3V
X5R
603

10UF

CRITICAL

C1216

10UF

603

X5R

6.3V

20%

CRITICAL

C1201

20%

6.3V
X5R
603

10UF

C1202

10UF

603

X5R

6.3V

20%

C1203

20%

6.3V
X5R
603

10UF

CRITICAL

C1204

10UF

603

X5R

6.3V

20%

CRITICAL

C1205

20%

6.3V
X5R
603

10UF

CRITICAL

C1206

10UF

603

X5R

6.3V

20%

CRITICAL

C1207

20%

6.3V
X5R
603

10UF

CRITICAL

C1208

20%

6.3V
X5R
603

10UF

CRITICAL

C1209

10UF

603

X5R

6.3V

20%

CRITICAL

C1229

20%

6.3V
X5R
603

10UF

CRITICAL

C1228

10UF

603

X5R

6.3V

20%

CRITICAL

C1227

20%

6.3V
X5R
603

10UF

CRITICAL
OMIT_TABLE

C1226

10UF

603

X5R

6.3V

20%

CRITICAL

C1225

20%

6.3V
X5R
603

10UF

CRITICAL

C1224

10UF

603

X5R

CRITICAL

C1223

20%

6.3V
X5R
603

10UF

CRITICAL
OMIT_TABLE

C1214

20%

6.3V
X5R
603

10UF10UF

X5R

6.3V

20%

10UF

603

X5R

6.3V

20%

CRITICAL

C1220

CRITICAL

603

X5R

6.3V

20%

C1231

10UF

603

X5R

6.3V

20%

OMIT_TABLE

CRITICAL

C1230

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1249

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1259

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1248

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1258

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1246

402-LF

CERM

6.3V

20%20%

6.3V
CERM
402-LF

2.2UF

CRITICAL

C1256

2.2UF

402-LF

CERM

20%

CRITICAL
OMIT_TABLE

C1245

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1244

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1255

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1254

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1243

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1253

20%

6.3V
CERM

2.2UF

CRITICAL
OMIT_TABLE

C1242

2.2UF

402-LF

CERM

20%

CRITICAL
OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1252

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1251

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1250

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL

C1267

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1266

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1265

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1264

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1263

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1262

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1261

2.2UF

402-LF

6.3V

20%

CRITICAL

C1260

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1291

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1292

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1293

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1294

20%

6.3V
CERM
402-LF

2.2UF

OMIT_TABLE

C1295

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1296

OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

C1283

20%

6.3V
CERM
402-LF

2.2UF

OMIT_TABLE

C1288

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1287

20%

6.3V
CERM
402-LF

2.2UF

OMIT_TABLE

C1286

OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

C1285

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1284

CRITICAL
270UF

TANT
CASE-B4-SM

20%
2V

CRITICAL

270UF

TANT
CASE-B4-SM

20%
2V

C1272

CRITICAL

2V

20%
TANT

270UF

C1271

CRITICAL

270UF

TANT

CASE-B4-SM

20%

2V

C1290

CRITICAL

270UF

TANT
CASE-B4-SM

20%
2V

11 54 66 66

10UF

603

X5R

6.3V

20%

CRITICAL

C1213

20%

6.3V
X5R
603

10UF

CRITICAL

C1212

10UF

603

X5R

6.3V

20%

CRITICAL

C1211

10UF

603

X5R

6.3V

20%

CRITICAL

C1219

603

6.3V

CRITICAL

10UF

603

X5R

6.3V

20%

CRITICAL

C1215

X5R

20%

CRITICAL
OMIT_TABLE

C1217

20%

6.3V
X5R
603

10UF

CRITICAL
OMIT_TABLE

C1218

10%
10V
X5R
201

0.01UF

C1281

OMIT_TABLE

20%

6.3V
X5R
603

10uF

C1280

SYNC_DATE=(02/11/2010)

SYNC_MASTER=(K99_MLB)

CPU Decoupling & VID

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

IMVP6_VID<0..6>

CPU_VID<0..6>

MAKE_BASE=TRUE

C1247

C1222

CRITICAL

C1210

C1257

OMIT_TABLE

CRITICAL

6.3V

C1221

CRITICAL

CRITICAL CRITICAL

C1200

10UF

20%
X5R

10UF

603

C1273

10UF

6.3V
603

C1240

6.3V
402-LF

OMIT_TABLE

2.2UF

OMIT_TABLE

CERM

OMIT_TABLE

C1270

CASE-B4-SM

OMIT_TABLE

CRITICAL

20%

6.3V

C1241

2.2UF

NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF

NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF

NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF

NO STUFF

OMIT_TABLE OMIT_TABLE

CRITICAL

12 OF 110

3.3.0

051-8467

12 OF 74

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

8

11

8

10 11

8

11 65

IN

BI

BI

BI
BI

OUT

IN

BI

IN

IN
IN

IN
IN

OUT
OUT
OUT

OUT

NC

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OBSDATA_B3 OBSDATA_D3

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TDI

OBSDATA_A3

SCL

VCC_OBS_AB

OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSDATA_A2

OBSFN_B0

PWRGD/HOOK0

HOOK3

SDA

OBSDATA_A0

518S0774

OBSFN_C1

NOTE: This is not the standard XDP pinout.

OBSDATA_B2

OBSDATA_A1

Direction of XDP adapter flex

Please place J1300 within 1" of
board edge with odd-numbered pins
facing edge. Avoid any tall
components between J1300 and edge.

TCK0

HOOK1

HOOK2

OBSDATA_C0

OBSFN_C0

OBSFN_D1

OBSDATA_D1

ITPCLK/HOOK4

VCC_OBS_CD

ITPCLK#/HOOK5

TMS

Use with 920-0782 Adapter Flex to support chipset debug.

TRSTn

TCK1

RESET#/HOOK6

OBSDATA_C3

TDO

OBSDATA_C1

OBSDATA_C2

OBSDATA_D0

OBSDATA_D2

OBSFN_A1

OBSFN_A0

XDP_PRESENT#

DBR#/HOOK7

OBSFN_D0

Micro2-XDP Connector

10 14 66

1K

XDP

1/20W

MF

201

5%

R1399

42

42

1%

XDP

54.9

201

1/20W

MF

R1315

XDP

10%
X5R

0.1UF

201

6.3V

C1300

201

6.3V

0.1UF

XDP

X5R

10%

C1301

10 66

10 66

10 66

10 14 66

PLACEMENT_NOTE=Place close to CPU to minimize stub.

5%

1K

XDP

1/20W

MF

201

R1303

10 66

10 66

10 66

10 66

14 66

14 66

10 66

10 66

10 66

10 25

19

10 66

19

F-ST-SM-HF

XDP_CONN
CRITICAL

DF40C-60DS-0.4V

J1300

eXtended Debug Port (Micro-XDP)

SYNC_DATE=03/01/2010

SYNC_MASTER=K99_MLB

=I2C_XDP_SCL

=I2C_XDP_SDA

CPU_PWRGD XDP_PWRGD

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_TCK

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2

XDP_BPM_L<3>
XDP_BPM_L<2>

XDP_BPM_L<1>
XDP_BPM_L<0>

TP_XDP_OBSDATA_D3

TP_XDP_OBSDATA_D2

TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D0

TP_XDP_OBSDATA_C3

TP_XDP_OBSDATA_C2

TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C0

JTAG_MCP_TDO

XDP_TRST_L

JTAG_MCP_TMS

TP_XDP_OBSDATA_B3

TP_XDP_OBSFN_B1

XDP_OBS20

=PP1V05_S0_XDP

XDP_BPM_L<5>
XDP_BPM_L<4>

TP_XDP_OBSDATA_B0

TP_XDP_OBSFN_B0

FSB_CPURST_L

FSB_CLK_ITP_P

XDP_TMS

XDP_TDI

XDP_TDO

XDP_DBRESET_L

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TDI

JTAG_MCP_TRST_L

=PP3V3_S0_XDP

13 OF 110

3.3.0

051-8467

13 OF 74

1 2

1

2

2

1

2

1

1 2

3

1

7

5

11

9

13

17

15

23

19
21

25
27
29

33

31

35

39

37

41
43
45
47
49
51
53

59

57

55

38
40

36

32
34

30

28

26

24

22

16
18
20

10

14

12

6
8

2
4

56
58
60

54

52

50

48

46

44

42

19

19

8

66

19

19

8

IN
IN
IN

IN

OUT

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

IN
BI

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT
OUT

IN

BI
BI

OUT

IN

IN

IN

IN

IN

IN

IN

CPU_A8*

CPU_DSTBN0*

CPU_DSTBP1*

CPU_D6*

CPU_D3*

CPU_D5*

CPU_D2*

CPU_D1*

CPU_DSTBP2*
CPU_DSTBN2*
CPU_DBI2*

CPU_D4*

CPU_DBI0*

CPU_DSTBP0*

CPU_DSTBN1*
CPU_DBI1*

CPU_DSTBP3*
CPU_DSTBN3*
CPU_DBI3*

CPU_A4*
CPU_A5*

CPU_A7*

CPU_A6*

CPU_A9*
CPU_A10*
CPU_A11*
CPU_A12*

CPU_A14*
CPU_A15*
CPU_A16*
CPU_A17*
CPU_A18*
CPU_A19*

CPU_A22*

CPU_A25*

CPU_A24*

CPU_A23*

CPU_A26*
CPU_A27*
CPU_A28*
CPU_A29*
CPU_A30*

CPU_A33*

CPU_A32*

CPU_A31*

CPU_A34*
CPU_A35*

CPU_A3*

CPU_ADSTB0*
CPU_ADSTB1*

CPU_REQ1*

CPU_REQ0*

CPU_REQ2*
CPU_REQ3*
CPU_REQ4*

CPU_ADS*
CPU_BNR*

CPU_DBSY*

CPU_BR0*

CPU_HITM*

CPU_HIT*

CPU_DRDY*

CPU_TRDY*

CPU_LOCK*

CPU_PROCHOT*
CPU_THERMTRIP*
CPU_FERR*

CPU_BSEL0

CPU_RS0*
CPU_RS1*
CPU_RS2*

BCLK_VML_COMP_GND

BCLK_VML_COMP_VDD

CPU_PECI

CPU_BSEL2
CPU_BSEL1

CPU_COMP_VCC
CPU_COMP_GND

CPU_D16*

CPU_D0*

CPU_D54*

CPU_D60*
CPU_D61*

CPU_D40*

CPU_D27*

CPU_D26*

CPU_D25*

CPU_D24*

CPU_D22*

CPU_D20*
CPU_D21*

CPU_D7*
CPU_D8*

CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*

CPU_D17*
CPU_D18*
CPU_D19*

CPU_D23*

CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*

CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*

CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*

BCLK_IN_P

BCLK_OUT_ITP_P

CPU_DEFER*

CPU_BPRI*

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

BCLK_OUT_ITP_N

BCLK_OUT_NB_P
BCLK_OUT_NB_N

BCLK_IN_N

CPU_IGNNE*

CPU_A20M*

CPU_INIT*

CPU_INTR

CPU_NMI
CPU_SMI*

CPU_DPRSLPVR

CPU_DPRSTP*

CPU_STPCLK*

CPU_DPSLP*

CPU_DPWR*

CPU_SLP*

CPU_RESET*

CPU_PWRGD

CPU_A21*

CPU_D63*

CPU_D62*

CPU_A20*

CPU_A13*

SYMBOL 1 OF 11

FSB

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Loop-back clock for delay matching.

9

9

9

10 66

10 13 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

10 66

10 66

10 66

10 66

10 66

10 66

13 66

13 66

10 66

10 66

10 66

10 66

10 66

10 66

10 66

10 66

10 13 66

10 66

10 66

10 66

10 66

10 54 66

9

10 40 66

10 40 66

7

10 66

7

10 66

49.9

MF

1/20W
201

1%

R1436

MF

1/20W

201

1%

49.9

R1431

MF

1/20W

201

49.9

1%

R1430

MF

1/20W
201

49.9

1%

R1435

MF

1/20W
201

62

5%

R1415

MF

1/20W

201

54.9

1%

R1410

MF

1/20W
201

150

NO STUFF

5%

R1440

54 66

7

10 66

7

10 66

10 66

10 66

10 66

10 66

7

10 66

BGA

MCP89U-A01

OMIT_TABLE

U1400

SYNC_MASTER=K99_MLB

MCP CPU Interface

SYNC_DATE=04/08/2010

FSB_A_L<17>

FSB_D_L<31>

FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>

FSB_A_L<25>

FSB_A_L<27>

FSB_A_L<24>

FSB_A_L<33>

FSB_DBSY_L

CPU_FERR_L

FSB_D_L<61>

FSB_D_L<37>

FSB_CPURST_L

CPU_SMI_L

CPU_IGNNE_L

FSB_D_L<45>

FSB_D_L<48>

FSB_D_L<51>

FSB_BPRI_L

FSB_A_L<34>

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_CLK_ITP_P

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<56>

FSB_D_L<49>

FSB_D_L<42>

FSB_D_L<40>

FSB_DINV_L<0>
FSB_DSTB_L_P<1>

FSB_D_L<6>

FSB_D_L<3>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_DSTB_L_N<2>

FSB_D_L<4>

FSB_DSTB_L_N<1>

FSB_A_L<15>
FSB_A_L<16>

FSB_A_L<19>

FSB_A_L<26>

FSB_A_L<28>

FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_ADS_L

FSB_HITM_L

FSB_HIT_L

FSB_DRDY_L

FSB_TRDY_L

FSB_LOCK_L

CPU_PROCHOT_L

PM_THRMTRIP_L

=MCP_BSEL<0>

FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>

MCP_BCLK_VML_COMP_VDD

CPU_PECI_MCP

=MCP_BSEL<2>
=MCP_BSEL<1>

FSB_D_L<16>

FSB_D_L<0>

FSB_D_L<54>

FSB_D_L<60>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<22>

FSB_D_L<20>
FSB_D_L<21>

FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>

FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>

FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>

FSB_D_L<23>

FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>

FSB_D_L<43>
FSB_D_L<44>

FSB_D_L<46>
FSB_D_L<47>

FSB_D_L<50>

FSB_D_L<53>

FSB_D_L<55>

FSB_D_L<57>

CPU_INIT_L
CPU_INTR
CPU_NMI

PM_DPRSLPVR

CPU_STPCLK_L

CPU_DPSLP_L
FSB_DPWR_L

FSB_D_L<63>

FSB_D_L<62>

=PP1V05_S0_MCP_FSB

=PP1V05_S0_MCP_FSB

FSB_D_L<41>

FSB_D_L<39>

FSB_D_L<38>

FSB_BNR_L

CPU_DPRSTP_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_BREQ0_L

FSB_REQ_L<0>

FSB_A_L<35>

FSB_REQ_L<1>

FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>

FSB_ADSTB_L<1>

FSB_A_L<32>

FSB_ADSTB_L<0>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

FSB_CLK_ITP_N

FSB_D_L<52>

CPU_A20M_L

FSB_DEFER_L

FSB_CLK_MCP_P
FSB_CLK_MCP_N

FSB_DINV_L<3>

FSB_A_L<3>

FSB_D_L<12>

FSB_DINV_L<1>

FSB_A_L<4>

FSB_A_L<18>

FSB_A_L<14>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<10>
FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

14 OF 110

3.3.0

051-8467

14 OF 74

121

2

121

2

1

2

1

2

1

2

Y40

J39

R34

M40

L38

L40

P39

M39

J37
J36
L35

L39

F39

J38

R35
U36

C37
C38
B35

V37
Y36

Y39

V40

V39
AA39
AA36
AA37

AC36
AA40
AA38
AF39
AD38
AC38

AJ39

AD40

AC37

AC40

AC39
AF36
AF40
AG39
AD39

AJ40

AF37

AD36

AG40
AG38

U38

Y37
AF38

U39

U40

V38

U37

V36

AG33
AD35

AF35

AG34

AD32

AD34

U32

AG32

AG37

V32

V35
AC33

F35

AF33
AD33
AF34

AK40

AK39

AG36

D35

E35

AK38
AK37

U35

M37

A37

B37
D36

J34

P36

P38

P37

P34

U34

R38
R33

P40
H40
L37
F38
F40
H38
M38
H39
J40

R36
R37
P35

R40

P33
P32
R32
R39
H36
F36
L33
M35
L34
M33
M36
M32

H35
H34
L36
M34
F37
H37
J35
D39
E36
D40
E40
C39
E38

C36
B38
E37
C35
A35

AJ33

AK32

AG35

AF32

AJ37
AJ36

AK33
AJ35

AJ34

AJ32

V33

AA33

Y33
Y35
AA35
AC35

D2

AA34

Y34

Y32
U33

V34

AC34

AA32

AD37

D38

A36

AJ38

Y38

66

8

14 20 23

8

14 20 23

66

66

66

66

66

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI

BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT

BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

MCKE0A_0

MCKE0A_1

MCS0A_0*

MCS0A_1*

+VIO_PLL_CPU

+VIO_PLL_CPU

+VIO_PLL_CPU

+VIO_PLL_FSB

+VIO_PLL_FSB

+VIO_PLL_FSB

+VIO_PLL_MEM
+VIO_PLL_MEM

+VIO_M2CLK_DLL

+VIO_M2CLK_DLL

+VIO_M2CLK_DLL

MA0_0

MA0_8

MA0_9

MA0_10

MCAS0*

MBA0_0

MA0_15
MA0_14

MBA0_2
MBA0_1

MWE0*

MRAS0*

MDQS0_0_N

MDQS0_0_P

MDQS0_1_N

MDQS0_1_P

MDQS0_2_N

MDQS0_2_P

+VIO_PLL_MEM

MCLK0A_1_P
MCLK0A_1_N

MODT0A_1
MODT0A_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_7

MA0_11

MA0_12

MA0_13

MDQS0_3_N

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_4_P

MDQS0_7_N

MDQS0_7_P

MDQS0_6_P

MDQM0_5

MDQM0_6

MDQM0_7

MDQ0_60

MDQ0_55

MDQ0_56

MDQ0_52
MDQ0_51

MDQ0_15

MDQ0_48

MDQ0_40
MDQ0_39

MDQM0_2

MDQM0_3

MDQM0_1
MDQM0_0

MDQM0_4

MDQ0_0

MDQ0_1

MDQ0_2

MDQ0_3

MDQ0_4

MDQ0_5

MDQ0_6

MDQ0_10
MDQ0_9

MDQ0_7

MDQ0_8

MDQ0_11

MDQ0_14
MDQ0_13
MDQ0_12

MDQ0_16

MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17

MDQ0_26
MDQ0_25

MDQ0_23
MDQ0_22

MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27

MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32

MDQ0_41

MDQ0_38
MDQ0_37

MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42

MDQ0_47

MDQ0_50
MDQ0_49

MDQ0_54
MDQ0_53

MDQ0_57

MDQ0_59
MDQ0_58

MDQ0_24

MDQ0_61

MDQ0_62

MDQ0_63

MDQS0_6_N

MCLK0A_0_N

MCLK0A_0_P

MEMORY PARTITION 0

SYMBOL 2 OF 11

MRESET0*

MDQM1_0

MDQM1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQ1_59

MDQ1_61
MDQ1_60

MDQS1_1_P
MDQS1_1_N
MDQS1_0_P

MRAS1*

MDQ1_47

MDQ1_43

MDQ1_58

MDQS1_0_N

MDQS1_2_P

MDQS1_3_N

MDQ1_0

MDQ1_3
MDQ1_2
MDQ1_1

MDQ1_11

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_16

MDQ1_17

MDQ1_18

MDQ1_19

MDQ1_20

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_25

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_30

MDQ1_31

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_40

MDQ1_41

MDQ1_42

MDQ1_44

MDQ1_45

MDQ1_46

MDQ1_48

MDQ1_49

MDQ1_50

MDQ1_51

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_55

MDQ1_56

MDQ1_57

MDQ1_62

MDQ1_63

MA1_14

MA1_15

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P

MDQS1_2_N

MDQ1_32

MEM_COMP_GND
MEM_COMP_VDD

MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

MDQ1_4

MDQ1_5

MDQ1_6

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_10

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MCS1A_0*

MCS1A_1*

MODT1A_0

MODT1A_1

MCKE1A_0

MCKE1A_1

MWE1*

MCAS1*

MBA1_1

MBA1_2

MBA1_0

SYMBOL 3 OF 11

MEMORY PARITION 1

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

550 mA

25 mA

25 mA

20 mA 70 mA

27 67

27 67

27 67

27 67

26 67

26 67

26 67

26 67

26 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

9

67

9

67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

21 26 27 32 67

21 26 27 32 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

28 67

29 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

29 67

28 67

29 67

29 67

29 67

28 67

28 67

28 67

28 67

9

67

9

67

21 28 29 32 67

21 28 29 32 67

9

67

9

67

28 29 32 67

28 29 32 67

26 27 28 29

MF

1/20W
201

1K

5%

R1520

MF

1/20W

201

40.2

1%

R1511

MF

1/20W

201

1%

40.2

R1510

BGA

MCP89U-A01

OMIT_TABLE

U1400

BGA

MCP89U-A01

OMIT_TABLE

U1400

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MCP Memory Interface

MEM_A_CLK_P<1>

PP1V05_S0_MCP_PLL_FSBMEM

MEM_A_CLK_N<1>

MEM_B_DQ<16>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>

MEM_RESET_L

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQ<59>

MEM_B_DQ<61>
MEM_B_DQ<60>

MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>

MEM_B_RAS_L

MEM_B_DQ<47>

MEM_B_DQ<43>

MEM_B_DQ<58>

MEM_B_DQS_N<0>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQ<0>

MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>

MEM_B_DQS_N<2>

MEM_B_DQ<32>

MCP_MEM_COMP_GND
MCP_MEM_COMP_VDD

MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_BA<0>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

=PP1V05_S0_MCP_M2CLK_DLL

MEM_A_A<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_CAS_L

MEM_A_BA<0>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_BA<2>
MEM_A_BA<1>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<60>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<52>
MEM_A_DQ<51>

MEM_A_DQ<15>

MEM_A_DQ<48>

MEM_A_DQ<40>
MEM_A_DQ<39>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<1>
MEM_A_DM<0>

MEM_A_DM<4>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<10>
MEM_A_DQ<9>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<11>

MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>

MEM_A_DQ<16>

MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>

MEM_A_DQ<26>
MEM_A_DQ<25>

MEM_A_DQ<23>
MEM_A_DQ<22>

MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>

MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>

MEM_A_DQ<41>

MEM_A_DQ<38>
MEM_A_DQ<37>

MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>

MEM_A_DQ<47>

MEM_A_DQ<50>
MEM_A_DQ<49>

MEM_A_DQ<54>
MEM_A_DQ<53>

MEM_A_DQ<57>

MEM_A_DQ<59>
MEM_A_DQ<58>

MEM_A_DQ<24>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQS_N<6>

=PP1V5R1V35_SW_MCP_MEM

=PP1V5R1V35_S3_MCP_MEM

15 OF 110

3.3.0

051-8467

15 OF 74

1

2

1

2

1

2

AM26

AM27

AN18

AP15

AG31

AG30

AG29

AF31

AF30

AF29

AH29
AH30

AK31

AK30

AJ30

AR20

AN24

AP24

AP18

AM17

AP17

AN26
AP26

AR26
AR18

AM18

AR17

AN34

AN35

AU36

AV36

AP32

AR32

AJ31

AM21
AN21

AP14
AN17

AP21

AP20

AR21

AN23

AM24

AM23

AR23

AP23

AR24

AR15

AP29

AR29

AR12

AM11

AN11

AT12

AR5

AR4

AT6

AR9

AM9

AN5

AU3

AU5

AT3

AN9
AV3

AU35

AN8

AM12
AP12

AN32

AT29

AT36
AN37

AM14

AM37

AM36

AR37

AR36

AM34

AM35

AN36

AT35
AV37

AR35

AU38

AT33

AV35
AT37
AT38

AN33

AP33
AR33
AP30
AR30
AM33

AP27
AN29

AT30
AT32

AR27
AT27
AM30
AN30
AN27

AR14
AR11
AP11
AM15
AN15

AT9

AN14
AT14

AP9
AN12
AT11

AT8

AR8

AP8

AV4

AM8

AV5

AR6

AT5

AM7

AN7

AM29

AT4

AN4

AN6

AU6

AN20

AM20

AM6

AR38

AW37

AU30

AV27

AY14

AV9

AY6

AR3

AM3

AT1
AU1

AY37
AY36
AN38

AW18

AY9

AW8

AM2

AN39

AV32

AY27

AM40

AT40
AU40
AN40

AV33

AU39

AV39

AY35

AW35

AY32

AU32

AY30

AY29

AW33

AY33

AV30

AW30

AU29

AU27

AV26

AU26

AW29

AV29

AY26

AW26

AY15

AV12

AW12

AU15

AV15

AU14

AU12

AU11

AU9

AY8

AY12

AY11

AW9

AV6

AW6

AV2

AU2

AV8

AU8

AW4

AW3

AR1

AR2

AN1

AM1

AV24

AU24

AN2
AN3
AY5
AY4
AV11
AW11
AV14
AW14
AW27

AW32

AW15

AL23
AL24

AU17
AY24
AW23
AU18
AY23
AU23
AV23
AT21
AT23
AU21
AV21
AY21
AW21
AY20

AM38

AM39

AR39

AR40

AV38

AW38

AU33

AV20
AW20

AT20
AU20

AY17

AT15

AW17

AT17

AT26

AT24

AY18

AV17

AT18

AW24

AV18

23

67

67

8

23

20 21 23

8

IN

IN

IN

IN

IN
IN

IN

IN

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

PEC_CLKREQ*/GPIO_51

PE2_REFCLK_P
PE2_REFCLK_N

PEA_CLKREQ*/GPIO_49

PEB_CLKREQ*/GPIO_50

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE_WAKE*

PE0_TX4_P
PE0_TX4_N

PE0_TX5_P
PE0_TX5_N

PE1_TX0_P
PE1_TX0_N

PE1_TX1_P
PE1_TX1_N

PEX_RST*

PEX0_TERM_P

PE0_RX4_P
PE0_RX4_N

PE0_RX5_N

PE0_RX5_P

PE1_RX0_P
PE1_RX0_N

PE1_RX1_P
PE1_RX1_N

+3.3V_PLL_HVDD

+VIO_PLL_PE

+VIO_PLL_PE

+VIO_PLL_PE

+VIO_PLL_XREF_XS

+VIO_PLL_XREF_XS

+VIO_PLL_XREF_XS

+VIO_PLL_SATA

+VIO_PLL_SATA

+VIO_PLL_SATA

+VIO_PLL_H
+VIO_PLL_H

PCI EXPRESS

SYMBOL 4 OF 11

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1
PE1 ports are Gen1-only. 2 RCs: x1, x1

+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[3:0] are not used,

+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

If PE0[4:5] and PE1[0:1] are not used,

1/20W

MF

201

2.49K

1%

PLACE_NEAR=U1400.U5:12.7 mm

R1610

7

34

34

9

9

9

9

7

34 68

7

34 68 34 68

34 68

25

7

34 68

7

34 68

9

68

9

68

9

9

9

9

9

MF

1/20W
201

5%

22K

R1600

MCP89U-A01

BGA

OMIT_TABLE

U1400

9

MCP PCIe Interfaces

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N

MCP_PEX0_TERMP

PCIE_CLK100M_AP_N

=PEG_R2D_C_N<5>

=PEG_R2D_C_P<5>

PCIE_WAKE_L

PCIE_CLK100M_AP_P

PEG_CLK100M_P

PCIE_RESET_L

TP_PCIE_CLK100M_PE2P
TP_PCIE_CLK100M_PE2N

TP_PCIE_PE1_D2RP

=PEG_D2R_P<4>

=PEG_D2R_P<5>

PP3V3_S0_MCP_PLL_HVDD

PCIE_AP_D2R_P

TP_PCIE_PE1_D2RN

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<4>

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

=PEG_D2R_N<5>

PP1V05_S0_MCP_PLL_PEXSATA

PCIE_AP_D2R_N

=PEG_D2R_N<4>

PEG_CLKREQ_L

AP_CLKREQ_L

ENET_CLKREQ_L

PEG_CLK100M_N

16 OF 110

3.3.0

051-8467

16 OF 74

1

2

1

2

U4

U3
U2

V1

U1

V5
V4

V2
V3

U7

Y3
Y2

AA7
AA6

AA2
AA3

Y8
Y9

U6

U5

Y4
Y5

AA8

AA9

AA4
AA5

Y7
Y6

W10

AG11

AG10

AG12

AH11

AH10

AH12

AE10

AF12

AE11

AF10
AF11

68

23

23

OUT

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI

BI
BI

OUT

OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

IN
IN

IFPA_TXD0_N

IFPA_TXD0_P

DDC_DATA0/GPIO_39

DDC_CLK0/GPIO_38

RGB_DAC_VREF

+3.3V_RGBDAC

IFPA_TXD1_P
IFPA_TXD1_N

DDC_CLK1/GPIO_40

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N

IFPB_TXD5_P
IFPB_TXD5_N

IFPB_TXD6_P
IFPB_TXD6_N

IFPB_TXD7_N

IFPB_TXD7_P

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD2_P
IFPA_TXD2_N

IFPA_TXD3_P
IFPA_TXD3_N

DP1_0_P/TMDS0_TX5_P
DP1_0_N/TMDS0_TX5_N

DP1_1_N/TMDS0_TX4_N

DP1_2_N/TMDS0_TX3_N

DP1_1_P/TMDS0_TX4_P

DP0_3_P/TMDS0_TXC_P

DDC_DATA1/GPIO_41

DP1_2_P/TMDS0_TX3_P

DP1_3_N/TMDS0B_TXC_N

DP1_3_P/TMDS0B_TXC_P

DP0_0_N/TMDS0_TX2_N

DP0_0_P/TMDS0_TX2_P

DP0_1_N/TMDS0_TX1_N

DP0_1_P/TMDS0_TX1_P

DP0_2_N/TMDS0_TX0_N

DP0_2_P/TMDS0_TX0_P

DP0_3_N/TMDS0_TXC_N

HPLUG_DET0/GPIO_20
HPLUG_DET1/GPIO_21
HPLUG_DET2/GPIO_22

DDC_DATA2/DP_AUX_CH0_N

DDC_CLK2/DP_AUX_CH0_P

DDC_DATA3/DP_AUX_CH1_N

DDC_CLK3/DP_AUX_CH1_P

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

LCD_PANEL_PWR/GPIO_58

IFPAB_VPROBE

IFPAB_RSET

TMDS0_VPROBE

TMDS0_RSET

+3.3V_PLL_DP0
+3.3V_PLL_DP0

+3.3V_PLL_USB

+3.3V_PLL_USB

+VIO_PLL_IFPAB
+VIO_PLL_IFPAB

+VIO_PLL_CORE_LEG
+VIO_PLL_CORE_LEG

+VIO_PLL_SPPLL0

+VIO_PLL_V

+VIO_PLL_SPPLL0

+VIO_PLL_V

+VIO_PLL_NV
+VIO_PLL_NV

+VDD_IFPA
+VDD_IFPB

+VIO_DP0

+VIO_DP0

+VIO_DP0

FLAT PANEL

RGB

SYMBOL 5 OF 11

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

=MCP_IFPB_TXD_P/N<0>

=MCP_IFPAB_DDC_CLK

GPIO Pull-Ups

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

NOTE: DP_AUX_CH1 also requires pull-downs if used for
dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then

210 mA

Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).

NOTE: No Composite/S-Video/Component Video support on MCP89

TMDS/HDMI
TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>

LVDS_IG_A_CLK_P/N

LVDS

Interface Mode

LVDS_IG_A_DATA_P/N<0>
LVDS_IG_A_DATA_P/N<1>

60 mA

40 mA

160 mA

140 mA

180 mA

30 mA

180 mA

(GMUX_INT)

LVDS_IG_A_DATA_P/N<2>
LVDS_IG_A_DATA_P/N<3>
LVDS_IG_B_CLK_P/N
LVDS_IG_B_DATA_P/N<0>
LVDS_IG_B_DATA_P/N<1>
LVDS_IG_B_DATA_P/N<2>
LVDS_IG_B_DATA_P/N<3>

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<5>

TMDS_IG_DDC_DATA

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<4>

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<3>

RGB DAC Disable:

Connect +3.3V_RGBDAC pin to GND.

(UNUSED)

(UNUSED)
(UNUSED)

LVDS: Power +VDD_IFPx at 1.8V

=MCP_IFPA_TXD_P/N<3>

=MCP_IFPA_TXD_P/N<2>

=MCP_IFPA_TXD_P/N<1>

=MCP_IFPA_TXD_P/N<0>

TMDS: Power +VDD_IFPx at 3.3V

=MCP_IFPB_TXD_P/N<1>
=MCP_IFPB_TXD_P/N<2>
=MCP_IFPB_TXD_P/N<3>

=MCP_IFPAB_DDC_DATA

=MCP_IFPA_TXC_P/N

=MCP_IFPB_TXC_P/N

MCP Signal

only pull-ups are necessary.

DDC Mode Pull-downs

160 mA

60 mA

20 mA

NOTE: 100K pull-downs required if
HPLUG_DET0/HPLUG_DET1 are not used.

40 mA

17

9

9

9

17 68

9

68

9

68

9

68

9

68

9

68

9

68

9

68

9

68

24 68

24 68

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

60

24 68

24 68

9

9

9

9

9

68

9

68

9

68

9

68

9

17 68

9

17 68

9

17 68

9

9

9

9

9

9

9

9

9

9

7

17 37

17

10K

5%

1/20W

MF 201

R1782

10K

5%

1/20W

MF 201

R1781

10K

5%

1/20W

MF 201

R1780

5%

100K

1/20W

MF 201

R1711

5%

100K

1/20W

MF 201

R1710

CKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2Gnd

BGA

MCP89U-A01

OMIT_TABLE

U1400

5%

100K

1/20W

MF 201

R1712

5%

100K

1/20W

MF 201

R1713

MCP Graphics

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MIKEY_MIC_LOAD_DET

AUD_IP_PERIPHERAL_DET

SATARDRVR_A_EN

=PP3V3_S0_MCP_GPIO

MIKEY_MIC_LOAD_DET

AUD_IP_PERIPHERAL_DET

DP_IG_AUX_CH1_N

=PP3V3R1V8_S0_MCP_IFP_VDD

DP_IG_ML0_N<1>

DP_IG_ML0_P<2>
DP_IG_ML0_N<2>

DP_IG_ML0_N<3>

DP_IG_ML0_P<3>

PP3V3_S0_MCP_DAC

TP_MCP_RGB_DAC_VREF

DP_IG_ML0_P<1>

DP_IG_ML0_P<0>
DP_IG_ML0_N<0>

DP_IG_ML1_P<3>
DP_IG_ML1_N<3>

DP_IG_ML1_P<2>
DP_IG_ML1_N<2>

DP_IG_ML1_N<1>

DP_IG_ML1_P<1>

DP_IG_ML1_P<0>
DP_IG_ML1_N<0>

DP_IG_HPD0
DP_IG_HPD1
SATARDRVR_A_EN

DP_IG_AUX_CH0_N

DP_IG_AUX_CH0_P

=PP1V05_S0_MCP_DP0_VDD

=MCP_IFPA_TXC_P
=MCP_IFPA_TXC_N

=MCP_IFPA_TXD_P<0>
=MCP_IFPA_TXD_N<0>

=MCP_IFPA_TXD_P<1>
=MCP_IFPA_TXD_N<1>

=MCP_IFPA_TXD_P<2>
=MCP_IFPA_TXD_N<2>

=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<3>

=MCP_IFPB_TXC_N

=MCP_IFPB_TXC_P

=MCP_IFPB_TXD_P<0>
=MCP_IFPB_TXD_N<0>

=MCP_IFPB_TXD_P<1>
=MCP_IFPB_TXD_N<1>

=MCP_IFPB_TXD_P<2>

=MCP_IFPB_TXD_N<3>

=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

LCD_IG_BKLT_PWM
LCD_IG_BKLT_EN
LCD_IG_PWR_EN

MCP_IFPAB_VPROBE
MCP_IFPAB_RSET

MCP_TMDS0_VPROBE
MCP_TMDS0_RSET

DP_IG_AUX_CH1_P

DP_IG_AUX_CH0_N

DP_IG_AUX_CH0_P

=MCP_IFPB_TXD_P<3>

=MCP_IFPB_TXD_N<2>

=PP1V05_S0_MCP_PLL_IFP

PP1V05_S0_MCP_PLL_CORE

DP_IG_AUX_CH1_N
PP3V3_S0_MCP_PLL_DP_USB

DP_IG_AUX_CH1_P

17 OF 110

3.3.0

051-8467

17 OF 74

1 2

1 2

1 2

1 2

1 2

C23

B23

F30

G30

J29

K30

D23
E23

J30

J24
H24

G24
F24

E24
D24

C24
B24

K26

J26

K24
K23

F23
G23

H23
J23

A29
B29

B27

D27
C27

H27

H30

E27

G27

F27

G26

H26

E26

F26

C26

D26

J27

C29
D30
E30

D29

E29

F29

G29

C30

B30

A30

C21
B21

H29
K27

L23
M23

M22

L22

L25
M25

L26
M26

L27

L28

M27

M28
L24

M24
A23

A24

B26

A26

A27

1 2
1 2

17

8

18 19

17

7

17 37

9

17 68

24

24

9

8

24

9

17 68

9

17 68

9

17 68

24

23

23

IN

BI

IN
IN
IN
IN

IN
IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

USB0_P
USB0_N

SATA_A1_TX_P
SATA_A1_TX_N

SATA_A1_RX_P

SATA_LED*/GPIO_30

SATA_TERMP

USB1_P
USB1_N

USB2_P
USB2_N

USB3_N

USB6_P

USB7_P
USB7_N

USB4_P
USB4_N

USB5_P
USB5_N

USB_OC0*/GPIO_25
USB_OC1*/GPIO_26

USB_RBIAS_GND

RGMII_RXD0
RGMII_RXD1
RGMII_RXD2

RGMII_RXCTL

RGMII_RXCLK

RGMII_INTR/GPIO_35

+3.3V_PLL_MAC_DUAL

RGMII_COMP_VDD
RGMII_COMP_GND

RGMII_VREF

RGMII_TXD3

RGMII_TXCLK
RGMII_TXCTL

RGMII_MDC

RGMII_MDIO

RGMII_RESET*

RGMII_RXD3

BUF_25MHZ

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

USB3_P

USB6_N

SATA_A0_TX_P
SATA_A0_TX_N

SATA_A0_RX_N
SATA_A0_RX_P

NC

SATA_A1_RX_N

LAN

SYMBOL 6 OF 11

USB

SATA

BI
BI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Bluetooth

Internal 19.5K Pull-Downs on all USB pairs

OHCI1/EHCI1

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

Connect RGMII_RXD<0:3> together to 10K pull-down.
Connect RGMII_RXCLK to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_MDIO to 10K pull-down.

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

20 mA

Internal MAC Disable:

All other pins can be left TP or NC.

AirPort (PCIe Mini-Card)

Camera/External E

External C

External A

EXTERNAL D

SD Card/ExpressCard

OHCI0/EHCI0

Geyser Trackpad/Keyboard

9

9

70

9

70

9

70

9

70

9

70

9

70

9

70

R1810

MF

1/20W

201

49.9

1%

R1811

MF

1/20W

201

1%

49.9

7

37 69

7

37 69

47 69 72

47 69 72

38 69

38 69

R1850

8.2K

MF

1/20W

201

5%

R1851

201

MF

8.2K

1/20W

5%

7

37 69

7

37 69

9

69

9

69

9

69

9

69

36 69

36 69

R1860

201

1%
1/20W

887

MF

9

68

9

68

9

68

9

68

35 68

35 68

35 68

35 68

R1805

MF

1/20W
201

2.49K

1%

9

R1800

MF

1/20W

201

5%

100K

U1400

OMIT_TABLE

BGA

MCP89U-A01

7

34 69

7

34 69

MCP SATA, USB & Ethernet

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

USB_EXTC_N

USB_BT_P

USB_SDCARD_N

USB_SDCARD_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTA_OC_L

=PP3V3_S5_MCP_GPIO

MCP_RGMII_VREF

=PP3V3_S0_MCP_GPIO

ENET_RXD<1>

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N

MCP_SATA_TERMP

PP3V3_ENET_MCP_PLL_MAC

MCP_MII_COMP_VDD

=PP3V3_ENET_MCP_RMGT

ENET_RXD<3>

USB_EXTA_P
USB_EXTA_N

USB_MINI_N

USB_MINI_P

USB_EXTC_P

USB_TPAD_N

USB_EXTD_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_HDD_D2R_N

USB_EXTD_P

TP_ENET_TXD<1>

TP_ENET_TXD<0>

TP_ENET_TXD<3>

TP_ENET_TXD<2>

TP_ENET_CLK125M_TXCLK
TP_ENET_TX_CTRL

TP_ENET_MDC

TP_MCP_CLK25M_BUF0_R

TP_ENET_RESET_L

ENET_MDIO

MCP_MII_COMP_GND

MXM_GOOD_L

ENET_RX_CTRL

ENET_ENERGY_DET

ENET_RXD<2>

ENET_RXD<0>

ENET_CLK125M_RXCLK

USB_EXTD_OC_L

USB_BT_N

MCP_USB_RBIAS_GND

USB_TPAD_P

18 OF 110

3.3.0

051-8467

18 OF 74

1

2

1

2

1

2

1

2

1

2

1

2

1

2

E21
D21

AF2
AF3

AF4

AG5

AG4

F21
G21

E20
D20

K21

G20

H20
J20

A20
A21

H21
J21

H14
G12

L19

C15
H17
C17

A15

D17

E17

J18
K15

K14

B15

D15
G14

C14

E15
H18

G17

G15

J14

J17

F17

F15

L21

F20

AF1
AG1

AG3
AG2

G5
V6

AK36

AM4
H15

AF5

36

8

19

8

17 19

68

23

70

8

20 23

70

7

37

69

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

IN

OUT
OUT
OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

OUT
OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

OUT

OUT

BI

BI

BI

BI

IN

IN

BI

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

BI

OUT

IN

PKG_TEST2

PKG_TEST

TEST_MODE_EN

SUS_CLK/GPIO_34

XTALOUT_RTC

XTALIN_RTC

XTALIN
XTALOUT

JTAG_TCK

JTAG_TRST*

JTAG_TDO
JTAG_TMS

JTAG_TDI

MGPU_PIO3/GPIO_24

MGPU_PIO1/GPIO_7
MGPU_PIO2/GPIO_23

MGPU_PIO0/GPIO_6

INTRUDER*

MEMVTT_EN/GPIO_45

MCP_MEMVDD_EN/GPIO_44

PWRGD

RTC_RST*

PWRGD_SB

RSTBTN*

PWRBTN*

KBRDRSTIN*/GPIO_56

A20GATE/GPIO_55

SIO_PME*/GPIO_31
EXT_SMI*/GPIO_32

SMB_ALERT*/GPIO_64

SMB_DATA1/MSMB_DATA

SMB_CLK1/MSMB_CLK

SMB_DATA0

SMB_CLK0

THERM_DIODE_N

THERM_DIODE_P

SPKR/GPIO_1

SPI_DO/GPIO_09

SPI_DI/GPIO_08

MCP_VID3/GPIO_16

MCP_VID2/GPIO_15

SLP_RMGT*

SLP_S3*

FANRPM1/GPIO_63/MGPIO_3

FANCTL1/GPIO_62

FANCTL0/GPIO_61

FANRPM0/GPIO_60/MGPIO_2

MISC_VDDEN4/GPIO_19
MEM_VDD_SEL/GPIO_46

MISC_VDDEN3/GPIO_18

MISC_VDDEN2/GPIO_17

MISC_VDDEN1/GPIO_48

MISC_VDDEN0/GPIO_47

LPC_DRQ0*/GPIO_43

LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLKRUN*/GPIO_42

LPC_SERIRQ

LPC_AD0

HDA_PULLDN_COMP

HDA_SYNC

HDA_RESET*

HDA_BITCLK

HDA_SDATA_OUT

HDA_SDATA_IN0

LPC_FRAME*

+VDD_HDA

SLP_S5*

MCP_WAKE_DIS*

MCP_WAKE_REQ*

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14

SPI_CLK/GPIO_11

SPI_CS0*/GPIO_10

LPC_RESET*

LPC_CLK0

HDA

LPC

SYMBOL 7 OF 11

MISC

OUT

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Platform-Specific Connections

behavior of Inte’s SLP_S4# signal

NOTE: MCP SLP_S5# signal has the

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

0 = USER mode (Normal boot mode)

FIXME: AUD_IPHS_SWITCH_EN WAS GPIO_2

internal ~9K
pull-up.

(IPU)

(IPU-S5)

(IPD)

(IPU)

(IPU-S5)

(IPD)

62.5 MHz

42.7 MHz

25.0 MHz

(IPU)

(IPU-S5)

(IPU)

(IPD)

70 mA

(IPD)

(IPU)

(IPU)

(IPU)

1
0

Frequency

24 MHz

14.31818 MHz

0

0
1

1

SPI Frequency Select

1

0

Frequency

BIOS Boot Select

0

LPC_FRAME#

LPC

(IPU)

(IPU)

0

NOTE: MCP89 does not support FWH, only
LPC ROMs. So Apple designs will

HDA_SYNC

I/F

SPI_CLK

BUF_SIO_CLK Frequency

1

SPI

not use LPC for BootROM override.

MCP_SPKR:

(IPD)

(IPU)

(IPU-S5)

(IPD)

For EMI Reduction on HDA interface

1

SPI_DO

31.2 MHz

Connects to SMC for automatic recovery.

HDA Output Caps

NOTE: 42 & 62 MHz use FAST_READ command.
Straps not provided on this page.

1 = SAFE mode (For ROMSIP recovery)

(IPD)

GPIO43 has

70 mA

has the behavior

signal.

NOTE: MCP SLP_S5# pin

of Intel’s SLP_S4#

GPIO Pull-Ups/Downs

7

39 41 69

19 25 69

7

39 41 25 69

201

MF

1/20W

5%

10K

R1961

201

MF

1/20W

22

5%

R1953

7

37 69

201

MF

1/20W

22

5%

R1952

MF

1/20W

201

5%

22

R1951

201

MF

1/20W

22

5%

R1950

7

37 69

7

37 69

7

37 69

201

MF

1/20W

1%

49.9

R1900

7

37 69

25

25

25

25

39

39

13

25

19 55

19 55

19 55

19 55

45 72

45 72

7

19 39 58

58

7

39 40 58

41 69

19 41 69

41 69

41 69

201

MF

1/20W

10K

5%

R1970

40

10K

5%
1/20W
MF
201

R1959

1K

1%
1/20W
MF
201

R1975

25 69

19 34 58

42 69

42 69

42 69

42 69

201

MF

1/20W

5%

10K

R1930

1/20W
201

MF

5%

100K

R1931

13

13

13

13

13

25

39

39

40

201

MF

1/20W

49.9K

1%

R1920

201

MF

1/20W

49.9K

1%

R1921

201

25V
NPO

10PF

5%

C1951

201

25V
NPO

5%

10PF

C1950

201

25V
NPO

5%

10PF

C1953

201

25V
NPO

5%

10PF

C1952

7

39 41

21

21 58

201

MF

1/20W

22

5%

R1960

201MF

1/20W

22

5%

R1910

201MF

1/20W

5%

22

R1912

201MF

1/20W

22

5%

R1911

201MF

1/20W

5%

22

R1913

7

39 41 69

7

39 41 69

7

39 41 69

7

39 41 69

39

7

37

7

19 41 48

19 22

7

19 37

19 39

19 38

19

39 40 58

9

19 40

10K

5%

1/20W

MF 201

R1996

R1980

201MF

1/20W

10K

5%

201MF

1/20W

5%

100K

R1987

10K

5%

1/20W

MF 201

R1990

201MF

1/20W

10K

5%

R1991

201MF

1/20W

5%

10K

R1989

201MF

1/20W

10K

5%

R1981

201MF

1/20W

100K

5%

R1992

201MF

1/20W

5%

100K

R1993

201MF

1/20W

5%

100K

R1994

201MF

1/20W

100K

5%

R1995

201MF

1/20W

100K

5%

R1986

7

19 41

7

39 41 19 25 69

R1965

201

MF

1/20W

33

5%

5%
MF

201

1/20W

10K

NO STUFF

R1966

5% 201MF

1/20W

10K

R1983

201MF

1/20W

5%

20K

R1998

201MF

1/20W

5%

100K

R1999

OMIT_TABLE

MCP89U-A01

BGA

U1400

470

201

MF

1/20W

5%

DRAM_CFG1:L

R1956

201

MF

1/20W

5%

DRAM_CFG0:H

10K

R1957

201

MF

1/20W

10K

5%

DRAM_CFG2:H

R1978

5%

10K

1/20W
MF
201

DRAM_CFG2:L

R1979

5%

10K

1/20W

MF

201

DRAM_CFG3:H

R1976

5%

10K

1/20W

MF

201

DRAM_CFG3:L

R1977

5%
1/20W
MF
201

10K

DRAM_CFG0:L

R1958

39

7

19 39 58

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MCP HDA, LPC & MISC

SPIROM_USE_MLB

MAKE_BASE=TRUE

PM_SLP_S4_L PM_SLP_S5_L

LPC_PWRDWN_L

LPC_RESET_L

MCP_TEST_MODE_EN

=PP3V3_S3_MCP_GPIO

MCP_VID<0>

PM_SLP_S4_L

PM_SLP_RMGT_L

PM_SLP_S3_L

SPI_MISO

MCP_VID<1>

MCP_MEM_VDD_SEL_1V5
MLB_RAM_CFG3

SMC_ADAPTER_EN
LPCPLUS_GPIO

RTC_CLK32K_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALIN

JTAG_MCP_TRST_L

JTAG_MCP_TMS

JTAG_MCP_TDI

SPIROM_USE_MLB

AUD_IPHS_SWITCH_EN
GFXVCORE_PWR_EN

SMC_IG_THROTTLE_L

MCP_MEM_VTT_EN

MCP_PS_PWRGD

RTC_RST_L

PM_SYSRST_DEBOUNCE_L

PM_PWRBTN_L

SMC_RUNTIME_SCI_L

AUD_I2C_INT_L

SMC_WAKE_SCI_L
PM_LATRIGGER_L

SMBUS_MCP_0_DATA

SMBUS_MCP_0_CLK

MCP_THMDIODE_N

MCP_VID<3>

MCP_VID<2>

MLB_RAM_CFG0

MCP_CPU_VTT_EN_L

LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

PM_CLKRUN_L

LPC_SERIRQ

LPC_AD_R<0>

MCP_HDA_PULLDN_COMP

HDA_RST_R_L

HDA_BIT_CLK_R

HDA_SDOUT_R

HDA_SDIN0

PM_BATLOW_L

MCP_WAKE_REQ_L

SPI_CLK_R

SPI_CS0_R_L

LPC_CLK33M_SMC_R

PM_RSMRST_L

MCP_SPKR

LPC_FRAME_R_L

LPC_AD<1>
LPC_AD<2>

HDA_SDOUT

HDA_RST_L

HDA_BIT_CLK

=PP3V3_S0_MCP_GPIO

HDA_SYNC

LPC_AD<0>

HDA_RST_R_L

LPC_AD<3>

=PP3V3R1V5_S0_MCP_HDA

PP3V3_G3_RTC

LPC_FRAME_L

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_SYNC_R

MCP_VID<3>

MCP_VID<2>

MLB_RAM_CFG1

PM_CLK32K_SUSCLK_R

MLB_RAM_CFG0

MLB_RAM_CFG1

MLB_RAM_CFG2

MLB_RAM_CFG3

LPC_RESET_L

SMBUS_MCP_1_DATA

SMBUS_MCP_1_CLK

AP_PWR_EN

MCP_THMDIODE_P

SPI_MOSI_R

ENET_LOW_PWR
SDCARD_RESET

MEM_EVENT_L

MLB_RAM_CFG2

HDA_SYNC_R

MCP_MEM_VDD_EN

SM_INTRUDER_L

JTAG_MCP_TDO

JTAG_MCP_TCK

MCP_CLK25M_XTALOUT

MCP_VID<1>

MCP_VID<0>

AP_PWR_EN

SPI_MISO

=PP3V3_S3_MCP_GPIO
=PP3V3_S0_MCP_GPIO

=PP3V3_S5_MCP_GPIO

SMC_IG_THROTTLE_L

GFXVCORE_PWR_EN

AUD_IPHS_SWITCH_EN

MCP_CPU_VTT_EN_L
LPCPLUS_GPIO

MEM_EVENT_L

SDCARD_RESET

ENET_LOW_PWR

19 OF 110

3.3.0

051-8467

19 OF 74

21

1 2

1 2

1 2

1 2

1

2

1

2

1

2

1

2

121

2

121

2

2

1

2

1

2

1

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2
1 2
1 2
1 2

1 2

1 2

1

2

1 2

1 2

1 2

C20

B20

A6

H9

C18

B18

A14
B14

A12

E12

C12
B12

D12

G9

E6
F9

D5

G18

C11

B11

E9

D18

F18

F12

H12

D3

F6

D14
J11

D9

C6

B6

C8

C5

D1

C2

E1

E14

B9

D6

E5

C9

A8

G7

F8

D8
E8

G11
D11

F11

E11

F14

A11

F2

H2
H3
H4

F1

H5H1

A5

A4

C4

B4

B3

C3

F3

J12

B8

A9

E18

E3
E4

G8

H10

F5
F4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

7

19 41 48

8

19

19

19

19

69 19 69

19 69

19 69

8

17 18 19

19 69

8

23

8

20 23

19 69

19 69

19 69

19 55

19 55

19

19

19

19

19

19

19 69

19 55

19 55

19 34 58

19 41 69

8

19

8

17 18 19

8

18

19 40

19 22

7

19 37

19

7

19 41

19 39

19 38

19

+VTT_CPU
+VTT_CPU
+VTT_CPU

+VDD_MEM
+VDD_MEM
+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM
+VDD_MEM

+VDD_MEM

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VDD_MEM

+VTT_CPU2

+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2

+3.3V_HVDD

+3.3V

+VTT_CPU2

+3.3V
+3.3V

+VDD_DUAL_AUXC
+VDD_DUAL_AUXC

+3.3V_VBAT

+3.3V_DUAL_USB
+3.3V_DUAL_USB

+3.3V_DUAL

+VTT_CPU

+VTT_CPU
+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU
+VTT_CPU

+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU

+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU

+3.3V_DUAL_RMGT

+3.3V_DUAL_RMGT

+VDD_DUAL_RMGT

+VDD_DUAL_RMGT

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

SYMBOL 8 OF 11

POWER I

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB
+VDD_COREB
+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREB

+VDD_COREA

+VDD_COREA
+VDD_COREA

+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA
+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA_SENSE
GND_COREA_SENSE

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_AVDD

+VIO_PE_AVDD
+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD

+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD

+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD

GND_COREB_SENSE

+VDD_COREB_SENSE

POWER II

SYMBOL 9 OF 11

GND GND

SYMBOL 10 OF 11

GND

GND GND

GND

SYMBOL 11 OF 11

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

400 MA

PE1[1:0])

2000 mA 4300 mA

200 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

30 mA

250 mA

150 mA

?? uA (G3)

5 mA (S0)

200 mA

40 mA

240 mA

140 mA

300 mA

regulators.

8450 mA (0.85V)

be used for remote sensing unless

15350 mA (0.85V)

(PE0[5:0]

COREA/COREB are powered by separate

(PE0[5:0], PE1[1:0])

1000 MA

100 mA

300 mA

Instead connect regulator sense point
as close to COREB FET as possible.

NOTE: VDD_COREx_SENSE signals should NOT

BGA

MCP89U-A01

OMIT_TABLE

U1400

BGA

MCP89U-A01

OMIT_TABLE

U1400

BGA

MCP89U-A01

OMIT_TABLE

U1400

MCP89U-A01

BGA

OMIT_TABLE

U1400

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MCP Power & Ground

=PP1V05_SW_MCP_FSB

=PP1V5R1V35_SW_MCP_MEM

=PPVCORE_S0_MCP

TP_MCP_VDDCOREA_SENSEP
TP_MCP_VDDCOREA_SENSEN

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP

PP3V3_G3_RTC

=PP0V9_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

=PP3V3_S0_MCP_HVDD

=PP1V05_S0_MCP_FSB

TP_MCP_VDDCOREB_SENSEP
TP_MCP_VDDCOREB_SENSEN

=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDD

PP1V05_S0_MCP_PE_AVDD

=PP1V05_S0_MCP_PE_DVDD

=PPVCORE_SW_MCP_GFX

=PP0V9_ENET_MCP_RMGT

20 OF 110

3.3.0

051-8467

20 OF 74

W30
N29
K31

AK2
AK25
AJ28

AL17

AL21

AK9
AK28
AJ11
AJ5
AJ29
AJ3
AJ20
AK10
AJ18
AK1
AJ1
AJ7
AJ8
AJ25
AJ16

AK11

AK18

AK27

AK14

AJ22

AK3

AJ21

AK22
AK8

AJ4

AA30

E32

L29

E33

C32

AK24

AC29

AC30
AD30
AB31
AC31
AD31
AC32

V9

V10

AD29

H11
K29

L18
K18

A18
L20

K20

J15

V29

Y29
W29

Y30

N30

AA29

L31

V30
U29

M29
M30
R30
P30
L32
T29
L30
U30
P29
R29

F32
H32
G32
A33

D32
AB30
AB29

C33

D33

A32

J33

T30

M31

F33

H33

J32

B33

G33

B32

B17

A17

L17

K17

AL30

AL29

AL27

AL26

AL20

AL18

AL15

AL14

AL12

AL11

AJ14

AJ13

AJ6

AK7

AJ15

AK6

AJ9

AK29

AJ2

AK23

AK17

AJ12

AJ10

AJ27

AK20

AK26

AK4

AK12

AJ19

AK16

AK13

AJ26

AK5

AK15

AJ17

AK21

AJ24

AJ23

AK19

M13

L14

L13

AB20

AB19

AB18

AB17

AB22

Y22

Y21

Y20

Y19

Y18

Y17

AB21

V22

V17
V19
V18

M14

V21

V20

V23

K4

L6

J5

L1

L2

J6

K11

L3

L4

M5

J7

J1

J2

L5

L11

M4

J4

M3

L9

K5

M12

M11

L7

K2

M9

M7
Y23
M2
AB23

R3

R12

N11

N2

N7

N5

R9

P1

R2

P8

P4

P3

R5

N10

P6

R7

AD24

P5

R10

N8

R4

P2

R1

P10

AA24

Y24

AD23

R11

P7

P12

P11

AC24

AB24

R6

N12

J3

N4

P9
R8

L8
M8
M10
L10
M6
L12
K10
K7
M1
K8

AD20

AD19

AD18

AD17

AD21
AD22

U11

T12

T11

W24

V24

U24

V11

U9
U8

AC8

AD6

AD8

AD9

AC9

AD7

AC10

AC7

AD10

AD11

AC11

AD12

AC12

AE12

AA10

AB10

V12

U12

W11
W12
Y11

Y12
AA11
AA12
AB11
AB12

AF6
AG8
AF7

AG9

AF8

AG6
AF9
AG7

AD1
AD2
AD3
AD4
AC3
AC4
AC5
AD5
AC6
AC1
AC2

J8

J9

W19

E10

AN25

AU34
AW19

AC21

AH31

AT31

AT10

T36

K37

AE4

T37

B5

C40

AB4

AB2

G4

AE5

AC20

AW34

AE8

W18

AT16

AB5
N34
AT2
W20

AW16

D7

B2
G37
D16
K39
G31

B7
L15

Y10
AW2
AH7
B13

AE37

AV1

AN19
AP10

W33

AB36

K13

AU13
AA23
AA31

Y31

AE33

AY3
N33

T2
B39

T4

AH37

V31

AU37

AW5
AU7
AT7

AN28

D4

AU19
AP25
AU22
AW13

T33

E7
AW7
H13

AL25

AL34

G13

AM32

B10

AY38

AU25

W4

D10

AU10

H31
AL31
U31

AE31

AN16

AA22

G10
B22
B19

AC18

B34
E22

AL22

K34

P31

G34

AP36

H25

U21

AU4
AA19

B31

AT19

W8

AT13

AP19

AH2

A38

AE39

AT34

AA18
AT25

U23
D22

AW31

W36
W39

AC23
AP22

W37

AP31

AN13

AU31
AL19
AL2

E28

AA20

AH34
B28
AV40
D28
H28
G36
AE36

AP16

E16

B16

V8
AM5

V7

H7

H6

AK35

AK34

W2

AP7
U17

E13

K33

AL13

AA17
T10

N31

AL39
T31

T7
W31

U18

AL10
AP34

W7
AP2

W5

M21
AE7

M19
M20

M18

M17

M15

T8
M16

D31

AN22

T34

AW22

K22

L16

E19

AU28

AW28

AE29

N37

N36

N39

AN10
AB8

AL5

AH39

AW39

G39
AB39

AL33
AW10

AC17
AH5

AH36

AB7

AB37

B36

D37

E39

C1

AL4

AW36

G22

U20

AU16
AB34

AL37

AC19
AN31

E2
T5

K19

H8

G2

AC22

H22

Y1

D19

W23

E25
K36

W21
D34

AP5

AE34
AT39

AL28

E34

K12

W34

U10

U19

AB33

B25

AP39

R31

AH8

A3

H19

W22

AP37

AA1

AL8

AH33
AT22

H16

AP28
AT28

AP13

U22

E31
G16

K25

AP4
G25

K28

AL16

AA21

K16

AL36

G19

AL7

T39
AH4

W17

AE30

D25

AE2

D13

AW25

G28

8

23 15 21 23

8

23

8

18 23

8

23

8

19 23

8

23

8

23

8

23

8

14 23

8

23

23 23

8

23

22 24

8

23

NC

NC

OUT

OUT

IN

BI

BI

BI

BI

D

G S

IN

VCC

D

DONE

G

GND

THRM

S

EN

CNFG

PAD

D

G

G

D

S

S

D

G

G

D

S

S

NC

K1

G

S

SENSE

D

KELVIN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NO STUBS on CKE signals!

DIMM CKE Clamps

Q2355/Q2356 chosen for low output capacitance.

CKE must be held low to keep memory in self-refresh.

Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.

Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.

Clamps enable before MCP89 MEMVDD rail switched off.

<R1>

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

Gated Rail Savings: 120mW

NV Requirements:

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

- Min Ramp-Up Time: 20 uS (10% to 90%)

- FET Ron <= 3.8 mOhms

4250 mA

(OR 1.35V)

Q2300

Type

Part

N-Channel

STMFS4854N

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

Loading

(G driven to VCC)

C2300 helps reduce input rail
droop during Q2300 turn-on.

Rds(on)

10 mOhm @3.2V

4.3 A (EDP)

44

44

MF

560K

1%
1/20W

201

R2305

19 58

0.1UF

402

CERM

10V

20%

C2305

CRITICAL

PLACE_NEAR=Q2300.9:2 mm

1206-1

CERM-X5R

6.3V

20%

100UF

C2300

15 28 29 32 67

15 28 29 32 67

15 26 27 32 67

15 26 27 32 67

SOD-VESM-HF

SSM3K15FV

Q2350

19

5%

10K

MF

1/20W

201

R2350

CRITICAL

TDFN

SLG5AP031

U2305

SOT-963

CRITICAL

NTUD3170NZXXG

Q2355

SOT-963

CRITICAL

NTUD3170NZXXG

Q2356

DFN

CRITICAL

STMFS4855NS

Q2300

MCP89 Memory Rail Gating

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MEMVTT_EN_L

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_A_CKE<0>

MEM_A_CKE<1>

=PP5V_S3_MCPDDRFET

MCP_MEM_VTT_EN

=PP5V_S3_MCPDDRFET

TP_MCPMEM_DONE

MCPMEM_CNFG

=PP1V5R1V35_SW_MCP_MEM

MCP_MEM_VDD_EN

=PP1V5R1V35_S0_MCPDDRFET

MCPDDRFET_SENSE

MCPDDRFET_KELVIN

MCPMEM_GATE

PP1V5R1V35_SW_MCP

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

23 OF 110

3.3.0

051-8467

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OUT

OUT

S

D

G

IN

CNFG

EN

S

THRM

GND

G

DONE

D

VCC

PAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

(G driven to VCC)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

Q2400

15.35 A (EDP)

NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

droop during Q2400 turn-on.

C2400 helps reduce input rail

N-Channel

Si4838BDY

3.2 mOhm @2.5V

- Min Ramp-Up Time: 100 uS (10% to 90%)

- FET Ron <= 2.5 mOhms

Gated Rail Savings: 860mW

NV Requirements:

Type

Part

Loading

Rds(on)

PLACE_NEAR=C2400.2:1 mm

SM

XW2401

SM

PLACE_NEAR=C2400.1:1 mm

XW2400

55 72

55 72

SO-8

SI4838BDY

CRITICAL

Q2400

19

20%
10V
CERM
402

0.1UF

C2405

100UF

PLACE_NEAR=Q2400.5:2 mm

CRITICAL

1206-1

CERM-X5R

6.3V

20%

C2400

10%
CERM

820PF

402

50V

C2406

SLG5AP033

TDFN

CRITICAL

U2405

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MCP89 GFX Core Rail Gating

MIN_NECK_WIDTH=0.12 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0.9V

MAKE_BASE=TRUE

PPVCORE_SW_MCP_GFX

=PPVCORE_S0_MCPGFXFET

=PP5V_S0_MCPFSBFET

TP_MCPGFX_DONE

GFXVCORE_PWR_EN

MCPGFX_CNFG

MCPGFX_GATE

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

=PPVCORE_SW_MCP_GFX

24 OF 110

3.3.0

051-8467

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20 24

NC

VOUT

EN

VIN

GND

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MCP 3.3V DP & USB PLL Power

<Ra>

<Rb>

210 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

260 mA

MCP CPU FSB (VTT) Power

MCP 3.3V PLL Power

50 mA

140 mA

800 mA

300 mA

555 mA

160 mA

325 mA

70 mA

240 mA

300 mA

5 mA (S0)

70 mA

30 mA

550 mA

100 mA200 mA

150 mA

200 mA

2000 mA

4300 mA (1.5V)

MCP 1.05V CPU/FSB/MEM PLL Power

MCP 1.05V PCIe/SATA PLL Power

MCP Memory Power

MCP 1.05V PCIE Digital Power

MCP 3.3V AUX/USB Power

MCP 3.3V I/O Power

MCP 3.3V MAC/SMU Power

MCP 0.9V AUX Core Power

250 mA

? uA (G3)

MCP 1.05V Memory DLL Power

MCP 1.05V Core/Misc PLL Power

MCP 0.9V MAC/SMU Power

MCP 1.05V SATA Digital Power

MCP S0 FSB (VTT) Power

MCP 3.3V/1.5V HDA Power

MCP 2.0V-3.3V RTC Power

MCP 1.05V PCIe Analog Power

500 mA

MCP 1.05V SATA Analog Power

8450 mA (0.85V)

MCP 3.3V MAC PLL POWER

20 mA 20 mA

MCP 3.3V PCIe/SATA I/O PLL Power

MCP Non-GFX Core Power

Vout = 0.8V * (Ra + Rb) / Rb, Rb ~ 320kOhms

20%

4.7UF

603

6.3V
CERM

C2590

20%
X5R

0.22UF

6.3V
201

C2503

20%
X5R

0201

6.3V

1.0UF

C2502

X5R

6.3V
201

10%

0.1UF

C2507

X5R

0.1UF

6.3V
201

10%

C2506

X5R

0.1UF

6.3V
201

10%

C2505

X5R

0.1UF

6.3V
201

10%

C2504

X5R

0.1UF

6.3V
201

10%

C2508

20%
X5R

6.3V

1.0UF

0201

C2532

20%
X5R

0201

1.0UF

6.3V

C2531

20%

4.7UF

402

X5R-1

4V

C2530

20%

4.7UF

402

X5R-1

4V

C2536

X5R

C2519

6.3V
201

0.1UF

10%

X5R
201

6.3V

10%

0.1UF

C2518

X5R

6.3V
201

10%

0.1UF

C2517

X5R

10%

6.3V
201

0.1UF

C2516

X5R

0.1UF

6.3V
201

10%

C2515

X5R

6.3V
201

10%

0.1UF

C2514

X5R

0.1UF

6.3V
201

10%

C2513

X5R

0.1UF

6.3V
201

10%

C2512

X5R

C2511

0.1UF

6.3V
201

10%20%

4.7UF

402

X5R-1

4V

C2510

0603

30-OHM-5A

L2560

30-OHM-5A

0603

L2567

20%
X5R

C2500

OMIT_TABLE

10UF

603-1

6.3V

20%

4.7UF

402

X5R-1

4V

C2501

X5R

6.3V
201

0.1UF

10%

C2527

X5R

6.3V
201

0.1UF

10%

C2526

20%

402

10V
CERM

0.1UF

C2591

X5R

6.3V
201

0.1UF

10%

C2537

X5R

0.1UF

C2533

10%

201

6.3V
X5R

10%

0.1UF

201

6.3V

C2534

X5R

0.1UF

10%

6.3V
201

C2529

20%

4.7UF

402

X5R-1

4V

C2528

X5R

C2549

0.1UF

10%

6.3V
201

20%

4.7UF

603

6.3V
CERM

C2548

X5R

6.3V
201

0.1UF

10%

C2535

20%

402

10V
CERM

0.1uF

C2554

20%

4.7uF

603

6.3V
CERM

C2553

20%

402

0.1uF

CERM

10V

C2551

20%

4.7uF

603

6.3V
CERM

C2550

20%

4.7uF

603

6.3V
CERM

C2543

20%

402

0.1uF

CERM

10V

C2544

20%

402

0.1uF

CERM

10V

C2545

20%

402

C2546

CERM

10V

0.1uF

20%

402

10V

0.1uF

CERM

C2547

20%
X5R

603-1

OMIT_TABLE

10UF

6.3V

C2520

20%

4.7UF

402

X5R-1

4V

C2521

20%
X5R

6.3V
0201

1.0UF

C2522

20%
X5R

6.3V
0201

1.0UF

C2523

20%
X5R

6.3V
0201

1.0UF

C2525

20%

4.7UF

402

X5R-1

4V

C2524

20%
X5R

OMIT_TABLE

10UF

6.3V

603-1

C2560

20%

4.7UF

402

X5R-1

4V

C2561

20%
X5R

1.0UF

0201

6.3V

C2562

20%
X5R

6.3V
0201

1.0UF

C2563

X5R

0.1UF

10%

201

6.3V

C2564

20%
X5R

OMIT_TABLE

10UF

603-1

6.3V

C2567

20%

4.7UF

402

X5R-1

4V

C2568

X5R

10%

201

6.3V

0.1UF

C2569

X5R

0.1UF

10%

201

6.3V

C2565

X5R

0.1UF

6.3V
201

10%

C2566

20%

4.7UF

402

X5R-1

4V

C2540

20%

4.7UF

C2595

PLACE_NEAR=R2595.1:50 mil

CERM

6.3V
603

20%

402

0.1UF

CERM

10V

C2596

20%

402

10V
CERM

0.1uF

C2597

MF

0.33

5%

1/16W

0402

R2595

20%

402

CERM

0.1uF

10V

C2542

20%

4.7UF

CERM

603

6.3V

C2541

X5R

6.3V
201

0.1UF

10%

C2572

X5R

0.1UF

6.3V
201

10%

C2571

20%

4.7UF

402

X5R-1

4V

PLACE_NEAR=R2570.1:50 mil

C2570

MF

1/16W

0402

0.33

5%

R2570

X5R

0.1UF

6.3V
201

10%

C2573

X5R

0.1UF

6.3V
201

10%

C2578

X5R

6.3V
201

0.1UF

10%

C2577

X5R
201

0.1UF

6.3V

10%

C2576

20%

4.7UF

402

X5R-1

4V

C2575

X5R

0.1UF

6.3V
201

10%

C2583

X5R

6.3V
201

0.1UF

10%

C2582

X5R

6.3V
201

10%

0.1UF

C2581

20%

4.7UF

402

X5R-1

4V

C2580

X5R

0.1UF

6.3V
201

10%

C2579

X5R

0.1UF

6.3V
201

10%

C2584

20%

4.7UF

603

6.3V
CERM

C2552

CRITICAL

0603

220-OHM-2.2A

L2570

220-OHM-2.2A

0603

CRITICAL

L2580

220-OHM-2.2A

0603

CRITICAL

L2575

220-OHM-2.2A

L2595

CRITICAL

0603

CRITICAL

L2590

FERR-240-OHM-200MA

0402

MCPHVDD:P3V3

20%

402

0.1UF

CERM

10V

C2556

20%

4.7UF

603

CERM

6.3V

C2555

0402

FERR-240-OHM-200MA

CRITICAL

L2555

20%

4.7UF

402

X5R-1

4V

C2559

20%

4.7UF

402

X5R-1

4V

C2538

SC70

CRITICAL

OMIT_TABLE

U2590

MIC5365-2.5V

R2590

10K

201

5%

1/20W

MF

MCPHVDD:P2V5

20%
X5R

MCPHVDD:P2V5

1.0UF

0201

6.3V

C2592

201

1%

665K

1/20W

MF

HVDDLDO:ADJ

R2591

HVDDLDO:ADJ

R2592

201

1%

316K

1/20W

MF

353S2988

IC,MIC5366,LDO REG,2.5V,150MA,SC70

1 CRITICALU2590

HVDDLDO:FIXED

353S2979

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HF

1 CRITICAL

HVDDLDO:ADJ

U2590

SYNC_DATE=04/08/2010

MCP Standard Decoupling

SYNC_MASTER=K99_MLB

PP3V3_S0_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

P2V8HVDD_FB

PP3V3_S0_MCP_PLL_HVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

P2V8HVDD_EN

=PP3V3_S0_MCP_PLL_UF

=PP1V05_SW_MCP_FSB

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PE_AVDD

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.25 MM
VOLTAGE=0V

MIN_NECK_WIDTH=0.25 MM

GND_MCP_PLL_DP_USB

GND_MCP_PLL_FSB

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V

=PP0V9_ENET_MCP_RMGT

=PP3V3_S0_MCP

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_PEXSATA

PP1V05_S0_MCP_PLL_FSBMEM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_MCP_M2CLK_DLL

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_FSB

=PP3V3_S5_MCP

=PP3V3R1V5_S0_MCP_HDA

PP3V3_G3_RTC

=PP1V05_S0_MCP_AVDD_UF

=PP3V3_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

PP3V3_ENET_MCP_PLL_MAC

=PP1V05_S0_MCP_PLL_UF

=PP3V3_S0_MCP_HVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE=PP1V05_S0_MCP_PE_DVDD

=PP0V9_S5_MCP_VDD_AUXC

=PP1V5R1V35_SW_MCP_MEM

=PPVCORE_S0_MCP

25 OF 110

3.3.0

051-8467

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