Apple A1369 Schematic

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DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

07/23/2010

SCHEM,MLB,K16

Schematic / PCB #’s

1 OF 74

051-8467

3.3.0

1 OF 110

2010-07-23

(MASTER)

38

(MASTER)

48

SecureDigital Card Reader

(MASTER)

37

(MASTER)

47

Left I/O (LIO) Connector

K99_MLB

36

03/01/2010

46

External USB Connectors

K99_MLB

35

04/08/2010

45

SATA CONNECTOR

K99_MLB

34

04/08/2010

40

X21 WIRELESS CONNECTOR

K99_MLB

33

04/08/2010

39

FSB/DDR3 Vref Margining

K99_MLB

32

04/08/2010

37

Memory Active Termination

K99_MLB

31

04/08/2010

36

DDR BYPASSING 2

K99_MLB

30

04/08/2010

35

DDR BYPASSING 1

K99_MLB

29

04/08/2010

34

DDR3 DRAM Channel B (32-63)

K99_MLB

28

04/08/2010

33

DDR3 DRAM Channel B (0-31)

K99_MLB

27

04/08/2010

32

DDR3 DRAM Channel A (32-63)

K99_MLB

26

04/08/2010

31

DDR3 DRAM Channel A (0-31)

(K99_MLB)

25

(02/11/2010)

28

SB Misc

K99_MLB

24

04/08/2010

26

MCP Graphics Support

K99_MLB

23

04/08/2010

25

MCP Standard Decoupling

K99_MLB

22

04/08/2010

24

MCP89 GFX Core Rail Gating

K99_MLB

21

04/08/2010

23

MCP89 Memory Rail Gating

K99_MLB

20

04/08/2010

20

MCP Power & Ground

K99_MLB

19

04/08/2010

19

MCP HDA, LPC & MISC

K99_MLB

18

04/08/2010

18

MCP SATA, USB & Ethernet

K99_MLB

17

04/08/2010

17

MCP Graphics

K99_MLB

16

04/08/2010

16

MCP PCIe Interfaces

K99_MLB

15

04/08/2010

15

MCP Memory Interface

K99_MLB

14

04/08/2010

14

MCP CPU Interface

K99_MLB

13

03/01/2010

13

eXtended Debug Port (Micro-XDP)

(K99_MLB)

12

(02/11/2010)

12

CPU Decoupling & VID

K99_MLB

11

04/08/2010

11

CPU Power & Ground

K99_MLB

10

04/08/2010

10

CPU FSB

(MASTER)

9

(MASTER)

9

Signal Aliases

(K99_MLB)

8

(02/11/2010)

8

Power Aliases

(K99_MLB)

7

(02/16/2010)

7

Functional Test / No Test

N/A

6

N/A

6

Revision History

N/A

5

N/A

5

K16 BOM Variants

K6_MLB

4

12/11/2009

4

BOM Configuration

MARTIN.YEH

3

2/25/2010

3

Power Block Diagram

ALAN.DAI

2

02/26/2010

2

System Block Diagram

74

K16_MLB

06/01/2010

Acoustic Cap BOM Config Tables

110

73

K99_MLB

04/08/2010

K99 RULE DEFINITIONS

109

72

T27_MLB

09/08/2009

K16/K99 Specific Constraints

108

71

K99_MLB

04/08/2010

SMC Constraints

106

70

K99_MLB

04/08/2010

Ethernet Constraints

104

69

K99_MLB

04/08/2010

MCP Constraints 2

103

68

K99_MLB

04/08/2010

MCP Constraints 1

102

67

K99_MLB

04/08/2010

Memory Constraints

101

66

K99_MLB

04/08/2010

CPU/FSB Constraints

100

65

K99_MLB

05/18/2010

Additional CPU/GPU Decoupling

99

64

K99_MLB

04/08/2010

LCD Backlight Support

98

63

(K99_MLB)

(03/01/2010)

LCD Backlight Driver

97

62

K16_MLB

06/01/2010

DisplayPort Connector

94

61

K99_MLB

04/08/2010

External DisplayPort Support

93

60

K99_MLB

07/23/2010

Internal DisplayPort Connector

90

59

K99_MLB

04/08/2010

Power FETs

79

58

K99_MLB

04/08/2010

Power Sequencing

78

57

K99_MLB

04/08/2010

Misc Power Supplies

77

56

(K99_MLB)

(03/01/2010)

CPUVTT (1.05V) Power Supply

76

55

(K99_MLB)

(02/11/2010)

MCP VCore Regulator

75

54

(K99_MLB)

(02/16/2010)

IMVP6 CPU VCore Regulator

74

53

K16_MLB

06/01/2010

1.5V/1.35V LVDDR3 Supply

73

52

K99_MLB

04/08/2010

5V / 3.3V Power Supply

72

51

(K99_MLB)

(02/16/2010)

PBus Supply & Battery Charger

70

50

(MASTER)

(MASTER)

DC-In & Battery Connectors

69

49

K99_MLB

04/08/2010

AUDI0: SPEAKER AMP

66

48

K99_MLB

04/08/2010

SPI ROM

61

47

K99_MLB

04/08/2010

WELLSPRING 1

57

46

K99_MLB

04/08/2010

Fan

56

45

K99_MLB

04/08/2010

Thermal Sensors

55

44

K99_MLB

04/08/2010

Current Sensing

54

43

K99_MLB

04/08/2010

Voltage & Current Sensing

53

42

K99_MLB

07/23/2010

K16/K99 SMus Connections

52

41

K99_MLB

04/08/2010

LPC+SPI Debug Connector

51

40

(K99_MLB)

(03/01/2010)

SMC Support

50

1051-8467 CRITICALSCH

SCHEM,MLB,K16

Sync

(.csa)

Date

Page

ContentsContents

(.csa)

Page

Date

Sync

39

K16_MLB

06/01/2010

SMC

49

820-2838 1

PCBF,MLB,K16

PCB CRITICAL

N/A

1

N/A

1

Table of Contents

SCHEM,MLB,K16

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

64-BIT
800MHZ

FSB

BASE FREQ.=200MHZ

64-BIT

64-BIT

DDR3-1066/1333MHZ

DDR3-1066/1333MHZ

BOOTROM

J1300

1.2 GHZ

U6100

SPI

SPKUSB

TMDS OUT

PANEL

LVDS OUT

(UP TO 8 DEVICES)

USB_7

PG 14

LPC+SPI

CONN

TRACKPAD

(IPD)

SMC

AUDIO CODEC

PG 17

UP TO 2 PORTS

USB_4

SATA_A0

USB_5

USB_0

USB_6

USB_2

PG 17

PG 18

J5700

SPEAKER

AMPS

LIO FLEX CONN

U6201

J4700

EXT

PG 18

HDA

PE1[0,1]:X1,X1 GEN1,UP TO 2 LANES

AIRPORT+

Y2810

BLUETOOTH

25MHZ

X4 DP LINK

SATA 2.0 3GBIT/S

PG 24

24.5X24.5MM

0.6MM PITCH
FCPBGA

1244P

FLAT

PG 60

DP0[3:0]

S3/S4

J6955

U6610

CTRL CONN

CHARGER,BATT CONN

SMS

PG 47

VOLTAGE/CURRENT SENSOR

PG 50,51

XDP CONN

SATA

U5515.U5535

J6950,U7000

CPU/MCP TEMP SENSOR

PENRYN

PG 16

PCI-E

J4501

SSD

INTERNAL

CONN

PG 6

SPEAKER

U6620

AMPS

LEFT

SPEAKER

J6700

HEADPHONE/

LINE IN

JACK

HEADPHONE

FILTER

PG 8

LINE IN

FILTER

PG 11

EXT USB

PG 6

LEFT

J4702

CAMERA+

CONN

ALS

J4610

I2C
MIKEY CAMERA

HDA

PG 36

USB

I2C

PG 49

PG 50

SPEAKER

J4600

U4800

PG 46

SD CARD

PG 50

HALL EFFECT

J4800

FAN CONN

U5920

SMB_A

SYS_LED

PM_SLP

LID

SMSFAN0ADC

SMB_B/0SMB_BSA

SERIAL
PORT

PG 40

MEMORY

U3300,3400

128MX8

PG 25,26

1GB

U3100,U3200

MEMORY

128MX8

USB 2.0

RGMII

PG 17

PE0[4,5]:X2,X1 GEN2,UP TO 2 LANES

SMB

DVI OUT

HDMI OUT

A

PG 9

PG 13

J5100

PG 37

1GB

SUPPORT GEN3,6.0GB/S

CTRL

LIO

POWER SUPPLY

RIGHT

CONN

CONN

CONN

SIL+

J6903

PG 35

PG 37

SD CARD

DP1[1:0]

PG 45

J5600

PG 42,43

PG 44

PG 52-57

CONN

PG 38

U4900

U1000

EXT USB

X2 DP LINK

DISPLAY

PG 62

J9400

CONN

DISPLAY

CONN

EXTERNAL

J9000

RGB OUT

SATA

PWR

PG 15

CONN

PG 34

RTC XTAL

PG 18

MCP

PG 24

Y2815

MISC

PG 18

PCIE GEN1

PE1_0

J4001

CONN

PG 33

LIO BOARD

PG 5

PG 18

PG 10

CONN

J6702

PG 9

PG 10

LPC

PG 18

LAN

GPIOs

FSB INTERFACE

MAIN

MEMORY

PG 18

B

PG 48

PG 27,28

SPI

32.768KHZ

NVIDIA
MCP89U

PG 12

INTEL CPU

System Block Diagram

SYNC_MASTER=ALAN.DAI SYNC_DATE=02/26/2010

2 OF 110

3.3.0

051-8467

2 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IN

BATTERY CHARGER

R7050

Q7080

PP18V5_DCIN_CONN

PBUS SUPPLY/

SLP_S3_L(P93)

VIN

PP4V5_AUDIO_ANALOG

V

SMC_BATT_ISENSE

01

PPVBAT_G3H_CHGR_R

P3V3S3_EN

CHGR_BGATE

EN2

Q7055

PPVBAT_G3H_CONN

PM_WLAN_EN_L

PM_SLP_S3_L

P1V5S0_EN

MCPCORES0_EN

RC

DELAY

16-4

Q7890,Q7891

DDRVTT_EN

S5

Q7930

MCPPLLDO_PGOOD

PP1V05_S0_MCP_PLL_REG

TPS74701

1.05V

U7740

ISL8009B

U7710

1.5V

PP1V5_S0_REG

ISL8009B

U7750

P3V3S0_EN

P5V3V3_PGOOD

PP0V9_S5_REG

VOUT1

(1A MAX CURRENT)

(25A MAX CURRENT)

PPMCPCORE_S0_R

(13A MAX CURRENT)

PP0V75_S0_REG

14

TPS51116

U7300

VOUT2

VOUT1

TPS51980

(5.3A MAX

(5.6A MAX CURRENT)

CURRENT)

Q7910

PP3V3_S5_REG

3.3V

LP8545

ENA

PPVOUT_SW_LCDBKLT

VOUT

U9701

02

(S5)

P16

U7400

02

VR_PWRGOOD_DELAY

SMC_CPU_ISENSE

PGOOD

TPS51982

VIN

CPU VCORE

(28A MAX CURRENT)

PPVCORE_S0_CPU

(11.5A MAX CURRENT)

(60MA MAX CURRENT)

PP3V42_G3H_REG

U6990

02

3.425V G3HOT
LT3470

VOUT

PBUS_G3H_VSENSE

V

VIN

CPUVTT

(1.05V)

ISL95870

U7600

06-1

PPVBAT_G3H_CHGR_REG

IMVP_VR_ON_R

PPBUS_G3H

PM_SLP_S3_L

U7840

P5VS3_EN_L

ISL6259

ENABLES

MAX8840

MCP89

DELAY

RC

DELAY

RC

CPUVTTS0_EN

16-5

16-6

AP_PWR_EN

Q7890

(9 TO 12.6V)

3S2P

PM_SLP_S3_L

U1400

PM_SLP_S4_L

MCP89

11

15

DELAY

RC

11-2

RC
DELAY

11-3

11-1

J6950

PBUSVSENSE_EN

DELAY

RC

P3V3S0_EN

(S0)

(S0)

16-2

16-1

16-1

04-1

=DDRREG_EN

=DDTVTT_EN

S3

MCPCORES0_EN

0.75V

02

VIN

EN

VIN

02

1.5V

P5VS3_EN_L

BKLT_EN

U4900

SMC

P60

A

ADAPTER

AC

6A FUSE

01

A

VOUT

Q7085

P3V3S5_EN_L

25

02

U7500

VOUT

20

PP1V5_S3_REG

VIN

VOUT

R7525

05

VIN

EN1

(RT)

5V

VREG3

VR_ON

28

PP3V3_S0_FET

PP3V3_S0
PP1V5_S0
PP1V05_S0

V2

V1

RST*

P1V5S0_PGOOD

P5V3V3_PGOOD

MCPCORES0_PGOOD

SLP_S5_L
SLP_S4_L
SLP_S3_L

09

ALL_SYS_PWRGD

05

SMC_ONOFF_L

RSMRST_PWRGD

SLP_S4_L(P94)

SLP_S5_L(P95)

U4900

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

99ms DLY

26

EN

U6200

VOUT

4.5V AUDIO

24

07

17

Q7940

P5VS0_EN

PP5V_S0_FET

SMC

29

U1000

CPU

U1400

PWRGD

CPUVTTS0_EN

02

EN_PSV

ENABLE

PP1V05_S0

03

RN5VD30A-F

SMC PWRGD

U5010

04

RST*

P17(BTN_OUT)

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

PLT_RST*

CPU_RESET#

PWRBTN*

PLTRST*

RESET*

CPUPWRGD(GPIO49)

PWRGOOD

RSMRST*

IMVP_VR_ON_R

PM_PWRBTN_L
SMC_RESET_L

25

PM_RSMRST_L

32

10

FSB_CPURST_L

30

CPU_PWRGD

LPC_RESET_L

31

13

PP5V_S3_REG

PGOOD1,2

ISL88042

V3

16

21

Q5315

EN

P5VS0_EN

DCIN(16.5V)

DDRREG_EN

SMC_DCIN_ISENSE

(S0)

F6905

R7020

VIN

(S5)

U7000

8A FUSE

F7040

VOUT

PBUS_VSENSE

PGOOD

SMC_CPU_VSENSE

CPUVTTS0_PGOOD

VOUT

PPBUS_G3H

VOUT2

VIN

04

U7201

SMC_ADAPTER_EN

ISL9563B

S0PGOOD_RST_L

P3V3S3_EN

PPMCPCORE_S0_REG

MCP_CORE

MCPMEM_GATE

Q2300

MCP_PS_PWRGD

U2850

CPUVTTS0_PGOOD

18

P3V3_S3_WLAN

PM_WLAN_EN_L

Q4050

PP3V3_S3_FET

PP1V5R1V35_SW_MCP

SMC_PM_G2_EN

CHGR_EN

U7870

K16 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H_OR_PBUS

Power Block Diagram

SYNC_MASTER=MARTIN.YEH

SYNC_DATE=2/25/2010

3 OF 110

3.3.0

051-8467

3 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

K16 BOM Variants on following page

ELPIDA

1

DRAM CFG CHART

HYNIX

SAMSUNG

Alternate Parts

Programmable Parts

4GB

2GB

SIZE

CFG 2

1

0

B

A

DIE REV

CFG 3

1

0

1

1

MICRON

CFG 0 CFG 1

VENDOR

0

1

0

0

0

Module Parts

BOM Groups

CRITICAL

ISL6259_SCREENED:YES

353S2929

1

U7000

ISL6259_SCREENED:NO

IC,ISL6259,BATCHARGER,4X4MM,QFN28

CRITICAL353S2392

1

U7000

DRAM_TYPE:MICRON_4GB

CRITICAL333S0557

4

MICRON,LVDDR3,2GBIT,9X11.5

DRAM_TYPE:MICRON_4GB

U3300,U3310,U3320,U3330

CRITICAL333S0557

4

MICRON,LVDDR3,2GBIT,9X11.5

U3400,U3410,U3420,U3430

333S0556

4

CRITICAL

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

U3200,U3210,U3220,U3230

DRAM_TYPE:MICRON_4GB

333S0557

4

MICRON,LVDDR3,2GBIT,9X11.5

U3100,U3110,U3120,U3130

CRITICAL

4

MICRON,LVDDR3,2GBIT,9X11.5

U3300,U3310,U3320,U3330

333S0556

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

CRITICAL

4

CRITICAL

4

333S0556

U3100,U3110,U3120,U3130

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

333S0556 CRITICAL

4

333S0555

4

HYNIX,LVDDR3,2GBIT,9X11.1

CRITICAL

U3400,U3410,U3420,U3430

333S0555

4

HYNIX,LVDDR3,2GBIT,9X11.1

U3200,U3210,U3220,U3230

CRITICAL

333S0555

4

U3300,U3310,U3320,U3330

HYNIX,LVDDR3,2GBIT,9X11.1

CRITICAL

333S0555 CRITICAL

HYNIX,LVDDR3,2GBIT,9X11.1

4

U3100,U3110,U3120,U3130

333S0566

U3100,U3110,U3120,U31304CRITICAL
U3200,U3210,U3220,U32304CRITICAL
U3300,U3310,U3320,U3330

CRITICAL

4

4

CRITICAL

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DRAM_TYPE:ELPIDA_2GB

U3400,U3410,U3420,U3430

4

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DRAM_TYPE:ELPIDA_2GB

4

U3200,U3210,U3220,U3230

DRAM_TYPE:ELPIDA_2GB

CRITICAL

U3100,U3110,U3120,U3130

333S0565

DRAM_TYPE:MICRON_2GB

333S0554

4

U3300,U3310,U3320,U3330

333S0554 CRITICAL

U3400,U3410,U3420,U3430

4

DRAM_TYPE:SAMSUNG_2GB

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

333S0553 CRITICAL
333S0554

U3100,U3110,U3120,U3130

CRITICAL4DRAM_TYPE:MICRON_2GB

DRAM_TYPE:MICRON_2GB

CRITICAL333S0554

4

U3200,U3210,U3220,U3230

U3300,U3310,U3320,U3330

333S0553

DRAM_TYPE:SAMSUNG_2GB

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

4

333S0553 CRITICAL

DRAM_TYPE:SAMSUNG_2GB

U3200,U3210,U3220,U3230

4

CRITICAL333S0553

DRAM_TYPE:SAMSUNG_2GB

4

4

CRITICAL

DRAM_TYPE:HYNIX_2GB

333S0552

DRAM_TYPE:HYNIX_2GB

HYNIX,LVDDR3,1GBIT,7.5X11.0

333S0552

4

CRITICAL

DRAM_TYPE:HYNIX_2GB

4

333S0552

333S0552

DRAM_TYPE:HYNIX_2GB

U3100,U3110,U3120,U3130

CRITICAL

4

337S3938

MCP89U:A03

IC,MCP89U-A03,24.5MMX24.5MM,1244FCBGA

1

CRITICAL

U1400

U1400

1

MCP89U:A02

337S3868

CRITICAL

1

337S3820

MCP89U:A01U1400

353S2988

ALL

138S0638138S0681

TAIYO YUDEN AS ALTERNATE

MAGLAYERS AS ALTERNATE

376S0926

TAIYO AS ALTERNATE

TAIYO AS ALTERNATE

CYNTEC AS ALTERNATE

CYNTEC/DALE AS ALTERNATES

TPS71725 ALTERNATE FOR U2590

MAGLAYERS AS ALTERNATE

FAIRCHILD AS ALTERNATE

MAGLAYERS AS ALTERNATE

ON SEMI AS ALTERNATE

155S0578 155S0367

152S0874

152S0586

IC,SMC,HS8/2117,9X9MM,TLP,HF

MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF,MU_CAP_22UF

BOOTROM:BLANK

DDR3:MICRON_4GB

DDR3:SAMSUNG_4GB

DDR3:HYNIX_4GB

CAPS:MU
CAPS:TY

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

CRITICAL335S0610

U6100

1

U4900

CRITICAL

1

SMC:BLANK

338S0563

152S0516

ALL

152S0847

ALL

353S2987

HVDDLDO:FIXED

ALL

107S0075107S0139

ALL

138S0673138S0671

ALL

104S0018104S0023

ALL

ALL

376S0610

ALL

155S0329155S0457

ALL

377S0066377S0107

ALL

SYNC_DATE=12/11/2009

SYNC_MASTER=K6_MLB

BOM Configuration

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:MICRON_4GB

U3300,U3310,U3320,U3330

ELPIDA,LVDDR3,1GBIT,7.5X10.6

4

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

CRITICAL

U3400,U3410,U3420,U3430

ELPIDA,LVDDR3,2GBIT,7.5X10.6

ELPIDA,LVDDR3,2GBIT,7.5X10.6

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DRAM_TYPE:ELPIDA_4GB
DRAM_TYPE:ELPIDA_4GB
DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:MICRON_4GB

U3400,U3410,U3420,U3430

IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28

333S0557

333S0566

333S0565

333S0565

CAPS:SS

SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF,SS_CAP_22UF

K16_COMMON

K16_MISC

K16_PROGPARTS

BOOTROM:UNLOCKED,SMC:PROG

LPCPLUS

K16_DEVEL:PVT

K16_DEVEL:ENG

DEVEL_BOM,SMC_DEBUG:YES,XDP

K16_DEBUG:ENG

K16_DEBUG:PROD

K16_DEBUG:PVT

DDR3:HYNIX_2GB

DDR3:MICRON_2GB

DDR3:SAMSUNG_2GB

DDR3:ELPIDA_2GB
DDR3:ELPIDA_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:ELPIDA_4GB

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

IC,MCP89U-A01,24.5MMX24.5MM,1244FCBGA

IC,MCP89U-A02,24.5MMX24.5MM,1244FCBGA

HYNIX,LVDDR3,1GBIT,7.5X11.0

HYNIX,LVDDR3,1GBIT,7.5X11.0

HYNIX,LVDDR3,1GBIT,7.5X11.0

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

SAMSUNG,LVDDR3,1GBIT,7.5X11.0

333S0566

BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

U3100,U3110,U3120,U3130

U3400,U3410,U3420,U3430

DRAM_TYPE:ELPIDA_2GB

ELPIDA,LVDDR3,2GBIT,7.5X10.6

4

333S0566

4

ELPIDA,LVDDR3,1GBIT,7.5X10.6

DP_ESD,DP_PWR:SMC,VFRQ:SLPS3,HVDDLDO:FIXED,MCPHVDD:P2V5,MCPPLL_R:REG,S0PGOOD_BJT,ISL6259_SCREENED:YES,DPI2C:SMC

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

U3200,U3210,U3220,U3230

U3400,U3410,U3420,U3430

MICRON,LVDDR3,1GBIT,8X11.5

MICRON,LVDDR3,1GBIT,8X11.5

MICRON,LVDDR3,1GBIT,8X11.5

MICRON,LVDDR3,1GBIT,8X11.5

333S0565

TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF,TY_CAP_22UF

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB

COMMON,ALTERNATE,PROJ:K16,K16_MISC,MCP89U:A03,K16_DEBUG:ENG,K16_PROGPARTS,SPI:41MHZ,LVDDR3:YES,WLAN_PCTL:HW,IPD_5V:S5_INT,IPD_3V3:S5

BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,MCPPLL_LDO,S3_S0_LED

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB

DRAM_CFG0:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_2GB

DRAM_CFG0:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB

DRAM_CFG0:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB

DRAM_CFG0:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB

SAMSUNG,LVDDR3,2GBIT,7.5X11.0

U3200,U3210,U3220,U3230

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:MICRON_2GB

U3300,U3310,U3320,U3330

4 OF 110

3.3.0

051-8467

4 OF 74

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

SAMSUNG

MURATA

TAIYO YUDEN

K16-Specific BOM Tables

Sub-BOMs

Bar Code Labels / EEE #’s

BOM Variants

CRITICAL

[EEEE_DCXL]

EEEE:DCXL

1825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCWT]

EEEE:DCWT

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

825-7557

[EEEE_DCWR]

EEEE:DCWR

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

[EEEE_DCXM]

EEEE:DCXM

1 CRITICAL825-7557

EEEE:DCWN

825-7557

[EEEE_DCWN]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

825-7557

EEEE:DCX3

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX3]

1

825-7557 1

[EEEE_DCWW]

EEEE:DCWW

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:DCWP

825-7557

[EEEE_DCWP]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX0]

825-7557

EEEE:DCX0

1 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX1]

825-7557

EEEE:DCX1

1 CRITICAL

825-7557

[EEEE_DCWX]

EEEE:DCWX

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

CRITICAL

EEEE:DCX2

[EEEE_DCX2]

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

1

825-7557

EEEE:DCX4

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCX4]

1 CRITICAL

[EEEE_DCX5]

EEEE:DCX5

1 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCWQ]

EEEE:DCWQ

1 CRITICAL

[EEEE_DCXK]

EEEE:DCXK

1 CRITICAL825-7557

1

EEEE:DCXC

CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCXC]

639-1092

PCBA,MLB,2.13GHZ HY 2GB,MU CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXJ,CAPS:MU,DDR3:HYNIX_2GB

PCBA,MLB,2.13GHZ HY 4GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX2,CAPS:TY,DDR3:HYNIX_4GB

639-1079

PCBA,MLB,2.13GHZ HY 4GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWX,CAPS:SS,DDR3:HYNIX_4GB

639-1075

PCBA,MLB,2.13GHZ HY 2GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX8,CAPS:TY,DDR3:HYNIX_2GB

639-1085

639-1082

PCBA,MLB,2.13GHZ,HY 2GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX5,CAPS:SS,DDR3:HYNIX_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWQ,CAPS:MU,DDR3:HYNIX_2GB

639-1070

PCBA,MLB,1.86GHZ HY 2GB,MU CAP,K16

PCBA,MLB,1.86GHZ HY 2GB,TY CAP,K16

639-1096

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXN,CAPS:TY,DDR3:HYNIX_2GB
K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXV,CAPS:MU,DDR3:HYNIX_4GB

639-1101

PCBA,MLB,1.86GHZ HY 4GB,MU CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXQ,CAPS:SS,DDR3:HYNIX_4GB

639-1098

PCBA,MLB,1.86GHZ HY 4GB,SS CAP,K16

639-1068

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWN,CAPS:TY,DDR3:HYNIX_4GB

PCBA,MLB,1.86GHZ HY 4GB,TY CAP,K16

639-1083

PCBA,MLB,1.86GHZ MI 2GB,MU CAP,K16

639-1090

PCBA,MLB,1.86GHZ MI 2GB,TY CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXG,CAPS:TY,DDR3:MICRON_2GB

639-1067

PCBA,MLB,1.86GHZ MI 4GB,SS CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWM,CAPS:SS,DDR3:MICRON_4GB

639-1088

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXD,CAPS:MU,DDR3:MICRON_4GB

PCBA,MLB,1.86GHZ MI 4GB,TY CAP,K16

639-1077

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCWR,CAPS:TY,DDR3:SAMSUNG_2GB

639-1071

PCBA,MLB,1.86GHZ SA 2GB,TY CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXM,CAPS:SS,DDR3:SAMSUNG_2GB

PCBA,MLB,1.86GHZ SA 2GB,SS CAP,K16

639-1095

PCBA,MLB,1.86GHZ SA 2GB,MU CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX3,CAPS:MU,DDR3:SAMSUNG_2GB

639-1080

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXP,CAPS:MU,DDR3:SAMSUNG_4GB

639-1097

PCBA,MLB,1.86GHZ SA 4GB,MU CAP,K16

639-1099

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXR,CAPS:MU,DDR3:MICRON_2GB

PCBA,MLB,2.13GHZ MI 2GB,MU CAP,K16

639-1093

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXK,CAPS:SS,DDR3:MICRON_4GB

PCBA,MLB,2.13GHZ MI 4GB,SS CAP,K16
PCBA,MLB,2.13GHZ MI 4GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWY,CAPS:TY,DDR3:MICRON_4GB

EEEE:DCX8

1 CRITICAL

[EEEE_DCX8]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557

EEEE:DCX6

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

[EEEE_DCX6]

EEEE:DCXG

825-7557

[EEEE_DCXG]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

[EEEE_DCXD]

EEEE:DCXD

1825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX7,CAPS:SS,DDR3:SAMSUNG_4GB

639-1084

PCBA,MLB,1.86GHZ SA 4GB,SS CAP,K16
PCBA,MLB,1.86GHZ SA 4GB,TY CAP,K16

639-1091

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXH,CAPS:TY,DDR3:SAMSUNG_4GB

EEEE:DCX7

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

[EEEE_DCX7]

825-7557

PCBA,MLB,2.13GHZ MI 4GB,MU CAP,K16

639-1100

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXT,CAPS:MU,DDR3:MICRON_4GB

PCBA,MLB,2.13GHZ MI 2GB,TY CAP,K16

639-1069

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWP,CAPS:TY,DDR3:MICRON_2GB

639-1087

PCBA,MLB,2.13GHZ MI 2GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXC,CAPS:SS,DDR3:MICRON_2GB

EEEE:DCXJ

[EEEE_DCXJ]

1 CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXH

1

[EEEE_DCXH]

CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXF

1 CRITICAL825-7557

[EEEE_DCXF]

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXN

[EEEE_DCXN]

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

EEEE:DCWM

[EEEE_DCWM]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL825-7557 1

825-7557

[EEEE_DCWV]

EEEE:DCWV

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

1

[EEEE_DCWY]

EEEE:DCWY

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCX9

1 CRITICAL

[EEEE_DCX9]

825-7557

PCBA,MLB,2.13GHZ HY 4GB,MU CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXF,CAPS:MU,DDR3:HYNIX_4GB

639-1089

639-1078

PCBA,MLB,1.86GHZ MI 2GB,SS CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX1,CAPS:SS,DDR3:MICRON_2GB

639-0837

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCXW,CAPS:SS,DDR3:HYNIX_2GB

PCBA,MLB,1.86GHZ,HY 2GB,SS CAP,K16

K16 BOM Variants

SYNC_DATE=N/A

SYNC_MASTER=N/A

825-7557
825-7557

1

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

PCBA,MLB,1.86GHZ MI 4GB,MU CAP,K16

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX6,CAPS:MU,DDR3:MICRON_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DCX0,CAPS:TY,DDR3:MICRON_4GB

639-1076

CPU:2.13GHZ

CRITICAL1 U1000

PDC,SLGEQ,PRQ,2.13,17W,1066,ED,6M,BGA

337S3758

CRITICAL1337S3751 U1000

CPU:1.86GHZ

PDC,SLGAB,PRQ,1.86,17W,1066,ED,6M,BGA

U49001 SMC:PROGCRITICAL

IC ASSY,SMC EXTERNAL,K16

341T0276
341T0275

IC ASSY,EFI UNLOCKED,K16

BOOTROM:UNLOCKED

U61001 CRITICAL

CRITICAL1 U6100

BOOTROM:LOCKED

341S2785

IC EFI ROM,PVT,LOCKED,K16

085-1327 1

DEVEL_BOM

CRITICALDEVEL

K16 MLB DEVELOPMENT BOM

607-6915 CRITICAL1

CMN PTS,PCBA,MLB,K16

CMNPTS

K16_CMNPTS

138S0634 CRITICAL

TY_CAP_2_2UF

1 C4807

CAP, 2.2UF, 6.3V, 20%, 0402CAP, 2.2UF, 6.3V, 20%, 0402

138S0633 CRITICAL

MU_CAP_2_2UF

1 C4807138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

1

SS_CAP_2_2UF

639-1072

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWT,CAPS:SS,DDR3:SAMSUNG_2GB

PCBA,MLB,2.13GHZ SA 2GB,SS CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX9,CAPS:TY,DDR3:SAMSUNG_2GB

639-1074

PCBA,MLB,2.13GHZ SA 2GB,MU CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWW,CAPS:MU,DDR3:SAMSUNG_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCWV,CAPS:MU,DDR3:SAMSUNG_4GB

639-1073

PCBA,MLB,2.13GHZ SA 4GB,SS CAP,K16

639-1081

PCBA,MLB,2.13GHZ SA 4GB,TY CAP,K16

639-1094

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 CRITICAL1

[EEEE_DCXP]

EEEE:DCXP

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 1

[EEEE_DCXQ]

EEEE:DCXQ

CRITICAL

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DCXR]

EEEE:DCXR

825-7557 CRITICAL1

EEEE:DCXT

[EEEE_DCXT]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DCXV

[EEEE_DCXV]

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

EEEE:DCXW

[EEEE_DCXW]

PCBA,MLB,1.86GHZ EL 2GB,SS CAP,K16

639-1451

PCBA,MLB,1.86GHZ EL 2GB,TY CAP,K16

639-1455

PCBA,MLB,2.13GHZ EL 2GB,SS CAP,K16

639-1454

PCBA,MLB,2.13GHZ EL 2GB,MU CAP,K16

639-1453

PCBA,MLB,1.86GHZ EL 2GB,MU CAP,K16

639-1450

639-1452

PCBA,MLB,2.13GHZ EL 2GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG50,CAPS:TY,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG52,CAPS:SS,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG51,CAPS:MU,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG53,CAPS:TY,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG4Y,CAPS:SS,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG4W,CAPS:MU,DDR3:ELPIDA_2GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCXL,CAPS:TY,DDR3:SAMSUNG_4GB

K16_CMNPTS,CPU:2.13GHZ,EEEE:DCX4,CAPS:SS,DDR3:SAMSUNG_4GB

PCBA,MLB,2.13GHZ SA 2GB,TY CAP,K16
PCBA,MLB,2.13GHZ SA 4GB,MU CAP,K16

639-1086

CRITICALC4807

EEEE:DG4Y

[EEEE_DG4Y]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 1 CRITICAL

EEEE:DG4W

[EEEE_DG4W]

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557 CRITICAL1

EEEE:DG53

[EEEE_DG53]

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DG52

[EEEE_DG52]

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DG51

[EEEE_DG51]

825-7557 CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:DG50

[EEEE_DG50]

825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1

1 CRITICAL825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG5P]

EEEE:DG5P

CRITICAL1825-7557

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG5W]

EEEE:DG5W

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

[EEEE_DG5T]

EEEE:DG5T

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

[EEEE_DG5V]

EEEE:DG5V

LBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL825-7557

[EEEE_DG5Q]

EEEE:DG5Q

1 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

825-7557

[EEEE_DG5R]

EEEE:DG5R

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG5P,CAPS:MU,DDR3:ELPIDA_4GB

PCBA,MLB,1.86GHZ EL 4GB,MU CAP,K16

639-1458

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG5W,CAPS:SS,DDR3:ELPIDA_4GB

PCBA,MLB,1.86GHZ EL 4GB,SS CAP,K16

639-1463

K16_CMNPTS,CPU:1.86GHZ,EEEE:DG5T,CAPS:TY,DDR3:ELPIDA_4GB

PCBA,MLB,1.86GHZ EL 4GB,TY CAP,K16

639-1460

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG5R,CAPS:TY,DDR3:ELPIDA_4GB

639-1461

PCBA,MLB,2.13GHZ EL 4GB,TY CAP,K16

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG5Q,CAPS:MU,DDR3:ELPIDA_4GB

PCBA,MLB,2.13GHZ EL 4GB,MU CAP,K16

639-1462

K16_CMNPTS,CPU:2.13GHZ,EEEE:DG5V,CAPS:SS,DDR3:ELPIDA_4GB

PCBA,MLB,2.13GHZ EL 4GB,SS CAP,K16

639-1459

K16_COMMON

CMN PTS,PCBA,MLB,K16

607-6915

K16_DEVEL:ENG

085-1327

K16 MLB DEVELOPMENT BOM

5 OF 110

3.3.0

051-8467

5 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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D

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8 7 5 4 2 1

7803283 - Changed 5V S3 regulator output from 5.02V to 5.12V nominal (pg. 72).
7809760 - Stuffed C9799 and clarified tables/BOMOPTIONs around these parts (pg. 97).

Proto 1 (ECO #0000884508, v2.0.0, P4 change #212783, 03/31/2010)

7796658 - Changed OMITs to OMIT_TABLEs (pp. 10-11, 14-20, 26, 31-36, 49, 61).

7796658 - Added alternates for two caps per GSM and removed unused alternates (pg. 4).

BOM:

BOM:

v2.1.0 (P4 change #??????, ??/??/2010)

v1.4.0 (P4 change #212757, 03/31/2010)

7761747 - Documented SMBus addresses for panel (pg. 52).
SD Card:
7800415 - Changed SD Card discharge R to more standard value (pg. 48).
Power Supplies:

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

7798399 - Consolidated 100pF caps (pp. 74, 75).

7809733 - Changed strapping to select 62.5MHz SPI bus frequency (pg. 4).

7796631 - Added XDP connection to SMBus aliases page (pp. 13, 52).
7808530 - Changed SMC ’MGMT’ SMBus pull-ups from 4.7K to 2K (pg. 52).

MCP SPI:

7788138 - Added feedback divider and BOM tables for more HVDD LDOs (pp. 4, 25).

7787883 - Added support for DP HPD wake / S4 state (pp. 4, 7, 8, 19, 49, 50, 78, 94).

7798425 - R/C value changes for 3.42V G3Hot power supply (pg. 69).

7796631 - Sorted BOM variants for easier verification (pg. 5).

7796683 - Stuffed RC on backlight driver PWM input (pg. 97).

7796658 - Changed RCs on some SMC analog inputs (pg. 54).

7796661 - Set up primary & alternate for power supply FET (pp. 4, 72).

7796648 - Changed DP and LCD power from PP3V3_S3 to PP3V3_S5 (pp. 8, 90).

7796626 - Changed port switch from TPS2052B to TPS2069 (pg. 46).

7742015 - Added RC to DDC pass FETs to avoid glitch (pp. 7, 93).

7761747 - Added resistors to connect TCON to SMC or MCP SMBus (pp. 4, 52, 90).

v1.1.0 (P4 change #211399, 03/24/2010)

v1.2.0 (P4 change #211839, 03/26/2010)

7787883 - Added PLACE_NEAR property on R5022 to avoid stub (pg. 50).

7787897 - Property/page fixes to reduce CheckPlus warnings/errors (pp. 7, 8, 12, 17, 74, 93, 108).

7769139 - Unstuffed SMS circuit (pg. 4).

7765466 - Added S3 pull-up to SMS_INT_L to prevent leakage path (pp. 50, 59).

SMC:

SMBus:

USB:

MCP:

SMC:

SMS:

General:

7761747 - Added TCON I2C nets to FUNC_TEST list for J9000 (pg. 7).

7796631 - Cosmetic clean-up (pg. 76).

7761747 - Added isolation FET and unstuffed series R’s on TCON I2C for now (pp. 4, 90, 108).

7796658 - Changed backlight driver back to non-E00 version (pp. 4, 97).

7796654 - Consolidated SSM6N15FE to SSM6N37FE (pg. 48).

7798445 - R value changes for 0.9V S5 power supply (pg. 77).

7800179 - R value changes for CPU VCore power supply (pg. 74).

7798399 - R/C value changes for 5V/3.3V power supply (pg. 72).

7796661 - Removed alternate FET, made some FETs primary to other APN (pp. 4, 72, 73, 76).

v1.3.0 (P4 change #212050, 03/26/2010)

7796658 - Changed backlight driver to E00 version (pg. 97).
BOM:

SMBus:

General:

SMBus:

Power Supply:

Power:

Proto 0 (ECO #0000876215, v1.0.0, P4 change #210266, 03/16/2010)

Revision History

Revision History

SYNC_MASTER=N/A

SYNC_DATE=N/A

6 OF 110

3.3.0

051-8467

6 OF 74

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(Need to add 5 GND TPs)

FUNC_TEST

Misc Voltages & Control Signals

(Need to add 27 GND TPs)

(Need 5 TPs)

(Need 4 TPs)

J6950 and 1 for shield)

(Need to add 4 GND TPs near

J9000: Internal DP Connector

(Need to add 6 GND TPs)

(Need to add 5 GND TPs)

(Need to add 6 GND TPs)

(Need to add 2 GND TPs)

(Need to add 6 GND TPs)

(Need to add 6 GND TPs)

(Need 2 TPs)

J5100: LPC+SPI Connector

J4800: SD Card Connector

(Need to add 5 GND TPs)

FUNC_TEST

FUNC_TEST

(Need 5 TPs)

J4001: AirPort / BT Connector

FUNC_TEST

FUNC_TEST

J6950: Battery Connector

J6903: Speaker Connector

FUNC_TEST

J6900: DC-In Connector

(Need 6 TPs)

J5700: IPD Flex Connector

J5600: Fan Connector

FUNC_TEST

FUNC_TEST

(Need to add 1 GND TP)

J4700: LIO Connector

J4501: SATA SSD Connector

FUNC_TEST

(Need 2 TPs)
(Need 2 TPs)

FUNC_TEST

FUNC_TEST

FUNC_TEST

Functional Test Points

NO_TEST

NO_TEST Nets

FSB Signals (Covered via CPU/MCP JTAG)

Functional Test / No Test

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(02/16/2010)

=I2C_TCON_SDA

TRUE

=I2C_TCON_SCL

TRUE

TRUE

DP_INT_ML_F_N<1>

TRUE

LED_RETURN_6

DP_INT_ML_F_P<1>

TRUE

DP_INT_ML_F_N<0>

TRUE

DP_INT_ML_F_P<0>

TRUE

DP_INT_AUX_CH_C_P

TRUE

DP_INT_AUX_CH_C_N

TRUE

DP_INT_HPD_CONN

TRUE

LED_RETURN_1

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LED_RETURN_4

TRUE

LED_RETURN_5

TRUE

PM_SLP_S3_L

TRUE

PM_SLP_S4_L

TRUE

SMC_PM_G2_EN

TRUE

PPVCORE_S0_MCP

TRUE

PPVCORE_S0_CPU

TRUE

PP0V9_S5

TRUE

PP0V9_ENET

TRUE

PP1V05_S0_MCP_PLL_UF

TRUE

PP1V05_S0

TRUE

PP1V5_S0

TRUE

PP3V3_ENET

TRUE

PP1V5R1V35_S3

TRUE

PP3V3_S0

TRUE

PP3V3_S0_HDD_R

TRUE

PP3V3_WLAN_F

TRUE

PP3V3_S3

TRUE

PP3V3_SW_DPPWR

TRUE

PP3V3_S5

TRUE

PP5V_S0

TRUE

PP3V42_G3H

TRUE

PP5V_S3

TRUE

PP5V_S3_RTUSB_A_F

TRUE

PPBUS_G3H_ISNS

TRUE

PPBUS_G3H

TRUE

PPDCIN_S5_S5

TRUE

PPVOUT_SW_LCDBKLT

TRUE

SMC_HDD_TEMP_CTL

TRUE

SATA_HDD_R2D_P

TRUE

SMC_HDD_OOB_TEMP

TRUE

SATA_HDD_R2D_N

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

PP3V3_S0_HDD_R

TRUE

TRUE

=PP1V8R1V5_S0_AUDIO

=PP3V3_S0_AUDIO

TRUE

TRUE

=PP3V42_G3H_ONEWIRE

=I2C_MIKEY_SDA

TRUE

=I2C_LIO_SCL

TRUE

=I2C_MIKEY_SCL

TRUE

=I2C_LIO_SDA

TRUE

SMC_LID

TRUE

=USB_PWR_EN

TRUE

SYS_ONEWIRE

TRUE

SMC_BC_ACOK

TRUE

TRUE

HDA_SYNC

TRUE

USB_EXTD_OC_L
HDA_RST_L

TRUE

HDA_BIT_CLK

TRUE

HDA_SDIN0

TRUE

HDA_SDOUT

TRUE

USB_CAMERA_N

TRUE

USB_CAMERA_P

TRUE

USB_EXTD_P

TRUE

TRUE

SPKRAMP_INR_P
USB_EXTD_N

TRUE

TRUE

AUD_GPIO_3

TRUE

SPKRAMP_INR_N

TRUE

AUD_I2C_INT_L

TRUE

AUD_IPHS_SWITCH_EN

TRUE

AUD_IP_PERIPHERAL_DET

LPC_AD<3..0>

TRUE

=PP5V_S0_LPCPLUS

TRUE

SD_WP

TRUE

SD_CD_L

TRUE

SD_CMD

TRUE

SD_D<7..0>

TRUE

LPCPLUS_GPIO

TRUE

SMC_NMI

TRUE

SMC_RX_L

TRUE

SMC_RESET_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

LPC_PWRDWN_L

TRUE

SPI_ALT_CS_L

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CLK

TRUE

SPIROM_USE_MLB

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SMC_MD1

TRUE

SMC_TX_L

TRUE

SMC_TRST_L

TRUE

SMC_TDO

TRUE

LPCPLUS_RESET_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

TRUE

SPI_ALT_MOSI

TRUE

=PP3V3_S5_LPCPLUS

TRUE

SD_CLK

TRUE

PP3V3_SW_SD_PWR

TRUE

=PP3V3_S3_BT

TRUE

AP_CLKREQ_Q_L

TRUE

AP_RESET_CONN_L

TRUE

PCIE_WAKE_L

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_AP_R2D_N

TRUE

WIFI_EVENT_L

TRUE

PP3V3_WLAN_F

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

PPVBAT_G3H_CONN

TRUE

SPKRAMP_R_P_OUT

TRUE

SPKRAMP_R_N_OUT

TRUE

=PP5V_S3_LIO_CONN

TRUE

=PP18V5_DCIN_CONN

TRUE

SMC_LID

TRUE

SMC_TPAD_RST_L

TRUE

=PP5V_S3_TPAD

TRUE

=PP3V42_G3H_TPAD

TRUE

=PP3V3_S3_TPAD

TRUE

USB_TPAD_CONN_P

TRUE

USB_TPAD_CONN_N

TRUE

=I2C_TPAD_SDA

TRUE

SMC_ONOFF_L

TRUE

=I2C_TPAD_SCL

TRUE

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE

TRUE

PP5V_S0

PP3V3_SW_LCD

TRUE

PPVOUT_SW_LCDBKLT

TRUE

USB_BT_P

TRUE

USB_BT_N

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_ADS_L

TRUE

FSB_A_L<35..3>

TRUE

FSB_LOCK_L

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_D_L<63..0>

TRUE

FSB_DINV_L<3..0>

TRUE

FSB_HIT_L

TRUE
TRUE

FSB_HITM_L

FSB_REQ_L<4..0>

TRUE

FSB_DSTB_L_P<3..0>

TRUE

7 OF 110

3.3.0

051-8467

7 OF 74

42 60

42 60

60 72

60 63

60 72

60 72

60 72

60 72

60 72

60

60 63

60 63

60 63

60 63

60 63

19 39 40 58

19 39 58

39 58

8

43

8

43

8

8

8

8

58

8

58 72

8

8

72

8

58 72

7

35

7

34 40

8

62

8

58 72

7 8

58

8

8

36

8

8

43 50

8

7

43 60 63

35 39

35 68

35 39

35 68

35 68

35 68

7

35

8

37

8

37

8

37

37 42

37 42

37 42

37 42

7

37 39 40 47

36 37 58

37 39

9

37 39 40

19 37 69

18 37

19 37 69

19 37 69

19 37 69

19 37 69

18 37 69

18 37 69

18 37 69

37 49 72

18 37 69

37 49

37 49 72

19 37

19 37

17 37

19 39 41 69

8

41

38

38

38 70

38 70

19 41

39 41

36 39 40 41

39 40 41 51

39 40 41

39 40 41

19 39 41

41 69

19 39 41

41 69

19 41 48

25 41 69

39 41

36 39 40 41

39 41

39 40 41

25 41

19 39 41

39 40 41

41 69

19 39 41 69

41 69

8

41

38 70

38

8

34

34

34

16 34

16 34 68

16 34 68

16 34 68

16 34 68

34 68

34 68

34 39 40

7

34 40

42 71

50

42 71

50 51

49 50

49 50

8

50

8

50

7

37 39 40 47

40 47

8

57

8

47

8

47

47 72

47 72

42 47

39 40 47

42 47

46

46

7 8

58

60

7

43 60 63

18 34 69

18 34 69

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

10 14 66

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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R

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SHEET

PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

"S5" Rails

3.30 A

0 mA

"G3Hot" (Always-Present) Rails

0.064

0.100 A

300mA

"S3" Rails

11.30 A

5.40 A

300mA

4250 mA

(OR 0.675V)

(OR 0.675V)

23.8 A

1.20 A

18 A

9.40 A

0.210 A

105 mA/241 mA

0.290 A

1.07 A + S3 + S0

"S0" Rails

1.274 A

"ENET" Rails

(OR 1.35V)

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(02/11/2010)

Power Aliases

=PP3V3_S5_P0V9ENETFET

=PP3V3_S5_P3V3S3FET

=PP3V42_G3H_SMCUSBMUX

=PPVIN_S5_SMCVREF

=PPDDR_S3_REG

=PPBUS_S0_LCDBKLT

=PPVIN_S0_MCPCORE

=PP3V3_S5_LPCPLUS

=PP5V_S3_AUDIO_AMP

PP3V3_G3_RTC

=PPVIN_S5_CPU_IMVP

VOLTAGE=8.4V
MAKE_BASE=TRUE

PPBUS_G3H_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V

PPDCIN_S5_S5

MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

=PPVIN_S3_DDRREG

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM

=PPVIN_S5_P5VP3V3

VOLTAGE=8.4V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

=PPBUS_G3H

=PPBUS_5V_S5

=PPVIN_S0_CPUVTTS0

=PPBUS_G3H_R_IN

=PP3V42_G3H_TPAD

=PP3V3_S5_MCPPWRGD

=PP3V3_S5_MCP

=PP3V3_S5_SMC

=PP3V42_G3H_CHGR
=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_REG

=PPBUS_G3H_R_OUT

=PP3V3_S0_FET

MAKE_BASE=TRUE

PP5V_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

=PP5V_S0_FET

MIN_LINE_WIDTH=0.6 MM

PP1V5_S0

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 mm

=PP1V5_S0_CPU

=PP1V8R1V5_S0_AUDIO

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_CPU

=PP1V5R1V35_S3_MCP_MEM

=PP3V3_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

=PPVIN_S0_DDRREG_LDO

=PP1V5R1V35_S0_MCPDDRFET
=PPLVDDR_S3_MEM_A

=PP5V_S3_LIO_CONN

=PP5V_S3_TPAD

=PP5V_S3_SYSLED

=PP5V_S3_REG

=PP5V_S3_MCPDDRFET
=PP5V_S3_RTUSB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_ENET

=PP3V3_S3_WLANISNS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_SMS

=PP1V05_S0_MCP_M2CLK_DLL
=PP1V05_S0_MCP_DP0_VDD
=PP1V05_S0_MCP_PE_DVDD
=PP1V05_S0_MCP_SATA_DVDD

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_DPCONN

=PP3V3_S0_PWRCTL

=PP3V3_S0_P1V5S0

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_IMVP

=PP3V3_S0_FAN

=PP3V3_S0_MCPTHMSNS

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_CSREGISNS
=PP3V3_S0_MCPCOREISNS

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

=PP3V3_S0_HDD

=PP3V3_S0_HDDISNS

=PP3V3_S0_BKLTISNS

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_DEBUGROM
=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_SMC

=PP3V3_S0_AUDIO

=PP18V5_DCIN_CONN

=PP1V05_SW_MCP_FSB

=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_MCP_FSB

=PP1V05_S0_XDP

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_PLL_UF

=PP5V_S0_MCPFSBFET

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP

=PP3V3_S0_MCP_HVDD

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_XDP

=PP5V_S0_BKL
=PP5VR3V3_S0_DPCADET

=PP1V5_S0_REG

=PPCPUVTT_S0_REG

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

=PP1V05_S0_MCP_PLL_OR

=PPVTT_S0_DDR_LDO

=PPMCPCORE_S0_REG

=PPVCORE_S0_CPU_REG

=PPDDRVTT_S0_MEM_B

=PPDDRVTT_S0_MEM_A

=PPVCORE_S0_MCPGFXFET

=PPVCORE_S0_MCP

=PPVCORE_S0_CPU

=PP3V3R1V5_S0_MCP_HDA

=PP1V5_S0_MCP_PLL_VLDO

=PP5V_S0_CPUVTTS0

=PP5V_S0_MCPREG

=PP5V_S0_CPU_IMVP

=PP5V_S0_LPCPLUS
=PP5V_S0_FAN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=0.75V

PPDDRVTT_S0

VOLTAGE=1.05V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_MCP

=PP0V9_ENET_MCP_RMGT

=PP3V3_S5_P0V9S5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP0V9_ENET

MAKE_BASE=TRUE

VOLTAGE=0.9V

=PP0V9_ENET_FET

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_SMBUS_SMC_MGMT
=PP3V3_S5_ROM

=PP0V9_S5_MCP_VDD_AUXC
=PP0V9_ENET_P0V9ENETFET

=PP3V3_S5_TPAD
=PP3V3_SMC_PME

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S5

PP0V9_S5

VOLTAGE=0.9V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

=PP3V3_S3_DBGLEDS

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

MIN_NECK_WIDTH=0.25 mm

=PP3V3_S3_FET

=PP0V9_S5_REG

=PP3V3_S5_REG

=PP3V3_ENET_FET_R

PPDDRVREF_S3

VOLTAGE=0.75V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

=PPLVDDR_S3_MEM_B

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm

PP1V5R1V35_S3

MAKE_BASE=TRUE

=PP5V_S3_P5VS0FET

=PP5V_S3_DDRREG

=PP3V3_S3_CARDREADER

=PP3V3_S3_MCP_GPIO
=PP3V3_S3_VREFMRGN
=PP3V3_S3_BT
=PP3V3_S3_WLAN

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_TPAD

=PP3V3_S3_PDCISENS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S3

=PPVTT_S3_DDR_BUF

=PP3V42_G3H_ONEWIRE

=PP3V3_S0_LCD

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_P3V3S0FET

=PP3V3_S5_VMON

=PP3V3_S5_MCP_GPIO

8 OF 110

3.3.0

051-8467

8 OF 74

59

59

36

40

53

64

55

7

41

49

19 20 23

54

7

7

51

53

7

52

7

43 50 51

57

56

44

7

47

25

20 23

39 40

51 58

58

42

44

50

44

59

7

58 59

7

58 72

11 12

7

37

7

58

10 11 12

15

23

18 20 23

53

21

26 27 30

7

50

7

57

40

52

21

36

7

43

42

15 23

17 24

20 23

20 23

63

62

58

57

57

54

46

45

45

44

44

44

7

58 72

35

43

43

42

42

42

41

42

40

7

37

7

50

20 23

23

57

14 20 23

13

7

23

22

23

20 23

20 23

17 18 19

13

63

62

57

56

7

43

57

53

55

54

32

32

22

20 23

11 12 65

19 23

57

56

55

54

7

41

46

7

43

20 23

57 58

7

59

59

42

48

20 23

59

47

40

7

58 72

7

50

7

59

57

52 58

9

28 29 31

7

72

59

53

38

19

33

7

34

34

43

7

47

53

7

33 53

7

37

60

62

59

58

18 19

OUT
OUT
OUT
OUT

OUT
OUT

BI

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT

BI

BI

BI

BI

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DisplayPort Pogo

806-1176

Digital Ground

(Provides PCB support for small finger above J9400)

DisplayPort PCB Stiffener

USB/SD Card Pogo

CPU Aliases

DisplayPort Aliases

External DisplayPort Signals

Internal DisplayPort Signals

MCPCOREISNS Signals

Charger Signal

LVDS Aliases

Unused PCI-E Lanes

PCI-E Aliases

Unused SATA ODD Signals

SATA Aliases

Unused USB Ports

USB Aliases

Misc MCP89 Aliases

CPU Heat Sink Mounting Bosses

870-1938

Fan Boss

860-1327

EMI I/O Pogo Pins

X21 Boss

860-1327

4x 860-1327

860-1327

SSD Boss

4x 860-1327

MCP Heat Sink Mounting Bosses

Plated Board Slot

Ethernet Aliases

870-1938

18 70

18 70

18 70

18 70

18 70

18 70

18 70

18

1/20W

5%

201

MF

10K

R0981

10K

1/20W

5%

201

MF

R0980

7

37 39 40 51

PLACE_NEAR=U7980.A1:5MM

0

MF-LF

402

5%

1/16W

R0911

8

18

1/20W

10K

MF

201

5%

R0982

R0984

1/20W

5%

201

MF

10K

MF

10K

201

5%
1/20W

R0983

10K

MF
201

5%
1/20W

R0985

SM

CRITICAL

POGO-2.0OD-3.6H-K86-K87

ZS0905

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

ZS0906

STDOFF-4.5OD1.9H-SM

Z0915

STDOFF-4.5OD1.8H-SM

Z0910

STDOFF-4.5OD1.8H-SM

Z0911

STDOFF-4.5OD1.8H-SM

Z0912

STDOFF-4.5OD1.8H-SM

Z0913

STDOFF-4.5OD1.8H-SM

Z0905

STDOFF-4.5OD1.9H-SM

Z0914

18 68

18 68

18 68

18 68

17 68

17 68

17 68

17 68

17

17

17

61

17

17 68

17 68

61

61

17 68

17 68

62 72

62 72

60 72

60 72

62 72

62 72

61

61

60 72

60 72

60

62

62

17

9

17 60

17

17

17

63

9

17 60

64

18 69

18 69

18 69

18 69

16 68

16 68

16

16

16

16

16

17

17

17

17

17

17

17

17

10 66

14

14

16

15 67

15 67

15 67

15 67

15 67

15 67

19

55

55

44

44

STDOFF-4.5OD1.8H-SM

Z0909

STDOFF-4.5OD1.8H-SM

Z0907

STDOFF-4.5OD1.8H-SM

Z0906

STDOFF-4.5OD1.8H-SM

Z0908

SL-2.3X3.9-2.9X4.5

TH-NSP

SL0900

Signal Aliases

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

ENET_RX_CTRL
ENET_MDIO

ENET_CLKREQ_L

DP_IG_ML1_P<2..3>

LCD_IG_PWR_EN

MAKE_BASE=TRUE

CPU_PECI_MCP

CPU_BSEL<0:2>

MAKE_BASE=TRUE

DP_IG_ML0_P<0..3>
DP_IG_ML0_N<0..3>

DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N

DP_IG_HPD0

DP_CA_DET

DP_AUX_CH_C_N
DP_AUX_CH_C_P

DP_IG_ML1_P<0..1>
DP_IG_ML1_N<0..1>

DP_IG_ML1_N<2..3>

DP_IG_AUX_CH1_P

DP_IG_HPD1

DP_IG_AUX_CH1_N

ENET_RXD_PD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

ENET_RXCLK_PD

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET_FET

=PP3V3_ENET_FET

MAKE_BASE=TRUE

SMC_BC_ACOK

=CHGR_ACOK

TP_DP_INT_MLP<2..3>

MAKE_BASE=TRUE

TP_DP_INT_MLN<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ENET_CLKREQ_L

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

ENET_ENERGY_DET

MCP_RGMII_VREF

ENET_CLK125M_RXCLK

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

=PP3V3_ENET_FET_R

LCD_BKLT_EN

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_INT_HPD

DP_INT_AUX_CH_N

MAKE_BASE=TRUE

DP_INT_AUX_CH_P

MAKE_BASE=TRUE

DP_INT_ML_N<0..1>

MAKE_BASE=TRUE

DP_INT_ML_P<0..1>

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_P

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_N

MAKE_BASE=TRUE

DP_EXT_HPD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_CA_DET

MAKE_BASE=TRUE

DP_EXT_AUX_CH_N

DP_EXT_AUX_CH_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_ML_N<0..3>

MAKE_BASE=TRUE

DP_EXT_ML_P<0..3>

=MCP_BSEL<0:2>

MAKE_BASE=TRUE

MCPCORES0_VO

MAKE_BASE=TRUE

MCPCORES0_ISP_R

=MCPCOREISNS_N
=MCPCOREISNS_P

NC_LVDS_IG_A_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_LVDS_DDC_DATA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_LVDS_DDC_CLK

NO_TEST=TRUE

NC_PEG_R2DCP<5:4>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2DCN<5:4>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<5:4>

NO_TEST=TRUE

NC_PEG_D2RP<5:4>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_CLK100MP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_CLK100MN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PEG_CLKREQ_L

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

NO_TEST=TRUE

NC_USB_MINIP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_MININ

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXTCN

NO_TEST=TRUE

NC_USB_EXTCP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREFTP_MCP_RGB_DAC_VREF

TP_MEM_A_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKN<1>

TP_MEM_A_A<15>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5

MAKE_BASE=TRUE

=MCP_IFPA_TXC_P

=MCP_IFPA_TXD_P<0..3>

=MCP_IFPA_TXC_N

=MCP_IFPB_TXC_N

=MCP_IFPB_TXC_P

=MCP_IFPA_TXD_N<0..3>

=MCP_IFPB_TXD_N<0..3>

=MCP_IFPB_TXD_P<0..3>

=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

=PEG_D2R_P<5:4>

=PEG_D2R_N<5:4>

=PEG_R2D_C_P<5:4>

=PEG_R2D_C_N<5:4>

PEG_CLK100M_P

PEG_CLKREQ_L

SATA_ODD_R2D_C_P

PEG_CLK100M_N

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P
SATA_ODD_D2R_N

USB_MINI_P
USB_MINI_N

USB_EXTC_N

USB_EXTC_P

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_A<15>

MEM_A_A<15>

MCP_MEM_VDD_SEL_1V5

LCD_IG_BKLT_EN

LCD_IG_PWR_EN

LCD_IG_BKLT_PWM

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.1 mm

VOLTAGE=0V

GND

SM-SP

MT0900

STIFFENER-K16-K99

NO STUFF

9 OF 110

3.3.0

051-8467

9 OF 74

121

2

1 2

1

2

1

2

1

2

1

2

1 1

1

1

1 1

1

1 1

1

1

1

1

1

1

59

17

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN

IN

IN
IN

IN

IN

OUT

BI
BI
BI
BI

OUT

IN
IN

A6*

BR0*

BPM0*

DBR*

DEFER*

DBSY*

A7*

A15*

A14*

REQ2*

A17*
A18*

PREQ*

IERR*

BPRI*

BNR*

A4*

TRST*

LINT1

TEST2

TEST4

A16*

A20M*

A3*

A30*
A31*
A32*

A34*
A35*

A5*

A8*

ADSTB0*

ADSTB1*

BCLK1

BPM2*
BPM3*

FERR*

HIT*

HITM*

IGNNE*

LINT0

RSVD7

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

TEST1

TEST3

TEST5
TEST6

PROCHOT*

REQ0*
REQ1*

REQ3*
REQ4*

SMI*

TCK

TDO

THERMTRIP*

THRMDA
THRMDC

TMS

PRDY*

BPM1*

RS2*

RS1*

RS0*

RESET*

DRDY*

ADS*

A19*
A20*
A21*

A23*

A22*

A24*
A25*
A26*
A27*
A28*
A29*

A33*

STPCLK*

A13*

A12*

A11*

BCLK0

TDI

TRDY*

LOCK*

INIT*

A10*

A9*

(1 OF 8)

XDP/ITP SIGNALS

ADDR GROUP0ADDR GROUP1

THERMAL

H CLK

ICH

CONTROL

D11*

D7*

D6*

D5*

D4*

D3*

D17*

D16*

DINV0*

DSTBP0*

DSTBN0*

D10*

D2*

SLP*

PWRGOOD

PSI*

GTLREF

DSTBP3*

DSTBP2*

DSTBN3*

DSTBN2*

DSTBN1*

DPWR*

DPSLP*

DPRSTP*

DINV3*

DINV2*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D53*

D52*

D51*

D50*

D49*

D48*

D47*

D46*

D45*

D44*

D43*

D42*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

D31*

D30*

D26*

D25*

D24*

D23*

D22*

D21*

D20*

D13*

D12*

D1*

D0*

COMP3

COMP2

COMP1

COMP0

BSEL2

BSEL1

BSEL0

D27*

D29*

D8*

DINV1*

DSTBP1*

D28*

D14*
D15*

D9*

D19*

D18*

D41*

(2 OF 8)

DATA GRP 3

DATA GRP1

MISC

DATA GRP 0

DATA GRP 2

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE_NEARs:

C1014.1:

R1006.1:

R1005.2:

PLACE_NEARs:

R1020.1:
R1021.1:
R1022.1:
R1023.1:

CPU JTAG Support

54.9

1%

201

1/20W

MF

R1000

68

5%

201

1/20W

MF

R1002

U1000.AW43:12.7 mm

1%

1K

201

1/20W
MF

R1005

1%

U1000.AW43:12.7 mm

2K

201

1/20W
MF

R1006

54.9

1%

U1000.AF2:12.7 mm

201

1/20W

MF

R1023

27.4

1%

U1000.AE1:12.7 mm

201

1/20W
MF

R1022

54.9

1%

U1000.AD44:12.7 mm

201

1/20W

MF

R1021

27.4

1%

U1000.AE43:12.7 mm

201

1/20W
MF

R1020

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

14 54 66

14 66

14 66

14 66

13 14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

9

66

9

66

9

66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

7

14 66

14 66

14 66

14 66

14 66

14 66

14 66

7

14 66

7

14 66

7

14 66

13 66

13 66

13 66

13 66

13 66

13 66

10 13 66

14 40 66

45 72

14 40 66

14 66

13 14 66

14 66

14 66

14 66

14 66

10 13 66

10 13 66

10 13 66

10 13 66

45 72

14 66

14 66

14 66

14 66

14 66

14 66

14 66

NO STUFF

5%

0

201

1/20W

MF

R1010

NO STUFF

1K

5%

201

1/20W

MF

R1011

54.9

1%

201

1/20W

MF

R1001

1%

54.9

201

1/20W

MF

R1090

1%

54.9

201

1/20W

MF

R1091

1%

54.9

201

1/20W

MF

R1093

7

14 66

7

14 66

7

14 66

7

14 66

MF

54.9

1%

201

1/20W

R1094

NO STUFF

1K

5%

201

1/20W
MF

R1012

U1000.AE41:12.7 mm

NO STUFF

X5R

10%

0.1UF

201

6.3V

C1014

1/20W

1%

54.9

PLACE_NEAR=J1300.52:12.7 mm

201

MF

R1092

13 25

14 66

14 66

NEED_TP=TRUE
NEED_TP=TRUE

OMIT_TABLE

BGA

PENRYN-SFF

CDC-QKWH-QS-1.2-10W-800-R0-1M

U1000

OMIT_TABLE

CDC-QKWH-QS-1.2-10W-800-R0-1M

BGA

PENRYN-SFF

U1000

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

CPU FSB

CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L

CPU_COMP<0>

XDP_TMS

FSB_A_L<23>

FSB_A_L<7>

FSB_REQ_L<3>
FSB_REQ_L<4>

CPU_INTR

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_BREQ0_L

CPU_IERR_L

FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L

XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_TDI

CPU_THERMD_N

PM_THRMTRIP_L

CPU_PROCHOT_L

XDP_BPM_L<5>

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_ADS_L
FSB_BNR_L

TP_CPU_PSI_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

XDP_TDO

XDP_TCK

FSB_CPURST_L

CPU_INIT_L

FSB_BPRI_L

TP_CPU_RSVD_J9
TP_CPU_RSVD_F4

TP_CPU_RSVD_V2
TP_CPU_RSVD_Y2
TP_CPU_RSVD_AG5

CPU_TEST1

FSB_D_L<19>

FSB_D_L<18>

CPU_FERR_L

FSB_D_L<11>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<17>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<0>

FSB_D_L<10>

FSB_D_L<2>

FSB_DSTB_L_N<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<1>

FSB_D_L<0>

CPU_COMP<1>

CPU_BSEL<2>

FSB_D_L<27>

FSB_D_L<29>

FSB_D_L<8>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

FSB_D_L<28>

FSB_D_L<14>
FSB_D_L<15>

FSB_D_L<9>

FSB_REQ_L<2>

CPU_A20M_L

FSB_A_L<34>

FSB_ADSTB_L<1>

CPU_IGNNE_L

FSB_REQ_L<1>

CPU_STPCLK_L

FSB_A_L<17>

FSB_A_L<12>

FSB_ADSTB_L<0>

FSB_A_L<27>

FSB_A_L<32>
FSB_A_L<33>

FSB_A_L<11>

FSB_A_L<28>

CPU_NMI
CPU_SMI_L

FSB_A_L<4>

FSB_A_L<15>
FSB_A_L<16>

FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>

FSB_A_L<29>
FSB_A_L<30>

FSB_A_L<35>

FSB_A_L<13>

FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<14>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<22>

FSB_DINV_L<0>

FSB_D_L<16>

CPU_COMP<3>

CPU_COMP<2>

FSB_A_L<10>

FSB_REQ_L<0>

FSB_A_L<3>

CPU_BSEL<1>

CPU_TEST2

CPU_BSEL<0>

=PP1V05_S0_CPU

XDP_TDO

XDP_TDI

TP_CPU_RSVD_AL5

CPU_GTLREF

FSB_RS_L<0>

FSB_LOCK_L

CPU_TEST4

FSB_HITM_L

FSB_HIT_L

XDP_BPM_L<3>

XDP_TRST_L

CPU_THERMD_P

XDP_TMS

XDP_TRST_L

XDP_TCK

FSB_A_L<18>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<24>

FSB_A_L<31>

TP_CPU_RSVD_H8

XDP_DBRESET_L

CPU_TEST4

CPU_TEST1
CPU_TEST2

TP_CPU_TEST5
TP_CPU_TEST6

TP_CPU_TEST3

10 OF 110

3.3.0

051-8467

10 OF 74

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1

2

1 2

1 2

1 2

1 2

1

2

2

1

1 2

T4

M2

AY8

J7

N5

J1

AA1

AB2

AE5

U1

AN1
AK4

AV2

B40

L5

J5V4

AV8

C5

D40

AE41

AC1

C7

P2

AJ1
AL1
AM2

AP2
AR1

W1

AB4

Y4

AN5

C35

BA5
AY2

D4

H2
F2

F10

C9

J9
F4
H8
V2
Y2
AG5
AL5

E37

C43

AY10
AC43

D38

R1
R5

P4
W5

E5

AV4

AU1

B10

BB34
BD34

AW5

AV10

BA7

K4

H4

K2

G5

F38

M4

AG1
AT4
AK2

AH2

AT2

AF4
AJ5
AH4
AM4
AP4
AR5

AU5

F8

AA5

AD4

AD2

A35

AW7

L1

N1

D8

AC5

T2

T40

E41

G39

H44

H40

J43

V40

P44

P40

J41

K40

N41

E43

D10

E7

BD10

AW43

AY38

AL43

AY40

AK44

U43

C41

B8

G7

BC37

AJ41

AU43

BA35

BB40

BA41

BC39

BC35

AT40

AY36

BB38

BA37

AR41

AW41

AU41

AV40

AT44

AV38

AL41

AN41

AP40

AG43

AK40

AM40

AM44

AH44

AF44

AG41

AJ43

AF40

AH40

AR43

AP44

T44

Y44

AD40

AB40

AA41

U41

N43

W41

R41

G41

M40

G43

F40

AF2

AE1

AD44

AE43

B38

C37

A37

AC41

Y40

L41

R43

W43

AA43

M44
L43

K44

AB44

V44

AN43

66

66

10

66

66

66

10

8

11 12

10 13 66

10 13 66

33 66

10

10 13 66

10 13 66

10 13 66

10

10

10

VCCA

VID

VCC

VCC

VCCP

(3 OF 8)

VSSSENSE

VCCSENSE

VCC VCC

(7 OF 8)

VCCP VCCP

(8 OF 8)

VSS VSS

(6 OF 8)

VSSVSS

(4 OF 8)

VSSVSS

(5 OF 8)

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

18 A (CULV Design Target)

17.6 A (CULV ICC_Max)

4500 mA (before VCC stable)
2500 mA (after VCC stable)

(CPU INTERNAL PLL POWER 1.5V)

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

BGA

OMIT_TABLE

U1000

BGA

CDC-QKWH-QS-1.2-10W-800-R0-1M

PENRYN-SFF

OMIT_TABLE

U1000

BGA

PENRYN-SFF

CDC-QKWH-QS-1.2-10W-800-R0-1M

OMIT_TABLE

U1000

54 66

PLACE_NEAR=U1000.BD12:25.4 mm

100

1%
1/20W
MF
201

R1100

PLACE_NEAR=U1000.BC13:25.4 mm

100

1%
1/20W
MF
201

R1101

54 66

12 54 66

12 54 66

12 54 66

12 54 66

12 54 66

12 54 66

12 54 66

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

CPU Power & Ground

=PPVCORE_S0_CPU

CPU_VID<1>
CPU_VID<2>

CPU_VID<6>

CPU_VID<5>

CPU_VID<3>

=PPVCORE_S0_CPU

CPU_VID<4>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0>

11 OF 110

3.3.0

051-8467

11 OF 74

T32
R33
P32

AP32

AR33

AE33

N33

H32

AT30

AT28

AM30

AM26

AP26

AF30

F32

AF32

AT34

F28

T26

AD28

AH28

AV26

B34

D34

N37

L37

AK38

BD8

BC7

BB10

BB8

BC5

M32

K32

V32
U33

AC33
AB32
AA33

Y32

AH32

AL33

AV32
AU33
AT32

BD32
BB32

B26
B30
B28
H26
F26
D26
H28
H30

F30
D30
D28
M26
K26
M28
M30
K28
K30
V26

P26
V28
V30
T28
T30
P28

P30
AD26
AB26

Y26

AB30
Y28
Y30
AK26
AH26
AF26
AK28
AK30

AH30
AF28

AP28
AP30
AM28

AY26

AT26
AY28

AV28
AV30

BB26
BD28

K38
J37
W37
V38

R37
P38
AC37
AB38
AA37

AG37
AF38

AJ37

U37

BD26

AY30

AN33
AM32

AK32
AJ33

AG33

W33

J33

AD32

L33

G33

BB4
AY4

BD12

BC13

AB28

AD30

AY32

BB14

BD14

AP14

BB18

BB16

K16
K18

D24

AF24

AF22

AH24

AK24

BB28

BD30

T22
T24

M18

AH22

AY20

BB30

B24
B22
H22
H24
F22

D22

K22

AD22
AD24

AB24

Y22
Y24

AK22

M22
M24

AB22

AP22
AP24
AM22
AM24
AY22
AY24
AV22
AV24
AT22
AT24
BD22
BD24
BB22
BB24

B20
B18
B16
H20
F20
D20
H16
H18
F16
F18
D18
D16
M20

K20
M16

T20
P20
V16
V18
T16
T18
P16
P18
AD20
AB20
Y20
AD16
AD18
AB16
AB18
Y16
Y18
AK20
AK16
AK18
AH20
AF20
AH16
AH18
AF16
AF18
AP20
AM20
AP16
AP18
AM16
AM18

AV20
AT20
AY16
AY18
AV16
AV18
AT16
AT18
BD20
BB20
BD16
BD18

AM14
AY14
AV14
AT14

V20

K24
V22
V24

P22
P24

F24

AC11

K36

G35

H36

F34

AK14
AJ11

AN37

B12

B14

AN35

AE35

AJ35

AK36

AC35

U35

V36

W35

J35

N35

AE37

L35

P36

AB36

AA35

AF36

AG35

AP36

AL35

C13

H12
H14
G11

F12
F14
E11
E13
D14
D12
K10
N11
N13
M14

L13
K12
K14
J11
J13
V10
P10
W11
W13
V12

U11
U13
T14
R11

R13
P12
P14
AB10
AD14

AB12
AB14
AA11
AA13
Y14
AK10
AF10
AK12

AH14
AG11
AG13
AF12
AF14
AE11
AE13
AP10
AR11
AR13

AN11
AN13
AL11
AL13
AU11
AU13
N7
N9
L7
L9

W9
U7
U9
R7
R9
AC7
AC9
AA7
AA9
AJ7

AE7
AE9
AR7
AR9
AN7
AN9
AL7
AL9
A33
A13

AG7
AG9

G13

L11

V14

AC13

AJ13

AP12

W7

AJ9

C33

E33

R35

E35
D32

F36

B32

AL37

AP38

AK6

AF6

AP6

AT8

AT6

AU9

AV6

AU7

AW9

AY6

AM8

AF8

AH8

Y8

AL3

AU3

A7

A5

A9

A11

A15

A19

A17

A25

A23

A21

A29

A27

A31

A41

A39

BA1

AW1

E1

G1

BA3

BB2

BC3

BD4

AW3

AN3

AR3

AE3

AA3

AC3

R3

U3

W3

J3

L3

N3

D2

E3

G3

B4

C3

BA9

BB6

BC9

BD6

AP8

AH6

Y6

AK8

AM6

AJ3
AG3

AW35

G25

G23

G21

C25
C23
C21

BA29

BA27

BA31
BC27
BC29

BC31

AU29

AU27

AW27
AW29

AW31
AU31

AL29

AN29
AL27

AN31
AL31
AN27

AR27
AR29

AE27
AE29
AR31

AG27
AG29

AE31
AJ27
AJ29

AJ31
AG31

AA29

AC29
AA27

AC27

AA31

AC31

R27
R29

R31
U27
U29

U31

W29

J29
W31
W27

J27

L29

N27
N29
L27

L31
J31

N31

E27
E29

G29

G27

E31

C27
G31

BA33
C31
C29

BB36
BC33

AV34
AU35
BD36

AW33

AY34

AV36

AP34
AM34

AB42

AR37

AE39

AG39

AH38

Y38

AA39

P42

AD42

Y42
AK42
AH42
AF42

AM42
AY42

B42

AM36

AR35

AH34

AH36

AK34

Y34

AB34

AD34

AF34

Y36

AD36

P34

T34

V34

T36

K34

M34

M36

H34

D36

B36

BA39

BC41

BD40

BD38

AT38

AU39

AU37

AW39

AW37

AL39

AM38

AN39

AR39

AJ39

AC39

R39

T38

W39

J39

L39

M38

N39

E39

G37

H38

C39

BA43

BB42

AY44

AV44

AT42

AV42

V42

M42

F44

D44

K42

T42

AP42

H42

D42

F42

U39

AD38

AT36

N21
N23

W25

J23

AN25

AN23

AN21

AR25

AR23

L21
L23

M10

E15

G15

C11

C15

BA17

BC17

AU19

AU17

AW19

AW17

AE17

L15

AB8

AB6

AD8

AD6

P8

P6

T8

T6

V8

V6

U5

K8

K6

M8

M6

D6

E9

F6

G9

H6

B6

BA13

BA11

BB12

BC11

BA15

BC15

AT12

AV12

AW13

AW11

AY12

AU15

AW15

AT10

AM12

AL15

AN15

AR15

AM10

AH12

AE15

AG15

AJ15

AH10

Y12

AD12

AA15

AC15

Y10

AD10

T12

R15

U15

W15

T10

M12

J15

N15

H10

BA19

BC19

AG19

U17

G19

G17

AU21

AA25

U21

AR19

AG17

AJ19

AJ17

AA19

AA17

AC19

AC17

R19

R17

U19

W19

W17

J19

J17

L19

L17

N19

N17

E19

E17

C17

C19

BA25

BA23

BA21

BC25

BC23

BC21

AU25

AU23

AW25

AL25

AL23

AL21

AE21

AG25

AJ21

AA23

AA21

AC25

AC23

AC21

R25

R23

R21

U25

U23

W23

W21

J25

J21

L25

E21

AR17

N25

AL19

AL17

AN19

AN17

AE19

E25

E23

AW23

AW21

AG23

AG21

AJ25

AJ23

AE23
AE25
AR21

1

2

1

2

8

11 12 65

8

11 12 65

8

12

8

10 11 12

8

10 11 12

IN

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LAYOUT NOTE:

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

PLACE ON OPPOSITE SIDE OF CPU

CPU VCORE VID CONNECTIONS

VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE:

PLACE C1281 NEAR PIN B34 OF U1000

PLACE C1291-C1296 CLOSE TO FSB DATA PINS

PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS

PLACE C1290 CLOSE TO CPU

1x 270uF, 12x 2.2uF

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

LAYOUT NOTE:

4x 270uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402

CPU VCORE HF AND BULK DECOUPLING

PLACE ON SAME SIDE AS CPU

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

LAYOUT NOTE:

10UF

603

X5R

6.3V

20% 20%

6.3V
X5R
603

10UF

CRITICAL

C1216

10UF

603

X5R

6.3V

20%

CRITICAL

C1201

20%

6.3V
X5R
603

10UF

C1202

10UF

603

X5R

6.3V

20%

C1203

20%

6.3V
X5R
603

10UF

CRITICAL

C1204

10UF

603

X5R

6.3V

20%

CRITICAL

C1205

20%

6.3V
X5R
603

10UF

CRITICAL

C1206

10UF

603

X5R

6.3V

20%

CRITICAL

C1207

20%

6.3V
X5R
603

10UF

CRITICAL

C1208

20%

6.3V
X5R
603

10UF

CRITICAL

C1209

10UF

603

X5R

6.3V

20%

CRITICAL

C1229

20%

6.3V
X5R
603

10UF

CRITICAL

C1228

10UF

603

X5R

6.3V

20%

CRITICAL

C1227

20%

6.3V
X5R
603

10UF

CRITICAL
OMIT_TABLE

C1226

10UF

603

X5R

6.3V

20%

CRITICAL

C1225

20%

6.3V
X5R
603

10UF

CRITICAL

C1224

10UF

603

X5R

CRITICAL

C1223

20%

6.3V
X5R
603

10UF

CRITICAL
OMIT_TABLE

C1214

20%

6.3V
X5R
603

10UF10UF

X5R

6.3V

20%

10UF

603

X5R

6.3V

20%

CRITICAL

C1220

CRITICAL

603

X5R

6.3V

20%

C1231

10UF

603

X5R

6.3V

20%

OMIT_TABLE

CRITICAL

C1230

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1249

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1259

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1248

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1258

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1246

402-LF

CERM

6.3V

20%20%

6.3V
CERM
402-LF

2.2UF

CRITICAL

C1256

2.2UF

402-LF

CERM

20%

CRITICAL
OMIT_TABLE

C1245

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1244

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1255

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1254

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1243

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1253

20%

6.3V
CERM

2.2UF

CRITICAL
OMIT_TABLE

C1242

2.2UF

402-LF

CERM

20%

CRITICAL
OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1252

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1251

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1250

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL

C1267

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1266

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1265

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1264

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1263

20%

6.3V
CERM
402-LF

2.2UF

CRITICAL
OMIT_TABLE

C1262

2.2UF

402-LF

CERM

6.3V

20%

CRITICAL
OMIT_TABLE

C1261

2.2UF

402-LF

6.3V

20%

CRITICAL

C1260

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1291

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1292

2.2UF

402-LF

CERM

6.3V

20%

OMIT_TABLE

C1293

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1294

20%

6.3V
CERM
402-LF

2.2UF

OMIT_TABLE

C1295

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1296

OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

C1283

20%

6.3V
CERM
402-LF

2.2UF

OMIT_TABLE

C1288

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1287

20%

6.3V
CERM
402-LF

2.2UF

OMIT_TABLE

C1286

OMIT_TABLE

20%

6.3V
CERM
402-LF

2.2UF

C1285

OMIT_TABLE

2.2UF

402-LF

CERM

6.3V

20%

C1284

CRITICAL
270UF

TANT
CASE-B4-SM

20%
2V

CRITICAL

270UF

TANT
CASE-B4-SM

20%
2V

C1272

CRITICAL

2V

20%
TANT

270UF

C1271

CRITICAL

270UF

TANT

CASE-B4-SM

20%

2V

C1290

CRITICAL

270UF

TANT
CASE-B4-SM

20%
2V

11 54 66 66

10UF

603

X5R

6.3V

20%

CRITICAL

C1213

20%

6.3V
X5R
603

10UF

CRITICAL

C1212

10UF

603

X5R

6.3V

20%

CRITICAL

C1211

10UF

603

X5R

6.3V

20%

CRITICAL

C1219

603

6.3V

CRITICAL

10UF

603

X5R

6.3V

20%

CRITICAL

C1215

X5R

20%

CRITICAL
OMIT_TABLE

C1217

20%

6.3V
X5R
603

10UF

CRITICAL
OMIT_TABLE

C1218

10%
10V
X5R
201

0.01UF

C1281

OMIT_TABLE

20%

6.3V
X5R
603

10uF

C1280

SYNC_DATE=(02/11/2010)

SYNC_MASTER=(K99_MLB)

CPU Decoupling & VID

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

IMVP6_VID<0..6>

CPU_VID<0..6>

MAKE_BASE=TRUE

C1247

C1222

CRITICAL

C1210

C1257

OMIT_TABLE

CRITICAL

6.3V

C1221

CRITICAL

CRITICAL CRITICAL

C1200

10UF

20%
X5R

10UF

603

C1273

10UF

6.3V
603

C1240

6.3V
402-LF

OMIT_TABLE

2.2UF

OMIT_TABLE

CERM

OMIT_TABLE

C1270

CASE-B4-SM

OMIT_TABLE

CRITICAL

20%

6.3V

C1241

2.2UF

NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF

NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF

NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF

NO STUFF

OMIT_TABLE OMIT_TABLE

CRITICAL

12 OF 110

3.3.0

051-8467

12 OF 74

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

8

11

8

10 11

8

11 65

IN

BI

BI

BI
BI

OUT

IN

BI

IN

IN
IN

IN
IN

OUT
OUT
OUT

OUT

NC

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OBSDATA_B3 OBSDATA_D3

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TDI

OBSDATA_A3

SCL

VCC_OBS_AB

OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSDATA_A2

OBSFN_B0

PWRGD/HOOK0

HOOK3

SDA

OBSDATA_A0

518S0774

OBSFN_C1

NOTE: This is not the standard XDP pinout.

OBSDATA_B2

OBSDATA_A1

Direction of XDP adapter flex

Please place J1300 within 1" of
board edge with odd-numbered pins
facing edge. Avoid any tall
components between J1300 and edge.

TCK0

HOOK1

HOOK2

OBSDATA_C0

OBSFN_C0

OBSFN_D1

OBSDATA_D1

ITPCLK/HOOK4

VCC_OBS_CD

ITPCLK#/HOOK5

TMS

Use with 920-0782 Adapter Flex to support chipset debug.

TRSTn

TCK1

RESET#/HOOK6

OBSDATA_C3

TDO

OBSDATA_C1

OBSDATA_C2

OBSDATA_D0

OBSDATA_D2

OBSFN_A1

OBSFN_A0

XDP_PRESENT#

DBR#/HOOK7

OBSFN_D0

Micro2-XDP Connector

10 14 66

1K

XDP

1/20W

MF

201

5%

R1399

42

42

1%

XDP

54.9

201

1/20W

MF

R1315

XDP

10%
X5R

0.1UF

201

6.3V

C1300

201

6.3V

0.1UF

XDP

X5R

10%

C1301

10 66

10 66

10 66

10 14 66

PLACEMENT_NOTE=Place close to CPU to minimize stub.

5%

1K

XDP

1/20W

MF

201

R1303

10 66

10 66

10 66

10 66

14 66

14 66

10 66

10 66

10 66

10 25

19

10 66

19

F-ST-SM-HF

XDP_CONN
CRITICAL

DF40C-60DS-0.4V

J1300

eXtended Debug Port (Micro-XDP)

SYNC_DATE=03/01/2010

SYNC_MASTER=K99_MLB

=I2C_XDP_SCL

=I2C_XDP_SDA

CPU_PWRGD XDP_PWRGD

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_TCK

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2

XDP_BPM_L<3>
XDP_BPM_L<2>

XDP_BPM_L<1>
XDP_BPM_L<0>

TP_XDP_OBSDATA_D3

TP_XDP_OBSDATA_D2

TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D0

TP_XDP_OBSDATA_C3

TP_XDP_OBSDATA_C2

TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C0

JTAG_MCP_TDO

XDP_TRST_L

JTAG_MCP_TMS

TP_XDP_OBSDATA_B3

TP_XDP_OBSFN_B1

XDP_OBS20

=PP1V05_S0_XDP

XDP_BPM_L<5>
XDP_BPM_L<4>

TP_XDP_OBSDATA_B0

TP_XDP_OBSFN_B0

FSB_CPURST_L

FSB_CLK_ITP_P

XDP_TMS

XDP_TDI

XDP_TDO

XDP_DBRESET_L

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TDI

JTAG_MCP_TRST_L

=PP3V3_S0_XDP

13 OF 110

3.3.0

051-8467

13 OF 74

1 2

1

2

2

1

2

1

1 2

3

1

7

5

11

9

13

17

15

23

19
21

25
27
29

33

31

35

39

37

41
43
45
47
49
51
53

59

57

55

38
40

36

32
34

30

28

26

24

22

16
18
20

10

14

12

6
8

2
4

56
58
60

54

52

50

48

46

44

42

19

19

8

66

19

19

8

IN
IN
IN

IN

OUT

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

IN
BI

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT
OUT

IN

BI
BI

OUT

IN

IN

IN

IN

IN

IN

IN

CPU_A8*

CPU_DSTBN0*

CPU_DSTBP1*

CPU_D6*

CPU_D3*

CPU_D5*

CPU_D2*

CPU_D1*

CPU_DSTBP2*
CPU_DSTBN2*
CPU_DBI2*

CPU_D4*

CPU_DBI0*

CPU_DSTBP0*

CPU_DSTBN1*
CPU_DBI1*

CPU_DSTBP3*
CPU_DSTBN3*
CPU_DBI3*

CPU_A4*
CPU_A5*

CPU_A7*

CPU_A6*

CPU_A9*
CPU_A10*
CPU_A11*
CPU_A12*

CPU_A14*
CPU_A15*
CPU_A16*
CPU_A17*
CPU_A18*
CPU_A19*

CPU_A22*

CPU_A25*

CPU_A24*

CPU_A23*

CPU_A26*
CPU_A27*
CPU_A28*
CPU_A29*
CPU_A30*

CPU_A33*

CPU_A32*

CPU_A31*

CPU_A34*
CPU_A35*

CPU_A3*

CPU_ADSTB0*
CPU_ADSTB1*

CPU_REQ1*

CPU_REQ0*

CPU_REQ2*
CPU_REQ3*
CPU_REQ4*

CPU_ADS*
CPU_BNR*

CPU_DBSY*

CPU_BR0*

CPU_HITM*

CPU_HIT*

CPU_DRDY*

CPU_TRDY*

CPU_LOCK*

CPU_PROCHOT*
CPU_THERMTRIP*
CPU_FERR*

CPU_BSEL0

CPU_RS0*
CPU_RS1*
CPU_RS2*

BCLK_VML_COMP_GND

BCLK_VML_COMP_VDD

CPU_PECI

CPU_BSEL2
CPU_BSEL1

CPU_COMP_VCC
CPU_COMP_GND

CPU_D16*

CPU_D0*

CPU_D54*

CPU_D60*
CPU_D61*

CPU_D40*

CPU_D27*

CPU_D26*

CPU_D25*

CPU_D24*

CPU_D22*

CPU_D20*
CPU_D21*

CPU_D7*
CPU_D8*

CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*

CPU_D17*
CPU_D18*
CPU_D19*

CPU_D23*

CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*

CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*

CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*

BCLK_IN_P

BCLK_OUT_ITP_P

CPU_DEFER*

CPU_BPRI*

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

BCLK_OUT_ITP_N

BCLK_OUT_NB_P
BCLK_OUT_NB_N

BCLK_IN_N

CPU_IGNNE*

CPU_A20M*

CPU_INIT*

CPU_INTR

CPU_NMI
CPU_SMI*

CPU_DPRSLPVR

CPU_DPRSTP*

CPU_STPCLK*

CPU_DPSLP*

CPU_DPWR*

CPU_SLP*

CPU_RESET*

CPU_PWRGD

CPU_A21*

CPU_D63*

CPU_D62*

CPU_A20*

CPU_A13*

SYMBOL 1 OF 11

FSB

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Loop-back clock for delay matching.

9

9

9

10 66

10 13 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

7

10 66

10 66

10 66

10 66

10 66

10 66

10 66

13 66

13 66

10 66

10 66

10 66

10 66

10 66

10 66

10 66

10 66

10 13 66

10 66

10 66

10 66

10 66

10 54 66

9

10 40 66

10 40 66

7

10 66

7

10 66

49.9

MF

1/20W
201

1%

R1436

MF

1/20W

201

1%

49.9

R1431

MF

1/20W

201

49.9

1%

R1430

MF

1/20W
201

49.9

1%

R1435

MF

1/20W
201

62

5%

R1415

MF

1/20W

201

54.9

1%

R1410

MF

1/20W
201

150

NO STUFF

5%

R1440

54 66

7

10 66

7

10 66

10 66

10 66

10 66

10 66

7

10 66

BGA

MCP89U-A01

OMIT_TABLE

U1400

SYNC_MASTER=K99_MLB

MCP CPU Interface

SYNC_DATE=04/08/2010

FSB_A_L<17>

FSB_D_L<31>

FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>

FSB_A_L<25>

FSB_A_L<27>

FSB_A_L<24>

FSB_A_L<33>

FSB_DBSY_L

CPU_FERR_L

FSB_D_L<61>

FSB_D_L<37>

FSB_CPURST_L

CPU_SMI_L

CPU_IGNNE_L

FSB_D_L<45>

FSB_D_L<48>

FSB_D_L<51>

FSB_BPRI_L

FSB_A_L<34>

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_CLK_ITP_P

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<56>

FSB_D_L<49>

FSB_D_L<42>

FSB_D_L<40>

FSB_DINV_L<0>
FSB_DSTB_L_P<1>

FSB_D_L<6>

FSB_D_L<3>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_DSTB_L_N<2>

FSB_D_L<4>

FSB_DSTB_L_N<1>

FSB_A_L<15>
FSB_A_L<16>

FSB_A_L<19>

FSB_A_L<26>

FSB_A_L<28>

FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_ADS_L

FSB_HITM_L

FSB_HIT_L

FSB_DRDY_L

FSB_TRDY_L

FSB_LOCK_L

CPU_PROCHOT_L

PM_THRMTRIP_L

=MCP_BSEL<0>

FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>

MCP_BCLK_VML_COMP_VDD

CPU_PECI_MCP

=MCP_BSEL<2>
=MCP_BSEL<1>

FSB_D_L<16>

FSB_D_L<0>

FSB_D_L<54>

FSB_D_L<60>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<22>

FSB_D_L<20>
FSB_D_L<21>

FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>

FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>

FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>

FSB_D_L<23>

FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>

FSB_D_L<43>
FSB_D_L<44>

FSB_D_L<46>
FSB_D_L<47>

FSB_D_L<50>

FSB_D_L<53>

FSB_D_L<55>

FSB_D_L<57>

CPU_INIT_L
CPU_INTR
CPU_NMI

PM_DPRSLPVR

CPU_STPCLK_L

CPU_DPSLP_L
FSB_DPWR_L

FSB_D_L<63>

FSB_D_L<62>

=PP1V05_S0_MCP_FSB

=PP1V05_S0_MCP_FSB

FSB_D_L<41>

FSB_D_L<39>

FSB_D_L<38>

FSB_BNR_L

CPU_DPRSTP_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_BREQ0_L

FSB_REQ_L<0>

FSB_A_L<35>

FSB_REQ_L<1>

FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>

FSB_ADSTB_L<1>

FSB_A_L<32>

FSB_ADSTB_L<0>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

FSB_CLK_ITP_N

FSB_D_L<52>

CPU_A20M_L

FSB_DEFER_L

FSB_CLK_MCP_P
FSB_CLK_MCP_N

FSB_DINV_L<3>

FSB_A_L<3>

FSB_D_L<12>

FSB_DINV_L<1>

FSB_A_L<4>

FSB_A_L<18>

FSB_A_L<14>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<10>
FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

14 OF 110

3.3.0

051-8467

14 OF 74

121

2

121

2

1

2

1

2

1

2

Y40

J39

R34

M40

L38

L40

P39

M39

J37
J36
L35

L39

F39

J38

R35
U36

C37
C38
B35

V37
Y36

Y39

V40

V39
AA39
AA36
AA37

AC36
AA40
AA38
AF39
AD38
AC38

AJ39

AD40

AC37

AC40

AC39
AF36
AF40
AG39
AD39

AJ40

AF37

AD36

AG40
AG38

U38

Y37
AF38

U39

U40

V38

U37

V36

AG33
AD35

AF35

AG34

AD32

AD34

U32

AG32

AG37

V32

V35
AC33

F35

AF33
AD33
AF34

AK40

AK39

AG36

D35

E35

AK38
AK37

U35

M37

A37

B37
D36

J34

P36

P38

P37

P34

U34

R38
R33

P40
H40
L37
F38
F40
H38
M38
H39
J40

R36
R37
P35

R40

P33
P32
R32
R39
H36
F36
L33
M35
L34
M33
M36
M32

H35
H34
L36
M34
F37
H37
J35
D39
E36
D40
E40
C39
E38

C36
B38
E37
C35
A35

AJ33

AK32

AG35

AF32

AJ37
AJ36

AK33
AJ35

AJ34

AJ32

V33

AA33

Y33
Y35
AA35
AC35

D2

AA34

Y34

Y32
U33

V34

AC34

AA32

AD37

D38

A36

AJ38

Y38

66

8

14 20 23

8

14 20 23

66

66

66

66

66

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI

BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT

BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

MCKE0A_0

MCKE0A_1

MCS0A_0*

MCS0A_1*

+VIO_PLL_CPU

+VIO_PLL_CPU

+VIO_PLL_CPU

+VIO_PLL_FSB

+VIO_PLL_FSB

+VIO_PLL_FSB

+VIO_PLL_MEM
+VIO_PLL_MEM

+VIO_M2CLK_DLL

+VIO_M2CLK_DLL

+VIO_M2CLK_DLL

MA0_0

MA0_8

MA0_9

MA0_10

MCAS0*

MBA0_0

MA0_15
MA0_14

MBA0_2
MBA0_1

MWE0*

MRAS0*

MDQS0_0_N

MDQS0_0_P

MDQS0_1_N

MDQS0_1_P

MDQS0_2_N

MDQS0_2_P

+VIO_PLL_MEM

MCLK0A_1_P
MCLK0A_1_N

MODT0A_1
MODT0A_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_7

MA0_11

MA0_12

MA0_13

MDQS0_3_N

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_4_P

MDQS0_7_N

MDQS0_7_P

MDQS0_6_P

MDQM0_5

MDQM0_6

MDQM0_7

MDQ0_60

MDQ0_55

MDQ0_56

MDQ0_52
MDQ0_51

MDQ0_15

MDQ0_48

MDQ0_40
MDQ0_39

MDQM0_2

MDQM0_3

MDQM0_1
MDQM0_0

MDQM0_4

MDQ0_0

MDQ0_1

MDQ0_2

MDQ0_3

MDQ0_4

MDQ0_5

MDQ0_6

MDQ0_10
MDQ0_9

MDQ0_7

MDQ0_8

MDQ0_11

MDQ0_14
MDQ0_13
MDQ0_12

MDQ0_16

MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17

MDQ0_26
MDQ0_25

MDQ0_23
MDQ0_22

MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27

MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32

MDQ0_41

MDQ0_38
MDQ0_37

MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42

MDQ0_47

MDQ0_50
MDQ0_49

MDQ0_54
MDQ0_53

MDQ0_57

MDQ0_59
MDQ0_58

MDQ0_24

MDQ0_61

MDQ0_62

MDQ0_63

MDQS0_6_N

MCLK0A_0_N

MCLK0A_0_P

MEMORY PARTITION 0

SYMBOL 2 OF 11

MRESET0*

MDQM1_0

MDQM1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQ1_59

MDQ1_61
MDQ1_60

MDQS1_1_P
MDQS1_1_N
MDQS1_0_P

MRAS1*

MDQ1_47

MDQ1_43

MDQ1_58

MDQS1_0_N

MDQS1_2_P

MDQS1_3_N

MDQ1_0

MDQ1_3
MDQ1_2
MDQ1_1

MDQ1_11

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_16

MDQ1_17

MDQ1_18

MDQ1_19

MDQ1_20

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_25

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_30

MDQ1_31

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_40

MDQ1_41

MDQ1_42

MDQ1_44

MDQ1_45

MDQ1_46

MDQ1_48

MDQ1_49

MDQ1_50

MDQ1_51

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_55

MDQ1_56

MDQ1_57

MDQ1_62

MDQ1_63

MA1_14

MA1_15

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P

MDQS1_2_N

MDQ1_32

MEM_COMP_GND
MEM_COMP_VDD

MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

MDQ1_4

MDQ1_5

MDQ1_6

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_10

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MCS1A_0*

MCS1A_1*

MODT1A_0

MODT1A_1

MCKE1A_0

MCKE1A_1

MWE1*

MCAS1*

MBA1_1

MBA1_2

MBA1_0

SYMBOL 3 OF 11

MEMORY PARITION 1

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

550 mA

25 mA

25 mA

20 mA 70 mA

27 67

27 67

27 67

27 67

26 67

26 67

26 67

26 67

26 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

9

67

9

67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

26 27 32 67

21 26 27 32 67

21 26 27 32 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

26 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

28 67

29 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

28 29 32 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

29 67

28 67

29 67

29 67

29 67

28 67

28 67

28 67

28 67

9

67

9

67

21 28 29 32 67

21 28 29 32 67

9

67

9

67

28 29 32 67

28 29 32 67

26 27 28 29

MF

1/20W
201

1K

5%

R1520

MF

1/20W

201

40.2

1%

R1511

MF

1/20W

201

1%

40.2

R1510

BGA

MCP89U-A01

OMIT_TABLE

U1400

BGA

MCP89U-A01

OMIT_TABLE

U1400

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MCP Memory Interface

MEM_A_CLK_P<1>

PP1V05_S0_MCP_PLL_FSBMEM

MEM_A_CLK_N<1>

MEM_B_DQ<16>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>

MEM_RESET_L

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQ<59>

MEM_B_DQ<61>
MEM_B_DQ<60>

MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>

MEM_B_RAS_L

MEM_B_DQ<47>

MEM_B_DQ<43>

MEM_B_DQ<58>

MEM_B_DQS_N<0>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQ<0>

MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>

MEM_B_DQS_N<2>

MEM_B_DQ<32>

MCP_MEM_COMP_GND
MCP_MEM_COMP_VDD

MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_BA<0>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

=PP1V05_S0_MCP_M2CLK_DLL

MEM_A_A<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_CAS_L

MEM_A_BA<0>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_BA<2>
MEM_A_BA<1>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<60>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<52>
MEM_A_DQ<51>

MEM_A_DQ<15>

MEM_A_DQ<48>

MEM_A_DQ<40>
MEM_A_DQ<39>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<1>
MEM_A_DM<0>

MEM_A_DM<4>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<10>
MEM_A_DQ<9>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<11>

MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>

MEM_A_DQ<16>

MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>

MEM_A_DQ<26>
MEM_A_DQ<25>

MEM_A_DQ<23>
MEM_A_DQ<22>

MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>

MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>

MEM_A_DQ<41>

MEM_A_DQ<38>
MEM_A_DQ<37>

MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>

MEM_A_DQ<47>

MEM_A_DQ<50>
MEM_A_DQ<49>

MEM_A_DQ<54>
MEM_A_DQ<53>

MEM_A_DQ<57>

MEM_A_DQ<59>
MEM_A_DQ<58>

MEM_A_DQ<24>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQS_N<6>

=PP1V5R1V35_SW_MCP_MEM

=PP1V5R1V35_S3_MCP_MEM

15 OF 110

3.3.0

051-8467

15 OF 74

1

2

1

2

1

2

AM26

AM27

AN18

AP15

AG31

AG30

AG29

AF31

AF30

AF29

AH29
AH30

AK31

AK30

AJ30

AR20

AN24

AP24

AP18

AM17

AP17

AN26
AP26

AR26
AR18

AM18

AR17

AN34

AN35

AU36

AV36

AP32

AR32

AJ31

AM21
AN21

AP14
AN17

AP21

AP20

AR21

AN23

AM24

AM23

AR23

AP23

AR24

AR15

AP29

AR29

AR12

AM11

AN11

AT12

AR5

AR4

AT6

AR9

AM9

AN5

AU3

AU5

AT3

AN9
AV3

AU35

AN8

AM12
AP12

AN32

AT29

AT36
AN37

AM14

AM37

AM36

AR37

AR36

AM34

AM35

AN36

AT35
AV37

AR35

AU38

AT33

AV35
AT37
AT38

AN33

AP33
AR33
AP30
AR30
AM33

AP27
AN29

AT30
AT32

AR27
AT27
AM30
AN30
AN27

AR14
AR11
AP11
AM15
AN15

AT9

AN14
AT14

AP9
AN12
AT11

AT8

AR8

AP8

AV4

AM8

AV5

AR6

AT5

AM7

AN7

AM29

AT4

AN4

AN6

AU6

AN20

AM20

AM6

AR38

AW37

AU30

AV27

AY14

AV9

AY6

AR3

AM3

AT1
AU1

AY37
AY36
AN38

AW18

AY9

AW8

AM2

AN39

AV32

AY27

AM40

AT40
AU40
AN40

AV33

AU39

AV39

AY35

AW35

AY32

AU32

AY30

AY29

AW33

AY33

AV30

AW30

AU29

AU27

AV26

AU26

AW29

AV29

AY26

AW26

AY15

AV12

AW12

AU15

AV15

AU14

AU12

AU11

AU9

AY8

AY12

AY11

AW9

AV6

AW6

AV2

AU2

AV8

AU8

AW4

AW3

AR1

AR2

AN1

AM1

AV24

AU24

AN2
AN3
AY5
AY4
AV11
AW11
AV14
AW14
AW27

AW32

AW15

AL23
AL24

AU17
AY24
AW23
AU18
AY23
AU23
AV23
AT21
AT23
AU21
AV21
AY21
AW21
AY20

AM38

AM39

AR39

AR40

AV38

AW38

AU33

AV20
AW20

AT20
AU20

AY17

AT15

AW17

AT17

AT26

AT24

AY18

AV17

AT18

AW24

AV18

23

67

67

8

23

20 21 23

8

IN

IN

IN

IN

IN
IN

IN

IN

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

PEC_CLKREQ*/GPIO_51

PE2_REFCLK_P
PE2_REFCLK_N

PEA_CLKREQ*/GPIO_49

PEB_CLKREQ*/GPIO_50

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE_WAKE*

PE0_TX4_P
PE0_TX4_N

PE0_TX5_P
PE0_TX5_N

PE1_TX0_P
PE1_TX0_N

PE1_TX1_P
PE1_TX1_N

PEX_RST*

PEX0_TERM_P

PE0_RX4_P
PE0_RX4_N

PE0_RX5_N

PE0_RX5_P

PE1_RX0_P
PE1_RX0_N

PE1_RX1_P
PE1_RX1_N

+3.3V_PLL_HVDD

+VIO_PLL_PE

+VIO_PLL_PE

+VIO_PLL_PE

+VIO_PLL_XREF_XS

+VIO_PLL_XREF_XS

+VIO_PLL_XREF_XS

+VIO_PLL_SATA

+VIO_PLL_SATA

+VIO_PLL_SATA

+VIO_PLL_H
+VIO_PLL_H

PCI EXPRESS

SYMBOL 4 OF 11

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1
PE1 ports are Gen1-only. 2 RCs: x1, x1

+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[3:0] are not used,

+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

If PE0[4:5] and PE1[0:1] are not used,

1/20W

MF

201

2.49K

1%

PLACE_NEAR=U1400.U5:12.7 mm

R1610

7

34

34

9

9

9

9

7

34 68

7

34 68 34 68

34 68

25

7

34 68

7

34 68

9

68

9

68

9

9

9

9

9

MF

1/20W
201

5%

22K

R1600

MCP89U-A01

BGA

OMIT_TABLE

U1400

9

MCP PCIe Interfaces

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N

MCP_PEX0_TERMP

PCIE_CLK100M_AP_N

=PEG_R2D_C_N<5>

=PEG_R2D_C_P<5>

PCIE_WAKE_L

PCIE_CLK100M_AP_P

PEG_CLK100M_P

PCIE_RESET_L

TP_PCIE_CLK100M_PE2P
TP_PCIE_CLK100M_PE2N

TP_PCIE_PE1_D2RP

=PEG_D2R_P<4>

=PEG_D2R_P<5>

PP3V3_S0_MCP_PLL_HVDD

PCIE_AP_D2R_P

TP_PCIE_PE1_D2RN

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<4>

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

=PEG_D2R_N<5>

PP1V05_S0_MCP_PLL_PEXSATA

PCIE_AP_D2R_N

=PEG_D2R_N<4>

PEG_CLKREQ_L

AP_CLKREQ_L

ENET_CLKREQ_L

PEG_CLK100M_N

16 OF 110

3.3.0

051-8467

16 OF 74

1

2

1

2

U4

U3
U2

V1

U1

V5
V4

V2
V3

U7

Y3
Y2

AA7
AA6

AA2
AA3

Y8
Y9

U6

U5

Y4
Y5

AA8

AA9

AA4
AA5

Y7
Y6

W10

AG11

AG10

AG12

AH11

AH10

AH12

AE10

AF12

AE11

AF10
AF11

68

23

23

OUT

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI

BI
BI

OUT

OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

IN
IN

IFPA_TXD0_N

IFPA_TXD0_P

DDC_DATA0/GPIO_39

DDC_CLK0/GPIO_38

RGB_DAC_VREF

+3.3V_RGBDAC

IFPA_TXD1_P
IFPA_TXD1_N

DDC_CLK1/GPIO_40

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N

IFPB_TXD5_P
IFPB_TXD5_N

IFPB_TXD6_P
IFPB_TXD6_N

IFPB_TXD7_N

IFPB_TXD7_P

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD2_P
IFPA_TXD2_N

IFPA_TXD3_P
IFPA_TXD3_N

DP1_0_P/TMDS0_TX5_P
DP1_0_N/TMDS0_TX5_N

DP1_1_N/TMDS0_TX4_N

DP1_2_N/TMDS0_TX3_N

DP1_1_P/TMDS0_TX4_P

DP0_3_P/TMDS0_TXC_P

DDC_DATA1/GPIO_41

DP1_2_P/TMDS0_TX3_P

DP1_3_N/TMDS0B_TXC_N

DP1_3_P/TMDS0B_TXC_P

DP0_0_N/TMDS0_TX2_N

DP0_0_P/TMDS0_TX2_P

DP0_1_N/TMDS0_TX1_N

DP0_1_P/TMDS0_TX1_P

DP0_2_N/TMDS0_TX0_N

DP0_2_P/TMDS0_TX0_P

DP0_3_N/TMDS0_TXC_N

HPLUG_DET0/GPIO_20
HPLUG_DET1/GPIO_21
HPLUG_DET2/GPIO_22

DDC_DATA2/DP_AUX_CH0_N

DDC_CLK2/DP_AUX_CH0_P

DDC_DATA3/DP_AUX_CH1_N

DDC_CLK3/DP_AUX_CH1_P

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

LCD_PANEL_PWR/GPIO_58

IFPAB_VPROBE

IFPAB_RSET

TMDS0_VPROBE

TMDS0_RSET

+3.3V_PLL_DP0
+3.3V_PLL_DP0

+3.3V_PLL_USB

+3.3V_PLL_USB

+VIO_PLL_IFPAB
+VIO_PLL_IFPAB

+VIO_PLL_CORE_LEG
+VIO_PLL_CORE_LEG

+VIO_PLL_SPPLL0

+VIO_PLL_V

+VIO_PLL_SPPLL0

+VIO_PLL_V

+VIO_PLL_NV
+VIO_PLL_NV

+VDD_IFPA
+VDD_IFPB

+VIO_DP0

+VIO_DP0

+VIO_DP0

FLAT PANEL

RGB

SYMBOL 5 OF 11

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

=MCP_IFPB_TXD_P/N<0>

=MCP_IFPAB_DDC_CLK

GPIO Pull-Ups

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

NOTE: DP_AUX_CH1 also requires pull-downs if used for
dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then

210 mA

Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).

NOTE: No Composite/S-Video/Component Video support on MCP89

TMDS/HDMI
TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>

LVDS_IG_A_CLK_P/N

LVDS

Interface Mode

LVDS_IG_A_DATA_P/N<0>
LVDS_IG_A_DATA_P/N<1>

60 mA

40 mA

160 mA

140 mA

180 mA

30 mA

180 mA

(GMUX_INT)

LVDS_IG_A_DATA_P/N<2>
LVDS_IG_A_DATA_P/N<3>
LVDS_IG_B_CLK_P/N
LVDS_IG_B_DATA_P/N<0>
LVDS_IG_B_DATA_P/N<1>
LVDS_IG_B_DATA_P/N<2>
LVDS_IG_B_DATA_P/N<3>

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<5>

TMDS_IG_DDC_DATA

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<4>

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<3>

RGB DAC Disable:

Connect +3.3V_RGBDAC pin to GND.

(UNUSED)

(UNUSED)
(UNUSED)

LVDS: Power +VDD_IFPx at 1.8V

=MCP_IFPA_TXD_P/N<3>

=MCP_IFPA_TXD_P/N<2>

=MCP_IFPA_TXD_P/N<1>

=MCP_IFPA_TXD_P/N<0>

TMDS: Power +VDD_IFPx at 3.3V

=MCP_IFPB_TXD_P/N<1>
=MCP_IFPB_TXD_P/N<2>
=MCP_IFPB_TXD_P/N<3>

=MCP_IFPAB_DDC_DATA

=MCP_IFPA_TXC_P/N

=MCP_IFPB_TXC_P/N

MCP Signal

only pull-ups are necessary.

DDC Mode Pull-downs

160 mA

60 mA

20 mA

NOTE: 100K pull-downs required if
HPLUG_DET0/HPLUG_DET1 are not used.

40 mA

17

9

9

9

17 68

9

68

9

68

9

68

9

68

9

68

9

68

9

68

9

68

24 68

24 68

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

60

24 68

24 68

9

9

9

9

9

68

9

68

9

68

9

68

9

17 68

9

17 68

9

17 68

9

9

9

9

9

9

9

9

9

9

7

17 37

17

10K

5%

1/20W

MF 201

R1782

10K

5%

1/20W

MF 201

R1781

10K

5%

1/20W

MF 201

R1780

5%

100K

1/20W

MF 201

R1711

5%

100K

1/20W

MF 201

R1710

CKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2Gnd

BGA

MCP89U-A01

OMIT_TABLE

U1400

5%

100K

1/20W

MF 201

R1712

5%

100K

1/20W

MF 201

R1713

MCP Graphics

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MIKEY_MIC_LOAD_DET

AUD_IP_PERIPHERAL_DET

SATARDRVR_A_EN

=PP3V3_S0_MCP_GPIO

MIKEY_MIC_LOAD_DET

AUD_IP_PERIPHERAL_DET

DP_IG_AUX_CH1_N

=PP3V3R1V8_S0_MCP_IFP_VDD

DP_IG_ML0_N<1>

DP_IG_ML0_P<2>
DP_IG_ML0_N<2>

DP_IG_ML0_N<3>

DP_IG_ML0_P<3>

PP3V3_S0_MCP_DAC

TP_MCP_RGB_DAC_VREF

DP_IG_ML0_P<1>

DP_IG_ML0_P<0>
DP_IG_ML0_N<0>

DP_IG_ML1_P<3>
DP_IG_ML1_N<3>

DP_IG_ML1_P<2>
DP_IG_ML1_N<2>

DP_IG_ML1_N<1>

DP_IG_ML1_P<1>

DP_IG_ML1_P<0>
DP_IG_ML1_N<0>

DP_IG_HPD0
DP_IG_HPD1
SATARDRVR_A_EN

DP_IG_AUX_CH0_N

DP_IG_AUX_CH0_P

=PP1V05_S0_MCP_DP0_VDD

=MCP_IFPA_TXC_P
=MCP_IFPA_TXC_N

=MCP_IFPA_TXD_P<0>
=MCP_IFPA_TXD_N<0>

=MCP_IFPA_TXD_P<1>
=MCP_IFPA_TXD_N<1>

=MCP_IFPA_TXD_P<2>
=MCP_IFPA_TXD_N<2>

=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<3>

=MCP_IFPB_TXC_N

=MCP_IFPB_TXC_P

=MCP_IFPB_TXD_P<0>
=MCP_IFPB_TXD_N<0>

=MCP_IFPB_TXD_P<1>
=MCP_IFPB_TXD_N<1>

=MCP_IFPB_TXD_P<2>

=MCP_IFPB_TXD_N<3>

=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

LCD_IG_BKLT_PWM
LCD_IG_BKLT_EN
LCD_IG_PWR_EN

MCP_IFPAB_VPROBE
MCP_IFPAB_RSET

MCP_TMDS0_VPROBE
MCP_TMDS0_RSET

DP_IG_AUX_CH1_P

DP_IG_AUX_CH0_N

DP_IG_AUX_CH0_P

=MCP_IFPB_TXD_P<3>

=MCP_IFPB_TXD_N<2>

=PP1V05_S0_MCP_PLL_IFP

PP1V05_S0_MCP_PLL_CORE

DP_IG_AUX_CH1_N
PP3V3_S0_MCP_PLL_DP_USB

DP_IG_AUX_CH1_P

17 OF 110

3.3.0

051-8467

17 OF 74

1 2

1 2

1 2

1 2

1 2

C23

B23

F30

G30

J29

K30

D23
E23

J30

J24
H24

G24
F24

E24
D24

C24
B24

K26

J26

K24
K23

F23
G23

H23
J23

A29
B29

B27

D27
C27

H27

H30

E27

G27

F27

G26

H26

E26

F26

C26

D26

J27

C29
D30
E30

D29

E29

F29

G29

C30

B30

A30

C21
B21

H29
K27

L23
M23

M22

L22

L25
M25

L26
M26

L27

L28

M27

M28
L24

M24
A23

A24

B26

A26

A27

1 2
1 2

17

8

18 19

17

7

17 37

9

17 68

24

24

9

8

24

9

17 68

9

17 68

9

17 68

24

23

23

IN

BI

IN
IN
IN
IN

IN
IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

USB0_P
USB0_N

SATA_A1_TX_P
SATA_A1_TX_N

SATA_A1_RX_P

SATA_LED*/GPIO_30

SATA_TERMP

USB1_P
USB1_N

USB2_P
USB2_N

USB3_N

USB6_P

USB7_P
USB7_N

USB4_P
USB4_N

USB5_P
USB5_N

USB_OC0*/GPIO_25
USB_OC1*/GPIO_26

USB_RBIAS_GND

RGMII_RXD0
RGMII_RXD1
RGMII_RXD2

RGMII_RXCTL

RGMII_RXCLK

RGMII_INTR/GPIO_35

+3.3V_PLL_MAC_DUAL

RGMII_COMP_VDD
RGMII_COMP_GND

RGMII_VREF

RGMII_TXD3

RGMII_TXCLK
RGMII_TXCTL

RGMII_MDC

RGMII_MDIO

RGMII_RESET*

RGMII_RXD3

BUF_25MHZ

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

USB3_P

USB6_N

SATA_A0_TX_P
SATA_A0_TX_N

SATA_A0_RX_N
SATA_A0_RX_P

NC

SATA_A1_RX_N

LAN

SYMBOL 6 OF 11

USB

SATA

BI
BI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Bluetooth

Internal 19.5K Pull-Downs on all USB pairs

OHCI1/EHCI1

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

Connect RGMII_RXD<0:3> together to 10K pull-down.
Connect RGMII_RXCLK to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_MDIO to 10K pull-down.

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

20 mA

Internal MAC Disable:

All other pins can be left TP or NC.

AirPort (PCIe Mini-Card)

Camera/External E

External C

External A

EXTERNAL D

SD Card/ExpressCard

OHCI0/EHCI0

Geyser Trackpad/Keyboard

9

9

70

9

70

9

70

9

70

9

70

9

70

9

70

R1810

MF

1/20W

201

49.9

1%

R1811

MF

1/20W

201

1%

49.9

7

37 69

7

37 69

47 69 72

47 69 72

38 69

38 69

R1850

8.2K

MF

1/20W

201

5%

R1851

201

MF

8.2K

1/20W

5%

7

37 69

7

37 69

9

69

9

69

9

69

9

69

36 69

36 69

R1860

201

1%
1/20W

887

MF

9

68

9

68

9

68

9

68

35 68

35 68

35 68

35 68

R1805

MF

1/20W
201

2.49K

1%

9

R1800

MF

1/20W

201

5%

100K

U1400

OMIT_TABLE

BGA

MCP89U-A01

7

34 69

7

34 69

MCP SATA, USB & Ethernet

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

USB_EXTC_N

USB_BT_P

USB_SDCARD_N

USB_SDCARD_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTA_OC_L

=PP3V3_S5_MCP_GPIO

MCP_RGMII_VREF

=PP3V3_S0_MCP_GPIO

ENET_RXD<1>

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N

MCP_SATA_TERMP

PP3V3_ENET_MCP_PLL_MAC

MCP_MII_COMP_VDD

=PP3V3_ENET_MCP_RMGT

ENET_RXD<3>

USB_EXTA_P
USB_EXTA_N

USB_MINI_N

USB_MINI_P

USB_EXTC_P

USB_TPAD_N

USB_EXTD_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_HDD_D2R_N

USB_EXTD_P

TP_ENET_TXD<1>

TP_ENET_TXD<0>

TP_ENET_TXD<3>

TP_ENET_TXD<2>

TP_ENET_CLK125M_TXCLK
TP_ENET_TX_CTRL

TP_ENET_MDC

TP_MCP_CLK25M_BUF0_R

TP_ENET_RESET_L

ENET_MDIO

MCP_MII_COMP_GND

MXM_GOOD_L

ENET_RX_CTRL

ENET_ENERGY_DET

ENET_RXD<2>

ENET_RXD<0>

ENET_CLK125M_RXCLK

USB_EXTD_OC_L

USB_BT_N

MCP_USB_RBIAS_GND

USB_TPAD_P

18 OF 110

3.3.0

051-8467

18 OF 74

1

2

1

2

1

2

1

2

1

2

1

2

1

2

E21
D21

AF2
AF3

AF4

AG5

AG4

F21
G21

E20
D20

K21

G20

H20
J20

A20
A21

H21
J21

H14
G12

L19

C15
H17
C17

A15

D17

E17

J18
K15

K14

B15

D15
G14

C14

E15
H18

G17

G15

J14

J17

F17

F15

L21

F20

AF1
AG1

AG3
AG2

G5
V6

AK36

AM4
H15

AF5

36

8

19

8

17 19

68

23

70

8

20 23

70

7

37

69

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

IN

OUT
OUT
OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

OUT
OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

OUT

OUT

BI

BI

BI

BI

IN

IN

BI

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

BI

OUT

IN

PKG_TEST2

PKG_TEST

TEST_MODE_EN

SUS_CLK/GPIO_34

XTALOUT_RTC

XTALIN_RTC

XTALIN
XTALOUT

JTAG_TCK

JTAG_TRST*

JTAG_TDO
JTAG_TMS

JTAG_TDI

MGPU_PIO3/GPIO_24

MGPU_PIO1/GPIO_7
MGPU_PIO2/GPIO_23

MGPU_PIO0/GPIO_6

INTRUDER*

MEMVTT_EN/GPIO_45

MCP_MEMVDD_EN/GPIO_44

PWRGD

RTC_RST*

PWRGD_SB

RSTBTN*

PWRBTN*

KBRDRSTIN*/GPIO_56

A20GATE/GPIO_55

SIO_PME*/GPIO_31
EXT_SMI*/GPIO_32

SMB_ALERT*/GPIO_64

SMB_DATA1/MSMB_DATA

SMB_CLK1/MSMB_CLK

SMB_DATA0

SMB_CLK0

THERM_DIODE_N

THERM_DIODE_P

SPKR/GPIO_1

SPI_DO/GPIO_09

SPI_DI/GPIO_08

MCP_VID3/GPIO_16

MCP_VID2/GPIO_15

SLP_RMGT*

SLP_S3*

FANRPM1/GPIO_63/MGPIO_3

FANCTL1/GPIO_62

FANCTL0/GPIO_61

FANRPM0/GPIO_60/MGPIO_2

MISC_VDDEN4/GPIO_19
MEM_VDD_SEL/GPIO_46

MISC_VDDEN3/GPIO_18

MISC_VDDEN2/GPIO_17

MISC_VDDEN1/GPIO_48

MISC_VDDEN0/GPIO_47

LPC_DRQ0*/GPIO_43

LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLKRUN*/GPIO_42

LPC_SERIRQ

LPC_AD0

HDA_PULLDN_COMP

HDA_SYNC

HDA_RESET*

HDA_BITCLK

HDA_SDATA_OUT

HDA_SDATA_IN0

LPC_FRAME*

+VDD_HDA

SLP_S5*

MCP_WAKE_DIS*

MCP_WAKE_REQ*

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14

SPI_CLK/GPIO_11

SPI_CS0*/GPIO_10

LPC_RESET*

LPC_CLK0

HDA

LPC

SYMBOL 7 OF 11

MISC

OUT

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Platform-Specific Connections

behavior of Inte’s SLP_S4# signal

NOTE: MCP SLP_S5# signal has the

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

0 = USER mode (Normal boot mode)

FIXME: AUD_IPHS_SWITCH_EN WAS GPIO_2

internal ~9K
pull-up.

(IPU)

(IPU-S5)

(IPD)

(IPU)

(IPU-S5)

(IPD)

62.5 MHz

42.7 MHz

25.0 MHz

(IPU)

(IPU-S5)

(IPU)

(IPD)

70 mA

(IPD)

(IPU)

(IPU)

(IPU)

1
0

Frequency

24 MHz

14.31818 MHz

0

0
1

1

SPI Frequency Select

1

0

Frequency

BIOS Boot Select

0

LPC_FRAME#

LPC

(IPU)

(IPU)

0

NOTE: MCP89 does not support FWH, only
LPC ROMs. So Apple designs will

HDA_SYNC

I/F

SPI_CLK

BUF_SIO_CLK Frequency

1

SPI

not use LPC for BootROM override.

MCP_SPKR:

(IPD)

(IPU)

(IPU-S5)

(IPD)

For EMI Reduction on HDA interface

1

SPI_DO

31.2 MHz

Connects to SMC for automatic recovery.

HDA Output Caps

NOTE: 42 & 62 MHz use FAST_READ command.
Straps not provided on this page.

1 = SAFE mode (For ROMSIP recovery)

(IPD)

GPIO43 has

70 mA

has the behavior

signal.

NOTE: MCP SLP_S5# pin

of Intel’s SLP_S4#

GPIO Pull-Ups/Downs

7

39 41 69

19 25 69

7

39 41 25 69

201

MF

1/20W

5%

10K

R1961

201

MF

1/20W

22

5%

R1953

7

37 69

201

MF

1/20W

22

5%

R1952

MF

1/20W

201

5%

22

R1951

201

MF

1/20W

22

5%

R1950

7

37 69

7

37 69

7

37 69

201

MF

1/20W

1%

49.9

R1900

7

37 69

25

25

25

25

39

39

13

25

19 55

19 55

19 55

19 55

45 72

45 72

7

19 39 58

58

7

39 40 58

41 69

19 41 69

41 69

41 69

201

MF

1/20W

10K

5%

R1970

40

10K

5%
1/20W
MF
201

R1959

1K

1%
1/20W
MF
201

R1975

25 69

19 34 58

42 69

42 69

42 69

42 69

201

MF

1/20W

5%

10K

R1930

1/20W
201

MF

5%

100K

R1931

13

13

13

13

13

25

39

39

40

201

MF

1/20W

49.9K

1%

R1920

201

MF

1/20W

49.9K

1%

R1921

201

25V
NPO

10PF

5%

C1951

201

25V
NPO

5%

10PF

C1950

201

25V
NPO

5%

10PF

C1953

201

25V
NPO

5%

10PF

C1952

7

39 41

21

21 58

201

MF

1/20W

22

5%

R1960

201MF

1/20W

22

5%

R1910

201MF

1/20W

5%

22

R1912

201MF

1/20W

22

5%

R1911

201MF

1/20W

5%

22

R1913

7

39 41 69

7

39 41 69

7

39 41 69

7

39 41 69

39

7

37

7

19 41 48

19 22

7

19 37

19 39

19 38

19

39 40 58

9

19 40

10K

5%

1/20W

MF 201

R1996

R1980

201MF

1/20W

10K

5%

201MF

1/20W

5%

100K

R1987

10K

5%

1/20W

MF 201

R1990

201MF

1/20W

10K

5%

R1991

201MF

1/20W

5%

10K

R1989

201MF

1/20W

10K

5%

R1981

201MF

1/20W

100K

5%

R1992

201MF

1/20W

5%

100K

R1993

201MF

1/20W

5%

100K

R1994

201MF

1/20W

100K

5%

R1995

201MF

1/20W

100K

5%

R1986

7

19 41

7

39 41 19 25 69

R1965

201

MF

1/20W

33

5%

5%
MF

201

1/20W

10K

NO STUFF

R1966

5% 201MF

1/20W

10K

R1983

201MF

1/20W

5%

20K

R1998

201MF

1/20W

5%

100K

R1999

OMIT_TABLE

MCP89U-A01

BGA

U1400

470

201

MF

1/20W

5%

DRAM_CFG1:L

R1956

201

MF

1/20W

5%

DRAM_CFG0:H

10K

R1957

201

MF

1/20W

10K

5%

DRAM_CFG2:H

R1978

5%

10K

1/20W
MF
201

DRAM_CFG2:L

R1979

5%

10K

1/20W

MF

201

DRAM_CFG3:H

R1976

5%

10K

1/20W

MF

201

DRAM_CFG3:L

R1977

5%
1/20W
MF
201

10K

DRAM_CFG0:L

R1958

39

7

19 39 58

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MCP HDA, LPC & MISC

SPIROM_USE_MLB

MAKE_BASE=TRUE

PM_SLP_S4_L PM_SLP_S5_L

LPC_PWRDWN_L

LPC_RESET_L

MCP_TEST_MODE_EN

=PP3V3_S3_MCP_GPIO

MCP_VID<0>

PM_SLP_S4_L

PM_SLP_RMGT_L

PM_SLP_S3_L

SPI_MISO

MCP_VID<1>

MCP_MEM_VDD_SEL_1V5
MLB_RAM_CFG3

SMC_ADAPTER_EN
LPCPLUS_GPIO

RTC_CLK32K_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALIN

JTAG_MCP_TRST_L

JTAG_MCP_TMS

JTAG_MCP_TDI

SPIROM_USE_MLB

AUD_IPHS_SWITCH_EN
GFXVCORE_PWR_EN

SMC_IG_THROTTLE_L

MCP_MEM_VTT_EN

MCP_PS_PWRGD

RTC_RST_L

PM_SYSRST_DEBOUNCE_L

PM_PWRBTN_L

SMC_RUNTIME_SCI_L

AUD_I2C_INT_L

SMC_WAKE_SCI_L
PM_LATRIGGER_L

SMBUS_MCP_0_DATA

SMBUS_MCP_0_CLK

MCP_THMDIODE_N

MCP_VID<3>

MCP_VID<2>

MLB_RAM_CFG0

MCP_CPU_VTT_EN_L

LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

PM_CLKRUN_L

LPC_SERIRQ

LPC_AD_R<0>

MCP_HDA_PULLDN_COMP

HDA_RST_R_L

HDA_BIT_CLK_R

HDA_SDOUT_R

HDA_SDIN0

PM_BATLOW_L

MCP_WAKE_REQ_L

SPI_CLK_R

SPI_CS0_R_L

LPC_CLK33M_SMC_R

PM_RSMRST_L

MCP_SPKR

LPC_FRAME_R_L

LPC_AD<1>
LPC_AD<2>

HDA_SDOUT

HDA_RST_L

HDA_BIT_CLK

=PP3V3_S0_MCP_GPIO

HDA_SYNC

LPC_AD<0>

HDA_RST_R_L

LPC_AD<3>

=PP3V3R1V5_S0_MCP_HDA

PP3V3_G3_RTC

LPC_FRAME_L

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_SYNC_R

MCP_VID<3>

MCP_VID<2>

MLB_RAM_CFG1

PM_CLK32K_SUSCLK_R

MLB_RAM_CFG0

MLB_RAM_CFG1

MLB_RAM_CFG2

MLB_RAM_CFG3

LPC_RESET_L

SMBUS_MCP_1_DATA

SMBUS_MCP_1_CLK

AP_PWR_EN

MCP_THMDIODE_P

SPI_MOSI_R

ENET_LOW_PWR
SDCARD_RESET

MEM_EVENT_L

MLB_RAM_CFG2

HDA_SYNC_R

MCP_MEM_VDD_EN

SM_INTRUDER_L

JTAG_MCP_TDO

JTAG_MCP_TCK

MCP_CLK25M_XTALOUT

MCP_VID<1>

MCP_VID<0>

AP_PWR_EN

SPI_MISO

=PP3V3_S3_MCP_GPIO
=PP3V3_S0_MCP_GPIO

=PP3V3_S5_MCP_GPIO

SMC_IG_THROTTLE_L

GFXVCORE_PWR_EN

AUD_IPHS_SWITCH_EN

MCP_CPU_VTT_EN_L
LPCPLUS_GPIO

MEM_EVENT_L

SDCARD_RESET

ENET_LOW_PWR

19 OF 110

3.3.0

051-8467

19 OF 74

21

1 2

1 2

1 2

1 2

1

2

1

2

1

2

1

2

121

2

121

2

2

1

2

1

2

1

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2
1 2
1 2
1 2

1 2

1 2

1

2

1 2

1 2

1 2

C20

B20

A6

H9

C18

B18

A14
B14

A12

E12

C12
B12

D12

G9

E6
F9

D5

G18

C11

B11

E9

D18

F18

F12

H12

D3

F6

D14
J11

D9

C6

B6

C8

C5

D1

C2

E1

E14

B9

D6

E5

C9

A8

G7

F8

D8
E8

G11
D11

F11

E11

F14

A11

F2

H2
H3
H4

F1

H5H1

A5

A4

C4

B4

B3

C3

F3

J12

B8

A9

E18

E3
E4

G8

H10

F5
F4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

7

19 41 48

8

19

19

19

19

69 19 69

19 69

19 69

8

17 18 19

19 69

8

23

8

20 23

19 69

19 69

19 69

19 55

19 55

19

19

19

19

19

19

19 69

19 55

19 55

19 34 58

19 41 69

8

19

8

17 18 19

8

18

19 40

19 22

7

19 37

19

7

19 41

19 39

19 38

19

+VTT_CPU
+VTT_CPU
+VTT_CPU

+VDD_MEM
+VDD_MEM
+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM
+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM
+VDD_MEM

+VDD_MEM

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VDD_MEM

+VTT_CPU2

+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2
+VTT_CPU2

+3.3V_HVDD

+3.3V

+VTT_CPU2

+3.3V
+3.3V

+VDD_DUAL_AUXC
+VDD_DUAL_AUXC

+3.3V_VBAT

+3.3V_DUAL_USB
+3.3V_DUAL_USB

+3.3V_DUAL

+VTT_CPU

+VTT_CPU
+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU
+VTT_CPU

+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU

+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU

+VTT_CPU

+VTT_CPU

+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU
+VTT_CPU

+3.3V_DUAL_RMGT

+3.3V_DUAL_RMGT

+VDD_DUAL_RMGT

+VDD_DUAL_RMGT

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

+VDD_MEM

SYMBOL 8 OF 11

POWER I

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB
+VDD_COREB
+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB

+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREB

+VDD_COREA

+VDD_COREA
+VDD_COREA

+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB
+VDD_COREB

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA
+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA

+VDD_COREA_SENSE
GND_COREA_SENSE

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_DVDD

+VIO_PE_AVDD

+VIO_PE_AVDD
+VIO_PE_AVDD

+VIO_PE_AVDD

+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD
+VIO_PE_AVDD

+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD

+VIO_SATA_AVDD
+VIO_SATA_AVDD
+VIO_SATA_AVDD

+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD
+VIO_SATA_DVDD

GND_COREB_SENSE

+VDD_COREB_SENSE

POWER II

SYMBOL 9 OF 11

GND GND

SYMBOL 10 OF 11

GND

GND GND

GND

SYMBOL 11 OF 11

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

400 MA

PE1[1:0])

2000 mA 4300 mA

200 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

30 mA

250 mA

150 mA

?? uA (G3)

5 mA (S0)

200 mA

40 mA

240 mA

140 mA

300 mA

regulators.

8450 mA (0.85V)

be used for remote sensing unless

15350 mA (0.85V)

(PE0[5:0]

COREA/COREB are powered by separate

(PE0[5:0], PE1[1:0])

1000 MA

100 mA

300 mA

Instead connect regulator sense point
as close to COREB FET as possible.

NOTE: VDD_COREx_SENSE signals should NOT

BGA

MCP89U-A01

OMIT_TABLE

U1400

BGA

MCP89U-A01

OMIT_TABLE

U1400

BGA

MCP89U-A01

OMIT_TABLE

U1400

MCP89U-A01

BGA

OMIT_TABLE

U1400

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MCP Power & Ground

=PP1V05_SW_MCP_FSB

=PP1V5R1V35_SW_MCP_MEM

=PPVCORE_S0_MCP

TP_MCP_VDDCOREA_SENSEP
TP_MCP_VDDCOREA_SENSEN

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP

PP3V3_G3_RTC

=PP0V9_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

=PP3V3_S0_MCP_HVDD

=PP1V05_S0_MCP_FSB

TP_MCP_VDDCOREB_SENSEP
TP_MCP_VDDCOREB_SENSEN

=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDD

PP1V05_S0_MCP_PE_AVDD

=PP1V05_S0_MCP_PE_DVDD

=PPVCORE_SW_MCP_GFX

=PP0V9_ENET_MCP_RMGT

20 OF 110

3.3.0

051-8467

20 OF 74

W30
N29
K31

AK2
AK25
AJ28

AL17

AL21

AK9
AK28
AJ11
AJ5
AJ29
AJ3
AJ20
AK10
AJ18
AK1
AJ1
AJ7
AJ8
AJ25
AJ16

AK11

AK18

AK27

AK14

AJ22

AK3

AJ21

AK22
AK8

AJ4

AA30

E32

L29

E33

C32

AK24

AC29

AC30
AD30
AB31
AC31
AD31
AC32

V9

V10

AD29

H11
K29

L18
K18

A18
L20

K20

J15

V29

Y29
W29

Y30

N30

AA29

L31

V30
U29

M29
M30
R30
P30
L32
T29
L30
U30
P29
R29

F32
H32
G32
A33

D32
AB30
AB29

C33

D33

A32

J33

T30

M31

F33

H33

J32

B33

G33

B32

B17

A17

L17

K17

AL30

AL29

AL27

AL26

AL20

AL18

AL15

AL14

AL12

AL11

AJ14

AJ13

AJ6

AK7

AJ15

AK6

AJ9

AK29

AJ2

AK23

AK17

AJ12

AJ10

AJ27

AK20

AK26

AK4

AK12

AJ19

AK16

AK13

AJ26

AK5

AK15

AJ17

AK21

AJ24

AJ23

AK19

M13

L14

L13

AB20

AB19

AB18

AB17

AB22

Y22

Y21

Y20

Y19

Y18

Y17

AB21

V22

V17
V19
V18

M14

V21

V20

V23

K4

L6

J5

L1

L2

J6

K11

L3

L4

M5

J7

J1

J2

L5

L11

M4

J4

M3

L9

K5

M12

M11

L7

K2

M9

M7
Y23
M2
AB23

R3

R12

N11

N2

N7

N5

R9

P1

R2

P8

P4

P3

R5

N10

P6

R7

AD24

P5

R10

N8

R4

P2

R1

P10

AA24

Y24

AD23

R11

P7

P12

P11

AC24

AB24

R6

N12

J3

N4

P9
R8

L8
M8
M10
L10
M6
L12
K10
K7
M1
K8

AD20

AD19

AD18

AD17

AD21
AD22

U11

T12

T11

W24

V24

U24

V11

U9
U8

AC8

AD6

AD8

AD9

AC9

AD7

AC10

AC7

AD10

AD11

AC11

AD12

AC12

AE12

AA10

AB10

V12

U12

W11
W12
Y11

Y12
AA11
AA12
AB11
AB12

AF6
AG8
AF7

AG9

AF8

AG6
AF9
AG7

AD1
AD2
AD3
AD4
AC3
AC4
AC5
AD5
AC6
AC1
AC2

J8

J9

W19

E10

AN25

AU34
AW19

AC21

AH31

AT31

AT10

T36

K37

AE4

T37

B5

C40

AB4

AB2

G4

AE5

AC20

AW34

AE8

W18

AT16

AB5
N34
AT2
W20

AW16

D7

B2
G37
D16
K39
G31

B7
L15

Y10
AW2
AH7
B13

AE37

AV1

AN19
AP10

W33

AB36

K13

AU13
AA23
AA31

Y31

AE33

AY3
N33

T2
B39

T4

AH37

V31

AU37

AW5
AU7
AT7

AN28

D4

AU19
AP25
AU22
AW13

T33

E7
AW7
H13

AL25

AL34

G13

AM32

B10

AY38

AU25

W4

D10

AU10

H31
AL31
U31

AE31

AN16

AA22

G10
B22
B19

AC18

B34
E22

AL22

K34

P31

G34

AP36

H25

U21

AU4
AA19

B31

AT19

W8

AT13

AP19

AH2

A38

AE39

AT34

AA18
AT25

U23
D22

AW31

W36
W39

AC23
AP22

W37

AP31

AN13

AU31
AL19
AL2

E28

AA20

AH34
B28
AV40
D28
H28
G36
AE36

AP16

E16

B16

V8
AM5

V7

H7

H6

AK35

AK34

W2

AP7
U17

E13

K33

AL13

AA17
T10

N31

AL39
T31

T7
W31

U18

AL10
AP34

W7
AP2

W5

M21
AE7

M19
M20

M18

M17

M15

T8
M16

D31

AN22

T34

AW22

K22

L16

E19

AU28

AW28

AE29

N37

N36

N39

AN10
AB8

AL5

AH39

AW39

G39
AB39

AL33
AW10

AC17
AH5

AH36

AB7

AB37

B36

D37

E39

C1

AL4

AW36

G22

U20

AU16
AB34

AL37

AC19
AN31

E2
T5

K19

H8

G2

AC22

H22

Y1

D19

W23

E25
K36

W21
D34

AP5

AE34
AT39

AL28

E34

K12

W34

U10

U19

AB33

B25

AP39

R31

AH8

A3

H19

W22

AP37

AA1

AL8

AH33
AT22

H16

AP28
AT28

AP13

U22

E31
G16

K25

AP4
G25

K28

AL16

AA21

K16

AL36

G19

AL7

T39
AH4

W17

AE30

D25

AE2

D13

AW25

G28

8

23 15 21 23

8

23

8

18 23

8

23

8

19 23

8

23

8

23

8

23

8

14 23

8

23

23 23

8

23

22 24

8

23

NC

NC

OUT

OUT

IN

BI

BI

BI

BI

D

G S

IN

VCC

D

DONE

G

GND

THRM

S

EN

CNFG

PAD

D

G

G

D

S

S

D

G

G

D

S

S

NC

K1

G

S

SENSE

D

KELVIN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NO STUBS on CKE signals!

DIMM CKE Clamps

Q2355/Q2356 chosen for low output capacitance.

CKE must be held low to keep memory in self-refresh.

Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.

Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.

Clamps enable before MCP89 MEMVDD rail switched off.

<R1>

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

Gated Rail Savings: 120mW

NV Requirements:

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

- Min Ramp-Up Time: 20 uS (10% to 90%)

- FET Ron <= 3.8 mOhms

4250 mA

(OR 1.35V)

Q2300

Type

Part

N-Channel

STMFS4854N

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

Loading

(G driven to VCC)

C2300 helps reduce input rail
droop during Q2300 turn-on.

Rds(on)

10 mOhm @3.2V

4.3 A (EDP)

44

44

MF

560K

1%
1/20W

201

R2305

19 58

0.1UF

402

CERM

10V

20%

C2305

CRITICAL

PLACE_NEAR=Q2300.9:2 mm

1206-1

CERM-X5R

6.3V

20%

100UF

C2300

15 28 29 32 67

15 28 29 32 67

15 26 27 32 67

15 26 27 32 67

SOD-VESM-HF

SSM3K15FV

Q2350

19

5%

10K

MF

1/20W

201

R2350

CRITICAL

TDFN

SLG5AP031

U2305

SOT-963

CRITICAL

NTUD3170NZXXG

Q2355

SOT-963

CRITICAL

NTUD3170NZXXG

Q2356

DFN

CRITICAL

STMFS4855NS

Q2300

MCP89 Memory Rail Gating

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MEMVTT_EN_L

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_A_CKE<0>

MEM_A_CKE<1>

=PP5V_S3_MCPDDRFET

MCP_MEM_VTT_EN

=PP5V_S3_MCPDDRFET

TP_MCPMEM_DONE

MCPMEM_CNFG

=PP1V5R1V35_SW_MCP_MEM

MCP_MEM_VDD_EN

=PP1V5R1V35_S0_MCPDDRFET

MCPDDRFET_SENSE

MCPDDRFET_KELVIN

MCPMEM_GATE

PP1V5R1V35_SW_MCP

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

23 OF 110

3.3.0

051-8467

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OUT

OUT

S

D

G

IN

CNFG

EN

S

THRM

GND

G

DONE

D

VCC

PAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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SIZE

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SHEET

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

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8 7 5 4 2 1

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

(G driven to VCC)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

Q2400

15.35 A (EDP)

NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

droop during Q2400 turn-on.

C2400 helps reduce input rail

N-Channel

Si4838BDY

3.2 mOhm @2.5V

- Min Ramp-Up Time: 100 uS (10% to 90%)

- FET Ron <= 2.5 mOhms

Gated Rail Savings: 860mW

NV Requirements:

Type

Part

Loading

Rds(on)

PLACE_NEAR=C2400.2:1 mm

SM

XW2401

SM

PLACE_NEAR=C2400.1:1 mm

XW2400

55 72

55 72

SO-8

SI4838BDY

CRITICAL

Q2400

19

20%
10V
CERM
402

0.1UF

C2405

100UF

PLACE_NEAR=Q2400.5:2 mm

CRITICAL

1206-1

CERM-X5R

6.3V

20%

C2400

10%
CERM

820PF

402

50V

C2406

SLG5AP033

TDFN

CRITICAL

U2405

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

MCP89 GFX Core Rail Gating

MIN_NECK_WIDTH=0.12 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0.9V

MAKE_BASE=TRUE

PPVCORE_SW_MCP_GFX

=PPVCORE_S0_MCPGFXFET

=PP5V_S0_MCPFSBFET

TP_MCPGFX_DONE

GFXVCORE_PWR_EN

MCPGFX_CNFG

MCPGFX_GATE

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

=PPVCORE_SW_MCP_GFX

24 OF 110

3.3.0

051-8467

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20 24

NC

VOUT

EN

VIN

GND

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

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8 7 5 4 2 1

MCP 3.3V DP & USB PLL Power

<Ra>

<Rb>

210 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

260 mA

MCP CPU FSB (VTT) Power

MCP 3.3V PLL Power

50 mA

140 mA

800 mA

300 mA

555 mA

160 mA

325 mA

70 mA

240 mA

300 mA

5 mA (S0)

70 mA

30 mA

550 mA

100 mA200 mA

150 mA

200 mA

2000 mA

4300 mA (1.5V)

MCP 1.05V CPU/FSB/MEM PLL Power

MCP 1.05V PCIe/SATA PLL Power

MCP Memory Power

MCP 1.05V PCIE Digital Power

MCP 3.3V AUX/USB Power

MCP 3.3V I/O Power

MCP 3.3V MAC/SMU Power

MCP 0.9V AUX Core Power

250 mA

? uA (G3)

MCP 1.05V Memory DLL Power

MCP 1.05V Core/Misc PLL Power

MCP 0.9V MAC/SMU Power

MCP 1.05V SATA Digital Power

MCP S0 FSB (VTT) Power

MCP 3.3V/1.5V HDA Power

MCP 2.0V-3.3V RTC Power

MCP 1.05V PCIe Analog Power

500 mA

MCP 1.05V SATA Analog Power

8450 mA (0.85V)

MCP 3.3V MAC PLL POWER

20 mA 20 mA

MCP 3.3V PCIe/SATA I/O PLL Power

MCP Non-GFX Core Power

Vout = 0.8V * (Ra + Rb) / Rb, Rb ~ 320kOhms

20%

4.7UF

603

6.3V
CERM

C2590

20%
X5R

0.22UF

6.3V
201

C2503

20%
X5R

0201

6.3V

1.0UF

C2502

X5R

6.3V
201

10%

0.1UF

C2507

X5R

0.1UF

6.3V
201

10%

C2506

X5R

0.1UF

6.3V
201

10%

C2505

X5R

0.1UF

6.3V
201

10%

C2504

X5R

0.1UF

6.3V
201

10%

C2508

20%
X5R

6.3V

1.0UF

0201

C2532

20%
X5R

0201

1.0UF

6.3V

C2531

20%

4.7UF

402

X5R-1

4V

C2530

20%

4.7UF

402

X5R-1

4V

C2536

X5R

C2519

6.3V
201

0.1UF

10%

X5R
201

6.3V

10%

0.1UF

C2518

X5R

6.3V
201

10%

0.1UF

C2517

X5R

10%

6.3V
201

0.1UF

C2516

X5R

0.1UF

6.3V
201

10%

C2515

X5R

6.3V
201

10%

0.1UF

C2514

X5R

0.1UF

6.3V
201

10%

C2513

X5R

0.1UF

6.3V
201

10%

C2512

X5R

C2511

0.1UF

6.3V
201

10%20%

4.7UF

402

X5R-1

4V

C2510

0603

30-OHM-5A

L2560

30-OHM-5A

0603

L2567

20%
X5R

C2500

OMIT_TABLE

10UF

603-1

6.3V

20%

4.7UF

402

X5R-1

4V

C2501

X5R

6.3V
201

0.1UF

10%

C2527

X5R

6.3V
201

0.1UF

10%

C2526

20%

402

10V
CERM

0.1UF

C2591

X5R

6.3V
201

0.1UF

10%

C2537

X5R

0.1UF

C2533

10%

201

6.3V
X5R

10%

0.1UF

201

6.3V

C2534

X5R

0.1UF

10%

6.3V
201

C2529

20%

4.7UF

402

X5R-1

4V

C2528

X5R

C2549

0.1UF

10%

6.3V
201

20%

4.7UF

603

6.3V
CERM

C2548

X5R

6.3V
201

0.1UF

10%

C2535

20%

402

10V
CERM

0.1uF

C2554

20%

4.7uF

603

6.3V
CERM

C2553

20%

402

0.1uF

CERM

10V

C2551

20%

4.7uF

603

6.3V
CERM

C2550

20%

4.7uF

603

6.3V
CERM

C2543

20%

402

0.1uF

CERM

10V

C2544

20%

402

0.1uF

CERM

10V

C2545

20%

402

C2546

CERM

10V

0.1uF

20%

402

10V

0.1uF

CERM

C2547

20%
X5R

603-1

OMIT_TABLE

10UF

6.3V

C2520

20%

4.7UF

402

X5R-1

4V

C2521

20%
X5R

6.3V
0201

1.0UF

C2522

20%
X5R

6.3V
0201

1.0UF

C2523

20%
X5R

6.3V
0201

1.0UF

C2525

20%

4.7UF

402

X5R-1

4V

C2524

20%
X5R

OMIT_TABLE

10UF

6.3V

603-1

C2560

20%

4.7UF

402

X5R-1

4V

C2561

20%
X5R

1.0UF

0201

6.3V

C2562

20%
X5R

6.3V
0201

1.0UF

C2563

X5R

0.1UF

10%

201

6.3V

C2564

20%
X5R

OMIT_TABLE

10UF

603-1

6.3V

C2567

20%

4.7UF

402

X5R-1

4V

C2568

X5R

10%

201

6.3V

0.1UF

C2569

X5R

0.1UF

10%

201

6.3V

C2565

X5R

0.1UF

6.3V
201

10%

C2566

20%

4.7UF

402

X5R-1

4V

C2540

20%

4.7UF

C2595

PLACE_NEAR=R2595.1:50 mil

CERM

6.3V
603

20%

402

0.1UF

CERM

10V

C2596

20%

402

10V
CERM

0.1uF

C2597

MF

0.33

5%

1/16W

0402

R2595

20%

402

CERM

0.1uF

10V

C2542

20%

4.7UF

CERM

603

6.3V

C2541

X5R

6.3V
201

0.1UF

10%

C2572

X5R

0.1UF

6.3V
201

10%

C2571

20%

4.7UF

402

X5R-1

4V

PLACE_NEAR=R2570.1:50 mil

C2570

MF

1/16W

0402

0.33

5%

R2570

X5R

0.1UF

6.3V
201

10%

C2573

X5R

0.1UF

6.3V
201

10%

C2578

X5R

6.3V
201

0.1UF

10%

C2577

X5R
201

0.1UF

6.3V

10%

C2576

20%

4.7UF

402

X5R-1

4V

C2575

X5R

0.1UF

6.3V
201

10%

C2583

X5R

6.3V
201

0.1UF

10%

C2582

X5R

6.3V
201

10%

0.1UF

C2581

20%

4.7UF

402

X5R-1

4V

C2580

X5R

0.1UF

6.3V
201

10%

C2579

X5R

0.1UF

6.3V
201

10%

C2584

20%

4.7UF

603

6.3V
CERM

C2552

CRITICAL

0603

220-OHM-2.2A

L2570

220-OHM-2.2A

0603

CRITICAL

L2580

220-OHM-2.2A

0603

CRITICAL

L2575

220-OHM-2.2A

L2595

CRITICAL

0603

CRITICAL

L2590

FERR-240-OHM-200MA

0402

MCPHVDD:P3V3

20%

402

0.1UF

CERM

10V

C2556

20%

4.7UF

603

CERM

6.3V

C2555

0402

FERR-240-OHM-200MA

CRITICAL

L2555

20%

4.7UF

402

X5R-1

4V

C2559

20%

4.7UF

402

X5R-1

4V

C2538

SC70

CRITICAL

OMIT_TABLE

U2590

MIC5365-2.5V

R2590

10K

201

5%

1/20W

MF

MCPHVDD:P2V5

20%
X5R

MCPHVDD:P2V5

1.0UF

0201

6.3V

C2592

201

1%

665K

1/20W

MF

HVDDLDO:ADJ

R2591

HVDDLDO:ADJ

R2592

201

1%

316K

1/20W

MF

353S2988

IC,MIC5366,LDO REG,2.5V,150MA,SC70

1 CRITICALU2590

HVDDLDO:FIXED

353S2979

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HF

1 CRITICAL

HVDDLDO:ADJ

U2590

SYNC_DATE=04/08/2010

MCP Standard Decoupling

SYNC_MASTER=K99_MLB

PP3V3_S0_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

P2V8HVDD_FB

PP3V3_S0_MCP_PLL_HVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

P2V8HVDD_EN

=PP3V3_S0_MCP_PLL_UF

=PP1V05_SW_MCP_FSB

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PE_AVDD

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.25 MM
VOLTAGE=0V

MIN_NECK_WIDTH=0.25 MM

GND_MCP_PLL_DP_USB

GND_MCP_PLL_FSB

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V

=PP0V9_ENET_MCP_RMGT

=PP3V3_S0_MCP

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_PEXSATA

PP1V05_S0_MCP_PLL_FSBMEM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_MCP_M2CLK_DLL

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_FSB

=PP3V3_S5_MCP

=PP3V3R1V5_S0_MCP_HDA

PP3V3_G3_RTC

=PP1V05_S0_MCP_AVDD_UF

=PP3V3_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

PP3V3_ENET_MCP_PLL_MAC

=PP1V05_S0_MCP_PLL_UF

=PP3V3_S0_MCP_HVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE=PP1V05_S0_MCP_PE_DVDD

=PP0V9_S5_MCP_VDD_AUXC

=PP1V5R1V35_SW_MCP_MEM

=PPVCORE_S0_MCP

25 OF 110

3.3.0

051-8467

23 OF 74

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212

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2

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2

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2

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2

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2

1

2

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2

1

2

1

2

1

21

21

21

21

21

2

1

2

1

21

2

1

2

1

2

4

5

3

1

1

2

2

1

1

2

1

2

17

16

8

8

20

20

20

8

20

8

20

16

15

8

15

8

18 20

8

20

8

14 20

8

20

8

19

8

19 20

8

8

18

8

8

20

17

8

20

8

20

15 20 21

8

20

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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IV ALL RIGHTS RESERVED

SHEET

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A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

15350 mA (0.85V)

MCP GFX Core Power

140 mA

MCP 3.3V RGBDAC Power

If RGBDAC is used, requires ferrite (155S0382)

If RGBDAC is not used, tie to GND.

plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.

160 mA

MCP 1.05V DisplayPort Power

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

X5R

C2650

6.3V
201

10%

0.1UF

MF

1/20W
201

1K

1%

X5R

C2655

6.3V
201

10%

0.1UF

NO STUFF

20%

4.7UF

402

X5R-1

4V

C2640

R2670

1/20W

0

5%

201

MF

20%
X5R

C2600

OMIT_TABLE

6.3V

10UF

603-1

20%

4.7UF

402

X5R-1

4V

C2601

20%
X5R

C2602

6.3V
0201

1.0UF

20%
X5R

C2603

1.0UF

6.3V
0201

20%
X5R

C2604

201

6.3V

0.22UF

20%
X5R

C2605

201

0.22UF

6.3V
X5R

C2606

6.3V
201

10%

0.1UF

X5R

C2607

0.1UF

6.3V
201

10%

X5R

C2608

6.3V
201

10%

0.1UF

X5R

C2609

6.3V
201

10%

0.1UF

X5R

C2610

6.3V
201

10%

0.1UF

X5R

C2611

6.3V
201

10%

0.1UF

X5R

C2612

6.3V
201

10%

0.1UF

X5R

C2641

6.3V
201

0.1UF

10%

R2650

MF
201

1%

1K

SYNC_DATE=04/08/2010

MCP Graphics Support

SYNC_MASTER=K99_MLB

=PPVCORE_SW_MCP_GFX

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

GND_MCP_DAC_P3V3

MAKE_BASE=TRUE

MCP_IFPAB_VPROBE

MCP_TMDS0_RSET
MCP_TMDS0_VPROBE

MCP_IFPAB_RSET

=PP1V05_S0_MCP_DP0_VDD

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_PLL_IFP

R2655

NO STUFF

1/20W

NO STUFF

26 OF 110

3.3.0

051-8467

24 OF 74

2

1

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1

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212

1

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1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

20 22

17

17 68

17 68

17 68

17 68

8

17

17

17

IN

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

IN

NC
NC

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

B

Y

A

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MCP S0 PWRGD & CPU_VLD

RTC Crystal

MCP 25MHz Crystal

10K pull-up to 3.3V S0 inside MCP

Platform Reset Connections

LPC Reset (Unbuffered)

System Reset Circuit

PCIE Reset (Unbuffered)

NO STUFF

MAKE_BASE=TRUE

PCIE_RESET_L

SDCARD_PLT_RST_L

BKLT_PLT_RST_L

PM_SYSRST_L

AP_RESET_L

PCA9557D_RESET_L

MCP_CLK25M_XTALIN

ALL_SYS_PWRGD

VR_PWRGOOD_DELAY

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

LPC_CLK33M_SMC_R

SMC_LRESET_L

XDP_DBRESET_L

PM_CLK32K_SUSCLK_R

PM_CLK32K_SUSCLK

LPC_RESET_L

LPCPLUS_RESET_L

PM_SYSRST_DEBOUNCE_L

MCP_CLK25M_XTALOUT_R

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

RTC_CLK32K_XTALOUT_R

RTC_CLK32K_XTALIN

MCP_PS_PWRGD

=PP3V3_S5_MCPPWRGD

SB Misc

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(02/11/2010)

R2895

MF

1/20W

201

0

5%

38

U2850

74LVC1G08GW

SOT353

19

C2850

10%

201

X5R

6.3V

0.1UF

58 50 39

54

R2894

MF

1/20W

201

0

5%

34

64

R2893

5%

0

201

1/20W

MF

33

R2891

MF

1/20W

201

0

5%

Y2810

CRITICAL

7X1.5X1.4-SM

32.768K

69 39

69 41

7

39

C2899

6.3V

0201

1.0UF

20%

X5R

NO STUFF

R2899

MF

201

33

5%

1/20W

69 19

R2829

MF

1/20W

22

5%

PLACEMENT_NOTE=Place close to U1400

201

69 39

19

19

R2816

MF

1/20W

201

1M

5%

R2815

MF

1/20W

201

0

5%

Y2815

25.0000M

CRITICAL

SM-3.2X2.5MM

C2816

25V

NP0-C0G

201

12PF

5%

C2815

25V

NP0-C0G

201

12PF

5%

69 19

R2825

MF

1/20W

201

PLACEMENT_NOTE=Place close to U1400

5%

33

R2826

MF

1/20W

201

5%

33

PLACEMENT_NOTE=Place close to U1400

16

19

19

39

41

7

R2897

OMIT

SILK_PART=SYS RST

5%

0

PLACEMENT_NOTE=Place R2897 on BOTTOM

MF-LF

1/16W

402

R2881

MF

1/20W

201

PLACEMENT_NOTE=Place close to U1400

33

5%

R2883

MF

1/20W

201

PLACEMENT_NOTE=Place close to U1400

5%

33

R2896

MF

1/20W

201

0

5%

XDP

69 19

R2811

10.0M

0201

1/20W

MF

5%

NO STUFF

R2810

MF

1/20W

201

0

5%

C2811

25V

NP0-C0G

201

12PF

5%

C2810

25V

NP0-C0G

201

12PF

5%

19 13 10

28 OF 110

3.3.0

051-8467

25 OF 74

1 2

1 2

1 2

1

2

1 2

1 2

1 2

1

2

1 2

1 2

1 2

1 2

31

2 4

1 2

1

2

1 2

1 2

2

1

41

1 2

1 2

1 2

2

1

4

3

1

2

5

1 2

8

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CS1 IS FOR 2G DDP RANK CONTROL

A14/A15 FOR 2G/4G MONO ONLY

NC

NC NC

NC

NC

NC

NC

NCNC

NC

NC

NC

U3100

OMIT_TABLE

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

MEM_A_ZQ0

FBGA

20%

0.47UF

201

CERM-X5R-1

4V

C3102

20%

0.47UF

201

CERM-X5R-1

4V

C3101

20%

0.47UF

201

CERM-X5R-1

4V

C3100

201

240

1%MF1/20W

R3100

20%

0.47UF

201

CERM-X5R-1

4V

C3112

20%

0.47UF

201

CERM-X5R-1

4V

C3111

20%

0.47UF

201

CERM-X5R-1

4V

C3110

201

1/20W

240

MF

1%

R3110

FBGA

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

OMIT_TABLE

U3110

20%

0.47UF

201

CERM-X5R-1

4V

C3122

20%

0.47UF

201

CERM-X5R-1

4V

C3121

20%

0.47UF

201

CERM-X5R-1

4V

C3120

201

1/20W

240

MF

1%

R3120

FBGA

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

OMIT_TABLE

U3120

20%

0.47UF

201

CERM-X5R-1

4V

C3132

20%

0.47UF

201

CERM-X5R-1

4V

C3131

20%

0.47UF

201

CERM-X5R-1

4V

C3130

201

240

1/20WMF1%

R3130

U3130

FBGA

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

OMIT_TABLE

DDR3 DRAM Channel A (0-31)

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MEM_A_DQ<24>

MEM_A_DQS_P<3>

MEM_A_CKE<1>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_A<14>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_A<6>

MEM_A_DM<2>

MEM_A_DQ<9>

MEM_A_DQ<14>

MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<14>

MEM_A_CLK_N<0>

MEM_A_ODT<1>

MEM_A_RAS_L

MEM_A_ZQ1

MEM_A_CKE<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<1>
MEM_A_A<2>

MEM_A_A<0>

MEM_A_DM<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQ<15>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<12>

MEM_A_ZQ1

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PPLVDDR_S3_MEM_A

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_A<12>
MEM_A_A<13>

MEM_A_A<11>

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ2

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<0>

PPVREF_S3_MEM_VREFCA

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQ<21>

MEM_A_DQ<18>

MEM_A_DQ<16>

MEM_A_DQ<22>

MEM_A_DQ<23>
MEM_A_DQ<20>

MEM_A_DQ<19>
MEM_A_DQ<17>

MEM_A_ZQ2

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PPLVDDR_S3_MEM_A

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12>
MEM_A_A<13>

MEM_A_A<11>

MEM_A_ZQ3

MEM_A_ODT<1>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<1>
MEM_A_A<2>

MEM_A_A<0>

PPVREF_S3_MEM_VREFDQ

PPVREF_S3_MEM_VREFCA

MEM_A_DM<3>

MEM_A_DQS_N<3>

MEM_A_DQ<29>

MEM_A_DQ<27>
MEM_A_DQ<26>

MEM_A_DQ<28>
MEM_A_DQ<25>

MEM_A_ZQ3

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PPLVDDR_S3_MEM_A

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_A<12>
MEM_A_A<13>

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_A<4>

MEM_A_DQ<8>

PPVREF_S3_MEM_VREFDQ

PPVREF_S3_MEM_VREFCA

MEM_RESET_L

MEM_A_ODT<0>

PPVREF_S3_MEM_VREFDQ

MEM_A_WE_L

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_CLK_N<0>

MEM_A_ODT<0>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

=PPLVDDR_S3_MEM_A

MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_DQ<1>

MEM_A_DQ<7>

MEM_A_DQ<3>

MEM_A_DQ<0>

MEM_A_DQ<4>
MEM_A_DQ<2>
MEM_A_DQ<5>
MEM_A_DQ<6>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_DM<0>

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<8>

MEM_RESET_L

MEM_A_BA<2>
MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<9>
MEM_A_A<10>

MEM_A_ODT<1>

MEM_A_ZQ0

MEM_A_A<14>

MEM_A_CKE<1>

31 OF 110

3.3.0

051-8467

26 OF 74

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

1 2

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

15 67

15 67

15 21 26
27 32 67

15 67

15 67

15 26
27 32

67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 67

15 67

15 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

26

15 21 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67 15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26
27 32 67

15 26
27 32 67

26

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

15 26 27 28 29

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

26 27 28 29 33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

26

15 26 27
32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

15 26 27 28 29

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

26 27 28 29 33

26 27 28 29 33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 67

26 27 28 29 33

26 27 28 29 33

15 26 27 28 29

15 26 27 32 67

26 27 28 29 33

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

26 27 28 29 33

26 27 28 29 33

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 28 29

15 26 27 32 67

15 21 26 27 32
67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27
32 67

26

15 26 27 32 67

15 21 26 27 32 67

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

NC

NCNC

NC

NC

NC

A14/A15 FOR 2G/4G MONO ONLY

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC

NC

NC

NC

NC

NC

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC

NC

C3232

4V
CERM-X5R-1
201

0.47UF

20%

C3220

4V

CERM-X5R-1

201

0.47UF

20%

R3230

1%MF1/20W

240

201

U3230

OMIT_TABLE

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

FBGA

R3220

1%MF1/20W

240

201

U3220

OMIT_TABLE

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

FBGA

C3212

4V
CERM-X5R-1
201

0.47UF

20%

C3211

4V

CERM-X5R-1

201

0.47UF

20%

C3210

4V

CERM-X5R-1

201

0.47UF

20%

C3202

4V
CERM-X5R-1
201

0.47UF

20%

C3201

4V

CERM-X5R-1

201

0.47UF

20%

C3200

4V

CERM-X5R-1

201

0.47UF

20%

C3231

4V

CERM-X5R-1

201

0.47UF

20%

R3210

1%MF1/20W

240

201

U3210

OMIT_TABLE

128MX8-SDRAM-1066MHZ

FBGA

MT41J128M8HX-187E

R3200

1%MF1/20W

240

201

U3200

OMIT_TABLE

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

FBGA

C3230

4V

CERM-X5R-1

201

0.47UF

20%

C3222

4V
CERM-X5R-1
201

0.47UF

20%

C3221

4V

CERM-X5R-1

201

0.47UF

20%

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

DDR3 DRAM Channel A (32-63)

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ

=PPLVDDR_S3_MEM_A

=PPLVDDR_S3_MEM_A

PPVREF_S3_MEM_VREFCA

MEM_A_ODT<0>

PPVREF_S3_MEM_VREFDQ

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ11

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<1>
MEM_A_A<2>

MEM_A_A<0>

MEM_A_DM<7>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<60>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<58>

MEM_A_DQ<63>
MEM_A_DQ<56>

MEM_A_DQ<59>
MEM_A_DQ<57>

MEM_A_ZQ11

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PPLVDDR_S3_MEM_A

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12>
MEM_A_A<13>

MEM_A_A<11>

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ10

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<1>
MEM_A_A<2>

MEM_A_A<0>

PPVREF_S3_MEM_VREFDQ

MEM_A_DM<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<48>

MEM_A_DQ<55>
MEM_A_DQ<51>

MEM_A_DQ<50>
MEM_A_DQ<49>

MEM_A_ZQ10

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_A<12>
MEM_A_A<13>

MEM_A_A<11>

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ8

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<1>
MEM_A_A<2>

MEM_A_A<0>

PPVREF_S3_MEM_VREFDQ

PPVREF_S3_MEM_VREFCA

MEM_A_DM<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQ<32>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34>
MEM_A_DQ<35>

MEM_A_DQ<39>
MEM_A_DQ<33>

MEM_A_ZQ8

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

=PPLVDDR_S3_MEM_A

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12>
MEM_A_A<13>

MEM_A_A<11>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_A<14>

MEM_A_ZQ9

MEM_A_ODT<1>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_CKE<0>

MEM_RESET_L

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<1>
MEM_A_A<2>

MEM_A_A<0>

MEM_A_DM<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQ<42>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQ<43>

MEM_A_DQ<44>
MEM_A_DQ<45>

MEM_A_DQ<41>
MEM_A_DQ<46>

MEM_A_ZQ9

MEM_A_A<3>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_BA<1>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_N<0>

MEM_A_A<12>
MEM_A_A<13>

MEM_A_A<11>

32 OF 110

3.3.0

051-8467

27 OF 74

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

26 27 28 29 33

26 27 28 29 33

26 27 28 29 33

8

26 27 30

26 27 28 29 33

15 26 27 32 67

26 27 28 29 33

15 21 26 27
32 67

15 26 27
32 67

27

15 26 27 32
67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

15 26 27 28 29

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26
27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

27

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

15 26 27 28 29

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

26 27 28 29 33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

27

15 26 27
32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

15 26 27 28 29

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

26 27 28 29
33

26 27 28 29
33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 32 67

27

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 21 26 27 32 67

15 26 27 28 29

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

15 26 27 32 67

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC NC

NCNC

NC

NC

A14/A15 FOR 2G/4G MONO ONLY
CS1 IS FOR 2G DDP RANK CONTROL

NC

NC

NCNC

NC

NC

U3300

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

MEM_B_ZQ0

FBGA

OMIT_TABLE

C3302

4V
CERM-X5R-1
201

0.47UF

20%

C3301

4V

CERM-X5R-1

201

0.47UF

20%

C3300

4V

CERM-X5R-1

201

0.47UF

20%

R3300

1/20WMF1%

240

201

C3312

4V
CERM-X5R-1
201

0.47UF

20%

C3311

4V

CERM-X5R-1

201

0.47UF

20%

C3310

4V

CERM-X5R-1

201

0.47UF

20%

R3310

1%MF1/20W

240

201

U3310

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

FBGA

OMIT_TABLE

C3322

4V
CERM-X5R-1
201

0.47UF

20%

C3321

4V

CERM-X5R-1

201

0.47UF

20%

C3320

4V

CERM-X5R-1

201

0.47UF

20%

R3320

1%MF1/20W

240

201

U3320

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

FBGA

OMIT_TABLE

C3332

4V
CERM-X5R-1
201

0.47UF

20%

C3331

4V

CERM-X5R-1

201

0.47UF

20%

C3330

4V

CERM-X5R-1

201

0.47UF

20%

R3330

1%MF1/20W

240

201

U3330

128MX8-SDRAM-1066MHZ

MT41J128M8HX-187E

FBGA

OMIT_TABLE

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

DDR3 DRAM Channel B (0-31)

MEM_B_DQ<11>

PPVREF_S3_MEM_VREFDQ

MEM_B_BA<2>

MEM_B_DQ<12>

MEM_B_A<3>

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<7>

MEM_B_A<1>

MEM_B_DQ<3>

MEM_B_A<3>

MEM_B_ODT<0>

MEM_B_CKE<1>

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ3

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<28>

MEM_B_DQ<24>

MEM_B_DQ<27>
MEM_B_DQ<25>
MEM_B_DQ<31>
MEM_B_DQ<26>

MEM_B_DQS_P<3>
MEM_B_DQS_N<3>

MEM_B_DM<3>

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>
MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9>
MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ3

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_ZQ2

MEM_B_DQ<22>

MEM_B_DQ<16>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<23>

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>

MEM_B_DM<2>

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9>
MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ2

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_ZQ1

MEM_B_DQ<9>

MEM_B_DQ<14>

MEM_B_DQ<8>

MEM_B_DQ<10>
MEM_B_DQ<13>

MEM_B_DQ<15>

MEM_B_DQS_P<1>
MEM_B_DQS_N<1>

MEM_B_DM<1>

PPVREF_S3_MEM_VREFCA

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>
MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9>
MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ1

MEM_B_A<14>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_CLK_N<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

=PPLVDDR_S3_MEM_B

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_DQ<4>
MEM_B_DQ<2>

MEM_B_DQ<5>
MEM_B_DQ<6>

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_DM<0>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<8>

MEM_RESET_L

MEM_B_BA<2>
MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<9>
MEM_B_A<10>

MEM_B_ODT<1>

MEM_B_ZQ0

MEM_B_A<14>

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ

33 OF 110

3.3.0

051-8467

28 OF 74

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

1 2

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

15 67

26 27 28 29 33

15 28 29 32 67

15 67 15 28 29 32 67

15 67

15 67

15 67

15 28 29 32 67

15 67 15 28 29 32 67

15 28 29 32 67

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15 28
29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28
29 32 67

8

28 29 31

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

26 27 28 29 33

26 27 28 29 33

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 26 27 28 29

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29
32 67

28

15 28
29 32

67

15 21 28
29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

8

28 29 31

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

26 27 28 29 33

26 27 28 29 33

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 26 27 28 29

15 21 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

28

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29
32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

8

28 29 31

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

26 27 28 29 33

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 26 27 28 29

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

28

15 28 29 32 67

15 21 28 29 32 67

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15 21 28 29 32
67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

28

15 28 29 32 67

26 27 28 29 33

26 27 28 29 33

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

A11

A13

A12/BC*

CK*

ODT

CS*

NC

VSS

VSSQ

WE*

CAS*

RAS*

VDDQ

VDD

BA1

CK

A5

A3

ZQ

DQ1

DQ0

DQ3

DQ2

DQ4
DQ5
DQ6
DQ7

DQS

DQS*

DM/TDQS

TDQS*

VREFCA

VREFDQ

A0

A2

A1

A7

A6

A4

A8

RESET*

NC

BA2

CKE

BA0

A9
A10/AP

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

NCNC

NC

NC

A14/A15 FOR 2G/4G MONO ONLY

NC

NC

NC

NC

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC

20%

0.47UF

201

CERM-X5R-1

4V

C3432

20%

0.47UF

201

CERM-X5R-1

4V

C3420

201

240

1/20WMF1%

R3430

OMIT_TABLE

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

FBGA

U3430

201

240

1/20WMF1%

R3420

OMIT_TABLE

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

FBGA

U3420

20%

0.47UF

201

CERM-X5R-1

4V

C3412

20%

0.47UF

201

CERM-X5R-1

4V

C3411

20%

0.47UF

201

CERM-X5R-1

4V

C3410

20%

0.47UF

201

CERM-X5R-1

4V

C3402

20%

0.47UF

201

CERM-X5R-1

4V

C3401

20%

0.47UF

201

CERM-X5R-1

4V

C3400

20%

0.47UF

201

CERM-X5R-1

4V

C3431

201

240

1/20WMF1%

R3410

OMIT_TABLE

FBGA

MT41J128M8HX-187E

128MX8-SDRAM-1066MHZ

U3410

201

240

1/20WMF1%

R3400

OMIT_TABLE

MT41J128M8HX-187E

FBGA

128MX8-SDRAM-1066MHZ

U3400

20%

0.47UF

201

CERM-X5R-1

4V

C3430

20%

0.47UF

201

CERM-X5R-1

4V

C3422

20%

0.47UF

201

CERM-X5R-1

4V

C3421

DDR3 DRAM Channel B (32-63)

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MEM_B_DQ<61>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_DQ<49>

MEM_B_DQ<55>

MEM_B_DQS_P<6>
MEM_B_DQS_N<6>

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_ZQ9

MEM_B_ODT<1>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_RESET_L

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<6>
MEM_B_A<7>

MEM_B_A<1>
MEM_B_A<2>

MEM_B_A<0>

PPVREF_S3_MEM_VREFCA

MEM_B_DM<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQ<40>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<42>
MEM_B_DQ<47>

MEM_B_DQ<43>
MEM_B_DQ<41>

MEM_B_ZQ9

MEM_B_A<3>

MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_CLK_N<0>

MEM_B_A<12>
MEM_B_A<13>

MEM_B_A<11>

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_ZQ10

MEM_B_A<10>

MEM_B_A<9>

MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_RESET_L

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<1>
MEM_B_A<2>

MEM_B_A<0>

PPVREF_S3_MEM_VREFDQ

PPVREF_S3_MEM_VREFCA

MEM_B_DM<6>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<48>

MEM_B_DQ<53>

MEM_B_ZQ10

MEM_B_A<3>

MEM_B_A<5>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_CLK_N<0>

MEM_B_A<12>
MEM_B_A<13>

MEM_B_A<11>

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_ZQ11

MEM_B_ODT<1>

MEM_B_A<10>

MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_RESET_L

MEM_B_A<4>

MEM_B_A<6>
MEM_B_A<7>

MEM_B_A<1>
MEM_B_A<2>

MEM_B_A<0>

PPVREF_S3_MEM_VREFDQ

PPVREF_S3_MEM_VREFCA

MEM_B_DM<7>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>
MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_ZQ11

MEM_B_A<3>

MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_CLK_N<0>

MEM_B_A<12>
MEM_B_A<13>

MEM_B_A<11>

MEM_B_CLK_P<0>

MEM_B_CAS_L

PPVREF_S3_MEM_VREFDQ

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_ZQ8

MEM_B_ODT<1>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_RESET_L

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<1>
MEM_B_A<2>

MEM_B_A<0>

PPVREF_S3_MEM_VREFDQ

PPVREF_S3_MEM_VREFCA

MEM_B_DM<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQ<39>

MEM_B_DQ<34>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<35>
MEM_B_DQ<32>

MEM_B_DQ<38>
MEM_B_DQ<33>

MEM_B_ZQ8

MEM_B_A<3>

MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_BA<1>

=PPLVDDR_S3_MEM_B

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_CLK_N<0>

MEM_B_A<12>
MEM_B_A<13>

MEM_B_A<11>

34 OF 110

3.3.0

051-8467

29 OF 74

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

1 2

M7

N3

K7

G7

G1

H2
H1

A1A8B1D8F2F8J1J9L1L9N9N1B2B8C9D1D9

H3

G3

F3

E9

E2

C1

B9

M9

M1

K9

K1

G8

G2

D7

A9

A2

K8

F7

L2

K2

H8

C7

B3

C8

C2

E3
E8
D2
E7

C3
D3

B7
A7

J8

E1

K3

L3

L7

M2

M8

L8

N8

N2

A3

J3
G9

J2

M3
H7

J7

F1

H9
N7

F9

2

1

2

1

2

1

15 67

15 28 29 32 67

15 28 29 32 67

15 67

15 67

15 67

15 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

29

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

15 26 27 28 29

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

26 27 28 29 33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

8

28 29 31

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29
32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 21 28
29 32 67

15 28 29 32 67

29

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

15 26 27 28 29

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

26 27 28 29 33

26 27 28 29 33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 21 28 29
32 67

15 28 29
32 67

29

15 28 29 32
67

15 28 29 32 67

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

15 26 27 28 29

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

26 27 28 29 33

26 27 28 29 33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

8

28 29 31

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

26 27 28 29 33

15 21 28 29 32 67

15 28 29 32 67

29

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 21 28 29 32 67

15 28 29 32 67

15 26 27 28 29

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

26 27 28 29
33

26 27 28 29
33

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

15 28 29 32 67

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

2 CAPS ALONG PACKAGE EDGE2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGESCOLUMN OF THREE CAPS BETWEEN PACKAGES

CERM
402-LF

2.2UF

6.3V

20%

OMIT_TABLE

C3540

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3541

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3542

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3550

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3551

402-LF

20%

2.2UF

6.3V
CERM

OMIT_TABLE

C3530

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3531

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3554

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3555

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3544

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3545

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3546

CERM

20%

2.2UF

6.3V
402-LF

OMIT_TABLE

C3534

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3535

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3520

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3521

CERM

20%

6.3V
402-LF

2.2UF

OMIT_TABLE

C3510

CERM

20%

2.2UF

6.3V
402-LF

OMIT_TABLE

C3511

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3512

CERM

20%

6.3V
402-LF

2.2UF

OMIT_TABLE

C3500

2.2UF

CERM
402-LF

20%

6.3V

OMIT_TABLE

C3501

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3524

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3525

CERM

20%
402-LF

6.3V

2.2UF

OMIT_TABLE

C3514

20%
CERM

402-LF

6.3V

2.2UF

OMIT_TABLE

C3515

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3516

CERM
402-LF

20%

6.3V

2.2UF

OMIT_TABLE

C3504

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3505

DDR BYPASSING 1

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

=PPLVDDR_S3_MEM_A=PPLVDDR_S3_MEM_A

35 OF 110

3.3.0

051-8467

30 OF 74

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

8

26 27 30

8

26 27 30

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGESCOLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

C3640

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3641

402-LF

20%

6.3V

2.2UF

CERM

OMIT_TABLE

C3642

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3650

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3651

2.2UF

CERM
402-LF

20%

6.3V

OMIT_TABLE

C3630

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3631

CERM
402-LF

20%

6.3V

2.2UF

OMIT_TABLE

C3654

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3655

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3644

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3645

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3646

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3634

CERM

20%

2.2UF

6.3V
402-LF

OMIT_TABLE

C3635

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3620

CERM

20%

2.2UF

6.3V
402-LF

OMIT_TABLE

C3621

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3610

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3611

6.3V
402-LF

CERM

20%

2.2UF

OMIT_TABLE

C3612

CERM
402-LF

20%

6.3V

2.2UF

OMIT_TABLE

C3600

402-LF

CERM

6.3V

20%

2.2UF

OMIT_TABLE

C3601

CERM
402-LF

2.2UF

20%

6.3V

OMIT_TABLE

C3624

20%
402-LF

CERM

6.3V

2.2UF

OMIT_TABLE

C3625

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3614

2.2UF

20%
CERM

402-LF

6.3V

OMIT_TABLE

C3615

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3616

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3604

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

C3605

CERM
402-LF

20%

2.2UF

6.3V

OMIT_TABLE

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

DDR BYPASSING 2

=PPLVDDR_S3_MEM_B=PPLVDDR_S3_MEM_B

36 OF 110

3.3.0

051-8467

31 OF 74

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

8

28 29 31

8

28 29 31

IN

IN

IN
IN
IN

IN
IN
IN
IN

IN
IN
IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN
IN

IN
IN

IN
IN
IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Place Source Cterm at neckdown at first DRAM

Place RC end termination after last DRAM

MEM CLOCK TERMINATION

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

15 26 27 67

15 26 27 67

RP3702

4X0201

36

1/32W

5%

RP3702

36

4X0201

5%

1/32W

RP3706

4X0201

1/32W

5%

36

RP3702

4X0201

5%

1/32W

36

RP3702

4X0201

36

5%

1/32W

RP3704

5%

1/32W

36

4X0201

RP3707

36

5%

1/32W

4X0201

RP3703

4X0201

1/32W

5%

36

RP3704

4X0201

5%

1/32W

36

RP3703

5%

1/32W

4X0201

36

RP3703

4X0201

5%

1/32W

36

RP3703

4X0201

1/32W

5%

36

RP3704

4X0201

1/32W

5%

36

R3790

1/20W

5%

36

201

RP3706

36

5%

1/32W

4X0201

RP3706

5%

36

4X0201

1/32W

RP3701

1/32W

5%

4X0201

36

RP3701

4X0201

36

5%

1/32W

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 21 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

R3700

5%

1/20W

MF

30

201

R3701

5%

30

MF

1/20W

201

C3700

0.1UF

MEM_A_CLK_TERM_R

10%
X5R

6.3V

201

C3702

6.3V

X5R

0.1UF

10%
201

R3704

30

MF

1/20W

5%

201

R3705

30

5%
MF

1/20W

201

RP3701

5%

1/32W

36

4X0201

RP3701

5%

1/32W

36

4X0201

RP3707

5%

1/32W

36

4X0201

RP3704

4X0201

5%

1/32W

36

RP3706

4X0201

5%

1/32W

36

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

15 26 27 67

RP3715

1/32W

5%

36

4X0201

RP3715

5%

36

4X0201

1/32W

RP3715

1/32W

5%

36

4X0201

RP3711

1/32W

5%

36

4X0201

RP3709

1/32W

5%

36

4X0201

RP3715

1/32W

36

5%

4X0201

RP3710

4X0201

1/32W

36

5%

RP3709

4X0201

1/32W

5%

36

RP3711

1/32W

5%

36

4X0201

RP3709

4X0201

5%

1/32W

36

RP3708

5%

1/32W

36

4X0201

RP3708

5%

1/32W

36

4X0201

RP3711

5%361/32W

4X0201

RP3709

4X0201

36

5%

1/32W

RP3708

5%361/32W

4X0201

RP3713

5%361/32W

4X0201

RP3710

5%361/32W

4X0201

RP3710

5%

1/32W

36

4X0201

RP3710

5%

1/32W

36

4X0201

RP3708

1/32W

36

4X0201

5%

RP3713

5%

1/32W

36

4X0201

RP3714

1/32W

5%

4X0201

36

RP3714

1/32W

5%

4X0201

36

RP3714

1/32W

5%

36

4X0201

RP3714

1/32W

5%

36

4X0201

RP3713

1/32W

5%

36

4X0201

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 21 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 28 29 67

15 21 28 29 67

15 28 29 67

15 28 29 67

C3704

CERM

25V

5%

3.3PF

201

C3706

3.3PF

5%
25V
CERM
201

C3710

4V
CERM-X5R-1
201

0.47UF

20%

C3713

4V
CERM-X5R-1
201

0.47UF

20%

C3712

4V
CERM-X5R-1
201

0.47UF

20%

C3715

4V
CERM-X5R-1
201

0.47UF

20%

C3714

4V
CERM-X5R-1
201

0.47UF

20%

C3717

4V
CERM-X5R-1
201

0.47UF

20%

C3716

4V
CERM-X5R-1
201

0.47UF

20%

C3718

4V
CERM-X5R-1
201

0.47UF

20%

C3720

4V
CERM-X5R-1
201

0.47UF

20%

C3722

4V
CERM-X5R-1
201

0.47UF

20%

C3724

4V
CERM-X5R-1
201

0.47UF

20%

C3727

4V
CERM-X5R-1
201

0.47UF

20%

C3726

4V
CERM-X5R-1
201

0.47UF

20%

C3729

4V
CERM-X5R-1
201

0.47UF

20%

C3728

4V
CERM-X5R-1
201

0.47UF

20%

C3730

4V
CERM-X5R-1
201

0.47UF

20%

C3733

4V
CERM-X5R-1
201

0.47UF

20%

C3732

4V
CERM-X5R-1
201

0.47UF

20%

RP3707

5%

36

4X0201

1/32W

15 26 27 67

R3791

5%

36

1/20W

201

R3793

5%

36

1/20W

201

R3792

1/20W

36

5%

201

RP3713

36

1/32W

5%

4X0201

15 21 26 27 67

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

Memory Active Termination

MEM_B_ODT<0>

MEM_B_BA<2>
MEM_B_RAS_L

MEM_B_A<7>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_A<2>

MEM_B_A<12>

MEM_B_A<3>

MEM_B_A<13>

MEM_B_BA<1>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_CKE<1>

MEM_B_ODT<1>

MEM_B_BA<0>

MEM_B_A<1>

MEM_B_A<14>

MEM_B_WE_L
MEM_B_A<9>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<0>

MEM_A_A<12>
MEM_A_A<8>

MEM_A_A<14>

MEM_A_A<7>

MEM_A_CS_L<1>

MEM_A_CAS_L
MEM_A_RAS_L

MEM_B_CAS_L
MEM_B_A<8>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<1>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_A<9>

MEM_B_CLK_TERM_R

VOLTAGE=0V

VOLTAGE=0V

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<11>

MEM_A_A<2>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CKE<1>

MEM_A_A<0>

MEM_A_BA<1>

=PPDDRVTT_S0_MEM_A

=PPDDRVTT_S0_MEM_B

MEM_B_CLK_P<0>

MEM_A_BA<0>

MEM_A_A<3>

MEM_A_CLK_N<0>

37 OF 110

3.3.0

051-8467

32 OF 74

1 8
2 7
4 5
3 6

4 5

1 8

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1 8
4 5

1 2

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1 8
4 5
2 7

1 2

1 2

2

1

2

1

1 2

1 2

1 8
3 6

2 7

2 7
3 6

3 6
4 5

2 7

1 8
1 8

1 8

3 6

3 6

2 7

2 7

1 8

2 7

3 6

4 5

3 6
4 5

4 5

2 7

1 8

4 5

3 6

2 7

1 8

4 5

3 6

2 7

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1 8

1 2

1 2

1 2

1 8

15 26 27 67

15 28 29 67

8

8

15 28 29 67

15 26 27 67

OUT

OUT

V-

V+

V-

V+

V-

V+

V-

V+

IN

NC

NC

NC

RESET*

A0
A1
A2

SCL
SDA

P0
P1
P2

P5
P6
P7

P3
P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

watchdog will disable margining.
NOTE: Margining will be disabled across all

soft-resets and sleep/wake cycles.

Required zero ohm resistors when no VREF margining circuit stuffed

MEM VREF CAMEM VREF DQ

NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable

(RSVD for FBVREF)

both at the same time!

7.69mV / step @ output

+3.4mA - -3.4mA (- = sourced)

0.300V - 1.200V (+/- 450mV)

0.75V (DAC: 0x3A)

9.24mV / step @ output

0.000V - 1.191V (0x00 - 0x5C)

0.200V - 1.050V (+/- 500mV)

0.7V (DAC: 0x8B)

CPU GTLREF (FSB)

7

10mA max load

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

- =PPVTT_S3_DDR_BUF

Circuitry.

Circuitry.

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

- =I2C_VREFDACS_SCL

- =PP3V3_S3_VREFMRGN

3

C

0.000V - 1.501V (0x00 - 0x74)

A
1

Margined target:

VRef current:
DAC step size:

Nominal value

DAC range:

PCA9557D Pin:

DAC Channel:

D
5

MEM VREG

8.59mV / step @ output

1.998V - 1.002V (+/- 498mV)

0.000V - 1.501V (0x00 - 0x74)

1.5V (DAC: 0x3A)

D

+33uA - -33uA (- = sourced) +750uA - -528uA (- = sourced)

VREFMRGN:NO - Bypasses VREF Margining

Addr=0x98(WR)/0x99(RD)

Addr=0x30(WR)/0x31(RD)

BOM options provided by this page:
VREFMRGN:YES - Stuffs VREF Margining

buffers at once or VRef source may be overloaded.

NOTE: Must not enable more than two SO-DIMM margining

RST* on ’platform reset’ so that system

(OD)

53

C3910

201

10%
X5R

6.3V

0.1UF

VREFMRGN:YES

R3942

22.6K

1%

PLACE_NEAR=R7320.2:1mm

VREFMRGN:YES

MF

1/20W

201

R3940

VREFMRGN:YES

100K

201

1/20W
MF

5%

R3945

201

1/20W
MF

VREFMRGN:YES

5%

100K

10 66

R3944

1%

PLACE_NEAR=R1005.2:1mm

267

VREFMRGN:YES

MF

1/20W

201

B4

B1

U3920

VREFMRGN:YES

UCSP

MAX4253

CRITICAL

B4

B1

U3920

UCSP

MAX4253

VREFMRGN:YES

CRITICAL

B4

B1

U3940

VREFMRGN:YES

MAX4253

UCSP

CRITICAL

B4

B1

U3940

VREFMRGN:YES

MAX4253

UCSP

CRITICAL

R3900

NONE

OMIT

SHORT

402

NONE
NONE

R3910

OMIT

NONE

SHORT

NONE

402

NONE

25

R3921

PLACE_NEAR=U3230.E1.1:2.54MM

201

1/20W

MF

VREFMRGN:YES

1%

200

R3922

PLACE_NEAR=R3921.2:1MM

201

1/20W

MF

VREFMRGN:YES

133

1%

R3923

PLACE_NEAR=U3230.J8:2.54MM

VREFMRGN:YES

1/20W

MF

1%

200

201

R3924

PLACE_NEAR=R3923.2:1MM

201

1/20W

MF

1%

133

VREFMRGN:YES

R3925

100K

201

1/20W
MF

VREFMRGN:YES

5%

R3920

MF

100K

1/20W

5%

201

VREFMRGN:YES

QFN

PCA9557

U3910

VREFMRGN:YES

CRITICAL

42

42

CRITICAL

MSOP

DAC5574

VREFMRGN:YES

U3900

42

42

C3901

10%
201

X5R

6.3V

VREFMRGN:YES

0.1UF

C3900

VREFMRGN:YES

2.2UF

CERM

402-LF

20%

6.3V

C3940

10%
201

X5R

6.3V

VREFMRGN:YES

0.1UF

C3920

0.1UF

VREFMRGN:YES

6.3V
X5R
201

10%

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

FSB/DDR3 Vref Margining

RES,MF,1/20W,0.0 OHM,5,0201,SMD

117S0002

2

VREFMRGN:NOR3921,R3923

VREFMRGN_CA_DRAM_EN

VREFMRGN_CPUGTLREF_EN

PCA9557D_RESET_L

VREFMRGN_MEMVREG_EN

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_MEMVREG_BUF

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm

=I2C_VREFDACS_SDA

MIN_LINE_WIDTH=0.3 mm

PPVREF_S3_MEM_VREFDQ

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

CPU_GTLREF

DDRREG_FB

VREFMRGN_CPUGTLREF_BUF

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

VREFMRGN_DQ_BUF

VREFMRGN_DQ_DRAM_EN

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

VREFMRGN_DQ_DRAM

VREFMRGN_CA_DRAM

=I2C_VREFDACS_SCL

VREFMRGN_CA_BUF

=PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.15 MM

PPVREF_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3 mm
VOLTAGE=0.75V

=PP3V3_S3_VREFMRGN

39 OF 110

3.3.0

051-8467

33 OF 74

2

1

1 2

1

2

1

2

1 2

C4

C1

C3

C2

A4

A1

A3

A2

A4

A1

A3

A2

C4

C1

C3

C2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

12

15

3
4
5

1
2

6
7
9

12
13
14

16

10
11

17

8

8

3

5

4

2

16

7

9

10

2

1

2

1

2

1

2

1

26 27 28 29

8

53

26 27 28 29

8

OUT

IN

IN

IN

IN

IN

BI

BI

OUT
OUT

OUT
OUT

S

G

D

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

OUT

IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BLUETOOTH

AIRPORT

RDS(ON)

LOADING

MOSFET

20-30 MOHM @2.5V

TPCP8102

3V S3 WLAN FET

P-TYPE

0.750 A (EDP)

CHANNEL

514S0335

DLY = 60 MS +/- 20%

7

16

58

0.1UF

X5R201

PLACEMENT_NOTE=Place close to J4001.

10%

6.3V

C4030

16 68

16 68

0.1UF

PLACEMENT_NOTE=Place close to J4001.

6.3V

10% 201X5R

C4031

7

16 68

7

16 68

6.3V

10%
201

X5R

0.1UF

PLACEMENT_NOTE=Place close to Q4050.

C4021

7

18 69

7

18 69

10V

20%
805

X5R

10UF

PLACEMENT_NOTE=Place close to Q4050.

C4020

7

16 68

7

16 68

1%

CRITICAL

0.25W

0.020

805

MF-LF

R4052

43 72

43 72

CRITICAL

23V1K-SM

TPCP8102

Q4050

TDFN

SLG4AP016V

CRITICAL

U4002

201

6.3V

10%
X5R

0.1UF

C4053

16

25

19 58

5%

201

MF

100K

1/20W

R4053

1/20W

1%

201

MF

100K

R4055

1/20W

1%

201

MF

232K

R4054

PLACE_NEAR=J4001.27:1.5mm

0.1UF

X5R
201

10%

6.3V

C4032

SSD-K99

CRITICAL

F-RT-SM1

J4001

7

39 40

10%
16V

402

X5R

0.1UF

C4050

16V

10%
402

0.033UF

X5R

C4051

1/20W

5%

201

MF

100K

R4050

5%
1/20W

201

MF

10K

R4051

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

X21 WIRELESS CONNECTOR

PCIE_AP_R2D_C_N

PCIE_AP_R2D_N

USB_BT_P

USB_BT_N

AP_CLKREQ_Q_L

=PP3V3_S3_WLAN

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

PP3V3_WLAN_F

AP_PWR_EN

P3V3WLAN_VMON

AP_RESET_L

AP_CLKREQ_L

P3V3WLAN_SS

PM_WLAN_EN_L

ISNS_AIRPORT_P

PCIE_AP_R2D_C_P

PCIE_AP_R2D_P

AP_RESET_CONN_L

PCIE_WAKE_L

PCIE_AP_D2R_P

=PP3V3_S3_BT

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

ISNS_AIRPORT_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.25 mm

PP3V3_WLAN_R

WIFI_EVENT_L

PCIE_AP_D2R_N

=PP3V3_S3_WLAN

40 OF 110

3.3.0

051-8467

34 OF 74

1 2

1 2

2

1

2

1

43

21

7 85 6

4

31 2

4

8

6

3

5

9

7

1

2

2

1

1

2

1

2

1

2

2

1

18

21

19
20

10
11
12

13

16

15

14

17

9

1
2
3
4
5
6
7
8

1 2

2

1

1 2

1

2

7

68

7

8

34

7

40

7

68

7

7 8

OUT

OUT

NC
NC

OUT

OUT

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SATA SSD

0612

MF

1W

0.003

1%

CRITICAL

R4599

43 72

43 72

CRITICAL

SSD-K99

F-RT-SM1

J4501

201

5%
MF

0

1/20W

R4510

201

0

1/20W

MF

5%

R4511

0.1UF

20%
CERM

10V

PLACE_NEAR=J4501.1:1.5mm

402

C4501

18 68

18 68

18 68

18 68

X5R10V10% 201

0.01UF

PLACE_NEAR=J4501.3:1.5MM

C4516

PLACE_NEAR=J4501.8:1.5MM

10V 20110% X5R

0.01UF

C4510

PLACE_NEAR=J4501.7:1.5MM

20110V10% X5R

0.01UF

C4511

PLACE_NEAR=J4501.4:1.5MM

10V10% 201X5R

0.01UF

C4515

SYNC_DATE=04/08/2010

SATA CONNECTOR

SYNC_MASTER=K99_MLB

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
VOLTAGE=5V

PP3V3_S0_HDD_R

SATA_HDD_R2D_P

SMC_HDD_OOB_TEMP_CONN

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SMC_HDD_TEMP_CTL

SATA_HDD_R2D_N

SATA_HDD_D2R_C_N

SATA_HDD_D2R_C_P

SMC_HDD_TEMP_CTL_CONN

SMC_HDD_OOB_TEMP

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

TP_SSD_RSRVD

=PP3V3_S0_HDD

ISNS_HDD_P

ISNS_HDD_N

45 OF 110

3.3.0

051-8467

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

35 OF 74

4 3

2 1

18

21

19
20

10
11
12

13

16

15

14

17

9

1
2
3
4
5
6
7
8

1 2

1 2

2

1

1 2

1 2

1 2

1 2

7

68

7

39

7

68

7

68

7

68

7

39

OUT1

GND

TPAD

OUT2

OC1*

IN

EN1

EN2

OC2*

BI

BI

SYM_VER-1

IN
OUT

IN

OUT

VCC

GND

SELOE*

D+
D-

Y+
Y-

M+
M-

IOIONC

GND

VBUS

NC

IN

VBUS

D-

D+

GND

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Port Power Switch

USB/SMC Debug Mux

D4600.4
D4600.5

514-0740

(USB_EXTA_MUXED_P)
(USB_EXTA_MUXED_N)

SEL=0 Choose SMC
SEL=1 Choose USB

Right USB Port

MSOP

CRITICAL

U4690

TPS2052B

L4605

CRITICAL

0603

FERR-220-OHM-2.5A

PLACE_NEAR=J4600.1:3 mm

C4695

OMIT_TABLE

10UF

603

6.3V
X5R

20%

20%
CERM

10V
402

C4691

0.1UF

18 69

18 69

C4650

0.1UF

SMC_DEBUG:YES

10%

6.3V
X5R
201

R4650

10K

5%

201

1/20W
MF

L4600

DLP11S

90-OHM-100MA

CRITICAL

PLACE_NEAR=D4600.3:2 mm

PLACE_NEAR=D4600.2:2 mm

7

39 40 41

7

39 40 41

39

R4651

5%

SMC_DEBUG:NO

0

201

1/20W

MF

R4652

MF

1/20W

201

SMC_DEBUG:NO

0

5%

C4605

0.01uF

CERM

402

20%
16V

18

C4690

OMIT_TABLE

6.3V

20%
603

X5R

10UF

U4650

SMC_DEBUG:YES

TQFN

PI3USB102ZLE

CRITICAL

SIGNAL_MODEL=USB_MUX

6

1

D4600

RCLAMP0502N

PLACE_NEAR=J4600.2:2 mm

CRITICAL

SLP1210N6

PLACE_NEAR=J4600.3:2 mm

7

37 58

6.3V

POLY-TANT

20%

100UF

CASE-B2-SM

CRITICAL

C4696

J4600

CRITICAL

F-RT-TH

USB-RIGHT-K99

SYNC_MASTER=K99_MLB

External USB Connectors

SYNC_DATE=03/01/2010

=PP5V_S3_RTUSB

=USB_PWR_EN

USB_EXTA_OC_L

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_A_ILIM

USB_EXTA_MUXED_N

=PP3V42_G3H_SMCUSBMUX

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_A_F

VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

USB_LT1_P

USB_LT1_N

USB_EXTA_N

USB_EXTA_P

USB_EXTA_MUXED_P

USB_DEBUGPRT_EN_L

SMC_RX_L
SMC_TX_L

46 OF 110

3.3.0

051-8467

36 OF 74

7

1 9

6

8

2

3

4

5

21

2

1

2

1

2

1

1

2

4 3

1 2

1 2

1 2

2

1

2

1

93

10

8

7
6

1
2

5
4

2534

1

2

6

2
3
4

1

5

8

69 72

8

7

72

72

69 72

BI
BI

BI
BI

IN
IN

IN
IN

OUT

OUT

IN

IN

IN

IN

OUT

OUT
OUT
OUT
OUT
OUT

BI

BI

BI

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516S0862

(Right Speaker Enable)

10%

6.3V
X5R
201

0.1UF

PLACE_NEAR=J4700.34:1.5mm

C4720

10%

6.3V
X5R
201

0.1UF

PLACE_NEAR=J4700.23:1.5mm

C4710

0.1UF

201

X5R

6.3V

10%

PLACE_NEAR=J4700.26:1.5mm

C4700

F-ST-SM

AXK736327G

CRITICAL

J4700

7

18 69

7

18 69

7

18 69

7

18 69

7

19 69

7

19 69

7

19 69

7

19 69

7

19 69

7

18

7

36 58

7

42

7

42

7

19

7 9

39 40

7

17

7

19

7

49

7

49 72

7

49 72

7

42

7

42

7

39

7

39 40 47

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Left I/O (LIO) Connector

SMC_LID

=PP3V3_S0_AUDIO

HDA_SDIN0

USB_EXTD_OC_L
HDA_RST_L

USB_CAMERA_N
USB_CAMERA_P

HDA_SDOUT

USB_EXTD_P

USB_EXTD_N

SMC_BC_ACOK
=USB_PWR_EN

=I2C_LIO_SCL

SYS_ONEWIRE

=I2C_LIO_SDA

=I2C_MIKEY_SCL

AUD_GPIO_3

AUD_I2C_INT_L

SPKRAMP_INR_N
SPKRAMP_INR_P

=I2C_MIKEY_SDA

=PP3V42_G3H_ONEWIRE

=PP1V8R1V5_S0_AUDIO

HDA_SYNC

AUD_IP_PERIPHERAL_DET

AUD_IPHS_SWITCH_EN

HDA_BIT_CLK

47 OF 110

3.3.0

051-8467

37 OF 74

2

1

2

1

2

1

31

35

33

29

21
23
25
27

11
13
15
17
19

3

1

5
7
9

22
24

34

32

36

26
28
30

10
12
14
16
18
20

2

8

6

4

37

38

7 8 7 8

7 8

NC

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW
CARD_DETECT_GND

DAT6
DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

VSS

CLK
CMD

DAT0

SHLD_PIN

SHLD_PIN
SHLD_PIN

SHLD_PIN

DP

GPIO1

D4

D6

D5

PMOSO

VDD5V

DVDD

CLK

D7

D1

THRM_PAD

GND

EXTRSTZ*

X2

X1

AVDD

D3

D0

SD_CDZ

SD_WP

SD_CMD

PDMOD

DM

D2

RREF

NC NC

BI
BI

D

SG

D

SG

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PDMOD: POWER DOWN MODES
NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE

(IPU)

(IPD)

10K HIGH = REMOTE WAKE UP ENABLE

(IPD)

(IPU)

Max Current = 250 mA

516-0237

Keep this net short!

R4805 is for rail discharge. GL137 may cycle PMOS to

voltage must be less than 0.5V for at least 1ms per spec.

recover from card error. Off duration is 100ms and card

(IPU)

CRITICAL

0.22UH

0805-1

L4800

2

1

SD-CARD-K16

F-RT-TH

CRITICAL

J4800

GL137A

QFN

CRITICAL

U4800

CRITICAL

12.000MHZ-60PPM-16PF

2.50X2.00MM-SM

Y4800

6.3V

603

X5R

20%

10UF

C4800

BYPASS=U4800.15:16:5 mm

0.1UF

10%

201

X5R

6.3V

C4801

402

5%

MF-LF

1/16W

1M

NO STUFF

R4803

0.1UF

6.3V

201

X5R

10%

C4805

OMIT_TABLE

2.2UF

6.3V

20%

402-1

CERM

C4807

C4808

BYPASS=U4800.11:12:5 mm

0.1UF

10%

201

X5R

6.3V

0.1UF

BYPASS=U4800.26:27:5 mm

10%

201

X5R

6.3V

C4802 C4803

0.1UF

BYPASS=U4800.35:34:5 mm

10%

201

X5R

6.3V

0.1UF

BYPASS=U4800.6:5:5 mm

10%

201

X5R

6.3V

C4804

18 69

18 69

5%

25V

NP0-C0G

201

33PF

C4811

33PF

201

5%
25V
NP0-C0G

C4812

20%
X5R

603

10UF

6.3V

C4814

5%

201

1/20W
MF

47K

R4805

NO STUFF

0.1UF

10%
X5R

6.3V

201

C4813

R4806

MF

201

1%

715

1/20W

5%

10K

201

1/20W

MF

R4807

5%

10K

NO STUFF

201

1/20W

MF

R4809

5%

10K

201

1/20W

MF

R4812

10K

MF

201

1/20W

5%

NO STUFF

R4813

5%

0

201

1/20W

MF

R4804

NO STUFF

5%

10PF

201

NPO

25V

C4815

Q4800

SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

Q4800

19

25

SecureDigital Card Reader

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

SD_D<3>

GL137_PDMOD

SDCARD_PLT_RST

GL137_GPIO1

SDCARD_PLT_RST_L

USB_SDCARD_N
USB_SDCARD_P

SDCARD_RESET

SD_CD_L

SD_WP

SD_D<5>

SD_D<1>

SD_CMD

SD_CLK

PP3V3_SW_SD_PWR

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

SD_D<0>

SD_D<2>

SD_D<4>

SD_D<6>

SD_CLK_R

SD_D<7>

GL137_RESET_L

GL137_RREF

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

PP3V3_S3_CARDREADER_AVDD

=PP3V3_S3_CARDREADER

GL137_CLK12M_X1
GL137_CLK12M_X2

48 OF 110

3.3.0

051-8467

38 OF 74

20

19

18

17

3
6
5
2
7
8
9

1
10
11

13

12

16

14
15

4

5

28

16

19

18

21

141520

10

24

23

27

29

13

11

9

8

7

3

17

25

12

2
26
1

4

22

6

42

1 3

212

1

1 2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

2

1

1

2

1

2

1

2

1

2

1

2

1 2

2

1

3

4

5

6

1

2

7

70

7

7

7

70

7

70

7

70

7

70

7

7

70

7

70

7

70

7

70

70

7

70

8

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN
IN
IN
IN
IN
IN
IN
IN

IN

IN

OUT

IN

OUT

BI

IN

IN

OUT

BI
OUT

IN

OUT

OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN
IN

IN

IN

IN
IN

IN

IN

IN

IN

OUT

IN

IN

BI
BI
BI
BI
BI
BI

OUT
OUT

IN

IN

OUT

IN

IN

BI

BI

OUT

IN

OUT

OUT

NC

OUT

OUT

OUT

NC

NC
NC
NC

NC

NC

NC
NC

NC
NC
NC

NC

NC

NC

NC

NC
NC

NC
NC

NC

NC
NC

IN

OUT

OUT

P13
P14
P15
P16 P66

P10
P11
P12

P17

P20
P21
P22
P23
P24
P25
P26
P27

P30
P31
P32
P33
P34

P36
P37

P40
P41
P42
P43
P44
P45
P46
P47

P50
P51
P52

P60
P61
P62
P63
P64
P65

P67

P70
P71
P72
P73
P74
P75
P76
P77

P80
P81

P84
P85
P86

P90
P91
P92
P93
P94
P95
P96
P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0
PA1
PA2
PA3

PA6
PA7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

PE0
PE1
PE2
PE3
PE4
PF0

PF1
PF2
PF3
PF4
PF5
PF6
PF7

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

PH0
PH1
PH2
PH3
PH4
PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

IN

NC

IN

OUT

IN

BI

OUT

BI
BI
BI
BI

IN
IN
IN

OUT

BI

IN

IN
IN

BI

BI

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(OC)

(OC)

(EXCARD_PWR_EN)

(OC)

(OC)

(SMC_PECI_VSTP)

(SMC_PECI)
(SMC_PECI_VREF)

(OC)

(OC)
(OC)

(OC)

(OC)

(EXCARD_CP)

(EXCARD_OC_L)

H8S2117-R:

(OC)

(OC)

(OC)

(OC)

(OC)
(OC)

(OC)

those designated as inputs require pull-ups.

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

(DEBUG_SW_1)
(DEBUG_SW_2)

20%

22UF

603

6.3V

OMIT_TABLE

X5R-CERM-1

C4902

40 19

7

50 40 39

7

46 39

7

BYPASS=U4900.E1:D2:5 mm

4V

CERM-X5R-1

201

0.47UF

20%

C4907

10V

0.1UF

CERM

20%
402

C4903

10V
402

20%

BYPASS=U4900.M12:L9:5 mm

CERM

0.1UF

C4920

MF

1/20W

5%

4.7

PLACE_NEAR=C4920.1:2 mm

201

R4999

0.1UF

10V

20%
CERM

402

C4904

SM

XW4900

19

53

10V

0.1UF

CERM

20%
402

C4905

19

57

57 49 25

39

CERM

10V
402

0.1UF

20%

C4906

43

42

39

39

43

42

43

39

46 39

39 37

9 7

40 39 38 36

7

40 39 38 36

7

57

7

41

MF

5%

10K

1/20W

201

R4909

40

7

40

7

MF

1/20W

5%

10K

201

R4901

MF

1/20W

10K

5%

201

R4902

1/20W
MF

5%

0

NO STUFF

201

R4903

MF

1/20W

5%

10K

201

R4998

36

37

7

19

39

19

45

39

39

39

39

39

39

45

39

39

39

39

39

42 39

39

40 39

7

39

40 39

7

40 39

7

40 39

7

49 46 39

7

41

41

41

41

41

41

39

39

39

40 39 38 36

7

40 39 38 36

7

39

39

40 19

7

19

25

40

7

19

40 19

7

39

39

57 39 19

39

39

39

LGA-HF

H8S2117

OMIT_TABLE

U4900

LGA-HF

OMIT_TABLE

H8S2117

U4900

LGA-HF

H8S2117

OMIT_TABLE

U4900

39

57 19

7

35

7

35

7

39 34

7

39

68 40 19

7

68 40 19

7

68 40 19

7

68 40 19

7

68 40 19

7

25

68 25

39

41

57 39 19

7

19

68 25

41

41

39

SYNC_DATE=06/01/2010

SYNC_MASTER=K16_MLB

SMC

PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC

ALL_SYS_PWRGD

MEM_EVENT_L

SMC_TX_L

SMC_WAKE_SCI_L

SMC_PB4

SMC_GFX_OVERTEMP_L

SMB_0_S0_CLK

SMB_A_S3_CLK

PM_BATLOW_L

SMC_PA0

SMS_ONOFF_L

SMC_HDD_OOB_TEMP

SMC_TCK

RSMRST_PWRGD

PM_RSMRST_L
IMVP_VR_ON

SMC_PROCHOT_3_3_L

PM_PWRBTN_L

SMC_P20

SMC_P24

SMC_BMON_MUX_SEL

LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L

LPC_CLK33M_SMC
LPC_SERIRQ

SMB_MGMT_DATA

SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED

SMC_RX_L

SMC_PM_G2_EN

SMC_ADAPTER_EN

SMC_BIL_BUTTON_L
SMC_CPU_ISENSE

SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE

SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK

PM_CLKRUN_L

SMC_RESET_L

SMC_EXTAL

GND_SMC_AVSS

SMC_VCL

SMC_NMI

SMC_KBC_MDE

SMC_MD1

SMC_TRST_L

SMC_XTAL

MIN_NECK_WIDTH=0.10 MM

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM

SMC_PH3

SMC_THRMTRIP

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_DATA

SMB_BSA_CLK

SMC_MCP_SAFE_MODE

SMC_SYS_LED

SMC_ADC15

SMC_ADC14

SMC_NB_DDR_ISENSE

SMC_NB_CORE_ISENSE

SMC_ANALOG_ID

SMS_Z_AXIS

SMS_Y_AXIS

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SYS_ONEWIRE

PM_SYSRST_L

SMC_PA1

PM_SLP_S4_L

SMC_DP_HPD_L

SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_SLPS5_L

SMC_CASE_OPEN

USB_DEBUGPRT_EN_L

WIFI_EVENT_L

SMC_G3H_POWERON_L

SMC_TDI

PM_CLK32K_SUSCLK

SMC_TMS

SMC_LID

=SMC_SMS_INT
SMB_BSA_DATA

SMC_TDO

PM_SLP_S3_L

SMC_ONOFF_L
SMC_BC_ACOK
SMC_PME_S4_L

PM_SLP_S5_L

SMB_0_S0_DATA

SMC_HDD_TEMP_CTL

SMC_LRESET_L

LPC_AD<0>

SMC_P10

SMC_RSTGATE_L

LPC_PWRDWN_L

49 OF 110

3.3.0

051-8467

39 OF 74

2

1

2

1

2

1

2

1

1 2

2

1

12

2

1

2

1

121

2

1

2

1

2

1

2

B13
D11
C13
C12 J11

B12
A13
A12

D10

D13
E11
D12
F11
E13
E12
F13
E10

A9
D9
C8
B7
A8

D7
D6

D4
A5
B4
A1
C2
B2
C1
C3

G2
F3
E4

L13
K12
K11
J12
K13
J10

H12

N10
M11
L10
N11
N12
M13
N13
L12

A7
B6

A6
B5
C6

J4
G3
H2
G1
H4
G4
F4
F1

D8

D5

C7

L1

N2

N3
N1
M3
M2

K3
L2

B8
C9

B9
A10
C10
B10
C11
A11

G11
G13
F12
H13
G10
G12
H11
J13

M10

N9
K10

L8

M9

N8

K9

L7

K1
J3
K2
J1
K4
K5

N5
M6
L5
M5
N4
L4
M4

M8
N7
K8
K7
K6
N6
M7
L6

E2
F2
J2
A4
B3
C4

D3

F10

E3

C5

B11

L3

D2

E1

H10

M1

B1

E5

H1

D1

H3

L9

L11

M12

A2

A3

39

39

8

39

39

39

39

43

39

43 42 39

39

39

39

39

39

D

S G

IN

OUT

BI

IN

D

S G

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

IN
IN

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Unused Pins

SMC Aliases

TO CPU

TO SMC

SMC FSB to 3.3V Level Shifting

MR1* and MR2* must both be low to cause manual reset.

SMC Crystal Circuit

Mobiles: 3.42V

Desktops: 5V

SMC Reset "Button", Supervisor & AVREF Supply

(IPU)

(IPU)

Used on mobiles to support SMC reset via keyboard.

PLACEMENT_NOTEs:

NOTE: Internal pull-ups are to VIN, not V+.

SMC Pull-ups

Debug Power "Buttons"

System (Sleep) LED Circuit

SMC Pull-downs

Q5059

SOT563

SSM6N37FEAPE

R5070

10K

1/20W

MF 2015%

R5071

5%

100K

1/20W

MF 201

R5073

10K

MF 2015%

1/20W

R5074

MF5%

100K

1/20W

201

201

100K

5%

1/20W

MF

R5076

R5077

10K

1/20W

5% MF 201

10K

R5078

MF

1/20W

5% 201

10K

MF

1/20W

5%

R5079

201

10K

R5080

MF

1/20W

5% 201

201

R5085

10K

MF

1/20W

5%

1/20W

10K

201MF5%

R5086

R5088

10K

5%

1/20W

MF 201

DP_PWR:S0

R5090

5% 201

100K

1/20W

MF

39

10 14 66

R5062

5%

3.3K

201

1/20W

MF

10 14 66

39

Q5059

SOT563

SSM6N37FEAPE

R5091

100K

5%

1/20W

201MF

R5092

100K

5%

1/20W

201MF

R5089

NO STUFF

5%

10K

201MF

1/20W

10K

R5081

MF

1/20W

5% 201

R5010

5%

201

MF

1/20W

0

Y5010

5X3.2-SM

20.00MHZ

CRITICAL

C5011

5%

15PF

201

NPO

25V

C5010

5%

15PF

NPO

25V
201

MF

1/20W

5%

470K

R5087

201

5%

R5093

201

1/20W

MF

10K

39

39

39

39

39 19

39

39

39

39

39 43

39

39

39

39

R5096

1/20W

201

5%

0

MF

39 19

39

39

39

39

10K

R5094

5%

1/20W

MF 201

39

39

39

R5032

SIL

1.47K

1%
1/16W
MF-LF

402

R5031

SIL

523

1%
1/16W
MF-LF

402

R5030

SIL

40.2

1%
1/16W
MF-LF
402

Q5030

SIL

DMB54D0UV

SOT-563

50

Q5060

DMB53D0UV

SOT-563

R5061

201

MF

1/20W

5%

100K

Q5060

SOT-563

DMB53D0UV

R5060

201

MF

1/20W

5%

10K

39

19

U5010

VREF-3.3V-VDET-3.0V

DFN

7

47

7

39 40 47

R5000

5%

1K

1/20W
201

MF

C5026

10%
201

X5R

10V

0.01UF

C5025

6.3V

20%
603

X5R

10uF

OMIT_TABLE

C5001

201

10V

0.01UF

10%
X5R

7

39 41 51

C5020

0.47UF

6.3V

10%
402

CERM-X5R

39 40

39

R5015

Place R5015 on BOTTOM side

SILK_PART=PWR_BTN

OMIT

0

5%
1/10W
MF-LF
603

R5014

Place R5014 on TOP side

SILK_PART=PWR_BTN

OMIT

0

5%
1/10W
MF-LF

603

R5001

PLACEMENT_NOTE=Place R5001 on BOTTOM side

SILK_PART=SMC_RST

OMIT

5%

0

1/10W

603

MF-LF

39

39

39

39

R5040

5%

10K

1/20W

MF 201

39 40

R5020

DP_PWR:S0

MF

1/20W

201

0

5%

7

19 39 58

62

R5021

DP_PWR:SMC

MF

1/20W

201

0

5%

39

R5022

5%

0

201

1/20W

MF

DP_PWR:SMC

PLACE_NEAR=Q9441.2:5 mm

39 40 62

12

100K

5%

1/20W

MF 201

R5098

7

39 40 47

SMC Support

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(03/01/2010)

SMC_GFX_OVERTEMP_L

SMC_SLPS5_L

SMC_ADC15

SMS_X_AXIS

SMC_DP_HPD_L

PM_SLP_S3_L

DP_EXT_HPD_L

SMS_Y_AXIS
SMS_Z_AXIS
SMC_ADC14

SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
SMC_NB_MISC_ISENSE
SMC_ANALOG_ID
SMC_GPU_ISENSE
SMC_GPU_VSENSE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

=SMC_SMS_INT

MAKE_BASE=TRUE

SMC_G3H_POWERON_L

MCP_SPKR

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

MAKE_BASE=TRUE

SMC_HDD_ISENSE

MAKE_BASE=TRUE

SMC_CSREG_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_VSENSE

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

MAKE_BASE=TRUE

SMC_1V5S3_ISENSE

MAKE_BASE=TRUE

TP_SMC_ANALOG_ID

MAKE_BASE=TRUE

TP_SMC_GPU_ISENSE

MAKE_BASE=TRUE

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_L

MCP_WAKE_REQ_L

SMS_INT_L

MAKE_BASE=TRUE

SMC_MCP_SAFE_MODE

SMC_PH3

SMC_P24

SMC_P10
SMC_P20

SMC_RSTGATE_L

SMC_FAN_3_CTL

SMC_FAN_2_CTL

MAKE_BASE=TRUE

TP_SMC_PH3

MAKE_BASE=TRUE

TP_SMC_P24

TP_SMC_P20

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_SMC_P10

NO_TEST=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_FAN_3_TACH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_3_CTL

NO_TEST=TRUE

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

SMC_FAN_2_TACH

TP_SMC_FAN_1_TACH

MAKE_BASE=TRUE

SMC_FAN_1_TACH

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_SYS_KBDLED

SMS_ONOFF_L

TP_SMC_FAN_1_CTL

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_SMC_SYS_KBDLED

MAKE_BASE=TRUE

TP_SMS_ONOFF_L

SMC_THRMTRIP

SMC_PROCHOT

CPU_PROCHOT_BUF

CPU_PROCHOT_L_R

CPU_PROCHOT_L

PM_THRMTRIP_L

SMC_PROCHOT_3_3_L

=PP3V3_S0_SMC

SMC_EXTAL

SMC_TPAD_RST_L
SMC_ONOFF_L

=PP3V3_S5_SMC
=PPVIN_S5_SMCVREF

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

MIN_NECK_WIDTH=0.1 mm

SMC_ONOFF_L

PP3V3_S5_AVREF_SMC

MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

SMC_MANUAL_RST_L

SMC_RESET_L

SYS_LED_ANODE

SMC_SYS_LED

SYS_LED_ILIM

=PP5V_S3_SYSLED

SYS_LED_L_VDIV

SYS_LED_L

SMC_PA0

SMS_INT_L

=DP_PWR_EN

MAKE_BASE=TRUE

DP_PWR_EN

SMC_XTAL_R

SMC_XTAL

SMC_PA1

SMC_BC_ACOK

SMC_G3H_POWERON_L

SMC_DP_HPD_L

SMC_PB4

=PP3V3_S5_SMC

SMC_LID

SMC_BIL_BUTTON_L

SMC_CASE_OPEN

SMC_ADAPTER_EN

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

SMC_ONOFF_L

SMC_TX_L
SMC_RX_L

SMC_TMS
SMC_TDO
SMC_TDI

SMC_ODD_DETECT

SMC_TCK

PP3V3_WLAN_F

WIFI_EVENT_L

=PP3V3_SMC_PME

SMC_PME_S4_L

50 OF 110

3.3.0

051-8467

40 OF 74

3

4

5

1 2
1 2
1 2
1 2

1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2

1 2

1 2

6

1

2

1 2
1 2

1 2

1 2

1 2

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1

2

121

2

1 2 3

5 46

4

5

3

1

2

6

2

1

1

2

8

6

9

2

5

4

7

3

1

1

2

2

1

2

1

2

1

2

1

121

2

1

2

1 2

1 2

1 2

1 2

39

43

43

43

44

44

44

43

43

8

39

8

39 40

8

39 43 44

39

8

39

40

39

39

7 9

37 39

39 40

39 40

39

8

39 40

7

37 39 47

39

39

19 39 58

7

39 40 47

7

36 39 41

7

36 39 41

7

39 41

7

39 41

7

39 41

39

7

39 41

7

34

7

34 39

8

39 47

OUT

IN

E0/NC0

SCL

SDA

E2
E1

WC*

VCC

VSS

IN

BI

NC

BI

OUT

OUT

OUT

IN

IN

IN

OUT

IN

OUT

IN

IN

BI

BI
BI

OUT

BI

IN

OUT
OUT
OUT

OUT

OUT
OUT

OUT

IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

EFI Debug ROM

Write: 0xAC/0xAE
Read: 0xAD/0xAF

SPI Bus Series Termination

516S0573

LPC+SPI Connector

47

5%

LPCPLUS

201

1/20W
MF

R5126

48 69

47

5%

201

1/20W

MF

R5122

15

5%

201

1/20W

MF

R5112

19 69

47

LPCPLUS

5%

201

1/20W
MF

R5127

0

5%

LPCPLUS

201

1/20W
MF

R5128

M24M01-R

CRITICAL

SO8N

EFI_DEBUG

U5101

EFI_DEBUG

5%

0

1/20W

MF

201

R5101

NO STUFF

0

5%
1/20W
MF
201

R5104

NO STUFF

5%

0

1/20W

MF

201

R5102

EFI_DEBUG

0

5%
1/20W
MF
201

R5103

402

0.1UF

CERM

10V

20%

EFI_DEBUG

C5101

42

42

55909-0374

M-ST-SM

CRITICAL

LPCPLUS

J5100

7

19 39 69

7

39 40

7

39 40

7

39

7

25

7

36 39 40

7

39

48 69

5%

15

201

1/20W

MF

R5110

19 69

48 69

5%

15

201

1/20W

MF

R5111

19 69

7

25 69

7

19 39 69

7

19 39 69

7

19 39 69

7

19 48

7

19 39

7

19 39

7

39 40

7

39 40 51

7

39

7

39 40

7

36 39 40

7

19

7

19 39

7

19 39 69

48 69

5%

15

201

1/20W

MF

R5123

19 69

47

5%

201

1/20W

MF

R5120

47

5%

LPCPLUS

201

1/20W
MF

R5125

47

5%

201

1/20W

MF

R5121

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

LPC+SPI Debug Connector

SPI_CS0_R_L

SPI_MLB_MISO

=PP3V3_S0_DEBUGROM

DEBUGROM_E1

DEBUGROM_E2

SPI_MOSI

SPI_MISO

SPI_CLK_R

=I2C_DEBUGROM_SDA
=I2C_DEBUGROM_SCL

SPI_MOSI_R

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_CLK

SPI_MLB_CS_L

SPI_CS0_L

SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L

LPCPLUS_GPIO

SMC_RX_L

SMC_NMI

SMC_RESET_L

SMC_TCK

SMC_TDI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_ALT_CS_L

SPI_ALT_CLK

SPIROM_USE_MLB

LPC_AD<3>

LPC_AD<2>

LPC_CLK33M_LPCPLUS

=PP5V_S0_LPCPLUS

=PP3V3_S5_LPCPLUS

SPI_ALT_MISO

SPI_ALT_MOSI

LPC_AD<0>
LPC_AD<1>

LPC_FRAME_L

SMC_TMS

PM_CLKRUN_L

SMC_TDO

LPCPLUS_RESET_L

SMC_TRST_L
SMC_MD1
SMC_TX_L

51 OF 110

3.3.0

051-8467

41 OF 74

1

2

1 2

1 2

1

2

1

2

8

4

1

6

5

3
2

7

1

2

121

2

1

2

2

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

3

1

5

9

7

15

11
13

17
19
21
23
25
27
29

31

32

33

34

1 2

1 2

1 2

1 2

1

2

1 2

8

69

69

69

7

41 69

7

41 69

7

41 69

7

41 69

7

41 69

7

41 69

7 8

7 8

7

41 69

7

41 69

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

U1400

(MASTER)

Internal DP

(MASTER)

U4900

SMC "Management" SMBus Connections

(* = Multiple options)

Samsung LGD Samsung LGD AUO

Battery Manager - (Write: 0x16 Read: 0x17)

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *
Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

J9000

K16 K99

MCP89 SMBus 1 is slave port to

(Write: 0xE0 Read: 0xE1)

access internal thermal diodes.
Another slave port is available

at 0x10/0x11, probably not used.

U1400

MCP89

MCP89 SMBus "1" Connections

U4900

SMC

(MASTER)

Left I/O Board

ALS - N/A (Feature Removed)
Finstack Temp - (Write: 0x98 Read: 0x99)

U4900

SMC

(MASTER)

CPU Temp

EMC1413: U5515

J4700

(See Table)

Left I/O Board

Internal DP

(Write: 0x58 Read: 0x59)

Margin Control

(See Table)

J1300

Vref DACs

U3900

EFI Debug Serial

(Write: 0x30 Read: 0x31)

U3910

U5101
(Write: 0xAC/0xAE
Read: 0xAD/0xAF)

(Write: 0x72 Read: 0x73)

Mikey

J4700 (LIO Connector)

SMC

(MASTER)

SMC

Battery

Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)

(See Table)

J6950

(Write: 0x12 Read: 0x13)

ISL6259 - U7000

J5700

U4900

The bus formerly known as "Battery B"

Battery

(MASTER)

U4900

SMC

Trackpad

SMC "Battery A" SMBus Connections

Battery Charger

(Write: 0x90 Read: 0x91)

(MASTER)

(Write: 0x98 Read: 0x99)

MCP89 SMBus "0" Connections

SMC "0" SMBus Connections

U9701

LP8545 (Bklt)

MCP89

NOTE: SMC RMT bus remains powered and may be active in S3 state

EMC1413: U5535

XDP Connector

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

SMC "A" SMBus Connections

SMC "B" SMBus Connections

(Write: 0x98 Read: 0x99)

MCP Temp

(Write: 0xD8 Read: 0xD9)

201

MF

1/20W

2.61K

1%

R5280

201

MF

1/20W

2.61K

1%

R5281

5%

4.7K

MF

1/20W
201

R5261

MF

1/20W

201

5%

4.7K

R5260

MF

5%

1K

1/20W
201

R5271

201

MF

1/20W

5%

1K

R5270

201

2.0K

MF

5%
1/20W

NO STUFF

R5251

201

2.0K

MF

1/20W

5%

NO STUFF

R5250

201

MF

1/20W

NO STUFF

2.0K

5%

R5231

201

MF

1/20W

2.0K

5%

NO STUFF

R5230

MF

1/20W

201

1K

5%

R5200

MF

1/20W
201

5%

1K

R5201

201

MF

1/20W

0

5%

R5236

201

MF

1/20W

0

5%

R5235

MF

1/20W

5%

201

2.0K

R5291

2.0K

1/20W

201

5%
MF

R5290

DPI2C:SMC

MF

1/20W
201

5%

0

R5243

DPI2C:SMC

MF

1/20W

201

5%

0

R5242

201

5%
MF

1/20W

0

DPI2C:MCP

R5241

5%
MF

0

1/20W

201

DPI2C:MCP

R5240

K16/K99 SMus Connections

SYNC_MASTER=K99_MLB

SYNC_DATE=07/23/2010

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

=PP3V3_S5_SMBUS_SMC_MGMT

I2C_TCON_SDA

MAKE_BASE=TRUE

SMB_B_S0_DATA

SMB_B_S0_CLK =I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

SMB_A_S3_DATA

SMB_A_S3_CLK

=I2C_LIO_SDA

=I2C_LIO_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

SMBUS_MCP_1_CLK

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S3_SMBUS_SMC_A_S3

=I2C_BKL_1_SCL

=PP3V3_S0_SMBUS_MCP_0

=I2C_PCA9557D_SDA

I2C_TCON_SCL

MAKE_BASE=TRUE

=I2C_XDP_SDA

=I2C_XDP_SCL

=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA

=I2C_DEBUGROM_SDA

=I2C_DEBUGROM_SCL

=I2C_PCA9557D_SCL

=I2C_MIKEY_SDA

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

=I2C_TPAD_SCL

SMB_MGMT_CLK

=I2C_BKL_1_SDA

SMB_0_S0_DATA

SMB_0_S0_CLK

=I2C_TCON_SCL
=I2C_TCON_SDA

SMB_BSA_CLK

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

=SMBUS_BATT_SCL

=SMBUS_CHGR_SCL

SMB_MGMT_DATA

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

=PP3V42_G3H_SMBUS_SMC_BSA

=SMBUS_CHGR_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMB_BSA_DATA

=SMBUS_BATT_SDA

=I2C_TPAD_SDA

=PP3V3_S0_SMBUS_SMC_0_S0

=I2C_MCPTHMSNS_SDA

SMBUS_MCP_0_CLK

MAKE_BASE=TRUE

=I2C_MIKEY_SCL

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

=I2C_MCPTHMSNS_SCL

52 OF 110

3.3.0

051-8467

42 OF 74

121

2

121

2

121

2

121

2

121

2

121

2

121

2

121

2

121

2

2 1

2 1

70

70

8

71

38

38 44

44

38

38

37

7

37

7

70

68 19

68 19

8 8

8

62

8

33

71

13

13

33

33

40

40

33

37

7

70

46

7

38

62 38

38

59

7

59

7

38

70

7

49

50

38

70

8

50

70

7

38

49

46

7

8

44

68 19

37

7

70

68 19

70

70

44

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

OUT

OUT

OUT

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

EDP Current: 7 A
Max Vdiff: 13.0 mV

WF: Verify SO-DIMM current!

AirPort Current Sense / Filter

(For R and C)

MAX VOUT: 3.5V

SCALE: 0.4A / V

GAIN: 200X

(500V/V)

HDD Current Sense / Filter

MCP Voltage Sense / Filter

PBUS Voltage Sense Enable & Filter

WF: Verify Airport current!

EDP Current: 0.727 A?

Enables PBUS VSense
divider when high.

RTHEVENIN = 4573 Ohms

Place RC close to SMC

DIVIDER: 1/22

(CLIPS AT 2.2A)

(CLIPS AT 0.66A)

LCD Backlight Driver Input Current Sense / Filter

GAIN: 500X

SCALE: 0.2A / V
MAX VOUT: 3.33V

(500V/V)

PLACEMENT_NOTEs:

(500V/V)

EDP Current: 1.2 A?

Scale: 0.25A / V
MAX VOUT: 3V

MAX VOUT: 3.54V

SCALE: 0.667A / V

GAIN: 500X

PLACEMENT_NOTEs:

(For R and C)

CPU Voltage Sense / Filter

(200V/V)

PLACEMENT_NOTEs:

WF: Verify LCD backlight current!

Max Vdiff: ??? mV

EDP Current: ??? A

WF: Verify SSD current!

Max Vdiff: 14.6 mV

(For R and C)

(For R and C)

Place RC close to SMC

Place RC close to SMC

Gain: 200x

PLACEMENT_NOTEs:

Max Vdiff: 24.0 mV

DDR3 1V5R1V35 Current Sense / Filter

(CLIPS AT 0.825A)

(CLIPS AT 6.6A)

40

0.22UF

X5R

6.3V

20%

201

C5359

MF

201

1%

4.53K

1/20W

R5359

58

MF

1/20W

201

1%

100K

R5316

MF

1/20W

201

1%

100K

R5315

39

0.22UF

201

20%

6.3V
X5R

C5315

R5317

27.4K

1%

201

1/20W

MF

5.49K

1%

201

1/20W

MF

R5318

NTUD3169CZ

SOT-963

Q5315

40

40

40

40

4.53K

1%

Place close to SMC

1/20W

MF

201

R5365

20%

6.3V

0.22UF

Place close to SMC

X5R
201

C5365

0.1UF

10%
X5R

6.3V
201

C5360

INA210

U5360

SC70

Place close to SMC

0.22UF

X5R

20%

6.3V
201

C5375

Place close to SMC

6.3V

20%
X5R

201

0.22UF

C5385

SC70

INA210

U5370

SC70

INA211

U5380

Place close to SMC

0.22UF

X5R

20%

6.3V
201

C5395

SC70

INA211

U5390

6.3V
X5R

0.1UF

10%
201

C5370

0.1UF

C5380

201

6.3V

10%
X5R

10%

0.1UF

X5R

6.3V
201

C5390

4.53K

201

MF

1/20W

1%

Place close to SMC

R5375

4.53K

1%

Place close to SMC

1/20W

MF

201

R5385

201

MF

1/20W

1%

4.53K

R5395

53 72

53 72

34 72

34 72

35 72

35 72

63 72

63 72

SM

PLACE_NEAR=D9701.2:5 MM

XW5310

1%

1/20W

201

1M

MF

R5319

MF

1/20W

1%

201

47K

R5320

PLACE_NEAR=U4900:5 MM

1/20W

1%
MF

201

226K

R5321

OMIT_TABLE

PLACE_NEAR=U4900:5 MM

0402

20%

6.3V
X5R

2.2UF

C5310

39 40

SM

PLACE_NEAR=R7525.2:5 MM

XW5359

39

201

1/20W

1%
MF

4.53K

R5309

6.3V
201

20%
X5R

0.22UF

C5309

PLACE_NEAR=L7400.2:5 MM

SM

XW5309

SYNC_MASTER=K99_MLB

Voltage & Current Sensing

SYNC_DATE=04/08/2010

MCPVSENSE_IN

PBUS_G3H_VSENSE

PBUSVSENS_EN_L_DIV

=PBUSVSENS_EN

PBUSVSENS_EN_L

PPBUS_G3H

GND_SMC_AVSS

SMC_PBUS_VSENSE

LCDBKLT_VSEN

LCDBKLT_VSEN_DIV

SMC_ADC15

PPVOUT_SW_LCDBKLT

=PP3V3_S0_BKLTISNS

ISNS_LCDBKLT_N

=PP3V3_S0_HDDISNS

ISNS_P5VHDD_IOUT

ISNS_HDD_N

GND_SMC_AVSS

SMC_WLAN_ISENSE

GND_SMC_AVSS

ISNS_P5VWLAN_IOUT

=PP3V3_S3_WLANISNS

ISNS_1V5S3_IOUT

GND_SMC_AVSS

GND_SMC_AVSS

SMC_1V5S3_ISENSE

CPUVSENSE_IN

GND_SMC_AVSS

GND_SMC_AVSS

PPVCORE_S0_MCP

PPVCORE_S0_CPU

SMC_CPU_VSENSE

SMC_MCP_VSENSE

ISNS_1V5_S3_N

ISNS_1V5_S3_P

ISNS_AIRPORT_N

ISNS_AIRPORT_P

ISNS_LCDBKLT_P

SMC_HDD_ISENSE

ISNS_HDD_P

ISNS_LCDBKLT_IOUT

SMC_LCDBKLT_ISENSE

=PP3V3_S3_1V5S3ISNS

53 OF 110

3.3.0

051-8467

43 OF 74

2

1

1 2

1

2

1

2

2

1

1

2

1

2

6

2

1

3

5

4

1 2

2

1

2

1

2

3

14

5

6

2

1

2

1

2

3

14

5

6

2

3

14

5

6

2

1

2

3

14

5

6

2

1

2

1

2

1

1 2

1 2

1 2

1 2

1

2

1

2

1 2

2

1

1 2

1 2

2

1

1 2

7 8

50

39 40 43 44

7

60 63

8

8

39 40 43 44

39 40 43 44

8

39 40 43 44

39 40 43 44

39 40 43 44

39 40 43 44

7 8

7 8

8

V+

REFIN+

IN-

OUT

GND

OUT

OUT

IN

OUT

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

IN

IN

IN

OUT

IN

OUT

IN-

IN+ REF

V+

GND

IN

IN

OUT

IN

IN

OUT

IN-

IN+ REF

V+

GND

+IN

-IN

V+

V-

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VERIFY ALL RESISTOR AND GAINS

PLACEMENT_NOTEs:

GAIN: 200X

Scale: 2.778A / V

Gain: 36x

(CLIPS AT 3.3A)

GAIN: 100X

From charger

SCALE: 1A / V

(For R and C)

PLACEMENT_NOTEs:

Battery (BMON) Current Sense, MUX & Filter

ISL6259 Gain: 36x

Chipset Regulators High-Side Current Sense / Filter

INA213 Gain: 50x

For engineering, stuff BMON:ENG
For production, stuff BMON:PROD

CPU VCore Load Side Current Sense / Filter

(For Rs and C)

DCIN (AMON) Current Sense, RMUX & Filter

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R’s and C)

NOTE: Do not stuff R5415 and

(100V/V)

discharge) across R7050

MAX VOUT: 1.24V

ISL6259 Gain: 20x

Value: 20 mOhm

Sense R: R7020

MCP MEM VDD Current Sense / Filter

MAX VOUT: 2.38V

(Sense R "input")

Sense R is R7525, 1mOhm

Max VOut: 2.88V

(For R and C)

(For R and C)

R7593 at the same time!

Scale: 10A / V

Gain: 100x

Max Vdiff = 24.8mV

(Sense R "output")

(100V/V)

PLACEMENT_NOTEs:

Max Vdiff: 80mV

Value: 10 mOhm

Sense R: R7050

From charger

battery to PBUS (battery

NOTE: Monitoring current from

Battery side

Charger/Load side

MAX VOUT: 3.00V

SCALE: 2.5A / V

MCP VCore Current Sense Filter

MAX VOUT: 3.352V

R5431:

(200V/V)

201

0.1UF

6.3V

10%
X5R

C5417

SC70

INA210

U5402

40

20%

0.22UF

Place close to SMC

C5436

6.3V
402

X5R

39

6.3V

BMON:ENG

0.1UF

201

X5R

10%

C5418

51

PLACE_NEAR=U5413:2 mm

5%

BMON:PROD

201

1/20W

0

MF

R5431

1/20W

5%

BMON:ENG

100K

MF
201

R5423

10%

6.3V

BMON:ENG

0.1UF

X5R
201

C5459

39

54

R5480

NOSTUFF

Place close to SMC

402

MF-LF

1/16W

1%

17.4K

MF-LF

15.0K

1%

1/16W

402

Place close to SMC

R5471

39

10%

0.0068UF

CERM

25V

C5487

402

Place close to SMC

CRITICAL

NC7SB3157P6XG

SC70

U5413

BMON:ENG

39

51 71

51 71

CRITICAL

0612

0.002

1%
MF

1W

R5492

51

MF-LF

1%

NOSTUFF

R5482

Place close to SMC

402

1/16W

133K

40

MF

4.53K

1%

201

1/20W

Place close to SMC

R5416

6.3V
X5R

0.22UF

Place close to SMC

20%
201

C5472

55

5%

0

1/20W

MF

201

R5415

0.1UF

6.3V
X5R

10%

201

C5420

SC70

INA214

U5420

9

9

201

1/20W

5%

0

MF

R5411

40

Place close to SMC

402

6.3V

20%
X5R

0.22UF

C5435

201

X5R

6.3V

10%

0.1UF

C5400

201

1/20W

R5410

5%

0

MF

21

21

0.1UF

6.3V
X5R

C5434

10%

NOSTUFF

201

R5417

1/16W

1%

402

MF-LF

4.53K

Place close to SMC

Q5401

CRITICAL

2SA2154MFV-YAE

SOD

118

R5412

1/16W

1%

402

MF-LF

201

R5418

1%

4.53K

Place close to SMC

1/20W

MF

INA214

SC70

BMON:ENG

PLACEMENT_NOTE=Place near sense resistor

U5403

SC70-5

OPA330

U5400

C5470

402

0.068UF

10%
10V
CERM

201

R5481

150K

1%

1/20W

MF

300K

R5401

201

1%

1/20W

MF

402

C5490

0.0033UF

10%
50V
CERM

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

Current Sensing

GND_SMC_AVSS

CSREG_IOUT

BMON_INA_OUT

SMC_BMON_MUX_SEL

=PP3V42_G3H_BMON_ISNS

GND_SMC_AVSS

SMC_BATT_ISENSE

BMON_AMUX_OUT

CHGR_AMON

GND_SMC_AVSS

SMC_DCIN_ISENSE

MCPDDRFET_KELVIN

MCPDDR_SENSE_B

SMC_CPU_ISENSE

SMC_CSREG_ISENSE

ISNS_CSREG_N

=PP3V3_S0_CSREGISNS

GND_SMC_AVSS

IMVP6_PMON

MCPDDRFET_SENSE

=PP3V3_S0_MCPDDRISNS

MCPDDR_SENSE_C

CHGR_CSO_R_N

=PPBUS_G3H_R_OUT

ISNS_CSREG_P

SMC_MCP_DDR_ISENSE

GND_SMC_AVSS

MCPCORE_IOUT

=MCPCOREISNS_N

=MCPCOREISNS_P

GND_SMC_AVSS

SMC_MCP_CORE_ISENSE

CHGR_CSO_R_P

MCPDDR_SENSE_E

MCPDDR_SENSE_AMP

=PPBUS_G3H_R_IN

CHGR_BMON

=PP3V3_S0_MCPCOREISNS

MCPCORES0_IMON

54 OF 110

3.3.0

051-8467

44 OF 74

2

1

2

3

14

5

6

2

1

2

1

1 2

1

2

2

1

1

2

1 2

2

1

2

3

1

4

6

5

2

1 3

4

1

2

1 2

2

1

1 2

2

1

6

5

4 1

3

2

1

2

2

1

2

1

1

2

2

1

1 2

2

1

3

1

2

1 2

6

5

4 1

3

2

2

5

4

1

3

2

1

1 2

1 2

2

1

39 40 43 44

8

39 40 43 44

39 40 43 44

72

8

39 40 43 44

8

8

72

39 40 43 44

39 40 43 44

8

8

BI

BI

BI

BI

BI

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

BI

BI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Addr: 0x98(Wr)/0x99(Rd)

MCP Thermal Diode

FIXME: OFFGRID

Addr: 0x98(Wr)/0x99(Rd)

Local sensor for CPU Proximity

CPU Thermal Diode

CPU T-Diode Thermal Sensor

DRAM/SSD Temperature

Local sensor for MCP Proximity

MCP T-Diode Thermal Sensor

10%

0.1UF

201

X5R

6.3V

C5515

42

42

6.3V
X5R
201

PLACEMENT_NOTE=Place Q5501 near DRAMs below MCP

CRITICAL

SOT732-3

BC846BMXXH

Q5501

47

5%

201

1/20W

MF

R5515

5%

47

201

MF

1/20W

R5535

201

2.2NF

X5R

10V

10%

C5522

19 72

19 72

201

X5R

10V

2.2NF

10%

C5521

10 72

10 72

CRITICAL

DFN

PLACEMENT_NOTE=Place U5535 near MCP

U5535

EMC1413

PLACEMENT_NOTE=Place U5515 near CPU

CRITICAL

DFN

U5515

10K

5%

201

1/20W
MF

R5517

10K

1%

201

1/20W

MF

R5516

5%

10K

201

1/20W
MF

201

10%

2.2NF

10V
X5R

C5520

42

42

PLACEMENT_NOTE=Place Q5535 near J9000

CRITICAL

SOT732-3

BC846BMXXH

Q5535

2.2NF

10%
10V
X5R
201

C5523

Thermal Sensors

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MCP_THMDIODE_N

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_MCPTHMSNS_R

MLBR_THMDIODE_P

MLBR_THMDIODE_N

MCPTHMSNS_THERM_L

MCP_THMDIODE_P

=PP3V3_S0_MCPTHMSNS

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

CPUTHMSNS_ALERT_L

CPUTHMSNS_THERM_L

CPU_THERMD_P

CPU_THERMD_N

=PP3V3_S0_CPUTHMSNS

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

DRAMTHMSNS_D2_N

DRAMTHMSNS_D2_P

=I2C_MCPTHMSNS_SCL

MCPTHMSNS_ALERT_L

EMC1413

=I2C_MCPTHMSNS_SDA

R5537

10%

C5535

0.1UF
R5536

MF

1/20W

201

1%

15K

55 OF 110

3.3.0

051-8467

45 OF 74

2

1

2

1

1

2

3

1 2

1 2

2

1

2

1

11

5

4

1

9

10

6

3

2 7

8

121

2

1

2

1

2

2

1

1

2

3

2

1

72

72

8

8

72

D

GS

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

5V DC
TACH

MOTOR CONTROL
GND

518S0793

FAN CONNECTOR

NC

47K

201

MF

1/20W

5%

R5665

201

47K

1/20W

5%
MF

R5660

100K

MF

1/20W

5%

201

R5661

SOD-VESM-HF

SSM3K15FV

Q5660

FF14A-4C-R11DL-B-3H

F-RT-SM

CRITICAL

J5600

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

Fan

=PP3V3_S0_FAN

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

FAN_RT_PWM

=PP5V_S0_FAN

56 OF 110

3.3.0

051-8467

46 OF 74

1 2

1

2

1

2

1

2

3

2
3
4

1

5

6

8

39

39

7

7

8

BI
BI

OUT
IN

OUT

SYM_VER-1

BI

BI

BI

BI

BI

BI

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IPD Flex Connector

518S0794

PLACE_NEAR=J5700.10:1.5MM

C5710

0.1uF

20%

CERM

10V

402

0.1UF

X5R

6.3V

201

10%

PLACE_NEAR=J5700.13:1.5MM

C5720

7

42 47

FF14A-14C-R11DL-B-3H

J5700

F-RT-SM

CRITICAL

C5700

0.1UF

201

10%
X5R

6.3V

PLACE_NEAR=J5700.1:1.5MM

7

42 47

7

39 40 47

7

37 39 40 47

7

40 47

X7R-CERM

PLACE_NEAR=J5700.8:1.5MM

201

100PF

10%
25V

C5732

PLACE_NEAR=J5700.9:1.5mm

201

100PF

25V

X7R-CERM

10%

C5733

PLACE_NEAR=J5700.11:1.5MM

201

X7R-CERM

100PF

25V

10%

C5734

10%

PLACE_NEAR=J5700.12:1.5MM

201

X7R-CERM

25V

100PF

C5735

PLACE_NEAR=J5700.14:1.5MM

201

100PF

25V

X7R-CERM

10%

C5736

DLP0NS

90-OHM

L5710

18 69 72

18 69 72

7

47 72

7

47 72

0402-LF

PLACE_NEAR=J5700.10:1.5MM

L5720

FERR-120-OHM-1.5A

R5730

0

5%

MF-LF1/16W

402

IPD_3V3:S5

MF-LF

402

1/16W

0

R5731

5%

IPD_3V3:S3

7

47 72

7

47 72

39 40

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

WELLSPRING 1

=I2C_TPAD_SCL

USB_TPAD_CONN_P

SMC_LID

PP5V_S5_LDO

USB_TPAD_N

=I2C_TPAD_SDA

=PP3V3_S5_TPAD

=PP3V42_G3H_TPAD

USB_TPAD_P

USB_TPAD_CONN_N

=I2C_TPAD_SDA

SMC_LID

SMC_ONOFF_L

SMC_TPAD_RST_L

=I2C_TPAD_SCL

USB_TPAD_CONN_P

=PP3V3_S3_TPAD

SMC_TPAD_RST_L

PP5V_TPAD_FILT

VOLTAGE=5V

MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm

USB_TPAD_CONN_N

SMC_ONOFF_L

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

PP3V3_TPAD_CONN

VOLTAGE=3.3V

SMC_PME_S4_L

57 OF 110

3.3.0

051-8467

47 OF 74

2

1

2

1

14

13

12

11

16

10

15

1

4

3

2

5
6

9

8

7

2

1

2

1

2

1

2

1

2

1

2

1

4 3

1 2

21

57

8

7 8

7

42 47

7

37 39 40 47

7

39 40 47

7

40 47

7

42 47

7 8

OUT

IN

IN IN

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.

NOTE: 42 & 62 MHz use FAST_READ command.

31.2 MHz

25.0 MHz

41.7 MHz

62.5 MHz

MCP89 SPI Frequency Select

1

0

1

0

SPI_CLK

SPI_MOSI

1

1

0

0

Frequency

0.1UF

10%

201

X5R

6.3V

C6100

3.3K

5%

201

1/20W
MF

R6101

41 69

41 69

41 69 41 69

7

19 41

32MBIT

MX25L3205DM2I-12G

SOP

CRITICAL

OMIT_TABLE

U6100

5%

10K

SPI:41MHZ&SPI:62MHZ

201

1/20W
MF

R6151

5%

10K

SPI:25MHZ&SPI:31MHZ

201

1/20W
MF

R6153

10K

5%

SPI:25MHZ&SPI:41MHZ

201

1/20W

MF

R6152

10K

5%

SPI:31MHZ&SPI:62MHZ

201

1/20W

MF

R6150

SPI ROM

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

=PP3V3_S5_ROM

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_WP_L

SPI_MLB_MISO

SPI_MLB_CS_L

SPIROM_USE_MLB

61 OF 110

3.3.0

051-8467

48 OF 74

2

1

1

2

4 8

3

1

5

7

6

2

1

2

1

2

1

2

1

2

8

IN

IN

IN

IN-

IN+

OUT+
OUT-

GAIN

SHDN*

PVDD

NC

PGND

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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SHEET

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C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

6DB

SPEAKER AMPLIFIERS

SPEAKER LOWPASS
GAIN

80 HZ < FC < 132 HZ

APN:353S2888

X5R
201

10%

6.3V

CRITICAL

0.1UF

C6610

7

37 72

0.1UF

X5R

10%

6.3V
201

C6607

CRITICAL

C6601

47UF

POLY-TANT
2012-LLP

20%

6.3V

0

MF

201

5%

1/20W

R6610

7

37

7

37 72

U6610

WLP

MAX98300

100K

MF
201

5%
1/20W

NOSTUFF

R6612

6.3V

10%

201

X5R

0.1UF

CRITICAL

C6611

100K

MF
201

5%
1/20W

R6611

201

1/20W

NOSTUFF

5%

100K

MF

R6613

5%

0

1/16W
MF-LF

402

R6614

AUDI0: SPEAKER AMP

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

SPKRAMP_R_N_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

R_SPKRAMP_SHDN

PP5V_S3_U6610

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V

MAX98300_R_N

=PP5V_S3_AUDIO_AMP

SPKRAMP_INR_N

R_AMP_GAIN

SPKRAMP_INR_P

AUD_GPIO_3

MAX98300_R_P

66 OF 110

3.3.0

051-8467

49 OF 74

1 2

2

1

1

2

1 2

B3

A3

B1
C1

C3

C2

A1

B2

A2

1

2

1 2

1

2

1

2

1 2

7

50

7

50

72

8

72

NC

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

BI

IN

IN
IN

IN

IN

D

GS

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(For development only)

Debug LEDs

K16-Specific

518S0540

Battery Connector

Right Speaker Connector

518S0519

Vout = 1.25V * (1 + Ra / Rb)

(Switcher limit)

60MA MAX OUTPUT

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

<Ra>

<Rb>

MLB to LIO Power Cable Connector

518S0508

Vout = 3.425V

20%
50V

CERM

603

0.01UF

C6905

6.3V
X5R
603-1

10UF

CRITICAL
OMIT_TABLE

20%

C6999

0.22UF

10V

CERM

10%

402

C6994

201

MF

1/20W

1%

348K

R6995

5%
50V
CERM
201

22PF

C6995

201

MF

1/20W

1%

200K

R6996

10%
25V

X5R-CERM

603

2.2UF

C6990

1/8W

5%

805

MF-LF

10

R6905

CRITICAL

LT3470A

DFN

U6990

DP418C-SM

CRITICAL

33UH-20%-0.39A-0.435OHM

L6995

WTB-PWR-M82

M-RT-SM

CRITICAL

J6900

10%
10V
X5R
201

0.01UF

C6906

CRITICAL

SOT-323

BAT30CWFILM

D6905

CRITICAL

WTB-PWR-M82

M-RT-SM

J6950

0.1UF

402

X5R

25V

10%

C6950

1UF

402

X5R

16V

10%

C6951

10K

5%

1/20W

MF

201

R6950

42

42

RCLAMP2402B

NO STUFF

SC-75

CRITICAL

D6950

7

49

7

49

CRITICAL

78171-0002

M-RT-SM

J6903

2.0X1.25MM-SM

GREEN-3.6MCD

S3_S0_LED

D6910

5%

1K

S3_S0_LED

1/16W
MF-LF

402

R6940

S3_S0_LED

GREEN-3.6MCD

2.0X1.25MM-SM

D6920

R6941

S3_S0_LED

402

MF-LF

1/16W

5%

1K

SIL

GREEN-3.6MCD

2.0X1.25MM-SM

D6900

25 39 58

40

S3_S0_LED

SOD-VESM-HF

SSM3K15FV

Q6940

DC-In & Battery Connectors

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

SYS_LED_ANODE

ALL_SYS_PWRGD

=PP3V3_S3_DBGLEDS

DBGLED_S0_D

DBGLED_S0

SYS_DETECT_L

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

PPVBAT_G3H_CONN

SPKRAMP_R_N_OUT

SPKRAMP_R_P_OUT

PPBUS_G3H

PPDCIN_G3H_OR_PBUS

PPDCIN_G3H_OR_PBUS_R

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 mm

=PP5V_S3_LIO_CONN

=PP18V5_DCIN_CONN

P3V42G3H_FB

MIN_LINE_WIDTH=0.5 mm
SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

P3V42G3H_SW

DIDT=TRUE

P3V42G3H_BOOST

=PP3V42_G3H_REG

DBGLED_S3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

69 OF 110

3.3.0

051-8467

50 OF 74

2

1

2

1

2

1

1

2

2

1

1

2

2

1

1 2

4

3

6

2

8

5

7

1

9

21

1

6

5

4

3

2

2

1

3

1

2

1
2
3
4
5
6
7
8
9

2

1

2

1

1

2

3

2

1

4

2

1

3

K

A

1

2

K

A

1

2

K

A

1

2

3

8

7

7

51

7 8

43

51

7 8

7 8

8

OUT

OUT

IN
BI

OUT

AMON
BMON
ACOK

LGATE

PHASE

BOOT

SGATE
AGATE

CSIP
CSIN

DCIN

VNEG
CSOP
CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE
ICOMP
VCOMP

ACIN

SDA
VFRQ
CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

G

D

S

IN

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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SHEET

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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NOTICE OF PROPRIETARY PROPERTY:

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345678

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8 7 5 4 2 1

Inrush Limiter

through body diodes:

Reverse-Current Protection

* PBUS through Q7085,
Charger TOP FETs and

(CHGR_AGATE)

Q7055.

This node is powered

* DCIN through Q7080.

(AGND)

20V/V
36V/V

(OD)

(CHGR_DCIN)

(CHGR_SGATE)

30mA max load

(GND)

(CHGR_CSO_P)
(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

f = 400 kHz

Max Current = 8A

ACIN pin threshold is 3.2V, +/- 50mV
DIVIDER SETS ACIN THRESHOLD AT 12.18V
Input impedance of ~40K meets

sparkitecture requirements

FROM ADAPTER

TO SYSTEM

TO/FROM BATTERY

* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

Float CELL for 1S

10.5K

1%
1/20W
MF
201

R7011

0.1UF

201

X5R

6.3V

10%

C7042

470PF

201

X5R-X7R

16V

10%

C7016

1%

3.01K

1/20W

MF

201

R7016

470PF

201

X5R-X7R

16V

10%

C7015

220K

5%
1/20W
MF
201

R7015

1UF

402

X5R

10V

10%

C7002

1UF

402-1

X5R

10V

10%

C7000

402

5%

MF-LF

1/16W

4.7

R7001

30.1K

1%
1/20W
MF
201

R7010

PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm

SM

XW7000

1UF

402

X5R

10V

10%

C7001

0.1UF

402

X5R

25V

10%

C7021

0.1UF

402

X5R

25V

10%

C7022

402

0.047UF

X7R

16V

10%

C7020

PLACE_NEAR=U7000.25:2mm

0.22UF

402

CERM

10V

10%

C7025

CRITICAL

LFPAK-HF

RJK0305DPB

Q7035

201

5%
MF

10

1/20W

R7022

1/20W

201

5%
MF

10

R7021

33UF-0.06OHM

20%
25V

POLY-TANT

CASE-D3L

CRITICAL

C7030

CRITICAL

C7031

33UF-0.06OHM

POLY-TANT

CASE-D3L

20%
25V

CRITICAL

1206-1

7AMP-24V

F7040

R7086

332K

1%

1/20W

MF

201

62K

5%
1/20W
MF
201

R7081

0.22UF

603

X5R

25V

20%

C7005

44

44

42

42

0.01UF

201

X5R

10V

10%

C7011

0.47UF

402

X5R

10V

10%

C7050

1000PF

201

X7R

16V

10%

C7026

9

0612-3

MF

1W

0.5%

0.01

R7050

0.020

CRITICAL

0.5%
1W

0612

MF-LF

R7020

PLACE_NEAR=Q7030.5:1.5mm

0.001UF

402

X7R

50V

10%

C7037

10%
16V
X7R
201

1000PF

PLACE_NEAR=L7030.2:1.5mm

C7045

TQFN

ISL6259HRTZ

OMIT_TABLE

CRITICAL

U7000

201

MF

1/20W

5%

100K

NO STUFF

R7002

58

PWRPK-1212-8

SI7615DN

CRITICAL

Q7055

100

1%

1/20W

MF

201

R7013

CRITICAL

SOT-323

BAT30CWFILM

D7005

10%
25V
X5R
402

0.1UF

C7085

100K

5%

1/20W

MF

201

R7080

470K

1%
1/20W
MF
201

R7085

LFPAK-SM

CRITICAL

RJK0332DPB-01

Q7030

ELEC

11V

20%

62UF

CRITICAL

CASE-B2

C7041

20

1/20W

MF

5%

201

R7005

1UF

603-1

X5R

25V

10%

C7035

1UF

603-1

X5R

25V

10%

C7036

IHLP4040CZ-SM

CRITICAL

4.7UH-7.5A

L7030

201

5%
MF

1/20W

0

R7000

7

39 40 41

CRITICAL

SI5419DU

POWERPAK

Q7080

CRITICAL

SI5419DU

POWERPAK

Q7085

62UF

20%
11V

ELEC

CASE-B2

CRITICAL

C7043

11V

ELEC

CASE-B2

CRITICAL

20%

62UF

C7040

10%

1UF

603-1

X5R

25V

C7014

0.1UF

402

X5R

25V

10%

C7013

402

X7R

25V

10%

0.01UF

C7012

10UF

805

X5R

25V

10%

C7017

2.2

5%

1/20W

MF 201

R7051

0

5%

1/20W

MF 201

R7052

SYNC_DATE=(02/16/2010)

PBus Supply & Battery Charger

SYNC_MASTER=(K99_MLB)

CHGR_AGATE

PPDCIN_G3H_OR_PBUS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

CHGR_CSI_R_P

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

PPDCIN_G3H_CHGR

MIN_NECK_WIDTH=0.4 mm

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_AGATE_DIV

PPVBAT_G3H_CHGR_R

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=8.4V

PPVBAT_G3H_CONN

=PPBUS_G3H

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.4V

CHGR_CSI_R_N

SMC_RESET_L

CHGR_VCOMP_R

CHGR_CSO_R_P
CHGR_CSO_R_N

CHGR_VNEG_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

GND_CHGR_AGND

CHGR_RST_L
=SMBUS_CHGR_SCL

=PP3V42_G3H_CHGR

CHGR_CELL

CHGR_VFRQ

=SMBUS_CHGR_SDA

CHGR_ACIN

CHGR_VCOMP

CHGR_ICOMP

CHGR_UGATE

GATE_NODE=TRUE

DIDT=TRUE

CHGR_BGATE

PP5V1_CHGR_VDD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=5.1V

VOLTAGE=5.1V

PP5V1_CHGR_VDDP

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_CSO_N

CHGR_CSO_P

CHGR_VNEG

CHGR_CSI_N

CHGR_CSI_P

CHGR_SGATE

CHGR_BOOT

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_PHASE

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_LGATE

GATE_NODE=TRUE

DIDT=TRUE

=CHGR_ACOK

CHGR_BMON

CHGR_AMON

=PPDCIN_S5_CHGR

CHGR_SGATE_DIV

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_DCIN_D_R

CHGR_DCIN

70 OF 110

3.3.0

051-8467

51 OF 74

1

2

2

1

2

1

1

2

2

1

1

2

2

1

2

1

1 2

1

2

1 2

2

1

2

1

2

1

2

1

2

1

1 2 3

5

4

1 2

1 2

1

2

1

2

21

1

2

1

2

2

1

2

1

2

1

2

1

34

12

2134

2

1

2

1

9
15
14

21

23

25

26
1
28
27

2

8
18
17

29

22

20

19

16

24
5
7

3

10

4
6

12

11

13

1

2

1 2

5

3

4

1

2

3

1

2

2

1

1

2

1

2

5

1 2 3

4

1

2

1 2

2

1

2

1

21

1 2

4

5A

5

1

4

5A
5

1

1

2

1

2

2

1

2

1

2

1

2

1

1 2

1 2

50

71

7

50

8

71

44 71

44 71

8

58

71

71

71

71

8

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1
SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2
CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

GND/S2

VSW/S1/D2

GHS/G1

GLS/G2

VIN/D1

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

5.6A MAX OUTPUT

Vout = 5.0V

F=400KHZ

353S2678

5.3A MAX OUTPUT

Vout = 3.3V

F=400KHZ

1UF

10%
X5R

16V
402

C7200

CRITICAL

PCMC063T-SM

2.5UH-14A

L7260

1UF

X5R

10%
16V

402

C7241

402

0.1UF

10%
25V
X5R

C7264

OMIT

10UF

6.3V

603

20%

X5R

C7290

10%
25V
X5R
402

0.1UF

C7224

150UF

POLY-TANT

6.3V

20%

CRITICAL

CASE-B2-SM

C7252

X5R

10UF

805

20%
10V

C7250

402

16V

1UF

10%
X5R

C7281

PCMC063T-SM

2.5UH-14A

CRITICAL

L7220

OMIT_TABLE

10%

402

CERM

6.3V

1UF

C7203

OMIT_TABLE

6.3V

10UF

X5R

20%

603

C7205

1/20W
MF

1%

201

249K

R7206

58

SM

PLACE_NEAR=L7260.2:3mm

XW7261

10V

10%

402

CERM

0.22UF

C7201

1%

201

1/20W
MF

23.2K

R7260

1%

10K

201

1/20W
MF

R7261

1/20W

1%

41.2K

MF
201

R7220

1%

10K

201

MF

1/20W

R7221

11V

ELEC

CASE-B2

62UF

20%

CRITICAL

C7240

SM

PLACE_NEAR=U7201.28:1mm

XW7200

1%
1/20W
MF
201

3.16K

R7216

1/20W

MF

1%

1.87K

201

R7246

PLACE_NEAR=L7260.1:3mm

SM

XW7260

16V

10%
X5R

402

0.1UF

C7218

1/20W

MF

1%

1.87K

201

R7247

MF

1/20W

3.16K

1%

201

R7256

SM

PLACE_NEAR=L7220.1:3mm

XW7220

SM

PLACE_NEAR=L7220.2:3mm

XW7221

1%

6.04K

MF
201

1/20W

R7236

201

20K

1/20W
MF

1%

NO STUFF

R7237

SM

PLACE_NEAR=L7260.2:3mm

XW7262

SM

PLACE_NEAR=L7220.1:3mm

XW7222

CASE-B2-SM

TANT

6.3V

20%

150UF-0.018OHM-1.8A

CRITICAL

C7292

MF

1/20W

201

NO STUFF

1%

20K

R7239

10%

100PF

X7R-CERM

25V

201

C7239

1%

MF
201

6.04K

1/20W

R7238

X5R

10%

201

0.01UF

10V

C7238

58 58

5%0201MF1/20W

NO STUFF

R7248

0

201

1/20W
MF

5%

R7249

X7R

10%
16V

201

1000PF

PLACE_NEAR=L7260.2:1.5mm

C7272

16V

PLACE_NEAR=Q7260.2:1.5mm

X7R

10%

1000PF

201

C7283

PLACE_NEAR=Q7220.5.2:1.5mm

1000PF

201

10%
X7R

16V

C7270

10%
X7R

16V
201

1000PF

PLACE_NEAR=L7220.1.2:1.5mm

C7271

QFN

CRITICAL

TPS51980

U7201

ELEC

CRITICAL

CASE-B2

11V

20%

62UF

C7282

0

5%

MF-LF

402

1/16W

R7245

PLACE_NEAR=U7201.4:2mm

402

MF-LF

1/16W

0

5%

R7251

5%

0

1/16W
MF-LF
402

PLACE_NEAR=U7201.21:2mm

R7252

58

58

CRITICAL

SIZ700DT
POWERPAIR-6X3.7

Q7260

10%
X5R

10V

0.01UF

201

C7236

10%

100PF

X7R-CERM

25V
201

C7237

402

X5R

10%
16V

0.1UF

C7288

402

1/16W

5%

0

MF-LF

R7264

2

1

RJK03E0DNS

HWSON-8

CRITICAL

Q7225

HWSON-8

CRITICAL

RJK03E0DNS

Q7220

SYNC_MASTER=K99_MLB

5V / 3.3V Power Supply

SYNC_DATE=04/08/2010

P5VS3_VFB1

=PP5V_S3_REG

P5VS3_VFB1-R

DIDT=TRUE

SWITCH_NODE=TRUE

P5VS3_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

=PPVIN_S5_P5VP3V3

P3V3S5_CSN2

P3V3S5_COMP2

P5VS3_EN_R

P5VS3_COMP1

P5VS3_CSN1

P5VS3_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P5VS3_VBST_R

MIN_LINE_WIDTH=0.6 mm

P5VP3V3_VREF2P5VP3V3_VREF2

P5VS3_PGOOD

P5VS3_CSP1

P5VS3_VBST
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P5VP3V3_VREG3

P3V3S5_PGOOD

P3V3S5_VBST_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE

=PP5V_S3_REG

=PP3V3_S5_REG

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P3V3S5_LL

MIN_LINE_WIDTH=0.6 mm

P5VP3V3_VREF2

P3V3S5_VFB2_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P3V3S5_VBST

=P5V3V3_REG_EN

P3V3S5_RF

P5VS3_FUNC

P3V3S5_COMP2_R

=P3V3S5_EN

=P5VS3_EN

P5VS3_COMP1_R

P5VP3V3_VREG3

DIDT=TRUE

GATE_NODE=TRUE

P3V3S5_DRVH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

P3V3S5_CSP2_R

P5VS3_CSP1_R

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P5VS3_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P3V3S5_CSP2

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_DRVL

DIDT=TRUE

P5VP3V3_VREG5

P3V3S5_EN_R

P3V3S5_VFB2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

GND_P5VP3V3_SGND

051-8467

3.3.0

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10

22

9

16

14

11

7

1

2

1

2

1

2

1

2

4

5

8

1

6

7

3

2

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1

1 2

5

123

4

5

123

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52

8

52 52

52

8

52

8

58

52

52

57

MODE

VDDQSNS

COMP

NC0
NC1

VTTSNS

VTT

VTTREF

PGOOD

S3
S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN
IN
OUT

NC
NC

G

D

S

OUT

OUT

G

D

S

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Use LVDDR3:YES for fixed 1.35V operation or LVDDR3:NO for fixed 1.5V operation.

<Rb>

<Ra>

(GND_DDRREG_SGND)

(DDRREG_FB)

(DDRREG_VDDQSNS)

10mA max load
Vout = VDDQSNS/2

Vout = VTTREF

VTT Enable
VDDQ/VTTREF Enable
VDDQ PGOOD

(DDRREG_CSGND)

(DDRREG_DRVH)

Vout = 0.75V * (1 + Ra / Rb)

Vout = 1.501V / 1.352V
13A Max Output
f = 400 kHz

(DDRREG_VBST)

(DDRREG_LL)

(DDRREG_DRVL)

402

0.1UF

16V

10%
X5R

C7325

MF

1/20W

1%

15K

201

R7320

LVDDR3:YES

201

MF

1/20W

18.7K

1%

R7321

10%

1UF

16V
402

X5R

C7332

QFN

CRITICAL

TPS51116

U7300

4.7

1/16W
MF-LF

5%

402

R7305

6.3V
X5R-CERM-1
603

22UF

20%

OMIT_TABLE

C7361

6.3V

X5R-CERM-1

603

22UF

20%

OMIT_TABLE

C7360

SM

PLACE_NEAR=C7360.1:1 mm

XW7360

SM

PLACE_NEAR=Q7335.1:1 mm

XW7335

33000PF

201

X5R

10%

6.3V

C7350

57

4.7UF

10V
X5R

10%

805

C7300

57

201

1/20W

MF

1%

12K

R7310

IHLP2525CZ-SM

0.82UH-20%-13A-0.0067OHM

CRITICAL

L7330

SM

PLACE_NEAR=L7330.2:1 MM

XW7345

10UF

X5R

6.3V
603

20%

OMIT_TABLE

C7355

CASE-B2-SM

330UF

TANT

2.5V

CRITICAL

20%

C7341

CASE-B2-SM

CRITICAL

330UF

TANT

2.5V

20%

C7340

10UF

X5R

OMIT_TABLE

6.3V
603

20%

C7345

201

16V

1000PF

10%
X7R

PLACE_NEAR=Q7330.1:1.5mm

C7333

10%

402-1

X5R

10V

1UF

C7305

PLACE_NEAR=U7300.3:1 mm

PLACE_NEAR=U7300.25:1 mm

SM

XW7300

CRITICAL

PWRPK-12128

SIS426DN

Q7335

10%
X7R

16V
201

1000PF

LVDDR3:YES

C7320

100K

5%

201

MF

1/20W

R7380

71 42

71 42

CRITICAL

62UF

11V

ELEC

CASE-B2

20%

C7331

CASE-B2

62UF

11V

ELEC

CRITICAL

20%

C7330

PLACE_NEAR=R7350.1:1.5MM

16V

10%
X7R

201

1000PF

C7346

SIS426DN

PWRPK-12128

CRITICAL

Q7330

1%

1/4W

MF-LF

1206

CRITICAL

0.002

R7350

SYNC_DATE=06/01/2010

SYNC_MASTER=K16_MLB

1.5V/1.35V LVDDR3 Supply

LVDDR3:NO

R73211114S0331

RES,15K,1%,1/16W,MF-LF,0402

=PPVTT_S0_DDR_LDO

=PP3V3_S3_PDCISENS

DDRREG_PGOOD

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V

MIN_NECK_WIDTH=0.17 mm

GND_DDRREG_SGND

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVL

MIN_LINE_WIDTH=0.6 mm

=PPVTT_S3_DDR_BUF

ISNS_1V5_S3_N

=PPDDR_S3_REG

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_VDDQSNS

=PPVIN_S3_DDRREG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

GATE_NODE=TRUE

DDRREG_DRVH

MIN_LINE_WIDTH=0.6 mm

DDRREG_LL

SWITCH_NODE=TRUE
DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

VOLTAGE=5V

PP5V_S3_DDRREG_V5FILT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

=PP5V_S3_DDRREG

DDRREG_CSGND

MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm

DDRREG_CS

DDRREG_VBST

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VTTSNS

=DDRVTT_EN
=DDRREG_EN

ISNS_1V5_S3_P

PPDDR_S3_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V

=PPVIN_S0_DDRREG_LDO

DDRREG_FB

73 OF 110

3.3.0

051-8467

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3

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18

16

20

19

21

9

22

23

14

15

1 2

2

1

2

1

1 2

1 2

2

1

2

1

1

2

21

2

1

2

1

1

2

1

2 2

1

2

1

2

1

1 2

4

1 32

5

2

1

1

2

1

2

1

2

2

1

4

1 32

5

1

2 4

3

8

8

33

8

8

8

8

8

33

S

G

D

D

G

S

NC
NC

NC

OUT

NC

OUT

IN

NC

V5FILT

OSRSEL

ISLEW

VID6

DROOP

TRIPSEL

VR_TT*

THERM

GNDSNS

VREF

VID0
VID1
VID2
VID3
VID4
VID5

CSP
CSN

LL

VR_ON

GND

PGND

DPRSLPVR

DRVL

PGOOD

DRVH

VBST

PWRMON

DPRSTP*

CLK_EN*

VSNS

V5IN

TONSEL

IN
IN
IN
IN
IN
IN
IN

IN

IN

IN

IN

NC

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MIN_LINE_WIDTH MIN_NECK_WIDTH

28A @ 1V = 1.764V
Load Line = R7480 * 6 / (500U * R7414)

K = R7450 / (R7450 + R7451 + R7452)

Vpmon = 90 * K * R7480 * Vo * Io

OCP = 21.5mV / R7480 + 3.1A

(CPUIMVP_LL)

f = 300KHZ

MAX CURRENT = 28A

CRITICAL

0.36UH-30A-1.05MOHM

PCMC104T-SM

L7400

1UF

402

X5R

16V

10%

C7453

ELEC

CRITICAL

11V

20%

62UF

CASE-B2

C7458

CRITICAL

11V

CASE-B2

ELEC

62UF

20%

C7459

1UF

402

X5R

16V

10%

C7457

CRITICAL

S1

IRF6710

Q7400

DIRECTFET-MX

IRF6795

Q7451

CRITICAL

PLACE_NEAR=Q7400.1:1.5mm

1000PF

10%
16V
X7R
201

C7454

PLACE_NEAR=R7480.1:1.5MM

X7R

1000PF

10%
201

16V

C7455

0

MF

201

5%

1/20W

R7491

0

MF

201

5%

1/20W

R7492

X5R-X7R

16V

1UF

10%

603-2

C7414

5% 201

470

MF

1/20W

R7451

1/20W

5% 201

470

MF

R7452

25V
201

X7R-CERM

10%

100PF

C7451

1/16W

5%

402

MF-LF

0

R7415

25

44

39

201

25V

X7R-CERM

10%

100PF

C7452

X5R-CERM

10%

6.3V

4.7UF

603

C7412

2.2UF

CERM1

603

20%

6.3V

C7413

QFN

TPS51982RHB

CRITICAL

U7400

25V

5%

201

33PF

NP0-C0G

C7415

11 12 66

11 12 66

1%

2.1K

1/16W
MF-LF

402

R7414

1/20W

5%

201

MF

0

R7410

11 12 66

11 12 66

11 12 66

11 12 66

11 12 66

SM

XW7400

150K

MF

201

5%

1/20W

R7426

124K

MF
201

1%
1/20W

R7425

1/20W

5%

201

MF

10K

NO STUFF

R7421

11V

62UF

CRITICAL

20%

CASE-B2

ELEC

C7456

1/20W

5%

201

MF

2.0K

R7422

1/20W

201

1%
MF

499

R7453

14 66

10 14 66

201

10%

X7R-CERM

25V

NO STUFF

100PF

C7450

10V

10%

402

CERM

0.22UF

C7460

1%

402

1/16W
MF-LF

13.3K

R7450

NO STUFF

0

MF

5%

1/20W

201

R7411

62UF

20%
11V

ELEC

CASE-B2

CRITICAL

C7461

PMEG3010EB

SOD523

NO STUFF

D7415

11 66

11 66

0612

CRITICAL

0.00075

1%
1W
MF

R7480

SYNC_DATE=(02/16/2010)

IMVP6 CPU VCore Regulator

SYNC_MASTER=(K99_MLB)

IMVP6_ISLEW

0.20 MM0.25 MM

PP1V7_S0_IMVP6_VREF

0.20 MM0.25 MM

0.20 MM0.25 MM

IMVP6_THERM

0.25 MM 0.20 MM

IMVP6_DROOP

0.50 MM 0.20 MM

GND_IMVP6_SGND

PP5V_S0_IMVP6_V5FILT

0.20 MM0.25 MM

1.5 MM

0.20 MM

IMVP6_LL

0.25 MM 0.20 MM

IMVP6_VBST

0.20 MM

1.5 MM

IMVP6_DRVH

1.5 MM

0.20 MM

IMVP6_DRVL

1.5 MM

0.20 MM

IMVP6_VBST_RC

IMVP6_VSEN_N

IMVP6_CS_R_N

IMVP6_DROOP

IMVP6_PMON

=PP5V_S0_CPU_IMVP

IMVP6_ISLEW

PP1V7_S0_IMVP6_VREF

VOLTAGE=1.7V

IMVP6_TONSEL

CPU_VID<1>

IMVP_VR_ON

PM_DPRSLPVR

IMVP6_DRVL

DIDT=TRUE
GATE_NODE=TRUE

DIDT=TRUE

IMVP6_VBST

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<3>

CPU_VID<6>

CPU_VID<4>

CPU_VID<2>

CPU_VID<0>

CPU_VID<5>

PP5V_S0_IMVP6_V5FILT

VOLTAGE=5V

DIDT=TRUE

IMVP6_VBST_RC

IMVP6_VSEN_P

IMVP6_THERM

GND_IMVP6_SGND

VOLTAGE=0V

=PP3V3_S0_IMVP

=PPVIN_S5_CPU_IMVP

IMVP6_CS_N

IMVP6_CS_P

CPU_DPRSTP_L

IMVP6_DPRSLPVR

VR_PWRGOOD_DELAY

PPVCORE_S0_CPU_REG_R

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.2V

IMVP6_CS_R_P

=PPVCORE_S0_CPU_REG

DIDT=TRUE
SWITCH_NODE=TRUE

IMVP6_LL

IMVP6_DRVH

GATE_NODE=TRUE

DIDT=TRUE

74 OF 110

3.3.0

051-8467

54 OF 74

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71 2 6

2

1

2

1

1 2

1 2

2

1

1 2

1 2

2

1

1

2

2

1

2

1

2

1

31

29

30

10

32

27

8
7

5

1

16
15
14
13
12
11

4
3

19

25

2

33

23

20

22

17

18

26

9

24

6

21

28

2

1

1

2

1

2

1 2

1

2

1

2

1

2

1

2

1

2

1 2

2

1

2

1

1

2

1

2

1

2

1

2

43

21

54

54

54

54

54

54

54

54

54

54

54

66

72

54

8

54

54

54

54

54

54

66

54

54

8

8

72

72

72

8

54

54

IN

IN

IN

OUT

OUT

IN

IN

NC

IN
IN

NC

ISP

OCSET

ISN

ICOMP

LGATE

COMP

VDIFF

AF_EN

IMON

VID3

VID2

VDD

BOOT

FB

FDE

PGND

PGOOD PHASE

PVCC

RTN

THRM_PAD

VID0
VID1

VO

VSEN

VSS

VW

UGATE

VIN

RBIAS

SOFT

VR_ON

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(MCPCORES0_COMP)

1001 0.8125V

VID<3:0> VOLTAGE

1100 0.9750V

1111 0.9375V

0001 0.9125V

1011 0.7875V

1010 0.8000V

1000 0.8250V

0111 0.8375V

0110 0.8500V

0101 0.8625V

0000 0.9250V

1110 0.9500V

1101 0.9625V

0010 0.9000V
0011 0.8875V
0100 0.8750V

(MCPCORES0_UGATE)

OCP = R7569 * 10uA / (R7525 * (1 + R7575/R7573))

(MCPCORES0_PHASE)

(MCPCORES0_ICOMP)

(MCPCORES0_ISN)

K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27

(MCPCORES0_VW)

(MCPCORES0_VO)

MAX CURRENT: 15A

f = 300 kHz

(Q7560 Limit)

Vimon = 31 * Io * R7525 * (1 + R7575/R7573)

(MCPCORES0_VDIFF)

(MCPCORES0_FB)

(MCPCORES0_RTN)

(MCPCORES0_VSEN)

19

19

1/20W

1%

20

MF

201

R7568

R7566

20

1%
MF

1/20W

201

X7R

16V

1000PF

201

10%

C7570

MF

1/20W

1%

100

R7563

201

402

16V

10%

0.1UF

X5R

C7576

147K

1%

201

MF

1/20W

R7572

58

58

1/20W

201

1K

MF

5%

R7561

SM

PLACE_NEAR=U7500.33:1mm

XW7561

201

MF

1/20W

1%

22.1K

R7575

201

1/20W

1%
MF

10K

R7573

201

1/20W

MF

1%

9.76K

R7569

0

5%
1/10W
MF-LF
603

R7565

2

1

0.22UF

CERM-X7R

10V

5%

603

C7564

16V
402

X5R

1UF

10%

C7550

CRITICAL

603

1/10W

5%

2.2

R7560

MF-LF

X5R
402

16V

10%

1UF

C7562

1%
MF

1/20W

201

402

R7578

1%

1/20W

3.01K

201

MF

R7579

R7577

201

1%

1/20W

MF

150K

100PF

25V

X7R-CERM

201

10%

C7580

402

CERM

50V

10%

470PF

C7581

1%
MF

201

100

1/20W

R7571

0402

5%

CERM

2200PF

10V

C7582

0.001UF

X7R

50V

10%

402

C7579

1/20W

6.98K

1%
MF

201

R7576

10UF

4V
603

20%
X5R

C7566

CRITICAL

TANT
CASE-B4-SM

2V

270UF

20%

C7568

20%
2V
TANT
CASE-B4-SM

270UF

CRITICAL

C7565

20%
X5R

10UF

4V

603

C7567

402

16V

1UF

10%
X5R

C7561

PLACE_NEAR=Q7560.5:1.5mm

201

16V

1000PF

X7R

10%

C7563

R7500

MF-LF

1%

1/16W

402

100

C7573

201

NP0-C0G

25V

5%

47PF

201

NP0-C0G

25V

5%

47PF

C7575

0612

MF-1

CRITICAL

1W

1%

0.001

R7525

PCMC104T-SM

0.56UH-25A

CRITICAL

L7560

CRITICAL

CASE-B2

11V

ELEC

62UF

20%

C7540

44

CASE-B2

11V

ELEC

62UF

20%

CRITICAL

C7541

22 72

22 72

MF

R7593

5%

1/20W

201

NO STUFF

0

0

5% MF

1/20W

201

R7590

MF5%01/20W

201

R7591

C7578

1000PF

16V

10%
X7R

201

1000PF

X7R

16V

10%
201

C7577

MF

1/20W

5% 201

0

R7592

0

MF

1/20W

5% 201

R7594

19

19

CRITICAL

U7500

QFN

ISL9563B

201

16V

1000PF

X7R

10%

PLACE_NEAR=R7525.1:1.5MM

C7569

WPAK

RJK0365DPA-02

CRITICAL

Q7560

CRITICAL

RJK0208DPA

WPAK

Q7565

CASE-B2

11V

ELEC

62UF

20%

CRITICAL

C7543

CRITICAL

CASE-B2

11V

ELEC

62UF

20%

C7542

20%

270UF

2V

CASE-B4-SM

TANT

CRITICAL

C7571

20%

270UF

2V

CASE-B4-SM

TANT

CRITICAL

C7572

MCP VCore Regulator

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(02/11/2010)

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

MCPCORES0_BOOT

DIDT=TRUE

=PPMCPCORE_S0_REG

MCPCORES0_ISP_R

MIN_LINE_WIDTH=0.5 MM
GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MCPCORES0_UGATE

DIDT=TRUE

VOLTAGE=0V

GND_MCPCORES0_AGND

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm

MCPCORES0_ISP

MCPCORES0_ICOMP

PPMCPCORE_S0_R

VOLTAGE=1V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_IMON_R

MCP_VID0_REG

MCP_VID3_REG

MCPCORES0_IMON

MCP_VID<0>

MCP_VID<2>

=PPMCPCORE_S0_REG

MCPCORES0_VSEN_P

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

MCPCORES0_BOOT_R

DIDT=TRUE

=PP5V_S0_MCPREG

=PPVIN_S0_MCPCORE

MCPCORES0_OCSET

MCPCORES0_ISN

MCP_VID1_REG
MCP_VID2_REG

MCPCORES0_FDE

MCPCORES0_RTN

MCPCORES0_SOFT

MCPCORES0_COMP

MCPCORES0_RBIAS

MCPCORES0_PGOOD

MCPCORES0_VDIFF

MCPCORES0_VDIF_C

MCPCORES0_COMP_C

MCPCORES0_FB

MCPCORES0_VSEN_N

=MCPCORES0_EN

MCP_VID<1>

MCP_VID<3>

MCPCORES0_VSEN

MIN_NECK_WIDTH=0.2 MM

PP5V_S0_MCPREG_VDD

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

MCPCORES0_VW

MCPCORES0_VO

MCPCORES0_LGATE

GATE_NODE=TRUE
DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_PHASE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

75 OF 110

3.3.0

051-8467

55 OF 74

1 2

1 2

2

1

1

2

2

1

1

2

1

2

1 2

1

2

1

2

1 2

2

1

2

1

1 2

2

1

1 2

1 2

1 2

1 2

1 2

1

2

1 2

2

1

1

2

2

1

1

2

1

2

2

1

2

1

2

1

1 2

2

1

2

1

34

12

21

1

2

1

2

1 2

1 2
1 2

2

1

2

1

1 2
1 2

23

13

3

11

10

21

5

7

30

28

27

26

16

17

6

32

20

31 19

22

9

33

24
25

12

8

15

4

18

141

2

29

2

1

5

1 2 3

4

5

321

4

1

2

1

2

1

2

1

2

8

55

9

8

55

8

8

9

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

OUT

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OCP = R7641 x 8.5uA / R7640
Vout = 0.5V * (1 + Ra / Rb)

11.5A Max Output

Vout = 1.05V

f = 300 kHz

at desired location for
remote sensing.

(CPUVTTS0_VO)

<Ra>

<Rb>

Place XW7610, XW7611

(CPUVTTS0_OCSET)

58

R7640

CRITICAL

0.001

MF-1
0612

1W

1%

C7630

402

1UF

X5R

10%
16V

C7620

20%
11V

ELEC

62UF

CASE-B2

CRITICAL

C7621

CASE-B2

62UF

ELEC

11V

20%

CRITICAL

C7622

PLACE_NEAR=Q7630.1:1.5mm

X7R

10%

1000PF

16V
201

C7647

OMIT_TABLE

X5R

6.3V

10UF

603

20%

C7601

10UF

20%
X5R

10V
603

R7601

1/10W

5%

MF-LF

603

2.2

XW7600

SM

C7603

X7R

10%
16V

0.047UF

402

R7641

1.78K

1%

1/20W

MF

201

C7640

25V

5%

402

1000PF

NP0-C0G

R7642

201

MF

1/20W

1%

1.78K

1

2

R7644

201

MF

1/20W

1%

3.01K

R7645

2.74K

1%
1/20W
MF
201

U7600

ISL95870

UTQFN

CRITICAL

L7630

CRITICAL

0.82UH-20%-13A-0.0067OHM

IHLP2525CZ-SM

C7602

X5R
603

2.2UF

16V

10%

R7603

201

MF

1/20W

5%

0

58

C7605

201

16V

1000PF

10%
X7R

C7604

201

10%
X7R

16V

1000PF

R7604

3.01K

1%

1/20W

MF

201

R7605

201

2.74K

1/20W

MF

1%

C7648

CRITICAL

270UF

CASE-B4-SM

TANT

2V

20%

C7649

CRITICAL

270UF

CASE-B4-SM

TANT

2V

20%

C7623

1000PF

201

16V
X7R

10%

PLACE_NEAR=L7630.2:1.5mm

XW7611

SM

XW7610

SM

Q7630

CRITICAL

RJK03E0DNS

HWSON-8

Q7635

HWSON-8

RJK03E0DNS

CRITICAL

CPUVTT (1.05V) Power Supply

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(03/01/2010)

CPUVTTS0_CS_P

CPUVTTS0_OCSET

=PPCPUVTT_S0_REG

CPUVTTS0_LL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

PPCPUVTT_S0_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

CPUVTTS0_CS_N

CPUVTTS0_VO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm
DIDT=TRUE

CPUVTTS0_VBST

=PPVIN_S0_CPUVTTS0

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVTTS0_DRVH

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

CPUVTTS0_DRVL

=PPCPUVTT_S0_REG

CPU_VTTSENSE_P
CPU_VTTSENSE_N

CPUVTTS0_FB

CPUVTTS0_PGOOD

=PP5V_S0_CPUVTTS0

CPUVTTS0_RTN
CPUVTTS0_FSEL

=CPUVTTS0_EN

CPUVTTS0_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

CPUVTTS0_SREF

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S0_CPUVTTS0_VCC

76 OF 110

3.3.0

051-8467

56 OF 74

34

12

2

1

1

2

1

2 2

1

2

1

2

11

2

1 2

2

1

1

2

12

1

2

1

2

12

11

15

10

2

5

9

7

8

4

13

14

1

16

3

6

21

2

1

1

2

2

1

2

1

1

2

1

2

1

2

1

2

2

1

1 2

1 2

5

1 2 3

4

5

1 2 3

4

72

8

56

72

8

8

56

72

72

8

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

SS

IN0
IN1

THRML_PAD

EN FB

BIAS

OUT0
OUT1

GND

PG

OUT

OUT

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

OUT

GND

EN

OUT

IN

NC

NC

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

5.0V S5 IPD LDO

MCP 0.9V S5 (AUXC) Switcher

Vout = 5.0V

Vout = 0.8V * (1 + Ra / Rb)

Vout = 0.902V
MAX CURRENT = 1.5A

Vout = 0.8V * (1 + Ra / Rb)

MAX CURRENT = 0.016A

1.05V S0 MCP PLL LDO

Max Current = 0.5A

1.5V S0 Regulator

<Rb>

BOMOPTIONs:

MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER.
TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.

Vout = 1.508V

f = 1.6MHZ

f = 1.6MHZ

TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.

<Rb>

<Ra>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.05V

<Ra>

<Ra>

<Rb>

MAX CURRENT = 1.5A

MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.

PLACE_NEAR=U7750.1:1.5mm

CRITICAL

C7750

22UF

CERM

6.3V

805

20%

R7751

1/20W

2.55K

1%
MF

201

R7752

MF

1/20W

1%

20K

201

C7751

201

25V

NP0-C0G

47PF

5%

CRITICAL

L7750

2.2UH-3.25A

IHLP1616BZ-SM

58

U7750

DFN

CRITICAL

ISL8009B

201

C7743

10V
X5R

2.2NF

10%

MCPPLL_LDO

CRITICAL

U7740

TPS74701

SON

MCPPLL_LDO

R7747

201

MF

MCPPLL_LDO

4.42K

1%

1/20W

C7741

1UF

6.3V
402

CERM

10%

MCPPLL_LDO

MCPPLL_R:LDO

R7743

100

402

MF-LF

5%

1/16W

MCPPLL_LDO

C7740

1UF

402

CERM

6.3V

10%

R7746

201

MF

1/20W

MCPPLL_LDO

1%

1.37K

C7742

20%
4V
X5R
402

MCPPLL_LDO

4.7UF

1/16W

R7744

0

402

5%

MCPPLL_R:LDO

MF-LF

R7745

MCPPLL_R:REG

402

5%

MF-LF

1/16W

0

R7748

201

MF

1/20W

5%

0

MCPPLL_LDO

58

58

58

CRITICAL

ISL8009B

U7710

DFN

C7710

805

6.3V

CERM

20%

22UF

PLACE_NEAR=U7710.1:1.5mm

R7712

201

113K

1%
1/20W
MF

C7711

5%

47PF

201

25V

NP0-C0G

R7711

1%

100K

MF
201

1/20W

C7715

805

CERM

6.3V

20%

22UF

L7710

IHLP1616BZ-SM

CRITICAL

2.2UH-3.25A

58

R7750

402

1/16W

MCPPLL_R:LDO

5%

MF-LF

0

C7755

20%

22UF

CRITICAL

CERM

6.3V
805

PLACE_NEAR=U7710.1:1.5mm

X7R
201

C7712

16V

10%

1000PF

C7716

201

X7R

10%

1000PF

16V

PLACE_NEAR=L7710.2:1.5mm

PLACE_NEAR=U7750.1:1.5mm

1000PF

C7752

X7R

16V

10%
201

1000PF

C7756

16V

10%
X7R

PLACE_NEAR=L7750.2:1.5mm

201

SOT23-5

MIC5235-2.5V

OMIT_TABLE

U7760

IPD_5V:S5_EXT

C7761

X5R
402

16V

10%

1UF

402

X5R-CERM

C7760

IPD_5V:S5_EXT

2.2UF

20%
10V

58

IPD_5V:S3

R7760

1/16W

0

MF-LF

5%

402

5%

MF-LF

1/16W

0

R7761

PLACE_NEAR=J5700.10:1.5mm

IPD_5V:S5_INT

402

IPD_5V:S5_EXT

IC,LDO,MIC5235,5V,1%,150MA,SOT23-5

U7760

353S3034 1

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

Misc Power Supplies

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20mm

VOLTAGE=5V

PP5V_S5_LDO

P5VP3V3_VREG5

=PP3V3_S5_P0V9S5

P0V9S5_PGOOD

=PP3V3_S0_P1V5S0

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_S0_MCP_PLL_LDO_BIAS

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V5_S0_MCPPLLLDO

=PP5V_S3_TPAD

P5V_S5_EN

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_EN

=PP1V5_S0_MCP_PLL_VLDO

=PP1V5_S0_REG

=PP0V9_S5_REG

=P0V9S5_EN

P1V5S0_PGOOD

P1V5S0_FB

MCPPLLLDO_SS

=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_MCP_PLL_OR

MCPPLLLDO_PGOOD

MCPPLLLDO_PGOOD_R

MCPPLLLDO_FB

=PP3V3_S0_MCP_PLL_VLDO

MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

P1V5S0_SW

DIDT=TRUE

MIN_LINE_WIDTH=0.4 mm

P0V9S5_FB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

DIDT=TRUE

P0V9S5_SW

SWITCH_NODE=TRUE

=PPBUS_5V_S5

77 OF 110

3.3.0

051-8467

57 OF 74

2

1

1

2

1

2

2

1

21

1

8

6

5

2

3

4

7 9

2

1

7

1
2

11

5 8

4

9
10

6

3

1

2

2

1

1

2

2

1

1

221

1 2

1 2

1 2

1

8

6

5

2

3

4

7 9

2

1

1

2

2

1

1

2

2

1

21

1

2

2

1

2

1

2

1

2

1

2

1

2

3

51

4

2

1

2

1

1 2

1 2

47

8

58

8

7 8

8

8

8

8

8

8

8

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

D

SG

D

S G

D

SG

OUT

NC

IN

OUT

D

G S

OUT

VDD

OUT_A*

OUT_A

THRM

GND

IN_A

DLY_1C

IN_B

OUT_B

DLY

(OD,IPU)

(OD,IPU)

(OD,IPU)

(IPD)

1.3V

PAD

2:1

-

+

OUT

IN

OUT

IN

OUT

IN

THRM_PAD

GND

V3MON
V4MON

RST*

MR*

VDD

VDDA

V2MON

Q3

Q2

Q4

Q1

NC

NC

IN

OUT

OUT

IN

OUT

OUT

D

SG

IN

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Need to re-characterize for power sequencing!

S3 Rail Enables

ENET Rail Enables

Need to re-characterize for power sequencing!

S0 Rail Enables

VTT Rail Enable

VTT rail must ramp up in about
the same time as MEMVDD rail (Q2300).

PM_SLP_S3_LPM_SLP_S4_L

1 1

0

0

1

0

0

0

SMC_PM_G2_ENABLE

State

Run (S0)

1

0

1

1

Battery Off (G3Hot)

Soft-Off (S5)

Sleep (S3)

ISL6259 Frequency Select

Worst-Case Thresholds:
VDD: 2.9140V
V2MON: 3.000V

(IPU)

353S2718

Power Control Signals

Q3: 0.640V

Worst-Case Thresholds:
Q2: 0.XXXV

U7750 EN tied to VIN

V3MON: 0.610V
V4MON: 0.610V

S0 Rail PGOOD (BJT Version)

Q4: 0.660V

S0 Rail PGOOD Circuitry

S0 Rail PGOOD (ISL Version)

353S2809

Threshold: ??

DLY > 10 ms

Pull-up is with power FET.

S5 Rail Enables & PGOOD

Internal pull-ups 100K +/- 20%

3.3V w/Divider: 2.345V

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

NOTE: "AC" term valid only when Q7891 is stuffed

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

52

25 39 50

R7813

1/20W

0

201

5%
MF

C7813

NO STUFF

10V

0.068UF

10%
CERM

402

0

MF

201

1/20W

5%

R7812

NO STUFF

0.47UF

10V
X5R
402

10%

C7812

52

7

36 37

201

R7859

1/20W

MF

5%

100

59

5.1K

R7884

5%
1/20W

201

MF

0.47UF

10%

402

X5R

10V

C7884

59

57

7

19 39 40 58

19 39 40

19 34

SSM6N37FEAPE

SOT563

Q7890

SOT563

SSM6N37FEAPE

WLAN_PCTL:HW

Q7891

SSM6N37FEAPE

SOT563

Q7890

34

402

C7870

CERM

10V

20%

0.1uF

S0PGOOD_ISL

S0PGOOD_ISL

20.0K

R7871

1/16W

1%

MF-LF

402

R7870

10K

1/16W

402

1%

MF-LF

S0PGOOD_ISL

57

53

R7864

VFRQ:SLPS4

5%

0

201

MF

1/20W

MF

R7863

5%

0

201

VFRQ:SLPS3

1/20W

VFRQ:SLPS4&VFRQ:SLPS3

Q7860

SSM3K15FV

SOD-VESM-HF

R7861

MF

10K

201

1/20W

VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH

5%

R7860

5%

VFRQ:LOW

201

10K

1/20W
MF

51

SLG4AP012

TDFN

CRITICAL

U7840

220PF

25V
201

10%

C7841

X7R-CERM

6.3V
X5R
201

0.1UF

10%

C7840

39 57

52

10%

NO STUFF

C7801

33000PF

6.3V
X5R
201

7

39

52

19 21

S0PGOOD_ISL

U7870

TDFN

CRITICAL

ISL88042IRTJJZ

DFN2015H4-8

ASMCC0179

Q7820

S0PGOOD_BJT

CRITICAL

S0PGOOD_BJT

R7821

201

15K

1/20W
MF

1%

R7822

S0PGOOD_BJT

1%

MF

1/20W
201

7.15K

R7823

201

5%

1/20W

MF

1K

S0PGOOD_BJT

S0PGOOD_BJT

R7824

201

1K

1/20W

MF

5%

R7825

1/20W

S0PGOOD_BJT

201

MF

5%

1K

R7827

S0PGOOD_BJT

100

201

1/20W

MF

5%

R7828

S0PGOOD_BJT

201

1/20W

MF

5%

10

S0PGOOD_ISL

R7872

10

5%

1/20W

MF

201

R7826

201

MF

1/20W

1%

S0PGOOD_BJT

150K

19

59

59

52

59

R7840

201

0

5%
MF

1/20W

R7842

1/20W

MF

5%

201

0

R7841

1/20W

MF

5%

201

0

201

1/20W

MF

R7845

0

5%

R7843

0

201

5%
MF

1/20W

R7844

0

201

5%
MF

1/20W

57

SOT563

SSM6N37FEAPE

WLAN_PCTL:HW

Q7891

7

19 39 58

53

R7891

WLAN_PCTL:SW

5%
1/16W

0

402

MF-LF

1/20W

5.1K

MF

5%

201

R7811

NO STUFF

0.47UF

10%

C7846

10V
X5R
402

57

R7846

5%

0

MF-LF
402

1/16W

58

603

R7899

NO STUFF

MF-LF

1/10W

0

5%

402

C7810

0.47UF

10V
X5R

10%

58

43

R7810

100K

5%
MF

1/20W

201

R7882

201

15K

MF

1/20W

5%

201

MF

1/20W

5%

33K

R7881

22K

201

MF

R7880

5%
1/20W

C7882

10V
X5R
402

10%

0.47UF

402

10%
X5R

10V

0.47UF

C7881 C7880

10V
X5R

10%

402

0.47UF

56

7

19 39 40 58

R7879

201

1/20W

MF

5%

100K

55

R7820

10K

5%
MF

1/20W

201

55

56

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

Power Sequencing

S0PGOOD_BJT

S0PGOOD_BJT_L

VMON_3V3_DIV

PP1V5_S0

PP1V05_S0

DDRREG_EN

MAKE_BASE=TRUE

P0V9S5_PGOOD

CPUVTTS0_EN

MAKE_BASE=TRUE

=DDRREG_EN

=P3V3S3_EN

S5PGOOD_DLY

MAKE_BASE=TRUE

MCP_MEM_VDD_EN

PM_SLP_S3_R_L

MAKE_BASE=TRUE

=CPUVTTS0_EN

=P3V3S0_EN

MAKE_BASE=TRUE

P3V3S0_EN

=PBUSVSENS_EN

MCPCORES0_EN

MAKE_BASE=TRUE

PP3V3_S0

=DDRVTT_EN

P3V3S3_EN

MAKE_BASE=TRUE

=P5VS3_EN

PM_SLP_RMGT_L

MAKE_BASE=TRUE

=P3V3ENET_EN
=P0V9ENET_EN

=P1V5S0_EN

PM_SLP_S3_L

P1V5S0_EN

MAKE_BASE=TRUE

=PP3V42_G3H_CHGR

CHGR_VFRQ

CHGR_VFRQ_GATE

PM_SLP_S4_L

PP5V_S0

PP3V3_S0

=PP3V3_S5_VMON

VMON_Q4_BASE

VMON_EMITTER

=PP3V3_S0_PWRCTL

PP3V3_S0_VMON

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

VMON_Q3_BASE

PP1V5_S0
PP1V05_S0

S0PGOOD_RST_L

CPUVTTS0_PGOOD

MCPPLLLDO_PGOOD

MCPCORES0_PGOOD

P1V5S0_PGOOD

PM_SLP_S3_L

ALL_SYS_PWRGD

MAKE_BASE=TRUE

=MCPCORES0_EN

VMON_Q2_BASE

MAKE_BASE=TRUE

P5VS3_EN

=P0V9S5_EN

PP3V3_S5

PM_SLP_S4_L

=USB_PWR_EN

P3V3S5_PGOOD

P5VS3_PGOOD

MAKE_BASE=TRUE

P3V3S5_EN

P3V3S5_EN_L

AC_OR_S0_L

PM_WLAN_EN_L

AP_PWR_EN

SMC_ADAPTER_EN

PM_SLP_S3_L

SMC_PM_G2_EN

MAKE_BASE=TRUE

=P5V3V3_REG_EN

P5V_S5_EN

RSMRST_PWRGD

MAKE_BASE=TRUE

=P3V3S5_EN

=PP3V42_G3H_PWRCTL

=PP3V3_S5_P0V9S5

P3V3_BLEED

=PP3V3_S5_REG

P3V3S5_EN_L

=P5VS0_EN

78 OF 110

3.3.0

051-8467

58 OF 74

2 1

2

1

1 2

2

1

12

2

1

2

1

3

4

5

6

1

2

6

1

2

2

1

1

2

1

2

1 2

1 2

1

2

3

1

2

1

2

1

4

3

9

5

2

7

6

8

2

1

2

1

2

1

9

4

5
6 8

1

2

7

3

2

7

8

5

1

6

4

3

1

2

1

2

1 2

1 2

1 2

1

2

1 2

1 2

1

2

1 2

1 2

1 2

1 2

1 2

1 2

3

4

5

1

2

1 2

2

1

1

2

2

1

1

2

2

1

2

1

2

1

2

1

2

1

2

1

1

2

1

2

7 8

58 72

7 8

58

7 8

58 72

57

8

51

7

19 39 58

7 8

7 8

58 72

8

8

7 8

58 72

7 8

58

7

19 39 40 58

7 8

72

8

8

57

8

52

GND

VOUT

ON

VIN

D

S

G

D

SG

D

SG

IN

S

G

D

IN

IN

D

G S

D

G S

D

G S

IN

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Q7990

37 mOhm @2.5V

Type

ID(max)
Loading

Rds(on)

MOSFET

0.140 A (EDP)

3.25 A @85C

SI2312BDS
N-Channel

1.274 A (EDP)

P-Channel

MOSFET

Type
Rds(on)

5V S0 FET

P-Channel

MOSFET

Q7930

Q7910

Rds(on)

Q7940

U7980

18 mOhm Typ

TPS22924C
Load Switch

2 A

0.4 A (EDP)

50 mOhm Max

Loading

I(max)

R(on)

Type

Part

ID(max)

Type
Rds(on)

Loading

Type

TPCP8102

14 mOhm @4.5V

ID(max)

Loading

ID(max)

7.2 A @85C

3.3V S0 FET

0.100 A (EDP)

Part

P-Channel

FDC638P

65 mOhm @2.5V

65 mOhm @2.5V

2.0 A @85C

2.0 A @85C

FDC638P

Loading

3.294 A (EDP)

0.9V ENET FET

3.3V ENET Switch

3.3V S3 FET

FDC638P_G

SM

CRITICAL

Q7910

TPS22924

CRITICAL

CSP

U7980

OMIT_TABLE

10%

6.3V
CERM

402

1UF

C7980

X5R

10V

10%

0.01UF

201

C7991

CRITICAL

SI2312BDS

SOT23

Q7990

10%
X5R

6.3V

0.1UF

201

C7990

SSM6N37FEAPE

SOT563

Q7991

5%

100K

MF

1/20W

201

R7990

201

1/20W

MF

10K

1%

R7991

69.8K

1%
MF

1/20W

201

R7992

SSM6N37FEAPE

SOT563

Q7991

0.033UF

16V
X5R
402

10%

C7911

58

TPCP8102

23V1K-SM

CRITICAL

Q7930

CRITICAL

FDC638P_G

SM

Q7940

47K

201

MF

1/20W

5%

R7910

201

MF

1/20W

5%

10K

R7912

0.01UF

10%
X5R

201

10V

C7930

10%
16V
X5R
402

0.033UF

C7931

201

MF

1/20W

47K

5%

R7930

100K

201

MF

1/20W

5%

R7932

58

58

SSM3K15FV

SOD-VESM-HF

Q7903

SOD-VESM-HF

SSM3K15FV

Q7905

10%
16V

CERM

402

0.01UF

C7940

10%
16V
X5R
402

0.033UF

C7941

201

10V
X5R

10%

0.01UF

C7910

MF

1/20W

201

47K

5%

R7940

MF

1/20W

201

5%

47K

R7942

SOD-VESM-HF

SSM3K15FV

Q7945

58

58

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

Power FETs

P0V9ENET_SS

P0V9ENET_EN_L

P0V9ENET_EN_L_RC

=PP0V9_ENET_P0V9ENETFET

=P0V9ENET_EN

=PP3V3_S5_P0V9ENETFET

=PP0V9_ENET_FET

=PP3V3_S3_FET

P5VS0_EN_L

=P3V3S3_EN

=P3V3S0_EN

=P5VS0_EN

P3V3S3_EN_L

=PP3V3_S0_FET

=PP3V3_S5_P3V3S0FET

P3V3S0_EN_L

P5VS0_SS

=PP5V_S3_P5VS0FET

=PP5V_S0_FET

P3V3S3_SS

P3V3S0_SS

=PP3V3_ENET_FET

=P3V3ENET_EN

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S3FET

79 OF 110

3.3.0

051-8467

59 OF 74

5

6

2
1

4

3

C1

A1
B1

C2

B2

A2

2

1

2

1

2

1

3

2

1

6

1

2

1 2

1 2

1

2

3

4

5

2

1

7 85 6

4

31 2

5

6

2
1

4

3

1 2

1

2

1 2

2

1

1 2

1

2

1

2

3

1

2

3

1 2

2

1

1 2

1 2

1

2

1

2

3

8

8

8

8

8

8

8

8

9 8

8

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

NC

OUT

OUT
OUT
OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN

BI

BI

BI

IN

SYM_VER-2

SYM_VER-2

NC

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DisplayPort I/F

(DP_INT_AUX_CH_C_P)

4.7 kOhm to 3.3V

Pull-ups on panel side,

LCD Connector

Internal DP Connector: 518S0787

LED Backlight I/F

(DP_INT_AUX_CH_C_N)

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

12-OHM-100MA

TCM1210-4SM

CRITICAL

FL9001

C9023

DP_INT_ML_C_N<0>

100K

R9070

0402-LF

FERR-120-OHM-1.5A

R9060

DP_INT_AUX_CH_C_P

DP_INT_AUX_CH_C_N

DP_INT_ML_F_N<1>

DP_INT_HPD

DP_INT_ML_C_P<1>

DP_INT_ML_F_N<0>

DP_INT_ML_P<0>

=I2C_TCON_SCL

=I2C_TCON_SDA

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

DP_INT_ML_F_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<0>

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PP3V3_SW_LCD

DP_INT_HPD_CONN

LED_RETURN_4
LED_RETURN_3

LED_RETURN_5

=PP3V3_S0_LCD

DP_INT_AUX_CH_N

DP_INT_AUX_CH_P

DP_INT_ML_N<0>

DP_INT_ML_P<1>

DP_INT_ML_N<1>

LCD_IG_PWR_EN

LED_RETURN_2

DP_INT_ML_F_P<0>

LED_RETURN_1

LED_RETURN_6

PPVOUT_SW_LCDBKLT

SYNC_DATE=07/23/2010

SYNC_MASTER=K99_MLB

Internal DisplayPort Connector

L9004

12-OHM-100MA

7

41

7

41

9

71

9

71

9

17

9

71

9

71

9

71

9

71

7

62

7

62

7

62

7

62

7

62

7

62

9

MF
201

1/20W

5%

R9080

100K

5%
1/20W
MF
201

201

5%
MF

1/20W

0

R9050

100K

5%

1/20W

MF

201

J9000

F-RT-SM

CRITICAL

CABLINE-CA

10%
16V
X5R
402

0.1uF

C9022

0.1uF

402

X5R

16V

10%

C9021

0.1uF

402

X5R

16V

10%

C9020

10%
16V
X5R
402

0.1uF

C9025

10%
16V
X5R
402

0.1uF

C9024

0.1uF

402

X5R

16V

10%

10%
16V
X7R
201

C9017

5%

50V

C0G-CERM

603

1000PF

PLACEMENT_NOTE=PLACE CLOSE TO J9000

U9000

MFET-2X2

FPF1009

CRITICAL

C9009

0.1UF

201

X5R

6.3V

10%

R9014

1K

5%

1/20W

MF

201

C9011

10%

6.3V
X5R
201

0.1UF

C9012

10UF

603

X5R

6.3V

20%

OMIT_TABLE

1000PF

C9015

CRITICAL

FL9000

TCM1210-4SM

90 OF 110

3.3.0

051-8467

60 OF 74

2

1

2

1

1

2

2

1

6 7

1

2

3

4

5

2

1

2

1

1 2

1 2

1 2

1 2

1 2

1 2

31

35
36

33
34

1
2

5

4

3

6
7

10

9

8

20

19

17
18

16

14

13

12

11

21
22
23

30

29

28

27

26

25

24

15

32

37
38
39
40
41

1

2

1 2

1

2

1

2

4

32

1

4

32

1

21

7

71

7

71

7

71

71

71

7

71

7

71

71

71

7

7

8

7

71

7

42 62

IN

D

SG

D

S G

D

SG

D

S G

BI

BIBI

BI

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: Pulled up to 5V on DP connector page.

(DP_CA_DET_RC)

FET spec’ed for 1.5V Vgs operaiton.

201

6.3V

0.1UF

10%
X5R

C9300

0.1UF

10%
X5R

6.3V
201

C9301

9

SSM6N37FEAPE

SOT563

SIGNAL_MODEL=DP_AUXCH_FET

Q9302

SOT563

SSM6N37FEAPE

SIGNAL_MODEL=DP_AUXCH_FET

Q9302

CKPLUS_WAIVE=PdifPr_badTerm

SIGNAL_MODEL=DP_AUXCH_FET

SOT563

SSM6N37FEAPE

Q9300

SSM6N37FEAPE

SOT563

CKPLUS_WAIVE=PdifPr_badTerm

SIGNAL_MODEL=DP_AUXCH_FET

Q9300

9

9 9

9

X7R

10V

10%

3300PF

201

C9302

22

201

5%

1/20W

MF

R9302

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

External DisplayPort Support

DP_EXT_AUX_CH_P

DP_EXT_DDC_CLK

DP_AUX_CH_C_N

DP_CA_DET_RC

DP_EXT_DDC_DATA

DP_AUX_CH_C_P

DP_CA_DET

DP_EXT_AUX_CH_N

93 OF 110

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051-8467

61 OF 74

1 2

1 2

3

4

5

6

1

2

3

4

5

6

1

2

2

1

1 2

BI

IONCNC

IONCIO

IO

NC

GND

GND

DP_PWR

AUX_CHP

GND

RETURN

ML_LANE3P

GND

ML_LANE3N
GND

ML_LANE1P

ML_LANE2N

ML_LANE2P

ML_LANE1N

GND

CONFIG1

HOT_PLUG_DETECT

ML_LANE0P
ML_LANE0N

AUX_CHN

CONFIG2

SHIELD PINS

OUT

IN

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2

IN

IO
NC NC

IO

GND

OUT

IO
NC NC

IO

GND

IN

IN

IN

IN

IN

IN

G

D

S

G

D

S

OUT

G

D

S

G

D

S

BI

IN

IN

OC*

OUT

EN

GND

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

leakage of < 500 nA and gate to

NOTE: Q9440 must have Drain to Gate

Source resistance of > 5 MOhm.

DP to DVI/HDMI

(CA) has 100k
pull-up to DP_PWR.

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

Cable Adapter

Port Power Switch

71

9

0.01UF

10V
X5R
201

10%

C9400

X5R-CERM-1

22UF

603

OMIT_TABLE

6.3V

20%

C9480

SLP2510P8

CRITICAL

RCLAMP0524P

DP_ESD

D9410

3

20%

CASE-B2-SM

6.3V

100UF

CRITICAL

C9487

CRITICAL

MINIDSPLYPRT-K99

F-RT-TH

J9400

39

71

9

71

9

100K

201

1/20W

MF

5%

R9421

RCLAMP0524P

SLP2510P8

DP_ESD

D9411

3

10%

6.3V

0.1UF

X5R 201

C9415

10%

6.3V

0.1UF

201X5R

C9414

9

10%

6.3V

0.1UF

X5R 201

C9411

10%

6.3V

0.1UF

201X5R

C9410

MF

1/20W

201

100K

5%

DP_ESD

SC70-6-1

RCLAMP0504F

2 5

SLP2510P8

CRITICAL

DP_ESD

RCLAMP0524P

D9411

3

5%

1M

MF

1/20W
201

R9425

10%

6.3V

0.1UF

X5R 201

C9417

10%

6.3V

0.1UF

X5R 201

C9416

10%

6.3V

0.1UF

X5R 201

C9413

10%

6.3V

0.1UF

X5R 201

C9412

71

9

71

9

71

9

71

9

FERR-120-OHM-3A

0603

L9400

71

9

71

9

SOT-363

2N7002DW-X-G

Q9440

SOT-363

2N7002DW-X-G

Q9440

5%

100K

MF

1/20W

201

R9443

5%

201

100K

MF

1/20W

R9442

9

SOT-363

2N7002DW-X-G

Q9441

SOT-363

2N7002DW-X-G

Q9441

201

1/20W

MF

1M

5%

R9422

10K

201

MF

1/20W

5%

R9445

MF

1/20W

201

10K

5%

R9444

5%

100K

MF

1/20W

201

R9423

71

9

39

6.3V
X5R

10%

201

0.1UF

C9481

6.3V

20%

10UF

X5R
603

OMIT_TABLE

C9486

SOT23

CRITICAL

TPS2051B

U9480

6.3V
201

X5R

0.1UF

10%

C9485

DisplayPort Connector

SYNC_MASTER=K16_MLB

SYNC_DATE=06/01/2010

=PP3V3_S5_DP_PORT_PWR

=DP_PWR_EN

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50 MM

PP3V3_SW_DPPWR

HDMI_CEC

DP_EXT_HPD_L

PP3V3_SW_DPILIM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

PP3V3_SW_DPILIM

=PP3V3_S0_DPCONN

DP_EXT_AUX_CH_C_N

DP_EXT_ML_F_N<1>

DP_EXT_ML_F_P<1>

DP_EXT_ML_F_N<0>

DP_EXT_ML_F_P<0>

DP_EXT_ML_F_P<2>

DP_EXT_AUX_CH_C_P

=PP3V3_S0_DPCONN

TP_DPPWR_OC_L

DP_EXT_ML_F_P<3>
DP_EXT_ML_F_N<3>

DP_EXT_ML_F_N<2>

DP_CA_DET_Q

DP_EXT_ML_P<1>

DP_EXT_ML_N<1>

DP_EXT_HPD

DP_EXT_ML_P<3>

DP_EXT_ML_N<3>

DP_EXT_ML_N<0>

DP_EXT_ML_P<0>

DP_EXT_ML_N<2>

DP_EXT_ML_P<2>

DP_CA_DET_Q_L

=PP5VR3V3_S0_DPCADET

DP_EXT_CA_DET

D9400

CRITICAL

CRITICAL

DP_HPD_Q

DP_EXT_ML_C_P<0>

DP_EXT_ML_C_N<0>

TCM1210-4SM

FL9400

12-OHM-100MA

CRITICAL

DP_EXT_ML_C_P<1>

DP_EXT_ML_C_N<1>

FL9401

CRITICAL

12-OHM-100MA

DP_EXT_ML_C_P<2>

DP_EXT_ML_C_N<2>

TCM1210-4SM

FL9402

12-OHM-100MA

CRITICAL

TCM1210-4SM

R9420

12-OHM-100MA

CRITICAL

FL9403

TCM1210-4SM

DP_EXT_ML_C_P<3>

DP_EXT_ML_C_N<3>

POLY-TANT

94 OF 110

3.3.0

051-8467

62 OF 74

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1

2

1

1102 9 4 57 6

1

2

22

7

20

16

13

19

10

8

12
14

21

9

17

15

11

1

4

2

3
5

18

6

4

32

1

4

32

1

4

32

1

4

3 2

1

1

2

1
10

2
9

1 2

1 2

1 2

1 2

1

2

1

3

6

4

5
6

4
7

1

2

1 2

1 2

1 2

1 2

21

3

5

4

6

2

1

1

2

1

2

6

2

1

3

5

4

1

2

1

2

1

2

1

2

2

1

2

1

5

3

1

2

4

2

1

8

7

61

61

61

8

71

71

71

71

71

61

8

71

71

71

8

71

71

71

71

71

71

71

71

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

OUT1

FSET

GD

FILTER

ISET

PWM

EN

FAULT

THRM

GND_L

GND_SW

OUT6

VIN

VDDIO VLDO

FB

SW

OUT2

OUT4

OUT5

VSYNC

OUT3SCLK

SDA

GND_S

PAD

IN

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

I_LED=369/Riset

I_LED=20.3mA

see spec for others

NO STUFF R9740, C9740, C9741, R9754

(EEPROM should set EN_I_RES=1)

STUFF R9741

Addr: 0x58(Wr)/0x59(Rd)

FOR LP8543:

measurement on LED strings.

10.2 ohm resistors for current

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

Fpwm=9.62kHz

*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

MF

1/20W

5%

201

10K

R9755

201

5%
MF

10K

R9741

1210-1

10%

10UF

50V
X5R

C9799

1210-1

10%

10UF

X5R

50V

C9797

IHLP2525CZ-SM

22UH-2.5A

CRITICAL

L9701

CRITICAL

0612

MF

1W

0.01

0.5%

R9700

43 72

43 72

1/20W

201

MF

5%

0

R9757

CRITICAL

10%

PLACE_NEAR=L9701.1:3mm

25V
X5R
805

10UF

C9712

PLACE_NEAR=L9701.1:3mm

X5R
402

25V

10%

0.1UF

C9713

PLACE_NEAR=U9701.21:3mm

X7R-CERM
402

220PF

10%
50V

C9796

CRITICAL

SOD-123

RB160M-60G

D9701

0

BKLT:PROD

MF-LF

1/16W

5%

402

R9722

0

5%

BKLT:PROD

1/16W
MF-LF

402

R9721

402

MF-LF

1/16W

BKLT:PROD

0

5%

R9720

7

60

7

60

201

5%

1/20W

MF

0

R9753

7

60

7

60

7

60

7

60

R9718

5%

0

1/16W
MF-LF

402

BKLT:PROD

0

1/16W
MF-LF

BKLT:PROD

402

5%

R9719

5%

0

BKLT:PROD

1/16W
MF-LF

402

R9717

MF

R9715

100K

201

1/20W

1%

R9731

200K

201

1%

1/20W

MF

X5R
402

0.1UF

25V

10%

10%
25V

1UF

X5R

603-1

C9710C9711

0.1UF

6.3V
201

PLACE_NEAR=U9701.8:4mm

X5R

10%

SM

LP8545SQX

CRITICAL

LLP

OMIT_TABLE

U9701

0.01UF

PLACE_NEAR=U9701.22:3mm

0201

10V

10%

C9714

NO STUFF

201

MF

1/20W

5%

0

R9703

201

5%
MF

1/20W

0

R9702

9

33

201

MF

1/20W

5%

R9704

NP0-C0G
201

25V

33PF

5%

C9704

201

MF

1/20W

0

5%

R9701

42

42

1%
MF

201

R9716

PROJ:K16U9701

IC,LP8545,LED BKLT CTRLR,PRODUCTIO,LLP24

353S2896 CRITICAL1

IC,LP8545,LED BKLT CTRLR,LLP24,K99 VER

353S2967 PROJ:K991 CRITICALU9701

BKLT:ENG

R9720,R9721,R9722

103S0198 3

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

3 BKLT:ENG

R9717,R9718,R9719

103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

SYNC_DATE=(03/01/2010)

SYNC_MASTER=(K99_MLB)

LCD Backlight Driver

=PP3V3_S0_BKL_VDDIO

MIN_NECK_WIDTH=0.20 mm

BKL_ISEN1

MIN_LINE_WIDTH=0.5 mm

BKL_FSET
BKL_FLTR

PP5V_S0_BKL_VLDO

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

BKL_ISEN4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN5

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_SDA

LCD_BKLT_PWM

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm

=I2C_BKL_1_SCL

=I2C_BKL_1_SDA

PPBUS_SW_LCDBKLT_PWR

=PP5V_S0_BKL

PPBUS_SW_LCDBKLT_PWR

ISNS_LCDBKLT_N

BKL_VSYNC_R

BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_NECK_WIDTH=0.2 MM

PPVIN_SW_BKL_R

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 MM

PPBUS_SW_LCDBKLT_PWR_SW

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM
VOLTAGE=24V

SWITCH_NODE=TRUE
DIDT=TRUE

PPVOUT_SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=24V

BKL_ISEN2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

ISNS_LCDBKLT_P

BKL_EN

BKL_PWM

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.5mm

PPBUS_SW_BKL

VOLTAGE=12.6V

PLACE_NEAR=U9701.22:5mm

X7R

XW9710

BKL_ISET
BKL_SCL

1/20W

C9723

90.9K

1/20W

R9714

201

MF

1/20W

1%

18.2K

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

GND_BKL_SGND

VOLTAGE=0V

NO STUFF

TP_BKL_FAULT

97 OF 110

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051-8467

63 OF 74

1

2

1 2

2

1

2

1

21

34

12

1 2

212

1

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1 2

2

1

2

1

2

1

1 2

12

5

6

20

3

2

4

7

25

15

1

18

23

8

22

21

24

13

16

17

19

1410

11

9

2

1

1

2

1

2

1 2

2

1

1

2

1 2

1

2

8

63 64

8

63 64

7

43 60

IN

D

SG

D

SG

IN

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CHANNEL

.

0.4 A (EDP)

43 mOhm @4.5V

MOSFET

RDS(ON)
LOADING

PPBUS S0 LCDBkLT FET

FDC638APZ
P-TYPE

R9808

201

MF

1/20W

1%

301K

147K

201

1%
MF

1/20W

R9809

C9802

0.1UF

10%
16V
X5R
402

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

Q9806

25

SSM6N37FEAPE

SOT563

Q9807

SSM6N37FEAPE

SOT563

Q9807

10K

201

1/20W

5%
MF

R9810

CRITICAL

2AMP-32V

F9800

0603

9

LCD Backlight Support

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

=PPBUS_S0_LCDBKLT

LCDBKLT_EN_DIV

LCDBKLT_DISABLE

BKLT_PLT_RST_L

LCD_BKLT_EN

VOLTAGE=8.4V

PPBUS_SW_LCDBKLT_PWR

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

LCDBKLT_EN_L

VOLTAGE=8.4V

MIN_NECK_WIDTH=0.25 mm

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm

98 OF 110

3.3.0

051-8467

64 OF 74

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2

1

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2

1

3

1 2 5 6

4

6

1

2

3

4

5

1

2

21

8

63

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU

PLACE ON OPPOSITE SIDE OF CPU

PLACE ON OPPOSITE SIDE OF CPU

LAYOUT NOTE:

LAYOUT NOTE:

ADDITIONAL CPU VCORE HF DECOUPLING

40x 1uF 0402

C9909

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9908

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9907

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9906

OMIT_TABLE

402-LF

CRITICAL

6.3V

2.2UF

20%
CERM

C9905

OMIT_TABLE

2.2UF

6.3V

20%
402-LF

CERM

CRITICAL

C9904

2.2UF

OMIT_TABLE

6.3V

20%
402-LF

CERM

CRITICAL

C9903

CRITICAL

2.2UF

OMIT_TABLE

6.3V

20%
402-LF

CERM

C9902

OMIT_TABLE

CRITICAL

2.2UF

6.3V

20%
402-LF

CERM

C9901

OMIT_TABLE

2.2UF

CRITICAL

6.3V

20%
402-LF

CERM

C9900

OMIT_TABLE

2.2UF

6.3V

20%
402-LF

CERM

CRITICAL

C9919

OMIT_TABLE

2.2UF

6.3V

20%
402-LF

CERM

CRITICAL

C9918

OMIT_TABLE

CRITICAL

CERM

6.3V

2.2UF

20%
402-LF

C9917

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9916

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9915

402-LF

OMIT_TABLE

6.3V

2.2UF

20%
CERM

CRITICAL

C9914

CRITICAL

2.2UF

OMIT_TABLE

6.3V

20%
402-LF

CERM

C9913

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9912

OMIT_TABLE

CERM

CRITICAL

6.3V

2.2UF

20%
402-LF

C9911

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9910

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9929

OMIT_TABLE

CRITICAL

6.3V

2.2UF

20%
402-LF

CERM

C9928

2.2UF

402-LF

OMIT_TABLE

6.3V

20%
CERM

CRITICAL

C9927

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9926

OMIT_TABLE

2.2UF

6.3V

20%
402-LF

CERM

CRITICAL

C9925

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9924

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9923

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9922

OMIT_TABLE

2.2UF

6.3V

20%
402-LF

CERM

CRITICAL

C9921

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9920

OMIT_TABLE

CERM
402-LF

6.3V

2.2UF

20%

CRITICAL

C9939

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9938

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9937

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9936

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9935

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9934

OMIT_TABLE

CRITICAL

6.3V

2.2UF

20%
402-LF

CERM

C9933

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9932

OMIT_TABLE

CRITICAL

6.3V

2.2UF

20%
402-LF

CERM

C9931

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

C9930

OMIT_TABLE

6.3V

2.2UF

20%
402-LF

CERM

CRITICAL

SYNC_DATE=05/18/2010

SYNC_MASTER=K99_MLB

Additional CPU/GPU Decoupling

=PPVCORE_S0_CPU

99 OF 110

3.3.0

051-8467

65 OF 74

8

11 12

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

(CPU_VCCSENSE)
(CPU_VCCSENSE)

(FSB_CPURST_L)

(See above)

FSB 1X signals shown in signal table on right.

FSB 1X Signals

FSB 2X

Signals

NET_TYPE

SPACING

FSB 4X Signal Groups

PHYSICAL

FSB (Front-Side Bus) Constraints

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

CPU Signal Constraints

FSB Clock Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

FSB 2X signals / groups shown in signal table on right.

CPU / FSB Net Properties

ELECTRICAL_CONSTRAINT_SET

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1

Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.

SR DG recommends at least 25 mils, >50 mils preferred

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Intel Design Guide recommends FSB signals be routed only on internal layers.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps.

FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.

=4x_DIELECTRIC

FSB_DATA

?

TOP,BOTTOM

=STANDARD=STANDARD*

FSB_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

FSB_DSTB_55S

=55_OHM_SE

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=4x_DIELECTRICCLK_FSB

?

TOP,BOTTOM

8 MIL

CPU_8MIL

?

*

?

CPU_COMP

*

25 MIL

CPU_AGTL

?

*

=STANDARD

25 MIL

CPU_GTLREF

*

?

=3x_DIELECTRIC

?

CLK_FSB

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB_100D

8 MIL

*

?

MCP_FSB_COMP

CPU_ITP

*

?

=2:1_SPACING

MCP_50S

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

* =STANDARD=STANDARD

?

FSB_ADDR

*

=STANDARD

=2x_DIELECTRIC

*

FSB_DATA

?

*

FSB_DSTB

?

=3x_DIELECTRIC =5x_DIELECTRIC

?

FSB_DSTB

TOP,BOTTOM

=3x_DIELECTRIC

?

FSB_ADDR

TOP,BOTTOM

=3x_DIELECTRIC

?

TOP,BOTTOM

FSB_1X

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

CPU/FSB Constraints

25 MIL

?

CPU_VCCSENSE

*

CPU_AGTL

?

=2x_DIELECTRIC

TOP,BOTTOM

=27P4_OHM_SE

=27P4_OHM_SE

*

=27P4_OHM_SE =27P4_OHM_SE

7 MIL7 MIL

CPU_27P4S

* =STANDARD =STANDARD

CPU_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

FSB_1X

=STANDARD

?

TOP,BOTTOM

?

FSB_ADSTB

=4x_DIELECTRIC

FSB_ADSTB

?

*

=2x_DIELECTRIC

CPU_55S

CPU_AGTL

CPU_STPCLK_L

CPU_ASYNC

CPU_55S

PM_THRMTRIP_L

CPU_8MIL

PM_THRMTRIP_L

FSB_CLK_ITP

CLK_FSB

FSB_CLK_ITP_P

CLK_FSB_100D

CPU_55S

XDP_TRST_L

CPU_ITP

XDP_TRST_L

MCP_FSB_COMP

MCP_50S

MCP_CPU_COMP_VCC

MCP_CPU_COMP

MCP_50S

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP MCP_FSB_COMP

CPU_VCCSENSE

IMVP6_VSEN_N

CPU_27P4S

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_55S

IMVP6_VID<6..0>

CPU_8MIL

CPU_55S

CPU_VID<6..0>

CPU_8MIL

CPU_55S

XDP_BPM_L5

CPU_ITP

XDP_BPM_L<5>

CPU_55S

XDP_CPURST_L

CPU_ITP

CPU_55S

XDP_BPM_L

XDP_BPM_L<4..0>

CPU_ITP

CPU_55SXDP_TCK CPU_ITP

XDP_TCK

CPU_55S

XDP_TDO

XDP_TDO CPU_ITP

CPU_55SXDP_TMS CPU_ITP

XDP_TMS

CPU_55S

PM_DPRSLPVR

CPU_AGTL

PM_DPRSLPVR

FSB_CLK_MCP

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_N

FSB_CLK_CPU

FSB_CLK_CPU_N

CLK_FSB

CLK_FSB_100D

CLK_FSB_100D

FSB_CLK_ITP

CLK_FSB

FSB_CLK_ITP_N

FSB_1X

FSB_HIT_L

FSB_1X

FSB_55S

FSB_HITM_L

FSB_1XFSB_1X

FSB_55S

CPU_55S

CPU_SMI_L

CPU_ASYNC

CPU_AGTL

CPU_55S

CPU_PWRGD

CPU_AGTL

CPU_PWRGD

CPU_55S

CPU_PROCHOT_L

CPU_PROCHOT_L

CPU_AGTL

CPU_55S

CPU_FERR_L

CPU_FERR_L

CPU_8MIL

CPU_55S

CPU_BSEL<2..0>

CPU_AGTLCPU_BSEL

CPU_55S

CPU_AGTL

CPU_A20M_L

CPU_ASYNC

FSB_TRDY_L

FSB_1X FSB_1X

FSB_55S

FSB_1X

FSB_CPURST_L

FSB_CPURST_L

FSB_55S

FSB_LOCK_L

FSB_1XFSB_1X

FSB_55S

FSB_1X

FSB_DRDY_L

FSB_1X

FSB_55S

FSB_BNR_L

FSB_1XFSB_1X

FSB_55S

FSB_ADDR_GROUP1

FSB_ADDR

FSB_A_L<35..17>

FSB_55S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_DSTB_55S

FSB_D_L<31..16>

FSB_DATA

FSB_DATA_GROUP1

FSB_55S

FSB_DINV_L<1>

FSB_DATA

FSB_DATA_GROUP1

FSB_55S

FSB_D_L<63..48>

FSB_DATA

FSB_DATA_GROUP3

FSB_55S

FSB_DATA_GROUP3

FSB_DINV_L<3>

FSB_DATA

FSB_55S

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_DSTB_55S

FSB_DSTB

FSB_DSTB3

FSB_DSTB_L_N<3>

FSB_DSTB_55S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_A_L<16..3>

FSB_55S

FSB_ADDR_GROUP0

FSB_REQ_L<4..0>

FSB_ADDR

FSB_55S

FSB_ADSTB

FSB_ADSTB_L<1>

FSB_ADSTB1

FSB_55S

FSB_ADS_L

FSB_1X FSB_1X

FSB_55S

FSB_BREQ0_L

FSB_BREQ0_L

FSB_1X

FSB_55S

FSB_ADSTB

FSB_ADSTB_L<0>

FSB_ADSTB0

FSB_55S

CPU_55S

CPU_AGTL

FSB_CPUSLP_L

FSB_CPUSLP_L

FSB_DSTB0

FSB_DSTB_L_P<0>

FSB_DSTBFSB_DSTB_55S

FSB_DINV_L<2>

FSB_DATA

FSB_DATA_GROUP2

FSB_55S

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_DSTB1

FSB_DSTB_55S

FSB_DATA_GROUP0

FSB_DINV_L<0>

FSB_DATA

FSB_55S

FSB_DATA_GROUP0

FSB_D_L<15..0>

FSB_DATA

FSB_55S

FSB_DSTB

FSB_DSTB2

FSB_DSTB_L_N<2>

FSB_DSTB_55S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_55S

FSB_DATA

FSB_D_L<47..32>

FSB_DATA_GROUP2

FSB_55S

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_N<1>

FSB_DSTB_55S

FSB_BPRI_L

FSB_1XFSB_1X

FSB_55S

FSB_1X

FSB_DBSY_L

FSB_1X

FSB_55S

FSB_1X

FSB_DEFER_L

FSB_1X

FSB_55S

FSB_1X

FSB_RS_L<2..0>

FSB_1X

FSB_55S

CPU_GTLREF

CPU_50S

CPU_GTLREF CPU_GTLREF

MCP_50S

MCP_CPU_COMP_GND

MCP_CPU_COMP MCP_FSB_COMP

CPU_55S

CPU_AGTL

IMVP_DPRSLPVR

FSB_CLK_CPU

FSB_CLK_CPU_P

CLK_FSB

CLK_FSB_100D

CPU_55S

CPU_AGTL

FSB_DPWR_L

CPU_ASYNC

CPU_55S

CPU_AGTL

CPU_DPRSTP_L

CPU_DPRSTP_L

CPU_55S

CPU_AGTL

CPU_DPSLP_L

CPU_FROM_SB

MCP_BCLK_VML_COMP_GND

MCP_50S

MCP_CPU_COMP MCP_FSB_COMP

CPU_55S

CPU_IERR_L

CPU_IERR_L

CLK_FSB_100D

FSB_CLK_MCP

CLK_FSB

FSB_CLK_MCP_P

CPU_55S CPU_ITPXDP_TDI

XDP_TDI

CPU_27P4S

CPU_COMP CPU_COMP

CPU_COMP<0>

CPU_50S

CPU_COMP

CPU_COMP<1>

CPU_COMP

CPU_COMP

CPU_COMP<2>

CPU_27P4S

CPU_COMP

CPU_50S

CPU_COMP

CPU_COMP<3>

CPU_COMP

CPU_55S

CPU_NMI

CPU_ASYNC_R

CPU_AGTL

CPU_55S

CPU_INTR

CPU_ASYNC_R

CPU_AGTL

CPU_55S

CPU_INIT_L

CPU_INIT_L

CPU_AGTL

CPU_55S

CPU_AGTL

CPU_IGNNE_L

CPU_ASYNC

100 OF 110

3.3.0

051-8467

66 OF 74

10 14

10 14 40

13 14

10 13

14

14

54

54

11 54

11 54

12

11 12 54

10 13

13

10 13

10 13

10 13

10 13

14 54

14

10 14

13 14

7

10 14

7

10 14

10 14

10 13 14

10 14 40

10 14

9

10

10 14

10 14

10 13 14

7

10 14

10 14

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

10 14

7

10 14

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

10 14

10 14

10 14

10 14

10 33

14

10 14

10 14

10 14 54

10 14

14

10

14

10 13

10

10

10

10

10 14

10 14

10 14

10 14

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

No DQS to clock matching requirement.

All memory signals maximum length is 1.030 ps.

DDR3:

DQ signals should be matched within 5 ps of associated DQS pair.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
CMD/CTRL signals should be matched within 150 ps.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

MCP MEM COMP Signal Constraints

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2

Need to support MEM_*-style wildcards!

Memory Bus Spacing Group Assignments

NV DG says 3x inner, 4x outer

NV DG says 2x inner, 4x outer

NV DG says 4x inner, 5x outer

NV DG says 2x inner, 4x outer

NV DG says 2x inner, 4x outer
NV DG says 2x inner, 4x outer
NV DG says 2x inner, 4x outer
NV DG says 2x inner, 4x outer

Memory Bus Constraints

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

Memory Net Properties

MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

MEM_50S

=STANDARD* =STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

MEM_55S

=STANDARD* =STANDARD

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF =70_OHM_DIFF

* =70_OHM_DIFF =70_OHM_DIFF

MEM_70D

MCP_MEM_COMP

* =STANDARD =STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=2x_DIELECTRIC

MCP_MEM_COMP

*

?

MEM_DQS2MEM

*

MEM_CLKMEM_DQS

MEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS MEM_CMD

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

MEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS

MEM_CTRL2MEM

MEM_CTRL

*

MEM_CLK

MEM_CTRL2MEM

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATAMEM_CTRL

MEM_CTRL2MEM

*

MEM_CMD

MEM_CTRL

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

*

MEM_CLK2MEM

MEM_CLKMEM_CLK

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

MEM_2OTHER

**

MEM_DATA

**

MEM_DQS

MEM_2OTHER

* *

MEM_CMD

MEM_2OTHER

* *

MEM_CLK

MEM_2OTHER

**

MEM_CTRL

MEM_2OTHER

*

MEM_DATA2DATA

MEM_DATAMEM_DATA

MEM_DQS

*

MEM_DATA

MEM_DATA2MEM

MEM_CMD

*

MEM_DATA

MEM_DATA2MEM

MEM_CTRL

MEM_DATA2MEM

*

MEM_DATA

MEM_CLK

MEM_DATA

MEM_DATA2MEM

*

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

MEM_CMD2MEM

MEM_CMD

*

MEM_CMD2CMD

MEM_CMDMEM_CMD

*

MEM_CLK

MEM_CMD2MEM

*

MEM_CMD

MEM_CTRL

MEM_CMD2MEM

MEM_CMD

*

?

*

MEM_2OTHER

25 MIL

=1.5:1_SPACING

?

*

MEM_DATA2DATA

*

MEM_DQS2MEM

=3:1_SPACING

?

?

*

=3:1_SPACINGMEM_DATA2MEM

=3:1_SPACING

?

*

MEM_CMD2MEM

?

*

MEM_CMD2CMD

=1.5:1_SPACING

=4:1_SPACING

?

*

MEM_CLK2MEM

?

*

=2:1_SPACING

MEM_CTRL2CTRL

=2.5:1_SPACING

?

*

MEM_CTRL2MEM

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

Memory Constraints

MEM_55SMEM_A_DQ_BYTE7

MEM_DATA

MEM_A_DQ<63..56>

MEM_50S

MEM_A_CKE

MEM_CTRL

MEM_A_CKE<3..0>

MEM_50S

MEM_B_CKE

MEM_CTRL

MEM_B_CKE<3..0>

MEM_50S

MEM_A_CNTL

MEM_A_CS_L<3..0>

MEM_CTRL

MEM_50S

MEM_A_CMD

MEM_CMD

MEM_A_BA<2..0>

MEM_50S

MEM_A_CMD

MEM_CMD

MEM_A_RAS_L

MEM_55SMEM_A_DQ_BYTE2

MEM_DATA

MEM_A_DQ<23..16>

MEM_55SMEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DM<4>

MEM_55SMEM_A_DQ_BYTE6

MEM_A_DM<6>

MEM_DATA

MEM_A_DQS4

MEM_DQS

MEM_A_DQS_N<4>

MEM_70D

MEM_A_DQS6

MEM_DQS

MEM_A_DQS_N<6>

MEM_70D

MEM_A_DQS7

MEM_70D MEM_DQS

MEM_A_DQS_P<7>

MEM_B_CLK

MEM_70D

MEM_B_CLK_N<5..0>

MEM_CLK

MEM_50S

MEM_B_CNTL

MEM_CTRL

MEM_B_CS_L<3..0>

MEM_70D MEM_DQS

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_A_DQS3

MEM_70D MEM_DQS

MEM_A_DQS_P<3>

MEM_55SMEM_A_DQ_BYTE0

MEM_A_DM<0>

MEM_DATA

MEM_50S

MEM_A_CNTL

MEM_A_ODT<3..0>

MEM_CTRL

MEM_50S

MEM_A_CMD

MEM_A_A<15..0>

MEM_CMD

MEM_50S

MEM_A_CMD

MEM_CMD

MEM_A_CAS_L

MEM_50S

MEM_A_CMD

MEM_A_WE_L

MEM_CMD

MEM_55SMEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DQ<47..40>

MEM_55SMEM_A_DQ_BYTE1

MEM_A_DM<1>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE2

MEM_DATA

MEM_A_DM<2>

MEM_55SMEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DQ<39..32>

MEM_55SMEM_A_DQ_BYTE1

MEM_DATA

MEM_A_DQ<15..8>

MEM_DQSMEM_70D

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_DQS

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_70D

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_DQSMEM_70D

MEM_B_CLK

MEM_70D

MEM_B_CLK_P<5..0>

MEM_CLK

MEM_70D MEM_CLK

MEM_A_CLK

MEM_A_CLK_P<5..0>

MEM_70D MEM_CLK

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_55SMEM_A_DQ_BYTE3

MEM_A_DM<3>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DM<5>

MEM_A_DQS0

MEM_70D MEM_DQS

MEM_A_DQS_N<0>

MEM_A_DQS1

MEM_70D MEM_DQS

MEM_A_DQS_N<1>

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<2>

MEM_A_DQS2
MEM_A_DQS2

MEM_DQS

MEM_A_DQS_N<2>

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_70D MEM_DQS

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_70D MEM_DQS

MEM_A_DQS_N<5>

MEM_A_DQS5
MEM_A_DQS6

MEM_DQS

MEM_A_DQS_P<6>

MEM_70D

MEM_55S

MEM_DATA

MEM_B_DQ<47..40>

MEM_B_DQ_BYTE5

MEM_55S

MEM_DATA

MEM_B_DQ<39..32>

MEM_B_DQ_BYTE4

MEM_55S

MEM_DATA

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1

MEM_55S

MEM_DATA

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2

MEM_50S MEM_CMD

MEM_B_WE_L

MEM_B_CMD

MEM_55S

MEM_DATA

MEM_B_DQ<31..24>

MEM_B_DQ_BYTE3

MEM_55S

MEM_DATA

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7

MEM_55S

MEM_DATA

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6

MEM_55S

MEM_DATA

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0

MEM_55S

MEM_DATA

MEM_B_DM<0>

MEM_B_DQ_BYTE0

MEM_50S MEM_CMD

MEM_B_BA<2..0>

MEM_B_CMD

MEM_DQSMEM_70D

MEM_B_DQS_N<6>

MEM_B_DQS6

MEM_DQSMEM_70D

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_55S

MEM_DATA

MEM_B_DM<7>

MEM_B_DQ_BYTE7

MEM_DQSMEM_70D

MEM_B_DQS_P<6>

MEM_B_DQS6

MEM_DQSMEM_70D

MEM_B_DQS_P<5>

MEM_B_DQS5

MEM_DQS

MEM_B_DQS_N<4>

MEM_70D

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_N<5>

MEM_B_DQS5

MEM_DQSMEM_70D

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_DQSMEM_70D

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_DQSMEM_70D

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_DQSMEM_70D

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_55S

MEM_DATA

MEM_B_DM<6>

MEM_B_DQ_BYTE6

MEM_55S

MEM_DATA

MEM_B_DM<5>

MEM_B_DQ_BYTE5

MEM_55S

MEM_DATA

MEM_B_DM<3>

MEM_B_DQ_BYTE3

MEM_DQSMEM_70D

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_55S

MEM_DATA

MEM_B_DM<4>

MEM_B_DQ_BYTE4

MEM_55S

MEM_DATA

MEM_B_DM<2>

MEM_B_DQ_BYTE2

MEM_55S

MEM_DATA

MEM_B_DM<1>

MEM_B_DQ_BYTE1

MEM_50S

MEM_CTRL

MEM_B_CNTL

MEM_B_ODT<3..0>

MCP_MEM_COMP_VDD

MCP_MEM_COMPMCP_MEM_COMP MCP_MEM_COMP

MCP_MEM_COMP_GND

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_50S MEM_CMD

MEM_B_CAS_L

MEM_B_CMD

MEM_50S MEM_CMD

MEM_B_RAS_L

MEM_B_CMD

MEM_50S

MEM_B_A<15..0>

MEM_CMD

MEM_B_CMD

MEM_55SMEM_A_DQ_BYTE7

MEM_A_DM<7>

MEM_DATA

MEM_A_DQS0

MEM_A_DQS_P<0>

MEM_70D MEM_DQS

101 OF 110

3.3.0

051-8467

67 OF 74

15 27

15 21 26 27 32

15 21 28 29 32

15 26 27 32

15 26 27 32

15 26 27 32

15 26

15 27

15 26

15 27

15 27

15 27

15 27

15 27

9

15 28 29 32

15 28 29 32

15 27

15 26

15 26

15 26 27 32

9

15 26 27 32

15 26 27 32

15 26 27 32

15 26

15 27

15 26

15 26

15 27

15 26

15 28

15 28

15 27

9

15 28 29 32

9

15 26 27 32

9

15 26 27 32

15 26

15 27

15 26

15 26

15 26

15 26

15 26

15 27

15 26

15 27

15 27

15 29

15 29

15 28

15 28

15 28 29 32

15 28

15 29

15 29

15 28

15 28

15 28 29 32

15 29

15 29

15 29

15 29

15 29

15 29

15 29

15 28

15 29

15 28

15 28

15 28

15 28

15 28

15 29

15 29

15 28

15 29

15 29

15 28

15 28

15 28 29 32

15

15

15 28 29 32

15 28 29 32

9

15 28 29 32

15 27

15 26

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

PCI-Express

PHYSICAL

SPACING

NET_TYPENET_TYPE

MCP89 Net Properties

ELECTRICAL_CONSTRAINT_SET

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3

Analog Video Signal Constraints

- 75-ohm from output of three-pole filter to connector (if possible).

- 37.5-ohm from MCP to first termination resistor.

Digital Video Signal Constraints

NEED PCIe Gen1/Gen2 notes!

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.

- 50-ohm from first to second termination resistor.

CRT signal single-ended impedence varies by location:

R/G/B signals should be matched as close as possible and < 10 inches.

SATA Interface Constraints

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2

LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.

NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm.

SATA intra-pair matching should be 1 ps.

DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max trace length: LVDS 10 inches, DP 8.5 inches.

Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6

PCIE_90D

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF*

=90_OHM_DIFF

=90_OHM_DIFF

PCIE

?

TOP,BOTTOM

=4X_DIELECTRIC

20 MIL

CLK_PCIE

?

*

8 MIL

MCP_PEX_COMP

?

*

PCIE

=3X_DIELECTRIC

?

*

=100_OHM_DIFF

=100_OHM_DIFF

CLK_PCIE_100D =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

MCP Constraints 1

CRT_2CRT

*

CRTCRT

CRT_50S

=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE=50_OHM_SE =50_OHM_SE

CRT

*

?

20 MIL

TOP,BOTTOM

=4x_DIELECTRIC

?

DISPLAYPORT

?

LVDS

=4x_DIELECTRIC

TOP,BOTTOM

CRT_2CRT

?

*

15 MIL

?

*

CRT_2CLK

50 MIL

MCP_DAC_COMP

*

?

=2x_DIELECTRIC

CRT_SYNC

?

*

=4x_DIELECTRIC

*

?

CRT_2SWITCHER

250 MIL

?

*

LVDS

=3x_DIELECTRIC

=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

SATA

?

TOP,BOTTOM

=4x_DIELECTRIC

*

?

SATA_TERMP 8 MIL

?

SATA

*

=3x_DIELECTRIC

*

SATA_90D

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

=3x_DIELECTRIC

*

?

DISPLAYPORT

*

Y

20 MIL 20 MIL

=STANDARD

=STANDARD =STANDARD

MCP_DV_COMP

DP_90D

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF*

DP_90D

DP_IG_ML0_P<3..0>

DISPLAYPORT

DP_EXT_ML

DP_90D

DISPLAYPORT

DP_IG_AUX_CH0_P

DP_EXT_AUX_CH

DP_IG_AUX_CH0_N

DISPLAYPORT

DP_90D

DP_EXT_AUX_CH

MCP_DV_COMP

MCP_TMDS0_RSET

MCP_TMDS0_RSET

DP_INT_ML

DP_90D

DP_IG_ML1_P<1..0>

DISPLAYPORT

DP_INT_ML

DISPLAYPORT

DP_90D

DP_IG_ML1_N<1..0>

DP_IG_ML0_N<3..0>

DP_90D

DISPLAYPORT

DP_EXT_ML

LVDS_100D

LVDS_IG_A_CLK

LVDS_IG_A_CLK_P

LVDS

LVDS_IG_A_DATA

LVDS_100D

LVDS_IG_A_DATA_P<2..0>

LVDS

LVDS

LVDS_IG_A_DATA_P<3>

LVDS_100D

LVDS_IG_A_DATA3

LVDS_100D

LVDS_IG_A_DATA_N<3>

LVDS

LVDS_IG_A_DATA3

MCP_TMDS0_VPROBE

MCP_TMDS0_VPROBE

LVDS_IG_A_CLK_N

LVDS

LVDS_100D

LVDS_IG_A_CLK

LVDS_IG_B_CLK_P

LVDS

LVDS_IG_B_CLK

LVDS_100D

LVDS_IG_B_CLK_N

LVDS

LVDS_100D

LVDS_IG_B_CLK

PCIEPCIE_90D

PCIE_ENET_D2R_N

PCIEPCIE_90D

PCIE_ENET_D2R_C_P

PCIEPCIE_90D

PCIE_ENET_D2R_C_N

PCIEPCIE_90D

PCIE_FW_R2D_P

PCIE_FW_R2D

PCIE_FW_R2D_C_P

PCIEPCIE_90D
PCIEPCIE_90D

PCIE_FW_R2D_C_N

PCIE_FW_D2R

PCIE_FW_D2R_P

PCIEPCIE_90D

PCIE_FW_D2R_N

PCIEPCIE_90D

PCIE_FW_D2R_C_N

PCIEPCIE_90D

CLK_PCIE

PEG_CLK100M_P

CLK_PCIE_100D

MCP_PE0_REFCLK

PEG_CLK100M_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_AP_N

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_ENET_P

CLK_PCIE_100D

MCP_PE2_REFCLK

CLK_PCIE

PCIE_CLK100M_ENET_N

CLK_PCIE_100D

CRT_IG_R_C_PR

CRT

CRT_50SCRT_RED
CRT_50S

CRT_IG_G_Y_Y

CRT

CRT_GREEN

CRT_50S

CRT

CRT_IG_B_COMP_PB

CRT_BLUE

PCIE_CLK100M_FW_N

CLK_PCIE_100D

CLK_PCIE

PCIE_FW_D2R_C_P

PCIEPCIE_90D

PCIE_90D PCIE

PEG_D2R_N<15..0>

PEG_D2R_C_N<15..0>

PCIEPCIE_90D

PCIE_AP_R2D_C_P

PCIE_AP_R2D

PCIE_90D PCIE

MCP_SATA_TERMP

SATA_TERMP

MCP_SATA_TERMP

SATA

SATA_ODD_D2R_C_P

SATA_90D

SATA_ODD_D2R_C_N

SATASATA_90D

SATA

SATA_ODD_D2R_N

SATA_90D

SATA_ODD_D2R_P

SATASATA_ODD_D2R SATA_90D

SATA

SATA_ODD_R2D_N

SATA_90D

SATA

SATA_ODD_R2D_C_N

SATA_90D

SATA

SATA_ODD_R2D_P

SATA_90D

SATA_ODD_R2D_C_P

SATASATA_ODD_R2D SATA_90D

SATA

SATA_HDD_D2R_C_N

SATA_90D

SATA

SATA_HDD_D2R_C_P

SATA_90D

SATA

SATA_HDD_D2R_P

SATA_HDD_D2R SATA_90D

SATA

SATA_HDD_D2R_N

SATA_90D

SATA

SATA_HDD_R2D_N

SATA_90D

SATA_HDD_R2D_P

SATASATA_90D

SATA

SATA_HDD_R2D_C_N

SATA_90D

SATA_HDD_R2D_C_P

SATASATA_HDD_R2D SATA_90D

MCP_IFPAB_VPROBE

MCP_IFPAB_VPROBE

LVDS

LVDS_100D

LVDS_IG_B_DATA3

LVDS_IG_B_DATA_N<3>

LVDS

LVDS_100D

LVDS_IG_B_DATA3

LVDS_IG_B_DATA_P<3>

LVDS

LVDS_100D

LVDS_IG_B_DATA

LVDS_IG_B_DATA_P<2..0>

LVDS_100D

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_DATA

LVDS

DP_INT_AUX_CH

DP_IG_AUX_CH1_N

DP_90D

DISPLAYPORT

PCIEPCIE_90D

PCIE_ENET_R2D_N

PCIEPCIE_90D

PCIE_ENET_D2R_P

PCIE_ENET_D2R

PCIEPCIE_90D

PCIE_ENET_R2D_P

PCIEPCIE_90D

PCIE_ENET_R2D_C_N

PEG_D2R_C_P<15..0>

PCIEPCIE_90D

PEG_R2D_C_P<15..0>

PCIE_90D PCIE

PEG_R2D

PEG_D2R_P<15..0>

PCIE_90D PCIE

PEG_D2R

PCIE_AP_R2D_N

PCIEPCIE_90D

PCIE_90D PCIE

PEG_R2D_C_N<15..0>

PCIEPCIE_90D

PCIE_AP_R2D_P

MCP_IFPAB_RSET

MCP_IFPAB_RSET

MCP_DV_COMP

LVDS_100D

LVDS_IG_B_DATA

LVDS

LVDS_IG_B_DATA_N<2..0>

MCP_PEX_COMP

MCP_PEX0_TERMP

MCP_PEX_CLK_COMP

CLK_PCIE

PCIE_CLK100M_FW_P

CLK_PCIE_100D

MCP_PE3_REFCLK

PCIEPCIE_90D

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D

PCIE_FW_R2D_N

PCIEPCIE_90D

PCIE_CLK100M_AP_P

CLK_PCIE

CLK_PCIE_100D

MCP_PE1_REFCLK

PCIEPCIE_90D

PCIE_AP_D2R_N

PCIE_AP_D2R_P

PCIE_AP_D2R

PCIEPCIE_90D

PCIE_AP_R2D_C_N

PCIEPCIE_90D

PEG_R2D_N<15..0>

PCIE_90D PCIE

PCIE_90D PCIE

PEG_R2D_P<15..0>

CRT_50S

CRT_IG_VSYNC

CRT_SYNCCRT_SYNC

MCP_TV_DAC_VREF

MCP_DAC_COMPMCP_DAC_VREF

CRT_IG_HSYNC

CRT_SYNC

CRT_50S

CRT_SYNC

MCP_TV_DAC_RSET

MCP_DAC_COMPMCP_DAC_RSET

DP_INT_AUX_CH

DP_IG_AUX_CH1_P

DP_90D

DISPLAYPORT

102 OF 110

3.3.0

051-8467

68 OF 74

9

17

9

17

9

17

17 24

9

17

9

17

9

17

17 24

9

16

9

16

7

16 34

16 34

18

9

18

9

18

9

18

9

18

7

35

7

35

18 35

18 35

7

35

7

35

18 35

18 35

17 24

9

17

7

34

7

34

17 24

16

7

16 34

7

16 34

7

16 34

16 34

9

17

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.8

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.10

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.9

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.11

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.12

SIO Signal Constraints

(SMBUS_SMC_MGMT_SDA)

(SMBUS_SMC_MGMT_SCL)

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.7

SPACING

PHYSICAL

LPC Bus Constraints

HD Audio Interface Constraints

SPI Interface Constraints

USB 2.0 Interface Constraints

SMBus Interface Constraints

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

MCP89 Net Properties

USB_90D

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=STANDARD*

LPC_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

CLK_LPC_55S

*

=1.5x_DIELECTRIC

*

?

LPC

=2x_DIELECTRIC

?

*

CLK_LPC

*

?

USB

=2x_DIELECTRIC

=55_OHM_SE

* =STANDARD =STANDARD

SMB_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=2x_DIELECTRIC

?

*

SMB

* =STANDARD=STANDARD

HDA_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

?

*

8 MIL

MCP_HDA_COMP

=2x_DIELECTRIC

HDA

*

?

=STANDARD =STANDARD

CLK_SLOW_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

=1.5x_DIELECTRIC

*

CLK_SLOW

?

=STANDARD=STANDARD*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

SPI_55S

=55_OHM_SE

=1.5x_DIELECTRIC

*

SPI

?

8 MIL

=STANDARD

=STANDARD =STANDARD

8 MIL

=STANDARD

*

MCP_USB_RBIAS

USB

?

TOP,BOTTOM

=4x_DIELECTRIC

MCP Constraints 2

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

SPI

SPI_55S

SPI_ALT_CLK

SPI_55S

SPI

SPI_ALT_MISO

SPI_55S

SPI

SPI_ALT_MOSI

SPI

SPI_55S

SPI_ALT_CS_L

SPI_55S

SPI

SPI_MLB_CS_L

SPI

SPI_55S

SPI_MLB_MOSI

SPI_55S

SPI

SPI_MLB_CLK

SPI_CS0_L

SPI_55S

SPI

SPI

SPI_55S

SPI_MOSI

SPI_CLK

SPI

SPI_55S

HDA_55S

HDA

HDA_RST_R_L

HDA_RST_L

HDA_55S

HDA

HDA_RST_L

SPI_55S

SPI

SPI_MOSI

SPI_MOSI_R

SPI

SPI_55SSPI_CS0

SPI_CS0_R_L

HDA_SDIN_CODEC

HDA_55S

HDA

HDA_55S

HDA_SDOUT

HDA

HDA_SDOUT

HDA

HDA_SDOUT_R

HDA_55S

PM_CLK32K_SUSCLK_R

CLK_SLOWCLK_SLOW_55S

MCP_SUS_CLK

USB

USB_EXTC_N

USB_90D

USB

USB_90D

USB_SDCARD_N

USB_90D

USB

USB_EXTC

USB_EXTC_P

USB

USB_90D

USB_T57_P

USB_T57

USB_CAMERA_N

USB_90D

USB

USB_BT_P

USB_BT

USB

USB_90D

USB_TPAD

USB_TPAD_P

USB_90D

USB

USB_TPAD_N

USB_90D

USB

USB_IR

USB_90D

USB

USB_IR_P
USB_IR_N

USB

USB_90D

USB_EXTB_P

USB_EXTB

USB

USB_90D

USB_EXTB_N

USB

USB_90D

USB_90D

USB

USB_T57_N

USB_90D

USB

USB_WM_N

HDA_55S

HDA

HDA_BIT_CLK

HDA_BIT_CLK

HDA_55S

HDA

HDA_SYNC_R

HDA_SDIN0

HDA_55S

HDA

HDA_SDIN0

USB_CAMERA_P

USB

USB_CAMERA

USB_90D

USB_BT_N

USB

USB_90D

USB_90D

USB_EXTD_N

USB

USB_EXTD

USB_90D

USB_EXTD_P

USB

USB_90D

USB

USB_MINI_N

USB_EXTA_MUXED_N

USB

USB_90D

USB_MINI_P

USB_MINI

USB_90D

USB

USB_EXTA_MUXED_P

USB_90D

USB

USB_90D

USB_EXTA_N

USB

USB_EXTA_P

USB_90D

USB

USB_EXTA

LPC_CLK33M_LPCPLUS

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_SMC

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_SMC_R

CLK_LPC_55S

CLK_LPC

MCP_LPC_CLK0

LPC_55S

LPC_RESET_L

LPC

LPC_RESET_L

LPC_55S

LPC

LPC_FRAME_L

LPC_FRAME_L

LPC

LPC_55S

LPC_AD<3..0>

LPC_AD

SPI_MISO

SPI_55S

SPI_MISO

SPI

PM_CLK32K_SUSCLK

CLK_SLOW_55S CLK_SLOW

MCP_HDA_PULLDN_COMP

MCP_HDA_PULLDN_COMP

MCP_HDA_COMP

HDA_55S

HDA

HDA_BIT_CLK_R

HDA_55S

HDA_SYNC

HDA

HDA_SYNC

SMB_55S

SMB

SMBUS_MCP_1_DATA

SMB_55S

SMB

SMBUS_MCP_1_CLK

SMB_55S

SMBUS_MCP_0_DATA

SMB

SMBUS_MCP_0_DATA

SMB_55S

SMBUS_MCP_0_CLK

SMBUS_MCP_0_CLK

SMB

MCP_USB_RBIAS MCP_USB_RBIAS

MCP_USB_RBIAS_GND

USB_90D

USB

USB_SDCARD_P

USB_SDCARD

USB

USB_90D

USB_WM

USB_WM_P

SPI_55SSPI_CLK

SPI_CLK_R

SPI

SPI

SPI_55S

SPI_MLB_MISO

103 OF 110

3.3.0

051-8467

69 OF 74

7

41

7

41

7

41

7

41

41 48

41 48

41 48

41

41

41

19

7

19 37

19 41

19 41

7

19 37

19

19 25

9

18

18 38

9

18

7

18 37

7

18 34

18 47 72

18 47 72

7

19 37

19

7

19 37

7

18 37

7

18 34

7

18 37

7

18 37

9

18

36 72

9

18

36 72

18 36

18 36

7

25 41

25 39

19 25

19 25

7

19 39 41

7

19 39 41

19 41

25 39

19

19

7

19 37

19 42

19 42

19 42

19 42

18

18 38

19 41

41 48

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

88E1116R (Ethernet PHY) Constraints

Ethernet Net Properties

PHYSICAL

SD Card Net Properties

MCP RGMII (Ethernet) Constraints

SPACING

RGMII Net Properties

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NOTE: SD_D<7..5> are different to support

SPACING

NET_TYPE

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

ELECTRICAL_CONSTRAINT_SET

BCM5764M/BCM57765 co-layout.

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

SD Card Interface Constraints

=STANDARD

MCP_MII_COMP

*

7.5 MIL

=STANDARD=STANDARD

7.5 MIL

=STANDARD

=55_OHM_SE

=55_OHM_SE

* =STANDARD=STANDARD

ENET_MII_55S

=55_OHM_SE =55_OHM_SE

?

=3:1_SPACINGMCP_BUF0_CLK

*

ENET_MII

*

?

12 MIL

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF

ENET_MDI_100D

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

Ethernet Constraints

25 MIL

ENET_MDI

*

?

SD_55S

=55_OHM_SE=55_OHM_SE =55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE

*

SD_INTERFACE

=3X_DIELECTRIC

?

*

ENET_RESET_L

ENET_MIIENET_MII_55S

ENET_MII

ENET_MDIO

ENET_MDIO

ENET_MII_55S

ENET_RXCLK

ENET_CLK125M_RXCLK_R

ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S

ENET_RXD_STRAP

ENET_RXD<3..1>

ENET_MII_55S ENET_MIIENET_RXD

ENET_RX_CTRL

ENET_MII

ENET_RXD_R<3..0>

ENET_MII_55S

ENET_CLK125M_RXCLK

ENET_MII_55S ENET_MII

ENET_MIIENET_TXD

ENET_TXD<0>

ENET_MII_55S
ENET_MII_55S

ENET_TXD<3..1>

ENET_MIIENET_TXD

ENET_INTR_L

ENET_MII_55S

ENET_INTR_L

ENET_MII

RTL8211_CLK25M_CKXTAL1

MCP_BUF0_CLKENET_MII_55S

MCP_BUF0_CLK

MCP_CLK25M_BUF0

MCP_CLK25M_BUF0_R

ENET_MII_55S

MCP_MII_COMP_VDD

MCP_MII_COMP MCP_MII_COMP

MCP_MII_COMP_GND

MCP_MII_COMP MCP_MII_COMP

ENET_MII

ENET_MDC

ENET_MDC ENET_MII_55S

ENET_MII

ENET_PWRDWN_L

ENET_PWRDWN_L

ENET_MII_55S

ENET_MII_55S

ENET_CLK125M_TXCLK

ENET_MII

ENET_TXCLK

ENET_TX_CTRL

ENET_MII_55S ENET_MIIENET_TXD

ENET_MDI

ENET_MDI_100D

ENET_MDI_N<3..0>

ENET_MDI

ENET_MDI_P<3..0>

ENET_MDI

ENET_MDI_100D

SD_55S

SD_INTERFACE

SDCONN_DATA<4..0>

SD_INTERFACE

SD_DATA

SD_55S

SD_D<4..0>

SD_55S

SD_INTERFACE

BCM57765_CR_DATA<4>
SD_D<7..5>

SD_DATA_R

SD_INTERFACE

SD_55S

SD_INTERFACE

SD_55S

SDCONN_DATA<7..5>
BCM57765_CR_DATA<7..5>

SD_INTERFACE

SD_55S

SD_CLK SD_55S

SD_INTERFACE

SD_CLK

SD_55S

SD_INTERFACE

SDCONN_CLK

SD_55S

SD_INTERFACE

SD_CLK_R

SD_55S

SD_INTERFACE

SDCONN_CMD

SD_INTERFACE

SD_55SSD_CMD

SD_CMD

BCM57765_CR_CMD

SD_INTERFACE

SD_55S

ENET_RXD_STRAP

ENET_MII

ENET_RXD<0>

ENET_MII_55S

104 OF 110

3.3.0

051-8467

70 OF 74

9

18

9

18

9

18

9

18

18

18

7

38

7

38

7

38

38

7

38

9

18

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

SMC Constraints

SYNC_MASTER=K99_MLB

SYNC_DATE=04/08/2010

=STANDARD =STANDARD

0.1 MM 0.1 MM

*

=STANDARD=STANDARD

1TO1_DIFFPAIR

SMB_55S

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SCL

SMB

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SDA

SMB

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMB_55S

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SCL

SMB

SMB_55S

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMB

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SCL

SMB_55S

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SDA

SMB

SMB_55S

SMBUS_SMC_B_S0_SDA

SMB

SMBUS_SMC_B_S0_SDA

SMB_55S

SMBUS_SMC_B_S0_SCL

SMB

SMBUS_SMC_B_S0_SCL

SMB_55S

SMBUS_SMC_A_S3_SDA

SMB_55S

SMBUS_SMC_A_S3_SDA

SMB

CHGR_CSI

1TO1_DIFFPAIR

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI_N
CHGR_CSI_R_P

1TO1_DIFFPAIR

CHGR_CSO_R_N

1TO1_DIFFPAIR

CHGR_CSO_N

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSI_R_N

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

106 OF 110

3.3.0

051-8467

71 OF 74

42

42

42

42

7

42

7

42

42

42

42

42

51

51

51

44 51

51

51

51

44 51

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

(USB_EXTA)

(USB_TPAD)
(USB_TPAD)
(USB_TPAD)

NET_TYPE

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPACING

(USB_EXTA)

(USB_TPAD)

Misc Net Properties

PHYSICAL

(USB_EXTA)

(USB_EXTA)

ELECTRICAL_CONSTRAINT_SET

Power Net Properties

SPACING

NET_TYPE

PHYSICAL

Audio Net Properties

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

(DP_EXT_AUX_CH)

(DP_EXT_ML)

Graphics Net Properties

MCP Fanout Constraint Relaxations

SD CARD READER LAYOUT RELAXATIONS

=1:1_DIFFPAIR

*

=55_OHM_SE

SENSE_1TO1_55S

=55_OHM_SE=55_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR

PWR_P2MM

MEM_POWER

*

MEM_CLK

SB_POWER PWR_P2MM

SATA

*

SB_POWER PWR_P2MM

USB

*

GND

*

GND_P2MMENET_MDI

PWR_P2MM

MEM_POWER

*

MEM_CTRL

MEM_CLK

GND_P2MM

*

GND

MEM_CMD

GND_P2MM

*

GND

MEM_CTRL GND_P2MM

*

GND

MEM_DATA GND_P2MM

*

GND

*

1000

0.20 MM

PWR_P2MM

1000

0.20 MM

*

GND_P2MM

MEM_POWER

?

*

=STANDARD

GND

?

=STANDARD

*

PCIE

*

GND

GND_P2MM

GND_P2MM

USB

*

GND

SB_POWER PWR_P2MMCLK_PCIE

*

GND_P2MM

GND

*

LVDS

GND_P2MMCLK_PCIE

*

GND

GND_P2MM

SATA

*

GND

MEM_DQS

GND_P2MM

*

GND

GND_P2MM

CPU_GTLREF

*

GND

GND_P2MMCPU_COMP

*

GND

GND_P2MM

*

GND

CLK_FSB

PWR_P2MM

MEM_POWER

*

MEM_CMD

PWR_P2MM

MEM_POWER

*

MEM_DATA

PWR_P2MM

MEM_POWER

*

MEM_DQS

CPU_VCCSENSE

*

GND

GND_P2MM

=1:1_DIFFPAIR

=1:1_DIFFPAIR

*

DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

*

THERM_1TO1_55S

=1:1_DIFFPAIR

=55_OHM_SE =55_OHM_SE=55_OHM_SE

?

25 MILS

*

ENETCONN

=1:1_SPACING

*

SENSE

?

SYNC_MASTER=T27_MLB

SYNC_DATE=09/08/2009

K16/K99 Specific Constraints

=1:1_SPACING

?

*

AUDIO

=1:1_SPACING

?

*

THERM

0.1 MM

500 MIL

TOP

MCP_MII_COMP

0.25 MM

*

250 MIL

MCP_DV_COMP

0.1 MMTOP

MCP_USB_RBIAS

500 MIL

MCP_MEM_COMP

0.1 MM

500 MIL

TOP

MCP_DV_COMP

TOP

500 MIL

0.1 MM

*

0.09 MM

5.8 MM

MEM_40S

=STANDARD

SD_55S

*

USB_90D

USB

USB_TPAD_N

MCPTHMSNS_D2

MLBR_THMDIODE_P

THERM_1TO1_55S

THERM

THERM

CPU_THERMD_P

THERM_1TO1_55S

CPU_THERMD

DRAMTHMSNS_D2_P

THERM_1TO1_55S

THERM

CPUTHMSNS_D2

DRAMTHMSNS_D2_N

THERM_1TO1_55S

THERM

USB_TPAD_CONN_P

USB_90D

USB

USB_EXTA_MUXED_N

USB

USB_90D

USB_LT1_N

USB

USB_90D

USB_90D

USB_LT1_P

USB

USB

USB_EXTA_MUXED_P

USB_90D

USB_90D

USB

USB_TPAD_P

USB_TPAD_CONN_N

USB_90D

USB

THERM

CPU_THERMD_N

THERM_1TO1_55S

MLBR_THMDIODE_N

THERM_1TO1_55S

THERM

MCP_THMDIODE_P

THERM

THERM_1TO1_55S

MCP_THMDIODE

THERM

MCP_THMDIODE_N

THERM_1TO1_55S

CPUVTTS0_CS_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUVTTS0_CS_N

SENSE

SENSE_1TO1_55S

IMVP6_CS_R_N

SENSE

SENSE_1TO1_55S

IMVP6_CS_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_1V5_S3_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_1V5_S3_N

SENSE

SENSE_1TO1_55S

ISNS_CSREG_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_AIRPORT_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_AIRPORT_N

SENSE_1TO1_55S

SENSE

ISNS_CSREG_N

SENSE_1TO1_55S

SENSE
SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_HDD_P

ISNS_LCDBKLT_N

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

ISNS_HDD_N
ISNS_LCDBKLT_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR

CPU_VTTSENSE_P

SENSE_1TO1_55S

SENSE

CPU_VTTSENSE_N

SENSE

SENSE_1TO1_55S

SENSE_DIFFPAIR SENSE_1TO1_55S

MCPCORES0_VSEN_P

SENSE
SENSE

SENSE_1TO1_55S

MCPCORES0_VSEN_N

PP3V3_S5

SB_POWER

PP3V3_S0

SB_POWER

PP1V5_S0

SB_POWER

SPKRAMP_INR

SPKRAMP_INR_P

DIFFPAIR

AUDIO

MAX98300_R

MAX98300_R_P

AUDIO

DIFFPAIR

MAX98300_R_N

AUDIO

DIFFPAIR

I2C_SMC_SMS_SDA_R

SMBUS_SMC_MGMT_SDA

SMB

SMB_55S
SMB_55S

SMB

I2C_SMC_SMS_SCL_R

SMBUS_SMC_MGMT_SCL

DP_INT_ML_N<1..0>

DISPLAYPORT

DP_90D

DISPLAYPORT

DP_90D

DP_INT_ML_F_P<1..0>

DISPLAYPORT

DP_90D

DP_INT_ML_F_N<1..0>

DISPLAYPORT

DP_INT_AUX_CH_C_P

DP_90D

DP_INT_AUX_CH_N

DISPLAYPORT

DP_90D

DP_INT_AUX_CH_P

DISPLAYPORT

DP_90D

DISPLAYPORT

DP_EXT_ML_P<3..0>

DP_90D

DP_EXT_ML_N<3..0>

DISPLAYPORT

DP_90D

DISPLAYPORT

DP_EXT_ML_C_P<3..0>

DP_90D

DP_EXT_ML_C_N<3..0>

DISPLAYPORT

DP_90D
DP_90D

DISPLAYPORT

DP_EXT_ML_F_P<3..0>

DP_90D

DISPLAYPORT

DP_EXT_ML_F_N<3..0>
DP_EXT_AUX_CH_C_P

DP_90D

DISPLAYPORT

DP_90D

DP_EXT_AUX_CH_C_N

DISPLAYPORT

I2C_TCON_SCL

SMB

SMB_55S

I2C_TCON_SDA

SMB_55S

SMB

I2C_TCON_SDA_CONN

SMB

SMB_55S

I2C_TCON_SCL_CONN

SMB_55S

SMB

DP_INT_ML_P<1..0>

DISPLAYPORT

DP_90D

DP_INT_ML_C_P<1..0>

DISPLAYPORT

DP_90D
DP_90D

DISPLAYPORT

DP_INT_ML_C_N<1..0>

SPKRAMP_INR_N

DIFFPAIR

AUDIO

DP_90D

DISPLAYPORT

DP_INT_AUX_CH_C_N

IMVP6_CS_N

SENSE

SENSE_1TO1_55S

IMVP6_CS_R_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

MEM_POWER

PP1V5R1V35_S3

GND

GND

108 OF 110

3.3.0

051-8467

72 OF 74

18 47 69

45

10 45

45

45

7

47

36 69

36

36

36 69

18 47 69

7

47

10 45

45

19 45

19 45

56

56

54

54

43 53

43 53

44

34 43

34 43

44

35 43

43 63

35 43

43 63

56

56

22 55

22 55

7 8

58

7 8

58

7 8

58

7

37 49

49

49

9

60

7

60

7

60

7

60

9

60

9

60

9

62

9

62

62

62

62

62

9

62

9

62

42

42

60

60

9

60

60

60

7

37 49

7

60

54

54

7 8

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

K99 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

0.350 MM

5X_DIELECTRIC

?

*

*

1.5X_DIELECTRIC

0.105 MM

?

2X_DIELECTRIC

0.140 MM

?

*

0.210 MM

3X_DIELECTRIC

?

*

0.280 MM

*

4X_DIELECTRIC

?

ISL4,ISL9

0.250 MM0.250 MM

27P4_OHM_SE

Y

TOP,BOTTOM

0.110 MM

50_OHM_SE

Y

0.110 MM

Y

50_OHM_SE

ISL3,ISL4,ISL9,ISL10

0.090 MM 0.090 MM

55_OHM_SE =STANDARD=STANDARD=STANDARD

=STANDARDY =STANDARD*

40_OHM_SE

0.140 MM

ISL3,ISL4,ISL9,ISL10

Y

0.140 MM

=STANDARD50_OHM_SE

=STANDARD* Y

=STANDARD=STANDARD

=STANDARD

0.3 MM

BGA_P3MM

*

?

0.2 MM

*

BGA_P2MM

?

0.1 MM

?

*

BGA_P1MM

0.130 MM0.130 MM

0.155 MM0.155 MM

ISL4,ISL9

70_OHM_DIFF

Y

55_OHM_SE

ISL3,ISL4,ISL9,ISL10

Y

0.076 MM0.076 MM

ISL4,ISL9

80_OHM_DIFF

0.160 MM0.160 MM

0.125 MM0.125 MM

Y

0.130 MM0.130 MM

0.135 MM0.135 MM

ISL3,ISL10

Y

70_OHM_DIFF

TOP,BOTTOM

Y

55_OHM_SE

0.090 MM 0.090 MM

0.170 MM

40_OHM_SE

0.170 MM

Y

TOP,BOTTOM

15.5.1

NO_TYPE,BGA

MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

0.250 MM

27P4_OHM_SE

0.250 MM

Y

ISL3,ISL10

TOP,BOTTOM

0.130 MM0.130 MM

0.175 MM0.175 MM

70_OHM_DIFF

Y

70_OHM_DIFF

=STANDARD

=STANDARD

Y

*

=STANDARD

=STANDARD=STANDARD

=STANDARD =STANDARD

Y

=STANDARD

*

1:1_DIFFPAIR

0.1 MM 0.1 MM

0.200 MM

0.085 MM

Y

100_OHM_DIFF

0.085 MM

0.200 MM

ISL4,ISL9

0.105 MM

Y

90_OHM_DIFF

0.105 MM

0.210 MM 0.210 MM

ISL4,ISL9

0.089 MM

Y

90_OHM_DIFF

0.089 MM

0.210 MM 0.210 MM

ISL3,ISL10

=STANDARD

=STANDARD=STANDARD

=STANDARD

*

Y

=STANDARD

90_OHM_DIFF

0.140 MM

0.140 MM0.140 MM

0.140 MM

75_OHM_DIFF

ISL4,ISL9

Y

0.105 MM0.105 MM

95_OHM_DIFF

ISL4,ISL9

0.210 MM0.210 MM

Y

0.115 MM

95_OHM_DIFF

0.210 MM0.210 MM

0.115 MM

Y

TOP,BOTTOM

=STANDARD

95_OHM_DIFF

=STANDARD

Y

*

=STANDARD =STANDARD

=STANDARD

95_OHM_DIFF

ISL3,ISL10

0.210 MM0.210 MM

0.089 MM

Y

0.089 MM

100_OHM_DIFF

=STANDARD =STANDARD

=STANDARD=STANDARD

=STANDARD

*

Y

TOP,BOTTOM

Y

0.115 MM 0.115 MM

0.210 MM 0.210 MM

90_OHM_DIFF

0.160 MM0.160 MM

0.109 MM0.109 MM

ISL3,ISL10

Y

80_OHM_DIFF

80_OHM_DIFF

0.160 MM0.160 MM

0.140 MM0.140 MM

TOP,BOTTOM

Y

80_OHM_DIFF

=STANDARD

*

Y

=STANDARD

=STANDARD =STANDARD

=STANDARD

*

=DEFAULT

=DEFAULT

=DEFAULT

Y

12.7 MM

=DEFAULT

STANDARD

*

DEFAULT

0.076 MM

30 MM

0 MM 0 MM

Y

0.100 MM

75_OHM_DIFF

=STANDARD

=STANDARD

=STANDARDY

*

=STANDARD =STANDARD

75_OHM_DIFF

0.160 MM0.160 MM

0.160 MM0.160 MM

TOP,BOTTOM

Y

0.300 MM

100_OHM_DIFF

Y

0.075 MM 0.075 MM

0.300 MM

ISL3,ISL10

0.091 MM

Y

100_OHM_DIFF

TOP,BOTTOM

0.091 MM

0.200 MM 0.200 MM

Y

75_OHM_DIFF

0.120 MM

0.140 MM0.140 MM

0.120 MM

ISL3,ISL10

=STANDARD=STANDARD =STANDARD

=STANDARDY =STANDARD*

27P4_OHM_SE

=STANDARD=STANDARD

*

=STANDARD

Y =STANDARD=STANDARD

40_OHM_SE

?

*

=STANDARDPP1V5_MEM

0.25 MM

2.5:1_SPACING

*

?

=STANDARD

GND

*

?

0.2 MM

1000

GND_P2MM

*

1000

PWR_P2MM

*

0.2 MM

?

=STANDARDNB_STATIC

*

1:1_SPACING

*

?

0.1 MM

1.5:1_SPACING

?

*

0.15 MM

0.18 MM

*

?

1.8:1_SPACING

0.2 MM

*

?

2:1_SPACING

2.28:1_SPACING

?

*

0.228 MM

0.3 MM

3:1_SPACING

*

?

4:1_SPACING

*

0.4 MM

?

STANDARD

*

=DEFAULT

?

DEFAULT

0.1 MM

?

*

SYNC_DATE=04/08/2010

SYNC_MASTER=K99_MLB

K99 RULE DEFINITIONS

109 OF 110

3.3.0

051-8467

73 OF 74

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICALDESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICALDESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTIONQTYPART NUMBER CRITICAL

TAIYO YUDEN

MURATA

TAIYO YUDEN

TAIYO YUDEN

MURATA

TAIYO YUDEN

MURATA

SAMSUNG

SAMSUNG

SAMSUNG

SAMSUNG

22UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS

10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS

2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

MURATA

1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SYNC_DATE=06/01/2010

SYNC_MASTER=K16_MLB

Acoustic Cap BOM Config Tables

138S0688

TY_CAP_22UF

CRITICAL
CRITICAL

138S0688

TY_CAP_22UF

138S0629

CAP, 1UF, 6.3V, 10%, 0402

SS_CAP_1UF

CRITICAL

C7203,C7980

2

138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL10SS_CAP_2_2UF

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

10

SS_CAP_2_2UF

C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919

CRITICAL
CRITICAL

138S0632

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929

10

CRITICAL

138S0632

12

CAP, 2.2UF, 6.3V, 20%, 0402

SS_CAP_2_2UF

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

9

C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310

138S0635

SS_CAP_10UF

8

CAP, 10UF, 6.3V, 20%, 0603

138S0635

CAP, 2.2UF, 6.3V, 20%, 0402

138S0632

10

CRITICAL

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

SS_CAP_2_2UF

10

SS_CAP_2_2UF

CRITICAL

C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516

138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

SS_CAP_10UF

C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647

CRITICAL

CAP, 10UF, 6.3V, 20%, 0603

138S0626

SS_CAP_10UF

CRITICAL

C1280

1

138S0626

138S0625

8

CAP, 10UF, 6.3V, 20%, 0603

MU_CAP_10UF

C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999

MU_CAP_10UF

138S0625

CAP, 10UF, 6.3V, 20%, 0603

8

CRITICAL

C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647

CAP, 10UF, 6.3V, 20%, 0603

138S0625

MU_CAP_10UF

CRITICAL

C1280

1

CRITICAL

138S0627

TY_CAP_10UF

CAP, 10UF, 6.3V, 20%, 0603

1

C1280

TY_CAP_10UF

CAP, 10UF, 6.3V, 20%, 0603

138S0627

8

C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647

CRITICAL

CAP, 10UF, 6.3V, 20%, 0603

138S0627

TY_CAP_10UF

8

C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999

SS_CAP_2_2UF

10

CRITICAL

C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641

CAP, 2.2UF, 6.3V, 20%, 0402

SS_CAP_2_2UF

138S0632

10

CAP, 2.2UF, 6.3V, 20%, 0402

C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616

CRITICAL

C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

SS_CAP_2_2UF

138S0632

8

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

SS_CAP_2_2UF

138S0632

CAP, 2.2UF, 6.3V, 20%, 0402

C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541

10

CRITICAL

10

CAP, 2.2UF, 6.3V, 20%, 0402

138S0632

SS_CAP_2_2UF

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939

CAP, 2.2UF, 6.3V, 20%, 0402

C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641

MU_CAP_2_2UF

CRITICAL

10

138S0633

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

138S0633

MU_CAP_2_2UF

9

C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

MU_CAP_2_2UF

C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616

138S0633

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

8

138S0633

MU_CAP_2_2UF

C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

10

C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541

MU_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

138S0633

CRITICAL

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516

138S0633

MU_CAP_2_2UF

CRITICAL

12

138S0633

MU_CAP_2_2UF

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296

MU_CAP_2_2UF

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

10

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929

MU_CAP_2_2UF

138S0633

10

CRITICAL

C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919

MU_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

10

138S0632

CRITICAL

SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

CRITICAL

138S0632

SS_CAP_2_2UF

8

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267

CAP, 2.2UF, 6.3V, 20%, 0402

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

MU_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

138S0633
138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

8

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267

CRITICAL

MU_CAP_2_2UF

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

MU_CAP_2_2UF

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

138S0633

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL10MU_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

138S0634

C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310

9

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641

TY_CAP_2_2UF

138S0634

10

CRITICAL

C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616

TY_CAP_2_2UF

10

CAP, 2.2UF, 6.3V, 20%, 0402

138S0634

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

TY_CAP_2_2UF

138S0634

8

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516

TY_CAP_2_2UF

10

138S0634

CRITICAL

C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541

TY_CAP_2_2UF

138S0634

10

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

TY_CAP_2_2UF

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296

12

138S0634

TY_CAP_2_2UF

CRITICAL

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939

10

138S0634

TY_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICAL

C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929

10

138S0634

138S0634

TY_CAP_2_2UF

CRITICAL

C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919

10

138S0634

TY_CAP_2_2UF

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

TY_CAP_2_2UF

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267

CRITICAL

138S0634

CAP, 2.2UF, 6.3V, 20%, 0402

8

138S0634

TY_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

138S0634

TY_CAP_2_2UF

C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

CAP, 2.2UF, 6.3V, 20%, 0402

10

CRITICAL

MU_CAP_22UF

CRITICAL

MU_CAP_22UF

138S0688

TY_CAP_22UF

CRITICAL

CAP, 1UF, 6.3V, 10%, 0402

CRITICAL

MU_CAP_1UF

138S0628

2

C7203,C7980

CRITICAL

TY_CAP_1UF

CAP, 1UF, 6.3V, 10%, 0402

138S0630

2

C7203,C7980

138S0632
138S0632

138S0626

CRITICAL

138S0676

CRITICAL

SS_CAP_22UF

138S0676

SS_CAP_22UF
SS_CAP_22UF

MU_CAP_22UF

138S0676

CRITICAL

CRITICAL

CAP, 22UF, 6.3V, 20%, 0603

CAP, 22UF, 6.3V, 20%, 0603

CAP, 22UF, 6.3V, 20%, 0603

C1210,C1214,C1217,C1218

C1223,C1226,C1227

C1230,C4902,C7360,C7361,C9480

C1210,C1214,C1217,C1218

C1223,C1226,C1227

CAP, 22UF, 6.3V, 20%, 0603

CAP, 22UF, 6.3V, 20%, 0603

CAP, 22UF, 6.3V, 20%, 0603

138S0635

C1230,C4902,C7360,C7361,C9480

CRITICAL

C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

TY_CAP_2_2UF

CRITICAL

CAP, 2.2UF, 6.3V, 20%, 0402

10

8

CAP, 10UF, 6.3V, 20%, 0603

CAP, 22UF, 6.3V, 20%, 0603

C1230,C4902,C7360,C7361,C9480

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

CAP, 2.2UF, 6.3V, 20%, 0402

CAP, 2.2UF, 6.3V, 20%, 0402

CAP, 2.2UF, 6.3V, 20%, 0402

CRITICALCRITICAL

C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999

CAP, 22UF, 6.3V, 20%, 0603

C1223,C1226,C1227

C1210,C1214,C1217,C1218

CAP, 22UF, 6.3V, 20%, 0603

4
3
5

4
3
5

4
3
5

110 OF 110

3.3.0

051-8467

74 OF 74