Apple A1342 Schematic

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

PROD OK2FAB 11/01/2009

Schematic / PCB #’s

K84 MLB SCHEMATIC

1 OF 77

0000813234

C

051-7982

C.0.0

1 OF 109

PRODUCTION RELEASED

2009-11-01

External USB Connectors

35

02/05/2009

46

K24_MLB

SATA Connectors

34

01/19/2009

45

K24_MLB

ETHERNET CONNECTOR

33

04/06/2009

39

K24_MLB

Ethernet & AirPort Support

32

04/06/2009

38

K24_MLB

Ethernet PHY (RTL8211CL)

31

04/06/2009

37

K24_MLB

X16 WIRELESS CONNECTOR

30

01/27/2009

34

K24_MLB

DDR3 Support

29

04/06/2009

33

K24_MLB

DDR3 SO-DIMM Connector B

28

02/05/2009

32

K24_MLB

DDR3 SO-DIMM Connector A

27

02/05/2009

31

K24_MLB

FSB/DDR3 Vref Margining

26

04/06/2009

29

K24_MLB

SB Misc

25

02/15/2009

28

K24_MLB

MCP Graphics Support

24

04/06/2009

26

K24_MLB

MCP Standard Decoupling

23

04/06/2009

25

K24_MLB

MCP Power & Ground

22

04/06/2009

22

K24_MLB

MCP HDA & MISC

21

03/24/2009

21

K24_MLB

MCP SATA & USB

20

04/06/2009

20

K24_MLB

MCP PCI & LPC

19

04/06/2009

19

K24_MLB

MCP Ethernet & Graphics

18

04/06/2009

18

K24_MLB

MCP PCIe Interfaces

17

04/06/2009

17

K24_MLB

MCP Memory Misc

16

04/06/2009

16

K24_MLB

MCP Memory Interface

15

04/06/2009

15

K24_MLB

MCP CPU Interface

14

04/06/2009

14

K24_MLB

eXtended Debug Port(MiniXDP)

13

02/25/2009

13

K24_MLB

CPU Decoupling

12

03/30/2009

12

K24_MLB

CPU Power & Ground

11

04/06/2009

11

K24_MLB

CPU FSB

10

04/06/2009

10

K24_MLB

SIGNAL ALIAS

9

02/04/2009

9

K24_MLB

Power Aliases

8

02/04/2009

8

K24_MLB

FUNC TEST

7

02/04/2009

7

K24_MLB

Revision History

6

01/19/2009

6

K24_MLB

Revision History

5

01/19/2009

5

K24_MLB

BOM Configuration

4

01/19/2009

4

K24_MLB

Power Block Diagram

3

System Block Diagram

2

01/19/2009

2

K24_MLB

70

CPU/FSB Constraints

100

K24_MLB

04/06/2009

69

LCD Backlight Support

98

K24_MLB

04/06/2009

68

LCD Backlight Driver (MC34845)

97

VEMURI_K19I

02/09/2009

67

DisplayPort Connector

94

K24_MLB

04/06/2009

66

DISPLAYPORT SUPPORT

93

K24_MLB

04/06/2009

65

LVDS CONNECTOR

90

K24_MLB

02/15/2009

64

POWER FETS

79

K24_MLB

02/15/2009

63

POWER SEQUENCING

78

K24_MLB

02/15/2009

62

MISC POWER SUPPLIES

77

K24_MLB

03/24/2009

61

CPU VTT(1.05V) SUPPLY

76

K24_MLB

02/04/2009

60

MCP CORE REGULATOR

75

K24_MLB

02/15/2009

59

IMVP6 CPU VCore Regulator

74

K24_MLB

03/03/2009

58

1.5V/0.75V DDR3 SUPPLY

73

57

5V/3.3V SUPPLY

72

56

PBUS Supply/Battery Charger

70

K24_MLB

02/05/2009

55

DC-In & Battery Connectors

69

K24_MLB

02/05/2009

54

AUDIO: JACK TRANSLATORS

68

AUDIO

06/09/2009

53

AUDIO: JACK

67

AUDIO

06/09/2009

52

AUDI0: SPEAKER AMP

66

AUDIO

06/09/2009

51

AUDIO: HEADPHONE FILTER

65

AUDIO

06/09/2009

50

AUDIO: LINE INPUT FILTER

63

AUDIO

06/09/2009

49

AUDIO: CODEC/REGULATOR

62

AUDIO

06/09/2009

48

SPI ROM

61

K24_MLB

02/15/2009

47

DEBUG SENSORS AND ADC

60

K19_IMLB

02/25/2009

46 SMS

59

K24_MLB

03/04/2009

45

WELLSPRING 2

58

K24_MLB

02/25/2009

44

WELLSPRING 1

57

K24_MLB

03/04/2009

43 Fan

56

K24_MLB

04/06/2009

42

Thermal Sensors

55

K24_MLB

02/04/2009

41

Current Sensing

54

K24_MLB

01/27/2009

40

VOLTAGE SENSING

53

K24_MLB

04/06/2009

39

K84 SMBUS CONNECTIONS

52

K24_MLB

01/19/2009

38

LPC+SPI Debug Connector

51

K24_MLB

02/15/2009

37

SMC Support

50

K24_MLB

02/04/2009

77

K84 RULE DEFINITIONS

109

01/19/2009

K24_MLB

76

K84 SPECIAL CONSTRAINTS

107

01/19/2009

K24_MLB

75

SMC Constraints

106

04/06/2009

K24_MLB

74

Ethernet Constraints

104

04/06/2009

K24_MLB

73

MCP Constraints 2

103

04/06/2009

K24_MLB

72

MCP Constraints 1

102

03/30/2009

K24_MLB

Page Sync

Date

(.csa)

Contents

PCB

CRITICAL

1

820-2567

PCBF,MLB,K84

CRITICAL

1

SCH

051-7982

SCHEM,MLB,K84

Contents

Page

Date

Sync

(.csa)

71

Memory Constraints

101

04/06/2009

K24_MLB

36 SMC

49

K24_MLB

04/02/2009

Contents

Page Sync

(.csa)

Date

Table of Contents

1

01/19/2009

1

K24_MLB

SCHEM,MLB,K84

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINI DISPLAY PORT

10/100/1000M E-NET

USB 2.0

PG 56-64

PG 55

PG 45

PG 27,28

PG 43

PG 42

PG 48

PG 46

PG 38

PG 36,37

PG 35

PG 65PG 45PG 30

PG 53

PG 52

PG 51

PG 49

PG 33

PG 31

PG 30

MINI PCI-E

AirPort

J3401

PG 17

J3900

GIGABIT

RTL8211CL

PG 18

PG 19 PG 21

MIC

LINE-IN/LINE OUT

Amp

U6700

HEADPHONE/LINE OUT

MUX

LINE-IN

Speaker

U6500

U6610,U6620,U6630

J6700,J6701,J6702,J6703,J6704

Conns

Audio

U6201

CIRRUS LOGIC CS4206

Codec

Audio

PG 21

SMB

TRACKPAD

A

BSAB,0

SUDDEN MOTION SENSOR

U5920

U5515,U5535

Boot ROM

CURRENT & VOLTAGE SENSORS

Ser

Port80,serial

PG 53,54,60

U4900

FAN CONN AND CONTROL

ADC

CPU & MCP THERMAL SENSORS

J6950,J6900

DC-DC POWER SUPPLIES

DC/BATT CONN

J5601

SPI

SMC

H8S/2117

MEMORY

MAIN

J3100,J3200

DIMM

U6100

PG 13

XDP CONN

U1300

B03

MCP79

PG 21

Misc

FSB INTERFACE

2 SODIMMS

DDR3 1067MHZ

PG 15,16

PG 14

64-Bit

FSB

1067 MHZ

CORE 2 DUO

INTEL CPU

2.26 GHZ

PG 10

PENRYN

SYNTH

NVIDIA

U3700

RGMII

HDMI OUT

DP OUT

LVDS OUT

UP TO 20 LANES3

PCI-E

DVI OUT

U1400

Bluetooth

760 1

CAMERA

HDA

RGB OUT

SATA

GPIOs

LPC Conn

Prt

Fan

J5100

SPI

TRACKPAD/

KEYBOARD

Conn

ODD

HD

U1000

Amps

E-NET

Conn

SATA

98

PCI

(UP TO FOUR PORTS)

SATA

CLK

CTRL

TMDS OUT

Conn

LVDS

CONN

J9000

J9400

PWR

LPC

PG 19

USB

Connectors

EXTERNAL

2 3

(UP TO 12 DEVICES)

PG 20

J3401

J5800

J4600,4610

J9000

54

SMC

MIKEYDIMMS

CONN

PG 18

PG 65

PG 67

PG 20PG 34

PG 34

J4501

J4500

051-7982

C.0.0

2 OF 109

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

System Block Diagram

SYNC_DATE=01/19/2009

SYNC_MASTER=K24_MLB

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

04-1

PM_WLAN_EN_L

NAND GATE

GATE

15

PM_SLP_S3_L

PCI_RESET0#

RC DELAY

=DDRREG_EN

=DDTVTT_EN

TPS51116

PM_SLP_S3_L

P1V8S0_EN

PPVIN_S5_1V5S30V75S0

MCPCORES0_EN

PPVIN_S3_5VS3/PPVIN_S5_3V3S5

PP3V42_G3H_REG

P3V3S0_EN

PPVIN_S0_CPUVTTS0

PPCPUVCORE_VTT_ISNS_R

PPCPUVTT_S0_REG

Q5315

02

CPUVTT

(1.05V)

P5VS3_EN_L

SMC

SMC_PM_G2_EN

PPVOUT_S0_LCDBKLT

PP3V42_G3H_REG

CPU_RESET#

Q7800

P60

04

SMC_PM_G2_EN

EN0

EN2

P3V3S5_EN_L

U9700

MC34845

VIN

IN

ADAPTER

PPVIN_S0_MCPCORE

(13A MAX CURRENT)

PPMCPCORE_S0_REG

PPMCPCORE_S0_R

R7525

(13A MAX CURRENT)

(10A MAX CURRENT)

PP5V_S3_REG

CURRENT)

P5V3V3_PGOOD

P1V05S0_LDO_PGOOD

P5V3V3_PGOOD

PLT_RST*

IMVP_VR_ON(P16)

ALL_SYS_PWRGD

09

PP3V3_S0_FET

PP3V3_S0_PWRCTL

MCPCORESO_PGOOD

CPUVTTS0_PGOOD

P3V3S0_EN

Q7930

PP5VLT_S0_FET

Q7948

U6200

VOUT

P5VS0_EN

PP5VRT_S0_FET

P5VS0_EN

Q7940

PP5V_S3_REG

EN

VIN

EN1

U7750

(Q3841,Q3840)

FETS

28

1.05V SO

PPVIN_S5_CPU_IMVP

K84 POWER SYSTEM ARCHITECTURE

PPVCORE_S0_CPU_REG

ISL9504BCRZ

PPBUS_G3H

CPUVTTS0_PGOOD

(7.2A MAX CURRENT)

ENABLE

3.425V G3HOT LT3470

U6990

23

PPCPUVCORE_VTT_ISNS

0.01 OHM

VOUT

PBUS_VSENSE

02

EN_PSV

PP18V5_DCIN_CONN

SMC RESET "BUTTON"

NCP303LSN

U5000

VOUT

U7000

SLP_S5_L(P95)

LTC2909

PPVBAT_G3H_CHGR_OUT

02

PM_RSMRST_L

J6950

(9 TO 12.6V)

6A FUSE

PPVBAT_G3H_CHGR_REG

BATT_POS_F

PM_SLP_S4_L

F6905

TPS51117

U7600

PP1V05_ENET_FET

VR_ON

(44A MAX CURRENT)

1.05V (S5)

P3V3S3_EN

Q7910

P1V05ENET_EN

P1V05_S5_EN

3.3V

06

VOUT

08

VR_PWRGOOD_DELAY

PP1V05_S5_REG

PGOOD

U7400

01

U4900

Q7050

V

(S0)

PGOOD

05

VIN

VOUT1

VOUT2

Q3810

RC DELAY

VOUT

VOUT1

(RT)

DDRREG_EN

D6905

PP3V3_S5_REG

MCP79

V2

(S5)

AC

99ms DLY

PM_PWRBTN_L

SMC_RESET_L

IMVP_VR_ON

PWRGD(P12)

7A FUSE

CPU_PWRGD

VIN

P3V3_ENET_FET

MCPCORES0_EN

PBUSVSENS_EN

(S0)

RC

DELAY

V3

CHGR_BGATE

FETS

S3 TO S0

PWRBTN*

01

D6905

02

26

06

3S2P

11

11-1

RC DELAY

11-3

15

16-2

16-1

02

21

20

18

24

10

03

17

06-1

02

25

SMC

25

SLP_S4_L(P94)

PP1V8_S0_REG

P3V3ENET_EN_L

IMVP_VR_ON

RSMRST_PWRGD

U4900

SLP_S3_L(P93)

S0PGOOD_PWROK

19-1

PP3V3_S0

PP1V05_S0

RSMRST_IN(P13)

RSMRST_OUT(P15)

U7760

CHGR_EN

02

DELAY

F7000

14

S5

MCP79

MCPDDR_EN

CPUVTTS0_EN

1.8V LDO

PP1V5_S0

V1

RST*

MCP_CORE

S3

DCIN(16.5V)

U7870

SLP_S5_L

SMC_ONOFF_L

PWR_BUTTON(P90)

RST*

P17(BTN_OUT)

PP1V5_S3_REG

(Q7901 & Q7971)

PP0V75_S0_REG

P3V3S3_EN

15-1

11-2

0.75V

5V

PP1V5_S0_FET

(1A MAX CURRENT)

30

PLTRST*

EN

VIN

PPVIN_G3H_P3V42G3H

32

RESET*

CPU

U1000

U1400

29

07

13

PS_PWRGD

LPC_RESET_L

31

FSB_CPURST_L

CPUPWRGD(GPIO49)

PP3V3_S3_FET

04

CPU VCORE

VIN

VOUT

V

PP3V3_S5

MCP_PS_PWRGD

SMC_CPU_VSENSE

R5492

U2850

VOUT

VIN

VREG3

VOUT2

PGOOD1,2

PP1V5_S0

P16

(S5)

05

SLP_S4_L

CPUVTTS0_EN

PWRGOOD

22

RSMRST*

4.5V AUDIO

PP4V5_AUDIO_ANALOG

PP5V_S3

(4A MAX

TPS51125

U7200

TPS62202

SLP_S3_L

1.5V

U7300

ISL6263D

U7500

VOUT

EN

ISL8009B

TPS71745

SLP_S3#

PPBUS_S0_LCDBKLT_PWR

DELAY

RC

DELAY

16-3

16-4

16-6

16-5

16-1

P5VS0_EN

U1400

VIN

BATTERY CHARGER

PBUS SUPPLY/

ENABLES

ISL6258AHRTZ

P5VS3_EN_L

SMC_ADAPTER_EN

AP_PWR_EN

16

OR

Q3801,Q3805

3 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

Power Block Diagram

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

514-0705 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0689 PART FOR USB CONNECTORS

514-0718 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0694 PART FOR AUDIO CONNECTOR

514-0706 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0691 PART FOR MINI DP CONNECTOR

Module Parts

353S2718 IS NEW INTERSIL PART FOR FIXING B4 DONGLE ISSUE

BOM Groups

DEVELOPMENT BOM

Programmable Parts

3

Top

SIGNAL

BOTTOM

SIGNAL(High Speed) SIGNAL(High Speed)

Bar Code Labels / EEE #’s

K84 BOARD STACK-UP

8 9

2

4 5 6 7

GROUND

SIGNAL

10

POWER

11

GROUND

POWER

GROUND

SIGNAL(High Speed)

514-0704 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0692 PART FOR RJ45 CONNECTOR

LOCKED BOOTROM APN IS 341S2488

Alternate Parts

BOM Variants

4 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PCBA,MLB,FOX DDR CONN,K84

639-0035

K84_COMMON,CPU_2_0GHZ,FOX_DDR_CONN,EEE_8CG

PCBA,MLB,MLX DDR CONN,K84

K84_COMMON,CPU_2_0GHZ,MLX_DDR_CONN,EEE_A36

639-0254

K84 MLB DEVELOPMENT BOM

K84_DEVEL_ENG

085-0748

PCBA,MLB,FOX DDR CONN,PVT K84

639-0554

K84_COMMON_PVT,CPU_2_0GHZ,FOX_DDR_CONN,EEE_CXR

639-0555

PCBA,MLB,MLX DDR CONN,PVT K84

K84_COMMON_PVT,CPU_2_0GHZ,MLX_DDR_CONN,EEE_CY1

K84_COMMON

COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_ENG,K84_PROGPARTS

K84_DEVEL_PVT

XDP_CONN,LPCPLUS

CRITICAL

U1000

1

CPU_2_0GHZ

337S3769

PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7550

SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

K84_DEBUG_PROD

K84_DEVEL_ENG

DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN

K84_DEBUG_PVT

DEVEL_BOM_PVT,SMC_DEBUG_YES,XDP,NO_VREFMRGN

K84_DEBUG_ENG

DEVEL_BOM,SMC_DEBUG_YES,XDP

K84_PROGPARTS

BOOTROM_PROG,SMC_PROG,WELLSPRING_PROG

ONEWIRE_PU,DP_ESD,MIKEY,LDO_NO,MEM_SENSE,1P05_HIGH_SIDE_SENSE,MCP_T_DIODE_SENSOR,MCPSMC_DIGITEMP_YES

K84_MISC

K84_MCP

MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC

COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_PROD,K84_PROGPARTS

K84_COMMON_PVT

SYNC_DATE=01/19/2009

SYNC_MASTER=K24_MLB

BOM Configuration

K84 MLB DEVELOPMENT PVT

K84_DEVEL_PVT

085-1076

FOX_DDR_CONN

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA

J3200

CRITICAL516S0706

1

CONN,204P,SODIMM,P=0.6MM

FOX_DDR_CONN

J3100

1

CRITICAL516-0201

CONN,RCPT,RJ45,PLASTIC,HF,K83/K84

CRITICAL

J3900

1

514-0704

1

514-0706

CONN,RCPT,MDP,20P,PLASTIC,HF,K83/K84

J9400

CRITICAL

R6612,R6617,R6630,R6633

4

RES,MF,1/4W,6.8OHM,5%,0805,SMD

104S0033 CRITICAL

ZS0912,ZS0913,ZS0914,ZS0915,ZS0919

CRITICAL

5

POGO PIN,TALL,NOISE-IMPROVED,K84

870-1886

ZS0908,ZS0909,ZS0911

CRITICAL

POGO PIN,MED,NOISE-IMPROVED,K84

3

870-1885

CRITICAL

1

514-0718

J6700

CONN,RCPT,S/PDIF,TX,HF,CFR,K83/K84

CRITICAL

SCREW1,SCREW2,SCREW3,SCREW4

4

452-1708

SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97

CONN,204P,SODIMM,P=0.6MM,HF

J3100

MLX_DDR_CONN

1

CRITICAL516-0213

138S0602138S0603

ALL

MURATA AS ALTERNATE

128S0218128S0093

KEMET AS ALTERNATE

ALL

152S0516

ALL

MAGLAYERS AS ALTERNATE

152S0874

341S2485

1

SMC_PROGCRITICAL

U4900

IC,SMC,K84

338S0563

U4900

CRITICAL

1

SMC_BLANK

IC,SMC,HS8/2117,9X9MM,TLP,HF

CRITICAL

1

085-1076

K84 MLB DEVELOPMENT PVT

DEVEL_PVT

DEVEL_BOM_PVT

CRITICAL

U6100

1

BOOTROM_PROG

341S2487

IC,PRGRM,EFI BOOTROM,UNLOCK,K84

IC,WELLSPRING CONTROLLER,K84

U5701

WELLSPRING_PROG

341S2491 CRITICAL

1

CRITICAL

1

WELLSPRING_BLANK

U5701

337S2983

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

K84 MLB DEVELOPMENT BOM

DEVEL

085-0748

DEVEL_BOM

CRITICAL

1

5

POGO PIN,TALL,NOISE-IMPROVED,K84

870-1886

ZS0904,ZS0905,ZS0906,ZS0907,ZS0910

CRITICAL

POGO PIN,MED,NOISE-IMPROVED,K84

870-1885

ZS0900,ZS0901,ZS0902,ZS0903

4

CRITICAL

1

U7870

IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8

353S2718

CRITICAL

2

514-0705

J4600,J4610

CONN,RCPT,USB,4P,PLASTIC,HF,K83/K84

CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC

CRITICAL

J3200

MLX_DDR_CONN

1

516S0790

152S0778152S0693

DALE/VISHAY, MAGLAYERS AS ALTERNATE

ALL

152S0586

MAGLAYERS AS ALTERNATE

ALL

152S0847

EEE_CY1

[EEE:CY1]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEE_CXR

[EEE:CXR]

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

[EEE:A36]

EEE_A36

157S0055157S0058

ALL

DELTA AS ALTERNATE

152S0685

ALL

CYNTEC AS ALTERNATE

152S0796

826-4393

EEE_8CG

[EEE:8CG]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL

BOOTROM_BLANK

U6100

1

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

335S0610

IC,GMCP,MCP79,35X35MM,BGA1437,B03

CRITICAL

1

MCP_B03

U1400

338S0710

3

CRITICAL

POGO PIN,THIN,NOISE-IMPROVED,K84

870-1887

ZS0917,ZS0918,ZS0916

DALE/VISHAY AS ALTERNATE

ALL

104S0023104S0018

518S0774

1

CONN,RCPT,60P,P=0.4,STK HT 1.0

XDP_CONN

J1300

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

4/2/2009: RELEASE 9.2.0 (MAJOR):

- PAGE 97:DISCONNECTED PINS 2 AND 5 FROM GND PINS(13,19,21)AND CONNECTED SEPARATELY TO

- PAGE 97: RENAMED SINGLE PIN NET GND_LCDBKLT TO GND_LCDBKLT_PGND

- PAGE 49: FIXED PLACEMENT NOTE ASSOCIATED WITH C4907 (SHOULD BE: PLACE NEAR PIN E1)

- PAGE 7: SCRUBBED TPS AS PER UPDATE FROM TOM

- PAGE 4: CHANGED MCP P/N TO 338S0702 AS PER CHALLEE

- PAGE 90: ADDED C9017 (1000PF) CAP AS PER JOHN SCHEN

GND_LCDBKLT_PGND AND ASSIGNED MIN_LINE/NECK_WIDTH ATTRIBUTES

- PAGE 97: REPLACED D9710 WITH 40V PART- APN 371S0580 AS PER DEREK

- PAGE 97: STUFFED R9726 AND SWAPPED C9705 AND R9705 AS PER FREESCALE FOR COMPENSATION.

- ADDED BOMOPTION = NOSTUFF ATTRIBUTE TO R6725

C6871, U6870, C6872, R6872, & R6873

- PAGE 74: CHANGE L7400 AND L7401 TO 152S1019 AS PER DAYU FOR COST SAVING. ALSO, UPDATED ASSOCIATED TEXTS

- PAGE 94: REPLACED C9486 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY)

- PAGE 74: REMOVED C7400, C7402, R7451 AND R7452 AS PER DAYU

- PAGE 70: REPLACED R7080 WITH APN 107S0142 WHICH IS TRUE 4-TERMINAL SENSE RESISTOR WITH SMALLER PACKAGE

3. PAGES 31, 32: REPLACED 0.1UF 0204 TYPE DDR3 DECOUPLING CAPS WITH 0402 TYPE CAPS ( APPLE P/N : 132S1059)

- UPDATED THE SCHEMATICS, PCBF AND PCBA PART NUMBER INFO

- DELETED IR SPECIFIC NETS ON SATA CONNECTOR

- CORRECTD BOM CONFIG TABLES

1/23/2009: RELEASE 0.0.5-

1. PAGE 75: MCP VCORE INDUCTOR CHECK FOR PD: CHANGED L7560 TO 152S0966 AND THEN TO 152S0867. BUT NOW IT IS BACK TO 13A PART FOR NOW

15: PAGE 97: REPLACED BKLT DRIVER CKT WITH THAT OF FREESCALE PART, SIMILAR TO K19I

- PAGE 9: DELETED R0950 PCIE_FW_PRSNT_L ’S PD RESISTOR

- PAGE 54: REMOVED BMON CURRENT SENSE CIRCUIT

- UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_PROD AND BLANK PROGRAMMED PARTS. ALSO, DELETED BMON_ENG BOM OPTION

- DELETED KB BACKLIGHT DRIVER/DETECTION CKT

AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_NO WITH THESE 0 OHMS

- PAGE 50: ADDED UNUSED NET ALIAS FOR SMC_BIL_BUTTON_L (NC_SMC_BIL_BUTTON_L)

- PAGE 70: ADDED TP TO PIN 13

- REMOVED BOMOPTION = NOSTUFF ATTRIBUTE FROM R6724

- PAGE 39: REPLACED ETHERNET CONNECTOR WITH THAT OF M97A/K24 PART APN 514-0636 (SYNC’ED WITH K24)

- PAGE 60: CORRECTED PLACEMENT NOTE ASSOCIATED TO XW6080 TO REFLECT D9710 INSTEAD OF D9701

- PAGE 57: ADDED PLACEMENT NOTES TO C5702 AND C5704 AS PER JOHN SCHEN’S FEEDBACK SEL1 SIGNAL AND REMOVED 10K PD ON ST PIN. REPLACED C5926 WITH 0.01UF CAP AS PER DATA SHEET. AND,

- PAGE 4: ADDED 138S0603 AS ALT FOR 138S0602B FOR SUPPLY REDUNDANCY

- PAGE 76: REPLACED L7620 WITH ITS REPLACEMENT - APN 152S0518

- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 & C7240 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS

- PAGE 9: CHANGED ALIAS OF FW_PME_L TO TP_FW_PME_L

USB_IR_N/P

- PAGE 31 & 32: PIN SWAPS ON THE DDR3 CONNECTOR PAGES FOR ROUTING PURPOSES (REFER TO RON’S EMAIL)

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.0.0***

- PAGE 73: ADDED SHORT XW7304 FROM PIN 1 OF C7300 TO POWER GND (PIN 18)

- ADDED PLACEMENT NOTES TO XW SHORTS AS PER DAYU

13. PAGE 69: REPLACED BATTERY CONNECTER WITH PN 518S0540 AND BIL CONNECTOR WITH PN 518S0588. UPDATED CONNECTIONS ACCORDINGLY

6. PAGE 45: REPLACED SATA HDD CONNECTOR WITH APPLE PN 516S0350 AND UPDATED CONNECTIONS ACCORDINGLY

- NO CHANGES SINCE LAST MINOR RELEASE 0.0.2

- PAGE 70: DELETED R7050 CONNECTION BETWEEN CHGR_AGATE AND CHGR_LOWCURRENT_GATE

-PG. 67, NO STUFFED R6724

-PG. 67, DELETED L6706

-PG. 67 ADDED =PP3V3_S3_AUDIO NET

(MATCHES UPDATED ALIASES ON PAGE 8)

- PAGE 9: ADDED OMIT ATTRIBUTE TO THE LVDS HOLE

- PAGE 8: ADDED =PP5V_S3_P5VRTS0FET ALIAS, GOING TO 5V RT S0 FET CIRCUIT

- DELETED PAGES 41,42,43,48,97,98,105 [FIREWIRE, IR CONTROLLER, BACKLIGHT CKT]

INITIAL RELEASE 0.0.1-

- SET SOURCE SYNC OF AUDIO PAGES (62-63, 65-68) FROM LENG’S AUDIO PAGES

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

- PAGE 97: ADDED BOM OPTION - NOSTUFF- TO R9702 AS PER K19I

2/26/2009: RELEASE 4.0.0 (RFA RELEASE):

- PAGE 78: DELETING P5VLTS3_EN RC CIRCUIT AS IT IS NO LONGER NEEDED (SEE ABOVE). ALSO UPDATED

- NAME CHANGED TO TMLB. SO CALLING IT RELEASE 0.0.1

- PAGE 51: R5156, R5157 AND R5158 ARE NOW 0 OHM ISOLATION RESISTORS PLACED ON SPI BUS NEXT TO THE LOCATION WHERE

- PAGE 34: R3453 IS MODIFIED TO 110K RESISTOR, R3454 IS NOSTUFF AND R3453 IS PULLED UP TO PP3V3_WLAN_F.

- PAGE 9: ADDED UNUSED FIREWIRE LANE NETS AS TEST POINTS

- PAGE 4: UPDATED EEE NUMBER - 8CG

- PAGE 9: ADDED SMC_SYS_KBDLED TP ALIAS

- PAGE 8: DIVIDED PP5V_S3_REG INTO TWO BRANCHES - PP5VRT_S3_REG & PP5VLT_S3_REG

- PAGE 8: ADDED PP5V_S3_DEBUG_ADC_AVDD/DVDD & PP5V_S3_DEBUG_ISNS ALIASES FOR NEW SENSOR PAGE 60

- PAGE 28: REMOVED RTC POWER SOURCES CIRCUIT AND SUPERCAP_NO BOM OPTION FROM R2820

- PAGE 34: SINCE X16 AIRPORT CARD SOLUTION IS BEING USED, PP5V_S3_WLAN IS REPLACED BY PP3V3_S3_WLAN

- PAGE 34: DISCONNECTED PP5V_S3_BTCAMERA_F POWER RAIL FROM THE CONNECTOR AND REPLACED IT WITH PP3V3_S3_BT ALONG WITH THE USB CAMERA SIGNALS TO LVDS PAGE. ALSO, RENAMED THIS POWER RAIL TO PP5V_S3_CAMERA ON LVDS

- PAGE 34: REPLACED L3404 WLAN INDUCTOR WITH LOW DCR 0603 PART - APN 155S0367

- PAGE 45: CHANGED SATA HDD CONNECTOR TO APN 516S0616

- PAGE 45: ADDED SENSE RESISTORS R4598 AND R4599 ON 5V ODD AND 5V HDD RAILS RESPECTIVELY

- PAGE 39: REPLACED ETHERNET CONNECTOR WITH APN 514-0668 (SIMILAR TO K36B)

- PAGE 34: ADDED SENSE RESISTOR R3452 ON PP3V3_WLAN SIGNAL

(SIMILAR TO M96). CAMERA SIGNALS ARE ROUTED VIA LVDS CONNECTOR. MOVED PP5V_S3_BTCAMERA POWER CIRCUIT

THIS IS TO ENSURE 3.3V LEVEL AT THE INPUT OF U3402 AND MAINTAIN 100MS DELAY SPEC BETWEEN 3.3V POWER

(GOING TO Q3450). ALSO, REPLACED PP5V_WLAN WITH PP3V3_WLAN ON PAGE 6 (FUNCTIONAL TEST POINTS)

- PAGE 8: ADDED ALIAS PP5VLT_S3_V5IN UNDER PP5VRT_S3_REG

- PAGE 8: ADDED ALIAS PPVIN_S3_5VLTS3 UNDER PPBUSB

- PAGE 50: UNSTUFFED R5055 AND USED SMC_NB_MISC_ISENSE SIGNAL PORT (SMC) FOR CONNECTING PPBUSA ISENSE SIGNAL.

- PAGE 51: REPLACED TWO DEMUX SOLUTION WITH A SINGLE DEMUX 1X2 SOLUTION. APN USED - 353S2220

- PAGE 52: ADDED SENSOR ADC CONNECTION BLOCK UNDER ’SMC 0 SMBUS CONNECTIONS’ SECTION

- PAGE 70: ADDED BYPASS 0 OHM RESISTOR R7050 (NOSTUFF FOR NOW) OPTION FOR NEW CHIP WHICH WON’T REQUIRE U7060 SOLUTION

- PAGE 4: REMOVED 104S0018 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE

- PAGE 8: RENAMED PPVIN_S5_1V5S3_0V75S0 TO PPVIN_S5_1V5S30V75S0

- PAGE 8: DELETED PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_BKL_VDDIO, PP3V3_S0_MCP_PLL_VLDO

- PAGE 78: ADDED P5V_LTS3_PGOOD POWER GOOD SIGNAL (WIRED AND WITH OTHER S0 RAILS PGOOD) CORRESPONDING TO 5V LT

IT BRANCHES INTO TWO - ONE GOING TO MLB SPI ROM AND THE OTHER GOING TO LPC CONNECTOR. THESE RESISTORS ARE

- PAGE 4: REMOVED 152S0778 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE SINCE L7260 AS HAS BEEN REPLACED WITH THIS PART

- PAGE 54: MOVED PBUS INA210 CIRCUIT TO THIS CURRENT SENSOR PAGE. RENAMED REF DES AS PER THIS PAGE 54

- PAGE 55: DELETED J5590 CONNECTOR (CONNECTED TO HEAT-PIPE TEMPERATURE DETECTION RAILS)

- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 WITH 68UF OSCON CAP (APN 128S0275) & C7240 WITH 39UF (APN 128S0248)

- PAGE 55: REPLACED U5515 & U5535 WITH CHEAPER APN 353S2571

- PAGE 78: RENAMED P5VS3_EN_L TO P5VRTS3_EN_L (RT POWER SUPPLY ENABLE) AND ADDED R7814, C7814 S3 ENABLE CIRCUIT

- PAGE 75: CHANGED C7571 & C7560 TO 68UF OSCON CAPS (APN 128S0275)

- PAGE 77: REMOVED 1.05V S0 PLL LDO CIRCUIT. AND, REMOVED LDO_NO BOM OPTION FROM R7745

- PAGE 72: REPLACE Q7220 WITH SIZ700DT AND L7260 WITH SMALLER 10A PART (APN 152S0778)

- PAGE 71: CHANGED C7160 TO 39UF OSCON CAP (APN 128S0248)

- PAGE 69: REPLACED BATTERY CONNECTOR J6950 WITH APN 518S0540 (M96) CONNECTOR

- PAGE 69: ADDED D6951 ESD DIODE ON BIL SMBUS SIGNALS (NOSTUFF FOR NOW)

- PAGE 61: RENAMED SPI SIGNALS TO MATCH WITH CHANGES ON PAGE 51

PLACED ON THE LPC CONNECTOR BRANCH. THIS IS TO AVOID STUBS IN PRODUCTION

TO THE CARD GETTING STABLE AND AIRPORT GETTING OUT OF RESET

2. ADAPT JACK INSERT DETECT CIRCUIT TO CD3282 JACK INSERT DETECT FUNCTION.

5. PAGE 34: REPLACED SCHMITT’S TRIGGER WITH PN 311S0449

- PAGE 73: ADDED SENSE RESISTOR R7350 ON 1.5V DDR3 SUPPLY RAIL

- PAGE 69: ADDED BOM OPTION NOSTUFF TO D6950 FOR NOW

8. PAGE 46: REPLACED ESD DIODES WITH CHEAPER PN 377S0066

7. PAGE 45: ADDED 2 PIN CONNECTOR (APPLE PN 518S0519) FOR SIL

- PAGE 60: REMOVED WELLSPRING 3 PAGE (GOING BACK TO K24 SOLUTION) AND REPLACED IT WITH K19I DEBUG SENSOR PAGE (SCHUTIL SYNC)

- PAGE 73: UPDATED 1.5V/0.75V POWER SUPPLY WITH CORRECT NET NAMES REFLECTING 1.5V/0.75V INSTEAD OF 1.8V/0.9V AND

- PAGE 8: ADDED PP3V3_S3_BT ALIAS FOR BLUETOOTH ON RIGHT CLUTCH CONNECTOR PAGE

5V S3 IS DIVIDED INTO RT AND LT POWER SUPPLY AND WILL HAVE CORRESPONDING S0 FETS)

- PAGE 8: DIVIDED PP5V_S0_FET INTO TWO BRANCHES - PP5VRT_S0_FET & PP5VLT_S0_FET (FOR ROUTING PURPOSE,

- PAGE 4: CORRECTED APN FOR PROGRAMMED PARTS - SMC, BOOT ROM, WELLSPRING

- PAGE 4: REMOVED SUPERCAP_NO BOM OPTION. ADDED DEBUG_ADC BOM OPTION UNDER K84_DEVEL_ENG

***PAGES SYNC’ED FROM K24 SINCE LAST RELEASE 1.0.0***

3. REMOVED JACK EXTRACT CIRCUITRY, FUNCTION IS TAKEN OVER BY CD3282

- PAGE 34: ADDED CHOKES ON PCIE TX/RX SIGNALS. UPDATED PAGE 6 (FUNCTIONAL TEST POINTS) ACCORDINGLY

- PAGE 71: ADDED NEW PAGE FOR PP5V_LT_REG POWER SUPPLY. UPDATED ALL THE REF DES AS PER THE PAGE NUMBER

- PAGE 60: UPDATED WLAN DIVIDER CIRCUIT WITH 3V3 POWER RAIL INSTEAD OF 5V

[ONLY CHIP SELECT IS BEING DEMUXED]

ADDED ALIAS ON THIS PAGE

PAGE

- PAGE 76: REPLACE Q7620 WITH SIZ700DT

1. REPLACED MIKEY CD3272 WITH CD3282

(THIS IS FOR NEW SENSOR PAGE 60)

- PAGE 4: REMOVED LDO_YES BOM OPTION

4. REMOVE FM ANTENNA NET.

2. ADDED DIDT TO ALL THE GATE AND PHASE NETS

- ADDED DIDT ATTRIBUTE

- PAGE 28: DELETED FW_RESET_L SIGNAL

- PAGE 58: DELETED KB BKLT CIRCUIT

IN SYNC WITH PAGE 8 ALIASES

- PG 50: SWAPPED THE PART NUMBER AND THE ALTERNATE PART NUMBER FOR VR5020. MADE ISL60002 THE ALTERNATE PART

***PAGES SYNCED FROM K24 SINCE LAST RELEASE 2.0.0***

- CHANGED SPEAKER AMPS TO LM48310, PLACEHOLDERS FOR LM48311. LM48311 IS THE CSP VERSION OF THE LM48310.

***PAGES SYNCED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 2.0.0***

- REMOVED OPTIONAL STUFFING RESISTORS AROUND THE RE-TASKING JACK ANALOG SWITCH.

- CHANGED LDO TO B LP5900.

- PAGE 75: CHANGED R7525 TO 107S0132 FOR COST SAVING AS PER DAYU

- PAGE 74: CHANGED Q7401 AND Q7403 TO 376S0771 AS PER DAYU

- PAGE 74: CHANGED Q7400 AND Q7402 TO 376S0772 AS PER DAYU

- PAGE 74: REMOVED UNUSED NETWORK ON U7400 PIN 5 AND PIN 6 AS PER DAYU [R7406, C7410, R7427, R7426]

- PAGE 73: MOVED THE SENSE RESISTOR NEXT TO INDUCTOR

- PAGE 73: ADDED ONE MORE OSCON 39UF CAP ON INPUT SIDE

- PAGE 72: L7220 CHANGED TO 152S0778 FOR COST SAVING AS PER DAYU

- PAGE 71: DISCONNECTING EN_PSV (PIN 34) FROM P5VLTS3_EN SIGNAL AND CONNECTING IT TO

- PAGE 70: CHANGED Q7000 AND Q7001 CHEAPER TO 376S0667 (HAT1128) AS PER DAYU’S RECOMMENDATION

- PAGE 70: CHANGED Q7050 TO 376S0761 AS PER DAYU & K24 DESIGN

- PAGE 69: DELETED NOTE REGARDING INDUCTOR FILTER REQUIREMENT ON BATT_POS_F (AS PER JOHN SCHEN)

- PAGE 69: REPLACED BATTERY CONNECTOR WITH THAT OF K24 (APN 518-0359)

- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH THAT OF K24 (APN 518S0637) - SYNC’ED FROM K24

- PAGE 34: ADDED A TEXT NOTE THAT J3401 (AIRPORT CONNECTOR) COULD CHANGE TO 1.8MM HEIGHT APN 516S0582

- PAGE 90: REFRESHED THE SYMBOL OF U9000, PART NUMBER CHANGED TO 353S2603

- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH APN 518S0738

POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET

- PAGE 34: ADDED NOTE WITH REGARD TO 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN

- PAGE 34: ADDED NOTE WITH REGARD TO SMBUS CONNECTIONS TO THE AIRPORT CONNECTOR

- PAGE 13: REPLACED XDP CONNECTOR WITH MINI XDP CONNECTOR APN 516S0625

- PAGE 8: ADDED BACK - PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_MCP_PLL_VLDO

- PAGE 8: RENAMED PP1V05_S0_MCP_PLL_UF BACK TO PP1V05_S0_MCP_PLL_UF_R

- PAGE 74: STUFF R7413 AS PER DAYU

PP5VLT_S3_V5IN (5VRT PS)

- PAGE 4: ADDED LDO_NO BOM OPTION

- PAGE 54: REMOVED NOTE ON AMON AND BMON

- PAGE 77: ADDED BACK - 1.05 PLL LDO CIRCUIT

1/21/2009: RELEASE 0.0.4-

2/6/2009: MAJOR RELEASE 0.1.0 -

2/6/2009: WEEKLY RFA BOM RELEASE 1.0.0-

2/15/2009: RELEASE 2.0.0 (WEEKLY RFA)-

2/25/09: WEEKLY RFA RELEASE (3.0.0)

3/4/2009: RELEASE 5.0.0 (RFA)-

ASSOCIATED TEXT NOTE

- PAGE 97: FIXED CONNECTION POINT (DOT) FOR LCDBKLT_VIN

- PAGE 97: ADDED 0 OHMS SERIES RESISTOR ON LCD_BKLT_PWM FOR DEBUGGING PURPOSES

- PAGE 97: RENAMED LCD_BKLT_PWM TO LVDS_IG_BKL_PWM

- PAGE 97: CHANGED VOVP VALUE TO 6.9V AS PER FREESCALE FEEDBACK

- PAGE 97: ADDED R9726 (22K) AND SWAPPED C9705 AND R9705 LOCATIONS FOR NOISE REDUCTION

- PAGE 97: DELETED C9712 AS IT IS REDUNDANT

- PAGE 97: ADDED PLACEMENT NOTE ATTRIBUTE TO C9713 AND C9710 FOR PLACING THOSE NEAR L9710

- PAGE 78: ADDED 0 OHM ISOLATION RESISTORS ON POWER GOOD SIGNALS (BEFORE WIRED AND)

- PAGE 8: DELETED PP5V_S0_BKL, RENAMED PP1V05_S0_MCP_PLL_UF_R TO PP1V05_S0_MCP_PLL_UF

- PAGE 90: UPDATED LVDS CONNECTOR CONNECTIONS AS PER STEVE’S RECOMMENDATION. ADDED CAMERA SIGNALS

- PAGE 79: ADDED 5V LT S0 FET AND UPDATED NET NAMES FOR BOTH RT AND LT S0 FET CIRCUITS ACCORDINGLY

POWER SUPPLY

FOR GENERATING P5VLTS3_EN ENABLE SIGNAL FOR LT POWER SUPPLY

AS PER FREESCALE RECOMMENDATION

***PAGES SYNC’ED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 1.0.0***

17. PAGE 4: REMOVED BKLT_ENG BOM OPTION

16. PAGE 69: MOVED THE DECAP C6908 TO CORRECT PART U6901.5 ( SIMILAR TO K24)

- PAGE 45: CHANGED J4501 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

- PAGE 50: DELETED SMC_PPBUSA_ISENSE ALIAS AND STUFFED R5055

- PAGE 54: DELETED U5470 INA210 CIRCUIT AS THERE IS NO NEED

R7051 (6259_YES) CONNECTION BETWEEN CHGR_PIN26 AND CHGR_LOWCURRENT_GATE;

R7054 (6259_NO) CONNECTION BETWEEN CHGR_PIN6 AND GND_CHGR_SGND

- PAGE 73: RENAMED TEXT NOTE FOR =PP1V5_S3_REG NET TO VOLTAGE=1.5V

- PAGE 45: MIRROR’ED J4500 AND RECONNECTED PINS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

R7052 (6259_NO) CONNECTION BETWEEN CHGR_PIN26 AND GND_CHGR_SGND; R7053 (6259_YES) CONNECTION BETWEEN CHGR_PIN6 AND PIN 12 (VHST);

TO HAVE TWO PPBUS BRANCHES

- PAGE 97: STUFF R9716 AS PER KIRAN’S FEEDBACK

-PG. 68, ADDED R6873

-PG. 67, DELETED R6726

3/20/2009: RELEASE 7.1.0 (MAJOR)-

- PAGE 9: ADDED LVDS HOLE APN 998-1521

- PAGE 70: AS PER DAYU, ADDED:

- PAGE 4: CHANGE THE CPU TO NEW APNB 337S3704

3/24/2009: RELEASE 7.2.0 (MAJOR)-

AS PER DAYU

- PAGE 7: RENAMED PP5VRT_S3 TO PP5V_S3 ["LT" & "RT" NOMENCLATURE CLEAN-UP]

- DELETED PAGE 71 (5V S3 LT POWER SUPPLY) AS THERE IS NO NEED OF A SEPARATE 5V S3/S0 SUPPLY

- PAGE 8: COMBINED 5V S3 LT AND RT ALIASES INTO ONE =PP5V_S3_REG AND RENAMED NETS

- PAGE 21: UNSTUFFED R2143 PU ON MCP_GPIO_4 AS THERE IS ALREADY A 100K PU ON AUDIO PAGE

- PAGE 55: ADDED BC846BM NPN TRANSISTOR (APN 372S0129) TO MCP T-DIODE SENSOR CIRCUIT SIMILAR TO

- PAGE 9: ADDED ALIAS MCP_GPIO_4 FOR MIKEY MIC LOAD DETECT CIRCUIT

- PAGE 72: RENAMED NETS AND NOTES TO REMOVE REFERENCES TO RT POWER SUPPLY

- PAGE 72: ADDED C7282 APN 128S0218 IN PARALLEL WITH C7280 AS PER DAYU

- PAGE 73: REPLACED Q7320 AND Q7321 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 75: REPLACED C7576 WITH 0.022UF APN 132S0102 CAP TO INCREASE THE SLEW RATE

- PAGE 76: CORRECTED MAX OUTPUT NOTE TO REFLECT 7.2A INSTEAD OF 8A

- PAGE 75: REPLACED Q7560 AND Q7565 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 76: REPLACED Q7620 WITH 2 CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 78: ROUTED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL TO THE WIRED AND CIRCUIT

- PAGE 60: REPLACED DUAL PACKAGE OPA330 OPAMPS WITH SINGLE PACKAGE ONES - APN 353S2179

- PAGE 9: DELETED EXTRA MEDIUM POGO PIN ZS0912 AND SCREW HOLES Z0908, Z0909

- PAGE 74: REPLACED C7433 AND C7431 WITH 0.001UF CAPS APN 132S1035

- PAGE 77: ADDED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL VIA A 0 OHM RESISTOR TO PIN 3 (PG) OF THE LDO

- PAGE 78: DELETED P5V_LTS3_PGOOD AS THERE IS NO 5V LT POWER SUPPLY ANYMORE

[U6030, U6031, U6040, U6041]. ALSO, ADDED C6031 & C6041

- PAGE 7: DELETED PP5VLT_S3 NETS

- PAGE 8: DELETED =PPVIN_S3_5VLTS3, =PP5VLT_S3_V5IN NETS

3/25/2009: RELEASE 7.3.0 (MAJOR)-

(LT & RT NOMENCLATURE CLEAN-UP)

- PAGE 45: ADDED APN TEXT NOTE FOR SIL CONNECTOR

- PAGE 75: ADDED A NOTE OCP=14.5A TO R7575

3/26/2009: RELEASE 7.4.0 (MAJOR)-

- PAGE 72: REPLACED L7260 WITH APN 152S0959 AS PER DAYU

THAT IN CPU T-DIODE SENSOR AND STUFFED C5540

3/26/2009: RELEASE 7.5.0 (MAJOR)-

- PAGE 78: RENAMED =P5VRTS3_EN_L TO =P5VS3_EN_L

- PAGE 7: DELETED PP5V_S0, PP5V_S3 AND ADDED PP5VRT_S0,PP5VLT_S0, PP5VRT_S3, PP5VLT_S3 DEBUG

- PAGE 4: DELETING ENTRIES FOR 107S0138 AND 107S0139 FROM ALTERNATES PARTS TABLE AS THEY WOULD BE REPLACING

- PAGE 97: FOR 25KHZ OPERATION, CHANGE R9726 TO NO STUFF, INTERCHANGE R9705(6.8K) WITH C9705

- PAGE 25: CHANGED C2500,C2501,C2502,C2503,C2515,C2520,C2528,C2540,C2580,C2582,C2584,C2586,C2588,

- PAGE 74: ADDED PLACEMENT NOTES TO C7419,C7422 AND C7423 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 72: CONNECTED SMC_PM_G2_EN SIGNAL TO EN0 PIN 13 OF U7200 VIA A 100K RESISTOR FOR KEEPING THE POWER SUPPLY

- PAGE 73: MOVED C7344 NEXT TO R7350 AND ADDED PLACEMENT NOTE (JOHN SCHEN WANTED IT TO BE NEXT TO L7320

- PAGE 97: CHANGED C9711 FROM 0.1UF TO 1.0UF 0603 TYPE CAP AS PER FREESCALE FEEDBACK

- PAGE 97: CHANGED C9715 AND C9716 TO 50V CAPS FOR COST SAVING AND AS PER FREESCALE FEEDBACK

- PAGE 97: CHANGED R9710 TO 6.65K APN 114S0298 AND R9716 TO 226K APN 114S0445 PARTS AS PER

- PAGE 107: REMOVED FOLLOWING SENSOR NETS CONSTRAINTS: ISNS_P1V5S0MCP_P/ISNS_P1V5S0MCP_N;

- PAGE 9: REPLACED 5 SHORT POGO PINS WITH MEDIUM ONES AND ADDED THREE EXTRA MEDIUM ONES (TOTAL MEDIUM

-PG. 67, CONNECTED HP OUTPUTS TO NC OF U6700 AND LINE INPUTS TO NO OF U6700.

- PAGE 90: ADDED EMI CAPS (C9017-C9025) ON I2C, LED_RETURNS AND LCD_BKLT POWER RAILS GOING TO LVDS.

- PAGE 73: REPLACED C7307,C7308 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY)

- PAGE 70: ADDED BOM OPTION 6259_YES TO R7050 AND 6259_NO TO U7060 AND AMON PULLDOWN LOGIC

- PAGE 70: MOVED C7028 TO PPVBAT_G3H_CHGR_REG AS PER JOHN SCHEN’S FEEDBACK

REPLACED C5923-C5925 CAPS WITH 0.033 UF VALUES FOR CUT-OFF FREQUENCY OF ~146HZ

- PAGE 45: RENAMED =PP5V_S0_HDD_R TO PP5V_S0_HDD_R (AS PER UNALIASED.LST REPORT)

- PAGE 34: REPLACED THE AIRPORT CONNECTOR WITH 1.8 MM HEIGHT CONNECTOR APN 516S0582

- PAGE 52: REMOVED REFERENCES TO THE LED BACKLIGHT AS FREESCALE PART DOESN’T HAVE I2C BUS ACCESS

- PAGE 79: REPLACE Q7940 AND Q7948 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

- PAGE 90: REMOVED EMI CAPS [C9017-C9025] ON LED_RETURN, I2C AND LCD_BKLT POWER NETS

- PAGE 90: UPDATED LVDS CONNECTOR PINOUT CONNECTIONS AS PER STEVE’S NEW SPREADSHEET

- PAGE 97: CHANGED R9717 - R9722 FROM 0.1% TO 1% PARTS FOR COST SAVINGS AND AS PER FREESCALE FEEDBACK

- PAGE 107: ADDED CONSTRAINTS FOR FOLLOWING SENSOR NETS: ISNS_HDD_P/ISNS_HDD_N; ISNS_ODD_P/ISNS_ODD_N;

3/6/2009: RELEASE 6.0.0 (RFA:)-

- PAGE 74: STUFFED C7432 AS PER DAYU

OFF IN CASE IF SMC TURNS OFF

- PAGE 4: ADDED DALE/VISHAY ALTERNATES FOR 104S0023 --> 104S0018

- PAGE 73: DELETED NOTES AT THE BOTTOM RIGHT AFTER CONSULTING WITH DAYU

- PAGE 4: ADDED BOM OPTION 6259_NO TO THE TABLE UNDER K84_MISC BOM GROUP

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 5.0.0***

-PG. 67, CHANGED U6700 CB INPUT TO BE CONTROLLED BY CS4206 GPIO0.

- PAGE 75: ADDED PLACEMENT NOTE TO C7563 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 52: DELETED TERM BIL FROM SMC BATTERY & BIL CONNECTIONS

- PAGE 9: ADDED TP ALIASES TO IMVP6_VR_TT AND IMVP6_NTC

- PAGE 8: DELETED =PP3V42_G3H_5V3V3_EN AS IT IS NO LONGER USED

- PAGE 8: DELETED =PP3V3_S0_TPAD AS THERE IS NO KEYBOARD BACKLIGHT DRIVER

- PAGE 8: DELETED =PP3V42_G3H_AUDIO AS IT IS NO LONGER USED

- PAGE 4: ADDED 152S0693 AS ALT FOR 152S0778 FOR SUPPLY REDUNDANCY

-PG. 62, CHANGED TP_AUD_GPIO_0 TO AUD_GPIO_0.

- PAGE 72: REMOVED NOSTUFF’ED C7251 AS PER DAYU

- PAGE 69: CHANGED L6995 TOB APN 152S1017 FOR COT SAVING AND EFFICIENCY

- PAGE 70: ADDED PLACEMENT NOTE TO C7027 AS PER JOHN SCHEN’S FEEDBACK

CIRCUIT COMPONENTS. TURNED ON 6259_NO, FOR NOW, ON PAGE 4 TABLE

- PAGE 72: ADDED PLACEMENT NOTE TO C7230 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 73: ADDED PLACEMENT NOTE TO C7333 AS PER JOHN SCHEN’S FEEDBACK

DAYU PERFERRED IT TO BE AFTER THE SENSE RESISTOR

- PAGE 75: MOVED C7569 TO PPMCPCORE_S0_R AS PER JOHN SCHEN’S FEEDBACK

-PG.66, REPLACED THE LM48310’S (U6610/20/30) WITH LM48311’S

ADDED PLACEMENT NOTES TOO

(DAYU’S RECOMMENDATION)

ISNS_PVCORES0MCP_P/ISNS_PVCORES0MCP_N

-PG. 67, CHANGEED J6703 TO TWO PIN CONN.

-PG. 67, DELETED C6760/1/2/3.

-PG. 66, CHANGED C6630/31 TO 0.022UF

-PG. 66, CHANGED C6610/11 TO 0.022UF

-PG. 66, ADDED R6613/14/15/16/17

ISNS_LCDBKLT_P/ ISNS_LCDBKLT_N

POGO PINS = 8) AS PER NEW MCO

3/17/2009: RELEASE 7.0.0 (RFA)-

- PAGE 74: ADDED XW7401-XW7404 SHORTS ACROSS L7400 AND L7401 ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 6.0.0***

-PG. 67, DELETED R6725 AND NET =PP3V42G3H_AUDIO

-PG. 62, ADDED PLACEMENT COMMENT ATTR. TO XW6200/1

-PG. 67, ADDED PLACEMENT COMMENT ATTR. TO XW6700/1/10/11

-PG. 68, ADDED PLACEMENT COMMENT ATTR. TO XW6851/80

-PG. 66, REPLACED U6610/30 WITH LM48556 CKTS

-PG. 62, REPLACED C6225 WITH APN: 128S0216

- PAGE 9: REMOVING 2 EXTRA TALL POGO PINS (ZS0911, ZS0912) AS PER NEW MCO

- PAGE 45: REPLACE Q4590 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

- PAGE 59: REMOVING R5923 AND ONLY 1 PU ON SEL LINES IS ENOUGH

- PAGE 70: REPLACING R7020 WITH APN 107S0138 PART FOR COST SAVING

- PAGE 70: REPLACING R7008 WITH APN 107S0139 PART FOR COST SAVING

- PAGE 70: R7080 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER

- PAGE 73: R7350 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER

ISNS_AIRPORT_P/ISNS_AIRPORT_N; ISNS_1V5_S3_P/ISNS_1V5_S3_N;

- PAGE 77: CHANGED U7740 TO 500MA 1.05V LDO

- PAGE 7: RENAMED PP5V_S3_BTCAMERA_F WITH PP3V3_S3_BT_F

- PAGE 8: DELETED ALIAS =PP1V05_S0_SMC_LS AS IT IS NO LONGER NEEDED

- PAGE 52: DELETE J6955 REFERENCE AS THERE IS NO BIL CONNECTOR

- PAGE 54: REPLACING R5492 WITH APN 107S0139 PART FOR COST SAVING

- PAGE 97: ADDED DIDIT=TRUE ATTRIBUTE TO THE SWITCHING NODE PINS 3 & 4

- PAGE 97: NO STUFF’ED C9721 - C9726 AS PER FREESCALE FEEDBACK

-PG. 68, CHANGED AUD_PORTB_DET_L TO AUD_PORTA_DET_L.

-PG. 68, CHANGED AUD_PORTG_DET_L TO AUD_PORTB_DET_L.

-PG. 67, SET MIN. LINE AND NECK WIDTHS FOR AUD_CONN_L AND AUD_CONN_R

***PAGES SYNCED FROM K24 SINCE LAST RELEASE 5.0.0***

- PAGE 26: CHANGED C2615,C6210 TO 138S0653

- ADDED PLACEMENT NOTES (ATTRIBUTE) TO ALL XW SHORTS

- PAGE 7: ADDED PPBUS_R_G3H DEBUG VOLTAGE TEST POINT

- PAGE 34: REPLACE Q3450 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

-PG. 67, ADDED J6704

-PG. 65, DELETED R6521

-PG. 66, ADDED C6634/5

-PG. 66, ADDED R6631/2/3/4/5

-PG. 66, ADDED C6612/13

-PG. 65, ADDED R6523/4

FREESCALE FEEDBACK

VOLTAGE TEST POINTS

C2595 TO 138S0653

THE 107S0074/75 PARTS

AS IN K19I

-PG. 67, ADDED XW6702

-PG. 66, UPDATED 5V S3 ALIAS NOTES

1. PAGE 3: POWER BLOCK DIAGRAM - ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR. ALSO, ADDED SENSE RESISTOR ON PPBUS

- PAGE 8: ADDED =PP3V42_G3H_HALL FOR THE HALL EFFECT CONNECTOR

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.5.0***

- PAGE 69: ADDED HALL EFFECT CONNECTOR CIRCUIT J6955 APN 516S0787

- PAGE 8: ADDED PLACEMENT NOTE TO Q5502

- PAGE 8: DELETED =PP3V42_G3H_PPBUSAISNS AS PPBUS SENSE CIRCUIT HAS BEEN REMOVED

- PAGE 72: REPLACED C7282 WITH OSCON APN 128S0248 IN PARALLEL WITH C7280 AS PER DAYU

3/26/2009: RELEASE 7.6.0 (MAJOR)-

- ADDED OMIT BOM OPTION TO ALL THE XW SHORTS

- ADDED DIDT=TRUE ATTRIBUTE TO BOOT/VBST SIGNALS OF ALL THE SWITCHING SUPPLIES

- PAGE 8: DELETED =PP3V42_G3H_BATT AS THERE IS NO BIL CONNECTOR

- PAGE 8: ADDED =PP3V3_S3_AUDIO ALIAS NET FOR CASEY’S NEW CHANGES BELOW

- PAGE 8: RENAMED ALIAS =PP5V_S3_P5VS0FET TO =PP5V_S3_P5VLTS0FET AS THIS GOES TO 5V LT S0 FET CIRCUIT

- PAGE 79: RENAMED INPUT VOLTAGE NETS OF 5V S0 FET CIRCUITS TO REFLECT RT AND LT

1P05_HIGH_SIDE_SENSE OPTIONS UNDER K84_COMMON BOM GROUP

- PAGE 4: ADDED MCP_T_DIODE_SENSOR, MCPSMC_DIGITEMP_NO BOM OPTIONS UNDER K84_COMMON BOM GROUP

- PAGE 4: UPDATED DESCRIPTION FOR THE CPU

- PAGE 7: UPDATED TPS AS PER NEW UPDATE FROM TOM (SPREADSHEET ATTACHED TO THE RADAR)

- PAGE 12: REPLACED C1260 WITH APN 128S0267 AS PER DAYU

- PAGE 34: DELETED TEXT NOTE ASSOCIATED WITH J3401

ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 OHMS

OHMS

CONSTRAINT SET

3/31/2009: RELEASE 9.0.0 (RFA)-

- ADDED BACK PAGES 97-98 (LCD BACKLIGHT DRIVER AND SUPPORT CKT)

1/27/2009: TMLB FIRST RELEASE 0.0.1-

- REPLACED TEXT TMLB WITH MLB THROUGH OUT THE SCHEMATICS

2/5/2009: RELEASE 0.0.2 -

- COPIED TMLB OVER TO MLB AS K84 WILL BE PENRYN SKU WHILE K83 WILL BE ATOM SKU

- PAGE 4: UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_ENG FOR K84_COMMON BOM GROUP

- PAGE 8: DELETED FIREWIRE, IR AND BMON SPECIFIC NETS

- PAGE 55: REPLACED CPU/MCP THERMAL SENSORS U5515 ANDB U5535 WITH THE CHEAPER VERSION APNB 353S2573

2. PAGE 8: ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR, WHILE PPBUSB FEEDS 5V/3.3 V SUPPLY, LCD BKLT & PPBUS VOLTAGE SENSE CKT

- PAGE 4: ADDED CYNTEC ALTERNATES FOR 107S0074 --> 107S0138 [R7020] AND 107S0075

-PG. 67, ADDED R6725

- PAGE 70: REMOVED R7080 SENSE RESISTOR AND RENAMED =PPBUSB_G3H TO =PPBUS_G3H AS NO NEED

- PAGE 34: CHANGED J3401 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

- PAGE 7: DELETED PPBUS_R_G3H AS NO NEED OF TWO PPBUS BRANCHES

-PG. 66, CHANGED C6610/11/30/31 TO 0.015UF

-PG. 68, ADDED MIKEY MIC LOAD COMPARATOR CKT

-PG. 68, CORRECTED CODEC OUTPUT SIGNALS TABLE COMMENTS

- PAGE 8: COMBINED TWO SEPARATE PPBUSA/B BRANCHES INTO ONE =PPBUS_G3H

- PAGE 70: ADDED R7050 (6259_YES) CONNECTION FROM PIN 4 (VREF) TO PM_SLP_S3_L AS PER DAYU

- PAGE 59: REPLACED SMS PART WITH THE NEW BOSCH BMA141 ANALOG PART. ADDED R5923 10K PU RESISTOR ON

- DELETED NOTE ABOVE U6500

PP3V3_WLAN, R6010 HAS BEEN CHANGED TO 634K TO GET VDIVIDER = ~2V

- PAGE 55: ADDED MCP_T_DIODE_SENSOR BOM OPTION TO THE MCP T-DIODE THERMAL

CURRENT SENSE CIRCUIT AND WITH 1P05_HIGH_SIDE_SENSE FOR CPU 1.05V AND

CONNECTIONS. AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0

TO SMB_0_S0_DATA NETS

R9730 PIN SHORT TO ISOLATE NOISY PGND FROM THE SYSTEM GND. NAMED IT

- PAGE 97: RENAMED GND_LCDBKLT TO GND_LCDBKLT_SGND

SYSTEM GND

ALSO, CHANGED R9705 TO 10K 1% VALUE - APN 114S0315

4/1/2009: RELEASE 9.1.0 (MAJOR)-

14. PAGE 70: DIVIDED PPBUS INTO TWO BRANCHES - PPBUSA & PPBUSB. ADDED SENSE RESISTOR R7080 (2 MOHMS) ON PPBUSA. ALSO ADDED INA210 AMPLIFIER CKT ACROSS SENSE LINES. ADDED PP3V42_G3H_PPBUSAISNS (IN210 POWER) ALIAS ON PAGE 8

12. ADDED PAGE 60 AND COPIED OVER ZEPHYR2 SCHEMATICS PAGE FROM M97 IPD_FLEX_WELLSPRING. DELETED THE IPD BOARD CONNECTOR. CALLING IT WELLSPRING 3

10. PAGE 4: ADDED DEBUG_SENSE BOM OPTION TO THE K84_DEVEL_ENG BOM GROUP

11. PAGE 58: DELETED IPD FLEX CONNECTOR J5800. RENAMED PP18V5_S3, PP3V3_S3_LDO_R, PP3V3_S3_LDO TO PP18V5_S3_LDO, PP3V3_S3_IPD_R AND PP3V3_S3_IPD RESPECTIVELY TO MATCH WITH NEW ADDED PAGE 60 NET NAMES. UPDATED THESE NET NAMES ON PAGE 7 ALSO

9. PAGE 54: ADDED BOM OPTION- DEBUG_SENSE- TO CPU 1.05V/CPU VCORE HIGH SIDE CURRENT SENSE AND MCP MEM VDD CURRENT SENSE CIRCUITS FOR DEVELOPMENT BOM

4. PAGE 34: REPLACED AIRPORT CONNECTOR WITH PN 516S0580 AND UPDATED CONNECTIONS ACCORDINGLY

- NO CHANGES SINCE LAST MAJOR RELEASE 0.1.0

- PAGE 72: REPLACE Q7220 WITH SIZ700DT

- PAGE 7: DELETED IR_RX_OUT, PP5V_S3_IR_R, KBDLED_ANODE, SMC_KBDLED_PRESENT_L

- REMOVED ALS SPECIFIC NETS (PAGE 34 & 52)

- UPDATED PAGES 72-73 : 5V/3.3V & DDR3 POWER SUPPLIES AS PER FLO’S RECOMMENDATIONS

- CORRECTED BOM CONFIG TABLE (ADDED BACK BKLT_ENG)

1/21/2009: RELEASE 0.0.3-

- UPDATED BOM CONFIGURATIONS

1/21/2009: RELEASE 0.0.2-

- UPDATED SCHEMATIC AND PCB PART NUMBER INFO

- REPLACED K24 REFERENCES WITH K84

- ALL PAGES SYNC’ED FROM K24

1/19/2009:

Revision History

- PAGE 73: REPLACE 16V INPUT SIDE CAPS C7331 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS

[R7008] --> 107S0139

- PAGE 69: REMOVED BIL CIRCUIT AS IT NO LONGER A POR [R6960, C6954, D6951, C6953, C6952, J6955, C6951]

- PAGE 102: ADDED CONN_PCIE_MINI_R2D_P/N AND CONN_PCIE_MINI_D2R_P/N NETS IN THE

SENSOR CIRCUIT

- PAGE 54: REPLACED DEBUG_SENSE BOM OPTION WITH MEM_SENSE FOR MCP MEMORY VDD

- PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN SMC B SMBUS AND MCP SMBUS 1

- PAGE 9; ADDED 3 ADDITIONAL TALL POGO PINS AS PER NEW MCO AND DELETED ZS0909 SHORT POGO AS IT WAS EXTRA

- PAGE 7: DELETED SMC_BIL_BUTTON_L NET FROM BATT SIGNAL CONN GROUP AS BIL IS NO LONGER A POR

- PAGE 97: DISCONNECTED PGND (OF CAPS) FROM XW9700 AND ADDED A SEPARATE XW9701

- PAGE 97: FIXED THE LCDBKLT_VIN SIGNAL NAME ASSOCIATION TO THE CORRECT NET INSTEAD OF

- PAGE 69: REFRESHED HALL EFFECT SENSOR WITH THE NEW SYMBOL

- PAGE 52: FIXED SENSOR ADC SMBUS CONNECTIONS (BOTH SCL AND SDA WERE WRONGLY CONNECTED

- REMOVED NOTE RE: ROUTING TO MCP79 GPIO ABOVE U6870

- ADDED BOMOPTION = MIKEY ATTRIBUTE TO R6860, C6860, Q6802, R6864, R6865, & R6861

- UPDATED SIGNAL PATH CHART TO INCLUDE MCP79 GPIO ASSIGNMENTS

- ADDED BOMOPTION = MIKEY_LOAD_DET ATTRIBUTE TO R6870, R6871, C6870,

- CHANGED R6211 & R6212 FROM 39 OHMS TO 22 OHMS

***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 8.0.0***

- PAGE 4: ADDED MIKEY_LOAD_DET BOM OPTION UNDER K84_MISC BOM GROUP

- PAGE 75: ADDED C7590 (2.2UF) APN 138S0579 IN PARALLEL WITH C7563 AS PER DAYU

K19I UPDATES, EXCEPT VOLTAGE DIVIDER FOR PP3V3_WLAN [K19I USES 5V RAIL]. FOR

- PAGE 59: DELETED R5923 FROM THE TEXT NOTE

CPU VCORE HIGH SIDE CURRENT SENSE CIRCUIT

- PAGE 52: ADDED BOM OPTION MCPSMC_DIGITEMP_NO TO R5230 AND R5231

- PAGE 34: ADDED LC FILTER (L3406 AND C3432) ON PP3V3_S3_BT POWER RAIL AS PER JOHN SCHEN’S FEEDBACK

- PAGE 60: MANUALLY UPDATED RESISTORS VALUES (VOLTAGE DIVIDERS,AMPLIFIER GAINS, RC) TO MATCH WITH

- UPDATED SCHEM AND PCBF PART NUMBER INFO

- PAGE 4: ADDED 085 DEVELOPMENT BOM VARIANT & K84_DEVEL_ENG, K84_DEVEL_PVT BOM GROUPS

- PAGE 66: FIXED UNNAMED NETS CONNECTED TO - R6632

- PAGE 7: RENAMED RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR

- PAGE 7: DELETED THERMAL FUNC_TEST SECTION

- PAGE 9: FIXED BAD_TP_NC NETS - TP_RTL8211_CLK125, TP_PP3V3_ENET_PHY_VDDREG

- PAGE 34: RENAMED TITLE: RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR

- PAGE 69: CHANGE PIN OUTS OF J6955 AS PER CHINMAY

- PAGE 78: FIXED BAD_TP_NC NETS - TP_DDRREG_PGOOD

- PAGE 9: DELETED Z0912 MLB MOUNTING HOLE AS NO LONGER NEEDED

- PAGE 7: DELETED BATT SIGNAL CONN AND ADDED HALL EFFECT CONNECTOR TEST POINTS

- PAGE 7: SCRUBBED THROUGH THE FUNCTIONAL TEST POINTS AGAINST TOM’S SPREADSHEET

- PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN MIKEY AND MCP SMBUS 1 CONNECTIONS.

- PAGE 45: ADDED VOLTAGE, MIN LINE AND NECK WIDTH FOR PP5V_S0_HDD_FLT

- PAGE 4: ADDED SHORT POGO PIN 870-1699 AS ALTERNATE FOR THE MEDIUM ONES

- PAGE 4: DELETED DEBUG_SENSE BOM OPTION AND ADDED MEM_SENSE AND

- PAGE 74: FIXED UNNAMED NETS CONNECTED TO - XW7401, XW7402, XW7403 AND XW7404

- PAGE 9: ADDED TP_ ALIASES FOR - CARDREADER_RESET, USB_CARDREADER_N/P, AND

3/29/2009: RELEASE 8.0.0 (RFA)-

- PAGE 50: REPLACED R5030 WITH APN: 114S0114,(IT’S A 1% TOL, 1/16W, 0402, 84.5OHM RESISTOR)

- PAGE 52: ADDED 0 OHMS STUFFING OPTION TO CONNECT MIKEY SMBUS CONNECTIONS TO MCP SMBUS 0.

- PAGE 90:RE-ROUTED LED_RETURN SIGNALS FOR LAYOUT FEASIBILITY(CHIP WAS MOVED TO TOP SIDE)

- PAGE 49:FIXED PLACEMENT NOTES ASSOCIATED WITH R4999,C4920(SHOULD BE:PLACE NEAR PIN M12)

- PAGE 51: FIXED PLACEMENT NOTE ASSOCIATED WITH R5146 - PLACE NEAR U5110 INSTEAD OF SMC

- PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH SMBUS_SMC_B_S0_SCL/SDA

5 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=K24_MLB

Revision History

SYNC_DATE=01/19/2009

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

11/01/2009: RELEASE C.0.0 (FAB)-

ADDED APN 518S0774 FOR XDP CONNECTOR J1300 (TO REPLACE 998-2515)

- PAGE 4: ADDED APN 104S0033 (6.8 OHMS, 1/4W) RESISTORS IN MODULE PARTS TABLE FOR R6612, R6617, R6630 & R6633

- FINAL PVT OK2FAB RELEASE

09/21/2009: RELEASE A.0.0 (FAB)-

K84_DEBUG_PROD BOM GROUP IS TURNED ON

- PAGE 4: UPDATED BOM TABLES TO NOT INCLUDE ANY 085 DEVELOPMENT BOMS. AND,

- PAGE 3: UPDATED POWER SYSTEM BLOCK DIAGRAM

- PAGE 2: UPDATED SYSTEM BLOCK DIAGRAM

- PROD (POST 1ST MONTH OF PRODUCTION) OK2FAB RELEASE

09/16/2009: RELEASE 17.0.0 (FAB)-

- FINAL DVT OK2FAB RELEASE

- PAGE 50: CHANGED R5030 SIL RESISTOR TO 80.6 OHMS APN 114S0112 AS PER ID

- PAGE 66: ADDED BOMOPTION OMIT TO RESISTORS R6612, R6617, R6630 & R6633

- PROD_DEBUG (POST FIRST 5K UNTIL 1 MONTH INTO PRODUCTION) OK2FAB RELEASE

- PAGE 4: ADDED 1 NEW POR BOMS 639-0554, 639-0555 AND 1 NEW DEVELOPEMENT BOM

- PAGE 4: DELETED 353S2811 ENTRY FROM THE ALTERNATES TABLE

NUMBERS AS PER KIRAN’S EMAIL

- PAGE 57 : CHANGED R5714 TO 165 OHMS APN 114S0141 AS PER

05/11/2009: RELEASE 12.14.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL):

05/10/2009: RELEASE 12.13.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL):

- REMOVED R6725 AND =PP3V3_S3_AUDIO CONNECTION TO MAX14504 ANALOG SWITCH

- PAGE 75: CHANGED R7569 TO 11.3K APN 114S0319 FOR SETTING THE CORRECT OCSET AS PER DAYU

- PAGE 4: DELETED 152S0694 ALTERNATE ENTRY FOR 152S0138 AS IT IS NOT USED

I2C_MIKEY_SCL/SDA_R

- PAGE 9: ADDED 7 EXTRA TALL POGO PINS FOR EMI - 4 STUFFED AT THE BOTTOM,

- PAGE 8: ADDED GLOBAL DIGITAL GROUND NET WITH MIN_LINE/NECK_WIDTH

- PAGE 97: CHANGED MIN_NECK_WIDTH ASSOCIATED WITH PPVOUT_S0_LCDBKLT TO 0.24MM

4/2/2009: RELEASE 9.3.0 (MAJOR):

- PAGE 4: REMOVED 514-0706, 514-0705 AND 514-0718 FROM THE ALTERNATES TABLE

POR IS LOW NOISE POGO PINS

- PAGE 4: ADDED NEW INTERSIL ISL6258A (WITH IMPROVED CHARGE CURRENT ACCURACY

TO K84

- PAGE 4: REPLACED CPU APN 337S3704 WITH 337S3769 IN MODULE PARTS TABLE AND REMOVED 337S3704 FROM THE ALTERNATE PART TABLE AS POR IS 337S3769

- PAGE 4: REMOVE 870-1794, 870-1698 & 870-1820 FROM THE ALTERNATES TABLE AS

- PAGE 72 : CHANGED C7252, C7291 & C7292 BACK TO ORIGINAL APN 128S0271

05/20/2009: AGILE RELEASE PROTO 2 OK2FAB 13.0.0 (FAB):

- FINAL PROTO 2 OK2FAB RELEASE

***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 9.2.0***

- PAGE 4:B ADDED 5.95MM SANYO PART 128S0288 AS ALTERNATE TO 128S0271

- PAGE 4: REMOVED 138S0606 FROM THE ALTERNATES TABLE AS IT DOESN’T PERTAIN

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.6.0***

AND TO K84 MISC BOM GROUP. THIS IS TO STUFF ISL6258 PART

WITH EITHER ISL6258 OR ISL6259 DEPENDING UPON PAGE 4 BOM TABLE

- PAGE 52: DELETED TEXT NOTE ON BATTERY LED DRIVER AS IT IS NA TO K84

- PAGE 13: FIXED THE NOTE ON THE XDP PAGE- REPLACING 920-0620 ADAPTER

- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER

08/05/2009: RELEASE 15.3.0 (MAJOR)-

- PAGE 4: ADDED PDNI PLATED AUDIO CONNECTOR W/ CHAMFER APN 514-0718 AS AN

- PAGE 4: ADDED GOLD PLATED AUDIO CONNECTOR W/O CHAMFER APN 998-2622 AS AN ALTERNATE FOR J6700 APN 514-0694

- PAGE 4: ADDED GOLD PLATED RJ45 CONNECTOR APN 998-2621 AS AN ALTERNATE FOR

- PAGE 97: REFRESHED THE SYMBOL OF C9715 4.7UF APN 138S0661

08/27/2009: AGILE PDFC OK2FAB RELEASE 16.0.0 (FAB)-

- PAGE 59: ADDED NOSTUFF BOM OPTION ATTRIBUTE TO C5923-C5925 AS STATED

- PAGE 70: CHANGED R7047 FROM 10 OHM TO 0 OHM, 5%, APN:116S0004 TO FIX SLOW

- PAGE 4: ADDED GOLD PLATED MINI DP CONNECTOR APN 998-2626 AS AN ALTERNATE

- PAGE 4: ADDED LOW NOISE POGO PINS 870-1885 (MEDIUM), 870-1886 (TALL), AND

- PAGE 49: CHANGED C4950, C4951, C4952 TO APN:132S0131 (CAP,0402,0.033UF, 16V,10%) AS THESE WOULD BE USED TO ACHIEVE CUT-OFF FREQUENCY OF

SEEN BY SMC CHIP. CAPS ON SMS PAGE WOULD BE UNSTUFFED

~146HZ FOR SMS (AS PER THE VENDOR) AND FILTER THE NOISE TOO AS

- PAGE 4: ADDED GOLD PLATED USB CONNECTOR APN 998-2624 AS AN ALTERNATE FOR

- PAGE 4: ADDED METAL PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO

REPLACED R6961 WITH A 0 OHM RESISTOR AND NOSTUFF’ED C6955

- CONNECT AUDIO JACK SHIELD TO DIGITAL GROUND.

0.6/0.24MM

- PAGE 4: ADDED APN 138S0606 (TAIYO-YUDEN) AS AN ALTERNATE FOR APN 138S0602 ALTERNATE FOR J6700 APN 514-0694

- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER

- FINAL PDFC (PRE DVT) RELEASE!

- PAGE 70: CHANGED C7043 FROM 0.1UF TO 1UF, 10%, APN:138S0640 TO FIX SLOW

- PAGE 97: CHANGED L9710 BACK TO THE ORIGINAL APN 152S0826 AS 2525 PACKAGE CAN’T FIT IN

RJ45 J3900 CONNECTOR

- PAGE 50: CHANGED R5030 TO 48.7 OHMS APN 114S0091 (SIL CURRENT TO 12MA)

CONNECTED IT TO PIN 1 (RSMRST_PWRGD) TO FIX LEAKAGE ISSUE

3V3S5_DRVL (FIXED THE NET NAME- ADDED UNDERSCORE)

- PAGE 4:B ADDED 5.95MM SANYO PART 128S0286 AS ALTERNATE TO 128S0248

- PAGE 9: REPLACED Z0906,Z0907,Z0910 AND Z0911 MLB MOUNTING HOLES WITH 2.7 MM

- PAGE 4: UNDER K84_PROGPARTS BOM GROUP, REPLACED BLANK P/N WITH

AND VOLTAGE ATTRIBUTES

- PAGE 9: REPLACED Z0905 AND Z0913 MLB MOUNTING HOLES WITH 2.7 MM

- ADDED 100PF EMC CAP ON THREE SPEAKER CONNECTORS.

- PAGE 78: DELETED SYNONYMS AS THEY ARE NOT NEEDED ANYMORE

- PAGE 28: DELETED MAKE_BASE=TRUE ASSOCIATED WITH PCIE_RESET_L

CHARGING ISSUE, PER DAYU

SLOW CHARGING ISSUE, PER DAYU

- PAGE 70: CHANGED R7031 FROM 10 OHM TO 2.2 OHM, 5%, APN:116S0010 TO FIX

ABOVE. ALSO, EDITED THE NOTE ACCORDINGLY

870-1887 (THIN) AS ALTERNATES

J4600/J4610 APN 514-0689

FOR J9400 APN 514-0691

J3900 APN 514-0704

- PAGE 4: DELETED LOW NOISE MURRATA CAP ENTRY FROM THE ALTERNATES TABLE

ENGINEER

- PAGE 70: DISCONNECTED PM_SLP_S3_L FROM PIN 4 (VREF) AS IT WAS INCORRECTLY

- PAGE 97: NOSTUFFED C9716 AND CHANGED C9715 TO APN 138S0661 AS POR IS TO

- PAGE 46: REPLACED J4600 & J4610 USB CONNECTORS WITH POR PLASTIC CONNECTOR

- PAGE 4: DELETED CHGR_6258 AND RENAMED 6259_NO TO

07/27/2009: RELEASE 15.2.0 (MAJOR)-

HAVE SINGLE CAP LOW NOISE MURRATA CAP SOLUTION AS PER ACOUSTICS

CONNECTED, THEREBY CAUSING HIGHER SLEEP/SHUTDOWN POWER

132S0178 TO FIX THE SMART TEST FAILURE

- PAGE 49: CHANGED SMS NOISE FILTERING CAPS C4950-C4952 TO 0.47UF APN

07/21/2009: RELEASE 15.1.0 (MAJOR)-

CATEGORY AS PER CASEY

PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE

- PAGE 70: DELETED OMIT BOM OPTION FROM U7000 AS ISL6259 HAVE BEEN

- NO CHANGES SINCE LAST MAJOR 14.7.0. THIS IS FINAL EVT FAB RELEASE

PRODUCTION HAS NOW MOVED TO ITS ALTERNATE PART 353S2718

: ZS0920

- PAGE 78: ADDED 0 OHM BOM OPTION R7895 BETWEEN 1V05_S5_PGOOD AND RSMRST_PWRGD FOR DEBUG PURPOSES

06/11/2009: RELEASE 14.4.0 (MAJOR)-

- PAGE 97: CHANGED MIN_LINE/NECK_WIDTH ASSOCIATED WITH GND_LCDBKLT_SGND TO

- REMOVED OPTIONAL STUFF-AROUND RESISTORS FOR ANALOG SWITCH

- PAGE 9: DELETED GND MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES

- PAGE 78: DELETED MAKE_BASE=TRUE ASSOCIATED WITH ALL_SYS_PWRGD

- PAGE 9: ADDED ONE MORE TALL POGO PIN ON BOTTOM SIDE

4/3/2009: RELEASE: 9.6.0 (MAJOR):

- PAGE 78: ADDED BOMOPTION ATTRIBUTE OMIT TO U7870 AS NEW INTERSIL PART

PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE

- PAGE 39: ADDED BOMOPTION ATTRIBUTE OMIT TO J3900 AS NEW PG2 CONNECTOR

- PAGE 9: ADDED NOSTUFF BOM OPTION TO ZS0920

- PAGE 97: CHANGED R9710 TO 7.68K APN 114S0304 (LCD BKLT CURRENT TO 20MA)

06/25/2009: RELEASE 14.7.0 (MAJOR)-

ETHERNET JITTER ISSUE

- PAGE 49: REPLACED C4950-C4952 WITH 1UF APN 138S0640 CAPS

06/22/2009: RELEASE 14.6.0 (MAJOR)-

- PAGE 97: ADDED CRITICAL ATTRIBUTE TO C9715 & C9716

**PAGES SYNCED FROM CASEY’S AUDIO_MLB SINCE LAST RELEASE 12.1.0***

CASE_B2_SM DUE TO PACKAGING ERROR (SAME APN)

- PAGE 94: REPLACED J9400 DP CONNECTOR WITH POR PLASTIC CONNECTOR

- PAGE 75: CHANGE R7565 TO 1OHM APN 113S0023 PER RDAR://6812904

APN 514-0692

514-0691 ALTERNATE FOR 514-0690;

- NO CHANGE SINCE LAST RFA RELEASE 11.0.0. ***THIS IS A RESUBMIT AS PREVIOUS RFA DIDNT GO THROUGH***

4/23/2009 - RELEASE 12.1.0 (MAJOR):

ADDED CORRESPONDING NOTES-

- NO CHANGE SINCE LAST MINOR RELEASE 10.1.1

- PAGE 4: ADDED CPU APN 337S3769 AS ALTERNATE TO 337S3704

- PAGE 13: REPLACED J1300 XDP CONNECTOR WITH MORE ROBUST CONNECTOR

- PAGE 75: CHANGE Q7560 AND Q7565 TO SIS426 APN 376S0749 PER

- PAGE 39: REPLACED J3900 ETHERNET CONNECTOR WITH POR PLASTIC CONNECTOR

UNDER MODULE PARTS TABLE .

- PAGE 4: DELETED ENTRIES IN THE ALTERNATE BOM TABLE FOR THE FOLLOWING APN:

- PAGE 70: FIXED Q7001 DRAIN-SOURCE ORIENTATION

06/12/2009: RELEASE 14.5.0 (MAJOR)-

06/11/2009: RELEASE 14.3.0 (MAJOR)-

- PAGE 77: CHANGED R7780 TO 25.5K APN 114S0354 & R7781 TO 80.6K APN

DIAMETER PLATED HOLES - APN 998-1584

REMOVED

114S0402 AS PER DAYU

NETS TO FIX NOISE ISSUE

- PAGE 49: ADDED 0.1UF CAPS ON SMS_X_AXIS, SMS_Y_AXIS & SMS_Z_AXIS

- PAGE 4: ADDED APN 138S0661 LOW NOISE MURATA CAPS AS ALTERNATE FOR

4/6/2009 - RELEASE 11.0.0 (OK2FAB):

C9715 & C9716 TO FIX LCD BKLT AUDIBLE NOISE ISSUE

- PAGE 78: DISCONNECTED P1V05_S5_PGOOD FROM PIN 3 OF U7840 AND

4/5/2009: RELEASE 10.1.0 (MAJOR):

4/2/2009: RELEASE: 9.5.0 (MAJOR):

AS PER JOHN SCHEN

- PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH

05/22/2009: AGILE RELEASE PROTO 2 OK2FAB 14.0.0 (FAB)-

***RETRY***

RDAR://PROBLEM/6875543

SMC B SMBUS TO MCP79 SMBUS 1

05/08/2009: RELEASE 12.12.0 (MAJOR & WEEKLY ECO):

MIKEY TO MCP79 SMBUS 0 INSTEAD OF SMBUS 1 AND TO CONNECT

IT HAS I2C BUS PU TO S0 POWER RAIL

05/05/2009: RELEASE 12.11.0 (MAJOR & WEEKLY ECO):

- PAGE 97: CHANGED L9710 TO A BIGGER 2525 PACKAGE (LOW DCR) APN 152S0585 FOR

THOUGH POR IS PLASTIC MINI DP CONNECTOR PART

- PAGE 94: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS

THOUGH POR IS PLASTIC USB CONNECTOR PART

- PAGE 46: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS

- PAGE 4: ADDED 4 QUANTITIES OF DIMM CONNECTOR SCREWS APN 452-1708

5/01/2009: RELEASE 12.8.0 (MAJOR):

- PAGE 4: ADDED A36 EEE NUMBER FOR NEW BOM CONFIGURATION 639-0254 SUPPLY RAILS TO ADC CHIP I2C BUS

05/01/2009: RELEASE 12.9.0 (MAJOR):

- PAGE 4: UPDATED PLASTIC PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO 514-0690 PLASTIC ALTERNATE FOR 514-0691 METAL;

- PAGE 60: CHANGED U6050 INA 211 PART TO 200X GAIN INA 210 APN 353S2073

514-0688 PLASTIC ALTERNATE FOR 514-0689 METAL

- PAGE 46: REPLACED PLASTIC USB CONNECTORS WITH METAL APN 514-0689 PARTS

- PAGE 60: ADDED 0 OHMS SERIES RESISTORS R6003 AND R6004 ON AVDD AND DVDD

4/29/2009: RELEASE 12.7.0 (MAJOR & WEEKLY ECO):

- PAGE 60: CHANGED R6001 & R6002 TO 33 OHMS RESISTORS TO FIX UNDERSHOOT ON

ADDED TWO ENTRIES (J3200 AND J3100) FOR FOXCONN AND TWO FOR MOLEX

- PAGE 4: ADDED NEW BOM ENTRY 639-0254 FOR MOLEX DDR3 CONNECTOR CONFIG. ALSO,

- PAGE 76: CHANGED THE CPU VTT OVER CURRENT TRIP POINT PER RDAR://6792329 BY

- PAGE 67: MOVED L6707 & L6708 TO J6703 (FULL RANGE SPEAKER CONNECTOR)

4/28/2009: RELEASE 12.5.0 (MAJOR):

FOR EMI PURPOSES - L6707 & L6708

4/28/2009: RELEASE 12.4.0 (MAJOR):

- PAGE 74: CHANGED R7415 TO 10.5K AS PER RDAR://6792327

- PAGE 74: UNSTUFFED C7434 AS PER RDAR://6792327

- REPLACED J6700 WITH APN: 514-0694

4/24/2009 - RELEASE 12.2.0 (MAJOR):

- PAGE 70: ADDED OMIT BOM OPTION TO U7000 AS THIS PART WILL GET STUFFED

DIAMETER PLATED HOLES - APN 998-1584

AS PER KIRAN

- PAGE 97: CHANGED R9716 FROM 226K TO 243K TO CHANGE THE OVP POINT TO 35.3V

- PAGE 4: ADDED CHGR_6258 BOM OPTION UNDER MODULE PARTS TABLE

APN 514-0690

- ADDED DZ 6702 AND L6706

4/27/2009 - RELEASE 12.3.0 (MAJOR & WEEKLY ECO):

EDITED 639-0035 BOM NAME TO REFLECT FOXCONN DDR3 CONNECTOR.

- PAGE 57: DELETED NO_TEST = TRUE ATTRIBUTE FROM Z2_SCLK AND

- PAGE 34: RENAMED P5VWLAN_SS NET TO P3V3WLAN_SS

4/3/2009: RELEASE: 10.0.0 (RFA):

(DUE TO 0 OHMS)

IN MODULE PARTS TABLE

TO SHOW A SEPARATE CONNECTION FOR CLARITY

- PAGE 52: MOVED THE R5251 CONNECTION TO SENSOR ADC TO THE RIGHT SIDE

516-0213 AND 516S0709

514-0689 ALTERNATE FOR 514-0688 APN 998-2515

BOARD WITH 920-0782 ADAPTER FLEX

**SCHEMATIC AND BOM CLEAN-UP**

APN 514-0688

- PAGE 69: RENAMED 6259_NO/YES TO CHGR_6259_NO/YES

CHGR_6259_NO. REPLACED CHGR_6258 WITH CHGR_6259_NO

CHANGING R7604 FROM 8.87KN) TO 6.04KN)

RDAR://6812904

4/6/2009 - RELEASE 10.1.1 (MINOR):

- CONNECTED R6860 TO AUD_IP_PERPH_DET

- PAGE 46: DELETED TEXT NOTE RELATED TO R4691 & R4690 AS IT IS NA TO K84

- PAGE 74: CHANGED C7432 TO 0.001UF AS PER RDAR://6792327

- PAGE 74: CHANGED C7428 TO 0.47UF AS PER RDAR://6792327

BETWEEN CAPS AND CONNECTOR

BETTER EFFICIENCY

4/29/2009: RELEASE 12.6.0 (MAJOR & WEEKLY ECO):

- PAGE 94: REPLACED PLASTIC MINI DP CONNECTOR WITH METAL APN 514-0691 PART

ADDED CORRESPONDING NOTES-

- PAGE 4: REMOVED SHORT POGO PIN ALTERNATE

- PAGE 4: REVERTING MCP TO EARLIER USE APN 338S0710

J6704 FOR EMI PURPOSES - L6709 & L6710

05/04/2009: RELEASE 12.10.0 (MAJOR):

128S0286

128S0288

PROGRAMMED P/N

FROM FAN STANDOFF

3 UNSTUFFED ON THE TOP

- CHANGED MIN_WIDTH OF CODEC HP OUT NETS.

- PAGE 69: PUT R6961 BEFORE C6955 TO GET RC FILTER. ALSO, FOR NOW,

RDAR://PROBLEM/6752822

128S0286

- UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS

- PAGE 97: ADDED A 1000PF CAP (C9727) ON LCDBKLT_VIN NEAR PIN 1

- PAGE 77: CHANGED C7771 TO 47UF APN 138S0659 TO FIX ETHERNET JITTER ISSUE

- PAGE 72: REPLACED C7240 & C7282 WITH 5.95MM SANYO APN

JITTER ISSUE

RDAR://PROBLEM/6834630

- PAGE 60: CHANGED R6003 AND R6004 TO 10 OHMS 5% RESISTOR VALUES

- PAGE 73: REPLACED C7331 & C7345 WITH 5.95MM SANYO APN

ISSUE

- PAGE 70: REMOVED R7050 CHGR_6259_YES COMPONENT AS IT IS NOT NEEDED

CURRENT PER RDAR://PROBLEM/6752822

- PAGE 50: CHANGED R5714 TO 0 OHM APN 116S0004 PER

- PAGE 69: REFRESHED J6955 SYMBOL - APN 516S0787

- PAGE 67: CHANGED J6704 TO A THREE PIN CONNECTOR 518S0520

- PAGE 69: REFRESHED J6955 SYMBOL (HALL EFFECT CONNECTOR)

- PAGE 59: ADDED R5922 10 OHMS SERIES R ON VDD SUPPLY TO FIX SMS NOISE

ZS0916-ZS0918 WITH THINBC APN 870-1820 (2 MM) ONES

- PAGE 9: REPLACED ALL MEDIUM POGO PINS WITH APN 870-1794 (2 MM) AND

- PAGE 4: ADDED NEW ISL PART APN 353S2718 AS AN ALTERNATE TO FIX B4 DONGLE

- PAGE 4: REMOVING CHGR_6259_NO BOM OPTION AS ISL 6259 IS NOT POR

06/09/2009: RELEASE 14.1.0 (MAJOR)-

- ADDED R6862 PULL-UP RESISTOR TO PERPH. DETECT CKT.

***PAGES SYNCED FROM CASEY HARDY?S AUDIO_MLB SINCE LAST RELEASE 14.0.0***

(APN 138S0654): TO FIX B4 DONGLE ISSUE

C9400 & C9481 TO 4.7UF (APN 138S0618) & CHANGED C9480 TO 22UF

- PAGE 94: STUFFED C9485 AND CHANGED IT TO 22UF (APN 138S0654),CHANGED

WITH ISL 6258 (PM_SLP_S3_L DIRECTLY CONNECTS TO ISL 6258 PIN)

WITH XW SHORTS- XW7052 & XW7054

- PAGE 70: DELETED R7051 & R7053 CHGR_6259_YES BOM OPTIONS COMPONENTS

ISSUE

- PAGE 70: REMOVED CHGR_6259_YES/NO BOM ATTRIBUTES AS ISL 6259 IS NOT POR

- PAGE 70: REPLACING R7052 & R7054 CHGR_6259_NO BOM OPTION COMPONENTS

4/7/2009 - RELEASE 12.0.0 OK2FAB (RFA):

- PAGE 75: CHANGED C7565 AND C7568 TO CASE_B4_SM PACKAGE FROM

- PAGE 8: DELETED =PP3V3_S3_AUDIO ALIAS AS IT IS NO LONGER APPLICABLE Z2_MOSI AS THEY CONFLICT WITH FUNC_TEST ATTRIBUTE ON PAGE 7

**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.5.0***

06/10/2009: RELEASE 14.2.0 (MAJOR)-

- PAGE 77: ADDED 0 OHMS BOM OPTIONS R7782 BETWEEN PIN 4 OF U7750 (SKIP PIN) AND POWER RAIL AND R7783 BETWEEN PIN 4 AND GND. R7782 WILL BE NOSTUFF FOR NOW. THIS IS AS PER DAYU TO FIX

- PAGE 9: ADDED ONE MORE EXTRA TALL POGO PIN AS PER EMC RECOMMENDATION

- PAGE 57: CHANGED R5714 TO 113 OHMS APN 114S0125 (KB LED CURRENT TO 8.5MA)

07/17/2009: AGILE EVT OK2FAB RELEASE 15.0.0 (FAB)-

- PAGE 4: DELETED MIKEY_LOAD_DET BOM OPTION FROM THE TABLE UNDER K84_MISC

UPDATED NOTE BELOW THE ALTERNATES PARTS TABLE ACCORDINGLY

- PAGE 4: UPDATED ALTERNATES FOR MINI DP AND USB CONNECTORS WITH PG2

- PAGE 4: ADDED PG2 CONNECTOR APN 514-0704 IN THE MODULE PARTS TABLE FOR

- PAGE 4: DELETED 353S2310 PART FROM THE ALTERNATES BOM TABLE AS ALL

FOR U7870 TO FIX B4 DONGLE ISSUE CIRCUIT HAS BEEN REMOVED. SO R2143 NEEDS TO BE STUFFED NOW

- PAGE 21: DELETED NOSTUFF BOM ATTRIBUTE FROM R2143 AS MIKEY_LOAD_DET

- PAGE 4: ADDED NEW INTERSIL PART APN 353S2718 IN THE MODULE PARTS TABLE

PLASTIC CONNECTORS- APN 514-0706 (MDP) & 514-0705 (USB). AND,

ALTERNATE TABLE (MAKING ALTERNATES AS PRIMARY)

- FINAL PROTO 2 OK2FAB RELEASE

- UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS

(P7550)

08/31/2009: RELEASE 16.1.0 (MAJOR)-

- PAGE 53: REPLACED APN 376S0545 WITH 376S0820 @ Q5315 - PER ECO#0000737172

- PAGE 50: REPLACED DUAL Q5032 FET WITH TWO SINGLE Q5032 & Q5033 (APN 376S0612)

- PAGE 97: REPLACED C9717 WITH 1000PF CAP APN 132S0147 AND ADDED PLACEMENT NOTE

4/2/2009: RELEASE: 9.4.0 (MAJOR):

Revision History

- PAGE 72: REPLACED C7252, C7291 & C7292 WITH 5.95MM SANYO APN

- PAGE 97: UPDATED SCHEMATIC NOTE RELATED TO TARGET AND ACTUAL ISET & OVP

- PAGE 94: ADDED OMIT BOM OPTION TO J9400 MINI DP CONNECTOR

- PAGE 67: ADDED OMIT BOM OPTION TO J6700 AUDIO CONNECTOR

- PAGE 46: ADDED OMIT BOM OPTIONS TO J4600 & J4610 USB CONNECTORS

- PAGE 9: ADDED OMIT BOM OPTION ON ALL THE POGO PINS

AND ADDED TO MODULE PARTS TABLE AS THEY ARE NOW POR I/O CONNECTORS

CONNECTORS AS THEY ARE NO LONGER POR FOR DVT

- PAGE 4: REMOVED 998S APN FROM THE ALTERNATES TABLE PERTAINING TO I/O

LIMITS) APN 353S2811 AS AN ALTERNATE FOR APN 353S1832

870-1820) IN MODULE PARTS TABLE

- PAGE 13: ADDED OMIT TO J1300

- PAGE 52: CHANGED R5200, R5201, R5260 & R5261 TO 2K APN 116S0073

- PAGE 50: CHANGED R5030 TO 63.4 OHMS APN 114S0102 TO INCREASE THE SIL

- PAGE 37: CHANGED C3714 AND C3715 TO 2.2UF APN 138S0642 TO FIX ETHERNET

- PAGE 4: ADDED A TEXT NOTE STATING THAT ADC CAN ONLY WORK IN S0 STATE AS

- PAGE 4: DELETED SANYO 6.00MM OSCON CAPS 128S0248 & 128S0271 FROM THE

085-1076 FOR INITIAL RAMP

- PAGE 4: UPDATED BOM GROUPS TABLE TO REFLECT AFOREMENTIONED CHANGES. NEW DEVELOPMENT BOM ONLY HAS XDP CONNECTOR AND LPCPLUS COMPONENTS

- PAGE 4: ADDED 2 NEW EEES TO ATTACH WITH AFOREMENTIONED NEW 639 BOMS

- PAGE 70: REPLACED U7000 WITH THE NEW INTERSIL SCREENED PARTS APN 353S2811

- PAGE 4: TURNING ON BOM OPTION MCPSMC_DIGITEMP_YES AS POR IS TO CONNECT

870-1886 (IN PLACE OF 870-1698) & 870-1887 (IN PLACE OF

- PAGE 4: ADDED LOW NOISE POGO APNS 870-1885 (IN PLACE OF 870-1794),

10/12/2009: RELEASE B.0.0 (FAB)-

AS THAT’S THE PIN WIDTH

- PAGE 75: CHANGED L7560 TO APN 152S0526 - 0.68UH, 3.5MOHM,16A - AS PER DAYU

- PAGE 72: ADDED MIN_LINE/NECK_WIDTH ATTRIBUTES TO 5V_S3_DRVL, 3V3S5_VBST,

- PAGE 54:B CHANGED R5412 TO 118OHM (114S0127)

N-CH FETS FOR ROUTING PURPOSES (SIL ANODE SIGNAL)

6 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

Revision History

SYNC_MASTER=K24_MLB

SYNC_DATE=01/19/2009

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(NEED TO ADD 2 GND TP)

LVDS FUNC_TEST

(NEED 2 TP)

BATT POWER CONN FUNC_TEST

SATA HDD/SIL FUNC_TEST

(NEED TO ADD 2 GND TP)

(NEED TO ADD 3 GND TP)

(NEED TO ADD 1 GND TP)

MIC FUNC_TEST

SPEAKER FUNC_TEST

(NEED TO ADD 2 GND TP)

X16 WIRELESS CONN FUNC_TEST

(NEED 2 TP)

IPD_FLEX_CONN FUNC_TEST

(NEED 2 TP)

(NEED TO ADD 1 GND TP)

(NEED 2 TP)

(NEED TO ADD 2 GND TP)

(NEED 2 TP)

(NEED TO ADD 2 GND TP)

HALL EFFECT CONNECTOR FUNC_TEST

(NEED TO ADD 5 GND TP)

Functional Test Points

FAN CONNECTORS FUNC_TEST

(NEED TO ADD 1 GND TP)

KEYBOARD CONN FUNC_TEST

SATA ODD CONN FUNC_TEST

POWER NETS FUNC_TEST

DC POWER CONN FUNC_TEST

7 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SMC_LID_R

TRUE

SPKRAMP_R_P_OUT

TRUE

BI_MIC_HI

TRUE

LVDS_IG_DDC_DATA

TRUE

LVDS_IG_A_DATA_N<0>

PP5VLT_S0

TRUE

PP1V8_S0

TRUE

PM_SLP_S3_L

TRUE

PP3V3_S3_LDO

TRUE

PP18V5_S3

PP3V3_S5_AVREF_SMC

TRUE

WS_CONTROL_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD23

WS_KBD21

TRUE

WS_KBD17

TRUE

WS_KBD8

TRUE

WS_KBD7

TRUE

PP5V_S3_CAMERA_F

WS_KBD22

TRUE

WS_KBD20

TRUE

WS_KBD18

WS_KBD12

TRUE

LVDS_IG_A_DATA_N<1>

TRUE

LVDS_IG_A_DATA_N<2>

TRUE

PP5VRT_S0

WS_KBD15_CAP

TRUE

WS_KBD2

TRUE

PP0V75_S0

WS_KBD16_NUM

TRUE

ADAPTER_SENSE

TRUE

LVDS_IG_A_DATA_P<0>

TRUE

LVDS_IG_A_DATA_P<1>

TRUE

WS_KBD10

TRUE

PP5V_SW_ODD

TRUE

SATA_HDD_R2D_P

TRUE

LVDS_IG_A_CLK_F_N

TRUE

LVDS_IG_DDC_CLK

TRUE

LVDS_IG_A_DATA_P<2>

PP18V5_DCIN_FUSE

TRUE

WS_KBD19

TRUE

SMC_ODD_DETECT

TRUE

SATA_ODD_D2R_C_P

TRUE

LED_RETURN_2

TRUE

PPVCORE_S0_MCP

TRUE

PP5VRT_S0

TRUE

PP5V_S3

TRUE

PP1V5_S3

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP1V1R1V05_S5 PP3V3_S5

TRUE TRUE

PP3V42_G3H

TRUE

PPBUS_G3H

TRUE

PP3V3_ENET_PHY PP1V2R1V05_ENET

TRUE

PP5V_S0_HDD_FLT

PP3V3_WLAN

TRUE

PP3V3_G3_RTC

PPVOUT_S0_LCDBKLT

TRUE

PP4V5_AUDIO_ANALOG

TRUE

PM_SLP_S4_L

TRUE

SMC_PM_G2_EN

LED_RETURN_5

TRUE

PP3V3_LCDVDD_SW_F

TRUE

PP5V_SW_ODD

TRUE

PP1V5_S0

PP1V05_S0

TRUE

PPVCORE_S0_CPU

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

USB_CAMERA_CONN_N

TRUE

BI_MIC_LO

TRUE

FAN_RT_PWM

TRUE

BI_MIC_SHIELD

TRUE

CONN_USB2_BT_P

TRUE

SYS_DETECT_L BATT_POS_F

TRUE

PP3V42_G3H

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SATA_HDD_D2R_C_N

TRUE

PCIE_WAKE_L

TRUE

CONN_PCIE_MINI_R2D_N

LVDS_IG_A_CLK_F_P

TRUE

LED_RETURN_1

TRUE

LED_RETURN_3

TRUE

LED_RETURN_4

TRUE

PP3V3_WLAN

TRUE

PCIE_CLK100M_MINI_CONN_N

TRUE

SPKRAMP_SUB_P_OUT

SPKRAMP_SUB_N_OUT

TRUE

SPKRAMP_R_N_OUT

TRUE

SPKRAMP_L_P_OUT

SPKRAMP_L_N_OUT

TRUE

FAN_RT_TACH

TRUE

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_R2D_N

PP5V_S0_HDD_FLT

TRUE

SATA_ODD_R2D_N

TRUE

SYS_LED_ANODE_R

TRUE

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_R2D_P

TRUE

WS_KBD14

TRUE

WS_KBD13

WS_KBD11

TRUE

WS_KBD9

TRUE

PSOC_F_CS_L

TRUE

PP3V3_LCDVDD_SW_F

TRUE

PP3V3_S0_LCD_F

TRUE

Z2_CS_L

TRUE

MINI_CLKREQ_Q_L

TRUE

PP3V3_S3_LDO PP18V5_S3

TRUE

PPVOUT_S0_LCDBKLT

TRUE

Z2_DEBUG3 Z2_MOSI

TRUE

Z2_MISO

TRUE

Z2_BOOST_EN

TRUE

Z2_HOST_INTN

TRUE

Z2_CLKIN Z2_KEY_ACT_L

TRUE TRUE

Z2_RESET

TRUE

PSOC_MISO

USB_CAMERA_CONN_P

TRUE

PP5V_S3_CAMERA_F

TRUE

LED_RETURN_6

PICKB_L

TRUE

PSOC_MOSI

TRUE TRUE

PSOC_SCLK SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PP3V3_S3

TRUE TRUE

PP3V42_G3H WS_KBD1

TRUE

WS_KBD4

TRUE

WS_KBD6

TRUE

WS_KBD5

TRUE

WS_KBD3

TRUE

Z2_SCLK

TRUE

MINI_RESET_CONN_L

CONN_USB2_BT_N

TRUE

CONN_PCIE_MINI_R2D_P

TRUE

CONN_PCIE_MINI_D2R_N

TRUE

CONN_PCIE_MINI_D2R_P

TRUE

PP3V3_S3_BT_F

TRUE

SYNC_MASTER=K24_MLB

FUNC TEST

SYNC_DATE=02/04/2009

I397

I396

I395

I393

I392

I391

I390

I389

I388

I387

I386

I385

I383

I382

I381

I380

I379

I378

I377

I376

I375

I374

I372

I371

I370

I369

I368

I366

I365

I364

I363

I362

I361

I360

I359

I358

I357

I355

I354

I353

I352

I351

I350

I349

I348

I347

I346

I345

I344

I343

I342

I341

I340

I339

I338

I337

I336

I335

I334

I333

I332

I331

I330

I329

I328

I327

I326

I322

I321

I320

I319

I318

I317

I315

I314

I313

I312

I308

I307

I305

I304

I303

I302

I301

I300

I299

I298

I297

I295

I294

I293

I292

I290

I289

I288

I287

I285

I284

I283

I282

I281

I280

I279

I278

I276

I275

I274

I273

I272

I271

I270

I269

I268

I267

I266

I265

I264

I262

I261

I260

I259

I258

I257

I256

I255

I254

I253

I252

I251

I250

I249

I248

I247

I246

I245

I239

I238

I237

I231

I230

I229

I228

I227

I226

I16

I15

I12

55

53 52

54 53

65 18

72 65 18

8

67 63 36 32 21

45 7

37 36

44

65 7

44

72 65 18

8 7

44

8

44

55

72 65 18

44

47 34 7

72 34

72 65

65 18

72 65 18

55

44

36 34

72 34

68 65

8

8 7

8

8 7

8

8 7

8

34 7

30 7

25 22 21

68 65 47 7

49

63 37 36 21

63 57 36

68 65

65 7

47 34 7

8

72 30

73 65

54 53

43

54 53

73 30

55

56 55

8 7

75 39

72 34

30 17

72 30

72 65

68 65

30 7

72 30

53 52

43

72 34

34 7

72 34

34

72 34

44

45 44

65 7

65

45 44

30

45 7

68 65 47 7

45 44

45

45 44

73 65

65 7

68 65

45 44

75 39

8 7

44

45 44

30

73 30

72 30

30

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

"S3" RAILS

"S0,S0M" RAILS

DIGITAL GROUND

& CPU VTT SENSING RES.)

(BEFORE HIGH SIDE SENSING RES.)

(MCP VCORE AFTER SENSE RES)

(AFTER HIGH SIDE CPU VCORE

43 mA (A01)

127 mA (A01)

206 mA (A01)

57 mA (A01)

206 mA (A01)

(CPU VCORE PWR)

"ENET" RAILS

"S5" RAILS

PEX & SATA AVDD/DVDD aliases

"G3H" RAILS

8 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

VOLTAGE=0V

GND

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

=PP3V3_S3_BT

=PP3V42_G3H_HALL

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_TPAD

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_ONEWIRE

=PPVIN_S5_SMCVREF

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP5V_S3_TPAD

=PP5V_S3_DEBUG_ISNS

=PP3V3_S0_IMVP

=PP3V3_S0_FAN_RT

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_XDP

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_A

=PP1V5_S3_P1V5S0FET

=PPBUS_G3H

=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_VMON

=PP1V05_S0_MCP_HDMI_VDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0

=PP3V3R1V8_S0_MCP_IFP_VDD =PP1V8_S0_AUDIO

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S0

=PP1V5_S0_MCP_PLL_VLDO

=PP1V5_S0_MEM_MCP

=PP3V3_S0_CPUVTTISNS

=PPSPD_S0_MEM_B

=PPVCORE_S0_CPU_VSENSE

=PPVCORE_S0_CPU

=PP3V3_S0_MCPTHMSNS =PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_SATA_DVDD0

=PPCPUVTT_S0_REG

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_UF

MIN_NECK_WIDTH=0.2 mm

=PP3V3_ENET_PHY

=PP3V3_ENET_MCP_RMGT

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V2R1V05_ENET

=PP1V05_ENET_FET

=PP1V5_S0_FET

=PP5V_S0_FAN_RT

=PPMCPCORE_S0_REG

=PP1V8R1V5_S0_MCP_MEM

=PP3V3_S3_FET

=PPVCORE_S0_CPU_REG

=PP3V3_S5_MCP_GPIO

=PPVTT_S3_DDR_BUF

=PP1V05_ENET_MCP_PLL_MAC

=PP1V5_S0_CPU =PP1V5_S0_VMON

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_LCD

=PP3V3_S5_MEMRESET

=PP3V3_S5_P1V05ENETFET

=PP3V3_S5_P1V05S5

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S0FET

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S5

=PP3V42_G3H_REG

=PP3V3_ENET_FET

MAKE_BASE=TRUE

PP1V05_S0_MCP_SATA_AVDD

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_SATA_AVDD0

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

=PP0V75_S0_REG

=PP1V05_S5_REG

=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET

=PP18V5_G3H_CHGR

PPBUS_G3H_CPU_ISNS

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S0_MCP

MAKE_BASE=TRUE

PP0V75_S0

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PPCPUVCORE_VTT_ISNS

=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP

PPVTT_S3_DDR_BUF

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_DPCONN

=PP3V3_S0_VMON

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_P1V8S0

=PP3V3_S0_MCP_PLL_UF

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_DAC_UF

=PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_SATA_DVDD

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

MAKE_BASE=TRUE

VOLTAGE=1.05V

=PP1V05_S0_CPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.3 MM

PPVCORE_S0_CPU

=PP3V3_S3_SMS

=PPBUS_G3HRS5

=PPVIN_S3_5VS3

=PPBUS_S0_LCDBKLT

=PPVIN_S0_MCPCORE

=PPVIN_S5_3V3S5

=PPCPUVCORE_VTT_ISNS_R

=PP18V5_DCIN_CONN

=PPVIN_S5_1V5S30V75S0

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

=PP5VRT_S0_FET

=PP5V_S0_HDD

=PP5V_S0_DP_AUX_MUX

=PP5V_S0_VMON

=PP5V_S0_MCPREG

=PP5VLT_S0_FET

=PP5V_S0_CPU_IMVP

MIN_LINE_WIDTH=0.30 MM

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.20 MM

PP5VRT_S0

=PPVCORE_S0_MCP_VSENSE

=PP3V3_S0_PWRCTL

=PP3V3_S0_ODD

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=3.3V

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_AUDIO

=PP3V3_S0_LCD

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE

PP5VLT_S0

=PPSPD_S0_MEM_A

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_MCP

=PP3V3_S0_SMBUS_MCP_0

=PP5V_S3_P5VLTS0FET

=PP3V3_S0_FET

=PP5V_S0_LPCPLUS

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_MCPDDRISNS

=PP5V_S3_SYSLED

PP18V5_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=18.5V

=PP3V42_G3H_CHGR

=PP3V3_S5_SMC

=PP3V42_G3H_RTC_D

=PP3V3_S0_SMC

=PP5V_S3_1V5S30V75S0 =PP5V_S3_AUDIO

=PP5V_S3_MCPDDRFET

=PP5V_S3_EXTUSB

=PP5V_S3_AUDIO_AMP

=PP5V_S3_CAMERA

=PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_ODD

=PP5V_S3_P5VRTS0FET

=PP5V_S3_DEBUG_ADC_AVDD

=PP5V_S3_VTTCLAMP

=PP5V_S3_REG

=PP1V05_ENET_PHY

=PP1V05_ENET_MCP_RMGT

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V1R1V05_S5

MAKE_BASE=TRUE

=PP1V8_S0_REG

=PP3V3_S5_ROM

=PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_PWRCTL

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_PEX_AVDD0

=PP5V_S0_CPUVTTS0

=PP1V5_S3_REG

MAKE_BASE=TRUE

PP1V5_S3

MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V

=PP1V5_S3_MEM_B

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

=PP3V3_S3_TPAD

=PP3V3_S3_VREFMRGN

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_WLAN

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_A_S3

SYNC_DATE=02/04/2009

Power Aliases

SYNC_MASTER=K24_MLB

30

55

7

38

44

35

55

37

63

39

45

47

59

43

39

13

29

27

64

56

62

63

24 18

7

24 18

49

7

62

28

41

28

40

12 11

42

64

27

28

23 8 17

62 23

23 8 20

61

31

23 18

7 32

64

43

60

23 16

64

59

20 18

58 26

23

12 11

63

39

67

65

29

32

62

32

64

57 7

55

32

23

17

20

23

58

62

23 22

32

56

23 22 21

7

41

61

59

42

67

63

39

62

23

23 21

21 19 18

24

23 8

23

23 8

23 22

23 22 14

7

13 12 11 10

7

46

40

57

69

60

57

41

55

58

7

64

34

66

63

60

64

59

7

40

63

34

7

24

54 53 49

65

7

27

7

39

64

38

62

41

37

56

37 36

25

37

58

53 51 49

64

35

52

65

47

34

64

47

64

57

31

23 18

7

62

48 38

23 22

25

63

20

17

61

58

7

28

7

44

26

7

21

30

39

58

39

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MLB MOUNTING (TO TOPCASE) SCREW HOLES

(870-1820 )

EMI THINBC POGO PINS

EMI TALL POGO PINS

(870-1698 )

EMI IO MEDIUM POGO PINS

FAN STANDOFF

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

HEATSINK STANDOFFS

LVDS CONNECTOR HOLE

BELOW MCP

(870-1794 )

LEFT OF CPU

CPU VCORE ALIASES

MISC MCP79 ALIASES

DP HOTPLUG PULL-DOWN

UNUSED USB PORTS

0 0 1

1 1 1

0 1 0

0 0 0

0 1 1 1 0 0 1 0 1 1 1 0

266

(RSVD)

100

133

333

200

(166)

(400)

BSEL<2..0>

UNUSED CRT & TV-OUT INTERFACE

UNUSED GPU LANES

UNUSED ADDRESS PINS

SO-DIMM ALIASES

DACS ALIASES

PCI-E ALIASES

ABOVE CPU

SMC ALIASES

USB ALIASES

LAN ALIASES

CPU FSB FREQUENCY STRAPS

ETHERNET ALIASES

FSB MHZ

UNUSED FIREWIRE LANE

UNUSED EXPRESS CARD LANE

LVDS ALIASES

BELOW CPU

9 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

USB_MINI_N

USB_CARDREADER_P

USB_EXTC_N

USB_EXCARD_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

PCIE_CLK100M_FW_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_PRSNT_L

FW_PME_L

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_P

GMUX_JTAG_TDO

GMUX_JTAG_TCK_L

CPU_PECI_MCP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATA_N3

PM_SLP_RMGT_L

MAKE_BASE=TRUE

RTL8211_VDDREG

MAKE_BASE=TRUE

=P3V3ENET_EN

=PP3V3_ENET_PHY_VDDREG

TP_RTL8211_CLK125

LVDS_IG_A_DATA_P<3>

RTL8211_CLK125

MAKE_BASE=TRUE

MEM_B_A<15>

=P1V05ENET_EN

=RTL8211_REGOUT

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

MAKE_BASE=TRUE

CPU_BSEL<0:2>

USB_EXTD_P

USB_EXCARD_P

USB_MINI_P

USB_EXTD_N

TP_USB_CARDREADER_P

MAKE_BASE=TRUE

TP_USB_IR_P

MAKE_BASE=TRUE

TP_USB_CARDREADER_N

MAKE_BASE=TRUE

TP_USB_EXTC_N

CRT_IG_VSYNC

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_N

MAKE_BASE=TRUE

CARDREADER_RESET

TP_CARDREADER_RESET

MAKE_BASE=TRUE

GMUX_JTAG_TMS

MCP_GPIO_4

MAKE_BASE=TRUE

MIKEY_MIC_LOAD_DET

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<3:0>

GMUX_JTAG_TDI

TP_USB_EXTC_P

MAKE_BASE=TRUE

TP_USB_EXTD_N

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_IG_B_DATA_N<3:0>

TP_USB_EXCARD_P

MAKE_BASE=TRUE

TP_USB_EXCARD_N

TP_USB_MINI_N

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

MAKE_BASE=TRUE

=PEG_D2R_P<15:0>

=PEG_D2R_N<15:0>

=PEG_R2D_C_N<15:0>

=PEG_R2D_C_P<15:0>

MAKE_BASE=TRUE

TP_FW_PME_L

IMVP6_NTC

TP_IMVP6_NTC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_B_COMP_PB

IMVP6_VR_TT

TP_SMC_SYS_KBDLED

MAKE_BASE=TRUE

SMC_SYS_KBDLED

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_P

USB_EXTC_P

NC_LVDS_IG_A_DATA_P3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_P

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15:0>

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_N

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_R2D_C_N

MAKE_BASE=TRUE

TP_PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_P

TP_PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

PCIE_EXCARD_R2D_C_P

PEG_CLK100M_N

=MCP_MII_RXER

NC_LVDS_IG_B_DATA_P<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

=MCP_MII_COL

PEG_CLK100M_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

TP_MEM_A_A15

MAKE_BASE=TRUE

TP_MEM_B_A15

MCP_TV_DAC_VREF

MCP_CLK27M_XTALOUT

MEM_A_A<15>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_TV_DAC_VREF

MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_TV_DAC_RSET

TP_PEG_PRSNT_L

MAKE_BASE=TRUE

MCP_CLK27M_XTALIN

MCP_MII_PD

MAKE_BASE=TRUE

=MCP_MII_CRS

NC_PEG_D2R_N<15:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

PEG_PRSNT_L

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDI

MAKE_BASE=TRUE

TP_GMUX_JTAG_TCK_L

=DVI_HPD_GMUX_INT

PCIE_CLK100M_FW_N

HPLUG_DET2

MAKE_BASE=TRUE

=MCP_BSEL<0:2>

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

TP_EXCARD_CLKREQ_L

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_N

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_N

TP_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

TP_IMVP6_VR_TT

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDO

MAKE_BASE=TRUE

TP_GMUX_JTAG_TMS

MAKE_BASE=TRUE

TP_USB_MINI_P

=RTL8211_ENSWREG

FW_CLKREQ_L

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_P

TP_FW_CLKREQ_L

MAKE_BASE=TRUE

TP_USB_IR_N

MAKE_BASE=TRUE

USB_IR_N

USB_CARDREADER_N

USB_IR_P

MAKE_BASE=TRUE

TP_USB_EXTD_P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_N

SYNC_DATE=02/04/2009

SIGNAL ALIAS

SYNC_MASTER=K24_MLB

NOSTUFF

SM

2.0DIA-MLB-THIN-BC-K84

ZS0920

1

OMIT

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0919

1

OMIT

2.0DIA-MLB-THIN-BC-K84

SM

ZS0918

1

OMIT

2.0DIA-MLB-THIN-BC-K84

SM

ZS0917

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

OMIT

ZS0912

1

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

SM

ZS0913

1

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

SM

ZS0914

1

OMIT

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0915

1

OMIT

2.0DIA-MLB-THIN-BC-K84

SM

ZS0916

1

OMIT

3P2R2P7

Z0905

1

OMIT

3P2R2P7

Z0913

1

2.0DIA-MED-EMI-MLB-K84

OMIT

SM

ZS0911

1

OMIT

SM

2.0DIA-MED-EMI-MLB-K84

ZS0909

1

OMIT

2.0DIA-MED-EMI-MLB-K84

SM

ZS0908

1

OMIT

SM

2.0DIA-MED-EMI-MLB-K84

ZS0903

1

2.0DIA-MED-EMI-MLB-K84

OMIT

SM

ZS0902

1

OMIT

2.0DIA-MED-EMI-MLB-K84

SM

ZS0901

1

OMIT

2.0DIA-MED-EMI-MLB-K84

SM

ZS0900

1

OMIT

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0910

1

402

MF-LF

5% 1/16W

22

R0931

1

2

OMIT

3P2R2P7

Z0906

1

3P2R2P7

OMIT

Z0907

1

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

SM

ZS0907

1

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

SM

ZS0904

1

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

SM

ZS0906

1

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

SM

ZS0905

1

OMIT

3P2R2P7

Z0910

1

402

20K

1/16W

5% MF-LF

R0940

1

2

70 10 14

1/16W

5%

402

47K

MF-LF

R0930

1

2

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0904

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0901

1

OMIT

3P2R2P7

Z0911

1

20

73 20

20

17

19

72 17

17

14

21 32

31

18

28

32

31

18

20

18

17

19

21 54

18

19

18

17

59

36

20

17

72 17

17

18

17

18

27

18

17

18

17

18

17

31

17

73 20

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

CPU JTAG Support

PLACEMENT_NOTE (all 4 resistors):

10 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

XDP_TDI

XDP_TDO

XDP_TMS

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1>

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

TP_CPU_TEST5

TP_CPU_TEST3

TP_CPU_TEST6

TP_CPU_TEST7

FSB_CPUSLP_L CPU_PSI_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_N<3> FSB_DSTB_L_P<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

XDP_TRST_L

XDP_TCK

CPU_GTLREF CPU_TEST1 CPU_TEST2

CPU_TEST4

CPU_COMP<1>

CPU_COMP<0>

CPU_COMP<2> CPU_COMP<3>

=PP1V05_S0_CPU

FSB_LOCK_L

CPU_INIT_L

FSB_A_L<3> FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD_B2

TP_CPU_RSVD_V3

TP_CPU_RSVD_T2

TP_CPU_RSVD_N5

TP_CPU_RSVD_M4

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

CPU_THERMD_N

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_A20M_L CPU_FERR_L CPU_IGNNE_L

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

FSB_A_L<6>

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

CPU FSB

FCBGA

OMIT

PENRYN

U1000

N3

P5

P2

L2

P4

P1

R1

Y2

U5

R3

W6

A6

U4

Y5

U1

R4

T5

T3

W2

W5

Y4

J4

U2

V4

W3

AA4

AB2

AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3

AD1

AC4

G5

F1

C20

E1

H5

F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

AC2

AC1

D21

K3

H2

K2

J3

L1

C1

F3

F4

G3

M4

N5

T2

V3

B2

F6

D2

D22

D3

A3

D5

AC5

AA6

AB3

A24

B25

C7

AB5

G2

AB6

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

54.9

1/16W MF-LF

1%

402

R1092

1 2

FCBGA

PENRYN

OMIT

U1000

B22

B23

C21

R26

U26

AA1

Y1

E22

F24

J24

J23

H22

F26

K22

H23

N22

K25

P26

R23

E26

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

G22

T25

N25

Y22

AB24

V24

V26

V23

T22

U25

U23

F23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

AE24

AD24

G25

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

E25

AC22

AD23

AF22

AC23

E23

K24

G24

H25

N24

U22

AC20

E5

B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6

D7

C23

D25

C24

AF26

AF1

A26

C3

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

NO STUFF

X5R

0.1uF

10% 16V

402

C1014

1

2

402

MF-LF

1K

5% 1/16W

NO STUFF

R1012

1

2

1%

MF-LF

1/16W

649

402

R1094

1 2

70 14

1%

MF-LF

1/16W

54.9

402

R1093

1 2

1%

MF-LF

1/16W

54.9

402

R1091

1 2

54.9

1/16W MF-LF

1%

402

R1090

1 2

54.9

402

MF-LF

1%

1/16W

R1001

1

2

NO STUFF

1/16W

5%

MF-LF

1K

402

R1011

1

2

NO STUFF

5%

MF-LF

1/16W

0

402

R1010

1 2

70 14

76 42

70 13 10

70 14

70 14 13

70 14

70 37 14

76 42

70 37 14

25 13

70 13 10

70 13

70 14

70 9

70 14

70 14 13

59

70 14

70 59 14

70 14

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

R1020

1

2

Place within 12.7mm of CPU

402

MF-LF

1/16W

1%

54.9

R1021

1

2

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

R1022

1

2

Place within 12.7mm of CPU

54.9

1% 1/16W MF-LF

402

R1023

1

2

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

1%

MF-LF

2.0K

1/16W

402

R1006

1

2

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

402

1K

MF-LF

1% 1/16W

R1005

1

2

68

5% 1/16W MF-LF

402

R1002

1

2

1% 1/16W

54.9

MF-LF

402

R1000

1

2

70 13 10

70 26

70

13 12 11 8

70

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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345678

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8 7 5 4 2 1

2500 mA (after VCC stable)

4500 mA (before VCC stable)

(Socket-P KEY)

41 A (SV HFM)

130 mA

(CPU CORE POWER)

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

23 A (LV Design Target)

44 A (SV Design Target)

(BR1#)

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

30.4 A (SV LFM)

11 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VCCSENSE_N

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

CPU Power & Ground

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

R1100

1

2

OMIT

PENRYN

FCBGA

U1000

A4

A8

B11

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

B13

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

B16

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

B19

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

B21

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

B24

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

C5

AF21

A25

AF25

B1

C8

C11

C14

A11

C16

C19

C2

C22

C25

D1

D4

D8

D11

D13

A14

D16

D19

D23

D26

E3

E6

E8

E11

E14

E16

A16

E19

E21

E24

F5

F8

F11

F13

F16

F19

F2

A19

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

A23

J2

J5

J22

J25

K1

K4

K23

K26

L3

L6

AF2

L21

L24

M2

M5

M22

M25

N1

N4

N23

N26

B6

P3

P6

P21

P24

R2

R5

R22

R25

T1

T4

B8

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

PENRYN

OMIT

FCBGA

U1000

A7

A9

B9

B10

B12

B14

B15

B17

B18

B20

C9

C10

A10

C12

C13

C15

C17

C18

D9

D10

D12

D14

D15

A12

D17

D18

E7

E9

E10

E12

E13

E15

E17

E18

A13

E20

F7

F9

F10

F12

F14

F15

F17

F18

F20

A15

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

A17

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

A18

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

A20

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

B7

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

B26

C26

G21

V6

R21

R6

T21

T6

V21

W21

J6

K6

M6

J21

K21

M21

N21

N6

AF7

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AE7

70 59

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

R1101

1

2

70 59

12 11 8

12 8

13 12 10 8

12 11 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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Apple Inc.

PAGE

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A

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8 7 5 4 2 1

PLACEMENT_NOTE (C1200-C1219):

1x 10uF, 1x 0.01uF

1x 330uF, 6x 0.1uF 0402

SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231

CPU VCore HF and Bulk Decoupling

REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)

4X 330UF. 20X 22UF 0805

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

PLACEMENT_NOTE (C1240-C1243):

12 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PPVCORE_S0_CPU

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU Decoupling

SYNC_DATE=03/30/2009

SYNC_MASTER=K24_MLB

Place on secondary side.

CRITICAL

D2T-SM

470UF-4MOHM

2.0V

20%

POLY-TANT

C1243

1

23

CRITICAL

470UF-4MOHM

Place on secondary side.

D2T-SM

POLY-TANT

20%

2.0V

C1242

1

23

470UF-4MOHM

CRITICAL

Place on secondary side.

D2T-SM

20%

2.0V POLY-TANT

C1241

1

23

Place on secondary side.

470UF-4MOHM

CRITICAL

NOSTUFF

20%

D2T-SM

POLY-TANT

2.0V

C1240

1

23

6.3V

10uF

603

X5R

20%

C1250

1

2

16V

PLACEMENT_NOTE=Place C1281 near CPU pin B26.

10%

402

CERM

0.01UF

C1251

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1218

1

2

10V

402

0.1UF

CERM

20%

C1266

1

2

0.1UF

CERM

10V

402

20%

C1265

1

2

10V

402

0.1UF

CERM

20%

C1264

1

2

402

CERM

10V

0.1UF

20%

C1263

1

2

10V

402

0.1UF

CERM

20%

C1262

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1217

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1215

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1209

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1205

1

2

10V

402

0.1UF

20%

CERM

C1261

1

2

CRITICAL

6.3V

Place inside socket cavity on secondary side.

CERM-X5R

20%

805

22UF

C1210

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1200

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1219

1

2

CERM-X5R

6.3V

20%

805

22UF

CRITICAL

Place inside socket cavity on secondary side.

C1211

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1212

1

2

CRITICAL

Place inside socket cavity on secondary side.

22UF

805

20%

6.3V CERM-X5R

C1213

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1201

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1202

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1207

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1203

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1208

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1214

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1216

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1204

1

2

330UF

20%

2.5V TANT CASE-B2-SM

CRITICAL

C1260

1

2

CRITICAL

CERM-X5R

6.3V

20%

22UF

Place inside socket cavity on secondary side.

805

C1206

1

2

11 8

13 11 10 8

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN IN

OUT OUT OUT

OUT

NC

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

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PAGE TITLE

C

A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

(998-2515)

518S0774

SDA

TCK1

OBSDATA_B3

OBSFN_C1

OBSDATA_A1

OBSDATA_B1

OBSDATA_B2

VCC_OBS_AB

HOOK3

ITPCLK#/HOOK5

RESET#/HOOK6

MCP79-specific pinout

OBSDATA_C3

OBSDATA_D2 OBSDATA_D3

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

OBSDATA_C2

TRSTn

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

DBR#/HOOK7

TDO

HOOK2

OBSDATA_D0

VCC_OBS_CD

Direction of XDP module

OBSDATA_A2

OBSFN_A1

OBSDATA_A0

OBSFN_B1

OBSDATA_D1

ITPCLK/HOOK4

XDP_PRESENT#

OBSFN_D1

TMS

HOOK1

SCL

OBSFN_D0

Please avoid any obstructions

OBSFN_C0

TCK0

PWRGD/HOOK0

OBSDATA_C1

TDI

OBSDATA_C0

OBSDATA_A3

OBSFN_B0

OBSDATA_B0

OBSFN_A0

ON ODD-NUMBERED SIDE OF J1300

13 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

CPU_PWRGD

FSB_CPURST_L

XDP_DBRESET_L

XDP_TDO

XDP_TRST_L

XDP_TMS

XDP_TDI

JTAG_MCP_TDO

MCP_DEBUG<0>

MCP_DEBUG<3>

JTAG_MCP_TDI

MCP_DEBUG<4>

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_PWRGD

TP_XDP_OBSDATA_B3

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

XDP_BPM_L<1>

XDP_BPM_L<3> XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_BPM_L<5>

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

FSB_CLK_ITP_P

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TMS

TP_XDP_OBSFN_B0

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

TP_XDP_OBSFN_B1

XDP_BPM_L<0>

=PP1V05_S0_CPU

JTAG_MCP_TRST_L

=PP3V3_S0_XDP

MCP_DEBUG<1>

MCP_DEBUG<2>

TP_XDP_OBSDATA_B2

XDP_OBS20

eXtended Debug Port(MiniXDP)

SYNC_MASTER=K24_MLB

SYNC_DATE=02/25/2009

OMIT

CRITICAL

F-ST-SM

DF40C-60DS-0.4V

J1300

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48 49

5

50 51 52 53 54 55 56 57 58 59

6

60

7 8 9

21

70 10

19

25 10

70 10

70 14

21

73 19

21

70 10

1/16W

5%

1K

XDP

MF-LF

402

PLACEMENT_NOTE=Place close to CPU to minimize stub.

R1303

1 2

70 14 10

70 10

402

16V

XDP

0.1uF

10%

X5R

C1301

1

2

X5R

10% 16V

0.1uF

402

XDP

C1300

1

2

402

1/16W

54.9

MF-LF

1%

XDP

R1315

1

2

73 39 21

1/16W

5%

XDP

MF-LF

402

1K

R1399

1 2

70 14 10

70

12 11 10 8

8

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

IN

BI BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

Loop-back clock for delay matching.

(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)

20 mA 29 mA 15 mA

206 mA

270 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

14 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PM_THRMTRIP_L

FSB_D_L<13>

MCP_BCLK_VML_COMP_GND

FSB_DPWR_L

CPU_DPSLP_L

FSB_D_L<38>

FSB_D_L<43>

FSB_D_L<45>

CPU_DPRSTP_L

CPU_STPCLK_L

FSB_CPUSLP_L

FSB_CPURST_L

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_A20M_L

FSB_CLK_MCP_P FSB_CLK_MCP_N

FSB_CLK_ITP_N

FSB_CLK_ITP_P

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_DEFER_L

FSB_BPRI_L

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

MCP_CPU_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<2>

FSB_RS_L<1>

CPU_PROCHOT_L

CPU_PECI_MCP

FSB_TRDY_L

FSB_LOCK_L

FSB_HITM_L

FSB_HIT_L

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_ADSTB_L<0>

FSB_A_L<35>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

=PP1V05_S0_MCP_FSB

PP1V05_S0_MCP_PLL_FSB

FSB_D_L<14>

FSB_D_L<7>

FSB_A_L<10>

FSB_A_L<25>

FSB_A_L<34>

FSB_A_L<33>

FSB_DBSY_L FSB_DRDY_L

FSB_BNR_L

FSB_RS_L<0>

CPU_FERR_L

FSB_BREQ0_L

FSB_ADS_L

FSB_BREQ1_L

=PP1V05_S0_MCP_FSB

=MCP_BSEL<2>

=MCP_BSEL<0>

=MCP_BSEL<1>

SYNC_MASTER=K24_MLB

MCP CPU Interface

SYNC_DATE=04/06/2009

5%

62

MF-LF 402

1/16W

R1416

1

2

BGA

(1 OF 11)

MCP79-TOPO-B

OMIT

U1400

AK41

AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35

AG35

AG39

AE33

AG37

AG38

AG34

AN38

AL39

AG33

AL33

AF41

AJ33

AN36

AJ35

AJ37

AJ36

AJ38

AL37

AL34

AN37

AC34

AJ34

AL38

AL35

AN34

AR39

AN35

AE38

AE34

AC37

AE37

AE35

AB35

AD42

AE36

AK35

AD43

AA41

AE40

AL32

F41

D42

F42

AM42

AM43

Y43

W42

R42

T39

T42

T41

R41

T43

W35

AA37

W33

W34

Y40

AA36

AA34

AA38

AA35

U38

U36

U35

U33

U34

W38

W41

R33

U37

N34

N33

R34

R35

P35

R39

R37

R38

Y39

L37

L39

L38

N36

N38

J39

J38

J37

L42

M42

V42

P41

N41

N40

M40

H40

K42

H41

L41

H43

H42

Y41

K41

J40

H39

M43

Y42

P42

U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33

AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42

AD40

AH39

AH42

AF42

AC43

AG41

E41

AJ41

AH43

AC38

AA33

AC39

AC33

AC35

H38

AC41

AB41

AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

5%

MF-LF 402

1/16W

150

NO STUFF

R1440

1

2

1%

54.9

MF-LF

402

1/16W

R1410

1

2

5%

62

MF-LF

402

1/16W

R1415

1

2

1/16W

NO STUFF

MF-LF

402

5%

1K

R1420

1

2

1/16W

5%

MF-LF

402

NO STUFF

1K

R1421

1

2

MF-LF

1/16W

5%

402

1K

NO STUFF

R1422

1

2

MF-LF 402

1% 1/16W

49.9

R1435

1

2

1/16W

1%

402

MF-LF

49.9

R1430

1

2

49.9

MF-LF

402

1%

1/16W

R1431

1

2

MF-LF 402

1% 1/16W

49.9

R1436

1

2

70 10

70 37 10

9

70 59 10

70 10

70 13 10

70 10

70 13

70 10

70 13 10

70 10

9

70

23 22 14 8 23

70

23 22 14 8

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

15 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

TP_MEM_B_CLK2P

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MCP Memory Interface

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

71 28

(3 OF 11)

OMIT

MCP79-TOPO-B

BGA

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

71 28

71 27

(2 OF 11)

OMIT

MCP79-TOPO-B

BGA

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

17 mA 12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA

TP or NC for DDR2.

39 mA

87 mA (A01)

16 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_MEM_B_CKE<3>

TP_MEM_B_CKE<2>

TP_MEM_B_CS_L<2>

MCP_MEM_RESET_L

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_COMP_GND

TP_MEM_A_CLK4N

TP_MEM_A_CLK3P

TP_MEM_A_ODT<2> TP_MEM_A_ODT<3>

TP_MEM_A_CKE<2> TP_MEM_A_CKE<3>

TP_MEM_A_CLK5P TP_MEM_A_CLK5N

TP_MEM_A_CLK4P

TP_MEM_A_CLK3N

TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3>

PP1V05_S0_MCP_PLL_CORE

TP_MEM_B_CLK5P TP_MEM_B_CLK5N

TP_MEM_B_CLK4P TP_MEM_B_CLK4N

TP_MEM_B_CLK3P TP_MEM_B_CLK3N

TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2> TP_MEM_B_ODT<3>

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_COMP_VDD

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

MCP Memory Misc

29

BGA

OMIT

MCP79-TOPO-B

(4 OF 11)

U1400

AA22

AA39

AB22

AB7

AD22

AE20

AF24

AG24

AH35

AK7

AM28

AP12

AT25

AP30

AR36

AU10

F28

BC21

AY9

BC9

D34

F24

G30

G32

H31

K7

M38

M5

M6

M7

M9

N39

N8

P10

P33

P34

P37

P4

P40

P7

R36

R40

R43

R5

T10

T18

T20

AK11

T24

T26

T33

T34

T35

T37

T38

T6

T7

T9

U18

U20

U22

V10

V34

W5

AV23

AN25

BA30

BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17

AR15

BC16

BA13

AM41

AN41

AN17

AN15

AY16

BC13

AY32

U27

U28

T27

T28

AM17

AN20

AN24

AT17

AP16

AN22

AP20

AP24

AV16

AR16

AR20

AM19

AR24

AW15

AP22

AP18

AU16

AN18

AU24

AT21

AY29

AV24

AM21

AU20

AU22

AW27

BC17

AV20

AY17

AY18

AM15

AU18

AY25

AM23

AY26

AW19

AW24

BC25

AL30

AM31

AM25

AM27

AM29

AN16

BC29

40.2

1/16W

1%

402

MF-LF

R1611

1

2

MF-LF

402

1/16W

40.2

1%

R1610

1

2

23 16 8

71

23

23 16 8

71

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Int PU (S5)

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU

84 mA (A01)

Int PU

57 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

17 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PCIE_MINI_PRSNT_L

FW_CLKREQ_L

TP_PE4_CLKREQ_L TP_PE4_PRSNT_L

PCIE_FW_PRSNT_L

CARDREADER_RESET GMUX_JTAG_TDO

PCIE_WAKE_L

PCIE_MINI_D2R_P PCIE_MINI_D2R_N

PCIE_FW_D2R_P PCIE_FW_D2R_N

TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN

PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N

=PP1V05_S0_MCP_PEX_DVDD0

GMUX_JTAG_TCK_L

AUD_IP_PERIPHERAL_DET

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_P

=PEG_D2R_N<1>

=PEG_D2R_P<1>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_P<5>

=PEG_D2R_P<3>

=PEG_D2R_N<7>

=PEG_D2R_N<6> =PEG_D2R_P<7>

=PEG_D2R_N<5>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_P<10>

=PEG_D2R_P<9>

=PEG_D2R_P<8>

=PEG_D2R_N<10>

=PEG_D2R_N<12>

=PEG_D2R_N<11>

=PEG_D2R_P<13>

=PEG_D2R_P<11>

=PEG_D2R_P<12>

=PEG_D2R_N<15>

=PEG_D2R_N<14> =PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_N<13>

PEG_PRSNT_L

MCP_PEX_CLK_COMP

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1> =PEG_R2D_C_N<1>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<2> =PEG_R2D_C_N<2>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3> =PEG_R2D_C_N<3>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<6> =PEG_R2D_C_P<7> =PEG_R2D_C_N<7>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<10> =PEG_R2D_C_N<10>

=PEG_R2D_C_P<12> =PEG_R2D_C_N<12>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

PCIE_CLK100M_MINI_P

PEG_CLK100M_P PEG_CLK100M_N

PCIE_CLK100M_FW_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N

PCIE_MINI_R2D_C_P

PCIE_RESET_L

TP_PCIE_CLK100M_PE6N

PCIE_FW_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2>

=PEG_D2R_N<0>

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<2>

=PEG_D2R_P<0>

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

MINI_CLKREQ_L

PCIE_EXCARD_PRSNT_L

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

SYNC_DATE=04/06/2009

MCP PCIe Interfaces

SYNC_MASTER=K24_MLB

9

25

PLACEMENT_NOTE=Place within 12.7mm of U1400

NO STUFF

1/16W

1%

MF-LF 402

2.37K

R1710

1

2

9

72 30

9

72 9

72 30

9

30

9

72 9

30 7

9

72 30

9

BGA

OMIT

(5 OF 11)

MCP79-TOPO-B

U1400

Y12

AC12

AD12

V12

W12

AA12

AB12

M12

P12

R12

N12

T12

U12

M13

N13

P13

T17

W19

U17

V19

W16

W17

W18

U16

T19

U19

T16

C9

D11

E11

E7

F7

L8

L9

L6

L7

N10

N11

P9

N9

N6

N7

N4

N5

C7

D7

F6

E6

F5

E5

E3

E4

D3

C3

H5

G5

J6

J7

J4

J5

L10

L11

D4

C5

J1

H1

J3

J2

K3

K2

L3

L4

M3

M4

M1

M2

B4

C4

A3

A4

B2

B3

D1

C1

E1

D2

F2

E2

F4

F3

H4

G3

H2

H3

F11

G11

J9

K9

G9

H9

E9

F9

G7

H7

C8

D8

A8

B8

B7

A7

C6

B6

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

D5

D9

E8

C10

M15

B10

L16

L18

M16

M18

M17

M19

A11

K11

8

54

72

23

8

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

OUT

IN IN IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

In MCP79 these pins have undocumented internal

GPIOs 57-59 (if LCD panel is used):

by default, pull-downs (1K or stronger) must be used.

pull-ups (~10K to 3.3V S0). To ensure pins are low

Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.

=DVI_HPD_GMUX_INT:

Alias to DVI_HPD for systems using IFP for DVI.

(See below)

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: 20K pull-down required on DP_HPD_DET.

level-shifters.

NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without

Interface Mode

DP_IG_ML_P/N<0>

DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

131 mA (A01)

83 mA (A01)

MII, RGMII products will enable

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

RGB DAC Disable:

TV / Component

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

LVDS: Power +VDD_IFPx at 1.8V

95 mA (A01)

16 mA (A01)

8 mA

DP_IG_AUX_CH_P/N

=MCP_HDMI_HPD

TMDS_IG_HPD

=MCP_HDMI_DDC_DATA

=MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_TXD_P/N<1>

=MCP_HDMI_DDC_CLK

MCP Signal

=MCP_HDMI_TXD_P/N<0>

=MCP_HDMI_TXC_P/N

TMDS/HDMI

TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2>

TMDS_IG_DDC_DATA

TP_DP_IG_AUX_CHP/N

DP_IG_DDC_CLK

DP_IG_ML_P/N<2> DP_IG_ML_P/N<1>

DP_IG_ML_P/N<3>

DisplayPort

5 mA (A01)

RGB ONLY

avoids a leakage issue since

feature via software. This

NOTE: All Apple products set strap to

Network Interface Select

Interface

RGMII

MII

0

1

ENET_TXD<0>

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all TV_DAC signals.

TV DAC Disable:

Y / Y

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all RGB_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.

103 mA 103 mA

206 mA (A01)

Comp / Pb

MCP79 requires a S5 pull-up.

C / Pr

190 mA (A01, 1.8V)

18 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=DVI_HPD_GMUX_INT

LVDS_IG_BKL_PWM

MCP_CLK27M_XTALOUT

TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF

LPCPLUS_GPIO

=PP1V05_ENET_MCP_RMGT

=PP3V3_S5_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>

ENET_CLK125M_TXCLK ENET_TX_CTRL

MCP_MII_VREF

CRT_IG_VSYNC

CRT_IG_HSYNC

CRT_IG_B_COMP_PB

=MCP_MII_CRS

=MCP_MII_COL

=MCP_MII_RXER

TP_ENET_PWRDWN_L

ENET_MDC

ENET_RESET_L

ENET_RXD<1> ENET_RXD<2>

ENET_CLK125M_RXCLK ENET_RX_CTRL

ENET_RXD<3>

TP_ENET_INTR_L

ENET_RXD<0>

MCP_TV_DAC_RSET

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_CLK_N

LVDS_IG_B_CLK_P

LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_CLK_P

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_MCP_RGB_BLUE

TP_MCP_RGB_GREEN

TP_MCP_RGB_RED

MCP_DDC_CLK0 MCP_DDC_DATA0

MCP_CLK25M_BUF0_R

ENET_MDIO

=MCP_HDMI_HPD

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

MCP_TV_DAC_VREF

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

MCP_CLK27M_XTALIN

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXC_P

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

MCP_MII_COMP_VDD MCP_MII_COMP_GND

PP3V3_S0_MCP_DAC

=PP3V3R1V8_S0_MCP_IFP_VDD

PP3V3_S0_MCP_VPLL

=PP1V05_S0_MCP_HDMI_VDD

PP1V05_ENET_MCP_PLL_MAC

DP_IG_CA_DET

MCP_HDMI_VPROBE

MCP_HDMI_RSET

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_CLK_N

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_N<0>

MCP Ethernet & Graphics

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

74 31

72 24

74 31

72 24

66

65 7

9

74 31

9

72 65 7

74 31

72 65 7

72 65

74 31

1/16W MF-LF

402

47K

5%

R1820

1

2

38

100K

1/16W

5%

MF-LF

402

R1860

1

2

MF-LF

1/16W

100K

5%

402

R1861

1

2

MF-LF

5% 1/16W

402

10K

R1850

1

2

OMIT

MCP79-TOPO-B

BGA

(6 OF 11)

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16

B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31

F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32

G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39

E37

F40

B26

B27

C27

B22

J23

F23

E28

J24

K24

T23

U23

V23

M29

M28

J32

K32

T25

M27

M26

B40

A39

A40

B39

C39

B38

A41

J22

D21

C21

G23

A23

C22

C23

B23

E24

A24

D24

C26

B24

C24

C25

D25

C36

B36

D36

A36

E36

A35

C37

C38

D38

9

66

1%

402

49.9

MF-LF

1/16W

R1811

1

2

49.9

402

MF-LF

1/16W

1%

R1810

1

2

9

72 24

66

9

72 66

66

69

65

69 68

9

74 31

74 32

74 31

23

23 8

20 8

23 18 8

21 19 8

23 18 8

74

24

24 8

24

24 8

23

OUT

BI BI BI BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

19 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

FW_PWR_EN

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

TP_PCI_GNT0_L TP_PCI_GNT1_L

MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0> TP_PCI_C_BE_L<1> TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR

TP_PCI_SERR_L TP_PCI_STOP_L

TP_PCI_RESET1_L

TP_PCI_CLK0

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

LPC_RESET_L

LPC_PWRDWN_L

PCI_CLK33M_MCP_R

TP_PCI_CLK1

PCI_CLK33M_MCP

MEM_VTT_EN_R

TP_PCI_PERR_L

TP_PCI_AD<10>

TP_PCI_AD<8>

PCI_REQ1_L

PCI_REQ0_L

TP_PCI_INTY_L

TP_PCI_INTW_L

TP_PCI_AD<31>

TP_PCI_AD<30>

TP_PCI_AD<29>

TP_PCI_AD<28>

TP_PCI_AD<27>

TP_PCI_AD<25>

TP_PCI_AD<22>

TP_PCI_AD<19>

TP_PCI_AD<18>

TP_PCI_AD<17>

TP_PCI_AD<16>

TP_PCI_AD<12>

FW_PWR_EN AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L

MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3>

MCP_DEBUG<6> MCP_DEBUG<7>

MCP_RS232_SIN_L

=PP3V3_S0_MCP_GPIO

PM_CLKRUN_L

TP_LPC_DRQ0_L

FW_PME_L

TP_PCI_INTZ_L

GMUX_JTAG_TMS GMUX_JTAG_TDI

TP_PCI_AD<13>

TP_PCI_AD<11>

PM_LATRIGGER_L

TP_PCI_AD<26>

TP_PCI_AD<24>

TP_PCI_AD<23>

MCP_DEBUG<4> MCP_DEBUG<5>

TP_PCI_AD<9>

TP_PCI_AD<15>

TP_PCI_AD<20>

LPC_SERIRQ

TP_PCI_TRDY_L

TP_PCI_INTX_L

TP_PCI_AD<21>

TP_PCI_AD<14>

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

MCP PCI & LPC

9

54

73 13

13

19

9

25

22

5%

1/16W MF-LF

402

R1953

1 2

402

MF-LF1/16W

5%

22

R1952

1 2

402

22

MF-LF1/16W

5%

R1951

1 2

402

22

MF-LF1/16W

5%

R1950

1 2

5%

22

402

MF-LF1/16W

R1960

1 2

10K

5% 1/16W

402

MF-LF

R1961

1

2

19

402

MF-LF1/16W

5%

8.2K

R1992

1 2

8.2K

5%

1/16W MF-LF

402

R1994

1 2

8.2K

5%

1/16W MF-LF

402

R1990

1 2

8.2K

5%

1/16W MF-LF

402

R1991

1 2

8.2K

5%

1/16W MF-LF

402

R1989

1 2

22

5% 1/16W

402

MF-LF

PLACEMENT_NOTE=Place close to pin R8

R1910

1

2

38 36

73 25 38 36

38 36

OMIT

MCP79-TOPO-B

(7 OF 11)

BGA

U1400

AB18

H34

AB20

AB21

AB23

AB24

AB25

AB26

AB27

AB28

AB34

AB37

AB4

AB40

AC22

AC36

AC40

AB33

AC5

AD16

AD17

AD18

AD19

AD20

AD24

AD25

AD26

AD27

AD28

AD33

AD34

U24

U26

U39

U4

U8

V16

V17

V18

V20

V22

V24

V26

V27

V28

V33

V37

V4

V40

V7

W20

W22

W24

W36

W40

W43

Y16

Y17

Y18

Y19

Y20

Y22

Y24

Y25

Y26

Y27

AD3

AD2

AD1

AD5

AE9

AE1

AE2

AD4

AE12

AE5

AE6

AC3

AE10

AC9

AC10

AC11

AA1

AA5

Y5

W3

W6

W4

W7

AC4

V3

W8

V2

W9

U3

W11

U2

U5

U1

U6

AE11

T5

U7

AB3

AC6

AB2

AC7

AC8

AA2

AA3

AA6

AA11

W10

R6

R7

R8

R9

AD11

AA9

Y4

R3

U10

R4

U11

P3

P2

N3

N2

N1

AA10

Y1

AB9

T1

T2

V9

T3

U9

T4

R10

R11

AA7

Y2

Y3

73 38 36

73 25

73 38 36

19

73 19

19

73

73 19

19

21 18 8

BI BI

IN IN IN IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT OUT

IN

OUT OUT

IN IN

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ExpressCard

Bluetooth

External B

External C

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)

43 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

External D

External A

Camera

IR

84 mA (A01)

19 mA (A01)

AirPort (PCIe Mini-Card)

Geyser Trackpad/Keyboard

20 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_USB_10N

USB_BT_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTD_P

USB_MINI_N

USB_MINI_P

USB_EXTA_N

USB_EXTA_P

TP_SATA_D_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN TP_SATA_E_D2RP

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

TP_MCP_SATALED_L

TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN

TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN

TP_SATA_F_D2RN TP_SATA_F_D2RP

MCP_SATA_TERMP

USB_EXTD_N

USB_IR_N

USB_TPAD_P

PP1V05_S0_MCP_PLL_SATA

TP_SATA_C_D2RN TP_SATA_C_D2RP

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N

SATA_ODD_D2R_N SATA_ODD_D2R_P

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

USB_EXTC_OC_L EXCARD_OC_L

USB_EXTB_OC_L

USB_EXTA_OC_L

USB_EXTB_N

USB_EXTB_P

USB_EXCARD_P USB_EXCARD_N

TP_USB_10P

USB_EXTC_N

USB_EXTC_P

USB_CARDREADER_P USB_CARDREADER_N

SYNC_MASTER=K24_MLB

MCP SATA & USB

SYNC_DATE=04/06/2009

73 9

72 34

OMIT

(8 OF 11)

BGA

MCP79-TOPO-B

U1400

AD35

AD37

AD38

AE22

AE24

AE39

AE4

AD6

AF16

AF17

AF18

AF20

AF22

AF26

AF27

AF28

AF33

AF34

AF37

AF40

AG18

AG20

AG22

AG26

AG36

AG40

AH18

AH20

AH22

AH24

AJ12

AN11

AK12

AK13

AL12

AM11

AM12

AN12

AL13

AN14

AL14

AM13

AM14

AF19

AG16

AG17

AG19

AH17

AH19

AE16

L28

AJ5

AJ4

AJ6

AJ7

AJ9

AK9

AJ10

AJ11

AJ2

AJ1

AJ3

AK2

AL4

AK3

AL3

AM4

AM2

AM3

AM1

AN1

AN3

AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21

K21

J21

H21

A27

402

1/16W MF-LF

5%

8.2K

R2050

1

2

5%

8.2K

1/16W

402

MF-LF

R2051

1

2

402

1/16W MF-LF

5%

8.2K

R2052

1

2

5%

8.2K

MF-LF

1/16W

402

R2053

1

2

806

MF-LF

1%

1/16W

402

R2060

1

2

MF-LF

1% 1/16W

402

2.49K

R2010

1

2

37

35

9

73 35

73 30

73 44

73 9

73 65

9

73 35

23

73

72

23

8

18 8

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID* LLB*

PWRBTN* RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(MGPIO2)

(MGPIO3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

0

SPI_CLK

SPI_DO

0

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F

HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

(MXM_OK for MXM systems)

SAFE mode: For ROMSIP recovery

USER mode: Normal

Connects to SMC for automatic recovery.

Int PU

21 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP3V3_S0_MCP_GPIO

MCP_GPIO_4 AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L

ARB_DETECT

SPI_CLK_R

RTC_CLK32K_XTALOUT

HDA_SDIN0

SPI_CS0_R_L

SPI_MISO

MCP_HDA_PULLDN_COMP

RTC_RST_L

=PP3V3R1V5_S0_MCP_HDA

MCP_SPKR

=PP3V3_S0_MCP

PM_SLP_S4_L

PM_SLP_S3_L

AUD_I2C_INT_L

HDA_SYNC_R

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

SMC_ADAPTER_EN

SMC_WAKE_SCI_L

MEM_EVENT_L ODD_PWR_EN_L

HDA_RST_R_L

HDA_SYNC

SM_INTRUDER_L

PM_RSMRST_L

JTAG_MCP_TRST_L

MCP_TEST_MODE_EN

JTAG_MCP_TMS

MCP_VID<1> MCP_VID<2>

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDOUT_R

HDA_SYNC_R

PP3V3_G3_RTC

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

TP_MCP_KBDRSTIN_L

PM_SYSRST_DEBOUNCE_L

MCP_THMDIODE_N

SMBUS_MCP_0_CLK

SPI_MOSI_R

PM_CLK32K_SUSCLK_R

JTAG_MCP_TCK

MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

PP1V05_S0_MCP_PLL_NV

TP_SB_A20GATE

PM_SLP_RMGT_L

MCP_VID<1>

SMC_RUNTIME_SCI_L

=SPI_CS1_R_L_USE_MLB

HDA_BIT_CLK_R

HDA_SDOUT_R

PM_BATLOW_L

SMBUS_MCP_0_DATA

MCP_VID<2>

AP_PWR_EN

SMBUS_MCP_1_DATA

JTAG_MCP_TDO

JTAG_MCP_TDI

MCP_PS_PWRGD

PM_PWRBTN_L

TP_MCP_LID_L

SMBUS_MCP_1_CLK

MCP_THMDIODE_P

MCP_VID<0>

MCP_CPUVDD_EN

PM_DPRSLPVR

MCP_VID<0>

MCP_CPU_VLD

=PP3V3_S3_MCP_GPIO

AP_PWR_EN

MCP_GPIO_4

=PP3V3R1V5_S0_MCP_HDA

ARB_DETECT

TP_MCP_BUF_SIO_CLK

SMC_IG_THROTTLE_L

SYNC_MASTER=K24_MLB

SYNC_DATE=03/24/2009

MCP HDA & MISC

73 38

73 48 38

25

36

25

37 21

37

402

1/16W MF-LF

5%

10K

R2140

1

2

5%

MF-LF

10K

1/16W

402

R2143

1

2

402

100K

5%

MF-LF

1/16W

R2154

1

2

100K

1/16W

5%

MF-LF 402

R2151

1

2

MF-LF

5%

22K

1/16W

402

R2155

1

2

402

1/16W MF-LF

5%

22K

R2156

1

2

402

1/16W MF-LF

5%

22K

R2157

1

2

10K

5%

MF-LF

1/16W

402

R2141

1

2

MF-LF 402

1/16W

5%

10K

R2142

1

2

100K

5%

MF-LF

1/16W

402

R2147

1

2

36 28 27 21

37 36 32

25 25

54 21

34

OMIT

MCP79-TOPO-B

(9 OF 11)

BGA

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17

L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19

F19

J19

J18

L13

M25

M24

L20

M20

M21

J16

K16

AE18

AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15

B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

CERM

402

5%

10PF

50V

C2172

1

2

CERM

402

5%

10PF

50V

C2170

1

2

CERM 402

5%

10PF

50V

C2173

1

2

CERM 402

5% 50V

10PF

C2171

1

2

13

10K

5%

MF-LF

1/16W

402

R2150

1

2

402

1% 1/16W MF-LF

49.9

R2110

1

2

38

MF-LF

1/16W

22

5%

402

R2172

1 2

1/16W

BOOT_MODE_USER

MF-LF 402

10K

5%

R2181

1

2

1/16W

402

BOOT_MODE_SAFE

MF-LF

10K

5%

R2180

1

2

402

1/16W

5%

8.2K

MF-LF

R2160

1

2

1/16W MF-LF

10K

5%

402

R2163

1

2

402

1/16W MF-LF

22

5%

R2173

1 2

22

402

1/16W

5%

MF-LF

R2171

1 2

1/16W

22

5%

402

MF-LF

R2170

1 2

36

73 25

402

1/16W

1%

MF-LF

1K

R2190

1

2

1/16W

402

MF-LF

49.9K

1%

R2120

1

2

49.9K

402

1% 1/16W MF-LF

R2121

1

2

73 49

36

70 59

9

76 42

32 30 21

60 21

76 42

60 21

73 39

73 39 13

73 39

73 39 13

63 37 36 7

67 63 36 32 7

73 48 38

19 18 8

21 9

54 21

36 28 27 21

37 21

21

73

23 21 8

23 22 8

73 21

60 21

73 21

25 22 7

23

73 21

60 21

8

32 30 21

21 9

23 21 8

21

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

80 uA (S0)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 mA (A01)

22 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP3V3_S5_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

PP3V3_G3_RTC

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

MCP Power & Ground

(10 OF 11)

BGA

MCP79-TOPO-B

OMIT

U1400

AD10

AE8

AB10

AD9

Y10

AB11

AA8

Y9

G18

H19

J20

K20

G26

H27

J28

K28

A20

T21

U21

V21

AA25

AA26

AA27

AA28

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC23

AC24

AC25

AC26

AC27

AC28

AD21

AD23

W27

V25

AA18

U25

AE19

AE21

AE23

AE25

AE26

AE27

AE28

AF10

AF11

AA19

AH12

AF2

AF21

AF23

AF25

AF3

AF4

AF7

AH23

AF9

AA20

AG10

AG11

AG12

AG21

AG23

AG25

AG3

AG4

AA21

AG6

AG7

AG5

AG8

AG9

AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

Y21

AH21

AH3

AH4

AH5

AH6

AH7

AH9

AA24

W21

W23

Y23

W25

AF12

AA16

R32

P31

AF32

AE32

AH32

AJ32

AK31

AK32

AD32

AL31

AB32

AC32

B41

B42

C40

C41

C42

D39

D40

D41

E38

E39

E40

F37

F38

F39

G36

G37

G38

H35

H37

J34

J35

J36

K33

K34

K35

L32

L33

L34

M31

M32

M33

N31

N32

P32

Y32

AA32

T32

U32

V32

W32

AG32

BGA

OMIT

MCP79-TOPO-B

(11 OF 11)

U1400

AH26

AH33

AH34

AH37

AH38

AJ39

AJ8

AK10

AK33

AK34

AK37

AK4

AK40

AL36

AL40

AL5

AM10

AM16

AM18

AM20

AM22

AM24

AM26

AM30

AM34

AM35

AM37

AM38

AM5

AM6

AM7

AM9

AP26

AN28

AN30

AN39

AN4

Y7

AP10

AU26

AP14

AU14

AP28

AP32

AP34

AP36

AP37

AP4

AP40

AP7

AW23

AR28

AR32

AR40

AT10

AR12

AT13

AT29

AT33

AT6

AT7

AT9

AY21

AY22

L12

AU12

AU28

AP33

AU32

AR30

AU36

AU38

AU4

G28

F20

AV28

AV32

AV36

AV4

AV7

AW11

G20

AR43

AW43

AY10

AV12

AY30

AY33

AY34

AY37

AY38

AY41

AV40

BA1

BA4

AW31

AY6

L35

BC33

BC37

BC41

AY14

BC5

C2

D10

D14

D15

D18

D19

D22

D23

D26

D30

D37

D6

E13

E17

E21

E25

E29

E33

F12

F16

F32

F8

G10

G12

G14

G16

BC12

G22

G24

AW20

G34

G4

G43

G6

G8

H11

H15

AW35

H23

AN8

G40

J12

J8

K10

K12

K18

K26

K37

K4

K40

K8

AU1

L40

L43

L5

M10

M34

M35

M37

Y28

Y33

Y34

Y35

Y37

Y38

AB17

AB16

AN26

AD7

M11

AA4

AB19

AY13

P11

Y6

T11

V11

Y11

AH16

T22

23 8

23 21 8

25 21 7

23 8 23 14 8

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

19 mA (A01)

450 mA (A01)

43 mA (A01)

127 mA (A01)

206 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

131 mA (A01)105 mA (A01)

MCP PCIE (DVDD) Power

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

23065 mA (A01, 1.2V)

(No IG vs. EG data)

270 mA (A01)

MCP 3.3V Ethernet Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP 1.05V AUX Power

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP Core Power

4771 mA (A01, DDR3)

333 mA (A01)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

MCP SATA (DVDD) Power

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)

16996 mA (A01, 1.0V)

57 mA (A01)

562 mA (A01)

5 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP 1.05V RMGT Power

Apple: 7x 2.2uF 0402 (15.4 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

25 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_FSB

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_CORE

VOLTAGE=1.05V

PP1V05_S0_MCP_SATA_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_SATA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

=PP3V3_S0_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S5_MCP

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

MCP Standard Decoupling

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

402

20%

4V

4.7UF

X5R-1

C2503

1

2

10UF

20%

6.3V X5R 603

C2592

1

2

402

4V

20%

X5R-1

4.7UF

C2528

1

2

CERM

20%

0.1uF

402

10V

C2529

1

2

CERM

20%

0.1UF

402

10V

C2596

1

2

20%

CERM

0.1UF

402

10V

C2587

1

2

20%

CERM

0.1UF

402

10V

C2585

1

2

CERM

20%

402

10V

0.1UF

C2583

1

2

10V

402

0.1UF

CERM

20%

C2581

1

2

0.1uF

CERM

20%

402

10V

C2519

1

2

0.1uF

20%

CERM 402

10V

C2518

1

2

CERM

20%

0.1uF

402

10V

C2521

1

2

18

MF-LF

1%

1/16W

1.47K

402

R2591

1

2

0.1UF

CERM

20%

402

10V

C2591

1

2

1.47K

1/16W

1%

MF-LF

402

R2590

1

2

30-OHM-1.7A

0402

L2595

1 2

402

4V

4.7UF

20%

X5R-1

C2595

1

2

CERM

0.1UF

20%

402

10V

C2590

1

2

CERM

20%

402

10V

0.1UF

C2589

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2560

1

2

CERM

20%

0.1uF

402

10V

C2525

1

2

0.1uF

402

10V

20%

CERM

C2526

1

2

30-OHM-1.7A

0402

L2580

1 2

20%

402

4V

4.7UF

X5R-1

C2501

1

2

4.7UF

402

20%

4V

X5R-1

C2500

1

2

30-OHM-1.7A

0402

L2555

1 2

0402

30-OHM-1.7A

L2586

1 2

30-OHM-1.7A

0402

L2588

1 2

30-OHM-1.7A

0402

L2584

1 2

30-OHM-1.7A

0402

L2582

1 2

30-OHM-5A

0603

L2575

1 2

0603

30-OHM-5A

L2570

1 2

402

4V

20%

4.7UF

X5R-1

C2580

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2564

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2562

1

2

402

4V

4.7UF

20%

X5R-1

C2540

1

2

CERM

20%

402

10V

0.1UF

C2541

1

2

20%

CERM 402

10V

0.1UF

C2542

1

2

0.1UF

20%

CERM 402

10V

C2543

1

2

20%

CERM 402

10V

0.1UF

C2544

1

2

0.1UF

20%

CERM 402

10V

C2545

1

2

0.1UF

20%

CERM 402

10V

C2546

1

2

0.1UF

20%

CERM 402

10V

C2547

1

2

0.1UF

20%

CERM 402

10V

C2548

1

2

0.1UF

20%

CERM 402

10V

C2549

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2550

1

2

2.2UF

6.3V

20%

402-LF

CERM

C2551

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2552

1

2

2.2UF

6.3V

20%

402-LF

CERM

C2553

1

2

6.3V

2.2UF

20%

CERM 402-LF

C2575

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2576

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2573

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2574

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2570

1

2

402

20%

4.7UF

4V

X5R-1

C2520

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2571

1

2

CERM

6.3V

2.2UF

20%

402-LF

C2572

1

2

402

20%

4V

4.7UF

X5R-1

C2515

1

2

X5R 402-1

1UF

10% 10V

C2516

1

2

X5R 402-1

1UF

10% 10V

C2517

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2530

1

2

20%

2.2UF

6.3V

402-LF

CERM

C2531

1

2

6.3V

20%

402-LF

CERM

2.2UF

C2532

1

2

6.3V

2.2UF

20%

CERM 402-LF

C2533

1

2

2.2UF

6.3V

20%

402-LF

CERM

C2534

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2535

1

2

2.2UF

20%

402-LF

CERM

6.3V

C2536

1

2

0.1UF

CERM

20%

402

10V

C2512

1

2

0.1UF

CERM

20%

402

10V

C2513

1

2

0.1UF

CERM

20%

402

10V

C2508

1

2

0.1UF

CERM

20%

402

10V

C2509

1

2

0.1UF

CERM

20%

402

10V

C2510

1

2

0.1UF

CERM

20%

402

10V

C2511

1

2

X5R 402-1

1UF

10% 10V

C2504

1

2

X5R 402-1

1UF

10% 10V

C2505

1

2

X5R 402-1

1UF

10% 10V

C2506

1

2

X5R 402-1

1UF

10% 10V

C2507

1

2

402

20%

4V

4.7UF

X5R-1

C2502

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2555

1

2

402

20%

4.7UF

4V

X5R-1

C2586

1

2

402

4V

20%

4.7UF

X5R-1

C2584

1

2

402

4V

4.7UF

20%

X5R-1

C2588

1

2

402

20%

4.7UF

4V

X5R-1

C2582

1

2

8

22 8

62 8 14

17

21

16

8

20

18 8

23 18 8

22 21 8

21 8

22 8

8

22 14 8

16 8

18 8

8

23 18 8

8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

Apple: ???

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

190 mA (A01, 1.8V)

95 mA (A01)

16 mA (A01)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

16 mA (A01)

206 mA (A01)206 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)

REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT

SYNC FROM T18

CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC REMOVE HDCP ROMS

REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

26 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V05_S0_MCP_HDMI_VDD

MCP_IFPAB_RSET

MCP_HDMI_RSET

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3R1V8_S0_MCP_IFP_VDD

MCP_HDMI_VPROBE

PP3V3_S0_MCP_VPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MCP_IFPAB_VPROBE

VOLTAGE=3.3V

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MCP Graphics Support

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

CERM 402-LF

20%

2.2UF

6.3V

C2610

1

2

402

1/16W

1%

1K

MF-LF

R2620

1

2

402

0

5% 1/16W MF-LF

R2651

1

2

402

20%

CERM

0.1UF

10V

C2616

1

2

10V

20%

402

CERM

0.1uF

C2641

1

2

30-OHM-1.7A

0402

L2640

1 2

CERM

4.7UF

6.3V

20%

603

C2640

1

2

X5R-1

402

4V

4.7UF

20%

C2615

1

2

20%

402

CERM

NO STUFF

10V

0.1UF

C2630

1

2

MF-LF

1/16W

1%

1K

402

NO STUFF

R2630

1

2

CERM

10V

20%

0.1UF

NO STUFF

402

C2620

1

2

30-OHM-1.7A

0402

NO STUFF

L2650

1 2

6.3V

2.2UF

20%

402-LF

CERM

NO STUFF

C2650

1

2

18 8

72 18 72 18

8

18 8

72 18

18

72 18

18

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

Y

B

A

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCIE Reset (Unbuffered)

MCPSEQ_MIX is cross between MLB and internal power sequencing, which

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

MCP S0 PWRGD & CPU_VLD

10K pull-up to 3.3V S0 inside MCP

Reset Button

but results in MCP79 ROMSIP sequence happening after CPU powers up.

LPC Reset (Unbuffered)

REMOVE R2824 AND NET PCI_CLK33M_SLOT_A

CHANGE Y2810 AND U2850 TO SMALLER PARTS

REMOVE UNUSED PCIE RESET SIGNALS

ALIAS MEM_VTT_EN TO =DDRVTT_EN

CHANGE RESET BUTTOM TO RESET PADS

SYNC FROM T18

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

results in earlier ROMSIP and MCP FSB I/O interface initialization.

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

CHANGE RTC COIN CELL TO LDO & SUPERCAP

Platform Reset Connections

MCP 25MHz Crystal

RTC Crystal

PLACE C2819 CLOSE TO MCP79

28 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PCIE_RESET_L

MINI_RESET_L

=PP3V42_G3H_RTC_D

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.3 mm

RTC_CLK32K_XTALOUT

MAKE_BASE=TRUE

MEM_VTT_EN

PCA9557D_RESET_L

LPC_CLK33M_SMC_R

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT

SMC_LRESET_L

=PP3V3_S5_MCPPWRGD

VR_PWRGOOD_DELAY

S0_AND_IMVP_PGOOD

ALL_SYS_PWRGD

MCP_CPUVDD_EN

MCP_CPU_VLD

MCP_PS_PWRGD

XDP_DBRESET_L

PM_SYSRST_DEBOUNCE_L

PM_SYSRST_L

DEBUG_RESET_L

RTC_CLK32K_XTALIN

=DDRVTT_EN

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

PM_CLK32K_SUSCLK

MEM_VTT_EN_R

PM_CLK32K_SUSCLK_R

LPC_RESET_L

BKLT_PLT_RST_L

SB Misc

SYNC_MASTER=K24_MLB

SYNC_DATE=02/15/2009

5%

MF-LF

1/16W

0

402

R2820

1 2

6.3V

CERM 402

1UF

10%

PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79

C2819

1

2

21

MF-LF

5%

1/16W

0

402

MCPSEQ_SMC

R2853

1 2

MF-LF

5%

1/16W

0

402

MCPSEQ_MIX

R2852

1 2

21

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_SMC

R2850

1 2

402

20%

CERM

0.1UF

MCPSEQ_SMC

10V

C2850

1

2

402

0

1/16W

5%

MF-LF

MCPSEQ_MIX

R2851

1 2

63 36

59

21

SOT665

TC7SZ08AFEAPE

U2850

2

1

3

5

4

0

5% 1/16W MF-LF

402

R2810

1

2

1/16W MF-LF

402

5%

0

R2815

1

2

CRITICAL

7X1.5X1.4-SM

32.768K

Y2810

1 4

1/16W

5%

0

MF-LF

402

R2871

1 2

26

13 10

36

402

5% 1/16W MF-LF

XDP

0

R2898

1 2

NO STUFF

0

MF-LF

1/16W

5%

402

SILK_PART=SYS RST

R2890

1

2

33

402

MF-LF

1/16W

5%

R2899

1 2

X5R

10%

1UF

10V

402

NO STUFF

C2899

1

2

21

73 36

73 38

19

33

402

5% 1/16W MF-LF

R2870

1 2

64 58

5% 1/16W MF-LF

0

402

R2892

1 2

69

73 21

PLACEMENT_NOTE=Place close to U1400

402

MF-LF

5%

1/16W

22

R2829

1 2

73 36

21

402

1M

NO STUFF

1/16W

5%

MF-LF

R2816

1

2

25.0000M

CRITICAL

SM-3.2X2.5MM

Y2815

2 4

1 3

12pF

5%

50V

CERM

402

C2816

1 2

402

CERM

50V

12pF

5%

C2815

1 2

73 19

PLACEMENT_NOTE=Place close to U1400

MF-LF

5%

1/16W

33

402

R2825

1 2

PLACEMENT_NOTE=Place close to U1400

402

5% 1/16W MF-LF

33

R2826

1 2

17

21

30

36

38

0

MF-LF

402

5%

1/16W

R2891

1 2

PLACEMENT_NOTE=Place close to U1400

33

5% 1/16W MF-LF

402

R2881

1 2

33

MF-LF

5%

1/16W

402

PLACEMENT_NOTE=Place close to U1400

R2883

1 2

73 19

NO STUFF

10M

402

MF-LF

5%

1/16W

R2811

1

2

402

12pF

5% 50V CERM

C2811

1 2

402

5% 50V CERM

12pF

C2810

1 2

8 22 21 7

8

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

NC

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU FSB VREF

MEM B VREF CA

Place close to J3100.126

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

BOM options provided by this page:

NO_VREFMRGN

ADDR=0x98(WR)/0x99(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

ADDR=0x30(WR)/0x31(RD)

MEM B VREF DQ

VREFMRGN

Place close to J3200.126

Place close to J3200.1

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

10mA max load

Page Notes

MEM A VREF DQ MEM A VREF CA

Place close to J3100.1

Place close to U1000.AD26

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

(per DAC LSB)

- =I2C_VREFDACS_SCL

- =I2C_PCA9557D_SCL

Min DAC code 0x00 0x00 0x00 0x00 0x00

- =I2C_PCA9557D_SDA

- =I2C_VREFDACS_SDA

- =PP3V3_S5_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

Max DAC code 0x87 0x87 0x87 0x87 0x55

DAC channel A B A B C

29 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PPVTT_S3_DDR_BUF

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_DQ_SODIMMB_BUF

=PP3V3_S3_VREFMRGN

CPU_GTLREF

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMA_EN

PCA9557D_RESET_L

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

FSB/DDR3 Vref Margining

CRITICAL

1

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R2905

CRITICAL

1

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R2911

1

CRITICAL

NO_VREFMRGN

116S0004

R2909

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

R2903

NO_VREFMRGN

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

70 10

VREFMRGN

CERM

10V

402

20%

0.1UF

C2903

1

2

VREFMRGN

1/16W

100K

5%

402

MF-LF

R2913

1 2

CERM

VREFMRGN

0.1UF

10V

20%

402

C2905

1

2

20%

6.3V CERM 402-LF

2.2UF

VREFMRGN

C2900

CERM

20%

0.1UF

VREFMRGN

402

10V

C2901

1

2

39

MSOP

DAC5574

VREFMRGN

U2900

9

10

3

6

7

8

1

2

4

5

39

25

VREFMRGN

402

1/16W

5%

MF-LF

100K

R2908

1 2

20% 10V

VREFMRGN

402

CERM

0.1UF

C2904

1

2

PCA9557

VREFMRGN

QFN

U2901

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

100K

VREFMRGN

402

5%

MF-LF

1/16W

R2907

1 2

402

MF-LF

VREFMRGN

100K

5%

1/16W

R2901

1 2

VREFMRGN

5%

402

100K

1/16W MF-LF

R2902

1 2

VREFMRGN

1%

200

1/16W MF-LF

402

R2903

1 2

VREFMRGN

1%

200

1/16W MF-LF

402

R2905

1 2

VREFMRGN

1%

200

1/16W MF-LF

402

R2909

1 2

VREFMRGN

1%

200

1/16W MF-LF

402

R2911

1 2

UCSP

VREFMRGN

MAX4253

U2902

A3

A2

A1

A4

B1

B4

UCSP

MAX4253

VREFMRGN

U2902

C3

C2

C1

C4

B1

B4

UCSP

VREFMRGN

MAX4253

U2903

A3

A2

A1

A4

B1

B4

CERM 402

10V

20%

0.1UF

VREFMRGN

C2902

1

2

UCSP

MAX4253

VREFMRGN

U2904

A3

A2

A1

A4

B1

B4

UCSP

MAX4253

VREFMRGN

U2904

C3

C2

C1

C4

B1

B4

402

100

MF-LF

1%

VREFMRGN

1/16W

R2912

1 2

100

402

1%

VREFMRGN

1/16W MF-LF

R2914

1 2

402

MF-LF

1/16W

1%

100

VREFMRGN

R2910

1 2

MF-LF

VREFMRGN

402

1%

1/16W

100

R2906

1 2

402

100

1% 1/16W MF-LF

VREFMRGN

R2904

1 2

UCSP

MAX4253

VREFMRGN

U2903

C3

C2

C1

C4

B1

B4

58 8

28

27

28

27

8

26

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

BI

IN IN

BI

IN

BI BI

BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI

BI BI

BI

IN

BI BI

BI

OUT

BI

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

NC

BI

BIBI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP0V75_S0_MEM_VTT_A

SPD ADDR=0xA0(WR)/0xA1(RD)

BOM options provided by this page:

(NONE)

- =I2C_SODIMMA_SCL

"Factory" (top) slot

- =I2C_SODIMMA_SDA

516-0201

Power aliases required by this page:

- =PP1V5_S3_MEM_A

Page Notes

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

31 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MEM_A_DQ<14> MEM_A_DQ<11>

MEM_A_DQ<8>

MEM_A_DQ<13> MEM_A_DQ<12>

MEM_A_DQ<15> MEM_A_DQ<10>

MEM_A_DQS_N<0>

MEM_A_DQ<3>

MEM_A_DQ<24>

MEM_A_DQ<29>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<38>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<41> MEM_A_DQ<40>

MEM_A_DQ<19>

MEM_A_DQ<22>

=PP1V5_S3_MEM_A

MEM_A_DQ<18> MEM_A_DQ<17>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQ<28>

MEM_A_DQ<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<31>

MEM_A_DQ<27>

MEM_A_DM<3>

MEM_RESET_L

MEM_A_DM<1>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<16>

MEM_A_DQ<23>

MEM_A_DQ<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<2>

MEM_A_A<5>

MEM_A_DM<0>

MEM_A_DQ<6>

MEM_A_CKE<1>

MEM_A_A<11>

MEM_A_DQ<26>

MEM_A_DM<2>

MEM_A_A<10>

MEM_A_SA<1>

=PP0V75_S0_MEM_VTT_A

MEM_A_DQS_N<4> MEM_A_DQS_P<4>

MEM_A_CLK_N<0>

MEM_A_SA<0>

MEM_A_DQ<58> MEM_A_DQ<59>

MEM_A_DM<7>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<54> MEM_A_DQ<51>

MEM_A_DQS_N<6> MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DQ<46>

MEM_A_DM<5>

MEM_A_DQ<47>

=I2C_SODIMMA_SDA =I2C_SODIMMA_SCL

MEM_EVENT_L

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQS_N<7> MEM_A_DQS_P<7>

MEM_A_DQ<57> MEM_A_DQ<56>

MEM_A_DQ<50>

MEM_A_DQ<55>

MEM_A_DM<6>

MEM_A_DQ<48>

MEM_A_DQ<53>

MEM_A_DQS_P<5>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_CS_L<1>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_DQS_N<5>

MEM_A_DQ<39>

MEM_A_DM<4>

MEM_A_DQ<36>

MEM_A_DQ<37>

PP0V75_S3_MEM_VREFCA_A

MEM_A_CS_L<0> MEM_A_ODT<0>

MEM_A_BA<1> MEM_A_RAS_L

MEM_A_CLK_N<1>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_A<4>

MEM_A_A<14>

MEM_A_A<15>

=PPSPD_S0_MEM_A

MEM_A_DQ<25>

MEM_A_DQ<4>

MEM_A_DQ<2>

MEM_A_DQS_P<0>

MEM_A_DQ<5>

MEM_A_DQ<20> MEM_A_DQ<21>

MEM_A_DQ<30>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<0>

MEM_A_DQ<7>

MEM_A_ODT<1>

SYNC_MASTER=K24_MLB

SYNC_DATE=02/05/2009

DDR3 SO-DIMM Connector A

71 15

71 15 71 15

71 15

402

20% 10V CERM

0.1UF

C3111

1

2

402

10V

0.1UF

20%

CERM

C3112

1

2

402

0.1UF

20%

CERM

10V

C3113

1

2

402

0.1UF

20%

CERM

10V

C3114

1

2

402

20%

CERM

10V

0.1UF

C3115

1

2

402

0.1UF

20% 10V CERM

C3116

1

2

402

CERM

0.1UF

20% 10V

C3117

1

2

402

10V CERM

0.1UF

20%

C3110

1

2

2.2UF

20%

CERM 402-LF

6.3V

C3140

1

2

10K

MF-LF

1/16W

5%

402

R3140

1

2

10K

5%

402

1/16W MF-LF

R3141

1

2

71 15

CERM 402-LF

20%

2.2UF

6.3V

C3150

1

2

39

20%

2.2UF

6.3V

402-LF

CERM

C3151

1

2

36 28 21

71 15

402-LF

20%

6.3V

2.2UF

CERM

C3135

1

2

10V

20%

402

CERM

0.1UF

C3136

1

2

71 15

9

71 15

OMIT

F-RT-THB

CRITICAL

DDR3-SODIMM-DUAL-M97-3

J3100

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

71 15

29 28

71 15

CERM

6.3V

20%

2.2UF

402-LF

C3130

1

2

0.1UF

CERM 402

20% 10V

C3131

1

2

71 15

OMIT

F-RT-THB

DDR3-SODIMM-DUAL-M97-3

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99 100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

6.3V X5R 603

10UF

20%

C3101

1

2

603

X5R

6.3V

10UF

20%

C3100

1

2

8

26

8

26

8

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

BI

BI BI

IN

BI BI

BI

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

BI BI

BI

BI BIBI

BI BI

BI

BI BI

BI

IN

BI BI

BI

BI BI

IN

BI

IN

BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP0V75_S0_MEM_VTT_B

BOM options provided by this page:

Page Notes

"Expansion" (bottom) slot

516S0706

SPD ADDR=0xA2(WR)/0xA3(RD)

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

(NONE)

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

DDR3 GROUND RETURN CAPS (MCP SIDE)

- =PP1V5_S0_MEM_B

Signal aliases required by this page:

- =PP1V5_S3_MEM_B

Power aliases required by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

32 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V5_S3_MEM_B

MEM_B_DM<4>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

MEM_EVENT_L

MEM_B_DQ<53>

MEM_B_DQ<39>

MEM_B_DQ<32>

MEM_B_DQ<37>

MEM_B_DQ<52>

MEM_B_DQ<38>

MEM_B_DQ<33> MEM_B_DQ<36>

MEM_B_DQS_P<5>

MEM_B_DM<6>

MEM_B_DQ<47>

MEM_B_DQ<27> MEM_B_DQ<31>

MEM_B_DQ<26>MEM_B_DQ<30>

MEM_B_DQ<18>

MEM_B_DQ<21>

MEM_B_DQ<16>

MEM_B_DQ<22>

MEM_B_DQ<3>MEM_B_DQ<7>

MEM_B_DQ<19>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<6>

MEM_B_DQ<8>

MEM_B_DQ<20>

MEM_B_DQ<23>

MEM_B_DQ<63>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_CKE<0>

MEM_B_DQS_N<7>

MEM_B_SA<0>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<12>

MEM_B_DQ<46>

MEM_B_DQ<49>

MEM_B_DQ<41>

MEM_B_DQS_N<4>

MEM_B_DM<5>

MEM_B_CKE<1>

MEM_B_A<6> MEM_B_A<4>

MEM_B_A<2> MEM_B_A<0>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_DQ<34>

MEM_B_DQ<44>

MEM_B_DQ<40>

MEM_B_BA<2>

MEM_B_CLK_P<0>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_A<13> MEM_B_CS_L<1>

MEM_B_DQ<35>

MEM_B_DQ<45>

MEM_B_DQ<42> MEM_B_DQ<43>

MEM_B_DQ<48>

MEM_B_DQ<51> MEM_B_DQ<50>

MEM_B_DQ<59>

MEM_B_DQS_P<7>

MEM_B_DQ<57>

MEM_B_DQ<62>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_CLK_N<0>

MEM_B_DQS_P<4>

MEM_B_CAS_L

MEM_B_DQ<56> MEM_B_DQ<58>

MEM_B_SA<1>

MEM_B_DQ<61> MEM_B_DQ<60>

=PPSPD_S0_MEM_B

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DM<0>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<15> MEM_B_DQ<10>

MEM_B_DQ<17>

MEM_B_DQS_P<2>

MEM_B_DQ<5>

MEM_B_DQS_N<0> MEM_B_DQS_P<0>

MEM_B_DQ<2>

MEM_B_DQ<12> MEM_B_DQ<9>

MEM_B_DM<1> MEM_RESET_L

MEM_B_DQ<11>

MEM_B_DM<2>

MEM_B_DQ<29> MEM_B_DQ<25>

MEM_B_DQS_N<3> MEM_B_DQS_P<3>

MEM_B_DQ<4>

MEM_B_DM<3>

MEM_B_DQS_N<2>

=PP0V75_S0_MEM_VTT_B

MEM_B_DM<7>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQS_N<5>

PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<28>

MEM_B_DQ<24>

=PP1V5_S0_MEM_MCP

MEM_B_RAS_L

MEM_B_A<3>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_A<9>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

SYNC_MASTER=K24_MLB

SYNC_DATE=02/05/2009

DDR3 SO-DIMM Connector B

71 15

10V CERM

20%

0.1UF

402

C3215

1

2

2.2UF

6.3V CERM

20%

402-LF

C3235

1

2

CERM 402

20% 10V

0.1UF

C3236

1

2

71 15

10V CERM

20%

0.1UF

402

C3216

1

2

71 15

10V CERM

0.1UF

20%

402

C3217

1

2

71 15

9

71 15

29 27

71 15

10V CERM

0.1UF

20%

402

C3211

1

2

71 15

71 15 71 15

71 15

71 15 71 15

F-RT-BGA3

CRITICAL

DDR3-SODIMM

OMIT

J3200

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

F-RT-BGA3

DDR3-SODIMM

OMIT

J3200

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99 100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206

207 208

209 210

211 212

203 204

113

0.1UF

20% 10V CERM 402

C3222

1

2

10V CERM

20%

0.1UF

402

C3223

1

2

10V CERM

20%

0.1UF

402

C3224

1

2

71 15

10V CERM

20%

0.1UF

402

C3225

1

2

10V CERM

20%

0.1UF

402

C3226

1

2

10V CERM

0.1UF

20%

402

C3227

1

2

10V CERM

20%

0.1UF

402

C3228

1

2

10V CERM

20%

0.1UF

402

C3229

1

2

20%

CERM 402-LF

6.3V

2.2UF

C3240

1

2

MF-LF

1/16W

402

5%

10K

R3240

1

2

10K

1/16W MF-LF

5%

402

R3241

1

2

CERM 402-LF

6.3V

20%

2.2UF

C3230

1

2

71 15

CERM

10V

20%

0.1UF

402

C3212

1

2

71 15

10V

20%

0.1UF

402

CERM

C3213

1

2

71 15

X5R

6.3V

10UF

20%

603

C3200

1

2

10V

20%

402

CERM

0.1UF

C3231

1

2

20%

X5R

6.3V

603

10UF

C3201

1

2

0.1UF

CERM

10V

20%

402

C3210

1

2

2.2UF

6.3V

20%

402-LF

CERM

C3250

1

2

39

2.2UF

CERM 402-LF

6.3V

20%

C3251

1

2

36 27 21

71 15

10V CERM

20%

0.1UF

402

C3214

1

2

71 15

8

26

8

IN

OUT

D

Q2

SG

Q1

B

C

E

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

must be high before 1.5V starts to

3.3V S5 is used because MEM_RESET

rise to avoid glitch on MEM_RESET_L.

DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

33 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MCP_MEM_RESET_L

=PP1V5_S3_MEMRESET

MEM_RESET_RC_L

MEM_RESET_L

MEM_RESET

=PP3V3_S5_MEMRESET

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

DDR3 Support

5%

20K

1/16W

402

MF-LF

R3301

1

2

402

CERM

20%

0.1UF

10V

C3300

1

2

SOT-363

DMB53D0UDW

Q3305

5

3

64

2 1

10K

1/16W MF-LF

402

5%

R3300

1

2

5%

MF-LF

1/16W

0

402

R3309

2 1

1K

402

MF-LF

1/16W

5%

R3310

1

2

28 27

100K

402

MF-LF

1/16W

5%

R3305

1

2

16

8

OUT

IN

IN IN

IN

BI

Y

B

A

IN

SYM_VER-1

D

S G

D

S G

OUT

IN

D

GS

NC

NC NC

SYM_VER-1

OUT

S

G

D

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

606 MA NOMINAL MAX

RC VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN

BLUETOOTH

AIRPORT

20-30 MOHM @2.5V

P-TYPE

0.727 A (EDP)

3V S3 WLAN FET

TPCP8102

MOSFET

LOADING

RDS(ON)

CHANNEL

727 MA PEAK

155S0367

516S0582

3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET

34 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PM_WLAN_EN_L

CONN_PCIE_MINI_R2D_N

CONN_PCIE_MINI_D2R_P

CONN_PCIE_MINI_D2R_N

PP3V3_WLAN

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

CONN_PCIE_MINI_R2D_P

PCIE_CLK100M_MINI_CONN_P

CONN_USB2_BT_P

PP3V3_S3_BT_F

MINI_RESET_CONN_L

PCIE_WAKE_L

CONN_USB2_BT_N

PCIE_CLK100M_MINI_CONN_N

PCIE_MINI_R2D_C_N

PP3V3_WLAN_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

ISNS_AIRPORT_N

AP_PWR_EN

PCIE_MINI_PRSNT_L

PCIE_CLK100M_MINI_P

PCIE_MINI_D2R_N

WLAN_SMIT_RC

WLAN_SMIT_BUF

MINI_RESET_L

PP3V3_WLAN_F

WLAN_SMIT_DISCHRG

PCIE_CLK100M_MINI_N

PCIE_MINI_R2D_C_P

PCIE_MINI_D2R_P

MINI_CLKREQ_L

PM_WLAN_EN_L

VOLTAGE=3.3V

PP3V3_WLAN_R

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

P3V3WLAN_SS

PCIE_MINI_R2D_P

ISNS_AIRPORT_P

PCIE_MINI_R2D_N

USB_BT_P

USB_BT_N

=PP3V3_S3_WLAN

=PP3V3_S3_BT

MINI_CLKREQ_Q_L

=PP3V3_S3_WLAN

MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

SYNC_DATE=01/27/2009

X16 WIRELESS CONNECTOR

SYNC_MASTER=K24_MLB

10V

20%

CERM

402

0.1uF

PLACEMENT_NOTE=Place close to J3401.

C3422

1

2

1/16W

10K

MF-LF

5%

402

R3451

1

2

1/16W

5%

402

MF-LF

100K

R3450

1 2

402

10%

X5R

16V

0.033UF

C3451

1

2

402

10% 16V

0.1UF

X5R

C3450

1 2

CRITICAL

23V1K-SM

TPCP8102

Q3450

5 6 7 8

4

1 2 3

F-ST-SM

CRITICAL

500913-0302

J3401

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

FERR-120-OHM-1.5A

0402-LF

PLACEMENT_NOTE=PLACE L3406 NEAR J3401.

L3406

12

CERM

16V

10%

402

PLACEMENT_NOTE=PLACE C3432 NEAR J3401

0.01UF

C3432

1

2

0603

FERR-120-OHM-3A

L3404

1 2

76 47

1%

1/4W

MF

1206

0.002

CRITICAL

R3452

1 2 3 4

72 17

PLACEMENT_NOTE=Place close to J3401.

90-OHM-100MA

DLP11S

CRITICAL

L3405

1 2

34

CRITICAL

90-OHM-100MA

DLP11S

PLACEMENT_NOTE=Place close to J3401.

L3402

1 2

34

74LVC1G17

SOT353-1

U3402

2

3 1

5

4

1

MF-LF

402

1/16W

5%

R3455

1 2

SOD-VESM-HF

SSM3K15FV

Q3455

3

1

2

32 21

17

SOT563

SSM6N15FEAPE

Q3401

3

5

4

SOT563

SSM6N15FEAPE

Q3401

6

2

1

90-OHM DLP0NS

CRITICAL

PLACEMENT_NOTE=Place close to J3401.

L3403

1 2

34

CRITICAL

90-OHM-100MA

DLP11S

PLACEMENT_NOTE=Place close to J3401.

L3401

1 2

34

402

CERM

1UF

6.3V

10%

C3453

1

2

NOSTUFF

62K

1/16W MF-LF

5%

402

R3454

1

2

110K

1/16W

402

MF-LF

5%

R3453

1

2

X5R

10UF

805

20%

PLACEMENT_NOTE=Place close to Q3450.

10V

C3420

1

2

25

TC7SZ08AFEAPE

SOT665

U3401

2

1

3

5

4

73 20

0.1uF

402

CERM

10V

20%

PLACEMENT_NOTE=Place close to Q3450.

C3421

1

2

72 17

0.1uF

40216V X5R10%

PLACEMENT_NOTE=Place close to J3401.

C3431

1 2

72 17

0.1uF

16V10% X5R 402

PLACEMENT_NOTE=Place close to J3401.

C3430

1 2

32

30

17 7

32 30

72 7

7

72 7

73 7

7

73 7

72 7

47 30

72

30 8

8

7

30 8

IN IN IN IN

IN

BI

IN

BI

BI BI

OUT

OUT OUT OUT OUT

OUT

IN

DVDD33

VDDREG

REGOUT

MDI-[0]

RXD[2]/AN0

LED0/PHYAD0

LED2/RXDLY

LED1/PHYAD1

MDI-[3]

RXD[1]/TXDLY

RXD[3]/AN1

MDI-[1]

MDI+[1]

MDI+[3]

MDI+[2] MDI-[2]

RXCTL

MDC

PHYRSTB*

RSET

CLK125

CKXTAL2

CKXTAL1

MDI+[0]

RXD[0]

GND

MDIO

RXC

TXCTL

AVDD10

DVDD10

ENSWREG

TXD[3]

TXD[2]

TXD[1]

TXD[0]

TXC

AVDD33

FB10

LED

RESET

CLOCK

MANAGEMENT

MEDIA DEPENDENT

RGMII/MII

REFERENCE

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

If internal switcher is not used, VDDREG and REGOUT can float.

(43mA typ - 1000base-T)

( 7mA typ - Energy Detect)

(221mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

RXDLY = 0 (RXCLK transitions with data) TXDLY = 0 (No TXCLK Delay)

Configuration Settings:

If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

If internal switcher is used, must place inductor within 5mm

Alias to GND for external 1.05V supply.

PLACE R3796 CLOSE TO U1400, PIN D24

per RealTek request.

Reserved for EMI

Alias to =PP3V3_ENET_PHY for internal switcher.

HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.

ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.

(19mA typ - Energy Detect)

AN[1:0] = 11 (Full auto-negotiation)

PHYAD = 01 (PHY Address 00001)

WF: Marvell numbers, update for Realtek

37 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=RTL8211_REGOUT

ENET_MDI_N<0>

ENET_RXD_R<2>

RTL8211_PHYAD0

RTL8211_RXDLY

RTL8211_PHYAD1

ENET_MDI_N<3>

ENET_RXD_R<1>

ENET_RXD_R<3>

PP3V3_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENET_MDI_P<2> ENET_MDI_N<2>

ENET_RXCTL_R

ENET_MDC

RTL8211_PHYRST_L

RTL8211_RSET

TP_RTL8211_CLK125

TP_RTL8211_CKXTAL2

RTL8211_CLK25M_CKXTAL1

ENET_MDI_P<0>

ENET_RXD_R<0>

ENET_MDIO

ENET_CLK125M_RXCLK_R

ENET_TX_CTRL

=RTL8211_ENSWREG

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

ENET_CLK125M_TXCLK_R

ENET_RESET_L

ENET_CLK125M_TXCLK

ENET_RX_CTRL

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

ENET_CLK125M_RXCLK

=PP3V3_ENET_PHY

VOLTAGE=1.05V

PP1V05_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_ENET_PHY_VDDREG

=PP1V05_ENET_PHY

SYNC_DATE=04/06/2009

Ethernet PHY (RTL8211CL)

SYNC_MASTER=K24_MLB

RTL8251CA-VB-GR

CRITICAL

TQFP

U3700

10

40

6

41

42 43

32

28

36

152137

39

3

7

203347

34 35 38

30

2

1

5

4

9

8

12

11

31

29

48

46

19

13

14 16 17 18

22

27

23 24 25 26

44

45

74 18

MF-LF

402

1/16W

5%

0

R3796

1 2

402

5%

CERM

50V

10PF

NO STUFF

C3790

1

2

402

2.2UF

6.3V X5R

10%

C3714

1

2

0.1UF

16V X5R 402

10%

C3710

1

2

0.1UF

16V X5R

10%

402

C3711

1

2

FERR-120-OHM-1.5A

0402-LF

CRITICAL

L3715

1

2

402

0.1UF

16V X5R

10%

C3716

1

2

6.3V

402

X5R

2.2UF

10%

C3715

1

2

MF-LF

4.7K

5% 1/16W

402

R3751

1

2

1/16W

5%

4.7K

MF-LF

402

R3750

1

2

402

4.7K

MF-LF

5% 1/16W

R3757

1

2

402

MF-LF

5%

4.7K

1/16W

R3752

1

2

9

402

4.7K

MF-LF

5%

1/16W

R3756

1

2

402

4.7K

MF-LF

5%

1/16W

R3755

1

2

74 18

402

22

MF-LF1/16W

5%

R3795

1 2

402

22

MF-LF1/16W

5%

R3794

1 2

402

22

MF-LF1/16W

5%

R3793

1 2

402

MF-LF1/16W

5%

22

R3792

1 2

402

MF-LF1/16W

5%

22

R3791

1 2

MF-LF

5%

1/16W

22

402

R3790

1 2

74 33

74 32

74 18

0.1UF

16V X5R 402

10%

C3702

1

2

16V

0.1UF

X5R 402

10%

C3701

1

2

0.1UF

16V X5R 402

10%

C3700

1

2

0.1UF

16V X5R 402

10%

C3706

1

2

0.1UF

16V X5R 402

10%

C3705

1

2

CRITICAL

FERR-120-OHM-1.5A

0402-LF

L3705

1

2

10K

5%

MF-LF

1/16W

402

R3720

1

2

5%

4.7K

1/16W

NO STUFF

402

MF-LF

R3725

1

2

2.49K

1%

1/16W

402

MF-LF

R3730

1

2

20%

CERM 402

10V

NO STUFF

0.1UF

C3725

1

2

0

MF-LF

5%

1/16W

402

R3724

1 2

9

74

9

74

74 74

8

9

8

G

DS

IN

OUT

D

SG

IN

D

S G

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

I(max) = 1.7A (85C)

Rds(on) = 90mOhm max

@ 2.5V Vgs:

3.3V ENET FET

1.05V ENET FET

MOBILE:

RTL8211 25MHz Clock

1.8V Vgs

=P1V05ENET_EN. Nets separated on

Recommend aliasing PM_SLP_RMGT_L and

ARB for alternate power options.

Non-ARB:

=P3V3ENET_EN. Nets separated on

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

Recommend aliasing PM_SLP_RMGT_L and

ARB for alternate power options.

Pull-up is with power FET.

38 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

AP_PWR_EN

P1V05ENET_SS

P1V05ENET_EN_L_RC

=P3V3ENET_EN

SMC_ADAPTER_EN

PM_WLAN_EN_L

AC_OR_S0_L

=P1V05ENET_EN

=PP1V05_ENET_FET

P3V3ENET_EN_L

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

P3V3ENET_SS

=PP3V3_ENET_FET

PM_SLP_S3_L

=PP1V05_ENET_P1V05ENETFET

P1V05ENET_EN_L

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P1V05ENETFET

Ethernet & AirPort Support

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

5%

1/16W

100K

402

MF-LF

R3840

1 2

10K

402

1/16W

1%

MF-LF

R3841

1 2

9

SSM6N15FEAPE

SOT563

Q3841

3

5

4

9

SOT563

SSM6N15FEAPE

Q3801

3

5

4

10K

5%

402

MF-LF

1/16W

R3800

1

2

SI2312BDS

SOT23

CRITICAL

Q3840

3

1

2

69.8K

1/16W

1%

402

MF-LF

R3842

1

2

SOT563

SSM6N15FEAPE

Q3841

6

2

1

SSM6N15FEAPE

SOT563

Q3805

6

2

1

67 63 36 21 7

30 21

SOT563

SSM6N15FEAPE

Q3801

6

2

1

37 36 21

SSM6N15FEAPE

SOT563

Q3805

3

5

4

30

0.1UF

20%

CERM

10V

402

C3840

1

2

16V

0.01UF

CERM 402

10%

C3841

1

2

74 31

402

22

MF-LF

5%

1/16W

PLACEMENT_NOTE=Place close to U1400

R3895

1 2

74 18

MF-LF

402

100K

5%

1/16W

R3810

1 2

0.033UF

10%

402

X5R

16V

C3811

1

2

10%

402

0.01UF

16V

CERM

C3810

12

CRITICAL

NTR4101P

SOT-23-HF

Q3810

3

1

2

8

BI

PINS

SHIELD

TRAN_N0

TRAN_N3

TRAN_P3

TRAN_N1

TRAN_N2

TRAN_P2

TRAN_P1

TRAN_P0

ENET_MDI

RX

TX

RX

TX

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

514-0692

ETHERNET CONNECTOR

- COPY THIS PAGE FROM K36 CSA.39

PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902

39 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

ENET_MDI_N<0>

ENET_MDI_N<3>

ENET_MDI_P<0>

ENET_MDI_N<2>

PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS

ENET_CENTER_TAP<2>

ENET_CENTER_TAP<1>

ENET_CENTER_TAP<3>

ENET_CENTER_TAP<0>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENET_MDI_P<2>

ENET_CONN_CTAP

MIN_NECK_WIDTH=0.25MM

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6MM

ENET_MDI_TRAN_N<3>

ENET_MDI_TRAN_N<0>

ENET_MDI_TRAN_P<2>

ENET_MDI_TRAN_P<1>

ENET_MDI_TRAN_P<3>

ENET_MDI_TRAN_P<0>

ENET_MDI_TRAN_N<1>

ENET_MDI_TRAN_N<2>

ENET_MDI_N<1>

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

ETHERNET CONNECTOR

SM

TLA-6T213HF

CRITICAL

T3901

1

10

11

12

2

3

4

5

6 7

8

9

CRITICAL

SM

TLA-6T213HF

T3902

1

10

11

12

2

3

4

5

6 7

8

9

1000PF

CRITICAL

CERM 1206

10% 2KV

C3910

1

2

402

1/16W751%

MF-LF

R3903

1 2

1%

1/16W

402

MF-LF

75

R3902

1 2

1%

1/16W MF-LF

402

75

R3901

1 2

75

MF-LF1/16W

1% 402

R3900

1 2

10%

X5R

16V

402

0.1UF

C3903

1

2

10% 16V X5R

0.1UF

402

C3901

1

2

X5R

10%

402

16V

0.1UF

C3900

1

2

X5R

16V

402

10%

0.1UF

C3902

1

2

CRITICAL

F-R-TH

RJ45-10/100TX-K83

OMIT

J3900

10 11 12

9

2

6

5

8

1

3 4

7

CRITICAL

402-1

5%

10PF

CERM

50V

C3918

1

2

CRITICAL

402-1

50V CERM

10PF

5%

C3917

1

2

CRITICAL

402-1

10PF

50V

5%

CERM

C3916

1

2

10PF

CRITICAL

402-1

5%

CERM

50V

C3915

1

2

CRITICAL

402-1

50V CERM

10PF

5%

C3914

1

2

CRITICAL

402-1

50V

10PF

5%

CERM

C3913

1

2

CRITICAL

402-1

5%

10PF

50V CERM

C3912

1

2

CRITICAL

402-1

10PF

50V CERM

5%

C3911

1

2

74 31

74

OUT

S

G

D

NC

OUT

IN

SYM_VER-1

OUT

IN

D

SG

D

SG

SYM_VER-1

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SIL

518S0519

516S0616

ODD Power Control

ensure the drive is unpowered in S3/S5.

Indicates disc presence

SATA ODD

SATA HDD

516S0616

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

45 OF 109

PLACEMENT_NOTE=Place C4515 next to C4516

PLACEMENT_NOTE=Place C4511 next to C4510 PLACEMENT_NOTE=Place C4510 close to MCP79

PLACEMENT_NOTE=Place C4516 close to J4501

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

PLACEMENT_NOTE=Place FL4501 close to J4501

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYS_LED_ANODE_R

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_N

SATA_ODD_R2D_UF_P

=PP3V3_S0_ODD

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

PP5V_S0_HDD_R

ISNS_HDD_P

ISNS_HDD_N

ODD_PWR_EN_L

ODD_PWR_EN_LS5V_L

=PP3V3_S0_ODD

SATA_ODD_R2D_C_P

SATA_ODD_D2R_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_N

SATA_HDD_R2D_C_P

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_D2R_UF_N

SYS_LED_ANODE

SATA_HDD_D2R_UF_P

SATA_ODD_R2D_C_N

ISNS_ODD_P

=PP5V_S0_HDD

SATA_ODD_D2R_N

ISNS_ODD_N

SATA_HDD_R2D_C_N

SATA_HDD_R2D_UF_N

ODD_PWR_EN

PP5V_SW_ODD_R

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

ODD_PWR_SS

=PP5V_S3_ODD

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

SATA_ODD_R2D_P SATA_ODD_R2D_N

SMC_ODD_DETECT

SATA_HDD_R2D_P

SATA_HDD_R2D_UF_P

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.6mm

PP5V_S0_HDD_FLT

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

PP5V_SW_ODD

SYNC_DATE=01/19/2009

SATA Connectors

SYNC_MASTER=K24_MLB

54722-0164

CRITICAL

F-ST-SM

J4500

1

10

11 12

13 14

15 16

2

3 4

5 6

7 8

9

10% 402

CERM

0.01UF

16V

C4515

1 2

40216V10%

CERM

0.01UF

C4511

1 2

0.01UF

CERM

40210% 16V

C4510

1 2

10% 402

CERM

0.01UF

16V

C4516

1 2

72 20

CRITICAL

DLP11S

90-OHM-100MA

FL4502

1 2

34

0.1UF

CERM 402

20% 10V

C4502

1

2

CRITICAL

90-OHM-100MA

DLP11S

FL4501

12

3 4

CERM 402

10V

20%

0.1UF

C4501

1

2

0603

CRITICAL

FERR-70-OHM-4A

L4500

1 2

10% 402

CERM

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

16V

0.01UF

C4525

1 2

16V10% 402

CERM

0.01UF

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

C4526

1 2

16V10% 402

CERM

0.01UF

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

C4520

1 2

16V10% 402

CERM

0.01UF

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

C4521

1 2

10%

402

CERM

0.01UF

16V

C4596

1 2

10V

0.068UF

10% CERM

402

C4595

1

2

100K

1/16W

5%

MF-LF

402

R4595

1 2

1/16W

5%

402

MF-LF

100K

R4596

SOT563

SSM6N15FEAPE

Q4596

6

2

1

1/16W

5%

402

MF-LF

100K

R4597

SOT563

SSM6N15FEAPE

Q4596

3

5

4

72 20

DLP11S

CRITICAL

90-OHM-100MA

PLACEMENT_NOTE=Place FL4525 close to J4500

FL4525

1 2

34

PLACEMENT_NOTE=Place FL4520 close to J4500

CRITICAL

DLP11S

90-OHM-100MA

FL4520

12

3 4

21

402

33K

MF-LF

5%

1/16W

R4590

1

2

36 7

CRITICAL

23V1K-SM

TPCP8102

Q4590

5 6 7 8

4

1 2 3

76 47

CRITICAL

1206

MF

1/4W

0.002

1%

R4599

1 2 3 4

CRITICAL

MF

1/4W

1%

0.002

1206

R4598

123

4

CRITICAL

54722-0164

F-ST-SM

J4501

1

10 11 12 13 14 15 16

2

3 4 5 6 7 8 9

78171-0002

CRITICAL

M-RT-SM

J4502

3

4

1 2

CERM 402

0.001UF

50V

10%

C4531

1

2

4.7

MF-LF

402

5% 1/16W

R4531

12

7

72 7

72

34 8

72

37

72

8

72

8

72 7

72 7 72

7

47 7

OUT

BI

SYM_VER-1

IN

OUT

IN

SYM_VER-1

BI

OUT

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

IN

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1 OC2*

IN

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

We can add protection to 5V if we want, but leaving NC for now

Place L4600 and L4605 at connector pin

514-0689

CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION

We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.

SEL=1 Choose USB

SEL=0 Choose SMC

USB PORT B (BACK PORT)

USB/SMC Debug Mux

USB PORT A (FRONT PORT)

HAVE BEEN USED AS ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES

POR IS PLASTIC USB CONNECTOR PARTS BUT METAL PART’S SCHEMATIC AND CAD SYMBOLS

514-0689

Port Power Switch

46 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PP5V_S3_RTUSB_B_ILIM

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

PP5V_S3_RTUSB_A_ILIM

CONN_USB_EXTA_N

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

CONN_USB_EXTA_P

USB_EXTA_MUXED_P

USB_EXTA_MUXED_N

USB_EXTB_P

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_S3_RTUSB_B_F

MIN_NECK_WIDTH=0.5 mm

=USB_PWR_EN

=PP3V42_G3H_SMCUSBMUX

USB_EXTB_N

USB_DEBUGPRT_EN_L

SMC_TX_L

SMC_RX_L

USB_EXTA_P USB_EXTA_N

=PP5V_S3_EXTUSB

USB_EXTB_OC_L

USB_EXTA_OC_L

CONN_USB_EXTB_P

CONN_USB_EXTB_N

SYNC_DATE=02/05/2009

SYNC_MASTER=K24_MLB

External USB Connectors

RCLAMP0502N

SLP1210N6

CRITICAL

NOSTUFF

D4610

1

5 42 3

6

RCLAMP0502N

NOSTUFF

CRITICAL

SLP1210N6

D4600

1

5 42 3

6

OMIT

F-RT-TH

USB-K83

CRITICAL

J4610

1

2

3

4

5

6

7

8

OMIT

F-RT-TH

CRITICAL

USB-K83

J4600

1

2

3

4

5

6

7

8

MSOP

CRITICAL

TPS2064DGN

U4690

3

4

1

2

8

5

7

6

9

63

SMC_DEBUG_YES

PI3USB102ZLE

CRITICAL

TQFN

U4650

6

7

3

4

5

8

10

9

2

1

6.3V

603

10UF

X5R

20%

NOSTUFF

C4690

1

2

20

73 20

6.3V

CASE-B2-SM

POLY-TANT

20%

CRITICAL

100UF

C4616

1

2

6.3V X5R

10UF

603

20%

C4617

1

2

PLACEMENT_NOTE=NEAR J4610

DLP0NS

90-OHM

CRITICAL

L4610

1 2

34

FERR-220-OHM-2.5A

CRITICAL

PLACEMENT_NOTE=NEAR J4610

0603

L4615

1 2

0.01uF

CERM

20% 16V

402

C4615

1

2

20%

402

0.01uF

16V

CERM

C4605

1

2

MF-LF

1/16W

5%

402

0

SMC_DEBUG_NO

R4652

1 2

402

5%

0

MF-LF

1/16W

SMC_DEBUG_NO

R4651

1 2

36

38 37 36

PLACEMENT_NOTE=NEAR J4600

90-OHM

CRITICAL

DLP0NS

L4600

1 2

34

MF-LF 402

1/16W

10K

5%

R4650

1

2

402

10V

20%

SMC_DEBUG_YES

0.1UF

CERM

C4650

1

2

73 20

20

10V

0.1UF

20%

CERM 402

C4691

1

2

20%

10UF

6.3V X5R 603

C4695

1

2

POLY-TANT

100UF

CRITICAL

6.3V

20%

CASE-B2-SM

C4696

1

2

FERR-220-OHM-2.5A

CRITICAL

PLACEMENT_NOTE=NEAR J4600

0603

L4605

1 2

73

73 73

73

8

73

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

NOTE: P94 and P95 are shorted, P95 could be spare.

(See below)

(OC) (OC)

(OC)

(OC) (OC)

(DEBUG_SW_2)

(DEBUG_SW_1)

(OC)

(OC) (OC)

(OC)

.

SMC_IG_THROTTLE_L for MG systems.

SMC_PB3:

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

those designated as inputs require pull-ups.

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating,

49 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

ALS_LEFT

SMC_NB_DDR_ISENSE

SMC_FAN_3_CTL

SMC_RUNTIME_SCI_L

ALL_SYS_PWRGD RSMRST_PWRGD

SMC_PH2

PM_SLP_S5_L

PM_PWRBTN_L

SMC_FAN_2_CTL

SMC_EXCARD_CP

SMC_EXCARD_OC_L

GND_SMC_AVSS

SMC_PA5

MEM_EVENT_L

SMC_FAN_1_CTL

SMC_FAN_0_TACH

SMC_TMS

SMC_TDO

SMC_TCK

SMB_0_S0_DATA

PM_SLP_S3_L

SMC_BC_ACOK

SMC_RX_L

SMC_RSTGATE_L

=PP3V3_S5_SMC

SMC_BS_ALRT_L

SMC_ONOFF_L

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMB_0_S0_CLK

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMC_GFX_THROTTLE_L

SMS_ONOFF_L

SMB_MGMT_DATA

SMC_P41

LPC_SERIRQ

LPC_FRAME_L

LPC_AD<2>

ALS_GAIN

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_CLK

SMB_A_S3_DATA

SMB_BSA_CLK

SMB_BSA_DATA

=SMC_SMS_INT

SMC_MCP_SAFE_MODE

SMC_LID

SMC_SYS_LED

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_PB3

SMC_ODD_DETECT

PM_BATLOW_L

SYS_ONEWIRE

USB_DEBUGPRT_EN_L

PM_SYSRST_L

SMC_PA1

SMC_PA0

SMC_XTAL SMC_EXTAL

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC

PP3V3_S5_AVREF_SMC

SMC_TRST_L

SMC_MD1

SMC_KBC_MDE

SMC_VCL

SMC_NMI

SMC_RESET_L

PM_CLK32K_SUSCLK

SMC_WAKE_SCI_L

SMC_EXCARD_PWR_EN

PM_RSMRST_L

SMC_TDI

SMC_CASE_OPEN

LPC_AD<3>

SMC_LRESET_L

LPC_AD<1>

LPC_AD<0>

SMC_P26

SMC_P24

ESTARLDO_EN

IMVP_VR_ON

PM_SLP_S4_L

SMC_GPU_VSENSE

SMC_THRMTRIP

SMC_ADAPTER_EN

SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L

SMC_PM_G2_EN

SMC_GPU_ISENSE

SMC_NB_MISC_ISENSE

LPC_PWRDWN_L SMC_TX_L

PM_CLKRUN_L

SMB_MGMT_CLK

LPC_CLK33M_SMC

ALS_RIGHT

SMC_NB_CORE_ISENSE

SMC_ANALOG_ID

SMS_Y_AXIS SMS_Z_AXIS

SMC_FAN_1_TACH

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC

SYNC_MASTER=K24_MLB

SYNC_DATE=04/02/2009

37

39

73 25

37

63 37 21 7

67 63 32 21 7

39

9

73 25

25

73 38 19

402

0.033UF

X5R

16V

PLACEMENT_NOTE=PLACE C4952 CLOSE TO U4900 PIN K10

10%

C4952

1

2

402

0.033UF

X5R

16V

PLACEMENT_NOTE=PLACE C4951 CLOSE TO U4900 PIN N9

10%

C4951

1

2

402

0.033UF

X5R

16V

PLACEMENT_NOTE=PLACE C4950 CLOSE TO U4900 PIN M10

10%

C4950

1

2

H8S2117

OMIT

LGA-HF

U4900

M12

L11

L9

H3

A2

D1 H1

E5

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

OMIT

H8S2117

LGA-HF

U4900

N3 N1 M3 M2 N2 L1 K3 L2

B8 C9

B9 A10 C10 B10 C11 A11

G11 G13 F12 H13 G10 G12 H11 J13

M10

N9 K10

L8

M9

N8

K9

L7

K1 J3 K2 J1 K4 K5

N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 J2 A4 B3 C4

H8S2117

OMIT

LGA-HF

U4900

B12 A13 A12 B13 D11 C13 C12 D10

D13 E11 D12 F11 E13 E12 F13 E10

A9 D9 C8 B7 A8 D8 D7 D6

D4 A5 B4 A1 C2 B2 C1 C3

G2 F3 E4

L13 K12 K11 J12 K13 J10 J11 H12

N10 M11 L10 N11 N12 M13 N13 L12

A7 B6 C7 D5 A6 B5 C6

J4 G3 H2 G1 H4 G4 F4 F1

37

37 32 21

46

37

38 19

21

38

25

28 27 21

38 19

37

38 37 36 35

37

39

55 44 37

38 37

37

38 37

37

46

37

46

43

37

43

37

21

37

34 7

21

55

35

10K

MF-LF

5% 1/16W

402

R4998

1

2

NO STUFF

0

MF-LF

5% 1/16W

402

R4903

1

2

1/16W

5%

MF-LF

10K

402

R4902

1

2

MF-LF

10K

5% 1/16W

402

R4901

1

2

38

10K

MF-LF

5%

1/16W

402

R4909

1

2

39

63 57 7

38 37 36 35

55 37

37

41

40

41

37

40

41

20%

CERM

0.1UF

402

10V

C4906

1

2

37

63 25

63

21

20%

CERM

0.1UF

402

10V

C4905

1

2

59

21

SM

XW4900

12

20%

CERM

0.1UF

402

10V

C4904

1

2

PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PIN M12

5%

4.7

1/16W MF-LF

402

R4999

1 2

PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PIN M12

20%

CERM

0.1UF

402

10V

C4920

1

2

20%

0.1UF

10V

402

CERM

C4903

1

2

6.3V

0.47UF

CERM-X5R

402

10%

PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1

C4907

1

2

44 37

38 37

38 19

6.3V

20%

CERM

805

22UF

C4902

1

2

37

41 40 37

37

37 8

37

37 7

37

D

S G

IN

OUT

IN

OUT

IN

OUT

GND

OUT

IN

02

OUT

CD

GND

NC

OUT

IN

OUT

G

D

S

BI

IN

D

S G

D

G S

D

G S

OUT

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SMC Crystal Circuit

NC

SMC Reset "Button" / Brownout Detect

SMC AVREF Supply

PLACE R5016 ON TOP SIDE

PLACE R5015,R5001 ON BOTTOM SIDE

Debug Power "Button"

RADAR 5925345

TO SMC

SMC FSB to 3.3V Level Shifting

TO CPU

System (Sleep) LED Circuit

MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE

50 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYS_LED_L_VDIV

SYS_LED_ILIM

SMC_SYS_LED

=PP5V_S3_SYSLED

SYS_LED_ANODE

MCP_SPKR

=PP3V3_S5_SMC

SMC_RESET_L

SMC_RSTGATE_L

ALS_GAIN

NC_ALS_RIGHT

MAKE_BASE=TRUE

EXCARD_OC_L

SMC_P24

SMC_P41

ALS_LEFT

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

NC_SMC_PB3

MAKE_BASE=TRUE

SMC_EXCARD_PWR_EN

SMC_BIL_BUTTON_L

MAKE_BASE=TRUE

NC_SMC_BIL_BUTTON_L

SMC_FAN_2_CTL

SMC_GFX_THROTTLE_L

SMC_FAN_1_CTL

SMC_FAN_3_CTL

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

PM_THRMTRIP_L

CPU_PROCHOT_L

CPU_PROCHOT_L_R

CPU_PROCHOT_BUF

=PP3V3_S0_SMC

SMC_PROCHOT_3_3_L

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NC_ESTARLDO_EN

SMC_EXCARD_OC_L

=PP3V3_S5_SMC

MAKE_BASE=TRUE

NC_ALS_GAIN

MAKE_BASE=TRUE

TP_SMC_P24

SMC_MCP_DDR_ISENSE

MAKE_BASE=TRUE

SMC_THRMTRIP

SMC_EXTAL

SMC_ONOFF_L

=PP3V3_S0_SMC

SMC_XTAL

SMC_MANUAL_RST_L

SMC_PA0

SMC_PA1

MIN_LINE_WIDTH=0.4 mm

PP3V3_S5_AVREF_SMC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

SMC_BS_ALRT_L

MAKE_BASE=TRUE

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

=CHGR_ACOK

TP_SMC_P26

MAKE_BASE=TRUE

ESTARLDO_EN

SMC_FAN_2_TACH

SMC_ONOFF_L

SMC_LID

SMC_PH2

=PP3V3_S5_SMC

PM_SLP_S5_L

SMC_EXCARD_CP

PM_SLP_S4_L

SMC_PA5

SMC_BC_ACOK

SMC_GFX_OVERTEMP_L

SMC_FAN_1_TACH

SMC_FAN_3_TACH

SMC_CASE_OPEN

SMC_ADAPTER_EN

SMC_NB_MISC_ISENSE

SMC_GPU_ISENSE

SMC_PROCHOT

MAKE_BASE=TRUE

NC_SMC_ANALOG_ID

SMC_ANALOG_ID

SMC_GPU_VSENSE

SMC_P26

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

SMC_NB_DDR_ISENSE

SMC_NB_CORE_ISENSE

ALS_RIGHT

SMC_PB3

SMC_MCP_SAFE_MODE

MAKE_BASE=TRUE

SMS_INT_L=SMC_SMS_INT

SMC_ONOFF_L

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0V

GND_SMC_AVSS

MIN_NECK_WIDTH=0.2 mm

=PPVIN_S5_SMCVREF

SMC_TPAD_RST_L

SMC_TPAD_RST

SYS_LED_L

SMC_TX_L

SMC_RX_L

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

=PP3V3_S5_SMC

SMC Support

SYNC_MASTER=K24_MLB

SYNC_DATE=02/04/2009

ISL60002-33, INTERSIL

ALL

353S1381 353S1912

44 37 36

SOD-VESM-HF

SSM3K15FV

Q5032

3

1

2

SSM3K15FV

SOD-VESM-HF

Q5033

3

1

2

SSM6N15FEAPE

SOT563

Q5059

6

2

1

36

70 14 10

1/16W

5%

3.3K

402

MF-LF

R5062

1 2

SOT-563

DMB53D0UV

Q5060

5

3

4

MF-LF

1/16W

5%

100K

402

R5061

1

2

SOT-563

DMB53D0UV

Q5060

6

2

1

1/16W

5%

402

10K

MF-LF

R5060

1

2

36

10K

5% 1/16W MF-LF 402

R5010

1

2

402

5%

1/16W

0

MF-LF

R5011

1 2

36

NCP303LSN

SOT23-5-HF

CRITICAL

U5000

5

3

2

4

1

1/16W MF-LF 4025%

10K

R5054

1 2

10K

5% 1/16W MF-LF 402

R5055

1 2

5% 1/16W MF-LF 402

10K

R5053

1 2

1/16W MF-LF 4025%

10K

R5050

1 2

5%

10K

1/16W MF-LF 402

R5052

1 2

10K

5% 1/16W MF-LF 402

R5051

1 2

38 36

402

1K

MF-LF

5% 1/16W

R5000

1

2

0.1uF

402

CERM

20% 10V

C5000

1

2

10% 16V

CERM

402

0.01UF

C5001

1

2

SN74LVC1G02

SOT553-5

U5001

1

2

3

5

4

603

MF-LF

5% 1/10W

0

SILK_PART=SMC_RST

NOSTUFF

R5001

1

2

CERM

0.01UF

402

10% 16V

C5026

1

2

6.3V X5R

10uF

20%

603

C5025

1

2

REF3333

SOT23-3

CRITICAL

VR5020

3

1 2

SOD

2SA2154MFV-YAE

Q5030

1

3

2

34

10%

0.47UF

402

CERM-X5R

6.3V

C5020

1

2

402

80.6

1%

MF-LF

1/16W

R5030

1

2

1%

523

402

1/16W MF-LF

R5031

1

2

1% 1/16W MF-LF

402

1.47K

R5032

1

2

36

NOSTUFF

603

5%

MF-LF

0

1/10W

SILK_PART=PWR_BTN

R5016

1

2

470K

5% 1/16W 402MF-LF

R5087

1 2

CERM

15pF

50V

402

5%

C5010

1 2

402

50V

5%

CERM

15pF

C5011

1 2

CRITICAL

20.00MHZ

5X3.2-SM

Y5010

1

2

1/16W MF-LF

402

10K

5%

R5089

1 2

36

20 36

100K

MF-LF5% 1/16W 402

R5092

1 2

100K

1/16W5% MF-LF 402

R5091

1 2

NOSTUFF

1/10W

0

MF-LF

5%

603

SILK_PART=PWR_BTN

R5015

1

2

70 14 10

36

5%

100K

402MF-LF1/16W

R5090

1 2

MF-LF5% 1/16W

10K

402

R5088

1 2

5% 402MF-LF1/16W

10K

R5086

1 2

402MF-LF1/16W5%

10K

R5085

1 2

MF-LF 4025%

10K

1/16W

R5080

1 2

5% 402MF-LF1/16W

10K

R5079

1 2

1/16W

10K

5% MF-LF 402

R5078

1 2

5%

10K

402MF-LF1/16W

R5077

1 2

4021/16W5% MF-LF

100K

R5076

1 2

100K

5% MF-LF1/16W 402

R5074

1 2

MF-LF5% 402

10K

1/16W

R5073

1 2

10K

4021/16W MF-LF5%

R5072

1 2

100K

4021/16W5% MF-LF

R5071

1 2

402MF-LF5% 1/16W

10K

R5070

1 2

402

0

MF-LF

1/16W

5%

R5095

1 2

SOT563

SSM6N15FEAPE

Q5059

3

5

4

8

21

37 36 8

36

55 37 36

21

37 8

37 36 8

41

36

37 8

36

36 7

36

40

41

56

36

44 37 36

55 44 36

36

37 36 8

36

63 36 21 7

36

55 37 36

36

36 32 21

36

41

36

44 37 36

41 40 36

8

44

38 36 35

38 36

37 36 8

IN

BI

IN OUT OUT OUT

BI BI

IN OUT IN OUT OUT IN OUT IN

OUT OUT OUT

OUT IN

OUT

IN

BI

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

BI

VCC

GND

B1

A

S

B0

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516S0573

LPC+SPI Connector

Alternate SPI ROM Support

Pull-up on debug card

SEL HIGH OUTPUTS TO B1(ON BOARD ROM) SEL LOW OUTPUTS TO B0 (FRANKCARD ROM)

51 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MAKE_BASE=TRUE

SPIROM_USE_MLB

SPI_ALT_CS_L

SPI_ALT_MOSI

SPI_ALT_CLK

SPI_CLK_R

LPCPLUS_GPIO

SMC_RX_LSMC_TX_L

SPI_MOSI_R

SPI_MLB_CS_L

=SPI_CS1_R_L_USE_MLB

=PP3V3_S5_ROM

SPI_MISO

SPI_MOSI_R

=PP3V3_S5_ROM

SPI_CLK_R

SPI_ALT_MISO

SMC_MD1

=PP5V_S0_LPCPLUS

SMC_NMI

SMC_TMS DEBUG_RESET_L

SMC_TRST_L

SMC_TDO

LPC_AD<1>

LPC_AD<0>

SPI_ALT_MOSI

PM_CLKRUN_L

LPC_FRAME_L

SPI_ALT_MISO

=PP3V3_S5_LPCPLUS

SMC_RESET_L

LPC_AD<2>

LPC_CLK33M_LPCPLUS

LPC_AD<3>

SPIROM_USE_MLB SPI_ALT_CLK

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK

SPI_CS0_R_L

=PP3V3_S5_LPCPLUS

SYNC_MASTER=K24_MLB

SYNC_DATE=02/15/2009

LPC+SPI Debug Connector

73 38

CRITICAL

NC7SB3157P6XG

SC70

LPCPLUS

U5110

4 3

1

2

6

5

1/16W

5%

402

MF-LF

100K

R5140

1

2

21

73 38

73 48 38 21

38

10K

1/16W

402

MF-LF

5%

R5191

1

2

73 48 38 21

402

1/16W

5%

MF-LF

0

LPCPLUS

PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO

R5158

1 2

0

MF-LF

5%

1/16W

402

LPCPLUS

PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO

R5156

1 2

402

0

MF-LF

1/16W

LPCPLUS

5%

PLACEMENT_NOT=PLACENEXT TO WHERE IT BRANCHES INTO TWO

R5157

1 2

402

0

1/16W

5%

MF-LF

LPCPLUS_NOT

PLACEMENT_NOTE=PLACE NEXT TO U5110

R5146

1 2

73 48 21

73 48 38 21

73 36 19

73 48 38 21

73 21

MF-LF

5%

1/16W

402

10K

R5190

1

2

0.1UF

402

CERM

10V

20%

LPCPLUS

C5124

1

2

73 36 19

402

MF-LF

20K

5%

1/16W

R5144

1

2

73 25

48 38 48 38

38

37 36 35

36

18

37 36 35

36

37

36

25

37 36

36 19

73 36 19

73 38

73 36 19

55909-0374

CRITICAL

LPCPLUS

M-ST-SM

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

37 36

36 19

38

48 38 8

8

38 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SENSOR ADC CAN ONLY WORK IN S0 AS IT HAS I2C BUS PULLED UP TO S0 POWER RAIL

SMC

SMC "0" SMBus Connections

MCP79

SMC "B" SMBUS SIGNALS ALSO GET CONNECTED TO MCP SMBUS 1 CONNECTIONS(SEE LEFT SIDE)

(MASTER)

MCP79 SMBUS "0" CONNECTIONS

(See Table)

Battery Charger

SMC "Battery A" SMBus Connections

U1400

J6950

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "A" SMBus Connections

J5800

SMC

SMC "B" SMBus Connections

EMC1403-5: U5515

CPU Temp

SO-DIMM "A"

J3200

J3100

(MASTER)

U4900

U2901

U2900

Vref DACs

Margin Control

(Write: 0x30 Read: 0x31)

U4900

(MASTER)

(Write: 0x98 Read: 0x99)

(Write: 0x90 Read: 0x91)

TRACKPADMCP Temp

EMC1403-5: U5535

SENSOR ADC

(WRITE: 0X10 READ: 0X11)

U6000

BATTERY

(MASTER)

(Write: 0xA0 Read: 0xA1)

SMC

Mikey

U4900

U1400

(MASTER)

MCP79

(SLAVE: WRITE:0XE0 READ:0XE1)

SMC

(WRITE: 0X72 READ: 0X73)

U6880

SO-DIMM "B"

(Write: 0xA2 Read: 0xA3)

(Write: 0x98 Read: 0x99)

U6880

(WRITE: 0X72 READ: 0X73)

Mikey

(Write: 0x12 Read: 0x13)

U4900

MCP SMBUS1 ACTS AS SLAVE DEVICE FOR MCPSMC_DIGITEMP_YES STUFFED

(Write: 0x98 Read: 0x99)

U4900

SMC "B" SMBUS

U4900

SMC

MCP79 SMBUS "1" CONNECTIONS

ISL6258A - U7000

SMC "Management" SMBus Connections

The bus formerly known as "Battery B"

Battery Temp - (Write: 0x90 Read: 0x91)

Battery Manager - (Write: 0x16 Read: 0x17)

Battery

52 OF 109

051-7982

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=SMBUS_BATT_SCL

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

=I2C_SODIMMA_SDA

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

=PP3V3_S0_SMBUS_MCP_1

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

SMBUS_MCP_1_DATA

=I2C_MIKEY_SCL

SMBUS_MCP_1_CLK

=I2C_CPUTHMSNS_SCL

=I2C_VREFDACS_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

SMB_MGMT_CLK

=I2C_VREFDACS_SDA

SMB_MGMT_DATA

SMB_BSA_CLK

=I2C_MIKEY_SDA

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

I2C_MIKEY_SDA_R

=I2C_SODIMMA_SCL

=I2C_CPUTHMSNS_SDA

=I2C_SMC_ADCS_SCL

=I2C_MCPTHMSNS_SDA

=I2C_MCPTHMSNS_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=I2C_TPAD_SCL

=I2C_TPAD_SDA

SMB_A_S3_CLK

SMB_0_S0_DATA

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

I2C_MIKEY_SCL_R

SMB_BSA_DATA

I2C_MIKEY_SCL_R

SMB_A_S3_DATA

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

=SMBUS_BATT_SDA

=PP3V42_G3H_SMBUS_SMC_BSA

SMB_B_S0_CLK

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

=SMBUS_CHGR_SDA

=SMBUS_CHGR_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_MCP_0

MAKE_BASE=TRUE

I2C_MIKEY_SDA_R

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

SMB_B_S0_DATA

=I2C_SMC_ADCS_SDA

MAKE_BASE=TRUE

SMBUS_MCP_0_CLK

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

=PP3V3_S0_SMBUS_SMC_0_S0

SMB_0_S0_CLK

SYNC_DATE=01/19/2009

K84 SMBUS CONNECTIONS

SYNC_MASTER=K24_MLB

402

MF-LF

1/16W

5%

MCPSMC_DIGITEMP_YES

0

R5235

1

2

402

MF-LF

1/16W

0

MCPSMC_DIGITEMP_YES

5%

R5234

1

2

402

5% 1/16W MF-LF

MCPSMC_DIGITEMP_NO

0

R5233

1 2

402

1/16W

0

MF-LF

5%

MCPSMC_DIGITEMP_NO

R5232

1 2

MF-LF

5% 1/16W

0

MCPSMC_DIGITEMP_YES

402

R5203

1

2

1/16W

5%

0

402

MF-LF

MCPSMC_DIGITEMP_YES

R5204

1

2

5%

MF-LF 402

1/16W

4.7K

R5291

1

2

402

5%

1/16W

4.7K

MF-LF

R5290

1

2

MCPSMC_DIGITEMP_NO

5%

2.0K

MF-LF

402

1/16W

R5230

1

2

MCPSMC_DIGITEMP_NO

2.0K

5% 1/16W MF-LF 402

R5231

1

2

4.7K

402

MF-LF

5%

1/16W

R5250

1

2

4.7K

MF-LF

5% 1/16W

402

R5251

1

2

MF-LF

1K

1/16W

5%

402

R5270

1

2

1K

5%

402

MF-LF

1/16W

R5271

1

2

402

2.0K

5% 1/16W MF-LF

R5260

1

2

402

5% 1/16W MF-LF

2.0K

R5261

1

2

1K

MF-LF

1/16W

5%

402

R5281

1

2

MF-LF

1/16W

5%

1K

402

R5280

1

2

2.0K

402

MF-LF

1/16W

5%

R5201

1

2

402

2.0K

5% 1/16W MF-LF

R5200

1

2

55

75

27

28

39 36

8

75

73 21

54 39

73 21

42

26

75

36

26 36

36

54 39

39

27

42

47

42

8

45

36

26

8

39

36

39

36

75

55

8

39 36

56

8

39

75

39 36

47

73 21 13

8

36

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MCP Voltage Sense / Filter

CPU Voltage Sense / Filter

divider when high.

Place RC close to SMC

RTHEVENIN = 4573 OHMS

Place RC close to SMC

Enables PBUS VSense

PBUS VOLTAGE SENSE ENABLE & FILTER

53 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PBUSVSENS_EN_L_DIV

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm

PPBUS_G3HRS5_VSENSE

VOLTAGE=18.5V

PBUSVSENS_EN_L

=PBUSVSENS_EN

=PPBUS_G3HRS5

=PPVCORE_S0_MCP_VSENSE

GND_SMC_AVSS

SMC_PBUS_VSENSE

GND_SMC_AVSS

CPUVSENSE_IN

SMC_CPU_VSENSE

GND_SMC_AVSS

=PPVCORE_S0_CPU_VSENSE

MCPVSENSE_IN

SMC_MCP_VSENSE

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

VOLTAGE SENSING

PLACEMENT_NOTE=Place near U1000 center

SM

XW5309

1 2

402

0.22UF

20%

6.3V X5R

C5309

1

2

4.53K

1/16W

1%

402

MF-LF

R5309

1 2

36

PLACEMENT_NOTE=Place near U1400 center

SM

XW5359

1 2

SOT-963

NTUD3169CZ

Q5315

6

3

2

5

1

4

1% 1/16W MF-LF

402

5.49K

R5386

1

2

1%

402

MF-LF

1/16W

27.4K

R5385

1

2

402

6.3V

20%

X5R

0.22UF

C5385

1

2

36

MF-LF

100K

402

1%

1/16W

R5315

1

2

1%

1/16W

402

100K

MF-LF

R5316

1

2

63

1%

4.53K

1/16W MF-LF

402

R5359

1 2

402

0.22UF

6.3V X5R

20%

C5359

1

2

37

8

41 40 37 36

8

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

ININ

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DC-IN (AMON) CURRENT SENSE

DC-IN (BMON) CURRENT SENSE

Gain: 50x

Place RC close to SMC

CPU VCore Load Side Current Sense / Filter

Place RC close to SMC

MCP MEM VDD Current Sense Filter

PLACE R5401 AND C5490 CLOSE TO SMC

MCP VCore Current Sense Filter

MCP MEM VDD Current Sense

Place RC close to SMC

CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE

54 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

P1V5_S0_SENSE_AMP

P1V5_S0_SENSE_B

P1V5_S0_SENSE_E

P1V5_S0_SENSE

CHGR_BMON

=PP3V3_S0_MCPDDRISNS

ISNS_CPUVTT_P

ISNS_CPUVTT_N

=PPCPUVCORE_VTT_ISNS_R

MCPCORES0_IMON

P1V5_S0_KELVIN

=PP3V3_S0_CPUVTTISNS

=PPCPUVCORE_VTT_ISNS

SMC_DCIN_ISENSE

GND_SMC_AVSS

SMC_BATT_ISENSE

GND_SMC_AVSS

IMVP6_IMON

SMC_CPU_ISENSE

CPUVTT_IOUT

SMC_MCP_DDR_ISENSE

GND_SMC_AVSS

P1V5_S0_SENSE_C

SMC_CPU_FSB_ISENSE

CHGR_AMON

SMC_MCP_CORE_ISENSE

Current Sensing

SYNC_DATE=01/27/2009

SYNC_MASTER=K24_MLB

MEM_SENSE

SC70-5

OPA348

U5400

3

1

4

2

5

0.1uF

MEM_SENSE

10V CERM 402

20%

C5400

1

2

MEM_SENSE

402

0.1UF

10%

X5R

16V

C5434

1 2

402

MF-LF

1%

118

1/16W

MEM_SENSE

R5412

1

2

MF-LF

MEM_SENSE

0

402

5%

1/16W

R5411

1 2

MEM_SENSE

1/16W

0

MF-LF

5%

402

R5410

1

2

MEM_SENSE

2SA2154MFV-YAE

SOD

Q5401

1

3

2

64

402

0.22UF

20%

6.3V X5R

C5487

1

2

4.53K

MF-LF

1/16W

402

1%

R5481

1 2

36

1%

MF-LF

6.19K

1/16W

402

R5471

1 2

1/16W

1%

402

MF-LF

17.4K

R5480

1

2

59

20%

402

6.3V

0.22UF

X5R

C5470

1

2

36

X5R

20%

6.3V

402

0.22UF

C5490

1

2

MF-LF

1%

1/16W

402

4.53K

R5401

1 2

56

MEM_SENSE

4.53K

1/16W

1%

402

MF-LF

R5417

1 2

1% 1/16W MF-LF

402

4.53K

R5416

1 2

1P05_HIGH_SIDE_SENSE

1%

402

1/16W

4.53K

MF-LF

R5418

1 2

56 36

1P05_HIGH_SIDE_SENSE

6.3V

20%

402

X5R

0.22UF

C5436

1

2

37

8

1P05_HIGH_SIDE_SENSE

1W

0.5%

0.01

MF

0612-1

R5492

1 2 3 4

8

1P05_HIGH_SIDE_SENSE

SC70

INA213

U5402

2

5

4

6

1

3

1P05_HIGH_SIDE_SENSE

20% 10V

402

0.1uF

CERM

C5417

1

2

MEM_SENSE

20%

6.3V

402

0.22UF

X5R

C5435

1

2

37

64

0.22UF

6.3V

20%

X5R 402

C5472

1

2

37

8

76

60

8

41 40 37 36 41 40 37 36

41 40 37 36

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DETECT HEAT-PIPE TEMPERATURE

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

DETECT CPU DIE TEMPERATURE

PLACEMENT NOTE: PLACE U5535 NEAR MCP

DETECT MCP DIE TEMPERATURE

DETECT FIN-STACK TEMPERATURE

CPU T-Diode Thermal Sensor

PLACEMENT NOTE: PLACE U5515 NEAR CPU

APN 353S2571

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

MCP T-Diode Thermal Sensor

APN 353S2571

55 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP3V3_S0_MCPTHMSNS

=I2C_MCPTHMSNS_SDA

MCP_THMDIODE_P

MCPTHMSNS_THERM_L

MCPTHMSNS_ALERT_L

PP3V3_S0_CPUTHMSNS_R

MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

CPU_THERMD_N

CPU_THERMD_P

CPUTHMSNS_THERM_L

CPUTHMSNS_ALERT_L

=PP3V3_S0_CPUTHMSNS

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

=I2C_MCPTHMSNS_SCL

MCPTHMSNS_D2_N

PP3V3_S0_MCPTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

MCP_THMDIODE_N

MCPTHMSNS_D2_P

SYNC_DATE=02/04/2009

SYNC_MASTER=K24_MLB

Thermal Sensors

MCP_T_DIODE_SENSOR

5%

MF-LF

402

1/16W

47

R5535

1 2

SIGNAL_MODOL=EMPTY

50V

402

0.0022uF

10%

CERM

C5520

1

2

47

5% 1/16W MF-LF

402

R5515

1 2

10V CERM 402

20%

0.1uF

C5515

1

2

MCP_T_DIODE_SENSOR

SOT732-3

BC846BMXXH

PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION

Q5502

1

3

2

MCP_T_DIODE_SENSOR

DFN

CRITICAL

EMC1413

U5535

83

5

2

4

6

10

9

7

11

1

CRITICAL

DFN

EMC1413

U5515

83

5

2

4

6

10

9

7

11

1

SOT732-3

BC846BMXXH

Q5501

1

3

2

76 21

76 10

MCP_T_DIODE_SENSOR

402

50V

10%

CERM

SIGNAL_MODOL=EMPTY

0.0022uF

C5522

1

2

0.0022uF

SIGNAL_MODOL=EMPTY

10% 50V

CERM

402

C5521

1

2

MCP_T_DIODE_SENSOR

10V CERM 402

20%

0.1uF

C5535

1

2

39

MCP_T_DIODE_SENSOR

1%

MF-LF

1/16W

10K

402

R5536

1

2

MCP_T_DIODE_SENSOR

10K

MF-LF

5% 1/16W

402

R5537

1

2

1/16W

1%

402

MF-LF

10K

R5516

1

2

402

1/16W

5%

MF-LF

10K

R5517

1

2

39

MCP_T_DIODE_SENSOR

50V

402

10%

CERM

SIGNAL_MODOL=EMPTY

0.0022uF

C5540

1

2

8

76

D

GS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

518S0521

GND

MOTOR CONTROL

TACH

5V DC

56 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

FAN_RT_PWM

=PP5V_S0_FAN_RT =PP3V3_S0_FAN_RT

SMC_FAN_0_CTL

FAN_RT_TACH

SMC_FAN_0_TACH

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

Fan

M-RT-SM

78171-0004

CRITICAL

J5601

5

6

1 2 3 4

SOD-VESM-HF

SSM3K15FV

Q5660

3

1

2

100K

402

MF-LF

1/16W

5%

R5661

1

2

47K

1/16W MF-LF

402

5%

R5660

1

2

402

MF-LF

5%

1/16W

47K

R5665

1 2

7

8

36

7

36

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

Y

C

B

A

IN

OUT

IN

Y

B

A

Y

B

A

Y

B

A

NC

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

U5701 CHIP DECOUPLING

PLACE C5701, C5702 & C5703 CLOSE TO U5701

Alternate Parts

VDD PIN 22

TRACKPAD PICK BUTTONS KEYBOARD SCANNER

APN 311S0406

VDD

CLOSE TO U5701

18V BOOSTER

PSOC

IC

PIN NAME

V+

VOUT

VIN

CURRENT

80UA

10UA

R_SNS

2.55 KOHM

10 OHM

1.5 OHM

V_SNS POWER

0.012 V

0.255E-6 W

294E-6 W

75.2E-6 W

USB INTERFACES TO MLB

TO MLB CONNECTOR

APN 518S0637

LID CLOSE => SMC_LID_LC < 0.50V

LID OPEN => SMC_LID_LC ~ 3.42V

WHEN THE LID IS CLOSED

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

THE TPAD BUTTONS WILL BE DISABLE

PLACE THESE COMPONENTS CLOSE TO J5800

ISOLATION CIRCUIT

TPAD BUTTONS DISABLE

VDD PIN 49

PLACE C5704, C5705 & C5706

TMP102

SPI HOST TO Z2

0.204 V

0.6 V

0.0255 V

3V3 LDO

14MA (MAX)

60MA MAX

0.72E-3 W

36E-3 W

0.012 V

16.32E-6 W

96E-6 W

4MA (MAX)

4.7 OHM

0.0188 V

0.021 V

0.2 OHM

8MA (TYP)

VDD

60MA MAX

ISSP SDATA/I2C SDA

ISSP SCLK/I2C SCL

NC

KEYBOARD CONNECTOR

APN 337S2983

PSOC USB CONTROLLER

SMC_MANUAL_RESET LOGIC

57 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

WS_KBD15_C

WS_KBD16_NUM

SMC_ONOFF_L

TP_P7_7

TP_ISSP_SCLK_P1_1

WS_KBD15_CAP

WS_KBD1

PSOC_MISO

WS_KBD13

WS_KBD12

WS_KBD8

WS_KBD23

Z2_RESET

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KEY

DIFFERENTIAL_PAIR=USB2_TPAD

USB_TPAD_R_N

WS_KBD4

TP_ISSP_SDATA_P1_0

Z2_CLKIN

WS_KBD14

PP3V3_S3_PSOC

WS_KBD11

PICKB_L

=PP3V3_S3_TPAD

WS_KBD2 WS_KBD3 WS_KBD4

WS_LEFT_SHIFT_KEY

WS_CONTROL_KEY

=PP3V42_G3H_TPAD

PSOC_F_CS_L

WS_CONTROL_KBD

WS_KBD6

SMC_LID

BUTTON_DISABLE

WS_KBD17 WS_KBD16N

WS_KBD8

WS_KBD2

WS_KBD5 WS_KBD6

WS_KBD18

WS_KBD17

WS_KBD14

WS_KBD11

WS_KBD10

WS_KBD9

WS_KBD21

WS_KBD20

WS_KBD19

WS_KBD22

WS_LEFT_SHIFT_KBD

=PP3V42_G3H_TPAD

WS_LEFT_OPTION_KBD WS_CONTROL_KBD

WS_KBD7

TP_PSOC_SDA

PP3V3_S3_PSOC

TP_PSOC_SCL

WS_KBD22

USB_TPAD_P

WS_KBD5

=PP3V3_S3_TPAD

WS_KBD15_C

WS_KBD12

WS_KBD10 WS_KBD9

WS_KBD3

TP_PSOC_P1_3

WS_KBD13

WS_KBD23

WS_KBD21

WS_KBD19

WS_KBD7

WS_KBD18

SMC_TPAD_RST_L

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD

=PP3V42_G3H_TPAD

WS_KBD20

WS_LEFT_OPTION_KBD

BUTTON_DISABLE

WS_KBD1

=PP3V42_G3H_TPAD

=PP3V3_S3_TPAD

WS_LEFT_OPTION_KBD

=PP3V3_S3_TPAD

USB_TPAD_N

Z2_DEBUG3

TP_P4_5

Z2_KEY_ACT_L

PSOC_MOSI

WS_CONTROL_KBD

=PP3V3_S3_TPAD

WS_LEFT_SHIFT_KBD

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_S3_PSOC

Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY

Z2_CS_L

Z2_MISO

Z2_SCLK

PSOC_SCLK

Z2_MOSI

WS_CONTROL_KEY

WS_KBD16N

WS_KBD_ONOFF_L

SYNC_MASTER=K24_MLB

SYNC_DATE=03/04/2009

WELLSPRING 1

311S0406 311S0447

ALL

NXP PART AS ALTERNATE

402

10V

20%

CERM

0.1UF

C5725

12

CRITICAL

SOT665

TC7SZ08AFEAPE

U5725

2

1

3

5

4

402

0.1UF

20%

CERM

10V

C5726

12

402

CERM

10V

20%

0.1UF

C5727

12

CRITICAL

SOT665

TC7SZ08AFEAPE

U5727

2

1

3

5

4

CRITICAL

TC7SZ08AFEAPE

SOT665

U5726

2

1

3

5

4

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

44 8

10K

1%

1/16W

402

MF-LF

R5715

1 2

402

1% 1/16W MF-LF

113

R5714

1 2

402

MF-LF

1/16W

5%

1K

R5710

1 2

0.1UF

CERM 402

10V

20%

PLACEMENT_NOTE=NEAR J5713

C5710

1

2

55 37 36

MF-LF

5%

1.5

1/16W

402

R5704

1 2

SC70

SN74LVC1G10

CRITICAL

U5703

2

1

3

6

4

5

24

1/16W

5%

MF-LF

402

R5701

1 2

CRITICAL

MLF

CY8C24794

OMIT

U5701

20

21

45544653475248

51

25182617271628

15

412

421

435644

55

3310

349

358

367

376

385

394

403

2914

3013

3112

3211

24

235722 49

19

50

24

402

5%

1/16W MF-LF

R5702

1 2

20%

X5R 603

6.3V

4.7UF

C5701

1

2

402

CERM

50V

5%

100PF

PLACEMENT_NOTE=PLACE C5702 CLOSE TO U5701 VDD PIN 22

C5702

1

2

0.1UF

10%

402

X7R-CERM

16V

C5703

1

2

5%

100PF

50V CERM 402

PLACEMENT_NOTE=PLACE C5704 CLOSE TO U5701 VDD PIN 49

C5704

1

2

402

0.1UF

X7R-CERM

16V

10%

C5705

1

2

4.7UF

20%

6.3V X5R 603

C5706

1

2

402

MF-LF

1/16W

5%

33K

R5769

1

2

33K

402

MF-LF

5%

1/16W

R5770

1

2

402

MF-LF

33K

5% 1/16W

R5771

1

2

X7R-CERM

0.1UF

10%

402

16V

C5758

1

2

SSM3K15FV

SOD-VESM-HF

Q5701

3

1

2

44

7

37 36

7

44 7

45 7

44 7

45 7

44 7

44

73

44 7

45 7

44 7

44

44 7

45 7

44 7

44

44 8

45 7

44 7

44

44 7

44

44 7

44 8

44 7

44

44 7

73 20

44 7

44 8

44

44 7

37

73

44 8

44 7

44

44 7

44 8

44 7

44 8

73 20

45 7

44 7

44 8

44 7

44

45 7

44

45 7

44

7

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

VDD

VOUT

GND

CE

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3V3 LDO FOR IPD

IPD FLEX CONNECTOR

APN 353S1401

APN 353S1364

APN 152S0504

APN 371S0313

BOOSTER +18.5VDC FOR SENSORS

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

BOOSTER DESIGN CONSIDERATION:

- DROOP LINE REGULATION

- POWER CONSUMPTION

APN 516S0689

NC

58 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MIN_LINE_WIDTH=0.50MM

PP5V_S3_BOOSTER

MIN_NECK_WIDTH=0.20MM

PP5V_S3_VR

=PP5V_S3_TPAD

PP3V3_S3_LDO_R

Z2_RESET

PP18V5_S3

PSOC_MOSI PSOC_SCLK

=I2C_TPAD_SCL

PSOC_F_CS_L

Z2_BOOST_EN

PP3V3_S3_LDO

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP18V5_S3_SW

BOOST_SW

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

SWITCH_NODE=TRUE

Z2_CS_L

PSOC_MISO

Z2_BOOST_EN

Z2_MOSI

Z2_KEY_ACT_L

PICKB_L

=I2C_TPAD_SDA

0.20MM

0.50MM

PP3V3_S3_LDO

0.50MM

PP18V5_S3

0.20MM

Z2_CLKIN

Z2_HOST_INTN

Z2_SCLK

Z2_MISO

Z2_DEBUG3

=PP5V_S3_TPAD

INPUT_SW

0.50MM

0.20MM

BOOST_FB

0.50MM

0.20MM

WELLSPRING 2

SYNC_MASTER=K24_MLB

SYNC_DATE=02/25/2009

0.1UF

20% 10V

402

CERM

PLACEMENT_NOTE=NEAR J5800

C5800

1

2

402

1%

MF-LF

1/16W

71.5K

R5813

1

2

1M

402

1% 1/16W MF-LF

R5812

1

2

39PF

402

CERM

5% 50V

C5818

1

2

1%

402

MF-LF

1/16W

10

R5873

1 2

20%

6.3V X5R 603

4.7UF

C5854

1

2

0.1UF

X7R-CERM 402

16V

10%

C5838

1

2

1%

1/6W

MF

402-HF

0.2

R5836

1

2

CRITICAL

MLF

MM3243DRRE

VR5802

1

4

2

3

X5R

16V

10%

2.2UF

603

C5853

1

2

1%

MF-LF

1/16W

402

100K

R5811

1

2

3.3UH-870MA

VLF3010AT-SM-HF

CRITICAL

L5801

CRITICAL

TPS61045

QFN

U5805

53

4

617

8

9

2

2.2UF

10%

603

X5R

16V

C5817

1

2

0

402

MF-LF

1/16W

5%

R5805

1 2

0.1UF

16V X7R-CERM

10%

402

C5816

1

2

1/16W MF-LF

0

5%

402

R5806

1 2

1UF

X5R

25V

10%

603-1

C5819

1

2

B0520WSXG

SOD-323

CRITICAL

D5802

M-ST-SM

55560-0228

CRITICAL

J5800

1

10

1112

1314

1516

1718

19

2

20

2122

34

56

78

9

45 8

44 7

45 7

44 7

39

44 7

45 7

44 7

45 7

44 7

39

45 7 45 7

44 7

45 8

OUT

IN

GND

SEL0

VDD

ST

SEL1

DNC

AZ

AY

AX

AMUX

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ

R5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC

+Z (up)

Analog SMS

Front of system

+X

+Y

in correct orientation

Circle indicates pin 1 location when placed

placed on board top-side:

Desired orientation when

59 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SMS_ONOFF_L

MAKE_BASE=TRUE

SMS_PWRDN

PP3V3_S3_SMS_FILT

=PP3V3_S3_SMS

SMS_Y_AXIS

SMS_X_AXIS

SMS_Z_AXIS

SMS

MF-LF

10K

402

1/16W

5%

R5921

1

2

MF-LF

10

402

5%

1/16W

R5922

1 2

NOSTUFF

402

16V

10%

0.033UF

X5R

C5925

1

2

NOSTUFF

10%

X5R

16V

0.033UF

402

C5924

1

2

402

16V

0.01UF

10%

CERM

C5926

1

2

BMA141

LGA

CRITICAL

U5920

11

10

9

8

7

3

4

12

6

5

1

2

36

16V

10%

X5R 402

0.1UF

C5922

1

2

36

NOSTUFF

16V X5R

0.033UF

402

10%

C5923

1

2

8

COM

GND

THRM

DVDDAVDD

AD0 AD1

SDA SCL

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

VREF

REFCOMP

PAD

BI

IN

V+

REFIN+

IN-

OUT

GND

+IN

-IN

V+

V-

+IN

-IN

V+

V-

+IN

-IN

V+

V-

+IN

-IN

V+ V-

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LSB: 0.001V

GAIN: 200X

I2C ADDRESS: 0X10 / 0X11 ADC RANGE: 0V TO 4.096V

DIVIDER: ~ 2/3

DIVIDER: ~ 2/5

GAIN: 1239X GAIN: 561X

GAIN: 845X

GAIN: 273X

DIVIDER: 1/22

60 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PP5V_S3_DEBUG_ADC_DVDD_FILT

ADC_CH7

=I2C_SMC_ADCS_SDA

=PP5V_S3_DEBUG_ISNS

ADC_CH3

ADC_CH1

=PP5V_S3_DEBUG_ADC_AVDD

ADC_VREF

ADC_SCL

ADC_CH0

=I2C_SMC_ADCS_SCL

ADC_SDA

=PP5V_S3_DEBUG_ADC_DVDD

ISNS_LCDBKLT_IOUT

PPVOUT_S0_LCDBKLT_DIV

ISNS_HDD_IOUT

ISNS_HDD_R_N

ADC_CH7

ISNS_HDD_P

ISNS_1V5_S3_IOUT

ISNS_ODD_N

=PP5V_S3_DEBUG_ISNS

ISNS_ODD_IOUT

ISNS_ODD_R_N

ISNS_ODD_P

ISNS_ODD_R_P

ISNS_1V5_S3_R_P

ADC_CH1

PP5V_SW_ODD_DIV

PP3V3_WLAN_F_DIV

ISNS_AIRPORT_R_N

ISNS_AIRPORT_P

ADC_CH3

PP5V_SW_ODD_XW

PP5V_SW_ODD

ADC_CH4

ADC_CH5

ADC_CH4

ADC_REFCOMP

ADC_CH6

ADC_CH2

PP3V3_WLAN_F_XW

PPVOUT_S0_LCDBKLT_XW

PPVOUT_S0_LCDBKLT

ADC_CH6

ISNS_1V5_S3_P

ISNS_1V5_S3_N

ADC_CH5

ISNS_HDD_R_P

ISNS_HDD_N

PP3V3_WLAN_F

ADC_CH2

ISNS_AIRPORT_IOUT

ISNS_AIRPORT_R_P

ISNS_AIRPORT_N

ISNS_1V5_S3_R_N

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

=PP5V_S3_DEBUG_ISNS

ADC_CH0

PP5V_S3_DEBUG_ADC_AVDD_FILT

SYNC_MASTER=K19_IMLB SYNC_DATE=02/25/2009

DEBUG SENSORS AND ADC

1%

MF-LF

1/16W

412

DEBUG_ADC

402

R6061

1 2

MF-LF

1%

DEBUG_ADC

1/16W

499

402

R6050

1 2

MF-LF

499

1/16W

1%

402

DEBUG_ADC

R6051

1 2

76 34

2.2UF

20%

6.3V 402-LF

CERM

DEBUG_ADC

C6006

1

2

DEBUG_ADC

50V

470PF

CERM

402

10%

C6062

1

2

1%

DEBUG_ADC

348K

MF-LF

1/16W 402

R6062

1

2

470PF

10%

402

50V

CERM

DEBUG_ADC

C6063

1 2

DEBUG_ADC

348K

MF-LF

1/16W

1%

402

R6063

1 2

CERM

50V

10%

470PF

DEBUG_ADC

402

C6052

1

2

DEBUG_ADC

280K

1% MF-LF

402

1/16W

R6052

1

2

DEBUG_ADC

50V 402

470PF

CERM

10%

C6053

1 2

DEBUG_ADC

280K

MF-LF

1/16W

1%

402

R6053

1 2

1%

DEBUG_ADC

226K

MF-LF

1/16W

402

R6064

1 2

0.1UF

CERM 402

10V

20%

DEBUG_ADC

C6040

1

2

DEBUG_ADC

226K

MF-LF

1/16W

1%

402

R6054

1 2

0.1UF

DEBUG_ADC

CERM 402

10V

20%

C6000

1

2

PLACEMENT_NOTE=PLACE RC NEAR U6000

6.3V

10%

DEBUG_ADC

2.2UF

X5R 402

C6064

1

2

DEBUG_ADC

PLACEMENT_NOTE=PLACE RC NEAR U6000

2.2UF

10% X5R

6.3V 402

C6054

1

2

76 58

DEBUG_ADC

402

1/16W MF-LF

1%

3.65K

R6041

1 2

DEBUG_ADC

402

1%

MF-LF

1/16W

3.65K

R6040

1 2

DEBUG_ADC

10%

CERM

402

50V

470PF

C6042

1

2

1M

402

1/16W

1%

DEBUG_ADC

MF-LF

R6042

1

2

DEBUG_ADC

402

50V

10%

470PF

CERM

C6043

1 2

1%

1/16W

1M

MF-LF

402

DEBUG_ADC

R6043

1 2

MF-LF

1/16W

402

1%

DEBUG_ADC

226K

R6044

1 2

PLACEMENT_NOTE=PLACE RC NEAR U6000

10%

402

DEBUG_ADC

X5R

2.2UF

6.3V

C6044

1

2

10V

20%

402

CERM

0.1UF

DEBUG_ADC

C6004

1

2

DEBUG_ADC

1/16W

1%

MF-LF

226K

402

R6034

1 2

PLACEMENT_NOTE=PLACE RC NEAR U6000

6.3V

DEBUG_ADC

10% X5R

2.2UF

402

C6034

1

2

76 30

CERM 402

20% 10V

0.1UF

DEBUG_ADC

C6030

1

2

1%

1/16W

402

DEBUG_ADC

MF-LF

301K

R6033

1 2

DEBUG_ADC

243

1% 1/16W MF-LF

402

R6030

1 2

1/16W

402

MF-LF

1%

DEBUG_ADC

243

R6031

1 2

DEBUG_ADC

402

10%

CERM

470PF

50V

C6033

1 2

DEBUG_ADC

1/16W

1%

402

MF-LF

301K

R6032

1

2

402

CERM

10% 50V

DEBUG_ADC

470PF

C6032

1

2

76 30

DEBUG_ADC

0.1UF

10V

20%

402

CERM

C6002

1

2

MF-LF

681K

402

DEBUG_ADC

1% 1/16W

R6021

1

2

402

1/16W MF-LF

1M

DEBUG_ADC

1%

R6020

1

2

DEBUG_ADC

MF-LF

226K

1/16W

1%

402

R6022

1 2

PLACEMENT_NOTE=PLACE RC NEAR U6000

10%

2.2UF

X5R

6.3V 402

DEBUG_ADC

C6022

1

2

6.3V

DEBUG_ADC

10%

2.2UF

X5R 402

PLACEMENT_NOTE=PLACE RC NEAR U6000

C6012

1

2

DEBUG_ADC

226K

MF-LF

1/16W

1%

402

R6012

1 2

1M

402

1% 1/16W MF-LF

DEBUG_ADC

R6011

1

2

MF-LF

1/16W

1%

634K

402

DEBUG_ADC

R6010

1

2

OMIT

SM

PLACEMENT_NOTE=PLACE NEAR Q4590

XW6020

1 2

OMIT

SM

PLACEMENT_NOTE=PLACE NEAR Q3450

XW6010

1 2

DEBUG_ADC

6.3V X5R 603

20%

10UF

C6001

1

2

MF-LF

402

5%

1/16W

10

DEBUG_ADC

R6004

1 2

DEBUG_ADC

5%

10

1/16W

402

MF-LF

R6003

1 2

402

DEBUG_ADC

10V

20% CERM

0.1UF

C6031

1

2

402

20% 10V CERM

0.1UF

DEBUG_ADC

C6041

1

2

DEBUG_ADC

10UF

603

X5R

6.3V

20%

C6003

1

2

DEBUG_ADC

SC70-5

OPA330

U6031

3

4

1

2

5

OPA330

SC70-5

DEBUG_ADC

U6030

3

4

1

2

5

DEBUG_ADC

SC70-5

OPA330

U6041

3

4

1

2

5

OPA330

SC70-5

DEBUG_ADC

U6040

3

4

1

2

5

PLACEMENT_NOTE=PLACE CLOSE TO U4900

33

5%

1/16W

402

MF-LF

DEBUG_ADC

R6002

1 2

33

PLACEMENT_NOTE=PLACE CLOSE TO U4900

DEBUG_ADC

402

5% 1/16W MF-LF

R6001

1 2

DEBUG_ADC

SC70

INA210

U6050

2

5

4

6

1

3

MF-LF

DEBUG_ADC

47.0K

1% 1/16W

402

R6081

1

2

DEBUG_ADC

MF-LF

1M

402

1/16W

1%

R6080

1

2

DEBUG_ADC

6.3V

20%

603

X5R

10UF

C6005

1

2

OMIT

SM

PLACEMENT_NOTE=PLACE NEAR D9710

XW6080

1 2

DEBUG_ADC

226K

1%

MF-LF

1/16W

402

R6082

1 2

DEBUG_ADC

PLACEMENT_NOTE=PLACE RC NEAR U6000

6.3V

10% X5R

2.2UF

402

C6082

1

2

402

20%

0.1UF

CERM

10V

DEBUG_ADC

C6050

1

2

76 68

39

DEBUG_ADC

226K

1/16W

1%

402

MF-LF

R6074

1 2

DEBUG_ADC

6.3V

10%

2.2UF

PLACEMENT_NOTE=PLACE RC NEAR U6000

X5R 402

C6074

1

2

DEBUG_ADC

412

MF-LF

1/16W

1%

402

R6060

1 2

39

QFN

DEBUG_ADC

LTC2309

U6000

14 15

12

13

22 23 24

1 2 3 4 5

6

21

9

1011181920

8

16

17

25

7

47

47 8

47

8

47

8

76

47 8

76

47

76

47

34 7

47

68 65 7

47

76

30

47

76

47 8

47

ININ

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER SIZE

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PAGE TITLE

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A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

31 MHz

MCP79 SPI Frequency Select

Frequency

25 MHz

1 MHz

42 MHz

0

1

0

1

SPI_MOSI

0

SPI_CLK

1

0

1

61 OF 109

25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SPI_MLB_CS_L

SPI_CLK_R

SPI_CLK

SPI_WP_L

=PP3V3_S5_ROM

SPI_MOSI

SPI_HOLD_L

SPI_MISO_R

SPI_MOSI_R

SPI_MISO

SYNC_DATE=02/15/2009

SYNC_MASTER=K24_MLB

SPI ROM

402

MF-LF

3.3K

5% 1/16W

R6101

1

2

20%

402

CERM

10V

0.1UF

C6100

1

2

10K

1/16W

5% MF-LF

402

NO STUFF

R6191

1

2

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6105

1 2

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6152

1 2

73 38 21

32MBIT

MX25L3205DM2I-12G

CRITICAL

OMIT

SOP

U6100

1

4

7

6

5

2

8

3

38

73 38 21

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%

1/16W

0

402

R6150

1 2

10K

1/16W MF-LF

5%

402

NO STUFF

R6190

1

2

5%

3.3K

1/16W MF-LF

402

R6100

1

2

73 38 21

73

38 8

73

IN

OUT

IN

OUT

OUT OUT

OUT

IN IN IN IN

IN

OUT

IN

OUT

NR/FB

NC

IN

EN

GND

OUT

OUT OUT

IN IN IN

OUT

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

/SPDIF_OUT2

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

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SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL

GPIO3 = SPKR AMP SHDN CONTROL

GPIO1 = HP AMP CONTROL

4.5V POWER SUPPLY FOR CODEC

NOTES ON CODEC I/O

NC

APPLE P/N 353S2355

AUDIO CODEC

NC

NC NC

FR SPKR AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

EXT MIC CODEC INPUT

BI MIC CODEC INPUT

DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS

APPLE P/N 353S2456

DAC2/3 FSOUTPUTSE= 1.34VRMS

GPIO0 = ANALOG SW CONTROL

62 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

VOLTAGE=1.8V MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM

=PP1V8_S0_AUDIO

AUD_LO1_P_R

GND_AUDIO_HP_AMP

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

TP_AUD_GPIO_2 AUD_GPIO_3

CS4206_FLYP CS4206_FLYC

AUD_LO2_N_R

AUD_LO2_P_R

AUD_LO2_N_L

AUD_CODEC_MICBIAS

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

MIN_LINE_WIDTH=0.5MM

CS4206_VREF_ADC

CS4206_FLYN

4V5_NR

4V5_REG_IN

VOLTAGE=5V

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

GND_AUDIO_CODEC

HDA_RST_L

PP1V8_S0_AUDIO_DIG

VBIAS_DAC

AUD_LI_REF

AUD_LI_P_L

AUD_MIC_INP_L

TP_AUD_DMIC_CLK

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

=PP3V3_S0_AUDIO

4V5_REG_EN

=PP5V_S3_AUDIO

PP4V5_AUDIO_ANALOG

AUD_MIC_INN_L

AUD_MIC_INN_R

AUD_MIC_INP_R

AUD_LI_P_R

GND_AUDIO_HP_AMP

=PP3V3_S0_AUDIO

=PP5V_S3_AUDIO

CS4206_VCOM

TP_AUD_SPDIF_IN

GND_AUDIO_HP_AMP

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

AUD_SDI_RHDA_SDIN0

AUD_SPDIF_OUT_CHIP

AUD_SPDIF_OUT

AUD_SENSE_A

AUD_GPIO_1

AUD_GPIO_0

CS4206_FN

CS4206_FP

AUD_HP_PORT_REF

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

AUD_HP_PORT_L

MIN_NECK_WIDTH=0.10MMMIN_LINE_WIDTH=0.20MM

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM

TP_AUD_LO1_P_L TP_AUD_LO1_N_L

AUD_LO1_N_R

AUD_LO2_P_L

AUDIO: CODEC/REGULATOR

SYNC_MASTER=AUDIO

SYNC_DATE=06/09/2009

MF-LF

1/16W

402

22

5%

R6211

1 2

MF-LF

1/16W

402

22

5%

R6212

1 2

POLY-TANT

20%

10UF

CASE-B2-SM

16V

CRITICAL

C6225

1

2

53

CRITICAL

QFN

CS4206ACNZC

U6201

26

6

7

4

43 42

45

2

12

14 15

38 40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

19

11

8 5

13

47 48

10

49

25

46

24

29

28

9

41

44

3

1

27

51

50

FERR-220-OHM

0402

L6201

1 2

402

MF-LF

5%

NOSTUFF

1/16W

0

R6201

1 2

SM

PLACE NEAR U6200

XW6200

1 2

52

0.1UF

10%

402

X7R-CERM

16V

C6202

1

2

CRITICAL

SON

TPS71745

U6200

4

2

6

5

3

1

10V

402-1

X5R

10%

1UF

C6216

1

2

49 7

53

49 7

8

49 7

53

54 53 49 8

53 51 49 8

16V

20%

TANT-POLY

10UF

2012-LLP

C6219

1

2

TANT-POLY

20% 16V

2012-LLP

10UF

C6217

1

2

402

10% 16V

0.1UF

X5R

C6218

1

2

100K

402

5% 1/16W MF-LF

NOSTUFF

R6213

1

2

2.67K

1/16W

402

MF-LF

1%

R6210

1

2

0.1UF

X5R

10%

402

16V

C6214

1

2

X5R

16V

0.1UF

402

10%

C6211

1

2

16V

402

X5R

10%

0.1UF

C6215

1

2

1UF

10% 10V X5R 402

C6200

1

2

1%

MF-LF

402

1/16W

2.21K

R6200

1 2

0402

FERR-220-OHM

L6200

1 2

10% 10V

402

X5R

1UF

C6203

1

2

402

X5R

10V

10%

1UF

C6201

1

2

CRITICAL

10UF

6.3V

20%

X5R 603-1

C6213

1

2

54

52

51

52

54

73 21

4.7UF

4V X5R

20%

402

C6210

1

2

0603-SM

TANT

1UF

16V

20%

C6224

1

2

CRITICAL

20%

6.3V X5R

10UF

603-1

C6220

1

2

402-LF

CERM

6.3V

20%

2.2UF

C6223

1

2

CERM 402-LF

20%

6.3V

2.2UF

C6222

1

2

SM

PLACE NEAR C6220 AND C6221

XW6201

1 2

20%

X5R

6.3V

10UF

CRITICAL

603-1

C6221

1

2

53 51 49

54 53 50 49

53 51 49

54 53 49 8

53 51 49 8

53 51 49

54 53 50 49

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS FC_HP = 3.6 HZ

NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS) FC_LP = 43KHZ

63 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

AUD_LI_REF

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_R

GND_AUDIO_CODEC

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_P_R

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_L

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_L_DIV

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_GND

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUDIO: LINE INPUT FILTER

10

1%

402

MF-LF

1/16W

R6300

1

2

NOSTUFF

50V CERM 402

820PF

10%

C6313

1

2

NOSTUFF

50V CERM 402

820PF

10%

C6303

1

2

MF-LF

1/16W 402

1%

21.5K

R6312

1

2

MF-LF

1/16W 402

1%

21.5K

R6302

1

2

MF-LF

1/16W

402

1%

7.87K

R6311

1 2

MF-LF

1/16W

402

1%

7.87K

R6301

1 2

2.2UF

402

10V

20%

X5R-CERM

CRITICAL

C6311

1 2

20%

402

10V

2.2UF

CRITICAL

X5R-CERM

C6312

1 2

20% 10V

2.2UF

X5R-CERM

402

CRITICAL

C6302

1 2

402

10V

2.2UF

CRITICAL

X5R-CERM

20%

C6301

1 2

54 53 49

49

53

SVSS

INL

SHDN*

INR

VDD

PVSS

PGND

SGND

THRM

OUTR

OUTL

C1P C1N

PAD

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

APN: 353S1637

HP/LO AMP

NC

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

AV_PB = -1V/V, FC_LPF = 35.2KHZ

MAX9724 GAIN/FILTER COMPONENTS

65 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

AUD_LO_AMP_INL_M

GND_AUDIO_HP_AMP

AUD_GPIO_1

AUD_LO_AMP_OUTR

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

AUD_LO_AMP_OUTL

MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM

AUD_LO_AMP_OUTR

AUD_HP_PORT_R

AUD_HP_PORT_L

AUD_LO_AMP_INL_M

=PP5V_S3_AUDIO

AUD_LO_AMP_INR_M

GND_AUDIO_HP_AMP

AUD_HP_ZOBEL_R

AUD_HP_PORT_R

AUD_LO_AMP_INR_M

AUD_HP_ZOBEL_L

AUD_GPIO_1_R

MAX9724_SVSS

AUD_LO_AMP_OUTL

MAX9724_C1N

MAX9724_C1P

MIN_LINE_WIDTH=0.3MM

AUD_PP5V_F

MIN_NECK_WIDTH=0.2MM

AUD_HP_PORT_L

SYNC_DATE=06/09/2009

SYNC_MASTER=AUDIO

AUDIO: HEADPHONE FILTER

51 49

53 51 49

51 49

1%

2.21K

402

1/16W MF-LF

R6524

1

2

1%

2.21K

1/16W 402

MF-LF

R6523

1

2

53 51

49

51 49

5%

1/16W

402

MF-LF

0

R6520

1 2

50V COG 402

330PF

5%

CRITICAL

C6531

1 2

330PF

5%

CRITICAL

COG 402

50V

C6530

1 2

MF-LF

1/16W

402

13.7K

1%

R6532

1 2

402

MF-LF

1/16W

13.7K

1%

R6533

1 2

MF-LF

402

13.7K

1%

1/16W

R6530

1 2

1/16W

402

MF-LF

13.7K

1%

R6531

1 2

402

5% MF-LF

1/16W

100K

R6522

1

2

FERR-120-OHM-1.5A

0402-LF

L6520

1 2

X7R-CERM

0.1UF

402

10% 16V

C6520

1

2

6.3V

20%

10UF

X5R 603

C6521

1

2

1UF

X5R

10V 402

10%

CRITICAL

C6524

1

2

1UF

10V 402

10%

CRITICAL

X5R

C6523

1

2

CRITICAL

10%

1UF

402

X5R

10V

C6522

1

2

CRITICAL

TQFN

MAX9724A

U6500

3

1

6 8

11 10

247

5

9

13

12

1/16W

402

39

5%

MF-LF

R6510

1

2

402

X7R-CERM

16V

10%

0.1UF

CRITICAL

C6510

1

2

5% 1/16W MF-LF

402

39

R6500

1

2

402

16V

10%

X7R-CERM

0.1UF

CRITICAL

C6500

1

2

51

53 51 49

51

53 49 8

51

IN

IN-

SD*

IN+

OUTA

PVDD

GND

PGND

OUTB

VDD

CPVSS

OUT-

C1N

C1P

SD*

IN-

IN+

OUT+

SVDD

PGND SVSS

PVDD

CPVSS

OUT-

C1N

C1P

SD*

IN-

IN+

OUT+

SVDD

PGND SVSS

PVDD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

APN:353S2630

SATELLITE

DYNAMIC (SUB) AND PIEZO (SATELLITE) SPKR AMPLIFIERS

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

HPF FC = 775 HZ

SAT GAIN

APN:353S2630

SUB GAIN

SUB

APN:353S2621

5.6DB (1.91V/V)

6DB (2V/V)

80 HZ < HPF FC < 132 HZ

66 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

LM48311_R_N

LM48311_SUB_N

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT

SPKRAMP_R_N_OUT_R

LM48311_SUB_P

MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_SUB_N_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_SUB_P_OUT

MIN_NECK_WIDTH=0.20 MM

AUD_LO2_N_R

LM48556_C1P_R

LM48556_C1N_R

SPKRAMP_INSUB_P

SPKRAMP_INSUB_N

AUD_LO2_N_L

LM48556_C1P_L

LM48556_VSS_L

LM48556_C1N_L

LM48311_R_N_C

LM48311_R_P_C

SPKRAMP_INR_P

SPKRAMP_INR_N

AUD_LO2_P_L

LM48311_L_P_C

SPKRAMP_INL_P

SPKRAMP_INL_N

SPKRAMP_L_P_OUT_R

AUD_LO2_P_R

AUD_GPIO_3

SPKRAMP_SHDN

=PP5V_S3_AUDIO_AMP

LM48311_L_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT

SPKRAMP_L_N_OUT_R

SPKRAMP_SHDN

AUD_LO1_N_R

AUD_LO1_P_R

LM48311_L_N

SPKRAMP_SHDN

LM48311_L_N_C

SPKRAMP_R_N_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

LM48556_VSS_R

LM48311_R_P

=PP5V_S3_AUDIO_AMP

SPKRAMP_R_P_OUT_R

=PP5V_S3_AUDIO_AMP

AUDI0: SPEAKER AMP

SYNC_MASTER=AUDIO

SYNC_DATE=06/09/2009

402

CRITICAL

10%

0.015UF

16V X7R

C6631

1 2

16V X7R 402

10%

0.015UF

CRITICAL

C6630

1 2

0.015UF

10%

402

X7R

16V

CRITICAL

C6611

1 2

16V X7R 402

0.015UF

10%

CRITICAL

C6610

1 2

CERM

50V

180PF

NO STUFF

402

5%

C6634

1 2

1%

26.1K

402

1/16W MF-LF

R6634

1 2

NO STUFF

5%

180PF

402

CERM

50V

C6635

1 2

MF-LF

1/16W

26.1K

1%

402

R6635

1 2

MF-LF

1/8W

805

6.8

5%

OMIT

R6630

1 2

MF-LF

1/8W

805

6.8

5%

OMIT

R6633

1 2

1/16W

1%

13.7K

402

MF-LF

R6632

1 2

MF-LF

402

1%

1/16W

13.7K

R6631

1 2

180PF

NO STUFF

50V

CERM

402

5%

C6613

1 2

NO STUFF

180PF

50V

CERM

402

5%

C6612

1 2

5%

6.8

1/8W

MF-LF

OMIT

805

R6617

1 2

805

1/8W

5%

MF-LF

6.8

OMIT

R6612

1 2

MF-LF

26.1K

1%

402

1/16W

R6616

1 2

1%

26.1K

402

1/16W MF-LF

R6615

1 2

13.7K

MF-LF

402

1%

1/16W

R6614

1 2

402

1/16W

1%

13.7K

MF-LF

R6613

1 2

CRITICAL

10% 16V X5R-CERM 0805

10UF

C6605

1

2

CRITICAL

10V X5R 805

10%

4.7UF

C6633

1

2

10%

0805

X5R-CERM

16V

10UF

CRITICAL

C6632

1

2

BGA

CRITICAL

LM48556TL

U6630

D1

C2

C1

B3

A3

A1

B2

D2

D3

C3

A2

B1

10UF

CRITICAL

0805

16V X5R-CERM

10%

C6601

1

2

10%

4.7UF

805

X5R

10V

CRITICAL

C6604

1

2

0805

10UF

10% X5R-CERM

CRITICAL

16V

C6602

1

2

CRITICAL

BGA

LM48556TL

U6610

D1

C2

C1

B3

A3

A1

B2

D2

D3

C3

A2

B1

CRITICAL

LM48311

BGA

U6620

C2

C1

A1

A3 C3

B3

B2A2B1

49

0402

FERR-1000-OHM

L6631

1 2

49

0402

FERR-1000-OHM

L6621

1 2

10%

402

16V

0.1UF

X5R

CRITICAL

C6621

1 2

49

FERR-1000-OHM

0402

L6611

1 2

100K

5% MF-LF

402

1/16W

R6611

1

2

16V

CRITICAL

402

0.1UF

10% X5R

C6620

1 2

49

402

1/16W

0

MF-LF

5%

R6610

1 2

CRITICAL

47UF

20%

6.3V TANT1 2012-LLP

C6603

1

2

1UF

402

10% X5R

10V

C6608

1

2

402

1UF

10V

X5R

10%

C6609

1

2

49

0402

FERR-1000-OHM

L6630

1 2

0402

FERR-1000-OHM

L6610

1 2

FERR-1000-OHM

0402

L6620

1 2

1UF

10V

X5R 402

10%

C6607

1

2

49

53 7

52

52 8

53 7

52

53 7

52 8

IN IN

IN

OUT

BI

VCC

COM1

COM2

EN*

NC1

CB

NO1

NEG

GND

NO2

NC2

IN

OUT

IN

IN IN

OPERATING VOLTAGE 3.3

B - VCC

SHELL

SHIELD

PINS

HP DETECT

GND

PHS DETECT

AUDIO

A - VIN

POF

C - GND

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

APN:514-0694

RT. PIEZO

DYN. FULL RANGE

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

APN:518S0520

MIC CONNECTOR

SPEAKER CONNECTORS

APN: 353S2536

GND STUFFING OPTIONS FOR CMOS SWITCH

APN:518S0519

LEFT PIEZO

ANALOG AUDIO IO SWITCH

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

67 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SPKRAMP_SUB_N_OUT_CONN

SPKRAMP_SUB_P_OUT_CONN

AUD_CONNJ1_TIPDET

AUD_CONNJ1_TIP

AUD_IP_PERPH_DET_JACK

AUD_J1_TIPDET_R

HS_MIC_LO

AUD_IP_PERPH_DET

AUD_LO_AMP_OUTR

AUD_SWITCH_GND

AUD_LI_R

AUD_CONN_GND

GND_AUDIO_CODEC

SWITCH_CP

AUD_SWITCH_CTRL

MIN_LINE_WIDTH=0.2MM

AUD_CONN_R

MIN_NECK_WIDTH=0.15MM

AUD_LO_AMP_OUTR_SWITCH

AUD_LI_R_SWITCH

AUD_LO_AMP_OUTL_SWITCH

AUD_LI_L_SWITCH

BI_MIC_HI

HS_MIC_HI

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

AUD_CONN_L

BI_MIC_LO

AUD_LI_L

AUD_GPIO_0

AUD_LO_AMP_OUTL

PP_MAX14504_VCC

=PP5V_S3_AUDIO

AUD_HP_PORT_REF

AUD_LI_GND

MIN_LINE_WIDTH=0.4MM

AUD_CONN_GND

MIN_NECK_WIDTH=0.2MM

AUD_CONN_GND

GND_AUDIO_HP_AMP

AUD_CONN_L

AUD_CONN_R

BI_MIC_SHIELD

AUD_J1_SLEEVEDET_R

SPKRAMP_L_N_OUT

SPKRAMP_L_P_OUT

AUD_SPDIF_OUT

SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT

SPKRAMP_SUB_P_OUT

AUD_CONNJ1_SLEEVEDET

SPKRAMP_SUB_N_OUT

SPKRAMP_R_N_OUT_CONN

SPKRAMP_R_P_OUT_CONN

AUD_CONNJ1_RING

AUD_CONNJ1_MIC

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

AUD_CONNJ1_SLEEVE

=PP3V3_S0_AUDIO

SYNC_MASTER=AUDIO

AUDIO: JACK

SYNC_DATE=06/09/2009

402

5%

50V

100PF

CERM

C6701

1

2

1/16W

5%

MF-LF

402

4.7

R6701

1 2

5%

10K

MF-LF

1/16W

402

R6700

1 2

54

0402

CRITICAL

FERR-220-OHM

L6704

1 2

CRITICAL

0402

FERR-220-OHM

L6705

1 2

0402-LF

CRITICAL

FERR-120-OHM-1.5A

L6703

1 2

49

CRITICAL

78171-0003

M-RT-SM

J6704

4

5

1 2 3

0603

FERR-120-OHM-3A

CRITICAL

L6710

1 2

0603

FERR-120-OHM-3A

CRITICAL

L6709

1 2

0603

CRITICAL

FERR-120-OHM-3A

L6708

1 2

FERR-120-OHM-3A

0603

CRITICAL

L6707

1 2

0402

FERR-1000-OHM

L6706

1 2

54

CRITICAL

402

6.8V-100PF

DZ6702

1

2

F-RT-TH

AUDIO-JACK-TRANS-K83

OMIT

CRITICAL

J6700

1

12 13 14

2

3 4

5

6

7

8

9 10 11

5%

50V

100PF

CERM

402

C6707

1

2

5%

100PF

402

CERM

50V

C6706

1

2

50V

5%

402

CERM

100PF

C6705

1

2

5%

402

50V

100PF

CERM

C6704

1

2

50V

5%

100PF

402

CERM

C6703

1

2

CERM

50V

5%

100PF

402

C6702

1

2

402

MF-LF

1/16W

5%

24K

R6713

1

2

402

MF-LF

1/16W

5%

24K

R6712

1

2

PLACE NEAR J6700

SM

XW6702

1 2

52 7

M-RT-SM

78171-0002

CRITICAL

J6703

3

4

1 2

49

51

50

402

1/16W

0

5%

MF-LF

NOSTUFF

R6727

1 2

MF-LF

1/16W

5%

402

0

R6724

1 2

10V

1UF

X5R

10%

402

C6710

1

2

5%

MF-LF 402

1/16W

100K

R6721

1

2

WLP

MAX14504

CRITICAL

U6700

C2

B4

B1

B2

B3

C3

C4

C1

A2

A4

A1

A3

402

MF-LF

1/16W

5%

0

R6720

1 2

53

0

5%

402

1/16W MF-LF

R6716

1 2

402

MF-LF

1/16W

0

5%

R6719

1 2

1/16W

5%

0

MF-LF

402

R6718

1 2

0

402

1/16W

5%

MF-LF

R6717

1 2

402

1/16W MF-LF

5%

0

R6715

1 2

MF-LF

0

402

1/16W

5%

R6714

1 2

53

PLACE NEAR J6700

SM

XW6701

1 2

PLACE NEAR J6700

SM

XW6700

1 2

CERM

50V

402

10%

0.0033UF

C6711

1

2

49

402

CRITICAL

6.8V-100PF

DZ6701

1

2

54

FERR-1000-OHM

0402

L6701

1 2

FERR-1000-OHM

0402

L6702

1 2

CRITICAL

78171-0003

M-RT-SM

J6701

4

5

1

2

3

402

CRITICAL

6.8V-100PF

DZ6705

1

2

402

CRITICAL

6.8V-100PF

DZ6700

1

2

CRITICAL

6.8V-100PF

402

DZ6703

1

2

CRITICAL

402

6.8V-100PF

DZ6704

1

2

CRITICAL

M-RT-SM

78171-0002

J6702

3

4

1

2

52 7

402

6.3V

1UF

10% CERM

C6700

1

2

53

54 50 49

54 7

51 49 8

50

53 53

51 49

54 7

54 49 8

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

IN

OUT

IN

OUT

IN

BI

IN

OUT

IN

GND THM

ENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASSINT*

SCL

D

SG

D

SG

VEE1

VEE0 VCC

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

0X08 (8)

PORT B RIGHT(BUILT-IN MIC)

PORT A DETECT (HEADPHONES)

DET ASSIGNMENT

MCP79 GPIO_17 (PERIPH DETECT) MCP79 GPIO_4 (LOAD DETECT)

MCP79 GPIO_38

MIC_BIAS (80%)

PORT B DETECT(SPDIF DELEGATE)

NC

N/A

VREF/ENABLE

GPIO_0 AND GPIO_1

0X0D (13,V22,B,LEFT)

GPIO_3

COMP. TRIP PT. = 2.64V

PULLUPS ON MCP PAGE

0X06 (6)

DRC MIKEY

APN:353S2256

PIN COMPLEX

HP=80HZ, LP=8.82KHZ

HEADSET MIC

0X02 (2)

CONVERTER

PORT B LEFT(HEADSET MIC)

HP=80HZ

N/A

0X04 (4)

SPDIF OUT

SUB

N/A

0X09 (A) AND UI ELEMENT

0X09 (9,A)

0X0B (11)

MUTE CONTROL

DET ASSIGNMENT 0X09 (A)

0X0D (B)

NC

0X06 (6)

APN:376S0613

0X0C (12)

GPIO_3

N/A

0X03 (3)

FUNCTION

CODEC INPUT SIGNAL PATHS

0X04 (4)

0X05 (5)

0X02 (2)

HP/LINE OUT LINE IN SATELLITES

BUILT-IN MIC

0X10 (16)

0X0A (10)

CONVERTER

OUTPUT HIGH WHEN MIC BIAS LOADED OUTPUT LOW WHEN MIC BIAS UNLOADED

0X0D (13,B,RIGHT)

PIN COMPLEX

0X03 (03)

0X05 (5)

VOLUME

CODEC OUTPUT SIGNAL PATHS

MIKEY MIC LOAD DET CKT

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

EXTRACTION NOTIFICATION CKT

68 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM

VOLTAGE=3.3V

PP3V3_S0_AUDIO_F

AUD_J1_TIPDET_INV

AUD_IP_PERPH_DET

AUD_PERPH_DET_R

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

AUD_J1_SLEEVEDET_INV

AUD_IP_PERIPHERAL_DET

GND_AUDIO_CODEC

PERPH_DET_FILT

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

PP3V3_S0_AUDIO_F

AUD_OUTJACK_INSERT_L

GND_AUDIO_CODEC

MIC_LOAD_COMP_OUT

HS_MIC_HI

HS_MIC_BIAS_COMP

MIKEY_MIC_LOAD_DET

HS_MIC_BIAS

HS_RX_BP

HS_MIC_HI_RC

AUD_IPHS_SWITCH_EN

=I2C_MIKEY_SCL

GND_AUDIO_CODEC

AUD_MIC_INN_L

MIC_BIAS_FILT

BI_MIC_HI

AUD_CODEC_MICBIAS

AUD_MIC_INN_R

AUD_MIC_INP_L

BI_MIC_LO

PP3V3_S0_HS_RX

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM VOLTAGE=3.3V

=PP3V3_S0_AUDIO

PP3V3_S0_AUDIO_F

AUD_J1_DET_RC

AUD_J1_TIPDET_R

PP3V3_S0_AUDIO_F

AUD_I2C_INT_L

=I2C_MIKEY_SDA

BI_MIC_SHIELD

GND_AUDIO_CODEC

HS_MIC_BIAS

HS_SW_DET

HS_MIC_HI

AUD_PORTA_DET_L

HS_MIC_LO

AUD_PORTB_DET_L

AUD_SENSE_A

AUD_MIC_INP_R

GND_AUDIO_CODEC

BI_MIC_HI_F

BI_MIC_LO_F

AUDIO: JACK TRANSLATORS

SYNC_DATE=06/09/2009

SYNC_MASTER=AUDIO

402

1/16W

5%

300K

MIKEY

MF-LF

R6862

1

2

1/16W

0

MIKEY_LOAD_DET

5%

MF-LF

402

R6873

1 2

9

MIKEY_LOAD_DET

MF-LF

1/16W

1%

402

100K

R6872

1

2

X5R

16V

10%

0.1UF

402

MIKEY_LOAD_DET

C6872

1

2

MIKEY_LOAD_DET

100K

402

1/16W MF-LF

1%

R6871

1

2

MIKEY_LOAD_DET

MF-LF

2.21K

1/16W 402

1%

R6870

1

2

MIKEY_LOAD_DET

50V CERM

5%

402

27PF

C6870

1

2

MIKEY_LOAD_DET

50V CERM 402

27PF

5%

C6871

1

2

UCSP

CRITICAL

MAX9028EBT+

MIKEY_LOAD_DET

U6870

B3

B1

A2

A1

A3

B2

5% 1/16W

300K

402

MF-LF

R6801

1

2

MIKEY

MF-LF

1/16W

5%

100K

402

R6865

1

2

220K

MIKEY

402

5% 1/16W MF-LF

R6864

1

2

10V CERM 402

20%

0.1UF

MIKEY

C6860

1

2

MIKEY

5%

1/16W

15K

MF-LF

402

R6860

1 2

MIKEY

SOT563

SSM6N15FEAPE

Q6802

3

5

4

MIKEY

SOT563

SSM6N15FEAPE

Q6802

6

2

1

MIKEY

6.3V

10%

1UF

CERM 402

CRITICAL

C6880

1

2

CD3275

DRC

MIKEY

U6880

3

10

2

8

9

4

7

1

6

5

11

54 53 49 8

FERR-1000-OHM

0402

L6862

1 2

402

CERM

0.1UF

20%

10V

C6861

1

2

402

MIKEY

0

1/16W

5%

MF-LF

R6861

17

402-1

1/16W

1%

MF

2.4K

R6853

1 2

100

402

1% 1/16W MF-LF

R6850

1 2

402

10% 25V

0.1UF

CRITICAL

X5R

C6851

1 2

49

402

25V

10%

X5R

0.1UF

MIKEY

CRITICAL

C6886

1 2

MIKEY

2.2K

5%

402

MF-LF

1/16W

R6884

1 2

19

39

21

20%

MIKEY

402

6.3V TANT

CRITICAL

2.2UF

C6882

1

2

FERR-1000-OHM

MIKEY

0402

L6880

1 2

16V

MIKEY

402

CERM

0.01UF

10%

C6881

1

2

MIKEY

1/16W

402

100K

MF-LF

5%

R6880

1

2

1/16W

1K

MF-LF

1%

402

MIKEY

R6881

1

2

49

PLACE NEAR C6886

SM

XW6880

1 2

402

CRITICAL

MIKEY

25V

10%

X5R

0.1UF

C6883

1 2

1/16W MF-LF 402

MIKEY

100K

5%

R6883

1

2

MIKEY

X7R

CRITICAL

10%

25V 402

0.0082UF

C6884

1

2

CERM

5%

50V 402

CRITICAL

27PF

MIKEY

C6885

1

2

MF-LF 402

MIKEY

5%

2.2K

1/16W

R6882

1

2

53

54 53

0402

FERR-1000-OHM

L6850

1 2

0402

FERR-1000-OHM

L6851

1 2

CRITICAL

2.2UF

20%

6.3V TANT 402

C6852

1

2

53 7

49

PLACE NEAR J6701

SM

XW6851

1 2

MF-LF

1/16W

5%

100K

402

R6852

1

2

10%

CRITICAL

50V

0.001UF

CERM

402

C6853

1

2

CRITICAL

0.1UF

X5R

402

25V

10%

C6850

1 2

CRITICAL

27PF

5%

402

CERM

50V

C6854

1

2

MF

402-1

1%

1/16W

2.4K

R6851

1 2

SOT563

SSM6N15FEAPE

Q6801

6

2

1

SSM6N15FEAPE

SOT563

Q6801

3

5

4

SOT563

SSM6N15FEAPE

Q6800

6

2

1

SSM6N15FEAPE

SOT563

Q6800

3

5

4

402

20.0K

1%

MF-LF

1/16W

R6805

1

2

54 53

49

16V CERM

0.01UF

10%

402

C6802

1

2

5%

MF-LF

1/16W

220K

402

R6804

1

2

MF-LF

402

220K

1/16W

5%

R6803

1 2

MF-LF

1% 1/16W

39.2K

402

R6806

1

2

53

5%

402

MF-LF

1/16W

47K

R6802

1 2

10V

20% CERM

0.1UF

402

C6801

1

2

54

53

54 53 50 49

54 53

54 53 50 49

54

54 53 50 49

54 53

54

54 53 50 49

54 53 49 8

54

54 53 50 49

54

54 53 50 49

NC

VCC

EXTINT

NC

GND

BI

Y

B

A

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

P3 P4 P5 P6 P7 P8

P1 P2

P9

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

HALL EFFECT CONNECTOR

516S0787

BATTERY CONNECTOR

Vout = 1.25V * (1 + Ra / Rb)

1-Wire OverVoltage Protection

NC

<Ra>

<Rb>

518-0359

(Switcher limit)

250MA MAX OUTPUT

Vout = 3.425V

518S0656

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

MagSafe DC Power Jack

69 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

ADAPTER_SENSE_R

MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P3V42G3H_SW

DIDT=TRUE

=SMBUS_BATT_SDA

SYS_DETECT_L

=SMBUS_BATT_SCL

=PP3V42_G3H_ONEWIRE

ADAPTER_SENSE

SYS_ONEWIRE

SMC_BC_ACOK

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.3 mm

PPDCIN_S5_P3V42G3H

MIN_NECK_WIDTH=0.3 mm

=PP18V5_DCIN_CONN

SMC_BC_ACOK_VCC

=PP18V5_DCIN_CONN

P3V42G3H_BOOST

DIDT=TRUE

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.4 mm

PPVIN_G3H_P3V42G3H

MIN_NECK_WIDTH=0.2 mm

BATT_POS_F

SMC_LID

BATT_POS_F

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 mm VOLTAGE=12.6V

P3V42G3H_FB

=PP3V42_G3H_REG

=PP3V42_G3H_HALL

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=1mm

PP18V5_DCIN_FUSE

SMC_LID_R

SYNC_DATE=02/05/2009

SYNC_MASTER=K24_MLB

DC-In & Battery Connectors

F-ST-SM

ASP-146700-03

J6955

1 2 3 4 5 6

33UH-20%-0.44A-0.455OHM

CRITICAL

D52LC-SM

L6995

1 2

M-RT-TH

CRITICAL

BAT-K24

J6950

10 11 12 13

1 2 3 4 5 6 7 8 9

2.0K

402

5%

1/16W

MF-LF

ONEWIRE_PU

R6929

1 2

LT3470A

DFN

CRITICAL

U6990

2

3

1

5

7

8 4

9

6

1/16W

5%

MF-LF

0

402

R6961

1 2

10%

NOSTUFF

0.001UF

402

CERM

50V

C6955

1

2

402

1/16W MF-LF

5%

10K

R6950

1

2

TC7SZ08AFEAPE

SOT665

U6901

2

1

3

5

4

36

SC70-5

MAX9940

U6900

5

2

4

3

1

PLACEMENT_NOTE=PLACE NEAR U6901

0.1UF

402

CERM

10V

20%

C6908

1

2

SC-75

CRITICAL

RCLAMP2402B

NOSTUFF

D6950

3

1

2

CRITICAL

6AMP-24V

1206-1

F6905

1 2

10%

402

25V X5R

0.1UF

C6950

1

2

402

MF-LF

1/16W

5%

0

R6928

1 2

HN2D01JEAPE

SOT665

D6905

1

3

5

4

2

M-RT-SM

78048-0573

CRITICAL

J6900

1

2

3

4

5

805

5%

1/8W

47

MF-LF

R6905

1 2

10% 25V X5R 805

10UF

C6990

1

2

402

200K

MF-LF

1/16W

1%

R6996

1

2

22pF

50V

402

CERM

5%

C6995

1

2

1% 1/16W MF-LF

348K

402

R6995

1

2

X5R 402

20%

6.3V

0.22uF

C6994

1

2

6.3V

20%

CERM

CRITICAL

805

22UF

C6999

1

2

50V

0.01UF

603

20%

CERM

C6905

1

2

39

7

39

8

7

37 36

55 8

56 55 7

44 37 36

56 55 7

8

7

GND

VCC

D

SG

D

SG

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF ACIN

SDA

VHST SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

D

G

S

D1

D3

D4

S3 S2

GATE

S1

D2

D1

D3

D4

S3 S2

GATE

S1

D2

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PBUS SUPPLY / BATTERY CHARGER

(CHGR_ACIN)

(CHGR_CSON)

MAX CURRENT = 7A

(CHGR_CSOP)

(CHGR_CSO_R_N)

(??? limited)

PWM FREQ. = 400 kHz

TO SYSTEM

BATTERY CHARGE LIMITING FETS

AMON PULLDOWN LOGIC

70 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=SMBUS_CHGR_SDA

CHGR_ICOMP

GND_CHGR_SGND

CHGR_BGATE

BATT_POS_F

=PP3V42_G3H_CHGR

CHGR_AGATE CHGR_CSIP CHGR_CSIN

CHGR_BGATE

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.3 MM

PPVDCIN_G3H_PRE

CHGR_LOWCURRENT_GATE

GND_CHGR_SGND

PPVBAT_G3H_CHGR_OUT

=PP3V42_G3H_CHGR

CHGR_LOWCURRENT_REF

CHGR_SGATE

CHGR_BMON

TP_CHGR_TRKL

CHGR_LGATE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

CHGR_AMON

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CHGR_PHASE

=PPBUS_G3H

PPVBAT_G3H_CHGR_OUT

CHGR_CSO_R_P

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

=CHGR_ACOK

CHGR_VCOMP_R

CHGR_VNEG_R

CHGR_VDD

CHGR_VDD_R

CHGR_VDD

CHGR_VDD_L

CHGR_CSIN_XW7021

CHGR_CSIP_XW7020

CHGR_AMON

MIN_LINE_WIDTH=0.6 MM

PP18V5_S5_CHGR_SW_R

MIN_NECK_WIDTH=0.3 MM

CHGR_PIN6

CHGR_PIN26

GND_CHGR_SGND

CHGR_LOWCURRENT_GATE_R

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.6 MM

PPVDCIN_G3H_PRE2

=SMBUS_CHGR_SCL

=PP18V5_G3H_CHGR

CHGR_PIN6

CHGR_PIN26

CHGR_AMON

CHGR_BOOT

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

CHGR_UGATE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CHGR_DCIN

GND_CHGR_SGND

CHGR_CSO_R_N

CHGR_ACIN

CHGR_CSON

CHGR_CSOP

CHGR_VNEG

CHGR_VCOMP

CHGR_DCIN

CHGR_VDDP

=PP3V42_G3H_CHGR

PBUS Supply/Battery Charger

SYNC_MASTER=K24_MLB

SYNC_DATE=02/05/2009

0.1UF

16V

10% X5R

402

C7051

1

2

10% CERM

402

16V

0.01uF

C7050

1

2

OMIT

SM

PLACEMENT_NOT=PLACE XW7054 CLOSE TO U7000

XW7054

1 2

PLACEMENT_NOT=PLACE XW7052 CLOSE TO U7000

OMIT

SM

XW7052

1 2

20% 50V

CERM

0.001UF

402

C7028

1

2

CRITICAL

HAT1128R01

SOI

Q7001

5

6

7

8

4

1

2

3

SOI

HAT1128R01

CRITICAL

Q7000

5

6

7

8

4

1

2

3

SI7137DP

SO-8

CRITICAL

Q7050

5

4

1 2 3

1W MF

0.01

CRITICAL

0612-1

0.5%

R7008

1 2 3 4

PLACEMENT_NOTE=PLACE C7027 ACROSS PIN 5 OF Q7020 AND PINS 1/2/3 OF Q7021

CERM

0.001UF

402

20% 50V

C7027

1

2

1SS418

SOD-723-HF

D7010

1 2

CRITICAL

IHLP4040DZ-SM

4.7UH-9.5A

L7000

1 2

402

X5R

16V

10%

0.033UF

C7042

1

2

CRITICAL

QFN

ISL6258AHRTZ

U7000

3

14

1

6

26

9

16

15

25

27

28

17

18

2

5

21

22

23

11 10

29

13

24

7

19

20

12

8

4

MF-LF

402

5%

1/16W

0

R7047

1 2

402

1/16W

5%

MF-LF

2.2

R7031

1 2

16V

CASED2E-SM

POLY-TANT

CRITICAL

20%

33UF

C7008

1

2

10%

603-1

X5R

25V

1UF

C7011

1

2

CRITICAL

1206

7AMP

F7000

1 2

RJK0305DPB

CRITICAL

LFPAK-HF

Q7021

5

4

1 2 3

CRITICAL

RJK0305DPB

LFPAK-HF

Q7020

5

4

1 2 3

402

MF-LF

1/16W

1%

1.82K

R7061

1

2

5%

1M

402

1/16W

MF-LF

NOSTUFF

R7075

1

2

MF-LF

1/16W

5%

1M

402

R7074

1

2

402

1K

MF-LF

1/16W

5%

R7073

1

2

1/16W

402

1%

9.31K

MF-LF

R7011

1

2

MF-LF

30.1K

1/16W

1%

402

R7010

1

2

1UF

10% 16V

402

X5R

C7043

1 2

5%

62K

402

MF-LF

1/16W

R7001

1 2

MF-LF

1/16W

402

62K

5%

R7062

1

2

0.1UF

25V

10% X5R

402

C7062

1

2

402

X5R

10%

0.1UF

25V

C7061

1

2

402

MF-LF

5% 1/16W

10

R7023

1 2

10

402

MF-LF

1/16W

5%

R7021

1 2

10V

10%

402

0.047UF

CERM

C7024

1

2

OMIT

SM

PLACEMENT_NOT=PLACE XW7020 ON PAD OF R7020

XW7020

1 2

OMIT

SM

PLACEMENT_NOT=PLACE XW7021 ON PAD OF R7020

XW7021

1 2

SOT563

SSM6N15FEAPE

Q7070

3

5

4

SSM6N15FEAPE

SOT563

Q7070

6

2

1

0.1UF

10% 25V

402

X5R

C7060

1

2

SOT23-5

TL331

CRITICAL

U7060

1

3

4

5

2

1/16W

5%

MF-LF

402

100K

R7098

1

2

402

MF-LF

5%

1/16W

100K

R7099

1 2

MF-LF

1%

1/16W

57.6K

402

R7060

1

2

402

25V

10% X5R

0.1UF

C7063

1

2

0.001UF

X7R 402

10% 50V

C7026

1

2

SM

PLACEMENT_NOT=PLACE XW7000 CLOSE TO U7000

OMIT

XW7000

1 2

402

50V

10%

CERM

470PF

C7046

1

2

MF-LF

3.01K

1%

402

1/16W

R7046

1

2

402

10%

CERM

50V

0.001UF

C7045

1

2

402

56.2K

MF-LF

1%

1/16W

R7045

1

210%

402

16V CERM

0.01UF

C7044

1

2

25V X5R 402

10%

0.1UF

C7010

1

2

1UF

10V

10%

402-1

X5R

C7047

1

2

1UF

402-1

10V

10% X5R

C7040

1

2

22UF

CRITICAL

POLY-TANT

25V

20%

CASE-D2-SM

C7021

1

2

20%

22UF

CRITICAL

POLY-TANT

25V CASE-D2-SM

C7020

1

2

603-1

10% X5R

25V

1UF

C7022

1

2

10%

1UF

X5R

25V 603-1

C7023

1

2

402-1

X5R

1UF

10V

10%

C7041

1 2

10%

25V

402

X5R

0.1UF

C7025

1

2

402

MF-LF

5%

4.7

1/16W

R7040

1 2

0612-1

0.02

1W MF

CRITICAL

0.5%

R7020

1

2

39

56

55 7

56 8

56

56 8

41

56 41

8

56

76

37

56

56 41

56

39

8

56

56 41

56

76

56

56 8

IN

D

SG

D

SG

G

D

S

G

D

S

DRVH1

SKIPSEL

VBST1

GND

THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREF

VIN

TONSEL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- COPY THIS PAGE FROM K36 CSA.76

ROUTING NOTE:

Place XW7204 by Pin 2 of L7220.

EMI request

ROUTING NOTE:

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

EMI request

MAX CURRENT = 4A

VOUT = (2 * RC / RD) + 2

NC

VOUT = (2 * RA / RB) + 2

EMI request

PWM FREQ. = 375 KHZ

Place XW7205 by C7252.

ROUTING NOTE:

5V S3/3.3V S5 POWER SUPPLY

EMI request

ROUTING NOTE:

Place XW7202 by C7292.

EMI request

Place XW7201 between Pin 15 and Pin 25 of U7200.

EMI request

PWM FREQ. = 300 KHZ

Place XW7203 by Pin1 OF L7260.

EMI request

MAX CURRENT = 10A

72 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP5V_S3_REG

VOLTAGE=5V

3V3S5_ENTRIP

3V3S5_LL_SNUBBER

GND_5V3V3S5_SGND

P5V3V3_PGOOD

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

3V3S5_DRVL

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

3V3S5_LL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

3V3S5_DRVH

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

3V3S5V02VO2

=PP3V3_S5_REG

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V MIN_LINE_WIDTH=1.5 mm

3V3S5_VFB

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

5V_S3_LL

=PPVIN_S3_5VS3

DIDT=TRUE

5V_S3_VBST

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

5V_S3_VFB

5V_S3_VFB_XW7203

5VS3_3V3S5_VREF

5V3V3S5_REG3

GND_5V3V3S5_SGND

SMC_PM_G2_EN

3V3S5_VFB_R7270

=P5VS3_EN_L

=P3V3S5_EN_L

5V3V3_REG_EN

=PPVIN_S5_3V3S5

5V_S3_LL_SNUBBER

5V_S3_ENTRIP

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

5V_S3_DRVH

=PPVIN_S3_5VS3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

5V_S3_DRVL

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

3V3S5_VBST

5V_S3_VO1

5V/3.3V SUPPLY

402

CERM

10% 10V

0.22UF

C7271

1

2

10UF

6.3V 603

X5R

20%

C7270

1

2

10%

1UF

X5R

25V 603-1

C7272

1

2

402

MF-LF

1%

1/16W

75K

R7272

1

2

MF-LF 402

1/16W

75K

1%

R7271

1

2

CRITICAL

TPS51125

QFN

5V3V3S5_REG5

U7200

21 10

19 12

13

1 6

15

20 11

23

14

25

4

22

9

18

2 5

16

24

7

3

8

17

CRITICAL

SIS426DN

PWRPK-12128

Q7261

CRITICAL

PWRPK-12128

SIS426DN

Q7260

6.3V

20%

10UF

603

X5R

C7290

1

2

CASE-B2-SM

150UF-.025-OHM

CRITICAL

TANT

20%

6.3V

C7291

1

2

CASE-B2-SM

CRITICAL

150UF-.025-OHM

TANT

6.3V

20%

C7292

1

2

X5R

10% 25V

603-1

1UF

C7281

1

2

1/16W 402

10K

1% MF-LF

R7268

1 2

MF-LF

1% 402

1/16W

15.0K

R7267

1 2

0.1UF

10% 402

16V X5R

C7260

12

CASE-B2-SM

150UF-.025-OHM

TANT

6.3V

20%

CRITICAL

C7252

1

2

X5R

10% 25V

1UF

603-1

C7241

1

2

1% 402

MF-LF

1/16W

10K

R7269

1 2

402

MF-LF

1%

6.49K

1/16W

R7270

1 2

10UF

6.3V

20% 603

X5R

C7250

1

2

39UF-0.027OHM

POLY

20% 16V

CRITICAL

B1A-SM

C7282

1

2

100K

1/16W MF-LF

5%

402

R7273

1 2

CRITICAL

PCMC063T-SM

4.7UH-10A

L7220

1 2

SIZ700DT

POWERPAK-6X3.7

CRITICAL

Q7220

1

6

4 5

2 3 7

8

CRITICAL

PCMB104E4R7-SM

4.7UH-13A-15MOHM

L7260

1 2

CRITICAL

POLY

16V

20%

39UF-0.027OHM

B1A-SM

C7240

1

2

ELEC C6-SM

16V

CRITICAL

20%

68UF

C7280

1

2

NO STUFF

402

1/16W

5%

MF-LF

2.2

R7294

1

2

NO STUFF

402

CERM

50V

5%

100PF

C7294

1

2

MF-LF 402

NO STUFF

2.2

1/16W

5%

R7295

1

2

NO STUFF

100PF

402

5% 50V

CERM

C7295

1

2

402

50V

0.001UF

CERM

20%

C7233

1

2

402

50V CERM

20%

0.001UF

C7232

1

2

50V

0.001UF

20% 402

CERM

C7231

1

2

10% X5R

402

0.1UF

16V

C7220

12

402

50V CERM

20%

0.001UF

PLACEMENT_NOTE=PLACE C7230 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7220

C7230

1

2

PLACEMENT_NOT=PLACE XW7204 BY PIN 2 OF L7220

OMIT

SM

XW7204

12

PLACEMENT_NOT=PLACE XW7205 BY C7252

OMIT

SM

XW7205

12

PLACEMENT_NOT=PLACE XW7203 BY PIN 1 OF L7260

OMIT

SM

XW7203

12

PLACEMENT_NOT=PLACE XW7202 BY C7292

SM

OMIT

XW7202

12

SOT563

SSM6N15FEAPE

Q7221

3

5

4

SOT563

SSM6N15FEAPE

Q7221

6

2

1

63

PLACEMENT_NOT=PLACE XW7201 BETWEEN PIN 15 AND PIN 25 OF U7200

OMIT

SM

XW7201

1 2

10UF

X5R

20% 603

6.3V

C7273

1

2

8

57

63

8

57 8

57

63 36 7

8

57 8

VDDQSET

S3

COMP

VTT

THRM_PAD

DRVH

LL

PGNDCS_GND

CS

PGOOD

NC1

S5

NC0

GND

VTTGND

MODE

DRVL

VTTREF VLDOIN VBST V5IN

VDDQSNS

VTTSNSV5FILT

SYM (1 OF 2)

OUT

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Place XW7301 by L7320.

ROUTING NOTE:

VOUT = 0.75V * (1 + RA / RB)

1.5V/0.75V(DDR3) POWER SUPPLY

ROUTING NOTE:

Place XW7303 by C7308.

MAX CURRENT = 13A

PWM FREQ. = 400 KHZ

ROUTING NOTE:

of U7300.

Place XW7300 between

ROUTING NOTE:

Pin 3 and Pin 25

ROUTING NOTE:

PUT 6 VIAS UNDER THE THERMAL PAD

CONNECT CS_GND TO

ROUTING NOTE:

STATE

S0

PM_SLP_S4_L

HIGH HIGH LOW

PP1V5_S3

1.5V

0.75V

PP0V75_S0

1.5V

HIGH

0.0V

S3

LOW

0.0V

0.0VS5/G3HOT

Q7321 PIN1,2.3

<RA>

Place XW7302 by Q7321.

PM_SLP_S3_L

NC

EMI request

NC

USING KEVIN CONNECTION.

<RB>

73 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

1V5S3_VBST_RC

DIDT=TRUE

1V5S3_LL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V5S3_V5FILT_XW

ISNS_1V5_S3_N

1V5S3_LL_SNUBBER

MIN_NECK_WIDTH=0.25 mm

1V5S3_DRVL

MIN_LINE_WIDTH=1 mm

DIDT=TRUE

PP1V5_S3_REG_R

GND_1V5S3_CSGND

=PP3V3_S3_PDCISENS

=DDRVTT_EN

DIDT=TRUE

1V5S3_VBST

1V5S3_V5FILT

=PP5V_S3_1V5S30V75S0

=DDRREG_EN

1V5S3_CS

GND_1V5S3_SGND

=PPVTT_S3_DDR_BUF

DDRREG_PGOOD

=PP0V75_S0_REG

1V5S3_DRVH

DIDT=TRUE

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm

1V5S3_VDDQSET

1V5S3_VTTSNS

=PP1V5_S3_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=1.5V

ISNS_1V5_S3_P

1V5S3_VDDQSNS

=PPVIN_S5_1V5S30V75S0

1.5V/0.75V DDR3 SUPPLY

SM

PLACEMENT_NOT=PLACE XW7304 BY C7300

OMIT

XW7304

1 2

CRITICAL

CSD58858Q3

3.3X3.3-QFN

Q7321

5

4

1 2 3

CSD58858Q3

3.3X3.3-QFN

CRITICAL

Q7320

5

4

1 2 3

20% 50V CERM 402

PLACE CLOSE TO L7320

0.001UF

C7344

1

2

0612

MF-1

1W

0.001

1%

PLACE NEXT TO L7320

CRITICAL

R7350

12 34

16V

20% POLY

CRITICAL

B1A-SM

39UF-0.027OHM

C7345

1

2

76 47

402

1/16W

NO STUFF

MF-LF

2.2

5%

R7390

1

2

402

50V

CERM

5%

100PF

NO STUFF

C7390

1

2

SM

PLACEMENT_NOT=PLACE XW7303 BY C7308

OMIT

XW7303

1 2

PLACEMENT_NOT=PLACE XW7302 BY Q7321

SM

OMIT

XW7302

1 2

SM

OMIT

PLACEMENT_NOTE=PLACE XW7301 BY L7320

XW7301

1 2

50V

0.001UF

20% 402

CERM

PLACEMENT_NOTE=PLACE C7333 ACROSS Q7320 PWR AND Q7321 GND

C7333

1

2

603-1

1UF

25V X5R

10%

C7332

1

2

20% 16V POLY

CRITICAL

B1A-SM

39UF-0.027OHM

C7331

1

2

100K

MF-LF

402

1/16W

5%

R7399

1 2

CRITICAL

20%

330UF

TANT

2.5V CASE-B2-SM

C7343

10V X5R

1UF

10% 402-1

C7300

1 2

X5R-CERM-1 603

22UF

20%

6.3V

C7308

1

2

22UF

X5R-CERM-1

6.3V 603

20%

C7307

1

2

0.033UF

16V X5R

10% 402

C7340

1 2

6.3V

20% 603

X5R

10UF

C7301

1

2

CERM

50V

100PF

5% 402

NO STUFF

C7303

1 2

1/16W 402

0.1% MF

20K

R7322

1 2

20.0K

MF-LF

1/16W

402

1%

R7321

PLACEMENT_NOT=PLACE XW7300 BETWEEN PIN 3 AND PIN 25 OF U7300

SM

OMIT

XW7300

1 2

5%

4.7

MF-LF

1/16W 402

R7307

1 2

402

1/16W MF-LF

1%

10.7K

R7310

1

2

603

6.3V

10UF

20% X5R

C7302

1

2

6.3V X5R 603

10UF

20%

C7341

1

2

2.5V TANT

20%

330UF

CRITICAL

CASE-B2-SM

C7342

402

X5R

10%

16V

0.1uF

C7309

1

2

1/16W

5%

0

402

MF-LF

R7300

1 2

CRITICAL

SM-IHLP-1

1.0UH-13A-5.6M-OHM

L7320

1 2

CRITICAL

QFN

TPS51116

U7300

6

16

17

21

19

3

20

4 7

12

18

1310

11

25

141522

9

8

23

24

1

5

2

8

64 25

63

26 8

63

8

IN

OUT

IN

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

S

G

D

S

G

D

G

S

D

G

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IMVP6_VO)

(IMVP6_PHASE2)

PIMA104E-R36MN0R755 DCR=0.75MOHM

(IMVP6_VW)

(IMVP6_PHASE1)

PIMA104E-R36MN0R755 DCR=0.75MOHM

PSI*

(IMVP6_ISEN1)

LOAD LINE SLOPE = -2.1 MV/A

PWM FREQ. = 300 KHZ

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

2-PHASE CCM

(IMVP6_VSUM)

OPERATION MODE

1-PHASE CCM

(NC)

(GND)

(IMVP6_VO)

(GND)

MIN_LINE_WIDTH

DPRSLPVR

MIN_NECK_WIDTH

(IMVP6_ISEN2)

1-PHASE DCM

0

1

0

1

0

1

MIN_NECK_WIDTHMIN_LINE_WIDTH

ERT-J1VR103J

(IMVP6_FB)

(IMVP6_COMP)

MIN_LINE_WIDTH MIN_NECK_WIDTH

0

1-PHASE DCM

0

MAX CURRENT = 44A

FROM SMC

DPRSTP*

0

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

IMVP6 CPU VCORE REGULATOR

74 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

CPU_VID<4>

CPU_VID<0>

IMVP_DPRSLPVR

PM_DPRSLPVR

=PP5V_S0_CPU_IMVP

IMVP6_BOOT1

DIDT=TRUE

CPU_PSI_L

DIDT=TRUE

IMVP6_BOOT1_RC

=PPVIN_S5_CPU_IMVP

IMVP6_SOFT

CPU_VCCSENSE_N

IMVP6_NTC

=PPVIN_S5_CPU_IMVP

IMVP6_ISEN2

0.25 MM 0.25 MM

IMVP6_LGATE2

0.25 MM 0.25 MM

IMVP_VR_ON

IMVP6_VO

0.25 MM 0.20 MM

GND_IMVP6_SGND

0.50 MM 0.20 MM

MIN_LINE_WIDTH=0.25 MM VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

PP5V_S0_IMVP6_VDD

0.20 MM

IMVP6_DFB

0.25 MM

IMVP6_DROOP

0.25 MM 0.20 MM

0.25 MM0.25 MM

IMVP6_VSEN

IMVP6_RTN

0.25 MM 0.25 MM

IMVP6_VW

0.25 MM0.25 MM

CPU_VID<1>

0.25 MM

1.5 MM

IMVP6_PHASE1

IMVP6_COMP_RC

CPU_VID<5>

IMVP6_UGATE2

0.25 MM0.25 MM

0.20 MM0.25 MM

IMVP6_OCSET

0.25 MM

IMVP6_FB2

0.20 MM

0.20 MM0.25 MM

IMVP6_COMP

0.25 MM

1.5 MM

IMVP6_UGATE1

0.25 MM 0.25 MM

IMVP6_BOOT1

0.20 MM0.25 MM

IMVP6_RBIAS

0.20 MM0.25 MM

IMVP6_VDIFF

0.20 MM0.25 MM

IMVP6_FB

IMVP6_VSUM

0.20 MM0.25 MM

CPU_DPRSTP_L

0.25 MM0.25 MM

IMVP6_PHASE2

IMVP6_VDIFF_RC

0.25 MM 0.25 MM

IMVP6_ISEN1

=PP3V3_S0_IMVP

1.5 MM

0.25 MM

IMVP6_LGATE1

0.20 MM0.25 MM

IMVP6_SOFT

0.25 MM0.25 MM

IMVP6_BOOT2

IMVP6_BOOT2_RC

DIDT=TRUE

CPU_VID<2>

IMVP6_IMON

DIDT=TRUE

IMVP6_BOOT2

IMVP6_VDIFF

CPU_VID<6>

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

IMVP6_PHASE1

IMVP6_DFB

CPU_VCCSENSE_P

IMVP6_RBIAS

IMVP6_FB2

IMVP6_VR_TT

VR_PWRGOOD_DELAY

IMVP6_DROOP

IMVP6_PHASE2_XW

PPVCORE_S0_CPU_XW_2

=PPVIN_S5_CPU_IMVP

IMVP6_PHASE1_XW

DIDT=TRUE

IMVP6_UGATE1

IMVP6_LGATE1

DIDT=TRUE

IMVP6_ISEN1

PPVCORE_S0_CPU_XW

=PPVCORE_S0_CPU_REG

GND_IMVP6_SGND

CPU_VID<3>

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP3V3_S0_IMVP6_3V3

DIDT=TRUE

IMVP6_LGATE2

DIDT=TRUE

IMVP6_PHASE2

IMVP6_UGATE2

DIDT=TRUE

IMVP6_ISEN2

IMVP6_OCSET

IMVP6_FB IMVP6_COMP IMVP6_VW

IMVP6_RTN

VOLTAGE=0V

GND_IMVP6_SGND

IMVP6_VO_R

IMVP6_VSUM

IMVP6_VO

IMVP6_VSEN

SYNC_DATE=03/03/2009

SYNC_MASTER=K24_MLB

IMVP6 CPU VCore Regulator

CERM

20%

0.001UF

50V

402

C7433

1 2

0.001UF

50V

20%

CERM

402

C7431

1 2

OMIT

SM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7401

XW7404

1

2

OMIT

PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7401

SM

XW7403

1

2

OMIT

SM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7400

XW7402

1

2

OMIT

SM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400

XW7401

1

2

CRITICAL

PIMA104E-SM

0.36UH-20%-40A-0.00075OHM

L7401

1 2

PIMA104E-SM

0.36UH-20%-40A-0.00075OHM

CRITICAL

L7400

1 2

CRITICAL

DIRECTFET-MX

IRF6795

Q7403

1 2 6 7

5

3 4

DIRECTFET-MX

CRITICAL

IRF6795

Q7401

1 2 6 7

5

3 4

S1

IRF6710

CRITICAL

Q7402

1 2 5 64

3

CRITICAL

S1

IRF6710

Q7400

1 2 5 64

3

POLY-TANT

33UF

20% 16V

CRITICAL

CASED2E-SM

C7401

1

2

50V

0.001UF

20%

402

CERM

PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401

C7423

1

2

CERM

20%

0.001UF

50V 402

PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403

C7422

1

2

PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401

0.001UF

402

20% 50V

CERM

C7419

1

2

50V

20%

402

CERM

0.001UF

C7420

1

2

2.0K

402

5% 1/16W MF-LF

R7447

1

2

ISL9504BCRZ

CRITICAL

QFN

U7400

48

36

26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

1UF

10%

603-1

X5R

25V

C7411

1

2

10% 25V

1UF

X5R 603-1

C7418

1

2

CRITICAL

CASED2E-SM

POLY-TANT

33UF

16V

20%

C7408

1

2

CASED2E-SM

POLY-TANT

20% 16V

33UF

CRITICAL

C7417

1

2

33UF

16V

CRITICAL

20% POLY-TANT

CASED2E-SM

C7409

1

2

MF-LF 402

5% 1/16W

0

R7424

1 2

1/16W MF-LF 402

0

5%

R7425

1 2

499

1% 1/16W

MF-LF 402

R7445

1

2

CRITICAL

0603-LF

10KOHM-5%

R7431

1

2

402

MF-LF

1/16W

5%

1

R7407

1 2

MF-LF

1

1/16W

402

5%

R7404

1 2

6.3V

402

CERM-X5R

10%

0.22uF

C7403

1 2

6.3V CERM-X5R 402

10%

0.22uF

C7421

1 2

1/16W MF-LF

1%

402

3.92K

R7430

1

2

CERM 402

50V

NO STUFF

10%

0.001UF

C7416

1

2

402

0.001UF

10% 50V CERM

C7406

1

2

147K

1% 1/16W MF-LF 402

R7408

1 2

0.015uF

16V

10%

402

X7R

C7405

1 2

X5R

6.3V

20%

603

10UF

C7435

1

2

CERM-X5R

NOSTUFF

10%

10.0V

0.12UF

402

C7434

1

2

402

0

MF-LF

5% 1/16W

R7423

1

2

MF-LF

1/16W

402

5%

0

R7422

1

2

0.001UF

20%

402

50V CERM

C7432

1 2

CERM-X5R 402

0.47UF

10%

6.3V

C7428

1

2

180pF

5%

402

CERM

50V

C7429

1

2

1%

1K

1/16W

402

MF-LF

R7418

1

2

402

1/16W

1%

5.36K

MF-LF

R7417

1 2

6.81K

MF-LF

1/16W

1%

402

R7410

1

2

50V CERM

0.001UF

402

10%

C7407

1

2

220PF

5% 25V

402

CERM

C7413

1

2

97.6K

MF-LF

1/16W

1%

402

R7414

1

2

CERM

50V

470PF

402

10%

C7414

1

2

255

MF-LF

1/16W

1%

402

R7411

1

2

MF-LF

1K

1/16W

1%

402

R7409

1

2

1K

1% 1/16W MF-LF 402

R7413

1 2

16V

10%

402

X5R

0.1uF

C7430

1

2

5%

MF-LF

1/16W

10

402

R7421

1 2

0.01UF

16V

10% CERM

402

C7496

1

2

402

10%

1UF

CERM

6.3V

C7426

1

2

MF-LF

1/16W

10

402

5%

R7412

1 2

MF-LF

1/16W

402

10

5%

R7420

1 2

16V

402

X5R

10%

0.1UF

C7427

1

2

MF-LF 402

1% 1/16W

3.65K

R7443

1

2

402

10%

6.3V CERM-X5R

0.22uF

C7404

1 2

MF-LF

1/16W

402

10K

1%

R7405

1 2

402

10.5K

1% 1/16W MF-LF

R7415

1

2

1/16W

1%

402

13.7K

MF-LF

R7416

1

2

16V X5R

402

10%

0.1UF

C7415

1

2

3.65K

MF-LF 402

1/16W

1%

R7401

1

2

10K

MF-LF 402

1/16W

1%

R7400

1 2

OMIT

SM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400

XW7400

1

2

70 11

70

70 21

8

59

10

59 8

59

70 11

9

59 8

59

36

59

70 11

59

70 11

59

59 59

59

70 14 10

59

8

59

70 11

41

59

70 11

59

70 11

59

9

25

59

59 8

59

8

59

70 11

59

IN

OUT

OCSET

ICOMP

RBIAS

LGATE

THRM_PAD

FDE

IMON

PVCC

PHASE

UGATE

BOOT

VDD

VSS

VIN

VO

VSEN

VDIFF

FB

COMP

VW

SOFT

PGND

ISN

ISP

RTN

PGOOD

AF_EN

VR_ON

OFFSET1

OFFSET0

VID2

VID1

VID0

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(MCPCORES0_LGATE)

(MCPCORES0_PHASE)

(MCPCORES0_UGATE)

(MCPCORES0_ICOMP)

(Q7560 Limit)

110 +0.75V

(MCPCORES0_VW)

(MCPCORES0_ISN)

(MCPCORES0_VDIFF)

(MCPCORES0_FB)

(MCPCORES0_COMP)

(MCPCORES0_RTN)

000 +1.05V

001 +1.00V

010 +0.95V

011 +0.90V

100 +0.85V

101 +0.80V

111 +0.70V

VID<2:0> MCP TARGET

MAX CURRENT: 13A

(MCPCORES0_VSEN)

OCP=14.5A

(MCPCORES0_VO)

f = 300 kHz

75 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MCPCORES0_VO

=PPMCPCORE_S0_REG

VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM

GND_MCPCORES0_AGND

MCPCORES0_VSEN

MCPCORES0_OCSET

MCPCORES0_ICOMP

MCPCORES0_ISN

MCPCORES0_ISP

MCP_VID1_R

5V_S0_MCPREG_VIN

VOLTAGE=5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM

MCPCORES0_VDIFF

MCPCORES0_IMON

MCPCORES0_FB

=PPMCPCORE_S0_REG

MCPCORES0_IMON_R

MCPCORES0_PGOOD

=MCPCORES0_EN

MCPCORES0_RSEN_P

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

MCP_VID<0>

MCPCORES0_RSEN_N

MCP_VID<1>

=PPMCPCORE_S0_REG

MCPCORES0_COMP

MCPCORES0_RBIAS

MCPCORES0_SOFT

MCPCORES0_FDE

MCPCORES0_OS1

MCPCORES0_VW

MCP_VID<2>

MCP_VID2_R

MCPCORES0_OS0

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V

PPMCPCORE_S0_R

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_ISP_R

=PP5V_S0_MCPREG

MCPCORES0_BOOT_R

0.2 MM

0.25 MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MCPCORES0_LGATE

MIN_LINE_WIDTH=0.5 MM

MCPCORE_SNUBBER

MCPCORES0_UGATE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

DIDT=TRUE

MCPCORES0_BOOT

0.25 MM

0.2 MM

MCP_VID0_R

MCPCORES0_PHASE

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

SWITCHNODE

=PPVIN_S0_MCPCORE

MCPCORES0_RTN

MCP CORE REGULATOR

SYNC_DATE=02/15/2009

SYNC_MASTER=K24_MLB

PWRPK-12128

CRITICAL

SIS426DN

Q7565

5

4

1 2 3

SIS426DN

CRITICAL

PWRPK-12128

Q7560

5

4

1 2 3

603

16V X5R

2.2UF

10%

C7590

1

2

68UF

20%

CRITICAL

C6-SM

ELEC

16V

C7571

1

2

X7R

10% 50V

402

0.001UF

C7569

1

2

C6-SM

CRITICAL

16V ELEC

68UF

20%

C7560

1

2

PCMB065T-SM

CRITICAL

0.68UH-16A

L7560

1 2

1W

1%

0.001

0612

MF

R7525

12 34

0

5%

402

MF-LF

1/16W

R7593

1 2

402

47PF

CERM

5% 50V

C7575

1

2

402

CERM

5%

50V

47PF

C7573

1

2

402

MF-LF

1/16W

100

1%

R7500

1 2

PLACEMENT_NOTE=PLACE C7563 ACROSS PIN 5 OF Q7560 AND PINS 1/2/3 OF Q7565

X7R 402

50V

10%

0.001UF

C7563

1

2

10% 25V

603-1

X5R

1UF

C7561

1

2

603

10UF

4V X5R

20%

C7567

1

2

CRITICAL

CASE-B4-SM

270UF

20% 2V TANT

C7565

1

2

CASE-B4-SM

270UF

20% 2V TANT

CRITICAL

C7568

1

2

10UF

4V

20%

603

X5R

C7566

1

2

10% 402

0.001UF

50V X7R

NO STUFF

C7589

1

2

1

5%

603

MF-LF

1/10W

NO STUFF

R7589

1

2

1/16W

1%

402

MF-LF

6.98K

R7576

1

2

10% 50V

402

X7R

0.001UF

C7579

1

2

50V

10%

402

CERM

560PF

C7582

1 2

1%

100

1/16W 402

MF-LF

R7571

1

2

50V

10%

402

CERM

560PF

C7581

1 2

50V

5%

402-1

CERM

68PF

C7580

1 2

MF-LF

402

1/16W

1%

133K

R7577

1 2

1/16W

1%

402

MF-LF

2.21K

R7579

1 2

MF-LF

1/16W

1%

402

100

R7578

1 2

10%

402

X5R

16V

1UF

C7562

1

2

603

1/10W

5%

MF-LF

2.2

R7560

1 2

1UF

10% 16V

402

X5R

C7550

1

2

0.22UF

603

5%

10V

CERM-X7R

C7564

1 2

MF-LF

1/10W

5%

603

1

R7565

1 2

MF-LF

1%

1/16W

11.3K

402

R7569

1 2

402

1/16W MF-LF

10K

1%

R7573

1

2

402

1% 1/16W

47.0K

MF-LF

R7575

1

2

SM

PLACEMENT_NOTE=PLACE XW7561 CLOSE TO PIN 15 OF U7500

OMIT

XW7561

1 2

QFN

ISL6263D

U7500

30

17

5

6

32

10

28

11

13

21

3

23 24

20

31 19

22

1

9

2

33

18

16

7

25 26 27

14

12

29

8

15

4

1/16W

5%

402

MF-LF

1K

R7561

1

2

MF-LF

0

5%

1/16W

402

R7590

1 2

63

1/16W

1% MF-LF

150K

402

R7572

1

2

16V

0.022UF

10%

CERM-X5R

402

C7576

1

2

5%

402

MF-LF

0

1/16W

R7591

1 2

1%

402

NOSTUFF

20.0K

MF-LF

1/16W

PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE

R7581

1

2

NOSTUFF

402

MF-LF

20.0K

1% 1/16W

PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE

R7580

1

2

1/16W

402

5%

MF-LF

0

R7592

1 2

1% MF-LF

20.0K

402

1/16W

PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE

R7583

1

2

1/16W

1% MF-LF

20.0K

402

PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE

R7582

1

2

MF-LF 402

1/16W

1%

100

R7563

1

2

0.001UF

402

X7R

10% 50V

C7570

1

2

20

1% 1/16W MF-LF

402

R7566

1 2

20

1/16W MF-LF

1%

402

R7568

1 2

21

SM

OMIT

PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP

XW7562

1 2

SM

OMIT

PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP

XW7563

1 2

60 8

41

60 8

8

VBST

TON

LL

DRVH

DRVL

V5FILT

V5DRV

PGND

GND

EN_PSV

VOUT

TRIP

VFB

THRM_PAD

PGOOD

SYM 2

IN

OUT

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ROUTING NOTE:

CPUVTT POWER SUPPLY

(=PPCPUVTT_S0_REG)

(GND)

(CPUVTTS0_VFB)

Place XW7600 between Pin 7 and Pin 15 of U7600.

F = 320 KHZ

VOUT = 1.052V

7.2A MAX OUTPUT

Place XW7601 by C7660.

ROUTING NOTE:

Vout = 0.75V * (1 + Ra / Rb)

<Ra>

<Rb>

76 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

CPUVTTS0_VOUT

CPUVTTS0_VFB

GND_CPUVTTS0_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

SWITCH_NODE=TRUE

CPUVTTS0_LL

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

CPUVTTS0_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

CPUVTTS0_VBST

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_TON

=PP5V_S0_CPUVTTS0

CPUVTTS0_VSNS

CPUVTTS0_DRVL

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

=PPVIN_S0_CPUVTTS0

=PPCPUVTT_S0_REG

CPUVTTS0_PGOOD

=CPUVTTS0_EN

CPUVTTS0_TRIP

PP5V_S0_CPUVTTS0_V5FILT

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

CPU VTT(1.05V) SUPPLY

SYNC_MASTER=K24_MLB

SYNC_DATE=02/04/2009

CRITICAL

CSD58858Q3

3.3X3.3-QFN

Q7621

5

4

1 2 3

CSD58858Q3

CRITICAL

3.3X3.3-QFN

Q7620

5

4

1 2 3

2.5V TANT

CASE-B2-SM

CRITICAL

20%

330UF

C7660

1

2

OMIT

PLACEMENT_NOT=PLACE XW7601 BY C7660

SM

XW7601

1

2

CRITICAL

PCMB065T-SM

2.2UH-8.0A

L7620

1 2

0.001UF

402

20% 50V

CERM

C7661

1

2

20%

0.001UF

50V 402

CERM

PLACEMENT_NOTE=PLACE C7696 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7620

C7696

1

2

301

1%

MF-LF

402

1/16W

R7601

1 2

6.04K

1%

402

MF-LF

1/16W

R7604

1

2

63

10%

402-1

10V X5R

1UF

C7601

1

2

OMIT

PLACEMENT_NOT=PLACE XW7600 BETWEEN PIN 7 AND PIN 15 OF U7600

SM

XW7600

1 2

CRITICAL

QFN

TPS51117RGY_QFN14

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

10%

4.7UF

X5R-CERM 603

6.3V

C7604

1

2

0.1UF

10%

X7R

603-1

50V

C7603

1

2

20% 16V

CRITICAL

POLY-TANT

CASED2E-SM

33UF

C7630

1

2

X5R

1UF

25V

10%

603-1

C7695

1

2

200K

1/16W

402

1%

MF-LF

R7603

1

2

1%

402

1/16W MF-LF

20.0K

R7671

1

2

1%

402

MF-LF

1/16W

8.06K

R7670

1

2

100PF

5%

50V

CERM

402

NO STUFF

C7670

1

2

SM

OMIT

PLACEMENT_NOTE=Place XW7665 next to L7620

XW7665

1

2

X5R

10UF

6.3V

603

20%

C7665

1

2

8

VI

SW

EN

FB

GND

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

SS

IN0 IN1

THRML_PAD

EN FB

BIAS

OUT0 OUT1

GND

PG

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MCP 1.05V S5 (AUXC) SUPPLY

VOUT = 0.8V * (1 + RA / RB)

<Rb>

1.05V S0 PLL LDO

Vout = 1.05V MAX CURRENT = 0.5A

VOUT = 0.8V * (1 + RA / RB)

1.8V S0 SWITCHER

<Ra>

MAX CURRENT = 200MA

<Ra>

FREQ = 1.6MHZ

Vout = 1.05V

MAX CURRENT = 0.8A

<Rb>

77 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

DIDT=TRUE

PP1V05_S0_MCP_PLL_UF_LDO

=PP1V5_S0_MCP_PLL_VLDO

=PP3V3_S0_MCP_PLL_VLDO

=P1V8S0_EN

P1V8S0_SW

DIDT=TRUE

P1V05S0_LDO_SS

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PLL_UF_R

P1V05S0_LDO_PGOOD

P1V05S0_LDO_FB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_VLDO_BIAS

P1V05S0_PGOOD

=PP1V8_S0_REG

=PP3V3_S0_P1V8S0

DIDT=TRUE

1V05S5_FB

=PP1V05_S5_REG

PP3V3_S5_P1V05S5_R_SKIP

P1V05_S5_PGOOD

=P1V05_S5_EN

=PP3V3_S5_P1V05S5

MISC POWER SUPPLIES

SYNC_MASTER=K24_MLB

SYNC_DATE=03/24/2009

402

0

5% 1/16W MF-LF

R7783

1

2

NOSTUFF

402

0

5% 1/16W MF-LF

R7782

1

2

5%

402

MF-LF

1/16W

0

LDO_YES

R7748

1 2

4.42K

LDO_YES

MF-LF

1/16W

402

1%

R7747

1 2

LDO_YES

MF-LF

1/16W

402

1%

1.37K

R7746

1 2

NOSTUFF

402

CERM

50V

10%

0.0022UF

C7743

1

2

CRITICAL

SON

LDO_YES

TPS74701

U7740

4

5 8

6

1 2

9 10

37

11

402

6.3V

10%

1UF

CERM

LDO_YES

C7741

1

2

MF-LF

5%

LDO_YES

100

1/16W

402

R7743

1 2

LDO_YES

CERM

402

6.3V

10%

1UF

C7740

1

2

LDO_YES

X5R

4V 402

20%

4.7UF

C7742

1

2

LDO_NO

402

1/16W

5%

0

MF-LF

R7745

1 2

0

1/16W

LDO_YES

MF-LF

402

5%

R7744

1 2

CRITICAL

DFN

ISL8009B

U7750

2

7

8

3

54

9

6

1

63

1V05S5_SW

IHLP1616BZ-SM

2.2UH-3.25A

CRITICAL

L7770

1 2

CERM

402

50V

5%

47PF

C7776

1

2

1% 1/16W

80.6K

402

MF-LF

R7781

1

2

25.5K

1/16W

1% MF-LF

402

R7780

1

2

CERM 805

22UF

CRITICAL

20%

6.3V

C7750

1

2

0805

X5R

47UF

CRITICAL

20%

6.3V

C7771

1

2

CRITICAL

TPS62202

SOT23-5

U7760

3

4

2

5

1

603

6.3V X5R

20%

10uF

C7760

1

2

6.3V X5R

10uF

603

20%

C7762

1

2

CRITICAL

PCAA031B-SM

10UH-0.55A-330MOHM

L7760

1 2

8

63

23 8

8

63

8

63

8

OUT

D

G S

D

G S

OUT

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

VDD

MR*

RST*

V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Unused PGOOD signal

(PM_S4_STATE_L)

V4MON THRESHOLD IS 0.6V

V3MON THRESHOLD IS 0.6V

V2MON THRESHOLD IS 2.866V

NC

S3 ENABLE

Power Control Signals

PM_SLP_S4_L

(PM_SLP_S3_L)

3.3V_S0, 1.8V_S0 ENABLE

MCPDDR, CPUVTT,MCPCORES0 ENABLE

1.5V S0 AND 1.05V S0 ENABLE

SMC_PM_G2_ENABLE

1

0

PM_SLP_S3_L

1

11

Run (S0)

Sleep (S3)

Soft-Off (S5)

0

01

00

State

Battery Off (G3Hot)

353S2310

(S0PGOOD_PWROK)

OTHER S0 RAILS PGOOD

TPS3808 MR* HAS INTERNAL PULLUP

VOLTAGE MONITOR

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

3.3V 1.05V S5 ENABLE

78 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PM_G2_P3V3S5_EN_L

MAKE_BASE=TRUE

=PP1V05_S0_VMON

=PP1V5_S0_VMON

P1V05_S5_PGOOD

RSMRST_PWRGD

=PP3V42_G3H_PWRCTL

TP_U7840_MR_L

P1V05S0_LDO_PGOOD

ALL_SYS_PWRGD

=PP3V3_S5_PWRCTL

P5V3V3_PGOOD

MCPCORES0_PGOOD

=PP3V3_S0_PWRCTL

PM_G2_P1V05S5_EN

MAKE_BASE=TRUE

PP3V3_VMON_VDD

=P5VS3_EN_L

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

P3V3S0_EN

=P3V3S0_EN

MAKE_BASE=TRUE

MCPCORES0_EN

TP_DDRREG_PGOOD

=P1V05_S5_EN

=DDRREG_EN

=USB_PWR_EN

=PP3V42_G3H_PWRCTL

=MCPCORES0_EN

=MCPDDR_EN

=CPUVTTS0_EN

=P1V8S0_EN

=PBUSVSENS_EN

=P5VS0_EN

MCPDDR_EN

MAKE_BASE=TRUE

CPUVTTS0_EN

MAKE_BASE=TRUE

PM_SLP_S3_L_BUF

PM_SLP_S3_L

SMC_PM_G2_EN

=P3V3S5_EN_L

CT

=PP3V3_S0_VMON

PM_SLP_S3_L_INVERT

MAKE_BASE=TRUE

=PP5V_S0_VMON

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

S0PGOOD_PWROK

CPUVTTS0_PGOOD

PM_SLP_S4_L

MAKE_BASE=TRUE

=P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_PGOOD

POWER SEQUENCING

64

61

60

MF-LF

5%

402

1/16W

10K

R7820

1

2

60

1/16W

5%

MF-LF

100K

402

R7879

1

2

67 36 32 21 7

61

6.3V

402

10%

0.47UF

CERM-X5R

C7880

1

2

10%

CERM-X5R

0.47UF

6.3V

402

C7881

1

2

402

10%

CERM-X5R

0.47UF

NO STUFF

6.3V

C7882

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C7883

1

2

402

5%

1/16W MF-LF

22K

R7880

1

2

402

MF-LF

5%

1/16W

33K

R7881

1

2

402

0

MF-LF

1/16W

5%

R7882

1

2

402

MF-LF

1/16W

5%

10K

R7883

1

2

62

1/16W

100K

5%

402

MF-LF

R7810

1

2

40

58

6.3V

10%

0.47UF

402

CERM-X5R

C7810

1 2

402

5.1K

5%

MF-LF

1/16W

R7811

1 2

37 36 21 7

57 36 7

5%

MF-LF

402

1/16W

100K

R7800

1

2

64

MF-LF

1/16W

5%

402

0

R7895

1 2

62

402

0

MF-LF

5%

1/16W

R7893

1 2

5%

0

1/16W MF-LF

402

R7894

1 2

402

5%

MF-LF

1/16W

0

R7891

1 2

402

1/16W MF-LF

0

5%

R7890

1 2

5%

0

402

MF-LF

1/16W

R7892

1 2

402

1%

20.0K

MF-LF

1/16W

R7871

1

2

402

MF-LF

1%

1/16W

10K

R7870

1

2

64

0.47UF

10%

CERM-X5R

402

6.3V

C7884

1

2

402

MF-LF

1/16W

5%

5.1K

R7884

1 2

OMIT

ISL88042IRTEZ

TDFN

U7870

4

1

8

9

3

5

6

2

7

64

100

402

5%

1/16W MF-LF

R7859

12

35

57

CERM

10V

0.1uF

402

20%

C7870

1

2

57

CERM-X5R

0.47UF

10%

6.3V

402

C7801

1

2

CERM

402

0.001UF

20% 50V

C7841

1

2

CERM

20%

0.1uF

10V

402

C7840

1

2

TPS3808G33DBVRG4

SOT23-6

U7840

4

2

3

15

6

MF-LF

1/16W

402

5%

100K

R7840

1

2

NO STUFF

0.47UF

10%

6.3V

CERM-X5R

402

C7812

1 2

5% 1/16W MF-LF

0

402

R7812

1 2

62

5%

5.1K

402

MF-LF

1/16W

R7801

12

10%

NO STUFF

CERM

10V

402

0.068UF

C7802

1

2

10%

CERM

0.068UF

402

10V

NO STUFF

C7813

1

2

1/16W

402

68K

MF-LF

5%

R7813

12

36 25

1/16W

100K

5%

402

MF-LF

R7802

12

SOD-VESM-HF

SSM3K15FV

Q7800

3

1

2

SOD-VESM-HF

SSM3K15FV

Q7813

3

1

2

57

8

62

36

63 8

8

63 8

8

58

S

G

D

S

G

D

G S

IN

D

SG

D

SG

IN

D

G S

D

G S

SGD

IN

D

SG

D

SG

D

S

KELVIN

NC

GND

SENSE

G

OUT

D

G S

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

376S0778

3.3V S3 FET

CHANNEL

MOSFET

RDS(ON)

1.431 A (EDP)

3.3V S0 FET

FDC606P

P-TYPE

26 MOHM @4.5V

RDS(ON)

LOADING

MOSFET

CHANNEL

0.182 A (EDP)

48 mOhm @4.5V

P-TYPE

FDC638P

3.3V S3 FET

MCP79 DDRVTT FET

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.

MUST GUARANTEE MEM_CKE SIGNALS ARE LOW

IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE

90mA max load @ 0.9V

81mW max power

CKT FROM T18

(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)

1.5V S0 FET

CHANNEL

RDS(ON)

MOSFET

LOADING

N-TYPE

5A (EDP)

6.3 mOHM @4.5V VGS

Rome SenseFET

1.5V S0 FET

MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

UNTIL AFTER RAIL TURNS BACK ON OR DIMMS

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

WILL EXIT SELF-REFRESH PREMATURELY.

BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

LOW THROUGH VTT TERMINATION RESISTORS.

3.3V S0 FET

LOADING

RDS(ON)

MOSFET

CHANNEL

LOADING

TPCP8102

P-TYPE

13.5 MOHM @4.5V

0.48 A (EDP)

13.5 MOHM @4.5V

P-TYPE

TPCP8102

LOADING

CHANNEL

MOSFET

RDS(ON)

5.0V LT S0 FET

5.0V RT S0 FET

376S0778

5.0V RT S0 FET

5.0V LT S0 FET

1.302 A (EDP)

79 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP5VRT_S0_FET

P5V0LTS0_SS

=PP5V_S3_P5VLTS0FET

=P5VS0_EN

P5V0LTS0_EN_L

P5V0RTS0_SS

=P5VS0_EN

=P3V3S0_EN

=PP3V3_S0_FET

P1V5_S0_SENSE

MCPDDR_SS

=PP5V_S3_MCPDDRFET

MCPDDR_EN_L_RC

=PP1V5_S0_FET

=PP1V5_S3_P1V5S0FET

P1V5_S0_KELVIN

MCPDDR_EN_L

=MCPDDR_EN

=PP5V_S3_VTTCLAMP

VTTCLAMP_EN

VTTCLAMP_L

=PPVTT_S0_VTTCLAMP

=DDRVTT_EN

=PP3V3_S3_FET

P3V3S3_SS

P3V3S3_EN_L

=P3V3S3_EN

P3V3S0_SS

=PP3V3_S5_P3V3S0FET

P3V3S0_EN_L

=PP3V3_S5_P3V3S3FET

P5V0RTS0_EN_L

=PP5V_S3_P5VRTS0FET

=PP5VLT_S0_FET

SYNC_MASTER=K24_MLB

SYNC_DATE=02/15/2009

POWER FETS

64 63

SOD-VESM-HF

SSM3K15FV

Q7945

3

1

2

47K

1/16W

MF-LF

402

5%

R7942

1

2

1/16W

47K

402

MF-LF

5%

R7940

1 2

16V

CERM

10%

0.01UF

402

C7910

1 2

402

X5R

16V

10%

0.033UF

C7941

1

2

10%

16V

CERM

402

0.01UF

C7940

1 2

41 41

DFN

ROME

CRITICAL

Q7901

9

4

5

6

8

1 2 37

CERM

402

20% 10V

0.1UF

C7902

1

2

MF-LF

1/16W

402

10K

5%

R7901

1 2

1/16W

5%

100K

MF-LF

402

R7903

1

2

CERM 402

0.068UF

10V

10%

C7903

1

2

SSM6N15FEAPE

SOT563

Q7971

6

2

1

402

47K

5% 1/16W MF-LF

R7971

1 2

SSM6N15FEAPE

SOT563

Q7971

3

5

4

63

FDC606P_G

SOT-6

CRITICAL

Q7930

1 2 5 6

3

4

SOD-VESM-HF

SSM3K15FV

Q7905

3

1

2

SOD-VESM-HF

SSM3K15FV

Q7903

3

1

2

58 25

SSM6N15FEAPE

SOT563

Q7975

3

5

4

100K

MF-LF

402

1/16W

5%

R7976

1

2

MF-LF

603

10

5% 1/10W

R7975

12

402

NO STUFF

0.001UF

20% 50V

CERM

C7976

1

2

SSM6N15FEAPE

SOT563

Q7975

6

2

1

63

402

100K

MF-LF

1/16W

5%

R7932

1

2

1/16W

MF-LF

402

47K

5%

R7930

1 2

10%

402

X5R

16V

0.033UF

C7931

1

2

0.01UF

402

CERM

16V

10%

C7930

1 2

402

10K

1/16W

MF-LF

5%

R7912

1

2

402

1/16W

5%

47K

MF-LF

R7910

1 2

402

10%

X5R

16V

0.033UF

C7911

1

2

64 63

SSM3K15FV

SOD-VESM-HF

Q7947

3

1

2

5%

402

MF-LF

1/16W

47K

R7943

1

2

5%

MF-LF

402

47K

1/16W

R7944

1 2

0.01UF

402

CERM

16V

10%

C7943

1 2

0.033UF

10% 16V

X5R

402

C7942

1

2

23V1K-SM

TPCP8102

CRITICAL

Q7948

5 6 7 8

4

1 2 3

23V1K-SM

CRITICAL

TPCP8102

Q7940

5 6 7 8

4

1 2 3

CRITICAL

FDC638P_G

SM

Q7910

1

2

5

6

3

4

8

SYM_VER-1

FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED

ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY

SYM_VER-1

NC

OUT

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LVDS CONNECTOR:518S0650

LVDS I/F

(LVDS DDC POWER)

CAMERA I/F

CAMERA

LCD CONNECTOR

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

LED BKLT I/F

90 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

=PP5V_S3_CAMERA

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

PP3V3_LCDVDD_SW

MIN_NECK_WIDTH=0.20 MM

=PP3V3_S0_LCD

USB_CAMERA_P

USB_CAMERA_N

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

=PP3V3_S5_LCD

LVDS_IG_PANEL_PWR

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

PP3V3_S0_LCD_F

LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P

LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0>

PPVOUT_S0_LCDBKLT

LED_RETURN_5

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<2>

LVDS_IG_DDC_CLK

LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1>

LED_RETURN_6

LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP5V_S3_CAMERA_F

VOLTAGE=5V

USB_CAMERA_CONN_N

USB_CAMERA_CONN_P

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

PP3V3_LCDVDD_SW_F

LVDS_IG_DDC_DATA

SYNC_DATE=02/15/2009

LVDS CONNECTOR

SYNC_MASTER=K24_MLB

0402-LF

FERR-120-OHM-1.5A

L9004

1 2

1/16W MF-LF

100K

5%

402

R9008

1

2

100K

5%

MF-LF

1/16W

402

R9009

1

2

PLACEMENT_NOTE=PLACE CLOSE TO J9000

5% 50V C0G-CERM

1000PF

603

C9017

1

2

FPF1009

MFET-2X2

CRITICAL

U9000

617

2

3

4

5

73 20

CRITICAL

PLACEMENT_NOTE=PLACE CLOSE TO J9000.

90-OHM DLP0NS

L9060

12

3 4

402

CERM

20% 10V

0.1uF

C9016

1

2

FERR-120-OHM-1.5A

0402-LF

L9050

12

F-RT-SM

CRITICAL

20474-030E-11

J9000

31 32

33 34

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

4 5 6 7 8 9

10%

402

16V X5R

0.1UF

C9009

1

2

CRITICAL

AMC2012-SM

90-OHM-200MA

L9080

1

23

4

50V

10% X7R

0.001UF

402

C9010

1

2

0.001UF

402

10% X7R

50V

C9015

1

2

402

1K

5% 1/16W MF-LF

R9014

1

2

0402-LF

120-OHM-0.3A-EMI

CRITICAL

L9008

1 2

16V

0.1UF

402

X5R

10%

C9011

1

2

X5R

6.3V

20%

10UF

603

C9012

1

2

8

72 18

8

18

7

72 7

72 18 7

68 47 7

68 7

72 18 7

18 7

72 18 7

68 7

7

73 7

7

18 7

D

SG

D

GS

BI

D

S G

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AUX CH has 100K pull up/down on the MLB)..

Display Port Interoperability spec says that sources

external adapter for pull ups on DDC lines (since DP

or sinks which do both DP and DVI must depend on the

93 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP5V_S0_DP_AUX_MUX

DP_IG_CA_DET

DP_CA_DET

DDC_CA_DET_LS5V_L

DP_IG_DDC_DATA

MAKE_BASE=TRUE

DP_IG_DDC_CLK

MAKE_BASE=TRUE

=MCP_HDMI_DDC_DATA

MAKE_BASE=TRUE

DP_ML_N<1>

MAKE_BASE=TRUE

DP_ML_P<0>

=MCP_HDMI_TXC_N

DP_ML_P<3>

MAKE_BASE=TRUE

DP_ML_N<3>

=MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2>

MAKE_BASE=TRUE

DP_ML_N<0>

MAKE_BASE=TRUE

DP_ML_P<1>

MAKE_BASE=TRUE

DP_ML_N<2>

MAKE_BASE=TRUE

DP_ML_P<2>

=MCP_HDMI_HPD

DP_HPD

MAKE_BASE=TRUE

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_P

DP_AUX_CH_C_P

DP_IG_DDC_DATA

DP_AUX_CH_SW_P

DP_IG_AUX_CH_P

DP_AUX_CH_SW_N

DP_AUX_CH_C_N

DP_IG_DDC_CLK

DP_IG_AUX_CH_N

DISPLAYPORT SUPPORT

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

1/16W

402

MF-LF

5%

1K

R9306

1

2

5% 1/16W MF-LF 402

100K

R9302

1

2

402

10% 16V X5R

0.1UF

C9301

1 2

18

67

SOT563

SSM6N15FEAPE

Q9300

3

5

4

72 67

72 18

66

SSM3K15FV

SOD-VESM-HF

Q9301

3

1

2

0.1UF

X5R

10% 16V

402

C9300

1 2

5%

1/16W

33

402

MF-LF

R9300

1 2

33

5%

MF-LF

402

1/16W

R9301

1 2

SOT563

SSM6N15FEAPE

Q9300

6

2

1

8

66

18

72 67

18

72 67

18

18 72 67

72 67

18 67

18

72

OUT

BI

IN

IO NC NC

IO

GND

OUT

IO NC NC

IO

GND

IO NC NC

IO

GND

IO NC NC

IO

GND

IN

G

D

S

G

D

S

SYM_VER-2

G

D

S

G

D

S

BI

IN

OC*

OUT

EN

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P ML_LANE3N

ML_LANE2N

CONFIG1 CONFIG2

BOT ROW TOP ROW

TH PINS SM PINS

SHIELD PINS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

100K if DP_HPD is used.

MCP79 requires pull

down HPD input with

(CA) has 100k

to 100K (DPv1.1a).

pull-up to DP_PWR.

greater than or equal

DP Source must pull

DP to DVI/HDMI

down HPD input with

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

Cable Adapter

Port Power Switch

514-0691

POR IS PLASTIC MINI DP CONNECTOR BUT METAL PART’S SCHEMATIC AND CAD SUMBOLS HAVE BEEN USED BEACUSE ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES

94 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

DP_ML_CONN_N<0>

DP_CA_DET_Q

DP_ML_CONN_N<3>

DP_ML_C_N<3>

DP_AUX_CH_C_P

DP_AUX_CH_C_N

=PP3V3_S0_DPCONN

TP_DPPWR_OC_L

DP_ML_CONN_P<0>

DP_ML_P<3>

DP_ML_C_N<2>

DP_ML_C_P<2>

DP_ML_C_N<1>

DP_ML_C_P<1>

DP_ML_C_P<0>

DP_ML_C_N<0>

DP_ML_N<0>

DP_CA_DET_L_Q

=PP3V3_S0_DPCONN

DP_CA_DET

DP_HPD_L_Q

DP_ML_N<3>

DP_ML_P<0>

DP_ML_P<1>

DP_ML_N<1>

DP_ML_P<2>

DP_ML_N<2>

DP_HPD

PM_SLP_S3_L

=PP3V3_S5_DP_PORT_PWR

DP_ML_C_P<3>

DP_ML_CONN_P<3>

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

PP3V3_S0_DPILIM

DP_ML_CONN_P<1>

HDMI_CEC

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

DP_ML_CONN_N<2>

DP_ML_CONN_P<2>

DP_ML_CONN_N<1>

DP_HPD_Q

SYNC_MASTER=K24_MLB

DisplayPort Connector

SYNC_DATE=04/06/2009

MINIDSPLYPRT-K83

OMIT

F-RT-THSM

CRITICAL

J9400

18

16

4

6

20

1

78

1314

2

2122

5

3

11

9

17

15

12

10

19

SOT23

TPS2051B

CRITICAL

U9480

4

2

5

3

1

63 36 32 21 7

72 66

603

X5R-CERM-1

6.3V

22UF

CRITICAL

20%

C9486

1

2

6.3V

X5R-CERM-1

22UF

603

20%

C9485

1

2

20%

X5R-CERM

6.3V

4.7UF

402

C9481

1

2

20%

22UF

X5R-CERM-1

603

6.3V

C9480

1

2

100K

402

1/16W MF-LF

5%

R9446

1

2

SOT-363

2N7002DW-X-G

Q9441

6

2

1

MF-LF

1/16W

402

5%

1M

R9422

1

2

SOT-363

2N7002DW-X-G

Q9441

3

5

4

5%

1/16W

402

MF-LF

10K

R9445

1

2

1/16W

402

5%

MF-LF

10K

R9444

1

2

TCM1210-4SM

12-OHM-100MA

FL9403

1

23

4

TCM1210-4SM

12-OHM-100MA

FL9400

1

2 3

4

12-OHM-100MA TCM1210-4SM

FL9402

1

2 3

4

TCM1210-4SM

12-OHM-100MA

FL9401

1

2 3

4

100K

1/16W

402

5%

MF-LF

R9442

1

2

1/16W

402

MF-LF

5%

100K

R9443

1

2

SOT-363

2N7002DW-X-G

Q9440

6

2

1

2N7002DW-X-G

SOT-363

Q9440

3

5

4

72 66

100K

402

1/16W MF-LF

5%

R9423

1

2

0603

FERR-120-OHM-3A

L9400

1 2

X5R-CERM

6.3V

20%

4.7UF

402

C9400

1

2

72 66

0.1uF

16V 402X5R10%

C9412

1 2

16V10% 402X5R

0.1uF

C9413

1 2

16V10% 402X5R

0.1uF

C9416

1 2

16V10% 402X5R

0.1uF

C9417

1 2

DP_ESD

SLP2510P8

CRITICAL

RCLAMP0524P

D9410

3

2 1

9

10

1M

1/16W

5%

MF-LF 402

R9425

1

2

SLP2510P8

DP_ESD

CRITICAL

RCLAMP0524P

D9411

3

5 4

6 7

SC70-6-1

RCLAMP0504F

CRITICAL

DP_ESD

D9400

1

3

4

6

2 5

DP_ESD

CRITICAL

SLP2510P8

RCLAMP0524P

D9410

3

5 4

6 7

1/16W MF-LF

5%

100K

402

R9420

1

2

16V10% 402X5R

0.1uF

C9410

1 2

10% 16V 402

0.1uF

X5R

C9411

1 2

66

40210% X5R

0.1uF

16V

C9414

1 2

16V

0.1uF

X5R10% 402

C9415

1 2

CRITICAL

DP_ESD

SLP2510P8

RCLAMP0524P

D9411

3

2 1

9

10

MF-LF

100K

1/16W

5%

402

R9421

1

2

72 66

66

72

72 72

67 8

72

67 8

8

72

72 72

72

OUT

IN

VIN

VDC2

VDC1

EN

WAKE

PWM

COMP

OVP

VOUT

SWB

SWA

FAIL

THRM

PGNDB

PGNDA

GND

ISET

CH1

CH2

CH3

CH4

CH5

CH6

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ACTUAL: ISET = 19.9MA, OVP = 35.2V

TARGET: ISET = 20MA, OVP = 35V

13.3 Inch Panel (9 LEDs per string)

WF: C9711 AND C9717 NOT IN REF SCHEMATIC.

(C9721-C9726)

PLACEMENT_NOTEs:

<Ra>(SGND)

(C9710-C9711)

PLACEMENT_NOTEs:

VOVP = 6.9V +/- 0.35V

OVP = Vovp * (1 + Ra/Rb)

<Rb>

f = 600kHz

<Riset>

ISET = 153mA / <Riset>

97 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

LVDS_IG_BKL_PWM

LVDS_IG_BKL_PWM_R

LCDBKLT_COMP

MIN_LINE_WIDTH=0.2 MM

LCDBKLT_FAIL

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_MC_CH2

BKL_MC_CH3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_MC_CH4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_MC_CH5

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_MC_CH6

BKL_MC_CH1

MIN_NECK_WIDTH=0.20 mm

PPBUS_S0_LCDBKLT_PWR

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=2.5V

PP2V5_S0_LCDBKLT

MIN_LINE_WIDTH=0.3 MM

PP5V5_S0_LCDBKLT

MIN_NECK_WIDTH=0.2 MM VOLTAGE=5.5V

LCDBKLT_COMP_RC

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

LCDBKLT_ISET

MIN_LINE_WIDTH=0.2 MM

LCDBKLT_OVP

ISNS_LCDBKLT_N

VOLTAGE=9V

MIN_NECK_WIDTH=0.38 MM

MIN_LINE_WIDTH=0.5 MM

PPVIN_BKL

DIDT=TRUE

PPVOUT_S0_LCDBKLT_SW

SWITCH_NODE=TRUE

VOLTAGE=50V

MIN_NECK_WIDTH=0.38 MM

MIN_LINE_WIDTH=0.5 MM

GND_LCDBKLT_PGND

MIN_LINE_WIDTH=0.3 MM

LCDBKLT_VIN

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.6 mm

GND_LCDBKLT_PGND

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MM

PPVOUT_S0_LCDBKLT

MIN_NECK_WIDTH=0.24 MM

ISNS_LCDBKLT_P

VOLTAGE=0V

GND_LCDBKLT_SGND

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.24 MM

SYNC_MASTER=VEMURI_K19I

SYNC_DATE=02/09/2009

LCD Backlight Driver (MC34845)

NOSTUFF

5%

PLACE NEAR U9700

402

CERM

100PF

50V

C9721

1

2

MC34845

CRITICAL

LLP

MIN_LINE_WIDTH=0.5 mm

U9700

7

8

9

10

11

12

17

6

14

131921

15

22

5

2

16

4 3

25

20

23

1

24

18

603

X7R

100V

10%

1000PF

PLACEMENT_NOTE=PLACE C9717 CLOSE TO D9710 PIN 2 & XW9701

C9717

1

2

69 18

56PF

50V

CERM

5%

402

C9706

1

2

1% 1/16W MF-LF

7.68K

402

R9710

1

2

603-1

25V

1UF

X5R

10%

C9711

1

2

MF-LF

402

1%

1M

1/16W

R9715

1

2

402

1% 1/16W MF-LF

243K

R9716

1

2

X5R-CERM

2.2UF

10V

20%

402

C9701

1

2

X5R-CERM

10V

2.2UF

20%

402

C9700

1

2

PLACEMENT_NOTE=PLACE CLOSE TO L9710

10%

X5R

25V

805

10UF

CRITICAL

C9710

1

2

65 7

SOD-123

CRITICAL

RB160M-40

PLACEMENT_NOTE=PLACE NEAR L9710

D9710

1 2

10% 50V X7R

2.2UF

CRITICAL

NOSTUFF

1206

C9716

1

2

4.7UF

CRITICAL

20%

X7R-CERM

50V

1206

C9715

1

2

10UH-2.1A

IHLP2020BZ11-SM

CRITICAL

L9710

1 2

PLACEMENT_NOTE=PLACE CLOSE TO U9700 PIN 1

603

50V C0G-CERM

5%

1000PF

C9727

1

2

10K

1/16W

1%

402

MF-LF

R9705

1

2

CERM

50V

0.0022UF

10%

402

C9705

1

2

OMIT

SM

XW9701

1 2

MF-LF

5%

402

1/16W

22K

R9726

1

2

0

5%

MF-LF

1/16W

402

R9725

12

76 47

1%

CRITICAL

0.020

805

MF-LF

0.25W

R9700

1 2 3 4

0.1UF

402

25V X5R

10%

PLACEMENT_NOTE=PLACE CLOSE TO L9710

C9713

1

2

402

MF-LF

5%

10

1/16W

R9730

1

2

NOSTUFF

MF-LF

5%

1/16W

402

0

R9702

1

2

402

1/16W

10.2

MF-LF

1%

R9719

1 2

1/16W

402

10.2

MF-LF

1%

R9722

1 2

10.2

1%

402

1/16W MF-LF

R9721

1 2

402

10.2

1% 1/16W MF-LF

R9720

1 2

1/16W MF-LF

1%

10.2

402

R9718

1 2

10.2

MF-LF

1% 1/16W

402

R9717

1 2

PLACEMENT_NOT=PLACE XW9700 FAR FROM THE NOISY PINS 3 AND 4

SM

OMIT

XW9700

1 2

50V CERM

5%

PLACE NEAR U9700

100PF

NOSTUFF

402

C9725

1

2

100PF

50V

CERM

5%

402

PLACE NEAR U9700

NOSTUFF

C9726

1

2

100PF

50V CERM

PLACE NEAR U9700

402

5%

NOSTUFF

C9723

1

2

5%

50V

100PF

402

NOSTUFF

PLACE NEAR U9700

CERM

C9724

1

2

PLACE NEAR U9700

5%

50V

CERM

402

100PF

NOSTUFF

C9722

1

2

69

68

65 47 7

OUT

IN

D

SG

D

SG

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LOADING

0.4 A (EDP)

43 mOhm @4.5V

P-TYPE

FDC638APZ

RDS(ON)

MOSFET

CHANNEL

PPBUS S0 LCDBkLT FET

MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS

98 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

LVDS_IG_BKL_ON

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

=PPBUS_S0_LCDBKLT

BKLT_EN_L

BKLT_PLT_RST_L

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_PWR

LVDS_IG_BKL_PWM

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

PPBUS_S0_LCDBKLT_EN_DIV

PPBUS_S0_LCDBKLT_EN_L

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

LCD Backlight Support

69 18

SSM6N15FEAPE

SOT563

Q9807

3

5

4

SOT563

SSM6N15FEAPE

Q9807

6

2

1

25

1K

5% 1/16W MF-LF 402

R9840

1

2

5%

MF-LF

1/16W

1K

402

R9841

1

2

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

Q9806

1 2 5 6

3

4

8

16V

10%

X5R

0.1UF

402

C9802

1

2

147K

1%

MF-LF

1/16W

402

R9809

1

2

1/16W

MF-LF

301K

1%

402

R9808

1

2

68

2AMP-32V

0402-HF

F9800

1 2

69 18

68 18

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

Some signals require 27.4-ohm single-ended impedance.

FSB Clock Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SR DG recommends at least 25 mils, >50 mils preferred

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

PHYSICAL

FSB 2X

FSB 4X Signal Groups

ELECTRICAL_CONSTRAINT_SET

FSB 1X Signals

SPACING

NET_TYPE

Signals

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)

CPU / FSB Net Properties

FSB (Front-Side Bus) Constraints

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe.

FSB 2X signals / groups shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.

100 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

FSB_DATA_GROUP0 FSB_50S

FSB_D_L<15..0>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB0

FSB_DSTB_L_P<0>

FSB_DSTB_50S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_50SFSB_DATA_GROUP1

FSB_D_L<31..16>

FSB_DATA

FSB_50SFSB_DATA_GROUP1

FSB_DINV_L<1>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_50SFSB_DATA_GROUP2

FSB_DINV_L<2>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB2

FSB_DSTB_L_N<2>

FSB_50S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_DATA

FSB_50SFSB_DATA_GROUP3

FSB_DINV_L<3>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB3

FSB_DSTB_L_N<3>

FSB_ADDR

FSB_ADDR_GROUP0

FSB_A_L<16..3>

FSB_50S

FSB_ADDR_GROUP0

FSB_REQ_L<4..0>

FSB_ADDR

FSB_50S

FSB_50SFSB_ADDR_GROUP1

FSB_ADDR

FSB_A_L<35..17> FSB_ADSTB_L<1>

FSB_ADSTB1

FSB_ADSTB

FSB_50S

FSB_1X FSB_1X

FSB_ADS_L

FSB_50SFSB_BREQ0_L

FSB_BREQ0_L

FSB_1X

FSB_50S

FSB_BREQ1_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_BNR_L

FSB_50S

FSB_1X FSB_1X

FSB_BPRI_L

FSB_50S

FSB_1X

FSB_DBSY_L

FSB_1X

FSB_50S

FSB_1X

FSB_DEFER_L

FSB_1X

FSB_50S

FSB_1X

FSB_DRDY_L

FSB_1X

FSB_50S

FSB_1X

FSB_HIT_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_HITM_L

FSB_50S

FSB_CPURST_L

FSB_1X

FSB_50S

FSB_1X

FSB_RS_L<2..0>

FSB_1X

FSB_50S

FSB_1X

FSB_TRDY_L

FSB_1X

CPU_50S

CPU_BSEL

CPU_BSEL<2..0>

CPU_AGTL

CPU_50S

CPU_FERR_L

CPU_8MIL

CPU_50S

CPU_ASYNC

CPU_IGNNE_L

CPU_AGTL

CPU_50S

CPU_INIT_L

CPU_AGTL

CPU_50SCPU_ASYNC_R

CPU_INTR

CPU_AGTL

CPU_50SCPU_ASYNC_R

CPU_NMI

CPU_AGTL

CPU_50S

CPU_PROCHOT_L

CPU_AGTL

CPU_50S

CPU_PWRGD

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_SMI_L

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_STPCLK_L

CPU_AGTL

CPU_50S

PM_THRMTRIP_L

CPU_8MIL

CPU_50S

FSB_CPUSLP_L

CPU_AGTL

CPU_50SCPU_FROM_SB

CPU_DPSLP_L

CPU_AGTL

CPU_50S

CPU_DPRSTP_L

CPU_AGTL

CPU_50S

CPU_ASYNC

FSB_DPWR_L

CPU_AGTL

MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_VDD

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_GND

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_VCC

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_GND

MCP_50S

FSB_CLK_CPU

FSB_CLK_CPU_P

CLK_FSB

CLK_FSB_100D

FSB_CLK_CPU

FSB_CLK_CPU_N

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP_P

FSB_CLK_ITP

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP_N

FSB_CLK_MCP CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_P

FSB_CLK_MCP CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_N

CPU_IERR_L

CPU_50S

CPU_IERR_L

CPU_50SPM_DPRSLPVR

CPU_AGTL

PM_DPRSLPVR

CPU_50S

CPU_AGTL

IMVP_DPRSLPVR

CPU_GTLREF

CPU_50S

CPU_GTLREF

CPU_COMP

CPU_50S

CPU_COMP<3>

CPU_COMP

CPU_COMP<2>

CPU_27P4S

CPU_COMP

CPU_COMP<1>

CPU_50S

CPU_COMP

CPU_COMP CPU_COMP

CPU_27P4S

CPU_COMP<0>

XDP_TDI CPU_50S CPU_ITP

XDP_TDI

XDP_TDO CPU_50S CPU_ITP

XDP_TDO

XDP_TMS CPU_50S CPU_ITP

XDP_TMS

XDP_TCK CPU_50S CPU_ITP

XDP_TCK

XDP_TRST_L

CPU_50S CPU_ITP

XDP_TRST_L

XDP_BPM_L

CPU_50S

XDP_BPM_L<4..0>

CPU_ITP

XDP_BPM_L5

CPU_50S CPU_ITP

XDP_BPM_L<5> XDP_CPURST_L

CPU_ITPCPU_50S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

IMVP6_VSEN_N

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_50S

IMVP6_VID<6..0>

CPU_8MIL

CPU_VID<6..0>

CPU_50S

CPU_8MIL

FSB_ADSTB

FSB_50S

FSB_ADSTB_L<0>

FSB_ADSTB0

FSB_DSTB_L_N<1>

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB1

FSB_50S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

CPU_50S

CPU_ASYNC

CPU_A20M_L

CPU_AGTL

FSB_50S

FSB_1X FSB_1X

FSB_LOCK_L

FSB_DATA_GROUP0 FSB_50S

FSB_DINV_L<0>

FSB_DATA

=2x_DIELECTRIC

* ?

FSB_ADSTB

* ?

FSB_1X

=STANDARD

?

FSB_ADDR

*

=STANDARD

=3x_DIELECTRIC

*

FSB_DSTB

?

=2x_DIELECTRIC

?*

FSB_DATA

=3x_DIELECTRIC

?

TOP,BOTTOMFSB_1X

=3x_DIELECTRIC

?

TOP,BOTTOMFSB_ADDR

=5x_DIELECTRIC

?

FSB_DSTB TOP,BOTTOM

=4x_DIELECTRICFSB_DATA

?

TOP,BOTTOM

=50_OHM_SE

=STANDARD

=50_OHM_SE=50_OHM_SE

FSB_50S

=STANDARD

*

=50_OHM_SE

=4x_DIELECTRIC

?

FSB_ADSTB

TOP,BOTTOM

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

FSB_DSTB_50S

=50_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

CPU/FSB Constraints

=2x_DIELECTRICTOP,BOTTOM

?

CPU_AGTL

TOP,BOTTOM

?

CLK_FSB

=4x_DIELECTRIC

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

CPU_50S

=STANDARD=STANDARD

*

CPU_27P4S

7 MIL 7 MIL

=27P4_OHM_SE=27P4_OHM_SE

*

=27P4_OHM_SE

=STANDARD

* ?

CPU_AGTL

* ?

CPU_8MIL

8 MIL

25 MIL

*

CPU_COMP

?

=2:1_SPACING

?*

CPU_ITP

?*

CPU_GTLREF 25 MIL

25 MIL

?

CPU_VCCSENSE

*

=STANDARD=STANDARD

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

MCP_50S

=50_OHM_SE

MCP_FSB_COMP

?*

8 MIL

CLK_FSB_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB

?

=3x_DIELECTRIC

14 10

14

14 10

14 13 10

14 10

10 9

14 10

37 14 10

14 13 10

14 10

37 14 10

14 10

59 14 10

14 10

14

14 10

14 13

14

10

59 21

59

26 10

10

13 10

13

59 11

14 10

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

Memory Net Properties

DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

PHYSICAL

Memory Bus Constraints

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MCP MEM COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DDR3:

DDR2:

101 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_CKE<3..0>

MEM_CLK

MEM_A_CLK

MEM_A_CLK_P<5..0>

MEM_70D_VDD

MEM_40S_VDD

MEM_A_CNTL

MEM_CTRL

MEM_A_CKE<3..0>

MEM_CLK

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_70D_VDD

MEM_40S_VDD

MEM_A_CNTL

MEM_A_ODT<3..0>

MEM_CTRL

MEM_40S_VDD

MEM_A_CNTL

MEM_A_CS_L<3..0>

MEM_CTRL

MEM_40SMEM_A_DQ_BYTE2

MEM_DATA

MEM_A_DM<2>

MEM_40SMEM_A_DQ_BYTE3

MEM_A_DM<3>

MEM_DATA

MEM_40SMEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DM<4>

MEM_40SMEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DM<5>

MEM_40SMEM_A_DQ_BYTE6

MEM_A_DM<6>

MEM_DATA

MEM_70D MEM_DQS

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_40SMEM_A_DQ_BYTE1

MEM_A_DM<1>

MEM_DATA

MEM_70D MEM_DQS

MEM_A_DQS_N<0>

MEM_A_DQS0

MEM_70D MEM_DQS

MEM_A_DQS_N<1>

MEM_A_DQS1

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<2>

MEM_A_DQS2

MEM_DQS

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_70D MEM_DQS

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_70D MEM_DQS

MEM_A_DQS_N<5>

MEM_A_DQS5

MEM_DQS

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_70D

MEM_DQS

MEM_A_DQS_P<6>

MEM_A_DQS6

MEM_70D

MEM_DQS

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_70D

MEM_40S_VDD MEM_CMD

MEM_A_CMD

MEM_A_BA<2..0>

MEM_40SMEM_A_DQ_BYTE0

MEM_A_DM<0>

MEM_DATA

MEM_40S

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0

MEM_DATA

MEM_40S

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_DATA

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE7

MEM_40S_VDD

MEM_A_CMD

MEM_CMD

MEM_A_CAS_L

MEM_40SMEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_DATA

MEM_40S_VDD

MEM_A_WE_L

MEM_A_CMD

MEM_CMD

MEM_40S

MEM_DATA

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2

MEM_40S

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1

MEM_DATA

MEM_40S_VDD MEM_CMD

MEM_A_RAS_L

MEM_A_CMD

MEM_40SMEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DQ<39..32>

MEM_40SMEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DQ<47..40>

MEM_DATA

MEM_40S

MEM_B_DQ<47..40>

MEM_B_DQ_BYTE5

MEM_DATA

MEM_B_DQ<39..32>

MEM_40SMEM_B_DQ_BYTE4

MEM_DATA

MEM_40S

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1

MEM_DATA

MEM_40S

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2

MEM_40S_VDD MEM_CMD

MEM_B_WE_L

MEM_B_CMD

MEM_DATA

MEM_40S

MEM_B_DQ<31..24>

MEM_B_DQ_BYTE3

MEM_DATA

MEM_40S

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7

MEM_DATA

MEM_40S

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0

MEM_DATA

MEM_40S

MEM_B_DM<0>

MEM_B_DQ_BYTE0

MEM_40S_VDD MEM_CMD

MEM_B_BA<2..0>

MEM_B_CMD

MEM_DQSMEM_70D

MEM_B_DQS_N<6>

MEM_B_DQS6

MEM_DQSMEM_70D

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_DATA

MEM_40S

MEM_B_DM<7>

MEM_B_DQ_BYTE7

MEM_DQSMEM_70D

MEM_B_DQS_P<6>

MEM_B_DQS6

MEM_DQSMEM_70D

MEM_B_DQS_P<5>

MEM_B_DQS5

MEM_DQS

MEM_B_DQS_N<4>

MEM_70D

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_N<5>

MEM_B_DQS5

MEM_DQSMEM_70D

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_DQSMEM_70D

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_DQSMEM_70D

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_DQSMEM_70D

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_DQSMEM_70D

MEM_B_DQS_P<0>

MEM_B_DQS0

MEM_DQSMEM_70D

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_DATA

MEM_40S

MEM_B_DM<6>

MEM_B_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_B_DM<5>

MEM_B_DQ_BYTE5

MEM_DATA

MEM_40S

MEM_B_DM<3>

MEM_B_DQ_BYTE3

MEM_DQSMEM_70D

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_DATA

MEM_40S

MEM_B_DM<4>

MEM_B_DQ_BYTE4

MEM_DATA

MEM_40S

MEM_B_DM<2>

MEM_B_DQ_BYTE2

MEM_DATA

MEM_40S

MEM_B_DM<1>

MEM_B_DQ_BYTE1

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_ODT<3..0>

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_CS_L<3..0>

MEM_B_CLK

MEM_B_CLK_N<5..0>

MEM_CLKMEM_70D_VDD

MEM_B_CLK

MEM_CLK

MEM_B_CLK_P<5..0>

MEM_70D_VDD

MCP_MEM_COMP_VDD

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MCP_MEM_COMP_GND

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_70D MEM_DQS

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_70D MEM_DQS

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_40S_VDD MEM_CMD

MEM_B_CAS_L

MEM_B_CMD

MEM_40S_VDD MEM_CMD

MEM_B_RAS_L

MEM_B_CMD

MEM_40S_VDD

MEM_B_A<14..0>

MEM_CMD

MEM_B_CMD

MEM_40S_VDD

MEM_A_A<14..0>

MEM_CMD

MEM_A_CMD

MEM_40SMEM_A_DQ_BYTE7

MEM_A_DM<7>

MEM_DATA

MEM_A_DQS_P<0>

MEM_70D MEM_DQS

MEM_A_DQS0

MEM_DQS

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_70D

MCP_MEM_COMP

8 MIL

* ?

=STANDARD

7 MIL7 MIL

Y

MCP_MEM_COMP

*

=STANDARD =STANDARD

MEM_DQSMEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS

MEM_CMD

*

MEM_CTRL2MEMMEM_CTRL

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA MEM_CTRL2MEM

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CTRL MEM_CTRL2MEM

MEM_CLK

*

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

MEM_CLK2MEM

MEM_CLK

*

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

*

MEM_CLK MEM_CLK

MEM_CLK2MEM

*

MEM_2OTHERMEM_DATA

* *

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_DQS

**

MEM_2OTHERMEM_CTRL

* *

MEM_2OTHER

MEM_CLK

**

MEM_DATA2MEMMEM_DATA

*

MEM_CMD

MEM_DATA

MEM_DATA2DATA

MEM_DATA

*

MEM_DATA2MEMMEM_DATA

*

MEM_DQS

MEM_DATA

*

MEM_DATA2MEMMEM_CTRL

*

MEM_DATA2MEMMEM_DATA

MEM_CLK

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

*

MEM_CMD

MEM_CMD2MEM

MEM_CTRL

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

?

=3:1_SPACING

MEM_DQS2MEM

*

25 MILMEM_2OTHER

* ?

MEM_DATA2MEM =3:1_SPACING

* ?

MEM_CMD2MEM

* ?

=3:1_SPACING

MEM_DATA2DATA

* ?

=1.5:1_SPACING

MEM_CTRL2MEM

* ?

=2.5:1_SPACING

MEM_CLK2MEM

* ?

=4:1_SPACING

MEM_CTRL2CTRL

=2:1_SPACING

* ?

=1.5:1_SPACING

MEM_CMD2CMD

* ?

MEM_40S_VDD

=40_OHM_SE=40_OHM_SE=40_OHM_SE

=STANDARD

*

=STANDARD

=40_OHM_SE

MEM_40S

=STANDARD

*

=STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=70_OHM_DIFF=70_OHM_DIFF

*

=70_OHM_DIFF=70_OHM_DIFF

=70_OHM_DIFF

MEM_70D_VDD

=70_OHM_DIFF

=70_OHM_DIFF =70_OHM_DIFF

*

=70_OHM_DIFF =70_OHM_DIFF

MEM_70D

MEM_CMDMEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

Memory Constraints

28 15

27 15

28 15

16

27 15

28 15

27 15

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

NET_TYPE

PHYSICAL

SPACING

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

Digital Video Signal Constraints

SATA Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

ELECTRICAL_CONSTRAINT_SET

PCI-Express

102 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PCIE_90D

PCIE

PCIE_FW_D2R_C_P

PCIE_90D

PCIE

PCIE_FW_D2R_C_N

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_P

MCP_PE1_REFCLK

CLK_PCIE

PCIE_CLK100M_MINI_N

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_CONN_P

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_CONN_N

MCP_PE4_REFCLK

PCIE_CLK100M_FC_P

CLK_PCIE

CLK_PCIE_100D

PCIE

PCIE_90D

CONN_PCIE_MINI_R2D_P

PCIE

PCIE_90D

CONN_PCIE_MINI_R2D_N

PCIE

PCIE_90D

CONN_PCIE_MINI_D2R_N

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_FC_N

PCIE

PCIE_90D

CONN_PCIE_MINI_D2R_P

MCP_PEX_CLK_COMP

MCP_PEX_COMP

PCIE_90D

PCIE

PCIE_MINI_R2D_C_N

PCIE_MINI_R2D_P

PCIE

PCIE_90D

PCIE_MINI_R2D

PCIE

PCIE_MINI_R2D_C_P

PCIE_FW_R2D

PCIE

PCIE_FW_R2D_C_P

PCIE_90D

PCIE_FW_D2R

PCIE

PCIE_FW_D2R_P

PCIE_90D

PCIE

PCIE_MINI_D2R_N

PCIE_90D

PCIE

PCIE_MINI_D2R

PCIE_MINI_D2R_P

PCIE

PCIE_90D

PCIE_FW_R2D_P

PCIE

PCIE_90D

PCIE_FW_R2D_C_N

PCIE_90D

PCIE

PCIE_MINI_R2D_N

PCIE

PCIE_FW_R2D_N

PCIE_90D

PCIE

PCIE_90D

PCIE_FW_D2R_N

DP_100D

DP_ML_CONN_N<3..0>

DISPLAYPORT

DP_ML

DP_ML_CONN_P<3..0>

DP_100D DISPLAYPORT

MCP_HDMI_RSET

MCP_DV_COMP

DP_AUX_CH_SW_N

DP_100D DISPLAYPORT

DISPLAYPORT

DP_AUX_CH_SW_P

DP_100D

DP_IG_AUX_CH_P

DP_100D DISPLAYPORT

DP_AUX_CH

DP_ML

DP_ML_N<3..0>

DP_100D DISPLAYPORT

SATA_90D_HDD

SATA

SATA_HDD_R2D_N

SATA_90D_HDD

SATA

SATA_HDD_R2D_P

SATA_90D_HDD

SATA_HDD_R2D_C_P

SATA

SATA_HDD_R2D

SATA_90D_HDD

SATA_HDD_R2D_C_N

SATA

SATA_90D_HDD

SATA_HDD_R2D_UF_P

SATA

SATA_90D_HDD

SATA

SATA_HDD_D2R_N

SATA_90D_HDD

SATA_HDD_D2R_UF_P

SATA

SATA_90D_HDD

SATA_HDD_D2R_UF_N

SATA

SATA_ODD_R2D_C_P

SATA

SATA_100D

SATA_ODD_R2D

SATA_100D

SATA_ODD_R2D_P

SATA

SATA_100D

SATA_ODD_R2D_C_N

SATA

SATA_90D_HDD

SATA_HDD_D2R_C_P

SATA

LVDS_IG_A_CLK_F_P

LVDS_100D

LVDS

LVDS_IG_A_CLK

LVDS_IG_A_CLK_N

LVDS_100D

LVDS

LVDS_IG_A_CLK_P

LVDS_100D

LVDS

LVDS_IG_A_CLK

MCP_SATA_TERMP

SATA_TERMP

MCP_SATA_TERMP

SATA_ODD_D2R_UF_N

SATA

SATA_100D

SATA

SATA_ODD_D2R_C_P

SATA_90D_HDDSATA_HDD_D2R

SATA

SATA_HDD_D2R_P

SATA_ODD_R2D_N

SATA

SATA_100D

SATA_ODD_R2D_UF_P

SATA

SATA_100D

SATA_ODD_R2D_UF_N

SATA

SATA_100D

SATA

SATA_100D

SATA_ODD_D2R_C_N SATA_ODD_D2R_UF_P

SATA_100D

SATA

SATA_100D

SATA

SATA_ODD_D2R_N

SATA_ODD_D2R

SATA_100D

SATA

SATA_ODD_D2R_P

SATA_90D_HDD

SATA

SATA_HDD_D2R_C_N

MCP_IFPAB_VPROBE

DP_100DTMDS_IG_TXD DISPLAYPORT

TMDS_IG_TXD_P<2..0>

SATA_90D_HDD

SATA_HDD_R2D_UF_N

SATA

MCP_HDMI_VPROBE

MCP_DV_COMP

MCP_IFPAB_RSET

MCP_IFPAB_RSET MCP_DV_COMP

LVDS_IG_A_DATA_N<2..0>

LVDS

LVDS_IG_A_DATA

LVDS_100D

LVDS_IG_A_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_IG_A_DATA

LVDS_IG_A_CLK_F_N

LVDS_100D

LVDS

DP_AUX_CH_C_N

DISPLAYPORTDP_100D

DP_AUX_CH_C_P

DP_100D DISPLAYPORT

DP_IG_AUX_CH_N

DP_100D DISPLAYPORT

TMDS_IG_TXD_N<2..0>

DP_100DTMDS_IG_TXD DISPLAYPORT

DP_100DTMDS_IG_TXC DISPLAYPORT

TMDS_IG_TXC_N

DP_100D DISPLAYPORT

DP_ML_C_N<3..0>

DISPLAYPORTDP_100D

DP_ML_C_P<3..0>

DISPLAYPORTDP_100D

DP_ML

DP_ML_P<3..0>

DISPLAYPORTDP_100DTMDS_IG_TXC

TMDS_IG_TXC_P

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

*

PCIE_90D

SYNC_DATE=03/30/2009

MCP Constraints 1

SYNC_MASTER=K24_MLB

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

*

CLK_PCIE_100D

8 MIL

?*

SATA_TERMP

*

SATA

=4x_DIELECTRIC

?

SATA_90D_HDD =90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

*

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

SATA_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

DP_100D

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF

LVDS_100D

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

*

MCP_DV_COMP

=STANDARD=STANDARD

=STANDARD

20 MIL20 MIL

Y

*

LVDS

* ?

=3x_DIELECTRIC

TOP,BOTTOM

SATA

?

=3x_DIELECTRIC

DISPLAYPORT

* ?

=3x_DIELECTRIC

?

=4x_DIELECTRICTOP,BOTTOM

LVDS

?*

20 MILCLK_PCIE

=3X_DIELECTRIC

?*

PCIE

?

=4x_DIELECTRICTOP,BOTTOM

DISPLAYPORT

?

8 MIL

*

MCP_PEX_COMP

?

=4X_DIELECTRICTOP,BOTTOM

PCIE

I183

I182

30 17

30 7

17

30 17

30

30 17

17 9

30 17

17 9

30

17 9

67

24 18

66

66 18

67 66

34 7

34 20

34

34 20

34

34 20

34 7

34 20

34 7

65 7

65 18

20

34

34 7

34 20

34 7

34

34 7

34

34 20

34 7

24 18

34

24 18

65 18 7

65 7

67 66

66 18

67

67 66

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PCI Bus Constraints

LPC Bus Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPI Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SIO Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

HD Audio Interface Constraints

SMBus Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

103 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

CONN_USB2_BT_P

USB_90D

USB

USB_90D

USB

CONN_USB2_BT_N

USB_90D

USB_CAMERA_N

USB

USB_90D

USB

USB_CAMERA_CONN_N

USB

USB_90D

USB_BT_N

USB_BT

USB_BT_P

USB

USB_90D

USB_CAMERA

USB_CAMERA_P

USB

USB_CAMERA_CONN_P

USB

USB_90D

SPI_MOSI_R

SPI_MOSI

SPI

SPI_55S

SPI

SPI_ALT_MOSI

SPI_55S

SPI

SPI_55S

SPI_ALT_MISO

SPI_55S

SPI

SPI_CS1_R_L

SPI_55S

SPI

SPI_CS1_R_L_USE_MLB

SPI

SPI_55S

SPI_CS0_L

SPI_MISO_R

SPI_55S

SPI

SPI_MOSI

SPI

SPI_55S

SPI_MISO

SPI

SPI_MISO

SPI

SPI_55SSPI_CS0

SPI_CS0_R_L

HDA_55S

HDA

HDA_SYNC_R

HDA_55S

HDA_SYNC

HDA

HDA_SYNC

SPI_55S

SPI_CLK

SPI

HDA_55S

HDA_SDOUT

HDA

HDA_SDOUT

SPI_55SSPI_CLK

SPI

SPI_CLK_R

SPI

SPI_55S

SPI_ALT_CLK

HDA_55S

HDA

HDA_BIT_CLK

HDA_55S

HDA

HDA_RST_L

HDA_55S

HDA

HDA_SDIN0

PM_CLK32K_SUSCLK

CLK_SLOW_55S

CLK_SLOW

PCI_AD24

PCI

PCI_AD<24>

PCI_55S

PCI

PCI_C_BE_L<3..0>

PCI_55S

PCI_C_BE_L

PCI

PCI_AD

PCI_PAR

PCI_55S

PCI_CNTL

PCI

PCI_IRDY_L

PCI_55S

PCI_CNTL

PCI

PCI_PERR_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI_STOP_L

PCI_CNTL

PCI

PCI_SERR_L

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_TRDY_L

PCI

PCI_55S

PCI_INTX_L

PCI_55S

PCI_INTY_L

PCI

CLK_PCI_55S CLK_PCI

PCI_CLK33M_MCP

MCP_PCI_CLK2

CLK_PCICLK_PCI_55S

PCI_CLK33M_MCP_R

LPC_CLK33M_LPCPLUS

CLK_LPCCLK_LPC_55S

MCP_DEBUG<7..0>

MCP_DEBUG

PCI

PCI_55S

PCI_AD<23..8>

PCI_AD

PCI

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_DEVSEL_L

PCI_AD

PCI_AD<31..25>

PCI

PCI_55S

PCI_REQ0_L

PCI

PCI_REQ0_L

PCI_55S

PCI

PCI_FRAME_L

PCI_55S

PCI_CNTL

USB_EXTA_P

USB_90D

USB

USB_EXTA

MCP_LPC_CLK0

CLK_LPC_55S CLK_LPC

LPC_CLK33M_SMC_R LPC_CLK33M_SMC

CLK_LPCCLK_LPC_55S

LPC_55SLPC_RESET_L

LPC

LPC_RESET_L

LPC_55S

LPC

LPC_FRAME_L

LPC_55S

LPC_AD

LPC

LPC_AD<3..0>

PCI_INTZ_L

PCI

PCI_55S

PCI_INTZ_L

PCI_INTW_L

PCI

PCI_INTW_L

PCI_55S

PCI

PCI_GNT1_L

PCI_55S

PCI_REQ1_L

PCI

PCI_55S

PCI

PCI_55S

PCI_GNT0_L

USB

USB_90D

USB_EXTA_MUXED_P

USB_90D

USB_EXTA_N

USB

USB_90D

CONN_USB_EXTA_N

USB

USB_90D

CONN_USB_EXTA_P

USB

USB_90D

USB_EXTA_MUXED_N

SMB_55S

SMB

SMBUS_MCP_1_DATA

MCP_HDA_PULLDN_COMP

MCP_HDA_COMP

PM_CLK32K_SUSCLK_R

CLK_SLOW

CLK_SLOW_55S

MCP_SUS_CLK

HDA_55S

HDA

HDA_SDOUT_R

MCP_USB_RBIAS

MCP_USB_RBIAS_GND

MCP_USB_RBIAS

SMB_55SSMBUS_MCP_0_CLK

SMBUS_MCP_0_CLK

SMB

SMBUS_MCP_0_DATA

SMB

SMBUS_MCP_0_DATA

SMB_55S

SMB

SMBUS_MCP_1_CLK

HDA_55S

HDA

HDA_BIT_CLK_R

HDA_RST_L

HDA_55S

HDA

HDA_RST_R_L

HDA

HDA_SDIN_CODEC

HDA_55S

USB_90D

USB

USB_EXTB_N

USB_90D

USB

USB_TPAD_R_N

USB_90D

USB

USB_TPAD_R_P

USB

USB_90D

USB_TPAD_N

USB_90D

USB

USB_TPAD

USB_TPAD_P

CONN_USB_EXTB_P

USB

USB_90D

USB

CONN_USB_EXTB_N

USB

USB_90D

USB_CARDREADER_N

USB_90D

USB

USB_CARDREADER_P

USB_SD

USB_90D

USB

USB_EXTB

USB_EXTB_P

USB

USB_90D

USB_IR_N

USB

USB_90D

USB_IR_P

USB_IR

=55_OHM_SE

*

=STANDARD =STANDARD

SMB_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=2x_DIELECTRIC

* ?

USB

MCP_USB_RBIAS

8 MIL 8 MIL

=STANDARD=STANDARD

=STANDARD =STANDARD

*

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

MCP Constraints 2

=STANDARD =STANDARD

CLK_SLOW_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

CLK_LPC_55S

*

* ?

LPC

6 MIL

?*

8 MIL

CLK_LPC

*

SPI

?

8 MIL

*

=STANDARD=STANDARD

HDA_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

* ?

CLK_PCI

8 MIL

* ?

PCI

=STANDARD

*

CLK_SLOW

?

8 MIL

?*

8 MIL

MCP_HDA_COMP

=2x_DIELECTRIC

HDA

* ?

=2x_DIELECTRIC

?*

SMB

=STANDARD

*

LPC_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

USB

?

TOP,BOTTOM =4x_DIELECTRIC

=STANDARD=STANDARD

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

SPI_55S

=55_OHM_SE

USB_90D

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

*

=90_OHM_DIFF

=STANDARD

*

=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

PCI_55S

=55_OHM_SE

=55_OHM_SE=55_OHM_SE

=STANDARD

CLK_PCI_55S

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

30 7

65 20

65 7

30 20

65 20

65 7

48 38 21

38

48

48 38 21

38 21

21

49 21

48

49 21

48 38 21

38

49 21

36 25

19

38 25

19 13

19

35 20

25 19

36 25

25 19

38 36 19

19

35

35 20

35

39 21

21

25 21

21

20

39 21 13

39 21

21

35 20

44

44 20

35

20 9

35 20

20 9

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

88E1116R (Ethernet PHY) Constraints

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

MCP RGMII (Ethernet) Constraints

SPACING

104 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MCP_MII_COMP

MCP_MII_COMP_VDD

MCP_MII_COMP

ENET_RXD_R<3..0>

ENET_MII_55S

ENET_MII

ENET_CLK125M_RXCLK

ENET_MII_55S

ENET_MII

ENET_RXCLK

ENET_RXD_STRAP

ENET_RXD<3..1>

ENET_MII_55S

ENET_MII

MCP_CLK25M_BUF0_R

ENET_MII_55S

MCP_CLK25M_BUF0

MCP_BUF0_CLK

RTL8211_CLK25M_CKXTAL1

MCP_BUF0_CLKENET_MII_55S

ENET_MII_55S

ENET_MII

ENET_MDIO

ENET_MDIO ENET_MDC

ENET_MDC ENET_MII

ENET_MII_55S

ENET_PWRDWN_L

ENET_MII_55S

ENET_MII

ENET_PWRDWN_L

ENET_RXD

ENET_RXD<0>

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_CLK125M_RXCLK_R

ENET_INTR_L

ENET_MII_55S

ENET_INTR_L

ENET_MII

MCP_MII_COMPMCP_MII_COMP

MCP_MII_COMP_GND

ENET_CLK125M_TXCLK_R

ENET_MII

ENET_MII_55S

ENET_TXCLK

ENET_MII

ENET_MII_55S

ENET_CLK125M_TXCLK

ENET_TXD

ENET_MII_55S

ENET_MII

ENET_TXD<3..1>

ENET_TXD0

ENET_MII

ENET_MII_55S

ENET_TXD<0>

ENET_TXD

ENET_TX_CTRL

ENET_MII

ENET_MII_55S

ENET_RESET_L

ENET_MII_55S

ENET_MII

ENET_MDI

ENET_MDI_N<3..0>

ENET_MDI_100D

ENET_MDI

ENET_MDI_P<3..0>

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI

ENET_MDI_TRAN_P<3..0>

ENET_MDI

ENET_MDI_100D

ENET_MDI_TRAN_N<3..0>

ENET_RXD

ENET_RX_CTRL

ENET_MII_55S

ENET_MII

ENET_RXCTL_R

ENET_MII

ENET_MII_55S

25 MIL

?*

ENET_MDI

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=55_OHM_SE

ENET_MII_55S

=STANDARD =STANDARD

*

?*

ENET_MII 12 MIL

=3:1_SPACING

* ?

MCP_BUF0_CLK

=STANDARD

7.5 MIL

=STANDARD =STANDARD

7.5 MIL

=STANDARD

*

MCP_MII_COMP

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

Ethernet Constraints

ENET_MDI_100D

=100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

18

31

31 18

32 18

32 31

31 18

31

18

31

31 18

33 31

33

31 18

31

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

106 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SMB

SMBUS_SMC_B_S0_SCL

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMB_55S

SMBUS_SMC_0_S0_SCL

SMB

SMB_55S

SMBUS_SMC_0_S0_SDA

SMB

SMB_55S

SMB

SMBUS_SMC_BSA_SCL

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMB_55SSMBUS_SMC_MGMT_SCL

SMB

SMBUS_SMC_MGMT_SDA

SMB_55S

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMBUS_SMC_A_S3_SDA

SMB

SMB_55S

SMBUS_SMC_A_S3_SCL

SMB

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSO_N

1TO1_DIFFPAIR

=STANDARD =STANDARD

0.1 MM 0.1 MM

*

=STANDARD=STANDARD

1TO1_DIFFPAIR

SMC Constraints

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

39

39 7

39

39 7

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER SIZE

D

R

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PAGE TITLE

C

A

D

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Apple Inc.

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A

B

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345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

K84 SENSOR NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

107 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

DIFFPAIR

CPUTHMSNS_D2_P

DIFFPAIR

CHGR_CSO_R_N

CHGR_CSO_R_P

DIFFPAIR

CPUTHMSNS_D2_N

DIFFPAIR

CPU_THERMD_P

DIFFPAIR

ISNS_AIRPORT_P

DIFFPAIR

ISNS_1V5_S3_R_N

ISNS_HDD_N

DIFFPAIR

ISNS_LCDBKLT_P

DIFFPAIR

ISNS_LCDBKLT_N

DIFFPAIR

ISNS_1V5_S3_P

DIFFPAIR

ISNS_AIRPORT_N

DIFFPAIR

ISNS_ODD_N

DIFFPAIR

ISNS_ODD_P

DIFFPAIR

ISNS_HDD_R_N

DIFFPAIR

MCPTHMSNS_D2_N

DIFFPAIR

ISNS_HDD_P

ISNS_CPUVTT_N

DIFFPAIR

CPU_THERMD_N

DIFFPAIR

ISNS_AIRPORT_R_N

DIFFPAIR

ISNS_1V5_S3_R_P

DIFFPAIR

ISNS_1V5_S3_N

DIFFPAIR

ISNS_AIRPORT_R_P

DIFFPAIR

ISNS_ODD_R_N

DIFFPAIR

ISNS_ODD_R_P

MCP_THMDIODE_N

DIFFPAIR

MCP_THMDIODE_P

MCPTHMSNS_D2_P

DIFFPAIR

ISNS_HDD_R_P

ISNS_CPUVTT_P

DIFFPAIR

=STANDARD =STANDARD

*

0.1 MM

=STANDARD=STANDARD

DIFFPAIR

0.1 MM

SYNC_DATE=01/19/2009

K84 SPECIAL CONSTRAINTS

SYNC_MASTER=K24_MLB

42

56

42

42 10

47 30

47

47 34

68 47

58 47

47 30

47 34

47

42

47 34

41

42 10

47

58 47

47

42 21

42

47

41

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

K84 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

109 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TOP,BOTTOM 0.310 MM

27P4_OHM_SE

Y

0.310 MM

TOP,BOTTOM 0.115 MM

Y

0.115 MM

50_OHM_SE

0.165 MMTOP,BOTTOM

40_OHM_SE

Y

0.100 MM

=STANDARD

*

40_OHM_SE

Y

=STANDARD

0.126 MM

*

0.076 MM

55_OHM_SE =STANDARD

=STANDARD=STANDARD

Y

0.076 MM

0.400 MM0.400 MM

ISL3,ISL4,ISL9,ISL10

100_OHM_DIFF_HDD

Y

0.083 MM 0.083 MM

110_OHM_DIFF

=STANDARD

*

=STANDARD=STANDARD

N

=STANDARD =STANDARD

0.280 MM

4X_DIELECTRIC

?

TOP,BOTTOM

0.210 MM

?

3X_DIELECTRIC

TOP,BOTTOM

0.350 MMTOP,BOTTOM

?

5X_DIELECTRIC

=STANDARD

27P4_OHM_SE

* Y

=STANDARD =STANDARD

0.222 MM 0.222 MM

110_OHM_DIFF

Y

ISL3,ISL4,ISL9,ISL10

0.330 MM 0.330 MM

0.075 MM0.075 MM

1:1_DIFFPAIR

*

=STANDARD

0.1 MM0.1 MM

=STANDARD=STANDARD

Y

110_OHM_DIFF TOP,BOTTOM

Y

0.330 MM 0.330 MM

0.077 MM0.077 MM

5X_DIELECTRIC

?

*

0.315 MM

4X_DIELECTRIC

?

*

0.252 MM

3X_DIELECTRIC

?

*

0.189 MM

2X_DIELECTRIC

*

?

0.126 MM

0.140 MMTOP,BOTTOM

?

2X_DIELECTRIC

?*

0.4 MM

4:1_SPACING

*

0.3 MM

?

3:1_SPACING

1.5:1_SPACING

*

0.15 MM

?

2:1_SPACING

0.2 MM

* ?

0.25 MM

?

2.5:1_SPACING

*

=DEFAULT

?

BGA_P3MM

=DEFAULTBGA_P2MM

* ?

*

0.1 MM

?

DEFAULT

STANDARD

* ?

=DEFAULT

BGA_P1MM

?*

=DEFAULT

BGA_P2MMBGA_P1MM

*

CLK_PCIE

BGA_P1MMCLK_SLOW

*

BGA_P2MM

BGA_P1MMFSB_DSTB BGA_P3MMFSB_DSTB

BGA_P1MM BGA_P2MM

*

CLK_PCI

CLK_LPC

BGA_P2MM

*

BGA_P1MM

BGA_P2MM

*

CLK_FSB

BGA_P1MM

* *

BGA_P1MM BGA_P1MM

*

BGA_P2MMBGA_P1MM

MEM_CLK

BGA_P1MM STANDARD

MEM_40S

STANDARDBGA_P1MM

MEM_40S_VDD

50_OHM_SE

*

=STANDARD =STANDARD

Y

=STANDARD

0.076 MM0.076 MM

0.100 MM

ISL3,ISL4,ISL9,ISL10

70_OHM_DIFF

Y

0.151 MM

0.224 MM 0.224 MM

=STANDARD

70_OHM_DIFF

=STANDARD

* N

=STANDARD

0.100 MMTOP,BOTTOM

70_OHM_DIFF

Y

0.185 MM

0.200 MM0.200 MM

*

=STANDARD=STANDARD

90_OHM_DIFF

=STANDARD

N

ISL3,ISL4,ISL9,ISL10

90_OHM_DIFF

Y

0.095 MM 0.095 MM

0.234 MM 0.234 MM

TOP,BOTTOM

Y

90_OHM_DIFF

0.220 MM 0.220 MM

0.112 MM0.112 MM

0.400 MM

0.095 MM0.095 MMTOP,BOTTOM100_OHM_DIFF_HDD

Y

0.400 MM

=STANDARD

N*

100_OHM_DIFF_HDD

=STANDARD

=STANDARD =STANDARD

=STANDARD

100_OHM_DIFF 0.075 MM 0.075 MM

0.244 MM0.244 MM

Y

ISL3,ISL4,ISL9,ISL10

100_OHM_DIFF TOP,BOTTOM 0.091 MM

0.230 MM 0.230 MM

0.091 MM

Y

100_OHM_DIFF

=STANDARD

*

=STANDARD

N

=STANDARD

0.090 MM

55_OHM_SE

Y

TOP,BOTTOM 0.090 MM

*

STANDARD =DEFAULT

=DEFAULT

12.7 MM

Y

30 MM

0.100MMDEFAULT

=50_OHM_SE

* Y

0 MM 0 MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA_P1MM

MM

15.5.1

SYNC_DATE=01/19/2009

K84 RULE DEFINITIONS

SYNC_MASTER=K24_MLB

Apple A1342 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual