Apple A1342 Schematic

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

DATE

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

3456

8 7 6 5 4 2 1

APPD

DESCRIPTION OF REVISION

PROD OK2FAB 11/01/2009

Schematic / PCB #’s

K84 MLB SCHEMATIC

1 OF 77

0000813234

051-7982

C.0.0

1 OF 109

PRODUCTION RELEASED

2009-11-01

External USB Connectors

02/05/2009

K24_MLB

SATA Connectors

01/19/2009

K24_MLB

ETHERNET CONNECTOR

04/06/2009

K24_MLB

Ethernet & AirPort Support

04/06/2009

K24_MLB

Ethernet PHY (RTL8211CL)

04/06/2009

K24_MLB

X16 WIRELESS CONNECTOR

01/27/2009

K24_MLB

DDR3 Support

04/06/2009

K24_MLB

DDR3 SO-DIMM Connector B

02/05/2009

K24_MLB

DDR3 SO-DIMM Connector A

02/05/2009

K24_MLB

FSB/DDR3 Vref Margining

04/06/2009

K24_MLB

SB Misc

02/15/2009

K24_MLB

MCP Graphics Support

04/06/2009

K24_MLB

MCP Standard Decoupling

04/06/2009

K24_MLB

MCP Power & Ground

04/06/2009

K24_MLB

MCP HDA & MISC

03/24/2009

K24_MLB

MCP SATA & USB

04/06/2009

K24_MLB

MCP PCI & LPC

04/06/2009

K24_MLB

MCP Ethernet & Graphics

04/06/2009

K24_MLB

MCP PCIe Interfaces

04/06/2009

K24_MLB

MCP Memory Misc

04/06/2009

K24_MLB

MCP Memory Interface

04/06/2009

K24_MLB

MCP CPU Interface

04/06/2009

K24_MLB

eXtended Debug Port(MiniXDP)

02/25/2009

K24_MLB

CPU Decoupling

03/30/2009

K24_MLB

CPU Power & Ground

04/06/2009

K24_MLB

CPU FSB

04/06/2009

K24_MLB

SIGNAL ALIAS

02/04/2009

K24_MLB

Power Aliases

02/04/2009

K24_MLB

FUNC TEST

02/04/2009

K24_MLB

Revision History

01/19/2009

K24_MLB

Revision History

01/19/2009

K24_MLB

BOM Configuration

01/19/2009

K24_MLB

Power Block Diagram

System Block Diagram

01/19/2009

K24_MLB

CPU/FSB Constraints

100

K24_MLB

04/06/2009

LCD Backlight Support

K24_MLB

04/06/2009

LCD Backlight Driver (MC34845)

VEMURI_K19I

02/09/2009

DisplayPort Connector

K24_MLB

04/06/2009

DISPLAYPORT SUPPORT

K24_MLB

04/06/2009

LVDS CONNECTOR

K24_MLB

02/15/2009

POWER FETS

K24_MLB

02/15/2009

POWER SEQUENCING

K24_MLB

02/15/2009

MISC POWER SUPPLIES

K24_MLB

03/24/2009

CPU VTT(1.05V) SUPPLY

K24_MLB

02/04/2009

MCP CORE REGULATOR

K24_MLB

02/15/2009

IMVP6 CPU VCore Regulator

K24_MLB

03/03/2009

1.5V/0.75V DDR3 SUPPLY

5V/3.3V SUPPLY

PBUS Supply/Battery Charger

K24_MLB

02/05/2009

DC-In & Battery Connectors

K24_MLB

02/05/2009

AUDIO: JACK TRANSLATORS

AUDIO

06/09/2009

AUDIO: JACK

AUDIO

06/09/2009

AUDI0: SPEAKER AMP

AUDIO

06/09/2009

AUDIO: HEADPHONE FILTER

AUDIO

06/09/2009

AUDIO: LINE INPUT FILTER

AUDIO

06/09/2009

AUDIO: CODEC/REGULATOR

AUDIO

06/09/2009

SPI ROM

K24_MLB

02/15/2009

DEBUG SENSORS AND ADC

K19_IMLB

02/25/2009

46 SMS

K24_MLB

03/04/2009

WELLSPRING 2

K24_MLB

02/25/2009

WELLSPRING 1

K24_MLB

03/04/2009

43 Fan

K24_MLB

04/06/2009

Thermal Sensors

K24_MLB

02/04/2009

Current Sensing

K24_MLB

01/27/2009

VOLTAGE SENSING

K24_MLB

04/06/2009

K84 SMBUS CONNECTIONS

K24_MLB

01/19/2009

LPC+SPI Debug Connector

K24_MLB

02/15/2009

SMC Support

K24_MLB

02/04/2009

K84 RULE DEFINITIONS

109

01/19/2009

K24_MLB

K84 SPECIAL CONSTRAINTS

107

01/19/2009

K24_MLB

SMC Constraints

106

04/06/2009

K24_MLB

Ethernet Constraints

104

04/06/2009

K24_MLB

MCP Constraints 2

103

04/06/2009

K24_MLB

MCP Constraints 1

102

03/30/2009

K24_MLB

Page Sync

Date

(.csa)

Contents

PCB

CRITICAL

820-2567

PCBF,MLB,K84

CRITICAL

SCH

051-7982

SCHEM,MLB,K84

Contents

Page

Date

Sync

(.csa)

Memory Constraints

101

04/06/2009

K24_MLB

36 SMC

K24_MLB

04/02/2009

Contents

Page Sync

(.csa)

Date

Table of Contents

01/19/2009

K24_MLB

SCHEM,MLB,K84

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

MINI DISPLAY PORT

10/100/1000M E-NET

USB 2.0

PG 56-64

PG 55

PG 45

PG 27,28

PG 43

PG 42

PG 48

PG 46

PG 38

PG 36,37

PG 35

PG 65PG 45PG 30

PG 53

PG 52

PG 51

PG 49

PG 33

PG 31

PG 30

MINI PCI-E

AirPort

J3401

PG 17

J3900

GIGABIT

RTL8211CL

PG 18

PG 19 PG 21

MIC

LINE-IN/LINE OUT

Amp

U6700

HEADPHONE/LINE OUT

MUX

LINE-IN

Speaker

U6500

U6610,U6620,U6630

J6700,J6701,J6702,J6703,J6704

Conns

Audio

U6201

CIRRUS LOGIC CS4206

Codec

Audio

PG 21

SMB

TRACKPAD

BSAB,0

SUDDEN MOTION SENSOR

U5920

U5515,U5535

Boot ROM

CURRENT & VOLTAGE SENSORS

Ser

Port80,serial

PG 53,54,60

U4900

FAN CONN AND CONTROL

ADC

CPU & MCP THERMAL SENSORS

J6950,J6900

DC-DC POWER SUPPLIES

DC/BATT CONN

J5601

SPI

SMC

H8S/2117

MEMORY

MAIN

J3100,J3200

DIMM

U6100

PG 13

XDP CONN

U1300

B03

MCP79

PG 21

Misc

FSB INTERFACE

2 SODIMMS

DDR3 1067MHZ

PG 15,16

PG 14

64-Bit

FSB

1067 MHZ

CORE 2 DUO

INTEL CPU

2.26 GHZ

PG 10

PENRYN

SYNTH

NVIDIA

U3700

RGMII

HDMI OUT

DP OUT

LVDS OUT

UP TO 20 LANES3

PCI-E

DVI OUT

U1400

Bluetooth

760 1

CAMERA

HDA

RGB OUT

SATA

GPIOs

LPC Conn

Prt

Fan

J5100

SPI

TRACKPAD/

KEYBOARD

Conn

ODD

U1000

Amps

E-NET

Conn

SATA

PCI

(UP TO FOUR PORTS)

SATA

CLK

CTRL

TMDS OUT

Conn

LVDS

CONN

J9000

J9400

PWR

LPC

PG 19

USB

Connectors

EXTERNAL

2 3

(UP TO 12 DEVICES)

PG 20

J3401

J5800

J4600,4610

J9000

SMC

MIKEYDIMMS

CONN

PG 18

PG 65

PG 67

PG 20PG 34

PG 34

J4501

J4500

051-7982

C.0.0

2 OF 109

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

System Block Diagram

SYNC_DATE=01/19/2009

SYNC_MASTER=K24_MLB

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

04-1

PM_WLAN_EN_L

NAND GATE

GATE

PM_SLP_S3_L

PCI_RESET0#

RC DELAY

=DDRREG_EN

=DDTVTT_EN

TPS51116

PM_SLP_S3_L

P1V8S0_EN

PPVIN_S5_1V5S30V75S0

MCPCORES0_EN

PPVIN_S3_5VS3/PPVIN_S5_3V3S5

PP3V42_G3H_REG

P3V3S0_EN

PPVIN_S0_CPUVTTS0

PPCPUVCORE_VTT_ISNS_R

PPCPUVTT_S0_REG

Q5315

CPUVTT

(1.05V)

P5VS3_EN_L

SMC

SMC_PM_G2_EN

PPVOUT_S0_LCDBKLT

PP3V42_G3H_REG

CPU_RESET#

Q7800

P60

SMC_PM_G2_EN

EN0

EN2

P3V3S5_EN_L

U9700

MC34845

VIN

ADAPTER

PPVIN_S0_MCPCORE

(13A MAX CURRENT)

PPMCPCORE_S0_REG

PPMCPCORE_S0_R

R7525

(13A MAX CURRENT)

(10A MAX CURRENT)

PP5V_S3_REG

CURRENT)

P5V3V3_PGOOD

P1V05S0_LDO_PGOOD

P5V3V3_PGOOD

PLT_RST*

IMVP_VR_ON(P16)

ALL_SYS_PWRGD

PP3V3_S0_FET

PP3V3_S0_PWRCTL

MCPCORESO_PGOOD

CPUVTTS0_PGOOD

P3V3S0_EN

Q7930

PP5VLT_S0_FET

Q7948

U6200

VOUT

P5VS0_EN

PP5VRT_S0_FET

P5VS0_EN

Q7940

PP5V_S3_REG

VIN

EN1

U7750

(Q3841,Q3840)

FETS

1.05V SO

PPVIN_S5_CPU_IMVP

K84 POWER SYSTEM ARCHITECTURE

PPVCORE_S0_CPU_REG

ISL9504BCRZ

PPBUS_G3H

CPUVTTS0_PGOOD

(7.2A MAX CURRENT)

ENABLE

3.425V G3HOT LT3470

U6990

PPCPUVCORE_VTT_ISNS

0.01 OHM

VOUT

PBUS_VSENSE

EN_PSV

PP18V5_DCIN_CONN

SMC RESET "BUTTON"

NCP303LSN

U5000

VOUT

U7000

SLP_S5_L(P95)

LTC2909

PPVBAT_G3H_CHGR_OUT

PM_RSMRST_L

J6950

(9 TO 12.6V)

6A FUSE

PPVBAT_G3H_CHGR_REG

BATT_POS_F

PM_SLP_S4_L

F6905

TPS51117

U7600

PP1V05_ENET_FET

VR_ON

(44A MAX CURRENT)

1.05V (S5)

P3V3S3_EN

Q7910

P1V05ENET_EN

P1V05_S5_EN

3.3V

VOUT

VR_PWRGOOD_DELAY

PP1V05_S5_REG

PGOOD

U7400

U4900

Q7050

(S0)

PGOOD

VIN

VOUT1

VOUT2

Q3810

RC DELAY

VOUT

VOUT1

(RT)

DDRREG_EN

D6905

PP3V3_S5_REG

MCP79

(S5)

99ms DLY

PM_PWRBTN_L

SMC_RESET_L

IMVP_VR_ON

PWRGD(P12)

7A FUSE

CPU_PWRGD

VIN

P3V3_ENET_FET

MCPCORES0_EN

PBUSVSENS_EN

(S0)

DELAY

CHGR_BGATE

FETS

S3 TO S0

PWRBTN*

D6905

3S2P

11-1

RC DELAY

11-3

16-2

16-1

06-1

SMC

SLP_S4_L(P94)

PP1V8_S0_REG

P3V3ENET_EN_L

IMVP_VR_ON

RSMRST_PWRGD

U4900

SLP_S3_L(P93)

S0PGOOD_PWROK

19-1

PP3V3_S0

PP1V05_S0

RSMRST_IN(P13)

RSMRST_OUT(P15)

U7760

CHGR_EN

DELAY

F7000

MCP79

MCPDDR_EN

CPUVTTS0_EN

1.8V LDO

PP1V5_S0

RST*

MCP_CORE

DCIN(16.5V)

U7870

SLP_S5_L

SMC_ONOFF_L

PWR_BUTTON(P90)

RST*

P17(BTN_OUT)

PP1V5_S3_REG

(Q7901 & Q7971)

PP0V75_S0_REG

P3V3S3_EN

15-1

11-2

0.75V

PP1V5_S0_FET

(1A MAX CURRENT)

PLTRST*

VIN

PPVIN_G3H_P3V42G3H

RESET*

CPU

U1000

U1400

PS_PWRGD

LPC_RESET_L

FSB_CPURST_L

CPUPWRGD(GPIO49)

PP3V3_S3_FET

CPU VCORE

VIN

VOUT

PP3V3_S5

MCP_PS_PWRGD

SMC_CPU_VSENSE

R5492

U2850

VOUT

VIN

VREG3

VOUT2

PGOOD1,2

PP1V5_S0

P16

(S5)

SLP_S4_L

CPUVTTS0_EN

PWRGOOD

RSMRST*

4.5V AUDIO

PP4V5_AUDIO_ANALOG

PP5V_S3

(4A MAX

TPS51125

U7200

TPS62202

SLP_S3_L

1.5V

U7300

ISL6263D

U7500

VOUT

ISL8009B

TPS71745

SLP_S3#

PPBUS_S0_LCDBKLT_PWR

DELAY

16-3

16-4

16-6

16-5

16-1

P5VS0_EN

U1400

VIN

BATTERY CHARGER

PBUS SUPPLY/

ENABLES

ISL6258AHRTZ

P5VS3_EN_L

SMC_ADAPTER_EN

AP_PWR_EN

Q3801,Q3805

3 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

Power Block Diagram

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

514-0705 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0689 PART FOR USB CONNECTORS

514-0718 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0694 PART FOR AUDIO CONNECTOR

514-0706 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0691 PART FOR MINI DP CONNECTOR

Module Parts

353S2718 IS NEW INTERSIL PART FOR FIXING B4 DONGLE ISSUE

BOM Groups

DEVELOPMENT BOM

Programmable Parts

Top

SIGNAL

BOTTOM

SIGNAL(High Speed) SIGNAL(High Speed)

Bar Code Labels / EEE #’s

K84 BOARD STACK-UP

8 9

4 5 6 7

GROUND

SIGNAL

POWER

GROUND

POWER

GROUND

SIGNAL(High Speed)

514-0704 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0692 PART FOR RJ45 CONNECTOR

LOCKED BOOTROM APN IS 341S2488

Alternate Parts

BOM Variants

4 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PCBA,MLB,FOX DDR CONN,K84

639-0035

K84_COMMON,CPU_2_0GHZ,FOX_DDR_CONN,EEE_8CG

PCBA,MLB,MLX DDR CONN,K84

K84_COMMON,CPU_2_0GHZ,MLX_DDR_CONN,EEE_A36

639-0254

K84 MLB DEVELOPMENT BOM

K84_DEVEL_ENG

085-0748

PCBA,MLB,FOX DDR CONN,PVT K84

639-0554

K84_COMMON_PVT,CPU_2_0GHZ,FOX_DDR_CONN,EEE_CXR

639-0555

PCBA,MLB,MLX DDR CONN,PVT K84

K84_COMMON_PVT,CPU_2_0GHZ,MLX_DDR_CONN,EEE_CY1

K84_COMMON

COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_ENG,K84_PROGPARTS

K84_DEVEL_PVT

XDP_CONN,LPCPLUS

CRITICAL

U1000

CPU_2_0GHZ

337S3769

PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7550

SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

K84_DEBUG_PROD

K84_DEVEL_ENG

DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN

K84_DEBUG_PVT

DEVEL_BOM_PVT,SMC_DEBUG_YES,XDP,NO_VREFMRGN

K84_DEBUG_ENG

DEVEL_BOM,SMC_DEBUG_YES,XDP

K84_PROGPARTS

BOOTROM_PROG,SMC_PROG,WELLSPRING_PROG

ONEWIRE_PU,DP_ESD,MIKEY,LDO_NO,MEM_SENSE,1P05_HIGH_SIDE_SENSE,MCP_T_DIODE_SENSOR,MCPSMC_DIGITEMP_YES

K84_MISC

K84_MCP

MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC

COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_PROD,K84_PROGPARTS

K84_COMMON_PVT

SYNC_DATE=01/19/2009

SYNC_MASTER=K24_MLB

BOM Configuration

K84 MLB DEVELOPMENT PVT

K84_DEVEL_PVT

085-1076

FOX_DDR_CONN

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA

J3200

CRITICAL516S0706

CONN,204P,SODIMM,P=0.6MM

FOX_DDR_CONN

J3100

CRITICAL516-0201

CONN,RCPT,RJ45,PLASTIC,HF,K83/K84

CRITICAL

J3900

514-0704

514-0706

CONN,RCPT,MDP,20P,PLASTIC,HF,K83/K84

J9400

CRITICAL

R6612,R6617,R6630,R6633

RES,MF,1/4W,6.8OHM,5%,0805,SMD

104S0033 CRITICAL

ZS0912,ZS0913,ZS0914,ZS0915,ZS0919

CRITICAL

POGO PIN,TALL,NOISE-IMPROVED,K84

870-1886

ZS0908,ZS0909,ZS0911

CRITICAL

POGO PIN,MED,NOISE-IMPROVED,K84

870-1885

CRITICAL

514-0718

J6700

CONN,RCPT,S/PDIF,TX,HF,CFR,K83/K84

CRITICAL

SCREW1,SCREW2,SCREW3,SCREW4

452-1708

SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97

CONN,204P,SODIMM,P=0.6MM,HF

J3100

MLX_DDR_CONN

CRITICAL516-0213

138S0602138S0603

ALL

MURATA AS ALTERNATE

128S0218128S0093

KEMET AS ALTERNATE

ALL

152S0516

ALL

MAGLAYERS AS ALTERNATE

152S0874

341S2485

SMC_PROGCRITICAL

U4900

IC,SMC,K84

338S0563

U4900

CRITICAL

SMC_BLANK

IC,SMC,HS8/2117,9X9MM,TLP,HF

CRITICAL

085-1076

K84 MLB DEVELOPMENT PVT

DEVEL_PVT

DEVEL_BOM_PVT

CRITICAL

U6100

BOOTROM_PROG

341S2487

IC,PRGRM,EFI BOOTROM,UNLOCK,K84

IC,WELLSPRING CONTROLLER,K84

U5701

WELLSPRING_PROG

341S2491 CRITICAL

CRITICAL

WELLSPRING_BLANK

U5701

337S2983

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

K84 MLB DEVELOPMENT BOM

DEVEL

085-0748

DEVEL_BOM

CRITICAL

POGO PIN,TALL,NOISE-IMPROVED,K84

870-1886

ZS0904,ZS0905,ZS0906,ZS0907,ZS0910

CRITICAL

POGO PIN,MED,NOISE-IMPROVED,K84

870-1885

ZS0900,ZS0901,ZS0902,ZS0903

CRITICAL

U7870

IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8

353S2718

CRITICAL

514-0705

J4600,J4610

CONN,RCPT,USB,4P,PLASTIC,HF,K83/K84

CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC

CRITICAL

J3200

MLX_DDR_CONN

516S0790

152S0778152S0693

DALE/VISHAY, MAGLAYERS AS ALTERNATE

ALL

152S0586

MAGLAYERS AS ALTERNATE

ALL

152S0847

EEE_CY1

[EEE:CY1]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEE_CXR

[EEE:CXR]

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEE:A36]

EEE_A36

157S0055157S0058

ALL

DELTA AS ALTERNATE

152S0685

ALL

CYNTEC AS ALTERNATE

152S0796

826-4393

EEE_8CG

[EEE:8CG]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

BOOTROM_BLANK

U6100

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

335S0610

IC,GMCP,MCP79,35X35MM,BGA1437,B03

CRITICAL

MCP_B03

U1400

338S0710

CRITICAL

POGO PIN,THIN,NOISE-IMPROVED,K84

870-1887

ZS0917,ZS0918,ZS0916

DALE/VISHAY AS ALTERNATE

ALL

104S0023104S0018

518S0774

CONN,RCPT,60P,P=0.4,STK HT 1.0

XDP_CONN

J1300

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

4/2/2009: RELEASE 9.2.0 (MAJOR):

- PAGE 97:DISCONNECTED PINS 2 AND 5 FROM GND PINS(13,19,21)AND CONNECTED SEPARATELY TO

- PAGE 97: RENAMED SINGLE PIN NET GND_LCDBKLT TO GND_LCDBKLT_PGND

- PAGE 49: FIXED PLACEMENT NOTE ASSOCIATED WITH C4907 (SHOULD BE: PLACE NEAR PIN E1)

- PAGE 7: SCRUBBED TPS AS PER UPDATE FROM TOM

- PAGE 4: CHANGED MCP P/N TO 338S0702 AS PER CHALLEE

- PAGE 90: ADDED C9017 (1000PF) CAP AS PER JOHN SCHEN

GND_LCDBKLT_PGND AND ASSIGNED MIN_LINE/NECK_WIDTH ATTRIBUTES

- PAGE 97: REPLACED D9710 WITH 40V PART- APN 371S0580 AS PER DEREK

- PAGE 97: STUFFED R9726 AND SWAPPED C9705 AND R9705 AS PER FREESCALE FOR COMPENSATION.

- ADDED BOMOPTION = NOSTUFF ATTRIBUTE TO R6725

C6871, U6870, C6872, R6872, & R6873

- PAGE 74: CHANGE L7400 AND L7401 TO 152S1019 AS PER DAYU FOR COST SAVING. ALSO, UPDATED ASSOCIATED TEXTS

- PAGE 94: REPLACED C9486 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY)

- PAGE 74: REMOVED C7400, C7402, R7451 AND R7452 AS PER DAYU

- PAGE 70: REPLACED R7080 WITH APN 107S0142 WHICH IS TRUE 4-TERMINAL SENSE RESISTOR WITH SMALLER PACKAGE

3. PAGES 31, 32: REPLACED 0.1UF 0204 TYPE DDR3 DECOUPLING CAPS WITH 0402 TYPE CAPS ( APPLE P/N : 132S1059)

- UPDATED THE SCHEMATICS, PCBF AND PCBA PART NUMBER INFO

- DELETED IR SPECIFIC NETS ON SATA CONNECTOR

- CORRECTD BOM CONFIG TABLES

1/23/2009: RELEASE 0.0.5-

1. PAGE 75: MCP VCORE INDUCTOR CHECK FOR PD: CHANGED L7560 TO 152S0966 AND THEN TO 152S0867. BUT NOW IT IS BACK TO 13A PART FOR NOW

15: PAGE 97: REPLACED BKLT DRIVER CKT WITH THAT OF FREESCALE PART, SIMILAR TO K19I

- PAGE 9: DELETED R0950 PCIE_FW_PRSNT_L ’S PD RESISTOR

- PAGE 54: REMOVED BMON CURRENT SENSE CIRCUIT

- UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_PROD AND BLANK PROGRAMMED PARTS. ALSO, DELETED BMON_ENG BOM OPTION

- DELETED KB BACKLIGHT DRIVER/DETECTION CKT

AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_NO WITH THESE 0 OHMS

- PAGE 50: ADDED UNUSED NET ALIAS FOR SMC_BIL_BUTTON_L (NC_SMC_BIL_BUTTON_L)

- PAGE 70: ADDED TP TO PIN 13

- REMOVED BOMOPTION = NOSTUFF ATTRIBUTE FROM R6724

- PAGE 39: REPLACED ETHERNET CONNECTOR WITH THAT OF M97A/K24 PART APN 514-0636 (SYNC’ED WITH K24)

- PAGE 60: CORRECTED PLACEMENT NOTE ASSOCIATED TO XW6080 TO REFLECT D9710 INSTEAD OF D9701

- PAGE 57: ADDED PLACEMENT NOTES TO C5702 AND C5704 AS PER JOHN SCHEN’S FEEDBACK SEL1 SIGNAL AND REMOVED 10K PD ON ST PIN. REPLACED C5926 WITH 0.01UF CAP AS PER DATA SHEET. AND,

- PAGE 4: ADDED 138S0603 AS ALT FOR 138S0602B FOR SUPPLY REDUNDANCY

- PAGE 76: REPLACED L7620 WITH ITS REPLACEMENT - APN 152S0518

- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 & C7240 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS

- PAGE 9: CHANGED ALIAS OF FW_PME_L TO TP_FW_PME_L

USB_IR_N/P

- PAGE 31 & 32: PIN SWAPS ON THE DDR3 CONNECTOR PAGES FOR ROUTING PURPOSES (REFER TO RON’S EMAIL)

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.0.0***

- PAGE 73: ADDED SHORT XW7304 FROM PIN 1 OF C7300 TO POWER GND (PIN 18)

- ADDED PLACEMENT NOTES TO XW SHORTS AS PER DAYU

13. PAGE 69: REPLACED BATTERY CONNECTER WITH PN 518S0540 AND BIL CONNECTOR WITH PN 518S0588. UPDATED CONNECTIONS ACCORDINGLY

6. PAGE 45: REPLACED SATA HDD CONNECTOR WITH APPLE PN 516S0350 AND UPDATED CONNECTIONS ACCORDINGLY

- NO CHANGES SINCE LAST MINOR RELEASE 0.0.2

- PAGE 70: DELETED R7050 CONNECTION BETWEEN CHGR_AGATE AND CHGR_LOWCURRENT_GATE

-PG. 67, NO STUFFED R6724

-PG. 67, DELETED L6706

-PG. 67 ADDED =PP3V3_S3_AUDIO NET

(MATCHES UPDATED ALIASES ON PAGE 8)

- PAGE 9: ADDED OMIT ATTRIBUTE TO THE LVDS HOLE

- PAGE 8: ADDED =PP5V_S3_P5VRTS0FET ALIAS, GOING TO 5V RT S0 FET CIRCUIT

- DELETED PAGES 41,42,43,48,97,98,105 [FIREWIRE, IR CONTROLLER, BACKLIGHT CKT]

INITIAL RELEASE 0.0.1-

- SET SOURCE SYNC OF AUDIO PAGES (62-63, 65-68) FROM LENG’S AUDIO PAGES

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

- PAGE 97: ADDED BOM OPTION - NOSTUFF- TO R9702 AS PER K19I

2/26/2009: RELEASE 4.0.0 (RFA RELEASE):

- PAGE 78: DELETING P5VLTS3_EN RC CIRCUIT AS IT IS NO LONGER NEEDED (SEE ABOVE). ALSO UPDATED

- NAME CHANGED TO TMLB. SO CALLING IT RELEASE 0.0.1

- PAGE 51: R5156, R5157 AND R5158 ARE NOW 0 OHM ISOLATION RESISTORS PLACED ON SPI BUS NEXT TO THE LOCATION WHERE

- PAGE 34: R3453 IS MODIFIED TO 110K RESISTOR, R3454 IS NOSTUFF AND R3453 IS PULLED UP TO PP3V3_WLAN_F.

- PAGE 9: ADDED UNUSED FIREWIRE LANE NETS AS TEST POINTS

- PAGE 4: UPDATED EEE NUMBER - 8CG

- PAGE 9: ADDED SMC_SYS_KBDLED TP ALIAS

- PAGE 8: DIVIDED PP5V_S3_REG INTO TWO BRANCHES - PP5VRT_S3_REG & PP5VLT_S3_REG

- PAGE 8: ADDED PP5V_S3_DEBUG_ADC_AVDD/DVDD & PP5V_S3_DEBUG_ISNS ALIASES FOR NEW SENSOR PAGE 60

- PAGE 28: REMOVED RTC POWER SOURCES CIRCUIT AND SUPERCAP_NO BOM OPTION FROM R2820

- PAGE 34: SINCE X16 AIRPORT CARD SOLUTION IS BEING USED, PP5V_S3_WLAN IS REPLACED BY PP3V3_S3_WLAN

- PAGE 34: DISCONNECTED PP5V_S3_BTCAMERA_F POWER RAIL FROM THE CONNECTOR AND REPLACED IT WITH PP3V3_S3_BT ALONG WITH THE USB CAMERA SIGNALS TO LVDS PAGE. ALSO, RENAMED THIS POWER RAIL TO PP5V_S3_CAMERA ON LVDS

- PAGE 34: REPLACED L3404 WLAN INDUCTOR WITH LOW DCR 0603 PART - APN 155S0367

- PAGE 45: CHANGED SATA HDD CONNECTOR TO APN 516S0616

- PAGE 45: ADDED SENSE RESISTORS R4598 AND R4599 ON 5V ODD AND 5V HDD RAILS RESPECTIVELY

- PAGE 39: REPLACED ETHERNET CONNECTOR WITH APN 514-0668 (SIMILAR TO K36B)

- PAGE 34: ADDED SENSE RESISTOR R3452 ON PP3V3_WLAN SIGNAL

(SIMILAR TO M96). CAMERA SIGNALS ARE ROUTED VIA LVDS CONNECTOR. MOVED PP5V_S3_BTCAMERA POWER CIRCUIT

THIS IS TO ENSURE 3.3V LEVEL AT THE INPUT OF U3402 AND MAINTAIN 100MS DELAY SPEC BETWEEN 3.3V POWER

(GOING TO Q3450). ALSO, REPLACED PP5V_WLAN WITH PP3V3_WLAN ON PAGE 6 (FUNCTIONAL TEST POINTS)

- PAGE 8: ADDED ALIAS PP5VLT_S3_V5IN UNDER PP5VRT_S3_REG

- PAGE 8: ADDED ALIAS PPVIN_S3_5VLTS3 UNDER PPBUSB

- PAGE 50: UNSTUFFED R5055 AND USED SMC_NB_MISC_ISENSE SIGNAL PORT (SMC) FOR CONNECTING PPBUSA ISENSE SIGNAL.

- PAGE 51: REPLACED TWO DEMUX SOLUTION WITH A SINGLE DEMUX 1X2 SOLUTION. APN USED - 353S2220

- PAGE 52: ADDED SENSOR ADC CONNECTION BLOCK UNDER ’SMC 0 SMBUS CONNECTIONS’ SECTION

- PAGE 70: ADDED BYPASS 0 OHM RESISTOR R7050 (NOSTUFF FOR NOW) OPTION FOR NEW CHIP WHICH WON’T REQUIRE U7060 SOLUTION

- PAGE 4: REMOVED 104S0018 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE

- PAGE 8: RENAMED PPVIN_S5_1V5S3_0V75S0 TO PPVIN_S5_1V5S30V75S0

- PAGE 8: DELETED PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_BKL_VDDIO, PP3V3_S0_MCP_PLL_VLDO

- PAGE 78: ADDED P5V_LTS3_PGOOD POWER GOOD SIGNAL (WIRED AND WITH OTHER S0 RAILS PGOOD) CORRESPONDING TO 5V LT

IT BRANCHES INTO TWO - ONE GOING TO MLB SPI ROM AND THE OTHER GOING TO LPC CONNECTOR. THESE RESISTORS ARE

- PAGE 4: REMOVED 152S0778 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE SINCE L7260 AS HAS BEEN REPLACED WITH THIS PART

- PAGE 54: MOVED PBUS INA210 CIRCUIT TO THIS CURRENT SENSOR PAGE. RENAMED REF DES AS PER THIS PAGE 54

- PAGE 55: DELETED J5590 CONNECTOR (CONNECTED TO HEAT-PIPE TEMPERATURE DETECTION RAILS)

- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 WITH 68UF OSCON CAP (APN 128S0275) & C7240 WITH 39UF (APN 128S0248)

- PAGE 55: REPLACED U5515 & U5535 WITH CHEAPER APN 353S2571

- PAGE 78: RENAMED P5VS3_EN_L TO P5VRTS3_EN_L (RT POWER SUPPLY ENABLE) AND ADDED R7814, C7814 S3 ENABLE CIRCUIT

- PAGE 75: CHANGED C7571 & C7560 TO 68UF OSCON CAPS (APN 128S0275)

- PAGE 77: REMOVED 1.05V S0 PLL LDO CIRCUIT. AND, REMOVED LDO_NO BOM OPTION FROM R7745

- PAGE 72: REPLACE Q7220 WITH SIZ700DT AND L7260 WITH SMALLER 10A PART (APN 152S0778)

- PAGE 71: CHANGED C7160 TO 39UF OSCON CAP (APN 128S0248)

- PAGE 69: REPLACED BATTERY CONNECTOR J6950 WITH APN 518S0540 (M96) CONNECTOR

- PAGE 69: ADDED D6951 ESD DIODE ON BIL SMBUS SIGNALS (NOSTUFF FOR NOW)

- PAGE 61: RENAMED SPI SIGNALS TO MATCH WITH CHANGES ON PAGE 51

PLACED ON THE LPC CONNECTOR BRANCH. THIS IS TO AVOID STUBS IN PRODUCTION

TO THE CARD GETTING STABLE AND AIRPORT GETTING OUT OF RESET

2. ADAPT JACK INSERT DETECT CIRCUIT TO CD3282 JACK INSERT DETECT FUNCTION.

5. PAGE 34: REPLACED SCHMITT’S TRIGGER WITH PN 311S0449

- PAGE 73: ADDED SENSE RESISTOR R7350 ON 1.5V DDR3 SUPPLY RAIL

- PAGE 69: ADDED BOM OPTION NOSTUFF TO D6950 FOR NOW

8. PAGE 46: REPLACED ESD DIODES WITH CHEAPER PN 377S0066

7. PAGE 45: ADDED 2 PIN CONNECTOR (APPLE PN 518S0519) FOR SIL

- PAGE 60: REMOVED WELLSPRING 3 PAGE (GOING BACK TO K24 SOLUTION) AND REPLACED IT WITH K19I DEBUG SENSOR PAGE (SCHUTIL SYNC)

- PAGE 73: UPDATED 1.5V/0.75V POWER SUPPLY WITH CORRECT NET NAMES REFLECTING 1.5V/0.75V INSTEAD OF 1.8V/0.9V AND

- PAGE 8: ADDED PP3V3_S3_BT ALIAS FOR BLUETOOTH ON RIGHT CLUTCH CONNECTOR PAGE

5V S3 IS DIVIDED INTO RT AND LT POWER SUPPLY AND WILL HAVE CORRESPONDING S0 FETS)

- PAGE 8: DIVIDED PP5V_S0_FET INTO TWO BRANCHES - PP5VRT_S0_FET & PP5VLT_S0_FET (FOR ROUTING PURPOSE,

- PAGE 4: CORRECTED APN FOR PROGRAMMED PARTS - SMC, BOOT ROM, WELLSPRING

- PAGE 4: REMOVED SUPERCAP_NO BOM OPTION. ADDED DEBUG_ADC BOM OPTION UNDER K84_DEVEL_ENG

***PAGES SYNC’ED FROM K24 SINCE LAST RELEASE 1.0.0***

3. REMOVED JACK EXTRACT CIRCUITRY, FUNCTION IS TAKEN OVER BY CD3282

- PAGE 34: ADDED CHOKES ON PCIE TX/RX SIGNALS. UPDATED PAGE 6 (FUNCTIONAL TEST POINTS) ACCORDINGLY

- PAGE 71: ADDED NEW PAGE FOR PP5V_LT_REG POWER SUPPLY. UPDATED ALL THE REF DES AS PER THE PAGE NUMBER

- PAGE 60: UPDATED WLAN DIVIDER CIRCUIT WITH 3V3 POWER RAIL INSTEAD OF 5V

[ONLY CHIP SELECT IS BEING DEMUXED]

ADDED ALIAS ON THIS PAGE

PAGE

- PAGE 76: REPLACE Q7620 WITH SIZ700DT

1. REPLACED MIKEY CD3272 WITH CD3282

(THIS IS FOR NEW SENSOR PAGE 60)

- PAGE 4: REMOVED LDO_YES BOM OPTION

4. REMOVE FM ANTENNA NET.

2. ADDED DIDT TO ALL THE GATE AND PHASE NETS

- ADDED DIDT ATTRIBUTE

- PAGE 28: DELETED FW_RESET_L SIGNAL

- PAGE 58: DELETED KB BKLT CIRCUIT

IN SYNC WITH PAGE 8 ALIASES

- PG 50: SWAPPED THE PART NUMBER AND THE ALTERNATE PART NUMBER FOR VR5020. MADE ISL60002 THE ALTERNATE PART

***PAGES SYNCED FROM K24 SINCE LAST RELEASE 2.0.0***

- CHANGED SPEAKER AMPS TO LM48310, PLACEHOLDERS FOR LM48311. LM48311 IS THE CSP VERSION OF THE LM48310.

***PAGES SYNCED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 2.0.0***

- REMOVED OPTIONAL STUFFING RESISTORS AROUND THE RE-TASKING JACK ANALOG SWITCH.

- CHANGED LDO TO B LP5900.

- PAGE 75: CHANGED R7525 TO 107S0132 FOR COST SAVING AS PER DAYU

- PAGE 74: CHANGED Q7401 AND Q7403 TO 376S0771 AS PER DAYU

- PAGE 74: CHANGED Q7400 AND Q7402 TO 376S0772 AS PER DAYU

- PAGE 74: REMOVED UNUSED NETWORK ON U7400 PIN 5 AND PIN 6 AS PER DAYU [R7406, C7410, R7427, R7426]

- PAGE 73: MOVED THE SENSE RESISTOR NEXT TO INDUCTOR

- PAGE 73: ADDED ONE MORE OSCON 39UF CAP ON INPUT SIDE

- PAGE 72: L7220 CHANGED TO 152S0778 FOR COST SAVING AS PER DAYU

- PAGE 71: DISCONNECTING EN_PSV (PIN 34) FROM P5VLTS3_EN SIGNAL AND CONNECTING IT TO

- PAGE 70: CHANGED Q7000 AND Q7001 CHEAPER TO 376S0667 (HAT1128) AS PER DAYU’S RECOMMENDATION

- PAGE 70: CHANGED Q7050 TO 376S0761 AS PER DAYU & K24 DESIGN

- PAGE 69: DELETED NOTE REGARDING INDUCTOR FILTER REQUIREMENT ON BATT_POS_F (AS PER JOHN SCHEN)

- PAGE 69: REPLACED BATTERY CONNECTOR WITH THAT OF K24 (APN 518-0359)

- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH THAT OF K24 (APN 518S0637) - SYNC’ED FROM K24

- PAGE 34: ADDED A TEXT NOTE THAT J3401 (AIRPORT CONNECTOR) COULD CHANGE TO 1.8MM HEIGHT APN 516S0582

- PAGE 90: REFRESHED THE SYMBOL OF U9000, PART NUMBER CHANGED TO 353S2603

- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH APN 518S0738

POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET

- PAGE 34: ADDED NOTE WITH REGARD TO 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN

- PAGE 34: ADDED NOTE WITH REGARD TO SMBUS CONNECTIONS TO THE AIRPORT CONNECTOR

- PAGE 13: REPLACED XDP CONNECTOR WITH MINI XDP CONNECTOR APN 516S0625

- PAGE 8: ADDED BACK - PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_MCP_PLL_VLDO

- PAGE 8: RENAMED PP1V05_S0_MCP_PLL_UF BACK TO PP1V05_S0_MCP_PLL_UF_R

- PAGE 74: STUFF R7413 AS PER DAYU

PP5VLT_S3_V5IN (5VRT PS)

- PAGE 4: ADDED LDO_NO BOM OPTION

- PAGE 54: REMOVED NOTE ON AMON AND BMON

- PAGE 77: ADDED BACK - 1.05 PLL LDO CIRCUIT

1/21/2009: RELEASE 0.0.4-

2/6/2009: MAJOR RELEASE 0.1.0 -

2/6/2009: WEEKLY RFA BOM RELEASE 1.0.0-

2/15/2009: RELEASE 2.0.0 (WEEKLY RFA)-

2/25/09: WEEKLY RFA RELEASE (3.0.0)

3/4/2009: RELEASE 5.0.0 (RFA)-

ASSOCIATED TEXT NOTE

- PAGE 97: FIXED CONNECTION POINT (DOT) FOR LCDBKLT_VIN

- PAGE 97: ADDED 0 OHMS SERIES RESISTOR ON LCD_BKLT_PWM FOR DEBUGGING PURPOSES

- PAGE 97: RENAMED LCD_BKLT_PWM TO LVDS_IG_BKL_PWM

- PAGE 97: CHANGED VOVP VALUE TO 6.9V AS PER FREESCALE FEEDBACK

- PAGE 97: ADDED R9726 (22K) AND SWAPPED C9705 AND R9705 LOCATIONS FOR NOISE REDUCTION

- PAGE 97: DELETED C9712 AS IT IS REDUNDANT

- PAGE 97: ADDED PLACEMENT NOTE ATTRIBUTE TO C9713 AND C9710 FOR PLACING THOSE NEAR L9710

- PAGE 78: ADDED 0 OHM ISOLATION RESISTORS ON POWER GOOD SIGNALS (BEFORE WIRED AND)

- PAGE 8: DELETED PP5V_S0_BKL, RENAMED PP1V05_S0_MCP_PLL_UF_R TO PP1V05_S0_MCP_PLL_UF

- PAGE 90: UPDATED LVDS CONNECTOR CONNECTIONS AS PER STEVE’S RECOMMENDATION. ADDED CAMERA SIGNALS

- PAGE 79: ADDED 5V LT S0 FET AND UPDATED NET NAMES FOR BOTH RT AND LT S0 FET CIRCUITS ACCORDINGLY

POWER SUPPLY

FOR GENERATING P5VLTS3_EN ENABLE SIGNAL FOR LT POWER SUPPLY

AS PER FREESCALE RECOMMENDATION

***PAGES SYNC’ED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 1.0.0***

17. PAGE 4: REMOVED BKLT_ENG BOM OPTION

16. PAGE 69: MOVED THE DECAP C6908 TO CORRECT PART U6901.5 ( SIMILAR TO K24)

- PAGE 45: CHANGED J4501 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

- PAGE 50: DELETED SMC_PPBUSA_ISENSE ALIAS AND STUFFED R5055

- PAGE 54: DELETED U5470 INA210 CIRCUIT AS THERE IS NO NEED

R7051 (6259_YES) CONNECTION BETWEEN CHGR_PIN26 AND CHGR_LOWCURRENT_GATE;

R7054 (6259_NO) CONNECTION BETWEEN CHGR_PIN6 AND GND_CHGR_SGND

- PAGE 73: RENAMED TEXT NOTE FOR =PP1V5_S3_REG NET TO VOLTAGE=1.5V

- PAGE 45: MIRROR’ED J4500 AND RECONNECTED PINS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

R7052 (6259_NO) CONNECTION BETWEEN CHGR_PIN26 AND GND_CHGR_SGND; R7053 (6259_YES) CONNECTION BETWEEN CHGR_PIN6 AND PIN 12 (VHST);

TO HAVE TWO PPBUS BRANCHES

- PAGE 97: STUFF R9716 AS PER KIRAN’S FEEDBACK

-PG. 68, ADDED R6873

-PG. 67, DELETED R6726

3/20/2009: RELEASE 7.1.0 (MAJOR)-

- PAGE 9: ADDED LVDS HOLE APN 998-1521

- PAGE 70: AS PER DAYU, ADDED:

- PAGE 4: CHANGE THE CPU TO NEW APNB 337S3704

3/24/2009: RELEASE 7.2.0 (MAJOR)-

AS PER DAYU

- PAGE 7: RENAMED PP5VRT_S3 TO PP5V_S3 ["LT" & "RT" NOMENCLATURE CLEAN-UP]

- DELETED PAGE 71 (5V S3 LT POWER SUPPLY) AS THERE IS NO NEED OF A SEPARATE 5V S3/S0 SUPPLY

- PAGE 8: COMBINED 5V S3 LT AND RT ALIASES INTO ONE =PP5V_S3_REG AND RENAMED NETS

- PAGE 21: UNSTUFFED R2143 PU ON MCP_GPIO_4 AS THERE IS ALREADY A 100K PU ON AUDIO PAGE

- PAGE 55: ADDED BC846BM NPN TRANSISTOR (APN 372S0129) TO MCP T-DIODE SENSOR CIRCUIT SIMILAR TO

- PAGE 9: ADDED ALIAS MCP_GPIO_4 FOR MIKEY MIC LOAD DETECT CIRCUIT

- PAGE 72: RENAMED NETS AND NOTES TO REMOVE REFERENCES TO RT POWER SUPPLY

- PAGE 72: ADDED C7282 APN 128S0218 IN PARALLEL WITH C7280 AS PER DAYU

- PAGE 73: REPLACED Q7320 AND Q7321 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 75: REPLACED C7576 WITH 0.022UF APN 132S0102 CAP TO INCREASE THE SLEW RATE

- PAGE 76: CORRECTED MAX OUTPUT NOTE TO REFLECT 7.2A INSTEAD OF 8A

- PAGE 75: REPLACED Q7560 AND Q7565 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 76: REPLACED Q7620 WITH 2 CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 78: ROUTED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL TO THE WIRED AND CIRCUIT

- PAGE 60: REPLACED DUAL PACKAGE OPA330 OPAMPS WITH SINGLE PACKAGE ONES - APN 353S2179

- PAGE 9: DELETED EXTRA MEDIUM POGO PIN ZS0912 AND SCREW HOLES Z0908, Z0909

- PAGE 74: REPLACED C7433 AND C7431 WITH 0.001UF CAPS APN 132S1035

- PAGE 77: ADDED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL VIA A 0 OHM RESISTOR TO PIN 3 (PG) OF THE LDO

- PAGE 78: DELETED P5V_LTS3_PGOOD AS THERE IS NO 5V LT POWER SUPPLY ANYMORE

[U6030, U6031, U6040, U6041]. ALSO, ADDED C6031 & C6041

- PAGE 7: DELETED PP5VLT_S3 NETS

- PAGE 8: DELETED =PPVIN_S3_5VLTS3, =PP5VLT_S3_V5IN NETS

3/25/2009: RELEASE 7.3.0 (MAJOR)-

(LT & RT NOMENCLATURE CLEAN-UP)

- PAGE 45: ADDED APN TEXT NOTE FOR SIL CONNECTOR

- PAGE 75: ADDED A NOTE OCP=14.5A TO R7575

3/26/2009: RELEASE 7.4.0 (MAJOR)-

- PAGE 72: REPLACED L7260 WITH APN 152S0959 AS PER DAYU

THAT IN CPU T-DIODE SENSOR AND STUFFED C5540

3/26/2009: RELEASE 7.5.0 (MAJOR)-

- PAGE 78: RENAMED =P5VRTS3_EN_L TO =P5VS3_EN_L

- PAGE 7: DELETED PP5V_S0, PP5V_S3 AND ADDED PP5VRT_S0,PP5VLT_S0, PP5VRT_S3, PP5VLT_S3 DEBUG

- PAGE 4: DELETING ENTRIES FOR 107S0138 AND 107S0139 FROM ALTERNATES PARTS TABLE AS THEY WOULD BE REPLACING

- PAGE 97: FOR 25KHZ OPERATION, CHANGE R9726 TO NO STUFF, INTERCHANGE R9705(6.8K) WITH C9705

- PAGE 25: CHANGED C2500,C2501,C2502,C2503,C2515,C2520,C2528,C2540,C2580,C2582,C2584,C2586,C2588,

- PAGE 74: ADDED PLACEMENT NOTES TO C7419,C7422 AND C7423 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 72: CONNECTED SMC_PM_G2_EN SIGNAL TO EN0 PIN 13 OF U7200 VIA A 100K RESISTOR FOR KEEPING THE POWER SUPPLY

- PAGE 73: MOVED C7344 NEXT TO R7350 AND ADDED PLACEMENT NOTE (JOHN SCHEN WANTED IT TO BE NEXT TO L7320

- PAGE 97: CHANGED C9711 FROM 0.1UF TO 1.0UF 0603 TYPE CAP AS PER FREESCALE FEEDBACK

- PAGE 97: CHANGED C9715 AND C9716 TO 50V CAPS FOR COST SAVING AND AS PER FREESCALE FEEDBACK

- PAGE 97: CHANGED R9710 TO 6.65K APN 114S0298 AND R9716 TO 226K APN 114S0445 PARTS AS PER

- PAGE 107: REMOVED FOLLOWING SENSOR NETS CONSTRAINTS: ISNS_P1V5S0MCP_P/ISNS_P1V5S0MCP_N;

- PAGE 9: REPLACED 5 SHORT POGO PINS WITH MEDIUM ONES AND ADDED THREE EXTRA MEDIUM ONES (TOTAL MEDIUM

-PG. 67, CONNECTED HP OUTPUTS TO NC OF U6700 AND LINE INPUTS TO NO OF U6700.

- PAGE 90: ADDED EMI CAPS (C9017-C9025) ON I2C, LED_RETURNS AND LCD_BKLT POWER RAILS GOING TO LVDS.

- PAGE 73: REPLACED C7307,C7308 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY)

- PAGE 70: ADDED BOM OPTION 6259_YES TO R7050 AND 6259_NO TO U7060 AND AMON PULLDOWN LOGIC

- PAGE 70: MOVED C7028 TO PPVBAT_G3H_CHGR_REG AS PER JOHN SCHEN’S FEEDBACK

REPLACED C5923-C5925 CAPS WITH 0.033 UF VALUES FOR CUT-OFF FREQUENCY OF ~146HZ

- PAGE 45: RENAMED =PP5V_S0_HDD_R TO PP5V_S0_HDD_R (AS PER UNALIASED.LST REPORT)

- PAGE 34: REPLACED THE AIRPORT CONNECTOR WITH 1.8 MM HEIGHT CONNECTOR APN 516S0582

- PAGE 52: REMOVED REFERENCES TO THE LED BACKLIGHT AS FREESCALE PART DOESN’T HAVE I2C BUS ACCESS

- PAGE 79: REPLACE Q7940 AND Q7948 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

- PAGE 90: REMOVED EMI CAPS [C9017-C9025] ON LED_RETURN, I2C AND LCD_BKLT POWER NETS

- PAGE 90: UPDATED LVDS CONNECTOR PINOUT CONNECTIONS AS PER STEVE’S NEW SPREADSHEET

- PAGE 97: CHANGED R9717 - R9722 FROM 0.1% TO 1% PARTS FOR COST SAVINGS AND AS PER FREESCALE FEEDBACK

- PAGE 107: ADDED CONSTRAINTS FOR FOLLOWING SENSOR NETS: ISNS_HDD_P/ISNS_HDD_N; ISNS_ODD_P/ISNS_ODD_N;

3/6/2009: RELEASE 6.0.0 (RFA:)-

- PAGE 74: STUFFED C7432 AS PER DAYU

OFF IN CASE IF SMC TURNS OFF

- PAGE 4: ADDED DALE/VISHAY ALTERNATES FOR 104S0023 --> 104S0018

- PAGE 73: DELETED NOTES AT THE BOTTOM RIGHT AFTER CONSULTING WITH DAYU

- PAGE 4: ADDED BOM OPTION 6259_NO TO THE TABLE UNDER K84_MISC BOM GROUP

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 5.0.0***

-PG. 67, CHANGED U6700 CB INPUT TO BE CONTROLLED BY CS4206 GPIO0.

- PAGE 75: ADDED PLACEMENT NOTE TO C7563 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 52: DELETED TERM BIL FROM SMC BATTERY & BIL CONNECTIONS

- PAGE 9: ADDED TP ALIASES TO IMVP6_VR_TT AND IMVP6_NTC

- PAGE 8: DELETED =PP3V42_G3H_5V3V3_EN AS IT IS NO LONGER USED

- PAGE 8: DELETED =PP3V3_S0_TPAD AS THERE IS NO KEYBOARD BACKLIGHT DRIVER

- PAGE 8: DELETED =PP3V42_G3H_AUDIO AS IT IS NO LONGER USED

- PAGE 4: ADDED 152S0693 AS ALT FOR 152S0778 FOR SUPPLY REDUNDANCY

-PG. 62, CHANGED TP_AUD_GPIO_0 TO AUD_GPIO_0.

- PAGE 72: REMOVED NOSTUFF’ED C7251 AS PER DAYU

- PAGE 69: CHANGED L6995 TOB APN 152S1017 FOR COT SAVING AND EFFICIENCY

- PAGE 70: ADDED PLACEMENT NOTE TO C7027 AS PER JOHN SCHEN’S FEEDBACK

CIRCUIT COMPONENTS. TURNED ON 6259_NO, FOR NOW, ON PAGE 4 TABLE

- PAGE 72: ADDED PLACEMENT NOTE TO C7230 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 73: ADDED PLACEMENT NOTE TO C7333 AS PER JOHN SCHEN’S FEEDBACK

DAYU PERFERRED IT TO BE AFTER THE SENSE RESISTOR

- PAGE 75: MOVED C7569 TO PPMCPCORE_S0_R AS PER JOHN SCHEN’S FEEDBACK

-PG.66, REPLACED THE LM48310’S (U6610/20/30) WITH LM48311’S

ADDED PLACEMENT NOTES TOO

(DAYU’S RECOMMENDATION)

ISNS_PVCORES0MCP_P/ISNS_PVCORES0MCP_N

-PG. 67, CHANGEED J6703 TO TWO PIN CONN.

-PG. 67, DELETED C6760/1/2/3.

-PG. 66, CHANGED C6630/31 TO 0.022UF

-PG. 66, CHANGED C6610/11 TO 0.022UF

-PG. 66, ADDED R6613/14/15/16/17

ISNS_LCDBKLT_P/ ISNS_LCDBKLT_N

POGO PINS = 8) AS PER NEW MCO

3/17/2009: RELEASE 7.0.0 (RFA)-

- PAGE 74: ADDED XW7401-XW7404 SHORTS ACROSS L7400 AND L7401 ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 6.0.0***

-PG. 67, DELETED R6725 AND NET =PP3V42G3H_AUDIO

-PG. 62, ADDED PLACEMENT COMMENT ATTR. TO XW6200/1

-PG. 67, ADDED PLACEMENT COMMENT ATTR. TO XW6700/1/10/11

-PG. 68, ADDED PLACEMENT COMMENT ATTR. TO XW6851/80

-PG. 66, REPLACED U6610/30 WITH LM48556 CKTS

-PG. 62, REPLACED C6225 WITH APN: 128S0216

- PAGE 9: REMOVING 2 EXTRA TALL POGO PINS (ZS0911, ZS0912) AS PER NEW MCO

- PAGE 45: REPLACE Q4590 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

- PAGE 59: REMOVING R5923 AND ONLY 1 PU ON SEL LINES IS ENOUGH

- PAGE 70: REPLACING R7020 WITH APN 107S0138 PART FOR COST SAVING

- PAGE 70: REPLACING R7008 WITH APN 107S0139 PART FOR COST SAVING

- PAGE 70: R7080 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER

- PAGE 73: R7350 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER

ISNS_AIRPORT_P/ISNS_AIRPORT_N; ISNS_1V5_S3_P/ISNS_1V5_S3_N;

- PAGE 77: CHANGED U7740 TO 500MA 1.05V LDO

- PAGE 7: RENAMED PP5V_S3_BTCAMERA_F WITH PP3V3_S3_BT_F

- PAGE 8: DELETED ALIAS =PP1V05_S0_SMC_LS AS IT IS NO LONGER NEEDED

- PAGE 52: DELETE J6955 REFERENCE AS THERE IS NO BIL CONNECTOR

- PAGE 54: REPLACING R5492 WITH APN 107S0139 PART FOR COST SAVING

- PAGE 97: ADDED DIDIT=TRUE ATTRIBUTE TO THE SWITCHING NODE PINS 3 & 4

- PAGE 97: NO STUFF’ED C9721 - C9726 AS PER FREESCALE FEEDBACK

-PG. 68, CHANGED AUD_PORTB_DET_L TO AUD_PORTA_DET_L.

-PG. 68, CHANGED AUD_PORTG_DET_L TO AUD_PORTB_DET_L.

-PG. 67, SET MIN. LINE AND NECK WIDTHS FOR AUD_CONN_L AND AUD_CONN_R

***PAGES SYNCED FROM K24 SINCE LAST RELEASE 5.0.0***

- PAGE 26: CHANGED C2615,C6210 TO 138S0653

- ADDED PLACEMENT NOTES (ATTRIBUTE) TO ALL XW SHORTS

- PAGE 7: ADDED PPBUS_R_G3H DEBUG VOLTAGE TEST POINT

- PAGE 34: REPLACE Q3450 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

-PG. 67, ADDED J6704

-PG. 65, DELETED R6521

-PG. 66, ADDED C6634/5

-PG. 66, ADDED R6631/2/3/4/5

-PG. 66, ADDED C6612/13

-PG. 65, ADDED R6523/4

FREESCALE FEEDBACK

VOLTAGE TEST POINTS

C2595 TO 138S0653

THE 107S0074/75 PARTS

AS IN K19I

-PG. 67, ADDED XW6702

-PG. 66, UPDATED 5V S3 ALIAS NOTES

1. PAGE 3: POWER BLOCK DIAGRAM - ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR. ALSO, ADDED SENSE RESISTOR ON PPBUS

- PAGE 8: ADDED =PP3V42_G3H_HALL FOR THE HALL EFFECT CONNECTOR

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.5.0***

- PAGE 69: ADDED HALL EFFECT CONNECTOR CIRCUIT J6955 APN 516S0787

- PAGE 8: ADDED PLACEMENT NOTE TO Q5502

- PAGE 8: DELETED =PP3V42_G3H_PPBUSAISNS AS PPBUS SENSE CIRCUIT HAS BEEN REMOVED

- PAGE 72: REPLACED C7282 WITH OSCON APN 128S0248 IN PARALLEL WITH C7280 AS PER DAYU

3/26/2009: RELEASE 7.6.0 (MAJOR)-

- ADDED OMIT BOM OPTION TO ALL THE XW SHORTS

- ADDED DIDT=TRUE ATTRIBUTE TO BOOT/VBST SIGNALS OF ALL THE SWITCHING SUPPLIES

- PAGE 8: DELETED =PP3V42_G3H_BATT AS THERE IS NO BIL CONNECTOR

- PAGE 8: ADDED =PP3V3_S3_AUDIO ALIAS NET FOR CASEY’S NEW CHANGES BELOW

- PAGE 8: RENAMED ALIAS =PP5V_S3_P5VS0FET TO =PP5V_S3_P5VLTS0FET AS THIS GOES TO 5V LT S0 FET CIRCUIT

- PAGE 79: RENAMED INPUT VOLTAGE NETS OF 5V S0 FET CIRCUITS TO REFLECT RT AND LT

1P05_HIGH_SIDE_SENSE OPTIONS UNDER K84_COMMON BOM GROUP

- PAGE 4: ADDED MCP_T_DIODE_SENSOR, MCPSMC_DIGITEMP_NO BOM OPTIONS UNDER K84_COMMON BOM GROUP

- PAGE 4: UPDATED DESCRIPTION FOR THE CPU

- PAGE 7: UPDATED TPS AS PER NEW UPDATE FROM TOM (SPREADSHEET ATTACHED TO THE RADAR)

- PAGE 12: REPLACED C1260 WITH APN 128S0267 AS PER DAYU

- PAGE 34: DELETED TEXT NOTE ASSOCIATED WITH J3401

ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 OHMS

OHMS

CONSTRAINT SET

3/31/2009: RELEASE 9.0.0 (RFA)-

- ADDED BACK PAGES 97-98 (LCD BACKLIGHT DRIVER AND SUPPORT CKT)

1/27/2009: TMLB FIRST RELEASE 0.0.1-

- REPLACED TEXT TMLB WITH MLB THROUGH OUT THE SCHEMATICS

2/5/2009: RELEASE 0.0.2 -

- COPIED TMLB OVER TO MLB AS K84 WILL BE PENRYN SKU WHILE K83 WILL BE ATOM SKU

- PAGE 4: UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_ENG FOR K84_COMMON BOM GROUP

- PAGE 8: DELETED FIREWIRE, IR AND BMON SPECIFIC NETS

- PAGE 55: REPLACED CPU/MCP THERMAL SENSORS U5515 ANDB U5535 WITH THE CHEAPER VERSION APNB 353S2573

2. PAGE 8: ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR, WHILE PPBUSB FEEDS 5V/3.3 V SUPPLY, LCD BKLT & PPBUS VOLTAGE SENSE CKT

- PAGE 4: ADDED CYNTEC ALTERNATES FOR 107S0074 --> 107S0138 [R7020] AND 107S0075

-PG. 67, ADDED R6725

- PAGE 70: REMOVED R7080 SENSE RESISTOR AND RENAMED =PPBUSB_G3H TO =PPBUS_G3H AS NO NEED

- PAGE 34: CHANGED J3401 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

- PAGE 7: DELETED PPBUS_R_G3H AS NO NEED OF TWO PPBUS BRANCHES

-PG. 66, CHANGED C6610/11/30/31 TO 0.015UF

-PG. 68, ADDED MIKEY MIC LOAD COMPARATOR CKT

-PG. 68, CORRECTED CODEC OUTPUT SIGNALS TABLE COMMENTS

- PAGE 8: COMBINED TWO SEPARATE PPBUSA/B BRANCHES INTO ONE =PPBUS_G3H

- PAGE 70: ADDED R7050 (6259_YES) CONNECTION FROM PIN 4 (VREF) TO PM_SLP_S3_L AS PER DAYU

- PAGE 59: REPLACED SMS PART WITH THE NEW BOSCH BMA141 ANALOG PART. ADDED R5923 10K PU RESISTOR ON

- DELETED NOTE ABOVE U6500

PP3V3_WLAN, R6010 HAS BEEN CHANGED TO 634K TO GET VDIVIDER = ~2V

- PAGE 55: ADDED MCP_T_DIODE_SENSOR BOM OPTION TO THE MCP T-DIODE THERMAL

CURRENT SENSE CIRCUIT AND WITH 1P05_HIGH_SIDE_SENSE FOR CPU 1.05V AND

CONNECTIONS. AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0

TO SMB_0_S0_DATA NETS

R9730 PIN SHORT TO ISOLATE NOISY PGND FROM THE SYSTEM GND. NAMED IT

- PAGE 97: RENAMED GND_LCDBKLT TO GND_LCDBKLT_SGND

SYSTEM GND

ALSO, CHANGED R9705 TO 10K 1% VALUE - APN 114S0315

4/1/2009: RELEASE 9.1.0 (MAJOR)-

14. PAGE 70: DIVIDED PPBUS INTO TWO BRANCHES - PPBUSA & PPBUSB. ADDED SENSE RESISTOR R7080 (2 MOHMS) ON PPBUSA. ALSO ADDED INA210 AMPLIFIER CKT ACROSS SENSE LINES. ADDED PP3V42_G3H_PPBUSAISNS (IN210 POWER) ALIAS ON PAGE 8

12. ADDED PAGE 60 AND COPIED OVER ZEPHYR2 SCHEMATICS PAGE FROM M97 IPD_FLEX_WELLSPRING. DELETED THE IPD BOARD CONNECTOR. CALLING IT WELLSPRING 3

10. PAGE 4: ADDED DEBUG_SENSE BOM OPTION TO THE K84_DEVEL_ENG BOM GROUP

11. PAGE 58: DELETED IPD FLEX CONNECTOR J5800. RENAMED PP18V5_S3, PP3V3_S3_LDO_R, PP3V3_S3_LDO TO PP18V5_S3_LDO, PP3V3_S3_IPD_R AND PP3V3_S3_IPD RESPECTIVELY TO MATCH WITH NEW ADDED PAGE 60 NET NAMES. UPDATED THESE NET NAMES ON PAGE 7 ALSO

9. PAGE 54: ADDED BOM OPTION- DEBUG_SENSE- TO CPU 1.05V/CPU VCORE HIGH SIDE CURRENT SENSE AND MCP MEM VDD CURRENT SENSE CIRCUITS FOR DEVELOPMENT BOM

4. PAGE 34: REPLACED AIRPORT CONNECTOR WITH PN 516S0580 AND UPDATED CONNECTIONS ACCORDINGLY

- NO CHANGES SINCE LAST MAJOR RELEASE 0.1.0

- PAGE 72: REPLACE Q7220 WITH SIZ700DT

- PAGE 7: DELETED IR_RX_OUT, PP5V_S3_IR_R, KBDLED_ANODE, SMC_KBDLED_PRESENT_L

- REMOVED ALS SPECIFIC NETS (PAGE 34 & 52)

- UPDATED PAGES 72-73 : 5V/3.3V & DDR3 POWER SUPPLIES AS PER FLO’S RECOMMENDATIONS

- CORRECTED BOM CONFIG TABLE (ADDED BACK BKLT_ENG)

1/21/2009: RELEASE 0.0.3-

- UPDATED BOM CONFIGURATIONS

1/21/2009: RELEASE 0.0.2-

- UPDATED SCHEMATIC AND PCB PART NUMBER INFO

- REPLACED K24 REFERENCES WITH K84

- ALL PAGES SYNC’ED FROM K24

1/19/2009:

Revision History

- PAGE 73: REPLACE 16V INPUT SIDE CAPS C7331 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS

[R7008] --> 107S0139

- PAGE 69: REMOVED BIL CIRCUIT AS IT NO LONGER A POR [R6960, C6954, D6951, C6953, C6952, J6955, C6951]

- PAGE 102: ADDED CONN_PCIE_MINI_R2D_P/N AND CONN_PCIE_MINI_D2R_P/N NETS IN THE

SENSOR CIRCUIT

- PAGE 54: REPLACED DEBUG_SENSE BOM OPTION WITH MEM_SENSE FOR MCP MEMORY VDD

- PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN SMC B SMBUS AND MCP SMBUS 1

- PAGE 9; ADDED 3 ADDITIONAL TALL POGO PINS AS PER NEW MCO AND DELETED ZS0909 SHORT POGO AS IT WAS EXTRA

- PAGE 7: DELETED SMC_BIL_BUTTON_L NET FROM BATT SIGNAL CONN GROUP AS BIL IS NO LONGER A POR

- PAGE 97: DISCONNECTED PGND (OF CAPS) FROM XW9700 AND ADDED A SEPARATE XW9701

- PAGE 97: FIXED THE LCDBKLT_VIN SIGNAL NAME ASSOCIATION TO THE CORRECT NET INSTEAD OF

- PAGE 69: REFRESHED HALL EFFECT SENSOR WITH THE NEW SYMBOL

- PAGE 52: FIXED SENSOR ADC SMBUS CONNECTIONS (BOTH SCL AND SDA WERE WRONGLY CONNECTED

- REMOVED NOTE RE: ROUTING TO MCP79 GPIO ABOVE U6870

- ADDED BOMOPTION = MIKEY ATTRIBUTE TO R6860, C6860, Q6802, R6864, R6865, & R6861

- UPDATED SIGNAL PATH CHART TO INCLUDE MCP79 GPIO ASSIGNMENTS

- ADDED BOMOPTION = MIKEY_LOAD_DET ATTRIBUTE TO R6870, R6871, C6870,

- CHANGED R6211 & R6212 FROM 39 OHMS TO 22 OHMS

***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 8.0.0***

- PAGE 4: ADDED MIKEY_LOAD_DET BOM OPTION UNDER K84_MISC BOM GROUP

- PAGE 75: ADDED C7590 (2.2UF) APN 138S0579 IN PARALLEL WITH C7563 AS PER DAYU

K19I UPDATES, EXCEPT VOLTAGE DIVIDER FOR PP3V3_WLAN [K19I USES 5V RAIL]. FOR

- PAGE 59: DELETED R5923 FROM THE TEXT NOTE

CPU VCORE HIGH SIDE CURRENT SENSE CIRCUIT

- PAGE 52: ADDED BOM OPTION MCPSMC_DIGITEMP_NO TO R5230 AND R5231

- PAGE 34: ADDED LC FILTER (L3406 AND C3432) ON PP3V3_S3_BT POWER RAIL AS PER JOHN SCHEN’S FEEDBACK

- PAGE 60: MANUALLY UPDATED RESISTORS VALUES (VOLTAGE DIVIDERS,AMPLIFIER GAINS, RC) TO MATCH WITH

- UPDATED SCHEM AND PCBF PART NUMBER INFO

- PAGE 4: ADDED 085 DEVELOPMENT BOM VARIANT & K84_DEVEL_ENG, K84_DEVEL_PVT BOM GROUPS

- PAGE 66: FIXED UNNAMED NETS CONNECTED TO - R6632

- PAGE 7: RENAMED RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR

- PAGE 7: DELETED THERMAL FUNC_TEST SECTION

- PAGE 9: FIXED BAD_TP_NC NETS - TP_RTL8211_CLK125, TP_PP3V3_ENET_PHY_VDDREG

- PAGE 34: RENAMED TITLE: RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR

- PAGE 69: CHANGE PIN OUTS OF J6955 AS PER CHINMAY

- PAGE 78: FIXED BAD_TP_NC NETS - TP_DDRREG_PGOOD

- PAGE 9: DELETED Z0912 MLB MOUNTING HOLE AS NO LONGER NEEDED

- PAGE 7: DELETED BATT SIGNAL CONN AND ADDED HALL EFFECT CONNECTOR TEST POINTS

- PAGE 7: SCRUBBED THROUGH THE FUNCTIONAL TEST POINTS AGAINST TOM’S SPREADSHEET

- PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN MIKEY AND MCP SMBUS 1 CONNECTIONS.

- PAGE 45: ADDED VOLTAGE, MIN LINE AND NECK WIDTH FOR PP5V_S0_HDD_FLT

- PAGE 4: ADDED SHORT POGO PIN 870-1699 AS ALTERNATE FOR THE MEDIUM ONES

- PAGE 4: DELETED DEBUG_SENSE BOM OPTION AND ADDED MEM_SENSE AND

- PAGE 74: FIXED UNNAMED NETS CONNECTED TO - XW7401, XW7402, XW7403 AND XW7404

- PAGE 9: ADDED TP_ ALIASES FOR - CARDREADER_RESET, USB_CARDREADER_N/P, AND

3/29/2009: RELEASE 8.0.0 (RFA)-

- PAGE 50: REPLACED R5030 WITH APN: 114S0114,(IT’S A 1% TOL, 1/16W, 0402, 84.5OHM RESISTOR)

- PAGE 52: ADDED 0 OHMS STUFFING OPTION TO CONNECT MIKEY SMBUS CONNECTIONS TO MCP SMBUS 0.

- PAGE 90:RE-ROUTED LED_RETURN SIGNALS FOR LAYOUT FEASIBILITY(CHIP WAS MOVED TO TOP SIDE)

- PAGE 49:FIXED PLACEMENT NOTES ASSOCIATED WITH R4999,C4920(SHOULD BE:PLACE NEAR PIN M12)

- PAGE 51: FIXED PLACEMENT NOTE ASSOCIATED WITH R5146 - PLACE NEAR U5110 INSTEAD OF SMC

- PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH SMBUS_SMC_B_S0_SCL/SDA

5 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=K24_MLB

Revision History

SYNC_DATE=01/19/2009

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

11/01/2009: RELEASE C.0.0 (FAB)-

ADDED APN 518S0774 FOR XDP CONNECTOR J1300 (TO REPLACE 998-2515)

- PAGE 4: ADDED APN 104S0033 (6.8 OHMS, 1/4W) RESISTORS IN MODULE PARTS TABLE FOR R6612, R6617, R6630 & R6633

- FINAL PVT OK2FAB RELEASE

09/21/2009: RELEASE A.0.0 (FAB)-

K84_DEBUG_PROD BOM GROUP IS TURNED ON

- PAGE 4: UPDATED BOM TABLES TO NOT INCLUDE ANY 085 DEVELOPMENT BOMS. AND,

- PAGE 3: UPDATED POWER SYSTEM BLOCK DIAGRAM

- PAGE 2: UPDATED SYSTEM BLOCK DIAGRAM

- PROD (POST 1ST MONTH OF PRODUCTION) OK2FAB RELEASE

09/16/2009: RELEASE 17.0.0 (FAB)-

- FINAL DVT OK2FAB RELEASE

- PAGE 50: CHANGED R5030 SIL RESISTOR TO 80.6 OHMS APN 114S0112 AS PER ID

- PAGE 66: ADDED BOMOPTION OMIT TO RESISTORS R6612, R6617, R6630 & R6633

- PROD_DEBUG (POST FIRST 5K UNTIL 1 MONTH INTO PRODUCTION) OK2FAB RELEASE

- PAGE 4: ADDED 1 NEW POR BOMS 639-0554, 639-0555 AND 1 NEW DEVELOPEMENT BOM

- PAGE 4: DELETED 353S2811 ENTRY FROM THE ALTERNATES TABLE

NUMBERS AS PER KIRAN’S EMAIL

- PAGE 57 : CHANGED R5714 TO 165 OHMS APN 114S0141 AS PER

05/11/2009: RELEASE 12.14.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL):

05/10/2009: RELEASE 12.13.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL):

- REMOVED R6725 AND =PP3V3_S3_AUDIO CONNECTION TO MAX14504 ANALOG SWITCH

- PAGE 75: CHANGED R7569 TO 11.3K APN 114S0319 FOR SETTING THE CORRECT OCSET AS PER DAYU

- PAGE 4: DELETED 152S0694 ALTERNATE ENTRY FOR 152S0138 AS IT IS NOT USED

I2C_MIKEY_SCL/SDA_R

- PAGE 9: ADDED 7 EXTRA TALL POGO PINS FOR EMI - 4 STUFFED AT THE BOTTOM,

- PAGE 8: ADDED GLOBAL DIGITAL GROUND NET WITH MIN_LINE/NECK_WIDTH

- PAGE 97: CHANGED MIN_NECK_WIDTH ASSOCIATED WITH PPVOUT_S0_LCDBKLT TO 0.24MM

4/2/2009: RELEASE 9.3.0 (MAJOR):

- PAGE 4: REMOVED 514-0706, 514-0705 AND 514-0718 FROM THE ALTERNATES TABLE

POR IS LOW NOISE POGO PINS

- PAGE 4: ADDED NEW INTERSIL ISL6258A (WITH IMPROVED CHARGE CURRENT ACCURACY

TO K84

- PAGE 4: REPLACED CPU APN 337S3704 WITH 337S3769 IN MODULE PARTS TABLE AND REMOVED 337S3704 FROM THE ALTERNATE PART TABLE AS POR IS 337S3769

- PAGE 4: REMOVE 870-1794, 870-1698 & 870-1820 FROM THE ALTERNATES TABLE AS

- PAGE 72 : CHANGED C7252, C7291 & C7292 BACK TO ORIGINAL APN 128S0271

05/20/2009: AGILE RELEASE PROTO 2 OK2FAB 13.0.0 (FAB):

- FINAL PROTO 2 OK2FAB RELEASE

***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 9.2.0***

- PAGE 4:B ADDED 5.95MM SANYO PART 128S0288 AS ALTERNATE TO 128S0271

- PAGE 4: REMOVED 138S0606 FROM THE ALTERNATES TABLE AS IT DOESN’T PERTAIN

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.6.0***

AND TO K84 MISC BOM GROUP. THIS IS TO STUFF ISL6258 PART

WITH EITHER ISL6258 OR ISL6259 DEPENDING UPON PAGE 4 BOM TABLE

- PAGE 52: DELETED TEXT NOTE ON BATTERY LED DRIVER AS IT IS NA TO K84

- PAGE 13: FIXED THE NOTE ON THE XDP PAGE- REPLACING 920-0620 ADAPTER

- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER

08/05/2009: RELEASE 15.3.0 (MAJOR)-

- PAGE 4: ADDED PDNI PLATED AUDIO CONNECTOR W/ CHAMFER APN 514-0718 AS AN

- PAGE 4: ADDED GOLD PLATED AUDIO CONNECTOR W/O CHAMFER APN 998-2622 AS AN ALTERNATE FOR J6700 APN 514-0694

- PAGE 4: ADDED GOLD PLATED RJ45 CONNECTOR APN 998-2621 AS AN ALTERNATE FOR

- PAGE 97: REFRESHED THE SYMBOL OF C9715 4.7UF APN 138S0661

08/27/2009: AGILE PDFC OK2FAB RELEASE 16.0.0 (FAB)-

- PAGE 59: ADDED NOSTUFF BOM OPTION ATTRIBUTE TO C5923-C5925 AS STATED

- PAGE 70: CHANGED R7047 FROM 10 OHM TO 0 OHM, 5%, APN:116S0004 TO FIX SLOW

- PAGE 4: ADDED GOLD PLATED MINI DP CONNECTOR APN 998-2626 AS AN ALTERNATE

- PAGE 4: ADDED LOW NOISE POGO PINS 870-1885 (MEDIUM), 870-1886 (TALL), AND

- PAGE 49: CHANGED C4950, C4951, C4952 TO APN:132S0131 (CAP,0402,0.033UF, 16V,10%) AS THESE WOULD BE USED TO ACHIEVE CUT-OFF FREQUENCY OF

SEEN BY SMC CHIP. CAPS ON SMS PAGE WOULD BE UNSTUFFED

~146HZ FOR SMS (AS PER THE VENDOR) AND FILTER THE NOISE TOO AS

- PAGE 4: ADDED GOLD PLATED USB CONNECTOR APN 998-2624 AS AN ALTERNATE FOR

- PAGE 4: ADDED METAL PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO

REPLACED R6961 WITH A 0 OHM RESISTOR AND NOSTUFF’ED C6955

- CONNECT AUDIO JACK SHIELD TO DIGITAL GROUND.

0.6/0.24MM

- PAGE 4: ADDED APN 138S0606 (TAIYO-YUDEN) AS AN ALTERNATE FOR APN 138S0602 ALTERNATE FOR J6700 APN 514-0694

- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER

- FINAL PDFC (PRE DVT) RELEASE!

- PAGE 70: CHANGED C7043 FROM 0.1UF TO 1UF, 10%, APN:138S0640 TO FIX SLOW

- PAGE 97: CHANGED L9710 BACK TO THE ORIGINAL APN 152S0826 AS 2525 PACKAGE CAN’T FIT IN

RJ45 J3900 CONNECTOR

- PAGE 50: CHANGED R5030 TO 48.7 OHMS APN 114S0091 (SIL CURRENT TO 12MA)

CONNECTED IT TO PIN 1 (RSMRST_PWRGD) TO FIX LEAKAGE ISSUE

3V3S5_DRVL (FIXED THE NET NAME- ADDED UNDERSCORE)

- PAGE 4:B ADDED 5.95MM SANYO PART 128S0286 AS ALTERNATE TO 128S0248

- PAGE 9: REPLACED Z0906,Z0907,Z0910 AND Z0911 MLB MOUNTING HOLES WITH 2.7 MM

- PAGE 4: UNDER K84_PROGPARTS BOM GROUP, REPLACED BLANK P/N WITH

AND VOLTAGE ATTRIBUTES

- PAGE 9: REPLACED Z0905 AND Z0913 MLB MOUNTING HOLES WITH 2.7 MM

- ADDED 100PF EMC CAP ON THREE SPEAKER CONNECTORS.

- PAGE 78: DELETED SYNONYMS AS THEY ARE NOT NEEDED ANYMORE

- PAGE 28: DELETED MAKE_BASE=TRUE ASSOCIATED WITH PCIE_RESET_L

CHARGING ISSUE, PER DAYU

SLOW CHARGING ISSUE, PER DAYU

- PAGE 70: CHANGED R7031 FROM 10 OHM TO 2.2 OHM, 5%, APN:116S0010 TO FIX

ABOVE. ALSO, EDITED THE NOTE ACCORDINGLY

870-1887 (THIN) AS ALTERNATES

J4600/J4610 APN 514-0689

FOR J9400 APN 514-0691

J3900 APN 514-0704

- PAGE 4: DELETED LOW NOISE MURRATA CAP ENTRY FROM THE ALTERNATES TABLE

ENGINEER

- PAGE 70: DISCONNECTED PM_SLP_S3_L FROM PIN 4 (VREF) AS IT WAS INCORRECTLY

- PAGE 97: NOSTUFFED C9716 AND CHANGED C9715 TO APN 138S0661 AS POR IS TO

- PAGE 46: REPLACED J4600 & J4610 USB CONNECTORS WITH POR PLASTIC CONNECTOR

- PAGE 4: DELETED CHGR_6258 AND RENAMED 6259_NO TO

07/27/2009: RELEASE 15.2.0 (MAJOR)-

HAVE SINGLE CAP LOW NOISE MURRATA CAP SOLUTION AS PER ACOUSTICS

CONNECTED, THEREBY CAUSING HIGHER SLEEP/SHUTDOWN POWER

132S0178 TO FIX THE SMART TEST FAILURE

- PAGE 49: CHANGED SMS NOISE FILTERING CAPS C4950-C4952 TO 0.47UF APN

07/21/2009: RELEASE 15.1.0 (MAJOR)-

CATEGORY AS PER CASEY

PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE

- PAGE 70: DELETED OMIT BOM OPTION FROM U7000 AS ISL6259 HAVE BEEN

- NO CHANGES SINCE LAST MAJOR 14.7.0. THIS IS FINAL EVT FAB RELEASE

PRODUCTION HAS NOW MOVED TO ITS ALTERNATE PART 353S2718

: ZS0920

- PAGE 78: ADDED 0 OHM BOM OPTION R7895 BETWEEN 1V05_S5_PGOOD AND RSMRST_PWRGD FOR DEBUG PURPOSES

06/11/2009: RELEASE 14.4.0 (MAJOR)-

- PAGE 97: CHANGED MIN_LINE/NECK_WIDTH ASSOCIATED WITH GND_LCDBKLT_SGND TO

- REMOVED OPTIONAL STUFF-AROUND RESISTORS FOR ANALOG SWITCH

- PAGE 9: DELETED GND MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES

- PAGE 78: DELETED MAKE_BASE=TRUE ASSOCIATED WITH ALL_SYS_PWRGD

- PAGE 9: ADDED ONE MORE TALL POGO PIN ON BOTTOM SIDE

4/3/2009: RELEASE: 9.6.0 (MAJOR):

- PAGE 78: ADDED BOMOPTION ATTRIBUTE OMIT TO U7870 AS NEW INTERSIL PART

PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE

- PAGE 39: ADDED BOMOPTION ATTRIBUTE OMIT TO J3900 AS NEW PG2 CONNECTOR

- PAGE 9: ADDED NOSTUFF BOM OPTION TO ZS0920

- PAGE 97: CHANGED R9710 TO 7.68K APN 114S0304 (LCD BKLT CURRENT TO 20MA)

06/25/2009: RELEASE 14.7.0 (MAJOR)-

ETHERNET JITTER ISSUE

- PAGE 49: REPLACED C4950-C4952 WITH 1UF APN 138S0640 CAPS

06/22/2009: RELEASE 14.6.0 (MAJOR)-

- PAGE 97: ADDED CRITICAL ATTRIBUTE TO C9715 & C9716

**PAGES SYNCED FROM CASEY’S AUDIO_MLB SINCE LAST RELEASE 12.1.0***

CASE_B2_SM DUE TO PACKAGING ERROR (SAME APN)

- PAGE 94: REPLACED J9400 DP CONNECTOR WITH POR PLASTIC CONNECTOR

- PAGE 75: CHANGE R7565 TO 1OHM APN 113S0023 PER RDAR://6812904

APN 514-0692

514-0691 ALTERNATE FOR 514-0690;

- NO CHANGE SINCE LAST RFA RELEASE 11.0.0. ***THIS IS A RESUBMIT AS PREVIOUS RFA DIDNT GO THROUGH***

4/23/2009 - RELEASE 12.1.0 (MAJOR):

ADDED CORRESPONDING NOTES-

- NO CHANGE SINCE LAST MINOR RELEASE 10.1.1

- PAGE 4: ADDED CPU APN 337S3769 AS ALTERNATE TO 337S3704

- PAGE 13: REPLACED J1300 XDP CONNECTOR WITH MORE ROBUST CONNECTOR

- PAGE 75: CHANGE Q7560 AND Q7565 TO SIS426 APN 376S0749 PER

- PAGE 39: REPLACED J3900 ETHERNET CONNECTOR WITH POR PLASTIC CONNECTOR

UNDER MODULE PARTS TABLE .

- PAGE 4: DELETED ENTRIES IN THE ALTERNATE BOM TABLE FOR THE FOLLOWING APN:

- PAGE 70: FIXED Q7001 DRAIN-SOURCE ORIENTATION

06/12/2009: RELEASE 14.5.0 (MAJOR)-

06/11/2009: RELEASE 14.3.0 (MAJOR)-

- PAGE 77: CHANGED R7780 TO 25.5K APN 114S0354 & R7781 TO 80.6K APN

DIAMETER PLATED HOLES - APN 998-1584

REMOVED

114S0402 AS PER DAYU

NETS TO FIX NOISE ISSUE

- PAGE 49: ADDED 0.1UF CAPS ON SMS_X_AXIS, SMS_Y_AXIS & SMS_Z_AXIS

- PAGE 4: ADDED APN 138S0661 LOW NOISE MURATA CAPS AS ALTERNATE FOR

4/6/2009 - RELEASE 11.0.0 (OK2FAB):

C9715 & C9716 TO FIX LCD BKLT AUDIBLE NOISE ISSUE

- PAGE 78: DISCONNECTED P1V05_S5_PGOOD FROM PIN 3 OF U7840 AND

4/5/2009: RELEASE 10.1.0 (MAJOR):

4/2/2009: RELEASE: 9.5.0 (MAJOR):

AS PER JOHN SCHEN

- PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH

05/22/2009: AGILE RELEASE PROTO 2 OK2FAB 14.0.0 (FAB)-

***RETRY***

RDAR://PROBLEM/6875543

SMC B SMBUS TO MCP79 SMBUS 1

05/08/2009: RELEASE 12.12.0 (MAJOR & WEEKLY ECO):

MIKEY TO MCP79 SMBUS 0 INSTEAD OF SMBUS 1 AND TO CONNECT

IT HAS I2C BUS PU TO S0 POWER RAIL

05/05/2009: RELEASE 12.11.0 (MAJOR & WEEKLY ECO):

- PAGE 97: CHANGED L9710 TO A BIGGER 2525 PACKAGE (LOW DCR) APN 152S0585 FOR

THOUGH POR IS PLASTIC MINI DP CONNECTOR PART

- PAGE 94: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS

THOUGH POR IS PLASTIC USB CONNECTOR PART

- PAGE 46: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS

- PAGE 4: ADDED 4 QUANTITIES OF DIMM CONNECTOR SCREWS APN 452-1708

5/01/2009: RELEASE 12.8.0 (MAJOR):

- PAGE 4: ADDED A36 EEE NUMBER FOR NEW BOM CONFIGURATION 639-0254 SUPPLY RAILS TO ADC CHIP I2C BUS

05/01/2009: RELEASE 12.9.0 (MAJOR):

- PAGE 4: UPDATED PLASTIC PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO 514-0690 PLASTIC ALTERNATE FOR 514-0691 METAL;

- PAGE 60: CHANGED U6050 INA 211 PART TO 200X GAIN INA 210 APN 353S2073

514-0688 PLASTIC ALTERNATE FOR 514-0689 METAL

- PAGE 46: REPLACED PLASTIC USB CONNECTORS WITH METAL APN 514-0689 PARTS

- PAGE 60: ADDED 0 OHMS SERIES RESISTORS R6003 AND R6004 ON AVDD AND DVDD

4/29/2009: RELEASE 12.7.0 (MAJOR & WEEKLY ECO):

- PAGE 60: CHANGED R6001 & R6002 TO 33 OHMS RESISTORS TO FIX UNDERSHOOT ON

ADDED TWO ENTRIES (J3200 AND J3100) FOR FOXCONN AND TWO FOR MOLEX

- PAGE 4: ADDED NEW BOM ENTRY 639-0254 FOR MOLEX DDR3 CONNECTOR CONFIG. ALSO,

- PAGE 76: CHANGED THE CPU VTT OVER CURRENT TRIP POINT PER RDAR://6792329 BY

- PAGE 67: MOVED L6707 & L6708 TO J6703 (FULL RANGE SPEAKER CONNECTOR)

4/28/2009: RELEASE 12.5.0 (MAJOR):

FOR EMI PURPOSES - L6707 & L6708

4/28/2009: RELEASE 12.4.0 (MAJOR):

- PAGE 74: CHANGED R7415 TO 10.5K AS PER RDAR://6792327

- PAGE 74: UNSTUFFED C7434 AS PER RDAR://6792327

- REPLACED J6700 WITH APN: 514-0694

4/24/2009 - RELEASE 12.2.0 (MAJOR):

- PAGE 70: ADDED OMIT BOM OPTION TO U7000 AS THIS PART WILL GET STUFFED

DIAMETER PLATED HOLES - APN 998-1584

AS PER KIRAN

- PAGE 97: CHANGED R9716 FROM 226K TO 243K TO CHANGE THE OVP POINT TO 35.3V

- PAGE 4: ADDED CHGR_6258 BOM OPTION UNDER MODULE PARTS TABLE

APN 514-0690

- ADDED DZ 6702 AND L6706

4/27/2009 - RELEASE 12.3.0 (MAJOR & WEEKLY ECO):

EDITED 639-0035 BOM NAME TO REFLECT FOXCONN DDR3 CONNECTOR.

- PAGE 57: DELETED NO_TEST = TRUE ATTRIBUTE FROM Z2_SCLK AND

- PAGE 34: RENAMED P5VWLAN_SS NET TO P3V3WLAN_SS

4/3/2009: RELEASE: 10.0.0 (RFA):

(DUE TO 0 OHMS)

IN MODULE PARTS TABLE

TO SHOW A SEPARATE CONNECTION FOR CLARITY

- PAGE 52: MOVED THE R5251 CONNECTION TO SENSOR ADC TO THE RIGHT SIDE

516-0213 AND 516S0709

514-0689 ALTERNATE FOR 514-0688 APN 998-2515

BOARD WITH 920-0782 ADAPTER FLEX

**SCHEMATIC AND BOM CLEAN-UP**

APN 514-0688

- PAGE 69: RENAMED 6259_NO/YES TO CHGR_6259_NO/YES

CHGR_6259_NO. REPLACED CHGR_6258 WITH CHGR_6259_NO

CHANGING R7604 FROM 8.87KN) TO 6.04KN)

RDAR://6812904

4/6/2009 - RELEASE 10.1.1 (MINOR):

- CONNECTED R6860 TO AUD_IP_PERPH_DET

- PAGE 46: DELETED TEXT NOTE RELATED TO R4691 & R4690 AS IT IS NA TO K84

- PAGE 74: CHANGED C7432 TO 0.001UF AS PER RDAR://6792327

- PAGE 74: CHANGED C7428 TO 0.47UF AS PER RDAR://6792327

BETWEEN CAPS AND CONNECTOR

BETTER EFFICIENCY

4/29/2009: RELEASE 12.6.0 (MAJOR & WEEKLY ECO):

- PAGE 94: REPLACED PLASTIC MINI DP CONNECTOR WITH METAL APN 514-0691 PART

ADDED CORRESPONDING NOTES-

- PAGE 4: REMOVED SHORT POGO PIN ALTERNATE

- PAGE 4: REVERTING MCP TO EARLIER USE APN 338S0710

J6704 FOR EMI PURPOSES - L6709 & L6710

05/04/2009: RELEASE 12.10.0 (MAJOR):

128S0286

128S0288

PROGRAMMED P/N

FROM FAN STANDOFF

3 UNSTUFFED ON THE TOP

- CHANGED MIN_WIDTH OF CODEC HP OUT NETS.

- PAGE 69: PUT R6961 BEFORE C6955 TO GET RC FILTER. ALSO, FOR NOW,

RDAR://PROBLEM/6752822

128S0286

- UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS

- PAGE 97: ADDED A 1000PF CAP (C9727) ON LCDBKLT_VIN NEAR PIN 1

- PAGE 77: CHANGED C7771 TO 47UF APN 138S0659 TO FIX ETHERNET JITTER ISSUE

- PAGE 72: REPLACED C7240 & C7282 WITH 5.95MM SANYO APN

JITTER ISSUE

RDAR://PROBLEM/6834630

- PAGE 60: CHANGED R6003 AND R6004 TO 10 OHMS 5% RESISTOR VALUES

- PAGE 73: REPLACED C7331 & C7345 WITH 5.95MM SANYO APN

ISSUE

- PAGE 70: REMOVED R7050 CHGR_6259_YES COMPONENT AS IT IS NOT NEEDED

CURRENT PER RDAR://PROBLEM/6752822

- PAGE 50: CHANGED R5714 TO 0 OHM APN 116S0004 PER

- PAGE 69: REFRESHED J6955 SYMBOL - APN 516S0787

- PAGE 67: CHANGED J6704 TO A THREE PIN CONNECTOR 518S0520

- PAGE 69: REFRESHED J6955 SYMBOL (HALL EFFECT CONNECTOR)

- PAGE 59: ADDED R5922 10 OHMS SERIES R ON VDD SUPPLY TO FIX SMS NOISE

ZS0916-ZS0918 WITH THINBC APN 870-1820 (2 MM) ONES

- PAGE 9: REPLACED ALL MEDIUM POGO PINS WITH APN 870-1794 (2 MM) AND

- PAGE 4: ADDED NEW ISL PART APN 353S2718 AS AN ALTERNATE TO FIX B4 DONGLE

- PAGE 4: REMOVING CHGR_6259_NO BOM OPTION AS ISL 6259 IS NOT POR

06/09/2009: RELEASE 14.1.0 (MAJOR)-

- ADDED R6862 PULL-UP RESISTOR TO PERPH. DETECT CKT.

***PAGES SYNCED FROM CASEY HARDY?S AUDIO_MLB SINCE LAST RELEASE 14.0.0***

(APN 138S0654): TO FIX B4 DONGLE ISSUE

C9400 & C9481 TO 4.7UF (APN 138S0618) & CHANGED C9480 TO 22UF

- PAGE 94: STUFFED C9485 AND CHANGED IT TO 22UF (APN 138S0654),CHANGED

WITH ISL 6258 (PM_SLP_S3_L DIRECTLY CONNECTS TO ISL 6258 PIN)

WITH XW SHORTS- XW7052 & XW7054

- PAGE 70: DELETED R7051 & R7053 CHGR_6259_YES BOM OPTIONS COMPONENTS

ISSUE

- PAGE 70: REMOVED CHGR_6259_YES/NO BOM ATTRIBUTES AS ISL 6259 IS NOT POR

- PAGE 70: REPLACING R7052 & R7054 CHGR_6259_NO BOM OPTION COMPONENTS

4/7/2009 - RELEASE 12.0.0 OK2FAB (RFA):

- PAGE 75: CHANGED C7565 AND C7568 TO CASE_B4_SM PACKAGE FROM

- PAGE 8: DELETED =PP3V3_S3_AUDIO ALIAS AS IT IS NO LONGER APPLICABLE Z2_MOSI AS THEY CONFLICT WITH FUNC_TEST ATTRIBUTE ON PAGE 7

**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.5.0***

06/10/2009: RELEASE 14.2.0 (MAJOR)-

- PAGE 77: ADDED 0 OHMS BOM OPTIONS R7782 BETWEEN PIN 4 OF U7750 (SKIP PIN) AND POWER RAIL AND R7783 BETWEEN PIN 4 AND GND. R7782 WILL BE NOSTUFF FOR NOW. THIS IS AS PER DAYU TO FIX

- PAGE 9: ADDED ONE MORE EXTRA TALL POGO PIN AS PER EMC RECOMMENDATION

- PAGE 57: CHANGED R5714 TO 113 OHMS APN 114S0125 (KB LED CURRENT TO 8.5MA)

07/17/2009: AGILE EVT OK2FAB RELEASE 15.0.0 (FAB)-

- PAGE 4: DELETED MIKEY_LOAD_DET BOM OPTION FROM THE TABLE UNDER K84_MISC

UPDATED NOTE BELOW THE ALTERNATES PARTS TABLE ACCORDINGLY

- PAGE 4: UPDATED ALTERNATES FOR MINI DP AND USB CONNECTORS WITH PG2

- PAGE 4: ADDED PG2 CONNECTOR APN 514-0704 IN THE MODULE PARTS TABLE FOR

- PAGE 4: DELETED 353S2310 PART FROM THE ALTERNATES BOM TABLE AS ALL

FOR U7870 TO FIX B4 DONGLE ISSUE CIRCUIT HAS BEEN REMOVED. SO R2143 NEEDS TO BE STUFFED NOW

- PAGE 21: DELETED NOSTUFF BOM ATTRIBUTE FROM R2143 AS MIKEY_LOAD_DET

- PAGE 4: ADDED NEW INTERSIL PART APN 353S2718 IN THE MODULE PARTS TABLE

PLASTIC CONNECTORS- APN 514-0706 (MDP) & 514-0705 (USB). AND,

ALTERNATE TABLE (MAKING ALTERNATES AS PRIMARY)

- FINAL PROTO 2 OK2FAB RELEASE

- UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS

(P7550)

08/31/2009: RELEASE 16.1.0 (MAJOR)-

- PAGE 53: REPLACED APN 376S0545 WITH 376S0820 @ Q5315 - PER ECO#0000737172

- PAGE 50: REPLACED DUAL Q5032 FET WITH TWO SINGLE Q5032 & Q5033 (APN 376S0612)

- PAGE 97: REPLACED C9717 WITH 1000PF CAP APN 132S0147 AND ADDED PLACEMENT NOTE

4/2/2009: RELEASE: 9.4.0 (MAJOR):

Revision History

- PAGE 72: REPLACED C7252, C7291 & C7292 WITH 5.95MM SANYO APN

- PAGE 97: UPDATED SCHEMATIC NOTE RELATED TO TARGET AND ACTUAL ISET & OVP

- PAGE 94: ADDED OMIT BOM OPTION TO J9400 MINI DP CONNECTOR

- PAGE 67: ADDED OMIT BOM OPTION TO J6700 AUDIO CONNECTOR

- PAGE 46: ADDED OMIT BOM OPTIONS TO J4600 & J4610 USB CONNECTORS

- PAGE 9: ADDED OMIT BOM OPTION ON ALL THE POGO PINS

AND ADDED TO MODULE PARTS TABLE AS THEY ARE NOW POR I/O CONNECTORS

CONNECTORS AS THEY ARE NO LONGER POR FOR DVT

- PAGE 4: REMOVED 998S APN FROM THE ALTERNATES TABLE PERTAINING TO I/O

LIMITS) APN 353S2811 AS AN ALTERNATE FOR APN 353S1832

870-1820) IN MODULE PARTS TABLE

- PAGE 13: ADDED OMIT TO J1300

- PAGE 52: CHANGED R5200, R5201, R5260 & R5261 TO 2K APN 116S0073

- PAGE 50: CHANGED R5030 TO 63.4 OHMS APN 114S0102 TO INCREASE THE SIL

- PAGE 37: CHANGED C3714 AND C3715 TO 2.2UF APN 138S0642 TO FIX ETHERNET

- PAGE 4: ADDED A TEXT NOTE STATING THAT ADC CAN ONLY WORK IN S0 STATE AS

- PAGE 4: DELETED SANYO 6.00MM OSCON CAPS 128S0248 & 128S0271 FROM THE

085-1076 FOR INITIAL RAMP

- PAGE 4: UPDATED BOM GROUPS TABLE TO REFLECT AFOREMENTIONED CHANGES. NEW DEVELOPMENT BOM ONLY HAS XDP CONNECTOR AND LPCPLUS COMPONENTS

- PAGE 4: ADDED 2 NEW EEES TO ATTACH WITH AFOREMENTIONED NEW 639 BOMS

- PAGE 70: REPLACED U7000 WITH THE NEW INTERSIL SCREENED PARTS APN 353S2811

- PAGE 4: TURNING ON BOM OPTION MCPSMC_DIGITEMP_YES AS POR IS TO CONNECT

870-1886 (IN PLACE OF 870-1698) & 870-1887 (IN PLACE OF

- PAGE 4: ADDED LOW NOISE POGO APNS 870-1885 (IN PLACE OF 870-1794),

10/12/2009: RELEASE B.0.0 (FAB)-

AS THAT’S THE PIN WIDTH

- PAGE 75: CHANGED L7560 TO APN 152S0526 - 0.68UH, 3.5MOHM,16A - AS PER DAYU

- PAGE 72: ADDED MIN_LINE/NECK_WIDTH ATTRIBUTES TO 5V_S3_DRVL, 3V3S5_VBST,

- PAGE 54:B CHANGED R5412 TO 118OHM (114S0127)

N-CH FETS FOR ROUTING PURPOSES (SIL ANODE SIGNAL)

6 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

Revision History

SYNC_MASTER=K24_MLB

SYNC_DATE=01/19/2009

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

(NEED TO ADD 2 GND TP)

LVDS FUNC_TEST

(NEED 2 TP)

BATT POWER CONN FUNC_TEST

SATA HDD/SIL FUNC_TEST

(NEED TO ADD 2 GND TP)

(NEED TO ADD 3 GND TP)

(NEED TO ADD 1 GND TP)

MIC FUNC_TEST

SPEAKER FUNC_TEST

(NEED TO ADD 2 GND TP)

X16 WIRELESS CONN FUNC_TEST

(NEED 2 TP)

IPD_FLEX_CONN FUNC_TEST

(NEED 2 TP)

(NEED TO ADD 1 GND TP)

(NEED 2 TP)

(NEED TO ADD 2 GND TP)

(NEED 2 TP)

(NEED TO ADD 2 GND TP)

HALL EFFECT CONNECTOR FUNC_TEST

(NEED TO ADD 5 GND TP)

Functional Test Points

FAN CONNECTORS FUNC_TEST

(NEED TO ADD 1 GND TP)

KEYBOARD CONN FUNC_TEST

SATA ODD CONN FUNC_TEST

POWER NETS FUNC_TEST

DC POWER CONN FUNC_TEST

7 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SMC_LID_R

TRUE

SPKRAMP_R_P_OUT

TRUE

BI_MIC_HI

TRUE

LVDS_IG_DDC_DATA

TRUE

LVDS_IG_A_DATA_N<0>

PP5VLT_S0

TRUE

PP1V8_S0

TRUE

PM_SLP_S3_L

TRUE

PP3V3_S3_LDO

TRUE

PP18V5_S3

PP3V3_S5_AVREF_SMC

TRUE

WS_CONTROL_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD23

WS_KBD21

TRUE

WS_KBD17

TRUE

WS_KBD8

TRUE

WS_KBD7

TRUE

PP5V_S3_CAMERA_F

WS_KBD22

TRUE

WS_KBD20

TRUE

WS_KBD18

WS_KBD12

TRUE

LVDS_IG_A_DATA_N<1>

TRUE

LVDS_IG_A_DATA_N<2>

TRUE

PP5VRT_S0

WS_KBD15_CAP

TRUE

WS_KBD2

TRUE

PP0V75_S0

WS_KBD16_NUM

TRUE

ADAPTER_SENSE

TRUE

LVDS_IG_A_DATA_P<0>

TRUE

LVDS_IG_A_DATA_P<1>

TRUE

WS_KBD10

TRUE

PP5V_SW_ODD

TRUE

SATA_HDD_R2D_P

TRUE

LVDS_IG_A_CLK_F_N

TRUE

LVDS_IG_DDC_CLK

TRUE

LVDS_IG_A_DATA_P<2>

PP18V5_DCIN_FUSE

TRUE

WS_KBD19

TRUE

SMC_ODD_DETECT

TRUE

SATA_ODD_D2R_C_P

TRUE

LED_RETURN_2

TRUE

PPVCORE_S0_MCP

TRUE

PP5VRT_S0

TRUE

PP5V_S3

TRUE

PP1V5_S3

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP1V1R1V05_S5 PP3V3_S5

TRUE TRUE

PP3V42_G3H

TRUE

PPBUS_G3H

TRUE

PP3V3_ENET_PHY PP1V2R1V05_ENET

TRUE

PP5V_S0_HDD_FLT

PP3V3_WLAN

TRUE

PP3V3_G3_RTC

PPVOUT_S0_LCDBKLT

TRUE

PP4V5_AUDIO_ANALOG

TRUE

PM_SLP_S4_L

TRUE

SMC_PM_G2_EN

LED_RETURN_5

TRUE

PP3V3_LCDVDD_SW_F

TRUE

PP5V_SW_ODD

TRUE

PP1V5_S0

PP1V05_S0

TRUE

PPVCORE_S0_CPU

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

USB_CAMERA_CONN_N

TRUE

BI_MIC_LO

TRUE

FAN_RT_PWM

TRUE

BI_MIC_SHIELD

TRUE

CONN_USB2_BT_P

TRUE

SYS_DETECT_L BATT_POS_F

TRUE

PP3V42_G3H

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SATA_HDD_D2R_C_N

TRUE

PCIE_WAKE_L

TRUE

CONN_PCIE_MINI_R2D_N

LVDS_IG_A_CLK_F_P

TRUE

LED_RETURN_1

TRUE

LED_RETURN_3

TRUE

LED_RETURN_4

TRUE

PP3V3_WLAN

TRUE

PCIE_CLK100M_MINI_CONN_N

TRUE

SPKRAMP_SUB_P_OUT

SPKRAMP_SUB_N_OUT

TRUE

SPKRAMP_R_N_OUT

TRUE

SPKRAMP_L_P_OUT

SPKRAMP_L_N_OUT

TRUE

FAN_RT_TACH

TRUE

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_R2D_N

PP5V_S0_HDD_FLT

TRUE

SATA_ODD_R2D_N

TRUE

SYS_LED_ANODE_R

TRUE

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_R2D_P

TRUE

WS_KBD14

TRUE

WS_KBD13

WS_KBD11

TRUE

WS_KBD9

TRUE

PSOC_F_CS_L

TRUE

PP3V3_LCDVDD_SW_F

TRUE

PP3V3_S0_LCD_F

TRUE

Z2_CS_L

TRUE

MINI_CLKREQ_Q_L

TRUE

PP3V3_S3_LDO PP18V5_S3

TRUE

PPVOUT_S0_LCDBKLT

TRUE

Z2_DEBUG3 Z2_MOSI

TRUE

Z2_MISO

TRUE

Z2_BOOST_EN

TRUE

Z2_HOST_INTN

TRUE

Z2_CLKIN Z2_KEY_ACT_L

TRUE TRUE

Z2_RESET

TRUE

PSOC_MISO

USB_CAMERA_CONN_P

TRUE

PP5V_S3_CAMERA_F

TRUE

LED_RETURN_6

PICKB_L

TRUE

PSOC_MOSI

TRUE TRUE

PSOC_SCLK SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PP3V3_S3

TRUE TRUE

PP3V42_G3H WS_KBD1

TRUE

WS_KBD4

TRUE

WS_KBD6

TRUE

WS_KBD5

TRUE

WS_KBD3

TRUE

Z2_SCLK

TRUE

MINI_RESET_CONN_L

CONN_USB2_BT_N

TRUE

CONN_PCIE_MINI_R2D_P

TRUE

CONN_PCIE_MINI_D2R_N

TRUE

CONN_PCIE_MINI_D2R_P

TRUE

PP3V3_S3_BT_F

TRUE

SYNC_MASTER=K24_MLB

FUNC TEST

SYNC_DATE=02/04/2009

I397

I396

I395

I393

I392

I391

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I378

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I376

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I371

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I365

I364

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I360

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I353

I352

I351

I350

I349

I348

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I343

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I340

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I336

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I334

I333

I332

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I330

I329

I328

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I312

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I307

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I304

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I299

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I275

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I261

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I231

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I16

I15

I12

53 52

54 53

65 18

72 65 18

67 63 36 32 21

45 7

37 36

65 7

72 65 18

8 7

72 65 18

47 34 7

72 34

72 65

65 18

72 65 18

36 34

72 34

68 65

8 7

34 7

30 7

25 22 21

68 65 47 7

63 37 36 21

63 57 36

68 65

65 7

47 34 7

72 30

73 65

54 53

73 30

56 55

8 7

75 39

72 34

30 17

72 30

72 65

68 65

30 7

72 30

53 52

72 34

34 7

72 34

45 44

65 7

45 44

45 7

68 65 47 7

45 44

73 65

65 7

68 65

45 44

75 39

8 7

45 44

73 30

72 30

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

"S3" RAILS

"S0,S0M" RAILS

DIGITAL GROUND

& CPU VTT SENSING RES.)

(BEFORE HIGH SIDE SENSING RES.)

(MCP VCORE AFTER SENSE RES)

(AFTER HIGH SIDE CPU VCORE

43 mA (A01)

127 mA (A01)

206 mA (A01)

57 mA (A01)

206 mA (A01)

(CPU VCORE PWR)

"ENET" RAILS

"S5" RAILS

PEX & SATA AVDD/DVDD aliases

"G3H" RAILS

8 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

VOLTAGE=0V

GND

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

=PP3V3_S3_BT

=PP3V42_G3H_HALL

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_TPAD

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_ONEWIRE

=PPVIN_S5_SMCVREF

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP5V_S3_TPAD

=PP5V_S3_DEBUG_ISNS

=PP3V3_S0_IMVP

=PP3V3_S0_FAN_RT

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_XDP

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_A

=PP1V5_S3_P1V5S0FET

=PPBUS_G3H

=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_VMON

=PP1V05_S0_MCP_HDMI_VDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0

=PP3V3R1V8_S0_MCP_IFP_VDD =PP1V8_S0_AUDIO

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S0

=PP1V5_S0_MCP_PLL_VLDO

=PP1V5_S0_MEM_MCP

=PP3V3_S0_CPUVTTISNS

=PPSPD_S0_MEM_B

=PPVCORE_S0_CPU_VSENSE

=PPVCORE_S0_CPU

=PP3V3_S0_MCPTHMSNS =PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_SATA_DVDD0

=PPCPUVTT_S0_REG

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_UF

MIN_NECK_WIDTH=0.2 mm

=PP3V3_ENET_PHY

=PP3V3_ENET_MCP_RMGT

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V2R1V05_ENET

=PP1V05_ENET_FET

=PP1V5_S0_FET

=PP5V_S0_FAN_RT

=PPMCPCORE_S0_REG

=PP1V8R1V5_S0_MCP_MEM

=PP3V3_S3_FET

=PPVCORE_S0_CPU_REG

=PP3V3_S5_MCP_GPIO

=PPVTT_S3_DDR_BUF

=PP1V05_ENET_MCP_PLL_MAC

=PP1V5_S0_CPU =PP1V5_S0_VMON

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_LCD

=PP3V3_S5_MEMRESET

=PP3V3_S5_P1V05ENETFET

=PP3V3_S5_P1V05S5

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S0FET

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S5

=PP3V42_G3H_REG

=PP3V3_ENET_FET

MAKE_BASE=TRUE

PP1V05_S0_MCP_SATA_AVDD

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_SATA_AVDD0

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

=PP0V75_S0_REG

=PP1V05_S5_REG

=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET

=PP18V5_G3H_CHGR

PPBUS_G3H_CPU_ISNS

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S0_MCP

MAKE_BASE=TRUE

PP0V75_S0

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PPCPUVCORE_VTT_ISNS

=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP

PPVTT_S3_DDR_BUF

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_DPCONN

=PP3V3_S0_VMON

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_P1V8S0

=PP3V3_S0_MCP_PLL_UF

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_DAC_UF

=PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_SATA_DVDD

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

MAKE_BASE=TRUE

VOLTAGE=1.05V

=PP1V05_S0_CPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.3 MM

PPVCORE_S0_CPU

=PP3V3_S3_SMS

=PPBUS_G3HRS5

=PPVIN_S3_5VS3

=PPBUS_S0_LCDBKLT

=PPVIN_S0_MCPCORE

=PPVIN_S5_3V3S5

=PPCPUVCORE_VTT_ISNS_R

=PP18V5_DCIN_CONN

=PPVIN_S5_1V5S30V75S0

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

=PP5VRT_S0_FET

=PP5V_S0_HDD

=PP5V_S0_DP_AUX_MUX

=PP5V_S0_VMON

=PP5V_S0_MCPREG

=PP5VLT_S0_FET

=PP5V_S0_CPU_IMVP

MIN_LINE_WIDTH=0.30 MM

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.20 MM

PP5VRT_S0

=PPVCORE_S0_MCP_VSENSE

=PP3V3_S0_PWRCTL

=PP3V3_S0_ODD

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=3.3V

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_AUDIO

=PP3V3_S0_LCD

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE

PP5VLT_S0

=PPSPD_S0_MEM_A

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_MCP

=PP3V3_S0_SMBUS_MCP_0

=PP5V_S3_P5VLTS0FET

=PP3V3_S0_FET

=PP5V_S0_LPCPLUS

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_MCPDDRISNS

=PP5V_S3_SYSLED

PP18V5_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=18.5V

=PP3V42_G3H_CHGR

=PP3V3_S5_SMC

=PP3V42_G3H_RTC_D

=PP3V3_S0_SMC

=PP5V_S3_1V5S30V75S0 =PP5V_S3_AUDIO

=PP5V_S3_MCPDDRFET

=PP5V_S3_EXTUSB

=PP5V_S3_AUDIO_AMP

=PP5V_S3_CAMERA

=PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_ODD

=PP5V_S3_P5VRTS0FET

=PP5V_S3_DEBUG_ADC_AVDD

=PP5V_S3_VTTCLAMP

=PP5V_S3_REG

=PP1V05_ENET_PHY

=PP1V05_ENET_MCP_RMGT

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V1R1V05_S5

MAKE_BASE=TRUE

=PP1V8_S0_REG

=PP3V3_S5_ROM

=PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_PWRCTL

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_PEX_AVDD0

=PP5V_S0_CPUVTTS0

=PP1V5_S3_REG

MAKE_BASE=TRUE

PP1V5_S3

MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V

=PP1V5_S3_MEM_B

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

=PP3V3_S3_TPAD

=PP3V3_S3_VREFMRGN

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_WLAN

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_A_S3

SYNC_DATE=02/04/2009

Power Aliases

SYNC_MASTER=K24_MLB

24 18

12 11

23 8 17

62 23

23 8 20

23 18

7 32

23 16

20 18

58 26

12 11

57 7

23 22

23 22 21

23 21

21 19 18

23 8

23 22

23 22 14

13 12 11 10

54 53 49

37 36

53 51 49

23 18

48 38

23 22

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

MLB MOUNTING (TO TOPCASE) SCREW HOLES

(870-1820 )

EMI THINBC POGO PINS

EMI TALL POGO PINS

(870-1698 )

EMI IO MEDIUM POGO PINS

FAN STANDOFF

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

HEATSINK STANDOFFS

LVDS CONNECTOR HOLE

BELOW MCP

(870-1794 )

LEFT OF CPU

CPU VCORE ALIASES

MISC MCP79 ALIASES

DP HOTPLUG PULL-DOWN

UNUSED USB PORTS

0 0 1

1 1 1

0 1 0

0 0 0

0 1 1 1 0 0 1 0 1 1 1 0

266

(RSVD)

100

133

333

200

(166)

(400)

BSEL<2..0>

UNUSED CRT & TV-OUT INTERFACE

UNUSED GPU LANES

UNUSED ADDRESS PINS

SO-DIMM ALIASES

DACS ALIASES

PCI-E ALIASES

ABOVE CPU

SMC ALIASES

USB ALIASES

LAN ALIASES

CPU FSB FREQUENCY STRAPS

ETHERNET ALIASES

FSB MHZ

UNUSED FIREWIRE LANE

UNUSED EXPRESS CARD LANE

LVDS ALIASES

BELOW CPU

9 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

USB_MINI_N

USB_CARDREADER_P

USB_EXTC_N

USB_EXCARD_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

PCIE_CLK100M_FW_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_PRSNT_L

FW_PME_L

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_P

GMUX_JTAG_TDO

GMUX_JTAG_TCK_L

CPU_PECI_MCP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATA_N3

PM_SLP_RMGT_L

MAKE_BASE=TRUE

RTL8211_VDDREG

MAKE_BASE=TRUE

=P3V3ENET_EN

=PP3V3_ENET_PHY_VDDREG

TP_RTL8211_CLK125

LVDS_IG_A_DATA_P<3>

RTL8211_CLK125

MAKE_BASE=TRUE

MEM_B_A<15>

=P1V05ENET_EN

=RTL8211_REGOUT

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

MAKE_BASE=TRUE

CPU_BSEL<0:2>

USB_EXTD_P

USB_EXCARD_P

USB_MINI_P

USB_EXTD_N

TP_USB_CARDREADER_P

MAKE_BASE=TRUE

TP_USB_IR_P

MAKE_BASE=TRUE

TP_USB_CARDREADER_N

MAKE_BASE=TRUE

TP_USB_EXTC_N

CRT_IG_VSYNC

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_N

MAKE_BASE=TRUE

CARDREADER_RESET

TP_CARDREADER_RESET

MAKE_BASE=TRUE

GMUX_JTAG_TMS

MCP_GPIO_4

MAKE_BASE=TRUE

MIKEY_MIC_LOAD_DET

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<3:0>

GMUX_JTAG_TDI

TP_USB_EXTC_P

MAKE_BASE=TRUE

TP_USB_EXTD_N

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_IG_B_DATA_N<3:0>

TP_USB_EXCARD_P

MAKE_BASE=TRUE

TP_USB_EXCARD_N

TP_USB_MINI_N

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

MAKE_BASE=TRUE

=PEG_D2R_P<15:0>

=PEG_D2R_N<15:0>

=PEG_R2D_C_N<15:0>

=PEG_R2D_C_P<15:0>

MAKE_BASE=TRUE

TP_FW_PME_L

IMVP6_NTC

TP_IMVP6_NTC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_B_COMP_PB

IMVP6_VR_TT

TP_SMC_SYS_KBDLED

MAKE_BASE=TRUE

SMC_SYS_KBDLED

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_P

USB_EXTC_P

NC_LVDS_IG_A_DATA_P3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_P

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15:0>

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_N

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_R2D_C_N

MAKE_BASE=TRUE

TP_PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_P

TP_PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

PCIE_EXCARD_R2D_C_P

PEG_CLK100M_N

=MCP_MII_RXER

NC_LVDS_IG_B_DATA_P<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

=MCP_MII_COL

PEG_CLK100M_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

TP_MEM_A_A15

MAKE_BASE=TRUE

TP_MEM_B_A15

MCP_TV_DAC_VREF

MCP_CLK27M_XTALOUT

MEM_A_A<15>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_TV_DAC_VREF

MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_TV_DAC_RSET

TP_PEG_PRSNT_L

MAKE_BASE=TRUE

MCP_CLK27M_XTALIN

MCP_MII_PD

MAKE_BASE=TRUE

=MCP_MII_CRS

NC_PEG_D2R_N<15:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

PEG_PRSNT_L

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDI

MAKE_BASE=TRUE

TP_GMUX_JTAG_TCK_L

=DVI_HPD_GMUX_INT

PCIE_CLK100M_FW_N

HPLUG_DET2

MAKE_BASE=TRUE

=MCP_BSEL<0:2>

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

TP_EXCARD_CLKREQ_L

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_N

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_N

TP_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

TP_IMVP6_VR_TT

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDO

MAKE_BASE=TRUE

TP_GMUX_JTAG_TMS

MAKE_BASE=TRUE

TP_USB_MINI_P

=RTL8211_ENSWREG

FW_CLKREQ_L

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_P

TP_FW_CLKREQ_L

MAKE_BASE=TRUE

TP_USB_IR_N

MAKE_BASE=TRUE

USB_IR_N

USB_CARDREADER_N

USB_IR_P

MAKE_BASE=TRUE

TP_USB_EXTD_P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_N

SYNC_DATE=02/04/2009

SIGNAL ALIAS

SYNC_MASTER=K24_MLB

NOSTUFF

2.0DIA-MLB-THIN-BC-K84

ZS0920

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0919

OMIT

2.0DIA-MLB-THIN-BC-K84

ZS0918

OMIT

2.0DIA-MLB-THIN-BC-K84

ZS0917

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0912

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0913

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0914

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0915

OMIT

2.0DIA-MLB-THIN-BC-K84

ZS0916

OMIT

3P2R2P7

Z0905

OMIT

3P2R2P7

Z0913

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0911

OMIT

2.0DIA-MED-EMI-MLB-K84

ZS0909

OMIT

2.0DIA-MED-EMI-MLB-K84

ZS0908

OMIT

2.0DIA-MED-EMI-MLB-K84

ZS0903

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0902

OMIT

2.0DIA-MED-EMI-MLB-K84

ZS0901

OMIT

2.0DIA-MED-EMI-MLB-K84

ZS0900

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0910

402

MF-LF

5% 1/16W

R0931

OMIT

3P2R2P7

Z0906

3P2R2P7

OMIT

Z0907

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0907

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0904

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0906

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0905

OMIT

3P2R2P7

Z0910

402

20K

1/16W

5% MF-LF

R0940

70 10 14

1/16W

402

47K

MF-LF

R0930

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0904

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0901

OMIT

3P2R2P7

Z0911

73 20

72 17

21 32

21 54

72 17

73 20

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI BI BI BI BI

OUT

IN IN IN IN IN

IN IN

OUT

IN IN

OUT

BI BI BI BI

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

CPU JTAG Support

PLACEMENT_NOTE (all 4 resistors):

10 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

XDP_TDI

XDP_TDO

XDP_TMS

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1>

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

TP_CPU_TEST5

TP_CPU_TEST3

TP_CPU_TEST6

TP_CPU_TEST7

FSB_CPUSLP_L CPU_PSI_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_N<3> FSB_DSTB_L_P<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

XDP_TRST_L

XDP_TCK

CPU_GTLREF CPU_TEST1 CPU_TEST2

CPU_TEST4

CPU_COMP<1>

CPU_COMP<0>

CPU_COMP<2> CPU_COMP<3>

=PP1V05_S0_CPU

FSB_LOCK_L

CPU_INIT_L

FSB_A_L<3> FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD_B2

TP_CPU_RSVD_V3

TP_CPU_RSVD_T2

TP_CPU_RSVD_N5

TP_CPU_RSVD_M4

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

CPU_THERMD_N

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_A20M_L CPU_FERR_L CPU_IGNNE_L

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

FSB_A_L<6>

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

CPU FSB

FCBGA

OMIT

PENRYN

U1000

AA4

AB2

AA3

A22

A21

AD4

AD3

AD1

AC4

C20

F21

D20

AC2

AC1

D21

D22

AC5

AA6

AB3

A24

B25

AB5

AB6

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

54.9

1/16W MF-LF

402

R1092

1 2

FCBGA

PENRYN

OMIT

U1000

B22

B23

C21

R26

U26

AA1

E22

F24

J24

J23

H22

F26

K22

H23

N22

K25

P26

R23

E26

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

G22

T25

N25

Y22

AB24

V24

V26

V23

T22

U25

U23

F23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

AE24

AD24

G25

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

E25

AC22

AD23

AF22

AC23

E23

K24

G24

H25

N24

U22

AC20

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

C23

D25

C24

AF26

AF1

A26

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

NO STUFF

X5R

0.1uF

10% 16V

402

C1014

402

MF-LF

5% 1/16W

NO STUFF

R1012

MF-LF

1/16W

649

402

R1094

1 2

70 14

MF-LF

1/16W

54.9

402

R1093

1 2

MF-LF

1/16W

54.9

402

R1091

1 2

54.9

1/16W MF-LF

402

R1090

1 2

54.9

402

MF-LF

1/16W

R1001

NO STUFF

1/16W

MF-LF

402

R1011

NO STUFF

MF-LF

1/16W

402

R1010

1 2

70 14

76 42

70 13 10

70 14

70 14 13

70 14

70 37 14

76 42

70 37 14

25 13

70 13 10

70 13

70 14

70 9

70 14

70 14 13

70 14

70 59 14

70 14

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

R1020

Place within 12.7mm of CPU

402

MF-LF

1/16W

54.9

R1021

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

R1022

Place within 12.7mm of CPU

54.9

1% 1/16W MF-LF

402

R1023

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

MF-LF

2.0K

1/16W

402

R1006

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

402

MF-LF

1% 1/16W

R1005

5% 1/16W MF-LF

402

R1002

1% 1/16W

54.9

MF-LF

402

R1000

70 13 10

70 26

13 12 11 8

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

2500 mA (after VCC stable)

4500 mA (before VCC stable)

(Socket-P KEY)

41 A (SV HFM)

130 mA

(CPU CORE POWER)

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

23 A (LV Design Target)

44 A (SV Design Target)

(BR1#)

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

30.4 A (SV LFM)

11 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VCCSENSE_N

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

CPU Power & Ground

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

1/16W

100

402

MF-LF

R1100

OMIT

PENRYN

FCBGA

U1000

B11

W23

W26

Y21

Y24

AA2

AA5

B13

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

B16

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

B19

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

B21

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

B24

AE19

AE23

AE26

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

C11

C14

A11

C16

C19

C22

C25

D11

D13

A14

D16

D19

D23

D26

E11

E14

E16

A16

E19

E21

E24

F11

F13

F16

F19

A19

F22

F25

G23

G26

H21

H24

A23

J22

J25

K23

K26

AF2

L21

L24

M22

M25

N23

N26

P21

P24

R22

R25

T23

T26

U21

U24

V22

V25

PENRYN

OMIT

FCBGA

U1000

B10

B12

B14

B15

B17

B18

B20

C10

A10

C12

C13

C15

C17

C18

D10

D12

D14

D15

A12

D17

D18

E10

E12

E13

E15

E17

E18

A13

E20

F10

F12

F14

F15

F17

F18

F20

A15

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

A17

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

A18

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

A20

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

B26

C26

G21

R21

T21

V21

W21

J21

K21

M21

N21

AF7

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AE7

70 59

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

1/16W

100

402

MF-LF

R1101

70 59

12 11 8

12 8

13 12 10 8

12 11 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

PLACEMENT_NOTE (C1200-C1219):

1x 10uF, 1x 0.01uF

1x 330uF, 6x 0.1uF 0402

SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231

CPU VCore HF and Bulk Decoupling

REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)

4X 330UF. 20X 22UF 0805

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

PLACEMENT_NOTE (C1240-C1243):

12 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PPVCORE_S0_CPU

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU Decoupling

SYNC_DATE=03/30/2009

SYNC_MASTER=K24_MLB

Place on secondary side.

CRITICAL

D2T-SM

470UF-4MOHM

2.0V

20%

POLY-TANT

C1243

CRITICAL

470UF-4MOHM

Place on secondary side.

D2T-SM

POLY-TANT

20%

2.0V

C1242

470UF-4MOHM

CRITICAL

Place on secondary side.

D2T-SM

20%

2.0V POLY-TANT

C1241

Place on secondary side.

470UF-4MOHM

CRITICAL

NOSTUFF

20%

D2T-SM

POLY-TANT

2.0V

C1240

6.3V

10uF

603

X5R

20%

C1250

16V

PLACEMENT_NOTE=Place C1281 near CPU pin B26.

10%

402

CERM

0.01UF

C1251

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1218

10V

402

0.1UF

CERM

20%

C1266

0.1UF

CERM

10V

402

20%

C1265

10V

402

0.1UF

CERM

20%

C1264

402

CERM

10V

0.1UF

20%

C1263

10V

402

0.1UF

CERM

20%

C1262

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1217

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1215

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1209

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1205

10V

402

0.1UF

20%

CERM

C1261

CRITICAL

6.3V

Place inside socket cavity on secondary side.

CERM-X5R

20%

805

22UF

C1210

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1200

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1219

CERM-X5R

6.3V

20%

805

22UF

CRITICAL

Place inside socket cavity on secondary side.

C1211

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1212

CRITICAL

Place inside socket cavity on secondary side.

22UF

805

20%

6.3V CERM-X5R

C1213

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1201

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1202

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1207

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1203

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1208

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1214

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1216

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1204

330UF

20%

2.5V TANT CASE-B2-SM

CRITICAL

C1260

CRITICAL

CERM-X5R

6.3V

20%

22UF

Place inside socket cavity on secondary side.

805

C1206

11 8

13 11 10 8

BI BI

OUT

IN IN

OUT

OUT OUT

BI BI

OUT

IN IN

OUT OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

(998-2515)

518S0774

SDA

TCK1

OBSDATA_B3

OBSFN_C1

OBSDATA_A1

OBSDATA_B1

OBSDATA_B2

VCC_OBS_AB

HOOK3

ITPCLK#/HOOK5

RESET#/HOOK6

MCP79-specific pinout

OBSDATA_C3

OBSDATA_D2 OBSDATA_D3

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

OBSDATA_C2

TRSTn

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

DBR#/HOOK7

TDO

HOOK2

OBSDATA_D0

VCC_OBS_CD

Direction of XDP module

OBSDATA_A2

OBSFN_A1

OBSDATA_A0

OBSFN_B1

OBSDATA_D1

ITPCLK/HOOK4

XDP_PRESENT#

OBSFN_D1

TMS

HOOK1

SCL

OBSFN_D0

Please avoid any obstructions

OBSFN_C0

TCK0

PWRGD/HOOK0

OBSDATA_C1

TDI

OBSDATA_C0

OBSDATA_A3

OBSFN_B0

OBSDATA_B0

OBSFN_A0

ON ODD-NUMBERED SIDE OF J1300

13 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

CPU_PWRGD

FSB_CPURST_L

XDP_DBRESET_L

XDP_TDO

XDP_TRST_L

XDP_TMS

XDP_TDI

JTAG_MCP_TDO

MCP_DEBUG<0>

MCP_DEBUG<3>

JTAG_MCP_TDI

MCP_DEBUG<4>

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_PWRGD

TP_XDP_OBSDATA_B3

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

XDP_BPM_L<1>

XDP_BPM_L<3> XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_BPM_L<5>

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

FSB_CLK_ITP_P

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TMS

TP_XDP_OBSFN_B0

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

TP_XDP_OBSFN_B1

XDP_BPM_L<0>

=PP1V05_S0_CPU

JTAG_MCP_TRST_L

=PP3V3_S0_XDP

MCP_DEBUG<1>

MCP_DEBUG<2>

TP_XDP_OBSDATA_B2

XDP_OBS20

eXtended Debug Port(MiniXDP)

SYNC_MASTER=K24_MLB

SYNC_DATE=02/25/2009

OMIT

CRITICAL

F-ST-SM

DF40C-60DS-0.4V

J1300

10 11 12 13 14 15 16 17 18 19

20 21 22 23 24 25 26 27 28 29

30 31 32 33 34 35 36 37 38 39

40 41 42 43 44 45 46 47 48 49

50 51 52 53 54 55 56 57 58 59

7 8 9

70 10

25 10

70 10

70 14

73 19

70 10

1/16W

XDP

MF-LF

402

PLACEMENT_NOTE=Place close to CPU to minimize stub.

R1303

1 2

70 14 10

70 10

402

16V

XDP

0.1uF

10%

X5R

C1301

X5R

10% 16V

0.1uF

402

XDP

C1300

402

1/16W

54.9

MF-LF

XDP

R1315

73 39 21

1/16W

XDP

MF-LF

402

R1399

1 2

70 14 10

12 11 10 8

IN IN IN

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI BI BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

BI BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Loop-back clock for delay matching.

(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)

20 mA 29 mA 15 mA

206 mA

270 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

14 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PM_THRMTRIP_L

FSB_D_L<13>

MCP_BCLK_VML_COMP_GND

FSB_DPWR_L

CPU_DPSLP_L

FSB_D_L<38>

FSB_D_L<43>

FSB_D_L<45>

CPU_DPRSTP_L

CPU_STPCLK_L

FSB_CPUSLP_L

FSB_CPURST_L

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_A20M_L

FSB_CLK_MCP_P FSB_CLK_MCP_N

FSB_CLK_ITP_N

FSB_CLK_ITP_P

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_DEFER_L

FSB_BPRI_L

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

MCP_CPU_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<2>

FSB_RS_L<1>

CPU_PROCHOT_L

CPU_PECI_MCP

FSB_TRDY_L

FSB_LOCK_L

FSB_HITM_L

FSB_HIT_L

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_ADSTB_L<0>

FSB_A_L<35>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

=PP1V05_S0_MCP_FSB

PP1V05_S0_MCP_PLL_FSB

FSB_D_L<14>

FSB_D_L<7>

FSB_A_L<10>

FSB_A_L<25>

FSB_A_L<34>

FSB_A_L<33>

FSB_DBSY_L FSB_DRDY_L

FSB_BNR_L

FSB_RS_L<0>

CPU_FERR_L

FSB_BREQ0_L

FSB_ADS_L

FSB_BREQ1_L

=PP1V05_S0_MCP_FSB

=MCP_BSEL<2>

=MCP_BSEL<0>

=MCP_BSEL<1>

SYNC_MASTER=K24_MLB

MCP CPU Interface

SYNC_DATE=04/06/2009

MF-LF 402

1/16W

R1416

BGA

(1 OF 11)

MCP79-TOPO-B

OMIT

U1400

AK41

AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35

AG35

AG39

AE33

AG37

AG38

AG34

AN38

AL39

AG33

AL33

AF41

AJ33

AN36

AJ35

AJ37

AJ36

AJ38

AL37

AL34

AN37

AC34

AJ34

AL38

AL35

AN34

AR39

AN35

AE38

AE34

AC37

AE37

AE35

AB35

AD42

AE36

AK35

AD43

AA41

AE40

AL32

F41

D42

F42

AM42

AM43

Y43

W42

R42

T39

T42

T41

R41

T43

W35

AA37

W33

W34

Y40

AA36

AA34

AA38

AA35

U38

U36

U35

U33

U34

W38

W41

R33

U37

N34

N33

R34

R35

P35

R39

R37

R38

Y39

L37

L39

L38

N36

N38

J39

J38

J37

L42

M42

V42

P41

N41

N40

M40

H40

K42

H41

L41

H43

H42

Y41

K41

J40

H39

M43

Y42

P42

U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33

AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42

AD40

AH39

AH42

AF42

AC43

AG41

E41

AJ41

AH43

AC38

AA33

AC39

AC33

AC35

H38

AC41

AB41

AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

MF-LF 402

1/16W

150

NO STUFF

R1440

54.9

MF-LF

402

1/16W

R1410

MF-LF

402

1/16W

R1415

1/16W

NO STUFF

MF-LF

402

R1420

1/16W

MF-LF

402

NO STUFF

R1421

MF-LF

1/16W

402

NO STUFF

R1422

MF-LF 402

1% 1/16W

49.9

R1435

1/16W

402

MF-LF

49.9

R1430

49.9

MF-LF

402

1/16W

R1431

MF-LF 402

1% 1/16W

49.9

R1436

70 10

70 37 10

70 59 10

70 10

70 13 10

70 10

70 13

70 10

70 13 10

70 10

23 22 14 8 23

23 22 14 8

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI BI BI BI

BI BI

BI BI BI

BI BI BI BI BI BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MEMORY

CONTROL

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI BI BI

BI BI BI BI BI BI

BI BI BI

BI BI BI BI BI BI

OUT

OUT OUT OUT OUT OUT OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

15 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

TP_MEM_B_CLK2P

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MCP Memory Interface

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

71 28

(3 OF 11)

OMIT

MCP79-TOPO-B

BGA

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

71 28

71 27

(2 OF 11)

OMIT

MCP79-TOPO-B

BGA

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

4771 mA (A01, DDR3)

17 mA 12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA

TP or NC for DDR2.

39 mA

87 mA (A01)

16 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_MEM_B_CKE<3>

TP_MEM_B_CKE<2>

TP_MEM_B_CS_L<2>

MCP_MEM_RESET_L

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_COMP_GND

TP_MEM_A_CLK4N

TP_MEM_A_CLK3P

TP_MEM_A_ODT<2> TP_MEM_A_ODT<3>

TP_MEM_A_CKE<2> TP_MEM_A_CKE<3>

TP_MEM_A_CLK5P TP_MEM_A_CLK5N

TP_MEM_A_CLK4P

TP_MEM_A_CLK3N

TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3>

PP1V05_S0_MCP_PLL_CORE

TP_MEM_B_CLK5P TP_MEM_B_CLK5N

TP_MEM_B_CLK4P TP_MEM_B_CLK4N

TP_MEM_B_CLK3P TP_MEM_B_CLK3N

TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2> TP_MEM_B_ODT<3>

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_COMP_VDD

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

MCP Memory Misc

BGA

OMIT

MCP79-TOPO-B

(4 OF 11)

U1400

AA22

AA39

AB22

AB7

AD22

AE20

AF24

AG24

AH35

AK7

AM28

AP12

AT25

AP30

AR36

AU10

F28

BC21

AY9

BC9

D34

F24

G30

G32

H31

M38

N39

P10

P33

P34

P37

P40

R36

R40

R43

T10

T18

T20

AK11

T24

T26

T33

T34

T35

T37

T38

U18

U20

U22

V10

V34

AV23

AN25

BA30

BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17

AR15

BC16

BA13

AM41

AN41

AN17

AN15

AY16

BC13

AY32

U27

U28

T27

T28

AM17

AN20

AN24

AT17

AP16

AN22

AP20

AP24

AV16

AR16

AR20

AM19

AR24

AW15

AP22

AP18

AU16

AN18

AU24

AT21

AY29

AV24

AM21

AU20

AU22

AW27

BC17

AV20

AY17

AY18

AM15

AU18

AY25

AM23

AY26

AW19

AW24

BC25

AL30

AM31

AM25

AM27

AM29

AN16

BC29

40.2

1/16W

402

MF-LF

R1611

MF-LF

402

1/16W

40.2

R1610

23 16 8

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

OUT

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Int PU (S5)

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU

84 mA (A01)

Int PU

57 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

17 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

PCIE_MINI_PRSNT_L

FW_CLKREQ_L

TP_PE4_CLKREQ_L TP_PE4_PRSNT_L

PCIE_FW_PRSNT_L

CARDREADER_RESET GMUX_JTAG_TDO

PCIE_WAKE_L

PCIE_MINI_D2R_P PCIE_MINI_D2R_N

PCIE_FW_D2R_P PCIE_FW_D2R_N

TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN

PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N

=PP1V05_S0_MCP_PEX_DVDD0

GMUX_JTAG_TCK_L

AUD_IP_PERIPHERAL_DET

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_P

=PEG_D2R_N<1>

=PEG_D2R_P<1>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_P<5>

=PEG_D2R_P<3>

=PEG_D2R_N<7>

=PEG_D2R_N<6> =PEG_D2R_P<7>

=PEG_D2R_N<5>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_P<10>

=PEG_D2R_P<9>

=PEG_D2R_P<8>

=PEG_D2R_N<10>

=PEG_D2R_N<12>

=PEG_D2R_N<11>

=PEG_D2R_P<13>

=PEG_D2R_P<11>

=PEG_D2R_P<12>

=PEG_D2R_N<15>

=PEG_D2R_N<14> =PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_N<13>

PEG_PRSNT_L

MCP_PEX_CLK_COMP

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1> =PEG_R2D_C_N<1>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<2> =PEG_R2D_C_N<2>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3> =PEG_R2D_C_N<3>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<6> =PEG_R2D_C_P<7> =PEG_R2D_C_N<7>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<10> =PEG_R2D_C_N<10>

=PEG_R2D_C_P<12> =PEG_R2D_C_N<12>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

PCIE_CLK100M_MINI_P

PEG_CLK100M_P PEG_CLK100M_N

PCIE_CLK100M_FW_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N

PCIE_MINI_R2D_C_P

PCIE_RESET_L

TP_PCIE_CLK100M_PE6N

PCIE_FW_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2>

=PEG_D2R_N<0>

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<2>

=PEG_D2R_P<0>

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

MINI_CLKREQ_L

PCIE_EXCARD_PRSNT_L

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

SYNC_DATE=04/06/2009

MCP PCIe Interfaces

SYNC_MASTER=K24_MLB

PLACEMENT_NOTE=Place within 12.7mm of U1400

NO STUFF

1/16W

MF-LF 402

2.37K

R1710

72 30

72 9

72 30

72 9

30 7

72 30

BGA

OMIT

(5 OF 11)

MCP79-TOPO-B

U1400

Y12

AC12

AD12

V12

W12

AA12

AB12

M12

P12

R12

N12

T12

U12

M13

N13

P13

T17

W19

U17

V19

W16

W17

W18

U16

T19

U19

T16

D11

E11

N10

N11

L10

L11

F11

G11

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

C10

M15

B10

L16

L18

M16

M18

M17

M19

A11

K11

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

OUT

IN IN IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

In MCP79 these pins have undocumented internal

GPIOs 57-59 (if LCD panel is used):

by default, pull-downs (1K or stronger) must be used.

pull-ups (~10K to 3.3V S0). To ensure pins are low

Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.

=DVI_HPD_GMUX_INT:

Alias to DVI_HPD for systems using IFP for DVI.

(See below)

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: 20K pull-down required on DP_HPD_DET.

level-shifters.

NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without

Interface Mode

DP_IG_ML_P/N<0>

DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

131 mA (A01)

83 mA (A01)

MII, RGMII products will enable

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

RGB DAC Disable:

TV / Component

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

LVDS: Power +VDD_IFPx at 1.8V

95 mA (A01)

16 mA (A01)

8 mA

DP_IG_AUX_CH_P/N

=MCP_HDMI_HPD

TMDS_IG_HPD

=MCP_HDMI_DDC_DATA

=MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_TXD_P/N<1>

=MCP_HDMI_DDC_CLK

MCP Signal

=MCP_HDMI_TXD_P/N<0>

=MCP_HDMI_TXC_P/N

TMDS/HDMI

TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2>

TMDS_IG_DDC_DATA

TP_DP_IG_AUX_CHP/N

DP_IG_DDC_CLK

DP_IG_ML_P/N<2> DP_IG_ML_P/N<1>

DP_IG_ML_P/N<3>

DisplayPort

5 mA (A01)

RGB ONLY

avoids a leakage issue since

feature via software. This

NOTE: All Apple products set strap to

Network Interface Select

Interface

RGMII

MII

ENET_TXD<0>

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all TV_DAC signals.

TV DAC Disable:

Y / Y

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all RGB_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.

103 mA 103 mA

206 mA (A01)

Comp / Pb

MCP79 requires a S5 pull-up.

C / Pr

190 mA (A01, 1.8V)

18 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=DVI_HPD_GMUX_INT

LVDS_IG_BKL_PWM

MCP_CLK27M_XTALOUT

TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF

LPCPLUS_GPIO

=PP1V05_ENET_MCP_RMGT

=PP3V3_S5_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>

ENET_CLK125M_TXCLK ENET_TX_CTRL

MCP_MII_VREF

CRT_IG_VSYNC

CRT_IG_HSYNC

CRT_IG_B_COMP_PB

=MCP_MII_CRS

=MCP_MII_COL

=MCP_MII_RXER

TP_ENET_PWRDWN_L

ENET_MDC

ENET_RESET_L

ENET_RXD<1> ENET_RXD<2>

ENET_CLK125M_RXCLK ENET_RX_CTRL

ENET_RXD<3>

TP_ENET_INTR_L

ENET_RXD<0>

MCP_TV_DAC_RSET

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_CLK_N

LVDS_IG_B_CLK_P

LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_CLK_P

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_MCP_RGB_BLUE

TP_MCP_RGB_GREEN

TP_MCP_RGB_RED

MCP_DDC_CLK0 MCP_DDC_DATA0

MCP_CLK25M_BUF0_R

ENET_MDIO

=MCP_HDMI_HPD

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

MCP_TV_DAC_VREF

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

MCP_CLK27M_XTALIN

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXC_P

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

MCP_MII_COMP_VDD MCP_MII_COMP_GND

PP3V3_S0_MCP_DAC

=PP3V3R1V8_S0_MCP_IFP_VDD

PP3V3_S0_MCP_VPLL

=PP1V05_S0_MCP_HDMI_VDD

PP1V05_ENET_MCP_PLL_MAC

DP_IG_CA_DET

MCP_HDMI_VPROBE

MCP_HDMI_RSET

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_CLK_N

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_N<0>

MCP Ethernet & Graphics

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

74 31

72 24

74 31

72 24

65 7

74 31

72 65 7

74 31

72 65 7

72 65

74 31

1/16W MF-LF

402

47K

R1820

100K

1/16W

MF-LF

402

R1860

MF-LF

1/16W

100K

402

R1861

MF-LF

5% 1/16W

402

10K

R1850

OMIT

MCP79-TOPO-B

BGA

(6 OF 11)

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16

B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31

F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32

G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39

E37

F40

B26

B27

C27

B22

J23

F23

E28

J24

K24

T23

U23

V23

M29

M28

J32

K32

T25

M27

M26

B40

A39

A40

B39

C39

B38

A41

J22

D21

C21

G23

A23

C22

C23

B23

E24

A24

D24

C26

B24

C24

C25

D25

C36

B36

D36

A36

E36

A35

C37

C38

D38

402

49.9

MF-LF

1/16W

R1811

49.9

402

MF-LF

1/16W

R1810

72 24

72 66

69 68

74 31

74 32

74 31

23 8

20 8

23 18 8

21 19 8

23 18 8

24 8

OUT

BI BI BI BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

19 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

FW_PWR_EN

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

TP_PCI_GNT0_L TP_PCI_GNT1_L

MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0> TP_PCI_C_BE_L<1> TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR

TP_PCI_SERR_L TP_PCI_STOP_L

TP_PCI_RESET1_L

TP_PCI_CLK0

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

LPC_RESET_L

LPC_PWRDWN_L

PCI_CLK33M_MCP_R

TP_PCI_CLK1

PCI_CLK33M_MCP

MEM_VTT_EN_R

TP_PCI_PERR_L

TP_PCI_AD<10>

TP_PCI_AD<8>

PCI_REQ1_L

PCI_REQ0_L

TP_PCI_INTY_L

TP_PCI_INTW_L

TP_PCI_AD<31>

TP_PCI_AD<30>

TP_PCI_AD<29>

TP_PCI_AD<28>

TP_PCI_AD<27>

TP_PCI_AD<25>

TP_PCI_AD<22>

TP_PCI_AD<19>

TP_PCI_AD<18>

TP_PCI_AD<17>

TP_PCI_AD<16>

TP_PCI_AD<12>

FW_PWR_EN AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L

MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3>

MCP_DEBUG<6> MCP_DEBUG<7>

MCP_RS232_SIN_L

=PP3V3_S0_MCP_GPIO

PM_CLKRUN_L

TP_LPC_DRQ0_L

FW_PME_L

TP_PCI_INTZ_L

GMUX_JTAG_TMS GMUX_JTAG_TDI

TP_PCI_AD<13>

TP_PCI_AD<11>

PM_LATRIGGER_L

TP_PCI_AD<26>

TP_PCI_AD<24>

TP_PCI_AD<23>

MCP_DEBUG<4> MCP_DEBUG<5>

TP_PCI_AD<9>

TP_PCI_AD<15>

TP_PCI_AD<20>

LPC_SERIRQ

TP_PCI_TRDY_L

TP_PCI_INTX_L

TP_PCI_AD<21>

TP_PCI_AD<14>

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

MCP PCI & LPC

73 13

1/16W MF-LF

402

R1953

1 2

402

MF-LF1/16W

R1952

1 2

402

MF-LF1/16W

R1951

1 2

402

MF-LF1/16W

R1950

1 2

402

MF-LF1/16W

R1960

1 2

10K

5% 1/16W

402

MF-LF

R1961

402

MF-LF1/16W

8.2K

R1992

1 2

8.2K

1/16W MF-LF

402

R1994

1 2

8.2K

1/16W MF-LF

402

R1990

1 2

8.2K

1/16W MF-LF

402

R1991

1 2

8.2K

1/16W MF-LF

402

R1989

1 2

5% 1/16W

402

MF-LF

PLACEMENT_NOTE=Place close to pin R8

R1910

38 36

73 25 38 36

38 36

OMIT

MCP79-TOPO-B

(7 OF 11)

BGA

U1400

AB18

H34

AB20

AB21

AB23

AB24

AB25

AB26

AB27

AB28

AB34

AB37

AB4

AB40

AC22

AC36

AC40

AB33

AC5

AD16

AD17

AD18

AD19

AD20

AD24

AD25

AD26

AD27

AD28

AD33

AD34

U24

U26

U39

V16

V17

V18

V20

V22

V24

V26

V27

V28

V33

V37

V40

W20

W22

W24

W36

W40

W43

Y16

Y17

Y18

Y19

Y20

Y22

Y24

Y25

Y26

Y27

AD3

AD2

AD1

AD5

AE9

AE1

AE2

AD4

AE12

AE5

AE6

AC3

AE10

AC9

AC10

AC11

AA1

AA5

AC4

W11

AE11

AB3

AC6

AB2

AC7

AC8

AA2

AA3

AA6

AA11

W10

AD11

AA9

U10

U11

AA10

AB9

R10

R11

AA7

73 38 36

73 25

73 38 36

73 19

21 18 8

BI BI

IN IN IN IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT OUT

IN IN

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

ExpressCard

Bluetooth

External B

External C

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)

43 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

External D

External A

Camera

84 mA (A01)

19 mA (A01)

AirPort (PCIe Mini-Card)

Geyser Trackpad/Keyboard

20 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_USB_10N

USB_BT_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTD_P

USB_MINI_N

USB_MINI_P

USB_EXTA_N

USB_EXTA_P

TP_SATA_D_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN TP_SATA_E_D2RP

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

TP_MCP_SATALED_L

TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN

TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN

TP_SATA_F_D2RN TP_SATA_F_D2RP

MCP_SATA_TERMP

USB_EXTD_N

USB_IR_N

USB_TPAD_P

PP1V05_S0_MCP_PLL_SATA

TP_SATA_C_D2RN TP_SATA_C_D2RP

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N

SATA_ODD_D2R_N SATA_ODD_D2R_P

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

USB_EXTC_OC_L EXCARD_OC_L

USB_EXTB_OC_L

USB_EXTA_OC_L

USB_EXTB_N

USB_EXTB_P

USB_EXCARD_P USB_EXCARD_N

TP_USB_10P

USB_EXTC_N

USB_EXTC_P

USB_CARDREADER_P USB_CARDREADER_N

SYNC_MASTER=K24_MLB

MCP SATA & USB

SYNC_DATE=04/06/2009

73 9

72 34

OMIT

(8 OF 11)

BGA

MCP79-TOPO-B

U1400

AD35

AD37

AD38

AE22

AE24

AE39

AE4

AD6

AF16

AF17

AF18

AF20

AF22

AF26

AF27

AF28

AF33

AF34

AF37

AF40

AG18

AG20

AG22

AG26

AG36

AG40

AH18

AH20

AH22

AH24

AJ12

AN11

AK12

AK13

AL12

AM11

AM12

AN12

AL13

AN14

AL14

AM13

AM14

AF19

AG16

AG17

AG19

AH17

AH19

AE16

L28

AJ5

AJ4

AJ6

AJ7

AJ9

AK9

AJ10

AJ11

AJ2

AJ1

AJ3

AK2

AL4

AK3

AL3

AM4

AM2

AM3

AM1

AN1

AN3

AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21

K21

J21

H21

A27

402

1/16W MF-LF

8.2K

R2050

8.2K

1/16W

402

MF-LF

R2051

402

1/16W MF-LF

8.2K

R2052

8.2K

MF-LF

1/16W

402

R2053

806

MF-LF

1/16W

402

R2060

MF-LF

1% 1/16W

402

2.49K

R2010

73 35

73 30

73 44

73 9

73 65

73 35

18 8

OUT

OUT OUT

OUT

IN IN

OUT

IN IN IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID* LLB*

PWRBTN* RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

(MGPIO2)

(MGPIO3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU (S5)

Int PU

25 MHz

42 MHz

LPC ROMs. So Apple designs will

HDA_SYNC

24 MHz

SPI_CLK

SPI_DO

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F

HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

LPC_FRAME#

Int PU

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

(MXM_OK for MXM systems)

SAFE mode: For ROMSIP recovery

USER mode: Normal

Connects to SMC for automatic recovery.

Int PU

21 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP3V3_S0_MCP_GPIO

MCP_GPIO_4 AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L

ARB_DETECT

SPI_CLK_R

RTC_CLK32K_XTALOUT

HDA_SDIN0

SPI_CS0_R_L

SPI_MISO

MCP_HDA_PULLDN_COMP

RTC_RST_L

=PP3V3R1V5_S0_MCP_HDA

MCP_SPKR

=PP3V3_S0_MCP

PM_SLP_S4_L

PM_SLP_S3_L

AUD_I2C_INT_L

HDA_SYNC_R

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

SMC_ADAPTER_EN

SMC_WAKE_SCI_L

MEM_EVENT_L ODD_PWR_EN_L

HDA_RST_R_L

HDA_SYNC

SM_INTRUDER_L

PM_RSMRST_L

JTAG_MCP_TRST_L

MCP_TEST_MODE_EN

JTAG_MCP_TMS

MCP_VID<1> MCP_VID<2>

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDOUT_R

HDA_SYNC_R

PP3V3_G3_RTC

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

TP_MCP_KBDRSTIN_L

PM_SYSRST_DEBOUNCE_L

MCP_THMDIODE_N

SMBUS_MCP_0_CLK

SPI_MOSI_R

PM_CLK32K_SUSCLK_R

JTAG_MCP_TCK

MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

PP1V05_S0_MCP_PLL_NV

TP_SB_A20GATE

PM_SLP_RMGT_L

MCP_VID<1>

SMC_RUNTIME_SCI_L

=SPI_CS1_R_L_USE_MLB

HDA_BIT_CLK_R

HDA_SDOUT_R

PM_BATLOW_L

SMBUS_MCP_0_DATA

MCP_VID<2>

AP_PWR_EN

SMBUS_MCP_1_DATA

JTAG_MCP_TDO

JTAG_MCP_TDI

MCP_PS_PWRGD

PM_PWRBTN_L

TP_MCP_LID_L

SMBUS_MCP_1_CLK

MCP_THMDIODE_P

MCP_VID<0>

MCP_CPUVDD_EN

PM_DPRSLPVR

MCP_VID<0>

MCP_CPU_VLD

=PP3V3_S3_MCP_GPIO

AP_PWR_EN

MCP_GPIO_4

=PP3V3R1V5_S0_MCP_HDA

ARB_DETECT

TP_MCP_BUF_SIO_CLK

SMC_IG_THROTTLE_L

SYNC_MASTER=K24_MLB

SYNC_DATE=03/24/2009

MCP HDA & MISC

73 38

73 48 38

37 21

402

1/16W MF-LF

10K

R2140

MF-LF

10K

1/16W

402

R2143

402

100K

MF-LF

1/16W

R2154

100K

1/16W

MF-LF 402

R2151

MF-LF

22K

1/16W

402

R2155

402

1/16W MF-LF

22K

R2156

402

1/16W MF-LF

22K

R2157

10K

MF-LF

1/16W

402

R2141

MF-LF 402

1/16W

10K

R2142

100K

MF-LF

1/16W

402

R2147

36 28 27 21

37 36 32

25 25

54 21

OMIT

MCP79-TOPO-B

(9 OF 11)

BGA

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17

L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19

F19

J19

J18

L13

M25

M24

L20

M20

M21

J16

K16

AE18

AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15

B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

CERM

402

10PF

50V

C2172

CERM

402

10PF

50V

C2170

CERM 402

10PF

50V

C2173

CERM 402

5% 50V

10PF

C2171

10K

MF-LF

1/16W

402

R2150

402

1% 1/16W MF-LF

49.9

R2110

MF-LF

1/16W

402

R2172

1 2

1/16W

BOOT_MODE_USER

MF-LF 402

10K

R2181

1/16W

402

BOOT_MODE_SAFE

MF-LF

10K

R2180

402

1/16W

8.2K

MF-LF

R2160

1/16W MF-LF

10K

402

R2163

402

1/16W MF-LF

R2173

1 2

402

1/16W

MF-LF

R2171

1 2

1/16W

402

MF-LF

R2170

1 2

73 25

402

1/16W

MF-LF

R2190

1/16W

402

MF-LF

49.9K

R2120

49.9K

402

1% 1/16W MF-LF

R2121

73 49

70 59

76 42

32 30 21

60 21

76 42

60 21

73 39

73 39 13

73 39

73 39 13

63 37 36 7

67 63 36 32 7

73 48 38

19 18 8

21 9

54 21

36 28 27 21

37 21

23 21 8

23 22 8

73 21

60 21

73 21

25 22 7

73 21

60 21

32 30 21

21 9

23 21 8

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

80 uA (S0)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 mA (A01)

22 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP3V3_S5_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

PP3V3_G3_RTC

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

SYNC_DATE=04/06/2009

SYNC_MASTER=K24_MLB

MCP Power & Ground

(10 OF 11)

BGA

MCP79-TOPO-B

OMIT

U1400

AD10

AE8

AB10

AD9

Y10

AB11

AA8

G18

H19

J20

K20

G26

H27

J28

K28

A20

T21

U21

V21

AA25

AA26

AA27

AA28

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC23

AC24

AC25

AC26

AC27

AC28

AD21

AD23

W27

V25

AA18

U25

AE19

AE21

AE23

AE25

AE26

AE27

AE28

AF10

AF11

AA19

AH12

AF2

AF21

AF23

AF25

AF3

AF4

AF7

AH23

AF9

AA20

AG10

AG11

AG12

AG21

AG23

AG25

AG3

AG4

AA21

AG6

AG7

AG5

AG8

AG9

AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

Y21

AH21

AH3

AH4

AH5

AH6

AH7

AH9

AA24

W21

W23

Y23

W25

AF12

AA16

R32

P31

AF32

AE32

AH32

AJ32

AK31

AK32

AD32

AL31

AB32

AC32

B41

B42

C40

C41

C42

D39

D40

D41

E38

E39

E40

F37

F38

F39

G36

G37

G38

H35

H37

J34

J35

J36

K33

K34

K35

L32

L33

L34

M31

M32

M33

N31

N32

P32

Y32

AA32

T32

U32

V32

W32

AG32

BGA

OMIT

MCP79-TOPO-B

(11 OF 11)

U1400

AH26

AH33

AH34

AH37

AH38

AJ39

AJ8

AK10

AK33

AK34

AK37

AK4

AK40

AL36

AL40

AL5

AM10

AM16

AM18

AM20

AM22

AM24

AM26

AM30

AM34

AM35

AM37

AM38

AM5

AM6

AM7

AM9

AP26

AN28

AN30

AN39

AN4

AP10

AU26

AP14

AU14

AP28

AP32

AP34

AP36

AP37

AP4

AP40

AP7

AW23

AR28

AR32

AR40

AT10

AR12

AT13

AT29

AT33

AT6

AT7

AT9

AY21

AY22

L12

AU12

AU28

AP33

AU32

AR30

AU36

AU38

AU4

G28

F20

AV28

AV32

AV36

AV4

AV7

AW11

G20

AR43

AW43

AY10

AV12

AY30

AY33

AY34

AY37

AY38

AY41

AV40

BA1

BA4

AW31

AY6

L35

BC33

BC37

BC41

AY14

BC5

D10

D14

D15

D18

D19

D22

D23

D26

D30

D37

E13

E17

E21

E25

E29

E33

F12

F16

F32

G10

G12

G14

G16

BC12

G22

G24

AW20

G34

G43

H11

H15

AW35

H23

AN8

G40

J12

K10

K12

K18

K26

K37

K40

AU1

L40

L43

M10

M34

M35

M37

Y28

Y33

Y34

Y35

Y37

Y38

AB17

AB16

AN26

AD7

M11

AA4

AB19

AY13

P11

T11

V11

Y11

AH16

T22

23 8

23 21 8

25 21 7

23 8 23 14 8

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

19 mA (A01)

450 mA (A01)

43 mA (A01)

127 mA (A01)

206 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

131 mA (A01)105 mA (A01)

MCP PCIE (DVDD) Power

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

23065 mA (A01, 1.2V)

(No IG vs. EG data)

270 mA (A01)

MCP 3.3V Ethernet Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP 1.05V AUX Power

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP Core Power

4771 mA (A01, DDR3)

333 mA (A01)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

MCP SATA (DVDD) Power

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)

16996 mA (A01, 1.0V)

57 mA (A01)

562 mA (A01)

5 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP 1.05V RMGT Power

Apple: 7x 2.2uF 0402 (15.4 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

25 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_FSB

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_CORE

VOLTAGE=1.05V

PP1V05_S0_MCP_SATA_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_SATA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

=PP3V3_S0_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S5_MCP

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

MCP Standard Decoupling

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

402

20%

4.7UF

X5R-1

C2503

10UF

20%

6.3V X5R 603

C2592

402

20%

X5R-1

4.7UF

C2528

CERM

20%

0.1uF

402

10V

C2529

CERM

20%

0.1UF

402

10V

C2596

20%

CERM

0.1UF

402

10V

C2587

20%

CERM

0.1UF

402

10V

C2585

CERM

20%

402

10V

0.1UF

C2583

10V

402

0.1UF

CERM

20%

C2581

0.1uF

CERM

20%

402

10V

C2519

0.1uF

20%

CERM 402

10V

C2518

CERM

20%

0.1uF

402

10V

C2521

MF-LF

1/16W

1.47K

402

R2591

0.1UF

CERM

20%

402

10V

C2591

1.47K

1/16W

MF-LF

402

R2590

30-OHM-1.7A

0402

L2595

1 2

402

4.7UF

20%

X5R-1

C2595

CERM

0.1UF

20%

402

10V

C2590

CERM

20%

402

10V

0.1UF

C2589

6.3V

2.2UF

20%

402-LF

CERM

C2560

CERM

20%

0.1uF

402

10V

C2525

0.1uF

402

10V

20%

CERM

C2526

30-OHM-1.7A

0402

L2580

1 2

20%

402

4.7UF

X5R-1

C2501

4.7UF

402

20%

X5R-1

C2500

30-OHM-1.7A

0402

L2555

1 2

0402

30-OHM-1.7A

L2586

1 2

30-OHM-1.7A

0402

L2588

1 2

30-OHM-1.7A

0402

L2584

1 2

30-OHM-1.7A

0402

L2582

1 2

30-OHM-5A

0603

L2575

1 2

0603

30-OHM-5A

L2570

1 2

402

20%

4.7UF

X5R-1

C2580

CERM 402-LF

20%

2.2UF

6.3V

C2564

6.3V

2.2UF

20%

402-LF

CERM

C2562

402

4.7UF

20%

X5R-1

C2540

CERM

20%

402

10V

0.1UF

C2541

20%

CERM 402

10V

0.1UF

C2542

0.1UF

20%

CERM 402

10V

C2543

20%

CERM 402

10V

0.1UF

C2544

0.1UF

20%

CERM 402

10V

C2545

0.1UF

20%

CERM 402

10V

C2546

0.1UF

20%

CERM 402

10V

C2547

0.1UF

20%

CERM 402

10V

C2548

0.1UF

20%

CERM 402

10V

C2549

6.3V

2.2UF

20%

402-LF

CERM

C2550

2.2UF

6.3V

20%

402-LF

CERM

C2551

6.3V

2.2UF

20%

402-LF

CERM

C2552

2.2UF

6.3V

20%

402-LF

CERM

C2553

6.3V

2.2UF

20%

CERM 402-LF

C2575

CERM 402-LF

20%

2.2UF

6.3V

C2576

6.3V

2.2UF

20%

402-LF

CERM

C2573

6.3V

2.2UF

20%

402-LF

CERM

C2574

6.3V

2.2UF

20%

402-LF

CERM

C2570

402

20%

4.7UF

X5R-1

C2520

6.3V

2.2UF

20%

402-LF

CERM

C2571

CERM

6.3V

2.2UF

20%

402-LF

C2572

402

20%

4.7UF

X5R-1

C2515

X5R 402-1

1UF

10% 10V

C2516

X5R 402-1

1UF

10% 10V

C2517

6.3V

2.2UF

20%

402-LF

CERM

C2530

20%

2.2UF

6.3V

402-LF

CERM

C2531

6.3V

20%

402-LF

CERM

2.2UF

C2532

6.3V

2.2UF

20%

CERM 402-LF

C2533

2.2UF

6.3V

20%

402-LF

CERM

C2534

6.3V

2.2UF

20%

402-LF

CERM

C2535

2.2UF

20%

402-LF

CERM

6.3V

C2536

0.1UF

CERM

20%

402

10V

C2512

0.1UF

CERM

20%

402

10V

C2513

0.1UF

CERM

20%

402

10V

C2508

0.1UF

CERM

20%

402

10V

C2509

0.1UF

CERM

20%

402

10V

C2510

0.1UF

CERM

20%

402

10V

C2511

X5R 402-1

1UF

10% 10V

C2504

X5R 402-1

1UF

10% 10V

C2505

X5R 402-1

1UF

10% 10V

C2506

X5R 402-1

1UF

10% 10V

C2507

402

20%

4.7UF

X5R-1

C2502

CERM 402-LF

20%

2.2UF

6.3V

C2555

402

20%

4.7UF

X5R-1

C2586

402

20%

4.7UF

X5R-1

C2584

402

4.7UF

20%

X5R-1

C2588

402

20%

4.7UF

X5R-1

C2582

22 8

62 8 14

18 8

23 18 8

22 21 8

21 8

22 8

22 14 8

16 8

18 8

23 18 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

Apple: ???

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

190 mA (A01, 1.8V)

95 mA (A01)

16 mA (A01)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

16 mA (A01)

206 mA (A01)206 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)

REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT

SYNC FROM T18

CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC REMOVE HDCP ROMS

REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

26 OF 109

051-7982

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V05_S0_MCP_HDMI_VDD

MCP_IFPAB_RSET

MCP_HDMI_RSET

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3R1V8_S0_MCP_IFP_VDD

MCP_HDMI_VPROBE

PP3V3_S0_MCP_VPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MCP_IFPAB_VPROBE

VOLTAGE=3.3V

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MCP Graphics Support

SYNC_MASTER=K24_MLB

SYNC_DATE=04/06/2009

CERM 402-LF

20%

2.2UF

6.3V

C2610

402

1/16W

MF-LF

R2620

402

5% 1/16W MF-LF

R2651

402

20%

CERM

0.1UF

10V

C2616

10V

20%

402

CERM

0.1uF

C2641

30-OHM-1.7A

0402

L2640

1 2

CERM

4.7UF

6.3V

20%

603

C2640

X5R-1

402

4.7UF

20%

C2615

20%

402

CERM

NO STUFF

10V

0.1UF

C2630

MF-LF

1/16W

402

NO STUFF

R2630

CERM

10V

20%

0.1UF

NO STUFF

402

C2620

30-OHM-1.7A

0402

NO STUFF

L2650

1 2

6.3V

2.2UF

20%

402-LF

CERM

NO STUFF

C2650

18 8

72 18 72 18

18 8

72 18

+ 53 hidden pages