Texas Instruments CD74HCT4520M96, CD74HCT4520M, CD74HCT4520E, CD74HC4520M96, CD74HC4520M Datasheet

Data sheet acquired from Harris Semiconductor

/
j

SCHS216

November 1997

CD74HC4518, CD74HC4520,

CD74HCT4520

High Speed CMOS Logic

Dual Synchronous Counters

[ /Title
(CD74
HC451
8,
CD74
HC452
0,
CD74
HCT45

20)
Sub­ect

Features

• Positive or Negative Edge Triggering

• Synchronous Internal Carry Propagation

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Description

The Harris CD74HC4518 is a dual BCD up-counter. The
Harris CD74HC4520 and CD74HCT4520 are dual binary
up-counters. Each device consists of two independent
internally synchronous 4-stage counters. The counter stages
are D-type flip-flops having interchangeable CLOCK and
ENABLE lines for incrementing on either the positive-going
or the negative-going transition of CLOCK. The counters are
cleared by high levels on the MASTER RESET lines. The
counter can be cascaded in the ripple mode by connecting
Q

to the ENABLE input of the subsequent counter while the

3

CLOCK input of the latter is held low.

Ordering Information

CC

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4518E -55 to 125 16 Ld PDIP E16.3
CD74HC4520E -55 to 125 16 Ld PDIP E16.3
CD74HCT4520E -55 to 125 16 Ld PDIP E16.3
CD74HC4520M -55 to 125 16 Ld SOIC M16.15
CD74HCT4520M -55 to 125 16 Ld SOIC M16.15

PKG.

NO.

Pinout

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer or diefor this partnumber is availablewhich meets allelec­trical specifications. Please contact your local sales office or
Harris customer service for ordering information.

CD74HC4518

CD74HC4520, CD74HCT4520

(PDIP, SOIC)

TOP VIEW

V

1CP

1E
1Q
1Q
1Q
1Q

1MR

GND

1
2
3

0

4

1

5

2

6

3

7
8

16

2MR

15
14

2Q

13

2Q

12

2Q

11

2Q

10

2E
2CP

9

CC

3
2
1
0

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1665.1

Functional Diagram

NOTE:

H = High State.
L = Low State.

↑ = High-to-Low Transition.
↓ = Low-to-High Transition.

X = Don’t Care.

CD74HC4518, CD74HC4520, CD74HCT4520

R

R

3

1Q

4

1Q

5

1Q

6

1Q

11

2Q

12

2Q

13

2Q

14

2Q

GND = 8
VCC = 16

0

1

2

3

0

1

2

3

thru Q3 = L

0

1CP

1E

1MR

2CP

2E

2MR

1

2

7

9

10

15

÷10/÷16

CL

÷10/÷16

CL

TRUTH TABLE

CP E MR OUTPUT STATE

↑ H L Increment Counter
L ↓ L Increment Counter
↓ X L No Change
X ↑ L No Change
↑ L L No Change
H ↓ L No Change
XXHQ

2

CD74HC4518, CD74HC4520, CD74HCT4520

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC (V)

o

C -40oCTO85oC

25

-55oC TO
125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - -------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - -------V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3

CD74HC4518, CD74HC4520, CD74HCT4520

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to 5.5 2 - - 2 - 2 - V

- - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

V

CC

- 4.5 to 5.5 - 100 360 - 450 - 490 µA

-2.1

o

C -40oCTO85oC

25

V

(V)

CC

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

-55oC TO
125oC

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

MR 1.2
CP 0.25

ENABLE 0.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Prerequisite for Switching Specifications

PARAMETER SYMBOL VCC (V)

HC TYPES

Maximum Clock
Frequency

CP Pulse Width t

MR Pulse Width t

f

MAX

2 6--5-4-MHz

4.5 30 - - 24 - 20 - MHz
6 35 - - 28 - 24 - MHz

W

2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14- -17-20- ns

W

2 100 - - 125 - 150 - ns

4.5 20 - - 25 - 30 - ns
6 17- -21-26- ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC4518, CD74HC4520, CD74HCT4520

Prerequisite for Switching Specifications (Continued)

PARAMETER SYMBOL V

Set-up Time,
Enable to CP

Removal Time,
MR to CP

Set-up Time,
CP to Enable

Removal Time,
MR to Enable

HCT TYPES

Maximum Clock
Frequency

Clock Pulse Width t
MR Pulse Width t
Set-up, Time

Enable to CP
Removal Time,

MR tp Enable

t

SU

t

REM

t

SU

t

REM

f

MAX

t

SU

t

REM

W
W

(V)

CC

2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14- -17-20- ns
2 0--0-0-ns

4.5 0 - - 0 - 0 - ns
6 0--0-0-ns
2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14- -17-20- ns
2 0--0-0-ns

4.5 0 - - 0 - 0 - ns
6 0--0-0-ns

4.5 25 - - 20 - 17 - MHz

4.5 20 - - 25 - 30 - ns

4.5 20 - - 25 - 30 - ns

4.5 16 - - 20 - 24 - ns

4.5 0 - - 0 - 0 - ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

CP to Q

n

Enable to Q

MR to Q

n

n

Output Transition Time t

Input Capacitance C
Maximum Clock Frequency f
Power Dissipation Capacitance

(Note 4, 5)

t

t

THL,tTLHCL

, tf = 6ns

r

PLH,

t

PHL

PLH,

t

PHL

PLH,

t

PHL

IN

MAX

C

PD

-40oC TO

TEST

CONDITIONS V

CC

25oC

(V)

85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CL = 50pF 2 - - 240 - 300 - 360 ns
CL = 50pF 4.5 - - 48 - 60 - 72 ns
CL = 15pF 5 - 20 - - - - - ns
CL = 50pF 6 - - 41 - 51 - 61 ns
CL = 50pF 2 - - 240 - 300 - 360 ns
CL = 50pF 4.5 - - 48 - 60 - 72 ns
CL = 15pF 5 - 20 - - - - - ns
CL = 50pF 6 - - 41 - 51 - 61 ns
CL = 50pF 2 - - 150 - 190 - 225 ns
CL = 50pF 4.5 - - 30 - 38 - 45 ns
CL = 15pF 5 - 12 - - - - - ns
CL = 50pF 6 - - 26 - 33 - 38 ns

= 50pF 2 - - 75 - 95 - 110 ns

CL = 50pF 4.5 - - 15 - 19 - 22 ns
CL = 50pF 6 13 16 19 ns
CL = 50pF - - - 10 - 10 - 10 pF
CL = 15pF 5 60 MHz
CL = 15pF 5 - 33 - - - - - pF

5

CD74HC4518, CD74HC4520, CD74HCT4520

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

CONDITIONS V

CC

(V)

HCT TYPES

Propagation Delay

CP to Q

n

Enable to Q

MR to Q

n

n

Output Transition Time t
Input Capacitance C
Maximum Clock Frequency f
Power Dissipation Capacitance

t

PLH,

t

PHL

t

PLH,

t

PHL

t

PLH,

t

PHL

THL,tTLHCL

IN

MAX

C

PD

CL = 50pF 4.5 - - 53 - 66 - 80 ns
CL = 15pF 5 - 22 - - - - - ns
CL = 50pF 4.5 - - 55 - 69 - 83 ns
CL = 15pF 5 - 23 - - - - - ns
CL = 50pF 4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - - - - - ns

CL = 50pF - - - 10 - 10 - 10 pF
CL = 15pF 5 - 50 - - - - - MHz

= 50pF 4.5 - - 15 - 19 - 22 ns

-5-33-----pF

(Note 4,5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per counter.

5. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC

-40oC TO
85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Timing Diagram

MASTER RESET

HC/HCT4520

HC4518

CLOCK

ENABLE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

12345678901234567890

Q

1

Q

2

Q

3

Q

4

Q

1

Q

2

Q

3

12345678910111213141501234

Q

4

FIGURE 6.

6

Waveforms

trC

L

CLOCK

90%

10%

CD74HC4518, CD74HC4520, CD74HCT4520

50%

10%

tfC

t

WL

L

tWL+ tWH=

50%

fC

50%

I

L

V

CC

GND

t

WH

t

rCL

CLOCK

= 6ns

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

t

WL

+ tWH=

I

fC

L

3V

1.3V
GND

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 7. HC CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

THL

90%
50%
10%

90%

t

50%

10%

PLH

INVERTING

OUTPUT

t

PHL

FIGURE 9. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tfC

L

V

CC

50%

GND

t

H(L)

V

CC

50%

t

SU(L)

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 8. HCT CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

= 6ns

tr = 6ns

INPUT

t

2.7V

1.3V

0.3V

THL

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

3V

1.3V
GND

t

H(L)

3V

1.3V

t

SU(L)

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 11. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V

SET, RESET

1.3V

90%

1.3V
t

t

PLH

TLH

90%

1.3V
10%

t

t

PHL

THL

OR PRESET

IC

C

L

50pF

FIGURE 12. HCTSETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

GND

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