MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION
The M37273M8-XXXSP and M37273MF-XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. They have a OSD, data slicer, and I2C-BUS interface, so it is useful for a channel selection system for TV with a closed caption decoder.
The features of the M37273E8SP and M37273EFSP are similar to those of the M37273M8-XXXSP and M37273MF-XXXSP except that the chip has a built-in PROM which can be written electrically. The difference between M37273M8-XXXSP and M37273MF-XXXSP are the ROM size and RAM size. Accordingly, the following descriptions will be for the M37273M8-XXXSP.
2. FEATURES |
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●Number of basic instructions |
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71 |
●Memory size |
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ROM .............. |
32K bytes |
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(M37273M8-XXXSP, M37273E8SP) |
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60K bytes |
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(M37273MF-XXXSP, M37273EFSP) |
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RAM ............... |
1152 bytes |
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(M37273M8-XXXSP, M37273E8SP) |
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1472 bytes |
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(M37273MF-XXXSP, M37273EFSP) |
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(*ROM correction memory included) |
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●Minimum instruction execution time |
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......................................... 0.5 μs (at 8 MHz oscillation frequency) |
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●Power source voltage ................................................. |
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5 V ± 10 % |
●Subroutine nesting ............................................. |
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128 levels (Max.) |
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●Interrupts ....................................................... |
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17 types, 16 vectors |
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●8-bit timers .................................................................................. |
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6 |
●Programmable I/O ports (Ports P0, P1, P2, P30, P31) |
............. 26 |
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●Input ports (Ports P50, P51) ........................................................ |
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2 |
●Output ports (Ports P52–P57,P6) .............................................. |
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14 |
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●12 V withstand ports ................................................................... |
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6 |
●LED drive ports ........................................................................... |
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4 |
●Serial I/O ............................................................ |
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8-bit 1 channel |
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●Multi-master I2C-BUS interface .............................. |
1 (2 systems) |
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●A-D comparator (6-bit resolution) ................................ |
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6 channels |
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●PWM output circuit ......................................................... |
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8-bit 6 |
●Power dissipation |
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In high-speed mode ......................................................... |
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165 mW |
(at VCC = 5.5V, 8 MHz oscillation frequency, OSD on, and Data |
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slicer on) |
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In low-speed mode ......................................................... |
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0.33 mW |
(at VCC = 5.5V, 32 kHz oscillation frequency) |
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●ROM correction function ................................................ |
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2 vectors |
●Closed caption data slicer |
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●OSD function |
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Display characters ................................... |
32 characters 2 lines |
(It is possible to display 3 lines or more by software) |
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Kinds of characters ........................................................ |
254 kinds |
Character display area ............................ |
CC mode: 16 26 dots |
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OSD mode: 16 20 dots |
Kinds of character sizes ..................................... |
CC mode: 1 kind |
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OSD mode: 8 kinds |
Kinds of character colors .................................. |
8 colors (R, G, B) |
Coloring unit ................... |
character, character background, raster |
Display position |
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Horizontal: 128 levels |
Vertical: 512 levels |
Attribute ........................................................................................ |
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CC mode: smooth italic, underline, flash, automatic solid space
OSD mode: border
Smoth roll-up
Window function
3. APPLICATION
TV with a closed caption decoder
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION .......................................................................... |
1 |
9. PROGRAMMING NOTES ........................................................ |
96 |
2. FEAUTURES ............................................................................. |
1 |
10. ABSOLUTE MAXIMUM RATINGS ......................................... |
97 |
3. APPLICATION ............................................................................ |
1 |
11. RECOMMENDED OPERATING CONDITIONS ..................... |
97 |
4. PIN CONFIGURATION .............................................................. |
3 |
12. ELECTRIC CHARACTERISTICS .......................................... |
98 |
5. FUNCTIONAL BLOCK DIAGRAM ............................................. |
4 |
13. A-D COMPARISON CHARACTERISTICS ........................... |
100 |
6. PERFORMANCE OVERVIEW ................................................... |
5 |
14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS ......... |
100 |
7. PIN DESCRIPTION ................................................................... |
7 |
15. PROM PROGRAMMING METHOD ..................................... |
101 |
8. FUNCTIONAL DESCRIPTION ................................................. |
11 |
16. DATA REQUIRED FOR MASK ORDERS ............................ |
102 |
8.1 CENTRAL PROCESSING UNIT (CPU) .................... |
11 |
17. MASK CONFIRMATION FORM ........................................... |
103 |
8.2 MEMORY .................................................................. |
12 |
18. MARK SPECIFICATION FORM ........................................... |
109 |
8.3 INTERRUPTS ........................................................... |
18 |
19. ONE TIME PROM VERSIONS M37272E8SP/FP, |
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8.4 TIMERS ..................................................................... |
23 |
M37272EFSP MARKING ..................................................... |
110 |
8.5 SERIAL I/O ................................................................ |
26 |
20. APPENDIX ........................................................................... |
111 |
8.6 MULTI-MASTER I2C-BUS INTERFACE .................... |
29 |
21. PACKAGE OUTLINE ........................................................... |
136 |
8.7 PWM OUTPUT CIRCUIT .......................................... |
42 |
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8.8 A-D COMPARATOR .................................................. |
46 |
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8.9 ROM CORRECTION FUNCTION ............................. |
48 |
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8.10 DATA SLICER ......................................................... |
49 |
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8.11 OSD FUNCTIONS ................................................... |
60 |
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8.11.1 Display Position ....................................... |
65 |
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8.11.2 Dot size .................................................... |
69 |
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8.11.3 Clock for OSD .......................................... |
70 |
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8.11.4 Field Determination Display ..................... |
71 |
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8.11.5 Memory For OSD ..................................... |
73 |
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8.11.6 Character Color ....................................... |
77 |
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8.11.7 Character Background Color ................... |
77 |
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8.11.8 OUT1, OUT2 Signals ............................... |
78 |
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8.11.9 Attribute .................................................... |
79 |
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8.11.10 Multiple Display ...................................... |
84 |
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8.11.11 Automatic Solid Space Function ............ |
85 |
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8.11.12 Window Function ................................... |
86 |
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8.11.13 OSD Output Pin Control ........................ |
88 |
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8.11.14 Raster Coloring Function ....................... |
89 |
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8.12. SOFTWARE RUNAWAY DETECT FUNCTION ..... |
91 |
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8.13. RESET CIRCUIT .................................................... |
92 |
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8.14. CLOCK GENERATING CIRCUIT ........................... |
93 |
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8.15. DISPLAY OSCILLATION CIRCUIT ........................ |
96 |
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8.16. AUTO-CLEAR CIRCUIT ......................................... |
96 |
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8.17. ADDRESSING MODE ............................................ |
96 |
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8.18. MACHINE INSTRUCTIONS ................................... |
96 |
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Rev. 1.0
2
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
4. PIN CONFIGURATION
P50/HSYNC 1
P51/VSYNC 2
P00/PWM0 3
P01/PWM1 4
P56 5
P02/PWM2 6
P57 7
P03/PWM3 8
P60 9
P04/PWM410
P05/PWM511
P06/INT2/AD412
P6113
P07/INT114
P6215
P23/TIM316
P24/TIM217
P2518
AVCC 19
HLF 20
VHOLD 21
CVIN 22
CNVSS 23
XIN 24
XOUT 25
VSS 26
XXXSP-XXXSP,M37273MF-M37273M8 M37273E8SP,M37273EFSP
52 P52/R
51 P53/G
50 P54/B
49 P55/OUT1
48 P63
47 P20/SCLK
46 P64
45 P21/SOUT
44 P65
43 P22/SIN
42 P66
41 P10/OUT2
40 P67
39 P11/SCL1
38 P12/SCL2
37 P13/SDA1
36 P14/SDA2
35 P15/AD1/INT3
34 P16/AD2
33 P17/AD3
32 P30/AD5
31 P31/AD6
30 RESET
29 P26/OSC1/XCIN
28 P27/OSC2/XCOUT
27 VCC
Outline 52P4B
Fig. 4.1 Pin Configuration (Top View)
Rev. 1.0
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.5 |
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M37273 of Diagram Block Functional 1.5 . |
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I/O ports P26, P27 |
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DIAGRAM BLOCK FUNCTIONAL |
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Clock input |
Clock output |
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Clock input for OSD/ |
Clock output for OSD/ |
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Reset input |
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Pins for data slicer |
sub-clock input |
sub-clock output |
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XIN XOUT |
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RESET AVCC |
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VCC |
VSS |
CNVSS |
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CVIN |
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VHOLD |
HLF |
OSC1/XCIN |
OSC2/XCOUT |
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30 |
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28 |
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Clock |
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Data slicer |
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generating |
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circuit |
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Data bus |
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Timer count source |
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selection circuit |
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ROM |
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RAM |
Progam |
Program |
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ROM |
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Timer 1 |
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SINGLE |
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correction |
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1152 bytes |
counter |
counter |
32 K bytes |
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T1 (8) |
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circuit |
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PCH (8) |
PCL (8) |
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Timer 2 |
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DECODER CAPTION CLOSED with MICROCOMPUTER CMOS BIT-8 CHIP |
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Address bus |
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T2 (8) |
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XXXSP–M37273MF XXXSP,–M37273M8 |
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Timer 3 |
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T3 (8) |
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Timer 4 |
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Control signal |
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T4 (8) |
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8-bit |
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Processor |
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Stack |
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Accumulator |
Index |
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Index |
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arithmetic |
status |
register |
register |
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pointer |
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Timer 5 |
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Instruction |
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A (8) |
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and |
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register |
X (8) |
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Y (8) |
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S (8) |
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decoder |
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T5 (8) |
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M37273EFSP M37273E8SP, |
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logical unit |
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PS (8) |
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Timer 6 |
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Instruction |
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CRT |
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register (8) |
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circuit |
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T6 (8) |
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CONTROLLER DISPLAY SCREEN-ON and |
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INT1 |
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A-D |
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Multi-master |
SI/O |
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PWM |
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MICROCOMPUTERS MITSUBISHI |
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comparator |
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I2C-BUS |
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interface |
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P0 (8) |
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P1 (8) |
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P2 (6) |
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P3 (2) |
SDA2 |
SDA1 SCL2 |
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P6 (8) |
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OUT2 |
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P5 (8) |
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P10 |
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OUT1 B G R VSYNC |
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HSYNC |
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14 12 11 10 |
8 |
6 |
4 |
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33 34 35 36 37 38 39 41 |
18 17 16 43 45 47 |
31 32 |
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40 42 44 46 48 15 13 |
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7 |
5 |
49 50 51 52 |
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1 |
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I/O port P0 |
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I/O port P1 |
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I/O port P2 |
I/O ports P30, P31 |
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Output ports P6 Output ports P52–P57 |
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INT2 |
INT3 |
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AD1–AD6 |
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SCL1 |
INS CLKS |
OUTS |
PWM5 |
PWM4 |
PWM3 PWM2 PWM1 |
PWM0 |
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Output for display |
Input ports P50, P51 |
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Synchronous signal input |
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0.1 .Rev |
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MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview
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Parameter |
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Functions |
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Number of basic instructions |
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71 |
||||
Instruction execution time |
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0.5 μs (the minimum instruction execution time, at 8 MHz oscillation fre- |
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quency) |
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Clock frequency |
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8 MHz (maximum) |
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Memory size |
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ROM |
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M37273M8-XXXSP, M37273E8SP |
32K bytes |
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M37273MF-XXXSP, M37273EFSP |
60K bytes |
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RAM |
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M37273M8-XXXSP, M37273E8SP |
1152 bytes (ROM correction memory included) |
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M37273MF-XXXSP, M37273EFSP |
1472 bytes (ROM correction memory included) |
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OSD ROM |
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10K bytes |
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OSD RAM |
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128 bytes |
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Input/Output |
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P0 |
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I/O |
8-bit 1 (N-channel open-drain output structure, can be used as PWM |
ports |
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output pins, INT input pins, A-D input pin) |
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P10–P17 |
I/O |
8-bit 1 (CMOS input/output structure, however, N-channel open-drain |
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output structure, when P11–P14 are used as multi-master I2C-BUS inter- |
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face, can be used as OSD output pin, A-D input pins, INT input pin, multi- |
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master I2C-BUS interface) |
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P20–P27 |
I/O |
8-bit 1 (P2 is CMOS input/output structure, however, N-channel open- |
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drain output structure when P20 and 21 are used as serial output, can be |
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used as serial input/output pins, timer external clock input pins, OSD clock |
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input/output pin, sub-clock input/output pins) |
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P30, P31 |
I/O |
2-bit 1 (CMOS input/output or N-channel open-drain output structure, |
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can be used as A-D input pins) |
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P50, P51 |
Input |
2-bit 1 (can be used as OSD input pins) |
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P52–P55,P6 |
Output |
14-bit 1 (CMOS output structure, can be used as OSD output pins) |
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Serial I/O |
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8-bit 1 |
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Multi-master I2C-BUS interface |
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1 (2 systems) |
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A-D comparator |
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6 channels (6-bit resolution) |
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PWM output circuit |
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8-bit 6 |
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Timers |
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8-bit timer 6 |
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ROM correction function |
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2 vectors |
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Subroutine nesting |
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128 levels (maximum) |
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Interrupt |
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<17 types> |
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INT external interrupt 3, Internal timer interrupt 6, Serial I/O interrupt |
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1, OSD interrupt 1, Multi-master I2C-BUS interface interrupt 1, Data |
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slicer interrupt 1, f(XIN)/4096 interrupt 1, VSYNC interrupt 1, BRK |
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instruction interrupt 1, reset 1 |
Clock generating circuit |
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2 built-in circuits (externally connected to a ceramic resonator or a quartz- |
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crystal oscillator) |
Data slicer |
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Built-in |
Rev. 1.0
5
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 6.2 Performance Overview (Continued)
|
Parameter |
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Functions |
|||
OSD function |
Number of display characters |
32 characters 2 lines |
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Dot structure |
CC mode: 16 20 dots (character display area : 16 20 dots) |
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OSD mode: 16 20 dots |
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Kinds of characters |
254 kinds |
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Kinds of character sizes |
CC mode: 1 kinds |
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1 screen : 8 |
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OSD mode: 8 kinds |
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Character font coloring |
1 screen: 8 kinds (per character unit) |
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Display position |
Horizontal: 128 levels, Vertical: 512 levels |
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Power source voltage |
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5V ± 10% |
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Power |
In high-speed |
OSD ON |
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Data slicer ON |
165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz) |
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dissipation |
mode |
OSD OFF |
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Data slicer OFF |
82.5 mW typ. ( at oscillation frequency f(XIN) = 8 MHz) |
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In low-speed |
OSD OFF |
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Data slicer OFF |
0.33 mW typ. ( at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stopped) |
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mode |
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In stop mode |
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0.055 mW ( maximum ) |
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Operating temperature range |
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–10 °C to 70 °C |
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Device structure |
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CMOS silicon gate process |
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Package |
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52-pin plastic molded DIP |
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Rev. 1.0
6
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
|
|
|
M37273E8SP, M37273EFSP |
|
|
|
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER |
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and ON-SCREEN DISPLAY CONTROLLER |
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7. PIN DESCRIPTION |
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Table 7.1 Pin Description |
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Pin |
Name |
Input/ |
Functions |
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Output |
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VCC, AVCC, |
Power source |
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Apply voltage of 5 V ± 10 % to (typical) VCC and AVCC, and 0 V to VSS. |
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VSS |
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CNVSS |
CNVSS |
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This is connected to VSS. |
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______ |
Reset input |
Input |
To enter the reset state, the reset input pin must be kept at a LOW for 2 μs or more (under |
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RESET |
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normal VCC conditions). |
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If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should |
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be maintained for the required time. |
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XIN |
Clock input |
Input |
This chip has an internal clock generating circuit. To control generating frequency, an |
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external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and |
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XOUT |
Clock output |
Output |
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and |
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the XOUT pin should be left open. |
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P00/PWM0– |
I/O port P0 |
I/O |
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually |
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P05/PWM5, |
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programmed as input or output. At reset, this port is set to input mode. The output structure |
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P06/INT2/AD4, |
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is N-channel open-drain output. (See note 1) |
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P07/INT1 |
PWM output |
Output |
Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output |
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structure is N-channel open-drain output. |
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External interrupt |
Input |
Pins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 respectively. |
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input |
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Analog input |
Input |
P06 pin is also used as analog input pin AD4. |
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P10/OUT2, |
I/O port P1 |
I/O |
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output |
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P11/SCL1, |
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structure is CMOS output. (See note 1) |
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P12/SCL2, |
OSD output |
Output |
Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output. |
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P13/SDA1, |
Multi-master |
I/O |
Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master |
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P14/SDA2, |
I2C-BUS interface |
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I2C-BUS interface is used. The output structure is N-channel open-drain output. |
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P15/AD1/INT3, |
Analog input |
Input |
Pins P10, P15–P17 are also used as analog input pin AD8, AD1–AD3 respectively. |
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P16/AD2, |
External interrupt |
Input |
P15 pin is also used as INT external interrupt input pin INT3. |
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P17/AD3 |
input |
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P20/SCLK, |
I/O port P2 |
I/O |
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output |
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P21/SOUT, |
|
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structure is CMOS output. (See note 1) |
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P22/SIN, |
Serial I/O synchronous |
I/O |
P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output |
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P23/TIM3, |
clock input/output port |
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structure is N-channel open-drain output. |
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P24/TIM2, |
Serial I/O data |
I/O |
P21 pin is also used as serial I/O data output pin SOUT. The output structure is open-drain |
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P25, |
output |
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output. |
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P26/OSC1/ |
Serial I/O data input |
Input |
P22 pin is also used as serial I/O data input pin SIN. |
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XCIN, |
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External clock |
Input |
Pins P23 and P24 are also used as timer external clock input pins TIM3 and TIM2 |
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P27/OSC2/ |
input for timer |
|
respectively. |
|
XCOUT |
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Clock input for OSD |
Input |
P26 pin is also used as OSD clock input pin OSC1. (See note 2) |
||
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Clock output for OSD |
Output |
P27 pin is also used as OSD clock input pin OSC2. The output structure is CMOS output. |
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(See note 2) |
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Sub-clock input |
Input |
P26 pin is also used as sub-clock input pin XCIN. |
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Sub-clock output |
Output |
P27 pin is also used as sub-clock output pin XCOUT. |
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Rev. 1.0
7
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 7.2 Pin Description (continued)
Pin |
Name |
Input/ |
Functions |
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Output |
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P30/AD5, |
I/O port P3 |
I/O |
Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port 0. |
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P31/AD6 |
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The output structure can be selected either CMOS output or N-channel open-drain output |
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structure. (See notes 1, 3) |
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Analog input |
Input |
Pins P30 and P31 are also used as analog input pins AD5 and AD6 respectively. |
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P50/HSYNC, |
Input port P5 |
Input |
Pin P50 and P51 are 2-bit input ports. |
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P51/VSYNC |
HSYNC input |
Input |
Pin P50 is also used as HSYNC input. This is a horizontal synchronous signal input for OSD. |
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VSYNC input |
Input |
Pin P51 is also used as VSYNC input. This is a vertical synchronous signal input for OSD. |
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P52/R, |
Output port P5 |
Output |
Ports P52–P57 are a 6-bit output port. The output structure is CMOS output. |
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P53/G, |
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P54/B, |
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OSD output |
Output |
Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output |
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P55/OUT1 |
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structure is CMOS output. |
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P56, P57 |
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P60–P67 |
Output port P6 |
Output |
Port P6 is an 8-bit output port. The output structure is CMOS output. |
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CVIN |
I/O for data slicer |
Input |
Input composite video signal through a capacitor. |
|
VHOLD |
|
Input |
Connect a capacitor between VHOLD and Vss. |
|
HLF |
|
I/O |
Connect a filter using of a capacitor and a resistor between HLF and Vss. |
Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
2:To switch output functions, set the raster color register and OSD control register. When pins P26 and P27 are used as the OSD clock input/output pins, set the corresponding bits of the port P2 direction register to “0” (input mode).
3:To switch output structures, set bits 2 and 3 of the port P3 direction register, When “0,” CMOS output ; when “1,” N-channel open-drain output.
Rev. 1.0
8
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Ports P00–P05
|
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N-channel open-drain output |
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Direction register |
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Ports P00–P05 |
Data bus |
Port latch |
Note : Each port is also used as follows : |
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P00–P05 : PWM0–PWM5 |
Ports P1, P2, P30, P31
Direction register
CMOS output
Data bus |
Port latch |
Ports P1, P2, P30, P31 |
Notes 1: Each port is also used as follows :
P10 : OUT2
P11 : SCL1
P12 : SCL2
P13 : SDA15
P14 : SDA2
P15 : AD1/INT3
P16 : AD2
P17 : AD3
2:The output structure of ports P30 and P31 can be selected either CMOS output or N-channel opendrain output structure (when selecting N-channel open-drain, it is the same with P06 and P07).
3:The output structure of ports P11–P14 is N-channel open-drain output when using as multi-master
I2C-BUS interface (it is the same with P06 and P07).
4:The output structure of ports P20 and P21 is N-channel open-drain output when using as serial output (it is the same as P06 and P07).
Fig. 7.1 I/O Pin Block Diagram (1)
Rev. 1.0
9
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Ports P06, P07
Data bus
P50, P51
Internal circuit
Direction register
Port latch
P52–P57, P6
CMOS input
Ports P50, P51
Internal circuit
Note : Each pin is also used as follows :
P50 : HSYNC
P51 : VSYNC
N-channel open-drain output
Ports P06, P07
Note : Each port is also used as follows :
P06 : INT2/AD4
P07 : INT1
CMOS output
Ports P52–P57, P6
Note : Each pin is also used as follows :
P52 : R
P53 : G
P54 : B
P55 : OUT1
Fig. 7.2 I/O Pin Block Diagram (2)
Rev. 1.0
10
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8. FUNCTIONAL DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
CPU Mode Register
b7b6 b5b4b3 b2b1b0 |
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1 |
1 |
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0 |
0 |
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CPU mode register (CM) [Address 00FB16] |
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B |
Name |
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Functions |
After reset |
R W |
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0, 1 |
Processor mode bits |
b1 b0 |
0 |
R W |
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(CM0, CM1) |
0 0: Single-chip mode |
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0 |
1: |
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1 |
0: Not available |
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1 |
1: |
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2 |
Stack page selection |
0: |
0 page |
1 |
R W |
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bit (CM2) (See note) |
1: |
1 page |
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3, 4 |
Fix these bits to “1.” |
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1 |
R W |
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5 |
XCOUT drivability |
0: LOW drive |
1 |
R W |
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selection bit (CM5) |
1: HIGH drive |
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6 |
Main Clock (XIN–XOUT) |
0: Oscillating |
0 |
R W |
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stop bit |
1: Stopped |
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(CM6) |
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7 |
Internal system clock |
0: XIN–XOUT selected |
0 |
R W |
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selection bit |
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(high-speed mode) |
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(CM7) |
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1: XCIN–XCOUT selected |
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(high-speed mode) |
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Note: This bit is set to “1” after the reset release.
Fig. 8.1.1 CPU Mode Register
Rev. 1.0
11
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.2 MEMORY
8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
8.2.3 ROM
ROM is used for storing user programs as well as the interrupt vector area.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and colors to display.
8.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
8.2.8 Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
8.2.5 OSD ROM
ROM for display is used for storing character data. |
8.2.9 ROM Correction Memory (RAM) |
|
This is used as the program area for ROM correction. |
¡M37273M8-XXXSP, M37273E8SP
|
000016 |
|
1000016 |
|
|
|
00BF16 |
|
Zero page |
|
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||
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|
00C016 |
SFR1 area |
|
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00FF16 |
||
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RAM |
010016 |
|
|
|
|
|
|
|
(1152 bytes)
01FF16 020016
SFR2 area
020F16
Not used
030016
0320 ROM correction function
16
Vector1: address 030016
Vector2: address 032016
|
05BF16 |
|
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|
|
|
|
|
Not used |
|
Not used |
OSD RAM |
080016 |
|
|
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(128 bytes) |
|
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087F16 |
|
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iSee note |
j |
|
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Not used |
|
|
OSD ROM |
140016 |
|
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|
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||
(10K bytes) |
3BFF16 |
|
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Not used |
|
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ROM |
800016 |
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||
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(32K bytes) |
FF0016 |
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FFDE16 |
|
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Special page |
|
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Interrupt vector area |
|||
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|||
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FFFF16 |
|
1FFFF16 |
||
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||||
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||
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Note: Refer to Table 8.11.3 OSD RAM. |
Fig. 8.2.1 Memory Map (M37273M8-XXXSP, M37273E8SP)
Rev. 1.0
12
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
¡M37273MF-XXXSP, M37273EFSP
|
|
|
|
000016 |
|
Zero page |
1000016 |
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|||
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00BF16 |
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00C016 |
SFR1 area |
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00FF16 |
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RAM |
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010016 |
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(1472 bytes) |
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01FF16 |
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020016 |
SFR2 area |
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020F16 |
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Not used |
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Not used |
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030016 |
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ROM correction function |
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032016 |
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Vector 1: address 0300 16 |
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Vector 2: address 0320 16 |
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06FF16 |
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Not used |
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OSD RAM |
080016 |
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|||||
(128 bytes) |
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||||||
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087F16 |
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||||
iSee note |
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||||
j |
Not used |
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||||||
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100016 |
|
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OSD ROM |
1140016 |
|
||
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|||||
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(10K bytes) |
13BFF16 |
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|||
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||
ROM |
|
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|||
(60K bytes) |
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Not used |
|||
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FF0016 |
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|||
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FFDE16 |
|
Special page |
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Interrupt vector area |
1FFFF16 |
|
|||||
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FFFF16 |
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||
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|
Note: Refer to Table 8.11.3 OSD RAM.
Fig. 8.2.2 Memory Map (M37273MF-XXXSP, M37273EFSP)
Rev. 1.0
13
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
■ SFR1 Area (addresses C016 to DF16)
<Bit allocation>
:
Function bit
Name :
: No function bit
0 : Fix this bit to “0” (do not write “1”)
1 : Fix this bit to “1” (do not write “0”)
Address |
Register |
Bit allocation |
b7
<State immediately after reset>
0: “0” immediately after reset
1: “1” immediately after reset
?: Indeterminate immediately after reset
State immediately after reset
b0 |
b7 |
b0 |
C016 |
Port P0 (P0) |
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? |
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C116 |
Port P0 direction register (D0) |
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0016 |
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C216 |
Port P1 (P1) |
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? |
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C316 |
Port P1 direction register (D1) |
|
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|
0016 |
|
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|
C416 |
Port P2 (P2) |
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? |
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C516 |
Port P2 direction register (D2) |
|
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|
0016 |
|
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|
C616 |
Port P3 (P3) |
|
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|
P31 |
P30 |
|
0 |
0 |
0 |
0 |
0 |
0 |
? |
? |
C716 |
Port P3 direction register (D3) |
|
T3SC |
|
|
P31CP30C |
P31DP30D |
|
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|
0016 |
|
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||||
C816 |
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? |
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C916 |
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? |
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CA16 |
Port P5 (P5) |
|
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|
? |
|
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|
CB16 |
OSD port control register (PF) |
PF7 |
|
PF5 |
PF4 |
PF3 |
PF2 |
0 |
0 |
|
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|
|
0016 |
|
|
|
||
CC16 |
Port P6 (P6) |
|
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|
0016 |
|
|
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|
CD16 |
|
|
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? |
|
|
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|
CE16 |
Caption data register 3 (CD3) |
|
CDL27CDL26CDL25CDL24CDL23CDL22 |
|
|
CDL21CDL20 |
|
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|
? |
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|||||
|
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|
||||
CF16 |
Caption data register 4 (CD4) |
|
CDH27CDH26CDH25CDH24CDH23CDH22CDH21CDH20 |
|
|
|
|
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|
? |
|
|
|
||||||
|
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|
||||
D016 |
OSD control register (OC) |
0 |
OC6 |
OC5 |
OC4 |
OC3 |
OC2 |
OC1 |
OC0 |
|
|
|
|
0016 |
|
|
|
||
D116 |
Horizontal position register (HP) |
|
HP6 |
HP5 |
HP4 |
HP3 |
HP2 |
HP1 |
HP0 |
|
|
|
|
0016 |
|
|
|
||
D216 |
Block control register 1 (BC1) |
|
BC17BC16BC15BC14BC13BC12 |
|
|
BC11BC10 |
|
|
|
|
? |
|
|
|
|||||
D316 |
Block control register 2 (BC2) |
|
BC27BC26BC25BC24BC23BC22 |
|
|
BC21BC20 |
|
|
|
|
? |
|
|
|
|||||
D416 |
Vertical position register 1 (VP1) |
VP17 |
VP16 |
VP15 |
VP14 |
VP13VP12 |
VP11 |
VP10 |
|
|
|
|
? |
|
|
|
|||
D516 |
Vertical position register 2 (VP2) |
VP27 |
VP26 |
VP25 |
VP24 |
VP23VP22 |
VP21 |
VP20 |
|
|
|
|
? |
|
|
|
|||
D616 |
Window register 1 (WN1) |
WN17WN16 |
|
WN15WN14WN13WN12 |
|
|
WN11WN10 |
|
|
|
|
? |
|
|
|
||||
|
|
|
|
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|
|
|
|
|
|
|
||
D716 |
Window register 2 (WN2) |
WN27WN26 |
|
WN25WN24WN23WN22 |
|
|
WN21WN20 |
|
|
|
|
? |
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
D816 |
I/O polarity control register (PC) |
0 |
PC6 |
PC5 |
PC4 |
PC3 |
|
PC2 |
PC1 |
PC0 |
|
|
|
|
4016 |
|
|
|
|
D916 |
Raster color register (RC) |
RC7 |
0 |
0 |
RC4 |
RC3 |
|
RC2 |
RC1 |
RC0 |
|
|
|
|
0016 |
|
|
|
|
DA16 |
|
|
|
|
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|
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|
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|
? |
|
|
|
|
DB16 |
|
|
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|
|
|
|
|
|
? |
|
|
|
|
DC16 |
Interrupt input polarity control register (RE) |
|
|
|
|
|
|
INT3 |
INT2 |
INT1 |
|
|
|
|
0016 |
|
|
|
|
DD16 |
|
|
|
|
0016 |
|
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|
0016 |
|
|
|
||
DE16 |
|
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|
|
0016 |
|
|
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|
|
|
|
0016 |
|
|
|
||
DF16 |
|
|
|
|
0016 (See note 1) |
|
|
|
|
0016 (See note 2) |
Notes 1: This is only M37273MF-XXXSP and M37273EFSP.
2: As for M37273M8-XXXSP and M37273E8SP, the reset value is ? (indeterminate).
Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (1)
Rev. 1.0
14
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
■ SFR1 Area (addresses E016 to FF16)
<Bit allocation> |
|
<State immediately after reset> |
||||||
|
|
: |
|
|
|
|
|
: “0” immediately after reset |
|
|
Function |
bit |
|
0 |
|||
|
|
|
|
|
|
|
||
|
: |
|
|
|
|
|||
Name |
|
|
|
|
|
: “1” immediately after reset |
||
|
|
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|
1 |
||||
|
|
|
|
|
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|
||
|
|
: No function bit |
|
|
: Indeterminate immediately |
|||
|
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|
|||||
|
|
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|
|||||
|
? |
|||||||
|
|
|
|
|
|
|
||
|
|
: Fix this bit to “0” |
|
|
after reset |
|||
|
|
|
|
|||||
0 |
|
|
|
|||||
|
|
|
|
|||||
|
|
(do not write “1”) |
|
|
|
|||
|
|
|
|
|||||
1 |
: Fix this bit to “1” |
|
|
|
||||
|
|
(do not write “0”) |
|
|
|
Address |
Register |
b7 |
|
Bit allocation |
|
|
b0 |
State immediately after reset |
|||||||||||||
|
|
|
|
|
|
|
|
|
|
b7 |
|
|
|
|
|
|
|
b0 |
|||
E016 |
Data slicer control register 1 (DSC1) |
0 |
1 |
1 |
0 |
0 |
DSC12DSC11DSC10 |
|
|
|
|
0016 |
|
|
|
||||||
E116 |
Data slicer control register 2 (DSC2) |
|
0 |
DSC25DSC24 |
DSC23 |
|
1 |
|
DSC20 |
|
? |
0 |
? |
0 |
|
? |
? |
0 |
? |
||
E216 |
Caption data register 1 (CD1) |
CDL17CDL16CDL15 |
CDL14 |
|
CDL13CDL12CDL11CDL10 |
|
|
|
|
|
0016 |
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
E316 |
Caption data register 2 (CD2) |
|
CDH17CDH16CDH15CDH14CDH13CDH12CDH11CDH10 |
|
|
|
|
|
|
|
0016 |
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
E416 |
Clock run-in detect register (CRD) |
CRD7 |
CRD6 |
CRD5 |
CRD4 |
CRD3 |
|
|
|
|
|
|
|
|
0016 |
|
|
|
|||
E516 |
Data clock position register (DPS) |
DPS7 |
DPS6 |
DPS5 |
DPS4 |
DPS3 |
0 |
1 |
|
0 |
|
|
|
|
0916 |
|
|
|
|||
E616 |
Caption position register (CPS) |
CPS7 |
CPS6 |
CPS5 |
CPS4 |
CPS3 |
CPS2 |
CPS1 |
|
CPS0 |
|
0 |
0 |
? |
0 |
|
0 |
0 |
0 |
0 |
|
E716 |
Data slicer test register 2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
0016 |
|
|
|
|||
E816 |
Data slicer test register 1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
0016 |
|
|
|
|||
E916 |
Synchronous signal counter register |
(HC) |
|
HC5 |
HC4 |
HC3 |
HC2 |
HC1 |
|
HC0 |
|
|
|
|
0016 |
|
|
|
|||
EA16 |
Serial I/O register (SIO) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
? |
|
|
|
||
EB16 |
Serial I/O mode register (SM) |
0 |
SM6 |
SM5 |
0 |
SM3 |
SM2 |
SM1 |
SM0 |
|
|
|
|
0016 |
|
|
|
||||
EC16 |
A-D control register 1 (AD1) |
|
|
|
ADC14 |
|
ADC12 |
ADC11 |
ADC10 |
|
0 |
0 |
0 |
? |
|
0 |
0 |
0 |
0 |
||
|
|
|
|
|
|
|
|
|
|
|
|||||||||||
ED16 |
A-D control register 2 (AD2) |
|
|
|
|
|
|
|
|
|
|
|
|
|
0016 |
|
|
|
|||
|
|
ADC25 |
ADC24 |
ADC23 |
ADC22ADC21 |
ADC20 |
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
EE16 |
Timer 5 (T5) |
|
|
|
|
|
|
|
|
|
|
|
|
|
0716 |
|
|
|
|||
EF16 |
Timer 6 (T6) |
|
|
|
|
|
|
|
|
|
|
|
|
|
FF16 |
|
|
|
|||
F016 |
Timer 1 (T1) |
|
|
|
|
|
|
|
|
|
|
|
|
|
FF16 |
|
|
|
|||
F116 |
Timer 2 (T2) |
|
|
|
|
|
|
|
|
|
|
|
|
|
0716 |
|
|
|
|||
F216 |
Timer 3 (T3) |
|
|
|
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FF16 |
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F316 |
Timer 4 (T4) |
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0716 |
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F416 |
Timer mode register 1 (TM1) |
TM17 |
TM16 |
TM15 |
TM14 |
TM13 |
TM12 |
TM11 |
TM10 |
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0016 |
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||||
F516 |
Timer mode register 2 (TM2) |
TM27 |
TM26 |
TM25 |
TM24 |
TM23 |
TM22 |
TM21 |
TM20 |
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0016 |
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||||
F616 |
I2C data shift register (S0) |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
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D0 |
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? |
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||
F716 |
I2C address register (S0D) |
SAD6 |
SAD5 |
SAD4 |
SAD3 |
SAD2 |
SAD1 |
SAD0 |
RBW |
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0016 |
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||||||
F816 |
I2C status register (S1) |
MST |
TRX |
BB |
PIN |
AL |
AAS |
AD0 |
LRB |
|
0 |
0 |
0 |
1 |
|
0 |
0 |
0 |
? |
||
F916 |
I2C control register (S1D) |
BSEL1 |
BSEL0 |
10BITSAD |
ALS |
ESO |
BC2 |
BC1 |
|
BC0 |
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0016 |
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|||
FA16 |
I2C clock control register (S2) |
ACK |
ACK |
FAST |
CCR4CCR3 |
CCR2 |
CCR1 |
CCR0 |
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0016 |
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|||||
BIT |
MODE |
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FB16 |
CPU mode register (CPUM) |
CM7 |
CM6 |
CM5 |
1 |
1 |
CM2 |
0 |
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0 |
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3C16 |
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|||
FC16 |
Interrupt request register 1 (IREQ1) |
|
IN3R |
VSCR |
OSDRTM4R |
TM3R |
TM2R |
TM1R |
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0016 |
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|||||
FD16 |
Interrupt request register 2 (IREQ2) |
0 |
TM56R |
IICR |
CK0 |
CKR |
S1R |
DSR |
|
IN1R |
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0016 |
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|
IN2R |
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FE16 |
Interrupt control register 1 (ICON1) |
|
IN3E |
VSCEOSDE |
TM4E |
TM3E |
TM2E |
TM1E |
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|
0016 |
|
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|
|||||
FF16 |
Interrupt control register 2 (ICON2) |
TM56CTM56E |
IICE |
IN2E |
CKE |
S1E |
DSE |
IN1E |
|
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|
|
0016 |
|
|
|
Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR1) (2)
Rev. 1.0
15
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
■ SFR2 Area (addresses 20016 to 20F16)
<Bit allocation> |
|
<State immediately after reset> |
|||||
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: |
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: “0” immediately after reset |
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Function |
bit |
0 |
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: |
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Name |
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1 |
: “1” immediately after reset |
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: No function bit |
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: Indeterminate immediately |
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? |
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: Fix this bit to “0” |
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after reset |
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0 |
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(do not write “1”) |
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1 |
: Fix this bit to “1” |
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||||
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(do not write “0”) |
|
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Address |
Register |
b7 |
|
Bit allocation |
|
b0 |
|
State immediately after reset |
b0 |
|||||||||||
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b7 |
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20016 |
PWM0 register (PWM0) |
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? |
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20116 |
PWM1 register (PWM1) |
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? |
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20216 |
PWM2 register (PWM2) |
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? |
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20316 |
PWM3 register (PWM3) |
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? |
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20416 |
PWM4 register (PWM4) |
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? |
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20516 |
PWM5 register (PWM5) |
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? |
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20616 |
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0016 |
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? |
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20716 |
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0016 |
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? |
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20816 |
PWM mode register 1 (PM1) |
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PM13 |
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PM10 |
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? |
? |
? |
? |
0 |
? |
? |
|
0 |
|
20916 |
PWM mode register 2 (PM2) |
0 |
0 |
PM25 |
PM24 |
PM23 |
PM22 |
PM21 |
PM20 |
|
0016 |
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|||||
20A16 |
ROM correction address 1 (high-order) |
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0016 |
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20B16 |
ROM correction address 1 (low-order) |
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0016 |
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|||||
20C16 |
ROM correction address 2 (high-order) |
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0016 |
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|||||
20D16 |
ROM correction address 2 (low-order) |
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0016 |
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|||||
20E16 |
ROM correction enable register (RCR) |
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RC1 |
RC0 |
|
0016 |
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|||||
20F16 |
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? |
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Fig. 8.2.5 Memory Map of Special Function Register 2 (SFR2)
Rev. 1.0
16
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Register
Processor status register (PS) Program counter (PCH)
Program counter (PCL)
<Bit allocation> |
|
<State immediately after reset> |
|||||
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: |
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: “0” immediately after reset |
|
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Function |
bit |
0 |
||
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|||||
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Name :
: No function bit
0: Fix to this bit to “0” (do not write to “1”)
1: Fix to this bit to “1” (do not write to “0”)
Bit allocation
1: “1” immediately after reset
?: Indeterminate immediately after reset
State immediately after reset
b7 |
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b0 |
b7 |
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b0 |
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N |
V |
T |
B |
D |
I |
Z |
C |
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? |
? |
? |
? |
? |
1 |
? |
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? |
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Contents of address FFFF |
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16 |
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Contents of address FFFE16 |
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Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset
Rev. 1.0
17
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MITSUBISHI MICROCOMPUTERS |
||
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M37273M8–XXXSP, M37273MF–XXXSP |
||||||
|
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M37273E8SP, M37273EFSP |
|||
|
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER |
|||||||
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and ON-SCREEN DISPLAY CONTROLLER |
||
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8.3 INTERRUPTS |
|
|
8.3.1 Interrupt Causes |
|||||
Interrupts can be caused by 17 different sources consisting of 4 ex- |
(1) VSYNC, OSD interrupts |
|||||||
ternal, 11 internal, 1 software, and reset. Interrupts are vectored in- |
The VSYNC interrupt is an interrupt request synchronized with |
|||||||
terrupts with priorities as shown in Table 8.3.1. Reset is also included |
the vertical sync signal. |
|||||||
in the table because its operation is similar to an interrupt. |
|
|
The OSD interrupt occurs after character block display to the |
|||||
When an interrupt is accepted, |
|
|
CRT is completed. |
|||||
The contents of the program counter and processor status regis- |
(2) INT1 to INT3 external interrupts |
|||||||
ter are automatically stored into the stack. |
|
|
||||||
The interrupt disable flag I is set to “1” and the corresponding |
The INT1 to INT3 interrupts are external interrupt inputs, the sys- |
|||||||
interrupt request bit is set to “0.” |
|
|
tem detects that the level of a pin changes from LOW to HIGH or |
|||||
The jump destination address stored in the vector address enters |
from HIGH to LOW, and generates an interrupt request. The in- |
|||||||
the program counter. |
|
|
put active edge can be selected by bits 3 to 5 of the interrupt |
|||||
Other interrupts are disabled when the interrupt disable flag is set to |
input polarity register (address 00DC16) : when this bit is “0,” a |
|||||||
“1.” |
|
|
|
change from LOW to HIGH is detected; when it is “1,” a change |
||||
All interrupts except the BRK instruction interrupt have an interrupt |
from HIGH to LOW is detected. Note that both bits are cleared to |
|||||||
request bit and an interrupt enable bit. The interrupt request bits are |
“0” at reset. |
|||||||
in interrupt request registers 1 and 2 and the interrupt enable bits are |
(3) Timers 1 to 4 interrupts |
|||||||
in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the |
||||||||
interrupt-related registers. |
|
|
An interrupt is generated by an overflow of timers 1 to 4. |
|||||
Interrupts other than the BRK instruction interrupt and reset are ac- |
|
|
|
|
|
|||
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,” |
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|
|||
and the interrupt disable flag is “0.” The interrupt request bit can be |
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|
|||
set to “0” by a program, but not set to “1.” The interrupt enable bit can |
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|||
be set to “0” and “1” by a program. |
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Reset is treated as a non-maskable interrupt with the highest priority. |
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|
|||
Figure 8.3.1 shows interrupt control. |
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Table 8.3.1 Interrupt Vector Addresses and Priority |
|
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||
Priority |
Interrupt Source |
|
Vector Addresses |
|
Remarks |
|
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||
1 |
Reset |
|
FFFF16, FFFE16 |
|
Non-maskable |
|
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2 |
OSD interrupt |
|
FFFD16, FFFC16 |
|
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|
||
3 |
INT1 external interrupt |
|
FFFB16, FFFA16 |
|
Active edge selectable |
|
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4 |
Data slicer interrupt |
|
FFF916, FFF816 |
|
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5 |
Serial I/O interrupt |
|
FFF716, FFF616 |
|
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6 |
Timer 4 interrupt |
|
FFF516, FFF416 |
|
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7 |
f(XIN)/4096 interrupt |
|
FFF316, FFF216 |
|
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8 |
VSYNC interrupt |
|
FFF116, FFF016 |
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9 |
Timer 3 interrupt |
|
FFEF16, FFEE16 |
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10 |
Timer 2 interrupt |
|
FFED16, FFEC16 |
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11 |
Timer 1 interrupt |
|
FFEB16, FFEA16 |
|
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||
12 |
INT3 external interrupt |
|
FFE916, FFE816 |
|
Active edge selectable |
|
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||
13 |
INT2 external interrupt |
|
FFE716, FFE616 |
|
Active edge selectable |
|
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14 |
Multi-master I2C-BUS interface interrupt |
|
FFE516, FFE416 |
|
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|
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15 |
Timer 5 • 6 interrupt |
|
FFE316, FFE216 |
|
Source switch by software (see note) |
|
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||
16 |
BRK instruction interrupt |
|
FFDF16, FFDE16 |
|
Non-maskable |
|
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|
|
|
|
|
Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
Rev. 1.0
18
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O function.
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to “0.”
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS interface.
(8) Timer 5 • 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software.
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction |
Interrupt |
|
request |
||
Reset |
||
|
Fig. 8.3.1 Interrupt Control
(9) BRK instruction interrupt
This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Rev. 1.0
19
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B |
Name |
|
|
Functions |
After reset |
R W |
|
|
|
|
|
|
|
|
|
0 |
Timer 1 interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
request bit |
(TM1R) |
1 |
: Interrupt request issued |
|
|
|
1 |
Timer 2 interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
request bit |
(TM2R) |
1 |
: Interrupt request issued |
|
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|
|
|
|
|
|
|
|
|
2 |
Timer 3 interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
request bit |
(TM3R) |
1 |
: Interrupt request issued |
|
|
|
3 |
Timer 4 interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
request bit |
(TM4R) |
1 |
: Interrupt request issued |
|
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|
|
4 |
OSD interrupt request |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
bit (OSDR) |
|
1 |
: Interrupt request issued |
|
|
|
|
|
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|
|
5 |
VSYNC interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
request bit |
(VSCR) |
1 |
: Interrupt request issued |
|
|
|
6 |
INT3 external interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
request bit |
(VSCR) |
1 |
: Interrupt request issued |
|
|
|
|
|
|
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|
|||
7 |
Nothing is assigned. This bit is a write disable bit. |
0 |
R — |
||||
|
When this bit is read out, the value is “0.” |
|
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|||
|
|
|
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|
|
|
|
: “0” can be set by software, but “1” cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7 b6b5b4b3 b2b1b0 |
|
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|||||||
0 |
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|
Interrupt request register 2 (IREQ2) [Address 00FD16] |
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|||
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B |
Name |
|
Functions |
After reset |
R W |
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|
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|
|
0 |
INT1 external interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
|
|
|
|
|
|
|
|
|
request bit (INIR) |
1 |
: Interrupt request issued |
|
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|
|
|
|
|
|
|
|
1 |
Data slicer interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
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|
|
|
|
|
|
|
|
request bit (DSR) |
1 |
: Interrupt request issued |
|
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|
2 |
Serial I/O interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
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|
|
|
|
|
|
request bit (S1R) |
1 |
: Interrupt request issued |
|
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|
3 |
f(XIN)/4096 interrupt |
0 |
: No interrupt request issued |
0 |
R |
|
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|
request bit (CKR) |
1 |
: Interrupt request issued |
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4 |
INT2 external interrupt |
0 |
: No interrupt request issued |
0 |
R |
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|
request bit (IN2R) |
1 |
: Interrupt request issued |
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5 |
Multi-master I2C-BUS |
0 |
: No interrupt request issued |
0 |
R |
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|
interrupt request bit (IICR) |
1 |
: Interrupt request issued |
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6 |
Timer 5 • 6 interrupt |
0 |
: No interrupt request issued |
0 |
R |
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|
request bit (TM56R) |
1 |
: Interrupt request issued |
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7 |
Fix this bit to “0.” |
|
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0 |
R |
W |
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: “0” can be set by software, but “1” cannot be set.
Fig. 8.3.3 Interrupt Request Register 2
Rev. 1.0
20
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B |
Name |
|
Functions |
After reset |
R W |
|
|
|
|
|
|
|
|
0 |
Timer 1 interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
|
enable bit |
(TM1E) |
1 |
: Interrupt enabled |
|
|
1 |
Timer 2 interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
|
enable bit |
(TM2E) |
1 |
: Interrupt enabled |
|
|
2 |
Timer 3 interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
|
enable bit |
(TM3E) |
1 |
: Interrupt enabled |
|
|
|
|
|
|
|
|
|
3 |
Timer 4 interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
|
enable bit |
(TM4E) |
1 |
: Interrupt enabled |
|
|
4 |
OSD interrupt enable bit |
0 |
: Interrupt disabled |
0 |
R W |
|
|
(OSDE) |
|
1 |
: Interrupt enabled |
|
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|
|
|
|
5 |
VSYNC interrupt enable |
0 |
: Interrupt disabled |
0 |
R W |
|
|
bit (VSCE) |
1 |
: Interrupt enabled |
|
|
|
6 |
INT3 external interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
|
enable bit |
(IN3E) |
1 |
: Interrupt enabled |
|
|
|
|
|
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||
7 |
Nothing is assigned. This |
bit is a write disable |
0 |
R — |
||
|
bit. When this bit is read out, the value is “0.” |
|
|
|||
|
|
|
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|
|
Fig. 8.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
Interrupt control register 2 (ICON2) [Address 00FF16]
B |
Name |
|
Functions |
After reset |
R W |
|
|
|
|
|
|
0 |
INT1 external interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
enable bit (IN1E) |
1 |
: Interrupt enabled |
|
|
1 |
Data slicer interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
enable bit (DSE) |
1 |
: Interrupt enabled |
|
|
|
|
|
|
|
|
2 |
Serial I/O interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
enable bit (S1E) |
1 |
: Interrupt enabled |
|
|
3 |
f(XIN)/4096 interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
enable bit (CKE) |
1 |
: Interrupt enabled |
|
|
|
|
|
|
|
|
4 |
INT2 external interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
enable bit (IN2E) |
1 |
: Interrupt enabled |
|
|
5 |
Multi-master I2C-BUS |
0 |
: Interrupt disabled |
0 |
R W |
|
interface interrupt enable |
1 |
: Interrupt enabled |
|
|
|
bit (IICE) |
|
|
|
|
6 |
Timer 5 • 6 interrupt |
0 |
: Interrupt disabled |
0 |
R W |
|
enable bit (TM56E) |
1 |
: Interrupt enabled |
|
|
|
|
|
|
|
|
7 |
Timer 5 • 6 interrupt |
0 |
: Timer 5 |
0 |
R W |
|
switch bit (TM56C) |
1 |
: Timer 6 |
|
|
|
|
|
|
|
|
Fig. 8.3.5 Interrupt Control Register 2
Rev. 1.0
21
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC 16]
B |
Name |
|
Functions |
After reset |
R |
W |
|
|
|
|
|
|
|
|
|
0 |
INT1 polarity switch bit |
0 |
: Positive polarity |
0 |
R |
W |
|
|
(INT1) |
1 |
: Negative polarity |
|
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|
|
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|
|
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|
4 |
INT2 polarity switch bit |
0 |
: Positive polarity |
0 |
R |
W |
|
|
(INT2) |
1 |
: Negative polarity |
|
|
|
|
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|
|
|
|
5 |
INT3 polarity switch bit |
0 |
: Positive polarity |
0 |
R |
W |
|
|
(INT3) |
1 |
: Negative polarity |
|
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|
4 |
Nothing is assigned. These bits are write disable bits. |
0 |
R |
— |
|||
to |
|||||||
When these bits are read out, the values are “0.” |
|
|
|
||||
7 |
|
|
|
||||
|
|
|
|
|
|
Fig. 8.3.6 Interrupt Input Polarity Register
Rev. 1.0
22
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.4 TIMERS
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer, simultaneously.
The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse, after the count value reaches “0016”.
8.4.5 Timer 5
Timer 5 can select one of the following count sources:
•f(XIN)/16 or f(XCIN)/16
•Timer 2 overflow signal
•Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F416) and bit 7 of the timer mode register 2
(address 00F516). When overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
8.4.1 Timer 1
Timer 1 can select one of the following count sources:
•f(XIN)/16 or f(XCIN)/16
•f(XIN)/4096 or f(XCIN)/4096
•External clock from the TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
8.4.2 Timer 2
Timer 2 can select one of the following count sources:
•f(XIN)/16 or f(XCIN)/16
•Timer 1 overflow signal
•External clock from the TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources:
•f(XIN)/16 or f(XCIN)/16
•f(XCIN)
•External clock from the TIM3 pin
The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
8.4.6 Timer 6
Timer 6 can select one of the following count sources:
•f(XIN)/16 or f(XCIN)/16
•Timer 5 overflow signal
The count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for timer 6, the timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) /16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN) /16 is not selected as the timer 3 count source. So set both bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before the execution of the STP instruction
(f(XIN) /16 is selected as timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected.
As a result of the above procedure, the program can start under a stable clock.
: When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes f(XCIN).
The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
8.4.4 Timer 4
Timer 4 can select one of the following count sources:
•f(XIN)/16 or f(XCIN)/16
•f(XIN)/2 or f(XCIN)/2
•f(XCIN)
The count source of timer 3 is selected by setting bits 1 and 4 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
Rev. 1.0
23
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 1
b7 b6 b5b4 b3 b2 b1 b0
Timer mode register 1 (TM1) [Address 00F4 16]
B |
Name |
Functions |
After reset |
R |
W |
0 |
Timer 1 count source |
0: f(XIN)/16 or f(XCIN)/16 (See note) |
0 |
R |
W |
|
selection bit 1 (TM10) |
1: Count source selected by bit 5 of TM1 |
|
|
|
|
|
|
|
|
|
1 |
Timer 2 count source |
0: Count source selected by bit 4 of TM1 |
0 |
R |
W |
|
selection bit 1 (TM11) |
1: External clock from TIM2 pin |
|
|
|
|
|
|
|
|
|
2 |
Timer 1 count |
0: Count start |
0 |
R |
W |
|
stop bit (TM12) |
1: Count stop |
|
|
|
|
|
|
|
|
|
3 |
Timer 2 count stop |
0: Count start |
0 |
R |
W |
|
bit (TM13) |
1: Count stop |
|
|
|
|
|
|
|
|
|
4 |
Timer 2 count source |
0: f(XIN)/16 or f(XCIN)/16 (See note) |
0 |
R |
W |
|
selection bit 2 |
1: Timer 1 overflow |
|
|
|
|
(TM14) |
|
|
|
|
5 |
Timer 1 count source |
0: f(XIN)/4096 or f(XCIN)/4096 (See note) |
0 |
R |
W |
|
selection bit 2 (TM15) |
1: External clock from TIM2 pin |
|
|
|
|
|
|
|
|
|
6 |
Timer 5 count source |
0: Timer 2 overflow |
0 |
R |
W |
|
selection bit 2 (TM16) |
1: Timer 4 overflow |
|
|
|
|
|
|
|
|
|
7 |
Timer 6 internal count |
0: f(XIN)/16 or f(XCIN)/16 (See note) |
0 |
R |
W |
|
source selection bit |
1: Timer 5 overflow |
|
|
|
|
(TM17) |
|
|
|
|
|
|
|
|
|
|
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.1 Timer Mode Register 1
Timer Mode Register 2
b7 b6 b5b4 b3 b2 b1 b0
Timer mode register 2 (TM2) [Address 00F5 16]
B |
Name |
|
|
Functions |
After reset |
R |
W |
|
0 |
Timer 3 count source |
(b6 at address 00C7 16) |
0 |
R |
W |
|||
|
selection bit (TM20) |
|
|
b0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0 0 : f(XIN)/16 or f(XCIN)/16 (See note) |
|
|
|
|
||
|
|
0 |
1 : f(XCIN) |
|
|
|
|
|
|
|
1 |
0 : |
|
|
|
|
|
|
|
1 1 : External clock from TIM3 pin |
|
|
|
|
||
1, 4 |
Timer 4 count source |
b4 |
b1 |
0 |
R |
W |
||
|
selection bits |
0 |
0 : Timer 3 overflow signal |
|
|
|
|
|
|
(TM21, TM24) |
0 |
1 : f(XIN)/16 or f(XCIN)/16 (See note) |
|
|
|
|
|
|
|
1 |
0 : f(XIN)/2 or f(XCIN)/2 (See note) |
|
|
|
|
|
|
|
1 |
1 : f(XCIN) |
|
|
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|
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|
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|
||
2 |
Timer 3 count |
0: Count start |
0 |
R |
W |
|||
|
stop bit (TM22) |
1: Count stop |
|
|
|
|
||
|
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|
|
|
||
3 |
Timer 4 count stop bit |
0: Count start |
0 |
R |
W |
|||
|
(TM23) |
1: Count stop |
|
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||
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|
||
5 |
Timer 5 count stop bit |
0: Count start |
0 |
R |
W |
|||
|
(TM25) |
1: Count stop |
|
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||
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|
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|
|
|
|
||
6 |
Timer 6 count stop bit |
0: Count start |
0 |
R |
W |
|||
|
(TM26) |
1: Count stop |
|
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|
|
||
|
|
|
|
|
|
|
||
7 |
Timer 5 count source |
0: f(XIN)/16 or f(XCIN)/16 (See note) |
0 |
R |
W |
|||
|
selection bit 1 |
1: Count source selected by bit 6 |
|
|
|
|
||
|
(TM27) |
|
of TM1 |
|
|
|
|
|
|
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|
|
|
|
|
|
|
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.2 Timer Mode Register 2
Rev. 1.0
24
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
XCIN |
CM7 |
|
|
|
|
|
|
|
|
|
|
TM15 |
|
Timer 1 latch (8) |
|
|
1/4096 |
|
|
|
|
|
8 |
|
|
|
|
|
|
XIN |
|
1/2 |
1/8 |
Timer 1 (8) |
|
|
|
TM10 |
|
|
|
|
TM12 |
8 |
|
|
|
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|
|
TM14 |
|
|
|
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|
8 |
|
|
|
|
Timer 2 latch (8) |
|
|
|
|
8 |
TIM2 |
|
TM11 |
Timer 2 (8) |
|
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|
TM13 |
8 |
|
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|
|
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|
8 |
|
|
|
|
FF16 |
|
|
|
T3SC |
Timer 3 latch (8) |
|
|
|
|
8 |
TIM3 |
|
TM20 |
Timer 3 (8) |
|
|
|
|
|
|
|
|
|
TM22 |
8 |
|
|
|
|
|
|
|
|
|
8 |
|
|
|
TM21 |
0716 |
|
|
|
Timer 4 latch (8) |
|
|
|
|
|
|
|
|
|
|
8 |
|
|
TM21 |
TM24 |
Timer 4 (8) |
|
|
|
||
|
|
|
TM23 |
8 |
|
|
|
|
|
|
|
|
TM16 |
8 |
|
|
|
|
|
|
Selection gate: |
Connected to |
|
Timer 5 latch (8) |
|
|
black side at |
|
8 |
|
|
reset |
|
|
|
|
|
TM27 |
Timer 5 (8) |
|
TM1 : Timer mode register 1 |
|
||
|
TM25 |
8 |
||
|
TM2 : Timer mode register 2 |
|
||
|
|
|
||
|
T3SC : Timer 3 count source |
|
8 |
|
|
switch bit (address 00C7 |
16) |
||
|
|
|||
|
CM : CPU mode register |
|
|
|
|
|
|
|
Timer 6 latch (8) |
|
|
|
|
8 |
|
|
|
TM17 |
Timer 6 (8) |
|
|
|
|
|
|
|
|
TM26 |
8 |
|
|
|
|
Timer 1 interrupt request
Timer 2 interrupt request
Reset
STP instruction
Timer 3 interrupt request
Timer 4 interrupt request
Timer 5 interrupt request
Timer 6 interrupt request
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2:When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3:In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8.4.3 Timer Block Diagram
Rev. 1.0
25
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.5 SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchronous clock I/O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as port P20–P22.
Bit 3 of the serial I/O mode register (address 00EB16) selects whether the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN pin for serial I/O, set the corresponding bit of the port P2 direction register (address 00C516) to “0.”
The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock.
XCIN
|
1/2 |
|
|
|
Data bus |
XIN |
1/2 |
1/2 |
Frequency divider |
||
|
CM7 |
|
1/2 1/4 |
1/8 |
1/16 |
|
|
|
|
|
SM1 |
|
|
Synchronous |
SM2 |
|
SM0 |
|
|
circuit |
|
|
|
|
P20 Latch |
|
|
|
|
SCLK |
SM3 |
|
Serial I/O counter (8) |
|
|
|
|
|
|
||
|
P21 Latch |
|
|
|
|
SOUT |
SM3 |
SM5 : LSB |
MSB |
|
|
|
|
|
(See note) |
||
|
|
|
|
||
SIN |
|
Serial I/O shift register (8) |
|
|
|
|
SM6 |
|
8 |
|
|
|
|
|
|
|
Selection gate: Connect to black side at reset.
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O interrupt request
Note : When the data is set in the serial I/O register (address 00EA16), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
Rev. 1.0
26
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Internal clock : The serial I/O counter is set to “7” during the write cycle into the serial I/O register (address 00EA16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.”
External clock : The an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 8.5.2. When using an external clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB.
2:When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
(Note)
Serial I/O output
SOUT
D0 D1 D2 D3 D4 D5 D6 D7
Serial I/O input
SIN
Interrupt request bit is set to “1”
Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
Fig. 8.5.2 Serial I/O Timing (for LSB first)
Rev. 1.0
27
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0 |
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Serial I/O mode register (SM) [Address 00EB16] |
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B |
Name |
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Functions |
After reset |
R W |
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0, 1 Internal synchronous |
b1 b0 |
0 |
R W |
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clock selection bits |
0 |
0: f(XIN)/4 or f(XCIN)/4 |
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(SM0, SM1) |
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0 |
1: f(XIN)/16 or f(XCIN)/16 |
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1 |
0: f(XIN)/32 or f(XCIN)/32 |
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1 |
1: f(XIN)/64 or f(XCIN)/64 |
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2 |
Synchronous clock |
0: External clock |
0 |
R W |
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selection bit |
(SM2) |
1: Internal clock |
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3 |
Port function |
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0: P20, P21 |
0 |
R W |
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selection bit |
(SM3) |
1: SCLK, SOUT |
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4 |
Fix this bit to “0.” |
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0 |
R W |
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5 |
Transfer direction |
0: LSB first |
0 |
R W |
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selection bit |
(SM5) |
1: MSB first |
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6 |
Transfer clock input |
0: Input signal from SIN pin |
0 |
R W |
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pin selection bit (SM6) |
1: Input signal from SOUT pin |
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7 |
Fix this bit to “0.” |
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0 |
R W |
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Fig. 8.5.3 Serial I/O Mode Register
Rev. 1.0
28
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6 MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications.
Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions.
This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits.
Table 8.6.1 Multi-master I2C-BUS Interface Functions
Item |
Function |
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In conformity with Philips I2C-BUS |
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standard: |
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10-bit addressing format |
Format |
7-bit addressing format |
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High-speed clock mode |
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Standard clock mode |
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standard: |
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Master transmission |
Communication mode |
Master reception |
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Slave transmission |
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Slave reception |
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SCL clock frequency |
16.1 kHz to 400 kHz (at f = 4 MHz) |
f : System clock = f(XIN)/2
Note : We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
Serial |
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Noise |
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Data |
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data |
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elimination |
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control |
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circuit |
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circuit |
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AL
circuit
BB circuit
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Serial |
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clock |
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elimination |
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control |
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circuit |
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circuit |
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b7 I2C address register (S0D) b0
SAD6 |
SAD5 |
SAD4 |
SAD3 |
SAD2 |
SAD1 |
SAD0 |
RBW |
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Interrupt |
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Interrupt |
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generating |
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request signal |
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Address comparator
b7 |
b0 |
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I2C data shift register |
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S0 |
b7 |
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b0 |
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AL AAS AD0 LRB |
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MST TRX |
BB |
PIN |
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I 2C status |
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register (S1) |
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Internal data bus |
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b7 |
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b0 |
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b7 |
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b0 |
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ACK |
ACK |
FAST |
CCR4 |
CCR3 |
CCR2 |
CCR1 |
CCR0 |
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BSEL1 |
BSEL0 |
10BIT |
ALS |
ESO |
BC2 |
BC1 |
BC0 |
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MODE |
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SAD |
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I2C control register (S1D) |
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I2C clock control register (S2) |
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System clock (φ) |
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Clock division |
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Bit counter |
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Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface
Rev. 1.0
29
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the
ESO bit of the I2C control register (address 00F916) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register
(address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register1(S0) [Address 00F616]
B |
Name |
Functions |
After reset |
R |
W |
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0 |
D0 to D7 |
This is an 8-bit shift register to store |
Indeterminate |
R |
W |
to |
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receive data and write transmit data. |
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7 |
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Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
Rev. 1.0
30