Global LCD Panel Exchange Center |
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LP156WF1
Liquid Crystal Display
Product Specification
SPECIFICATION
FOR
APPROVAL
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Preliminary Specification |
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Final Specification |
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Title |
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15.5” Full HD TFT LCD |
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Customer |
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Sony |
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SUPPLIER |
LG Display Co., Ltd. |
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*MODEL |
LP156WF1 |
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MODEL |
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Suffix |
TLC1 |
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*When you obtain standard approval, |
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please use the above model name without suffix |
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APPROVED BY |
SIGNATURE |
/
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Please return 1 copy for your confirmation with your signature and comments.
APPROVED BY |
SIGNATURE |
K. J. Kwon / S.Manager
REVIEWED BY
S. R. Kim / Manager
PREPARED BY
C.J. Park / Engineer
Products Engineering Dept. LG Display Co., Ltd
Ver. 1.0 |
Dec. 10, 2009 |
1 / 29 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LP156WF1
Liquid Crystal Display
Product Specification
Contents
No |
ITEM |
Page |
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COVER |
1 |
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CONTENTS |
2 |
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RECORD OF REVISIONS |
3 |
1 |
GENERAL DESCRIPTION |
4 |
2 |
ABSOLUTE MAXIMUM RATINGS |
5 |
3 |
ELECTRICAL SPECIFICATIONS |
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3-1 |
ELECTRICAL CHARACTREISTICS |
6-7 |
3-2 |
INTERFACE CONNECTIONS |
8 |
3-3 |
LVDS SIGNAL TIMING SPECIFICATION |
9-10 |
3-3 |
SIGNAL TIMING SPECIFICATIONS |
11-12 |
3-4 |
SIGNAL TIMING WAVEFORMS |
12 |
3-5 |
COLOR INPUT DATA REFERNECE |
13 |
3-6 |
POWER SEQUENCE |
14 |
4 |
OPTICAL SFECIFICATIONS |
15-17 |
5 |
MECHANICAL CHARACTERISTICS |
18-21 |
A |
APPENDIX. LPL PROPOSAL FOR SYSTEM COVER DESIGN |
22-24 |
6 |
RELIABLITY |
25 |
7 |
INTERNATIONAL STANDARDS |
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7-1 |
SAFETY |
26 |
7-2 |
EMC |
26 |
8 |
PACKING |
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8-1 |
DESIGNATION OF LOT MARK |
27 |
8-2 |
PACKING FORM |
27 |
9 |
PRECAUTIONS |
28-29 |
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Ver. 1.0 |
Dec. 10, 2009 |
2 / 29 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LP156WF1
Liquid Crystal Display
Product Specification
RECORD OF REVISIONS
Revision No |
Revision Date |
Page |
Description |
EDID |
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ver |
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0.0 |
Sep. 19. 2009 |
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First Draft (Preliminary Specification) |
0.0 |
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0.1 |
Oct. 1. 2009 |
6 |
Correct LED Power Inrush Current 1.5 1500 |
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11-12 |
Add Tentative Timing Table for 50Hz and 40Hz Refresh Rate |
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0.2 |
Nov 2. 2009 |
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Active area size 15.6inch 15.5inch |
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1.0 |
Dec. 10, 2009 |
- |
Final Draft |
1.0 |
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Ver. 1.0 |
Dec. 10, 2009 |
3 / 29 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LP156WF1
Liquid Crystal Display
Product Specification
1. General Description
The LP156WF1 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally white mode. This TFT-LCD has 15.5 inches diagonally measured active display area with FHD resolution (1920 horizontal by 1080 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144 colors. The LP156WF1 has been designed to apply the interface method that enables low power, high speed, low EMI. The LP156WF1 is intended to support applications where thin thickness, low power are critical factors and graphic displays are important. In combination with the vertical arrangement of the subpixels, the LP156WF1 characteristics provide an excellent flat display for office automation products such as Notebook PC. 
connector User
40
Pin
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EEPROM Block |
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for EDID |
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EEPROM Block |
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1 |
1920 |
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for Tcon Operating |
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TFT-LCD Panel |
LVDS |
Timing Control |
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(HD, GIP, TN) |
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2port |
(Tcon) Block |
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Mi |
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1080 |
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ni-L |
V |
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DVCC |
TCLKs |
DS |
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VCC |
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DVCC, AVDD |
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Source Driver |
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Power |
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VGH, VGL, GMA |
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Block |
GIP CLKs, DSC |
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(Bottom Bent) |
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VLED |
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VOUT_LED |
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LED Backlight Ass’y |
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LED Driver |
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FB1~6 |
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LED_EN |
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Block |
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PWM |
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Control & Data
Power 
EDID signal & Power
General Features
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Active Screen Size |
15.5 inches diagonal |
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Outline Dimension |
359.3(H, typ.) Ý 209.5(V, typ.) Ý 5.7(D,max) |
[mm]] |
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Pixel Pitch |
0.17925 mm x 0.17925 mm |
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Pixel Format |
1920 horiz. By 1080 vert. Pixels RGB strip arrangement |
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Color Depth |
6-bit, 262,144 colors |
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Luminance, White |
220 cd/m2(Typ.5 point) |
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Power Consumption |
Total 6.94 Watt(Typ.) @ LCM circuit 1.74 Watt (Typ.), B/L input 5.2 Watt (Typ.) |
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Weight |
470g ( Max.) / 450g ( Typ.) |
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Display Operating Mode |
Transmissive mode, normally white |
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Surface Treatment |
Hard Coating(3H), Glare treatment of the front polarizer |
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RoHS Compliance |
Yes |
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BFR / PVC / As Free |
Yes for all |
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Ver. 1.0 |
Dec. 10, 2009 |
4 / 29 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LP156WF1
Liquid Crystal Display
Product Specification
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter |
Symbol |
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Units |
Notes |
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Min |
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Max |
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Power Input Voltage |
VCC |
-0.3 |
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4.0 |
Vdc |
at 25 5 C |
Operating Temperature |
TOP |
0 |
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50 |
C |
1 |
Storage Temperature |
HST |
-20 |
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60 |
C |
1 |
Operating Ambient Humidity |
HOP |
10 |
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90 |
%RH |
1 |
Storage Humidity |
HST |
10 |
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90 |
%RH |
1 |
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Note : 1. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature should be 39 C Max, and no condensation of water.
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90% 80% |
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60 |
60% |
Wet Bulb |
50 |
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Temperature [ |
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40 |
40% |
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30 |
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20 |
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20% |
10 |
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0 |
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10% |
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Humidity[(%)RH]
Storage
Operation
-20 |
0 |
10 |
20 |
30 |
40 |
50 |
60 |
70 |
80 |
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Dry Bulb Temperature [ |
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Ver. 1.0 |
Dec. 10, 2009 |
5 / 29 |
|
|
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LP156WF1
Liquid Crystal Display
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
The LP156WF1 requires two power inputs. The first logic is employed to power the LCD electronics and to drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS |
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Values |
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Unit |
Notes |
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Min |
Typ |
Max |
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LOGIC : |
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Power Supply Input Voltage |
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VCC |
3.0 |
3.3 |
3.6 |
V |
1 |
Power Supply Input Current |
Mosaic |
ICC |
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530 |
610 |
mA |
2 |
Power Consumption |
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PCC |
- |
1.74 |
2.0 |
W |
2 |
Power Supply Inrush Current |
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ICC_P |
- |
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1500 |
mA |
3 |
LVDS Impedance |
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ZLVDS |
90 |
100 |
110 |
ȳ |
4 |
BACKLIGHT : ( with LED Driver) |
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LED Power Input Voltage |
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VLED |
7.0 |
12.0 |
21.0 |
V |
5 |
LED Power Input Current |
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ILED |
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433 |
500 |
mA |
6 |
LED Power Consumption |
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PLED |
- |
5.2 |
6.0 |
W |
6 |
LED Power Inrush Current |
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ILED_P |
- |
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1500 |
mA |
7 |
PWM Duty Ratio |
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5 |
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100 |
% |
8 |
PWM Jitter |
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0 |
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0.2 |
% |
9 |
PWM Impedance |
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ZPWM |
20 |
40 |
60 |
kȳ |
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PWM Frequency |
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FPWM |
200 |
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1000 |
Hz |
10 |
PWM High Level Voltage |
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VPWM_H |
3.0 |
- |
5.3 |
V |
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PWM Low Level Voltage |
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VPWM_L |
0 |
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0.3 |
V |
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LED_EN Impedance |
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ZPWM |
20 |
40 |
60 |
kȳ |
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LED_EN High Voltage |
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VLED_EN_H |
3.0 |
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5.3 |
V |
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LED_EN Low Voltage |
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VLED_EN_L |
0 |
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0.3 |
V |
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Life Time |
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12,000 |
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Hrs |
11 |
Ver. 1.0 |
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Dec. 10, 2009 |
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6 / 29 |
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
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LP156WF1 |
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Liquid Crystal Display |
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Product Specification |
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Note) |
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1. |
The measuring position is the connector of LCM and the test conditions are under 25 , fv = 60Hz, |
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Black pattern. |
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2. |
The specified Icc current and power consumption are under |
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the Vcc = 3.3V , 25 , fv = 60Hz condition and Mosaic pattern. |
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3. This Spec. is the max load condition for the cable impedance designing. 
4. The below figures are the measuring Vcc condition and the Vcc control block LGD used. 
The Vcc condition is same as the minimum of T1 at Power on sequence.
Rising time |
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3.3V |
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90% |
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Vcc |
10% |
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0V |
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0.5ms |
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5. |
This impedance value is needed for proper display and measured form LVDS Tx to the mating connector. |
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6. |
The measuring position is the connector of LCM and the test conditions are under 25 . |
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7. |
The current and power consumption with LED Driver are under the Vled = 12.0V , 25 , Dimming of |
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Max luminance and White pattern with the normal frame frequency operated(60Hz). |
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8. |
The below figures are the measuring Vled condition |
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12.0V |
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and the Vled control block LGD used. |
Rising time 90% |
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VLED control block is same with Vcc control block. |
VLED |
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0V |
10% |
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0.5ms |
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9. |
The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue. |
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10.If Jitter of PWM is bigger than maximum, it may induce flickering.
11.This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for more consistent brightness control at any specific level desired.
12.The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum value specified in table 7. under general user conditionU
Ver. 1.0 |
Dec. 10, 2009 |
7 / 29 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LP156WF1
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
Pin |
Symbol |
Description |
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Notes |
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1 |
Test Loop |
Test loop to 34pin |
[Interface Chip] |
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2 |
VCC |
LCD Logic and driver power (3.3V Typ.) |
1. LCD : |
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3 |
VCC |
LCD Logic and driver power (3.3V Typ.) |
SiW, ST2_BS(LCD Controller) |
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4 |
V EEDID |
DDC Power (3.3V) |
Including LVDS Receiver. |
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5 |
Bist |
LCD Panel Self Test Enable |
2. System : SiW LVDSRx or equivalent |
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6 |
Clk EEDID |
DDC Clock |
* Pin to Pin compatible with LVDS |
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7 |
DATA EEDID |
DDC Data |
[Connector] |
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8 |
ORX0- |
Negative LVDS differential data input |
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20455-040E-0x, I-PEX or its compatibles |
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9 |
ORX0+ |
Positive LVDS differential data input |
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10 |
GND |
High Speed Ground |
[Mating Connector] |
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11 |
ORX1- |
Negative LVDS differential data input |
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20345-#40E-## series |
or equivalent |
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12 |
ORX1+ |
Positive LVDS differential data input |
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13 |
GND |
High Speed Ground |
[Connector pin arrangement] |
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14 |
ORX2- |
Negative LVDS differential data input |
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15 |
ORX2+ |
Positive LVDS differential data input |
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16 |
GND |
High Speed Ground |
40 |
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1 |
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17 |
ORXC- |
Negative LVDS differential clock input |
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18 |
ORXC+ |
Positive LVDS differential clock input |
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19 |
GND |
High Speed Ground |
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[LCD Module Rear View] |
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20 |
ERX0- |
Negative LVDS differential data input |
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21 |
ERX0+ |
Positive LVDS differential data input |
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19 |
GND |
High Speed Ground |
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23 |
ERX1- |
Negative LVDS differential data input |
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24 |
ERX1+ |
Positive LVDS differential data input |
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19 |
GND |
High Speed Ground |
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26 |
ERX2- |
Negative LVDS differential data input |
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27 |
ERX2+ |
Positive LVDS differential data input |
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19 |
GND |
High Speed Ground |
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29ERXC-
Negative LVDS differential clock input
30ERXC+ 
Positive LVDS differential clock input
31
GND
LED Backlight Ground
32 |
GND |
LED Backlight Ground |
33 |
GND |
LED Backlight Ground |
34 |
Test Loop |
Test loop to 1pin |
35 |
PWM |
System PWM Signal input for dimming |
36 |
LED_EN |
LED Backlight On/Off |
37 |
NC |
No Connection |
38 |
VLED |
LED Backlight Power (7V-21V) |
39 |
VLED |
LED Backlight Power (7V-21V) |
40 |
VLED |
LED Backlight Power (7V-21V) |
Ver. 1.0 |
Dec. 10, 2009 |
8 / 29 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LP156WF1
Liquid Crystal Display
Product Specification
3-3. LVDS Signal Timing Specifications |
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3-3-1. DC Specification |
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Description |
Symb |
Min |
Max |
Unit |
Notes |
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ol |
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LVDS Differential Voltage |
|VID| |
100 |
600 |
mV |
- |
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LVDS Common mode Voltage |
VCM |
0.6 |
1.8 |
V |
- |
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LVDS Input Voltage Range |
VIN |
0.3 |
2.1 |
V |
- |
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3-3-2. AC Specification |
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Description |
Symbol |
Min |
Max |
Unit |
Notes |
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tSKEW |
- 400 |
+ 400 |
ps |
85MHz > Fclk ˻ |
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LVDS Clock to Data Skew Margin |
65MHz |
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tSKEW |
- 600 |
+ 600 |
ps |
65MHz > Fclk ˻ |
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25MHz |
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LVDS Clock to Clock Skew Margin (Even |
tSKEW_EO |
- 1/7 |
+ 1/7 |
Tclk |
- |
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to Odd) |
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Maximum deviation |
FDEV |
- |
· 3 |
% |
- |
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of input clock frequency during SSC |
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Maximum modulation frequency |
FMOD |
- |
200 |
KHz |
- |
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of input clock during SSC |
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Ver. 1.0 |
Dec. 10, 2009 |
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9 / 29 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
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