LG Display LC420WUH-SCM1 Specification

LC420WUH

Product Specification

SPECIFICATION

FOR

APPROVAL

( ) Preliminary Specification

( ● ) Final Specification

Title	42.0” WUXGA TFT LCD

BUYER	General
MODEL

SUPPLIER	LG Display Co., Ltd.
*MODEL	LC420WUH
SUFFIX	SCM1

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY

SIGNATURE

DATE

/

/

/

Please return 1 copy for your confirmation with your signature and comments.

SIGNATURE

APPROVED BY		DATE
P. Y KIM / Team Leader
REVIEWED BY
S. J LEE / Project Leader
PREPARED BY
S. M Lee / Engineer

TV Products Development Dept.

LG Display LCD Co., Ltd

Ver.1.2	1 /41

LC420WUH

Product Specification

CONTENTS

Number	ITEM	Page
	COVER	1
	CONTENTS	2
	RECORD OF REVISIONS	3
1	GENERAL DESCRIPTION	4
2	ABSOLUTE MAXIMUM RATINGS	5
3	ELECTRICAL SPECIFICATIONS	6
3-1	ELECTRICAL CHARACTERISTICS	6
3-2	INTERFACE CONNECTIONS	12
3-3	SIGNAL TIMING SPECIFICATIONS	15
3-4	DATA MAPPING AND TIMING	18
3-5	PANEL PIXEL STRUCTURE	19
3-6	POWER SEQUENCE	20
4	OPTICAL SPECIFICATIONS	21
5	MECHANICAL CHARACTERISTICS	25
6	RELIABILITY	28
7	INTERNATIONAL STANDARDS	29
7-1	SAFETY	29
7-2	ENVIRONMENT	29
8	PACKING	30
8-1	INFORMATION OF LCM LABEL	30
8-2	PACKING FORM	30
9	PRECAUTIONS	31
9-1	MOUNTING PRECAUTIONS	31
9-2	OPERATING PRECAUTIONS	31
9-3	ELECTROSTATIC DISCHARGE CONTROL	32
9-4	PRECAUTIONS FOR STRONG LIGHT EXPOSURE	32
9-5	STORAGE	32
9-6	HANDLING PRECAUTIONS FOR PROTECTION FILM	32

Ver.1.2	2 /41

LC420WUH

			Product Specification
		RECORD OF REVISIONS
Revision No.	Revision Date	Page		Description
1.2	Mar. 16..2010	-		Final Specification

Ver.1.2	3 /41

LC420WUH

Product Specification

1. General Description

The LC420WUH is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally black mode. It has a 42.02 inch diagonally measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot. Therefore, it can present a palette of more than 16.7M(true) colors.

It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important.

Power (VCC,VDD,HVDD,VGH,VGL)
Source Control Signal			Source Driver Circuit
Gate Control Signal	CN1	S1	S1920
	(60pin)
Gamma Reference Voltage		G1
mini-LVDS (RGB) for Left drive
Power (VCC,VDD,HVDD,VGH,VGL)			TFT - LCD Panel
Source Control Signal			(1920 × RGB × 1080 pixels)
			[Gate In Panel]
Gate Control Signal
	CN2
	(60pin)
Gamma Reference Voltage
mini-LVDS (RGB) for Right drive		G1080
			Scanning Block 2
High Input	CN4&5, 3pin*2ea, 8 Lamps/@ 68 mA		Scanning Block 1
High Input	CN6&7, 3pin*2ea, 8 Lamps/@ 68 mA		Scanning Block 2

General Features

	Active Screen Size	42.02 inches(1067.31mm) diagonal
	Outline Dimension	983.0(H) x 576.0 (V) x 35.5 mm(D) (Typ.)
	Pixel Pitch	0.4845 mm x 0.4845 mm
	Pixel Format	1920	horiz. by 1080 vert. Pixels, RGB stripe arrangement
	Color Depth	8-bit,	16.7 M colors ( 1.06B colors @ 10 bit (D) System Output )
	Drive IC Data Interface	Source D-IC : 8-bit mini-LVDS, gamma reference voltage, and control signals
		Gate D-IC : Gate In Panel
	Luminance, White	500 cd/m2 (Center 1point ,Typ.)
	Viewing Angle (CR>10)	Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
	Power Consumption	Total 158.0 W (Typ.)
		(Logic=9.0 W with T-CON, Backlight=149W @ with Inverter Iout duty : 100%)
	Weight	8.7Kg (Typ.)
	Display Mode	Transmissive mode, Normally black
	Surface Treatment	Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)

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LC420WUH

Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or damage to the LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter	Symbol		Value		Unit	Note
		Min		Max
Logic Power Voltage	VCC	-0.5		+4.0	VDC
Gate High Voltage	VGH	+18.0		+30.0	VDC
Gate Low Voltage	VGL	-8.0		-4.0	VDC
Source D-IC Analog Voltage	VDD	-0.3		+18.0	VDC	1
Gamma Ref. Voltage (Upper)	VGMH	½VDD-0.5		VDD+0.5	VDC
Gamma Ref. Voltage (Low)	VGML	-0.3		½ VDD+0.5	VDC
BL Operating Input Voltage	VBL	600		1150	VRMS
(One Side)
Panel Front Temperature	TSUR	-		+68	°C	4
Operating Temperature	TOP	0		+50	°C
Storage Temperature	TST	-20		+60	°C
						2,3
Operating Ambient Humidity	HOP	10		90	%RH
Storage Humidity	HST	10		90	%RH

Note: 1. Ambient temperature condition (Ta = 25 ± 2 °C )

2.Temperature and relative humidity range are shown in the figure below. Wet bulb temperature should be Max 39 °C and no condensation of water.

3.Gravity mura can be guaranteed below 40 condition.

4.The maximum operating temperature is based on the test condition that the surface temperature of display area is less than or equal to 68 with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 68 . The range of operating temperature may degrade in case of improper thermal management in final product design.

								90%
							60
									60%
	Wet Bulb					50				Storage
	Temperature [°C]				40				Humidity [(%)RH]
									40%	Operation
				30
			20
		10
	0								10%
-20	0	10	20	30	40	50	60	70	80
		Dry Bulb Temperature [°C]

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LC420WUH

Product Specification

3. Electrical Specifications

3-1. Electrical Characteristics

It requires several power inputs. The VCC is the basic power of LCD Driving power sequence, Which is used to logic power voltage of Source D-IC and GIP.

Table 2. ELECTRICAL CHARACTERISTICS

Parameter	Symbol	Condition	MIN	TYP	MAX	Unit	Note
Logic Power Voltage	VCC	-	3.0	3.3	3.6	VDC
Logic High Level Input Voltage	VIH		2.7		VCC	VDC
Logic Low Level Input Voltage	VIL		0		0.6	VDC
Source D-IC Analog Voltage	VDD	-	16.05	16.25	16.45	VDC
Half Source D-IC Analog	H_VDD	-	7.9	8.00	8.1	VDC
Voltage
Gamma Reference Voltage	VGMH	(GMA1 ~ GMA9)	½*VDD		VDD-0.2
	VGML	(GMA10 ~ GMA18)	0.2		½*VDD
Common Voltage	Vcom	-	6.6	6.9	7.2	V
Mini-LVDS Clock frequency	CLK	3.0V≤VCC ≤3.6V			312	MHz
mini-LVDS input Voltage	VIB		0.7 + (VID/2)		(VCC-1.2)	V
(Center)					− VID / 2
mini-LVDS input Voltage	VIB				0.8	V
Distortion (Center)		Mini-LVDS Clock
							5
mini-LVDS differential	VID	and Data	150		800	mV
Voltage range
mini-LVDS differential	VID		25		800	mV
Voltage range Dip
Gate High Voltage	VGH		27.39 @ 25	27.69 @ 25	27.99 @ 25	VDC
			28.85 @ 0	29.15 @ 0	29.45 @ 0
Gate Low Voltage	VGL		-5.5	-5.3	-5.1	VDC
GIP Bi-Scan Voltage	VGI_P	-	VGL	-	VGH	VDC
	VGI_N
GIP Refresh Voltage	VGH	-	VGL	-	VGH	V
	even/odd
GIP Start Pulse Voltage	VST	-	VGL	-	VGH	V
GIP Operating Clock	GCLK	-	VGL	-	VGH	V
Total Power Current	ILCD	-	525	750	975	mA	2
Total Power Consumption	PLCD	-		9.0		Watt	2

Note: 1. The specified current and power consumption are under the VLCD=12V., 25 ± 2°C, fV=120Hz condition whereas mosaic pattern(8 x 6) is displayed and fV is the frame frequency.

2.The above spec is based on the basic model.

3.All of the typical gate voltage should be controlled within 1% voltage level

4.Ripple voltage level is recommended under 10%

5.In case of mini-LVDS signal spec, refer to Fig 2 for the more detail.

6.Logic level Input Signal : SOE, POL, GSP, H_CONV, OPT_N

7.HVDD Voltage level is half of VDD and it should be between Gamma9 and Gamma10

Ver.1.2	6 /41

LC420WUH

Product Specification

VGH

VGHM

GND

VGL

Without GPM With GPM

FIG. 1 Gate Output Wave form without GPM and with GPM

VID
VID
		VIB
VCM (0V)		VIB
VID
VID
* Differential Probe	* Active Probe
FIG. 2 Description of VID,	VIB,	VID

* Source PCB

FIG. 3 Measure point

Ver.1.2	7 /41

										LC420WUH
				Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
							Values
	Parameter			Symbol					Unit	Note
						Min	Typ	Max
	Backlight Assembly :
	Operating Voltage			VBL1		-	1000	-
									VRMS	1, 2
	(one side,fBL=63KHz, IBL= 136 mARMS )			VBL2		-	1000	-
				IBL1		-	68	-
	Operating Current (one side)								mARMS	1
				IBL2		-	68	-
	Striking Voltage @ 0			VS		-	-	1110	VRMS	1, 3
	(Open Lamp Voltage @ one side)
	Operating Frequency			fBL		61	63	65	kHz	4
	Striking Time			S TIME		1.5	-	-	sec	3
	Power Consumption			PBL			149		Watt	6
	Burst Dimming Duty			{a/T} * 100		20		100	%	9
	Burst Dimming Frequency	PAL		1/T			100		Hz	9
		NTSC					120
	Parameter			Symbol			Values		Unit	Note
						Min	Typ	Max
	Lamp : (APPENDIX-V)
	Lamp Voltage (one side)			VLAMP		815	1100	1135	VRMS	2
	Lamp Current (one side)			ILAMP		3.0	8.5	9.0	mARMS
	Discharge Stabilization Time			TS		-	-	3	Min	5
	Lamp Frequency			f LAMP		661	63	65	KHz
	Established Starting Voltage @ 0			VS				1110	VRMS	3
	Life Time					50,000	60,000		Hrs	7

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LC420WUH

Product Specification

Note : The design of the inverter must have specifications for the lamp in LCD Assembly. The electrical characteristics of inverter are based on High-High Driving type.

The performance of the lamps in LCM, for example life time or brightness, is extremely influenced by the characteristics of the DC-AC inverter. So, all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. When you design or order the inverter, please make sure unwanted lighting caused by the mismatch of the lamp and the inverter (no lighting, flicker, etc) has never been occurred. When you confirm it, the LCD– Assembly should be operated in the same condition as installed in your instrument.

Do not attach a conductive tape to lamp connecting wire.

If you attach conductive tape to the lamp wire, not only luminance level can be lower than typical one

but also inverter operate abnormally on account of leakage current which is generated between lamp wire and conductive tape.

1. Specified values are defined for a Backlight Assembly.

( SCAN Block1 IBL:8 lamps, 8.5mA/Lamp and SCAN Block2 IBL:8 lamps, 8.5mA/Lamp ) and each value is measured at duty 100%.

The lamp voltage must be synchronized between Block1 and Block2. (The frequency and phase must be the same)

2.Operating voltage is measured at 25 ± 2°C(after 2hr.aging). The variance range for operating voltage is ± 10%.

3.The Striking Voltage (Open Lamp Voltage) [ Vopen ] should be applied to the lamps more than Striking

time (S TIME) for start-up. Inverter Striking Voltage must be more than Established Starting Voltage of lamp. Otherwise, the lamps may not be turned on. The used lamp current is typical value.

When the Striking Frequency is higher than the Operating Frequency, the parasitic capacitance can cause inverter shut down, therefore It is recommended to check it.

Vs = (Vpk-pk) / [ 2*root(2)]

Ver.1.2	9 /41

LC420WUH

Product Specification

4.Lamp frequency may produce interference with horizontal synchronous frequency. As a result this may cause beat on the display. Therefore, lamp frequency shall be away as much as possible from the horizontal synchronous frequency and its harmonics range in order to prevent interference.

There is no reliability problem of lamp, if the operation frequency is typ ± 5KHz. But it should be applied in less than ABSOLUTE MAXIMUM RATINGS max voltage

5.The brightness of the lamp after lighted for 5minutes is defined as 100%.

TS is the time required for the brightness of the center of the lamp to be not less than 95% at typical current. The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.

6.Maximum level of power consumption is measured at initial turn on.

Typical level of power consumption is measured after 2hrs aging at 25 ± 2°C.(@I out duty : 100%)

7.The life time is determined as the time at which brightness of the lamp is 50% compared to that of initial value at the typical lamp current on condition of continuous operating at 25 ± 2°C, based on duty 100%.

8.The output of the inverter must have symmetrical(negative and positive) voltage and current waveform (Unsymmetrical ratio is less than 10%). Please do not use the inverter which has not only unsymmetrical voltage and current but also spike wave.

Requirements for a system inverter design, which is intended to achieve better display performance, power efficiency and more reliable lamp characteristics.

It can help increase the lamp lifetime and reduce leakage current.

a.The asymmetry rate of the inverter waveform should be less than 10%.

b.The distortion rate of the waveform should be within √2 ±10%.

* Inverter output waveform had better be more similar to ideal sine wave.

* Asymmetry rate:

I p

| I p – I –p | / IRMS x 100%

* Distortion rate

I -p

I p (or I –p) / IRMS

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LC420WUH

Product Specification

9. The reference method of burst dimming duty ratio.

T

A

SCAN_Block1 or

SCAN_Block2

Output of Inverter to Lamp

90%

a

Point A

SCAN Block1 or SCAN Block2 PWM duty ={ A/T } * 100

Point A : rising time 90% of Iout point .

Point B : falling starting point .

I out duty = { a/T } * 100

+3.3V TTL

I-out

Point B

SCAN Block1 or SCAN Block2 Frequency = 1/T

We recommend not to be much different between SCAN BLK 1 or SCAN BLK2 duty and Iout duty .

Dimming current output rising and falling time may produce humming and inverter trans’ sound noise.

Burst dimming duty should be 100% for more than 1second after turn on.

Equipment

Oscilloscope :TDS3054B(Tektronix)

Current Probe : P6022 AC (Tektronix)

High Voltage Probe: P5100(Tektronix)

10. The Cable between the backlight connector and its inverter power supply should be connected directly with a minimized length. The longer cable between the backlight and the inverter may cause the lower luminance of lamp and may require more higher starting voltage ( Vs ).

11.The operating current must be measured as near as backlight assembly input.

12.The operating current unbalance between left and right side for each scanning block must be under 10% of Typical current.

│Left(Master) current – Right(Slave) Current│ 10% of typical current

Ver.1.2	11 /41

LC420WUH

Product Specification

3-2. Interface Connections

This LCD module employs two kinds of interface connection, two 60-pin FFC connector are used for the module electronics and two 3-pin Balance PCB connectors are used for the integral backlight system.

3-2-1. LCD Module

-LCD Connector (CN1): TF06L-60S-0.5SH (Manufactured by HRS) or Equivalent

Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION

No	Symbol	Description		No	Symbol	Description
1	GND	Ground		31	LLV3 -	Left Mini LVDS Receiver Signal(3-)
2	LTD_OUT	LTD OUTPUT		32	LLV3 +	Left Mini LVDS Receiver Signal(3+)
3	GCLK1	GIP GATE Clock 1		33	LCLK -	Left Mini LVDS Receiver Clock Signal(-)
4	GCLK2	GIP GATE Clock 2		34	LCLK +	Left Mini LVDS Receiver Clock Signal(+)
5	GCLK3	GIP GATE Clock 3		35	LLV2 -	Left Mini LVDS Receiver Signal(2-)
6	GCLK4	GIP GATE Clock 4		36	LLV2 +	Left Mini LVDS Receiver Signal(2+)
7	GCLK5	GIP GATE Clock 5		37	LLV1 -	Left Mini LVDS Receiver Signal(1-)
8	GCLK6	GIP GATE Clock 6		38	LLV1 +	Left Mini LVDS Receiver Signal(1+)
9	VGI_N	VGL		39	LLV0 -	Left Mini LVDS Receiver Signal(0-)
10	VGI_P	VGH		40	LLV0 +	Left Mini LVDS Receiver Signal(0+)
11	VGH_ODD	GIP Panel VDD for Odd GATE TFT		41	GND	Ground
12	VGH_EVEN	GIP Panel VDD for Even GATE TFT		42	SOE	Source Output Enable SIGNAL
13	VGL	GATE Low Voltage		43	POL	Polarity Control Signal
14	VST	VERTICAL START PULSE		44	GSP	GATE Start Pulse
15	GND	Ground		45	H_CONV	"H“ H 2dot Inversion/ "L" H 1dot Inversion
16	VCOM_L_FB	VCOM Left Feed-Back Output		46	OPT_N	“H” Normal Display
17	VCOM_L	VCOM Left Input		47	GND	Ground
18	GND	Ground		48	GMA 18	GAMMA VOLTAGE 18 (Output From LCD)
19	VDD	Driver Power Supply Voltage		49	GMA 16	GAMMA VOLTAGE 16
20	VDD	Driver Power Supply Voltage		50	GMA 15	GAMMA VOLTAGE 15
21	H_VDD	Half Driver Power Supply Voltage		51	GMA 14	GAMMA VOLTAGE 14
22	H_VDD	Half Driver Power Supply Voltage		52	GMA 12	GAMMA VOLTAGE 12
23	GND	Ground		53	GMA 10	GAMMA VOLTAGE 10 (Output From LCD)
24	VCC	Logic Power Supply Voltage		54	GMA 9	GAMMA VOLTAGE 9 (Output From LCD)
25	VCC	Logic Power Supply Voltage		55	GMA 7	GAMMA VOLTAGE 7
26	GND	Ground		56	GMA 5	GAMMA VOLTAGE 5
27	LLV5 -	Left Mini LVDS Receiver Signal(5-)		57	GMA 4	GAMMA VOLTAGE 4
28	LLV5 +	Left Mini LVDS Receiver Signal(5+)		58	GMA 3	GAMMA VOLTAGE 3
29	LLV4 -	Left Mini LVDS Receiver Signal(4-)		59	GMA 1	GAMMA VOLTAGE 1(Output From LCD)
30	LLV4 +	Left Mini LVDS Receiver Signal(4+)		60	NC	No Connection

Note : 1. Please refer to application note (Half VDD & Gamma Voltage setting & Control signal) for details. 2. These 'input signal' (OPT_N,H_CONV) should be connected

Ver.1.2	12 /41

							LC420WUH
			Product Specification
	-LCD Connector (CN2): TF06L-60S-0.5SH(Manufactured by HRS) or Equivalent
	Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
	No	Symbol	Description		No	Symbol	Description
	1	NC	No Connection		31	RLV1 -	Right Mini LVDS Receiver Signal(1-)
	2	GMA 1	GAMMA VOLTAGE 1 (Output From LCD)		32	RLV1 +	Right Mini LVDS Receiver Signal(1+)
	3	GMA 3	GAMMA VOLTAGE 3		33	RLV0 -	Right Mini LVDS Receiver Signal(0-)
	4	GMA 4	GAMMA VOLTAGE 4		34	RLV0 +	Right Mini LVDS Receiver Signal(0+)
	5	GMA 5	GAMMA VOLTAGE 5		35	GND	Ground
	6	GMA 7	GAMMA VOLTAGE 7		36	VCC	Logic Power Supply Voltage
	7	GMA 9	GAMMA VOLTAGE 9 (Output From LCD)		37	VCC	Logic Power Supply Voltage
	8	GMA 10	GAMMA VOLTAGE 10 (Output From LCD)		38	GND	Ground
	9	GMA 12	GAMMA VOLTAGE 12		39	H_VDD	Half Driver Power Supply Voltage
	10	GMA 14	GAMMA VOLTAGE 14		40	H_VDD	Half Driver Power Supply Voltage
	11	GMA 15	GAMMA VOLTAGE 15		41	VDD	Driver Power Supply Voltage
	12	GMA 16	GAMMA VOLTAGE 16		42	VDD	Driver Power Supply Voltage
	13	GMA 18	GAMMA VOLTAGE 18 (Output From LCD)		43	GND	Ground
	14	GND	Ground		44	VCOM_R	VCOM Right Input
	15	OPT_N	“H” Normal Display		45	VCOM_R_FB	VCOM Right Feed-Back Output
	16	H_CONV	"H“ H 2dot Inversion/ "L" H 1dot Inversion		46	GND	Ground
	17	GSP	GATE Start Pulse		47	VST	VERTICAL START PULSE
	18	POL	Polarity Control Signal		48	VGL	GATE Low Voltage
	19	SOE	Source Output Enable SIGNAL		49	VGH_EVEN	GIP Panel VDD for Even GATE TFT
	20	GND	Ground		50	VGH_ODD	GIP Panel VDD for Odd GATE TFT
	21	RLV5 -	Right Mini LVDS Receiver Signal(5-)		51	VGI_P	VGH
	22	RLV5 +	Right Mini LVDS Receiver Signal(5+)		52	VGI_N	VGL
	23	RLV4 -	Right Mini LVDS Receiver Signal(4-)		53	GCLK6	GIP GATE Clock 6
	24	RLV4 +	Right Mini LVDS Receiver Signal(4+)		54	GCLK5	GIP GATE Clock 5
	25	RLV3 -	Right Mini LVDS Receiver Signal(3-)		55	GCLK4	GIP GATE Clock 4
	26	RLV3 +	Right Mini LVDS Receiver Signal(3+)		56	GCLK3	GIP GATE Clock 3
	27	RCLK -	Right Mini LVDS Receiver Clock Signal(-)		57	GCLK2	GIP GATE Clock 2
	28	RCLK +	Right Mini LVDS Receiver Clock Signal(+)		58	GCLK1	GIP GATE Clock 1
	29	RLV2 -	Right Mini LVDS Receiver Signal(2-)		59	LTD_OUT	LTD OUTPUT
	30	RLV2 +	Right Mini LVDS Receiver Signal(2+)		60	GND	Ground

Note : 1.Please refer to application note (Half VDD & Gamma Voltage setting & Control signal) for details. 2. These 'input signal' (OPT_N,H_CONV) should be connected

Source Right PCB

#1

CN 2

#60

	CN 1
	Source Left PCB
#1	#60

Ver.1.2	13 /41