Global LCD Panel Exchange Center |
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LC320EXJ
Product Specification
SPECIFICATION
FOR
APPROVAL
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Preliminary Specification |
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Final Specification |
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32.0” WXGA TFT LCD |
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BUYER |
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Quatius |
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SUPPLIER |
LG Display Co., Ltd. |
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*MODEL |
LC320EXJ |
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MODEL |
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SUFFIX |
SEE1 (RoHS Verified) |
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*When you obtain standard approval, |
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please use the above model name without suffix |
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APPROVED BY
SIGNATURE
DATE
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Please return 1 copy for your confirmation with your signature and comments.
APPROVED BY |
SIGNATURE |
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DATE |
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J.T. Kim / Team Leader
REVIEWED BY
S.Y. Lee / Project Leader
PREPARED BY
Q-H. Jo / Engineer
TV Product Development Dept.
LG Display Co., Ltd.
Ver. 1.0 |
1 /34 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
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LC320EXJ
Product Specification
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CONTENTS |
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Number |
ITEM |
Page |
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COVER |
1 |
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CONTENTS |
2 |
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RECORD OF REVISIONS |
3 |
1 |
GENERAL DESCRIPTION |
4 |
2 |
ABSOLUTE MAXIMUM RATINGS |
5 |
3 |
ELECTRICAL SPECIFICATIONS |
6 |
3-1 |
ELECTRICAL CHARACTERISTICS |
6 |
3-2 |
INTERFACE CONNECTIONS |
7 |
3-3 |
SIGNAL TIMING SPECIFICATIONS |
8 |
3-4 |
SIGNAL TIMING WAVEFORMS |
9 |
3-5 |
COLOR DATA REFERENCE |
12 |
3-6 |
POWER SEQUENCE |
13 |
4 |
OPTICAL SPECIFICATIONS |
14 |
5 |
MECHANICAL CHARACTERISTICS |
17 |
6 |
MECHANICAL DIMENSION |
18 |
6-1 |
BOARD ASSEMBLY DIMENSION |
18 |
6-2 |
CONTROL BOARD ASSEMBLY DIMENSION |
19 |
7 |
RELIABILITY |
20 |
8 |
INTERNATIONAL STANDARDS |
21 |
8-1 |
ENVIRONMENT |
21 |
9 |
PACKING |
22 |
9-1 |
PACKING FORM |
22 |
10 |
PRECAUTIONS |
23 |
10-1 |
ASSEMBLY PRECAUTIONS |
23 |
10-2 |
OPERATING PRECAUTIONS |
23 |
10-3 |
ELECTROSTATIC DISCHARGE CONTROL |
24 |
10-4 |
PRECAUTIONS FOR STRONG LIGHT EXPOSURE |
24 |
10-5 |
STORAGE |
24 |
10-6 |
OPERATING CONDITION GUIDE |
24 |
Ver. 1.0 |
|
2 /34 |
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LC320EXJ
Product Specification
RECORD OF REVISIONS
Revision No. |
Revision Date |
Page |
Description |
0.0 |
Apr. 30, 2012 |
- |
Preliminary Specification (First Draft) |
Ver. 1.0 |
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3 /34 |
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LC320EXJ
Product Specification
1. General Description
The LC320EXJ is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate
implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as |
the active element. |
It is a transmissive type display operating in the normally black mode. It has a 31.5 inch |
diagonally measured |
active display area with WXGA resolution (768 vertical by 1366 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot. Therefore, it can present a palette of more than 16.7M(6bit + A-FRC) colors. 
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important. 
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EEPROM |
RGB |
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Source Driver Circuit |
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SCL |
SDA |
S1366 |
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S1 |
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LVDS Select #9 |
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G1 |
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LVDS 1Port |
CN1 |
Timing Controller |
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(30pin) |
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[LVDS Rx] |
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Control |
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+12.0V |
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Signals |
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G768 |
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Power Circuit |
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Block |
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Power Signals |
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General Features
Active Screen Size |
31.5 inches(800.4mm) diagonal |
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Outline Dimension |
715.0mm(H) x 411.0mm(V) x 1.4mm(D) (Typ.) |
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Pixel Pitch |
0.51075 |
X 0.51075 |
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Pixel Format |
1366 horiz. by 768 vert. pixels RGB stripe arrangement |
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Color Depth |
8bit(D), |
16,7 M colors |
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Drive IC Data Interface |
Source D-IC : 6-bit mini-LVDS, gamma reference voltage, and control signals |
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Gate D-IC : Gate In Panel |
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Transmittance (With POL) |
5.62 %(Typ.) |
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Viewing Angle (CR>10) |
Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.)) |
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Weight |
1.10Kg (Typ.) |
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Display Mode |
Transmissive mode, Normally black |
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Surface Treatment (Top) |
Hard coating(3H), Anti-glare treatment (Haze 1%) |
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Ver. 1.0 |
4 /34 |
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LC320EXJ
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter |
Symbol |
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Value |
Unit |
Remark |
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Min |
Max |
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Power Input voltage |
VLCD |
-0.3 |
+14.0 |
V [DC] |
X |
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Panel Front Temperature |
TSUR |
- |
+68 |
¶C |
4 |
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Operating Temperature |
TOP |
0 |
+50 |
¶C |
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Storage Temperature |
TST |
-20 |
+60 |
¶C |
2,3 |
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Operating Ambient Humidity |
HOP |
10 |
90 |
%RH |
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Storage Humidity |
HST |
10 |
90 |
%RH |
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Note: 1. |
Ambient temperature condition (Ta = 25 2 ¶C ) |
2. |
Temperature and relative humidity range are shown in the figure below. Wet bulb temperature |
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should be Max 39 ¶C and no condensation of water. |
3. |
Gravity mura can be guaranteed below 40 condition. |
4. |
The maximum operating temperature is based on the test condition that the surface temperature |
of display area is less than or equal to 68
with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area
from being over 68 . The range of operating temperature may degrade in case of improper thermal management in final product design.
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90% |
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60 |
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60% |
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Wet Bulb |
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40 |
50 |
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[(%)RH] |
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Temperature [¶C] |
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Humidity |
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40% |
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30 |
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20 |
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10 |
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10% |
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-20 |
0 |
10 |
20 |
30 |
40 |
50 |
60 |
70 |
80 |
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Dry Bulb Temperature [¶C] |
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Storage
Operation
Ver. 1.0 |
5 /34 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
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LC320EXJ
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit.
Table 2. ELECTRICAL CHARACTERISTICS |
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Parameter |
Symbol |
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Value |
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Unit |
Note |
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Min |
Typ |
Max |
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Circuit : |
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Power Input Voltage |
VLCD |
10.8 |
12.0 |
13.2 |
VDC |
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Power Input Current |
ILCD |
- |
340 |
445 |
mA |
1 |
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430 |
560 |
mA |
2 |
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Power Consumption |
PLCD |
- |
4.08 |
5.30 |
Watt |
1 |
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Rush current |
IRUSH |
- |
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3.0 |
A |
3 |
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Notes : 1. The specified current and power consumption are under the VLCD=12.0V, 25 2¶C, fV=60Hz condition whereas mosaic pattern(8 x 6) is displayed and fV is the frame frequency.
2.The current is specified at the maximum current
pattern.
3.The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4.Ripple voltage level is recommended under ·5% of typical voltage.
White : 255Gray
Black : 0Gray
Mosaic Pattern(8 x 6)
Ver. 1.0 |
6 /34 |
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LC320EXJ
Product Specification
3-2. Interface Connections
3-2-1. LCD Module
-LCD Connector(CN1) : KDF71G-30S-1H(Hirose) or FI-X30SSL-HF(JAE)
-Mating Connector : : FI-X30C2L (Manufactured by JAE) or Equivalente
Table 3. MODULE CONNECTOR(CN5) PIN CONFIGURATION
Pin No. |
Symbol |
Description |
Note |
1 |
VLCD |
Power Supply +12.0V |
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2 |
VLCD |
Power Supply +12.0V |
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3 |
VLCD |
Power Supply +12.0V |
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4 |
VLCD |
Power Supply +12.0V |
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5 |
GND |
Ground |
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6 |
GND |
Ground |
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7 |
GND |
Ground |
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8 |
GND |
Ground |
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9 |
LVDS Select |
H =JEIDA , L or NC = VESA |
Appendix IV |
10 |
uj |
No Connection |
4 |
11 |
GND |
Ground |
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12 |
RA- |
LVDS Receiver Signal(-) |
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RA+ |
LVDS Receiver Signal(+) |
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14 |
GND |
Ground |
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15 |
RB- |
LVDS Receiver Signal(-) |
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16 |
RB+ |
LVDS Receiver Signal(+) |
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17 |
GND |
Ground |
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18 |
RC- |
LVDS Receiver Signal(-) |
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19 |
RC+ |
LVDS Receiver Signal(+) |
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20 |
GND |
Ground |
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21 |
RCLK- |
LVDS Receiver Clock Signal(-) |
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22 |
RCLK+ |
LVDS Receiver Clock Signal(+) |
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23 |
GND |
Ground |
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24 |
RD- |
LVDS Receiver Signal(-) |
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25 |
RD+ |
LVDS Receiver Signal(+) |
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26 |
GND |
Ground |
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27 |
uj |
No Connection |
4 |
28 |
uj |
No Connection |
4 |
29 |
uj |
No Connection |
4 |
30 |
GND |
Ground |
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Notes : 1. All GND (Ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard. 
4. These pins are used only for LGD (Do not connect)
5.Specific pin No. #30 is used for “No signal detection” of system signal interface.
It should be GND for NSB (No Signal Black) while the system interface signal is not. If this pin is “H”, LCD Module displays AGP (Auto Generation Pattern).
Ver. 1.0 |
7 /34 |
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LC320EXJ
Product Specification
3-3. Signal Timing Specifications
Table 4 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timings should be satisfied with the following specification for normal operation.
{ G[UGG{ptpunG{hislGOklGv Gt P |
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ITEM |
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Min |
Typ |
Max |
Unit |
Note |
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Display |
tHV |
- |
1366 |
- |
tclk |
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Period |
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Horizontal |
Blank |
tHB |
90 |
162 |
410 |
tclk |
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Total |
tHP |
1456 |
1528 |
1776 |
tclk |
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Display |
tVV |
- |
768 |
- |
tHP |
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Period |
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Vertical |
Blank |
tVB |
20 |
22 |
240 |
tHP |
1 |
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(180) |
(295) |
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Total |
tVP |
788 |
790 |
1008 |
tHP |
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(894) |
(948) |
(1063) |
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Min |
Typ |
Max |
Unit |
Note |
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DCLK |
fCLK |
63.0 |
72.4 |
80.0 |
MHz |
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Horizontal |
fH |
45 |
47.4 |
55 |
KHz |
2 |
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Frequency |
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60 |
63 |
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Vertical |
fV |
Hz |
NTSC : |
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(47) |
(50) |
(53) |
57~63Hz |
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(PAL : 47~53Hz) |
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Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode). If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical 
refresh rate and the horizontal frequency
Timing should be set based on clock frequency.
Ver. 1.0 |
8 /34 |
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LC320EXJ
Product Specification
3-4. Signal Timing Waveforms
3-4-1. LVDS Input Signal Timing Diagram
0.7VDD
DE, Data
0.3VDD
DCLK |
tCLK |
0.5 Vcc |
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1366 |
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Invalid data |
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1 |
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1366 |
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Invalid data |
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DE(Data Enable) |
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tHV |
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tHT |
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DE(Data Enable) |
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768 |
1 |
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768 |
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tVV
tVT
Ver. 1.0 |
9 /34 |
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LC320EXJ
Product Specification
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS |
- |
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LVDS |
+ |
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V CM |
V IN _ MAX V IN _ MIN |
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# V CM = {(LVDS |
+) + ( LVDS - )}/2 |
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0V |
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Description |
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Symbol |
Min |
Max |
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Unit |
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Note |
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LVDS Common mode Voltage |
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VCM |
1.0 |
1.5 |
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V |
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- |
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LVDS Input Voltage Range |
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VIN |
0.7 |
1.8 |
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V |
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- |
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Change in common mode Voltage |
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VCM |
- |
250 |
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mV |
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- |
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2) AC Specification
Tclk
LVDS Clock
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A |
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LVDS Data |
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(Fclk = 1/Tclk ) |
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A |
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Tclk |
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LVDS 1’st Clock |
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80% |
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LVDS 2nd / 3rd / 4th Clock |
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20% |
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tSKEW_min tSKEW_max |
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tRF |
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Description |
|
Symbol |
Min |
Max |
Unit |
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|
Note |
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LVDS Differential Voltage |
High Threshold |
|
VTH |
100 |
300 |
mV |
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3 |
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Low Threshold |
|
VTL |
-300 |
-100 |
mV |
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LVDS Clock to Data Skew |
|
tSKEW |
- |
|(0.20*Tclk)/7| |
ps |
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- |
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LVDS Clock/DATA Rising/Falling time |
|
tRF |
260 |
|(0.3*Tclk)/7| |
ps |
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2 |
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Effective time of LVDS |
|
teff |
|·360| |
- |
ps |
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- |
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LVDS Clock to Clock Skew (Even to Odd) |
|
tSKEW_EO |
- |
|1/7* Tclk| |
ps |
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- |
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Note 1. All Input levels of LVDS signals are based on the EIA 644 Standard.
2.If tRF isn’t enough, teff should be meet the range.
3.LVDS Differential Voltage is defined within teff
Ver. 1.0 |
10 /34 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center |
www.panelook.com |
LC320EXJ
Product Specification
|
360ps |
|
0.5tui |
tui |
|
V+ |
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data |
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VTH |
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Vcm |
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VTL |
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V- |
360ps |
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data |
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teff |
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V+ |
tui : Unit Interval |
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clk |
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Vcm |
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V- |
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clk |
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Ver. 1.0 |
11 /34 |
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
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