LC550EUG
Product Specification
SPECIFICATION
FOR
APPROVAL
() Preliminary Specification
( ●) Final Specification
Title |
55.0” WUXGA TFT LCD |
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BUYER |
LGE |
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MODEL |
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SUPPLIER |
LG Display Co., Ltd. |
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*MODEL |
LC550EUG |
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SUFFIX |
PFF1 (RoHS Verified) |
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APPROVED BY
SIGNATURE
DATE
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Please return 1 copy for your confirmation with your signature and comments.
Ver. 1.0 |
1 /37 |
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LC550EUG |
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Product Specification |
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CONTENTS |
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Number |
ITEM |
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COVER |
1 |
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CONTENTS |
2 |
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RECORD OF REVISIONS |
3 |
1 |
GENERAL DESCRIPTION |
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2 |
ABSOLUTE MAXIMUM RATINGS |
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ELECTRICAL SPECIFICATIONS |
6 |
3-1 |
ELECTRICAL CHARACTERISTICS |
6 |
3-2 |
INTERFACE CONNECTIONS |
9 |
3-3 |
SIGNAL TIMING SPECIFICATIONS |
12 |
3-4 |
PANEL PIXEL STRUCTURE |
13 |
3-5 |
POWER SEQUENCE |
14 |
4 |
OPTICAL SPECIFICATIONS |
15 |
5 |
MECHANICAL CHARACTERISTICS |
21 |
6 |
RELIABILITY |
24 |
7 |
INTERNATIONAL STANDARDS |
25 |
7-1 |
SAFETY |
25 |
7-2 |
EMC |
25 |
7-3 |
Environment |
25 |
8 |
PACKING |
26 |
8-1 |
DESIGNATION OF LOT MARK |
26 |
8-2 |
PACKING FORM |
26 |
9 |
PRECAUTIONS |
27 |
9-1 |
MOUNTING PRECAUTIONS |
27 |
9-2 |
OPERATING PRECAUTIONS |
28 |
9-3 |
ELECTROSTATIC DISCHARGE CONTROL |
28 |
9-4 |
PRECAUTIONS FOR STRONG LIGHT EXPOSURE |
28 |
9-5 |
STORAGE |
28 |
9-6 |
OPERAGING CONDITION GUIDE |
28 |
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Ver. 1.0 |
2 /37 |
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LC550EUG
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Product Specification |
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RECORD OF REVISIONS |
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Revision No. |
Revision Date |
Page |
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Description |
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0.0 |
AUG, 15, 2012 |
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Preliminary Specification (First Draft) |
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0.1 |
Oct. 29. 2012 |
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Updated TBD Spec. |
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22,23 |
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Updated LCM mechanical drawing. |
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0.2 |
Nov. 27. 2012 |
15 |
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Updated Color Coordinates |
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32 |
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Updated LED Spec. |
1.0 |
Dec, 13, 2012 |
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Final Draft. |
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Ver. 1.0 |
3 /37 |
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LC550EUG
Product Specification
1. General Description
The LC550EUG is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive display type which is operating in the normally black mode. It has a 54.64 inch diagonally measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot. Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important.
Power (VCC, VDD, HVDD, VGH, VGL) |
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Source Driver Circuit |
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Gate Control Signal |
CN1 |
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S1 |
S1920 |
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Gamma Reference Voltage |
(50pin) |
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EPI (RGB & Control signal) for Left drive |
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G1 |
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Power (VCC, VDD, HVDD, VGH, VGL) |
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TFT - LCD Panel |
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Gate Control Signal |
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(1920 × RGB × 1080 pixels) |
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Gamma Reference Voltage |
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CN2 |
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[Gate In Panel] |
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(50pin) |
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EPI (RGB & Control Signal) for Right drive |
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G1080 |
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LED Anode |
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CN201 (8Pin) |
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LED Cathode |
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CN202 (8pin) |
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Back light Assembly |
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General Features |
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Active Screen Size |
54.64 inches(1387.80mm) diagonal |
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Outline Dimension |
1229.4 X 706.3 X 9.9(B)/21.9(D) |
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Pixel Pitch |
0.630 mm x 0.630 mm |
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Pixel Format |
1920 |
horiz. by 1080 vert. Pixels, RGB stripe arrangement |
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Color Depth |
8-bit, |
16.7 M colors ( 1.06B colors @ 10 bit (D) System Output ) |
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Drive IC Data Interface |
Source D-IC : 8-bit |
EPI, gamma reference voltage, and control signals |
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Gate D-IC : Gate In Panel |
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Luminance, White |
400cd/m2 (Center 1point ,Typ.) |
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Viewing Angle (CR>10) |
Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.)) |
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Power Consumption |
Total 81.58 W (Typ.) (Logic= 7.28 W with T-CON |
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LED Backlight=74.3W ( IF_cathode=150 mA) |
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Weight |
15.0Kg (Typ.) |
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Display Mode |
Transmissive mode, Normally black |
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Surface Treatment |
Hard coating(2H), Anti-glare treatment of the front polarizer (Haze < 1%) |
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Ver. 1.0 |
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4 /37 |
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LC550EUG
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
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Value |
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Parameter |
Symbol |
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Unit |
Note |
Min |
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Max |
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Logic & EPI Power Voltage |
VCC |
-0.5 |
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+2.2 |
VDC |
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Gate High Voltage |
VGH |
+18.0 |
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+30.0 |
VDC |
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Gate Low Voltage |
VGL |
-8.0 |
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-4.0 |
VDC |
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Source D-IC Analog Voltage |
VDD |
-0.3 |
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+18.0 |
VDC |
1 |
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Gamma Ref. Voltage (Upper) |
VGMH |
½VDD-0.5 |
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VDD+0.5 |
VDC |
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Gamma Ref. Voltage (Low) |
VGML |
-0.3 |
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½ VDD+0.5 |
VDC |
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LED Input Voltage |
VF |
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+97.5 |
VDC |
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Panel Front Temperature |
TSUR |
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+68 |
°C |
4 |
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Operating Temperature |
TOP |
0 |
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+50 |
°C |
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Storage Temperature |
TST |
-20 |
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+60 |
°C |
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2,3 |
Operating Ambient Humidity |
HOP |
10 |
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90 |
%RH |
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Storage Humidity |
HST |
10 |
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90 |
%RH |
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Note 1. Ambient temperature condition (Ta = 25 ± 2 °C )
2.Temperature and relative humidity range are shown in the figure below. Wet bulb temperature should be Max 39°C, and no condensation of water.
3.Gravity mura can be guaranteed below 40°C condition.
4.The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 68 . The range of operating temperature may be degraded in case of improper thermal management in final product design.
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90% |
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60 |
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60% |
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50 |
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[(%)RH] |
Storage |
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Wet Bulb |
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Temperature [°C] |
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40 |
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Humidity |
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40% |
Operation |
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30 |
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20 |
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10 |
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0 |
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10% |
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-20 |
0 |
10 |
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30 |
40 |
50 |
60 |
70 |
80 |
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Dry Bulb Temperature [°C] |
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Ver. 1.0 |
5 /37 |
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LC550EUG
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
It requires several power inputs. The VCC is the basic power of LCD Driving power sequence, Which is used to logic power voltage of Source D-IC and GIP.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter |
Symbol |
Condition |
MIN |
TYP |
MAX |
Unit |
Note |
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Logic Power Voltage |
VCC |
- |
1.62 |
1.8 |
1.98 |
VDC |
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Logic High Level Input Voltage |
VIH |
- |
1.4 |
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VCC |
VDC |
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Logic Low Level Input Voltage |
VIL |
- |
0 |
- |
0.4 |
VDC |
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Source D-IC Analog Voltage |
VDD |
- |
15.8 |
16.0 |
16.2 |
VDC |
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Half Source D-IC Analog |
H_VDD |
- |
7.8 |
8.0 |
8.2 |
VDC |
6 |
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Voltage |
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Gamma Reference Voltage |
VGMH |
(GMA1 ~ GMA9) |
H_VDD+0.2V |
- |
VDD-0.2 |
VDC |
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VGML |
(GMA10 ~ GMA18) |
0.2 |
- |
H_VDD-0.2V |
VDC |
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Common Voltage |
Vcom |
Reverse |
6.75 |
7.05 |
7.35 |
V |
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EPI input common voltage |
VCM |
LVDS Type |
0.8 |
VCC/2 |
1.3 |
V |
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EPI input differential voltage |
Vdiff |
- |
150 |
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500 |
mV |
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EPI Input eye diagram |
Veye |
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90 |
- |
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mV |
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@ 25 |
27.7 |
28 |
28.3 |
VDC |
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Gate High Voltage |
VGH |
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@ 0 |
29.7 |
30 |
30.3 |
VDC |
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Gate Low Voltage |
VGL |
- |
-6.8 |
-7 |
-7.2 |
VDC |
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GIP Bi-Scan Voltage |
VGI_P |
- |
VGL |
- |
- |
VDC |
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VGI_N |
- |
- |
- |
VGH |
VDC |
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GIP Refresh Voltage |
VGH |
- |
VGL |
- |
VGH |
V |
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even/odd |
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GIP Start Pulse Voltage |
VST |
- |
VGL |
- |
VGH |
V |
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GIP Operating Clock |
GCLK |
- |
VGL |
- |
VGH |
V |
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Total Power Current |
ILCD |
- |
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607 |
758 |
mA |
1 |
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Total Power Consumption |
PLCD |
- |
- |
7.28 |
9.1 |
Watt |
1 |
Note: 1. The specified current and power consumption are under the VLCD=12V., 25 ± 2°C, fV=60Hz condition whereas mosaic pattern(8 x 6) is displayed and fV is the frame frequency.
2.The above spec is based on the basic model.
3.All of the typical gate voltage should be controlled within 1% voltage level
4.Ripple voltage level is recommended under ±5% of typical voltage
5.In case of EPI signal spec, refer to Fig 2 for the more detail.
6.HVDD Voltage level is half of VDD and it should be between Gamma9 and Gamma10.
Ver. 1.0 |
6 /37 |
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LC550EUG
Product Specification
VGH
VGHM
GND
VGL
Without GPM |
With GPM |
FIG. 1 Gate Output Wave form without GPM and with GPM
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EPI + |
Vdiff |
Vdiff |
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0 V |
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Vdiff |
EPI - |
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Vcm |
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0 V |
(Differential Probe) |
(Active Probe) |
FIG. 2-1 EPI Differential signal characteristics
1 UI
0.5 UI
Veye
0 V
Veye
B1 B2
(Differential Probe)
FIG. 2-2 Eye Pattern of EPI Input
*Source PCB
FIG. 3 Measure point
Ver. 1.0 |
7 /37 |
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LC550EUG |
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Product Specification |
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Table 3. ELECTRICAL CHARACTERISTICS (Continue) |
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Parameter |
Symbol |
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Values |
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Unit |
Note |
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Min |
Typ |
Max |
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Backlight Assembly : |
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Forward Current |
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Anode |
IF (anode) |
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450 |
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mAdc |
±5% |
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(one array) |
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Cathode |
IF (cathode) |
142.5 |
150 |
157.5 |
mAdc |
2, 3 |
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Forward Voltage |
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VF |
75.0 |
82.5 |
87.5 |
Vdc |
4 |
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Forward Voltage Variation |
VF |
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1.7 |
Vdc |
5 |
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Power Consumption |
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PBL |
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74.3 |
78.8 |
W |
6 |
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Burst Dimming Duty |
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On duty |
1 |
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100 |
% |
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Burst Dimming Frequency |
1/T |
95 |
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182 |
Hz |
8 |
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LED Array : |
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Life Time |
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30,000 |
50,000 |
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Hrs |
7 |
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Note :The design of the LED driver must have specifications for the LED array in LCD Assembly. The electrical characteristics of LED driver are based on Constant Current driving type.
The performance of the LED in LCM, for example life time or brightness, is extremely influenced by the characteristics of the LED Driver. So, all the parameters of an LED driver should be carefully designed. When you design or order the LED driver, please make sure unwanted lighting caused by the mismatch of the LED and the driver (no lighting, flicker, etc) has never been occurred. When you confirm it, the LCD– Assembly should be operated in the same condition as installed in your instrument.
1.Electrical characteristics are based on LED Array specification.
2.Specified values are defined for a Backlight Assembly. (IBL : 2 LED array/LCM) 3.Each LED array has one anode terminal and 3 cathode terminals.
The forward current(IF) of the anode terminal is 450mA and it supplies 150mA into 3 strings, respectively
1string(25 LED PKG)
450mA |
° ° ° |
Cathode #1 |
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Anode#1 |
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150mA |
1 Array (3 Strings) |
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° ° ° |
Cathode #2 |
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150mA |
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° ° ° |
Cathode #3 |
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150mA |
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4.The forward voltage(VF) of LED array depends on ambient temperature (Appendix-V)
5.VF means Max VF-Min VF in one Backlight. So VF variation in a Backlight isn’t over Max. 1.7V
6.Maximum level of power consumption is measured at initial turn on.
Typical level of power consumption is measured after 1hrs aging at 25 ± 2°C.
7.The life time(MTTF) is determined as the time at which brightness of the LED is 50% compared to that of initial value at the typical LED current on condition of continuous operating at 25 ± 2°C, based on duty 100%.
8.The reference method of burst dimming duty ratio.
It is recommended to use synchronous V-sync frequency to prevent waterfall
(Vsync x 2 =Burst Frequency)
Though PWM frequency is over 182Hz (max252Hz), function of backlight is not affected.
Ver. 1.0 |
8 /37 |
|
|
LC550EUG
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, two 50-pin FFC connector are used for the module electronics and 8-pin / 8-pin connectors are used for the integral backlight system.
3-2-1. LCD Module
-LCD Connector (CN1): TF06L-50S-0.5SH (Manufactured by HRS) or Compatible
Table 3-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION
No |
Symbol |
Description |
|
No |
Symbol |
Description |
|
|
|
|
|
|
|
1 |
LTD_OUT |
LTD OUTPUT |
|
26 |
GND |
Ground |
|
|
|
|
|
|
|
2 |
NC |
No Connection |
|
27 |
EPI2- |
EPI Receiver Signal(2-) |
|
|
|
|
|
|
|
3 |
GCLK1 |
GIP GATE Clock 1 |
|
28 |
EPI2+ |
EPI Receiver Signal(2+) |
|
|
|
|
|
|
|
4 |
GCLK2 |
GIP GATE Clock 2 |
|
29 |
GND |
Ground |
|
|
|
|
|
|
|
5 |
GCLK3 |
GIP GATE Clock 3 |
|
30 |
GND |
Ground |
|
|
|
|
|
|
|
6 |
GCLK4 |
GIP GATE Clock 4 |
|
31 |
EPI1- |
EPI Receiver Signal(1-) |
|
|
|
|
|
|
|
7 |
GCLK5 |
GIP GATE Clock 5 |
|
32 |
EPI1+ |
EPI Receiver Signal(1+) |
|
|
|
|
|
|
|
8 |
GCLK6 |
GIP GATE Clock 6 |
|
33 |
GND |
Ground |
|
|
|
|
|
|
|
9 |
VGI_N |
GIP Bi-Scan (VGI_N = VGH) |
|
34 |
VCC |
Logic & EPI Power Voltage |
|
|
|
|
|
|
|
10 |
VGI_P |
GIP Bi-Scan (VGI_P = VGL) |
|
35 |
Vterm |
Vterm Power Voltage |
|
|
|
|
|
|
|
11 |
VGH_ODD |
GIP Panel VDD for Odd GATE TFT |
|
36 |
LOCKOUT3 |
LOCKOUT3 |
|
|
|
|
|
|
|
12 |
VGH_EVEN |
GIP Panel VDD for Even GATE TFT |
|
37 |
NC |
No Connection |
|
|
|
|
|
|
|
13 |
VGL |
GATE Low Voltage |
|
38 |
GND |
Ground |
|
|
|
|
|
|
|
14 |
VST |
VERTICAL START PULSE |
|
39 |
GMA 18 |
GAMMA VOLTAGE 18 (Output From LCD) |
|
|
|
|
|
|
|
15 |
GIP_Reset |
GIP Reset |
|
40 |
GMA 16 |
GAMMA VOLTAGE 16 |
|
|
|
|
|
|
|
16 |
VCOM_L_FB |
VCOM Left Feed-Back Output |
|
41 |
GMA 15 |
GAMMA VOLTAGE 15 |
|
|
|
|
|
|
|
17 |
VCOM_L |
VCOM Left Input |
|
42 |
GMA 14 |
GAMMA VOLTAGE 14 |
|
|
|
|
|
|
|
18 |
GND |
Ground |
|
43 |
GMA 12 |
GAMMA VOLTAGE 12 |
|
|
|
|
|
|
|
19 |
VDD |
Driver Power Supply Voltage |
|
44 |
GMA 10 |
GAMMA VOLTAGE 10 (Output From LCD) |
|
|
|
|
|
|
|
20 |
VDD |
Driver Power Supply Voltage |
|
45 |
GMA 9 |
GAMMA VOLTAGE 9 (Output From LCD) |
|
|
|
|
|
|
|
21 |
H_VDD |
Half Driver Power Supply Voltage |
|
46 |
GMA 7 |
GAMMA VOLTAGE 7 |
|
|
|
|
|
|
|
22 |
GND |
Ground |
|
47 |
GMA 5 |
GAMMA VOLTAGE 5 |
|
|
|
|
|
|
|
23 |
EPI3- |
EPI Receiver Signal(3-) |
|
48 |
GMA 4 |
GAMMA VOLTAGE 4 |
|
|
|
|
|
|
|
24 |
EPI3+ |
EPI Receiver Signal(3+) |
|
49 |
GMA 3 |
GAMMA VOLTAGE 3 |
|
|
|
|
|
|
|
25 |
GND |
Ground |
|
50 |
GMA 1 |
GAMMA VOLTAGE 1(Output From LCD) |
|
|
|
|
|
|
|
Note :
1. Please refer to application note for details. (GIP & Half VDD & Gamma Voltage setting)
Ver. 1.0 |
9 /37 |
|
|
LC550EUG
Product Specification
-LCD Connector (CN1): TF06L-50S-0.5SH (Manufactured by HRS) or Compatible
Table 3-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
|
|
No |
Symbol |
|
Description |
|
|
|
|
|
|
|
No |
|
|
Symbol |
|
|
|
Description |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
|
1 |
GMA 1 |
GAMMA VOLTAGE 1 (Output From LCD) |
|
|
26 |
|
|
|
|
GND |
Ground |
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
2 |
GMA 3 |
GAMMA VOLTAGE 3 |
|
|
|
|
|
|
|
27 |
|
|
|
|
EPI1- |
EPI Receiver Signal(4-) |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
3 |
GMA 4 |
GAMMA VOLTAGE 4 |
|
|
|
|
|
|
|
28 |
|
|
|
|
EPI1+ |
EPI Receiver Signal(4+) |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
4 |
GMA 5 |
GAMMA VOLTAGE 5 |
|
|
|
|
|
|
|
29 |
|
|
|
|
GND |
Ground |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
5 |
GMA 7 |
GAMMA VOLTAGE 7 |
|
|
|
|
|
|
|
30 |
|
|
|
|
H_VDD |
Half Driver Power Supply Voltage |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
|
6 |
GMA 9 |
GAMMA VOLTAGE 9 (Output From LCD) |
|
|
31 |
|
|
|
|
VDD |
Driver Power Supply Voltage |
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
|
7 |
GMA 10 |
GAMMA VOLTAGE 10 (Output From LCD) |
|
|
32 |
|
|
|
|
VDD |
Driver Power Supply Voltage |
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
8 |
GMA 12 |
GAMMA VOLTAGE 12 |
|
|
|
|
|
|
|
33 |
|
|
|
|
GND |
Ground |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
9 |
GMA 14 |
GAMMA VOLTAGE 14 |
|
|
|
|
|
|
|
34 |
|
|
|
VCOM_R |
VCOM Right Input |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
10 |
GMA 15 |
GAMMA VOLTAGE 15 |
|
|
|
|
|
|
|
35 |
|
|
VCOM_R_FB |
VCOM Right Feed-Back Output |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
11 |
GMA 16 |
GAMMA VOLTAGE 16 |
|
|
|
|
|
|
|
36 |
|
|
|
GIP_Reset |
GIP Reset |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
|
12 |
GMA 18 |
GAMMA VOLTAGE 18 (Output From LCD) |
|
|
37 |
|
|
|
|
VST |
VERTICAL START PULSE |
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
13 |
GND |
Ground |
|
|
|
|
|
|
|
38 |
|
|
|
|
VGL |
GATE Low Voltage |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
14 |
LOCKOUT6 |
LOCKOUT6 |
|
|
|
|
|
|
|
39 |
|
|
VGH_EVEN |
GIP Panel VDD for Even GATE TFT |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
15 |
LOCKIN3 |
LOCKIN3 |
|
|
|
|
|
|
|
40 |
|
|
|
VGH_ODD |
GIP Panel VDD for Odd GATE TFT |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
16 |
Vterm |
Vterm Power Voltage |
|
|
|
|
|
|
|
41 |
|
|
|
|
VGI_P |
GIP Bi-Scan (VGI_P = VGL) |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
17 |
VCC |
Logic & EPI Power Voltage |
|
|
|
|
|
|
|
42 |
|
|
|
|
VGI_N |
GIP Bi-Scan (VGI_N = VGH) |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
18 |
GND |
Ground |
|
|
|
|
|
|
|
43 |
|
|
|
|
GCLK6 |
GIP GATE Clock 6 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
19 |
EPI6- |
EPI Receiver Signal(6-) |
|
|
|
|
|
|
|
44 |
|
|
|
|
GCLK5 |
GIP GATE Clock 5 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
20 |
EPI6+ |
EPI Receiver Signal(6+) |
|
|
|
|
|
|
|
45 |
|
|
|
|
GCLK4 |
GIP GATE Clock 4 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
21 |
GND |
Ground |
|
|
|
|
|
|
|
46 |
|
|
|
|
GCLK3 |
GIP GATE Clock 3 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
22 |
GND |
Ground |
|
|
|
|
|
|
|
47 |
|
|
|
|
GCLK2 |
GIP GATE Clock 2 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
23 |
EPI5- |
EPI Receiver Signal(5-) |
|
|
|
|
|
|
|
48 |
|
|
|
|
GCLK1 |
GIP GATE Clock 1 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
24 |
EPI5+ |
EPI Receiver Signal(5+) |
|
|
|
|
|
|
|
49 |
|
|
|
|
NC |
No Connection |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
25 |
GND |
Ground |
|
|
|
|
|
|
|
50 |
|
|
|
LTD_OUT |
LTD OUTPUT |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
Note : 1. Please refer to application note for details. |
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
|
|
|
(GIP & Half VDD & Gamma Voltage setting) |
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CN 2 |
|
|
|
|
|
|
|
|
|
|
|
|
CN 1 |
|
|
|
|
|
|
|
|
Source Right PCB |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Source Left PCB |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
#1 #14 #15 |
#50 |
|
|
|
|
|
|
|
#1 |
|
#36 #50 |
|
|||||||||||||
|
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|
|||||||||
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|
|
LOCK6 LTD OUTPUT
|
|
|
System (or Control) PCB |
To SOC ( or T-Con) |
LOCK3 |
||
|
|
||
Ver. 1.0 |
10 /37 |
|
|
LC550EUG
Product Specification
3-2-2. Backlight Module |
|
[ CN201 ] |
[ CN202 ] |
|
1)LED Array assy Connector (Plug)
:HS100-L08N-N62 (black color, manufactured by UJU)
2)Mating Connector (Receptacle)
:IS100-L08T-C46 (black color, manufactured by UJU)
1)LED Array assy Connector (Plug)
:HS100-L08N-N62-A (natural color, manufactured by UJU) 2) Mating Connector (Receptacle)
: IS100-L08T-C46-A (natural color, manufactured by UJU)
Table 4. BACKLIGHT CONNECTOR PIN CONFIGURATION(CN201,CN202)
No |
Symbol(CN201) |
Description |
Note |
1 |
L1 Cathode |
LED Output Current |
|
2 |
L2 Cathode |
LED Output Current |
|
3 |
L3 Cathode |
LED Output Current |
|
4 |
N.C |
Open |
|
5 |
N.C |
Open |
|
6 |
N.C |
Open |
|
7 |
N.C |
Open |
|
8 |
Anode_L |
LED Input Current for |
|
L1~L3 |
|
||
|
|
|
No |
Symbol(CN202) |
Description |
Note |
1 |
Anode_R |
LED Input Current for |
|
R1~R3 |
|
||
|
|
|
|
2 |
N.C |
Open |
|
3 |
N.C |
Open |
|
4 |
N.C |
Open |
|
5 |
N.C |
Open |
|
6 |
R1 Cathode |
LED Output Current |
|
7 |
R2 Cathode |
LED Output Current |
|
8 |
R3 Cathode |
LED Output Current |
|
|
|
|
|
Rear view of LCM
Rear
87654321 87654321
CNT 201 |
CNT 202 |
Power Board
L
1
L
2
L
3
R
1
R
2
R
3
Ver. 1.0 |
11 /37 |
|
|
|
|
|
|
|
|
|
|
LC550EUG |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Product Specification |
|
|
|
|
|
|
|
|
3-3. Signal Timing Specifications |
|
|
|
|
|
|
|
|
|
|
Table 5. Timing Requirements |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Parameter |
Symbol |
Condition |
Min |
Typ |
Max |
Unit |
|
notes |
|
|
|
|
|
|
|
|
|
|
|
|
|
Unit Interval |
UI |
- |
1.37 |
1.44 |
1.70 |
ns |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Effective Veye width time |
B1&B2 |
- |
0.25 |
- |
- |
UI |
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Fig. 2 |
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Modulation Ratio of SSC |
Vspread |
@100KHz |
- |
- |
2 |
% |
|
1 |
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1st data to SOE rising time |
Ts1 |
- |
3 |
- |
- |
Packet |
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Fig.4 |
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SOE rising to last data |
Ts4 |
|
0 |
- |
- |
Packet |
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Fig.4 |
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Last data to SOE falling |
Ts5 |
- |
10 |
- |
- |
Packet |
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Fig.4 |
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EPI Bandwidth |
BW |
- |
0.588 |
- |
0.728 |
GBPS |
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notes :1. VModulation Ratio of SSC for 20KHz ~ 100kHz Modulation Frequency is calculated by (7 – 0.05*Fmod), where Fmod unit is KHz.
FIG 4. SOE Width & Timing
Ver. 1.0 |
12 /37 |
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