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FUJITSU SEMICONDUCTOR |
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DS07-13712-4E |
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DATA SHEET |
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16-Bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90470 Series
MB90473/474/477/478/F474L/F474H
■ DESCRIPTIONS
The FUJITSU MB90470 Series is a 16-bit general-purpose microcontroller designed for consumer products and other process control applications requiring high-speed and real-time processing.
The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for use with high-level languages, expanded addressing mode, enhanced multiply and divide instructions, and full bit processing. Also included is a built-in 32-bit accumulator for long-word processing.
Peripheral resources built into the MB90470 series include 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit input-output timer, 8/16-bit up-counter, PWC timer, I2C*2 interface, DTP/external interrupt, chip select, and 16-bit reload timer.
*1 : F2MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered trademark of FUJITSU, Ltd.
*2 : I2C license :
This product includes licensing of Philips I2C patents if used by the customer in an I2C system subject to the I2C standard specifications established by Philips.
■ PACKAGES
100-pin plastic QFP |
100-pin plastic LQFP |
(FPT-100P-M06) |
(FPT-100P-M05) |
MB90470 Series
■FEATURES
•Clocks
Minimum instruction execution time :
50.0ns at 5 MHz base oscillation with 4 × multiplier (internal operation at 20 MHz/3.3 V ± 0.3 V)
62.5ns at 4 MHz base oscillation with 4 × multiplier (internal operation at 16 MHz/3.0 V ± 0.3 V) Uses PLL clock multiplier.
•Maximum memory size
16Mbytes
•Instruction set optimized for control applications
Handles bit, byte, word, long-word data
23standard addressing modes
32-bit accumulator for enhanced high-precision calculation Signed multiply-divide and expanded RETI instructions
•Instruction system compatible with high-level language (C) multitasking
System stack pointer
Instruction set correlation and barrel shift instructions
•Non-multi bus or multi-bus compatible
•Program patch function (for two address pointers)
•Improved execution speed
4-byte queue
•Powerful interrupt functions
8external interrupt functions with 8-level programmable priority
•Data transfer functions ( DMA or Extended intelligent I/O service)
16channels maximum
µDMA maximum assured operation frequency : 16 MHz
Extended intelligent I/O service maximum assured operation frequency : 20 MHz
•Built-in ROM
Flash versions : 256 KB, Mask ROM versions : 128 KB/256 KB
•Built-in RAM
10KB/16 KB
•General purpose ports
84ports maximum
(includes 16 ports with input pull-up resistance setting, 14 ports with output open drain setting)
•A/D converter
RC sequential comparator type, 8 channels
10-bit resolution, conversion time 4.65 µs (at 20 MHz operation)
•I2C interface
1channel
•PG
1channel
•UART
1channel
•I/O expansion serial interface (SIO)
2channels
•8/16-bit up/down timer
1channel
•16-bit PWC
3channels (including 2-channel input comparison function)
(Continued)
2
MB90470 Series
(Continued)
•16-bit reload timer
1 channel (8-bit × 2-channel, 16-bit × 1-channel mode switching function provided)
•16-bit input-output timer
2-channel input capture, 6-channel output compare, 1-channel free run timer
•2 built-in clock generator systems
•Low power modes
Stop, sleep, CPU intermittent mode, watch mode, etc.
•Package options
QFP100/LQFP100
•Process
CMOS technology
•Supply voltage
Can operate on 3 V single supply systems (with 5 V interface provided by some pins with 3/5 V dual-supply capability)
3
MB90470 Series
■ PRODUCT LINEUP
Parameter |
Part number |
MB90F474L |
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MB90F474H |
MB90473 |
MB90474 |
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ROM capacity |
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FLASH 256 KB |
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FLASH 256 KB |
MASKROM |
MASKROM |
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128 KB |
256 KB |
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RAM capacity |
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16 KB |
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16 KB |
10 KB |
16 KB |
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Basic instructions |
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: 351 |
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Instruction bit length |
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: 8-bit, 16-bit |
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CPU functions |
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Instruction length |
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: 1 byte to 7 bytes |
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Data bit length |
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: 1-bit, 8-bit, 16-bit |
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Minimum instruction execution time |
: 62.5 ns (with 16 MHz machine clock) |
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General purpose input/output ports : 84 Max
Ports
General purpose input/output ports (CMOS output)
General purpose input/output ports (built-in pull-up resistance)
General purpose input/output ports (N-ch open drain)
UART |
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Stop-start synchronized : 1 channel |
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8/16-bit PPG timer |
8-bit 6-channel/16-bit 3-channel |
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8/16-bit up-down counter/timer |
Two 8-bit up-down counters with 6 event input pins |
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Two 8-bit reload/compare registers |
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16-bit |
16-bit free-run timer |
Channel : 1 |
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Overflow interrupt |
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input/ |
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Output compare (OCU) |
Channels : 6 |
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out- |
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Pin input source : from compare register match signal |
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put |
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Channels : 2 |
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timers |
Input capture (ICU) |
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Register rewritten from pin input (rising/falling/both edges) |
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DTP/external interrupt circuit |
External interrupt pins : 8 channels (set to edge or level correlation) |
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I/O expansion serial interface |
2-channel, built-in |
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I2C interface |
1-channel, built-in |
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18-bit counter |
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Time base timer |
Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms |
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(minimum times, at base oscillator frequency 4 MHz) |
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Conversion accuracy : 8/10-bit switchable |
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Single conversion mode (converts selected channel 1 time only) |
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A/D converter |
Scan conversion mode |
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(converts multiple consecutive channels, programmable up to 8 channels) |
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Continuous conversion mode (converts selected channels continuously) |
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Stop conversion mode (converts selected channel, stops and repeats) |
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Watchdog timer |
Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms |
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(minimum times, at base oscillator frequency 4 MHz) |
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Low power (standby) modes |
Sleep, stop, CPU intermittent, watch mode |
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Process |
CMOS |
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Flash model, low |
Flash model, high |
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Notes |
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voltage version |
voltage version |
Mask version |
Mask version |
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(f = 10 MHz or |
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(f = 20 MHz) |
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less at VCC = 2.4 V) |
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Emulator dedicated power supply |
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(Continued)
4
MB90470 Series
(Continued)
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Part number |
MB90477 |
MB90478 |
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MB90V470B |
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Parameter |
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ROM capacity |
MASKROM |
MASKROM |
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256 KB |
256 KB |
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RAM capacity |
8 KB |
8 KB |
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16 KB |
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Basic instructions |
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: 351 |
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: 8-bit, 16-bit |
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Instruction bit length |
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: 1 byte to 7 bytes |
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CPU functions |
Instruction length |
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: 1-bit, 8-bit, 16-bit |
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Data bit length |
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: 50 ns (with 20 MHz |
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Minimum instruction execution time |
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machine clock) |
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General purpose input/output ports : 84 Max |
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Ports |
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General purpose input/output ports (CMOS output) |
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General purpose input/output ports (built-in pull-up resistance) |
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General purpose input/output ports (N-ch open drain) |
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UART |
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Stop-start synchronized : 1 channel |
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8/16-bit PPG timer |
8-bit 6-channel/16-bit 3-channel |
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8/16-bit up-down counter/timer |
Two 8-bit up-down counters with 6 event input pins |
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Two 8-bit reload/compare registers |
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16-bit free-run timer |
Channel : 1 |
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16-bit |
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Overflow interrupt |
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input/ |
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Output compare (OCU) |
Channels : 6 |
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output |
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Pin input source : from compare register match signal |
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timers |
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Input capture (ICU) |
Channels : 2 |
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Register rewritten from pin input (rising/falling/both edges) |
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DTP/external interrupt circuit |
External interrupt pins : 8 channels (set to edge or level correlation) |
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I/O expansion serial interface |
2-channel, built-in |
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I2C interface |
1-channel, built-in |
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18-bit counter |
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Time base timer |
Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms |
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(minimum times, at base oscillator frequency 4 MHz) |
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Conversion accuracy : 8/10-bit switchable |
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Single conversion mode (converts selected channel 1 time only) |
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A/D converter |
Scan conversion mode |
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(converts multiple consecutive channels, programmable up to 8 channels) |
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Continuous conversion mode (converts selected channels continuously) |
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Stop conversion mode (converts selected channel, stops and repeats) |
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Watchdog timer |
Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms |
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(minimum times, at base oscillator frequency 4 MHz) |
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Low power (standby) modes |
Sleep, stop, CPU intermittent, watch mode |
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Process |
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CMOS |
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Mask version without |
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EVA function |
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Notes |
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Mask version |
I2C |
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User pin |
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built-in interface |
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Emulator dedicated power supply |
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Included |
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5
MB90470 Series
■ PIN ASSIGNMENTS
(TOP VIEW)
P20/A16 
P21/A17 
P22/A18 
P23/A19 
P24/A20/PPG0 
P25/A21/PPG1 
P26/A22/PPG2 
P27/A23/PPG3 
P30/A00/AIN0 
P31/A01/BIN0 
VSS 
P32/A02/ZIN0 
P33/A03/AIN1 
P34/A04/BIN1 
P35/A05/ZIN1 
P36/A06/PWC0 
P37/A07/PWC1 
P40/A08/SIN2 
P41/A09/SOT2 
P42/A10/SCK2 
P43/A11/MT00 
P44/A12/MT01 
VCC5
P45/A13/EXTC 
P46/A14/OUT4 
P47/A15/OUT5 
P70/SIN0 
P71/SOT0 
P72/SCK0 
P73/TIN0 
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2
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21
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27
28
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30
100 P17/AD15/D15
P74/TOT0 31
P16/AD14/D14 |
P15/AD13/D13 |
P14/AD12/D12 |
P13/AD11/D11 |
P12/AD10/D10 |
P11/AD09/D09 |
P10/AD08/D08 |
P07/AD07/D07 |
P06/AD06/D06 |
P05/AD05/D05 |
P04/AD04/D04 |
P03/AD03/D03 |
P02/AD02/D02 |
P01/AD01/D01 |
P00/AD00/D00 |
VCC3 |
X1 X0 |
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98 |
97 |
96 |
95 |
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92 |
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90 |
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88 |
87 |
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84 |
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P75/PWC2 |
P76/SCL |
P77/SDA |
AVCC |
AVRH |
AVSS |
P60/AN0 |
P61/AN1 |
P62/AN2 |
P63/AN3 |
Vss |
P64/AN4 |
P65/AN5 |
P66/AN6 |
P67/AN7 |
P80/IRQ0 |
P81/IRQ1 |
MD0 |
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81 VSS
MD1 50
80 |
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X0A |
79 |
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X1A |
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78 |
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P57/CLK |
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77 |
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RST |
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76 |
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P56/RDY |
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75 |
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P55/HAK |
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74 |
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P54/HRQ |
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P53/WRH |
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P52/WRL |
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P51/RD |
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P50/ALE |
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PA3/OUT3 |
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PA2/OUT2 |
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PA1/OUT1 |
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PA0/OUT0 |
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P97/IN1 |
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P96/IN0 |
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P95/PPG5 |
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P94/PPG4 |
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P93/FRCK/ADTG/CS3 |
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P92/SCK1/CS2 |
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P91/SOT1/CS1 |
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58 |
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P90/SIN1/CS0 |
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57 |
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P87/IRQ7 |
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56 |
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P86/IRQ6 |
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55 |
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P85/IRQ5 |
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54 |
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P84/IRQ4 |
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53 |
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P83/IRQ3 |
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52 |
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P82/IRQ2 |
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51 |
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MD2 |
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(FPT-100P-M06)
6
MB90470 Series
(TOP VIEW)
P22/A18
P23/A19
P24/A20/PPG0
P25/A21/PPG1
P26/A22/PPG2
P27/A23/PPG3
P30/A00/AIN0
P31/A01/BIN0
VSS
P32/A02/ZIN0
P33/A03/AIN1
P34/A04/BIN1
P35/A05/ZIN1
P36/A06/PWC0
P37/A07/PWC1
P40/A08/SIN2
P41/A09/SOT2
P42/A10/SCK2
P43/A11/MT00
P44/A12/MT01 VCC5 P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5 P70/SIN0
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21
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P21/A17 |
P20/A16 |
P17/AD15/D15 |
P16/AD14/D13 |
P15/AD13/D13 |
P14/AD12/D12 |
P13/AD11/D11 |
P12/AD10/D10 |
P11/AD09/D09 |
P10/AD08/D08 |
P07/AD07/D07 |
P06/AD06/D06 |
P05/AD05/D05 |
P04/AD04/D04 |
P03/AD03/D03 |
P02/AD02/D02 |
P01/AD01/D01 |
P00/AD00/D00 |
VCC3 |
X1 |
X0 |
VSS |
X0A |
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100 |
99 |
98 |
97 |
96 |
95 |
94 |
93 |
92 |
91 |
90 |
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87 |
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P71/SOT0 |
P72/SCK0 |
P73/TIN0 |
P74/TOT0 |
P75/PWC2 |
P76/SCL |
P77/SDA |
AVCC |
AVRH |
AVSS |
P60/AN0 |
P61/AN1 |
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P62/AN2 |
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P63/AN3 |
VSS |
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P64/AN4 |
P65/AN5 |
P66/AN6 |
P67/AN7 |
P80/IRQ0 |
P81/IRQ1 |
MD0 |
MD1 |
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X1A |
P57/CLK |
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77 |
76 |
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49 |
50 |
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MD2 |
P82/IRQ2 |
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75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P56/RDY
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
PA3/OUT3
PA2/OUT2
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/PPG5
P94/PPG4
P93/FRCK/ADTG/CS3
P92/SCK1/CS2
P91/SOT1/CS1
P90/SIN1/CS0
P87/IRQ7
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
(FPT-100P-M05)
7
MB90470 Series
■ PIN DESCRIPTION
Pin no. |
Pin name |
Circuit |
Description |
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LQFP |
QFP |
type |
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80 |
82 |
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X0 |
A |
Oscillator pin |
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81 |
83 |
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X1 |
A |
Oscillator pin |
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78 |
80 |
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X0A |
A |
32 kHz oscillator pin |
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77 |
79 |
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X1A |
A |
32 kHz oscillator pin |
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75 |
77 |
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B |
Reset input pin |
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RST |
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General purpose input/output ports. Set the pull-up resistance |
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P00 to P07 |
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setting register (RDR0) to add pull-up resistance (RD00-RD07 |
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C |
= “1” ) . (Not valid when set for output) |
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83 to 90 |
85 to 92 |
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In multiplex mode, these pins function as external address/ |
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AD00 to AD07 |
(CMOS) |
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data bus lower input/output pins. |
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D00 to D07 |
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In non-multiplex mode, these pins function as external data |
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bus lower output pins. |
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General purpose input/output ports. Set the pull-up resistance |
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P10 to P17 |
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setting register (RDR1) to add pull-up resistance (RD10-RD17 |
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93 to |
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C |
= “1” ) . (Not valid when set for output) |
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91 to 98 |
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In multiplex mode, these pins function as external address/ |
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100 |
AD08 to AD15 |
(CMOS) |
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data bus higher input/output pins. |
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D08 to D15 |
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In non-multiplex mode, these pins function as external data |
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bus higher output pins. |
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General purpose input/output ports. In external bus mode, pins |
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P20 to P23 |
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for which the corresponding bit in the external address output |
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control register (HACR) is “1” function as the general purpose |
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99 |
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input/output ports. |
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100 |
1 to 4 |
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E |
In multiplex mode, pins for which the corresponding bit in the |
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1 |
A16 to A19 |
(CMOS/H) |
external address output control register (HACR) is “0” function |
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2 |
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as the upper address output pins (A16 to A19) . |
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In non-multiplex mode, pins for which the corresponding bit in |
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A16 to A19 |
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the external address output control register (HACR) is “0” |
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function as the upper address output pins (A16 to A19) . |
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General purpose input/output ports. In external bus mode, pins |
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P24 to P27 |
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for which the corresponding bit in the external address output |
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control register (HACR) is “1” function as the general purpose |
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input/output ports. |
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E |
In multiplex mode, pins for which the corresponding bit in the |
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3 to 6 |
5 to 8 |
A20 to A23 |
external address output control register (HACR) is “0” function |
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(CMOS/H) |
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as the upper address output pins (A20 to A23) . |
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In non-multiplex mode, pins for which the corresponding bit in |
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A20 to A23 |
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the external address output control register (HACR) is “0” |
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function as the upper address output pins (A20 to A23) . |
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PPG0 to PPG3 |
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PPG timer output pins. |
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(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
8
MB90470 Series
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Pin no. |
Pin name |
Circuit |
Description |
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LQFP |
QFP |
type |
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P30 |
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General purpose input/output port. |
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7 |
9 |
A00 |
E |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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AIN0 |
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8/16-bit up-down timer input pin. (ch0) |
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P31 |
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General purpose input/output port. |
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8 |
10 |
A01 |
E |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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BIN0 |
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8/16-bit up-down timer input pin. (ch0) |
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P32 |
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General purpose input/output port. |
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10 |
12 |
A02 |
E |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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ZIN0 |
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8/16-bit up-down timer input pin. (ch0) |
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P33 |
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General purpose input/output port. |
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11 |
13 |
A03 |
E |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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AIN1 |
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8/16-bit up-down timer input pin. (ch1) |
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P34 |
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General purpose input/output port. |
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12 |
14 |
A04 |
E |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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BIN1 |
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8/16-bit up-down timer input pin. (ch1) |
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P35 |
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General purpose input/output port. |
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13 |
15 |
A05 |
E |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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ZIN1 |
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8/16-bit up-down timer input pin. (ch1) |
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P36, P37 |
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General purpose input/output ports. |
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14 |
16 |
A06, A07 |
E |
In non-multibus bus mode, this pin functions as an external |
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15 |
17 |
(CMOS/H) |
address pin. |
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PWC0, PWC1 |
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Functions as PWC input pin. |
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P40 |
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General purpose input/output port. |
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16 |
18 |
A08 |
G |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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SIN2 |
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Single serial I/O input pin |
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P41 |
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General purpose input/output port. |
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17 |
19 |
A09 |
F |
In non-multibus bus mode, this pin functions as an external |
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(CMOS) |
address pin. |
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SOT2 |
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Single serial I/O output pin |
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(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
9
MB90470 Series
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Pin no. |
Pin name |
Circuit |
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Description |
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LQFP |
QFP |
type |
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P42 |
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General purpose input/output port. |
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18 |
20 |
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A10 |
G |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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SCK2 |
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Single serial I/O clock input/output pin |
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P43, P44 |
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General purpose input/output ports. |
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19 |
21 |
A11, A12 |
F |
In non-multibus bus mode, this pin functions as an external |
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20 |
22 |
(CMOS) |
address pin. |
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MT00, MT01 |
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PG input pins |
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P45 |
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General purpose input/output ports. |
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22 |
24 |
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A13 |
G |
In non-multibus bus mode, this pin functions as an external |
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(CMOS/H) |
address pin. |
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EXTC |
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PG input pin |
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P46, P47 |
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General purpose input/output ports. |
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23 |
25 |
A14, A15 |
F |
In non-multibus bus mode, this pin functions as an external |
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24 |
26 |
(CMOS) |
address pin. |
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OUT4/OUT5 |
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Output compare event output pins |
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P50 |
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General purpose input/output port. In external bus mode, this |
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D |
pin functions as the ALE pin |
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68 |
70 |
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ALE |
(CMOS) |
In external bus mode, this pin functions as the address load |
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enable signal (ALE) pin |
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P51 |
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General purpose input/output port. In external bus mode, this |
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69 |
71 |
D |
pin functions as the RD pin. |
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(CMOS) |
In external bus mode, this pin functions as the read strobe |
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RD |
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output (RD) pin. |
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General purpose input/output port. In external bus mode, this |
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P52 |
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pin functions as the |
WRL |
pin when the WRE bit in the EPCR |
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D |
register is set to “1”. |
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70 |
72 |
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In external bus mode, this pin functions as the lower data write |
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(CMOS) |
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strobe output |
(WRL) |
pin. When the WRE bit in the EPCR |
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WRL |
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register is set to “0”,this pin functions as a general purpose |
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input/output port. |
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General purpose input/output port. In external bus mode with |
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P53 |
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16-bit bus width, this pin functions as the |
WRH |
pin when the |
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D |
WRE bit in the EPCR register is set to “1”. |
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71 |
73 |
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In external bus mode with 16-bit bus width, this pin functions |
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(CMOS) |
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as the higher data write strobe output |
(WRH) |
pin. When the |
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WRH |
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WRE bit in the EPCR register is set to “0”,this pin functions as |
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a general purpose input/output port. |
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(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
10
MB90470 Series
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Pin no. |
Pin name |
Circuit |
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Description |
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LQFP |
QFP |
type |
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General purpose input/output port. In external bus mode, this |
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P54 |
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pin functions as the HRQ pin when the HDE bit in the EPCR |
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72 |
74 |
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D |
register is set to “1”. |
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(CMOS) |
In external bus mode, this pin functions as the hold request |
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HRQ |
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input (HRQ) pin. When the HDE bit in the EPCR register is set |
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to “0”,this pin functions as a general purpose input/output port. |
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General purpose input/output port. In external bus mode, this |
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P55 |
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pin functions as the |
HAK |
pin when the HDE bit in the EPCR |
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D |
register is set to “1”. |
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73 |
75 |
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In external bus mode, this pin functions as the hold acknowl- |
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(CMOS) |
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edge output (HAK) pin. When the HDE bit in the EPCR register |
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HAK |
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is set to “0”,this pin functions as a general purpose input/output |
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port. |
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General purpose input/output port. In external bus mode, this |
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P56 |
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pin functions as the DRY pin when the RYE bit in the EPCR |
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74 |
76 |
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D |
register is set to “1”. |
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(CMOS) |
In external bus mode, this pin functions as the external ready |
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RDY |
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input (RDY) pin. When the RYE bit in the EPCR register is set |
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to “0”,this pin functions as a general purpose input/output port. |
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General purpose input/output port. In external bus mode, this |
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P57 |
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pin functions as the CLK pin when the CKE bit in the EPCR |
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D |
register is set to “1”. |
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76 |
78 |
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In external bus mode, this pin functions as the machine cycle |
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(CMOS) |
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clock output (CLK) pin. When the CKE bit in the EPCR register |
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CLK |
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is set to “0”,this pin functions as a general purpose input/output |
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port. |
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36 to 39 |
38 to 41 |
P60 to P63 |
H |
General purpose input/output ports. |
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AN0 to AN3 |
(CMOS) |
Analog input pins. |
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41 to 44 |
43 to 46 |
P64 to P67 |
H |
General purpose input/output ports. |
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AN4 to AN7 |
(CMOS) |
Analog input pins. |
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25 |
27 |
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P70 |
G |
General purpose input/output port. |
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SIN0 |
(CMOS/H) |
UART data input pin. |
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26 |
28 |
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P71 |
F |
General purpose input/output port. |
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SOT0 |
(CMOS) |
UART data output pin. |
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27 |
29 |
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P72 |
G |
General purpose input/output port. |
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SCK0 |
(CMOS/H) |
UART clock input pin. |
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28 |
30 |
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P73 |
G |
General purpose input/output port. |
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TIN0 |
(CMOS/H) |
16-bit reload timer event input pin. |
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29 |
31 |
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P74 |
F |
General purpose input/output port. |
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TOT0 |
(CMOS) |
16-bit reload timer output pin. |
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(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
11
MB90470 Series
|
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Pin no. |
Pin name |
Circuit |
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Description |
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LQFP |
QFP |
type |
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30 |
32 |
P75 |
G |
General purpose input/output port. |
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PWC2 |
(CMOS/H) |
PWC input pin. |
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P76 |
I |
General purpose input/output port. |
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31 |
33 |
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2 |
2 |
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SCL |
(NMOS/H) |
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I C interface data input/output pin. During I C interface |
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operation, the port output should be set to High-Z level. |
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P77 |
I |
General purpose input/output port. |
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32 |
34 |
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2 |
2 |
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SDA |
(NMOS/H) |
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I |
C interface clock input/output pin. During I C interface |
|
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operation, the port output should be set to High-Z level. |
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45 |
47 |
P80, P81 |
E |
General purpose input/output ports. |
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46 |
48 |
IRQ0, IRQ1 |
(CMOS/H) |
External interrupt input pins. |
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50 to 55 |
52 to 57 |
P82 to P87 |
E |
General purpose input/output ports. |
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IRQ2 to IRQ7 |
(CMOS/H) |
External interrupt input pins. |
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P90 |
E |
General purpose input/output port. |
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56 |
58 |
SIN1 |
Single serial I/O data input pin. |
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(CMOS/H) |
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CS0 |
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Chip select 0. |
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P91 |
D |
General purpose input/output port. |
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57 |
59 |
SOT1 |
Single serial I/O data output pin. |
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(CMOS) |
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CS1 |
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Chip select 1. |
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P92 |
E |
General purpose input/output port. |
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58 |
60 |
SCK1 |
Single serial I/O clock input/output pin. |
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(CMOS/H) |
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CS2 |
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Chip select 2. |
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P93 |
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General purpose input/output port. |
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FRCK |
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In free run timer operation, this pin functions as the external |
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E |
clock input pin. |
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59 |
61 |
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ADTG |
(CMOS/H) |
In A/D converter operation, this pin functions as the external |
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trigger input pin. |
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CS3 |
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Chip select 3. |
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60 |
62 |
P94 |
D |
General purpose input/output port. |
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PPG4 |
(CMOS) |
PPG timer output pin. |
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61 |
63 |
P95 |
D |
General purpose input/output port. |
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PPG5 |
(CMOS) |
PPG timer output pin. |
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62 |
64 |
P96 |
E |
General purpose input/output port. |
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IN0 |
(CMOS/H) |
Functions as input capture ch 0 trigger input. |
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(Continued)
LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
12
MB90470 Series
(Continued)
Pin no. |
Pin name |
Circuit |
Description |
||
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||||
LQFP |
QFP |
type |
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63 |
65 |
P97 |
E |
General purpose input/output port. |
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IN1 |
(CMOS/H) |
Functions as input capture ch 1 trigger input. |
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64 to 67 |
66 to 69 |
PA0 to PA3 |
D |
General purpose input/output ports. |
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OUT0 to OUT3 |
(CMOS) |
Output compare event output pins. |
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33 |
35 |
AVCC |
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A/D converter power supply pin. |
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34 |
36 |
AVRH |
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A/D converter external reference power pin. |
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35 |
37 |
AVSS |
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A/D converter power supply pin. |
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47 to 49 |
49 to 51 |
MD0 to MD2 |
J |
Input pins for specifying operating mode. |
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(CMOS/H) |
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82 |
84 |
VCC3 |
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3.3 V ± 0.3 V power supply pin (VCC3) . |
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21 |
23 |
VCC5 |
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3.3 V ± 0.3 V/5.0 V ± 0.5 V dual power supply pin (VCC5) . |
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9 |
11 |
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40 |
42 |
VSS |
Power supply input pins (GND) . |
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79 |
81 |
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LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package
Notes : • For use as a 3.3 V single supply device, apply the same voltage to the VCC3 and VCC5 power supply pins.
•For use with a dual power supply, apply the respective voltages to the VCC3 and VCC5 power supply pins.
•In use with a dual power supply, a total of 32 pins (P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/ A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5 and P70/SIN0 to P77/SDA) can be used in a 5 V interface. Note that all other pins must be used in 3 V interface.
•In use with a dual power supply, it is not possible to turn on only the 5 V or the 3 V power supply independently. Always turn on both power supplies simultaneously. (It is recommended that the 3 V power to the MB90470 series be turned on first.)
13
MB90470 Series
■ I/O CIRCUIT TYPES |
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Type |
Circuit |
Remarks |
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X1, X1A |
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Oscillator feedback resistance : |
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X0, X0A |
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X1,X0 |
1 MΩ approx. |
A |
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X1A,X0A |
10 MΩ approx. |
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Includes standby control |
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Standby control |
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signal |
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B |
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Hysteresis with pull-up resistance |
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HYS |
Input resistance 50 kΩ approx. |
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CTL |
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Includes input pull-up resistance control |
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C |
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CMOS level input/output |
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Resistance : 50 kΩ approx. |
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CMOS |
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D |
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CMOS level input/output |
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CMOS
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Hysteresis input |
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CMOS level input/output |
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CMOS |
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(Continued)
14
MB90470 Series
(Continued)
Type |
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Circuit |
Remarks |
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Open drain |
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F |
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control signal |
CMOS level input/output |
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CMOS |
Includes open drain control |
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Open drain |
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control signal |
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CMOS level output |
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G |
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Hysteresis input |
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Includes open drain control |
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HYS |
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H |
CMOS level input/output |
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Analog input |
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CMOS |
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Analog input |
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Digital output |
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I |
Hysteresis input |
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N-ch open drain output |
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HYS |
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(Flash model) |
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Flash model |
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CMOS level input |
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Control signal |
Includes high voltage control for FLASH |
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test |
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J |
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Mode input |
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Spreading resistance |
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(Mask version) |
Mask version |
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HYS |
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Hysteresis input port |
15
MB90470 Series
■HANDLING DEVICES
(1)Strictly observe maximum rated voltages (prevent latchup)
When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins other than mediumand high-withstand voltage pins, or to voltages lower than VSS, or when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AVCC, AVRH) and analog input do not exceed the digital power supply (VCC) .
(2) Treatment of unused pins
If unused input pins are left open, abnormal operation or latchup may cause permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 kΩ.
Also any unused input/output pins should be left open in output status, or if set to input status should be treated in the same way as input pins.
(3) Precautions for use of external clock signals
Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used 20 MHz should be used as a guideline for an upper frequency limit.
The following figure shows a sample use of external clock signals.
X0
OPEN X1
(4) Power supply pins
When using multiple VCC/VSS sources, always make sure to design devices with external connections of all power supply pins to supply or ground elements, in order to prevent latchup, reduce unwanted radiation, and prevent abnormal strobe signal operation due to rise in ground level, as well as to maintain total rated output current. In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC and VSS as close to the pins as possible.
(5) Crystal oscillator circuits
Abnormal operation of this device can result from noise in the proximity of the X0/X1 and X0A/X1A pins. For stable operation, it is strongly recommended that the printed circuit artwork provide capacitors placed as close as possible between the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) as well as ground, and be wired so as to avoid crossing other wiring wherever possible.
16
MB90470 Series
(6) Precautions for use of external oscillators (crystals)
The target value for the upper limit of oscillator (crystals) frequencies should be 20 MHz. Also, when operating at internal frequencies of 16 MHz, the PLL multiplier should be used.
(7) Proper power-on/off sequence
The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC.
Note : VCC = VCC3 = VCC5
(8) Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AVCC = AVRH = VCC, and AVSS = VSS.
(9) Power-on procedures
In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise during power-on should be attained within 50 s (0.2 V to 2.7 V) .
(10) Stable power supply
Even within the operating range of the VCC supply voltage, rapid changes in supply voltage may cause abnormal operation. As a basis for stable operation, it is recommended that voltage variation be restricted in order to limit VCC ripple fluctuations (P-P values) to 10% at commercial frequencies of 50 Hz to 60 Hz, and transient fluctuations to 0.1 V/ms at instantaneous points such as power switching.
(11) Precautions for use of two power supplies
The MB90470 series usually uses the 3-V power supply as the main power source. With VCC3 = 3 V and VCC5 = 5 V, however, it can interface with P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/A07/PWC1,
P40/A08/SIN2 to P47/A15/OUT5, P70/SIN0 to P77/SDA for the 5-V power supply separetely from the 3-V power supply at all operation mode.
(Caution) The analog power supply for the A/D converter (AVCC, AVSS etc.) can only operate with the 3 V system.
(12) Crystal oscillator circuits during power-saving operation
When the power supply is lower than 2.0 V, the external crystal oscillator may not operate even when power is on. For this reason, the use of an external clock signal is recommended.
(13)Caution : low-voltage flash models (2.4 V to 3.6 V/10 MHz) do not have security functions
(14)Treatment of unused input pins
N.C. (internally connected) pins should always be left open.
(15) When the dual-supply MB90470 series is used as a 1-supply device, use connections so that X0A = VSS, and X1A = Open.
17
MB90470 Series
(16)For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.
For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V.
(17)Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
18
MB90470 Series
■ BLOCK DIAGRAM
X0, X1, RST
X0A, X1A
MD2, MD1, MD0
SIN0
SOT0
SCK0
SIN1, SIN2
SOT1, SOT 2 
SCK1, SCK2
AVCC
AVRH
AVSS
ADTG
AN0 to AN7
PWC0
PWC1
PWC2
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CPU |
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Clock |
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8 |
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FMC-16LX |
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control circuit |
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series core |
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RAM |
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ROM
µDMA
Communication prescaler 
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2 |
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MC2F |
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UART |
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16LX- |
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I/O expansion serial |
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BUS |
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interface × 2 channels |
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A/D converter |
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(10-bit) |
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16-bit PWC
3 channels
Interrupt controller
8/16-bit PPG
8/16-bit up/down counter
µPG
Chip select
Input/output timer
16-bit input capture × 2
16-bit output compare × 6
16-bit free-run timer
16-bit reload timer
I2C interface
External interrupt
I/O ports
8 |
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8 |
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8 |
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8 |
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8 |
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8 |
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8 |
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8 |
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8 |
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8 |
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4 |
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P00 |
P10 |
P20 |
P30 |
P40 |
P50 |
P60 |
P70 |
P80 |
P90 |
PA0 |
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P07 |
P17 |
P27 |
P37 |
P47 |
P57 |
P67 |
P77 |
P87 |
P97 |
PA3 |
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PPG0, PPG1
PPG2, PPG3 
PPG4, PPG5
AIN0, AIN1
BIN0, BIN1 
ZIN0, ZIN1
EXTC
MT00
MT01
CS0, CS1,
CS2, CS3
IN0, IN1
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
TIN0
TOT0
SCL
SDA
8
IRQ0 to IRQ7
P00 to P07 (8 pins) |
: Input pull-up resistance setting register provided. |
P10 to P17 (8 pins) |
: Input pull-up resistance setting register provided. |
P40 to P47 (8 pins) |
: Open drain setting register provided. |
P70 to P75 (6 pins) |
: Open drain setting register provided. |
P76, P77 (2 pins) |
: Open drain |
Note : In the above diagram, I/O ports are shown sharing pin numbers with the built-in function blocks. However pins may not be used as I/O ports when they are in use as pins for build-in function modules.
19
MB90470 Series
■ MEMORY MAP |
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Single chip |
Internal ROM external bus |
External ROM external bus |
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FFFFFFH |
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ROM area |
ROM area |
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Address 1# |
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010000H |
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ROM area |
ROM area |
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FF bank image |
FF bank image |
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004000H |
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* |
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Address 2# |
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RAM |
Register |
RAM |
Register |
RAM |
Register |
000100H |
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0000D0H |
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Peripheral |
Peripheral |
Peripheral |
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000000H |
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: Internal |
: External |
: Access not available |
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* : In models where address 2# coincides with 004000H, there is no external area.
Model |
Address 1# |
Address 2# |
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MB90473 |
FE0000H |
002900H |
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MB90474 |
FC0000H |
004000H |
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MB90477/478 |
FC0000H |
002100H |
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MB90F474 |
FC0000H |
004000H |
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MB90V470 |
(FC0000H) |
004000H |
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The image of FF bank ROM is reflected in the top of the 00 bank, for greater efficiency in using the C compiler for small models. The lower 16-bit address on the FF bank is the same as the lower 16-bit address on the 00 bank, so that it is possible to reference tables in ROM without using the pointer for a far specification.
For example, when accessing 00C000H, it is actually the content of ROM at FFC000H that is accessed. Here, because the ROM area on the FF bank exceeds 48 KB, it is not possible to view the entire area in the image on the 00 bank. Therefore, the image from FF4000H to FFFFFFH is visible on the 00 bank, and FF0000H to FF3FFFH is visible only on the FF bank.
20
MB90470 Series
■F2MC-16L CPU PROGRAMMING MODEL
• Special purpose registers
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AH |
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AL |
Accumulator |
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USP |
User stack pointer |
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SSP |
System stack pointer |
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PS |
Processor status |
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PC |
Program counter |
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DPR |
Direct page register |
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PCB |
Program bank register |
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DTB |
Data bank register |
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USB |
User stack bank register |
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SSB |
System stack bank register |
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ADB |
Additional data bank register |
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8 bit |
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16 bit |
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32 bit |
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• General purpose registers
MSB |
LSB |
16 bit
000180H + RP × 10H 
RW0
RL0
RW1
RW2
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RL1 |
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RW3 |
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R1 |
R0 |
RW4 |
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RL2 |
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R3 |
R2 |
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RW5 |
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R5 |
R4 |
RW6 |
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RL3 |
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R7 |
R6 |
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RW7 |
• Processor status
15 |
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13 |
12 |
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8 |
7 |
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0 |
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PS |
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ILM |
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RP |
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CCR |
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21
MB90470 Series
■ I/O MAP
Address |
Register name |
Symbol |
Access |
Resource name |
Default |
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00H |
Port 0 data register |
PDR0 |
R/W |
Port |
0 |
XXXXXXXX |
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01H |
Port 1 data register |
PDR1 |
R/W |
Port |
1 |
XXXXXXXX |
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02H |
Port 2 data register |
PDR2 |
R/W |
Port |
2 |
XXXXXXXX |
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03H |
Port 3 data register |
PDR3 |
R/W |
Port |
3 |
XXXXXXXX |
|
|
|
|
|
|
|
|
|
04H |
Port 4 data register |
PDR4 |
R/W |
Port |
4 |
XXXXXXXX |
|
|
|
|
|
|
|
|
|
05H |
Port 5 data register |
PDR5 |
R/W |
Port |
5 |
XXXXXXXX |
|
|
|
|
|
|
|
|
|
06H |
Port 6 data register |
PDR6 |
R/W |
Port |
6 |
XXXXXXXX |
|
|
|
|
|
|
|
|
|
07H |
Port 7 data register |
PDR7 |
R/W |
Port |
7 |
1 1XXXXXX |
|
|
|
|
|
|
|
|
|
08H |
Port 8 data register |
PDR8 |
R/W |
Port |
8 |
XXXXXXXX |
|
|
|
|
|
|
|
|
|
09H |
Port 9 data register |
PDR9 |
R/W |
Port |
9 |
XXXXXXXX |
|
|
|
|
|
|
|
||
0AH |
Port A data register |
PDRA |
R/W |
Port A |
- - - - XXXX |
||
|
|
|
|
|
|
||
0BH |
Port 3 timer input enable register |
UDRE |
R/W |
Up/down timer |
XX 0 0 0 0 0 0 |
||
input control |
|||||||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
0CH |
Interrupt/DTP enable register |
ENIR |
R/W |
|
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
||
0DH |
Interrupt/DTP enable register |
EIRR |
R/W |
DTP/external |
0 0 0 0 0 0 0 0 |
||
0EH |
Demand level setting register |
ELVR |
R/W |
interrupt |
0 0 0 0 0 0 0 0 |
||
|
|
|
|
|
|
||
0FH |
Demand level setting register |
R/W |
|
|
0 0 0 0 0 0 0 0 |
||
|
|
|
|||||
|
|
|
|
|
|
|
|
10H |
Port 0 direction register |
DDR0 |
R/W |
Port |
0 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
11H |
Port 1 direction register |
DDR1 |
R/W |
Port |
1 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
12H |
Port 2 direction register |
DDR2 |
R/W |
Port |
2 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
13H |
Port 3 direction register |
DDR3 |
R/W |
Port |
3 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
14H |
Port 4 direction register |
DDR4 |
R/W |
Port |
4 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
15H |
Port 5 direction register |
DDR5 |
R/W |
Port |
5 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
16H |
Port 6 direction register |
DDR6 |
R/W |
Port |
6 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
17H |
Port 7 direction register |
DDR7 |
R/W |
Port |
7 |
- - 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
18H |
Port 8 direction register |
DDR8 |
R/W |
Port |
8 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
19H |
Port 9 direction register |
DDR9 |
R/W |
Port |
9 |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
||
1AH |
Port A direction register |
DDRA |
R/W |
Port A |
- - - - 0 0 0 0 |
||
|
|
|
|
|
|
||
1BH |
Port 4 pin register |
ODR4 |
R/W |
Port 4 (OD control) |
0 0 0 0 0 0 0 0 |
||
|
|
|
|
|
|
||
1CH |
Port 0 resistance register |
RDR0 |
R/W |
Port 0 (pull-up) |
0 0 0 0 0 0 0 0 |
||
|
|
|
|
|
|
||
1DH |
Port 1 resistance register |
RDR1 |
R/W |
Port 1 (pull-up) |
0 0 0 0 0 0 0 0 |
||
|
|
|
|
|
|
||
1EH |
Port 7 pin register |
ODR7 |
R/W |
Port 7 (OD control) |
- - 0 0 0 0 0 0 |
||
|
|
|
|
|
|
||
1FH |
Analog input enable register |
ADER |
R/W |
Port 5, A/D |
1 1 1 1 1 1 1 1 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(Continued) |
|
22
MB90470 Series
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Register name |
Symbol |
Access |
Resource name |
Default |
|
|
|
|
|
|
|
|
|
|
20H |
Serial mode register 0 |
SMR0 |
R/W |
|
0 0 0 0 0 X 0 0 |
|
|
|
|
|
|
|
|
|
|
21H |
Serial control register 0 |
SCR0 |
R/W |
|
0 0 0 0 0 1 0 0 |
|
|
|
|
|
|
UART0 |
|
|
|
22H |
Serial input register/ serial output |
SIDR/ |
R/W |
XXXXXXXX |
|
|
|
register |
SODR0 |
|
|
|||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
23H |
Serial status register |
SSR0 |
R/W |
|
0 0 0 0 1 0 0 0 |
|
|
|
|
|
|
|
|
|
|
24H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
25H |
Clock divider control register |
CDCR |
R/W |
Communication |
0 0 - - 0 0 0 0 |
|
|
prescaler (UART) |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
26H |
Serial mode control status register 0 |
SMCS0 |
R/W |
|
- - - - 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
27H |
Serial mode control status register 0 |
SMCS0 |
R/W |
SCI1 (ch0) |
0 0 0 0 0 0 1 0 |
|
|
|
|
|
|
|
|
|
|
28H |
Serial data register |
SDR0 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
29H |
Clock divider control register |
SDCR0 |
R/W |
Communication |
0 - - - 0 0 0 0 |
|
|
prescaler (SCI0) |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2AH |
Serial mode control status register 1 |
SMCS1 |
R/W |
|
- - - - 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
2BH |
Serial mode control status register 1 |
SMCS1 |
R/W |
SCI2 (ch1) |
0 0 0 0 0 0 1 0 |
|
|
|
|
|
|
|
|
|
|
2CH |
Serial data register |
SDR1 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
2DH |
Clock divider control register |
SDCR1 |
R/W |
Communication |
0 - - - 0 0 0 0 |
|
|
prescaler (SCI1) |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2EH |
PPG reload register L (ch0) |
PRLL0 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
2FH |
PPG reload register H (ch0) |
PRLH0 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
30H |
PPG reload register L (ch1) |
PRLL1 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
31H |
PPG reload register H (ch1) |
PRLH1 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
32H |
PPG reload register L (ch2) |
PRLL2 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
33H |
PPG reload register H (ch2) |
PRLH2 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
34H |
PPG reload register L (ch3) |
PRLL3 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
35H |
PPG reload register H (ch3) |
PRLH3 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
36H |
PPG reload register L (ch4) |
PRLL4 |
R/W |
8/16-bit PPG |
XXXXXXXX |
|
|
37H |
PPG reload register H (ch4) |
PRLH4 |
R/W |
(ch0-ch5) |
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
38H |
PPG reload register L (ch5) |
PRLL5 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
39H |
PPG reload register H (ch5) |
PRLH5 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
3AH |
PPG0 operating mode control register |
PPGC0 |
R/W |
|
0 X 0 0 0XX 1 |
|
|
|
|
|
|
|
|
|
|
3BH |
PPG1 operating mode control register |
PPGC1 |
R/W |
|
0 X 0 0 0 0 0 1 |
|
|
|
|
|
|
|
|
|
|
3CH |
PPG2 operating mode control register |
PPGC2 |
R/W |
|
0 X 0 0 0XX 1 |
|
|
|
|
|
|
|
|
|
|
3DH |
PPG3 operating mode control register |
PPGC3 |
R/W |
|
0 X 0 0 0 0 0 1 |
|
|
|
|
|
|
|
|
|
|
3EH |
PPG4 operating mode control register |
PPGC4 |
R/W |
|
0 X 0 0 0XX 1 |
|
|
|
|
|
|
|
|
|
|
3FH |
PPG5 operating mode control register |
PPGC5 |
R/W |
|
0 X 0 0 0 0 0 1 |
|
|
|
|
|
|
|
|
|
|
40H |
PPG0, 1 output control register |
PPG01 |
R/W |
8/16-bit PPG |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(Continued) |
|
23
MB90470 Series
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Register name |
Symbol |
Access |
Resource name |
Default |
|
|
|
|
|
|
|
|
|
|
41H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
42H |
PPG2, 3 output control register |
PPG23 |
R/W |
8/16-bit PPG |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
43H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
44H |
PPG4, 5 output control register |
PPG45 |
R/W |
8/16-bit PPG |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
45H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
46H |
Control status register |
ADCS1 |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
47H |
ADCS2 |
R/W |
A/D converter |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
48H |
Data register |
ADCR1 |
R |
XXXXXXXX |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
49H |
ADCR2 |
R |
|
0 0 0 0 0 XXX |
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
4AH |
Output compare register (ch0) low |
OCCP0 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
||
|
4BH |
Output compare register (ch0) high |
|
XXXXXXXX |
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
4CH |
Output compare register (ch1) low |
OCCP1 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
||
|
4DH |
Output compare register (ch1) high |
|
XXXXXXXX |
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
4EH |
Output compare register (ch2) low |
OCCP2 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
||
|
4FH |
Output compare register (ch2) high |
|
XXXXXXXX |
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
50H |
Output compare register (ch3) low |
OCCP3 |
R/W |
16-bit output timer |
XXXXXXXX |
|
|
|
|
|
|
|||
|
51H |
Output compare register (ch3) high |
output compare |
XXXXXXXX |
|
||
|
|
|
|
||||
|
|
|
|
|
(ch0-ch5) |
|
|
|
52H |
Output compare register (ch4) low |
OCCP4 |
R/W |
XXXXXXXX |
|
|
|
|
|
|||||
|
|
|
|
|
|
||
|
53H |
Output compare register (ch4) high |
|
XXXXXXXX |
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
54H |
Output compare register (ch5) low |
OCCP5 |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
||
|
55H |
Output compare register (ch5) high |
|
XXXXXXXX |
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
56H |
Output compare control register (ch0) |
OCS0 |
R/W |
|
0 0 0 0 - - 0 0 |
|
|
|
|
|
|
|
|
|
|
57H |
Output compare control register (ch1) |
OCS1 |
R/W |
|
- - - 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
58H |
Output compare control register (ch2) |
OCS2 |
R/W |
|
0 0 0 0 - - 0 0 |
|
|
|
|
|
|
|
|
|
|
59H |
Output compare control register (ch3) |
OCS3 |
R/W |
|
- - - 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
5AH |
Output compare control register (ch4) |
OCS4 |
R/W |
16-bit output timer |
0 0 0 0 - - 0 0 |
|
|
5BH |
Output compare control register (ch5) |
OCS5 |
R/W |
OCU (ch4, 5) |
- - - 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
5CH |
Input capture register (ch0) low |
IPCP0 |
R |
|
XXXXXXXX |
|
|
|
|
|
|
|
|
|
|
5DH |
Input capture register (ch0) high |
R |
16-bit output timer |
XXXXXXXX |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
5EH |
Input capture register (ch1) low |
|
R |
XXXXXXXX |
|
|
|
IPCP1 |
Input capture (ch0, 1) |
|
||||
|
|
|
|
|
|
||
|
5FH |
Input capture register (ch1) high |
R |
XXXXXXXX |
|
||
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
60H |
Input capture control register |
ICS01 |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
61H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(Continued) |
|
24
MB90470 Series
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Register name |
Symbol |
Access |
Resource name |
Default |
|
|
|
|
|
|
|
|
|
|
62H |
Timer data register low |
TCDT |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
63H |
Timer data register high |
TCDT |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
64H |
Timer control status register |
TCCS |
R/W |
16-bit output timer |
0 0 0 0 0 0 0 0 |
|
|
65H |
Timer control status register |
TCCS |
R/W |
Free run timer |
0 - - 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
66H |
Compare clear register low |
CPCLR |
R/W |
|
XXXXXXXX |
|
|
|
|
|
|
|
||
|
67H |
Compare clear register high |
|
XXXXXXXX |
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
68H |
Up down count register ch0 |
UDCR0 |
R |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
69H |
Up down count register ch1 |
UDCR1 |
R |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
6AH |
Reload compare register ch0 |
RCR0 |
W |
8/16-bit up-down |
0 0 0 0 0 0 0 0 |
|
|
6BH |
Reload compare register ch1 |
RCR1 |
W |
timer-counter |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
6CH |
Counter control register low ch0 |
CCRL0 |
R/W |
|
0 X 0 0 X 0 0 0 |
|
|
|
|
|
|
|
|
|
|
6DH |
Counter control register high ch0 |
CCRH0 |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
6EH |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
6FH |
ROM mirror function select register |
ROMM |
W |
ROM mirror function |
- - - - - - - 1 |
|
|
|
|
|
|
|
|
|
|
70H |
Counter control register low ch1 |
CCRL1 |
R/W |
8/16-bit up-down |
0 X 0 0 X 0 0 0 |
|
|
|
|
|
|
|
|
|
|
71H |
Counter control register high ch1 |
CCRH1 |
R/W |
- 0 0 0 0 0 0 0 |
|
|
|
timer-counter |
|
|||||
|
|
|
|
|
|
|
|
|
72H |
Count status register ch0 |
CSR0 |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
73H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
74H |
Count status register ch1 |
CSR1 |
R/W |
8/16-bit UDC |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
75H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
76H |
PWC0 control status register |
PWCSR0 |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|||
|
77H |
16-bit PWC timer |
0 0 0 0 0 0 0 X |
|
|||
|
|
|
|
|
|||
|
78H |
PWC0 data buffer register |
PWCR0 |
R/W |
(ch0) |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|||
|
79H |
|
0 0 0 0 0 0 0 0 |
|
|||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
7AH |
PWC1 control status register |
PWCSR1 |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|||
|
7BH |
16-bit PWC timer |
0 0 0 0 0 0 0 X |
|
|||
|
|
|
|
|
|||
|
7CH |
PWC1 data buffer register |
PWCR1 |
R/W |
(ch1) |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|||
|
7DH |
|
0 0 0 0 0 0 0 0 |
|
|||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
7EH |
PWC2 control status register |
PWCSR2 |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|||
|
7FH |
16-bit PWC timer |
0 0 0 0 0 0 0 X |
|
|||
|
|
|
|
|
|||
|
80H |
PWC2 data buffer register |
PWCR2 |
R/W |
(ch2) |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|||
|
81H |
|
0 0 0 0 0 0 0 0 |
|
|||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
82H |
PWC0 division ratio register |
DIVR0 |
R/W |
PWC (ch0) |
- - - - - - 0 0 |
|
|
|
|
|
|
|
|
|
|
83H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
84H |
PWC1 division ratio register |
DIVR1 |
R/W |
PWC (ch1) |
- - - - - - 0 0 |
|
|
|
|
|
|
|
|
|
|
85H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(Continued) |
|
25
MB90470 Series
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Register name |
Symbol |
Access |
Resource name |
Default |
|
|
|
|
|
|
|
|
|
|
86H |
PWC2 division ratio register |
DIVR2 |
R/W |
PWC (ch2) |
- - - - - - 0 0 |
|
|
|
|
|
|
|
|
|
|
87H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
88H |
I2C bus status register |
IBSR |
R |
|
0 0 0 0 0 0 0 0 |
|
|
89H |
I2C bus control register |
IBCR |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
8AH |
I2C bus clock select register |
ICCR |
R/W |
I2C functions |
- - 0XXXXX |
|
|
8BH |
I2C bus address register |
IADR |
R/W |
|
- XXXXXXX |
|
|
8CH |
I2C bus data register |
IDAR |
R/W |
|
XXXXXXXX |
|
|
8DH |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
8EH |
PG control register |
PGCSR |
R/W |
PG |
0 0 0 0 0 - - - |
|
|
|
|
|
|
|
|
|
|
8FH to 9BH |
|
Prohibited |
|
|
|
|
|
|
|
|
|
|
|
|
|
9CH |
DMA status register |
DSRL |
R/W |
DMA |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
9DH |
DMA status register |
DSRH |
R/W |
DMA |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
9EH |
Program address detection control |
PACSR |
R/W |
Address Match |
0 0 0 0 0 0 0 0 |
|
|
status resister |
Detection Function |
|
||||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
9FH |
Delay interrupt source generate/ |
DIRR |
R/W |
Delay interrupt |
- - - - - - - - 0 |
|
|
release register |
generator module |
|
||||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
A0H |
Low power mode register |
LPMCR |
R/W |
Low power modes |
0 0 0 1 1 0 0 0 |
|
|
|
|
|
|
|
|
|
|
A1H |
Clock select register |
CKSCR |
R/W |
Low power modes |
1 1 1 1 1 1 0 0 |
|
|
|
|
|
|
|
|
|
|
A2H, A3H |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
A4H |
DMA stop status register |
DSSR |
R/W |
DMA |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
A5H |
Auto ready function select register |
ARSR |
W |
External pins |
0 0 1 1 - - 0 0 |
|
|
|
|
|
|
|
|
|
|
A6H |
External address output control |
HACR |
W |
External pins |
0 0 0 0 0 0 0 0 |
|
|
register |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A7H |
Bus control signal control register |
EPCR |
W |
External pins |
1 0 0 0 * 1 0 - |
|
|
|
|
|
|
|
|
|
|
A8H |
Watchdog control register |
WDTC |
R/W |
Watchdog timer |
XXXXX 1 1 1 |
|
|
|
|
|
|
|
|
|
|
A9H |
Time base timer control register |
TBTC |
R/W |
Time base timer |
1 X X 0 0 1 0 0 |
|
|
|
|
|
|
|
|
|
|
AAH |
Watch timer control register |
WTC |
R/W |
Watch timer |
1 0 0 0 1 0 0 0 |
|
|
|
|
|
|
|
|
|
|
ABH |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
ACH |
DMA control register |
DERL |
R/W |
DMA |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
ADH |
DMA control register |
DERH |
R/W |
DMA |
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
AEH |
Flash memory control status register |
FMCR |
R/W |
Flash memory |
0 0 0 X 0 0 0 0 |
|
|
interface |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AFH |
|
Prohibited |
|
|
|
|
|
|
|
|
|
|
|
|
|
B0H |
Interrupt control register 00 |
ICR00 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B1H |
Interrupt control register 01 |
ICR01 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B2H |
Interrupt control register 02 |
ICR02 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B3H |
Interrupt control register 03 |
ICR03 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
(Continued)
26
MB90470 Series
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Register name |
Symbol |
Access |
Resource name |
Default |
|
|
|
|
|
|
|
|
|
|
B4H |
Interrupt control register 04 |
ICR04 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B5H |
Interrupt control register 05 |
ICR05 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B6H |
Interrupt control register 06 |
ICR06 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B7H |
Interrupt control register 07 |
ICR07 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B8H |
Interrupt control register 08 |
ICR08 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
B9H |
Interrupt control register 09 |
ICR09 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
BAH |
Interrupt control register 10 |
ICR10 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
BBH |
Interrupt control register 11 |
ICR11 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
BCH |
Interrupt control register 12 |
ICR12 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
BDH |
Interrupt control register 13 |
ICR13 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
BEH |
Interrupt control register 14 |
ICR14 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
BFH |
Interrupt control register 15 |
ICR15 |
R/W |
|
XXXX 0 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C0H |
Chip select MASK register 0 |
CMR0 |
R/W |
Chip select functions |
0 0 0 0 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C1H |
Chip select area register 0 |
CAR0 |
R/W |
|
1 1 1 1 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C2H |
Chip select MASK register 1 |
CMR1 |
R/W |
|
0 0 0 0 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C3H |
Chip select area register 1 |
CAR1 |
R/W |
|
1 1 1 1 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C4H |
Chip select MASK register 2 |
CMR2 |
R/W |
|
0 0 0 0 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C5H |
Chip select area register 2 |
CAR2 |
R/W |
|
1 1 1 1 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C6H |
Chip select MASK register 3 |
CMR3 |
R/W |
|
0 0 0 0 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C7H |
Chip select area register 3 |
CAR3 |
R/W |
|
1 1 1 1 1 1 1 1 |
|
|
|
|
|
|
|
|
|
|
C8H |
Chip select control register |
CSCR |
R/W |
|
- - - - 0 0 0 * |
|
|
|
|
|
|
|
|
|
|
C9H |
Chip select control active level register |
CALR |
R/W |
|
- - - - 0 0 0 0 |
|
|
|
|
|
|
|
|
|
|
CAH |
Timer control status registers |
TMCSR |
R/W |
|
0 0 0 0 0 0 0 0 |
|
|
|
|
|
|
|||
|
CBH |
16-bit reload timer |
- - - - 0 0 0 0 |
|
|||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
CCH |
16-bit timer register |
TMR/ |
R/W |
XXXXXXXX |
|
|
|
|
|
|||||
|
CDH |
16-bit reload register |
TMRLR |
|
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
CEH, CFH |
|
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
|
D0H to FFH |
|
External area |
|
|
|
|
|
|
|
|
|
|
|
|
|
100H to #H |
|
RAM area |
|
|
|
|
|
|
|
|
|
|
|
|
|
1FF0 |
Program address detection resister0 |
|
|
|
|
|
|
(Low order address) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1FF1 |
Program address detection resister0 |
PADR0 |
R/W |
Address Match |
XXXXXXXX |
|
|
(Middle order address) |
Detection Function |
|
||||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
1FF2 |
Program address detection resister0 |
|
|
|
|
|
|
(High order address) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(Continued) |
|
27
MB90470 Series
(Continued)
Address |
Register name |
Symbol |
Access |
Resource name |
Default |
|
|
|
|
|
|
|
|
|
1FF3 |
Program address detection resister1 |
|
|
|
|
|
(Low order address) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1FF4 |
Program address detection resister1 |
PADR1 |
R/W |
Address Match |
XXXXXXXX |
|
(Middle order address) |
Detection Function |
||||
|
|
|
|
|
||
|
|
|
|
|
|
|
|
1FF5 |
Program address detection resister1 |
|
|
|
|
|
(High order address) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Interrupt symbols : |
|
|
|
|
||
R/W : Read/write enabled |
|
|
|
|
||
R |
: Read only |
|
|
|
|
|
W |
: Write only |
|
|
|
|
|
Default value symbols :
0: This bit initialized to “0”
1: This bit initialized to “1”
* : This bit initialized to “0” or “1” X : Default value undefined
- : This bit is not used.
28
MB90470 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS & INTERRUPT CONTROL REGISTERS
|
EI2OS |
DMA |
Interrupt vector |
Interrupt control |
||
Interrupt source |
register |
|||||
support |
channel no. |
|
|
|
|
|
|
No. |
Address |
No. |
Address |
||
|
|
|
||||
|
|
|
|
|
|
|
Reset |
|
|
#08 |
FFFFDCH |
|
|
|
|
|
|
|
|
|
INT9 instruction |
|
|
#09 |
FFFFD8H |
|
|
|
|
|
|
|
|
|
Exception |
|
|
#10 |
FFFFD4H |
|
|
|
|
|
|
|
|
|
INT0 |
|
0 |
#11 |
FFFFD0H |
ICR00 |
0000B0H |
|
|
|
|
|
||
INT1 |
|
× |
#12 |
FFFFCCH |
||
|
|
|
||||
|
|
|
|
|
|
|
INT2 |
|
× |
#13 |
FFFFC8H |
ICR01 |
0000B1H |
|
|
|
|
|
||
INT3 |
|
× |
#14 |
FFFFC4H |
||
|
|
|
||||
|
|
|
|
|
|
|
INT4 |
|
× |
#15 |
FFFFC0H |
ICR02 |
0000B2H |
|
|
|
|
|
||
INT5 |
|
× |
#16 |
FFFFBCH |
||
|
|
|
||||
|
|
|
|
|
|
|
INT6 |
|
× |
#17 |
FFFFB8H |
ICR03 |
0000B3H |
|
|
|
|
|
||
INT7 |
|
× |
#18 |
FFFFB4H |
||
|
|
|
||||
|
|
|
|
|
|
|
PWC1 |
|
× |
#19 |
FFFFB0H |
ICR04 |
0000B4H |
|
|
|
|
|
||
PWC2 |
|
× |
#20 |
FFFFACH |
||
|
|
|
||||
|
|
|
|
|
|
|
PWC0 |
|
1 |
#21 |
FFFFA8H |
ICR05 |
0000B5H |
|
|
|
|
|
||
PPG0/PPG1 counter borrow |
|
2 |
#22 |
FFFFA4H |
||
|
|
|
||||
|
|
|
|
|
|
|
PPG2/PPG3 counter borrow |
|
3 |
#23 |
FFFFA0H |
ICR06 |
0000B6H |
|
|
|
|
|
||
PPG4/PPG5 counter borrow |
|
4 |
#24 |
FFFF9CH |
||
|
|
|
||||
|
|
|
|
|
|
|
8/16-bit |
|
|
|
|
|
|
up/down counter timer compare/ |
|
× |
#25 |
FFFF98H |
|
|
underflow /overflow/ |
|
ICR07 |
0000B7H |
|||
|
|
|
|
|||
amp down inversion (ch0, 1) |
|
|
|
|
|
|
|
|
|
|
|
|
|
Input capture (ch0) load |
|
5 |
#26 |
FFFF94H |
|
|
|
|
|
|
|
|
|
Input capture (ch1) load |
|
6 |
#27 |
FFFF90H |
ICR08 |
0000B8H |
|
|
|
|
|
||
Output compare (ch0) match |
|
8 |
#28 |
FFFF8CH |
||
|
|
|
||||
|
|
|
|
|
|
|
Output compare (ch1) match |
|
9 |
#29 |
FFFF88H |
ICR09 |
0000B9H |
|
|
|
|
|
||
Output compare (ch2) match |
|
10 |
#30 |
FFFF84H |
||
|
|
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||||
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Output compare (ch3) match |
|
× |
#31 |
FFFF80H |
ICR10 |
0000BAH |
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Output compare (ch4) match |
|
× |
#32 |
FFFF7CH |
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Output compare (ch5) match |
|
× |
#33 |
FFFF78H |
ICR11 |
0000BBH |
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|
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||
UART send end |
|
11 |
#34 |
FFFF74H |
||
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||||
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16-bit free run timer/ |
|
12 |
#35 |
FFFF70H |
|
|
16-bit reload timer overflow |
|
ICR12 |
0000BCH |
|||
|
|
|
|
|||
UART receive end |
|
7 |
#36 |
FFFF6CH |
|
|
|
|
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|
|
(Continued)
29
MB90470 Series
(Continued)
|
EI2OS |
DMA |
Interrupt vector |
Interrupt control |
|||
Interrupt source |
register |
||||||
support |
channel no. |
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|
No. |
Address |
No. |
Address |
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SIO1 |
|
13 |
#37 |
FFFF68H |
ICR13 |
0000BDH |
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|
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SIO2 |
|
14 |
#38 |
FFFF64H |
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|||||
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|
|
|
|
|
I2C interface |
× |
× |
#39 |
FFFF60H |
ICR14 |
0000BEH |
|
A/D |
|
15 |
#40 |
FFFF5CH |
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|
|
|||||
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|
|
|
|
|
|
|
Flash write/erase, time base timer, |
× |
× |
#41 |
FFFF58H |
|
|
|
watch timer* |
ICR15 |
0000BFH |
|||||
|
|
|
|
||||
Delay interrupt generator module |
× |
× |
#42 |
FFFF54H |
|
|
|
|
|
|
|
|
|
|
|
: Interrupt request flag cleared by the interrupt clear signal. The stop request is available. 
: Interrupt request flag cleared by the interrupt clear signal.
×: Interrupt request flag not cleared by the interrupt clear signal.
*: Note that flash write/erase cannot be used at the same time as the time base timer or watch timer.
Note : • If two or more interrupt sources have the same interrupt number, the resource will clear both interrupt request flags at the EI2OS/DMAC interrupt clear signal. Thus when EI2OS/µDMA function of two sources is used, the other interrupt function cannot be used. The interrupt request enable bit of the corresponding resource should be set to “0” for software polling processing.
• Maximum assured operation frequency of µDMA is 16 MHz.
30
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