Datasheet WM5628LIN, WM5628LIDW, WM5628LCN, WM5628LCDW, WM5628IN Datasheet (Wolfson)

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WM5628L, WM5628

3 & 5V Octal 8-Bit Voltage Output DAC

with Serial Interface

Production Data

Sept. 1996 Rev 2

Description

WM5628L and WM5628 are Octal 8-bit digital to analogue
converters (DAC) controlled via a serial interface. Each
DAC's output voltage range is programmable for either x1
or x 2 its reference input voltage, allowing near rail to rail
operation for the x 2 output range. High impedance
buffered voltage reference inputs are provided for each
group of four DACs. WM5628L operates on a single
supply voltage of 3 V while WM5628 operates on 5 V .
WM5628/L interfaces to all popular microcontrollers and
microprocessors via a three wire serial interface with CMOS
compatible, schmitt trigger, digital inputs. An 12 bit
command word comprises 3 DAC select bits, an output
range selection bit and 8-bits of data.
Individual or all DAC outputs are changed using
WM5628/L's double buffered DAC registers and the
separate LOAD and LDAC inputs. DAC outputs are
updated simultaneously by writing a complete set of new
values and then pulsing the LDAC input.
The DAC outputs are optimised for single supply
operation and driving ground referenced loads.
An internal power-on-reset function sets the DAC's input
codes to zero at power up.
Ideal in space critical applications WM5628/L is available
in wide-bodied and DIP packages for commercial (0

o

C) and industrial (-40oC to 85oC) temperature ranges.

70

o

C to

Pin Configuration

Features

• Eight 8-bit voltage output DAC's

• Three wire serial interface

• Programmable x1 or x 2 output range.

• Power-on-reset sets outputs to zero

• Buffered voltage reference inputs

• Simultaneous DAC output update

Key Specifications

• Single supply operation:
WM5628L : 3 V
WM5628 : 5 V

• 0 to 4 V output (x 2 output range) at 5 V V

DD

• 0 to 2.5 V output (x 2 output range) at 3 V VDD

• Guaranteed monotonic output

Applications

• Programmable d.c. voltage sources

• Digitally controlled attenuator/amplifier

• Signal synthesis

• Mobile communications

• Automatic test equipment

• Process control

Ordering Information

16 pin N and DW packages

Top View

1

DD

16

2

15

3

14

4

13

5

12

6

11

7

10

89

DAC
DAC
Ref1
LDAC
Load
Ref2
DAC

Tel: [phone] Fax: [phone]

ACB

ACA
GND
Data

CLK

V
ACE
ACF DAC

Production Data data sheets contain
final specifications current on publication
date. Supply of products conforms to
Wolfson Microelectronics standard terms
and conditions

DEVICE TEMP. RANGE PACKAGE

WM5628CN 0oC to 70oC 16 pin plastic DIP

o

WM5628CDW 0

C to 70oC 16 pin wide-bodied plastic SO
WM5628IN -40oC to 85oC 16 pin plastic DIP
WM5628IDW -40oC to 85oC 16 pin wide-bodied plastic SO
WM5628LCN 0oC to 70oC 16 pin plastic DIP
WM5628LCDW 0oC to 70oC 16 pin wide-bodied plastic SO
WM5628LIN -40oC to 85oC 16 pin plastic DIP
WM5628LIDW -40oC to 85oC 16 pin wide-bodied plastic SO

Wolfson Microelectronics

Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK

email: [e-mail]

www: http://www.wolfson.co.uk

© 1996 Wolfson Microelectronics

WM5628L, WM5628

R

R

D

L

V

A

B

C

D

E

F

G

H

Block Diagram

14

ef 1

DD

6

9

Latch

Latch

DAC

8

x 2

2

DAC

9

Latch

9

Latch

9

ef 2

11

5

CLK

ata

oad

4

12

Serial Interface

Latch

9

Latch

9

Latch

9

Latch

9

Latch

Latch

Latch

Latch

Latch

Latch

Latch

Latch

DAC

8

DAC

8

DAC

8

DAC

8

DAC

8

DAC

8

DAC

8

Power-on-Reset

x 2

x 2

x 2

x 2

x 2

x 2

x 2

1

DAC

16

DAC

15

DAC

7

DAC

8

DAC

9

DAC

10

DAC

13

3

2

Wolfson Microelectronics

WM5628L, WM5628

Absolute Maximum Ratings (note 1)

Supply Voltage (VDD - VGND) . . . . . . . . . . . . +7V

Digital Inputs . . . . . . . . . . .GND - 0.3 V, VDD + 0.3 V

Reference inputs . . . . . . . GND - 0.3 V, V

DD + 0.3 V

Recommended Operating Conditions

SYMBOL MIN NOMINAL MAX UNIT

Supply voltage WM5628 VDD 4.75 5.25 V
Supply V oltage WM5628L VDD 2.7 5.25 V
Reference input range, X1 gain VREF 3.3 VDD - 1.5 V
DAC output load resistance to GND RL 10 kΩ
High level digital input voltage VIH 0.8 VDD V
Low level digital input voltage VIL 0.8 V
Clock frequency FCLK 1 MHz

Electrical Characteristics: WM5628

VDD = 5 V, GND = 0 V, VREF = 2 V, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Power Supply

Supply current I

Static Accuracy

Resolution 8 Bits
Monotonicity 8 Bits
Differential Nonlinearity DNL VREF = 2 V, Range x 2. (note 3) ± 0.1 ± 0.9 LSB
Integral Nonlinearity INL VREF = 2 V, Range x 2. (note 4) ± 1.0 LSB
Zero-code error ZCE VREF = 2 V , Range x 2. (note 5) 30 mV
Zero-code error Input code = 00 Hex (note 6) 10 µV/OC
temperature coefficient
Zero-code error supply Input code = 00 Hex, 0.5 mV/V
rejection VDD = 5 V ± 5 % (note 7)
Full scale error FSE VREF = 2 V, Range x 2. (note 8) ± 60 mV
Full scale error Input code = FF Hex (note 9) ± 25 µV/OC
temperature coefficient
Full scale error supply Input code = FF Hex, 0.5 mV/V
rejection VDD = 5 V ± 5 % (note 10)
Output sink current IO(SINK) Each DAC output 20 µA

Output source current IO(SOURCE) 2mA

DD Outputs unloaded, 4.0 mA

digital inputs = 0 V or VDD

Operating temperature range, TA . . . . . . T

WM5628_C_ . . . . . . . . . . . . . . 0oC to +70oC

WM5628_I_ . . . . . . . . . . . . . . . -40oC to +85oC

Storage T emperature . . . . . . . . . . -50oC to +150oC

Lead T emperature 1.6mm (1/16 inch)

from case for 10 secs . . . . . . . . . . . . . 260

MIN to TMAX

O

C

Wolfson Microelectronics

3

WM5628L, WM5628

Electrical Characteristics: WM5628L

VDD = 3 .6V, GND = 0 V , V REF = 2 V x 1 gain, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Power Supply

Supply current IDD VDD = 3.3v 4 mA

Static Accuracy

Resolution 8 Bits
Monotonicity 8 Bits
Differential Nonlinearity DNL VREF = 1.25 V, Range x 2. (note 3) ± 0.9 LSB
Integral Nonlinearity I NL VREF = 1.25 V, Range x 2. (note 4) ± 1.0 LSB
Zero-code error ZCE VREF = 1.25 V , Range x 2. (note 5) 0 30 mV
Zero-code error Input code = 00 Hex (note 6) 10 µV/OC
temperature coefficient
Full scale error FSE VREF = 1.25 V , Range x 2. (note 8) ± 60 mV
Full scale error Input code = FF Hex (note 9) ± 25 µV/OC
temperature coefficient
Output sink current IO(SINK) Each DAC output 20 µA
Output source current IO(SOURCE) 1mA
Power supply IREF VDD = 3.3V, VREF = 1.5V 0.5 mV/V
sensitivity PSRR

Electrical Characteristics: WM5628 & WM5628L

VDD = 2.7 to 5.5V, GND = 0 V, V REF = 2 V x 1 gain, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital Inputs

High level input current I
Low level input current IIL VI = 0V ±10 µA
Input capacitance CI 15 pF

Timing Parameters

Data input setup time tSD 50 n s
Data input hold time tHD 50 n s

CLK to Load tHL 50 ns

to CLK tSL 50 ns

Load
Load duration t WL 250 ns
LDAC duration t WD 250 n s

Load

to LDAC tLD 0ns

Reference Inputs

Reference input VREF A, B, C, D, inputs GND VDD-1.5 V
voltage
Reference input A, B, C, D, inputs 15 pF
capacitance
Reference A, B, C, D inputs (note 1 1) -60 dB
feedthrough
Channel to channel A, B, C, D inputs (note 12) -60 dB
isolation

IH VI = VDD ±10 µA

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Wolfson Microelectronics

WM5628L, WM5628

Electrical Characteristics: WM5628 & WM5628L (continued)

VDD = 3 .6V , GND = 0 V, VREF = 2 V x 1 gain, RL = 10 kΩ, CL = 100 pF, TA = full range, unless otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Performance

Output settling time T o 1/2LSB, VDD=3V & 5V (note 13) 10 µs
Output slew rate 1 V/µs
Input bandwidth (note 14) 100 kHz
Large Signal Bandwidth Measured at -3dB point 100 kH z
Digital Crosstalk Clk = 1MHz sq wave measured at -50 dB

DACA - DACD

Notes:

1. Absolute Maximum Ratings are stress ratings only.
Permanent damage to the device may be caused by
continuously operating at or beyond these limits.
Device functional operating range limits are given
under Recommended Operating Conditions.
Guaranteed performance specifications are given
under Electrical Characteristics at the test conditions
specified.

2. Total Unadjusted Error is the sum of integral linearity
error, zero code error and full scale error over the input
code range.

3. Differential Nonlinearity (DNL) is the difference
between the measured and ideal 1 LSB amplitude
change of any two adjacent codes. A guarantee of
monotonicity means the output voltage changes in the
same direction (or remains constant) as a change in
the digital input code.

4. Integral Nonlinearity (INL) is the maximum deviation of
the output from the line between zero and full scale
(excluding the effects of zero code and full-scale
errors).

5. Zero code error is the deviation from zero voltage
output when the digital input code is zero.

6. Zero code error temperature coefficient is given by:
ZCETC = (ZCE(T

max - ZCE(Tmin)) /VREF x 10

6

/ (Tmax

- Tmin)

8. Full-scale error is the deviation from the ideal full-scale
output (V

REF - 1LSB) with an output load of 10kΩ

9. Full-Scale T emperature Co-ef ficient is given by:
FSETC = (FSE(Tmax) - FSE(Tmin)) / VREF x 10
/ Tmax - T min)

10. Full Scale Error Rejection Ratio (FSE-RR) is
measured by varying the V

DD voltage from 4.5 to

5.5 V d.c. and measuring the proportion of this signal
imposed on the full-scale output voltage

11 Reference feedthrough is measured at a DAC output

with an input code = 00 Hex with a V

REF input = 1 Vdc

+ 1 VPP at 10kHz

12. Channel to channel isolation is measured at a DAC
output with an input code of one DAC to FF Hex and
the code oa all other DACs to oo Hex with a V
put = 1 V

dc + 1 Vpp at 10kHz

13 Setting time is the time for the output signal to remain

within ±0.5 LSB of the final measurement value for a
digital input code change of 00 Hex to FF Hex. For
WM 5628: V
WM5628L: V

DD = 5V , VREF = 2V and range = x 2. For

DD = 3, VREF = 1.25V and range = x 2.

14 Reference bandwidth is the -3dB bandwidth with an

input at VREF = 1.25 Vdc =+ 2 Vpp with a digital input
code of full-scale.

6

REF in-

7. Zero-code Error Rejection Ratio (ZCE-RR) is
measured by varying the V

DD voltage, from 4.5 to 5.5

V d.c., and measuring the proportion of this signal
imposed on the zero-code output voltage.

Wolfson Microelectronics

5

WM5628L, WM5628

s

Parameter Measurement Information

DACA
DACB
DACC

.
.

DACH

Slewing Settling Time and Linearity Measurements

Typical Performance Characteristics

Typical DNL, INL and TUE * at VDD = 5 V

10KΩ CL - 100pF

0.2

0.1
0

Error (lsb)

-0.1

-0.2
0 32 64 96 128 160 192 224 256

0.5

0.25
0

Error (lsb)

-0.25

-0.5
0 32 64 96 128 160 192 224 256

* see note 2

Differential Nonlinearity

VDD = 5 V, Vref = 2.5 V, Range x 1, TA = 25oC

Input Code

Total Unadjusted Error

VDD = 5 V, Vref = 2.5 V, Range x 1, TA = 25oC

Input C ode

Integra l Nonline a rity

VDD = 5 V, Vref =2.5 V, Range x 1, TA = 25oC

0.4

0.2

0

Error (lsb)

-0.2

0 32 64 96 128 160 1 92 224 256

Input Code

Differentia l Nonline arity

VDD = 5 V, Vref = 1.25 V, Range x 2, TA = 25oC

0.2

0.1
0

Error (l

-0.1

-0.2
0 32 64 96 1 28 160 192 2 24 256

Input Code

6

Wolfson Microelectronics

Typical Performance Characteristics (continued)

s

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nt

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)

V
T
V
R
I

s

)

)

R
I

5

V

V

V

V

V
V

V

Typical DNL, INL and TUE * at VDD = 5 V (continued)

WM5628L, WM5628

Integra l Nonline arity

VDD = 5 V, Vref = 1.25 V, Ra n g e x 2, TA = 25oC

0.4

0.2
0

Error (l

-0.2
0 32 64 96 128 1 60 192 224 2 56

Input Code

Typical DNL, INL and TUE at VDD = 3 V

Differential Nonlinearity

VDD = 3 V, Vref = 1.25 V, Ran g e x 2, TA = 25oC

0.2

0.1
0

Error (lsb)

-0.1

-0.2
0 32 64 96 128 160 192 224 256

Input Code

Total Una djusted Error

VDD = 3 V, Vref = 1.25 V, Ran ge x 2, TA = 25oC

0.5

0.25
0

Error (l

-0.25

-0.5
0 32 64 96 128 160 192 224 2 56

Input Code

Total Unadjusted E rror

VDD = 5 V, Vref = 1.25 V, Ra n ge x 2, TA = 25oC

0.5

0.25
0

-0.25

Error (l

-0.5

0 32 64 96 128 160 192 224 256

Input Code

Integral Nonlinearity

V

= 3 V, Vref = 1.25 V, Rang e x 2, TA = 25oC

DD

0.5

0.25
0

-0.25

Error (lsb)

-0.5

0 32 64 96 128 1 60 192 224 256

Input Code

Output Source Curre

vs Output Volt age

8

7

6

5

4

DD = 5 V

(mA
I

= 25OC

A

out

= 2 V

ref

3

ange = x 2

n put code = 255

2

1

0

012345

V

(V

out

2.4

2.2

1.8

IDD (mA

1.6

1.4

Supply Current v

Temperature

DD + 3V
ref = 1.25

DD = 5
ref = 2

o

C

ange = x 2

2

nput Code = 25

-50 -25 0 25 50 75 100

Temperature ('C

Wolfson Microelectronics

7

WM5628L, WM5628

y

)

)

V
T

V
I

y

z)

)

V
T
V
I

T ypical Performance Characteristics (continued)

Large Signal Frequenc

Response

2
0

-2

-4

-6

-8

-10

DD = 5 V

A

-12

= 25OC

ref = 1.25 Vdc + 2 Vpp

Relative Gain (dB

-14

nput Code = 255

-16

-18

-20
1101001000

Frequency (kHz

Positive Rise and Settling Time VDD = 3 V

500 mV/Vert. div
2 µs/Hor. div

VDD = 3 V

O

A = 25

C

T
code 00 to FF Hex
Range = x 2
Vref = 1.25 V

Small Signal Frequenc

Response

10

0

-10

-20

DD = 5 V

-30

= 25OC

A

ref = 2 Vdc + 0.5 V

-40

nput code = 255

Relative Gain (dB

-50

-60
1 10 100 1000 10000

pp

Frequency (kH

Negative Fall and Settling Time VDD = 3 V

VDD = 3 V

O

A = 25

C

T

500 mV/Vert. div
2 µs/Hor. div

code FF to 00 Hex
Range = x 2
Vref = 1.25 V

Rise time = 2.5 µs, Positive slew rate = 0.80 µs
Settling time = 4.5 µs

Positive Rise and Settling Time VDD = 5 V

1 V/Vert. div
2 µs/Hor. div

DD = 5 V

V

O

A = 25

C

T
code 00 to FF Hex
Range = x 2
Vref = 2 V

Rise time = 3.75 µs, Positive slew rate = 0.54 µs
Settling time = 5.9 µs

8

Wolfson Microelectronics

Fall time = 4.85 µs, Negative slew rate = 0.41 µs
Settling time = 8.0 µs

Negative Fall and Settling Time VDD = 5 V

VDD = 5 V

O

C

TA = 25
code FF to 00 Hex
Range = x 2
Vref = 2 V

1 V/Vert. div
5 µs/Hor. div

Fall time = 5.9 µs, Negative slew rate = 0.54 µs
Settling time = 8.5 µs

Equivalent Input and Output Circuits

D

Data Input Timing

Load and LDAC Timing

Timing Waveforms

WM5628L, WM5628

CLK

ata

50 %

t

SD

t

HD

CLK

Load

50 %

t

HL

t

WL

t

LD

t

SL

t

WD

LDAC

Wolfson Microelectronics

9

WM5628L, WM5628

1 2 3 4 5 6 7 8 9 10 11

12

L

L

L

1 2 3 4 5 6 7 8 9 10 11 12

L

Timing Diagrams

CLK

Data

Load

DAC

A1A2A0

RNG

D7 D6 D5 D4 D3 D2 D1 D0

Figure 1. Load controlled update (LDAC = 0)

1 2 3 4 5 6 7 8 9 10 11

CLK

Data

Load

DAC

A1A2A0

RNG

D7 D6 D5 D4 D3 D2 D1 D0

Figure 2. LDAC controlled update

CLK

Data

A2 A1 A0

RNG

12

D7 D6 D5 D4 D3 D2 D1 D0

Load

DAC

CLK

Data

Load

DAC

Figure 3. Load controlled update (LDAC = 0) using 8-bit serial word.

1 2 3 4 5 6 7 8 9 10 11 12

A2 A1 A0

RNG

D7 D6 D5 D4 D3 D2 D1 D0

Figure 4. LDAC controlled update using 8-bit serial word.

10

Wolfson Microelectronics

WM5628L, WM5628

Pin Descriptions

Pin Name Type Function

1 DACB Analogue output DAC B output
2 DACA Analogue input DAC A output
3 GND Supply Ground return
4 Data Digital input Serial data input
5 CLK Digital input Serial interface clock, negative edge sensitive
6VDD Supply Positive supply voltage
7 DACE Analogue output DAC E output
8 DACF Analogue output DAC F output
9 DACG Analogue output DAC G output
10 DACH Analogue output DAC H output
11 Ref2 Analogue input Reference to DACE, DACF, DACG and DACH
12 Load Digital input Serial input load
13 LDAC Digital input DAC update latch control
14 Ref1 Analogue input Reference to DACA, DACB, DACC and DACD
15 DACD Analogue output DAC D output
16 DACC Analogue output DAC C output

Functional Description

DAC operation

Each of WM5628/L 's eight digital to analogue converters
(DACs) are implemented using a single resistor string with
256 taps corresponding to each of the input 8-bit codes.
One end of a resistor string is connected to the GND pin
and the other end is driven from the output of a reference
input buffer. The use of a resistor string guarantees
monotonicity of the DAC's output voltage. Linearity depends
upon the matching of the resistor string's individual elements
and the performance of the output buffe r. Two high input
impedance voltage reference buffers are provided, each
driving four DACs,

Each DAC has a voltage output amplifier which is
programmable for gains of x1 or x 2 through the serial
interface. The DAC output amplifiers feature rail to rail
output stages, allowing outputs over the full supply voltage
range to be achieved with a x 2 gain setting and a V
reference voltage input. Used in this way a slight
degradation in linearity will occur as the output voltage
approaches V

A power-on-reset activates at power up resetting the DACs
inputs to code 0. Each output voltage is given by:

DD.

out = Vref x CODE/256 x (RNG+1 )

V

DD/2

Data Interface

WM5628/L's eight double buffered DAC inputs allow
several ways of controlling the update of each DAC's
output.

Serial data is input, MSB first, into the DA T A input pin Serial
Input DAC Address and Output Tables using CLK, LOAD
and LDAC control inputs and comprises 3 DAC address
bits, an output range (RNG) bit and 8 DAC input bits.

With the LOAD pin high data is clocked into the DATA pin
on each falling edge of CLK. Any number of data bits may
be clocked in, only the last 12 bits are used. When all data
bits have been clocked in, a falling edge at the LOAD pin
latches the data and RNG bits into the correct 9 bit input
latch using the 3 bit DAC address.

If the LDAC input pin is low, the second latch at the DAC
input is transparent, and the DAC input and RNG bit will be
updated on the falling edge of LOAD simultaneously with
the input latch, as shown in figure 1. If the LDAC input is high
during serial data input, as shown in figure 2, the falling edge
of the LOAD input stores the data in the addressed input
latch. The falling edge of LDAC updates the second latches
from the input latches and hence the DAC outputs.

Where: RNG controls the output gains of x 1 and x 2

CODE is the range 0 to 255

Wolfson Microelectronics

11

WM5628L, WM5628

Functional Description (continued)

Using these inputs individual DACs can be updated using
one 12 bit serial input word and the LOAD pin. Using both
LOAD and LDAC, all or selected DACs can be updated
after an appropriate number of data words have been
inputted. Figures 3 &4 illustrate operation with the 8 clock
pulses available from some microprocessors. If the data
input is interrupted in this way the clock input must be held
low during the break in clock pulses.

The RNG bit controls the DAC output range. When RNG = 0
the output is between Vref(A,B,C,D) and GND and when
RNG = 1 the range is between 2 x Vref (A,B,C,D) and GND.

Serial Input DAC Address and Output Tables

A2 A1 A0 DAC Updated

0 0 0 DACA
0 0 1 DACB
0 1 0 DACC
0 1 1 DACD
1 0 0 DACE
1 0 1 DACF
1 1 0 DACG
1 1 1 DACH

D7 D6 D5 D4 D3 D2 D1 D0 Output Voltage

0 0 0 0 0 0 0 0 GND
0 0 0 0 0 0 0 1 (1/256) x Ref (1 + RNG)

0 1 1 1 1 1 1 1 (127/256) x Ref (1 + RNG)
1 0 0 0 0 0 0 0 (128/256) x Ref (1 + RNG)

1 1 1 1 1 1 1 1 (255/256) x Ref (1 + RNG)

12

Wolfson Microelectronics

Functional Description (Continued)

Linearity, offset, and gain error using
single end supplies

When an amplifier is operated from a single supply, the
voltage offset can still be either positive or negative. With a
positive offset, the output voltage changes on the first code
change. With a negative offset the output voltage may not
change with the first code depending on the magnitude of
the offset voltage.
The output amplifier, with a negative voltage of fset, attempts
to drive the output to a negative voltage. However , because
the most negative supply rail is GND, the output cannot drive
to a negative voltage.
So when the output offset voltage is negative, the output
voltage remains at ZERO volts until the input code value
produces a sufficient output voltage to overcome the
inherent negative offset voltage, resulting in the transfer
function shown below

WM5628L, WM5628

This negative offset error, not the linearity error, produces
this breakpoint. The transfer function would have followed
the dotted line if the output buffer could drive to a negative
voltage.
For a DAC, linearity is measured between ZERO input code
( all inputs 0 ) and full scale code ( all inputs 1 ) after offset
and full scale are adjusted out or accounted for in some way .
However, single supply operation does not allow for
adjustment when the offset is negative due to the break­point in the transfer function. So the linearity in the unipolar
mode is measured between full scale code and the lowest
code which produces a positive output voltage. The code is
calculated from the maximum specification for the negative
offset.

Effect of negative offset (single supply)

Wolfson Microelectronics

13

WM5628L, WM5628

Package Descriptions

Dual-In-Line Package

N or P

N

0.005
Min.

1

0.070 Max.

Pin spacing

0.100 B.S.C.

A

0.045

0.030

0.022

0.014

O

105

O

90

0.014

0.008

Dimension 'A' Variations

0.325

0.290

0.280

0.240

Seating
plane

0.210 Max.

0.150

0.115

0.015
Min.

NMinMax

8 0.355 0.400
14 0.735 0.775
16 0.735 0.775
20 0.940 0.975

Notes:

A. Dimensions are in inches
B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001)
C. N is the maximum number of terminals
D. All end pins are partial width pins as shown, except the 14 pin package which is full width.

N/2

14

Rev. 1 November 96

Wolfson Microelectronics

Package Description

Wide body Plastic Small-Outline Package

1,27 B.S.C.

0,51

16

0,33

0,25 M

WM5628L, WM5628

DW - 16 pin shown

PINS**

9

DIM

A MAX

16

10,50

20

13,00

24

15,60

28

18,10

10,65
10,00

7,60
7,40

18

2,65
2,35

A

0,30
0,10

0,10

A MIN

0,33
0,23

0o - 8

10,10

o

12,60

Gauge Plane

15,20

1,27
0,40

17,70

0.75 x 45

0.25 x 45

Notes:

A. Dimensions in millimeters.
B. Complies with Jedec standard MS-013.
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion.
E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not

exceed 0.25mm.

0
0

Wolfson Microelectronics

Rev. 1 November 96

15