Apple Q16C Schematic

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

78

6

5

4

3

ECN

ZONE

03

REV

384363

DESCRIPTION OF CHANGE

ENGINEERING RELEASED

12

CK
APPD

DATE

06/03/05

ENG
APPD

?

DATE

MARIAS

D

CSAPDF CSAPDF

TABLE_TABLEOFCONTENTS_HEAD

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2 2

TABLE_TABLEOFCONTENTS_ITEM

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C

B

15 15

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16 16

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17 17

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39 48

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40 50

TABLE_TABLEOFCONTENTS_ITEM

CONTENTS

Table Of Contents
Board Information
System Block Diagram
Power Block Diagram
Revision History
Q16C Pin Swaps
Functional Test Points
I2C Connections
JTAG Connections
Power Synonyms
Signal Synonyms
Power Inputs
Battery Charger

12.8V PBUS/PMU Supplies
5V/3.3V Supplies

1.8V/1.5V Supplies

2.5V Supply
Vesta Power & Misc
I2 Power
I2 Power Supplies
I2 Supplemental
I2 Miscellaneous
PCI Clock Buffer
LEDs/Reset/Debug
Power Management Unit (PMU05)
Power Sequencing
Fan Controller
ALS Support
Sudden Motion Sensor
Q16C Internal I/O I
Q16C Internal I/O II
I2 Processor Interface
A8 MaxBus (CPU0)
A8 Configuration Straps
A8 Power (CPU0)
CPU VCore Supply
CPU AVDD Supply
I2 Memory Interface
Memory Series Termination
DDR2 SO-DIMM Slot A

SYNC MASTER

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

N/A
MULLET
MULLET
MULLET

N/A

N/A

N/A

N/A

N/A

DATE

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

N/A
05/25/2005
05/25/2005
05/25/2005

N/A

N/A

N/A

N/A

N/A

TABLE_TABLEOFCONTENTS_HEAD

41 52

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

42 55

TABLE_TABLEOFCONTENTS_ITEM

43 56

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44 57

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45 58

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46 59

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47 60

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48 61

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49 62

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51 64

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52 65

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53 66

TABLE_TABLEOFCONTENTS_ITEM

54 67

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55 68

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56 69

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57 70

TABLE_TABLEOFCONTENTS_ITEM

58 71

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59 72

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60 73

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61 74

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62 75

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63 81

TABLE_TABLEOFCONTENTS_ITEM

64 82

TABLE_TABLEOFCONTENTS_ITEM

65 84

TABLE_TABLEOFCONTENTS_ITEM

66 85

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67 86

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68 88

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69 89

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70 90

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71 91

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72 92

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73 93

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74 100

TABLE_TABLEOFCONTENTS_ITEM

75 110

TABLE_TABLEOFCONTENTS_ITEM

76 111

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77 112

TABLE_TABLEOFCONTENTS_ITEM

78 113

TABLE_TABLEOFCONTENTS_ITEM

79 114

TABLE_TABLEOFCONTENTS_ITEM

80 115

TABLE_TABLEOFCONTENTS_ITEM

CONTENTS

DDR2 SO-DIMM Slot B
M11 Frame Buffer Constraints
I2 AGP Interface
GPU (M11) AGP Interface
GPU VCore Supply
GPU (M11) Core Power
GPU (M11) I/O Power
GPU (M11) Frame Buffer I/F
GPU Frame Buffer A
GPU Frame Buffer B
GPU (M11) GPIOs/Straps
GPU (M11) Clocks/Misc
GPU (M11) DVI/DAC Outputs
Lower TMDS Transmitter
Upper TMDS Transmitter
Internal Display Conns
External Display Conns
BootROM
I2 PCI Interface
Q85 Airport/BT Connector
Cardbus
NEC USB2
I2 UATA Interface
HDD/ODD Connectors
I2 Ethernet Interface
Vesta Ethernet PHY
Ethernet Connector
I2 FireWire Interface
Vesta FireWire PHY
FireWire Ports
FireWire Series Term
I2 USB Interface
NEC USB2 Interface
Audio Board Connector
Spacing & Physical Constraints
Spacing & Physical Constraints 2
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page

EVTSTD

SYNC MASTER

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

DATE

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

D

C

B

DIMENSIONS ARE IN MILLIMETERS

XX

A

PART#

051-6929

820-1875

826-4393

826-4393

826-4393

826-4393

QTY

DESCRIPTION

SCHEM,MARIAS-STD,Q16C

1

PCBF,MARIAS,12L-STD,Q16C

1

1

LBL,P/N LABEL,PCB,28MM x 6MM

1

LBL,P/N LABEL,PCB,28MM x 6MM

1

LBL,P/N LABEL,PCB,28MM x 6MM

1

LBL,P/N LABEL,PCB,28MM x 6MM

8

REFERENCE DESIGNATOR(S)

SCH1

PCB1

[EEE:SYT]

[EEE:SYU]

[EEE:TMJ]

[EEE:TMK]

BOM OPTION

Q16C_BTR_VRAM_S

Q16C_BST_VRAM_S

Q16C_BTR_VRAM_H

Q16C_BST_VRAM_H

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

67

5

4

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

DRAFTER

ENG APPD

QA APPD

RELEASE

3

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

TITLE

DRAWING NUMBER

D

Apple Computer Inc.

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SCHEM,MARIAS-STD,Q16C

051-6929

REV.

SHT

1

1

03

OF

A

115

78

6

5

4

3

12

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_ASSIGNMENT

D

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_ASSIGNMENT

TABLE_SPACING_ASSIGNMENT

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

Layer-specific rules for 90-ohm differential impedance

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

Layer-specific rules for 100-ohm differential impedance

TABLE_SPACING_RULE

TABLE_SPACING_RULE

C

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

Layer-specific rules for 110-ohm differential impedance

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

Portable-specific Override Rules

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_SPACING_RULE

B

TABLE_SPACING_RULE

TABLE_SPACING_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

BOM NUMBER

Design-Specific Rules

**
*
*
*

*
*

TOP,BOTTOM

*

TOP,BOTTOM

*

TOP,BOTTOM

*

*

*

*

*
*

*

*

*

*

*

*

*

1MM
1MM
1MM
1MM

Y

Y
Y

Y
Y

Y
Y

0.25 MM

0.15 MM

0.15 MM

BOM NAME

STANDARD
BGA_P1MM
BGA_P2MM

DEFAULT

AGP_STB

CLOCK

RAM_DIFF

DEFAULT

90_OHM_DIFF
90_OHM_DIFF

90_OHM_DIFF
90_OHM_DIFF

100_OHM_DIFF
100_OHM_DIFF

100_OHM_DIFF
100_OHM_DIFF

110_OHM_DIFF
110_OHM_DIFF

110_OHM_DIFF
110_OHM_DIFF

AGP 0.2 MM201

AGP_STB

VGA

TV

VGA

TV

630-7015
630-7016
630-7184
630-7185

10 *
20

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

251

151

151

PCBA,MLB,BETTERMHZ,MARIAS,VRAM_S,Q16C

PCBA,MLB,BESTMHZ,MARIAS,VRAM_S,Q16C

PCBA,MLB,BETTERMHZ,MARIAS,VRAM_H,Q16C

PCBA,MLB,BESTMHZ,MARIAS,VRAM_H,Q16C

BOM GROUP

A

gCommon
gCommon1
gCommon2
gCommon3
gCommon4

5V_HD_LOGIC,BACKUP_BATT,CPU_A7PM,I2_FW_BETA,I2_MAXBUS_50OHM,MAXBUS_1V8,gCommon1

MMM_ACCEL_KIONIX,GPU_PWRPLAY,GPU_SS,GPU_LVDDR_2V8,GPU_MEMIO_1V8,gCommon2

I2_REV1_NOT,I2_MAXBUS_FBCLK_MATCHED,I2_AGP_FBCLK_MATCHED,I2_PCI_FBCLK_MATCHED,gCommon3

CPU_VCORE_3STATES,I2_MAXBUS_166MHZ,I2VCORE_1V5,I2VCORE_BURST,gCommon4

VESTA_PORT2_DISABLE,DVO_1V8,TMDS_DUAL,VCORE_OFFSET,VCORE_OFFSET_SW,gUSB

gUSB

gQ16C

Q16C_PARTS,BOOTROM_PROG,PMU_PROG,DEVELOPMENT,MAXBUS_TBEN_SYNC
gQ16C_BTR
gQ16C_BST

1.25 MM

1.25 MM0.20 MM

2.5 MM0.1 MM

BGA_P1MM
BGA_P2MM
BGA_P2MM
BGA_P2MM

=DEFAULT =DEFAULT=DEFAULT=DEFAULTSTANDARD

0.118 MM

0.125 MM

0.092 MM

0.100 MM

0.080 MM

0.085 MM

0.1 MM

0.1 MM

0.15 MM 15.0 MM10.0 MM

"1MM" area defined around BGAs to
reduce DRCs caused by fan-out.

"BGA_P2MM" rule ensures these critical
signals do not fan-out routed next
to any other signals.

0.100 mm0.100 MM

0.200 MM

0.200 MM

0.1 MM

0.1 MM

0.200 MM

0.200 MM

0.1 MM

0.1 MM

0.330 MM

0.300 MM

0.1 MM

0.1 MM

=DEFAULT =DEFAULT=DEFAULT =DEFAULT

=DEFAULT =DEFAULT=DEFAULT

=60_OHM_SE=60_OHM_SE=60_OHM_SE

BOM OPTIONS

USB2_NEC,USB1P1_I2

A7PM_1P5_LGA,CPU0_BUSRATIO_9.0X

A7PM_1P67_LGA,CPU0_BUSRATIO_10.0X

=DEFAULT=DEFAULT =DEFAULT=DEFAULT=DEFAULT=DEFAULT

12.5 MM

12.5 MM

1.25 MM

2.5 MM

2.5 MM

5 MM
5 MM

2.5 MM

2.5 MM 1.0 MM2.5 MM

5 MM
5 MM

2.5 MM

2.5 MM 1.0 MM2.5 MM

5 MM
5 MM

=60_OHM_SE=60_OHM_SE=60_OHM_SE=60_OHM_SE

=60_OHM_SE

15.0 MM0.10 MM

15.0 MM

1.0 MM2.5 MM

1.0 MM2.5 MM

1.0 MM2.5 MM

1.0 MM2.5 MM

=DEFAULT

Layer-specific rules for 60-ohm single-ended impedance

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

60_OHM_SE

Layer-specific rules for 50-ohm single-ended impedance

TABLE_SPACING_RULE

TABLE_SPACING_RULE

50_OHM_SE

TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE

50_OHM_SE

BOM OPTIONS

COMMON,ALTERNATE,gQ16C,gQ16C_BTR,Q16C_BTR_VRAM_S,VRAM_SAMSUNG,gCommon

COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_S,VRAM_SAMSUNG,gCommon

COMMON,ALTERNATE,gQ16C,gQ16C_BTR,Q16C_BTR_VRAM_H,VRAM_HYNIX,gCommon

COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_H,VRAM_HYNIX,gCommon

BOM OPTIONS

GND_CHASSIS_UPPER_DVI

GND_CHASSIS_FW_LOWER_DVI

GND_CHASSIS_LCD

GND_CHASSIS_INVERTER

GND_CHASSIS_BATT_CHGR

*

1778_ITH_RC

I256

1778_VRNG

I257

GPU_DVOD_R<18>

I258

LTC3412_RUNSS

I259

TMDS_CONN_CLKP

I260

TP_NEC_SMC

I261

TP_NEC_SMI_L

I262

TP_NEC_SRCLK

I277

TP_USB2_PWREN<0>

I263

TP_USB2_PWREN<2>

I264

TP_USB2_PWREN<3>

I265

UATA_DD_R<0>

I244

UATA_DD_R<8>

I245

UATA_DD_R<10>

I246

UATA_DA_R<0>

I247

UATA_DA_R<1>

I248

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CHASSIS GND CONNECTIONS

MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

Y

*

Y*

NO_TEST Properties

NO_TEST=TRUE

45

NO_TEST=TRUE

45

53

NO_TEST=TRUE

6

NO_TEST=TRUE

17

NO_TEST=TRUE

57

NO_TEST=TRUE

62

NO_TEST=TRUE

62

62

NO_TEST=TRUE

73

NO_TEST=TRUE

73

NO_TEST=TRUE

73

NO_TEST=TRUE

63

NO_TEST=TRUE

6

63

NO_TEST=TRUE

6

63

NO_TEST=TRUE

6

63

6

NO_TEST=TRUE

63

6

NO_TEST=TRUE

=GND_CHASSIS_DVI_HOLE
=GND_CHASSIS_DVI2
=GND_CHASSIS_DVI4

=GND_CHASSIS_FW_HOLE
=GND_CHASSIS_DVI1
=GND_CHASSIS_DVI3
=GND_CHASSIS_TV
=GND_CHASSIS_ENET
=GND_CHASSIS_FW_PORT1
=GND_CHASSIS_FW_PORT2
=GND_CHASSIS_FW_EMI

=GND_CHASSIS_LCD1
=GND_CHASSIS_LCD2
=GND_CHASSIS_LCD3
=GND_CHASSIS_LCD4

=GND_CHASSIS_INV_GND_CLIP
=GND_CHASSIS_INVERTER1
=GND_CHASSIS_INVERTER2

=GND_CHASSIS_BATTCHGR_HOLE
=GND_CHASSIS_SLEEP_LED

0.076 MM

2.5 MM

0.100 MM 0.100 MM

TP_VESTA_DNC_E9

I266

TP_VESTA_F1000

I267

TP_VESTA_PHYA<0>

I268

TP_VESTA_REGSEN2

I269

TP_VESTA_SPD0

I270

USB_NEC_BT_N

I271

USB_NEC_N<1>

I272

USB_NEC_N<2>

I273

USB_NEC_N<3>

I274

USB_NEC_P<0>

I275

USB_NEC_P<1>

I276

SI_TMDS_DN<5>

I249

SI_TMDS_DN<4>

I250

SI_TMDS_DP<3>

I251

SI_TMDS_DN<2>

I252

SI_TMDS_DN<1>

I253

SI_TMDS_DN<0>

I254

SI_TMDS_CLKP

I255

=50_OHM_SE

0.125 MM

2

57

57

2

57

57

57

67

70

70

70

56

56

56

56

2

56

56

2

30

=50_OHM_SE

2.5 MM 1.0 MM

1.25 MM

NO_TEST=TRUE

18

NO_TEST=TRUE

66

66

NO_TEST=TRUE

18

NO_TEST=TRUE
NO_TEST=TRUE

66

NO_TEST=TRUE

11

6

NO_TEST=TRUE

73

NO_TEST=TRUE

73

NO_TEST=TRUE

73

NO_TEST=TRUE

73

NO_TEST=TRUE

73

NO_TEST=TRUE

55

NO_TEST=TRUE

55

NO_TEST=TRUE

55

NO_TEST=TRUE

54

NO_TEST=TRUE

54

NO_TEST=TRUE

54

NO_TEST=TRUE

54

TABLE_BOARD_INFO

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

Module Components

PART NUMBER

343S0325 CRITICAL
337S3135
341S1772
337S3162
337S3163
337S3077
338S0252
335S0088
341S1736
343S0356

333S0314

QTY

1
1
1
1
1
1
1
1
1
1
4

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

4

DESCRIPTION

IC,ASIC,I2,REV1.1,NB/SB,974 BGA

IC,PMU05,BLANK,QFP

IC,PMU05,V1,QFP

IC,A7PM,R1.5,1.67GHZ,LGA,1.28V,23W,85C

IC,A7PM,R1.5,1.5GHZ,LGA,1.28V,23W,85C

IC,A8,xxxGHZ

IC,GPU,M11P

BOOTROM,BLANK

IC,BOOTROM,B,Q16C

IC,ASIC,VESTA,V1.3,LF

REFERENCE DES

U2100
U2700
U2700
U3600
U3600
U3600
U5700
U7100
U7100
U8500

U6200,U6250,U6300,U6350

U6200,U6250,U6300,U6350

BOARD HOLES

HEATSINK MOUNTS

ZT0200

HOLE-VIA-P5RP25

1

ZT0201

HOLE-VIA-P5RP25

1

ZT0202

HOLE-VIA-P5RP25

1

ZT0203

HOLE-VIA-P5RP25

1

MECH. HOLES

TP_LEFT_KYBRD_SCREW

TP_RT_KYBRD_SCREW

TP_OPTICAL_DRIVE_SCREW

BOARD STACK-UP AND CONSTRUCTION

1
2

3
4

5
6

7
8

9

10
11

12

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL333S0317
CRITICAL

BOM OPTION

PMU_BLANK

PMU_PROG

A7PM_1P67_LGA

A7PM_1P5_LGA

CPU_A8

BOOTROM_BLANK

BOOTROM_PROG

VRAM_SAMSUNG

VRAM_HYNIX

LEFT CPU

UPPER RT GPU

LWR CPU

LWR RT GPU

ZT0221

HOLE-VIA-P5RP25

1

ZT0222

HOLE-VIA-P5RP25

1

ZT0223

HOLE-VIA-P5RP25

1

SEE BOARD FILE FOR DETAILED INFORMATION

CONVENTIONAL CONSTRUCTION WITH Pxx TH VIA

PREPREG
CORE

PREPREG
CORE

PREPREG
CORE

PREPREG
CORE

PREPREG
CORE

PREPREG

APPLE COMPUTER INC.

CHASSIS MOUNTS

ZT0210

HOLE-VIA-P5RP25

=GND_CHASSIS_DVI_HOLE

2

=GND_CHASSIS_FW_HOLE

2

=GND_CHASSIS_BATTCHGR_HOLE

2

INVERTER

=GND_CHASSIS_INV_GND_CLIP

2

SIGNAL (1/2 OZ + COPPER PLATING)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

SIGNAL (1/2 OZ)

GROUND (1/2 OZ)

CUT POWER PLANE (1 OZ)

CUT POWER PLANE (1 OZ)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

SIGNAL (1/2 OZ)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ + COPPER PLATING)

NO_TYPE,1MM

Board Information

SYNC_MASTER=N/A

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

SCALE

1

ZT0211

HOLE-VIA-P5RP25

1

BATT. CHGR

ZT0212

HOLE-VIA-P5RP25

1

1

SH0200

2

OG-503040

SHLD-SM

3

DRAWING NUMBER

051-6929

SHT

NONE

2

DVI

1394

MM

SYNC_DATE=N/A

OF

115

D

C

B

A

REV.

03

8

67

5

4

3

2

1

78

J23

Ethernet

Connector

P.28

4 DATA PAIRS

D

U43

J24

FW - A

Connector

P.30

2 DATA PAIRS
@ 200MHz

U36

FireWire

Ethernet

PHY

P.29

P.28

G/MII

3.3V

10/100/1000

8BIT TX
8BIT RX
125MHZ

U15/U20/U58

MMM

P.25

C

U41

BATTERY

CURRENT

SENSOR

P.25

NOT USED

NOT USED

NOT USED

ETHERNET

10/100/1000

USB PORT A

USB PORT B

USB PORT C

J3

BlueTooth (LIO)

NOT USED

USB PORT D

P.27

USB PORT E

J10

USB PORT F

SPIDEY

1394 OHCI

3.3V

8BIT TX/RX

50MHZ

P.13
P.14
P.14
P.14

P.14
P.14
P.14

6

PHY

FIREWIRE

400 MB/S

P.13

5

J20

FW - B

Connector

P.30

J15

SW MODEM

Connector

2 DATA PAIRS
@ 400MHZ

J13

ODD

Connector

P.26

J12

HDD

Connector

P.26

UIDE

UATA 100

P.13

EIDE

P.13

EIDE

NOT USED

CARDSLOT

P.13

U51

INTREPID

P.27

P.14

I2S

BOOTROM

P.13
P.14

SCCA

P.14

VIA/PMU

P.14

P.12

I2C

PCI

64BITS

33MHZ

P.12

I2CI2S

P.24

MAXBUS

B

MAXBUS

1.8V

167MHZ
32BIT ADDRESS
64BIT DATA

U56

P.8

DDR MEMORY

U16/U18/U28/U27

P.9

MEMORY BUS

2.5V

167MHZ
64BITS

4X AGP

P.12

J4

4

J3

LIO/Audio

Connector

P.27

U53/J1/J18

Fan

I2C

Circuit

P.27

J28

Serial Debug

AGP BUS

1.5V/3.3V
32BITS
66MHZ

J19

J8

SLEEP

LED

P.24

Connector

P.27

U11

BOOT ROM

1M X 8

P.9

U47

ATI
M11

64MB

P.19-22

Inverter

Connector

P.23

LVDS

J14

LCD Panel

Connector

P.23

EDID (I2C)

APOLLO

CPU

(MPC7447)

P.5-6

CPU PLL

Config

P.7

PMU

2:1 DDR MUXES

P.10

J25

A

DDR SDRAM DIMM 0

DDR SDRAM DIMM 1

SO-DIMM Connector

P.11

3

J2

ALS BOARD

Connector

P.24

J26

Battery

Connector

P.32

J6

S-VIDEO

J21

S-Video

P.23

COMPOSITE

RUX Board
Connector

P.24

SMBUS

3.3V

U28

PMU

P.31

SERIAL

5V

AIRPORT

Connector

P.26

MEMORY
CH. A

(INTERNAL MEM)

MEMORY
CH. B

(INTERNAL MEM)

J22

(INTERNAL MEM)

(INTERNAL MEM)

TMDS

RGB

(VIA SIL1162)

DVI-I

ConnectorConnector

P.23

J16

BACKUP

BATTERY

CONNECTOR

P.33

Power Supply

& Charger

P.32-36

MEMORY

CH. C

MEMORY
CH. D

DDC

System Block Diagram

SYNC_MASTER=N/A

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

C692

SUPERCAP

J27

J5

CARDBUS

Connector

P.18

U8

TI PCI1510

CardBus

Controller

P.18

U17

NEC USB2.0

EHCI HC

P.17

J3

LEFT USB

(VIA LIO)

P.27

J17

RIGHT USB

(VIA STATLER)

P.27

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

SIZE

DRAWING NUMBER

D

051-6929

SCALE

NONE

12

P.33

DC-In

Connector

P.32

33MHZ
16/32 BITS

3.3V/5V

PCI BUS

32BITS
33MHZ

3.3V

SHT

OF

3

SYNC_DATE=N/A

REV.

03

115

D

C

B

A

8

67

5

4

3

2

1

78

6

POWER SYSTEM ARCHITECTURE

5

4

3

12

1V20_REF

-

>~13.44V TURNS-ON
<~13.44V SHUTS-OFF

D

AC

ADAPTER

IN

INRUSH

LIMITER

PG 32

+24V_PBUS

PG 32

14V_PBUS

PG 33

+

RUN/SS

BUCK

REGULATOR

VCC

(LTC1625)

PG 33

AC: 12.8V

NO AC: BATTERY VOLTAGE

1625 NOT RUNNING

+PBUS

BACKLIGHT

INVERTER

+5V_MAIN

MAIN 2.5V/1.5V

(MAX1715)

SHUTDOWN: STOPPED

SLEEP: RUNNING

TURNS ON OUTPUT @ 2.4V

SHUTDOWN: RUNNING

SLEEP: RUNNING

RUN: RUNNING

+5V_MAIN

+3V_PMU

+BATT

C

LDO

PG 33

+3V_PMU

+4_6V_BU

RC AT 1M*0.047UF @ 24V

STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW

RUN/SS - 5V

TURNS ON AT >1V
<100UA ALLOWED

INTERNAL ZENER CLAMP TO 6V

MAIN 3V/5V

PGOOD

+5V_MAIN

3V_5V_OK

DC/DC

(LTC3707)

VCC

14V_PBUS

BACKUP

BATTERY

CHARGER INPUT

& BOOST OUTPUT

B

BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V
(UNTIL DRAINED)

PG 33

14V CHARGES BACKUP BATTERY

24V IS OUTPUT ONLY FROM

BACKUP BATTERY

STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW

NO INRUSH PROTECTION

WHEN ONLY BATTERY IS CONNECTED

PG 34

SHUTDOWN: STOPPED

SLEEP: RUNNING

RUN: RUNNING

INTERNAL ZENER CLAMP TO 6V

<100UA ALLOWED

TURNS ON AT >1V

RUN/SS - 3V

RC AT 1M*0.1UF @ 24V

+24V_PBUS

STBYMD

BATTERY

CHARGER

SHUTDOWN: STOPPED

(MAX1772)

PG 32

+BATT

NO INRUSH PROTECTION

3S 2P 18650 CELLS

A

BATTERY VOLTAGE

FEED-IN PATH

PG 32

WHEN ONLY BATTERY IS CONNECTED

HOLDS BOTH RUN/SS AT GND
WHEN IT’S CONNECTED TO GND

TURNS CONTROL TO RUN/SS
WHEN IT’S OPEN

+3.3V_MAIN

DC/DC

(LTC3411)

SLEEP: STOPPED

RUN: RUNNING

PG 36

+PBUS

+1.8V_MAIN

MAXBUS

DCDC_EN_L

+PBUS

DCDC_EN

SLEEP

GPU_VCORE

SEQUENCING

1M & 0.1UF @14V, IT TAKES
~5.88MS TO START SWITCHER

SHUT-DOWN

SLEEP

SLEEP_L_LS5

DCDC_EN

DCDC_EN_L

+5V_MAIN

+5V_SLEEP

+3V_MAIN

+3V_SLEEP

3V_5V_OK

+2_5V_MAIN

+2_5V_SLEEP

+1_5V_MAIN

+1_5V_SLEEP

1_5V_2_5V_OK

(MAX1715 OUTPUT)

1_5V_2_5V_OK

(AT LTC1778 RUN/SS)

GPU_VCORE

(D3HOT)

GPU_VCORE

(D3COLD)

AFTER PMU IS UP AND RUNNING
DCDC_EN_L WILL PULL ON1/ON2
LOW IN SHUTDOWN

VCC

SHUTDOWN: STOPPED

D3_COLD

1_5V_2_5V_OK

DCDC_EN_L
D3_HOT

~2.23MS

+5V_MAIN

VCC

DC/DC

PG 36

RUN: RUNNING

ON1/ON2

EXT_VCC

PGOOD

+5V_MAIN

DC/DC

(LTC1778)

SLEEP: D3COLD

RUN: RUNNING

TURNS ON AS LOW AS 0.8V/TYP 1.5V

INTERNAL 1.2UA CURRENT SOURCE

RUN/SS

D3_HOT

RUN

~7.36MS

2.4V - ??? MS

??? MS

??? MS

~8.2MS

SLEEP

MAP31 DDR CORE
MAP31 DDR I/O
DDR POWER

+2.5V_MAIN

1_5V_2_5V_OK

+1.5V_MAIN

INTREPID CORE
AGP I/O

GPU_VCORE

+1.2V

PG 20

1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
+5V_MAIN TURNS ON

HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
DCDC_EN_L OR PMU_POWERUP_L
BECOMES ’1’; MUCH LESS THAN THE
RC CHARGING AT INT_VCC (5V)

RUN

SHUT-DOWN

+5V_MAIN

VCC

SHUTDOWN: STOPPED

Power Block Diagram

SYNC_MASTER=N/A

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

DCDC_EN

SLEEP

MAXBUS

SEQUENCING

+PBUS

SHDN

DC/DC

(MAX1717)

SLEEP: STOPPED

RUN: RUNNING

PG 35

CPU_VCORE

(+1.385V)

NOTICE OF PROPRIETARY PROPERTY

SIZE

DRAWING NUMBER

D

051-6929

NONE

SHT

4

SCALE

SYNC_DATE=N/A

OF

115

D

C

B

A

REV.

03

8

67

5

4

3

2

1

78

6

5

4

3

12

REVISION HISTORY

PRE-EVT

04/04/2005
04/06/2005

04/06/2005
04/11/2005

D

04/12/2005

04/13/2005
04/14/2005

04/18/2005
04/19/2005

04/20/2005

04/21/2005
04/22/2005

05/03/2005

05/04/2005
05/05/2005

05/10/2005 - Various Pb-free component replacements
05/13/2005

05/16/2005

05/20/2005
05/21/2005
05/23/2005

05/24/2005
05/25/2005

05/26/2005
05/31/2005

06/01/2005

C

- Beginning revision history

- Made DDR2 and FB pin swaps as requested by CM

- Modem connector moved to non-shared page

- Chassis grounds partitioned as in previous products

- CPU0 Vcore A/B select line hooked to I2 GPIO1

- Made additional FB pin swaps

- Changed DDR2 CS/CKE RPAKs to RPAK2P (added RP4871, RP4876)

- Implemented more DDR2 pin swaps

- Implemented FireWire pin swaps

- Added remaining spacing and physical rule tables

- Added upper LVDS channel to functional test page

- Changed battery sense resistor to 0.006 ohm (R1250)

- Stuffed R2903 to disable FW port power when off on AC

- Changed audio caps to X5R (CA033, CA050, CA051)

- Corrected MIN_LINE_WIDTH properties on PP3V3_PWRON

- Corrected TMDS DIFFERENTIAL_PAIR properties at DVI connector

- Reduced MIN_NECK_WIDTH property on GND to 0.2 mm for TMDS parts

- Corrected line and neck width properties

- Added RAM_DQS_N pulldowns

- Added high/low swing BOMOPTIONs for DVO on SI TMDS parts

- Added 1.5V DVO option to GPU

- Removed series R isolating VG from digital ground on FW ports (per design guide)

- Changed GPU to M11

- Moved FB series R to page 6104/15/2005

- Updated straps, VREF inputs and decoupling on GPU

- Corrected synonym problems on PMU port usage

- Added CPU0 VCore VID mux

- Added NO_TEST properties to buses between JTAG enabled devices

- Corrected ENET power rail to PWRON from RUN (for Wake-on-LAN)

- Fixed ENET_LOWPWR and VESTA_RESET circuits per Vesta design guide

- Changed R5880 to 6.34K to take GPU Vcore to 1.3V/1.05V

- Added page 6 and modified pages 11,35,81 for design specific pin swaps

- Corrected STOP_AGP_L net name (hooked to I2 now) and removed redundant pullup

- Added external pullups to replace missing internal I2 pullups

- Added ADC caps at PMU

- Corrected load capacitance for Vesta FireWire crystal (to 18pF)

- Disconnected FW_POWERDOWN from Vesta LPWR_1394 pin

- Corrected pulldown resistor value for 0.006 ohm battery current sense

- Changed 220uF CPU VCore caps to 330 uF LF caps

- Changed GPU FB MVREFs into separate dividers

- Pinswapped UATA I/F, DVO I/F, USB pulldowns

- Added extra cap at input to I2 USBAVDD

- Added pulldowns to unused serial debug signals (DTR/RTS)

- Added pulldown to Vesta LPWR_1394

- Added PDIAG signal between HDD and ODD connectors

- Various Pb-free component replacements

- Pinswaps for I2 RPAKs to match up with Q41C style layout

- Various Pb-free component replacements

- Added Hynix VRAM option and PCBAs

- Various Pb-free component replacements05/19/2005

- Added TBEN sync circuit

- Various Pb-free component replacements

- Added DASP signal between HDD and ODD connectors

- Corrected AGP_INT_L connection between I2 and GPU

- Corrected VGA sync connections at GPU

- Release as REV 01 for Pre-EVT/EVT

- Added NEC USB2 controller

- Added ZDB clock buffer for PCI clocks

- Various Pb-free component replacements

- Removed SMS PIC microcontroller

- Added 2 0.1uF caps to GPU Vcore regulator output

- Corrected USB2 diff pair and spacing/physical rules on port connections

- Corrected FireWire VP caps to 50V

- Various Pb-free component replacements

D

C

B

B

03

5

1

SYNC_DATE=N/A

OF

115

A

REV.

03

A

APPLE COMPUTER INC.

8

67

5

4

3

SYNC_MASTER=N/A

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

DRAWING NUMBER

D

051-6929

NONE

SHT

SCALE

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FW Series Rs

USB Pulldowns

MAXBUS Pullups

I2S Series Rs

Lower DVO Series Rs

PCI Pullups

AGP Pullups

Upper DVO Series Rs

UATA Series Rs

(IDE_CS1FX_L)

051-6929

03

115

6

SYNC_MASTER=N/A

SYNC_DATE=N/A

Q16C Pin Swaps

MAKE_BASE=TRUE

UATA_DD<15>

MAKE_BASE=TRUE

UATA_DD<3>

MAKE_BASE=TRUE

UATA_DD<7>

MAKE_BASE=TRUE

UATA_DD<2>

MAKE_BASE=TRUE

UATA_DD<14>

MAKE_BASE=TRUE

UATA_DD<11>

MAKE_BASE=TRUE

UATA_CS0_L

MAKE_BASE=TRUE

UATA_DD<12>

=RP8151P8

=RP8150P6
=RP8150P5

=RP8150P7

=RP8150P8

=RP8151P5

=RP8151P6

=RP8151P7

=RP8151P1

=RP8150P2

=RP8150P4

=RP8150P3

=RP8150P1

=RP8151P4

=RP8151P3

=RP8151P2

MAKE_BASE=TRUE

UATA_DD_R<15>

MAKE_BASE=TRUE

UATA_DD_R<3>

MAKE_BASE=TRUE

UATA_DD_R<2>

MAKE_BASE=TRUE

UATA_DD_R<7>

MAKE_BASE=TRUE

UATA_CS0_L_R

MAKE_BASE=TRUE

UATA_DD_R<11>

MAKE_BASE=TRUE

UATA_DD_R<14>

MAKE_BASE=TRUE

UATA_DD_R<12>

GPU_DVOD<17>

MAKE_BASE=TRUE

GPU_DVOD<19>

MAKE_BASE=TRUE

GPU_DVOD<21>

MAKE_BASE=TRUE

GPU_DVOD<8>

MAKE_BASE=TRUE

GPU_DVO_CLKP

MAKE_BASE=TRUE

GPU_DVO_VSYNC

MAKE_BASE=TRUE

GPU_DVO_DE

MAKE_BASE=TRUE

GPU_DVOD<15>

MAKE_BASE=TRUE

=RP6822P6

=RP6822P8
=RP6822P7

=RP6821P5

=RP6821P6

=RP6821P7

=RP6821P8

=RP6822P5

=RP6822P2
=RP6822P3

=RP6822P1

=RP6821P3
=RP6821P4

=RP6821P1
=RP6821P2

=RP6822P4

GPU_DVOD_R<15>

MAKE_BASE=TRUE

GPU_DVOD_R<17>

MAKE_BASE=TRUE

GPU_DVOD_R<19>

MAKE_BASE=TRUE

GPU_DVOD_R<21>

MAKE_BASE=TRUE

GPU_DVOD_R<8>

MAKE_BASE=TRUE

GPU_DVO_CLKP_R

MAKE_BASE=TRUE

GPU_DVO_VSYNC_R

MAKE_BASE=TRUE

GPU_DVO_DE_R

MAKE_BASE=TRUE

USB_I2_TPAD_N

MAKE_BASE=TRUE

USB_I2_TPAD_P

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_P

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_N

MAKE_BASE=TRUE

=RP9212P5

=RP9212P6

=RP9212P7

=RP9212P8

MAKE_BASE=TRUE

GPU_DVOD<18>

MAKE_BASE=TRUE

GPU_DVOD<23>

MAKE_BASE=TRUE

GPU_DVOD<22>

MAKE_BASE=TRUE

GPU_DVOD<20>

=RP6823P5

=RP6823P6

=RP6823P7

=RP6823P8

=RP5611P1

=RP5610P2

=RP5610P4

=RP5610P3

=RP5610P1

=RP5611P4

=RP5611P3

=RP5611P2

AGP_GNT_L

MAKE_BASE=TRUE

AGP_STOP_L

MAKE_BASE=TRUE

AGP_DEVSEL_L

MAKE_BASE=TRUE

AGP_FRAME_L

MAKE_BASE=TRUE

AGP_IRDY_L

MAKE_BASE=TRUE

AGP_RBF_L

MAKE_BASE=TRUE

AGP_REQ_L

MAKE_BASE=TRUE

AGP_TRDY_L

MAKE_BASE=TRUE

=RP7250P1

=RP7250P3

=RP7250P2

=RP7250P4

PCI_AIRPORT_GNT_L

MAKE_BASE=TRUE

PCI_IRDY_L

MAKE_BASE=TRUE

PCI_TRDY_L

MAKE_BASE=TRUE

PCI_STOP_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GPU_DVOD_R<14>

=RP6723P4

MAKE_BASE=TRUE

GPU_DVOD_R<0>

=RP6723P3

MAKE_BASE=TRUE

GPU_DVOD_R<1>

=RP6723P2

MAKE_BASE=TRUE

GPU_DVOD_R<2>

=RP6723P1

MAKE_BASE=TRUE

GPU_DVOD_R<12>

=RP6722P4

MAKE_BASE=TRUE

GPU_DVOD_R<13>

=RP6722P3

MAKE_BASE=TRUE

GPU_DVOD_R<5>

=RP6722P2

MAKE_BASE=TRUE

GPU_DVOD_R<3>

=RP6722P1

MAKE_BASE=TRUE

GPU_DVO_HSYNC_R

=RP6721P4

MAKE_BASE=TRUE

GPU_DVOD_R<10>

=RP6721P3

MAKE_BASE=TRUE

GPU_DVOD_R<9>

=RP6721P2

=RP6723P5

MAKE_BASE=TRUE

GPU_DVOD<14>

=RP6723P6

MAKE_BASE=TRUE

GPU_DVOD<0>

=RP6723P7

MAKE_BASE=TRUE

GPU_DVOD<1>

=RP6723P8

MAKE_BASE=TRUE

GPU_DVOD<2>

=RP6722P5

MAKE_BASE=TRUE

GPU_DVOD<12>

=RP6722P6

MAKE_BASE=TRUE

GPU_DVOD<13>

=RP6722P7

MAKE_BASE=TRUE

GPU_DVOD<5>

=RP6722P8

MAKE_BASE=TRUE

GPU_DVOD<3>

=RP6721P5

MAKE_BASE=TRUE

GPU_DVO_HSYNC

=RP6721P6

MAKE_BASE=TRUE

GPU_DVOD<10>

=RP6721P7

MAKE_BASE=TRUE

GPU_DVOD<9>

MAKE_BASE=TRUE

GPU_DVOD_R<11>

=RP6721P1

MAKE_BASE=TRUE

GPU_DVOD_R<6>

=RP6720P4

MAKE_BASE=TRUE

GPU_DVOD_R<4>

=RP6720P2

MAKE_BASE=TRUE

GPU_DVOD_R<7>

=RP6720P3

MAKE_BASE=TRUE

GPU_DVOD_R<16>

=RP6720P1

=RP6720P5

MAKE_BASE=TRUE

GPU_DVOD<6>

=RP6721P8

MAKE_BASE=TRUE

GPU_DVOD<11>

=RP6720P7

MAKE_BASE=TRUE

GPU_DVOD<4>

=RP6720P6

MAKE_BASE=TRUE

GPU_DVOD<7>

=RP6720P8

MAKE_BASE=TRUE

GPU_DVOD<16>

=RP6823P4

=RP6823P2
=RP6823P3

=RP6823P1

MAKE_BASE=TRUE

GPU_DVOD_R<18>

MAKE_BASE=TRUE

GPU_DVOD_R<23>

MAKE_BASE=TRUE

GPU_DVOD_R<22>

MAKE_BASE=TRUE

GPU_DVOD_R<20>

UATA_DA<1>

MAKE_BASE=TRUE

UATA_DD<1>

MAKE_BASE=TRUE

UATA_DD<0>

MAKE_BASE=TRUE

UATA_DD<13>

MAKE_BASE=TRUE

UATA_DA<0>

MAKE_BASE=TRUE

UATA_DD<10>

MAKE_BASE=TRUE

UATA_DA<2>

MAKE_BASE=TRUE

UATA_DD<8>

MAKE_BASE=TRUE

UATA_DD<5>

MAKE_BASE=TRUE

UATA_DD<6>

MAKE_BASE=TRUE

UATA_DD<4>

MAKE_BASE=TRUE

UATA_DD<9>

MAKE_BASE=TRUE

=RP8153P6

=RP8153P8
=RP8153P7

=RP8152P5

=RP8152P6

=RP8152P7

=RP8152P8

=RP8153P2
=RP8153P3

=RP8153P1

=RP8152P3
=RP8152P4

=RP8152P1
=RP8152P2

=RP8154P5

=RP8154P6

=RP8154P7

=RP8154P8

=RP8153P5

=RP8154P4

=RP8154P2
=RP8154P3

=RP8154P1

=RP8153P4

UATA_DA_R<1>

MAKE_BASE=TRUE

UATA_DD_R<0>

MAKE_BASE=TRUE

UATA_DD_R<1>

MAKE_BASE=TRUE

UATA_DD_R<13>

MAKE_BASE=TRUE

UATA_DA_R<0>

MAKE_BASE=TRUE

UATA_DD_R<8>

MAKE_BASE=TRUE

UATA_DD_R<10>

MAKE_BASE=TRUE

UATA_DA_R<2>

MAKE_BASE=TRUE

UATA_DD_R<6>

MAKE_BASE=TRUE

UATA_DD_R<5>

MAKE_BASE=TRUE

UATA_DD_R<9>

MAKE_BASE=TRUE

UATA_DD_R<4>

MAKE_BASE=TRUE

=RP3513P2
=RP3513P3

=RP3512P3
=RP3512P4

=RP3512P1
=RP3512P2

=RP3514P1

=RP3513P4

=RP3514P2
=RP3514P3

MAXBUS_CPU1_DBG_L

MAKE_BASE=TRUE

MAXBUS_ARTRY_L

MAKE_BASE=TRUE

MAXBUS_AACK_L

MAKE_BASE=TRUE

MAXBUS_CPU0_DRDY_L

MAKE_BASE=TRUE

MAXBUS_CPU1_DRDY_L

MAKE_BASE=TRUE

MAXBUS_CPU0_INT_L

MAKE_BASE=TRUE

MAXBUS_CPU1_INT_L

MAKE_BASE=TRUE

MAXBUS_CPU1_BR_L

MAKE_BASE=TRUE

MAXBUS_TA_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

I2S1_MCLK

I2S1_SB_TO_DEV_DTO

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2S1_SYNC

MAKE_BASE=TRUE

I2S1_BITCLK

MAKE_BASE=TRUE

I2S0_SYNC

MAKE_BASE=TRUE

I2S0_MCLK

MAKE_BASE=TRUE

I2S0_BITCLK

I2S0_SB_TO_DEV_DTO

MAKE_BASE=TRUE

=RP1151P5

=RP1151P6

=RP1151P8
=RP1151P7

=RP1150P5

=RP1150P6

=RP1150P8
=RP1150P7

=RP1151P4

=RP1151P3

=RP1151P2

=RP1151P1

=RP1150P4

=RP1150P3

=RP1150P2

=RP1150P1

MAKE_BASE=TRUE

I2S1_BITCLK_R

MAKE_BASE=TRUE

I2S1_MCLK_R

I2S1_SB_TO_DEV_DTO_R

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2S1_SYNC_R

MAKE_BASE=TRUE

I2S0_SYNC_R

MAKE_BASE=TRUE

I2S0_MCLK_R

MAKE_BASE=TRUE

I2S0_BITCLK_R

I2S0_SB_TO_DEV_DTO_R

MAKE_BASE=TRUE

MAXBUS_CPU0_BR_L

MAKE_BASE=TRUE

MAXBUS_CPU0_HIT_L

MAKE_BASE=TRUE

MAXBUS_CPU1_HIT_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAXBUS_CPU0_BG_L

MAXBUS_CPU1_BG_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAXBUS_TBEN_I2

MAXBUS_CPU0_DBG_L

MAKE_BASE=TRUE

MAXBUS_TS_L

MAKE_BASE=TRUE

=RP3511P1

=RP3510P2

=RP3510P4

=RP3510P3

=RP3510P1

=RP3511P4

=RP3511P3

=RP3511P2

=RP7251P2

PCI_AIRPORT_REQ_L

MAKE_BASE=TRUE

=RP7251P1

PCI_CBUS_REQ_L

MAKE_BASE=TRUE

=RP7251P3

PCI_CBUS_GNT_L

MAKE_BASE=TRUE

=RP7251P4

PCI_FRAME_L

MAKE_BASE=TRUE

=RP9211P5

=RP9211P6

=RP9211P7

=RP9211P8

=RP9210P5

=RP9210P6

=RP9210P7

=RP9210P8

USB2_I2_P<1>

MAKE_BASE=TRUE

USB2_I2_N<1>

MAKE_BASE=TRUE

USB2_I2_N<3>

MAKE_BASE=TRUE

USB2_I2_P<3>

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_P

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_N

MAKE_BASE=TRUE

USB_I2_BT_N

MAKE_BASE=TRUE

USB_I2_BT_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_P

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_N

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_N

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_P

MAKE_BASE=TRUE

USB_NEC_TPAD_P

MAKE_BASE=TRUE

USB_NEC_TPAD_N

MAKE_BASE=TRUE

USB_NEC_BT_N

MAKE_BASE=TRUE

USB_NEC_BT_P

=RP9300P8
=RP9300P7
=RP9300P6
=RP9300P5

=RP9301P8
=RP9301P7
=RP9301P6
=RP9301P5

MAKE_BASE=TRUE

FW_D_R<4>

MAKE_BASE=TRUE

FW_D_R<2>

MAKE_BASE=TRUE

FW_D_R<3>

MAKE_BASE=TRUE

FW_D_R<0>

MAKE_BASE=TRUE

FW_D_R<6>

MAKE_BASE=TRUE

FW_D_R<1>

MAKE_BASE=TRUE

FW_D_R<5>

=RP9101P2
=RP9101P3
=RP9101P4

=RP9100P3
=RP9100P4

=RP9101P1

=RP9101P7
=RP9101P6
=RP9101P5

=RP9100P5

=RP9100P6

=RP9101P8

=RP9100P1
=RP9100P2

=RP9100P8
=RP9100P7

FW_D<7>

MAKE_BASE=TRUE

FW_D<3>

MAKE_BASE=TRUE

FW_D<2>

MAKE_BASE=TRUE

FW_D<4>

MAKE_BASE=TRUE

FW_D<6>

MAKE_BASE=TRUE

FW_D<0>

MAKE_BASE=TRUE

FW_D<1>

MAKE_BASE=TRUE

FW_D<5>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAXBUS_TEA_L

MAKE_BASE=TRUE

FW_D_R<7>

62

62

62

62

64

64

64

64

64

64

64

64

61

61

61

64

64

64

64

64

64

64

64

64

64

64

64

61

63

63

63

63

63

63

63

63

55

55

55

44

44

44

44

44

44

44

44

60

60

60

55

53 63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

33

33

33

34

33

74

74

74

74

33

33

33

33

33

60

11

68

68

68

68

68

68

68

69

69

69

69

69

69

69

69

33

68

7

7

7

7

7

7

7

7

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

55

55

55

54

54

54

54

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55 53

53

53

53

53

53

53

53

11

11

11

11 72

72

72

72

55

55

55

55

55

55

55

55

43

43

43

43

43

43

43

43

43

43

43

43

43

43

43

43

59

59

59

59

11

59

59

59

53 54

53 54

53 54

53 54

53 54

53 54

53 54

53 54

53 54

53 54

53 54

54 55

54 54

54 54

54 54

54 55

54 55

54 54

54 54

54 54

54 54

54 54

53 54

53 54

53 54

53 54

53 54

54 54

54 54

54 54

54 54

54 55

55

55

55

55

2

53

53

53

7

7

7

7

7

7

7

7

7

7

7

7

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

2

2

63

63

2

2

2

63

63

63

63

63

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

30

30

30

30

7

7

7

7

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

22

22

22

22

22

22

22

22

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

59 11

59 11

59 11

59 59

72

72

72

72

72

72

72

72

72

72

72

72

11

11

11

11

11

11

11

11

11

11

2

11

73

73

73

73

73

73

73

73

9

9

9

9

9

9

9

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

9

9

9

9

9

9

9

9

32

9

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LT USB RT USB

BATT

BACKUP

SCCA

ALS

CPU FANGPU FAN

SYSTEM

of left USB connector.

of right USB connector.

of ALS connector.

Place within 25 mm
of debug connector.

Place within 25 mm
of battery connector.

Place within 25 mm

Place within 25 mm

Place within 25 mm

Place within 25 mm
of fan connector.

of fan connector.

Place within 25 mm

Place within 25 mm
of TPAD connector.

of power supply.

Place within 50 mm

Place 2 TPs @ connector

Place 5-10 GND TPs.

Enhanced MAC-1 Test Coverage

Functional test points use a P6 pad placed on bottom side.

Place within 50 mm

of audio connector.

Place within 25 mm

of inverter connector.

Place within 25 mm

of LVDS connector.

Place within 25 mm

POWER

LVDSUATA

INVERTER

AUDIO

of ODD/HDD connector.

I1

I10

I100

I101

I102

I104

I105
I106

I107
I108

I109

I11

I110
I111

I112

I113

I114

I115

I116

I117
I118

I119

I12

I120

I121

I13
I14

I15

I16

I17

I18

I19

I2

I20

I21

I22

I23

I24

I25

I29

I3

I30

I31

I32

I33

I34

I35

I36

I37

I38

I39

I4

I40

I41
I42

I43

I44

I45

I46

I47

I48

I49

I5

I50

I51

I52

I53

I55

I56

I57
I58

I59

I6

I60

I61

I62

I63

I64
I65

I66

I68

I69

I7

I70

I71

I72

I73

I74

I75

I76

I77

I78

I79

I8

I80

I81
I82

I83

I84
I85

I86

I87

I88

I89

I9

I90

I91

I96

I97

I98

Functional Test Points

115

03

051-6929

7

SYNC_MASTER=N/A

SYNC_DATE=N/A

FUNC_TEST=YES

GND_AUDIO_PGND

GND_AUDIO_AGND

FUNC_TEST=YES

AUDIO_GPIO_11

FUNC_TEST=YES

AUDIO_EXT_MCLK_SEL

FUNC_TEST=YES

AUDIO_I2S_DTIB_SEL

FUNC_TEST=YES

AUDIO_LI_OPTICAL_PLUG_L

FUNC_TEST=YES

AUDIO_LO_OPTICAL_PLUG_L

FUNC_TEST=YES

FUNC_TEST=YES

AUDIO_LI_DET_L

FUNC_TEST=YES

AUDIO_LO_DET_L

FUNC_TEST=YES

AUDIO_SPDIFRX_RESET_L

FUNC_TEST=YES

AUDIO_CODEC_RESET_L

FUNC_TEST=YES

AUDIO_SPKR_MUTE_L

FUNC_TEST=YES

AUDIO_LO_MUTE_L

FUNC_TEST=YES

I2S0_DEV_TO_SB_DTI

FUNC_TEST=YES

I2S0_SB_TO_DEV_DTO

FUNC_TEST=YES

I2S0_SYNC

FUNC_TEST=YES

I2S0_BITCLK

FUNC_TEST=YES

I2S0_MCLK

FUNC_TEST=YES

=I2C_AUDIO_SDA

FUNC_TEST=YES

=I2C_AUDIO_SCL

FUNC_TEST=YES

=PP3V3_RUN_AUDIO

PP3V3_PWRON_AUDIO_AVDD

FUNC_TEST=YES

PP5V_PWRON_AUDIO_AVDD

FUNC_TEST=YES

PP5V_PWRON_AUDIO_PVDD

FUNC_TEST=YES

UATA_INTRQ

FUNC_TEST=YES

UATA_STOP

FUNC_TEST=YES

UATA_RESET_L

FUNC_TEST=YES

UATA_HSTROBE

FUNC_TEST=YES

UATA_CS1_L

FUNC_TEST=YES

UATA_CS0_L

FUNC_TEST=YES

UATA_DA<2..0>

FUNC_TEST=YES

UATA_DSTROBE

FUNC_TEST=YES

UATA_DMACK_L

FUNC_TEST=YES

UATA_DMARQ

FUNC_TEST=YES

UATA_DD<15..0>

FUNC_TEST=YES

FUNC_TEST=YES

PP3V3R5V_RUN_HDD_LOGIC

FUNC_TEST=YES

=PP5V_RUN_ODD

FUNC_TEST=YES

=PP5V_RUN_HDD

FUNC_TEST=YES

GND_INVERTER

FUNC_TEST=YES

BRIGHT_PWM

FUNC_TEST=YES

PP5V_INV_SW

FUNC_TEST=YES

PPBUS_INVERTER

FUNC_TEST=YES

PP3V3_LCD_CONN

FUNC_TEST=YES

=PP3V3_DDC_LCD

FUNC_TEST=YES

LVDS_DDC_DATA

FUNC_TEST=YES

LVDS_DDC_CLK

CLKLVDS_L_N

FUNC_TEST=YES

CLKLVDS_L_P

FUNC_TEST=YES

FUNC_TEST=YES

LVDS_L2_P

FUNC_TEST=YES

LVDS_L2_N

FUNC_TEST=YES

LVDS_L1_N

FUNC_TEST=YES

LVDS_L1_P

FUNC_TEST=YES

LVDS_L0_N

FUNC_TEST=YES

CLKLVDS_U_N

FUNC_TEST=YES

LVDS_L0_P

FUNC_TEST=YES

CLKLVDS_U_P

FUNC_TEST=YES

LVDS_U2_N

FUNC_TEST=YES

LVDS_U2_P

FUNC_TEST=YES

LVDS_U1_N

FUNC_TEST=YES

LVDS_U1_P

FUNC_TEST=YES

LVDS_U0_N

FUNC_TEST=YES

LVDS_U0_P

=FTP_GND

FUNC_TEST=YES

PP3V3_ALL

FUNC_TEST=YES

PP5V_RUN

FUNC_TEST=YES

PP3V3_PWRON

FUNC_TEST=YES

PP5V_PWRON

FUNC_TEST=YES

PP2V5_PWRON

FUNC_TEST=YES

PP1V8_PWRON

FUNC_TEST=YES

PPVCORE_RUN_GPU

FUNC_TEST=YES

PPVCORE_RUN_CPU

FUNC_TEST=YES

PP12V8_ALL_PBUSB

FUNC_TEST=YES

FUNC_TEST=YES

PP24V_ALL_PBUSA

FUNC_TEST=YES

PP24V_ADAPTER

FUNC_TEST=YES

PP5V_TPAD_F

FUNC_TEST=YES

USB_TPAD_P

FUNC_TEST=YES

USB_TPAD_N

FUNC_TEST=YES

PP3V3_PWRON_DS1775_R

FUNC_TEST=YES

SYS_OVERTEMP_L

FUNC_TEST=YES

PP3V3_ALL_HALL_EFFECT_R

FUNC_TEST=YES

SYS_LID_OPEN_F

FUNC_TEST=YES

SYS_POWER_BUTTON_L_F
=FTP_SLEEP_LED

FUNC_TEST=YES
FUNC_TEST=YES

SYS_CHARGE_LED_L

FUNC_TEST=YES

SYS_ADAPTER_ANALOG_AC_DET

FUNC_TEST=YES

KBDLED_ANODE

FUNC_TEST=YES

KBDLED_RETURN

FUNC_TEST=YES

=I2C_DS1775_SDA

FUNC_TEST=YES

=I2C_DS1775_SCL

FUNC_TEST=YES

=PP5V_FAN1_PWR

FAN1_PWM

FUNC_TEST=YES

FUNC_TEST=YES

FAN1_TACH

=FTP_GND

FUNC_TEST=YES

FUNC_TEST=YES

=PP5V_FAN2_PWR

FUNC_TEST=YES

FAN2_TACH

FUNC_TEST=YES

FAN2_PWM

FUNC_TEST=YES

=FTP_GND

FUNC_TEST=YES

=PP3V3_PWRON_LEFT_ALS

FUNC_TEST=YES

ALS_0_OUT

FUNC_TEST=YES

ALS_GAIN_BOOST

FUNC_TEST=YES

SCCA_RXD

FUNC_TEST=YES

SCCA_TXD_L

FUNC_TEST=YES

=PPVIO_BU_BATT

FUNC_TEST=YES

=PPVOUT_BU_BATT

=PP5V_PWRON_RIGHT_USB

FUNC_TEST=YES

USB2_RIGHT_PORT_P

FUNC_TEST=YES

USB2_RIGHT_PORT_N

FUNC_TEST=YES

FUNC_TEST=YES

=PP5V_PWRON_LEFT_USB

FUNC_TEST=YES

USB2_LEFT_PORT_N

FUNC_TEST=YES

USB2_LEFT_PORT_P

64

64

64

30

31

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

64

64

64

64

64

63

63

64

64

64

63

64

64

56

56

56

56

56

56

56

56

56

56

56

56

56

56

56

56

56

56

56

10

30

30

25

74

74

30

30

30

30

31

31

31

10

31

31

31

10

31

31

28

24

24

31

31

31

31

31

74

74

74

74

74

22

22

22

22

22

22

22

22

22

22

22

22

6

6

6

6

8

8

10

74

74

74

63

63

63

63

63

6

6

63

63

63

6

64

10

10

56

56

56

56

56

10

51

51

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

7

10

10

10

10

10

10

10

10

10

10

10 30

11

11

30

11

30

30

30

30

24

12

28

28

8

8

10

27

27

7

10

27

27

7

10

25

25

22

22

10

10

10

11

11

10

11

11

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U2100

JA000U2100

SPDIF

Codec

Audio Board

(Write: 0x8C Read: 0x8D)
(Write: 0x22 Read: 0x23)

(MASTER)

U5700

GPU I2C Bus

EXT TMDS/S

EXT TMDS/M

U6700

U6800

(Write: 0x70 Read: 0x71)

(Write: 0x72 Read: 0x73)

PMU SMBus

PMU unstead. One ADT7467 connects to NB

NOTE: Neither option is necessary when

PMU

Signal aliases required by this page:

- GOV_I2C / GOV_I2C_BYPASS

I2C bus 1 to resolve address conflict.

Selects whether MMM MCU is powered all

BOM options provided by this page:

Power aliases required by this page:

MMM_MCU_PMU BOM option is selected.

(NONE)

it can be monitored by in shutdown.

ALL moves the MCU to the PMU I2C bus so

the time or only when the system is on.

Most devices are connected directly to

Allows bypassing Governator I2C bus.

- MMM_PWR_ALL / MMM_PWR_PWRON

J790

Battery Conn

(Write: 0x16 Read: 0x17)

(MASTER)

PMU

U1300

(NONE)

PMU I2C Bus

U1300

(MASTER)

(MASTER)

SouthBridge I2C Bus

J5000A / J5000B

DIMMs

(Write: 0xA0 / 0xA2,
Read: 0xA1 / 0xA3)

(MASTER)

I2

NorthBridge I2C Bus

I2

GPU

Page Notes

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

DIFFERENTIAL_PAIR

U3000

ADT7467

(Write: 0x5C Read: 0x5D)

DS1775

On Trackpad Flex

(Write: 0x92 Read: 0x93)

7.15K

1%

402

MF-LF

1/16W

2

1

R0851

402

MF-LF

1/16W

1%

7.15K

2

1

R0850

402

MF-LF

1/16W

5%

1K

2

1

R0821

1/16W
MF-LF

1K

5%

402

2

1

R0820

402

1K

MF-LF

1/16W

5%

2

1

R0843

402

MF-LF

1/16W

5%

1K

2

1

R0842

5%
1/16W
MF-LF

1K

402

2

1

R0841

1K

5%
1/16W
MF-LF

402

2

1

R0840

2.0K

5%
MF-LF

402

1/16W

2

1

R0830

5%

2.0K

402

MF-LF

1/16W

2

1

R0831

051-6929

115

8

03

I2C Connections

SYNC_MASTER=N/A

SYNC_DATE=N/A

=I2C_DS1775_SDA

=I2C_DS1775_SCL

=I2C_ADT7467_SDA

=I2C_ADT7467_SCL

MAKE_BASE=TRUE

I2C_I2_NB_SCL

MAKE_BASE=TRUE

I2C_I2_NB_SDA

I2C I2C

I2C_I2_SB_SCL

I2C I2C

I2C_I2_SB_SDA

I2C I2C

I2C_GPU_TMDS_SDA

I2CI2C

I2C_GPU_TMDS_SCL

I2C I2C

I2C_I2_NB_SCL

I2C_NB

I2C I2C

I2C_PMU_SMB_SDA

I2C_PMU_SDA

I2C I2C

I2C_PMU_SCL

I2C I2C

I2CI2C

I2C_PMU_SMB_SCL

I2C I2C

I2C_I2_NB_SDA

I2C_NB

=I2C_I2_NB_SDA

=I2C_SODIMM_SDA

=I2C_I2_NB_SCL

=I2C_SODIMM_SCL

=PPI2C_I2_NB

=PPI2C_I2_SB

=I2C_I2_SB_SDA

=I2C_I2_SB_SCL

=I2C_PMU_SMB_SDA

=I2C_BATT_SDA

=I2C_PMU_SDA

=I2C_PMU_SCL

=I2C_PMU_SMB_SCL

=PPI2C_SYS1

=I2C_BATT_SCL

=PPI2C_SYS0

MAKE_BASE=TRUE

I2C_PMU_SCL

MAKE_BASE=TRUE

I2C_PMU_SDA

I2C_PMU_SMB_SCL

MAKE_BASE=TRUE

I2C_PMU_SMB_SDA

MAKE_BASE=TRUE

=PPI2C_GPU

I2C_GPU_TMDS_SCL

MAKE_BASE=TRUE

I2C_GPU_TMDS_SDA

MAKE_BASE=TRUE

=I2C_SI_M_SCL

=I2C_SI_M_SDA

=I2C_SI_S_SCL

=I2C_SI_S_SDA

=I2C_GPU_TMDS_SCL

=I2C_GPU_TMDS_SDA

I2C_I2_SB_SCL

MAKE_BASE=TRUE

I2C_I2_SB_SDA

MAKE_BASE=TRUE

=I2C_AUDIO_SCL

=I2C_AUDIO_SDA

30

30

41

41

74

74

7

7

27

27

8

8

8

8

8

8

8

8

8

8

8

8

22 40

22 40

10

10

22

22

25 12

25

25

25

10

12

10

8

8

8

8

10

8

8

54

54

55

55

51

51

8

8

7

7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MAXBUS

Nets not requiring TPs due to JTAG

PMU (BOOTBANGER)

ENET

FIREWIRE

VESTA

CPU0

I2

I100
I101

I102

I103

SM-LF

1/16W

10K

5%

8

1

RP0990

SM-LF

10K

1/16W

5%

6

3

RP0990

1K

5%
1/16W
MF-LF

402

2

1

R0990

SM-LF

10K

1/16W

5%

2

7

RP0990

1/16W

402

MF-LF

5%

10K

2

1

R0950

MF-LF

5%

1/16W

402

10K

2

1

R0981

5%
1/16W
MF-LF

10K

402

2

1

R0982

402

MF-LF

1/16W

5%

10K

2

1

R0983

200

5%
1/16W
MF-LF

402

2

1

R0984

NO STUFF

10K

402

MF-LF

1/16W

5%

2

1

R0980

I76
I77

I78
I79

I80

I81
I82

I83

I85

I86
I87

I88
I89

I90

I91

I92

I93

I94
I95

I96

I97
I98

I99

03

051-6929

9

115

JTAG Connections

SYNC_DATE=N/A

SYNC_MASTER=N/A

JTAG_I2_TDI

MAKE_BASE=TRUE

=JTAG_I2_TDI

=JTAG_I2_TCK

=JTAG_I2_TRST_L

=JTAG_I2_TMS

=JTAG_I2_TDO

TP_JTAG_I2_TDO

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_ASIC_TRST_L

MAKE_BASE=TRUE

JTAG_ASIC_TMS

MAKE_BASE=TRUE

JTAG_ASIC_TCK

=PP3V3_PWRON_JTAG_ASIC

=JTAG_BBANGER_TCK

=JTAG_BBANGER_TRST_L

=JTAG_BBANGER_TMS

=JTAG_BBANGER_TDI

=JTAG_CPU0_TDI

=JTAG_CPU0_TCK

=JTAG_CPU0_TRST_L

=JTAG_CPU0_TMS

=JTAG_CPU0_TDO

TP_JTAG_CPU_TDO

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_CPU_TMS

MAKE_BASE=TRUE

JTAG_CPU_TCK

MAKE_BASE=TRUE

JTAG_CPU_TRST_L

MAKE_BASE=TRUE

JTAG_CPU_TDI

=PPJTAG_CPU

=JTAG_VESTA_TDI

=JTAG_VESTA_TRST_L
=JTAG_VESTA_TCK

MAKE_BASE=TRUE

TP_JTAG_VESTA_TDI TP_JTAG_VESTA_TDO

MAKE_BASE=TRUE

=JTAG_VESTA_TDO

=JTAG_VESTA_TMS

MAKE_BASE=TRUE

TP_JTAG_VESTA_TCK

MAKE_BASE=TRUE

JTAG_VESTA_TRST_L

MAKE_BASE=TRUE

TP_JTAG_VESTA_TMS

MAXBUS_WT_L

NO_TEST=YES

MAXBUS_GBL_L

NO_TEST=YES

MAXBUS_TBST_L

NO_TEST=YES

MAXBUS_CI_L

NO_TEST=YES

MAXBUS_DATA<63..0>

NO_TEST=YES

MAXBUS_ADDR<31..0>

NO_TEST=YES

MAXBUS_TSIZ<2..0>

NO_TEST=YES

MAXBUS_TT<4..0>

NO_TEST=YES

MAXBUS_DTI<2..0>

NO_TEST=YES

NO_TEST=YES

ENET_CRS

NO_TEST=YES

ENET_RX_ER

NO_TEST=YES

ENET_TX_EN

NO_TEST=YES

ENET_TX_ER

NO_TEST=YES

ENET_RXD<7..0>

NO_TEST=YES

FW_D<7..0>

NO_TEST=YES

FW_D_R<7..0>

NO_TEST=YES

FW_LPS_R

NO_TEST=YES

FW_LREQ

ENET_MDIO

NO_TEST=YES

ENET_MDC

NO_TEST=YES

ENET_RX_DV

NO_TEST=YES

ENET_COL

NO_TEST=YES

FW_LPS

NO_TEST=YES

FW_LREQ_R

NO_TEST=YES

ENET_TXD<7..0>

NO_TEST=YES

FW_CTL_R<1..0>

NO_TEST=YES

FW_CTL<1..0>

NO_TEST=YES

33

33

33

33

33

32

33

33

33

33

65

65

65

69

68

71

71

65

65

65

65

71

71

71

71

22

22

22

22

22

10

25

25

25

25

34

34

34

34

34

10

18

18

18

18

18

32

32

32

32

21

32

32

32

32

11

11

11

11

11

6

6

68

69

11

11

11

11

69

68

11

68

69

JUMPER

JUMPER

JUMPER

JUMPER

JUMPER

JUMPER

JUMPER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

805

MF-LF

1/8W

5%

0

21

R1018

0

5%

1/8W

MF-LF

805

21

R1015

805

MF-LF

1/8W

5%

0

21

R1025

0

5%

1/8W

MF-LF

805

21

R1033

SM

21

XW1013

OPEN

21

XW1050

OPEN

21

XW1033

OPEN

21

XW1025

OPEN

21

XW1018

OPEN

21

XW1015

OPEN

21

XW1012

OPEN

21

XW1017

SM

21

XW1019

SYNC_MASTER=N/A

SYNC_DATE=N/A

051-6929

03

115

10

Power Synonyms

MAKE_BASE=TRUE

PP3V3_PWRON

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP3V3_PWRON_USB2

=PP3V3_PWRON_I2_MAXBUS

=PPVIO_PCI_USB2

=PP3V3_RUN_AUDIO

MAKE_BASE=TRUE

PP3V3_ALL

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP3V3_ALL_DEBUG

=PP3V3_ALL_BATT0_DET

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm

PP3V3_VESTA

MAKE_BASE=TRUE

=PP3V3_ENETFW

=PP3V3_FW

MIN_NECK_WIDTH=0.15 mm

MAKE_BASE=TRUE

PP5V_TPAD

VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PP1V8_PWRON

=FTP_GND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MAKE_BASE=TRUE

PP5V_RUN

PP1V5_PWRON_REG

VOLTAGE=1.5V

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PP1V8_PWRON_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE
VOLTAGE=1.8V

PP2V5_PWRON_REG

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

=PP1V5_I2_AGP

=PP1V5_PWRON_RUNFET

=PP1V8_PWRON_I2_RAM

=PP1V8_PWRON_DDR2

=PP1V8_PWRON_RUNFET

=PP2V5_ENET
=PPVIN_PWRON_I2PLLVDD

=PP2V5_PWRON_RUNFET

=PP1V5_PWRON_REG

VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PP1V5_PWRON

=PP1V8_PWRON_REG

=PP2V5_PWRON_REG

MAKE_BASE=TRUE

PP2V5_PWRON

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm

=PPVCORE_CPU_ADT7467

MIN_NECK_WIDTH=0.15 mm

VOLTAGE=1.3V
MIN_LINE_WIDTH=0.25 mm

MAKE_BASE=TRUE

PPVCORE_CPU_ADT7467

=PPFW_P3V3VESTA

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=33V

MAKE_BASE=TRUE

PPFW_CABLE_POWER

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=12.8V
MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PP12V8_ALL_PBUSB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=24V

MAKE_BASE=TRUE

PP24V_ALL_PBUSA

=PPBUS_DVI_PWRSW

VOLTAGE=12.8V

PPBUS_DVI_PWRSW

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.25 mm

MAKE_BASE=TRUE

=PP24V_PBUSA_HOLDUP_CAPS

=PP5V_PWRON_LEFT_USB

=PP5V_PWRON_CPUVCORE_VDD

=PP5V_PWRON_CPUVCORE_PWRSEQ

=PP5V_PWRON_GPUVCORE_PWRMSR

=PP5V_PWRON_LTC1778_GPU_EXTVCC

=PP5V_PWRON_TPS2211

=PP5V_PWRON_MAX1715_VDD

=PP5V_PWRON_PWRSEQ

=PP1V5R1V8_I2_MAXBUS

=PP1V5R1V8_MAXBUS

=PP1V5_RUN_RUNFET

MAKE_BASE=TRUE

PP1V5_RUN

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.5V

=PP1V5_GPU

=PPVBATT_BATT_VSNS

PPVBATT_BATT_CHRG_VSNS

MAKE_BASE=TRUE
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

=PPVIN_BATT_CHRG_VSNS

=PP24V_ADAPTER_CONN

=PPVBATT_ISNS_N

=PP24V_ADAPTER_PMU_SUPPLY

=PP24V_ADAPTER_RAW

=PPVBATT_BATTERY_PMU_SUPPLY

=PPVBATT_BATT

PPVBATT_BATT

MAKE_BASE=TRUE
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PP24V_ADAPTER

MAKE_BASE=TRUE
VOLTAGE=24V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PPI2C_GPU

=PP3V3_GPU

=PP3V3_PCI

=PP3V3_DDC_LCD

=PP3V3_DDC_DVI

=PP3V3_ALL_PWRSEQ

=PP3V3_PWRON_INVERTER

PPVCORE_PWRON_I2_REG

VOLTAGE=1.7V

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

=PPVCORE_PWRON_I2_REG

PPVCORE_PWRON_I2

VOLTAGE=1.7V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

=PPVCORE_PWRON_I2

=PP1V05R1V3_GPU_VCORE

=PPVCORE_GPU_REG

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PPVCORE_GPU_REG

VOLTAGE=1.3V

=PPFW_PORT2

=PPVCORE_CPU_REG

=PPVCORE_CPU0

=PP3V3_PWRON_JTAG_ASIC

=PPI2C_I2_NB
=PPI2C_I2_SB
=PPI2C_SYS1

=PP3V3_ADT7467

=PP3V3_PWRON_BT

=PP3V3_PWRON_CPUVCORE_OFFSET

=PP3V3_PWRON_CPUVCORE_VID

=PP3V3_PWRON_LCD

=PP3V3_PWRON_LEFT_ALS

=PP3V3_PWRON_LTC3412

=PP3V3_PWRON_MMM

=PP3V3_PWRON_MODEM

=PP3V3_PWRON_PMU

=PP3V3_PWRON_RUNFET

=PP3V3_PWRON_DS1775

=PP3V3_PWRON_TPS2211

=PP3V3_PWRON_VGASYNC

=PP3V3_PWRON_AUDIO_AVDD

=PP3V3_PWRON_REG
PP3V3_PWRON_REG

VOLTAGE=3.3V

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PP5V_PWRON_REG

MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP5V_PWRON_REG

=PP3V3_ALL_PMU

=PP3V3_ALL_HALL_EFFECT

=PP5V_RUN_HDDFET

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

MAKE_BASE=TRUE

PP5V_RUN_HDD

=PP5V_RUN_HDD

=PP5V_FAN1_PWR

=PPVIN_GPU_LVDDR_LDO

PP3V3_GPU

MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP3V3_GPU_PWRSEQ

=PP2V5_GPU

=PP2V5_GPU_PVDD

=PP2V5_GPU_A2VDD

=PP2V5_GPU_PWRSEQ

=PP2V5_GPU_LVDS_IO

PP2V5_GPU

MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP3V3_RUN_SI

=PPI2C_SYS0

=PP3V3_GPU =PP3V3_AGP

=PP3V3_GPU_VDDR3

=PP1V5_GPU_VDD15

=PP1V5_AGP=PP1V5_GPU

=PP4V85_ALL_VREG

PP4V85_ALL

MAKE_BASE=TRUE
VOLTAGE=4.85V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

=PP4V85_ALL_A29_DET

=PPVIN_ALL_LTC1625
=PPVIN_ALL_BATT_CHGR
=PPVIN_ALL_LTC3707

=PP12V8_PBUS_PMU_SUPPLY
=PPVIN_ALL_MAX1715

=PP12V8_PBUSB_HOLDUP_CAPS

=PPVIN_LTC1778_GPU

=PPVIN_CPUVCORE_MAX1717

=PPBUS_FWPWRSW

=PPBUS_INVERTER

=PPVBATT_BATT_PBUSA

=PP14VR24V_ALL_PBUS_A

=PPVOUT_BU_BATT

=PPVBATT_BATT_PBUSB

=PP12V8_LTC1625_VREG

=PPVIO_BU_BATT

=PP3V3_VESTA_1V2REG

=PP3V3_VESTA

=PP3V3_VESTA_2V5REG

=PP3V3_VESTA_REG

VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PP2V5_VESTA

VOLTAGE=1.2V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP1V2_VESTA

MAKE_BASE=TRUE

=PP2V5_VESTA
=PP2V5_ENETFW

=PP1V2_VESTA
=PP1V2_ENETFW

=PPFW_PHY_CPS
=PPFW_PORT1

=PP2V5_VESTA_LDO

=PP1V2_VESTA_REG

=PPBUS_FW_FET

=PP3V3_ALL_VREG

=PP3V3_ALL_PBUS_ILIM

=PP3V3_ALL_LTC1625_SW

=PP3V3_ALL_BATT_CHGR

=PP3V3_ALL_A29_DET

=PP3V3_ALL_AC_DETECT

=PPVREF_PMU

=PP5V_PWRON_PMU_SUPPLY

=PP5V_PWRON_LTC1625_EXTVCC

=PP5V_PWRON_RUNFET

=PP5V_PWRON_LTC3707_EXTVCC

=PP5V_RUN_ODD

=PP5V_RUN_FANPWM

=PPBU_RUN_FW

=PP5V_RUN_KEYBRD_LED
=PP5V_RUN_DVI_DDC

=PP5V_RUN_RUNFET

=PP3V3_RUN_RUNFET

=PP2V5_RUN_PCI1510
=PP2V5_GPU

=PP2V5_RUN_RUNFET

=PP3V3_BATT_IMON

MAKE_BASE=TRUE

PP3V3_ALL_PMU_AVCC

=PP3V3_RUN_KEYBRD_LED

=PP3V3_GPU_GPIOS

=PP5V_TPAD

=PP5V_TPAD_FET

VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP2V5_RUN

MAKE_BASE=TRUE

=PP1V8_GPU

=PP1V8_RUN_RUNFET

=PP1V8_GPU_PANEL_IO

=PP1V8_GPU

=PP2V8_GPU_LVDS_IO

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=2.8V
MIN_NECK_WIDTH=0.25 mm

PP2V8_GPU_LVDDR

MAKE_BASE=TRUE

=PP2V8_GPU_LVDDR_LDO

=PPVIN_CPU0_AVDD

=PP5V_FAN2_PWR

=PP1V8_GPU_DVO

=PP3V3_PCI_AIRPORT
=PP3V3_RUN_PCI1510_R
=PP3V3_RUN_HDD
=PP3V3_GPU_CLOCKS
=PP3V3_RUN_FWPORTPWRSW
=PP3V3_RUN_FANTACH

=PPVOUT_CPU0_AVDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.22V

MAKE_BASE=TRUE

PPAVDD_CPU0

=PPAVDD_CPU0

=PP1V5_PWRON_I2PLL_LDO

=PP5V_RUN_PWRSEQ

=PP1V5_PWRON_I2_USBPLL

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2PLL

=PP1V5_PWRON_I2_PLL

=PP3V3_RUN_PWRSEQ

=PPJTAG_CPU

=TPS2211_SHDN_L

=PP5V_PWRON_AUDIO_AVDD
=PP5V_PWRON_AUDIO_PVDD

PP5V_PWRON

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

=PP5V_PWRON_RIGHT_USB
=PP5V_PWRON_SLEEPLED
=PP5V_PWRON_TRACKPAD
=PP5V_PWRON_INVERTER

=PP2V7R5V5_PWRON_I2VCORE

=PP3V3_PWRON_I2_MISC
=PP3V3_PWRON_RT_ALS
=PP3V3_PWRON_VDDSPD
=PP3V3_PCI_ROM
=PP2V5R3V3_PWRON_I2_ENET
=PP3V3_I2_PCISLOTEGPIOS
=PP3V3_PWRON_I2_AGPPCI
=PP3V3_PWRON_I2_IO1

=PP1V5_GPU_PWRSEQ

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PP1V5_GPU

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.38 mm

=PP1V5_GPU_DVO

=PP1V8R2V5_GPU_FB_VIO
=PP1V8_FB_VDD
=PP1V8_FB_VDDQ

=PP1V8_GPU_TPVDD

=PP1V8_GPU_AVDD

PPVCORE_RUN_CPU

MAKE_BASE=TRUE
VOLTAGE=1.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVCORE_RUN_GPU

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE
VOLTAGE=1.3V

=PP1V8_GPU_PWRSEQ
=PP1V8_GPU_MEMVMODE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.8V

MAKE_BASE=TRUE

PP1V8_GPU

=PP3V3_PWRON_I2_IO2
=PP3V3_ENET

=PP1V8_RAM_I2_VREF
=PP1V8_RUN_TBEN_SYNC

VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PP1V8_RUN

=PP3V3_PCI_USB2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_RUN

=PP3V3_PCI_ZDB

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm

GND

34

47

74

7

70

7

41

7

74

33

7

56 31

25

64

31

55

44

44

31

31

66

69

69

64

53

31

31

41

48

50

50

7

73

19

62

7

24

12

69

69

7

7

43

16

38

40

16

67

20

17

16

16

17

7

27

18

7

57

31

7

36

36

45

45

61

16

26

32

21

16 10

12 13

31

12

14

12

14

13

8

10

59

7

57

26

56

20 19

46 45

70

36 35

9

8

8

8

27

60

36

36

56

7

17

29

30

25

15

30

61

57

74

15

15

24

30

15

7

7

52

52

10

51

53

52

47

54

8

10 43

47

46

43 10

14 12

14

13

15

14

16

31

45

36

18

56

13

13

7

13

14

7

18

18

18

18

18

66

18

66

69

70

18

18

18

14

13

14

13

12

12

25

14

14

15

15

7

27

18

28

57

15

15

61

10

17

12

25

28

51

30 15

10 16

47 10

47 52

37

7

47

60

61

64

52

18

27

37 35

20

26

72

19

26

9

61

74

74

7

7

24

15

56

20

22

28

40

58

65

22

19

19

52

47

47

49

49

53

53

7

52

48

19

66

38

21

62

23

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

USB Controller Mux

USB Port Assignments

CPU Clocks

PCI

- I2S0_SYNC(_R)

- I2S0_BITCLK(_R)

I2S0 Series Rs

- I2S0_SB_TO_DEV_DTO(_R)

GPU

- I2S1_MCLK(_R)

- I2S1_BITCLK(_R)

- I2S1_SYNC(_R)

One resistor for each of:

- I2S1_SB_TO_DEV_DTO(_R)

I2S1 Series Rs

MISC

PMU Connections

Vesta Ethernet

- I2S0_MCLK(_R)

One resistor for each of:

I105

I106

I107

I108

402

MF-LF

22

5%

1/16W

MAXBUS_TBEN_SYNC

21

R1130

10

MAXBUS_TBEN_SYNC

1/16W
MF-LF

402

5%

21

R1111

22

5%
1/16W
MF-LF

402

21

R1120

402

MF-LF

5%
1/16W

0

21

R1137

0

5%
1/16W
MF-LF

USB2_I2

402

21

R1165

USB2_NEC

0

5%
1/16W
MF-LF

402

21

R1164

MF-LF

1/16W

5%

0

USB2_NEC

402

21

R1166

USB2_I2

MF-LF

1/16W

5%

0

402

21

R1167

MF-LF

1/16W

5%

0

USB1P1_NEC

402

21

R1174

MF-LF

1/16W

5%

0

USB2_I2

402

21

R1161

MF-LF

1/16W

5%

0

USB2_NEC

402

21

R1160

USB2_NEC

0

5%
1/16W
MF-LF

402

21

R1162

0

5%
1/16W
MF-LF

USB2_I2

402

21

R1163

MF-LF

1/16W

5%

0

USB1P1_NEC

402

21

R1170

USB1P1_I2

MF-LF

1/16W

5%

0

402

21

R1175

USB1P1_NEC

0

5%
1/16W
MF-LF

402

21

R1176

0

5%
1/16W
MF-LF

USB1P1_I2

402

21

R1177

USB1P1_I2

MF-LF

1/16W

5%

0

402

21

R1171

USB1P1_NEC

0

5%
1/16W
MF-LF

402

21

R1172

0

5%
1/16W
MF-LF

USB1P1_I2

402

21

R1173

402

5%
1/16W
MF-LF

0

21

R1135

402

MF-LF

1/16W

5%

0

21

R1136

10

1/16W
MF-LF

402

5%

21

R1110

MF-LF

1/16W

5%

402

22

21

R1140

402

MF-LF

1/16W

5%

100K

2

1

R1185

33

5%

1/16W
SM-LF

5

6

7

8

4

3

2

1

RP1150

SM-LF

1/16W

5%

33

5

6

7

8

4

3

2

1

RP1151

Signal Synonyms

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

03

115

11

USB_I2_BT_N

PCI_SLOTD_GNT_L

PCI_SLOTD_INT_L

=RP1150P6

=ENET_TX_EN

=ENET_TX_ER

=ENET_TXD<7..0>

=ENET_RXD_R<7..0>

MAKE_BASE=TRUE

ENET_RXD<7..0>

=ENET_RX_DV_R

MAKE_BASE=TRUE

ENET_RX_DV

=ENET_RX_ER_R

ENET_RX_ER

MAKE_BASE=TRUE

=ENET_COL_R

ENET_COL

MAKE_BASE=TRUE

=ENET_CRS_R

ENET_CRS

MAKE_BASE=TRUE

=VESTA_CLK125M_GBE_REF

ENET_CLK125M_GBE_REF

MAKE_BASE=TRUE

=VESTA_CLK125M_RX

MAKE_BASE=TRUE

ENET_CLK125M_RX

=VESTA_CLK25M_TX

MAKE_BASE=TRUE

ENET_CLK25M_TX

=VESTA_MDC

ENET_MDC

MAKE_BASE=TRUE

=VESTA_MDIO

MAKE_BASE=TRUE

ENET_MDIO

ENET_TX_EN

MAKE_BASE=TRUE

ENET_TX_EN_R

ENET_TX_ER

MAKE_BASE=TRUE

ENET_TX_ER_R

ENET_TXD<7..0>

MAKE_BASE=TRUE

ENET_TXD_R<7..0>

=VESTA_ENERGYDET

TP_ENET_ENERGYDET

MAKE_BASE=TRUE

USB2_NEC_P<0>

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_P

USB2_NEC_N<0>

MAKE_BASE=TRUE

USB2_NEC_LEFT_PORT_N

USB2_NEC_N<1>

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_N

USB2_NEC_P<1>

MAKE_BASE=TRUE

USB2_NEC_RIGHT_PORT_P

USB2_NEC_P<2>

MAKE_BASE=TRUE

USB_NEC_BT_P

USB2_NEC_N<2>

MAKE_BASE=TRUE

USB_NEC_BT_N

USB2_NEC_P<3>

MAKE_BASE=TRUE

USB_NEC_TPAD_P

USB2_NEC_N<3>

MAKE_BASE=TRUE

USB_NEC_TPAD_N

USB2_I2_P<0>

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_P

USB2_I2_N<0>

MAKE_BASE=TRUE

USB2_I2_LEFT_PORT_N

USB2_I2_N<2>

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_N

USB2_I2_P<2>

MAKE_BASE=TRUE

USB2_I2_RIGHT_PORT_P

USB2_I2_P<4>

MAKE_BASE=TRUE

USB_I2_BT_P

USB2_I2_N<5>

MAKE_BASE=TRUE

USB_I2_TPAD_N

USB2_I2_N<4>

MAKE_BASE=TRUE

USB_I2_BT_N

USB2_I2_P<5>

MAKE_BASE=TRUE

USB_I2_TPAD_P

TP_PMU_AN_P0_1

MAKE_BASE=TRUE

SYS_PWRSEQ_1

TP_PMU_AN_P0_2

MAKE_BASE=TRUE

SYS_PWRSEQ_2

TP_PMU_AN_P0_4

MAKE_BASE=TRUE

SYS_PWRSEQ_4

TP_PMU_AN_P0_3

MAKE_BASE=TRUE

SYS_PWRSEQ_3_L

TP_PMU_AN_P0_5

MAKE_BASE=TRUE

SYS_PWRSEQ_5

TP_PMU_P7_4

MAKE_BASE=TRUE

SYS_PWRSEQ_6_L

TP_PMU_AN_P10_5

MAKE_BASE=TRUE

SYS_PWRSEQ_FINAL

MAKE_BASE=TRUE

TP_PMU_P3_0

MAKE_BASE=TRUE

TP_PMU_P3_1

MAKE_BASE=TRUE

TP_PMU_P3_2

MAKE_BASE=TRUE

TP_PMU_P3_3

TP_PMU_P7_5

MAKE_BASE=TRUE

PMU_CHARGE_V

=ADT7467_THERM_L

MAKE_BASE=TRUE

SYS_OVERTEMP_L

=CPU_HRESET_L

MAKE_BASE=TRUE

PMU_CPU_HRESET_L

TP_GOV_RESET_L

MAKE_BASE=TRUE

GOV_RESET_L

TP_PMU_AN_P10_6

MAKE_BASE=TRUE

SYS_PMU_ANALOG_AC_DET

=I2_STOPCPU_L

MAKE_BASE=TRUE

PMU_CPU_CLK_EN

=I2_STOPXTAL_L

MAKE_BASE=TRUE

PMU_SYS_CLK_EN

=CPU0_VID_AB_SEL

=CPU0_MAX1717_AB_SEL

=SLEEP_LED_CONN

NO_TEST=YES

MAKE_BASE=TRUE

NC_MAXBUS_CPU1_QACK_LTP_MAXBUS_CPU1_QACK_L

=ROM_PWD_L

MAKE_BASE=TRUE

PCI_RESET_L

MAKE_BASE=TRUE

TP_I2_GPIO_11

I2_GPIO_11

MAKE_BASE=TRUE

CPU0_VID_AB_SEL

I2_GPIO_EXT_02

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

MAKE_BASE=TRUE

SLEEP_LED_IOUT

=SLEEP_LED_IOUT

MAKE_BASE=TRUE

CPU0_MAX1717_AB_SEL

=SPI_I2_REQ

ENET_RESET_L

=RP1151P1
=RP1151P2
=RP1151P3
=RP1151P4

=RP1151P8
=RP1151P7
=RP1151P6
=RP1151P5

MAKE_BASE=TRUE
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.15 mm

AGP_VREF

AGP_CLK66M_GPU

AGP_CLK66M_GPU_R

=AGP_GPU_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=SI_TMDS_RESET_L

=GPU_AGP_VREF

=AGP_VREF

=I2_AGP_VREF

MAKE_BASE=TRUE

SI_TMDS_RESET_L

TP_EXTTMDS_RESET_L

=RP1150P1
=RP1150P2
=RP1150P3
=RP1150P4

=RP1150P8
=RP1150P7

=RP1150P5

=PCI_CLK33M_ZDB_IN

=CLK33M_TBEN_SYNC

=PCI_CLK33M_AIRPORT

=PCI_AIRPORT_REQ_L

=PCI_AIRPORT_GNT_L

=PCI_AIRPORT_INT_L

MAKE_BASE=TRUE

PCI_CLK33M_ZDB

MAKE_BASE=TRUE

PCI_CLK33M_TBEN_SYNC

MAKE_BASE=TRUE

PCI_CLK33M_AIRPORT

MAKE_BASE=TRUE

PCI_AIRPORT_INT_L

MAKE_BASE=TRUE

PCI_AIRPORT_GNT_L

PCI_SLOTA_GNT_L

PCI_AIRPORT_REQ_L

MAKE_BASE=TRUE

PCI_SLOTA_REQ_L

MAKE_BASE=TRUE

PCI_CLK33M_ZDB_R

TP_PCI_CLK33M_SLOTA_R

MAKE_BASE=TRUE

PCI_CLK33M_TBEN_SYNC_R

TP_PCI_CLK33M_SLOTD_R

MAKE_BASE=TRUE

PCI_CLK33M_AIRPORT_R

=PCI_CLK33M_ZDBOUT_R<0>

=PCI_AIRPORT_IDSEL

MAKE_BASE=TRUE

PCI_AD<17>

=PCI_AIRPORT_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=PCI_CLK33M_CBUS

=PCI_CBUS_REQ_L

=PCI_CBUS_GNT_L

=PCI_CBUS_INT_L

=PCI_CBUS_IDSEL

MAKE_BASE=TRUE

PCI_AD<20>

=PCI_CBUS_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

=PCI_CLK33M_USB2

PCI_CBUS_REQ_L

MAKE_BASE=TRUE

PCI_SLOTD_REQ_L

MAKE_BASE=TRUE

PCI_CLK33M_CBUS

MAKE_BASE=TRUE

PCI_CBUS_GNT_L

MAKE_BASE=TRUE

PCI_CBUS_INT_L

PCI_CLK33M_USB2

MAKE_BASE=TRUE

=PCI_USB2_REQ_L

=PCI_USB2_GNT_L

=PCI_USB2_INT_L

=PCI_USB2_IDSEL

MAKE_BASE=TRUE

PCI_AD<21>

=PCI_USB2_RESET_L

MAKE_BASE=TRUE

PCI_RESET_L

MAKE_BASE=TRUE

PCI_USB2_GNT_L

PCI_SLOTE_GNT_L

MAKE_BASE=TRUE

PCI_USB2_REQ_L

PCI_SLOTE_REQ_L

MAKE_BASE=TRUE

PCI_USB2_INT_L

PCI_SLOTE_INT_L

PCI_CLK33M_CBUS_R

MAKE_BASE=TRUE

=PCI_CLK33M_ZDBOUT_R<1>

MAKE_BASE=TRUE

PCI_CLK33M_USB2_R

=PCI_CLK33M_ZDBOUT_R<2>

TP_PCI_CLK33M_ZDBOUT3

MAKE_BASE=TRUE

=PCI_CLK33M_ZDBOUT_R<3>

=MAXBUS_CPU0_CLK

=SYSCLK_TBEN_SYNC

MAKE_BASE=TRUE

MAXBUS_CLK_CPU0

MAXBUS_CLK_CPU0_R

MAXBUS_CLK_TBEN_SYNC

MAKE_BASE=TRUE

MAXBUS_CLK_CPU1_R

MAKE_BASE=TRUE

TP_MAXBUS_CLK_CPU1_R

USB_BT_P

NET_SPACING_TYPE=USB2
NET_PHYSICAL_TYPE=USB2
DIFFERENTIAL_PAIR=USB_BT

USB_BT_N

NET_SPACING_TYPE=USB2
NET_PHYSICAL_TYPE=USB2
DIFFERENTIAL_PAIR=USB_BT

USB_TPAD_P

NET_SPACING_TYPE=USB2
NET_PHYSICAL_TYPE=USB2
DIFFERENTIAL_PAIR=USB_TPAD

USB_TPAD_N

NET_SPACING_TYPE=USB2
NET_PHYSICAL_TYPE=USB2
DIFFERENTIAL_PAIR=USB_TPAD

USB2_LEFT_PORT_N

DIFFERENTIAL_PAIR=USB2_LT_PORT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB2_RIGHT_PORT_P

DIFFERENTIAL_PAIR=USB2_RT_PORT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB2_RIGHT_PORT_N

DIFFERENTIAL_PAIR=USB2_RT_PORT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

USB_NEC_BT_P

USB_I2_BT_P

USB_NEC_BT_N

USB_NEC_TPAD_P

USB_I2_TPAD_P

USB_I2_TPAD_N

USB_NEC_TPAD_N

USB2_NEC_LEFT_PORT_P

USB2_I2_LEFT_PORT_P

USB2_I2_LEFT_PORT_N

USB2_NEC_LEFT_PORT_N

USB2_I2_RIGHT_PORT_P

USB2_NEC_RIGHT_PORT_P

USB2_I2_RIGHT_PORT_N

USB2_NEC_RIGHT_PORT_N

PCI_SLOTA_INT_L

USB2_LEFT_PORT_P

DIFFERENTIAL_PAIR=USB2_LT_PORT

NET_PHYSICAL_TYPE=USB2

NET_SPACING_TYPE=USB2

62

62

61

61

62

11

30

60

60

61

11

11

59

65

65

65

65

65

65

65

9

9

9

11

11

11

11

11

6

11

11

11

11

11

11

11

11

11

11

25

25

25

55

6

6

59

25

59

25

6

6

60

25

30

30

74

31

31

11

11

6

11

11

11

11

11

11

11

11

11

11

11

11

59

74

6

59

22

6

66

66

66

66

9

66

9

66

9

66

9

66

9

66

65

66 65

66 65

66

9

66

9

65

65

65

66

73

6

73

6

73

6

73

6

73

6

73

2

73

6

73

6

72

6

72

6

72

6

72

6

72

6

72

6

72

6

72

6

25 26

25 26

25 26

25 26

25 26

25 26

25 26

25

25

25

25

25 13

27

7

34 25

25

25 12

22 25

22 25

36

36

30

32

58 11

22

22

24

22

65

6

6

6

6

6

6

6

6

44 43

44 11

54

44

44

43

51

6

6

6

6

6

6

6

23

21

60

60

60

60

59

59

59

59

23

60 58

60 11

61

61

61

61

61 58

61 11

62

59

62

62

62

62 59

62 11

22

22

22

23

23

23

33

21

32

32

60

60

7

7

7

7

7

6

6

2

6

6

6

6

6

6

6

6

6

6

6

6

22

7

G

D

S

G

D

S

V-

V+

GND

OUT

VIN+ VIN-

V+

G

D

S

V-

V+

G

D

S

G

D

S

GATE

D4
D3

D2

D1

S2

S3

S1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

DIFFERENTIAL_PAIR

to facilitate design reuse)

(Connector is on separate page

Adapter Connector Side

ADAPTER INPUT/INRUSH LIMITER

GREATER THAN 13.1V DETECT

signal to enable use of AC in system. Q1208 ensures SYS_ACIN
goes low as soon as SYS_AC_DET goes low. Therefore, hardware
immediately disables the AC upon removal but only software can
enable AC after detection by the PMU.

System Side

AIRLINE

Q11 (65W)
A29 (45W)

ADAPTER

ADAPTER IDs
ID RANGE

0.33-0.99V

2.31-2.97V

1.65-2.31V

A29 ADAPTER DETECTION

0.589-0.663V

PIN VOLTAGE

2.007-2.066V

2.558-2.661V

BATTERY INPUT/CURRENT SENSE

(BATT_IN_PD)

SYS_AC_DET indicates adapter presence. SYS_ACIN is code-controlled

470K

5%
1/16W
MF-LF
402

1

2

R1209

0.1uF

20%
50V
CERM
805

1

2

C1210

402

MF-LF

1/16W

5%

330K

1

2

R1210

0.01uF

20%
16V

CERM

402

2

1

C1200

5%
1/16W
MF-LF

402

1M

21

R1206

MF-LF

20.0K

402

1/16W

1%

1

2

R1201

402

MF-LF

1/16W

1%

100K

2

1

R1204

402

MF-LF

1/16W

1%

97.6K

1

2

R1202

402

MF-LF

1/16W

1%

57.6K

1

2

R1205

10K

1%
1/16W
MF-LF

402

1

2

R1203

402

MF-LF

1/16W

5%

10K

2

1

R1208

402

MF-LF

1/16W

5%

470K

1

2

R1207

2N7002DW-X-F

SOT-363

4

5

3

Q1215

2N7002DW-X-F

SOT-363

1

2

6

Q1208

SM-LF

LMC7211

2

5

1

3

4

U1200

603

X5R

4V

20%

10UF

2

1

C1252

49.9K

402

MF-LF

1/16W

1%

21

R1252

SM

21

XW1252

0.006

2512

MF-LF

1W

1%

21

R1250

SM

21

XW1251

249K

1%
1/16W
MF-LF
402

2

1

R1251

SOT23-5-LF

CRITICAL

INA138

43

5 1

2

U1250

402

0.1UF

20%
10V

CERM

2

1

C1250

100K

5%
1/16W
MF-LF
402

2

1

R1228

402

CERM

10V

20%

0.1uF

2

1

C1220

2N7002

SOT23-LF

2

1

3

Q1220

4.7M

5%

1/16W

402

MF-LF

21

R1227

SM-LF

LMC7211

2

5

1

3

4

U1220

402

MF-LF

1/16W

1%

52.3K

2

1

R1225

402

MF-LF

1/16W

1%

100K

1

2

R1221

127K

1%
1/16W
MF-LF
402

2

1

R1226

100K

1%
1/16W
MF-LF
402

2

1

R1222

1/16W
MF-LF
402

402K

1%

2

1

R1223

10K

5%
1/16W
MF-LF

402

21

R1224

SM-LF

FERR-50-OHM

21

L1250

SM

FERR-EMI-100-OHM

21

L1253

SM

FERR-EMI-100-OHM

21

L1254

FERR-EMI-100-OHM

SM

1

2

L1252

FERR-50-OHM

SM-LF

21

L1251

CRITICAL

87438-0832

M-RT-SM

8

7

6

5

4

3

2

1

J1250

2N7002DW-X-F

SOT-363

4

5

3

Q1208

402

MF-LF

1/16W

5%

10K

2

1

R1215

2N7002DW-X-F

SOT-363

1

2

6

Q1215

10K

5%
1/16W
MF-LF

402

2

1

R1216

I317

I318

402

MF-LF

1/16W

5%

1K

21

R1255

470K

5%
1/16W
MF-LF
402

2

1

R1256

IRF7416BF

SOI

3
2
1

4

8
7
6
5

Q1210

SYNC_DATE=N/A

SYNC_MASTER=N/A

12

115

051-6929

03

Power Inputs

=I2C_BATT_SDA

=I2C_BATT_SCL

BATT_ISNS

MAKE_BASE=TRUE

PPVBATT_BATT_RAW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=12.8V

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

PPVBATT_ISNS_VINP

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PPVBATT_ISNS_VINN

VOLTAGE=12.8V

=PPVBATT_ISNS_N

=PP4V85_ALL_A29_DET

A29_DETECT

=PP3V3_ALL_A29_DET

A29_DET_L

A29_DET_REF

SYS_ADAPTER_ANALOG_AC_DET

ANALOG_AC_DET

SYS_PMU_ANALOG_AC_DET

BATT_ISNS_R

AC_ENABLE_L

SYS_ACIN_L

SYS_ACIN

SYS_AC_DET_L

=PP3V3_ALL_AC_DETECT

SYS_AC_DET

1V20_REF

AC_DET_DIV

THERM THERM

PPVBATT_ISNS_VINN

BATTERY_ISNS

THERM THERM

PPVBATT_ISNS_VINP

BATTERY_ISNS

SYS_BATT0_DET_L

=PPVBATT_BATT_VSNS

=PP3V3_BATT_IMON

VOLTAGE=10.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVBATT_BATTPOS_CONN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_BATT_CONN

VOLTAGE=0V

BATT_DATA

BATT_CLK

BATT0_DET_L

=PP3V3_ALL_BATT0_DET

VOLTAGE=24V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PP24V_ADAPTER_SW

AC_ENABLE_GATE

=PP24V_ADAPTER_RAW

25

74

18

25

8

8

25

12 12

10

10

13

10

7

11

13

13

24

10

25

14

12

12

24

10

10

10

13

10

CSIP
CSIN

BATT

PGND

DLO

LX

DHI

BST

DLOV

LDO

CELLS

GND

CSSNCSSP

REF

CCS

CCI

CCV

IINP

ICHG

ICTL

VCTL

RFIN

ACOK

ACIN

DCIN

CLS

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

S

D

G

G

D

S

GND

OUT

PG

RS-

V+

RS+

NC2

NC1

GATE

D4
D3

D2

D1

S2

S3

S1

GATE

D4
D3

D2

D1

S2

S3

S1

V-

V+

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

TABLE_5_ITEM

Place close to RS-

SWITCHER CURRENT CONTROL

CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V

SWITCHER VOLTAGE CONTROL

NC

NC

NC

(GND)

WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF
WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON

RC TIME IS 480K*10UF @ +3V_PMU

PMU SELECTS BETWEEN TWO VOLTAGES

CHARGE THROTTLED BY LOW BATTERY VOLTAGE

I = (0.2048/R ) * (V / V )

CHG

For 4.20V cells, VCTL = 0.245 REFIN

For 4.15V cells, VCTL = 0.123 REFIN

BATT

V = CELLS X (4.096 + (0.4096 * V / V ))

PLACE R383 CLOSE TO LTC1625
ROUTE LTC1625_ITH CAREFULLY

PROTECTION

BACKFEED

PLACE U1370 NEXT TO R1300

(+3V_PMU)

OD OUTPUT LOW - WHEN AC GREATER THAN 18V

_62

ICTL

REFIN

REFIN

VCTL

+PBUS CURRENT LIMIT

BATTERY SWITCH-OVER CIRCUIT

MAX1772

CRITICAL

QSOP-LF

15

13

4

20

23

2

28

14
10

98

22

21

24

1

27 26

19
18

3

16

7

5

6

25

17

12

11

U1300

603

CERM

10V

20%

1uF

2

1

C1317

MF-LF

1/16W

47K

5%

402

2

1

R1390

10K

5%
1/16W
MF-LF

402

2

1

R1391

5AMP-125V

SM-LF

2

1

F1390

5AMP-125V

SM-LF

2

1

F1395

402

MF-LF

1K

1/16W

1%

2

1

R1324

1K

402

MF-LF

1/16W

1%

2

1

R1323

33

5%

1/4W
1206

MF-LF

21

R1319

5%

402

100K

1/16W
MF-LF

2

1

R1317

2N7002DW-X-F

SOT-363

4

5

3

Q1392

402

MF-LF

1%

158K

1/16W

2

1

R1392

SOT23

MMBD914XXG

31

D1319

402

MF-LF

1/16W

5%

47K

2

1

R1395

402

MF-LF

1/16W

5%

10K

2

1

R1396

1/10W

5%

MF-LF

603

1

2

1

R1304

2N7002DW-X-F

SOT-363

1

2

6

Q1340

2N7002DW-X-F

SOT-363

4

5

3

Q1340

0.1uF

20%
25V

CERM

603

2

1

C1319

100K

402

MF-LF

1/16W

5%

2

1

R1340

10uF

6.3V

20%
X5R

603

2

1

C1392

SOT-363

2N7002DW-X-F

1

2

6

Q1348

10K

1%
1/16W
MF-LF
402

2

1

R1346

SOT-363

2N7002DW-X-F

4

5

3

Q1348

SOT-363

2N7002DW-X-F

1

2

6

Q1347

100K

MF-LF

1/16W

5%

402

2

1

R1347

2N7002DW-X-F

SOT-363

4

5

3

Q1347

0.1uF

805

CERM

50V

20%

2

1

C1320

BAS16TW-X-F

SOT-363

5 2

DP1390

BAS16TW-X-F

SOT-363

43

DP1390

1206

CERM

25V

20%

4.7uF

2

1

C1305

MF-LF

402

5%

1/16W

100K

2

1

R1318

1206

CERM

25V

20%

4.7uF

2

1

C1306

1206

CERM

25V

20%

4.7uF

2

1

C1308

1206

CERM

25V

20%

4.7uF

2

1

C1307

4.12K

1%
1/16W
MF-LF

402

2

1

R1329

1%
1/16W

402

10K

MF-LF

2

1

R1328

IRF7811W

CRITICAL

SO-8-LF

321

4

8765

Q1301

4.7

5%

MF-LF

402

1/16W

2

1

R1301

LMC7111
SOT23-5-LF

2

5

1

3

4

U1380

2N7002DW-X-F

SOT-363

1

2

6

Q1384

2N7002DW-X-F

SOT-363

4

5

3

Q1384

4.7

402

MF-LF

5%
1/16W

2

1

R1302

BAS16TW-X-F

SOT-363

6 1

DP1390

10V
603

CERM

20%

1uF

2

1

C1384

1206

10%

0.47UF

50V

CERM

2

1

C1301

MF-LF

1%

402

1/16W

6.34K

2

1

R1330

SMB

MBRS140XXG

2

1

D1300

10%

0.47UF

1206

CERM

50V

2

1

C1302

2N7002DW-X-F

SOT-363

1

2

6

Q1330

2N7002DW-X-F

SOT-363

4

5

3

Q1330

TO-252-LF

CRITICAL

SUD45P03

3

1

4

Q1395

NO STUFF

10%
402

CERM

50V

0.0022UF

2

1

C1321

1206

X7R

50V

2.2UF

10%

2

1

C1312

50V

2.2UF

10%

1206

X7R

2

1

C1313

2.2UF

50V

10%

1206

X7R

2

1

C1316

1206

X7R

50V

10%

2.2UF

2

1

C1314

1206

X7R

2.2UF

10%
50V

2

1

C1315

MF-LF

5%

1/16W

402

47K

2

1

R1360

1/16W
MF-LF

402

5%

68K

2

1

R1361

603

50V

20%

0.01UF

CERM

2

1

C1361

2N7002DW-X-F

SOT-363

1

2

6

Q1392

10%
50V
X7R
603-1

0.1UF

2

1

C1371

50V

20%
CERM

0.01uF

603

2

1

C1370

CRITICAL

603

1/16W

0.1%

2.21k

MF-LF

2

1

R1370

CRITICAL

MAX4172

TSSOP-LF

8

21

7

64

3

5

U1370

603

CRITICAL

42.2K

0.1%
1/16W
MF-LF

2

1

R1380

402

0.1uF

20%
10V

CERM

2

1

C1380

603

MF-LF

1/16W

0.1%

51.1K

CRITICAL

2

1

R1383

CRITICAL

603

42.2K

0.1%
1/16W
MF-LF

2

1

R1381

603

82.5K

0.1%
1/16W

CRITICAL

MF-LF

2

1

R1382

402

MF-LF

1/16W

1%

1K

2 1

R1386

402

MF-LF

1/16W

1%

150

2 1

R1387

402

MF-LF

1/16W

1%

10K

2 1

R1385

402

100K

5%
1/16W
MF-LF

2

1

R1384

CERM

603

10V

20%

1uF

2

1

C1327

100K

1%
1/16W
MF-LF

402

2

1

R1321

402

0.1uF

CERM

10V

20%

21

C1386

2512-1

CRITICAL

MF

1W

1%

0.025

21

R1300

ELEC

25V

20%

33uF

SM1

2

1

C1311

IRF7416BF

SOI

3
2
1

4

8
7
6
5

Q1360

CRITICAL

SOI

IRF7416BF

3
2
1

4

8
7
6
5

Q1390

12.7K

1/16W

1%
MF-LF

402

2

1

R1322

50V
1210

CERM

20%

1uF

2

1

C1303

SM1-LF

10uH

CRITICAL

21

L1300

2512

MF-LF

0.05

1%
1W

21

R1303

5%
1/10W
MF-LF

603

1

2

1

R1305

402

20%
16V
CERM

0.01uF

2

1

C1326

20%
25V

0.1uF

CERM

603

2

1

C1322

0.1uF

20%
25V
CERM
603

2

1

C1323

27.4K

402

MF-LF

1/16W

1%

2

1

R1341

4.12K

1%

1/16W

402

MF-LF

2

1

R1342

402

MF-LF

1/16W

1%

10K

2

1

R1344

20.0K

OMIT

1%
1/16W
MF-LF

402

2

1

R1345

5.23K

402

MF-LF

1/16W

1%

2

1

R1343

20%
16V

CERM

0.01uF

402

2

1

C1325

1K

1/16W
MF-LF

1%

402

2

1

R1348

CRITICAL

RLA130N03

SO8

321

4

8765

Q1300

SM-LF

LMC7211

2

5

1

3

4

U1350

402

1K

MF-LF

1%

1/16W

2

1

R1325

1%
1/16W
MF-LF

402

100K

2

1

R1353

1%
1/16W

MF-LF

402

100K

2

1

R1354

499K

1%

402

MF-LF

1/16W

2

1

R1351

100K

1%
1/16W
MF-LF
402

2

1

R1352

0.047uF

10%
16V
CERM
402

2

1

C1352

0.1uF

20%
10V
CERM
402

2

1

C1350

SOT23

MMBD914XXG

3

1

D1303

20%
10V

0.1uF

402

CERM

2

1

C1324

1206

4.7uF

CERM

25V

20%

2

1

C1309

1206

CERM

25V

20%

4.7uF

2

1

C1310

SM

21

XW1300

4.7

603

MF-LF

1/10W

5%

2

1

R1320

R1345

Q16C_PARTS

1

114S0343

RES,20K,1%,1/16W,MF-LF,402

R1345

Q41C_PARTS

1

114S0382

RES,48.7K,1%,1/16W,MF-LF,402

SYNC_DATE=N/A

SYNC_MASTER=N/A

03

051-6929

115

13

Battery Charger

VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

1772_GND

1772_DHI

=PPVIN_ALL_BATT_CHGR

1772_LX

PMU_BATT0_CHARGE

SYS_ACIN_L_RC

SYS_ACIN_L

PMU_CHARGE_V

=PPVOUT_BATT_CHRG

1772_CLS

BATT_LOW

=PPVBATT_BATT

1772_DCIN

PP24V_ADAPTER_SW

BATT_DIV

=PPVIN_BATT_CHRG_VSNS

1772_REF

1772_DLO

1772_ACOK_L

1772_ACIN

BKFD_PROT_EN_L

SYS_ACIN

BATT_24PBUS_EN BATT_14PBUS_EN

BATT_14V_GATE

=PPVBATT_BATT_PBUSB

VOLTAGE=14V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVBATT_BATT_PBUSB_FUSE

A29_DETECT

1772_CSIP
1772_CSIN

1772_CCI

A29_CLS_ADJ

A29_DETECT

1V65_REF

=PP3V3_ALL_BATT_CHGR

=PP3V3_ALL_BATT_CHGR

BATTV_HIGH

=PP3V3_ALL_BATT_CHGR

1772_LDO

1772_CCS

BATTV_LOW

CHARGE_DISABLE

BATT_LOW_L

1772_CCV

1772_CCV_RC

1772_CELLS

1772_CSSN

1772_DLOV
1772_BST

1772_BST_ESR

1772_VCTL

1772_IINP

1772_ICHG

1772_CSSP

1772_ACOK_L

1772_ICTL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=14V

PPVOUT_BATT_CHRG_R

=PP3V3_ALL_PBUS_ILIM

OVER_18V_ADJ

A29_CURRENT_ADJ

CURRENT_THRESHOLD

MAX4172_OUT

IAC_FB

1625_COMP

LTC1625_ITH

AC_GTR_18V

=PP3V3_ALL_PBUS_ILIM

ADAPTER_I_REG

IAC_RC_COMP

BKFD_PROT_GATE

PP24V_ADAPTER_ILIM_P

VOLTAGE=24V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=14V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PPVBATT_BATT_PBUSA_FUSE

BATT_24V_GATE

=PPVBATT_BATT_PBUSA

PP24V_ADAPTER_SW

=PP14VR24V_ALL_PBUS_A

MAKE_BASE=TRUE

PPVBATT_BATT_PBUSA_FUSE

25

13

18

13

13

13

13

13

13

13

10

25

12

11

10

12

10

13

12

10

12

10

10

10

13

10

14

10

13

10

12

10

13

V-

V+

G1

S1

D1

G2

D2

S2

SHUT

PLUS5VTAP

LP2951

ERR

FDBK

GND

SENSE

OUTIN

VTAP

IN OUT

SENSE

GND

FDBK

ERR

LP2951

SHUT

BOOST

SW

SGND PGND

TK

VIN

SYNC
RUN/SS

VPROG

ITH
FCB

INTVCC

TG

VOSENSE

BG

LTC1625

EXTVCC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

MAIN BATTERY OR BACKUP BATTERY

BOOTSTRAP SYSTEM FROM ADAPTER,

WHEN +24V_PBUS IS BELOW ~13.1V,
1625 IS SHUT-OFF

KEEP VIN/TK LOOP SHORT

NC

12.8V PBUS SUPPLY

CONNECT LTC1625 TK PIN AT TOP-SIDE FET

NC
NC

NC

NC

OUTPUT AT U23.1 IS 5.65V
OUTPUT AT U22.8 IS 5.4V

IF SUPERCAP BOM OPTION IS CHOSEN:

PMU SUPPLY

SUPERCAP HOOKS IN HERE

NC

NC

603

MF-LF

1/10W

5%

1

1

2

R1427

402

MF-LF

1/16W

1%

4.99K

1

2

R1425

SO8

RLA130N03

CRITICAL

321

4

8765

Q1400

MMBD914XXG

SOT23

3 1

D1420

10V
402

CERM

20%

0.1uF

2

1

C1400

402

158K

1%
1/16W
MF-LF

2

1

R1401

16.2K

402

MF-LF

1/16W

1%

2

1

R1402

SM-LF

LMC7211

2

5

1

3

4

U1420

402

CERM

10V

20%

0.1uF

2

1

C1420

1%

1/16W

402

MF-LF

97.6K

2

1

R1420

10K

1/16W
MF-LF

402

1%

2

1

R1421

1M

402

MF-LF

1/16W

1%

21

R1422

SC70-6-LF

FDG6324L

CRITICAL

1

5

6

Q1430

SC70-6-LF

FDG6324L

CRITICAL

4

3
2

6

Q1430

402

MF-LF

1/16W

5%

470K

2

1

R1430

603

MF-LF

5%

2.2

1/10W

2

1

R1410

4.7uF

1206

CERM

10V

20%

2

1

C1411

0

1/16W
MF-LF
402

5%

NO STUFF

2

1

R1415

402

MF-LF

1/16W

5%

0

2

1

R1416

SM

21

XW1400

MBR0540XXG

SOD-123

21

D1450

390

5%

1/4W

MF-LF

1206

21

R1450

MBR0540XXG

SOD-123

21

D1452

1/10W
MF-LF
603

5%

1

2

1

R1461

20%

603

X5R

6.3V

10UF

2

1

C1461

SOD-123

MBR0520LXXG

BACKUP_BATT

21

D1460

MBR0520LXXG

SOD-123

21

D1461

20%
10V
CERM
402

0.1uF

2

1

C1460

603

1/10W
MF-LF

5%

1

BACKUP_BATT

2

1

R1453

20%
CERM

805

10V

2.2uF

BACKUP_BATT

2

1

C1453

470pF

10%
50V
CERM
603

2

1

C1452

MF-LF

1/16W

402

1%

294K

OMIT

2

1

R1451

MF-LF

402

1/16W

1%

100K

2

1

R1452

402

0.1uF

20%
10V

CERM

2

1

C1451

SOI-LF

3

2

6

18

4

7

5

U1450

805

CERM

50V

20%

0.1uF

2

1

C1450

0.0047uF

25V
CERM
402

10%

NO STUFF

2

1

C1412

SO-8-LF

CRITICAL

IRF7811W

321

4

8765

Q1401

MBRS140XXG

SMB

2

1

D1400

MMBD914XXG

SOT23

31

D1451

SM1

CRITICAL

8.0uH-6.8A

3

1

2

L1400

10%

1206

X7R

50V

2.2UF

2

1

C1403

2.2UF

10%

1206

X7R

50V

2

1

C1405

1206

X7R

50V

10%

2.2UF

2

1

C1407

2.2UF

10%
50V
X7R
1206

2

1

C1404

2.2UF

10%
50V
X7R
1206

2

1

C1406

2.2UF

10%
50V
X7R
1206

2

1

C1408

SOI-3.3V-LF1

6

3

2

18

4

7

5

U1460

805

25V

20%
CERM

0.22uF

2

1

C1410

4.7uF

20%

25V
CERM
1206

2

1

C1402

25V
1206

CERM

20%

4.7uF

2

1

C1401

MBR0540XXG

SOD-123

21

D1410

CRITICAL

SSOP-LF

8

7

16
15 13

2

14

639

5

11

4

1

12

10

U1400

603

CERM

25V

5%

4700pF

2

1

C1421

603

CERM

50V

10%

470pF

2

1

C1425

805

CERM

50V

20%

0.1uF

2

1

C1427

603

CERM

25V

5%

4700pF

2

1

C1426

12.8V PBUS/PMU Supplies

SYNC_DATE=N/A

SYNC_MASTER=N/A

03

051-6929

14

115

114S3575

1

RES,MF,1/16W,357K OHM,1%,0402,SMD

R1451

SUPERCAP

?

114S2945

1

RES,MF,1/16W,394K OHM,1%,0402,SMD

R1451

BACKUP_BATT

?

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_LTC1625_EXTVCC_SW

1625_ENABLE

1625_ENABLE_L

=PP5V_PWRON_LTC1625_EXTVCC

=PP4V85_ALL_VREG

=PP5V_PWRON_PMU_SUPPLY

PP3V3_ALL_ESR

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

=PP5V_SUPERCAP

FB_4_85V_BU

1625_BST

1625_VFB

1V20_REF

1625_DIV

=PP3V3_ALL_LTC1625_SW

1625_VIN

1625_RUNSS

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

1625_INTVCC

1625_FCB

VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

1625_SGND

1625_BG

=PP12V8_LTC1625_VREG

1625_COMP

COMP_RC

1625_BST_ESR

VOLTAGE=18V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PPVIN_ALL_ADAPT_OR_BATT

=PPVBATT_BATTERY_PMU_SUPPLY

=PP12V8_PBUS_PMU_SUPPLY

PP24V_ADAPT_PMU_ILIM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=24V

=PP24V_ADAPTER_PMU_SUPPLY

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=4.6V

PP4V85_ALL_ESR

1625_VSW

=PPVIN_ALL_LTC1625

1625_TG

PP4V6_ALL_RAW

MAKE_BASE=TRUE
VOLTAGE=4.6V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

3V_PMU_VTAP

=PP3V3_ALL_VREG

10

10

10

12

10

10

13

10

10

10

10

10

SGND PGND

STBYMD

FCB
FREQSET

SNS1-

PGOOD

VOSNS2

VOUT

3.3

VCCVCC

EXT INT VIN

TG2

SW2

SNS2-

BG2

SNS2+

BOOST2

ITH2
RUN/

SS2SS1

SNS1+

BG1

SW1

BOOST1

TG1

VOSNS1
ITH1
RUN/

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3.3V/5V SWITCHER

NC

DIODE WILL ENSURE REGULATOR TURNS ON QUICKLY
POWERDOWN DELAY IS AROUND 4MS-15.6MS, VIA RC NETWORK

5V START TO TURN ON ~12.5MS =5V3V3PWRON_EN_L goes low
3V START TO TURN ON ~25MS AFTER =5V3V3PWRON_EN_L goes low

CRITICAL

LTC3707

SSOP-LF

12

4

24

1627

1726

6

9

13

14

3

2

15

1

28

20

11

8

21

5

7

22

1825

1923

10

U1500

MF-LF

1/16W

5%

10

402

2

1

R1502

1206

0.005

1%

1/4W

CRITICAL

MF-LF

21

R1551

0.22uF

20%
25V

CERM

805

2

1

C1511

20%
16V

CERM

402

0.01uF

21

C1585

TSOP-LF

SI3443DV

4

3 6

5
2
1

Q1585

TSOP-LF

SI3443DV

4

3 6

5
2
1

Q1580

0.1uF

402

CERM

10V

20%

21

C1580

603

X5R

6.3V

20%

10UF

2

1

C1581

603

MF-LF

1/10W

5%

2.2

2

1

R1511

0.001uF

402

CERM

50V

20%

21

C1514

TSOP-LF

SI3443DV

4

3 6

5
2
1

Q1590

50V

CERM

0.0022uF

10%

402

12

C1590

113K

1%
1/16W
MF-LF

402

2

1

R1504

SOD-123

MBR0540XXG

2

1

D1511

MBR0540XXG

SOD-123

2

1

D1561

603

MF-LF

1/10W

5%

2.2

2

1

R1561

MMBD914XXG

SOT23

3 1

D1533

1M

5%
1/16W
MF-LF

402

21

R1533

CERM

16V

20%

0.01uF

402

2

1

C1533

10UF

20%

6.3V
X5R
603

2

1

C1586

21.5K

1%
1/16W
MF-LF

402

2

1

R1505

220pF

5%
25V
CERM
402

2

1

C1532

SOT23-LF

2N7002

2

1

3

Q1533

NO STUFF

180pF

5%
50V
CERM
402

2

1

C1504

4.7uF

20%
10V
CERM
1206

2

1

C1530

CERM

10V

20%

0.1uF

402

2

1

C1560

SMB

MBRS140XXG

2

1

D1551

MBRS140XXG

SMB

2

1

D1501

0.047uF

10%
16V

CERM

402

2

1

C1510

4.7uH

CRITICAL

IHLP-5050

2 1

L1501

4.7uH

CRITICAL

IHLP-5050

21

L1551

NO STUFF

0.0022UF

10%
50V
CERM
402

2

1

C1565

NO STUFF

0.0022UF

10%
50V

CERM

402

2

1

C1515

CASE-D4-LF

CRITICAL

330uF

20%

6.3V
TANT

2

1

C1553

CASE-D4-LF

6.3V

20%

330uF

TANT

CRITICAL

2

1

C1503

CRITICAL

RLA130N03

SO8

3 2 1

4

8 7 6 5

Q1501

SO8

RLA130N03

CRITICAL

321

4

8765

Q1551

CRITICAL

IRF7811W

SO-8-LF

3 2 1

4

8 7 6 5

Q1502

CRITICAL

IRF7811W

SO-8-LF

321

4

8765

Q1552

X7R

50V

10%

2.2UF

1206

2

1

C1570

X7R

50V

10%

2.2UF

1206

2

1

C1571

X7R

50V

10%

2.2UF

1206

2

1

C1572

2.2UF

10%
50V
X7R
1206

2

1

C1573

2.2UF

10%
50V
X7R
1206

2

1

C1522

2.2UF

10%
50V
X7R
1206

2

1

C1523

X7R

50V

10%

2.2UF

1206

2

1

C1521

2.2UF

10%
50V
X7R
1206

2

1

C1520

CERM

25V

20%

0.22uF

805

2

1

C1561

B2

POLY

6.3V

20%

100UF

C1587

B2

POLY

6.3V

20%

100UF

2

1

C1582

100UF

20%

6.3V
POLY
B2

2

1

C1591

TSOP-LF

SI3443DV

4

3 6

5
2
1

Q1535

603

X5R

6.3V

20%

10UF

2

1

C1592

10UF

20%

6.3V
X5R
603

2

1

C1536

NO STUFF

100K

5%
1/16W
MF-LF

402

2

1

R1535

NO STUFF

180pF

5%

50V

CERM

402

2

1

C1554

63.4K

1%
1/16W
MF-LF
402

2

1

R1554

20.0K

1%
1/16W
MF-LF
402

2

1

R1555

402

0.01uF

20%
16V

CERM

2

1

C1531

0

5%
1/16W
MF-LF

402

2

1

R1532

100K

1%
1/16W
MF-LF
402

2

1

R1530

100K

1%
1/16W
MF-LF
402

2

1

R1531

CERM

50V

10%

0.0022uF

402

2

1

C1562

CERM

50V

5%

100pF

402

2

1

C1563

402

MF-LF

1/16W

1%

12.7K

2

1

R1562

0.0022uF

10%
50V

CERM

402

2

1

C1512

402

100pF

5%
50V
CERM

2

1

C1513

15.0K

1%
1/16W
MF-LF

402

2

1

R1512

22uF

20%

10V
CERM
1210

2

1

C1552

22uF

20%
10V
CERM
1210

2

1

C1551

22uF

20%
10V
CERM
1210

2

1

C1502

22uF

20%

10V
CERM
1210

2

1

C1501

SM

2

1

XW1500

402

MF-LF

1/16W

5%

10

2

1

R1503

10

5%
1/16W
MF-LF

402

2

1

R1552

10

5%
1/16W
MF-LF

402

2

1

R1553

1206

CRITICAL

1/4W

1%

0.005

MF-LF

21

R1501

0.001uF

402

CERM

50V

20%

21

C1564

402

MF-LF

1/16W

5%

1M

2

1

R1510

402

MF-LF

1/16W

5%

1M

2

1

R1560

5V/3.3V Supplies

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

03

115

15

3V_TG

=PPVIN_ALL_LTC3707

3V_SW

5V_TG

5V_SW

=PP3V3_PWRON_RUNFET

3V3RUN_EN_L

=PP3V3_RUN_RUNFET

5V_RSNS

5V_ITH_RC

5V_BOOST_ESR

3V_BOOST_ESR

3V_ITH_RC

3V_RSNS

=PP3V3_PWRON_REG

3707_FCB

3707_FSET

5V_SNSM

=5V3VPWRON_PGOOD

3V_VOSNS

=PP5V_PWRON_LTC3707_EXTVCC

3V_BOOST

3V_BG

3V_SNSP
3V_SNSM

3V_ITH

3V_RUNSS

5V_BOOST

5V_BG

5V_SNSP

5V_VOSNS
5V_ITH
5V_RUNSS

3707_STBYMD

=5V3V3PWRON_EN_L

5V3VPWRON_EN_L_RC

=PP5V_RUN_HDDFET

5VRUNHD_EN_L

=PP5V_RUN_RUNFET

5VRUN_EN_L

=PP5V_PWRON_RUNFET

=PP5V_PWRON_TRACKPAD

=5VPWRONTPAD_EN_L

=PP5V_TPAD_FET

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

3707_SGND

VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

3707_INTVCC

=PP5V_PWRON_REG

10

10

26

10

10

26

10

26

10

26

10

26

10

10

26

10

10

AGND

THRML

NC_28

NC_23

NC_15

BST2

OUT1

TON

PGOOD
REF

DL1

LX1

DH1

VCC

BST1

ON2

ON1

ILIM2

ILIM1

OUT2

SKIP

DL2

LX2

PGND

DH2

VDD

V+

FB1

FB2

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

POWER DOWN DELAY 1.5MS TO 3.5MS

DIODE PROVIDE PROVIDE QUICK TURN-ON

NC
NC

NC

MAX1715_GND

1.5V/1.8V SWITCHER

603

CERM

10V

20%

1uF

2

1

C1632

402

MF-LF

1/16W

5%

20

2 1

R1630

MAX1715

CRITICAL

QSOP-LF

2021

4

5

29

69

7

22

14

1

11

10

28

23

15

1627

12

3

13

2

1924

1726

1825

8

U1600

SM4-LF

4.7uH

CRITICAL

21

L1651

RLA130N03

CRITICAL

SO8

3 2 1

4

8 7 6 5

Q1651

SO8

RLA130N03

CRITICAL

321

4

8765

Q1601

402

MF-LF

1/16W

1%

158K

2

1

R1671

402

MF-LF

1/16W

1%

158K

2

1

R1621

BAS16TW-X-F

SOT-363

5 2

DP1620

4.7

5%
1/10W
MF-LF

603

21

R1670

4.7

5%
1/10W
MF-LF

603

21

R1620

CERM

25V

20%

0.1uF

603

2

1

C1670

B130LBT01XF

SMB

2

1

D1651

5.11K

1%
1/16W
MF-LF
402

2

1

R1651

10K

1%
1/16W
MF-LF
402

2

1

R1652

CERM

25V

20%

0.1uF

603

2

1

C1620

CRITICAL

SM4-LF

4.7uH

21

L1601

402

MF-LF

1/16W

5%

0

2

1

R1634

NO STUFF

0

5%
MF-LF

1/16W
402

2

1

R1633

CASE-D2E-LF

POLY

2.5V-ESR9V

20%

330UF

2

1

C1653

CASE-D2-LF

POLY

6.3V

20%

150uF

2

1

C1604

CRITICAL

4.7uF

20%
25V
CERM
1206

2

1

C1601

CRITICAL

4.7uF

20%
25V
CERM
1206

2

1

C1602

CRITICAL

4.7uF

20%

25V
CERM
1206

2

1

C1652

CRITICAL

4.7uF

20%

25V
CERM
1206

2

1

C1651

402

MF-LF

1/16W

5%

0

NO STUFF

2

1

R1631

402

MF-LF

1/16W

5%

0

NO STUFF

2

1

R1632

SMB

B130LBT01XF

2

1

D1601

SM

21

XW1600

603

X5R

6.3V

20%

10UF

2

1

C1686

10UF

20%

6.3V
X5R
603

2

1

C1603

10UF

20%

6.3V
X5R
603

2

1

C1655

2.2uF

20%
10V
CERM
805

2

1

C1631

805

2.2uF

20%
10V
CERM

2

1

C1630

BAS16TW-X-F

SOT-363

6 1

DP1620

330K

5%

1/16W

MF-LF

402

21

R1640

402

0.01uF

20%
16V
CERM

2

1

C1640

SI3446DV

TSOP-LF

4

36

5

2

1

Q1685

SOT23-LF

2N7002

2

1

3

Q1640

402

MF-LF

1/16W

5%

100K

2

1

R1641

1000pF

10%
25V
X7R
402

2

1

C1685

NO STUFF

50V

402

CERM

0.0022UF

10%

2

1

C1621

NO STUFF

0.0022UF

10%
50V

CERM

402

2

1

C1671

8.06K

402

MF-LF

1/16W

1%

2

1

R1601

402

MF-LF

1/16W

1%

10K

2

1

R1602

SO-8

CRITICAL

IRF7805ZPBF

3 2 1

4

8 7 6 5

Q1652

SO-8

CRITICAL

IRF7805ZPBF

321

4

8765

Q1602

BAS16TW-X-F

SOT-363

4 3

DP1620

POLY
CASE-D2E-LF

2.5V-ESR9V

330UF

20%

2

1

C1605

SI6467BDQ-E3

TSSOP

CRITICAL

7632

4

851

Q1680

X5R

6.3V

20%

10UF

603

2

1

C1680

100K

5%
1/16W
MF-LF
402

2

1

R1680

603

2200pF

CERM

50V

5%

21

C1681

402

NO STUFF

1000PF

10%
25V
X7R

2

1

C1682

1.8V/1.5V Supplies

SYNC_DATE=N/A

SYNC_MASTER=N/A

03

051-6929

16

115

1V8RUN_EN_L

=PP1V8_PWRON_RUNFET

=PP1V8_RUN_RUNFET

1_5V_FB

1_8V_BOOST1_5V_BOOST

MAX1715_TON

1_8V_BST

1_5V_ILIM

MAX1715_GND

1_8V_ILIM

MAX1715_SKIP

1_8V_FB

MAX1715_REF

1_5V_BST

1_5V_DL

=PP1V5_RUN_RUNFET

=PP1V5_PWRON_RUNFET

=1V8_1V5PWRON_PGOOD

1V5RUN_EN

PP5V_MAX1715_VCC

VOLTAGE=5V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

=PP5V_PWRON_MAX1715_VDD

=PPVIN_ALL_MAX1715

MAX1715_ON

MAX1715_EN_L_RC

=1V8_1V5PWRON_EN_L

1_8V_DL

=PPVIN_ALL_MAX1715

1_5V_LX

1_5V_DH

1_8V_LX

=PPVIN_ALL_MAX1715

1_8V_DH

MAX1715_GND

VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP1V5_PWRON_REG

=PP1V8_PWRON_REG

16

16

16

26

10

10

16

10 10

26

26

10 10

26

10

10

16

10

10

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH
SYNC/MODE

RUN/SS

RT

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

2.5V SWITCHER

CONTINUOUS MODE

BURST MODE

CERM

6.3V

20%

22UF

1206

2

1

C1700

MF-LF

1/16W

1%

15.0K

402

2

1

R1720

1000PF

5%

25V

CERM

603

2

1

C1721

SM

21

XW1700

CRITICAL

LTC3412

TSSOP-LF

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U1700

CERM

50V

5%

100PF

402

2

1

C1720

MF-LF

1/16W

1%

110K

402

2

1

R1731

MF-LF

1/16W

1%

75K

402

2

1

R1732

CERM

50V

5%

22PF

402

2

1

C1730

402K

MF-LF

1/16W

1%

402

2

1

R1730

CERM

50V

10%

470PF

402

2

1

C1722

4.7M

5%
1/16W
MF-LF

402

2

1

R1722

MF-LF

1/16W

5%

0

NO STUFF

402

2

1

R1724

0

5%
1/16W
MF-LF
402

2

1

R1723

MF-LF

1/16W

1%

309K

402

2

1

R1733

CRITICAL

1.0uH-3.48A

SM-LF

21

L1700

22UF

20%

6.3V
CERM
1206

2

1

C1701

CERM

6.3V

20%

22UF

1206

2

1

C1710

2N7002DW-X-F

SOT-363

4

5

3

Q1740

10%
25V
X7R
402

1000pF

21

C1780

TSSOP

SI6467BDQ-E3

7632

4

851

Q1780

X5R

6.3V

20%

10UF

603

2

1

C1781

22UF

20%

6.3V
CERM
1206

2

1

C1711

051-6929

17

03

115

SYNC_DATE=N/A

SYNC_MASTER=N/A

2.5V Supply

LTC3412_GND

VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=2V5PWRON_PGOOD

LTC3412_ITH

LTC3412_RUNSS

=PP3V3_PWRON_LTC3412

LTC3412_ITH_RC

LTC3412_VFB

LTC3412_VFB_DIV

LTC3412_SYNC

LTC3412_RT

=2V5PWRON_EN_L

=PP2V5_RUN_RUNFET

2V5RUN_EN_L

=PP2V5_PWRON_RUNFET

LTC3412_SW

=PP2V5_PWRON_REG

26

2

10

26

10

26

10

10

VESTA MISC

1 OF 3

PVDDDVDD

AVDDL

AVDD

GND

AGND

OVDD

REGSUP1
REGSEN1
REGCTL1

REGSUP2
REGSEN2
REGCTL2

2.5V_EN

NC

DNC

DNC

DNC

NC

TDO
TCK
TMS
TRST*

TDI

RESET*

PVINSVIN

SHDN/RT
SYNC/MODE

SW
VFB
ITH

PGOOD

PGND SGND

GND

VOUT

VIN

NOISE

CONT

G

D

S

G

D

S

G

D

S

ON/OFF

GND

VOUT

FB

VIN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Burst Mode

Mode

Continuous

Port Power Switch

1.2V Regulator

Page Notes

- =PPBUS_FW (system supply for bus power)

Signal aliases required by this page:

- =PP3V3_RUN_FWPORTPWRSW

- =PPBU_RUN_FW (backup PHY power)

regulator will be in continuous mode.

regulator. If both options are off the

Power aliases required by this page:

Controls operating mode of Vesta 1.2V

BOM options provided by this page:

Vout = 2.5V @ 150 mA

<R1>

2.5V LDO

<R2>

- VESTA1V2_BURST / VESTA1V2_PULSE

(NONE)

Vout = 1.199V @ 1.2 A

Vout = 0.8V * (1 + (R2 / R1))

3.3V Regulator

If =FWPWR_PWRON is NC:

Enables port power when machine is

Enables port power when machine is

If =FWPWR_PWRON is low when off:

running or on AC.

Pulse Mode

Vout = 3.3V @ 500mA

L6/M6 L9/M9

R1952 to enable wirespeed feature

NC

N5/N6

N9/N10

NC?

NC?

running or on AC and not shut down.

NC

(Int PU)

Schmitt trigger

Reset circuit per Vesta design guide

0.1uF

CERM

402

20%
10V

2

1

C1910

0.1uF

CERM

402

20%
10V

2

1

C1911

0.1uF

CERM

402

20%
10V

2

1

C1912

0.1uF

CERM

402

20%
10V

2

1

C1913

10V

20%

402

CERM

0.1uF

2

1

C1903

0.1uF

CERM

402

20%
10V

2

1

C1902

0.1uF

402

20%
10V

CERM

2

1

C1901

CERM

402

10V

20%

0.1uF

2

1

C1900

10V

20%

402

CERM

0.1uF

2

1

C1922

10V

20%

402

CERM

0.1uF

2

1

C1925

10V

20%

402

CERM

0.1uF

2

1

C1921

10V

20%

402

CERM

0.1uF

2

1

C1924

10V

CERM

20%

402

0.1uF

2

1

C1931

10V

20%

402

CERM

0.1uF

2

1

C1930

10V

20%

402

CERM

0.1uF

2

1

C1920

10V

20%

402

CERM

0.1uF

2

1

C1923

10V

CERM

402

20%

0.1uF

2

1

C1943

10V

20%

402

CERM

0.1uF

2

1

C1942

10V

20%

402

CERM

0.1uF

2

1

C1941

10V

20%

402

CERM

0.1uF

2

1

C1940

1uF

CERM

402

6.3V

10%

2

1

C1950

OMIT

FBGA-200

BCM5462

D8

E8

E10

D7

E7

H4

E2

E1

F2

F1

G4

G5

N4

A15

K1

F15

A7

A1

M13

C3

K2

J2

F14

C14

B7B2A2

J1

C15

B15

B1

E9

C9

B9

N10

N9N6N5M9M6L9L6

R12R3P11

P10

P5

P4

N8N7M8M7L8

L7

J12

J11

P9P8P7

P6

H12

H11

M3

U8500

20K

1/16W

402

5%

MF-LF

2

1

R1950

6.3V

20%

603

X5R

10UF

2

1

C1908

FERR-EMI-600-OHM

SM

21

L1900

CRITICAL

LTC3411

MSOP-LF

9

2

4

7

1

3

6

8

5

10

U1990

100pF

CERM
402

5%
50V

2

1

C1993

1/16W

4.99K

MF-LF

402

1%

2

1

R1996

10%

0.0033uF

CERM
402

50V

2

1

C1994

SM1-LF

2.2uH

CRITICAL

21

L1990

22pF

CERM

402

5%

50V

2

1

C1992

4.99K

MF-LF
402

1%
1/16W

2

1

R1997

MF-LF
402

1%
1/16W

10K

2

1

R1998

6.3V
805

X5R

22uF

20%

2

1

C1995

6.3V

10%

1uF

CERM

402

2

1

C1991

1/16W

5%

402

MF-LF

10

21

R1990

6.3V

20%

603

X5R

10UF

2

1

C1990

324K

MF-LF
402

1%
1/16W

2

1

R1995

1/16W

5%

402

MF-LF

1M

2

1

R1994

1M

MF-LF

5%

1/16W

402

2

1

R1991

10K

MF-LF

402

5%

1/16W

VESTA1V2_PULSE

2

1

R1993

10K

MF-LF

402

5%

1/16W

VESTA1V2_BURST

2

1

R1992

SM

21

XW1990

16V

20%

402

CERM

0.01uF

2

1

C1981

6.3V

10%

1uF

CERM

402

2

1

C1980

6.3V

20%

603

X5R

10UF

2

1

C1982

1/16W

5%

402

MF-LF

330K

2

1

R1966

402

16V

20%

CERM

0.01uF

2

1

C1965

1/16W

5%

402

MF-LF

470K

2

1

R1965

BAS16TW-X-F

SOT-363

43

DP1960

BAS16TW-X-F

SOT-363

5 2

DP1960

SOT-363

BAS16TW-X-F

61

DP1960

10K

MF-LF

402

5%

1/16W

21

R1961

100K

402

5%
1/16W
MF-LF

2

1

R1960

470K

MF-LF

402

5%

1/16W

2

1

R1963

CRITICAL

MM1572FN

SOT-25A

51

4

2

3

U1980

CRITICAL

B340XF

SMB

21

D1965

NDS9407

CRITICAL

SOI-LF

3
2

1

4

8

7

6
5

Q1965

1.5A-24V

MINISMDC

21

F1965

1/16W

5%

402

MF-LF

10K

2

1

R1952

MMBRM140XXG

SMD

2

1

D1970

2N7002

SOT23-LF

2

1

3

Q1960

10K

1/16W

402

5%

MF-LF

2

1

R1951

SOT-363

2N7002DW-X-F

1

2

6

Q1950

2N7002DW-X-F

SOT-363

4

5

3

Q1950

SMD20E40C-X-F

SC-59

3

2

1

D1975

SM-LF

LM2594

CRITICAL

8

7

56

4

U1970

10uF

CERM
2320

N20P20%

50V

2

1

C1970

CRITICAL

POLY

6.3V

20%

B2

100UF

2

1

C1971

CRITICAL

100uH-0.8A

PLC

21

L1970

SYNC_DATE=N/A

SYNC_MASTER=N/A

Vesta Power & Misc

115

19

051-6929

03

=PP3V3_VESTA

VESTA_RESET_L_RC

VESTA_RESET

VESTA_RESET_L

PPBUS_FWPWRSW_F

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=25V

=PPBUS_FWPWRSW

=PP2V5_VESTA

=PP3V3_VESTA

=PP1V2_VESTA

=PP3V3_VESTA

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PP1V2_VESTA_AVDDL

TP_VESTA_DNC_E9

TP_VESTA_DNC_C9

TP_VESTA_DNC_B9

=JTAG_VESTA_TRST_L

=JTAG_VESTA_TMS

=JTAG_VESTA_TCK

=JTAG_VESTA_TDI
=JTAG_VESTA_TDO

TP_VESTA_2_5V_EN

TP_VESTA_REGCTL1

TP_VESTA_REGSUP1
TP_VESTA_REGSEN1

TP_VESTA_REGCTL2

TP_VESTA_REGSUP2
TP_VESTA_REGSEN2

VESTA1V2_MODE

FWPWR_EN_L

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

FWPWR_EN

=FWPWR_PWRON

=PP2V5_VESTA_LDO

=PP1V2_VESTA_REG

=PP3V3_VESTA_2V5REG

VESTA1V2_ITH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VESTA2V5_NOISE

=PPBUS_FW_FET

PPBUS_FW_FET_D

VOLTAGE=25V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

FWPWR_EN_L_DIV

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

=PPBU_RUN_FW

=PPFW_P3V3VESTA

=PP3V3_VESTA_REG

PPVIN_VESTA3V3

VOLTAGE=33V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

FWPWR_RUN

FWPWR_ACIN

SYS_ACIN

=PP3V3_RUN_FWPORTPWRSW

VESTA1V2_ITH_RC

VESTA1V2_VFB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VESTA1V2_SW

VESTA3V3_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VESTA1V2_SGND

VOLTAGE=0V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PPVOUT_VESTA1V2

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm

=PP3V3_VESTA_1V2REG

VESTA1V2_RT

66

66

66

25

18

18

18

13

10

66

10

10

10

10

10

2

9

9

9

9

9

2

26

10

10

10

10

10

10

10

12

10

10

VDD15_0

VDD15_1

VDD15_2

VDD15_3

VDD15_4

VDD15_5

VDD15_6

VDD15_7

VDD15_8

VDD15_9

VDD15_10

VDD15_11

VDD15_12

VDD15_13

VDD15_15

VDD15_14

VDD15_16

VDD15_17

VDD15_18

VDD15_19

VDD15_20

VDD15_21

VDD15_22

VDD15_23

VDD15_24

VSS_49

VSS_48

VSS_46
VSS_47

VSS_45

VSS_44

VSS_43

VSS_41
VSS_42

VSS_40

VSS_39

VSS_38

VSS_35
VSS_36
VSS_37

VSS_33
VSS_34

VSS_32

VSS_30
VSS_31

VSS_28
VSS_29

VSS_27

VSS_25
VSS_26

VSS_23
VSS_24

VSS_21

VSS_20

VSS_19

VSS_17
VSS_18

VSS_15

VSS_13

VSS_12

VSS_10
VSS_11

VSS_5

VSS_2
VSS_3
VSS_4

VSS_1

VSS_0

VSS_98
VSS_99

VSS_149

VSS_148

VSS_96
VSS_97

VSS_95

VSS_93
VSS_94

VSS_91
VSS_92

VSS_90

VSS_88
VSS_89

VSS_86

VSS_85

VSS_87

VSS_83
VSS_84

VSS_82

VSS_81

VSS_80

VSS_79

VSS_78

VSS_147

VSS_146

VSS_145

VSS_143
VSS_144

VSS_142

VSS_141

VSS_140

VSS_138
VSS_139

VSS_137

VSS_136

VSS_135

VSS_133
VSS_134

VSS_131
VSS_132

VSS_130

VSS_128
VSS_129

VSS_198
VSS_199

VSS_197

VSS_196

VSS_195

VSS_193
VSS_194

VSS_192

VSS_191

VSS_190

VSS_188
VSS_189

VSS_186
VSS_187

VSS_185

VSS_183
VSS_184

VSS_182

VSS_181

VSS_180

VSS_179

VSS_178

VSS_77

VSS_76

VSS_75

VSS_74

VSS_73

VSS_72

VSS_70
VSS_71

VSS_69

VSS_67
VSS_68

VSS_65
VSS_66

VSS_64

VSS_62
VSS_63

VSS_60
VSS_61

VSS_58

VSS_57

VSS_59

VSS_126
VSS_127

VSS_125

VSS_123
VSS_124

VSS_122

VSS_121

VSS_120

VSS_117
VSS_118
VSS_119

VSS_116

VSS_115

VSS_112

VSS_114

VSS_113

VSS_111

VSS_110

VSS_107

VSS_109

VSS_108

VSS_55
VSS_56

VSS_53

VSS_52

VSS_54

VSS_50
VSS_51

VSS_106

VSS_105

VSS_102
VSS_103
VSS_104

VSS_100
VSS_101

VSS_176
VSS_177

VSS_175

VSS_174

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_167
VSS_168

VSS_166

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_156

VSS_155

VSS_153
VSS_154

VSS_152

VSS_150
VSS_151

VSS_22

VSS_16

VSS_14

VSS_9

VSS_8

VSS_7

VSS_6

CORE POWER & GND

(1 of 14)

VDD33_47

VDD33_46

VDD33_45

VDD33_44

VDD33_41
VDD33_42
VDD33_43

VDD33_39
VDD33_40

VDD33_38

VDD33_37

VDD33_36

VDD33_34
VDD33_35

VDD33_33

VDD33_32

VDD33_31

VDD33_30

VDD33_29

VDD33_28

VDD33_27

VDD33_26

VDD33_24
VDD33_25

VDD33_23

VDD33_21
VDD33_22

VDD33_19
VDD33_20

VDD33_18

VDD33_16
VDD33_17

VDD33_15

VDD33_14

VDD33_13

VDD33_12

VDD33_11

VDD33_8

VDD33_5
VDD33_6
VDD33_7

VDD33_3
VDD33_4

VDD33_0

VDD33_2

VDD33_1

VDD33_9

VDD33_10

(2 of 14)

3.3V I/O POWER

PLL1_AVDD

PLL2_AVDD

PLL1_VSSA

PLL3_AVDD

PLL2_VSSA

PLL4_AVDD

PLL3_VSSA

PLL4_VSSA

PLL5_AVDD

PLL5_VSSA

PLL6_AVDD

PLL6_VSSA

PLL7_AVDD

PLL7_VSSA

PLL9_AVDD

PLL9_VSSA

AGP TRACK

PLL9

PCI TRACK

PLL7

PLL6

SYS TRACK

ATA

PCI
AGP

INT REF

PLL5

SYSCLK

PLL4

AGP(SS)

PCI(SS)

49.15 MHZ

PLL3

45.16 MHZ

PLL2

32/48 MHZ

PLL1

(3 of 14)

PLL POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3.3V I/O DECOUPLING

1 X 10uF (0603)
48 X 1uF (0402)

Power aliases required by this page:

- =PPVCORE_PWRON_I2

- =PP3V3_PWRON_I2_IO1

- =PP3V3_PWRON_I2_IO2

- =PP3V3_PWRON_I2_AGPPCI

- =PP3V3_PWRON_I2_MAXBUS
NOTE: The four 3.3V rails are meant to be
aliased together. They are called

Signal aliases required by this page:

BOM options provided by this page:

(NONE)

(NONE)

is at least one 10uF cap per rail.

aliased together, make sure there

NOTE: When these four rails are not

out separately for test purposes.

(48 Balls on I2)

VDD33_AGP

I2S and some GPIOs

Page Notes

- =PP1V5_PWRON_I2_PLL

MAXBUS

VDD33_

VDD33_PCI (18)

VDD33_IO_2 (12)

For GPIOs, Pwr Mgt

For USB, FireWire,

VDD33_IO_1 (14)

25 X 1uF (0402)

(25 Balls on I2)

VCore Bypassing

4 X 10uF (0603)

1uF

CERM

402

10%

6.3V
2

1

C2158

6.3V

10%

402

CERM

1uF

2

1

C2126

6.3V

10%

402

CERM

1uF

2

1

C2133

10UF

X5R
603

20%

6.3V
2

1

C2147

6.3V

10%
CERM

402

1uF

2

1

C2144

1uF

CERM

402

10%

6.3V
2

1

C2163

OMIT

I2

BGA

E29

E26

E23

E20

E2

E17

E14

E11

B8

B5

AB22

B35

B32

B29

B26

B23

B20

B2

B17

B14

B11

AB16

AR8

AR5

AR35

AR32

AR29

AR26

AR23

AR20

AR2

AR17

AB15

AR14

AR11

AM8

AM7

AM5

AM35

AM32

AM29

AM26

AM23

AB12

AM20

AM2

AM17

AM14

AM11

AJ8

AJ5

AJ35

AJ32

AJ29

AA29

AJ27

AJ26

AJ24

AJ23

AJ20

AJ2

AJ17

AJ14

AJ11

AH14

AA25

AG29

AG14

AG11

AF8

AF5

AF35

AF32

AF29

AF27

AF2

AA21

AF18

AF10

AE25

AE20

AE19

AE17

AE15

AE14

AD29

AD21

AA17

Y8

Y5

Y35

Y32

Y29

Y22

Y2

Y18

Y16

Y11

AD16

W26

W25

W21

W19

W15

V28

V20

V16

V12

U8

AC5

U5

U35

U32

U28

U25

U21

U2

U16

U13

T20

AC35

T18

T16

R29

R25

R22

R20

R19

R17

R15

R13

AC32

P8

P5

P35

P32

P29

P27

P24

P21

P2

P17

AC29

N25

N23

N18

N16

N14

M26

M23

M21

M19

M17

AC26

M15

M13

L8

L5

L35

L32

L29

L27

L20

L2

AC25

K29

K26

K25

K23

K20

K17

K14

K11

K10

H8

AC20

H5

H35

H32

H29

H27

H26

H24

H23

H20

H2

AC2

H18

H17

H15

H14

H12

H11

E8

E5

E35

E32

AB24

AA15

AA13

R21

R18

R16

P20

P16

N17

AC19

Y17

Y15

W22

W20

W18

AC16

V22

V19

V17

U22

U20

U18

U15

T22

T19

T15

AB21

AA22

U2100

6.3V

10%

402

CERM

1uF

2

1

C2139

6.3V

10%

402

CERM

1uF

2

1

C2138

OMIT

I2

BGA

N13

L6

L3

L10

J8

AP32

AP29

AP26

AP23

AL30

AL29

AL27

AL26

H6

AL24

AL23

AH27

AH26

AH24

AH23

AH20

AD22

AD20

AC21

H3

M22

M18

M16

Y13

AM3

AJ6

AJ3

AF9

AF6

AF3

F5

AF11

AC6

AC3

AC15

AB13

T13

R14

P6

P3

P12

E3

AH17

U2100

1uF

CERM

402

10%

6.3V
2

1

C2169

1uF

CERM

402

10%

6.3V
2

1

C2168

1uF

CERM

402

10%

6.3V
2

1

C2152

1uF

CERM

402

10%

6.3V
2

1

C2151

6.3V

10%

402

CERM

1uF

2

1

C2132

6.3V

10%

402

CERM

1uF

2

1

C2131

6.3V

10%

402

CERM

1uF

2

1

C2130

6.3V

10%

1uF

402

CERM

2

1

C2101

6.3V

10%

402

CERM

1uF

2

1

C2102

6.3V

10%

CERM
402

1uF

2

1

C2103

6.3V

10%

402

CERM

1uF

2

1

C2104

6.3V

10%

CERM
402

1uF

2

1

C2105

6.3V

10%

CERM
402

1uF

2

1

C2106

6.3V

10%

402

CERM

1uF

2

1

C2107

1uF

CERM

402

10%

6.3V
2

1

C2150

6.3V

10%

402

1uF

CERM

2

1

C2109

4.7

5%

MF-LF

402

1/16W

21

R2101

4.7

5%

MF-LF

402

1/16W

21

R2102

4.7

5%

MF-LF

402

1/16W

21

R2103

4.7

MF-LF

5%

402

1/16W

21

R2104

4.7

5%

MF-LF

402

1/16W

21

R2105

4.7

MF-LF

5%

402

1/16W

21

R2106

4.7

MF-LF

5%

402

1/16W

21

R2107

4.7

5%

402

1/16W
MF-LF

21

R2109

I2

BGA

OMIT

AL10

AK10

AH21

AH22

N24

M24

AE9

AD9

H10

H9

AJ19

AK19

Y19

AA19

Y20

AA20

U2100

1uF

CERM

402

10%

6.3V
2

1

C2162

6.3V

20%

603

X5R

10UF

2

1

C2146

6.3V

20%

603

X5R

10UF

2

1

C2149

6.3V

20%

603

X5R

10UF

2

1

C2148

20%

603

X5R

10UF

6.3V

2

1

C2199

1uF

CERM

402

10%

6.3V
2

1

C2157

1uF

CERM

402

10%

6.3V
2

1

C2156

1uF

10%

6.3V
CERM

402

2

1

C2174

1uF

CERM

402

10%

6.3V
2

1

C2155

1uF

CERM

402

10%

6.3V
2

1

C2161

1uF

CERM

402

10%

6.3V
2

1

C2160

1uF

CERM

402

10%

6.3V
2

1

C2167

1uF

CERM

402

10%

6.3V
2

1

C2166

1uF

CERM

402

10%

6.3V
2

1

C2165

1uF

CERM

402

10%

6.3V
2

1

C2173

1uF

CERM

402

10%

6.3V
2

1

C2172

CERM

402

1uF

10%

6.3V
2

1

C2171

1uF

CERM

402

10%

6.3V
2

1

C2170

6.3V

10%

402

CERM

1uF

2

1

C2179

6.3V

10%

402

CERM

1uF

2

1

C2178

6.3V

10%

402

CERM

1uF

2

1

C2177

6.3V

10%

402

CERM

1uF

2

1

C2176

1uF

10%

6.3V

402

CERM

2

1

C2175

6.3V

10%

402

CERM

1uF

2

1

C2185

6.3V

10%

402

CERM

1uF

2

1

C2191

6.3V

10%

402

CERM

1uF

2

1

C2184

6.3V

10%

1uF

402

CERM

2

1

C2183

6.3V

10%

402

CERM

1uF

2

1

C2182

6.3V

10%

402

CERM

1uF

2

1

C2181

1uF

CERM

402

10%

6.3V
2

1

C2154

6.3V

10%

402

CERM

1uF

2

1

C2180

6.3V

10%

402

CERM

1uF

2

1

C2190

6.3V

10%

402

CERM

1uF

2

1

C2189

6.3V

10%

402

CERM

1uF

2

1

C2188

6.3V

10%

402

CERM

1uF

2

1

C2187

6.3V

10%

402

CERM

1uF

2

1

C2186

6.3V

10%

402

CERM

1uF

2

1

C2197

6.3V

10%

402

CERM

1uF

2

1

C2196

1uF

CERM

402

10%

6.3V
2

1

C2153

6.3V

10%

402

CERM

1uF

2

1

C2195

6.3V

10%

402

CERM

1uF

2

1

C2194

6.3V

10%

402

CERM

1uF

2

1

C2193

6.3V

10%

402

CERM

1uF

2

1

C2192

6.3V

10%

402

CERM

1uF

2

1

C2125

6.3V

10%

402

CERM

1uF

2

1

C2137

1uF

CERM

402

10%

6.3V
2

1

C2159

6.3V

10%

402

CERM

1uF

2

1

C2124

6.3V

10%

402

CERM

1uF

2

1

C2136

6.3V

10%

402

CERM

1uF

2

1

C2135

6.3V

10%

402

CERM

1uF

2

1

C2129

6.3V

10%

402

CERM

1uF

2

1

C2123

6.3V

10%

402

CERM

1uF

2

1

C2122

6.3V

10%

402

CERM

1uF

2

1

C2128

6.3V

10%

402

CERM

1uF

2

1

C2134

6.3V

10%

1uF

CERM
402

2

1

C2143

1uF

CERM

402

10%

6.3V
2

1

C2164

6.3V

10%

1uF

CERM
402

2

1

C2142

6.3V

10%

1uF

CERM
402

2

1

C2141

6.3V

10%

1uF

CERM
402

2

1

C2140

6.3V

10%

402

CERM

1uF

2

1

C2121

6.3V

10%

402

CERM

1uF

2

1

C2127

6.3V

10%

402

CERM

1uF

2

1

C2120

21

115

03

051-6929

I2 Power

SYNC_MASTER=N/A

SYNC_DATE=N/A

=PPVCORE_PWRON_I2

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL9AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL7AVDD

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL6AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL5AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL4AVDD

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL3AVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.5V

PP1V5_PWRON_I2_PLL2AVDD

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

PP1V5_PWRON_I2_PLL1AVDD

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

=PP3V3_PWRON_I2_IO2

=PP1V5_PWRON_I2_PLL

=PP3V3_PWRON_I2_IO1

=PP3V3_PWRON_I2_AGPPCI

=PP3V3_PWRON_I2_MAXBUS

10

10

10

10

10

10

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH
SYNC/MODE

RUN/SS

RT

ADJ

BYP
GND

OUT

NC

NC

SHDN

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Rb>

<Ra>

Vout = 0.8V * (1 + (Ra / (Rb1 + Rb2)))

<Ra>

<Rb1>

<Rb2>

Vburst = 0.8V * (Rb2 / (Rb1 + Rb2))

If I2VCORE_BURST is selected:
Iburst = (Vburst - 0.2V) * (3.75A / 0.8V)

Iadj = 30nA at 25 C

I2 PLL LDO

- =PP1V5_PWRON_I2PLLVDD_LDO

- =PPVIN_PWRON_I2PLLVDD

indicated LTC3412 output voltage.

- I2VCORE_xVx

- I2VCORE_CONT / I2VCORE_BURST

burst mode for LTC3412 regulator.

- =I2VCORE_PGOOD

BOM options provided by this page:

Selects appropriate resistor for the

Selects between forced continuous and

Signal aliases required by this page:

- =PPVCORE_PWRON_I2_REG

Page Notes

Power aliases required by this page:

NC

NC

I2 VCore Regulator

- =PP2V7R5V5_PWRON_I2VCORE

Open-Collector

One for each PVIN pin

Vout = 1.22V * (1 + Ra/Rb) + (Iadj * Ra)

LTC3412

CRITICAL

TSSOP-LF

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U2200

402

309K

MF-LF

1/16W

1%

2

1

R2204

CRITICAL

1.0uH-3.48A

SM-LF

21

L2200

SM

21

XW2200

I2VCORE_1V5

1/16W

402

MF-LF

1%

162K

2

1

R2210

1%

MF-LF

110K

402

1/16W

2

1

R2211

402

22pF

5%
50V
CERM

2

1

C2210

1/16W

1%

75K

402

MF-LF

2

1

R2212

5%

1/16W

402

0

MF-LF

I2VCORE_BURST

2

1

R2209

1/16W

5%

I2VCORE_CONT

MF-LF

402

0

2

1

R2208

CERM

50V

5%

100pF

402

2

1

C2206

1206

CERM

22uF

20%

6.3V

2

1

C2201

1206

CERM

22uF

20%

6.3V

2

1

C2200

1206

CERM

22uF

20%

6.3V
2

1

C2216

1206

6.3V

20%

CERM

22uF

2

1

C2215

MF-LF

1/16W

1%

15.0K

402

2

1

R2205

603

CERM

5%

1000pF

25V

2

1

C2205

CERM

50V

10%

470pF

402

2

1

C2207

1/16W
MF-LF

402

4.7M

5%

2

1

R2207

CRITICAL

LT1962-ADJ

MSOP-LF

5

1

7

6

8

4

3

2

U2250

CERM

1uF

10V

20%

603

2

1

C2250

10%

0.01uF

16V

CERM

402

2

1

C2254

1%
1/16W
MF-LF
402

15.8K

2

1

R2255

1%
1/16W
MF-LF
402

68.1K

2

1

R2256

20%

6.3V
X5R

10uF

603

2

1

C2259

RES,185K,1%,MF-LF,0402

114S0437

1

R2210

I2VCORE_1V6

R2210

114S0446

1

I2VCORE_1V8

RES,232K,1%,MF-LF,0402

22

115

03

051-6929

I2 Power Supplies

SYNC_MASTER=N/A

SYNC_DATE=N/A

114S0442

R2210

1

I2VCORE_1V7

RES,210K,1%,MF-LF,0402

=PPVIN_PWRON_I2PLLVDD

=PP2V7R5V5_PWRON_I2VCORE

I2VCORE_ITH_RC

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.15 mm

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

I2VCORE_RUNSS

MIN_NECK_WIDTH=0.15 mm

I2VCORE_ITH

MIN_LINE_WIDTH=0.20 mm

I2VCORE_RT

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

=I2VCORE_PGOOD

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.75 mm

I2VCORE_SW

I2PLLVDD_BYP

I2PLLVDD_ADJ

I2VCORE_MODE

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.20 mm

I2VCORE_MODE_VDIV

=PP1V5_PWRON_I2PLL_LDO

=PPVCORE_PWRON_I2_REG

VOLTAGE=0V
MIN_LINE_WIDTH=0.75 mm
MIN_NECK_WIDTH=0.25 mm

GND_I2VCORE

I2VCORE_VFB

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.15 mm

10

10

26

10

10

GND

VCC

PRE

Q

CLK

D
CLR

Q*

GND

VCC

PRE

Q

CLK

D
CLR

Q*

GND

VCC

PRE

Q

CLK

D
CLR

Q*

IN

IN

IN

OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

NCNC

PCI Feedback Clock Ladder

AGP Feedback Clock Ladder

Keep short Keep short

Signal

MAXBUS_DATA<62>

MAXBUS_DATA<54>

MAXBUS_DATA<44:41>

HIGH

LOW

LOW

HIGH

Tied

33-Ohm MaxBus Drivers

50-Ohm MaxBus Drivers

1394a Support (Legacy Mode)

1394b Support (Beta Mode)

Description

See Table Below

Tied

0000

0110

Description

133.12MHz CPU / 266.24MHz DDR

149.76MHz CPU / 299.52MHz DDR

166.40MHz CPU / 332.80MHz DDR

171.95MHz CPU / 342.90MHz DDR

177.49MHz CPU / 354.98MHz DDR

183.04MHz CPU / 366.08MHz DDR

188.59MHz CPU / 377.18MHz DDR

194.13MHz CPU / 388.26MHz DDR

199.68MHz CPU / 399.36MHz DDR

I2 Configuration Straps

DIFFERENTIAL_PAIR

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

MaxBus Feedback Clock Network

1000

0100

1100

0010

1010

1110

0001

1/16W

5%

MF-LF

10K

402

MAXBUS_D41_PU

2

1

R2310

1/16W

5%

402

10K

MF-LF

I2_MAXBUS_33OHM

2

1

R2303

I104

I105

CRITICAL

74AUC1G74

BGA-YZP

MAXBUS_TBEN_SYNC

A2

C1

D2

B2

D1

B1

C2

A1

U2390

BGA-YZP

74AUC1G74

CRITICAL

MAXBUS_TBEN_SYNC

A2

C1

D2

B2

D1

B1

C2

A1

U2391

CRITICAL

BGA-YZP

74AUC1G74

MAXBUS_TBEN_SYNC

A2

C1

D2

B2

D1

B1

C2

A1

U2392

MF-LF

1/16W

10K

402

5%

MAXBUS_D44_PD

2

1

R2305

0.1uF

20%
10V
CERM
402

MAXBUS_TBEN_SYNC

2

1

C2390

402

CERM

10V

20%

0.1uF

MAXBUS_TBEN_SYNC

2

1

C2391

0.1uF

20%
10V
CERM
402

MAXBUS_TBEN_SYNC

2

1

C2392

0

5%
1/16W
MF-LF

402

MAXBUS_TBEN_SYNC

21

R2392

I119

1/16W

5%

MF-LF

10K

402

I2_FW_BETA

2

1

R2300

I120

402

10K

MF-LF

5%

1/16W

I2_FW_LEGACY

2

1

R2301

10K

MF-LF

5%

1/16W

402

MAXBUS_D42_PU

2

1

R2308

10K

MF-LF
402

5%
1/16W

MAXBUS_D41_PD

2

1

R2311

I2_AGP_FBCLK_MATCHED

1/16W

402

MF-LF

5%

0

21

R2365

I2_AGP_FBCLK_MATCHED

MF-LF

402

5%

0

1/16W

21

R2367

I2_AGP_FBCLK_SHORTEST

402

0

MF-LF

1/16W

5%

2

1

R2360

10K

MF-LF

402

5%

1/16W

MAXBUS_D42_PD

2

1

R2309

I2_PCI_FBCLK_MATCHED

402

MF-LF

1/16W

5%

0

21

R2385

I2_PCI_FBCLK_MATCHED

MF-LF

402

5%

1/16W

0

21

R2387

5%
1/16W
MF-LF

0

402

I2_PCI_FBCLK_SHORTEST

2

1

R2380

10K

MF-LF

5%
1/16W

402

MAXBUS_D43_PU

2

1

R2306

0

402

MF-LF

1/16W

5%

I2_MAXBUS_FBCLK_SHORTEST

21

R2340

5%

MF-LF

10K

402

1/16W

MAXBUS_D44_PU

2

1

R2304

I2_MAXBUS_FBCLK_MATCHED

5%
1/16W
MF-LF

402

0

2

1

R2350

I2_MAXBUS_FBCLK_MATCHED

0

402

MF-LF

1/16W

5%

2

1

R2352

32

43

59

1/16W

5%

402

MF-LF

10K

MAXBUS_D43_PD

2

1

R2307

43

59

32

10K

MF-LF
402

5%
1/16W

I2_MAXBUS_50OHM

2

1

R2302

MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_183MHZ

MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_166MHZ

MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_194MHZ

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD

I2_MAXBUS_177MHZ

MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_172MHZ

MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD

I2_MAXBUS_150MHZ

I2_MAXBUS_133MHZ

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PU

I2_MAXBUS_200MHZ

I2_MAXBUS_189MHZ

MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2 Supplemental

23

115

03

051-6929

I2_MAXBUS_FBCLK_MATCHED

=PP1V5R1V8_MAXBUS

MAXBUS_DATA<42>
MAXBUS_DATA<41>

MAXBUS_DATA<44>
MAXBUS_DATA<43>

MAXBUS_DATA<54>

MAXBUS_DATA<62>

I2_MAXBUS_FBCLK_OUT

MAKE_BASE=TRUE

I2_MAXBUS_FBCLK_IN

=I2_MAXBUS_FBCLK_IN

I2_MAXBUS_FBCLK_MATCHED

I2_FBCLK I2_FBCLK

I2_MAXBUS_FBCLK_IN

I2_FBCLK I2_FBCLK

I2_AGP_FBCLK_MATCHED

I2_FBCLKI2_FBCLK

I2_FBCLKI2_FBCLK

I2_AGP_FBCLK_IN

I2_AGP_FBCLK_MATCHED

I2_AGP_FBCLK_OUT

I2_AGP_FBCLK_IN

MAKE_BASE=TRUE

=I2_AGP_FBCLK_IN

I2_PCI_FBCLK_MATCHED

I2_PCI_FBCLK_OUT

I2_PCI_FBCLK_IN

MAKE_BASE=TRUE

=I2_PCI_FBCLK_IN

TBEN_SYNC_F2TBEN_SYNC_F1

TBEN_SYNC_CLR_L

=PP1V8_RUN_TBEN_SYNC

MAXBUS_TBEN_SYNC

MAXBUS_TBEN

I2_FBCLK I2_FBCLK

I2_PCI_FBCLK_IN

I2_FBCLK I2_FBCLK

I2_PCI_FBCLK_MATCHED

=SYSCLK_TBEN_SYNC

CLOCK CLOCK

CLOCK CLOCK

=CLK33M_TBEN_SYNC

=CLK33M_TBEN_SYNC

=SYSCLK_TBEN_SYNC

34

33

33

33

33

33

33

33

32

32

32

32

32

32

33

21

21

21

21

21

10

9

9

9

9

9

9

21

21

21

21

21

21

21

21

21

10

32

21

21

11

11

11

11

GPIO_16_H - See Ethernet Sym

EXT_05_H - See Ethernet Sym

GPIO INTERFACE

TEST/JTAG

(4 OF 14)

MISCELLANEOUS

I2S 0

I2S 1

I2C

POWER MGMT/CLOCK

SCCB/VIA

SCCA

REF_CLK_IN

REF_CLK_OUT

PWR_SPDREQ_L

PWR_STPXTL_L

REF_PURESET_L

PWR_STPCPU_L

JTG_TRSTN_L

JTG_TMS_H
JTG_TCK_H

JTG_TDI_H

TST_PLLEN_H

TST_TEI_H

SCC_TRXCB_H

SCC_GPIOB_L

SCC_RXDB_H

SCC_RXDA_H

PWR_SPDACK_L

PWR_INTRWD_H

PWR_PCI_PME_L

JTG_TDO_H

SCC_RTSB_L

SCC_TXDB_L

SCC_TXDA_L

EXT_00_H
EXT_01_H
EXT_02_H

EXT_08_H
EXT_09_H

EXT_11_H

EXT_15_H

EXT_14_H

GPIO_EXT_01_H

GPIO_EXT_03_H

GPIO_EXT_02_H

GPIO_05_H

GPIO_04_H

GPIO_06_H

GPIO_11_H

GPIO_09_H

IIC_CLK_0_H

IIC_D_0_H

IIC_CLK_2_H

IIC_D_2_H

AUD_DTO_A_H
AUD_CLKOUT_A_H
AUD_BITCLK_A_H

AUD_SYNC_A_H

MOD_DTO_B_H
MOD_CLKOUT_B_H
MOD_BITCLK_B_H

MOD_SYNC_B_H

AUD_DTI_A_H

MOD_DTI_B_H

GPIO_15_H

GPIO_12_H

EXT_12_H

PWR_PENDINT_H

GPIO_EXT_00_H

EXT_16_H

EXT_13_H

EXT_10_H

EXT_03_H
EXT_04_H

EXT_07_H

EXT_06_H

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Pull-up/down to be provided by audio page.

(I2_XTAL)

Page Notes

DIFFERENTIAL_PAIR

SPACING

PHYSICAL

NET_TYPE

(I2_XTAL)

ELECTRICAL_CONSTRAINT_SET

(Int PU - rev 1)

Pull-up/down to be provided by audio page. (*) - See above

Internal pull-up to 3.3V PWRON

GPIO_12 0x0_0076 N/A Yes

(Int PU - rev 1)

(Int PU)

GPIO_16

GPIO_15

GPIO_12

GPIO_11

GPIO_09

GPIO_04

GPIO_05
GPIO_06

Alternate GPIO Functions

Use MAKE_BASE to force net name

GPIO_EXT_00

EXT_16

EXT_15

EXT_14

EXT_12

Pull-up/down to be provided by audio page.

Internal pull-up to 3.3V PWRON

10K Pull-up to 3.3V on I2 PCI page.

Pull-up/down to be provided by audio page. (*) - See above

GPIO_01 0x0_006B 15 (0x0F) No SPIREQ (When SPISReqEn = 1)
GPIO_02 0x0_006C 16 (0x10) Yes PCI_GNT_2_L (When PCI1_Slot2En = 10)

EXT_13 0x0_0065 59 (0x3B) No PCI_GNT_2_L (When PCI1_Slot2En = 11)
EXT_14 0x0_0066 60 (0x3C) No PCI_REQ_2_L (When PCI1_Slot2En = 11)

EXT_00 0x0_0058 46 (0x2E) Yes PCI_REQ_2_L (When PCI1_Slot2En = 10)

(Int PU)

EXT_16 0x0_0068 62 (0x3F) Yes

(Int PU - rev 1)

Pull-up/down to be provided by design.

Pull-up/down to be provided by audio page.

Pull-up/down to be provided by audio page.
Pull-up/down to be provided by audio page.

Pull-up/down to be provided by audio page.

Pull-up/down to be provided by audio page.

10K Pull-up to 3.3V on I2 PCI page.

Internal pull-up to 3.3V PWRON

(I2_EXT_14)

10K Pull-up to Enet OVdd on I2 Enet page.

Internal pull-up to 3.3V PWRON

(I2_EXT_13)

(I2_EXT_08)

10K Pull-up to 3.3V on I2 AGP page.

Internal pull-up to 3.3V PWRON

Pull-up/down to be provided by audio page.

Pull-up/down to be provided by audio page.

Internal pull-up to 3.3V PWRON

GPIO Pull-ups / Pull-downs

GPIO_EXT_03

GPIO_EXT_02

GPIO_EXT_01

EXT_13

EXT_11

EXT_10

EXT_09

EXT_08

EXT_07

EXT_06

EXT_01
EXT_02
EXT_03
EXT_04

EXT_00

EXT_05

GPIO_03 0x0_006D 17 (0x11) Yes

(Int PU)

(Int PU)

Pin Address MPIC Int Int PU? Alt Func

EXT_07 0x0_005F 53 (0x35) No

EXT_05 0x0_005D 51 (0x33) No
EXT_06 0x0_005E 52 (0x34) No

EXT_01 0x0_0059 47 (0x2F) Yes

EXT_03 0x0_005B 49 (0x31) No
EXT_04 0x0_005C 50 (0x32) No

EXT_10 0x0_0062 56 (0x38) No

EXT_09 0x0_0061 55 (0x37) Yes

EXT_02 0x0_005A 48 (0x30) No

(Int PU)

(Int PU)

EXT_15 0x0_0067 61 (0x3D) No

GPIO_00 0x0_006A 14 (0x0E) No

GPIO_15 0x0_0079 N/A No

GPIO_06 0x0_0070 N/A No

GPIO_04 0x0_006E N/A No

GPIO_09 0x0_0073 N/A No
GPIO_11 0x0_0075 N/A Yes

GPIO_16 0x0_007A N/A No

GPIO_05 0x0_006F N/A No

(Int PU)

Put crystal circuit close to I2

Crystal load capacitance is 16pF

(Int PU)

EXT_08 0x0_0060 54 (0x36) Yes

Pin Direction

Signal Direction

EXT_12 0x0_0064 58 (0x3A) Yes

EXT_11 0x0_0063 57 (0x39) Yes

(Master)

(Master)

(Slave)

(Slave)

- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI)

is used, or else =PP3V3_PWRON_I2_GPIO.

Should be same as =PP3V3_PCI if slot E

Signal aliases required by this page:

Power aliases required by this page:

Use for I2 revisions > 1.0

- I2_REV1_NOT

BOM options provided by this page:

(NONE)

- =PP3V3_PWRON_I2_GPIO

(*) - Rev 1.0: Internal pull-up to 3.3V PWRON

(*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

(*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

OMIT

I2

BGA

AL6
AL5

AL2

AE5

AL1

AL3

AG5

AL4AM1

AK3

AC12

AC13

AH7
AH6

AH5 AK5

AK6

AK7

AL7

G6

G5J5
J6

J7

AP1

AN2

AN4AN6

AN3

F1

J3

F4

J1

AH3

AH4

AJ1

AK2

AG6

AG7

G2

AG8

G1

G3

M1

G4

H1

AE4

AF1

AG2

AG3

AG1

AK1

AG4

AN33

AR33

J2

AH2

AT19

AK4

AH1

D2

C1E1

F2

F3

U2100

50V

22pF

CERM
402

5%

2

1

C2410

402

5%
1/16W
MF-LF

0

2

1

R2411

18.432M

CRITICAL

8X4.5MM-SM1

21

Y2410

5%

402

CERM

22pF

50V

2

1

C2411

NO STUFF

5%
1/16W
MF-LF

402

10M

21

R2410

5%
1/16W
MF-LF

402

10K

2

1

R2400

5%
1/16W
MF-LF
402

10K

2

1

R2401

SM-LF

10K

1/16W

5%

72

RP2450

SM-LF

10K

1/16W

5%

81

RP2450

10K

402

MF-LF

1/16W

5%

2

1

R2490

SM-LF

5%

1/16W

10K

63

RP2450

5%
1/16W
MF-LF

10K

402

I2_REV1_NOT

21

R2455

SM-LF

5%

1/16W

10K

54

RP2450

5%

10K

1/16W
MF-LF

402

I2_REV1

21

R2451

5%

10K

1/16W
MF-LF

402

I2_REV1

21

R2452

SYNC_DATE=N/A

SYNC_MASTER=N/A

I2 Miscellaneous

051-6929

03

115

24

MMM_FFIRQ_L

=PP3V3_PWRON_I2_MISC

I2_GPIO_EXT_02

VIA_ACK_L
VIA_CLK

I2_TST_TEI

=JTAG_I2_TDI

I2_CLK18M_XOUT

=SPI_I2_MOSI

=JTAG_I2_TRST_L

=I2_STOPXTAL_L

SYS_WARM_RESET_L

=I2_STOPCPU_L

=JTAG_I2_TMS

=SPI_I2_CLK

=JTAG_I2_TCK

VIA_PMU_TO_SB

I2S1_DEV_TO_SB_DTI

I2S0_SB_TO_DEV_DTO_R
I2S0_MCLK_R

I2S0_SYNC_R

I2S1_SB_TO_DEV_DTO_R
I2S1_MCLK_R
I2S1_BITCLK_R
I2S1_SYNC_R

I2S0_BITCLK_R

FW_POWERDOWN

AUDIO_CODEC_RESET_L

PMU_INT_L

AUDIO_LI_DET_L

AUDIO_LO_DET_L

PCI_SLOTE_REQ_L

PCI_SLOTE_GNT_L

MODEM_RING2SYS_L

MMM_FFIRQ_L

AUDIO_I2S_DTIB_SEL

PCI_SLOTA_INT_L

AGP_INT_L

AUDIO_LO_OPTICAL_PLUG_L

=I2C_I2_SB_SDA

=I2C_I2_SB_SCL

=I2C_I2_NB_SDA

=I2C_I2_NB_SCL

SCCA_TXD_L

VIA_SB_TO_PMU
VIA_REQ_L

NB_SUSPENDREQ_L

I2_CLK18M_XOUT_R
I2_CLK18M_XIN

=PP3V3_PWRON_I2_MISC

I2_TST_PLLEN

=SPI_I2_MISO

PCI_SLOTE_INT_L

PCI_SLOTE_GNT_L

=SPI_I2_REQ

PCI_SLOTE_REQ_L

=PP3V3_I2_PCISLOTEGPIOS

AUDIO_SPDIFRX_RESET_L

I2_GPIO_EXT_02

AUDIO_LO_MUTE_L
AUDIO_SPKR_MUTE_L

I2_EXT_14

PCI_SLOTE_INT_L

=JTAG_I2_TDO

I2_GPIO_11

FW_POWERDOWN

AUDIO_LI_OPTICAL_PLUG_L

MODEM_RESET_L

AUDIO_EXT_MCLK_SEL

I2S0_DEV_TO_SB_DTI

SCCA_RXD

TP_I2_PENDINT

SYS_WATCHDOG

NB_SUSPENDACK_L

SYS_PME_L

I2_CLK18M_XIN

XTALXTAL

I2_CLK18M_XOUT

XTALXTAL

I2_XTAL

XTAL XTAL

I2_CLK18M_XOUT_R

I2S1_DTI

I2S I2S

I2S1_DEV_TO_SB_DTI

I2S0_SYNC

I2S I2S

I2S0_SYNC_R

I2S0_MCLK

I2S I2S

I2S0_MCLK_R

I2S1_BITCLK

I2S1_BITCLK_R

I2SI2S

I2S1_SB_TO_DEV_DTO_R

I2S1_DTO

I2SI2S

I2S0_SB_TO_DEV_DTO_R

I2S0_DTO

I2S I2S

I2S0_BITCLK

I2S I2S

I2S0_BITCLK_R

I2S0_DEV_TO_SB_DTI

I2S0_DTI

I2SI2S

I2S1_SYNC

I2S1_SYNC_R

I2SI2S

I2S1_MCLK

I2S1_MCLK_R

I2SI2S

PMU_SB_NMI_L

I2_EXT_13

AUDIO_GPIO_11

=SPI_I2_REQ

MMM_SIRQ_L

I2_EXT_08

PCI_SLOTD_INT_L

74

74

25

22

22

62

30

22

22

22

22

22

22

22

22

74

74

74

22

22

30

25

74

59

44

74

24

22

22

22

22

22

74

22

74

74

22

74

74

22

24

62

30

22

22

22

22

22

22

22

22

22

74

22

59

22

10

11

25

25

9

22

9

11

25

11

9

9

25

22

6

6

6

6

6

6

6

6

22

7

25

7

7

11

11

25

22

7

11

43

7

8

8

8

8

7

25

25

25

22

22

10

11

11

11

11

10

7

11

7

7

11

9

11

22

7

30

7

7

7

25

25

25

22

22

22

22

6

6

6

6

6

6

7

6

6

25

7

11

25

11

CLKIN

CLKOUT

1Y3

GND

1Y2

1Y1

1Y0

VDD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

DIFFERENTIAL_PAIR

Page Notes

- =PP3V3_PWRON_I2_GPIO

Power aliases required by this page:

Should be same as =PP3V3_PCI if slot E

- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI)

Use for I2 revisions > 1.0

Signal aliases required by this page:

is used, or else =PP3V3_PWRON_I2_GPIO.

- I2_REV1_NOT

BOM options provided by this page:

(NONE)

CRITICAL

SOIC

CDCVF2505

6

4

8

1

7

5

2

3

U2500

402

CERM

10V

20%

0.1uF

2

1

C2501

NO STUFF

402

CERM

20%
50V

0.001uF

2

1

C2502

1uF

10%

6.3V
CERM

402

2

1

C2500

I72

I73
I74

I75
I76

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6929

03

115

25

PCI Clock Buffer

=PCI_CLK33M_ZDB_IN

=PCI_CLK33M_ZDBOUT_R<3>

=PCI_CLK33M_ZDBOUT_R<2>

=PCI_CLK33M_ZDBOUT_R<1>

=PCI_CLK33M_ZDBOUT_R<0>

PCI_CLK_DELAY_ADJ

=PP3V3_PCI_ZDB

CLOCK CLOCK

=PCI_CLK33M_ZDBOUT_R<0>

PCI_ZDBOUT0

CLOCKCLOCK

=PCI_CLK33M_ZDB_IN

CLOCK CLOCK

=PCI_CLK33M_ZDBOUT_R<1>

PCI_ZDBOUT1

CLOCK CLOCK

=PCI_CLK33M_ZDBOUT_R<2>

PCI_ZDBOUT2

CLOCKCLOCK

=PCI_CLK33M_ZDBOUT_R<3>

PCI_ZDBOUT3

23

23

23

23

23

23

23

23

23

23

11

11

11

11

11

10

11

11

11

11

11

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(WAS COMM_TRXC)

(WAS COMM_GPIO_L)

(WAS PMU_BOOT_CE)

NC

NC

NC

SERIAL DEBUG INTERFACE

PMU RESET CIRCUIT

PLACE "SYS RESET" IN SILK NEAR RESISTOR

PLACE "PMU RESET" IN SILK NEAR RESISTOR

DEBUGGING AIDS

PLACE ON TOP SIDE NEAR FRONT EDGE OF BOARD

PLACE "POWER BTN" IN SILK NEAR RESISTOR

CHARGE LED

SLEEP LED

100

5%
1/16W
MF-LF

402

2

1

R2600

470K

5%
1/10W
MF-LF

603

OMIT

21

R2691

603

MF-LF

1/10W

5%

470K

OMIT

21

R2692

2N7002DW-X-F

SOT-363

1

2

6

Q2680

100K

5%
1/16W
MF-LF
402

2

1

R2680

BAS16TW-X-F

SOT-363
6 1

DP2680

2N3906

SOT23-LF

2

3

1

Q2600

SOT-363

BAS16TW-X-F

5 2

DP2680

SOT-363

2N7002DW-X-F

4

5

3

Q2680

402

MF-LF

1/16W

5%

2.2K

2

1

R2601

470K

5%
1/16W
MF-LF
402

2

1

R2610

4.7K

5%
1/16W
MF-LF

402

R2602

2N7002

SOT23-LF

2

1

3

Q2601

CRITICAL

DEVELOPMENT

QT500166-L020

M-ST-SM

9

87

65

43

2

1615

1413

1211

10

1

J2690

DEVELOPMENT

10K

5%
1/16W
MF-LF
402

2

1

R2696

DEVELOPMENT

10K

5%
1/16W
MF-LF

402

2

1

R2695

603

MF-LF

1/10W

5%

470K

OMIT

21

R2690

LEDs/Reset/Debug

051-6929

03

115

26

SYNC_MASTER=N/A

SYNC_DATE=N/A

PMU_RESET_L

PMU_CUSTOMER_RESET

SLEEP_LED_SW_L

SYS_LED

=SLEEP_LED_IOUT

=PP5V_PWRON_SLEEPLED

SLEEP_LED_L

SYS_ONEWIRE

SYS_CHARGE_LED_L

=PP3V3_ALL_PMU

=PP3V3_ALL_PMU

SYS_AC_DET_L

PMU_RESET_L

SYS_POWER_BUTTON_L

SYS_RESET_BUTTON_L

SYS_POWER_BUTTON_L

SYS_BATT0_DET_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

SLEEP_LED_I

=PP3V3_ALL_DEBUG

SCCA_TXD_L

PMU_BOOT_SCLK
PMU_BOOT_CNVSS

PMU_RESET_L

PMU_BOOT_BUSY

PMU_BOOT_RXD

PMU_BOOT_TXD

PMU_BOOT_RP_L

SCCA_RXD

NO_TEST=TRUE

COMM_DTR_L

NO_TEST=TRUE

COMM_RTS_L

57

57

36

36

25

25

30

30

25

74

24

24

25

25

36

25

25

22

25

22

24

25

11

10

25

7

10

10

12

24

24

25

24

12

10

7

25

25

24

25

25

25

25

7