Apple iMac A1419 Schematic

J95 MLB SKL EMERALD

1 OF 93

LAST_MODIFICATION=Thu Feb 12 14:48:08 2015

CPU & CHIPSET: CPU CORE VR (VCC)

CPU & CHIPSET: PCH 1V0 VR

CPU & CHIPSET: CPU CORE VR (VCCSA)

DISPLAY: LCD Backlight Driver (LP8565)

DRAM: SO-DIMM Connector A Slot0

SMC: SMBus Connections

SMC: Controller Support

USB-A: EXTERNAL USB PORTS A & B

samihan_mlb_slk

samihan_mlb_slk

CAMERA: Controller Support

DEBUG: LEDs

BOM Configuration

SCHEM,K72,MLB ULTIMATE

HDD: SSD Temp Sense

01/30/2015

samihan_mlb_slk

DRAM: SO-DIMM CONNECTOR B SLOT1

DRAM: SO-DIMM Connector A Slot1

01/30/2015

01/30/2015

samihan_mlb_slk

TBT/DP: Host (1 of 2)

WIRELESS: Airport/Bluetooth

samihan_mlb_slk

35

01/30/2015

PLATFORM POWER: FET-Controlled S0 and S4

samihan_mlb_slk

AUDIO: Detects/Grounding

samihan_mlb_slk

samihan_mlb_slk

DRAM: VREF/VTT EN

6

TBT/DP: Connector A

samihan_mlb_slk

samihan_mlb_slk

67

69

68

64

65

66

63

62

61

60

56

55

54

53

52

51

50

47

46

45

44

43

42

41

40

39

38

37

35

34

33

32

30

29

28

27

26

25

24

23

22

20

19

18

16

15

14

13

11

10

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_skl

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/15/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

9

7

6

5

4

3

2

1

jerrychow_skl

jerrychow_skl

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

12/12/2014

12/12/2014

103

104

105

106

107

109

110

111

112

113

114

119

120

82

84

85

86

87

88

90

92

93

96

97

99

101

102

jerrychow_skl

jerrychow_skl

jerrychow_skl

jerrychow_skl

12/12/2014

12/12/2014

12/12/2014

12/12/2014

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

mlb_hsw_em

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

jerrychow_skl

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

02/02/2015

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/12/2014

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

samihan_mlb_skl

samihan_mlb_skl

01/15/2015

01/15/2015

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

01/30/2015

01/30/2015

01/30/2015

01/30/2015

70

71

72

73

75

77

78

81

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

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01/30/2015

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

74

73

72

71

70

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

41

40

39

38

37

36

34

33

32

31

30

29

28

27

26

25

23

22

21

20

19

18

17

16

15

14

12

11

10

9

8

7

5

4

1

J95 RULE DEFINITIONS

Unused Signal Aliases

Signal Aliases

GRAPHICS: GPU VDDCI VR

GRAPHICS: GPU VDDQ VR

GRAPHICS: GPU CORE VR (PHASES 4-6)

GRAPHICS: GPU CORE VR (PHASES 1-3)

GRAPHICS: GPU CORE VR

GFX: Emerald Gnds & Unused

GFX: Emerald GPIOS,CLK,STRAPS

GFX: Emerald IntDP/TBT DP

GDDR5 Frame Buffer B

GDDR5 Frame Buffer A

GFX: Emerald FRAME BUFFER

GFX: Emerald CORE/FB POWER

GFX: Emerald PCIe

PLATFORM POWER: PM Power Good

PLATFORM POWER: Regulator Enables

DISPLAY: Backlight Driver 2

PLATFORM POWER: 3.3V S5/5V S4 VR

CPU & CHIPSET: CPU VDDQ VR

CPU & CHIPSET: CPU CORE VR (VCCGT)

CPU & CHIPSET: CPU CORE VR

PLATFORM POWER: Connectors / VReg G3Hot

AUDIO: Speaker ID

Audio: Spkr/Mic Conn.

AUDIO: Jack, Mikey, CHS Switch

AUDIO: RIGHT SPKR AMP

AUDIO: LEFT SPKR AMP

AUDIO: HEADPHONE AMP

AUDIO: CODEC/REGULATORS

FAN: System Fan

CPU & CHIPSET: SPI and Debug Connector

SMC: Controller

USB-A: EXTERNAL USB PORTS C & D

DISPLAY: MUXing

DISPLAY: Support

CAMERA: Controller

SD CARD: Connector

ETHERNET: Support & Connector

ETHERNET: PHY (CAESAR IV)

SDD/HDD:SATA/SSD Connectors

Thunderbolt: Power Support

CPU & CHIPSET: Chipset Support

CPU & CHIPSET: XDP

CPU & CHIPSET: PCH Grounds

CPU & CHIPSET: Clocks/HDA/JTAG

CPU & CHIPSET: CPU Power

CPU & CHIPSET: CPU DMI/PEG/FDI/RSVD

SENSORS: Temperature Sensors

SENSORS: I and V Sense(Continued)

SENSORS: I and V Sense

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

TBT/DP: Host (2 of 2)

DRAM: ALIASES AND BITSWAPS

DRAM: SO-DIMM CONNECTOR B SLOT0

CPU & CHIPSET: Project Chipset Support

samihan_mlb_slk

CPU & CHIPSET: CPU VCCIO VR

J95 RULE DEFINITIONS

samihan_mlb_slk

GRAPHICS: GPU 1V8 VR

75

01/30/2015

samihan_mlb_slk

24

CPU & CHIPSET: CPU Ground

01/30/2015

01/30/2015

samihan_mlb_slk

TBT/DP: Connector B

TBT/DP: DDC Crossbar

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

Power Connectors/Aliases

GRAPHICS: GPU 0V95 VR

samihan_mlb_slk

13

samihan_mlb_slk

samihan_mlb_slk

CPU & CHIPSET: CPU Clock/Misc/JTAG/CFG

8

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

2

3

CPU & CHIPSET: PCH RTC/DMI/PM/CPU_Misc

CPU & CHIPSET: PCH GPIO/Misc

CPU & CHIPSET: PCH Power/Decoupling

42

69

MECHANICAL: Holes/PD parts

CPU & CHIPSET: PCH PCI-E/USB

CPU & CHIPSET: CPU Decoupling

76

12

samihan_mlb_slk

CPU & CHIPSET: DDR3L Interfaces

SCHEM,MLB,SKYLAKE,EMERALD,J95

051-00673

2015-02-12

1 OF 121

0.24.0

LAST_MODIFIED=Thu Feb 12 14:48:08 2015

SCHEM,J95, mlb_skl_EM

TITLE=J95_skl_am
ABBREV=DRAWING

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

ECNREV DESCRIPTION OF REVISION

DRAWING TITLE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

CK
APPD

2 1

1245678

B

D

6 5 4 3

C

A

PAGE

C

A

D

DATE

R

SHEET

D

SIZEDRAWING NUMBER

BRANCH

7

B

3

II NOT TO REPRODUCE OR COPY IT

IV ALL RIGHTS RESERVED

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

SYNCCONTENTS

SYNCCONTENTSPAGE

<CSA>

PAGE

DATE

DATE

<CSA>

DRAWING

DRAWING

www.laptoprepairsecrets.com

CPU SOCKET

J95 ALTERNATES

J95 SCHEMATIC / PCB #'S

GPU and VRAM

CPUs

BOM Variants

.

BOM Groups

Programmable Parts

Bar Code Labels / EEEE #'s

ASICs

2 OF 93

2 OF 121

0.24.0

051-00673

J95_PROGPARTS SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG

311S0370

311S00004

Config. Logic GateALL

138S0750138S0855

4.7uF 0402ALL

J95_COMMON

COMMON,VR_BULKCAP:CURRENT,ALTERNATE,J95_PROGPARTS,GPU_AM_EM,GPU_Emerald,XDP,SPEAKERID,FBVDDQ_DFLT:1V5,SMCREG:SUP

PCBA,MLB SKL,EMERALD PROA,VRAM_HYNIX,2GB,J95

J95,MLB_CMNPTS,CPU:BEST,SSD:Y,GPU:EMERALD_PROA,FB:4G_HYNIX,EEEE:GHN4

639-00957

1

337S00114

CPU

CRITICAL

CPU,SKL,QH8E,ES,P0,4/2,2.2,95W,LGA1151

CPU:ULT

CPU,SKL,QHQF,ES2,Q0,2.6G,95W,LGA1151

CPU

CPU:CTO_2.6G

CRITICAL

337S00122

1

CPU,SKL,QH73,ES,P0,4/2,2.3,95W,LGA1151

CRITICAL1337S00113

CPU

CPU:CTO

XDP_CONN,T112,DEVEL_AUDIO

J95_DEVEL

BOM Configuration

SYNC_MASTER=J17_DINI SYNC_DATE=03/15/2013

378S0391 378S0390

DEGUG LEDSALL

311S00008

311S0271

AND GATEALL

376S00016

ALL MOSFET,P-CH,20V,1A

376S0644

SOCKET.MOLEX,LGA1151,H4

CRITICAL

U05001

511S00002

J95_COMMON

PCBA,MLB_SKL,COMMON PARTS,J95

685-00062

376S00015

XSTR,FET,DL NCH,60V

376S0610

ALL

138S1103

4.7uF 0402

138S0719

ALL

107S0240107S0255

Alt 1mOhm sense

ALL

107S00029107S00030

ALL

Alt 5mOhm sense

ALL197S0479

12MHZ CAM/NXP XTAL

197S0478

377S0126377S0147 ALL

USB Diode Array

CRITICALPCBF,MLB SKL EM,J95820-00291 1 J95PCB1

LABEL,MLB,2D EEEE_GHN5 EEEE:GKCV

CRITICAL825-7896

1

CPU,SKL,QH8F,ES2,P0,4/2,2.2GHZ,65W,LGA1151

CPU:BEST

CRITICAL

337S00121

1

CPU

CRITICAL

337S00124

1

U1100

IC,PCH-H,SKL,SUPRSKU,C0,QHPT,ES2,BG1151

343S0616

1

IC,BCM57766A1,ENET&SD,8X8

U3900

CRITICAL

353S3328

353S00095

2:4 Diff MUXALL

132S0448132S0447

ALL

0.1uF 0201

311S0377

AND GATEALL

311S0250

128S0220128S0398

ALL 3.3V INPUT CAP

341S3778 IC,CAMERA FLASH,V7230,J16/J17

1 U4202

CRITICAL CAMROM:PROG

J95,MLB_CMNPTS,CPU:CTO_2.6G,SSD:Y,GPU:EMERALD_PROA,FB:4G_HYNIX,EEEE:GKCT

639-01039 PCBA,MLB SKL,95W,EMERALD PROA,VRAM_HYNIX,2GB,J95

U9200,U9250,U9300,U9350 FB:4G_HYNIX4333S00043 CRITICAL

IC,HYN,GDDR5,4GBIT,64MX32,7GBPS,25NM

376S00001

376S0659

MOSFET,P-CH,20VALL

ALL372S0186

Alternate Temp Diode

372S0185

FB:4G_ELPIDA4333S00044 CRITICALU9200,U9250,U9300,U9350

IC,ELP,GDDR5,4GBIT,64MX32,7GBPS,25NM

825-7896

LABEL,MLB,2D EEEE:GHN4EEEE_GHN41

CRITICAL

SCH,MLB SKL EM,J95 CRITICAL051-00673 SCH11 J95

155S0830 155S0316

FERR BD,600 OHM,25,0.5A

ALL

138S0775138S0860

Single-source 1uF 402

ALL

138S0638 10uF Caps138S0681 ALL

341S3912

IC,ENETROM,ADESTO,V1,15,J78

U3990

341S00016

197S0480 ALL197S0481

25MHX PCH XTAL

CRITICALPCBA,MLB SKL EM COMMON PARTS,J95685-00062 CMNPTS MLB_CMNPTS1

985-00098

PCBA,DEV,MLB_SKL,J95

DEVELOPMENT,J95_DEVEL

LABEL,MLB,2D EEEE:GHN5EEEE_GHN5

CRITICAL825-7896

1

825-7896 CRITICAL

LABEL,MLB,2D1 EEEE:GKCTEEEE_GHN4

IC,SMC12-B1,40MHZ/50DMIPS,MCU,157BGA

338S1214

CRITICAL SMC:BLANK

1 U5000

341S00152

TBTROM:PROGCRITICAL

U28901

IC,T29,EPROM,FR,VTBD,POC,J95

335S0915

TBTROM:BLANK

1

CRITICAL

U2890

IC,SRL SPI FLASH ROM,4MBIT,50MHZ,USON8

335S0854

1

CRITICAL

U3990

CIVROM:BLANK

1-MBIT,SPI FLASH ROM SOIC, HF

341S3912

IC,ENET ROM,NUMONYX,V1.15,J16/J16G/J17

CIVROM:PROG

U3990

CRITICAL

1

341S00262

1

SMC:PROG

U5000

CRITICAL

IC,SMC-B1,EXTERNAL,VXXXX,POC-S,J78AM

335S0852

CRITICAL

U4202

CAMROM:BLANK

1

IC,FLASH,SPI,1MBIT,3V3

341S00058

CRITICAL BOOTROM:PROG

1 U5210

IC,EFI,V0174,J78

335S00006

U5210

CRITICAL BOOTROM:BLANK

1

IC,64 MBIT SPI SERIAL FLASH

338S1247 1

U2800

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

CRITICAL

J95,MLB_CMNPTS,CPU:BEST,SSD:Y,GPU:EMERALD_PROA,FB:4G_ELPIDA,EEEE:GHN5

639-00959 PCBA,MLB SKL,EMERALD PROA,VRAM_ELPIDA,2GB,J95

PCBA,MLB SKL,95W,EMERALD PROA,VRAM_ELPIDA,2GB,J95 J95,MLB_CMNPTS,CPU:CTO_2.6G,SSD:Y,GPU:EMERALD_PROA,FB:4G_ELPIDA,EEEE:GKCV639-01040

311S0657

311S00072

ALL Dual 2 INP AND GATE

1 CRITICAL

U8700

337S00077 GPU:EMERALD_PROA

IC,GPU,AMD,ES,EMERALD,PROA,128BIT,FCBGA1093

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_HEAD

BOM NUMBER BOM NAME BOM OPTIONS

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

www.laptoprepairsecrets.com

THIS LED IS DRIVEN BY GPU GPIOS:

GFX_OK_L LOW LIGHTS THE LED DIMLY

CPUVCC_S0_PWRGD Led

VIDEO ON Led

GPU GOOD Led

DP_LINK_OK HIGH LIGHTS THE LED FULLY

ALL_SYS_PWRGD Led

S5 Led

VCCIO_S0_PWRGD Led

P1V0_S3_PWRGD Led

3 OF 93

3 OF 121

0.24.0

051-00673

PM_PGOOD_REG_CPUVCC_S0

=PP3V3_S0_LED

=PP3V3_S4_LED

TCON_BLC_EN_LED

VIDEO_ON_DRAIN

VIDEO_ON_R

GPU_PRESENT_R

=PP3V3_S0_LED

GFX_OK_L

CPUVCC_S0_LED_R

DP_LINK_OK

GPU_PRESENT_DRAIN

=PP3V3_S4_LED

=PP3V3_S5_LED

CORE_VOLTAGES_ON

CORE_VOLTAGES_ON_R

ITS_PLUGGED_IN

ALL_SYS_PWRGD

P1V05_S0_LED_R

PM_PGOOD_FET_P1V0_S3

=PP3V3_S4_LED

VCCIO_S0_LED_R

VCCIO_S0_LED

PM_PGOOD_REG_P0V95_S0

P1V05_S0_LED

=PP3V3_S4_LED

CPUVCC_S0_LED

DEBUG: LEDs

SYNC_DATE=02/11/2013SYNC_MASTER=J17_MAX

4

5

3

Q0302

SOT-363

2N7002DW-X-G

CRITICAL

1

2N7002

SOT23-HF1

Q0304

3

2

2

1

3

Q0305

SOT23-HF1

2N7002

2

1

3

SOT23-HF1

2N7002

Q0306

72 71

K

A

CRITICAL

0805

GRN-6MCD-0.03A

LE0305

SILK_PART=5

2

1

R0307

402

1/16W

1K

MF-LF

5%

73 61

K

A

LE0306

SILK_PART=6

0805

GRN-6MCD-0.03A

CRITICAL

2

1

R0308

MF-LF
402

5%
1/16W

1K

87 72

CRITICAL

SILK_PART=7

0805

GRN-6MCD-0.03A

LE0307

A

K

1K

5%

MF-LF

1/16W

402

R0309

1

2

21

R0305

0402

1/16W

5.6K

1%

MF

80 45

2

1

R0306

0201

MF-LF

0.1%

5K

1/20W

2

1

C0303

0.1UF

NOSTUFF

10V
X5R-CERM

10%

0201

DEFAULT_CAPACITOR_100000pF_2_1

2

1

C0302

0201

10V

0.1UF

10%

DEFAULT_CAPACITOR_100000pF_2_1

X5R-CERM

NOSTUFF

2

1

3

Q0303

2N7002

SOT23-HF1

40

80 45

1

2

6

Q0302

CRITICAL

2N7002DW-X-G

SOT-363

K

A

LE0303

GRN-6MCD-0.03A

0805

SILK_PART=3

CRITICAL

2

1

R0303

MF-LF

1/16W

402

1K

5%

K

A

LE0301

GRN-6MCD-0.03A

CRITICAL

SILK_PART=1

0805

2

1

R0301

1K

1/16W

402

MF-LF

5%

K

A

LE0304

SILK_PART=4

GRN-6MCD-0.03A

0805

CRITICAL

73 44

2

1

R0304

1K

1/16W

402

MF-LF

5%

K

A

LE0302

GRN-6MCD-0.03A

0805

CRITICAL

SILK_PART=2

2

1

R0302

1K

MF-LF

1/16W

402

5%

89 3

89 3

89 3

89 3

89

89 3

89 3

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

S

D

G

D

S

G

D

S

G

D

S

G

IN

IN

IN

IN

D

S

G

IN

IN

S

D

G

IN

www.laptoprepairsecrets.com

APN: 860-00201

860-5675 (PLATED HOLE, 8.41mm pad Top, 8mm pad Bot)

EMERALD EMI FENCE

Display EMI Springs

APN: 870-00886

998-5527 (PLATED HOLES, 8MM DIA, 10MM PAD)

(998-5013. PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT)

T29 BUMPER

998-01489 (PLATED HOLES, 2.1MM INNER DIAMETER, 5.5MM PAD)

CPU Heatsink

4MM PLATED HOLES (998-4158)

HEATPIPE MTG HOLES

998-5014 (PLATED HOLES, 4MM DRILL, 8.5MM TOP, 8MM BOT)

SSD STANDOFF

X238D WIRELESS CARD MTG HOLES

APN: 860-00198

Rear Cover

Rear Cover

860-5674 (PCB STANDOFF)

GPU HEATSINK MOUNTING FEATURES

LOL Boss

4 OF 93

4 OF 121

0.24.0

051-00673

FENCE,GPU,EMERALD,90,J95

860-02579

1 GPU_EmeraldCRITICAL

SF0404

SYNC_DATE=02/11/2013SYNC_MASTER=J17_MAX

MECHANICAL: Holes/PD parts

1

2

2.8OD1.2ID-2.6H-SM

NUT0401

SF0403

1

SM

SPRING-FINGER-6.26H

1

SF0402

SM

SPRING-FINGER-6.26H

SF0401

SPRING-FINGER-6.26H

SM

1

NUT0402

STDOFF-7.14OD10H-TH-1.5-5.2

1

NUT0413

1

5.5OD2.65ID-6.5H-SM

CRITICAL

1

ZH0422

4P3R2P1-5P5B-NSP

ZH0421

1

4P3R2P1-5P5B-NSP

10.0R8.0

1

ZH0426

STDOFF-7P14OD16P45H-TH-1.5-5.2A

ZH0418

1

STDOFF-7P14OD16P45H-TH-1.5-5.2A

ZH0415

1

1

ZH0417

8P5R4P0-8P0B-NSP

ZH0416

1

8P5R4P0-8P0B-NSP

8P5R4P0-8P0B-NSP

ZH0414

1

8P5R4P0-8P0B-NSP

1

ZH0413

ZH0403

8P5R5-NSP

1

8P5R5-NSP

ZH0402

1

8P5R5-NSP

ZH0401

11

8P5R5-NSP

ZH0400

ZH0425

1

6P0R3P2-NSP6P0R3P2-NSP

ZH0424

1

6P0R3P2-NSP

ZH0423

1

6P0R3P2-NSP

ZH0420

1

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

to match Intel symbol.

Port D pins out of order

5 OF 93

051-00673

0.24.0

5 OF 121

=PPVCCIO_S0_CPU

=PEG_D2R_N<0>

DMI_S2N_P<3>

DMI_N2S_P<1>

CPU_EDP_RCOMP

=PEG_R2D_C_N<1>

DMI_N2S_N<3>

DMI_N2S_P<3>

DMI_N2S_P<2>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

=PEG_D2R_P<5>

=PEG_R2D_C_N<13>

=PEG_D2R_P<13>

=PEG_D2R_P<7>
=PEG_D2R_P<8>

=PEG_D2R_P<6>

DMI_S2N_P<1> =PEG_D2R_N<4>

=PEG_R2D_C_N<12>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<14>

=PEG_D2R_P<3>
=PEG_D2R_P<4>

=PEG_D2R_P<9>
=PEG_D2R_P<10>

=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>

=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>

=PEG_R2D_C_P<15>

DMI_N2S_P<0>

=PEG_D2R_P<14>

=PEG_D2R_P<11>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<2>

=PEG_D2R_N<3>

DMI_S2N_N<1>

=PEG_D2R_P<2>

=PEG_D2R_N<12>

=PEG_D2R_N<14>

=PEG_D2R_N<11>

DMI_S2N_N<0>

DMI_S2N_P<0>

=PEG_D2R_N<13>

=PEG_D2R_N<15>

=PEG_R2D_C_N<15>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<5>

=PEG_D2R_N<6>

=PEG_D2R_N<2>

=PEG_D2R_P<1>

=PEG_D2R_P<12>

=PEG_D2R_P<15>

=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>

=PEG_D2R_N<5>

=PEG_D2R_N<9>
=PEG_D2R_N<10>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<9>

=PEG_D2R_P<0>

DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<2>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>

=PEG_D2R_N<1>

CPU_PEG_RCOMP

=PPVCCIO_S0_CPU

SYNC_DATE=06/30/2014SYNC_MASTER=J78_MLB

CPU & CHIPSET: CPU DMI/PEG/FDI/RSVD

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

1/20W
MF
201

2

1

R0510

1%

24.9

PLACE_NEAR=U0500.L7:15MM

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

544753

LGA

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

SKYLAKE_S

OMIT_TABLE

U0500

C13D21

E22

A23

D23

C21

D22

B23

C23

B12
A12

E18

D19

E20

B18

D18

C19

D20

C11
B11

A14

B15

A16

B17

B14

C15

B16

C17

E12
D12

D14

M9

D10

C9

H10

G9

E10

D9

G10

F9

V3

U1

V2

A18

B13

544753

LGA

SKYLAKE_S

OMIT_TABLE

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

Y4
AA5
AB3
AC5

Y3
AA4
AB4
AC4

AC1
AD2
AE1
AF3

AC2
AD3
AE2
AF2

L7

B7
C6
D5
E4
F5
G4
H5
J4
K5
L4
M5
N4
P5
R4
T5
U4

B8
C7
D6
E5
F6
G5
H6
J5
K6
L5
M6
N5
P6
R5
T6
U5

A6
B5
C4
D3
E2
F3
G2
H3
J2
K3
L2
M3
N2
P3
R1
T3

A5
B4
C3
D2
E1
F2
G1
H2
J1
K2
L1
M2
N1
P2
R2
T2

1/20W
MF
201

2

1

R0530

1%

24.9

PLACE_NEAR=U0500.M9:15MM

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

89 17 10 8 5

89 17 10 8 5

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

DIGITAL DISPLAY INTERFACES

10 OF 11

EDP

DDI3_AUXP

DDI1_AUXN

DDI3_TXP[3]

DDI3_TXN[0]

DDI2_TXP[2]
DDI2_TXN[3]
DDI2_TXP[3]

DDI2_TXN[1]

DDI2_TXN[2]

EDP_RCOMP

EDP_AUXP

DDI1_TXP[3]

DDI1_TXP[0]

DDI1_TXN[3]

DDI1_TXN[1]

DDI1_TXN[0]

DDI2_TXP[0]

DDI2_TXN[0]

EDP_DISP_UTIL

DDI1_AUXP

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]

EDP_TXP[2]

EDP_TXN[2]

EDP_TXP[3]

EDP_TXN[3]

EDP_AUXN

DDI2_TXP[1]

DDI1_TXP[1]
DDI1_TXN[2]
DDI1_TXP[2]

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

DDI3_AUXN

DDI2_AUXN
DDI2_AUXP

DDI3_TXP[0]
DDI3_TXN[1]
DDI3_TXP[1]
DDI3_TXN[2]
DDI3_TXP[2]
DDI3_TXN[3]

DMI

PCI EXPRESS BASED INTERFACE SIGNALS

1 OF 11

DMI_TXP[3]

DMI_TXP[2]

DMI_TXN[0]

DMI_TXP[1]

DMI_TXP[0]

DMI_TXN[1]

DMI_RXP[3]

DMI_RXP[2]

DMI_RXN[0]
DMI_RXN[1]
DMI_RXN[2]

DMI_RXP[1]

DMI_RXP[0]

DMI_RXN[3]

PEG_TXP[15]

PEG_TXP[13]

PEG_TXP[12]

PEG_TXP[11]

PEG_TXP[9]

PEG_TXP[8]

PEG_TXP[6]

PEG_TXP[5]

PEG_TXP[3]

PEG_TXP[2]

PEG_TXP[1]

PEG_TXP[0]

PEG_TXN[15]

PEG_TXN[14]

PEG_TXN[13]

PEG_TXN[10]

PEG_TXN[9]

PEG_TXN[8]

PEG_TXN[7]

PEG_TXN[6]

PEG_TXN[5]

PEG_TXN[4]

PEG_TXN[3]

PEG_TXN[2]

PEG_TXN[1]

PEG_RXP[8]

PEG_RXP[1]

PEG_RXP[0]

PEG_RXN[15]

PEG_TXN[0]

PEG_RXP[15]

PEG_RXP[14]

PEG_RXP[13]

PEG_RXP[12]

PEG_RXP[11]

PEG_RXP[10]

PEG_RXP[9]

PEG_RXP[7]

PEG_RXP[6]

PEG_RXP[5]

PEG_RXP[4]

PEG_RXP[3]

PEG_RXP[2]

PEG_RXN[7]

PEG_RXN[2]

PEG_RXN[1]

PEG_RXN[0]

PEG_RXN[3]

PEG_RXN[8]

PEG_RXN[5]
PEG_RXN[6]

PEG_RXN[9]
PEG_RXN[10]
PEG_RXN[11]
PEG_RXN[12]
PEG_RXN[13]
PEG_RXN[14]

PEG_TXP[14]

PEG_TXP[10]

PEG_TXP[7]

PEG_TXP[4]

PEG_TXN[11]
PEG_TXN[12]

PEG_RXN[4]

PEG_RCOMP

DMI_TXN[2]
DMI_TXN[3]

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

DDR VTT CNTL Level Shifting Circuitry

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (default) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

R0624.2:

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION(default) 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED(default) 0 = ENABLED

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION(default) 0 = LANES REVERSED

R0623.1:

R0621.2:

6 OF 93

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.6000

6 OF 121

0.24.0

051-00673

TP_CPU_RSVD_TP3

CPU_CFG<5>

CPU_CFG<18>
CPU_CFG<19>

CPU_VIDSOUT

PM_SYNC

CPU_PECI

TP_CPU_RSVD_TP8

TP_CPU_RSVD_TP7

TP_CPU_RSVD_TP5

TP_CPU_RSVD_TP12
TP_CPU_RSVD_TP13

CPU_PROCHOT_L

=PP1V0_S3_CPU

PM_DOWN

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

CPU_CFG<6>
CPU_CFG<7>

CPU_CFG<16>

CPU_VIDSCLK

XDP_BPM_L<3>

XDP_CPU_TMS

CPU_RESET_L

CPU_CFG<13>

DDR_VTT_CNTL

XDP_BPM_L<1>
XDP_BPM_L<2>

XDP_CPU_TCK

PROC_TRIGIN

XDP_CPU_TDI
XDP_CPU_TDO

CPU_CFG<1>

XDP_CPU_TRST_L

CPU_CFG<11>

CPU_CFG<0>

PROC_TRIGOUTPROC_TRIGOUT_R

XDP_BPM_L<0>

CPU_CFG<15>

CPU_CLK100M_PCI_P

CPU_CLK24M_SSC_P

CPU_CFG<3>
CPU_CFG<4>

CPU_CFG<2>

CPU_SKTOCC_L

TP_CPU_RSVD_TP10

=PP1V0_S3_CPU

CPU_VIDALERT_L

TP_CPU_RSVD_TP9

PM_EN_LDO_DDRVTT_S0_R

DDR_VTT_CNTL_3V3

PM_SLP_S3_L

CPU_PWRGD

CPU_VIDSOUT_R

DDR_VTT_CNTL

=PP3V3_S4_MEMRESET

TP_CPU_RSVD_TP14
TP_CPU_RSVD_TP15

TP_CPU_RSVD_TP6

TP_CPU_RSVD_TP4

CPU_BCLK100M_P

CPU_BCLK100M_N

CPU_PROCHOT_R_L

CPU_CATERR_L

CPU_VIDSCLK_R

CPU_CLK100M_PCI_N

CPU_CLK24M_SSC_N

PM_DOWN_R

TP_CPU_RSVD_TP1
TP_CPU_RSVD_TP2

PM_EN_LDO_DDRVTT_S0

CPU_THRMTRIP_L

CPU_VIDALERT_R_L

CPU_CFG<14>

CPU_CFG<9>
CPU_CFG<10>

CPU_CFG_RCOMP

CPU_CFG<17>

CPU_CFG<12>

CPU_CFG<8>

=PP1V0_S3_CPU

SYNC_MASTER=J78_MLB

CPU & CHIPSET: CPU Clock/Misc/JTAG/CFG

SYNC_DATE=06/30/2014

17

17

72

12

17 12

17

17

17

17 11

17

73 72 45

44 36 12

MF-LF

1/16W

402

R0633

0

5%

12

MF-LF

1/16W

402

1%

PLACE_NEAR=U0500.C39:38mm

1 2

499

R0603

MF-LF

1/16W

402

R0623

5%

2 1

PLACE_NEAR=U0500.E38:12.7mm

0

MF-LF

1/16W

402

2

0

1

R0625

5%

MF-LF

1/16W

402

1%

1

100

2

R0624

PLACE_NEAR=U0500.E40:12.7mm

MF-LF

1/16W

402

1%

PLACE_NEAR=R0603.2:1mm

2

1K

R0601

1

MF-LF

1/16W

402

51

5%

2

R0640

1

MF-LF

1/16W

402

PLACE_NEAR=R0604:5mm

NOSTUFF

R0606

1K

5%

1

2

64

MF-LF

1/16W

402

NOSTUFF

5%

12

R0632

0

MF-LF

1/16W

402

R0631

100K

1

2

5%

MF-LF

1/16W

402

R0630

2

NOSTUFF

100K

5%

1

Q0600

SSM6N37FEAP

4

5

3

SOT563

SSM6N37FEAP

Q0600

SOT563

1

2

6

17

17

17

91 17

17

91 17

91 17

91 17

17

17

17

17

17

17

17

17

17

17

17

17

MF-LF

1/16W

402

2

5%

1K

R0610

1

12

12

MF-LF

1/16W

402

33

R0605

2 1

5%

12

MF-LF

1/16W

402

PLACE_NEAR=U0500.D8:7MM

R0604

20

5%

12

17

17

61

61

61

MF-LF

1/16W

402

220

1

R0622

2

5%

MF-LF

1/16W

402

1%

PLACE_NEAR=U0500.E39:12.7mm

R0621

1

2

56.2

MF-LF

1/16W

402

R0642

2

1K

5%

PLACE_NEAR=U0500.F16:10mm

1

NOSTUFF

F35
F37

J13
J14

AW38

AW2

AV39

AV1

J8

J7

L12

J17

J11

AU9

C40

AU40

K8

J19

J15

D15

H12

H11

L10

B39

L8

AC37
AU10
AU39

AK27

K13

K12

AB37
AB38

AJ24

AC38

AJ25
AJ26
AJ27
AJ28

AK22

AK21

G34

G35

H34

H33

J33
J35
K32

L31

M32

L33

K11

K10

AJ29
AJ30

K34

LGA

544753

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

SKYLAKE_S

OMIT_TABLE

U0500

M11

D8

C39

OMIT_TABLE

F16

G16

U0500

SKYLAKE_S

LGA

544753

W4

D16
D17
G14
H14

D13

H15
F15

H18
G21
H20

E16

H17
G20
F20
F21
H19

G18
F18

J9

K9

W2
W1

G7

E8

B10

AB36

F11

G12
H13

F13

D1
B3

F12

E7

AB35

D11

E38
E40

AC36

W5

E39

E14
F14

F17

F19

H16

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

B9

F8

11

11

11

11

17 12

1

2

201

MF

R0690

1/20W

1%

49.9

PLACE_NEAR=U0500.M11:10mm

11

11

61 45 44

45

45 44 12

45

17 12

MF-LF

1/16W

402

PLACE_NEAR=U0500.F8:25mm

NOSTUFF

R0611

2

1

10K

5%

17

89 10 8 6

6

89 10 8 6

6

89

89 10 8 6

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

BI

OUT

IN

IN

OUT

IN

IN

IN

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

IN

OUT

SG

D

SG

D

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

OUT

IN

OUT

BI

OUT

BI

OUT

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

RESERVED

SYM 11 OF 11

RSVD

RSVD

RSVD

RSVD
RSVD

RSVD
RSVD

RSVD

RSVD

RSVD

RSVD

RSVD
RSVD

RSVD
RSVD

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_TP

RSVD

RSVD

RSVD_TP
RSVD_TP

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD_TP

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_TP

RSVD_TP

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

THERMALPWR

2 OF 11

CLOCK

CFG[0]

BPM_2*

BPM_1*

BPM_0*

PROC_SELECT*

BPM_3*

PROC_PREQ*

PROC_TCK

PROC_TMS

PROC_TDI

PROC_TDO

DDR_VTT_CNTL

CFG[11]

CFG[10]

PCI_BCLKN
PCI_BCLKP

BCLKN

THERMTRIP*

PROC_TRST*

PECI

PM_SYNC

PM_DOWN

PROCPWRGD

SKTOCC*

CLK24N
CLK24P

PROC_TRIGOUT

BCLKP

CFG[2]
CFG[3]
CFG[4]
CFG[5]

CFG[7]
CFG[8]
CFG[9]

CFG[12]

CFG[17]
CFG[18]
CFG[19]

CFG[6]

CFG[14]
CFG[15]
CFG[16]

CFG[13]

CFG[1]

VIDSOUT

VIDSCK

VIDALERT*

CFG_RCOMP

PROC_TRIGIN

PROC_PRDY*

PROCHOT*

CATERR*

RESET*

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

OUT

IN

BI

www.laptoprepairsecrets.com

051-00673

0.24.0

7 OF 121

7 OF 937 OF 93

0.24.0

051-00673

7 OF 121

MEM_A_DQ<61>

MEM_B_DQ<40>

MEM_A_DQ<46>
MEM_A_DQ<47>

MEM_A_DQ<7>

MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>

MEM_A_DQ<55>

MEM_A_DQ<43>

MEM_B_DQ<55>

MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>

MEM_A_DQ<25>

MEM_A_CLK_N<1>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_B_BA<0>

MEM_A_CAS_L

MEM_B_CLK_N<1>

MEM_A_DQ<29>
MEM_A_DQ<30>

MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>

MEM_A_DQ<42>

MEM_A_DQ<44>

MEM_A_DQ<14>
MEM_A_DQ<15>

MEM_B_DQ<63>

MEM_B_DQ<54>

MEM_B_DQ<33>

MEM_A_DQS_P<3>

MEM_A_DQS_P<6>

MEM_A_DQS_N<1>
MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<0>

MEM_A_DQS_N<3>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

TP_DDR1_PAR

MEM_B_RAS_L

MEM_B_ODT<2>

MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_A<3>

MEM_B_DQ<41>

MEM_A_A<1>

MEM_A_RAS_L

MEM_B_CKE<3>

MEM_B_CS_L<0>

TP_DDR0_PAR

MEM_A_CKE<3>

MEM_A_CS_L<1>

MEM_A_CS_L<3>

MEM_A_ODT<2>

MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_DQS_P<2>

MEM_A_A<13>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_DQ<40>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_CLK_N<0>

MEM_A_CLK_N<3>

MEM_A_CKE<2>

MEM_A_CS_L<2>

MEM_A_DQS_P<0>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_DQS_P<1>

MEM_A_DQ<4>

MEM_A_DQ<0>

MEM_A_CLK_N<2>

MEM_B_DQ<36>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_CAS_L

MEM_B_DQS_P<0>

MEM_B_DQ<44>

MEM_B_DQ<11>
MEM_B_DQ<12>

CPU_DIMM_VREFCA

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<60>

MEM_A_DQ<58>

MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<48>

MEM_A_DQ<45>

MEM_A_DQ<41>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<8>

MEM_A_DQ<11>

MEM_A_DQ<16>

MEM_A_DQ<5>
MEM_A_DQ<6>

MEM_A_DQ<3>

MEM_A_DQ<12>

MEM_A_DQ<10>

MEM_A_DQ<19>
MEM_A_DQ<20>

MEM_A_DQ<1>
MEM_A_DQ<2>

MEM_B_DQ<8>

MEM_B_DQ<10>

MEM_B_DQ<13>
MEM_B_DQ<14>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<62>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<57>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<20>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<21>

MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>

MEM_B_DQ<17>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<2>

MEM_B_CKE<1>

MEM_B_CKE<2>

MEM_B_CLK_P<2>

MEM_B_CLK_P<3>

MEM_B_CLK_N<3>

MEM_B_CS_L<3>

MEM_B_CS_L<2>

MEM_B_CS_L<1>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ODT<3>

MEM_B_WE_L

MEM_B_A<0>
MEM_B_A<1>

MEM_B_A<7>
MEM_B_A<8>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<14>
MEM_B_A<15>

MEM_B_DQS_P<1>

MEM_B_DQS_P<6>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>

MEM_B_DQS_N<3>

MEM_B_DQS_N<5>

MEM_A_DQ<53>

MEM_A_DQ<59>

CPU_DIMMB_VREFDQCPU_DIMMA_VREFDQ

MEM_B_DQ<0>

MEM_B_DQ<6>

MEM_B_DQ<15>
MEM_B_DQ<16>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQS_P<7>

MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<4>
MEM_A_A<5>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CLK_P<2>

MEM_A_CKE<1>

MEM_A_CLK_P<1>

MEM_A_CLK_P<3>

MEM_A_ODT<3>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<57>

MEM_A_DQS_P<4>
MEM_A_DQS_P<5>

MEM_A_A<2>

MEM_A_DQS_N<7>

MEM_B_DQ<56>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>

MEM_B_DQS_N<2>

SYNC_DATE=06/30/2014SYNC_MASTER=J78_MLB

CPU & CHIPSET: DDR3L Interfaces

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

23

23

23

24 23

24 23

23

23

23

23

23

23

23

22 21

22 21

22 21

22 21

22 21

22 21

21

21

21

21

21

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

21

21

21

21

21

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

544753

SKYLAKE_S

OMIT_TABLE

LGA

U0500

AY25

AL18
AM18
AW28

AP16

AY29

AV29

AW29

AU29

AM21

AP21

AN21

AP20

AM20

AP22

AN20

AP19

AP17
AN15
AN17
AM15

AD34
AD35

AG35

AH35
AE35
AE34

AG34

AH34
AK35

AL35

AK32

AL32

AK34

AL34

AK31

AL31
AP35
AN35
AN32
AP32
AN34
AP34
AN31
AP31

AL29

AM29

AP29
AR29

AM28

AL28
AR28
AP28
AR12
AP12

AM13

AL13
AR13
AP13

AM12

AL12
AP10
AR10

AR7
AP7
AR9
AP9
AR6
AP6

AM10

AL10

AM7

AL7

AM9

AL9

AM6

AL6
AJ6
AJ7

AE6

AF7
AH7
AH6
AE7

AF6

AF34
AK33
AN33
AN29
AN13
AR8
AM8
AG6
AN26

AF35
AL33
AP33
AN28
AN12
AP8
AL8
AG7
AN25

AR25

AR26
AM26
AM25

AP26

AP25

AL25
AL26

AL19
AL22
AM22
AM23
AP23
AL23
AW26
AY26
AU26
AW27
AP18
AU27
AV27
AR15
AY28
AU28

AM16
AL16
AP15
AL15

AL20

AN18

AC39

AL17

AU37

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

OMIT_TABLE

LGA

544753

SKYLAKE_S

U0500

AT23

AY13
AV15
AW23

AY11

AY24

AW24

AV24

AV25

AV18

AY17

AV16

AU16

AW18

AW17

AW16

AT16

AW12
AU11
AV13
AV10

AE38
AE37
AG38
AG37
AE39
AE40
AG39
AG40

AJ38
AJ37
AL38
AL37
AJ40
AJ39
AL39

AL40
AN38
AN40
AR38
AR37
AN39
AN37
AR39
AR40

AW37

AU38
AV35

AW35

AV37

AT35

AU35

AY8

AW8

AV6
AU6
AU8
AV8

AW6

AY6
AY4
AV4
AT1
AT2
AV3

AW4

AT4
AT3
AP2

AM4

AP3

AM3

AP4

AM2

AP1

AM1

AK3
AH1
AK4
AH2
AH4
AK2
AH3
AK1

AF39
AK39
AP39
AU36
AW7
AU3
AN3
AJ3
AU32

AF38
AK38
AP38
AV36
AV7
AU2
AN2
AJ2
AV32

AU33

AT33

AW33

AV31
AU31
AV33

AW31

AY31

AW15
AU18
AU17
AV19
AT19
AU20
AV20
AU21
AT20
AT22
AY14
AU22
AV22
AV12
AV23
AU24

AW11
AU14
AU12
AY10

AY15

AW13

AC40

AV14

AB40

24

24

22

22

24

24

22

22

24

24

24

24

24

24

22

22

22

22

22

22

20

20 20

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NCNC

NC

MEMORY CHANNEL DDR1

SYM 4 OF 11

DDR1_DQ[18]/DDR0_DQ[50]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_VREF_DQ

DDR1_ECC[7]

DDR1_ECC[3]

DDR1_ECC[2]

DDR1_ECC[1]

DDR1_ECC[0]

DDR1_DQ[62]

DDR1_DQ[61]

DDR1_ECC[4]
DDR1_ECC[5]
DDR1_ECC[6]

DDR1_DQ[63]

DDR1_DQ[47]/DDR1_DQ[31]

DDR1_DQ[46]/DDR1_DQ[30]

DDR1_DQ[45]/DDR1_DQ[29]

DDR1_DQ[44]/DDR1_DQ[28]

DDR1_DQ[43]/DDR1_DQ[27]

DDR1_DQ[42]/DDR1_DQ[26]

DDR1_DQ[41]/DDR1_DQ[25]

DDR1_DQ[57]

DDR1_DQ[56]

DDR1_DQ[55]

DDR1_DQ[54]

DDR1_DQ[53]

DDR1_DQ[52]

DDR1_DQ[51]

DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]

DDR1_DQ[50]

DDR1_DQ[49]

DDR1_DQ[48]

DDR1_DQ[40]/DDR1_DQ[24]

DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]

DDR1_DQ[39]/DDR1_DQ[23]

DDR1_DQ[38]/DDR1_DQ[22]

DDR1_DQ[37]/DDR1_DQ[21]

DDR1_DQ[36]/DDR1_DQ[20]

DDR1_DQ[35]/DDR1_DQ[19]

DDR1_DQ[34]/DDR1_DQ[18]

DDR1_DQ[33]/DDR1_DQ[17]

DDR1_DQ[28]/DDR0_DQ[60]

DDR1_DQ[26]/DDR0_DQ[58]

DDR1_DQ[23]/DDR0_DQ[55]

DDR1_DQ[22]/DDR0_DQ[54]

DDR1_DQ[20]/DDR0_DQ[52]

DDR1_DQ[25]/DDR0_DQ[57]

DDR1_DQ[24]/DDR0_DQ[56]

DDR1_DQ[21]/DDR0_DQ[53]

DDR1_DQ[9]/DDR0_DQ[25]

DDR1_DQ[8]/DDR0_DQ[24]

DDR1_DQ[7]/DDR0_DQ[23]

DDR1_DQ[6]/DDR0_DQ[22]

DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_DQ[2]/DDR0_DQ[18]
DDR1_DQ[3]/DDR0_DQ[19]
DDR1_DQ[4]/DDR0_DQ[20]

DDR1_DQ[19]/DDR0_DQ[51]

DDR1_ALERT*

DDR1_CKN[0]

DDR1_CKE[0]

DDR1_CKP[0]

DDR1_CKP[1]

DDR1_CKN[1]

DDR1_CKN[2]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKP[2]

DDR1_CKN[3]

DDR1_CS_3*

DDR1_CS_2*

DDR1_ODT[0]
DDR1_ODT[1]

DDR1_ODT[3]

DDR1_ODT[2]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_PAR

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[3]
DDR1_MA[4]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT*

DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSP[6]

DDR1_DQSP[8]

DDR1_DQSP[7]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSN[6]
DDR1_DQSN[7]
DDR1_DQSN[8]

DDR1_DQ[27]/DDR0_DQ[59]

DDR1_CS_1*

DDR1_RAS*/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE*/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS*/DDR1_CAB[1]/DDR1_MA[15]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_CS_0*

DDR1_CKP[3]
DDR1_CKE[3]

DDR1_DQ[17]/DDR0_DQ[49]

DDR1_DQ[16]/DDR0_DQ[48]

DDR1_DQ[15]/DDR0_DQ[31]

DDR1_DQ[14]/DDR0_DQ[30]

DDR1_DQ[13]/DDR0_DQ[29]

DDR1_DQ[12]/DDR0_DQ[28]

DDR1_DQ[11]/DDR0_DQ[27]

DDR1_DQ[10]/DDR0_DQ[26]

DDR1_DQ[5]/DDR0_DQ[21]

SYM 3 OF 11

MEMORY CHANNEL DDR0

DDR0_ALERT*

DDR0_ODT[2]
DDR0_ODT[3]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSN[8]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_CAS*/DDR0_CAB[1]/DDR0_MA[15]

DDR0_RAS*/DDR0_CAB[3]/DDR0_MA[16]

DDR0_DQ[46]/DDR1_DQ[14]

DDR0_CKE[3]

DDR0_CS_0*

DDR0_WE*/DDR0_CAB[2]/DDR0_MA[14]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQ[2]

DDR0_DQ[1]

DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

DDR0_DQ[61]/DDR1_DQ[45]

DDR_VREF_CA

DDR0_ECC[7]

DDR0_ECC[2]

DDR0_ECC[5]
DDR0_ECC[6]

DDR0_ECC[4]

DDR0_ECC[3]

DDR0_ECC[1]

DDR0_ECC[0]

DDR0_DQ[45]/DDR1_DQ[13]

DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]

DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]

DDR0_DQ[44]/DDR1_DQ[12]

DDR0_DQ[43]/DDR1_DQ[11]

DDR0_DQ[42]/DDR1_DQ[10]

DDR0_DQ[41]/DDR1_DQ[9]

DDR0_DQ[40]/DDR1_DQ[8]

DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]

DDR0_DQ[26]/DDR0_DQ[42]

DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]

DDR0_DQ[22]/DDR0_DQ[38]

DDR0_DQ[21]/DDR0_DQ[37]

DDR0_DQ[20]/DDR0_DQ[36]

DDR0_DQ[19]/DDR0_DQ[35]

DDR0_DQ[10]

DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]

DDR0_DQ[0]

DDR0_DQ[3]

DDR0_DQ[9]

DDR0_DQ[7]

DDR0_DQ[6]

DDR0_DQ[5]

DDR0_DQ[4]

DDR0_DQ[18]/DDR0_DQ[34]

DDR0_DQ[17]/DDR0_DQ[33]

DDR0_DQ[16]/DDR0_DQ[32]

DDR0_DQ[11]

DDR0_DQ[8]

DDR0_DQ[58]/DDR1_DQ[42]

DDR0_DQ[57]/DDR1_DQ[41]

DDR0_DQ[56]/DDR1_DQ[40]

DDR0_DQ[55]/DDR1_DQ[39]

DDR0_DQ[54]/DDR1_DQ[38]

DDR0_DQ[53]/DDR1_DQ[37]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[8]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT*

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

DDR0_MA[3]
DDR0_MA[4]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_PAR

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_ODT[0]
DDR0_ODT[1]

DDR0_CS_1*
DDR0_CS_2*
DDR0_CS_3*

DDR0_CKN[3]

DDR0_CKP[3]

DDR0_CKP[2]
DDR0_CKE[2]

DDR0_CKE[1]

DDR0_CKN[2]

DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CKE[0]

DDR0_CKP[0]

DDR0_CKN[0]

DDR0_VREF_DQ

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUTOUT

www.laptoprepairsecrets.com

8 OF 93

0.24.0

8 OF 121

051-00673

=PPVCCSA_S0_CPU

=PPVCCIO_S0_CPU

PM_VCCST_PWRGD

=PPVCC_S0_CPU

VCCSA_SENSE

PM_VCCST_PWRGD_CPU

=PPVCC_S0_CPU

=PPVDDQ_S3_CPU

=PP1V0_S3_CPU

VCCIO_SENSE

=PPVCCSA_S0_CPU

VSS_SAIO_SENSE

=PP1V0_S3_CPU

VSS_SENSE

VCCGT_SENSE

=PPVCCIO_S0_CPU

VCC_SENSE

=PPVCCGT_S0_CPU

=PPVCC_S0_CPU

=PPVDDQ_S3_CPU

=PPVCCGT_S0_CPU

VSSGT_SENSE

SYNC_DATE=06/30/2014SYNC_MASTER=J78_MLB

CPU & CHIPSET: CPU Power

1%

1

2

402

1/16W
MF-LF

2.8K

R0808

MF-LF

1/16W

1%

402

2

1

6.04K

R0807

5%

201

MF

100

2

1

1/20W

R0806

MF
201

2

1

100

R0805

1/20W

5%

5%

100

1

2

201

MF

R0804

1/20W

100

MF

5%

1

2

R0803

1/20W

201

MF

1

2

201

1/20W

5%

100

R0802

1/20W
MF
201

2

1

5%

100

R0801

MF

1/20W

2

1

201

5%

100

R0800

61

61

73 17

61

65 61

61

61

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

V33
V34

AE4

AF4

Y8

Y7

Y36

W34

W36
W37

LGA

OMIT_TABLE

SKYLAKE_S

544753

U0500

AA34
AA35
AA36
AA37
AA38
AB33
AB34
G36
G37
G38
G39
G40
H36
H38
H40
J36
J37
J38
J39
J40
K36
K38
K40
L34
L35
L36
L37
L38
L39
L40
M33
M34
M36
M38
M40
N34
N35
N36

N39
N40
P33
P34
P36
P38
P40
R34
R35
R36
R37
R38
R39
R40

F39

T33
T34
T36
T38
T40
U34
U35
U36
U37

U39
U40

V38
V40

W38

Y38

AJ23
AK11
AK14
AK24

M8

P8
T8

U8

W8

V4

AJ9

AA6
AA7
AB6
AB7
AB8
AC7
AC8

N7

P7

R7

AD5

T7

U7

V7

W7

Y6

V5
V6

F38

F36

V36

Y34

Y33

W35

U38

U2

N37
N38

SKYLAKE_S

H22

G29

A27

G26

AJ22

G24

B25

A26

H23

G23

544753

LGA

OMIT_TABLE

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

A25

A28
A29
A30

AJ12

AJ14

AJ17
AJ18
AJ19
AJ20
AJ21

B27
B29
B31
B32
B33
B34

B35
B36
B37
C25
C26
C27
C28
C29
C30
C32
C34
C36
D25
D27
D29
D31
D32
D33
D34
D35
D36
E24
E25
E26
E27

E30
E32
E34
E36
F23
F24
F25
F27
F29
F31
F32
F33

H25

J23

J25
J26
J27

J29
J30
J31
K16
K18
K20
K21
K23
K25
K27
K29M24

M26

M28

M30

C38

AT18

AT21
AU13
AU15
AU19
AU23
AV11
AV17

AW10
AW14

AW25

AY12
AY16
AY18
AY23

D38

AJ15

AJ13

F34

AJ11

J22

L25

L26

L27

L28

L29

L30

M13

M14

L22
L23
L24

L21

L20

L19

L18

L17

L16M16

M18

M20

M22

L15

L14

K31

E29

E28

J21

G25

H27

H32

AJ16

G32

J28

G30

AV21

H31

H29

G27
G28

J24

89 10 8

89 17 10 8 5

89 10 8

89 10 8

89

10 8

89 10 8 6

89 10 8

89

10

8 6

89 17 10 8 5

89 10 8

89 10 8

89 10 8

89 10 8

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

NC

SYM 6 OF 11

POWER

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCGT

VCCGT

VCCST

VCCST_PWRGD

VCCST

VSSGTX_SENSE

VCCGT

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCPLL_OC

VCCPLL

VCCIO

VCCIO

VCCIO

VCCGT

VCCGT

VSSGT_SENSE

VCCGT_SENSE

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT
VCCGT

VCCGT

VCCGT
VCCGT
VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT

VCCGT

VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT

VCCGT

VCCIO

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCSA_SENSE

VCCIO_SENSE

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VSS_SAIO_SENSE

VCCGT

SYM 5 OF 11

VCC

VDDQ

VDDQ

VDDQ

VCC

VCC

VCC

VCC
VCC

VCCVDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VCC_SENSE
VSS_SENSE

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

www.laptoprepairsecrets.com

Vinafix

0.24.0

051-00673

9 OF 121

9 OF 93

SYNC_MASTER=J78_MLB SYNC_DATE=06/30/2014

CPU & CHIPSET: CPU Ground

LGA

OMIT_TABLE

SKYLAKE_S

544753

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

A7
A11
A13
A15
A17
A24

AA3
AA8

AA33

AB5

AB39

AC3

AC6
AC33
AC34
AC35

AD1

AD4

AD6

AD7

AD8
AD33
AD36
AD37
AD38
AD39
AD40

AE3

AE5

AE8
AE33
AE36

AF1

AF5

AF8
AF33
AF36
AF37
AF40

AG1
AG2
AG3
AG4
AG5

AG8
AG33
AG36

AH5

AH8
AH33
AH36
AH37
AH38
AH39
AH40

AJ1
AJ4
AJ5

AJ8
AJ31
AJ32
AJ33
AJ34

AJ35
AJ36
AK5
AK6
AK7
AK8
AK9
AK10
AK12
AK13
AK15
AK16
AK17
AK18
AK19
AK20
AK23
AK25
AK26
AK28
AK29
AK30
AK36
AK37
AK40
AL1
AL2
AL3
AL4
AL5
AL11
AL14
AL21
AL24
AL27
AL30
AL36
AM5
AM11
AM14
AM17
AM19
AM24
AM27
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AM38
AM39
AM40
AN1
AN4
AN5
AN6
AN7
AN8
AN9
AN10

AY3

H8

G8

C2

B38

D40

A4

Y35

Y5

Y37

P35

G19

F22

W33

W6

V8

U33

U6

T39

T35

T4

T1

R33

R8

R6

R3

P39

P37

P4

P1

N33

N8

N6

N3

M39

M37

M35

M29

M27

M25

M23

M21

M17

M15

M12

M10

M7

M4

M1

L32

L13

L11

L9

L6

L3

K39

K37

K35

K33

K30

K28

K26

K24

K22

K19

K17

K15

K14

K7

K4

K1

J34

J32

J20

J18

J16

J12

J10

J6

J3

H39

H37

H35

H30

H28

H26

H24

H21

H9

H7

H4

H1

G33

G31

G22

G17

G15

G13

G11

G6

G3

F40

F30

F28

F26

F10

F7

F4

F1

E37

E35

E33

E31

E23

E21

M19

T37

U3

V1

V35
V37
V39
W3

E17

E9

E19

E15

E13

E11

LGA

SKYLAKE_S

544753

OMIT_TABLE

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

AR1

AT12
AT13

D7

AU25

LGA

OMIT_TABLE

SKYLAKE_S

544753

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

AN11
AN14
AN16
AN19
AN22
AN23
AN24
AN27
AN30
AN36

AP5
AP11
AP14
AP24
AP27
AP30
AP36
AP37
AP40

AR2

AR3

AR4

AR5
AR11
AR14
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR27
AR30
AR31
AR32
AR33
AR34
AR35
AR36

AT5
AT6
AT7
AT8

AT9
AT10
AT11

AT14
AT15
AT17
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31

AT32
AT34
AT36
AT37
AT38
AT39
AT40
AU1
AU4
AU5
AU7

AU30
AU34
AV2
AV5
AV9
AV26
AV28
AV30
AV34
AV38
AW3
AW5
AW9
AW30
AW32
AW34
AW36
AY5
AY7
AY9
AY27
AY30
B6
B24
B26
B28
B30
C5
C8
C10
C12
C14
C16
C18
C20
C22
C24
C31
C33
C35
C37
D4

D24
D26
D28
D30
D37
D39
E3
E6

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

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A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GROUND

SYM 7 OF 11

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS

VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS

GROUND

SYM 9 OF 11

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS_NCTF

VSS_NCTF

VSS_NCTF
VSS_NCTF

VSS
VSS
VSS

GROUND

SYM 8 OF 11

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS

www.laptoprepairsecrets.com

Intel Recommendation:4x 22UF 0603 (top side outside cavity) Intel Recommendation:2x 22UF 0603 near top side cavity

Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

Memory (CPU VCCDDR) DECOUPLING

Apple Implementation: VCCST/VCCPLL: 1X 22UF 0603/2X 1UF 0402

CPU VCCSA / VCCST+VCCPLL DECOUPLING

Apple Implementation:(following Intel recommendation w/ 0603)
Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

CPU VCORE DECOUPLING

Intel Recommendation:12x 22UF 0805 (top side cavity)

6x 22UF 0603 (top side cavity)

5x 22UF 0805 (top side outside cavity)

1x 22UF 0805 (top side cavity)

ADDED CRITICAL PROPERTY TO CPU CORE DECOUPLING

4x 47UF 0805 (top side outside cavity)

Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

Intel Recommendation:9x 47UF 0805 (top side cavity)

Apple Implementation: 30x 22uF 0603

Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

Apple Implementation:26x 22UF 0603

DUE TO ACOUSTICS CONCERNS

BULK CAPS ON CPU VREG PAGE 71

CPU GT DECOUPLING

Intel Recommendation:5x 22UF 0603 (top side cavity)

CPU VCCIO DECOUPLING

Layout Note: These caps should be placed on top side cavity.

Apple Implementation:9x 22UF 0603 (J78 carry over)

10 OF 93

10 OF 121

0.24.0

051-00673

=PPVCCGT_S0_CPU

=PPVCCIO_S0_CPU

=PPVCCSA_S0_CPU

=PPVCC_S0_CPU

=PPVDDQ_S3_CPU

=PP1V0_S3_CPU

CPU & CHIPSET: CPU Decoupling

SYNC_MASTER=J78_MLB SYNC_DATE=06/30/2014

2

1

CASE-D2-SM

C10B6

CRITICAL

POLY

470UF-0.006OHM

20%
2V

1

2

2V

20%

470UF-0.006OHM

POLY

C1099

CASE-D2-SM

CRITICAL

0402

1

X6S

1.0UF

10%
25V

C10C8

22

1

C10C6

0402

X6S

25V

10%

1.0UF

2

1

0402

C10C7

10%

1.0UF

X6S

25V

0402

2

1

X6S

25V

10%

1.0UF

C10C4

20%
4V
X6S

CRITICAL

C10B0

0603-1

1

2

22UF

4V

20%

X6S

CRITICAL

22UF

0603-1

1

2

C10B1

CRITICAL

X6S

20%
4V

C10B2

22UF

0603-1

1

2

X6S

CRITICAL

C10B3

4V

20%

22UF

0603-1

1

2

X6S

22UF

20%
4V

CRITICAL

C10B4

0603-1

1

2

X6S

4V

CRITICAL

22UF

20%

C10B5

0603-1

1

2

CRITICAL

C1040

22UF

20%

X6S

4V

0603-1

1

2

NOSTUFF

X6S

4V

20%

22UF

CRITICAL

C1041

NOSTUFF

0603-1

1

2

NOSTUFF

20%

X6S

CRITICAL

4V

22UF

0603-1

1

2

C1042

20%
4V
X6S

CRITICAL

C1050

22UF

0603-1

1

2

C1051

20%

X6S

CRITICAL

22UF

4V

0603-1

1

2

CRITICAL

22UF

20%
4V

C1052

X6S
0603-1

1

2

CRITICAL

20%
4V
X6S

22UF

0603-1

1

2

C1053

CRITICAL

C1054

22UF

X6S

4V

20%

0603-1

1

2

X6S

22UF

20%
4V

CRITICAL

C1055

0603-1

1

2

C1056

CRITICAL

4V
X6S

20%

22UF

0603-1

1

2

20%

22UF

CRITICAL

C1057

X6S

4V

0603-1

1

2

4V

CRITICAL

X6S

20%

C1058

22UF

0603-1

1

2

C10C9

22UF

0603-1

1

2

X6S

4V

20%

0603-1

C1070

2

1

CRITICAL

X6S

20%
4V

22UF

2

1

C1071

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1072

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1080

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1081

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1082

X6S

20%
4V

CRITICAL

0603-1

22UF

2

1

C1060

4V

20%

X6S

CRITICAL

22UF

0603-1

X6S

CRITICAL

2

1

C1061

4V

20%

22UF

0603-1

2

1

C1062

20%

22UF

X6S

CRITICAL

4V

0603-1

2

1

C1083

4V

CRITICAL

X6S

20%

22UF

0603-1

2

1

C1084

X6S

4V

20%

22UF

CRITICAL

0603-1

2

1

C1085

20%

X6S

CRITICAL

22UF

4V

0603-1

2

1

C1086

22UF

4V

CRITICAL

20%

0603-1

X6S

2

1

C1087

CRITICAL

X6S

22UF

20%
4V

0603-1

2

1

C1088

CRITICAL

X6S

22UF

20%
4V

0603-1

2

1

C1089

0603-1

CRITICAL

X6S

22UF

20%
4V

20%

2

1

C1073

4V

22UF

X6S

CRITICAL

0603-1

2

1

C1079

X6S
0603-1

20%

CRITICAL

4V

22UF

2

1

C1078

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1077

4V

20%

X6S
0603-1

22UF

CRITICAL

2

1

C1076

20%

22UF

X6S
0603-1

4V

CRITICAL

2

1

C1075

20%

22UF

X6S

CRITICAL

0603-1

4V

2

1

C1074

4V

20%

22UF

X6S
0603-1

CRITICAL

2

1

C1069

CRITICAL

22UF

20%
4V

0603-1

X6S

2

1

C1068

CRITICAL

22UF

20%
4V
X6S
0603-1

2

1

C1067

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1066

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1065

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1064

X6S

4V

20%

22UF

CRITICAL

0603-1

C1063

2

1

22UF

0603-1

X6S

20%
4V

CRITICAL

C10C0

22UF

2

1

4V

20%

X6S
0603-1

CRITICAL

C10C1

X6S
0603-1

22UF

CRITICAL

2

1

4V

20%

CRITICAL

4V

1

2

0603-1

C10C3

22UF

20%

X6S

0603-1

20%

C10C2

CRITICAL

X6S

2

1

4V

22UF

0603-1

2

1

C1025

4V

20%

22UF

X6S

CRITICAL

4V

20%

X6S
0603-1

C1024

1

2

CRITICAL

22UF

CRITICAL

4V

20%

22UF

X6S
0603-1

C1023

1

2

22UF

4V

20%

X6S
0603-1

CRITICAL

C1022

1

2

2

1

C1021

4V

20%

X6S
0603-1

CRITICAL

22UF

2

1

C1020

0603-1

CRITICAL

20%
4V
X6S

22UF

X6S

4V

20%

22UF

CRITICAL

0603-1

C1019

1

2

X6S

4V

20%

22UF

CRITICAL

0603-1

C1018

1

2

X6S

4V

0603-1

20%

22UF

CRITICAL

C1017

1

2

CRITICAL

4V

20%

22UF

X6S
0603-1

C1016

1

2

CRITICAL

4V

20%

22UF

0603-1

X6S

C1015

1

2

0603-1

CRITICAL

X6S

22UF

4V

20%

C1014

1

2

4V

20%

22UF

X6S

CRITICAL

C1013

1

2

0603-1

22UF

0603-1

CRITICAL

X6S

20%
4V

C1012

1

2

CRITICAL

X6S

22UF

4V

20%

0603-1

C1011

1

2

CRITICAL

C1000

0603-1

2

1

22UF

20%
4V
X6S

2

1

C1001

X6S

22UF

20%
4V

CRITICAL

0603-1

C1002

2

1

20%
4V

22UF

X6S
0603-1

CRITICAL

22UF

CRITICAL

C1003

20%
4V
X6S
0603-1

2

1

2

1

C1004

22UF

4V

20%

X6S

CRITICAL

0603-1

2

1

C1005

4V

20%

22UF

X6S
0603-1

CRITICAL

2

1

C1006

4V

22UF

X6S

CRITICAL

0603-1

20%

2

1

C1007

20%

22UF

0603-1

4V
X6S

CRITICAL

2

1

C1008

4V

20%

22UF

CRITICAL

0603-1

X6S

2

1

C1009

X6S

22UF

20%
4V

CRITICAL

0603-1

2

1

C1010

0603-1

CRITICAL

X6S

4V

22UF

20%

C10C5

22UF

1

20%

0603-1

X6S

4V

2

89 8

89 17 8 5

89 8

89 8

89 8

89 8 6

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

clkout for server only

24MHz SE output

direct 100MHz clock dif core ref clock from PCH to processor

direct 24MHz diff crystal ref clock from PCH to processor

11 OF 93

0.24.0

051-00673

11 OF 121

PEG_CLKREQ_L

AP_CLKREQ_PCH_L

SSD_CLKREQ_PCH_L

PEG_CLKREQ_L

PCH_JTAGX

=PP1V0_S5_PCH_VCC

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

PCIE_CLK100M_TBT_P

ITPXDP_CLK100M_P

TP_PCH_1

PCIE_CLK100M_AP_P

PEG_CLKREQ_L

PCIE_CLK100M_AP_N

TBT_PWR_EN_PCH

PCH_XTAL24_IN
PCH_XTAL24_OUT

PEG_CLK100M_P

PEG_CLK100M_N

PCH_DIFFCLK_BIASREF

ITPXDP_CLK100M_N

CPU_BCLK100M_N

CPU_BCLK100M_P

CPU_CLK24M_SSC_N

CPU_CLK24M_SSC_P

CPU_CLK100M_PCI_N

CPU_CLK100M_PCI_P

TBT_PWR_REQ_L

TBT_CLKREQ_L

SSD_CLKREQ_PCH_L

PCH_JTAGX

XDP_PCH_TMS

PCH_XTAL24_IN_R

PCH_XTAL24_OUT_R

PCH_ITP_PMODE

XDP_PCH_TCK

TP_PCH_2

HDA_SDIN0

HDA_RST_R_L

TP_HDA_SDIN1

HDA_SDOUT_R

HDA_BIT_CLK_R

HDA_SYNC

HDA_SYNC_R

HDA_RST_L

HDA_SDOUT

HDA_BIT_CLK

LPC_CLK24M_SMC

AP_CLKREQ_PCH_L

AP_CLKREQ_L

XDP_CPU_TCK

SSD_CLKREQ_L

PCH_JTAGX

SSD_CLKREQ_PCH_L

XDP_PCH_TDI

ENET_CLKREQ_L

AP_CLKREQ_PCH_L

SSD_CLKREQ_L

=PP1V0_S5_PCH_VCC

PCH_ITP_PMODE

XDP_PCH_TDO

PCIE_CLK100M_TBT_N

LPC_CLK24M_SMC_R

AP_CLKREQ_L

ENET_CLKREQ_L

TBT_CLKREQ_L

=PP3V3_S0_PCH_VCC

CPU & CHIPSET: Clocks/HDA/JTAG

SYNC_MASTER=J95_DEBORAH SYNC_DATE=10/20/2014

R1115

2

2.7K

1

0.1%

MF

1/16W

0402

PLACE_NEAR=U1100.E1:5MM

91 17

1

R1100

5% MF

10K

2

2011/20W

91 17

6

6

6

6

6

6

35 11

32 11

26 11

10K

R1101

1/20W2MF5% 201

1

33 11

17 11

17

10K

2011/20W5%

R1104

MF

1 2

17

17

17

2

201MF5%

R1105

1/20W

1

1K

MF

R1106

1/20W

201

5%

2

51

1

17 6

R1108

NOSTUFF

10K

1

1/20W 201

2

MF5%

35

35

32

10K

R1125

1

201

2

MF1/20W5%

19 14

27 14

R1121

402

21

MF-LF

0

5%

1/16W

1 2

402

0

1/16W
MF-LF

5%

R1116

32

R1114

100K

5% 201

21

MF1/20W

26

R1107

100K

5%

1 2

201MF1/20W

44

PLACE_NEAR=U1100.BC17:10MM

R1120

1

33

MF-LF

5%

1/16W

402

2

1

2

201

MF

5%

1M

1/20W

R1102

1

0201

2

25V
CER

10PF

5%

C1102

10PF

1

25V

5%

0201

2

C1101

CER

R1119

1

2

5%

0

1/20W
MF
0201

R1118

1

0

5%

2

0201

MF

1/20W

26

10K

R1113

1/20W 2015%

2

MF

1

1

24.000MHZ-20PPM-9.5PF-60OHM

1.60X1.20MM

2 4

3

Y1101

91 11

74

BB24

BD32

A5

R11

BC17

R2

Y5

U3

R4

P2

N2

W11

R7

E6

G4

L5

P1

W7

U2

R3

P3

N3

R8

D8

E5 E1

BD33

BB33

BA33

BC33

BB31

BC32

AT33

BD25

AT24

AR17

AV19

L2

J2

J1

G1

F1

G2

H2

U1100

FCBGA

SKL-PCH-H

A6

TBD

R13

U7

U5

L7

N7
N8

D7

D3
F2

D5

OMIT_TABLE

AW24

BC24

AW33

CRITICAL

W10

BE25

AR31

L1

52

0201

1

0

5%

MF

1/20W

R1117

2

AB13

AR2

AP2

AR3

CRITICAL

SKL-PCH-H

AM1

AJ33
AM43
AN42
AL42
AJ42

BA9

BC8

BB7

BD9

AT2

C1

D1
N29
N31

P24
P27
P29

P31
R24
R27
U13

W13

AE17
AF17

AG14

AN29
AR22

BD8

AG15

AN2

OMIT_TABLE

AM2

BD1
BE2

AR19

AN17

AN3

AP1

AJ38

TBD

U1100

BE7

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AH44

AJ35

FCBGA

52

52

52

74

52

R1110

1

PLACE_NEAR=U1100.BD9:5MM

33

MF 2011/20W

5%

2

1

201

5%

MF1/20W

33

2

R1109

PLACE_NEAR=U1100.BA9:5MM

1

2011/20W5%MF

R1112

2

33

PLACE_NEAR=U1100.BD8:7MM

1

MF

33

2011/20W

2

5%

PLACE_NEAR=U1100.BB7:6MM

R1111

33

33

91 11

11

11

91 11

11

89 15 11

11

11

91

91

18

11

11

11

11

33 11

89 15 11

17 11

32 11

35 11

26 11

89 19 18 15 14 12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

NC

NC

NC

NC

OUT

OUT

IN

OUT

NC

NC

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

CLOCK SIGNALS

PCI EXPRESS

CLOCKS & CONTROL

SYM 2 OF 12

/ESPI_CLK

XTAL24_IN

XTAL24_OUT

CLKOUT_SRC_P2

CLKOUT_SRC_N3
CLKOUT_SRC_P3

CLKOUT_SRC_N4
CLKOUT_SRC_P4

CLKOUT_SRC_P1

CLKOUT_SRC_N1

CLKOUT_SRC_N0
CLKOUT_SRC_P0

CLKOUT_SRC_P15

CLKOUT_SRC_N15

CLKOUT_SRC_P14

CLKOUT_SRC_N14

CLKOUT_SRC_P13

CLKOUT_SRC_N13

CLKOUT_SRC_P12

CLKOUT_SRC_N12

CLKOUT_SRC_P11

CLKOUT_SRC_N11

CLKOUT_SRC_P10

CLKOUT_SRC_N10

CLKOUT_SRC_P9

CLKOUT_SRC_N9

CLKOUT_SRC_P8

CLKOUT_SRC_N8

CLKOUT_SRC_P7

CLKOUT_SRC_N7

CLKOUT_SRC_P6

CLKOUT_SRC_N6

CLKOUT_SRC_P5

CLKOUT_SRC_N2

XCLK_BIASREF

GPP_A16/CLKOUT_48

CLKOUT_ITPXDP_N

CLKOUT_CPUBCLK_N

CLKOUT_CPUBCLK_P

CLKOUT_CPUNSSC_N
CLKOUT_CPUNSSC_P

GPP_A10/CLKOUT_LPC1

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

GPP_B7/SRCCLKREQ2*

GPP_H9/SRCCLKREQ15*

GPP_H7/SRCCLKREQ13*

GPP_H6/SRCCLKREQ12*

GPP_H5/SRCCLKREQ11*

GPP_H0/SRCCLKREQ6*

GPP_B6/SRCCLKREQ1*

GPP_B5/SRCCLKREQ0*

GPP_H8/SRCCLKREQ14*

GPP_H4/SRCCLKREQ10*

GPP_H3/SRCCLKREQ9*

GPP_H2/SRCCLKREQ8*

GPP_H1/SRCCLKREQ7*

GPP_B9/SRCCLKREQ4*

GPP_B8/SRCCLKREQ3*

GPP_B10/SRCCLKREQ5*

CLKOUT_SRC_N5

GPP_A9/CLKOUT_LPC0

OUT

JTAG

AUDIO

RSVD & TP PINS

SYM 1 OF 12

HDA_BCLK

DISPA_BCLK

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

TP1
TP2

ITP_PMODE

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAGX

RSVD

RSVD

HDA_SYNC

HDA_SDI1

HDA_SDI0

HDA_SDO

DISPA_SDI

DISPA_SDO

GPP_D5/I2S0_SFRM

GPP_D7/I2S0_RXD

GPP_D6/I2S0_TXD

GPP_D8/I2S0_SCLK

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

HDA_RST*

RSVD

OUT

OUT

IN

OUT

OUT

NC

NC

NC

NC

NC

OUT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

OUT

www.laptoprepairsecrets.com

BATLOW only in mobile package

PlACE R1217 NEAR TRACE T-POINT

12 OF 121

0.24.0

051-00673

12 OF 93

PCH_STRP_BOOT_LPC

LPC_SERIRQ

PCIE_WAKE_L

PCH_RCIN_TERM

PROC_TRIGIN_R

PM_SYNC_R

XDP_PCH_OBSDATA_B2

PCH_TRST_L

PCH_PRDY_L

PCH_SUSACK_L

PM_RSMRST_PCH_L

PCH_BATLOW_L

TP_PCH_SLP_WLAN_L

PM_PCH_SYS_PWROK

PM_SYSRST_L

LPC_PWRDWN_L

PCH_PECI

XDP_PCH_OBSDATA_A2

PROC_TRIGOUT

PCH_PROCPWRGD

LPC_AD_R<1>

LPC_AD_R<0>

PLT_RESET_L

PCH_SRTCRST_L

PCH_MEM_RESET_L

CPU_PECI

CPU_PWRGD

DMI_S2N_N<1>

DMI_S2N_P<0>

=PP1V0_S3_VCCST

=PP3V3_S0_PCH_VCC

DMI_N2S_N<3>

=PPVDDQ_S3_MEMRESET

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

SPI_IO_R<2>

SPI_IO_R<3>

SPI_MOSI_R

SPI_MISO

SPI_CS0_R_L

TP_CLINK_DATA

PCH_STRP_NOREBOOT

PCH_STRP_BOOT_LPC

DMI_N2S_N<0>

DMI_S2N_N<2>

DMI_N2S_P<3>

DMI_N2S_N<2>

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_N2S_P<2>

DMI_S2N_P<3>

DMI_N2S_P<0>

DMI_S2N_P<1>

DMI_S2N_P<2>

PROC_TRIGIN

PM_SYNC

=PP3V3_G3_PCH_RTC

PCH_SRTCRST_L
PCH_INTRUDER_L

RTC_RESET_L

PCH_STRP_GPP_B23

PM_SLP_S4_L

PM_CLK32K_SUSCLK_R

LPC_CLKRUN_L

PM_THRMTRIP_PCH_R_L

XDP_CPU_TRST_L

PM_THRMTRIP_L

PM_DOWN

SMC_RUNTIME_SCI_L

LPC_AD_R<2>

PCH_RCIN_TERM

PM_SLP_SUS_L

PCH_PECI

PCH_VRALERT_L

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

LPC_SERIRQ

LPC_FRAME_R_L

LPC_AD_R<3>

PCH_VRALERT_L

SMC_WAKE_SCI_L

TP_PCH_SLP_LAN_L

PM_SLP_SUS_L

TP_PM_SLP_A_L

PM_SLP_S3_L

PM_SLP_S5_L

DMI_S2N_N<3>

CPU_RESET_L

PCH_PREQ_L

PCH_STRP_GPP_B23

SPI_CLK_R

TP_PCH_GPP_A12

=PP3V3_S5_PCH_VCC

DMI_S2N_N<0>

PM_PWRBTN_L

PM_PCH_PWROK

TP_CLINK_RESET_L

PCH_PME_L

PCIE_WAKE_L

PM_ACPRESENT

PCH_PME_L

RTC_RESET_L

PCH_INTRUDER_L

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PM_ACPRESENT

TP_PCH_GPP_A12

PCH_BATLOW_L

PM_PWRBTN_L

LPC_CLKRUN_L

PCH_STRP_NOREBOOT

PM_RSMRST_PCH_L

MEM_RESET_L

PCH_SUSWARN_L

TP_CLINK_CLK

SYNC_DATE=10/20/2014SYNC_MASTER=J95_DEBORAH

CPU & CHIPSET: PCH RTC/DMI/PM/CPU_Misc

73 17 12

44

5%

3.0K

2

MF

1

2011/20W

R1211

NOSTUFF

5%

MF33201

1/20W1 2

R1225

36 32 19 12

44 19

72 44 12

72 44 32 12

45

73 72 45 44 36 12 6

44 18 17

73 45 17

82 73 39 19

19

73 17 12

44 17 12

R1286

0201

MF

1/20W

5%

0

2

1

44 12

45

17 6

1/16W

2

402

1K

MF-LF

1

5%

R1218

PLACE_NEAR=R1219.2:3MM

6

17 6

45

44 6

1

MF 0201

1/20W

2

0

5%

R1226

MF

1/20W

NOSTUFF

5%

21

13

201

R1217

1/20W 201

1 2

1K

5%

R1210

MF

18

18

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AY5

C29

AJ3

BC23
BD24

AT27

OMIT_TABLE

CRITICAL

FCBGA

U1100

AF41

SKL-PCH-H

G27

AT4

A30

A28

B30

B29

B28

C27

K29

E26

G24

N27

L29

E24

L27

B27

AE44

AJ4

AH2

AL2

AK1

AT3

AK2

AM3

TBD

AL3

1

5%

1/16W

33

402

MF-LF

2

PLACE_NEAR=U1100.AL2:12.7MM

R1228

17

17 6

17

6

6

1

R1212

1/20W

2

5% MF 201

100K

46

46

46

46 17

5

MF

100K

201

1

1/20W

R1213

5%

2

5

5

5

5

5

5

5

5

5

5

1/20W

R1214

1

100K

5%

2

MF 201

5

5

5

5

5

402

2

X5R

10V

10%

1UF

1

C1201C1200

10%
10V

402

X5R

1UF

1

2

R1200

MF

1

201

2

5%
1/20W

1M

R1215

MF

2

100K

2011/20W5%

1

NOSTUFF

44 14

1/20W

1%

560

MF

1 2

201

PLACE_NEAR=U1100.AL3:12.7MM

R1219

201

R1230

2

5% MF

1

1/20W

10K

24 23 22 21

1K

1/16W
MF-LF

1

2

402

5%

R1261

1

16V

10%
X7R-CERM

0.1UF

0402

2

C1261

1 2

5%

MF

0201

0

1/20W

R1271

21

402

1/16W

5%

R1216

PLACE_NEAR=U1100.AM3:12.7MM

33

MF-LF

1K

1/20W

R1206

201

2

5% MF

1

44 14

1

10K

5% MF

2

1/20W

R1231

201

10K

2

5% 201MF

1

R1234

1/20W

100K

2

5%

1

201MF1/20W

R1290

10K

R1204

2011/20W2MF

1

NOSTUFF

5%

MF

100K

R1237

1

5% 201

2

1/20W

5%

1K

2

R1203

201

1

MF1/20W

1/20W

5%

201

MF

1

2

100K

R1220

5%

MF

2

201

1/20W

R1201

1

20K

20K

1/20W
MF
201

1

R1202

5%

2

BC26

AT17

BC10

BB15

BD19

AN15

BE16

BB17

BD13

CRITICAL

TBD

FCBGA

BC14

AT13

BA17

BC15

BB13

BB10

BA11

BD14

AW15

BD15

BA13

AW11

AY1

BB27

BD17

AW22

BC18

BC13

BD23

AV11

U1100

SKL-PCH-H

BE11

AV15

AV22
AT19
BD16

AT22

AW1

BB19

OMIT_TABLE

BD11

AR15

AV13

BD10

AW17

BC9

5%

8.2K

201

2

R1236

1/20W

1

MF

10K

1/20W MF

2

5%

1

201

R1235

MF

R1233

5% 201

1 2

10K

1/20W

MF

2

5% 2011/20W

1

10K

R1232

46

46 17

2 1

R1229

402

MF-LF

5%

1/16W

33

PLACE_NEAR=U1100.AJ4:5MM

R1224

33

201MF1/20W

5%

1 2

44

44

44

44

2

201

5%

MF1/20W

1

33

R1221

R1222

1/20W

5%

201

1 2

33

MF

33

201

MF

5%

1 2

R1223

1/20W

6

17

17

AT31

AW31

BD31

BB29

BE30

BC29

BC31

AT29

AR29

AV29

BC27

BD28

BD27

AW27

AR24

FCBGA

CRITICAL

TBD

OMIT_TABLE

BD30

AV2

AV3

AW2

U1100

SKL-PCH-H

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

12

44 12

12

12

12

12

89 61

89 19 18 15 14 11

89

91

12

12

89 15

12

12

45 18 12

12

12

12

12

12

12

72 44 32 12

72 44 12

73 72 45 44 36 12 6

12

91

12

91

12

12

89 19 18 15 14 13

91

12

36 32 19 12

12

12

45 18 12

12

12

12

12

44 17 12

12

12

91

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

BI

IN

OUT

OUT

OUT

BI

IN

OUT

DMI

CPU/MISC

SYM 5 OF 12

PROCPWRGD

PM_DOWN

PM_SYNC

DMI_TXN0

DMI_TXP1

GPP_B3/CPU_GP2

THERMTRIP*

DMI_TXN1

PRDY*

PREQ*

GPP_B23/SML1ALERT*/PCHHOT*

PLTRST_PROC*

DMI_RXP3

DMI_RXP2

DMI_RXN3

DMI_RXN2

DMI_RXP1

DMI_RXN1

DMI_RXP0

DMI_RXN0

DMI_TXP3

DMI_TXN3

DMI_TXP2

DMI_TXN2

DMI_TXP0

PCH_TRIGIN

PCH_TRIGOUT

GPP_E3/CPU_GP0

GPP_B4/CPU_GP3

PECI

GPP_E7/CPU_GP1

CPU_TRST*

OUT

OUT

IN

IN

IN

NC

NC

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

NC

OUT

IN

/SX_EXIT_HOLDOFF*

RTC

ESPI/LPC

/SUSPWRDNACK

SYM 4 OF 12

SYSTEM POWER MANAGEMENT

GPD7/RSVD

SYS_RESET*

GPP_A15/SUSACK*

DSW_PWROK

GPP_A3/LAD2/ESPI_IO2

GPP_A2/LAD1/ESPI_IO1

GPP_A1/LAD0/ESPI_IO0

GPD2/LAN_WAKE*

GPP_B2/VRALERT*

GPP_A0/RCIN*/ESPI_ALERT1*

GPD8/SUSCLK

WAKE*

GPP_A14/SUS_STAT*/ESPI_RESET*

GPP_A8/CLKRUN*

GPD0/BATLOW*

GPP_B12/SLP_S0*

GPP_A12/BMBUSY*/ISH_GP6

GPD9/SLP_WLAN*

GPP_A11/PME*

GPP_B13/PLTRST*

SYS_PWROK

PCH_PWROK

GPD10/SLP_S5*

GPD5/SLP_S4*

GPD4/SLP_S3*

RTCX2

RTCX1

RSMRST*

INTRUDER*

RTCRST*

SRTCRST*

GPP_A5/LFRAME*/ESPI_CS0*

SLP_LAN*

SLP_SUS*

GPD6/SLP_A*

GPD11/LANPHYPC

GPP_A4/LAD3/ESPI_IO3

GPP_A7/PIRQA*/ESPI_ALERT0*

GPP_A6/SERIRQ/ESPI_CS1*

GPD1/ACPRESENT

GPD3/PWRBTN*

GPP_A13/SUSWARN*

DRAM_RESET*

BI

BI

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

BI

BI

BI

BI

OUT

BI

BI

GSPIC-LINK

SPI

SYM 3 OF 12

GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS*

GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

SPI0_CS1*

SPI0_CS2*

SPI0_MOSI

SPI0_MISO

SPI0_IO2

SPI0_IO3

CL_CLK

CL_DATA

GPP_B17/GSPI0_MISO

CL_RST*

SPI0_CS0*

SPI0_CLK

GPP_B15/GSPI0_CS*

GPP_B16/GSPI0_CLK

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USB2_ID HAS WEAK PULLUP

051-00673

0.24.0

13 OF 93

13 OF 121

PCIE_TBT_D2R_P<2>

TBT_POC_RESET_L

PCIE_RCOMPN

PCH_SATAXPCIE6_SATAGP6

USB_EXTC_OC_L
USB_EXTB_OC_L
USB_EXTD_OC_L

PCH_CAM_EXT_BOOT_R_L

SATA_HDD_D2R_N
SATA_HDD_D2R_P

SATA_HDD_R2D_C_P

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_N<0>
PCIE_SSD_R2D_P<0>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_N<1>

PCH_DEVSLP0

PCH_DEVSLP2

PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_D2R_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_D2R_N<3>
PCIE_TBT_D2R_P<3>

PCIE_AP_D2R_N
PCIE_AP_D2R_P

PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

PCH_SATAXPCIE0_SATAGP0

PCH_SATAXPCIE2_SATAGP2

PCH_SATAXPCIE1_SATAGP1

PCH_SATAXPCIE4_SATAGP4

PCH_SATAXPCIE3_SATAGP3

PCH_SATAXPCIE7_SATAGP7

PCH_SATAXPCIE5_SATAGP5

WOL_EN

PCH_CAM_EXT_BOOT_L

PCIE_RCOMPP

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_N<2>
PCIE_SSD_R2D_P<2>

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_N<3>
PCIE_SSD_R2D_P<3>

PCH_SATALED_L

SSD_PWR_EN

HDD_PWR_EN

PCH_SSD_RESET_L

SSD_BFH_L

SSD_SR_EN_L

PCH_DEVSLP1

PCH_SATALED_L

SSD_SR_EN_L

PCIE_SSD_R2D_P<1>

PCIE_TBT_R2D_C_N<2>

SDCONN_STATE_CHANGE

=PP3V3_S4_PCH_VCC

=PP3V3_S5_PCH_VCC

PCH_CAM_RESET

PCH_CAM_RESET_R

SATA_HDD_R2D_C_N

PCIE_TBT_R2D_C_N<3>
PCIE_TBT_R2D_C_P<3>

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCH_USB_RBIAS

PCH_USB_VBUSSENSE

PCH_USB2_ID

USB_EXTD_OC_L

USB_EXTC_OC_L

USB_EXTB_OC_L

USB3_EXTC_TX_P

USB3_EXTC_RX_F_P

USB3_EXTC_TX_N

USB3_EXTC_RX_F_N

USB3_EXTB_TX_P

USB3_EXTB_TX_N

USB3_EXTB_RX_F_N

USB3_EXTA_TX_N
USB3_EXTA_TX_P

USB3_EXTA_RX_F_P

USB3_EXTD_TX_P

USB3_EXTD_TX_N

USB3_EXTD_RX_F_P

USB3_EXTD_RX_F_N

USB_EXTA_N
USB_EXTA_P

USB3_EXTB_RX_F_P

USB_EXTA_OC_L

USB_EXTA_OC_L

USB3_EXTA_RX_F_N

USB_EXTC_P

USB_EXTB_P

USB_EXTB_N

USB_EXTC_N

USB_EXTD_N

USB_EXTD_P

USB_BT_N

USB_CAMERA_N
USB_CAMERA_P

USB_BT_P

CPU & CHIPSET: PCH PCI-E/USB

SYNC_MASTER=J95_DEBORAH SYNC_DATE=10/20/2014

5% MF

1 2

NOSTUFF

2011/20W

R1303

10K

26

33

33

33

33

33

33

33

33

32

32

32

32

NOSTUFF

1/20W5%

2

201

10K

MF

R1304

1

35

35

32

32

42 17 13

42 17 13

43 17 13

43 17 13

201

PLACE_NEAR=U1100.AG3:11.4MM

1%

MF

1

113

R1314

2

1/20W

R1315

2

1

1%

100

201

MF

1/20W

PLACE_NEAR=U1100.C17:11.4MM

AL7

AB3
AB2

V1

V2

AL8

AJ7

AE2

Y43

AG3

AG2

W43

G11

W44

C13
D13

OMIT_TABLE

B12

B8

B10

AG10

AG8

AF5

AA1

AJ8

C14

CRITICAL

U1100

AD42

H13

G13

B13

A14

E11

A9

A12

C8

B11

C11

A7

B7

AJ13

W3

AA2

AF3

AD7

W2

AF2

AC2

AE1

AD5

AD10

AD39

AD43

FCBGA

TBD

C15

B15

K13

B14

AC44

AD2

AD3

SKL-PCH-H

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

Y41

AJ11

K15

AC3

AG7

R1307

NOSTUFF

201

10K

MF5% 1/20W

2 1

43

43

43

43

5%

2

1/20W MF 201

1

10K

NOSTUFF

R1308

42

42

R1318

1K

5%

201

MF

1/20W

1

2

42

1/20W

10K

1 2

MF 201

R1317

5%

33 14

42

35

35

36 14

42

10K

R1310

1

MF 201

2

5% 1/20W

33 13

34 14

33 14

33 14

39

39

MF-LF

R1401

2

5%

1/16W

33

402

1

PLACE_NEAR=U1100.P44:10MM

R1402

MF-LF

1/16W

21

33

402 5%

PLACE_NEAR=U1100.U36:10MM

42

27

33

33

33

33

42

R1301

1K

1/16W

402

MF-LF

2

1

5%

42

33 17 13

17

17

17

17

17

17

17

17

42

17

17

17

B24

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AG35 AG43

AB39

AD31

AB33

AE45

B38

A41

H40

E45

E22

L22

E41

C38

F41

E42

A39

D43

D22

G19

OMIT_TABLE

FCBGA

CRITICAL

TBD

SKL-PCH-H

U1100

AG36

AG39

AG42

AD35

AD38

AB44

AB41
AB42

G15

A16
B16

G17

K17

B20

C20

E20

B21

K19

L19

C22

G22

B22
A23

K22

C23

B23

K24

L24

C24

G31
H31

C31

E29

C32
B32

L31

K31

C33

B33

G33
H33

B35
A35

G35
E35

C36
B36

D39
E37

B39

A40

K37
G37

G45
G44

L37
L39

H43
H44

N39
N38

K44
J45

H15

A21

B19

AC43

B18

C17

AA45

AB35

AA44

AD44

AB43
AB36

E17

F45

H42

B31

G29

L17

C19

33

33

33

33

33

33

42

33

33

43

26

26

26

26

26

26

26

43

26

26

26

26

26

26

26

26

43

43

43

42

42

43

43

38

38

43

201MF5%

21

10K

1/20W

R1316

43 17 13

42 17 13

43 17 13

14

33 17 13

33 13

37 14

89 14

89 19 18 15 14 12

14

42 17 13

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

NC

NC

NC

NC

NC

NC

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

OUT

BI

BI

IN

IN

IN

IN

USB2

USB3

SYM 7 OF 12

USB3_3_TXP

USB3_3_TXN

USB3_3_RXP

USB3_3_RXN

USB3_2_TXP

USB3_2_TXN

USB3_2_RXP

USB3_2_RXN

USB2_COMP

GPP_F18/USB2_OC7*

GPP_F17/USB2_OC6*

GPP_F16/USB2_OC5*

GPP_F15/USB2_OC4*

USB2N_2

USB2_VBUSSENSE

USB2_ID

GPP_E12/USB2_OC3*

GPP_E11/USB2_OC2*

GPP_E9/USB2_OC0*

GPP_E10/USB2_OC1*

USB2N_14
USB2P_14

USB2N_13
USB2P_13

USB2N_12
USB2P_12

USB2N_11
USB2P_11

USB2N_10
USB2P_10

USB2N_9

USB2P_9

USB2P_7

USB2N_7

USB2N_8

USB2P_1

USB2N_4

USB2P_3

USB2N_3

USB2P_5

USB2N_5

USB2P_4

USB2N_6

USB2P_6

USB2P_8

USB3_6_TXP

USB3_6_RXP

USB3_6_TXN

USB3_6_RXN

USB3_5_TXP

USB3_5_TXN

USB3_5_RXN
USB3_5_RXP

USB3_4_TXN
USB3_4_TXP

USB3_4_RXP

USB3_4_RXN

USB3_1_TXP

USB3_1_TXN

USB3_1_RXP

USB3_1_RXN

USB2P_2

USB2N_1

NC

NC

NC

NC

NC

NC

IN

IN

OUT

OUT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

BI

BI

IN

NC

OUT

NC

NC

NC

NC

NC

NC

NC

OUT

NC

NC

NC

NC

NC

NC

NC

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

NC

NC

NC

NC

OUT

OUT

IN

IN

NC

IN

IN

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SYM 8 OF 12

PCIE/SATA/USB3

PCIE10_TXP/SATA1A_TXP

PCIE10_TXN/SATA1A_TXN

PCIE10_RXP/SATA1A_RXP

PCIE9_TXP/SATA0A_TXP

PCIE9_TXN/SATA0A_TXN

PCIE14_TXP/SATA1B_TXP

PCIE15_RXN/SATA2_RXN

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP

PCIE10_RXN/SATA1A_RXN

PCIE13_RXN/SATA0B_RXN

PCIE13_TXN/SATA0B_TXN

PCIE13_RXP/SATA0B_RXP

PCIE13_TXP/SATA0B_TXP

PCIE14_RXN/SATA1B_RXN

PCIE14_RXP/SATA1B_RXP

PCIE14_TXN/SATA1B_TXN

PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_F5/DEVSLP3
GPP_F6/DEVSLP4

GPP_F8/DEVSLP6

GPP_F7/DEVSLP5

GPP_F9/DEVSLP7

GPP_E8/SATALED*

PCIE5_RXN
PCIE5_RXP

PCIE5_TXP

PCIE5_TXN

PCIE6_RXP

PCIE6_RXN

PCIE6_TXP

PCIE6_TXN

PCIE7_RXN
PCIE7_RXP

PCIE7_TXN
PCIE7_TXP

PCIE8_RXN

PCIE8_TXN

PCIE8_RXP

PCIE8_TXP

PCIE11_RXN
PCIE11_RXP

PCIE11_TXN
PCIE11_TXP

PCIE12_RXP

PCIE12_RXN

PCIE12_TXP

PCIE12_TXN

PCIE1_RXN/USB3_7_RXN
PCIE1_RXP/USB3_7_RXP

PCIE1_TXN/USB3_7_TXN
PCIE1_TXP/USB3_7_TXP

PCIE2_RXN/USB3_8_RXN
PCIE2_RXP/USB3_8_RXP

PCIE2_TXN/USB3_8_TXN
PCIE2_TXP/USB3_8_TXP

PCIE3_RXN/USB3_9_RXN
PCIE3_RXP/USB3_9_RXP

PCIE3_TXN/USB3_9_TXN
PCIE3_TXP/USB3_9_TXP

PCIE4_RXN/USB3_10_RXN

PCIE4_TXN/USB3_10_TXN

PCIE4_RXP/USB3_10_RXP

PCIE4_TXP/USB3_10_TXP

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E2/SATAXPCIE2/SATAGP2

GPP_E1/SATAXPCIE1/SATAGP1

GPP_F1/SATAXPCIE4/SATAGP4

GPP_F0/SATAXPCIE3/SATAGP3

GPP_F4/SATAXPCIE7/SATAGP7

GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6

GPP_F10/SCLOCK
GPP_F11/SLOAD

GPP_F13/SDATAOUT0

GPP_F12/SDATAOUT1

PCIE_RCOMPN

PCIE_RCOMPP

PCIE19_RXN
PCIE19_RXP

PCIE19_TXN
PCIE19_TXP

PCIE20_RXN
PCIE20_RXP

PCIE20_TXN
PCIE20_TXP

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

NC

NC

NC

NC

IN

NC

NC

NC

IN

IN

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

NC

NC

NC

NC

NC

www.laptoprepairsecrets.com

GPPI IS ON VCC3V3_PRIM

14 OF 121

14 OF 93

0.24.0

051-00673

JTAG_ISP_TDO

JTAG_TBT_TMS_PCH

SMC_RUNTIME_SCI_L

PCH_SMBALERT_L

SSD_BFH_L

PCH_CAM_RESET

DP_TBT_SEL

JTAG_ISP_TDI

ENET_LOW_PWR_PCH

ENET_MEDIA_SENSE

JTAG_ISP_TCK

TBT_PWR_REQ_L

AUD_IPHS_SWITCH_EN_PCH

WOL_EN

PCH_STRP_LPC_L

SMC_WAKE_SCI_L

HDD_PWR_EN

TBT_PWR_EN_PCH

SSD_PWR_EN

PCH_CAM_EXT_BOOT_L

TCON_RESET_R_L

TCON_RESET_R_L

SPIROM_USE_MLB

AUD_IPHS_SWITCH_EN_PCH

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

JTAG_ISP_TDO

TBT_CIO_PLUG_EVENT_R_L

DP_TBT_SEL

JTAG_TBT_TMS_PCH

JTAG_ISP_TCK

ENET_MEDIA_SENSE

SDCONN_OC_L

=PP3V3_S0_PCH_VCC

SDCONN_OC_L

SDCONN_STATE_CHANGE

BKLT_FAULT_INT_L

JTAG_ISP_TDI

PCH_EDP_HPD_PD

TCON_RESET_L

=PP3V3_S4_PCH_VCC

=PP3V3_S5_PCH_VCC

PCH_STRP_TOPBLK_SWP_L

ENET_LOW_PWR_PCH

PCH_BOARD_ID<1>

PCH_BOARD_ID<0>

PCH_BOARD_ID<2>

=PP3V3_S5_PCH_VCC

PCH_BOARD_ID<3>

SMBUS_PCH_DATA

PCH_STRP_LPC_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

SML_PCH_0_CLK
SML_PCH_0_DATA

SML_PCH_1_CLK

SML_PCH_1_DATA

GPU_NEPTUNE_EMERALD_ID

PCH_SSD_RESET_L

CPU & CHIPSET: PCH GPIO/Misc

SYNC_MASTER=J95_DEBORAH SYNC_DATE=10/20/2014

MF 201

1 2

100K

1/20W

R1404

5%

100K

1

MF1/20W 201

2

R1490

5%

19 14

MF 201

1

R1489

10K

1/20W

2

NOSTUFF

5%

10K

1

MF 2011/20W

2

R1412

5%

19 14

33

21

R1405

PLACE_NEAR=U1100.M45:10MM

1/16W

MF-LF

402

5%

2

10K

R1453

1/20W

1

201MF

NOSTUFF

5%

2011/20W MF

10K

R1417

21

5%

R1411

2 1

MF 201

10K

1/20W5%

19 14

58 41 14

19

1 2

MF1/20W 201

R1425

10K

5%

40

R1450

2011/20W MF

21

10K

5%

56

58

1/20W MF 201

21

R1421

10K

5%

37 14

BE21
BD18
BC22

AN24

SKL-PCH-H

AU41

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AT44

BC19

BD26

AL27

AR27

AK44

AT43

AN43

AL43

TBD

FCBGA

U1100

BB22
BD21

BB43

BB39

AU44

AU43

AR45
AR39
AN44

AL44

AL35

AJ39

AK45

AJ43

AN36
AN38
AN41

AM44

AH43

AJ44

AL39

AL36

AR44

AG44

AR41

AR38

AT42

BD22

AY44

OMIT_TABLE

CRITICAL

AV43

BA41
AV44

BA40

AW42

AW44

BB41

AW45

1/20W 201

R1415

10K

1 2

MF5%

47

47

47

47

47

47

BD38

BE39

W39

W36

U1100

N44

M45

R35

L44

U35

Y44

R42

P43

N43

BD7

R39

U41

P44

N42

U42

M44

R43

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

W42

R41

R36

BE34

TBD

FCBGA

OMIT_TABLE

W35

U43

U36

T45

R44

U39

L43

BD34

AW35

BD35

BC35

BB36

BC36

BC38

BD36

AW4

AY2
AV4

BB3

BD6

BE5
BE6

T44

BC4

V44

BA4

BA35

BA5

BB38

SKL-PCH-H

CRITICAL

BD39

2

MF 201

1

R1414

10K

1/20W5%

201

2

R1451

MF1/20W

1

10K

5%

R1424

10K

MF 2011/20W

1 2

5%

35 14

69

R1416

201MF1/20W

2

100K

1

5%

19 14

19 14

19 14

46

91 80

5%

MF

1/20W

2

1

1K

R1440

NOSTUFF

201

R1443

2

1

1K

5%
1/20W
MF

NOSTUFF

201

R1442

1

2

1/20W
MF

NOSTUFF

1K

5%

201

1

1K

2

201

MF

1/20W

5%

NOSTUFF

R1441

45

37 13

1

R1429

2

201MF1/20W

10K

5%

201

MF

R1426

1

100K

1/20W

2

5%

201MF1/20W

21

10K

R1428

NOSTUFF

5%

2

1

201

MF

1/20W

10K

R1423

5%

R1422

2

1

201

10K

1/20W
MF

5%

1/20W

2

MF

1

201

R1427

10K

5%

MF

2 1

2011/20W

R1403

5%

10K

R1407

MF

10K

1

201

2

1/20W5%

1/20W

10K

R1406

2

MF

1

2015%

19 14

19 14

44 12

14

33 13

13

58 41 14

19 14

19 14

35 14

19 14

27 11

19 14

36 13

14

44 12

34 13

19 11

33 13

13

14

37 14

89 19 18 15 12 11

89 13

89 19 18 15 14 13 12

89 19 18 15 14 13 12

14

14

33 13

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

INTEGRATED SENSOR

GPPA/

GPPB

GPPC/SMLINK/I2C/UART

GPPD/INTEGRATED SENSOR/UART/I2C

SYM 6 OF 12

GPP_D9

GPP_D3

GPP_D2

GPP_D1

GPP_D0

GPP_B14/SPKR

GPP_B11

GPP_B1

GPP_A18/ISH_GP0

GPP_A17/ISH_GP7

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

GPP_D4/ISH_I2C2_SDA/I2C3_SDA

GPP_D21
GPP_D22

GPP_D16/ISH_UART0_CTS*

GPP_D15/ISH_UART0_RTS*

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

GPP_D12

GPP_D11

GPP_D10

GPP_C23/UART2_CTS*

GPP_C22/UART2_RTS*

GPP_C21/UART2_TXD

GPP_C19/I2C1_SCL

GPP_C20/UART2_RXD

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPP_C16/I2C0_SDA

GPP_C14/UART1_RTS*/ISH_UART1_RTS*

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C11/UART0_CTS*

GPP_C10/UART0_RTS*

GPP_C9/UART0_TXD

GPP_C8/UART0_RXD

GPP_C7/SML1DATA

GPP_C6/SML1CLK

GPP_C5/SML0ALERT*

GPP_C4/SML0DATA

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C1/SMBDATA

GPP_B0

GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_C0/SMBCLK

OUT

BI

BI

OUT

IN

BI

GPPH/I2C/INTEGRATED SENSOR

/SMLINK

GPPG

GPPF/

BACKLIGHTGPPI/DISPLAY

SYM 9 OF 12

GPP_F19/EDP_VDDEN

GPP_F14

GPP_F22
GPP_F23

GPP_I0/DDPB_HPD0

GPP_I2/DDPD_HPD2

GPP_I1/DDPC_HPD1

GPP_F21/EDP_BKLTCTL

GPP_I3/DDPE_HPD3

GPP_F20/EDP_BKLTEN GPP_G2/FAN_TACH_2

GPP_G1/FAN_TACH_1

GPP_G3/FAN_TACH_3

GPP_G5/FAN_TACH_5

GPP_G4/FAN_TACH_4

GPP_G6/FAN_TACH_6
GPP_G7/FAN_TACH_7

GPP_G11/FAN_PWM_3

GPP_G9/FAN_PWM_1

GPP_G10/FAN_PWM_2

GPP_G8/FAN_PWM_0

GPP_G12/GSXDOUT

GPP_G14/GSXDIN

GPP_G15/GSXSRESET*

GPP_G13/GSXSLOAD

GPP_G16/GSXCLK

GPP_G17/ADR_COMPLETE

GPP_G18/NMI*
GPP_G19/SMI*

GPP_G21

GPP_G20

GPP_G22
GPP_G23

GPP_I4/EDP_HPD

GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA

GPP_H10/SML2CLK
GPP_H11/SML2DATA
GPP_H12/SML2ALERT*

GPP_H13/SML3CLK
GPP_H14/SML3DATA
GPP_H15/SML3ALERT*

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H19/ISH_I2C0_SDA

GPP_H18/SML4ALERT*

GPP_H21/ISH_I2C1_SDA

GPP_H20/ISH_I2C0_SCL

GPP_H22/ISH_I2C1_SCL
GPP_H23

GPP_G0/FAN_TACH_0

IN

IN

OUT

IN

OUT

BI

IN

IN

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

www.laptoprepairsecrets.com

placeholder for 2.2uH, .33ohm, 100mA inductor

VCCRTC: 1mA Max, 1mA Idle

VCCPGPPEF: 141mA Max, 0mA Idle

VCCPGPPBCH: 273mA Max, 0mA Idle

VCCPGPPA: 88mA Max, 0mA Idle

VCCPCIEPLL: 37mA Max, 0mA Idle

VCC: 6150mA Max, 0mA Idle

VCCHDAPLL: 8mA Max, 0mA Idle

VCCMPHY: 4090mA Max, 0mA Idle

VCCSPI: 13mA Max, 0mA Idle

VCCCLK5: 8mA Max, 0mA Idle

VCCDSW: 502mA Max, 2.06mA Idle

Current data from EDS (doc #546717, Rev 0.7).

VCCHDA: 75mA Max, 0mA Idle

VCCCLK2: 204mA Max, 0mA Idle

VCCCLK1: 35mA Max, 0mA Idle

NEED TO ADD 47UF BULK CAPS TO 1.0V AND 3.3V RAIL

VCCPRIM_3P3: 370mA Max, 0mA Idle

VCCMPHYPLL: 25mA Max, 0mA Idle

VCCPGPPG: 132mA Max, 0mA Idle

VCCRTCPRIM: 1mA Max, 0mA Idle

VCCPGPPG: 132mA Max, 0mA Idle

VCCPGPPD: 106mA Max, 0mA Idle

VCCAPLLEBB NOT IN EDS TABLE: 30mA Max, 0mA Idle

VCCCLK1: 35mA Max, 0mA Idle

placeholder for 2.2uH, .33ohm, 100mA inductor

placeholder for 2.2uH, .33ohm, 100mA inductor

VCCCLK4: 36mA Max, 0mA Idle

VCCCLK3: 58mA Max, 0mA Idle

051-00673

0.24.0

15 OF 121

15 OF 93

=PP1V0_S5_PCH_VCC

PP1V0_S5_PCH_VCC_CLK_F

PPVOUT_PCH_DCPDSW_1P0

=PP3V3_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

PP1V0_S5_PCH_VCC_CLK_F

PPVOUT_PCH_DCPRTC

=PP3V3_S5_PCH_VCC

PP1V0_S5_PCH_VCCUSB2HDA_PLL

=PP3V3_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

SNS_1V0_S5_N

=PP1V0_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

PP1V0_S5_PCH_VCCUSB2HDA_PLL

=PP3V3_S5_PCH_VCC

SNS_1V0_S5_P

PP1V0_S5_PCH_VCC_MPHYPCIE3_PLL

=PP3V3_S5_PCH_VCC

=PP3V3_G3_PCH_RTC

=PP3V3_S0_PCH_VCC

=PP3V3_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

PP1V0_S5_PCH_VCCUSB2HDA_PLL

PP1V0_S5_PCH_VCC_MPHYPCIE3_PLL

=PP1V0_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

SYNC_DATE=10/20/2014SYNC_MASTER=J95_DEBORAH

CPU & CHIPSET: PCH Power/Decoupling

0603

L1503

2.2UH-20%-0.19A-0.221OHM

1 2

0603

1 2

2.2UH-20%-0.19A-0.221OHM

L1502

2.2UH-20%-0.19A-0.221OHM

21

0603

L1501

C1509

25V

20%

22UF

X5R

2

1

0805

C1508

0805

1

2

X5R

22UF

20%
25V

C1507

25V

20%

22UF

X5R

2

1

0805

C1506

25V

20%

22UF

X5R

2

1

0805

C1526

25V

20%

22UF

X5R

2

1

0805

C1525

0805

1

2

X5R

22UF

20%
25V

C1503

25V

20%

22UF

X5R

2

1

0805

0805

1

2

X5R

22UF

20%
25V

C1502

67

SM

NO_XNET_CONNECTION=1

1

2

XW1501

67

PLACE_NEAR=XW1501.2:1MM

XW1500

NO_XNET_CONNECTION=1

1

2

SM

BA20

AL41

CRITICAL

TBD

SKL-PCH-H

OMIT_TABLE

FCBGA

B43

AA23

AA28

BA24

AJ41

BA31

V28

BE4

BC44
BC45

BE3

AJ5
AL5

BE43

BE42

BE41

BA22

BA26

BB45

BA45

BC42

V26

AN19

AC17

AC28
AD15

AE23

Y25

AL22

AJ25

AN5
BD3

BA29

AD13

N17

V17

R17

K2

U20

R19

BA15

K3

AJ23

AJ20

AE26

AD41

BD40

A43

AC26

AC23

Y23

C45

C44

W15

U23
U25
U26

U21

U1100

AA26

AJ21

BYPASS=U1100.AJ5::3MM

2

1

C1539

10V
CERM

0.1UF

20%

402

BYPASS=U1100.BA20::3MM

2

1

0.1UF

20%
10V
CERM
402

C1538

C1537

0.1UF

2

1

BYPASS=U1100.BA22::3MM

CERM

10V

20%

402

C1536

2

1

BYPASS=U1100.BA45::5MM

402

CERM

10%

6.3V

1UF

BYPASS=U1100.BC44::1MM

C1535

0.1UF

2

1

CERM

10V

402

20%

2

1

C1534

CERM

0.1UF

402

20%
10V

BYPASS=U1100.BA31::1MM

0.1UF

BYPASS=U1100.AN19::1MM

C1533

2

1

10V

20%

CERM
402

402

C1531

0.1UF

20%
10V
CERM

2

1

BYPASS=U1100.R17::1MM

CERM

BYPASS=U1100.R19::5MM

2

1

C1532

402

10%

6.3V

1UF

BYPASS=U1100.V28::3MM

1

0.1UF

20%
10V

C1530

2

402

CERM

BYPASS=U1100.AD15::5MM

2

1

C1527

402

1UF

6.3V

10%

CERM

2

1

402

6.3V

10%

CERM

1UF

C1528

BYPASS=U1100.AL22::5MM

2

1

C1529

10%

1UF

BYPASS=U1100.AL22::5MM

402

CERM

6.3V

C1524

20%

2

1

BYPASS=U1100.AC28::1MM

0.1UF

CERM

10V

402

0.1UF

2

1

C1523

CERM

10V

20%

402

BYPASS=U1100.AC23::1MM

2

1

C1522

BYPASS=U1100.AA28::1MM

20%
10V
CERM

0.1UF

402

2

1

C1521

10V

20%

CERM
402

BYPASS=U1100.AA23::1MM

0.1UF

0.1UF

2

1

C1520

20%

402

10V
CERM

BYPASS=U1100.Y23::1MM

2

1

C1512

1UF

BYPASS=U1100.W15::1MM

6.3V

10%

402

CERM

0.1UF

20%

C1511

2

1

BYPASS=U1100.U21::1MM

402

CERM

10V

CERM

BYPASS=U1100.A43::5MM

2

1

C1513

1UF

10%

6.3V

402

402

BYPASS=U1100.BC42::1MM

2

1

C1514

CERM

10V

0.1UF

20%

BYPASS=U1100.BA20::5MM

2

1

C1519

1UF

10%

CERM

6.3V

402

C1515

2

1

20%
10V
CERM

0.1UF

BYPASS=U1100.AJ41::3MM

402

402

10V

0.1UF

C1516

BYPASS=U1100.AD41::3MM

2

1

CERM

20%

C1518

BYPASS=U1100.BA22::5MM

1

1UF

10%

2

CERM
402

6.3V

2

1

402

20%

CERM

10V

BYPASS=U1100.BA26::3MM

0.1UF

C1517

BYPASS=U1100.BA29::5MM

2

1

402

CERM

6.3V

10%

1UF

C1504

2

1

10V

0.1UF

402

CERM

20%

BYPASS=U1100.AN5::3MM

C1501

BYPASS=U1100.AD13::5MM

1

2

C1505

6.3V

10%

1UF

402

CERM

CERM

402

1UF

10%

6.3V

BYPASS=U1100.K2::5MM

C1510

1

2

89 15 11

15

89 19 18 15 14 13 12

89
19 18
15 14

13

12

15

89 19 18 15 14 13 12

15

89 19 18 15 14 13 12

89 15 11

89 15 11

89 19 18

15 14
13 12

15

89 19 18 15 14 13 12

15

89 19 18

15 14 13 12

89 12

89 19 18 14 12 11

89 19 18 15 14 13 12

89 15 11

89 15 11

89 15 11

15

15

89

15 11

89 19 18 15

14 13 12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

PRIMARY WELL

PCIE2/SATA2/PCIE3

ANALOG PLL USB3/

GPPD PRIMARY WELL

GPPE/GPPEF

RTC LOGIC PW/VRM

GPPG PRIMARY WELL

GPPA PRIMARY WELL

ANALOG PLL USB2/VRM

PRIMARY WELL HVCMOS

MOD PHY PRIMARY

GPPB/GPPC/GPPH

MIPI PLL

HD AUDIO POWER

CLOCK BUFFERS PRIMARY 1.0 V

THERMAL SENSOR PW

AUDIO PLL

SPI

RTC WELL SUPPLY

PRIMARY WELL

DEEP SX WELL

POWER

SYM 10 OF 12

PRIMARY WELL

PCIE PLL EBB PRIMARY

VCCSPI

VCCAPLLEBB_1P0

VCCPRIM_1P0 VCCMPHY_1P0

VCCMPHY_1P0

VCCMPHY_1P0

VCCMPHY_1P0

VCCDSW_3P3

VCCMIPIPLL_1P0
VCCMIPIPLL_1P0

VCCPRIM_1P0

VCCPRIM_1P0
VCCPRIM_1P0

VCCAMPHYPLL_1P0

VCCPGPPBCH

VCCPGPPG

VCCRTCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCCLK5

VCCHDA

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK2
VCCCLK2

VCCCLK1

VCCATS

DCPDSW_1P0

VCCPRIM_3P3

VCCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCHDAPLL_1P0

VCCMPHY_1P0

VCCPGPPBCH

VCCPGPPD
VCCPGPPD

DCPRTC

VCCRTC

VCCSPI

VCCSPI

VCCUSB2PLL_1P0

VCCUSB2PLL_1P0

VCCPRIM_3P3

VCCPGPPD

VCCPGPPD

VCCPRIM_3P3

VCCPGPPA

VCCPGPPEF
VCCPGPPEF

VCCDSW_3P3

VCCPRIM_1P0

VCCPRIM_1P0

VCCAMPHYPLL_1P0

www.laptoprepairsecrets.com

0.24.0

16 OF 93

16 OF 121

051-00673

SYNC_DATE=10/20/2014SYNC_MASTER=J95_DEBORAH

CPU & CHIPSET: PCH Grounds

CRITICAL

TBD

SKL-PCH-H

FCBGA

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

OMIT_TABLE

U1100

AB11
AB14
AB15
AB31
AB32
AB38

AC1
AC18
AC20
AC21
AC25
AC29
AC45

AD4

AD8
AD11
AD14
AD32
AD33
AD36

AE4
AE18
AE20
AE21
AE25
AE28
AE29
AE42

AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29

AG4
AG11
AG13
AG31
AG32
AG33
AG38

AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45

AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36

AK4
AK42

AL4
AL10
AL11
AL13
AL17
AL19
AL24
AL29

AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN4
AN7
AN8
AN10
AN11
AN22
AN27
AN31
AN39
AP4
AP11
AR5
AR7
AR9
AR33
AR34
AR42
AT9
AT10
AT15
AT36
AU1
AU7
AU35
AU36
AU39
AU45
AV6
AV17
AV24
AV27
AV31
AV33
AW9
AW13
AW19
AW29
AW37
AY38
AY45
BA1
BB1
BB11
BB16
BB21
BB25
BB30
BB34
BC1
BC2
BD2
BD43
BD44
BD45
BE9
BE14
BE18
BE23
BE28
BE32
BE37
BE40
BE44

FCBGA

CRITICAL

TBD

SKL-PCH-H

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

OMIT_TABLE

U1100

A2
A3

A4
A18
A25
A32
A37
A42
A44

B1

B2

B3

B6
B25
B37
B40
B44
B45

C2

C4
C10
C28
C37
C42
D10
D12
D15
D16
D17
D19
D21
D24
D25
D27
D29
D30
D31
D33
D35
D36
D45
E13
E15
E31
E33

F8

F44

G9

G42

H3

H17
H19
H22
H24
H27
H29
H35

J3
J5

J7
J10
J11
J39

K4
K10
K27
K33
K36
K42
K43

L4

L8
L12
L13
L15
L41

M35
M42
N4
N5
N10
N15
N19
N22
N24
N35
N36
N41
P17
P19
P22
P45
R5
R10
R14
R22
R29
R33
R38
T1
T2
T4
T42
U4
U8
U10
U11
U14
U15
U17
U18
U28
U29
U31
U32
U33
U38
V3
V18
V20
V21
V23
V25
V29
V45
W4
W8
W14
W31
W32
W33
W38
Y17
Y18
Y20
Y21
Y26
Y28
Y29
AA4
AA17
AA18
AA20
AA21
AA25
AA29
AA42
AB4
AB5
AB7
AB8
AB10

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SYM 12 OF 12

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS

SYM 11 OF 12

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

www.laptoprepairsecrets.com

there is a horizontal mirroring for

WF: SB DPDG says HOOK1 is BP_PWRGD_RST#

PCH SIGNALS

PCH/XDP Signal Isolation Notes:

NOTE: This is a MERGED XDP: = Primary XDP with CPU & PCH JTAGs in a Dual-Scan-Chain

OBSDATA_B2

HOOK3

OBSDATA_C0

OBSFN_C1

TMS

CRB has no-stuff S3 pull-up on PREQ_L

OBSDATA_A1

HOOK2

To configure CPU and PCH JTAG in an ICT Daisy-Chain:

drive ICT_JTAG_DAISY_L to Ground.

OBSFN_D1

OBSFN_D0

OBSFN_A0

SDA

Connect Hook2 to CFG<0>

OBSDATA_A2
OBSDATA_A3

NOTE: TDI and TMS are terminated in CPU.

ICT CPU & PCH JTAG

Daisy-Chain Support (S0):

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_B1

OBSDATA_B0

PDG allows any value from 51 to 3K

support chipset debug.

ITPCLK/HOOK4

OBSDATA_C2

OBSFN_C1

OBSDATA_C0

OBSDATA_B3

PWRGD/HOOK0

XDP_PRESENT#

SCL

998-2516

ICT CPU & PCH JTAG

(as in CRB)

and pull-up to S0

Drive ICT_JTAG_DAISY to 5V and

signal destination (to minimize stub).

from PCH to J1850 and path to non-XDP

signal path needs to split between route

HOOK2

OBSDATA_C1

OBSDATA_A2

Secondary (PCH) Micro2-XDP

TP1847 = TRST_L

Primary Micro2-XDP

there is a horizontal mirroring for

use with 921-0133 Adapter Flex to

OBSDATA_D2

OBSFN_D1

Extra BPM Testpoints

OBSFN_B1

HOOK1

TRSTn

OBSFN_A1

OBSDATA_C1

OBSDATA_C3

use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout,

RESET#/HOOK6

OBSFN_C0

OBSDATA_D0

OBSDATA_C3

VCC_OBS_AB

OBSDATA_D0

VCC_OBS_CD

ITPCLK#/HOOK5

OBSDATA_A3

OBSDATA_A0

OBSFN_A1

OBSFN_B0

TCK0

DBR#/HOOK7

OBSDATA_D3

OBSDATA_D1

OBSFN_C0

OBSFN_A0

OBSDATA_A0
OBSDATA_A1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

OBSFN_B1

TDO

OBSFN_B0

XDP_PRESENT#

998-2516

OBSFN_D0

R187x and R189x should be placed where

HOOK1 ITPCLK#/HOOK5

RESET#/HOOK6

TCK1 TDI

VCC_OBS_CD

ITPCLK/HOOK4

SCL

SDA

HOOK3

VCC_OBS_AB

DBR#/HOOK7

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1

Test-Points:

TP1840 = TMS

TP1841 = TDI

TP1842 = TDO

TP1843 = TCK0

(TP1844 = TCK1)

TP1845 = DAISY
TP1846 = DAISY_L

NOTE: This is not the standard XDP pinout,

support chipset debug.

OBSDATA_C2

XDP SIGNALS

18 OF 121

17 OF 93

0.24.0

051-00673

PM_PCH_SYS_PWROK

XDP_BPM_L<2>

XDP_PCH_SATALED_L

XDP_CPU_TDO

XDP_CPU_TDO_PCH_TDI

XDP_PCH_SATAXPCIE7_SATAGP7

XDP_PCH_CPU_GP1

XDP_PCH_CPU_GP0

XDP_PCH_RSMRST_L

=SMBUS_XDP_SDA

XDP_PM_SYSRST_L

XDP_PCH_ITP_PMODE

=PP3V3_S5_ROM

PM_PWRBTN_L

CPU_RESET_L

PCH_ITP_PMODE

SPI_IO_R<2>

XDP_PCH_USB2_OC0_L

XDP_CPU_TDI

XDP_CPU_TDO

=SMBUS_XDP_SCL

XDP_PCH_TDO

XDP_PCH_SATAXPCIE3_SATAGP3

XDP_PCH_DEVSLP2

XDP_CPU_TCK

XDP_PCH_TDI

XDP_PCH_SATAXPCIE6_SATAGP6

XDP_PCH_SATAXPCIE4_SATAGP4

XDP_CPU_TDI_PCH_TDI XDP_PCH_TDI

=PPVCCIO_S0_CPU

=PP1V0_S3_XDP

XDP_CPU_TMS

XDP_CPU_PCH_TDO

XDP_CPU_TRST_L

XDP_CPU_TDO

XDP_PCH_SATAXPCIE1_SATAGP1

XDP_PCH_TCK_R_2

XDP_DBRESET_L

CPU_CFG<1>

CPU_CFG<0>

CPU_CFG<16>

XDP_PCH_TDO

=PP5V_S5_XDP

XDP_CPU_PCH_TCK

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

XDP_BPM_L<0>

XDP_CPU_PRDY_L

CPU_CFG<5>

XDP_CPU_TRST_L

XDP_CPU_PRESENT_L

XDP_BPM_L<3>

CPU_PWRGD

CPU_CFG<4>

XDP_PCH_DEVSLP1

CPU_CFG<11>

CPU_CFG<13>

XDP_CPURST_L

XDP_CPU_TMS

=SMBUS_XDP_SCL

ICT_JTAG_DAISY_L

XDP_PCH_SATAXPCIE0_SATAGP0

CPU_CFG<2>

XDP_CPU_PREQ_L

CPU_CFG<12>

ITPXDP_CLK100M_P

XDP_PCH_TCK

ICT_JTAG_DAISY

CPU_CFG<18>

=PP1V0_S5_XDP

XDP_CPU_TDI

XDP_VR_READY

CPU_CFG<14>

CPU_CFG_3_R

CPU_CFG<17>

CPU_CFG<19>

XDP_BPM_L<1>

CPU_CFG<3>

ITPXDP_CLK100M_N

XDP_PCH_USB2_OC1_L

XDP_PCH_DEVSLP0

=SMBUS_XDP_SDA

CPU_CFG<7>

XDP_CPU_PWRGD

CPU_CFG<15>

=PP1V0_S5_XDP

CPU_CFG<6>

PM_RSMRST_PCH_L

PM_VCCST_PWRGD

XDP_PCH_TDO
XDP_PCH_TDI

XDP_PCH_TMS

=PP1V0_S3_XDP

XDP_PCH_USB2_OC3_L

XDP_PCH_CPU_GP0

XDP_PCH_DEVSLP0

XDP_PCH_DEVSLP1
XDP_PCH_DEVSLP2

XDP_PCH_RSMRST_L

XDP_PCH_SATALED_L

XDP_PM_SYSRST_L

XDP_PCH_USB2_OC0_L

XDP_PCH_USB2_OC2_L

XDP_PCH_USB2_OC1_L

PCH_PREQ_L

PCH_PRDY_L

PCH_SATAXPCIE6_SATAGP6

PCH_SATAXPCIE7_SATAGP7

PCH_DEVSLP0

PCH_ITP_PMODE

PCH_SATALED_L

PM_RSMRST_PCH_L

PM_SYSRST_L

USB_EXTA_OC_L

USB_EXTC_OC_L

USB_EXTB_OC_L

USB_EXTD_OC_L

XDP_CPU_HOOK2_R

XDP_CPU_PWRBTN_L

SPI_MOSI_R

XDP_PCH_SATAXPCIE2_SATAGP2

XDP_CPU_PREQ_L

XDP_PRDY_L_R

XDP_PCH_PRDY_L_R

XDP_PREQ_L_R

XDP_PCH_PRDY_L

XDP_PCH_SATAXPCIE4_SATAGP4
XDP_PCH_SATAXPCIE5_SATAGP5

XDP_PCH_SATAXPCIE6_SATAGP6

XDP_PCH_SATAXPCIE3_SATAGP3

XDP_PCH_SATAXPCIE2_SATAGP2

XDP_PCH_PREQ_L

XDP_CPU_PRDY_L

PCH_SATAXPCIE2_SATAGP2

PCH_SATAXPCIE0_SATAGP0
PCH_SATAXPCIE1_SATAGP1

PCH_SATAXPCIE3_SATAGP3
PCH_SATAXPCIE4_SATAGP4

PCH_SATAXPCIE5_SATAGP5

XDP_PCH_OBSDATA_A2

PCH_DEVSLP1

PCH_DEVSLP2

XDP_PCH_OBSDATA_B2

XDP_PCH_SATAXPCIE1_SATAGP1

XDP_PCH_SATAXPCIE0_SATAGP0

XDP_PCH_PRDY_L

XDP_PCH_PREQ_L

XDP_PCH_PREQ_L_R

XDP_CPU_TCK

XDP_PCH_TCK

=PP1V0_S5_XDP

XDP_PCH_USB2_OC3_L

XDP_PCH_USB2_OC2_L

XDP_PCH_SATAXPCIE5_SATAGP5

XDP_PCH_CPU_GP1

XDP_PCH_ITP_PMODE

XDP_PCH_SATAXPCIE7_SATAGP7

SYNC_MASTER=J95_ANDREW

CPU & CHIPSET: XDP

SYNC_DATE=01/24/2015

6

6

20%

10V

XDP

0.1UF

CERM

C1898

402

1

2

XDP

20%

10V

0.1UF

CERM

C1899

402

1

2

0201

1/20W

5%

MF

2

0

PLACE_NEAR=U1100.AT4:28mm

R1852

1

R1850

0

PLACE_NEAR=U1100.AT3:28mm

02011/20W

5%

21

MF

2

1/20W

5%

1

0201

MF

NOSTUFF

0

R1851

PLACE_NEAR=R1850:10mm

NOSTUFF

0201MF

0

2

5%

1/20W

PLACE_NEAR=R1852:10mm

R1853

1

1

TP-P6

TP1847

TP-P6

1

TP1844

1

TP-P6

TP1842

TP1841

TP-P6

1

TP-P6

TP1840

1

6

0

MF

5%

1/20W

R1803

0201

21

NOSTUFF

NOSTUFF

5%
1/20W
MF
201

R1801

2.2K

1

2

5%
1/20W

PLACE_NEAR=U0500.F11:28mm

201

2

51

R1823

XDP

MF

1

5%

0

21

MF

1/20W

NOSTUFF

0201

R1829

R1837

1/20W

0

5%

0201

1

MF

2

NOSTUFF

R1843

0

5%

NOSTUFF

1/20W

21

MF

0201

1/20W

0

5%
MF

R1844

NOSTUFF

21

0201

5%

2.2K

MF
201

2

1

1/20W

R1836

3

1

2

DFN1006H4-3

Q1844

DMN32D2LFB4

201

2

1

MF

1/20W

5%

1M

R1854

3

2

DFN1006H4-3

1

Q1845

DMN32D2LFB4

17 11

R1847

201

MF
1%

21

1/20W

XDP

150

1

R1839

2

MF

201

5%

1/20W

XDP

1K

0201

MF

2

5%

1/20W

0

1

R1849

PLACE_NEAR=U0500.B10:28mm

PLACE_NEAR=U0500.B9:28mm

R1848

0201MF

5%

21

0

1/20W

5%

MF

R1838

0

1 2

1/20W

PLACE_NEAR=J1800.51:5MM

0201

0201

MF

1/20W5%

2

0

R1828

1

73 8

PLACE_NEAR=U0500.U2:16.5mm

1/20W

NOSTUFF

1K

21

R1891

5%

MF 201

0201MF

1/20W

5%

0

21

XDP

R1807

46 12

0

MF

R1826

21

5%

1/20W

0201

XDP

402

1

0.1UF

2

20%

C1805

10V

CERM

XDP

0

NOSTUFF

R1899

MF

0201

5%

1

1/20W

2

46 12

5%

XDP

1

1/20W

R1825

MF

2

0

0201

5%
1/16W
MF-LF

1

1K

402

2

NOSTUFF

R1898

17 11

2

201

MF

1

R1808

5%
1/20W

2.2K

17 11

73 17 12

XDP

1K

21

5%

1/20W

MF

201

PLACE_NEAR=U0500.AB35:16.5mm

R1806

42 13

42 13

43 13

43 13

R1834

OMIT

SHORT

21

402NONE NONE NONE

R1832

OMIT

NONENONE

2

NONE 402

1

SHORT

R1835

OMIT

SHORT

402

1 2

NONE NONE NONE

R1833

OMIT

NONE 402

1 2

NONE NONE

SHORT

44 18 12

73 17 12

12

12 6

6

OMIT

R1884

NONE NONE NONE

1 2

SHORT

402

13

13

13

13

13

13

13

13

91 11

91 11

17 11 6

DMN5L06VK-7

Q1840

2

1

6

SOT563

PLACE_NEAR=J1800.58:5.08MM

SOT563

DMN5L06VK-7

4

5

3

PLACE_NEAR=J1800.57:5.08MM

Q1840

DMN5L06VK-7

PLACE_NEAR=J1800.58:5.08MM

2

6

1

SOT563

Q1846

5

4

DMN5L06VK-7

3

PLACE_NEAR=J1800.57:6MM

SOT563

Q1846

2

201

51

R1862

1

XDP

MF

5%
1/20W

U1100.AR2:3.5mm

1/20W
MF

PLACE_NEAR=U1100.AN3:28mm

R1866

1

201

2

5%

XDP

51

47 17

MF

1/20W

1

2

51

5%

J1850.51:2.54mm

R1860

201

XDP

R1861

MF

51

5%

201

2

1

XDP

1/20W

U1100.AP2:4mm

47 17

R1887

OMIT

402NONENONENONE

1 2

SHORT

SHORT

R1886

OMIT

NONE 402NONE

1 2

NONE

R1882

OMIT

NONE

SHORT

NONE

1 2

402NONE

R1879

OMIT

NONE

SHORT

402

1 2

NONE NONE

R1878

OMIT

NONE

SHORT

NONE

1 2

NONE 402

R1875

OMIT

SHORT

402

1 2

NONE NONE NONE

2

R1874

OMIT

NONENONE 402NONE

1

SHORT

NONE

R1872

OMIT

2

402NONE

SHORT

1

NONE

R1873

OMIT

NONE

1 2

NONE 402NONE

SHORT

SHORT

OMIT

402NONENONE

1 2

R1883

NONE

R1880

SHORT

402

OMIT

1

NONENONE2NONE

R1881

SHORT

OMIT

NONE

2

402NONE1NONE

NONE

R1896

NONE

OMIT

402NONE

SHORT

1 2

R1897

402

OMIT

NONE

2

NONENONE

SHORT

1

R1894

SHORT

1

NONE

OMIT

NONE

2

402NONE

NONE

R1895

SHORT

NONE

OMIT

402

21

NONE

PLACE_NEAR=U1100.AT4:28mm

NONE

SHORT

OMIT

R1893

2

NONE

1

402NONE

NONE

PLACE_NEAR=U1100.AT3:28mm

1

SHORT

R1890

OMIT

402NONE2NONE

1/20W 201MF

R1804

5%

2

220

1

NOSTUFF

1

2

XDP

C1806

20%

402

10V

0.1UF

CERM

6

CERM

2

C1804

NOSTUFF

0.1UF

402

10V

20%

1

33 13

12

13

13

17 11

13

12

12

6

R1840

2

1

1M

5%
1/20W
MF
201

6

201

1/20W

5%

MF

2

1M

1

R1841

PLACE_NEAR=J1800.51:5.08mm

201

5%

2

MF

1M

1

R1842

1/20W

TP1845

1

TP-P6

PLACE_NEAR=J1800.51:5.08mm

1/20W

5%

2

201

1

MF

1K

R1845

TP-P6

1

TP1846

1

TP-P6

TP1843

DMN32D2LFB4

PLACE_NEAR=J1800.51:5.08mm

Q1842

2

1

3

DFN1006H4-3

6

2

1

3

Q1848

DFN1006H4-3

PLACE_NEAR=J1850.55:5.08mm

DMN32D2LFB4

17 6

17 6

TP1803

1

TP-P6

TP-P6

1

TP1802

6

6

XDP

1K

1/16W

5%

402

2

1

R1831

MF-LF

6

6

6

6

C1800

0.1UF

20%

2

1

10V

CERM

402

XDP

6

0.1UF

XDP

CERM
402

10V

1

C1801

2

20%

XDP_CONN

19

22

28

13

51

55

53

43

36

49

58

35

60

46

3

21

4

56

23

8

61

57

M-ST-SM

2

56

7

910

1112

1516

1718

20

27

2930

3132

33

3940

4142

45

47

50

54

62

6364

34

38

44

48

52

59

14

25

37

24

26

DF40RC-60DP-0.4V

1

J1850

CRITICAL

24

17

22

58

51

39

53

59

J1800

13

8

54

CRITICAL

M-ST-SM

30

25

63

48

60

49

62

61

38

35

34

31

29

23

21

19

15

12 11

7

5

3

1

14

64

16

9

37

56

32

52

18

26

44

33

20

42

46

6

4

2

50

43

41

45

36

DF40RC-60DP-0.4V

10

28 27

XDP_CONN

40

47

57

55

6

PLACE_NEAR=U0500.AB35:16.5mm

1 2

1K

R1800

5%

1/20W

MF

201

NOSTUFF

0201

0

1

R1802

2

XDP

5%

1/20W

MF

5%

NOSTUFF

2 1

R1824

1/20W

MF 201

51

PLACE_NEAR=J1800.51:5MM

12

XDP

51

R1820

201

1/20W

MF5%

201

MF

5%

1K

21

R1805

PLACE_NEAR=R1808.2:5MM

1/20W

NOSTUFF

17 6

17 6

17 12 6

6

18

17 11

73 45 12

44 12

0.1UF

C1881

XDP

10V

20%

402

CERM

1

2

402

1

2

CERM

10V

20%

0.1UF

C1880

XDP

47 17

47 17

91 6

91 6

11

17 11

91 6

91 6

6

6

12 6

6

17

17 6

17

17

17

17

17

17

89 46

17

17 6

17 6

17 11

17

17

17 11 6

17 11

17

17

17 11

89 10 8 5

89 17

17 6

17 12 6

17 6

17

89

17

17

17 11

89 17

17

17

89 17

89 17

17

17

17

17

17

17

17

17

17

17

17

17

17 6

17

17

17

17

17

17

17

17 6

17

17

17

17

89 17

17

17

17

17

17

17

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

TP

TP

TP

TP

TP

IN

GS

SYM_VER_3

D

GS

SYM_VER_3

D

NC

NC

OUT

NC

NCNC

NC

IN

OUT

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

BI

NC

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

IN

IN

OUT

D S

VER 5

G

D S

VER 5

G

DS

VER 5

G

DS

VER 5

G

IN

BI

NC

NC

NC

NC

NC

NC

IN

BI

BI

BI

BI

OUT

BI

IN

IN

IN

IN

TP

TP

TP

GS

SYM_VER_3

D

IN

GS

SYM_VER_3

D

IN

BI

TP

TP

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

BI

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

SMC controls strap enable to allow in-field control of strap setting.

PCH RTC Crystal

(APN: 998-6925)

COIN-CELL HOLDER

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH Reset Button

Place TP1901-TP1903 on bottom side

RTC Power Sources

18 OF 93

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

19 OF 121

0.24.0

051-00673

PCH_CLK32K_RTCX1

RTC_RESET_L

PP3V3_G3_RTC_SW

SMC_ASSERT_RTCRST_R

PP3V3_G3_RTC

PP3V3_G3H_RTC_D_R

PCH_CLK32K_RTCX2_R

PPVBATT_G3_RTC_R

=PP3V3_G3H_RTC_D

HDA_SDOUT_R

PPVBATT_G3_RTC

=PP3V3_S0_PCH_VCC

PM_SYSRST_L

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S5_PCH_VCC

XDP_DBRESET_L

PCH_CLK32K_RTCX2

SMC_ASSERT_RTCRST

SPI_DESCRIPTOR_OVERRIDE_R

SYNC_DATE=09/10/2014SYNC_MASTER=BRANCH_SYEDKAR

CPU & CHIPSET: Chipset Support

C1931

CERM

0.1UF

20%
10V

402

1

2

R1941

5%

1

2

30K

1/16W
MF-LF
402

R1940

1K

5%

2

1/16W
MF-LF
402

1

BAT-HLDR-RCPT-J94-J95

J1900

SM

21

50V
C0G

5%

1

0402

PLACE_NEAR=Y1910.1:2MM

C1911

2

12PF

5%

50V

0402

PLACE_NEAR=Y1910.4:2MM

C1910

1 2

12PF

C0G

0.1UF

10V

20%

CERM

402

1

2

C1930

21

MF-LF

5%

1/16W

10K

402

R1930

SOT-23-HF

NTR4101P

CRITICAL

Q1930

3

1

2

44

2

NTR1P02L

SOT23-3-HF

Q1920

3

1

330

PLACE_NEAR=R1111.2:15MM

R1921

1/16W 4025% MF-LF

1 2

11

12

12

1/16W

402

MF-LF

5%

10M

R1911

1

2

402

5%

1K

1/16W
MF-LF

R1902

2 1

R1910

2

402

MF-LF

0

1/16W

5%

1

PLACE_NEAR=U1100.BD10:25.4MM

Y1910

41

SM-HF

32.768K-12.5PF

CRITICAL

PLACE_NEAR=U1100.BC9:25.4MM

1.4-SQ-NSP

TP1902

SM-PAD

1

OMIT

TP1900

1.97X2.02MM-NSP

SMT-PAD

OMIT

1

OMIT

SM-PAD

1

1.4-SQ-NSP

TP1903

1.97X2.02MM-NSP

SMT-PAD

OMIT

TP1901

1

D1900

SOT-363

BAT54DW-X-G

1

4

6

3

5

2

44 17 12

1/16W

402

MF-LF

5%

4.7K

R1995

1

2

1/16W

5%

402

MF-LF

0

OMIT

SILK_PART=SYS RESET

R1997

1

2

XDP

1/16W

402

5%

MF-LF

0

R1996

1 2

17

45 12

89

89

89 19 15 14 12 11

89 19 15 14 13 12

45

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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THE POSESSOR AGREES TO THE FOLLOWING:

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SHEET

PAGE TITLE

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A

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

S D

G

IN

D

G

S

OUT

OUT

IN

NC NC

NC NC

OUTIN

www.laptoprepairsecrets.com

GPIO Glitch Prevention

Platform Reset Connections

TBT_PWR_EN goes high for JTAG Programming

Unbuffered

TBT_LC can be on when S0 is off and vice-versa.

U2060 Supports I/Os powered when VCC = 0V

Isolation ensure no leakage to FR or PCH

Same as J45, J90,RR RefDesign

Buffered

19 OF 93

20 OF 121

0.24.0

051-00673

TBT_PWR_EN_PCH

JTAG_TBT_TCK_B

TBT_PWR_EN

JTAG_TBT_TCK

JTAG_ISP_TCK

LPC_PWRDWN_L

TBT_CIO_PLUG_EVENT_R_L

TBT_CIO_PLUG_EVENT_L

TBT_PWR_EN

SMC_LRESET_L

MAKE_BASE=TRUE

SSD_RESET_L

TP_VR_GPU_RESET_L

=PP3V3_TBTLC

JTAG_TBT_TMS

=PP3V3_S0_PCH_VCC

JTAG_TBT_TDO

TP_GPU_RESET_L

TBT_PCIE_RESET_L

ENET_SD_RESET_L

JTAG_TBT_TDI

JTAG_ISP_TDI

PLT_RST_BUF_GPU_L

PLT_RST_BUF_TBT_L

JTAG_TBT_TMS_PCH

=PP3V3_S5_RSTBUF

=PP3V3_S5_RSTBUF

=PP3V3_S0_RSTBUF

PLT_RST_BUF_SSD_L

=PP3V3_S0_PCH_VCC

JTAG_ISP_TDO

PLT_RST_BUF_L AP_RESET_L

MAKE_BASE=TRUE

PLT_RESET_L

=PP3V3_S5_RSTBUF

PCIE_WAKE_L

TBT_WAKE_L

=PP3V3_S4_TBT

AUD_IPHS_SWITCH_EN

ENET_LOW_PWR

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S5_PCH_VCC

PM_PCH_PWROK

PM_PCH_PWROK

ENET_LOW_PWR_PCH

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

CPU & CHIPSET: Project Chipset Support

26

26

26

5%

10K

201

MF

1/20W

R2063

1

2

5%
1/20W

201

10K

MF

R2062

1

2

14

14

26

2

1

C2013

0.1UF

10%
16V

0201

X5R-CERM

26 19

14

37 35

2

1

C2050

402

CERM

10V

0.1UF

20%

14

82 73 39 19 12

56

82 73 39 19 12

14

CERM-X5R

2

1

0201

0.1UF

10%

6.3V

C2075

2

1

0201

C2070

0.1UF

CERM-X5R

6.3V

10%

SOT1226

74LVC1G34GX

2 4

U2075

5

3

1

SOT891

1

5

U2070

6

74LVC2G34

2

74LVC2G34

CKPLUS_WAIVE=unconnected_pins

U2070

SOT891

2

5

3 4

14

MF-LF

402

1/16W

5%

R2095

1

1K

2

1/20W

0201

21

R2019

MF

5%

0

CERM

20%

402

10V

0.1UF

C2060

1

2

14

MF

1/20W

5%

10K

201

R2061

1

2

U2060

SN74AUP3G07DQER

7

X2SON

1

3

6

4

8

5

2

26 19

44 12

14 11

NO STUFF

2

0

5%

MF

1/20W

0201

R2071

1

2

1

CRITICAL

SOD

Q2070

3

R2070

1

10K

MF-LF

1/16W

5%

402

2

21

R2017

0201

5%

1/20W

MF

0

8

U2000

74LVC2G08GT/S505

5 3

7

4

6

2

1

SOT833

CRITICAL

74LVC2G08GT/S505

CRITICAL

U2050

SOT833

1

5

2

6

8

7

3

4

26

1/20W

100K

MF
201

5%

R2016

1

2

26

90

33

MF-LF

402

5%

1/16W

R2090

1 2

33

C2080

10V

402

0.1UF

CERM

20%

1

2

MC74VHC1G08

CRITICAL

SOT23-5-HF

4

1

U2080

3

2

5

MF-LF

1/16W

402

R2080

5%

100K

1

2

21

R2092

MF-LF

402

5%

33

1/16W

21

MF-LF

1/16W

402

R2091

33

5%

21

R2088

MF-LF

402

33

5%

1/16W

GPU_AM_EM

R2094

5%

1/16W

1

33

MF-LF

402

2

12

MF-LF

5%

1/16W

33

402

R2055

1 2

37

32

90

44

89

89 19 18 15 14 12 11

89 19

89 19

89

89 19 18 15 14 12 11

89 19

36 32 12 26

89 72 31 30 29 27 26

89 18 15 14 13 12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

IN

IN

OUT

OUTIN

IN

OUTIN

IN

OUT

IN

IN

NC

NC

Y

A

34

Y

A

34

OUT

IN

2Y2A

3A3Y

1A

VCC

1Y

GND

OUT

IN

IN

D

S

G

A2

B1

A1

VCC

B2

GND

Y2

Y1

08

A2

B1

A1

VCC

B2

GND

Y2

Y1

08

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

www.laptoprepairsecrets.com

of margining option.

VRef Dividers

Always used, regardless

22 OF 121

20 OF 93

051-00673

0.24.0

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3000

MEM_VREFCA_A_RC

=PPDDR_S3_MEMVREF

CPU_DIMMA_VREFDQ

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFDQ_A

CPU_DIMMB_VREFDQ

MEM_VREFDQ_A_RC

MEM_VREFDQ_B_RC

PPVREF_S3_MEM_VREFCACPU_DIMM_VREFCA

SYNC_DATE=03/10/2014SYNC_MASTER=J78_DAVID

DRAM: VREF/VTT EN

7

7

7

2

0201

MF

1/20W

1%

R2263

1 2

PLACE_NEAR=C2260.1:2MM

1%

0201

2

MF

1 2

PLACE_NEAR=C2240.1:2MM

R2243

1/20W

R2221

PLACE_NEAR=R2223.2:1.5MM

MF-LF

1/16W

402

1%

1K

1

2

PLACE_NEAR=R2221.2:1mm

MF-LF

402

1/16W

1%

1K

R2222

1

2

PLACE_NEAR=R2243.2:1mm

402

1%

1K

MF-LF

1/16W

R2241

1

2

R2220

1%

1/20W

MF

201

24.9

1 2

PLACE_NEAR=C2220.1:2mm

2

2

1%

0201

1/20W

MF

R2223

1

X5R-CERM

6.3V

10%

C2220

1

2

0201

0.022UF

MF-LF

1/16W

402

1%

1K

R2242

1

2

PLACE_NEAR=R2241.2:1mm

1%

1K

MF-LF

1/16W

402

1

2

R2261

PLACE_NEAR=R2263.2:1mm

24.9

1%

1/20W

MF

201

R2240

1 2

MF-LF

PLACE_NEAR=R2261.2:1mm

1K

1/16W

1%

402

1

2

R2262

24.9

1%

1/20W

MF

201

R2260

1 2

0.022UF

10%

6.3V

1

2

C2240

0201

X5R-CERM

0201

X5R-CERM

0.022UF

10%

6.3V

C2260

2

1

89

24 23

22 21

24 23 22 21

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

www.laptoprepairsecrets.com

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

P/N: 516S1019

Power aliases required by this page:

- =PPDDRVTT_S0_MEM_A

- =I2C_SODIMMA_SDA

BOM options provided by this page:

- =PPVDDQ_S3_MEM_A

- =PP1V5_S0_MEM_A

(NONE)

Page Notes

- =I2C_SODIMMA_SCL

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

21 OF 93

23 OF 121

0.24.0

051-00673

=PPDDRVTT_S0_MEM_A

MEM_A_A<5>

PPVREF_S3_MEM_VREFDQ_A

=MEM_A_DQ<22>

MEM_A_CKE<0>

=PPVDDQ_S3_MEM_A

MEM_A_BA<2>

MEM_A_CLK_N<0>

MEM_A_A<10>

MEM_A_CAS_L

=MEM_A_DQ<32>

=MEM_A_DQS_N<4>

=MEM_A_DQ<34>
=MEM_A_DQ<35>

=MEM_A_DQ<40>
=MEM_A_DQ<41>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQS_P<7>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

MEM_A_A<0>

=PPVDDQ_S3_MEM_A

=PPDDRVTT_S0_MEM_A

PPVREF_S3_MEM_VREFCA

MEM_DIMM0_SA<0>

MEM_DIMM0_SA<0>

MEM_DIMM0_SA<1>

MEM_DIMM0_SA<1>

MEM_EVENT_L

=PP3V3_S0_MEM_A_SPD

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<5>

MEM_A_CS_L<0>

MEM_A_RAS_L

MEM_A_CLK_N<1>

=MEM_A_DQS_N<3>

MEM_RESET_L

=MEM_A_DQS_N<0>

=MEM_A_DQ<31>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=MEM_A_DQ<62>
=MEM_A_DQ<63>

=MEM_A_DQ<53>

=MEM_A_DQ<60>
=MEM_A_DQ<61>

=MEM_A_DQ<52>

=MEM_A_DQ<45>

=MEM_A_DQ<44>

=MEM_A_DQ<47>

=MEM_A_DQ<36>
=MEM_A_DQ<37>

=MEM_A_DQ<38>
=MEM_A_DQ<39>

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CLK_P<1>

MEM_A_A<2>

MEM_A_A<6>
MEM_A_A<4>

MEM_A_A<11>
MEM_A_A<7>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

=MEM_A_DQ<30>

=MEM_A_DQS_P<3>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

=MEM_A_DQ<21>

=MEM_A_DQ<13>

=MEM_A_DQ<14>
=MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<12>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<4>
=MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_A<3>

=MEM_A_DQ<2>
=MEM_A_DQ<3>

=MEM_A_DQ<8>
=MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_P<2>

=MEM_A_DQ<24>
=MEM_A_DQ<25>

=MEM_A_DQ<19>

=MEM_A_DQ<26>

MEM_A_CLK_P<0>

MEM_A_A<1>

=MEM_A_DQ<33>

=MEM_A_DQS_P<4>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<48>
=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<56>
=MEM_A_DQ<57>

=MEM_A_DQ<58>
=MEM_A_DQ<59>

=PP3V3_S0_MEM_A_SPD

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<2>

MEM_A_WE_L

MEM_A_CS_L<1>

=MEM_A_DQ<27>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<0>
=MEM_A_DQ<1>

SYNC_DATE=10/30/2013SYNC_MASTER=J78_NAT

DRAM: SO-DIMM Connector A Slot0

SODIMM-P0.60-D8

F-ANG-SM-1

J2300

205

206

207

208

209

194

SODIMM-P0.60-D8

F-ANG-SM-1

CRITICAL

J2300

9897

9695

9291

90

86

89

85

107

8483

119

80

78

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

15
17

4
6

16
18

21
23

33
35

22
24

34
36

39
41

51
53

40
42

50
52

57
59

67
69

56
58

68
70

129
131

141
143

130
132

140
142

147
149

157
159

146
148

158
160

163
165

175
177

164
166

174
176

181
183

191
193

180
182

192

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

81 82

87 88

93 94

99 100

105 106

111 112

117 118

123 124

199

126

1 2
3

8

9

13 14

19 20

25 26

31 32

37 38

43 44

48

49

54

55

60

61

65 66

71 72

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

25 22

1UF

402

10V
X5R

10%

C2350

1

2

C2351

10V
402

1UF

X5R

10%

1

2

1UF

402

10V
X5R

10%

C2352

1

2

10V
402

1UF

X5R

10%

1

2

C2353

10V
CERM
402

20%

0.1UF

C2323

1

2

CERM
402

20%
10V

0.1UF

C2322

1

2

CERM

10V

20%

402

0.1UF

C2321

1

2

CERM
402

20%
10V

0.1UF

C2320

1

2

CERM
402

20%
10V

0.1UF

C2319

1

2

CERM
402

20%
10V

0.1UF

C2318

1

2

10V

20%

402

CERM

0.1UF

C2317

1

2

CERM
402

10V

20%

0.1UF

C2316

1

2

CERM
402

20%
10V

0.1UF

C2315

1

2

402

CERM

20%
10V

0.1UF

C2314

1

2

10V

20%

402

CERM

0.1UF

C2313

1

2

CERM
402

20%
10V

0.1UF

C2312

1

2

CERM

10V

20%

402

0.1UF

C2311

1

2

402

10V

20%
CERM

0.1UF

C2310

1

2

X5R
603

20%

10UF

6.3V

C2301

1

2

X5R
603

10UF

20%

6.3V

C2300

1

2

2.2UF

402-LF

CERM

20%

6.3V

C2340

1

2

R2340

MF-LF
402

5%
1/16W

10K

1

2

1/16W
402

MF-LF

5%

10K

R2341

1

2

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

7

22 7

22 7

22 7

22 7

22 7

7

7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

7

47 22

47

22

45 44 24 23 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

6.3V

2.2UF

CERM
402-LF

20%

C2335

1

2

CERM
402

20%
10V

0.1UF

C2336

1

2

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

7

25 22

25 22

25 22

25 22

25 22

7

7

22 7

22 7

7

7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

24 23 22 12

25 22

25 22

25 22

25 22

25 22

25 22

25 22

7

25 22

25 22

2.2UF

402-LF

20%
CERM

6.3V

C2330

1

2

402

20%
CERM

10V

0.1UF

C2331

1

2

25 22

25 22

89 22 21

22 20

89 22 21 89 22 21

89 22 21

24 23 22 20

21

21

21

21

89 22 21

89 22 21

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

BI

NC

NC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI BI

BI

www.laptoprepairsecrets.com

P/N: 516S1019

- =I2C_SODIMMA_SDA

- =PPDDRVTT_S0_MEM_A

Page Notes

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =I2C_SODIMMA_SCL

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

- =PPVDDQ_S3_MEM_A

Power aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

22 OF 93

24 OF 121

0.24.0

051-00673

=PP3V3_S0_MEM_A_SPD

=PP3V3_S0_MEM_A_SPD

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_A<3>

=MEM_A_DQ<54>
=MEM_A_DQ<55>

=MEM_A_DQS_P<0>

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQ<6>
=MEM_A_DQ<7>

=MEM_A_DQ<1>

=MEM_A_DQ<12>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

=MEM_A_DQ<21>

=MEM_A_DQ<22>
=MEM_A_DQ<23>

=MEM_A_DQ<28>
=MEM_A_DQ<29>

=MEM_A_DQS_P<3>

=MEM_A_DQ<30>

MEM_A_CKE<3>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<2>
MEM_A_A<0>

MEM_A_CLK_P<3>

MEM_A_ODT<3>

MEM_A_ODT<2>

MEM_A_BA<1>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQ<45>

=MEM_A_DQ<52>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DQS_P<7>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

=MEM_A_DQ<2>
=MEM_A_DQ<3>

=MEM_A_DQ<8>
=MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_P<2>

=MEM_A_DQ<24>
=MEM_A_DQ<25>

=MEM_A_DQ<19>

=MEM_A_DQ<26>

MEM_A_CKE<2>

MEM_A_A<5>

MEM_A_CLK_P<2>

MEM_A_A<1>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<48>

=MEM_A_DQS_P<6>

=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<56>
=MEM_A_DQ<57>

=MEM_A_DQ<58>
=MEM_A_DQ<59>

=PP3V3_S0_MEM_A_SPD

=PPDDRVTT_S0_MEM_A

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

MEM_RESET_L

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

MEM_A_CLK_N<2> MEM_A_CLK_N<3>

MEM_A_RAS_L

MEM_A_WE_L MEM_A_CS_L<2>
MEM_A_CAS_L

MEM_A_CS_L<3>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

MEM_EVENT_L

=MEM_A_DQ<27>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<0>

MEM_DIMM1_SA<1>

MEM_DIMM1_SA<1>

MEM_DIMM1_SA<0>

MEM_DIMM1_SA<0>

MEM_A_A<10>

=PPDDRVTT_S0_MEM_A

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ_A

SYNC_DATE=10/30/2013SYNC_MASTER=J78_NAT

DRAM: SO-DIMM Connector A Slot1

209

208

207

206

205

J2400

SODIMM-P0.60-D8

F-ANG-SM-1

113

204203

196195

190189

185

184

179

178

173

172

168167

162161

156155

151

150

145

144

139

138

134133

128127

7271

6665

61

60

55

54

49

48

4443

3837

3231

2625

2019

1413

9

8

3

21

126

199

124123

118117

112111

106105

10099

9493

8887

8281

7675

125

200
202201

197

121

114

30

110

120

116

122

77

198

186
188

169
171

152
154

135
137

62
64

45
47

27
29

10
12

194

192

182

180

193

191

183

181

176

174

166

164

177

175

165

163

160

158

148

146

159

157

149

147

142

140

132

130

143

141

131

129

70

68

58

56

69

67

59

57

52

50

42

40

53

51

41

39

36

34

24

22

35

33

23

21

18

16

6

4

17

15

7

5

187

170

153

136

63

46

28

11

7473

104

102

103

101

115

79

108

109

78
80

119

83 84

107

85

89

86

90

91 92

95 96
97 98

J2400

F-ANG-SM-1

SODIMM-P0.60-D8

CRITICAL

25 21

2

1

C2450

10V

1UF

402

X5R

10%

2

1

C2451

402

10V

1UF

X5R

10%

2

1

1UF

402

10V
X5R

10%

C2452

2

1

C2453

402

1UF

10V
X5R

10%

2

1

CERM
402

20%
10V

0.1UF

C2423

2

1

C2422

CERM
402

20%
10V

0.1UF

2

1

C2421

CERM
402

20%
10V

0.1UF

2

1

C2420

10V
CERM
402

0.1UF

20%

2

1

C2419

402

20%
10V
CERM

0.1UF

2

1

C2418

20%
10V

402

CERM

0.1UF

2

1

C2417

402

CERM

10V

20%

0.1UF

2

1

C2416

CERM
402

20%
10V

0.1UF

2

1

C2415

10V

20%

402

CERM

0.1UF

2

1

C2414

10V

20%

402

CERM

0.1UF

2

1

C2413

10V

20%

402

CERM

0.1UF

2

1

C2412

10V

20%

402

CERM

0.1UF

2

1

C2411

10V

20%

402

CERM

0.1UF

2

1

C2410

10V

20%

402

CERM

0.1UF

2

1

C2401

10UF

20%

6.3V
603

X5R

2

1

C2400

10UF

20%

6.3V
603

X5R

2

1

C2440

2.2UF

CERM
402-LF

20%

6.3V

2

1

R2440

402

5%
MF-LF

10K

1/16W

2

1

R2441

1/16W

5%

402

MF-LF

10K

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

7

21 7

21 7

21 7

21 7

21 7

7

7

21 7

21 7

21 7

21 7

21 7

21 7

21 7

7

47 21

47

21

45 44 24 23 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

2

1

C2435

20%

2.2UF

CERM

6.3V
402-LF

2

1

C2436

10V

20%

402

CERM

0.1UF

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

7

25 21

25 21

25 21

25 21

25 21

7

7

21 7

21 7

7

7

21 7

21 7

21 7

21 7

21 7

21 7

21 7

21 7

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

24 23 21 12

25 21

25 21

25 21

25 21

25 21

25 21

25 21

7

25 21

25 21

2

1

C2430

20%

402-LF

2.2UF

CERM

6.3V

2

1

C2431

10V

20%
CERM

402

0.1UF

25 21

25 21

89 22 21

89 22 21

89 22 21

89 22 21

89 22 21

89 22 21

22

22

22

22

89 22 21

24 23 21 20

21 20

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

BI

NC

NC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI BI

BI

www.laptoprepairsecrets.com

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Page Notes

Power aliases required by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

(NONE)

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V5_S0_MEM_B

- =PPDDRVTT_S0_MEM_B

- =PPVDDQ_S3_MEM_B

P/N: 516S1019

23 OF 93

VOLTAGE=0.675V

25 OF 121

0.24.0

051-00673

=PPDDRVTT_S0_MEM_B

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFCA

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

MEM_DIMM2_SA<1>

=MEM_B_DQ<0>

=MEM_B_DQ<16>

=MEM_B_DQ<18>

=MEM_B_DQ<27>

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<4>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_CS_L<0>MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CLK_N<1>MEM_B_CLK_N<0>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<2>

MEM_RESET_L

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

=PPVDDQ_S3_MEM_B

MEM_B_BA<2>

MEM_B_A<12>
MEM_B_A<9>

MEM_B_A<8>

=PPDDRVTT_S0_MEM_B

=PP3V3_S0_MEM_B_SPD

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50>
=MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42>
=MEM_B_DQ<43>

=MEM_B_DQ<40>
=MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32>
=MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_CKE<0>

=MEM_B_DQ<26>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<17>

=MEM_B_DQ<10>
=MEM_B_DQ<11>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62>
=MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQ<53>

=MEM_B_DQ<60>
=MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<47>

=PPVDDQ_S3_MEM_B

=MEM_B_DQ<36>
=MEM_B_DQ<37>

=MEM_B_DQ<38>
=MEM_B_DQ<39>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<6>
MEM_B_A<4>

MEM_B_A<11>
MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<13>

=MEM_B_DQ<14>
=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<1>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<4>
=MEM_B_DQ<5>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_A<10>
MEM_B_BA<0>

MEM_B_A<13>

=PP3V3_S0_MEM_B_SPD

=PP3V3_S0_MEM_B_SPD

SYNC_DATE=10/30/2013SYNC_MASTER=J78_NAT

DRAM: SO-DIMM CONNECTOR B SLOT0

24 7

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

47

24

25 24

25 24

24 22 21 12

25 24

25 24

25 24

25 24

25 24

10%
X5R

1UF

402

10V

C2550

1

2

25 24

25 24

25 24

25 24

6.3V

20%

402-LF

CERM

2.2UF

C2540

1

2

1/16W

5%

402

MF-LF

10K

R2540

1

2

1/16W

5%
MF-LF

10K

402

R2541

1

2

25 24

10%
X5R

402

10V

1UF

C2551

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

402

10%
X5R

1UF

10V

C2552

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

7

24 7

24 7

24 7

24 7

24 7

45 44 24 22 21

6.3V

2.2UF

CERM
402-LF

20%

C2535

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

C2536

CERM

0.1UF

20%

402

10V

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

F-ANG-SM-1

SODIMM-P0.60-D8

J2500

205

206

207

208

209

CRITICAL

SODIMM-P0.60-D8

F-ANG-SM-1

J2500

9897

9695

9291

90

86

89

85

107

8483

119

80

78

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

15
17

4
6

16
18

21
23

33
35

22
24

34
36

39
41

51
53

40
42

50
52

57
59

67
69

56
58

68
70

129
131

141
143

130
132

140
142

147
149

157
159

146
148

158
160

163
165

175
177

164
166

174
176

181
183

191
193

180
182

192
194

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

81 82

87 88

93 94

99 100

105 106

111 112

117 118

123 124

199

126

1 2
3

8

9

13 14

19 20

25 26

31 32

37 38

43 44

48

49

54

55

60

61

65 66

71 72

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

X5R
603

6.3V

10UF

20%

C2500

1

2

X5R
603

6.3V

20%

10UF

C2501

1

2

0.1UF

CERM
402

20%
10V

C2518

1

2

25 24

0.1UF

10V
402

CERM

20%

C2510

1

2

0.1UF

CERM
402

20%
10V

C2511

1

2

0.1UF

10V

20%

402

CERM

C2512

1

2

0.1UF

10V
CERM

20%

402

C2519

1

2

0.1UF

CERM
402

10V

20%

C2520

1

2

0.1UF

10V
CERM
402

20%

C2521

1

2

0.1UF

10V

20%

402

CERM

C2522

1

2

0.1UF

10V
CERM
402

20%

C2513

1

2

0.1UF

CERM
402

20%
10V

C2514

1

2

0.1UF

10V
402

CERM

20%

C2515

1

2

7

0.1UF

20%
CERM

402

10V

C2516

1

2

0.1UF

10V

20%

402

CERM

C2523

1

2

7

7

24 7

24 7

24 7

24 7

0.1UF

CERM

10V
402

20%

C2517

1

2

7

24 7

24 7

24 7

7

25 24

25 24

25 24

25 24

25 24

7

25 24

C2530

6.3V

20%
CERM

402-LF

2.2UF

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

24 7

20%

0.1UF

10V
402

CERM

C2531

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

24 7

7

7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

7

47

24

10%
X5R

10V
402

1UF

C2553

1

2

89 24 23

24 20

24 22 21 20

23

23

23

23

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

NC

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

Page Notes

Signal aliases required by this page:

Power aliases required by this page:

- =PP1V5_S0_MEM_B

(NONE)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =I2C_SODIMMA_SCL

- =PPVDDQ_S3_MEM_B

- =PPDDRVTT_S0_MEM_B

P/N: 516S1019

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

24 OF 93

VOLTAGE=0.675V

26 OF 121

0.24.0

051-00673

=MEM_B_DQ<0>

=MEM_B_DQ<16>

=MEM_B_DQ<18>

=MEM_B_DQ<27>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<4>

MEM_B_CS_L<3>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_CLK_N<2>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<1>

MEM_B_BA<2>

MEM_B_A<12>
MEM_B_A<9>

MEM_B_A<8>

=PPDDRVTT_S0_MEM_B

=PP3V3_S0_MEM_B_SPD

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50>
=MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42>
=MEM_B_DQ<43>

=MEM_B_DQ<40>
=MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32>
=MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<2>

MEM_B_A<5>

MEM_B_CKE<2>

=MEM_B_DQ<26>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<17>

=MEM_B_DQ<10>
=MEM_B_DQ<11>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<1>

MEM_B_A<3>

MEM_B_A<10>
MEM_B_BA<0>

MEM_B_A<13>

=MEM_B_DQ<54>
=MEM_B_DQ<55>

=MEM_B_DQS_P<0>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<6>
=MEM_B_DQ<7>

=MEM_B_DQ<12>

=MEM_B_DQ<20>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

=MEM_B_DQ<13>

=MEM_B_DQ<21>

=MEM_B_DQ<22>
=MEM_B_DQ<23>

=MEM_B_DQ<28>
=MEM_B_DQ<29>

=MEM_B_DQS_P<3>

=MEM_B_DQ<30>

=PPVDDQ_S3_MEM_B

MEM_B_CKE<3>

MEM_B_A<15>
MEM_B_A<14>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<2>
MEM_B_A<0>

MEM_B_CLK_P<3>

MEM_B_ODT<3>

MEM_B_ODT<2>

MEM_B_BA<1>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<47>

=MEM_B_DQ<44>

=MEM_B_DQ<46>

=MEM_B_DQS_P<5>

=MEM_B_DQ<45>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<53>

=MEM_B_DQS_P<7>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

=MEM_B_DQ<31>

=MEM_B_DQS_N<0>

MEM_RESET_L

=MEM_B_DQS_N<3>

MEM_B_CLK_N<3>

MEM_B_RAS_L

MEM_B_CS_L<2>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<7>

MEM_EVENT_L

=PP3V3_S0_MEM_B_SPD

=PP3V3_S0_MEM_B_SPD

=PPVDDQ_S3_MEM_B

MEM_DIMM3_SA<1>

MEM_DIMM3_SA<1>

MEM_DIMM3_SA<0>

MEM_DIMM3_SA<0>

PPVREF_S3_MEM_VREFCA

=MEM_B_DQ<52>

=PPDDRVTT_S0_MEM_B

PPVREF_S3_MEM_VREFDQ_B

SYNC_MASTER=J78_NAT SYNC_DATE=10/30/2013

DRAM: SO-DIMM CONNECTOR B SLOT1

23 7

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

47

23

25 23

25 23

23 22 21 12

25 23

25 23

25 23

25 23

25 23

402

10V

1UF

X5R

10%

C2650

1

2

25 23

25 23

25 23

25 23

CERM
402-LF

20%

2.2UF

6.3V

C2640

1

2

1/16W

5%

402

MF-LF

10K

R2640

1

2

1/16W

5%

402

MF-LF

10K

R2641

1

2

25 23

1UF

402

10V
X5R

10%

C2651

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

1UF

402

10V
X5R

10%

C2652

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

7

23 7

23 7

23 7

23 7

23 7

45 44 23 22 21

2.2UF

CERM
402-LF

20%

6.3V

C2635

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

CERM
402

20%
10V

0.1UF

C2636

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

F-ANG-SM-1

SODIMM-P0.60-D8

J2600

205

206

207

208

209

SODIMM-P0.60-D8

F-ANG-SM-1

CRITICAL

J2600

9897

9695

9291

90

86

89

85

107

8483

119

80

78

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

15
17

4
6

16
18

21
23

33
35

22
24

34
36

39
41

51
53

40
42

50
52

57
59

67
69

56
58

68
70

129
131

141
143

130
132

140
142

147
149

157
159

146
148

158
160

163
165

175
177

164
166

174
176

181
183

191
193

180
182

192
194

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

81 82

87 88

93 94

99 100

105 106

111 112

117 118

123 124

199

126

1 2
3

8

9

13 14

19 20

25 26

31 32

37 38

43 44

48

49

54

55

60

61

65 66

71 72

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

20%

10UF

6.3V
603

X5R

C2600

1

2

10UF

20%

6.3V
603

X5R

C2601

1

2

10V

20%

402

CERM

0.1UF

C2618

1

2

25 23

10V

20%

402

CERM

0.1UF

C2610

1

2

10V

20%

402

CERM

C2611

1

2

0.1UF

10V

20%

402

CERM

0.1UF

C2612

1

2

CERM
402

20%
10V

0.1UF

C2619

1

2

CERM
402

10V

20%

0.1UF

C2620

1

2

402

20%
10V
CERM

0.1UF

C2621

1

2

CERM
402

20%
10V

0.1UF

C2622

1

2

CERM
402

20%
10V

0.1UF

C2613

1

2

CERM
402

20%
10V

0.1UF

C2614

1

2

CERM
402

20%
10V

0.1UF

C2615

1

2

7

CERM
402

20%
10V

0.1UF

C2616

1

2

CERM
402

20%
10V

0.1UF

C2623

1

2

7

7

23 7

23 7

23 7

23 7

CERM
402

20%
10V

0.1UF

C2617

1

2

7

23 7

23 7

23 7

7

25 23

25 23

25 23

25 23

25 23

7

25 23

2.2UF

20%
CERM

402-LF

6.3V

C2630

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

23 7

20%
10V
CERM
402

0.1UF

C2631

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

23 7

7

7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

7

47

23

10%

1UF

402

10V
X5R

C2653

1

2

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

24

24

24

24

23 22 21 20

89 24 23

23 20

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

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IN

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OUT

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NC

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

NC

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

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IN

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IN

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IN

www.laptoprepairsecrets.com

THERE ARE NO PIN SWAPS

25 OF 93

27 OF 121

0.24.0

051-00673

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>

=MEM_A_DQ<3>

=MEM_A_DQ<4>

=MEM_A_DQ<5>

=MEM_A_DQ<6>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQ<14>

=MEM_A_DQ<15>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<23>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<26>

=MEM_A_DQ<27>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQ<32>

=MEM_A_DQ<33>

=MEM_A_DQ<34>

=MEM_A_DQ<35>

=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<42>

=MEM_A_DQ<43>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQ<50>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_A_DQ<53>

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<58>

=MEM_A_DQ<59>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<0>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<3>

=MEM_A_DQS_P<4>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<6>

=MEM_A_DQS_P<7>

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<8>

=MEM_B_DQ<9>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<12>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<16>

=MEM_B_DQ<17>

=MEM_B_DQ<18>

=MEM_B_DQ<19>

=MEM_B_DQ<20>

=MEM_B_DQ<21>

=MEM_B_DQ<22>

=MEM_B_DQ<23>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<26>

=MEM_B_DQ<27>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQ<32>

=MEM_B_DQ<33>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

=MEM_B_DQ<40>

=MEM_B_DQ<41>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQ<46>

=MEM_B_DQ<47>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<58>

=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQ<62>

=MEM_B_DQ<63>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<4>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<0>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<3>

=MEM_B_DQS_P<4>

=MEM_B_DQS_P<5>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<7>

MEM_A_DQ<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MEM_A_DQ<3>

MAKE_BASE=TRUE

MEM_A_DQ<4>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MEM_A_DQ<8>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<9>

MEM_A_DQ<10>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<11>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<18>

MEM_A_DQ<19>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<25>

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<28>

MEM_A_DQ<29>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<30>

MEM_A_DQ<31>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<32>

MEM_A_DQ<33>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<34>

MEM_A_DQ<35>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<36>

MEM_A_DQ<37>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQ<47>

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MAKE_BASE=TRUE

MEM_A_DQ<50>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<51>

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<55>

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MEM_A_DQ<63>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<5>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_B_DQ<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<10>

MEM_B_DQ<11>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<12>

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQ<15>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<16>

MEM_B_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<19>

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<22>

MEM_B_DQ<23>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<24>

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<30>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<32>

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MEM_B_DQ<41>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<42>

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<47>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MEM_B_DQ<50>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<51>

MEM_B_DQ<52>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<53>

MEM_B_DQ<54>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<55>

MAKE_BASE=TRUE

MEM_B_DQ<56>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MEM_B_DQ<58>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<59>

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

=MEM_B_DQ<34>

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

DRAM: ALIASES AND BITSWAPS

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24 23

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

6 - PCIE_RST_2_N

0 - GPIO_13

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

7 - PCIE_RST_3_N

If strap != bit then security is enabled?

Used for straps in host mode

DEBUG: For monitoring current/voltage

SNK0 AC Coupling

SNK1 AC Coupling

(TBT_SPI_MISO)(TBT_SPI_MOSI)

(TBT_SPI_CLK)

depends on the code in the flash.

bit in the flash, so the active-level

Security strap setting is XORed with

(TBT_SPI_CS_L)

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

8 - GPIO_15
9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

11 - GPIO_0

5 - PCIE_RST_1_N

3 - GPIO_3

2 - GPIO_2

4 - GPIO_5

1 - GPIO_1

10 - GPIO_14

13 - GPIO_10

12 - GPIO_12

NOTE: The following pins require testpoints:

26 OF 93

28 OF 121

0.24.0

051-00673

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

TBT_CLK25M_IN

TBT_GPIO7

TBT_GPIO2

TBT_TMU_CLK_OUT

TBT_CLK25M_IN

TBT_CLK25M_OUT

TBT_CLK25M_OUTTBT_CLK25M_R

HDMITBTMUX_SEL_TBT

TBT_B_CONFIG2_BUF

TBT_WAKE_L

=TBT_BATLOW_L
TBTDP_AUXIO_EN

TP_TBT_THERM_DP

JTAG_TBT_TCK
JTAG_TBT_TDO

TBT_PCIE_RESET_L

JTAG_TBT_TDI
JTAG_TBT_TMS

PP3V3_TBTLC

=PP3V3_S4_TBT

TBTDP_AUXIO_EN

=TBT_BATLOW_L

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK1_AUX_C_N

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK0_AUX_C_N

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<3>

PP3V3_TBTLC

PCIE_TBT_R2D_C_N<0>

=PP3V3_S4_TBT

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CP<2>

TP_TBT_MONDC1

TP_TBT_MONDC0

TBTROM_WP_L

TBTROM_HOLD_L

TBT_TEST_PWR_GOOD

TBT_TEST_EN

TBT_SPI_MISO

TBT_RSENSE

TBT_PWR_ON_POC_RST_L

TBT_MONOBSP
TBT_MONOBSN

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR_L

TBT_DDC_XBAR_EN_L

TBT_DDC_XBAR_EN_L

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_N<0> TBT_B_HV_EN

TBT_B_HV_EN

TBT_B_DP_PWRDN

TBT_B_DP_PWRDN

TBT_B_D2R_P<1>

TBT_B_CIO_SEL

TBT_A_R2D_C_N<0>

TBT_A_HV_EN

TBT_A_DP_PWRDN

TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

PCIE_TBT_R2D_P<3>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_N<0>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_N<0>

DP_TBTSRC_HPD

DP_TBTSNK1_AUX_P

DP_TBTSNK1_AUX_P

DP_TBTSNK1_AUX_N

DP_TBTSNK1_AUX_N

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_AUX_P

DP_TBTSNK0_AUX_P
DP_TBTSNK0_AUX_N

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_HPD

DP_TBTPB_ML_C_P<3>
DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_HPD

DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_N<2>

DP_TBTPB_ML_C_P<1>

TBT_B_LSRX

HDMITBTMUX_SEL_TBT

TBT_B_CONFIG1_BUF

TBT_B_LSTX

DP_TBTSRC_HPD

TBT_B_D2R_N<0>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUX_C_P

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_ML_P<1>

TBT_PWR_EN

TBT_CIO_PLUG_EVENT_L

TBT_SPI_CLK

DP_TBTSNK1_AUX_C_P

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

TBT_DFT_STRAP_3

TBT_ROM_SECURITY_XOR

TBT_DFT_STRAP_1

PCIE_TBT_D2R_C_N<3>

TBT_RBIAS

TP_TBT_PCIE_RESET0_L

PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>

TBT_SPI_MOSI

PP3V3_TBTLC

DP_TBTSNK0_ML_P<0>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_AUX_N

TBT_B_D2R_P<0>

TBT_B_D2R_N<1>

TBT_A_HV_EN
TBT_A_CIO_SEL
TBT_A_DP_PWRDN

TBT_B_R2D_C_P<1>

DP_TBTSNK0_ML_P<2>
DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<1>
DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<0>

TP_DP_TBTSRC_ML_CP<3>

TP_DP_TBTSRC_ML_CP<1>
TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<2>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CN<2>

PP3V3_TBTLC

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

TBT_A_LSRX

TBT_A_LSTX

TBT_A_D2R_N<1>

TBT_A_D2R_P<1>

TBT_A_CONFIG2_BUF

TBT_A_CONFIG1_BUF

TBT_A_R2D_C_P<1>
TBT_A_R2D_C_N<1>

DP_TBTSNK1_ML_N<3>

TBT_SPI_CS_L

TBT/DP: Host (1 of 2)

SYNC_DATE=11/06/2014SYNC_MASTER=BRANCH_JERRYCHOW

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

21

C2847

10% 16V

0.1UF

X5R-CERM 0201

21

C2846

10% 16V

0.1UF

X5R-CERM 0201

21

C2844

16V10%

0.1UF

X5R-CERM 0201

21

C2845

16V10% X5R-CERM

0.1UF

0201

21

C2843

16V10% X5R-CERM

0.1UF

0201

2

1

R2891

MF

1/20W

201

3.3K

5%

21

C2842

16V10% X5R-CERM

0.1UF

0201

21

C2841

16V10% X5R-CERM

0.1UF

0201

21

C2840

16V10% X5R-CERM

0.1UF

0201

21

C2807

020110%

0.1UF

16V
X5R-CERM

21

C2806

020110%

0.1UF

16V
X5R-CERM

21

C2805

0201

0.1UF

10%

16V
X5R-CERM

21

C2804

0.1UF

10% X5R-CERM 0201

16V

2

1

R2892

MF

1/20W

201

3.3K

5%

21

C2803

10%

16V

0.1UF

X5R-CERM 0201

21

C2802

020110%

0.1UF

16V
X5R-CERM

21

C2800

020110%

0.1UF

16V
X5R-CERM

21

C2801

0.1UF

020110%

16V
X5R-CERM

2

1

R2851

201

1M

MF

1/20W

5%

21

R2850

0201

0

5%

1/20W

MF

21

C2850

0201

12PF

5%

25V

NP0-C0G

21

C2851

0201

5%

25V

NP0-C0G

12PF

3 1

4 2

Y2850

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

J4

L22

J24

L24

K5

U2

E16

P1

AB23

AA24

AA4

AB1

AB7

W8

R6

U6

W2

AA6

AD1

U20

AB21
AD21

W20

R4

AD17

AD9

AD5

AD19

AD11

AD7

P5

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

V3

M5
P7

N6

A22
B23

A20
B21

M1

D3

W24
U24

W22
U22

R24
N24

R22
N22

K3
K1

N8

J6

M3

A18
B19

A16
B17

J22

G24

E24

G22

E22

L4
L2

W18
W16

AC24

AD23

V1

AD3

AB3

T3

T1

F3P3

R2N2

M7

V7

T7

Y1

Y7

H5

L6

F1R8

Y3

AA2

T5

U8

AC2

J2

A14
B15

A12
B13

A10
B11

A8
B9

U4

H3
H1

E6
D5

E8
D7

E10

D9

E12
D11

AB5

G4
G2

E14
D13

D15

E18
D17

E20
D19

U2800

FALCON_RIDGE_1_FCBGA_FALCON

CRITICAL

OMIT_TABLE

FCBGA

FALCON RIDGE

W6

L8

AD15

AD13

2

1

R2832

1%

MF

1/20W

201

200K

1/20W

100K

R2879

2

5%

1

201

MF

2

5%

1

R2878

201

1/20W

MF

100K

2

1

R2882

MF

1/20W

201

5%

100K

2

1

R2884

5%

100K

MF

1/20W

201

2

1

R2829

10K

201

1/20W

MF

5%

2

1

R2881

MF

1/20W

201

5%

100K

2

1

R2862

MF

1/20W

201

10K

5%

2

1

R2867

MF

1/20W

201

10K

5%

NO STUFF

2

1

R2863

MF

1/20W

201

10K

5%

2

1

R2861

5%

10K

201

1/20W
MF

30 29 26

31 26

3

8

9

7

4

25

1

6

U2890

4MBIT

USON

W25X40CLXIG

OMIT_TABLE

CRITICAL

2

1

R2883

5%

201

1/20W
MF

100K

19

31 26

19

2

1

R2880

100K

MF

1/20W

201

5%

2

1

R2885

NO STUFF

5%

10K

201

1/20W

MF

2

1

R2886

NO STUFF

5%

201

1/20W
MF

10K

2

1

R2887

10K

201

MF

1/20W

5%

2

1

R2888

5%

10K

201

1/20W

MF

2

1

R2815

NONE

NOSTUFF

NONE
NONE

OMIT

0201

27

11

11

NO STUFF

2

1

R2899

MF

5%

1/20W

10K

201

11

19

27 26

30 26

30

30 26

29 26

29

29 26

29

29

29

29

29

19

19

19

19

30

30

30

30

30

30

30

19

30

30

29

29

79

79

2

1

C2890

BYPASS=U2890::2mm

1UF

10%

6.3V
CERM

402

79

79

79

79

79

79

79

79

21

C2839

0201

X5R-CERM

0.1UF

16V10%

21

C2838

0201

0.1UF

X5R-CERM

16V10%

21

C2837

10% 0201

0.1UF

X5R-CERM

16V

21

C2836

X5R-CERM

0201

0.1UF

16V10%

21

C2835

X5R-CERM

0.1UF

020116V10%

21

C2834

0.1UF

0201

X5R-CERM

16V10%

21

C2833

0201

0.1UF

X5R-CERM

16V10%

21

C2832

0.1UF

X5R-CERM

16V10% 0201

21

C2831

0201

0.1UF

X5R-CERM

16V10%

21

C2830

0201

0.1UF

X5R-CERM

16V10%

21

C2820

0201

0.1UF

X5R-CERM

16V10%

21

C2821

0201

0.1UF

X5R-CERM

16V10%

2

1

R2855

1%

1K

201

MF

1/20W

21

C2822

0201

X5R-CERM

10% 16V

0.1UF

21

C2823

0201

0.1UF

X5R-CERM

16V10%

21

C2824

0201

X5R-CERM

0.1UF

10% 16V

21

C2825

0201

0.1UF

X5R-CERM

16V10%

21

C2826

0201

0.1UF

X5R-CERM

10% 16V

21

C2827

0201

0.1UF

X5R-CERM

16V10%

21

C2828

0201

0.1UF

X5R-CERM

10% 16V

79

79

79

79

79

79

79

79

79

79

21

C2829

0.1UF

16V10% 0201

X5R-CERM

2

1

R2893

MF

1/20W

201

3.3K

5%

29

29

2

1

R2831

MF

1/20W

201

100K

5%

2

1

R2830

MF

1/20W

201

100K

5%

30

30

30

30

30

30

31

30

30

30

29

29

29

29

29

29

29

29

29

31

2

1

R2825

100

5%

MF

1/20W

201

80

80

2

1

R2890

MF

1/20W

201

3.3K

5%

26

26

26

26

26

89 27 26

89 72 31 30 29 27 26 19

30 29 26

31 26

89 27 26

89 72 31 30 29 27 26 19

41

41

91

27 26

31 26

30 26

30 26

29 26

29 26

41 26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

41 26

26

26

91

89 27 26

26

26

26

26

26

26

26

26

26

41

41

41

41

41

41

26

26

41

41

89 27 26

26

26

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

NC

NC

DISPLAY PORT

PORTS

SYM 1 OF 2

PCIE GEN2

MISC

PERP_3

PERN_0

TMS

TDI

PERST_OD_N

GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_AUX_P

PA_DPSRC_HPD

PA_CIO1_RX_P

PA_DPSRC_1_P

PA_DPSRC_3_P

PA_CIO0_TX_P/DPSRC_0_P

PA_CIO1_TX_P/DPSRC_2_P

PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE

PA_CIO0_RX_P

DPSNK1_0_P

DPSNK1_AUX_P

DPSNK1_HPD

DPSNK1_2_P

DPSNK1_3_P

DPSNK0_AUX_P

DPSNK0_HPD

DPSNK0_0_P

DPSNK0_1_P

DPSNK0_2_P

DPSNK0_3_P

EE_CS_N

TEST_PWR_GOOD

TEST_EN

TDO

TCK

EE_CLK

EE_DO

MONOBSP
MONOBSN

THERMDA

EE_DI

MONDC0
MONDC1

PWR_ON_POC_RSTN

PERN_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0

PB_AUX_P

PB_LSRX/CIO_3_LSOE

PB_LSTX/CIO_3_LSEO

PB_DPSRC_HPD

PB_DPSRC_3_P

PB_DPSRC_1_P

PB_CIO3_RX_P

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_11/PB_CIO_SEL/BYP1

GPIO_1/PB_HV_EN/BYP0

GPIO_14
GPIO_15

PB_CONFIG2/CIO_2_LSOE

PB_CONFIG1/CIO_2_LSEO

PB_CIO3_TX_P/DPSRC_2_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO2_RX_P

GPIO_9/SX_CTRL_OD*

GPIO_7_OD/CIO_SCL_OD

GPIO_6_OD/CIO_SDA_OD

GPIO_4/WAKE_OD_N

GPIO_3/FORCE_PWR

DPSRC_0_P

DPSRC_1_P

DPSRC_3_P

DPSRC_2_P

DPSRC_HPD_OD

GPIO_2/TMU_CLK_IN/AC_PRESENT

TMU_CLK_OUT

XTAL_25_IN

GPIO_17
GPIO_18
GPIO_19

RSVD_GND

GPIO_16/DEVICE_PCIE_RST_N

REFCLK_100_IN_P

PCIE_CLKREQ_OD_N

RBIAS

PETN_3

PETP_3

PETN_2

RSENSE

PETP_2

PETN_1

PETP_1

PETP_0
PETN_0

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

DPSNK0_0_N

DPSNK0_1_N

DPSNK0_2_N

DPSNK0_3_N

DPSNK0_AUX_N

DPSNK1_0_N

DPSNK1_2_N

DPSNK1_3_N

DPSNK1_AUX_N

DPSRC_0_N

DPSRC_1_N

DPSRC_2_N

DPSRC_3_N

GPIO_8/EN_CIO_PWR_N_OD

PA_AUX_N

PA_CIO0_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO1_RX_N

PA_CIO1_TX_N/DPSRC_2_N

PA_DPSRC_1_N

PA_DPSRC_3_N

PB_AUX_N

PB_CIO2_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO3_RX_N

PB_CIO3_TX_N/DPSRC_2_N

PB_DPSRC_1_N

PB_DPSRC_3_N

REFCLK_100_IN_N

XTAL_25_OUT

DPSRC_AUX_P
DPSRC_AUX_N

DPSNK1_1_N

DPSNK1_1_P

OUT

IN

DI/IO0

HOLD*

WP*

CLK

CS*

THRM_PADGND

DO/IO1

VCC

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

IN

IN

IN

IN

BI

BI

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

www.laptoprepairsecrets.com

U2940

TPS22920

Load Switch

1200 mA EDP

Push-pull output

Isolated to reduce noise from SVR

Part

Type

R(on)

@ 1.05V

Max Current = 4A (85C)

8 mOhm Typ

11.5 mOhm Max

1.05V TBT "CIO" Switch

25 mA EDP

1900 mA EDP

Internal switch not functional on RR.

Delay = 4.04ms nominal

TBT "POC" Power-up Reset

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

Vth = 2.508V nominal

SVR input to RR - 1100 mA EDP

100 mA EDP

EDP: 1.25 A

2.4 W (Single-Port)

3.1 W (Dual-Port)

Pull-up (S0) on PCH page

POC input to RR - 150 mA EDP

700 mA EDP

27 OF 93

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.5000

DIDT=TRUE
SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.5000

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1800

MIN_LINE_WIDTH=0.4000

29 OF 121

0.24.0

051-00673

PP1V05_TBT

TBT_PWR_ON_POC_RST_L

TBTPOCRST_SENSE

=PP3V3_S0_PCH_GPIO

TBT_POC_RESET_L

TBT_PWR_REQ_L

=PP3V3_S0_PCH_GPIO

TBT_EN_CIO_PWR_L

=PP3V3_S4_TBT

PP1V05_TBT

P1V05TBT_SW

PP1V05_TBTRDV

PP3V3_TBTRDV PP3V3_S4_TBT_F

TBTPOCRST_MR_L

TBTPOCRST_CT

TBT_EN_CIO_PWR

SMC_DELAYED_PWRGD

PP1V05_TBTCIO

PP3V3_TBTLC

=PP3V3_S4_TBT

PP3V3_TBTLC

SYNC_MASTER=BRANCH_JERRYCHOW SYNC_DATE=09/10/2014

TBT/DP: Host (2 of 2)

20%

1.0UF

X5R

6.3V

0201-1

C2930

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2931

1

2

0201-1

20%

1.0UF

X5R

6.3V

C2932

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2902

1

2

1.0UF

X5R

6.3V

20%

0201-1

C2901

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2900

1

2

0201-1

20%

1.0UF

X5R

6.3V

C2905

1

2

20%

6.3V
X5R

0201-1

1.0UF

C2904

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2921

1

2

10UF

20%

0402-1

CERM-X5R

6.3V

C2920

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2903

1

2

FALCON_RIDGE_1_FCBGA_FALCON

OMIT_TABLE

CRITICAL

FCBGA

FALCON RIDGE

U2800

B5

A4
A6
B3

J8

K9

L14
M15
M17

P17
V19

J10
J12
K11
L10
M11
N10
N14
P11
P15
R10
R14
T11
T15
U10
U14
V11

G10
G12
G14
G16
G18
H19

H9

J18

K15
K17
K19

K7

L16
M19

P19
T19

U18

V15

V17
W12
W14

D1
E2
H11
N4
V5
W4

Y5

H13
H15
H17
H7
L18
N18
R18
W10

A2

A24

AA14
AA20
AA22

AA8
AB11
AB17
AC10
AC12
AC14
AC16
AC18
AC20
AC22

AC4
AC6
AC8

B1

B7
C10
C12
C14
C16
C18

C2
C20
C22
C24

C4

C6

C8
D21
D23

E4

F11
F13
F15
F17
F19
F21
F23

F5

F7

F9

G20
G6
G8
H21
H23
J14
J16
J20
K13
K21
K23
L12
L20
M13
M21
M23
M9
N12
N16
N20
P13
P21
P23
P9
R12
R16
R20
T13
T17
T21
T23
T9
U12
U16
V13
V21
V23
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y9

SOT563

DMN5L06VK-7

Q2945

3

5

4

SOT563

DMN5L06VK-7

Q2945

6

2

1

330PF

X7R

10%
16V

0201

C2995

1

2

1/20W

100K

201

MF

5%

R2992

1

2

TPS3895ADRY

USON

CRITICAL

U2990

5

1

2

3

4

6

14 11

X7R-CERM

10%
50V

0.001UF

0402

C2991

1

2

DMN32D2LFB4

DFN1006H4-3

Q2995

3

1

2

100K

5%
1/20W
MF
201

R2990

1

2

73 45 44

MF

201

100K

1/20W

5%

R2995

1

2

13

X5R

10%

0.1UF

25V

402

C2990

1

2

1/20W
MF
201

24.9K

1%

R2991

1

2

26

SHORT_SM_BASE

PLACE_NEAR=C2961.1:1MM

OMIT

SM

XW2960

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2950

1

2

CERM-X5R

6.3V

0402-1

10UF

20%

C2951

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2952

1

2

20%

10UF

0402-1

CERM-X5R

6.3V

C2953

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2961

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2960

1

2

26

1.0UF

6.3V
X5R

0201-1

20%

C2970

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2980

1

2

1.0UF

0201-1

20%

X5R

6.3V

C2981

1

2

20%

X5R

6.3V

0201-1

1.0UF

C2940

1

2

CRITICAL

CSP

TPS22920

U2940

D1

D2

A2

B2

C2

A1

B1

C1

100K

201

MF

1/20W

5%

R2945

1

2

NSR1020MW2T1G

SOD-323

CRITICAL

D2920

A

K

6.3V

CERM-X5R

0402-1

10UF

20%

C2923

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2922

1

2

DEFAULT_INDUCTOR_680.000000nH_2_1

SM

680NH-30%-3.6A-35MOHM

CRITICAL

L2920

1 2

X5R

6.3V

1.0UF

20%

0201-1

C2910

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2911

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2906

1

2

27

89 27

89 27

89 72 31 30 29 27 26 19

27

31

31

31

89 27 26

89 72 31 30 29 27 26 19

89 27 26

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SYM 2 OF 2

VCC

GND

SVR_IND

SVR_AMON

VSS

SVR_VCC1P0

VCC1P0_RDV_DECAP

VCC3P3

VCC3P3_LC

VCC3P3_RDV_DECAP

VSS

VCC1P0_CIO

DS

VER 5

G

GS

D

VER 3

VCC

CT

SENSE_OUTENABLE

SENSE

GND

OUT

GS

SYM_VER_3

D

IN

IN OUT

IN

VIN

ON

GND

VOUT

NC

www.laptoprepairsecrets.com

Page Notes

- =TBT_RESET_L

Power aliases required by this page:

- =PP15V_TBT_REG (15V Boost Output)

TBTBST:Y - Stuffs 15V boost circuitry.

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP1V05_TBT_FET (1.05V FET Output)

Signal aliases required by this page:

- =TBT_CLKREQ_L

BOM options provided by this page:

28 OF 93

051-00673

0.24.0

30 OF 121

SYNC_DATE=10/09/2013SYNC_MASTER=J78_JERRY

Thunderbolt: Power Support

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

NOTE: Polarity Swapped for layout!

TBT: UNUSED

TBT Dir

Thunderbolt Connector A

514-0831

353S3812

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(Both C's)

on AC-coupled signals.

(Both C's)

NOTE: Polarity Swapped for layout!

(0-18.9V)

TBT: TX_1

TBT: TX_0

(0-18.9V)

DP Dir

DP Dir

TBT : RX_0

to 100K (DPv1.1a).

Low: 0 - 0.8V

High: 2.0 - 5.0V

Sink HPD range:

greater than or equal

down HPD input with

DP Source must pull

TBT : RX_1

(Both C's)

Nominal Min Max

3.3V/HV Power MUX

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

V3P3 must be S4 to support

IV3P3 1100mA 1030mA 1200mA

Nominal Min Max

353S3931

18.9V Max

TBT Dir

TBT: Terminated

470k R's for ESD protection

TBT: LSX_R2P/P2R (P/N)

wake from Thunderbolt devices.

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

(Both C's)

29 OF 93

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=15V

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.3800

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

MIN_LINE_WIDTH=0.3800

VOLTAGE=15V

MIN_NECK_WIDTH=0.2000

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

32 OF 121

0.24.0

051-00673

TBT_A_CONFIG2_RC_R

TBT_A_HPD_R

=TBT_S0_EN

TBT_A_HV_EN

=TBTAPWRSW_EN

=PP3V3_S4_TBTAPWRSW

DP_TBTPA_ML_C_N<1>

DP_TBTPA_AUXCH_C_P

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_P<0>

DP_TBTPA_AUXCH_C_N

DP_TBTPA_HPD

TBT_A_LSTX
TBT_A_LSRX

TBTAPWRSW_ISET_V3P3

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_S0

TBTACONN_20_RC

TBTACONN_1_C

TBT_A_R2D_P<1>

TBT_A_R2D_P<0>

TBT_A_R2D_N<1>

TBT_A_HPD

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R1_AUXDDC_N

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_RC

TBT_A_CONFIG1_RC

DP_TBTPA_ML_N<1>

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

TBT_A_CIO_SEL
TBTDP_AUXIO_EN
TBT_A_DP_PWRDN

TBT_A_D2R_P<1>

TBT_A_R2D_N<0>

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

TBTACONN_7_C

PP3V3RHV_S4_TBTAPWR_F

TBT_A_D2R_C_N<0>

TBT_A_D2R_C_P<0>

DP_TBTPA_ML_P<3>
DP_TBTPA_ML_N<3>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

TBT_A_HPD

TBT_A_D2R_P<0>

TBT_A_D2R_N<0>

=PPHV_SW_TBTAPWRSW

PP3V3RHV_S4_TBTAPWR

TBT_A_D2R_C_P<1>

DP_TBTPA_AUXCH_N

DP_TBTPA_AUXCH_P

DP_TBTP_A_DDC_DATA

DP_TBTP_A_DDC_CLK

TBT_A_CONFIG1_BUF

DP_TBTPA_ML_P<1>

DP_TBTPA_ML_C_P<1>

TBT_A_D2R_N<1>

TBT_A_D2R_C_N<1>

=PP3V3_S4_TBT

SYNC_MASTER=BRANCH_JERRYCHOW SYNC_DATE=09/10/2014

TBT/DP: Connector A

DEFAULT_RESISTOR_0.001OHM_2_1

1/20W

5%

0

MF
201

R3292

1

2

DEFAULT_RESISTOR_0.001OHM_2_1

MF

2011/20W

5%

0

R3291

1 2

10%

0201

X7R

330PF

16V

C3295

1

2

16V

10%

X7R

330PF

0201

C3294

1

2

35.7K

R3211

201

1/20W
MF

1%

1

2

35.7K

1%

1/20W

201

MF

R3210

1

2

GND_VOID=TRUE

GND_VOID=TRUE

4

1

CBTL05024

U3220

CRITICAL

HVQFN24-COMBO

SIGNAL_MODEL=CBTL05024_HVQFN24_COMBO_CBTL05024_TBT

2

24

23
22

1816

5

10

11

6

20

19

9

21

1712

13

14

157

8

25

3

10%
25V
X5R-CERM
0201

0.01UF

C3206

1

2

0201

X5R-CERM

25V

10%

0.01UF

C3205

1

2

26

26

GND_VOID=TRUE

C3276

201

4V

20%
CERM-X5R-1

0.47UF

1 2

21

201

4V

20%

0.47UF

GND_VOID=TRUE

C3277

CERM-X5R-1

26

2

1

C3220

CERM-X5R

6.3V

0.1UF

10%

0201

26

30 26

26

GND_VOID=TRUE

MF

1/20W

5%

470K

201

R3278

1

2

1/20W

201

GND_VOID=TRUE

470K

5%

MF

R3279

1

2

CRITICAL

17

CD3211A1RGP

QFN

U3210

5

16 4

1

2

3

13

15

11 10

9

8

12
14

21

19
20

18

6
7

10

CON_F40ANG_25MT_MDP_DUAL_TH_F_ANG_TH_DUAL_MDP_D8

F-ANG-TH

DUAL-MDP-D8

CRITICAL

J3200

18

16

4
6

20

1

78

1314

2

5

3

11

9

17

15

12

19

41

42

43

44

45

46

47

48

49

50

51

52

65

10%

X5R-CERM

4.7UF

25V

0603

C3215

1

2

26

26

X5R 0201

0.22UF

6.3V20%

GND_VOID=TRUE

C3279

1 2

0201

20% 6.3V
X5R

0.22UF

GND_VOID=TRUE

C3278

1 2

26

26

GND_VOID=TRUE

6.3V

CERM-X5R

10%

0201

0.1UF

C3231

1 2

0201

10% 6.3V
CERM-X5R

0.1UF

GND_VOID=TRUE

C3230

1 2

26

26

GND_VOID=TRUE

20%
X5R

6.3V

0.22UF

0201

C3233

1 2

0.22UF

20%

X5R

6.3V

0201

GND_VOID=TRUE

C3232

1 2

26

26

CERM-X5R-1 201

4V20%

0.47UF

GND_VOID=TRUE

C3274

1 2

GND_VOID=TRUE

CERM-X5R-1

20% 4V

201

0.47UF

C3275

1 2

26

26

31

31

26

0201

CERM-X5R

6.3V

0.1UF

10%

C3221

1

2

50V

603-1

X7R

0.1UF

10%

C3211

1

2

1/16W

1%

MF-LF

36.5K

402

R3212

1

2

72 30

72

26

201

GND_VOID=TRUE

5%
1/20W
MF

R3272

1

2

470K

201

470K

MF

1/20W

5%

GND_VOID=TRUE

R3273

2

1

GND_VOID=TRUE

0.22UF

20%
X5R

6.3V
0201

C3273

1 2

GND_VOID=TRUE

0201

6.3V

X5R

20%

0.22UF

C3272

1 2

26

26

X5R

6.3V20%
0201

0.22UF

GND_VOID=TRUE

C3270

1 2

X5R

6.3V20%
0201

GND_VOID=TRUE

C3271

1 2

0.22UF

5%

1/20W

MF

470K

201

GND_VOID=TRUE

R3271

1

2

GND_VOID=TRUE

5%
1/20W

470K

MF
201

R3270

1

2

C3210

603-1X7R

50V

0.1UF

10%

1

2

31

CRITICAL

0603

FERR-120-OHM-3A

L3200

1 2

201

MF

1M

5%
1/20W

R3251

1

2

201

1/20W

MF

1M

5%

R3252

1

2

6.3V

100UF

POLY-TANT

20%

CASE-B2-SM

CRITICAL

C3287

1

2

6.3V

22UF

20%

X5R-CERM-1

603

CRITICAL

C3280

1

2

402

0.1UF

10V

20%

CERM

C3281

1

2

201

1/20W

MF

100K

5%

R3241

1

2

NO_XNET_CONNECTION=1

GND_VOID=TRUE

201

1/20W

5%
MF

1K

R3295

1

2

GND_VOID=TRUE

NO_XNET_CONNECTION=1

1K

5%

1/20W

MF

201

R3294

1

2

10%

0.01UF

50V
X7R-CERM
0402

C3201

1

2

12

5%

1/20W MF

201

R3201

1 2

10%

0201

X5R-CERM

0.01UF

25V

C3202

1

2

26

26

0402

C3200

10%
50V

0.01UF

X7R-CERM

1

2

89

29

29

29

29

29

29

29

29

29

29

29

29

89

89 72 31 30 27 26 19

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DDC_DAT
DDC_CLK

CA_DETOUT

AUXIO-

AUXIO+

TB- TB_ENA

AUXIO_EN

DP_PD

VDD

AUX-

HPDOUT

DP-

LSTX

DP+

GND THMPAD

HPD

DPMLO-

DPMLO+

CA_DET

AUX+

LSRX

TB+

OUT

OUT

OUT

IN

IN

IN

PAD

FAULTZ

VHV

ENHVU

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

GND THRM

OUT

ISET_V3P3

V3P3

NC

PORT A

ML_LANE2P
ML_LANE2N

RETURN

SHLD

ML_LANE0P

GND0

GND3

ML_LANE1P

ML_LANE0N

ML_LANE3P

GND1

ML_LANE3N

GND2

AUX_CHP

HPD

AUX_CHN

CONFIG2

DP_PWR

GND4

SHLD

CONFIG1

ML_LANE1N

IN

IN

BI

BI

IN

IN

OUT

OUT

OUT

IN

IN

BI

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

www.laptoprepairsecrets.com

(Both C's)

THUNDERBOLT CONNECTOR B

DP Dir

NOTE: Polarity Swapped for layout!

Low: 0 - 0.8V

greater than or equal

TBT: TX_0

BAUER2 ISET no can limit current to 3.1A if Rset is shorted to GND FOR SINGLE-FAULT PROTECTIO

NOTE: Polarity Swapped for layout!

470k R's for ESD protection
on AC-coupled signals.

TBT: Terminated

18.9V Max

353S3931

IV3P3 1100mA 1030mA 1200mA

Nominal Min Max

V3P3 must be S4 to support

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

(Both C's)

TBT Dir

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

to 100K (DPv1.1a).

(0-18.9V)

DP Source must pull

down HPD input with

High: 2.0 - 5.0V

514-0831

DP Dir

TBT : RX_0

TBT Dir

TBT : RX_1

Sink HPD range:

Nominal Min Max
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT: LSX_B_R2P/P2R (P/N)

TBT: RX_1

(Both C's)

(Both C's)

TBT: UNUSED

wake from Thunderbolt devices.

3.3V/HV Power MUX

353S3812

30 OF 93

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

MIN_LINE_WIDTH=0.3800
MIN_NECK_WIDTH=0.2000
VOLTAGE=18.9V

MIN_LINE_WIDTH=0.3800
MIN_NECK_WIDTH=0.2000
VOLTAGE=18.9V

MIN_LINE_WIDTH=0.3800
MIN_NECK_WIDTH=0.2000

VOLTAGE=18.9V

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

MIN_LINE_WIDTH=0.3800
MIN_NECK_WIDTH=0.2000

VOLTAGE=15V

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

MIN_LINE_WIDTH=0.3800

MIN_NECK_WIDTH=0.2000

VOLTAGE=15V

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

33 OF 121

0.24.0

051-00673

TBT_B_D2R_P<0>

=TBT_S0_EN

TBT_B_HV_EN

=TBTBPWRSW_EN

=PP3V3_S4_TBTBPWRSW

=PPHV_SW_TBTBPWRSW

TBT_B_LSTX

DP_TBTPB_HPD

=PP3V3_S4_TBT

TBT_B_DP_PWRDN

TBTDP_AUXIO_EN

TBT_B_CONFIG1_BUF

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_N<0>

DP_TBTPB_AUXCH_C_P

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<3>

TBT_B_LSRX

TBT_B_CIO_SEL

TBT_B_CONFIG2_RC_R

TBT_B_HPD_R

TBTBPWRSW_ISET_V3P3

TBTBPWRSW_ISET_S3

TBTBPWRSW_ISET_S0

TBTBCONN_7_C

TBTBCONN_20_RC

TBTBCONN_1_C

TBT_B_HPD

TBT_B_D2R_C_P<1>

TBT_B_D2R_C_N<1>

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R1_AUXDDC_N

TBT_B_CONFIG1_RC

TBT_B_CONFIG1_RC

PP3V3RHV_S4_TBTBPWR

DP_TBTPB_ML_P<1>

DP_B_LSX_ML_P<1>

DP_B_LSX_ML_N<1>

DP_B_LSX_ML_N<1>

TBT_B_D2R_N<0>

DP_B_LSX_ML_P<1>

DP_TBTPB_ML_C_N<3>

TBT_B_D2R_C_N<0>

DP_TBTPB_ML_N<1>

TBT_B_R2D_N<0>

DP_TBTPB_ML_N<3>

TBT_B_HPD

TBT_B_D2R_C_P<0>

DP_TBTPB_ML_P<3>

TBT_B_R2D_N<1>

TBT_B_R2D_P<1>

TBT_B_R2D_P<0>

PP3V3RHV_S4_TBTBPWR_F

TBT_B_CONFIG2_RC

TBT_B_D2R_P<1>

DP_TBTP_B_DDC_CLK

DP_TBTP_B_DDC_DATA

DP_TBTPB_AUXCH_P

DP_TBTPB_AUXCH_N

DP_TBTPB_AUXCH_C_N

TBT_B_D2R_N<1>

SYNC_DATE=09/10/2014SYNC_MASTER=BRANCH_JERRYCHOW

TBT/DP: Connector B

MF

1/20W

1%

35.7K

R3311

1

2

201201

1%

35.7K

1/20W

MF

R3310

1

2

GND_VOID=TRUE

GND_VOID=TRUE

SIGNAL_MODEL=CBTL05024_HVQFN24_COMBO_CBTL05024_TBT

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

CBTL05024

HVQFN24-COMBO

U3320

1
2

24

23
22

1816

5

4

10

11

6

20

19

9

21

1712

13

14

157

8

25

3

31

5%

1M

MF

1/20W

201

R3352

1

2

201

1/20W
MF

1M

5%

R3351

1

2

NO_XNET_CONNECTION=1

GND_VOID=TRUE

1

201

1/20W

MF

5%

1K

R3395

2

26

GND_VOID=TRUE

NO_XNET_CONNECTION=1

201

MF

1/20W

5%

1K

R3394

1

2

GND_VOID=TRUE

201

MF

1/20W

5%

470K

R3379

1

2

GND_VOID=TRUE

X5R 0201

20% 6.3V

0.22UF

C3379

1 2

26

26

26

26

0201

GND_VOID=TRUE

0.22UF

X5R

6.3V20%

C3378

1 2

C3375

201CERM-X5R-1

20% 4V

0.47UF

GND_VOID=TRUE

1 2

CERM-X5R-1

0.47UF

C3376

GND_VOID=TRUE

201

4V

20%

1 2

GND_VOID=TRUE

0.47UF

20%
CERM-X5R-14V201

C3374

1 2

72 29

26

72

10%

X5R-CERM

4.7UF

25V

0603

C3315

1

2

603-1X7R

50V

0.1UF

10%

C3310

1

2

CD3211A1RGP

QFN

CRITICAL

U3310

5

16 4

1

2

3

13

15

11 10

9

8

12
14

17

21

19
20

18

6
7

50V

603-1

X7R

0.1UF

10%

C3311

1

2

GND_VOID=TRUE

CERM-X5R-1

0.47UF

20%

4V

201

C3377

1 2

10%
50V

0.01UF

X7R-CERM

0402

C3300

1

2

6.3V

100UF

POLY-TANT

20%

CASE-B2-SM

CRITICAL

C3387

1

2

6.3V

22UF

20%

X5R-CERM-1

603

CRITICAL

C3380

1

2

0.1UF

10V

20%

CERM
402

C3381

1

2

5%

100K

MF

1/20W

201

R3341

1

2

10%

0201

X5R-CERM

0.01UF

25V

C3302

1

2

GND_VOID=TRUE

201

470K

5%
1/20W
MF

R3378

1

2

10%

0.01UF

50V
X7R-CERM
0402

C3301

1

2

12

5%

1/20W MF

201

R3301

1 2

F-ANG-TH

DUAL-MDP-D8

J3200

CON_F40ANG_25MT_MDP_DUAL_TH_F_ANG_TH_DUAL_MDP_D8

55

58

CRITICAL

38

36

24
26

40

21

2728

3334

22

25

23

31

29

37

35

32

30

39

53

54

56

57

59

60

61

62

63

64

65

0.01UF

0201

X5R-CERM

25V

10%

C3306

1

2

R3312

MF-LF
402

36.5K

1%
1/16W

1

2

26

26

26

26

0201

GND_VOID=TRUE

20%
X5R

6.3V

0.22UF

C3333

1 2

0.1UF

CERM-X5R

6.3V

10%

0201

C3320

1

2

C3332

0.22UF

20%

X5R

6.3V

0201

GND_VOID=TRUE

1 2

6.3V

0201

10%

GND_VOID=TRUE

CERM-X5R

0.1UF

C3331

1 2

CERM-X5R

GND_VOID=TRUE

0.1UF

6.3V10%

0201

C3330

1 2

0.01UF

10%
25V

X5R-CERM

0201

C3305

1

2

201

470K

MF

1/20W

5%

GND_VOID=TRUE

R3373

1

2

GND_VOID=TRUE

5%

470K

1/20W
MF
201

R3372

1

2

GND_VOID=TRUE

0201

6.3V

X5R

20%

0.22UF

C3372

1 2

GND_VOID=TRUE

0.22UF

20%
X5R

6.3V
0201

C3373

1 2

0.1UF

10%

6.3V
CERM-X5R

0201

C3321

1

2

26

26

5%

1/20W

MF

470K

201

GND_VOID=TRUE

R3371

1

2

GND_VOID=TRUE

5%
1/20W

470K

MF
201

R3370

1

2

X5R

6.3V20%
0201

0.22UF

GND_VOID=TRUE

C3371

1 2

X5R

6.3V20%
0201

0.22UF

GND_VOID=TRUE

C3370

1 2

26

26

26

29 26

26

31

31

26

26

26

CRITICAL

0603

FERR-120-OHM-3A

L3300

1 2

DEFAULT_RESISTOR_0.001OHM_2_1

0

5%
1/20W
MF
201

R3392

1

2

DEFAULT_RESISTOR_0.001OHM_2_1

0

5%

1/20W

MF

201

R3391

1 2

0201

X7R

330PF

10%
16V

C3395

1

2

0201

X7R

330PF

16V

10%

C3394

1

2

26

26

89

89

89 72 31 29 27 26 19

30

30

30

30

30

30

30

30

30

30

30

30

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DDC_DAT
DDC_CLK

CA_DETOUT

AUXIO-

AUXIO+

TB- TB_ENA

AUXIO_EN

DP_PD

VDD

AUX-

HPDOUT

DP-

LSTX

DP+

GND THMPAD

HPD

DPMLO-

DPMLO+

CA_DET

AUX+

LSRX

TB+

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

PAD

FAULTZ

VHV

ENHVU

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

GND THRM

OUT

ISET_V3P3

V3P3

NC

PORT B

ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

GND0
ML_LANE0P

GND4

SHLD

SHLD

ML_LANE3P
ML_LANE3N

HPD

GND2

DP_PWR

CONFIG2

CONFIG1

AUX_CHP
AUX_CHN

ML_LANE1P

ML_LANE0N

GND1

IN

IN

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

IN

BI

IN

IN

IN

OUT

IN

www.laptoprepairsecrets.com

Dual-Port Host DDC Crossbar

25 mA EDP

1200 mA EDP

(TO 5024 TB MUX)

1

INB

INA

0

INB

INA

OUTA0 =

OUTB0 =

SAI/SBI =

NOTE: CABLE ADAPTERS ARE REQUIRED TO HAVE

2.2K INTERNAL PULL-UPS.

Additional DeCaps added for CSA-29 ( csa-29 is syncing from J44 )

700 mA EDP

31 OF 93

MISS_N_DIFFPAIR

MISS_P_DIFFPAIR

MISS_N_DIFFPAIR

MISS_P_DIFFPAIR

34 OF 121

0.24.0

051-00673

TBT_A_CONFIG2_BUF

=PP3V3_S4_TBT

TBT_B_CONFIG2_BUF

PP3V3_TBTRDV

PP1V05_TBTRDV

TBT_BATLOW_L

MAKE_BASE=TRUE

PP1V05_TBTCIO

=TBT_BATLOW_L

=PP3V3_S4_TBT

DP_TBTSNK1_EG_DDC2CLK

DP_TBTP_A_DDC_DATA

DP_TBTP_A_DDC_CLK

DP_TBTP_B_DDC_DATA

=PP3V3_S0_DP

DP_TBTSNK0_EG_DDC1DATA

DP_TBTP_B_DDC_CLK

DP_TBTSNK0_EG_DDC1CLK

DP_TBTSNK1_EG_DDC2DATA

TBT_A_CONFIG2_RC

TBT_B_CONFIG2_RC

=PP3V3_S0_DP

TBT_DDC_XBAR_EN

TBT_DDC_XBAR_EN_L

SYNC_DATE=11/05/2014SYNC_MASTER=BRANCH_JERRYCHOW

TBT/DP: DDC Crossbar

26

100K

5%

1/20W

MF

201

R3450

1

2

SOT-553

NL17SZ17

U3420

2

31

5

4

NL17SZ17

SOT-553

U3410

2

31

5

4

CERM

10V

402

20%

0.1UF

C3420

1

2

20%

402

10V
CERM

0.1UF

C3410

1

2

79

79

79

79

TS3DS10224

CRITICAL

QFN

U3400

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

14

15

1211

21

13

10%

6.3V

0.1UF

0201

CERM-X5R

C3400

1

2

30

30

29

29

0201-1

1.0UF

20%

6.3V
X5R

C2982

1

2

20%

1.0UF

0201-1

6.3V
X5R

C3407

1

2

20%

1.0UF

0201-1

6.3V
X5R

C3433

1

2

0201-1

20%

1.0UF

6.3V
X5R

C3434

1

2

0201-1

1.0UF

20%

6.3V
X5R

C3435

1

2

DMN32D2LFB4

DFN1006H4-3

Q3450

3

1

2

26

89 72 31 30 29 27 26 19

26

27

27

27

26

89 72 31 30 29 27 26 19

89 40 31

29

30

89 40 31

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

NC

NC

NC

NC

BI

BI

BI

BI

PAD

ENB

THRM

GND

INB-

SAI

INA+

INA-

ENA

SBO

OUTB0+
OUTB0-

OUTB1-

OUTB1+

SAO

OUTA0-

OUTA0+

OUTA1-

OUTA1+

VCC

INB+

SBI

BI

OUT

BI

OUT

D

SG

SYM_VER_2

www.laptoprepairsecrets.com

2 A (EDP)

Supervisor & CLKREQ# Isolation

N-TYPE

AP & BT Load Switch

TPS22924B

18.4 MOHM @3.3V

SWITCH

CHANNEL

LOADING

RDS(ON)

BLUETOOTH

514S0335

AIRPORT

Delay = 130 ms +/- 20%

Wake from BT in G3H circuit

32 OF 93

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.5000

MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

35 OF 121

0.24.0

051-00673

SMC_BT_PWR_EN

PCIE_WAKE_L

PP3V3_S4_AP_FLT

AP_WAKE_L

SMC_PME_S4_WAKE_L

USB_BT_WAKEN

AP_CLKREQ_Q_L

AP_CLKREQ_Q_L

AP_EVENT_L

AP_RESET_CONN_L

AP_RESET_CONN_L

AP_WAKE_L

P3V3AP_VMON

PCIE_AP_R2D_N

PP3V3_G3H_BT_FET

PP3V3_G3H_BT_FLT

PP3V3_S4_AP_FET

PP3V3_S4_AP_FLT

USB_BT_MUX_N

USB_BT_MUX_N
USB_BT_MUX_P

USB_BT_MUX_P

=PP3V3_G3H_BT

PCIE_AP_R2D_C_P

PCIE_CLK100M_AP_P

USB_BT_P

USB_BT_N

PCIE_AP_D2R_P

PCIE_AP_R2D_C_N

PCIE_CLK100M_AP_N

PCIE_AP_D2R_N

=PP3V3_G3H_BT

PM_SLP_S5_L

AP_PWR_EN

=PP3V3_S4_AP

AP_CLKREQ_L

AP_PWR_EN

AP_RESET_L

AP_RESET_CONN_R_L

=PP3V3_S4_APPP3V3_S4_AP_FLT

PCIE_AP_R2D_P

SYNC_MASTER=J16_IG SYNC_DATE=04/29/2013

WIRELESS: Airport/Bluetooth

45

1/20W

5%

201

MF

33

R3533

1 2

10V

10%

0.1UF

X5R-CERM
0201

C3500

1

2

CRITICAL

CSP

TPS22924

U3510

C1

C2

A2
B2

A1
B1

SLG4AP041V

TDFN

CRITICAL

U3530

6

5

7

3

8

4

2

9

1

CRITICAL

SOD

Q3501

3

1

2

SOD

CRITICAL

Q3570

3

1

2

CRITICAL

FERR-220-OHM-2.5A

0603

L3501

1 2

FERR-220-OHM-2.5A

CRITICAL

0603

L3502

1 2

TPS22924B

CSP

CRITICAL

U3540

C1

C2

A2
B2

A1
B1

13

13

USB3740

DFN

SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO

CRITICAL

U3501

9

1

7

10

2

6

8

3

4

5

72 44 12

1/20W

MF

15K

1%

201

R3501

1

2

45 44

MF-LF

10K

5%
1/16W

402

R3570

1

2

20%

10UF

603

6.3V
X5R

C3504

1

2

0402

X7R-CERM

16V

0.1UF

10%

C3503

1

2

10%

0.1UF

16V
X7R-CERM
0402

C3502

1

2

45 44

13

13

6.3VCERM-X5R

0201

0.1UF

C3506

1

10%

2

6.3VCERM-X5R0201

C3505

1

0.1UF

10%

2

11

11

CRITICAL

SSD-K99

F-RT-SM1

J3500

19

20

21

1

2

3

4

6

7

8

9

10

11

12

13

14

15

16

17

18

5

13

13

X7R-CERM

16V

0402

0.1UF

10%

C3507

1

2

10UF

20%

603

6.3V
X5R

C3508

1

2

45 32

MF-LF

1/16W

1%

402

100K

R3530

1

2

1/16W
MF-LF
402

1%

100K

R3532

1

2

402

232K

1%
1/16W
MF-LF

R3531

1

2

0.1uF

10V
CERM
402

20%

C3530

1

2

11

45 32

19

36 19 12

32

32

32

32

32

32

32

45

32

32

32

32

32

89 32

89 32

89 45 32

89 45 32

32

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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SHEET

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C

A

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2 1

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

VIN

ON

VOUT

GND

NC

VREF

DLY

(OD)

PAD

-

+

RESET*

SENSE

VDD

IN

THRM

GND

MR*

EN

OUT

D

S

G

D

S

G

GND

VOUT

ON

VIN

BI

BI

DM

OE*

VDD

GND

DP

S

DP_1

DM_1

DM_2

DP_2

IN

OUT

BI

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

IN

www.laptoprepairsecrets.com

518S0893

H=2.7V,L=3.3V (SSD PULLS PIN LOW FOR 3.3V)

SATA Activity LED

376S0981

PM_EPO_L N-FET INVERTER ON CSA 76

PCIE TX2

Current SSD Conn Pinout

-------------------------

PCIE Pinout on UBX:

RXD0_N=22, TXD0_N=34
RXD0_P=21, TXD0_P=35

RXD1_N=19, TXD1_N=37

POR:514S0457 (tall)

RXD1_P=18, TXD1_P=38

RXD3_N=12, TXD3_N=44

RXD2_N=15, TXD2_N=41
RXD2_P=14, TXD2_P=42

RXD3_P=11, TXD3_P=45

RXD0_P=22, TXD0_P=34
RXD0_N=21, TXD0_N=35

RXD1_P=19, TXD1_P=37
RXD1_N=18, TXD1_N=38

RXD2_P=15, TXD2_P=41
RXD2_N=14, TXD2_N=42

PCIE Pinout for S3X

--------------------

RXD3_N=11, TXD3_N=45

RXD3_P=12, TXD3_P=44

TO SSD VR

(POLARITY REVERSED)

PD_L (S3X ONLY)

(POLARITY REVERSED)

PCIE TX1

PCIE TX0

HDD SIGNAL CONNECTOR

PCIE TX3

GS3 SSD

152S1060

PPVSSD S4 FET

33 OF 93

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
VOLTAGE=3.3V

37 OF 121

0.24.0

051-00673

=PP3V3_S5_SSD_PWRCTL

PM_PGOOD_REG_P5V_S4_R

=PP12V_S5_FET_PWRCTL

PM_EPO

PM_EN_FET_P3V3_S4_SSD

PM_PGOOD_REG_P5V_S4

PM_EN_FET_P3V3_S4_SSD

PP3V3_S4_FET_SSD

SSD_PWR_EN

SSD_CLKREQ_L

PCIE_CLK100M_SSD_P

PCIE_SSD_R2D_C_N<0>

PCIE_CLK100M_SSD_N

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<3>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_N<1>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_N<3>

SSD_BFH_R_L

PCIE_SSD_R2D_C_P<3>

SSD_RESET_L

PCH_SSD_RESET_L

PCIE_SSD_R2D_P<3>

SSD_ISOL_FET_GATE

STORAGE_RESET_L

LPSR_EN_R_L

STORAGE_RESET_L

PCIE_SSD_R2D_N<2>

SATA_HDD_D2R_N
SATA_HDD_D2R_P

=PP3V3_S0_LED_SATA

SATALED_R_L

SATA_HDD_R2D_N

PM_EPO_L

=PP3V3_S5_PWRCTL

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N

SATA_HDD_R2D_P

PCH_SATALED_L

SSD_V_SEL

=PP3V3_S5_SMC

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_P<0>

PCIE_SSD_R2D_C_P<0>

SSD_BFH_L

PP3V3_S4_SSD_FLT

PP3V3_S4_SSD_FLT

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_N<3>

PCIE_SSD_D2R_P<3>

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

P3V3SSD_S4

PM_EN_SSD_L

=PPVSSD_S5_FET_S4_SSD

STORAGE_RESET_R_L

PM_EPO_L

SSD_V_SEL

SMC_OOB2_D2R_L

SMC_OOB2_R2D_L

=PPVSSD_S4_CONN

LPSR_EN_L

=PP3V3_S5_SSD_PWRCTL

SSD_SR_EN_L

LPSR_EN_L

SSD_ISOL_FET_GATE

SSD_ISOL_FET_GATE

PP3V3_S4_SSD_FLT

SYNC_MASTER=J16_IG

SDD/HDD:SATA/SSD Connectors

SYNC_DATE=04/29/2013

GRN-6MCD-0.03A

0805

DEVELOPMENT

DS3799

SILK_PART=SATA ACTIVE

A

K

DEVELOPMENT

R3799

330

5%
1/10W
MF-LF

603

1

2

R3792

100K

5%
1/16W

2

402

MF-LF

1

SN74LVC1G02

U3782

SOT553-5

5

3

1

2

4

0

MF-LF

21

1/16W

5%

402

R3793

IRLHS6242TRPBF

8

CRITICAL

Q3771

2 5

4 7

3

PQFN2X2

61

CRITICAL

0.22UH+/-20%-0.006OHM-9A

PLACE_NEAR=J3700.1:10.1MM

L3700

SSD:Y

1

PIMB042T-SM

2

BP08

TP-BP-P19XP55SMP14X45O

1

BP07

TP-BP-P19XP55SMP14X45O

1

TP-BP-P19XP55SMP14X45O

BP06

1

1

TP-BP-P19XP55SMP14X45O

BP05

19

1/20W

5%

NOSTUFF

MF

0

R3790

0201

21

Q3772

2N7002DW-X-G

3

4

5

SOT-363

CRITICAL

66

402

100K

2

5%
1/16W

1

R3795

MF-LF

NOSTUFF

89

CRITICAL

Q3772

6

2

1

SOT-363

2N7002DW-X-G

R3791

1

MF-LF

2

1/16W

10K

5%

402

10%

0402

2

50V

1

C3792

0.01UF

X7R-CERM

0.47UF

NOSTUFF

C3783

402

6.3V

10%

2

CERM-X5R

1

1/16W

5%

0

1 2

MF-LF

R3782

402

72 66

0.1UF

0201

C3782

2

1

6.3V

10%

CERM-X5R

72 71 66 60 33

U3781

CRITICAL

TC7SZ08FEAPE

4

5

3

1

2

SOT665

C3781

0.1UF

CERM-X5R

6.3V

2

1

10%

0201

SSD:Y

0201X5R

1 2

20% 6.3V

0.22UF

GND_VOID=TRUE

C3712

PLACE_NEAR=J3700.22:5MM

C3710

GND_VOID=TRUE

X5R

PLACE_NEAR=J3700.19:5MM

SSD:Y

0.22UF

02016.3V20%

21

0.22UF

PLACE_NEAR=J3700.21:5MM

0201X5R

1 2

20% 6.3V

SSD:Y

GND_VOID=TRUE

C3713

C3714

PLACE_NEAR=J3700.15:5MM

X5R

GND_VOID=TRUE

SSD:Y

0.22UF

02016.3V20%

21

0.22UF

C3715

PLACE_NEAR=J3700.14:5MM

GND_VOID=TRUE

SSD:Y

0201X5R6.3V20%

21

GND_VOID=TRUE

SSD:Y

0.22UF

0201X5R6.3V20%

21

C3711

PLACE_NEAR=J3700.19:5MM

C3717

20%

GND_VOID=TRUE

6.3V

PLACE_NEAR=J3700.11:5MM

0.22UF

SSD:Y

2

X5R10201

SSD:Y

1 2

20% X5R 0201

0.22UF

PLACE_NEAR=J3700.12:5MM

6.3V

C3716

GND_VOID=TRUE

5%

21

0

0201

MF

1/20W

R3773

NOSTUFF

1 2

R3771

0

NOSTUFF

0201

MF

1/20W

5%

402

2

1

1/16W

5%

10K

NOSTUFF

MF-LF

R3776

13

R3772

402

2

10K

1/16W
MF-LF

5%

1

DMN5L06VK-7

SOT563

1

2

6

Q3770

3

5

DMN5L06VK-7

SOT563

Q3770

4

R3770

MF-LF

1

2

402

1/16W

10K

5%

14 13

13

13

13

13

13

13

13

13

14 13

SSD:Y

MF-LF

21

1/16W

5%

0

R3775

402

1/16W

R3715

MF-LF

100K

SSD:Y

402

5%

1

2

72 71 66 60 33

5%

R3719

SSD:Y

0

MF-LF

1/16W

1 2

402

1/16W

R3720

NOSTUFF

5%

0

1 2

402

MF-LF

M-ST-SM

PSA127-0747-A01-1H

CRITICAL

J3720

1

SILK_PART=HDD

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

2

3

4

5

6

7

9

8

TP-BP-P19XP55SMP14X45O

BP04

1

BP03

TP-BP-P19XP55SMP14X45O

1

TP-BP-P19XP55SMP14X45O

BP02

1

1

TP-BP-P19XP55SMP14X45O

BP01

GND_VOID=TRUE

20

9

4

49

GND_VOID=TRUE

GND_VOID=TRUE

40

15

14

GND_VOID=TRUE

12

42

43

GND_VOID=TRUE

SSD-J90

CRITICAL

GND_VOID=TRUE

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53
52
51

50

48
47

46
45
44

41

39
38
37
36
35
34
33

32
31
30
29

28

27

26

25

24

23

22

21

19

18

17

16

13

11

10

8

7

5

3

2

1

SSD:Y

F-RT-SM

GND_VOID=TRUE

GND_VOID=TRUE

SILK_PART=SSD

6

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

J3700

R3713

100K

MF-LF

2

1

1/16W

5%

402

5%

MF-LF

R3712

2

1

1/16W

100K

402

13

13

13

13

13

13

13

13

11

11

13

13

13

13

0.01UF

C3724

402

X7R

GND_VOID=TRUE

25V10%

1 2

GND_VOID=TRUE

2

10%

C3723

25V

0.01UF

X7R

402

1

402

GND_VOID=TRUE

X7R25V

0.01UF

C3722

1 2

10%

402

0.01UF

GND_VOID=TRUE

25V10% X7R

C3721

1 2

45

45

0.1UF

C3700

2

1

20%
10V

402

SSD:Y

CERM

SSD:Y

C3701

20%

0.1UF

402

2

1

CERM

10V

89 66 33

89 71

33

33

11

33

33

33

89

89 73 72 66

17 13

33

89 45

14 13

33

33

89

33

89

33

89 66 33

33

33

33

33

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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SHEET

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D

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

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D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

02

G

S

D

A

A

A

A

IN

NC

NC

NC

S

D

G

IN

OUT

S

D

G

IN

IN

A

B

Y

IN

G

D

S

VER 1

G

D

S

VER 1

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

A

A

A

A

NC

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

OUT

www.laptoprepairsecrets.com

4AMP,

(max 0.7A,ave 0.3A)

REMOVE R3813 AND SHORT R3812 AFTER HDD_PWR_EN WORKS

(max 2.8A,ave 0.6A)

for Test Only

R3813 IS NO STUFF

IDLE IS AT 1.5V

(PULL UP TO 3V3_S5 INSIDE PCH)

12mOhm

376S0910

Drive active: Valid signal protocol

Notes:

Drive disconnected: Pulled high

Trip is 1.0V

Low:

From drive:

0.0V to 0.3V

1.2V to 2.0V

518S0865

HDD POWER

HDD OOB TEMP SENSING

HDD 5V_S0 FET

353S3672

VIH: 2.4V TO 5.5V

HDD 12V_S0 FET

353S3098

High:

Drive asleep: HDD drives HDD_OOB_TEMP low

4nF = 2.3V/ms Ramp Rate

34 OF 93

38 OF 121

0.24.0

051-00673

=PP12V_S0_HDD

=PP5V_S0_HDD_PWR

=PP12V_S0_HDD_PWR

=PP3V3_S0_SENSE

HDD_PWR_EN

PP12V_S0_HDD_FET =PP5V_S0_HDD

PP5V_S0_HDD_FET

=PP3V3_S0_SENSE

SMC_OOB1_RX_FILT

SMC_OOB1_RX_CN

SMC_OOB1_D2R_R

SMC_OOB1_D2R_L

HDD_PWR_EN_R

HDD_PWR_EN_L

HDD_OOB_1V00_REF

HDD_12V_S0_GATE

HDD5V_RAMP_CAP

FET_HDD_SLGSW

HDD: SSD Temp Sense

SYNC_MASTER=J78_KENNY SYNC_DATE=03/10/2014

1/10W

5%

603

100

MF-LF

R3810

1 2

CRITICAL

TDFN

SLG5AP026

U3810

5

6

7

4

3

2

8

9

1

1UF

X5R

10%

603

16V

C3810

1

2

89

44

5%

402

1K

1/16W
MF-LF

R3805

1

2

5%

402

MF-LF

1/16W

150K

R3804

1

2

5%

402

MF-LF

1/16W

180K

R3802

1

2

5%

402

3.3K

1/16W
MF-LF

R3803

1 2

0.022UF

10%
50V

0402

X7R

C3830

1

2

CRITICAL

78047-0773

M-ST-SM-1

SILK_PART=PWR

J3830

1

2

3

4

5

6

7

0402

FERR-220-OHM

L3830

1 2

1206-1

10%

10UF

25V
X7R-CERM

C3831

1

2

20%

X5R
603

10V

10UF

C3832

1

2

16V

0.1UF

10%

X7R-CERM
0402

C3801

1

2

0.1UF

10%
16V
X7R-CERM
0402

C3800

1

2

25V

0.0047UF

0402

CERM

10%

C3821

1

2

CRITICAL

TDFN

SLG5AP304V

U3820

7 3

8

2 5

1

CRITICAL

SSM6N15AFEAP

SOT563

Q3820

3

5

4

5%

402

10K

1/16WMF-LF

R3821

1

2

SOT563

SSM6N15AFEAP

CRITICAL

Q3820

6

2

1

4021%

MF-LF

1/16W

100K

NOSTUFF

R3813

1

2

14 13

402

100K

1%
1/16W
MF-LF

R3801

1

2

402

232K

1%
1/16W
MF-LF

R3800

1

2

CRITICAL

SC70-5

LMV331

U3800

2

3

1

4

5

5%

402

MF-LF

1/16W

0

R3812

1 2

89

CRITICAL

IRFH3702TRPBF

PQFN

Q3810

5

4

1

16V

20%

0.1UF

603

CERM

C3820

1

2

89

89

89

89 50 49 48 34

89

89 50 49 48 34

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PAD

VCC

G

D2

D1

NC

ON

PG

GND

THRM

NC

OUT

OUT

CAP

ON S

D

VDD

GND

G S

D

G S

D

IN

GND

VCC+

NC

OUT

S

D

G

www.laptoprepairsecrets.com

NOTE: 30 PPM crystal required

If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.

If ENET switching regulator is

BCM requests SD CR[0:7], CMD, CLK termination.

(IPU-ENET)

No MS (Memory Stick) Insert feature needed.

ENET supports both active-levels for WP.

(See note)

SD_DETECT can only be used active low due to errata.

(IPD-ENETM)

Resistor

NOTE: "IPx" == Programmable pull-up/down

(IPU-ENET)

used, this pin should have

ENET_SR_DISABLE

ENET_CR Signals

(IPU-ENET)

Internal 1.2V Switching Regulator pins.

Limiting

Current

VDD for Card Reader I/O

(IPD)

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

(IPD)

(OD)

the card reader on-chip I/O.

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

(IPU-ENET)

other 3 SPI pins configures ENET for the

(IPU-ENET)

WAKE#

(See note)

396mA (1000base-T, Caesar II)

Atmel AT45DB011D (1Mbit) ROM. If a different

(OD)

o

ROM is used then the straps must change.

(NO IPU OR IPD-ENET)

Must isolate from PCIe WAKE# if PHY
is powered-down in S3/S5. Standard
N-channel FET isolation suggested.

281mA (1000base-T max power, Caesar IV)

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

NOTE: ENETM requires SI pull-down instead of SO.

(OD)

Special Star routing needed on these pins. Decoupling on Pg 37.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

(IPx-ENET)

(IPD-ENET)

ENET 1.2V SR IS ENABLED IF FLOATING.

a 1K pull-down to GND

Connect only to U3900 pin 20.

NOTE: Pull-down on SO plus internal pull-ups on

(IPD)

(OD)

Control signal to light LED or control SD bus power.

(IPU)

Ethernet 25MHz Crystal

(Required ROM size 1 Mbit)

Avoids need for EFI to program at startup.

info as well as code for Bonjour proxy.

ROM contains MAC address, PCIe config

PHY Non-Volatile Memory

051-00673

0.24.0

39 OF 121

35 OF 93

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.4000

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.4000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.1500

=PP3V3_ENET_PHY

ENET_SR_DISABLE

ENET_SD_CMD

SDCONN_DATA<3>

SDCONN_DATA<1>

SDCONN_DATA<0>

ENET_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_ENET_R2D_P

=PP3V3_ENET_PHY

ENET_XTAL_OUT_R

ENET_XTAL_OUT

PP3V3_ENET_PHY_BIASVDDH

ENET_LOW_PWR

=PP3V3R1V8_CR_VDDIO

PCIE_ENET_R2D_C_P

=PP3V3_S0_ENET

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N

=ENET_SR_VFB

PCIE_CLK100M_ENET_P

PCIE_ENET_D2R_P

ENET_SR_LX

=PP1V2_ENET_PHY

SDCONN_CLK

PP3V3_ENET_PHY_AVDDH

PP1V2_ENET_PHY_PCIEPLL

PP1V2_ENET_PHY_GPHYPLL

PP1V2_ENET_PHY_AVDDL

PCIE_ENET_R2D_N

PCIE_ENET_D2R_C_P

PCIE_ENET_D2R_C_N

ENETCONN_MDI_P<3>

ENETCONN_MDI_P<2>

ENETCONN_MDI_P<1>

ENETCONN_MDI_P<0>

ENETCONN_MDI_N<3>

ENETCONN_MDI_N<1>

ENETCONN_MDI_N<0>

ENET_XTALVDDH

ENET_VMAIN_PRSNT

ENET_SD_CLK

ENET_SCLK ENET_MOSI

ENET_MISO

ENET_MISO

ENET_CS_L

ENET_CR_DATA<3>

SDCONN_CMD

ENET_CR_PWREN

SDCONN_WP

ENET_MOSI
ENET_CS_L

=ENET_WAKE_L

SMB_ENET_SCL

ENET_RESET_L

ENET_SD_DETECT_L

ENET_MEDIA_SENSE

SDCONN_DATA<2>

ENETCONN_MDI_N<2>

ENET_CR_DATA<0>
ENET_CR_DATA<1>
ENET_CR_DATA<2>

SMB_ENET_SDA

ENET_SCLK

ENET_XTAL_OUT

ENET_TRAFFICLED_L

ENET_XTAL_IN

ENET_RDAC

ENET_XTAL_IN

PP3V3R1V8_ENET_LR_OUT

ETHERNET: PHY (CAESAR IV)

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

2

1

R3997

1/16W

5%

402

4.7K

MF-LF

2

1

C3915

4.7UF

6.3V

X5R-CERM1

402

20%

2

1

C3930

4.7UF

6.3V
X5R-CERM1

20%

402

2

1

C3900

10%

0.1UF

X5R-CERM

0201

16V

C3946

1

20PF

CERM

50V

0402

5%

2

CERM

1

20PF

C3945

2

5%

50V

0402

PLACE_NEAR=U3900.18:10MM

3.2X2.5MM-SM

3

25.000MHZ-20PPM-12PF-85C

Y3900

CRITICAL

2

1

4

21

0

5%

MF-LF

1/16W

R3945

402

2

1

R3946

402

MF-LF

5%

NOSTUFF

1M

1/16W

17

19

18

3

58

62

56

7

61

35

20

50
49

46
47

44
43

40
41

67

69

13

151416

68

2

65

10

6

64

1

66

38

11

28

27

33
34

31
30

32

29

59

4

9

8

5

36

63

57

60

55

54

53

52

22

23

24

25

26

21

12

37

51

45

39

48

42

U3900

BCM57766C0KMLG

OMIT_TABLE

QFN-8X8

21

L3930

0402

CRITICAL

FERR-600-OHM-300MA-0.85OHM

21

L3920

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

21

L3910

FERR-600-OHM-300MA-0.85OHM

0402

CRITICAL

21

L3905

0402

FERR-600-OHM-300MA-0.85OHM

CRITICAL

21

L3900

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

21

R3974

201

33

MF5% 1/20W

PLACEMENT_NOTE=PLACE R3974 NEAR U3900

21

R3973

5% 201

33

MF1/20W

PLACEMENT_NOTE=PLACE R3973 NEAR U3900

21

R3972

2011/20W

33

5% MF

PLACEMENT_NOTE=PLACE R3972 NEAR U3900

21

R3971

5% 1/20W

33

MF 201

PLACEMENT_NOTE=PLACE R3971 NEAR U3900

21

R3979

33

201MF5% 1/20W

PLACEMENT_NOTE=PLACE R3979 NEAR U3900

2

1

C3990

10%

0.1UF

X5R-CERM
0201

16V

21

C3956

10%

0.1UF

X5R-CERM

16V

0201

21

C3955

10%

0.1UF

X5R-CERM

0201

16V

21

C3951

0.1UF

10%

0201

16V

X5R-CERM

21

C3950

10%

0201

16V

0.1UF

X5R-CERM

2

1

C3936

X5R-CERM

10%

0.1UF

0201

16V

2

1

C3931

0.1UF

10%

0201

16V

X5R-CERM

2

1

C3926

10%

0.1UF

16V

X5R-CERM

0201

2

1

C3921

10%

0.1UF

16V

0201

X5R-CERM

2

1

C3916

10%

0.1UF

16V
X5R-CERM
0201

2

1

C3911

X5R-CERM
0201

10%

0.1UF

16V

2

1

C3910

0201

X5R-CERM

10%
16V

0.1UF

2

1

C3905

10%

0.1UF

X5R-CERM

0201

16V

21

R3961

201

33

1/20W5% MF

PLACEMENT_NOTE=PLACE R3961 NEAR U3900

37

5

6

8

12

3

7

4

U3990

OMIT_TABLE

AT45DB011D

SOIC-8S1

21

R3981

5%

1K

MF-LF

402

1/16W

37

37

37

37

37

36

2

1

R3910

4.7K

MF-LF

402

5%

1/16W

14

37

37

2

1

R3990

NOSTUFF

4.7K

MF-LF
402

5%
1/16W

37

37

2

1

R3940

MF-LF

402

5%

1/16W

4.7K

2

1

R3941

402

4.7K

MF-LF

1/16W

5%

36

36

36

36

36

36

36

36

13

13

13

13

2

1

MF-LF

1/16W

1%

1.24K

402

R3965

37 19

36

11

11

11

2

1

R3942

1/16W

1K

402

MF-LF

5%

2

1

C3920

X5R-CERM1
402

4.7UF

6.3V

20%

21

L3925

CRITICAL

FERR-600-OHM-0.5A

SM

2

1

C3925

402

X5R-CERM1

4.7UF

6.3V

20%

2

1

C3935

20%
X5R

6.3V
603

10UF

89 36 35

89 36 35

35

36

89

36

36

36

35 35

35

35

35

35

35

35

35

35

35

36

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

NC

NC

NC

NC

NC

NC

TRD2_P

GPHY_PLLVDDL

PCIE_PLLVDDL

AVDDL

RDAC

XTALO

XTALI

THRM_PAD

CLKREQ*

PCIE_REFCLK_P

PCIE_RXD_N

VMAIN_PRSNT

TRD2_N

TRD1_N

TRD0_N

TRD1_P

TRD0_P

TRAFFICLED*/SERIAL_DI

SPD100LED*/SERIAL_DO

SR_VDD

SR_VDDP

SR_VFB

SR_LX

VDDCAVDDH

PCIE_REFCLK_N

PCIE_TXD_N

SMB_CLK

PERST*

SMB_DATA

VDDO

XTALVDDH

BIASVDDH

SI/EEDATA

LOW_PWR

CS*/EECLK

SO_LINKLED*

SCLK_SPD1000LED*

SR_DISABLE

CR_DATA1
CR_DATA2
CR_DATA3

PCIE_RXD_P

PCIE_TXD_P

CR_CMD

SD_DETECT

GPIO_2/MEDIA_SENSE

GPIO_1/LR_OUT

GPIO_0/CR_ACT_LED*

TRD3_P

TRD3_N

CR_CLK

CR_WP*

CR_DATA0

CR_DATA6
CR_DATA7

MS_INS*

CR_LED*/CR_BUS_PWR

CR_DATA5

CR_DATA4

WAKE*

NC

IN

VCC

GND

SI

WP*

SO

SCK

CS*

RESET*

BI

BI

BI

BI

OUT

OUT

OUT

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

OUT

OUT

IN

IN

www.laptoprepairsecrets.com

CAESAR IV WAKE# ISOLATION

CAESAR IV 1.2V INT.VR CMPTS

514-0822

Power decoupling

157S0058

Feedback loop

3.3V ENET FET

ENET Enable Generation

"ENET" = "S0" || ("S4" && "WOL_EN")

CAESAR IV ACTIVITY LED

SILKSCREEN:ENET ACT

36 OF 93

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

DIDT=TRUE

VOLTAGE=1.2V

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.3000

VOLTAGE=3.3V

40 OF 121

0.24.0

051-00673

WOL_EN

=PP3V3_ENET_PHY

ENET_TRAFFICLED_L

PM_SLP_S3_L

=PP3V3_S4_FET_ENET PP3V3_ENET_FET

=PP3V3_ENET_PHY

ENETCONN_MDI_P<3>

ENETCONN_MDI_P<2>

ENETCONN_MDI_P<1>

ENETCONN_MDI_P<0>

ENETCONN_MDI_N<3>

ENETCONN_MDI_N<2>

ENETCONN_MDI_N<0>

PP1V2_ENET_INTREG

PP1V2_ENET_INTREG

MAKE_BASE=TRUE

PM_EN_ENET_L P3V3ENET_SS

ENETCONN_TCT

ENETCONN_MDI_T_P<3>

ENETCONN_MDI_T_P<3>

ENETCONN_MDI_T_P<2>

ENETCONN_MDI_T_P<2>
ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_P<0>

ENETCONN_MDI_T_P<0>

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_N<2>

ENETCONN_MDI_T_N<2>

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_N<0>

ENETCONN_MCT3

ENETCONN_MCT2

ENETCONN_MCT1

ENETCONN_MCT0

ENET_ACT

ENET_SR_LX

=ENET_SR_VFB

=PP1V2_ENET_PHY

=ENET_WAKE_L

=PP3V3R1V8_CR_VDDIO

ENET_WAKE_L

MAKE_BASE=TRUE

PCIE_WAKE_L

=PP3V3_ENET_PHY

ENETCONN_MDI_N<1>

ENETCONN_MCT_BS

PP3V3R1V8_ENET_LR_OUT

MAKE_BASE=TRUE

ETHERNET: Support & Connector

SYNC_DATE=12/07/2012SYNC_MASTER=J16_IG

LFE8904CF

CRITICAL

SM

T4010

1

2

3

4

5

6 7

8

9

10

11

12

CRITICAL

LFE8904CF

SM

T4000

1

2

3

4

5

6 7

8

9

10

11

12

6.3V
402

X5R-CERM1

20%

4.7UF

C4030

1

2

10%

0.1UF

X5R-CERM

16V
0201

C4031

1

2

10%

0.1UF

16V
0201

X5R-CERM

C4032

1

2

RCPT-RJ45-D8

F-ANG-TH

CRITICAL

J4000

1

2

3

4

5

6

7

8

9
10
11
12
13
14

SOD

CRITICAL

Q4070

3

1

2

0.1UF

CERM

10V

20%

402

C4001

1

2

0.1UF

CERM

10V

20%

402

C4002

1

2

35

35

0.1UF

10V
CERM

20%

402

C4003

1

2

0.1UF

10V

20%

402

CERM

C4004

1

2

35

35

35

35

35

35

10%

1206

NOSTUFF

2KV

1000PF

CERM

C4000

1

2

75

5%

MF-LF

1/16W

402

R4000

1

2

MF-LF

75

5%
1/16W

402

R4001

1

2

75

1/16W
MF-LF
402

5%

R4002

1

2

36

36

MF-LF
402

1/16W

5%

75

R4003

1

2

36

36

36

36

36

36

10%

0.1UF

0402

X7R-CERM

16V

C4013

1

2

X5R

6.3V

20%

10UF

603

C4012

1

2

4.7UH-0.8A

CRITICAL

PCAA031B-SM

L4010

1 2

DEFAULT_RESISTOR_0.001OHM_K_A

DEVELOPMENT

GRN-6MCD-0.03A

0805

LED4050

A

K

DEVELOPMENT

402

MF-LF

1/16W

5%

330

R4050

1

2

MF-LF

1/16W

402

5%

10K

R4070

1

2

6.3V
X5R-CERM1
402

20%

4.7UF

C4010

1

2

10%

0.1UF

0402

X7R-CERM

16V

C4011

1

2

73 72 45 44 12 6

SOT-363

2N7002DW-X-G

CRITICAL

Q4021

3

5

4

CRITICAL

2N7002DW-X-G

SOT-363

Q4021

6

2

1

14 13

1/16W
MF-LF

402

5%

10K

R4020

1

2

100K

1/16W

5%

MF-LF

402

R4021

1 2

0.033UF

16V

402

X5R

10%

C4020

1

2

SOT-23-HF

NTR4101P

CRITICAL

Q4020

3

1

2

0402

X7R-CERM

50V

0.01UF

10%

C4021

12

36

36

36

36

36

36

36

36

89 36 35

35

89 89

89 36 35

36

36 35

35

35

35

35

32 19 12

89 36 35

35

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

RX

TX

RX

TX

PINS

ENET_MDI

ENET_MDI_TRAN3+
ENET_MDI_TRAN1­ENET_MDI_TRAN2-

ENET_MDI_TRAN0+

ENET_MDI_TRAN0-

SHIELD

ENET_MDI_TRAN3-

ENET_MDI_TRAN1+

ENET_MDI_TRAN2+

D

S

G

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

S

D

G

S

D

G

IN

S D

G

BI

BI

BI

BI

BI

BI

BI

BI

www.laptoprepairsecrets.com

-> TO PCH GPIO

FROM SD CONN ->

When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms
regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

DLY block is 20ms nominal

-> TO ENET CHIP

353S2548

SD CARD CONNECTOR

J16:516-0249 / J17:512-0038

SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.

SD CARD 3.3V OVERCURRENT PROTECTION CHIP

SD switch is normally connected (i.e. gnd)

37 OF 93

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

VOLTAGE=3.3V

41 OF 121

0.24.0

051-00673

SDCONN_OC_L

SDCONN_ILIM

SDCONN_ILIM_R

SDCONN_DETECT_L
SDCONN_WP

SDCONN_DATA<2>

SDCONN_DATA<0>

=PP3V3_S0_SDCARD

SDCONN_DATA<1>

ENET_CR_PWREN

ENET_SD_DETECT_L

SDCONN_STATE_CHANGE

ENET_LOW_PWR

=PP3V3_S4_SDCARD

SDCONN_CLK

ENET_SD_RESET_L

SDCONN_DATA<3>
SDCONN_CMD

ENET_RESET_LSLG_ENET_RESET_R_L

SDCONN_DETECT_L

SDCONN_CLK_R

SD_DETECT_LVL

=PP3V3_S0_SW_SD_PWR

=PP3V3_S0_SW_SD_PWR

PP3V3_S0_SW_SD_PWR

MAKE_BASE=TRUE

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

SD CARD: Connector

14

CRITICAL

0402

47NH-1.3OHM

L4102

1 2

13K

MF-LF

1/16W

1%

402

R4119

1

2

1/16W

402

13K

1%

MF-LF

R4118

1

2

CRITICAL

SD-CARD-D8

F-ANG-TH1

J4100

1

5

2

14

7
8

9
10
11
12
13

16
17
18
19
20
21
22
23
24
25
26
27

4

3

6

15

35

CRITICAL

TPS2553

SON

U4100

4 3

5

2

6

1

7

35

35

35

35

1/16W
MF-LF

10K

5%

402

R4115

1

2

CRITICAL

SLG4AP026V

TDFN

U4111

6

9

7

1

8

5

2

3

4

11

10

NOSTUFF

402

50V

5%

15PF

CERM

C4170

1

2

NOSTUFF

50V
CER-C0G
0402

22PF

5%

C4171

1

2

19

1/16W
MF-LF

402

10K

5%

NOSTUFF

R4110

1

2

35 19

1UF

402-1

10V
X5R

10%

C4110

1

2

35

14 13

33

MF-LF

1/16W

5%

402

R4114

1 2

35

0.1UF

X7R-CERM

0402

16V

10%

C4101

1

2

0603

X5R-CERM1

6.3V

22UF

20%

C4100

1

2

47K

402

1/16W
MF-LF

5%

R4100

1

2

0402

X7R-CERM

16V

0.1UF

10%

C4103

1

2

20%

603

10UF

6.3V
X5R

C4102

1

2

35

35

35

37

89

89

37

37

37

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

NC

NC

NC

NC

SHLD_PIN

WRITE_PROTECT_SWITCH

CD/DAT3

VSS
VDD
CLK

CMD

VSS

DAT4

DAT0
DAT1
DAT2

DAT7

DAT5
DAT6

SHLD_PIN
SHLD_PIN
SHLD_PIN

CRD_DETECT_SWITCH

SHLD_PIN

SHLD_PIN
SHLD_PIN
SHLD_PIN

SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN

IN

PAD

IN

EN

ILIM

FAULT*

GND

OUT

THRML

BI

BI

BI

BI

PAD

(OD)

(OD)

XOR

(IPU)

XOR

LOGIC

RST

DLY

DET_CH_EN*

RST_IN*

DET_IN

DET_LVL

DET_CHNGD*

DET_OUT

RST_OUT*

VDD

THRM

GND

LOW_PWR

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

www.laptoprepairsecrets.com

APN:518S0879

Camera/ALS/DMIC connector

GPIO3, EXT/IN FIRMWARE BOOT SEL

'1' = POSITIVE EDGE

SPI clock during power-on.

of pos/neg edge sampling of

'0' = NEGATIVE EDGE

335S0852

'0'= INT FW

'1'= EXT FW

GENERAL GPIO AFTER POWER ON

UART1_TX is strap for selection

STITCH THERMAL PAD TO INNER GROUND

Use 100 ohms and 150pF for 10MHz filter

337S4151

GPIO3 CAN BE CONFIGED AS

USB CAMERA CONTROLLER

CRYSTAL

SERIAL FLASH

38 OF 93

MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
VOLTAGE=1.2V VOLTAGE=1.2V

MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
VOLTAGE=3.3V

VOLTAGE=5V

MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1500

42 OF 121

0.24.0

051-00673

AUD_DMIC_CLK AUD_DMIC_CLK_CONN

AUD_DMIC_SDA1 AUD_DMIC_SDA1_CONN

CAM_AGND

CAM_AGND

CAM_AGND

CAM_EXT_BOOT

CAM_PLLGND

CAM_PLLGND

CAM_PROC_RESET_L

CAM_RX

CAM_SF_CLK

CAM_SF_CLK

CAM_SF_CLK_R

CAM_SF_CS_L

CAM_SF_CS_L
CAM_SF_DIN

CAM_SF_DINCAM_SF_DIN_R

CAM_SF_DOUT

CAM_SF_DOUT

CAM_SF_DOUT_R

CAM_SF_HOLD_L

CAM_SF_WP_L

CAM_SF_WP_L

CAM_TEST

CAM_TX

CAM_USB_VRES

CAM_XTAL_IN

CAM_XTAL_IN

CAM_XTAL_OUT

CAM_XTAL_OUT CAM_XTAL_OUT_R

I2C_CAMSENSOR_SCL

I2C_CAMSENSOR_SCL

I2C_CAMSENSOR_SDA

I2C_CAMSENSOR_SDA

MIPI_RESISTOR

PP1V2_S0_CAMFILT PP1V2_S0_F_R

PP1V8_S0_CAMERA_F

PP1V8_S0_CAMERA_F

PP3V3_S0_ALS_F

PP3V3_S0_ALS_F

PP3V3_S0_CAMFILT

PP5V_S0_CAMERA_F

PP5V_S0_CAMERA_F

SMB_ALS_F_SCL

SMB_ALS_F_SCL

SMB_ALS_F_SDA

SMB_ALS_F_SDA

SMIA_CLK_N

SMIA_CLK_N

SMIA_CLK_P

SMIA_CLK_P

SMIA_DATA_N

SMIA_DATA_N

SMIA_DATA_P

SMIA_DATA_P

TP_CAM_GPIO1

TP_CS_PWD_L

TP_ISM_CLK

TP_ISM_RST_L

=PP3V3_S0_CAMERA

GND_AUDIO_DMIC

=PP1V8_S0_CAMERA

PP1V2_S0_CAMERA

PP1V2_S0_CAMERA

USB_CAMERA_P

=SMB_ALS_SDA

=PP5V_S0_CAMERA

USB_CAMERA_N

=PP3V3_S0_ALS

=SMB_ALS_SCL

=PP3V3_S0_AUDIO

=PP3V3_S0_CAMERA

=PP1V8_S0_CAMERA

=PP3V3_S0_CAMERA

PP3V3_DMIC_CONN

SYNC_DATE=11/05/2013SYNC_MASTER=J78_NAT

CAMERA: Controller

C0G

25V

5%

18PF

0201

C4227

1 2

18PF

C0G

25V

5%

0201

C4225

1 2

F-RT-SM

20455-A20E-32

J4200

21

22

23

24

25

26

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

CRITICAL

3.2X2.5MM-SM

12.000MHZ-30PPM-10PF-85C

Y4200

2 4

1 3

402

1UF

16V
X5R

10%

C4265

1

2

5%

MF

1/20W

4.7K

201

R4208

1

2

10K

MF

1/20W

1%

201

R4207

1

2

PLACE_NEAR=U4202:5mm

1%

1/20W

33

MF

201

R4209

1 2

PLACE_NEAR=U4200:5mm

MF 1%

33

1/20W201

R4205

12

PLACE_NEAR=U4200:5mm

1%

33

MF

1/20W 201

R4203

1 2

MF

1%

201

10K

1/20W

R4206

1

2

MX25L1006EZUI-10G

USON

OMIT_TABLE

1MBIT-104MHZ

CRITICAL

U4202

1

4

7

6

5

2

9

8

3

5%

402

CERM

50V

NOSTUFF

150PF

C4268

1

2

5%

1/20W

MF

0201

0

R4268

1 2

5%

402

CERM

50V

NOSTUFF

150PF

C4267

1

2

5%

0

MF

0201

1/20W

R4267

1 2

402

16V

1UF

X5R

10%

C4266

1

2

FERR-1000-OHM

0402

L4206

1 2

FERR-1000-OHM

0402

L4204

1 2

1UF

10%
16V
X5R
402

C4264

1

2

0402

FERR-1000-OHM

L4202

1 2

402

16V

1UF

X5R

10%

C4262

1

2

5%

10

MF

1/20W 201

R4220

1 2

FERR-1000-OHM

0402

L4210

1 2

0201

CERM-X5R

6.3V

0.1UF

10%

C4220

1

2

0402

FERR-600-OHM-300MA-0.85OHM

L4220

1 2

1%

MF
201

1/20W

10K

R4210

1

2

1%

MF

10K

1/20W

201

R4211

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

C4228

1

2

1/20W

47

1%

MF

201

R4215

1 2

1%

MF
201

1/20W

1M

R4214

1

2

0

R4264

1 2

0

R4260

1 2

FERR-1000-OHM

0402

L4200

1 2

1K

1/20W

1%

MF
201

R4219

1

2

MF

1/20W

1K

1%

201

R4218

1

2

VC0359

CRITICAL

FQFN

U4200

9
10

38

37

36
41
42

163443

15

35

44

48
47
46
12

17

32

31

33

29

30

27

28

45

7

40

8

39

1

6
3
5
4
2

11

49

14
13

21

20

23

19

24

18

22

26

25

0201

CERM-X5R

6.3V

0.1UF

10%

C4213

1

2

0201

6.3V

0.1UF

10%

CERM-X5R

C4214

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

C4217

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

C4224

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

C4215

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

C4219

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

PLACE_NEAR=U4200:5mm

C4226

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

C4223

1

2

SHORT-0201

XW4203

1

2

SHORT-0201

XW4202

1 2

1.0UF

20%

0201-1

6.3V
X5R

C4222

1

2

PLACE_NEAR=U4200:5mm

1/20W

1%

MF

8.2K

201

R4213

1

2

47

1/20W
MF

1%

201

R4216

1

2

PLACE_NEAR=U4200:5mm

MF

1/20W

24K

1%

201

R4204

1

2

20%

1.0UF

0201-1

6.3V
X5R

C4221

1

2

0201-1

X5R

20%

1.0UF

6.3V

C4216

1

2

0201

CERM-X5R

6.3V

0.1UF

10%

C4218

1

2

52

52

38

38

38

39

38

38

39

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

89 39 38

52

89 39 38

39

38

39 38

13

47

89

13

89

47

89 58 55 54 52

89 39 38

89 39 38

89 39 38

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

PAD

SI/SIO0

SO/SIO1

GND

THRM

VCC

CS*
WP*

SCLK

HOLD*

NC

NC

NC

PAD

DVDD3

MAVDD33

NC

CLKOUT

USB_VDDL0

DVSS3

OVSS1

SF_WP*

THRM

UART1_TX

UART1_RX

RST*

USB_VRES

TEST

CS_RSTB

CS_CLK

VDDA_PLL

DVDD6

DVDD4

VSSA_PLL

SF_CS*

CS_SDA

LED_FIXED

USB_PADP
USB_PADM

CS_SCK

OVSS2

USB_VSDL0

MIPI_RESISTOR

SF_CLK

CS_PWDB

SF_DIN
SF_DOUT

MRXDATAINN

CLKIN

MRXCLKINN

MRXCLKINP

MRXDATAINP

GPIO9

GPIO3

GPIO1

GPIO0

USB_VSSA0

DVSS4

DVSS6

MAVSS

USB_VDDA0

OVDD1

OVDD2

www.laptoprepairsecrets.com

PP1V2_S0_CAMERA VREG

Camera Processor ExtBoot Cntl

Camera Processor Reset

39 OF 93

MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
VOLTAGE=1.2V

43 OF 121

0.24.0

051-00673

=PP1V8_S0_CAMERA

PCH_CAM_RESET_R

=PP3V3_S0_CAMERA

PM_PCH_PWROK PM_PCH_PWROK

=PP3V3_S0_CAMERA

=PP3V3_S0_CAMERA

P1V2_S0_EN

CAM_P1V2_RST_HOLDOFF_L

CAM_P1V2_RST_HOLDOFF

PP1V2_S0_CAMERA

PCH_CAM_EXT_BOOT_R_L

=PP3V3_S0_CAMERA

CAM_PROC_RESET

CAM_PROC_RESET_L

CAM_EXT_BOOT_L

CAM_EXT_BOOT

PP1V2_S0_CAMERA

SYNC_MASTER=J78_NAT SYNC_DATE=11/05/2013

CAMERA: Controller Support

SOT902

74LVC2G08GM/S505

U4300

7

6

4

8

1

SOT902

74LVC2G08GM/S505

U4300

3

2

4

8

5

201

MF

1/20W

5%

1K

R4304

1

2

10K

201

5%
1/20W
MF

R4306

1

2

SOT-363-LF

MMDT3904-X-G

Q4310

5

3

4

SOT-363-LF

MMDT3904-X-G

Q4310

2

6

1

10%

1UF

X5R-CERM

10V

0402

C4322

1

2

201

MF

1/20W

5%

4.7K

R4320

1

2

201

1/20W
MF

10K

5%

R4302

1

2

SSM3K15AMFVAP

CRITICAL

SOD

Q4302

3

1

2

SOD

CRITICAL

Q4300

3

1

2

X5R-CERM
402

10V

2.2UF

20%

C4301

1

2

51K

201

MF

1/20W

5%

R4300

1

2

10%

1UF

16V

402

X5R

C4320

1

2

DFN

CRITICAL

ISL9021AIRUWZ-T

U4320

3

4

2
5

1

6

6.3V

402

20%

X5R-CERM1

4.7UF

C4324

1

2

10%

CERM-X5R

6.3V

0.1UF

0201

C4300

1

2

89 38

13

89 39 38

82 73 39 19 12

82

73

39

19

12

89 39 38

89 39 38

39 38

13

89 39 38

38

38

39 38

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

08

B

A

Y

08

B

A

Y

D

S

G

D

S

G

GND

VIN

VO

NC
NC

EN

NC

NC

www.laptoprepairsecrets.com

DISPLAY TCON MASTER I2C (NOT USED FOR J95)

PULL-DOWN

155S0367

518S0886

POWERED SOURCE_DETECT
PULL-UP

DISPLAYPORT

INTERNAL DP(STRAIGHT)

DISPLAY TCON SLAVE I2C (CONNECTS TO SMC)

DISPLAYPORT

SOURCE_DETECT

40 OF 93

MIN_LINE_WIDTH=0.4000

VOLTAGE=12V

MIN_NECK_WIDTH=0.2000

VOLTAGE=12V
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

44 OF 121

0.24.0

051-00673

TCON_BLC_EN

DP_INT_PIN_54

PP12V_LCD_F

DP_INT_SPDIF_AUDIO

BLC_LSYNC

DP_INT_PIN_55

DP_INTPNL_ML_AUX_C_N

TCON_RESET_L

DP_INT_PIN_57

DP_INT_PIN_1

DP_INT_PIN_9

TCON_BLC_EN_LED

=PP3V3_S0_DP

=PP3V3_S0_INTDPMUX

=PP12V_S0_LCD

DP_INT_EG_SL_AUX_C_P

PP12V_LCD

DP_INTPNL_ML_C_P<2>

DP_INTPNL_ML_C_P<1>

DP_INTPNL_ML_C_P<0>

DP_INTPNL_ML_C_N<3>

DP_INTPNL_ML_C_N<1>

DP_INTPNL_ML_C_N<0>

DP_INT_EG_SL_P<2>

DP_INT_EG_SL_P<1>

DP_INT_EG_SL_P<0>

DP_INT_EG_SL_N<3>

DP_INT_EG_SL_N<1>

DP_INT_EG_SL_N<0>

DP_INT_EG_SL_C_P<3>

DP_INT_EG_SL_C_P<3>

DP_INT_EG_SL_C_P<2>

DP_INT_EG_SL_C_P<2>

DP_INT_EG_SL_C_P<1>

DP_INT_EG_SL_C_P<1>

DP_INT_EG_SL_C_P<0>

DP_INT_EG_SL_C_P<0>

DP_INT_EG_SL_C_N<3>

DP_INT_EG_SL_C_N<3>

DP_INT_EG_SL_C_N<2>

DP_INT_EG_SL_C_N<2>

DP_INT_EG_SL_C_N<1>

DP_INT_EG_SL_C_N<1>

DP_INT_EG_SL_C_N<0>

DP_INT_EG_SL_C_N<0>

BLC_VSYNC

DP_INT_EG_SL_N<2>

DP_INT_EG_SL_P<3>

BLC_EN

DP_INTPNL_ML_C_P<3>

DP_INTPNL_ML_C_N<2>

DP_INTPNL_ML_HPD

DP_INTPNL_ML_AUX_C_P

SMB_DP_TCON_SLA_SCL

SMB_DP_TCON_SLA_SDA

DP_INT_EG_SL_HPD

DP_INT_EG_SL_AUX_C_N

DP_INT_EG_SL_AUX_P

DP_INT_EG_SL_AUX_N

DISPLAY: Support

SYNC_DATE=1/27/2015SYNC_MASTER=J95_ANDREW

47

402

1/16W

0

5%

NOSTUFF

R4419

1 2

402

0

5%

1/16W

NOSTUFF

R4418

1 2

1/16W

5%

402

0

NOSTUFF

R4417

1 2

79

79

3

69 45

14

X7R-CERM

0.1UF

16V

0402

10%

C4421

1

2

SOT665

CRITICAL

TC7SZ08FEAPE

PLACE_NEAR=J4400:4MM

U4400

2

1

3

5

4

0201

CERM-X5R

0.1UF

10%

6.3V

C4400

1

2

2AMP-32V

0603

F4400

1 2

5%

0

402

1/16W

R4415

1 2

80

201

5%
1/20W

100K

MF

1

2

R4406

6.3V

CERM-X5R

0.1UF

0201

C4458

1 2

10%

CERM-X5R

0.1UF

0201

6.3V10%

C4459

1 2

5%
1/20W
MF
201

100K

1

2

R4407

1/20W

100K

5%

201

MF

1

2

R4400

CERM-X5R

10%

0.1UF

0201

6.3V

C4453

1 2

0.1UF

CERM-X5R

10%

0201

6.3V

C4454

1 2

CERM-X5R

6.3V
0201

10%

0.1UF

C4451

1 2

6.3V
0201

10%

CERM-X5R

0.1UF

C4450

1 2

CERM-X5R 0201

10% 6.3V

C4455

1 2

0.1UF

10%

0201

6.3V

CERM-X5R

0.1UF

1 2

C4456

CERM-X5R

6.3V

0.1UF

10%

0201

C4457

1 2

10%

0.1UF

CERM-X5R 0201

6.3V

C4452

1 2

79

79

79

79

79

79

79

79

91

52

91

69

41

41

41

41

41

41

41

41

41

41

69 41

47

69

F-RT-SM

20525-160E-01

CRITICAL

J4400

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

49

FERR-120-OHM-3A

0603

L4400

1 2

20%

0.001UF

0402

CERM

50V

C4401

1

2

10%
16V

10UF

X5R-CERM
0805

C4420

1

2

89 31

89 41

89

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

NC

NC

BI

BI

OUT

OUT

IN

A

B

Y

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

BI

OUT

www.laptoprepairsecrets.com

PD is on the LR page

TP to DP aliases

41 OF 93

45 OF 121

0.24.0

051-00673

=PP3V3_S0_INTDPMUX

DP_TBT_SEL

=PP1V8_S0_DP

DP_INTPNL_ML_C_P<0>

DP_INTPNL_ML_AUX_C_P

DP_INTPNL_ML_C_N<3>

DP_INTPNL_ML_C_P<3>

DP_INTPNL_ML_C_N<2>

DP_INTPNL_ML_C_N<1>

DP_INTPNL_ML_C_P<1>

DP_INTPNL_ML_C_N<0>

DP_INTPNL_ML_HPD

DP_INT_EG_ML_AUX_P

=PP3V3_S0_INTDPMUX

=PP3V3_S0_INTDPMUX

DP_INTPNL_ML_AUX_C_N

DP_INTPNL_ML_C_P<2>

DP_TBTSRC_HPD

DP_INT_EG_ML_AUX_N

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<3>

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<3>

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<2>

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<2>

DP_TBTSRC_ML_P<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<1>

DP_TBTSRC_ML_P<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<0>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<3>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<3>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<2>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<2>

DP_TBTSRC_ML_N<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<1>

DP_TBTSRC_ML_N<0>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<0>

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_P

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_P

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_N

DP_TBTSRC_AUXCH_N

DP_TBTSRC_AUX_C_P
DP_TBTSRC_AUX_C_N

DP_INTPNL_ML_P<3>

DP_INTPNL_ML_P<2>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_P<0>

DP_INTPNL_ML_N<3>

DP_INTPNL_ML_N<2>

DP_INTPNL_ML_N<1>

DP_INTPNL_ML_N<0>

DP_INTPNL_ML_AUX_P

DP_INTPNL_ML_AUX_N

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_P<2>

DP_INT_EG_ML_P<1>

DP_INT_EG_ML_P<0>

DP_INT_EG_ML_N<3>

DP_INT_EG_ML_N<2>

DP_INT_EG_ML_N<1>

DP_INT_EG_ML_N<0>

DP_INT_EG_ML_HPD

DP_INT_EG_ML_AUX_C_P
DP_INT_EG_ML_AUX_C_N

DP_GPU_MUX_EN

TP_DP_TBTSRC_ML_CP<3>

DP_TBTSRC_ML_C_P<3>

DP_TBTSRC_ML_C_P<3>

TP_DP_TBTSRC_ML_CP<2>

DP_TBTSRC_ML_C_P<2>

DP_TBTSRC_ML_C_P<2>

TP_DP_TBTSRC_ML_CP<1>

DP_TBTSRC_ML_C_P<1>

DP_TBTSRC_ML_C_P<1>

TP_DP_TBTSRC_ML_CP<0>

DP_TBTSRC_ML_C_P<0>

DP_TBTSRC_ML_C_P<0>

TP_DP_TBTSRC_ML_CN<3>

DP_TBTSRC_ML_C_N<3>

DP_TBTSRC_ML_C_N<3>

TP_DP_TBTSRC_ML_CN<2>

DP_TBTSRC_ML_C_N<2>

DP_TBTSRC_ML_C_N<2>

TP_DP_TBTSRC_ML_CN<1>

DP_TBTSRC_ML_C_N<1>

DP_TBTSRC_ML_C_N<1>

TP_DP_TBTSRC_ML_CN<0>

DP_TBTSRC_ML_C_N<0>

DP_TBTSRC_ML_C_N<0>

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_AUXCH_CN

=PP1V8_S0_DP

SYNC_MASTER=J78_KENNY SYNC_DATE=10/09/2013

DISPLAY: MUXing

5%

1/20W

MF 0201

0

R4559

1 2

5%

1/20W

0

0201MF

R4558

1 2

CBTL06142EEE

CRITICAL

TFBGA

U4500

H1

H2

J9

H9

J6

H6

C2

H8

H5

J8

J5

A4

B4

A5

B5

A6

B6

A9

A8

B9

B8

D9

D8

E9

E8

F9

F8

B1

B2

D1

D2

E1

E2

F1

F2

B3

C8G8H4

H7

G2

A1

J2

H3

J1

A2

J4

B7

6.3V

0201

CERM-X5R

10%

0.1UF

C4507

1 2

0201

6.3VCERM-X5R

0.1UF

10%

C4506

1 2

6.3V

0201

CERM-X5R

0.1UF

10%

C4505

1 2

0201

6.3VCERM-X5R

0.1UF

10%

C4504

1 2

6.3V

0201

CERM-X5R

0.1UF

10%

C4503

1 2

6.3V

0201

CERM-X5R

0.1UF

10%

C4502

1 2

0201

6.3VCERM-X5R

0.1UF

10%

C4501

1 2

0201

6.3VCERM-X5R

0.1UF

10%

C4500

1 2

1/20W

MF

201

5%

470K

R4512

1

2

470K

5%

MF
201

1/20W

R4513

1

2

5%

MF

201

470K

1/20W

R4510

1

2

MF

5%
1/20W

201

470K

R4511

1

2

26

26

26

26

26

26

26

26

26

26

5%

1/20W

MF

10K

201

R4504

1

2

201

MF

5%

100K

1/20W

R4503

1

2

1/20W

100K

MF

5%

201

R4502

1

2

69 40

40

58 14

MF

5%
1/20W

10K

U4500.A1:8MM

201

NOSTUFF

R4501

1

2

26

1/20W

201

MF

200K

1%

R4500

1

2

6.3V

10%

CERM-X5R

0.1UF

0201

C4510

1 2

6.3V

10%

CERM-X5R

0.1UF

0201

C4511

1 2

41

41

41

41

41

41

41

41

79

79

40

6.3VCERM-X5R

10%

0.1UF

0201

C4509

1 2

0201

CERM-X5R

10%

0.1UF

6.3V

1 2

C4508

40

40

40

40

40

40

40

40

79

79

79

79

79

79

79

79

80

6.3V
CERM-X5R
0201

10%

0.1UF

C4569

1

2

CERM-X5R

6.3V

0201

0.1UF

10%

C4568

1

2

41

41

41

41

41

41

41

41

89 41 40

89 41

89 41 40

89 41 40

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

41

89 41

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DOUT_0-

AUX-

GND

GND

DIN1_0+

XSD*

HPD_1

DIN1_2-

DAUX1+

DIN1_3+

DDC_DAT2

DAUX2-

DDC_CLK2

HPD_2

GPU_SEL

DIN1_2+

DOUT_1+
DDC_CLK1
DDC_DAT1

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-

DIN2_1+

DDC_AUX_SEL

DIN2_1-

AUX+

HPDIN

DIN2_2+
DIN2_2-

DIN2_3+
DIN2_3-

DAUX2+

DIN2_0-

DIN2_0+

DAUX1-

DOUT_1-

DOUT_0+
DIN1_3-

DIN1_0-

GND

GND

GND

GND

VDD

VDD

DIN1_1+
DIN1_1-

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

OUT

NC

NC

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

EXT PORT B

514-0825

514-0817

EXT PORT A

42 OF 93

VOLTAGE=5V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=5V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=5V
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

46 OF 121

0.24.0

051-00673

USB_EXTA_OC_L

USB_EXTB_OC_L

USB3_EXTB_TX_F_N

USB2_EXTA_N

USB3_EXTA_RX_F_N

PP5V_S4_EXTA_F

PM_EN_USB_PWR

PP5V_S4_EXTA_ILIM

PP5V_S4_EXTB_ILIM

SMC_DEBUGPRT_EN_L

SMC_DEBUGPRT_RX_L

SMC_DEBUGPRT_TX_L

USB2_EXTB_N
USB2_EXTB_P

USB3_EXTA_TX_C_N

USB3_EXTA_TX_C_P

USB3_EXTB_TX_C_N

USB3_EXTB_TX_C_P

USB_ILIM1

USB_ILIM1_R

=PP5V_S4_USB

USB_EXTB_OC_Q_L
USB_EXTA_OC_Q_L

=PP3V3_G3H_SMC_USBMUX

USB3_EXTA_TX_N

USB3_EXTB_TX_N

USB3_EXTA_TX_P

USB3_EXTA_RX_F_P

USB3_EXTB_RX_F_N

USB3_EXTB_TX_P

USB_EXTA_P

USB_EXTA_N

USB_EXTA_OC_Q_L

USB_EXTB_OC_Q_L

=PP3V3_S4_PWRCTL

USB3_EXTB_TX_F_P

USB3_EXTB_RX_F_P

USB3_EXTA_TX_F_N

USB3_EXTA_TX_F_P

USB3_EXTA_RX_N
USB3_EXTA_RX_P

USB2_EXTA_P

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

USB_EXTB_N

USB_EXTB_P

PP5V_S4_EXTB_F

USB3_EXTB_RX_P

USB3_EXTB_RX_N

SYNC_DATE=10/21/2013SYNC_MASTER=J78_DAVID

USB-A: EXTERNAL USB PORTS A & B

1%

402

MF-LF

1/16W

11.5K

R4602

1

2

10V

20%

402

0.1UF

CERM

C4607

1

2

FERR-120-OHM-3A

0603

L4601

1 2

13

13

13

13

10V
CERM

20%

402

0.1UF

C4617

1

2

SOD

NOSTUFF

CRITICAL

Q4621

3

1

2

201

1/20W

5%

0

MF

R4622

1 2

201

5%

MF

1/20W

0

R4612

1 2

17 13

17 13

201

100K

5%

MF

1/20W

R4621

1

2

201

100K

5%
1/20W
MF

R4611

1

2

SOD

NOSTUFF

CRITICAL

Q4611

3

1

2

D4601

CRITICAL

ESD112-B1-02ELS

0201

1

2

CRITICAL

ESD112-B1-02ELS

0201

D4606

1

2

CKPLUS_WAIVE=pdifpr_badterm

8

SIGNAL_MODEL=PI3USB102_TQFN_PI3USB102EZLE_MOJO

CRITICAL

PI3USB102EZLE

TQFN

CKPLUS_WAIVE=ndifpr_badterm

CKPLUS_WAIVE=ndifpr_badterm

CKPLUS_WAIVE=pdifpr_badterm

U4610

6

7

3

4

5

10

9

2

1

44

0603

FERR-120-OHM-3A

1 2

L4611

MF-LF

402

1/16W

100K

5%

R4605

1

2

13

13

13

1%
1/16W
MF-LF

402

11.5K

R4603

1

2

ESD112-B1-02ELS

0201

CRITICAL

D4612

1

2

ESD112-B1-02ELS

0201

CRITICAL

D4613

1

2

0201

CRITICAL

D4614

1

2

ESD112-B1-02ELS

ESD112-B1-02ELS

0201

CRITICAL

D4615

1

2

ESD112-B1-02ELS

0201

CRITICAL

D4603

1

2

ESD112-B1-02ELS

0201

CRITICAL

D4602

1

2

CRITICAL

ESD112-B1-02ELS

0201

D4605

1

2

ESD112-B1-02ELS

D4604

0201

CRITICAL

1

2

SLP1210N6

CRITICAL

RCLAMP0582N

D4611

1

452 3

6

CRITICAL

F-ANG-TH

USB-NO2-T86-D8

J4610

2
3
4

10
11
12
13
14
15
16
17
18
19
20
21
22

7

5
6

8
9

1

CRITICAL

USB-NO1-T86-D8

F-ANG-TH

J4600

2
3
4

10
11
12
13
14
15
16
17
18
19
20
21
22

7

5
6

8
9

1

13

13

45 44

45 44

20%
10V

402

CERM

0.1UF

C4606

1

2

CRITICAL

330UF-25MOHM

CASE-D2E

TANT

20%

6.3V

C4602

1

2

0201

0.1UF

6.3VCERM-X5R10%

C4619

1 2

0.1UF

0201CERM-X5R 6.3V10%

C4618

1 2

0.1UF

02016.3VCERM-X5R10%

C4609

1 2

C4608

0201

0.1UF

6.3V10% CERM-X5R

1 2

CRITICAL

120-OHM-90MA

DLP0NS

L4612

1 2

34

CRITICAL

120-OHM-90MA

DLP0NS

L4602

1 2

34

CRITICAL

0504

80OHM-25%-100MA

GND_VOID=TRUE

L4614

1

2

3

4

CRITICAL

0504

80OHM-25%-100MA

GND_VOID=TRUE

L4613

1

2

3

4

80OHM-25%-100MA

CRITICAL

GND_VOID=TRUE

0504

L4604

1

2

3

4

80OHM-25%-100MA

CRITICAL

0504

GND_VOID=TRUE

L4603

1

2

3

4

13

13

13

0402

X7R-CERM

0.01UF

16V

20%

C4615

1

2

0402

16V

20%

X7R-CERM

0.01UF

C4605

1

2

402

20%
10V

CERM

0.1UF

C4601

1

2

CRITICAL

SON

TPS2561DR

U4600

4
5

10

6

1

7

2
3

9
8

11

72 43

89 43

42

42

89

42

42

89 71 64 43

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

IN

IN

D

S

G

OUT

OUT

D

S

G

M-

M+

Y-

Y+

D-

D+

OE* SEL

GND

VCC

IN

BI

BI

BI

IO

IO

VBUS

GND

NC

NC

SHIELD

STDA_SSRX-

VBUS

GND_DRAIN

D+

D-

GND

STDA_SSRX+

STDA_SSTX­STDA_SSTX+

SHIELD

STDA_SSRX-

VBUS

GND_DRAIN

D+

D-

GND

STDA_SSRX+

STDA_SSTX­STDA_SSTX+

BI

BI

OUT

IN

SYM_VER-1

SYM_VER-1

L1

L2

L1

L2

L1

L2

L1

L2

BI

IN

IN

PAD

EN1

FAULT2*

FAULT1*

EN2

IN_1

IN_0

ILIM

OUT1

OUT2

THRM

GND

www.laptoprepairsecrets.com

J16:514-0827
J17:514-0842

J16:514-0826
J17:514-0841

EXT PORT C

EXT PORT D

43 OF 93

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

47 OF 121

0.24.0

051-00673

USB_EXTD_N

PM_EN_USB_PWR

=PP5V_S4_USB

USB3_EXTD_RX_F_N

USB_EXTD_OC_Q_L

USB3_EXTD_RX_F_P

USB_EXTC_OC_Q_L

USB3_EXTC_TX_P

USB3_EXTD_TX_N

USB3_EXTD_TX_P

USB3_EXTC_RX_F_P

USB_EXTD_P

USB_ILIM2_R

USB_ILIM2

USB3_EXTD_TX_C_P

USB3_EXTD_TX_C_N

USB3_EXTC_TX_C_P

USB3_EXTC_TX_C_N

USB2_EXTD_P

USB2_EXTD_N

USB2_EXTC_P

USB2_EXTC_N

PP5V_S4_EXTD_F

PP5V_S4_EXTC_ILIM PP5V_S4_EXTC_F

USB3_EXTC_TX_F_P

USB3_EXTC_TX_F_N

USB3_EXTC_RX_P

USB3_EXTC_RX_N

USB3_EXTD_TX_F_P

USB3_EXTD_TX_F_N

USB3_EXTD_RX_P

USB3_EXTD_RX_N

PP5V_S4_EXTD_ILIM

USB_EXTD_OC_L

USB_EXTD_OC_Q_L

USB_EXTC_OC_Q_L

=PP3V3_S4_PWRCTL

USB_EXTC_OC_L

USB3_EXTC_TX_N

USB3_EXTC_RX_F_N

USB_EXTC_P

USB_EXTC_N

USB-A: EXTERNAL USB PORTS C & D

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

2

1

C4701

0.1UF

402

20%

CERM

10V

11

8

9

3

2

7

1

6

10

5

4

U4700

CRITICAL

TPS2561DR

SON

2

1

R4702

11.5K

MF-LF

402

1%

1/16W

2

1

C4715

0.01UF

X7R-CERM

0402

20%
16V

2

1

C4717

0.1UF

CERM
402

10V

20%

2

1

C4705

0.01UF

0402

X7R-CERM

20%
16V

2

1

C4707

0.1UF

402

CERM

10V

20%

13

13

21

0603

FERR-120-OHM-3A

L4711

21

R4712

MF

201

5%

0

1/20W

21

R4722

1/20W

201

5%

0

MF

17 13

17 13

2

1

3

Q4721

SOD

NOSTUFF

CRITICAL

2

1

R4711

100K

5%
1/20W
MF
201

2

1

R4721

5%
1/20W

201

100K

MF

2

1

3

Q4711

SOD

NOSTUFF

CRITICAL

13

13

2

1

R4703

11.5K

MF-LF

402

1%

1/16W

2

1

D4712

ESD112-B1-02ELS

0201

CRITICAL

2

1

D4713

ESD112-B1-02ELS

0201

CRITICAL

2

1

D4714

ESD112-B1-02ELS

0201

CRITICAL

2

1

D4715

ESD112-B1-02ELS

0201

CRITICAL

2

1

D4702

ESD112-B1-02ELS

0201

CRITICAL

2

1

D4703

ESD112-B1-02ELS

0201

CRITICAL

2

1

D4704

ESD112-B1-02ELS

0201

CRITICAL

2

1

D4705

ESD112-B1-02ELS

0201

CRITICAL

6

32 5 4

1

D4711

SLP1210N6

RCLAMP0582N

CRITICAL

6

32 5 4

1

D4701

CRITICAL

SLP1210N6

RCLAMP0582N

1

9

8

6

5

7

22

21

20

19

18

17

16

15

14

13

12

11

10

4

3

2

J4710

F-ANG-TH

USB-NO4-T86-D8

CRITICAL

1

9

8

6

5

7

22

21

20

19

18

17

16

15

14

13

12

11

10

4

3

2

J4700

CRITICAL

F-ANG-TH

USB-NO3-T86-D8

2

1

C4702

6.3V

330UF-25MOHM

CASE-D2E

TANT

CRITICAL

20%

21

L4701

FERR-120-OHM-3A

0603

13

13

21

C4719

CERM-X5R10%

0.1UF

02016.3V

21

C4718

6.3VCERM-X5R10%

0.1UF

0201

4

3

2

1

L4714

CRITICAL

80OHM-25%-100MA

0504

GND_VOID=TRUE

13

13

21

C4709

CERM-X5R10% 6.3V 0201

0.1UF

21

C4708

10% CERM-X5R 6.3V

0.1UF

0201

4

3

2

1

L4704

GND_VOID=TRUE

80OHM-25%-100MA

CRITICAL

0504

4 3

21

L4712

CRITICAL

DLP0NS

120-OHM-90MA

4 3

21

L4702

CRITICAL

120-OHM-90MA

DLP0NS

4

3

2

1

L4713

CRITICAL

80OHM-25%-100MA

0504

GND_VOID=TRUE

4

3

2

1

L4703

CRITICAL

80OHM-25%-100MA

0504

GND_VOID=TRUE

13

13

13

13

72 42

89 42

43

43

43

43

89 71 64 42

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PAD

EN1

FAULT2*

FAULT1*

EN2

IN_1

IN_0

ILIM

OUT1
OUT2

THRM

GND

BI

BI

OUT

OUT

D

S

G

D

S

G

BI

BI

IO

IO

VBUS

GND

NC

NC

IO

IO

VBUS

GND

NC

NC

SHIELD

STDA_SSRX-

VBUS

GND_DRAIN

D+

D-

GND

STDA_SSRX+

STDA_SSTX­STDA_SSTX+

SHIELD

STDA_SSRX-

VBUS

GND_DRAIN

D+

D-

GND

STDA_SSRX+

STDA_SSTX­STDA_SSTX+

IN

IN

L1

L2

IN

IN

L1

L2

SYM_VER-1

SYM_VER-1

L1

L2

L1

L2

OUT

OUT

OUT

OUT

www.laptoprepairsecrets.com

arch

proj

LINK_OK

arch

analog

J95 new:Was SMC_S5_PWRGD_VIN

proj

int

arch

J95 new:was G3_POWERON_L

arch

arch

arch

arch

arch

GPU's GPIO-19 = CTF

analog

arch

arch

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

arch

proj

GFX_OK

arch

int arch

arch

proj
arch

arch

arch

analog

arch
proj

int

proj

proj

arch int

arch

od
od
od

od
od

analog

int

arch

arch

arch

arch

proj

analog

arch

od

analog

(OD)

analog

arch
arch

int

proj

analog

arch
arch

proj

arch

arch

arch

arch
arch

int

int

int

arch int

proj

arch

proj

arch

od

proj

proj int

int

int

odarch

arch

proj

arch

arch

od

proj
proj

arch

od

od

arch

arch

arch od

arch

od

od

od

arch

arch

arch

arch
arch

arch

od
od

arch

arch

arch

arch

arch

analog

analog

arch

proj

proj

proj

proj
proj

proj

proj

analog
analog

analog

analog

analog

proj

proj

proj

proj

proj

proj

proj

proj
proj

proj
proj

analog

analog

analog

analog
analog

analog

analog

analog
analog

arch

arch

analog

analog

proj

proj
proj analog

analog

proj

NOTE: Unused pins have "SMC_Pxx" names. Unused

arch

arch

int

arch

arch

arch

arch

arch

int

arch analog

arch

pwm

arch

arch

arch

J95 new:Was SMS_INT_L

TCON_OK

J95 new:Was SMC_G3_WAKESRC_EN

proj

proj

arch

arch

44 OF 93

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.1000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

50 OF 121

0.24.0

051-00673

SMC_RUNTIME_SCI_L

SMBUS_SMC_2_S0_SDA

AP_EVENT_L

SMC_CLK32K

PP1V2_G3H_SMC_VDDC

SMC_DELAYED_PWRGD

SMC_PME_S4_WAKE_L

SMC_PP4

=PP3V3_G3H_SMC

SMC_SYS_LED

SMC_ADC23

CPU_PROCHOT_L
SMC_VCCIO_CPU_DIV2

SMC_CPU_CATERR_L

LPC_CLK24M_SMC

LPC_AD<2>

LPC_AD<1>

LPC_AD<3>

SMBUS_SMC_4_ASF_SDA

SMBUS_SMC_5_G3H_SDA

SMC_PM_G2_EN

CPU_THRMTRIP_3V3

SPI_DESCRIPTOR_OVERRIDE_L

SMC_PC4

SMC_ADC16

SMC_ADC22

SMC_GFX_THROTTLE_L

SMC_PH3

SMC_PH2

GFX_SMC_ALERT_R

LPC_AD<0>

SMC_TOPBLK_SWP_L

SMC_PN5

SMC_PN7

SMC_PN6

SMC_PP7

SMC_PP6

SMC_PP5

SMC_DEBUGPRT_TX_L

SMS_USBC_INT_L

ENET_ASF_GPIO

SMC_DP_HPD_L

SMC_PP0

SMC_PECI_L

CPU_PECI

SMC_ADC13

LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ

SMC_WAKE_SCI_L

SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_4_ASF_SCL

SMC_PN3

SMC_PF0

SMC_EXTAL

SMC_FAN_1_CTL

SMC_ADC21

SMBUS_SMC_1_S0_SCL

SMC_BATLOW_L

GND_SMC_AVSS

PP3V3_G3H_AVREF_SMC

SMC_ADC14

SMC_PL7

SMC_PME_S4_DARK_L

SMC_PL6

SMBUS_SMC_2_S0_SCL

SMC_ADC1

SMC_ADC3

SMC_ADC11
SMC_ADC12

SMC_ADC6

SMC_ADC9LPC_PWRDWN_L

SMC_ADC2

SMC_ADC0

SMC_ADC20

SMC_ADC10

SMC_ADC15

SMC_ADC5

SMC_ADC4

SMC_ADC7
SMC_ADC8

SMBUS_SMC_0_S0_SCL

SMC_XTAL

SMC_WAKE_L

SMC_TMS
SMC_TDO
SMC_TDI

SMC_TCK

SMC_RESET_L

SMC_FAN_0_CTL

PP3V3_G3H_SMC_VDDA

PM_CLKRUN_L

NC_SMC_XOSC1

NC_SMC_HIB_L

SMC_PQ3

SMC_ADC18
SMC_ADC19

SMC_ADC17

SMBUS_SMC_5_G3H_SCL

SMBUS_SMC_0_S0_SDA

ALL_SYS_PWRGD

SMC_PF1

SMC_PJ3

SMC_PJ2

SMC_PF2

SMC_DEBUGPRT_EN_L
GFX_SMC_CTF_3V3

SMC_THRMTRIP

PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L
SMC_PH7

SMC_OOB1_D2R_L
SMC_OOB1_R2D_LSMC_RX_L

SMC_TX_L

PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L

SMC_PROCHOT

PM_DSW_PWRGD

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_PF3
S5_PWRGD
SMC_PM_PCH_SYS_PWROK

SMC_BC_ACOK

SMBUS_SMC_1_S0_SDA

SMC_DEBUGPRT_RX_L

SYNC_DATE=11/06/2014SYNC_MASTER=BRANCH_JERRYCHOW

SMC: Controller

45

80

10%

CERM
402

6.3V

1UF

1

2

C5012

10%

CERM
402

6.3V

1UF

C5011

1

2

10%

CERM
402

6.3V

1UF

1

2

C5010

6.3V
X5R

0201-1

1.0UF

20%

PLACE_NEAR=U5000.D1:4mm

C5020

1

2

PLACE_NEAR=U5000.D2:4mm

0201

10V
X5R-CERM

0.01UF

10%

C5021

1

2

45

45

45

45

45

45

10%

0.1UF

CERM-X5R

6.3V

0201

C5001

1

2

10%

0.1UF

CERM-X5R

6.3V

0201

C5007

1

2

10%

0.1UF

CERM-X5R

6.3V

0201

C5008

1

2

10%

0.1UF

CERM-X5R

6.3V

0201

1

2

C5009

10%

0.1UF

CERM-X5R

6.3V

0201

C5006

1

2

10%

0.1UF

CERM-X5R

6.3V

0201

C5005

1

2

10%

0.1UF

CERM-X5R
0201

6.3V

C5004

1

2

10%

0.1UF

0201

C5003

1

2

6.3V
CERM-X5R

0.1UF

10%

CERM-X5R

6.3V

0201

C5016

1

2

10%

0.1UF

CERM-X5R

6.3V

0201

C5015

1

2

10%

0.1UF

6.3V

0201

CERM-X5R

C5014

1

2

10%

0.1UF

6.3V

0201

CERM-X5R

C5013

1

2

0201

10%

0.1UF

6.3V
CERM-X5R

C5017

1

2

45

45

45

45

34

61 45 6

FILTER_2P_0402_30_OHM_1_7A

30-OHM-1.7A

0402

L5001

1 2

18

73

80

45

45

45

45

45

45

45

45 32

45

45

45

45

72 32 12

72 12

73 72 45 36 12 6

45

45

45

45

45 32

45

51

51

45

45

51

51

45

45

45

45

45

45 12 6

14 12

45 24 23 22 21

18 17 12

17 12

45

73 3

45

42

45

45

45

45

45

45 42

45 42

45

73 45 27

73 45

71 66 45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

47

47

47

47

47

47

47

47

14 12

19 12

45

12

19

12

11

12

12

12

12

10V

X5R-CERM

0603-1

1UF

20%

C5002

1

2

1M

MF

1/20W

5%

201

R5002

1

2

45

46 45

SM

PLACE_NEAR=U5000.A1:4MM

SHORT_SM_BASE

XW5000

12

LM4FSXAH5BB

OMIT_TABLE

BGA

U5000

A1
C7
D9
E5
F9
H5
H9
J5
J8
J11

K11

C3

E3

M12

A2

G12

G13

B11

G10 C10

A10
A11
B10

K12

D7

E6
E8
E9

F10

J7
J9

J10

D3

J1
J6

K13

D6

D1

D2

N13

M10

N10

M5

K7

N9

OMIT_TABLE

BGA

U5000

E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8

K2
K1
L2

E10
D13

M4

N2
N8

M8

L8

N7

M7

N4
N3

B13
A13
C12
D11
H12

G11

D12

F13

C13

F12

H13

L1

C4
C6

L9
K9

J4
J2

B12

C11

A12

H11

L13

G3

D10

L11

N12

M13

L12

J12

J13

L5
D8
K6

D4
E4

F5
N5

N6

K5

M6

L6

M2
M3
L4
N1

L10

M9

F4

C9
B9
A9
C8

D5

C5

L3

M1

F11
E11

E13
E12

L7

K3
K4

J3
H4
H3
G4

H10

F3

M11

N11

LM4FSXAH5BB

K10

K8

89 51 45

45

49 48 45

45 45

46 45

45

45

46 45

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

BI

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

IN

IN

OUT

BI

BI

OUT

IN

OUT

IN

OUT

NC

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

IN

OUT

BI

IN

IN

IN

BI

BI

BI

BI

IN

IN

(2 OF 2)

VDD

VBAT

OSC1

SWDIO/TMS

SWCLK/TCK

XOSC1

OSC0

NC

GND

PK4/RTCCLK

GNDA

VDDA

VREFA+

XOSC0

WAKE*
HIB*

RST*

TDI

SWO/TDO

VREFA-

VDDC

(1 OF 2)

C0+

T2CCP1/PJ3

T2CCP0/PJ2

T1CCP0/PJ0

PF5

PF4

T3CCP1/PJ5/C2-

T3CCP0/PJ4/C2+

I2C5SCL

PN5/FAN0TACH3
PN6/FAN0PWM4

SSI1TX/PF1

I2C2SCL

I2C4SCL

PQ4/IRQ128

PQ3/IRQ127

I2C5SDA

I2C1SDA

SSI0TX/PA5

PP0/IRQ116

PN7/FAN0TACH4

SSI1RX/PF0

I2C4SDA

PQ6/IRQ130

PP2/IRQ118

I2C1SCL

SSI0FSS/PA3

SSI0CLK/PA2

U0TX

PP1/IRQ117

PN4/FAN0PWM3

SSI1CLK/PF2

I2C3SCL

WT0CCP1/PG5

PQ7/IRQ131

PP5/IRQ121

SSI0RX/PA4

U0RX

PC5/C1+

SSI1FSS/PF3

I2C3SDA

WT0CCP0/PG4

PP7/IRQ123

PQ5/IRQ129

WT2CCP1/PH1

WT2CCP0/PH0

C0-

PP4/IRQ120

PP3/IRQ119

PH2/FAN0PWM5

WT3CCP0/PH4

PH3/FAN0TACH5

LPC0SERIRQ

WT5CCP1/PM3

WT3CCP1/PH5
WT4CCP0/PH6

AIN19

AIN18

WT4CCP1/PH7

PN2/FAN0PWM2

AIN16
AIN17

LPC0SCI*

U1RX/B0

PQ2/IRQ126

T0CCP0/PB6
T0CCP1/PB7

AIN02
AIN03

USB0DM
USB0DP

U1TX/PB1

I2C0SCL

PQ1/IRQ125

AIN00
AIN01

I2C0SDA

PN3/FAN0TACH2

PP6/IRQ122

PQ0/IRQ124

LPC0RESET*

PK6/FAN0PWM1

PECI0TX

PECI0RX

AIN12

LPC0AD0

PK5

T1CCP1/PJ1

AIN22

AIN20

AIN10

AIN06

AIN15

PK7/FAN0TACH1

AIN23

AIN21

AIN11

AIN09

AIN05

I2C2SDA

C1-

AIN04

PM6/FAN0PWM0
PM7/FAN0TACH0

AIN14

AIN13

LPC0PD*

LPC0CLKRUN*

AIN07
AIN08

LPC0AD2

LPC0AD1

LPC0FRAME*

LPC0CLK

LPC0AD3

www.laptoprepairsecrets.com

Power Button

IC0I

IC0G

ID2R

(LED-3)

(LED-4)
(LED-3)

IG1C

Skylake PDG 543611 tabel 12-4

(J95 renamed)

(J95 new)

IG0I

(J95 new)

Project-specific Aliases

(5K PU AT MLB)

IC0C

GPU GPIO19_CTF

To SMC

HSW: PusPull, no PU

SKL: OpenDrain, 1K PU at CPU page CSA-6

PROCHOT Support

PECI Support

Serial/JTAG Interface Pull-ups

AC/DC Burst Mode Enable

SMC 32KHz Clock

VG0C

IG1F

IG0C

VC0G

ID20

VC0C

VD20

VD2R

197S0478

SMC Crystal

Note:

(ipu)

Note:

Arch Pull Up/Down

IG1A

IM0R

VM0R

IH02

IC0M

IC0S

Unused Project-specific

VG0I

VH1R

IH1R

IH05

To SMC

(Gated GPU GPIO19_CTF)

and ACDC_BURST_EN_L could be floating.

and chip is not yet configured.

case when SMC is initializing in S5,

Level-shifter that allows SMC to drive PECI

(ipu)

Note: IPU are pulled to VIN rail

SMC Supervisor and AVREF Supply

Open-drain stage on S4 to account

SMC Controlled RTC Reset

To absorb current from discharging RTC Reset CAP

Place this circuit near the Tee point to minimize reflections

Comparator VRef

ADC Channel Aliases

Platform Thermal Control

To PCH

PDG table 12-8

1K PU + 590 Resistor at CSA-12

(1OOK PD AT BLC)

45 OF 93

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1000

VOLTAGE=0V

PLACE_NEAR=U5000.G13:15MM

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1000

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4000

51 OF 121

0.24.0

051-00673

MAKE_BASE=TRUE

NC_SMC_PF0

SMC_OOB2_R2D_L

MAKE_BASE=TRUE

PM_THRMTRIP_R_L

PM_THRMTRIP_L

CPU_THRMTRIP_3V3

SMC_TT_R

=PP3V3_S0_SMC

MAKE_BASE=TRUE

VSNS_P12VG3HSMC_ADC0

SMC_TDO

SMC_TDI

SMC_RX_L

SMC_PECI_L

GND_SMC_AVSS

=PP3V3_G3H_SMC

SMBUS_SMC_5_G3H_SCL

SMC_PN6

SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_SMBUS_SMC_5_G3H_SCL

NC_SMBUS_SMC_5_G3H_SDA

MAKE_BASE=TRUE

NC_SMC_OOB1_R2D_L

MAKE_BASE=TRUE

SMC_PC4

SMC_PQ3

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

SMC_OOB1_R2D_L

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_SMC_G3_WAKESRC_EN

SMC_ADC23

NC_G3_POWERON_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_S5_PWRGD_VIN

MAKE_BASE=TRUE

NC_SMC_PP5

NC_SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

SMC_BT_PWR_EN

MAKE_BASE=TRUE

NC_SMC_PP6

MAKE_BASE=TRUE

NC_SMC_PP7

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_PME_S4_DARK_L

SMC_PP4

SMC_ADC21

SMC_ADC20

SMC_ADC19

SMC_PME_S4_DARK_L

SMC_PP6

SMC_PP5

SMC_CLK32K

PM_SLP_S3_L

BURSTMODE_EN_L

=PP3V3_S5_SMC

ACDC_BURST

ACDC_BURST_EN_L

SMC_XTAL

SMC_XTAL_R

MAKE_BASE=TRUE

VSNS_CPUVCC

SMC_RESET_L

SMC_ADC15

MEM_EVENT_L

SMC_DEBUGPRT_RX_L

AP_EVENT_L

=PPVIN_G3H_SMCVREF

PM_CLK32K_SUSCLK_R

=PP3V3_S4_AP

SMC_PM_PCH_SYS_PWROKPM_PCH_SYS_PWROK

SMC_TOPBLK_SWP_L

SMC_PME_S4_WAKE_L

SMS_USBC_INT_L

=PP3V3_G3H_SMC

PM_DSW_PWRGD

ENET_ASF_GPIO

SMC_BC_ACOK
SMC_SYS_LED

PCH_STRP_TOPBLK_SWP_L

PP3V3_S4_AP_FET

=PP3V3_S0_SMC

SMC_CPU_CATERR_L

VSNS_P12VS0_CPUCORE

MAKE_BASE=TRUE

SMC_MANUAL_RST_L

PP3V42_G3H_SMC_SPVSR

ISNS_CPUVCC_GT

MAKE_BASE=TRUE

ISNS_P12VG3H

MAKE_BASE=TRUE

PP3V3_G3H_AVREF_SMC

SMC_ADC18

SMC_ADC14

SMC_ADC22

SMC_ADC16

SMC_ADC17

SMC_ADC13

PM_CLKRUN_L

SMC_DEBUGPRT_TX_L

SMC_TMS

SMC_TCK

SMC_TX_L

SMC_PM_G2_EN

SMC_DELAYED_PWRGD

SMC_BT_PWR_EN

MAKE_BASE=TRUE

ISNS_P12VS0_CPUCORE

SMC_EXTAL

AP_PWR_EN

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

RTC_RESET_L_R

SMC_ASSERT_RTCRST

CPU_PECI_R

CPU_PECI

SMC_RESET_R_L

RTC_RESET_L

CPU_PROCHOT_L_R

CPU_PROCHOT_L

GFX_SMC_CTF_3V3

GFX_SMC_CTF_R

SMC_THRMTRIP

GFX_TMTP_R

SMC_PN5

MAKE_BASE=TRUE

ACDC_BURST_EN_L

SMC_PJ3

SMC_OOB2_D2R_L

MAKE_BASE=TRUE

SMC_PH2

SMC_PL6

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

SMC_PN3

MAKE_BASE=TRUE

NC_SMC_PF1

NC_SMC_SMC_BATLOW_L

MAKE_BASE=TRUE

SMC_PH3

SMC_DP_HPD_L

=PP3V3_G3H_SMC

SMC_BATLOW_L

SMBUS_SMC_5_G3H_SDA

=PP3V3_S5_SMC

=PP3V3_S4_SMC

CPU_THRMTRIP_L

SMC_PROCHOT

PM_SLP_S3_BUF_L

MAKE_BASE=TRUE

ISNS_P12VS0_HDD

SMC_PP7

SMC_PL7

SMC_PF1

SMC_PF0

SMC_PN7

MAKE_BASE=TRUE

NC_SMC_PF2

MAKE_BASE=TRUE

SMC_ASSERT_RTCRST

TCON_BLC_EN

MAKE_BASE=TRUE

GFX_OK_L

MAKE_BASE=TRUE

DP_LINK_OK

MAKE_BASE=TRUE

SMC_ACDC_ID

MAKE_BASE=TRUE

SMC_PP0

SMC_PJ2

SMC_ADC2

ISNS_CPUVCC

MAKE_BASE=TRUE

VSNS_CPUVCC_GT

MAKE_BASE=TRUE

SMC_PF2

GFX_PCH_THRMTRIP

PWR_BTN

MAKE_BASE=TRUE

NC_SMC_PF3SMC_PF3

SMC_PH7

MAKE_BASE=TRUE

ISNS_CPUVCC_IO

MAKE_BASE=TRUE

ISNS_P12VS0_FBVDDQ

NC_SMC_PH3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

VSNS_VDDQS3_DDR

VSNS_GPUCORE_ALT

MAKE_BASE=TRUE

SMC_ADC5

SMC_ADC3

SMC_ADC1

MAKE_BASE=TRUE

ISNS_GPUCORE_ALT

MAKE_BASE=TRUE

VSNS_GPU_VDDCI

MAKE_BASE=TRUE

ISNS_P12VS0_GPUCORE

MAKE_BASE=TRUE

ISNS_HDDS0

MAKE_BASE=TRUE

VSNS_SSD_S4

MAKE_BASE=TRUE

ISNS_VDDQS3_DDR

ISNS_SSD_S4

MAKE_BASE=TRUE

ISNS_P12VS0_GPU_AUX

MAKE_BASE=TRUE

MAKE_BASE=TRUE

ISNS_GPU_VDDCI

SMC_ADC12

SMC_ADC11

SMC_ADC10

SMC_ADC8

SMC_ADC7

SMC_ADC6

MAKE_BASE=TRUE

ISNS_CPUVCC_SA

SMC_ADC4

MAKE_BASE=TRUE

ISNS_P1V35S0SMC_ADC9

=PP3V3_G3H_SMC

MAKE_BASE=TRUE

SMC_ONOFF_L

CPU_TT_OC_L

CPU_CATERR_L

=PP1V0_S3_SMC

SMC_PECI_L_R

SMC_VCCIO_CPU_DIV2

=PP1V0_S3_SMC

SYNC_MASTER=BRANCH_JERRYCHOW SYNC_DATE=11/06/2014

SMC: Controller Support

C0G

50V

12PF

5%

0402

C5166

1

2

5%
50V

0402

C0G

12PF

C5165

1

2

SOT665

TC7SZ08FEAPE

U5140

2

1

3

5

4

2

100K

MF

1/20W

201

5%

R5155

1

32

CERM-X5R

0.1UF

10%

6.3V
0201

C5140

1

2

44 14

201

MF

1/20W5%

1K

R5154

1 2

1000PF

NOSTUFF

0402

25V5%

C5103

1

2

CERM

46 44

R5103

0

1/20W

MF 0201
5%

12

20%

4.7UF

6.3V

X5R-CERM1

402

C5102

1

2

47

5%

402

MF-LF

1/16W

R5102

1 2

44

5%

201

10K

MF

1/20W

R5181

1 2

21

R5186

1/16W5%

MF-LF 402

100K

R5184

5% 1/16W

100K

402MF-LF

1 2

402

NOSTUFF

1M

1/16W5%
MF-LF

R5166

1

2

10K

MF

1/20W

201

5%

R5171

1 2

10K

MF

1/20W

201

5%

R5170

1 2

2

1

10K

201

1/20W

5%

MF

R5124

R5194

330

1/16W

402

5%

1

MF-LF

2

NOSTUFF

C5199

2

1

1.0UF

X5R-CERM

6.3V

0402

20%

2

1

5%
1/16W
MF-LF

402

R5199

10K

18 12

2

1

3

SOD

SSM3K15AMFVAP

Q5199

CRITICAL

0.1UF

X7R-CERM

16V10%

2

1

C5131

0402

U5000.K1:3mm

CRITICAL

2

1

3

SOD

SSM3K15AMFVAP

Q5125

1

Q5135

SOD

3

2

CRITICAL

SSM3K15AMFVAP

6

402

5%

MF-LF

43

12

1/16W

R5138

60

1

201

MF

1/20W

5%

10K

R5141

2

CRITICAL

SOT563

SSM6N15AFEAP

Q5140

3

5

4

10K

1/20W

5%

MF

201

1

2

R5140

SOT563

CRITICAL

Q5140

6

2

1

SSM6N15AFEAP

12

44

Q5123

3

5

4

CRITICAL

SOT563

SSM6N15AFEAP

1/20W

10K

1

2

MF

201

5%

R5126

80

CRITICAL

SSM6N15AFEAP

Q5123

1

6

SOT563

2

6

0201

MF

1/20W5%

0

R5149

12

44

44 73 17 12

R5148

0201

MF

1/20W

5%

0

12

201

1/20W

100K

MF

5%

R5187

1 2

R5192

5%

201

1/20W

MF

20K

1 2

1

5%

201

1/20W

MF

20K

R5193

2

5%

201

1/20W

MF

10K

R5198

1 2

5%

201

1/20W

MF

10K

R5197

1 2

5%

201

1/20W

MF

10K

R5196

1 2

5%

201

1/20W

MF

10K

R5195

1 2

5%

201

1/20W

MF

100K

R5191

1 2

5%

201

1/20W

MF

10K

R5190

1 2

R5179

5%

201

1/20W

MF

100K

1 2

60

5%

R5120

10K

MF

1/20W

201

2 1

12

PLACE_NEAR=U1100.AN15:12.7MM

MF-LF

402

1/16W

22

5%

R5160

12

44

R5180

5%
MF

10K

201

1/20W

1 2

5%
MF

10K

1/20W

201

R5175

1 2

1/20W5%

MF

10K

201

R5185

1 2

44

1

1/16W

U5000.K1:5mm

MF-LF

2

402

1%

33.2K

R5131

R5130

MF-LF

21

10K

1%

402

1/16W

U5000.K1:5mm

44 12 6

402

2

1

1/16W

5%

330

MF-LF

R5137

2

1

R5136

NONE
NONE

402

NONE

NOSTUFF

OMIT

44

MF-LF

2

1

R5135

1/16W

0

402

5%

5%

201MF

100K

1/20W

R5178

1 2

61 44 6

44

1/16W
MF-LF

5%

0

402

R5165

12

44

SM

43

21

SILK_PART=PwrBtn

DEVELOPMENT

NTC020AK1JB260T

J5120

100K

5%

1/16W

MF-LF

402

R5105

1

2

10%

0402

X7R-CERM

16V

0.01UF

C5106

1

2

0603-1

X5R-CERM

10V

20%

C5105

1

2

1UF

0.01UF

10%

16V

X7R-CERM

0402

C5101

1

2

0.47UF

6.3V
CERM-X5R

1

2

402

10%

C5100

9

VREF-3.3V-VDET-3.0V

DFN

CRITICAL

U5100

4

2

6

7

8

5

1

3

1 2

1/20W

5%

MF

56

R51A2

201

100K

402MF-LF

5% 1/16W

1 2

R51A1

MF

1/20W

201

5%

100

R51A0

1 2

Y5165

3.2X2.5MM-SM

12.000MHZ-30PPM-10PF-85C

CRITICAL

2 4

1 3

44

2

1

C5125

CERM-X5R
0201

6.3V

0.1UF

10%

NOSTUFF

80

21

R5125

33K

201

MF

5%

1/20W

U5000.L7:5mm

2

1

C5127

CERM-X5R

10%

6.3V

0201

0.1UF

NOSTUFF

21

R5127

MF

5%

1/20W

33K

201

R5128

2

1

5%
1/20W

201

MF

33K

CRITICAL

SOT563

SSM6N37FEAP

Q5127

3

5

4

Q5127

CRITICAL

1

2

6

SOT563

SSM6N37FEAP

0

MF

5%

12

0201

1/20W

R5143

R5129

2 1

0

0201

1/20W

5%

MF

33

89 45

48 44

44

44

44

49 48 44

89 51 45 44

44

44

44

44

44

44

44

44

45 32

44

44

44

44

44

44

44

73 72 44 36 12 6

89 45 33

45

44

48

44

44 24 23 22 21

44 42

44 32

89

89 32

44 32

44

89 51 45 44

73 44

44

44

44

32

89 45

48

48

48

44

44

44

44

44

44

44

44

44 42

46 44

46 44

44

71 66 44

73 44 27

48

44

45

45 18

44 45

44

33

44

44 45

44

44

44

89 51 45 44

44

44

89 45 33

89

49

44

44

44

44

44

45 18

69

40

80 3

80 3

60 44

44

44

48

48

44

44

44

48

48

49

48

44

44

44

48

49

48

49

49

49

49

48

49

44

44

44

44

44

44

48

44

49 44

89 51 45 44

89 45

89 45

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

A

B

Y

OUT

IN OUT

OUT

OUT

OUT

D

S

G

D

S

G

D

S

G

IN

OUT

G S

D

G S

D

BI

IN

G S

D

IN

G S

D

IN OUT

OUTIN

OUT

IN

OUT

OUT

BI

IN

BI

IN

OUT

NC

NC

PAD

SN0903049

V+ VIN

MR2*

DELAY

RESET*

GND

THRM

MR1*

REFOUT

OUTIN

SG

D

SG

D

www.laptoprepairsecrets.com

T112 Connector

QUAD_IO MODE (MODE 0 & 3) SUPPORTED

SPI FREQ: 50 MHZ FOR PCH

SPI BootROM

SPI Series Termination

46 OF 93

52 OF 121

0.24.0

051-00673

=PP3V3_S5_ROM

SPI_IO_R<2>

SPI_IO_R<3>

SPI_CS0_R_L

SPI_MLB_IO<3>

SPI_MOSI_R

SPI_CLK_R

SPI_MLB_IO<2>

SPI_MLB_MOSI
SPI_MLB_MISO

SPI_MLB_CLK

SPI_ALT_MISO

SPI_MLBROM_CS_L

=PP3V3_S5_ROM

SPI_MLB_A

SPI_MLB_CS_L
SPIROM_USE_MLB

SPI_ALT_IO<2>

SPI_CS0_L

SPI_IO<3>

SPI_ALT_CS_L

SPI_MLB_MOSI

SPI_ALT_CS_L

SPI_ALT_CLK

SMC_RESET_L

SPI_ALT_IO<3>

SPI_MLB_CS_L

SPI_MISO_R

SMC_TCK

SMC_TMS

SPIROM_USE_MLB

SPI_MLB_MISO

SPI_ALT_MOSI

=PP3V3_G3H_T112

SPI_MOSI

SPI_IO<2>

SPI_ALT_IO<3>
SPI_ALT_IO<2>

SPI_ALT_MISO
SPI_ALT_MOSI

SPI_ALT_CLK

SPI_CLK

SPI_MISO

SPI_MLB_IO<3>

SPI_MLB_IO<2>

SPI_MLB_CLK

SYNC_DATE=03/13/2013SYNC_MASTER=J17_TONY

CPU & CHIPSET: SPI and Debug Connector

R5210

1

2

402

10K

MF-LF

5%

1/16W

2

1

R5240

402

5%

1K

MF-LF

1/16W

2

1

R5241

1/16W
MF-LF

5%

402

1K

402

R5211

MF-LF

5%

1/16W

100K

1

2

21

402

15

5%
1/16W
MF-LF

R5237

PLACE_NEAR=U5210.2:2.8MM

C5205

2

1

402

1UF

10%

6.3V
CERM

U5205

74LVC1G99

SOT833

5

6

4

1

8

7

3

2

PLACE_NEAR=U5210:25.4mm

8

9

2

7

3

5

6

4

1

U5210

WSON

MX25L6473EZNI-10G

64MBIT

CRITICAL

OMIT_TABLE

2

402

MF-LF

43

5%

1

PLACE_NEAR=J5200.10:10.5MM

1/16W

R5232

2

1/16W

43

5%

402

1

PLACE_NEAR=J5200.9:5MM

MF-LF

R5231

21

R5236

15

MF-LF

402

1/16W

5%

PLACE_NEAR=U1100.BD30:10.2MM

21

R5235

1/16W

402

5%

MF-LF

15

PLACE_NEAR=U1100.BC29:10.2MM

12

R5234

21

PLACE_NEAR=U5210.7:5MM

43

402

MF-LF

1/16W

5%

17 12

R5233

43

PLACE_NEAR=U5210.3:5MM

1/16W
MF-LF

5%

1 2

402

CRITICAL

T112

DF40PC-12DP-0.4V-51

16

15

14 13

11

9

8 7

6 5

4 3

2 1

J5200

PLACE_NEAR=U5210:25.4mm

M-ST-SM

12

10

PLACE_NEAR=U5210.2:9MM

MF-LF

402

1/16W

5%

2

R5230

43

1

PLACE_NEAR=U5210.5:10mm

2

R5229

43

1

1/16W

402

MF-LF

5%

MF-LF

2

PLACE_NEAR=U5210.6:5mm

1/16W

5%

1

43

R5228

402

2

5%

43

1

R5227

402

MF-LF

1/16W

PLACE_NEAR=U5205.3:5mm

2

1

5%

402

MF-LF

1/16W

43

PLACE_NEAR=J5200.5:5MM

R5226

1/16W

2

1

5%

402

43

MF-LF

PLACE_NEAR=J5200.3:5MM

R5225

100K

2

1

R5212

5%

402

MF-LF

1/16W

12

402

2

R5220

5%
1/16W
MF-LF

15

PLACE_NEAR=U1100.BD31:10MM

1

12

46 14

PLACE_NEAR=U1100.BB29:10.2MM

21

R5222

5%

402

15

1/16W
MF-LF

21

R5221

1/16W
MF-LF

402

15

5%

PLACE_NEAR=U1100.BC31:10MM

12

17 12

R5224

2

1

PLACE_NEAR=J5200.4:10MM

402

43

MF-LF

1/16W

5%

MF-LF
402

5%

2

R5223

PLACE_NEAR=J5200.6:5MM

1/16W

43

1

2

1

C5210

1UF

6.3V
CERM

402

10%

89 46 17

46

46

46

46

46

46

89 46 17

46

46

46

46

46

46

45 44

46

46

45 44

45 44

46 14

46

46

89

46

46

46

46

46

46

46

46

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND

C

OE*

YA

B

D

VCC

EPAD

VCC

GND

SCLK

CS*

SI/SIO0

SO/SIO1

SIO2

SIO3

BI

BI

IN

OUT

IN

IN

IN

www.laptoprepairsecrets.com

In range 0x10 to 0x2F, needs clarification.

Vref Control

0x30 Write

U9901

SMC (SMBus 1)

NE DISCONNECTED

U5000

GRAPHICS SMB

U8700

J4400

TG0d (AM)

U5600

AM & EM CONNECTED

AM & EM have same addresses

Unused Signal Aliases page

U5000

SMC (SMBus 2)

EMC1414-1:

0X99 Read

0X98 Write

0X83 READ

NE will send to NC alias on

only on AM and EM boards.

SVID GPU VR SMBus is connected

GPU VR I2C

0X82 WRITE

0x52 Write

0X61 WRITE

Panel/Vendor ID:

IR3566B:

0X62 READ

Display TCon

U1100

0x9E Write
0x9F Read

TMP421:

0x1A Write
0x1B Read

0xA4 Write

DIMM 2:

0x89 Read

0x73 Read

0x72 Write

Unused PCH SM Link

J6500

U5000

0x77 Read

CHS

XDP

0x59 Read

U1100

0x99 Read

PCH (SMBus)

Mux

0x76 Write

Line Legend

Master
Slave

0xA1 Read

U2201

J2300

0x94 Write

U2200

U6551

J1800,J1850

Mikey

VRef DAC

J2500

U5600

U1100

SMC (SMBus 0)

0x31 Read

Temp Sensors "T1"

DIMM 0:

EMC1414-1 (PROD):

0x53 Read

ALS

0x92 Write

U5650
EMC1428-7:

UA100

FOR J78:

0x95 Read

Memory Channel A

0x98 Write

U8100

0xA5 Read

0x58 Write

0xA0 Write

U5650

Temp Sensors "T2"

J4200

ADDRESSES USED IN TCON:

Backlight Control

U5000

U9901

PCH (SML 1)

0x98 Write

0x88 Write

0x99 Read

0x93 Read

SMC (SMBus 3)

Graphics Subsystem Temp

TG1d (AM)

Memory Channel B

47 OF 93

53 OF 121

0.24.0

051-00673

SMB_2_S0_DATA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SML_PCH_0_DATA

SML_PCH_0_CLK

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_3

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS =PP3V3_S0_SMBUS_SMC_0

=PP3V3_S0_SMBUS_SMC_2

GFX_SMBDAT_B

GFX_SMBCLK_B

=PP3V3_S0_SMBUS_SMC_1

SMB_3_DATA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMB_3_CLK

MAKE_BASE=TRUE

SMB_1_S0_DATA

SMB_1_S0_CLK

MAKE_BASE=TRUE

SMB_0_S0_DATA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMB_0_S0_CLK

SMBUS_SMC_3_SDA

SMB_DP_TCON_SLA_SDA

SMBUS_SMC_3_SCL

SMB_DP_TCON_SLA_SCL

SMBUS_SMC_2_S0_SDA

=SMB_ALS_SDA

SMBUS_SMC_2_S0_SCL

=SMB_ALS_SCL

SMBUS_SMC_1_S0_SDA

=SMB_VR_GPU_SDA

GPU_SMB_DAT_R

SMBUS_SMC_1_S0_SCL

=SMB_VR_GPU_SCL

GPU_SMB_CLK_R

SML_PCH_1_DATA

SMBUS_SMC_0_S0_SDA

=SMB_SNS1_SDA

=SMB_SNS2_SDA

SML_PCH_1_CLK

SMBUS_SMC_0_S0_SCL

=SMB_SNS1_SCL

=SMB_SNS2_SCL

=I2C_BKLT_SDA

=I2C_CHS_SDA

=I2C_MIKEY_SDA

=I2C_SODIMMA_SDA

=I2C_SODIMMB_SDA

=SMBUS_XDP_SDA

=I2C_BKLT_SCL

=I2C_CHS_SCL

=I2C_MIKEY_SCL

=I2C_SODIMMA_SCL

=I2C_SODIMMB_SCL

=SMBUS_XDP_SCL

MAKE_BASE=TRUE

SMB_2_S0_CLK

MAKE_BASE=TRUE

SMBUS_PCH_CLK

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SYNC_MASTER=BRANCH_JERRYCHOW SYNC_DATE=08/26/2014

SMC: SMBus Connections

NOSTUFF

470K

1/16W

5%

MF-LF
402

R5333

1

2

NOSTUFF

470K

5%

1/16W

402

MF-LF

R5332

1

2

402

MF-LF

1/16W

5%

0

GPU_AM_EM

R5381

12

0

402

5%
1/16W
MF-LF

GPU_AM_EM

R5380

12

5%

10K

1/16W

402

MF-LF

R5365

1

2

MF-LF

5%

10K

1/16W

402

R5364

1

2

1/16W
MF-LF

3.3K

5%

402

R5330

1

2

5%
1/16W

402

3.3K

MF-LF

R5331

1

2

402

3.3K

5%
1/16W
MF-LF

R5320

1

2

402

3.3K

5%

MF-LF

1/16W

R5321

1

2

402

1/16W

4.7K

5%

MF-LF

R5310

1

2

402

5%

MF-LF

1/16W

4.7K

R5311

1

2

402

3.9K

5%
1/16W
MF-LF

R5300

1

2

402

3.9K

MF-LF

5%
1/16W

R5301

1

2

5%
1/16W
MF-LF

402

2.2K

R5360

1

2

MF-LF
402

1/16W

5%

2.2K

R5361

1

2

14

14

89

89 47

89 47 89

89

80

80

89

44

40

44

40

44

38

44

38

44

82

81

44

82

81

14

44

50

50

14

44

50

50

69

56

56

22

21

24

23

17

69

56

56

22

21

24

23

17

14

14

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

GPU highside sense for GPU Core Regulator

26A (PEAK)

GPU FB (VG1F=VD20, IG1F:ADC11)

GPU highside sense for GPU Frame Buffer 1.5V VDDQ Regulator

GAIN: 100 V/V

Gain: 200 V/V

26A (PEAK)

353S2073

NOTE:VSNS on S5 to avoid burning G3H Power

353S2208

RANGE: 0-16.5A

GAIN: 100 V/V

10KHz Sampling filter

GAIN: 100 V/V

CPU VCCIO (VC0I=tbd, IC0I:ADC8)

CPU Core VCC_SA (VC0S=1.05V, IC0S:ADC10)

SMC IMON 12A/3.0V

SMC IMON 50A/3.0V

10KHz Sampling filter

10KHz Sampling filter

Gain: 100 V/V

IMON

AMETHYST - 3.0V=200A

NEPTUNE - 0.9V=180A

12V G3H (VD2R:ADC0/ID2R:ADC1)

AC/DC lowside sense (System total)

Range: 0-3.3A

RANGE: 0-16.5A

CPU highside sense for CPU Core Regulator

VR IMON 12A/1.2V

Max 50A
VR IMON 50A/1.2V

Max 100A

353S2208

Range: 0-16.5A

353S2208

AMETHYST WILL BYPASS THE OPAMP

353S2208

RANGE: 0-4A

AMETHYST - 3.0V=200A

NEPTUNE - 2.7V=180A

Gain: 200 V/V

353S2073

VR IMON 100A/1.2V

Gain:2.5

Max 12A

Gain:2.5

PP12V_S0_GPU (VG1C=VD20, IG1C:ADC17)

10KHz Sampling filter

Gain:2.5

1KHz Sampling filter

SMC IMON:100A/3.0V

PP12V_S0_CPU (VD20:ADC2 /ID20:ADC3)

GPU highside sense for GPU 0.9V & 1.8V VR

GPU AUX RAILS (VG1A=VD20, IG1A:ADC16)

Alternate low side V-sense and IMON amp

CPU Core GT (VC0G:ADC6/IC0G:ADC7)

CPU Core (VC0C:ADC4/IC0C:ADC5)

Range: 0-7A

GPU Core - Alt (VG0C:ADC12/IG0C:ADC13)

48 OF 93

54 OF 121

0.24.0

051-00673

GND_SMC_AVSS

ISNS_CPUGT_FB_R

R_CPUGT_IM_R

GND_SMC_AVSS

=PP5V_S0_ISENSE

PP12V_G3H_SNS

VSNS_P12VG3H

=PP12V_S5_SNS

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_P12VG3H

ISNS_P12VG3H_R

=PP3V3_S5_SENSE

ISNS_P12VS0_GPU_AUX

GND_SMC_AVSS

=PP3V3_S0_SENSE

VSNS_P12VS0_CPUCORE

=PP3V3_S0_SENSE

R_CPU_SA_IM_R

VSNS_CPUVCC_GT

GND_SMC_AVSS

ISNS_P12VS0_FBVDDQ

VREG_GPU_IMON_R

SNS_P12VG3H_P

SNS_P12VG3H_N

ISNS_P12V_FDQ_R

ISNS_P12VS0_GPUC_R

REG_CPUVCC_SA_IMON

REG_CPUVCC_GT_IMON

=PP12V_G3H_SNS_R

GND_SMC_AVSS

PPVCCIO_S0_SNS_CPU

=PPVCCIO_S0_SNS_CPU_R

ISNS_CPUVCC_IO

=PP3V3_S0_SENSE

SNS_VCCIO_N

=PP5V_S0_ISENSE

ISNS_VCCIO_R

VSNS_CPUVCC

R_CPU_IM_R

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_GPUCORE_ALT

REG_CPUVCC_IMON

ISNS_GPUCORE_FB_R

ISNS_CPUVCC_GT

ISNS_CPUGT_FB

GND_SMC_AVSS

ISNS_CPU_SA_FB_R

ISNS_CPU_SA_FB

ISNS_CPUVCC_SA

=PP5V_S0_ISENSE

VSNS_GPUCORE_ALT

SNS_P12VS0_GPUCORE_P

=PP12V_S0_SNS_GPUCORE_R

PP12V_S0_SNS_FBVDDQ

ISNS_P12VS0_CPUCORE

GND_SMC_AVSS

ISNS_CPU_FB

=PPVCC_S0_SNS_CPU

GND_SMC_AVSS

ISNS_CPUVCC

GND_SMC_AVSS

ISNS_P12VS0_GPUA_R

GND_SMC_AVSS

VR_GPU_IMON

ISNS_GPUCORE_FB

=PP12V_S0_SNS_CPUCORE_R

PP12V_S0_SNS_CPUCORE

=PP3V3_S0_SENSE

ISNS_P12VS0_CPUC_R

SNS_P12VS0_GPUCORE_N

PP12V_S0_SNS_GPU_AUX

ISNS_P12VS0_GPUCORE

SNS_P12VS0_CPUCORE_P

SNS_P12VS0_CPUCORE_N

=PP3V3_S0_SENSE

SNS_P12VS0_FBVDDQ_N

SNS_P12VS0_FBVDDQ_P

=PP12V_S0_SNS_FBVDDQ_R

=PP12V_S0_SNS_FBVDDQ_R

SNS_P12VS0_GPUA_P

SNS_P12VS0_GPUA_N

=PP5V_S0_ISENSE

=PPGPUCORE_S0_SNS

PP12V_S0_SNS_GPUCORE

=PPVCCGT_S0_SNS_CPU

GND_SMC_AVSS

SNS_VCCIO_P

ISNS_CPU_FB_R

SYNC_DATE=09/10/2014SYNC_MASTER=BRANCH_JERRYCHOW

SENSORS: I and V Sense

2

1

0201

0.22UF

20%

C5465

X5R

6.3V

R5465

1

1%

U5000.A6:10mm

2

201

4.53K

1/20W

MF

CERM-X5R

2

1

0201

C5425

10%

6.3V

0.1UF

R5425

1/20W

1 2

201

1K

U5000.F1:10mm

MF

1%

R5495

MF-LF

U5000.B6:10mm

4.53K

2

1% 1/16W

402

1

C5495

20%

6.3V

X5R

0.22UF

0201

1

2

C5485

X5R

6.3V

0201

2

20%

0.22UF

1

R5485

4.53K

U5000.A4:10mm

1/16W

2

402

MF-LF

1

1%

1/20W

1%

MF

15K

1 2

201

R5494

1/20W

1%

MF

15K

1 2

201

R5484

R5464

201

15K

MF

1%

1/20W

21

CRITICAL

INA214_SC70_INA214

SC70

INA214

U5420

2

5

4

6

1

3

0612

CRITICAL

U5420.5:20mm

1%

1W

4 3

2 1

MF-2

0.001

R5420

2

C5420

0201

X5R

6.3V

1

0.22UF

20%

21

R5421

U5000.F2:10mm

402MF-LF

1/16W1%

18.2K

2

1

R5422

MF-LF

1/16W

402

1%

6.04K

45

0.22UF

2

1

C5422

X5R

0201

6.3V

20%

45

89

21

R5493

10K

402

MF-LF

1/16W

1%

10K

21

R5492

MF-LF

1/16W1%

402

X7R-CERM

0.01UF

2

1

0402

16V20%

C5490

U5490

CRITICAL

5

2

4

1

3

SC70-5

OPA348

U7000.28:10mm

61

45

21

1%

1/16W

MF-LF

402

R5483

10K

21

R5482

402

MF-LF

1%

10K

1/16W

16V

0402

1

2

20%

C5480

0.01UF

X7R-CERM

2

1

3

U5480

5

4

CRITICAL

SC70-5

U7000.2:10mm

OPA348

61

R5481

1%
MF-LF

4.53K

402

1/16W

2

U5000.B4:10mm

1

45

6.3V

0.22UF

20%

0201

X5R

C5481

1

2

45

CRITICAL

0612

1W

1%

0.001

MF-2

U5430.5:20mm

1 2
3 4

R5430

C5415

6.3V

2

1

20%

0.22UF

X5R 0201

2

1

C5455

0201

10%

0.1UF

6.3V

CERM-X5R

21

R5446

0

1/20W

GPU_AM_EM

5%

0201

MF

U5440.4:6MM

GPU_NEPT

1%

20K

MF 1/20W

201

R5444

1 2

U5440.4:6MM

4

INA214_SC70_INA214

5

INA214

3

1

6

2

U5450

SC70

CRITICAL

CRITICAL

U5410

INA214

3

1

6

4

5

2

SC70

INA214_SC70_INA214

CRITICAL

INA210_SC70_INA210

U5470

6

3

14

5

2

SC70

INA210

0201

2

6.3V

X5R

20%

0.22UF

C5470

1

0612-5

1 2
3 4

CRITICAL

0.005

1%

1WMF

U5470.5:20mm

R5470

89

X5R

0201

6.3V

20%

0.22UF

C5472

1

2

1

402

MF-LF

4.53K

1%

1/16W

R5472

2

U5000.G2:10mm

45

2

1

201

5%

20K

1/20W
MF

R5406

1

MF

5%

201

1/20W

20K

2

R5436

GPU_NEPT

2

1

R5443

10K

1%

MF

1/20W

201

82

21

R5442

GPU_NEPT

1%

10K

1/20W

201

MF

2

0402

X7R-CERM

16V

20%

GPU_NEPT

C5440

1

0.01UF

0.1UF

0201

10%

6.3V

CERM-X5R

C5445

U5000.C2:10mm

2

1

1/20W

R5445

1K

201

MF

1%

U5000.C2:10MM

21

U5000.C1:10mm

R5441

MF

4.53K

2

1/20W

1

1%

201

2

X5R

C5441

0.22UF

6.3V

1

20%

0201

45

45

4

U5440

5

1

3

GPU_NEPT

OPA348
SC70-5

2

CRITICAL

RA117.1:10MM

C5430

0201

X5R

6.3V

20%

0.22UF

1

2

89

4.53K

1%

1/20W

MF

201

R5435

U5000.B5:10mm

1 2

C5435

0201

X5R

6.3V

0.22UF

20%

2

1

45

4

INA210

CRITICAL

INA210_SC70_INA210

SC70

U5430

2

5

6

1

3

U5410.5:20mm

CRITICAL

1%

1W

MF-2

0612

0.001

R5410

1 2
3 4

INA214_SC70_INA214

CRITICAL

3

1

6

4

5

2

U5400

SC70

INA214

89

1

0.005

CRITICAL

U5450.5:20mm

43

2

0612-5

R5450

MF

1%

1W

21

R5455

1K

1%

MF-LF

1/16W

402

U5000.A6:10mm

C5450

0201

X5R

6.3V

2

1

20%

0.22UF

89

45

6.3V
0201X5R

2

1

C5410

0.22UF

20%

U5000.G1:10mm

R5415

21

402

MF-LF

1/16W

1%

4.53K

45

R5461

U5000.B3:10mm

402

4.53K

1% 1/16W

MF-LF

1 2

C5461

20%

X5R

0201

0.22UF

6.3V

1

2

45

61

45

1/16W

402

1%

MF-LF

1 2

10K

R5463

1/16W

MF-LF

R5462

1%

1 2

10K

402

C5460

X7R-CERM

0.01UF

16V

0402

20%

1

2

U7000.14:12mm

1

5

SC70-5

U5460

CRITICAL

OPA348

3

4

2

2

1

R5402

U5000.E2:10mm

402 MF-LF

1/16W

1%

6.04K

0.001

43

21

R5400

U5400.5:20mm

0612

1W

1%

MF-2

CRITICAL

2

1

C5400

0.22UF

20%

0201

6.3V

X5R

21

R5405

U5000.E1:10mm

1K

MF-LF

1/16W1%

402

89

21

MF-LF

18.2K

402

1/16W

1%

R5401

0201

CERM-X5R

6.3V

2

1

C5405

0.1UF

10%

45

2

1

C5402

0201

6.3V

0.22UF

20%
X5R

45

49 48 45 44

49 48 45 44

89 48

89

49 48 45 44

49 48 45 44

89

49 48 45 44

89 50

49 48 34

89 50 49 48 34

49 48 45 44

89

49

48 45 44

89

89 50

49 48 34

89 48

49 48 45 44

49 48 45 44

49 48 45 44

89 48

89

49 48 45 44

89

49 48 45 44

49 48 45 44

49 48 45 44

89

89 50 49 48 34

89 50 49 48 34

89 48

89 48

89 48

89

89

49 48 45 44

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND

V+

REFIN+

IN-

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

OUT

IN-

IN+ REF

V+

OUT

OUT

IN

OUT

OUT

OUT

OUT

GND

OUT

IN-

IN+ REF

V+

GND

V+

REFIN+

IN-

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

www.laptoprepairsecrets.com

Range: 0-8.25A

Range: 0-13.2A

VDDQ S3 (VC0M=VM0R, IC0M:ADC9)

HDD S0 (VH05=5V, IH05:ADC19)

VDDQ lowside sense for SO-DIMM modules

353S2216

353S2073
Gain: 200 V/V
Range: 0-3.3A

Gain: 200 V/V
Range: 0-1.65A

353S3597

GPU_VDDCI S0 (VG0I:ADC14 /IG0I: ADC15)

Gain: 500 V/V

353S2073

I/V-sense for HDD 5V

Gain: 200 V/V

353S3597

Gain: 500 V/V

353S2216

Range: 0-13.2A

SSD S4 (VR1R:ADC20 / IH1R:ADC21)

I-SENSE FOR SSD / V-SENSE FOR PPSSD_S4)

HDD 12V CURRENT SENSE

VDDQ lowside sense for SO-DIMM modules

VDDQ S3 (VM0R:ADC22/ IM0R:ADC23)

Current Sensing via RA500 : 0.5_mOHM

RANGE : 0-15A

GAIN : 200 V/V

PP12V_S0_HDD (VH02=VD20, IH02:ADC18)

49 OF 93

55 OF 121

0.24.0

051-00673

GND_SMC_AVSS

ISNS_GPU_VDDCI

GND_SMC_AVSS

ISNS_SSD_S4

=PPHDD_S0_SNS_R

SNS_HDD_P

SNS_HDD_N

PP12V_S0_HDD_SNS

SNS_P12VS0_HDD_P

=PP3V3_S0_SENSE

ISNS_12V_HDD_R

ISNS_P12VS0_HDD

GND_SMC_AVSS

ISNS_HDDS0

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_P1V35S0

ISNS_VDDQS3_DDR

VSNS_VDDQS3_DDR

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_VDDQS3_DDR_R

GPU_ISNS_VDDCI_P

P3V3S0_U5510

VDDCI_I2V

PPHDD_S0_SNS

=PP12V_S0_HDD_SNS_R

ISNS_HDDS0_R

VSNS_SSD_S4

ISNS_SSDS4_R

GND_SMC_AVSS

GND_SMC_AVSS

SNS_VDDQS3_DDR_P

SNS_SSD_P

PPVSSD_S4_REG_SNS

SNS_SSD_N

=PPVSSD_S4_REG_SNS_R

SNS_P12VS0_HDD_N

ISNS_P1V35S0_R

SNS_P1V35S0_N

PP1V35_S3_SNS

=PP3V3_S0_SENSE

SNS_P1V35S0_P

SNS_VDDQS3_DDR_N

=PPVDDQ_S3_SNS_DDR_R

=PP3V3_S0_SENSE

PPVDDQ_S3_SNS_DDR

=PP1V35_S3_SNS_R

VSNS_GPU_VDDCI

=PP3V3_S0_GPU

GPU_ISNS_VDDCI_N

SSD:N2 C5525,C5526117S0201 RES,0 OHM,201

SSD:YC5525,C55262132S0304 CAP,0.22UF,201

SYNC_MASTER=BRANCH_JERRYCHOW SYNC_DATE=09/10/2014

SENSORS: I and V Sense(Continued)

89

1 2
3 41WCRITICAL

SSD:Y

R5520

0.002

1%

TFT

0612

U5520.A1:6mm

2

1

X5R

6.3V

20%

0201

0.22UF

C5530

U5530

SC70

INA211

CRITICAL

1

6

4

5

2

3

INA210_SC70_INA211

CRITICAL

R5530

1%

1W

MF

0.0005

0612-2

1 2
3 4

U5530.5:20mm

2

R5536

MF

20K

5%

1

1/20W

201

21

R5535

201

4.53K

MF

U5000.A5:10mm

1%

1/20W

0.22UF

2

1

C5535

X5R
0201

6.3V

20%

45

89

U5560.5:20mm

MF 1W

1%

0.005

CRITICAL

43

21

0612-5

R5560

3

1

6

4

5

2

CRITICAL

SC70

INA210_SC70_INA210

U5560

INA210

2

1

C5560

X5R

6.3V

0.22UF

20%

0201

B2A1

A2

B1

WCSP-4

CRITICAL

INA216A4YFFX

U5550

21

R5561

MF-LF

1%

402

1/16W

4.53K

U5000.H1:10mm

89

K

A

DZ5550

CDZ3.0B

SM

I734

43

21

R5550

0.010

1/4WMF

1%

0805-2

CRITICAL

U5550.A2:20mm

89

21

R5553

U5000.H2:10mm

1/16W

1%

MF-LF

402

4.53K

2

1

C5561

X5R 0201

20%

0.22UF

6.3V

2

1

0201

20%

0.22UF

6.3V
X5R

C5553

45

45

U5510

3

1

6

4

5

2

INA210_SC70_INA210

INA210

SC70

CRITICAL

2

1

C5513

0201X5R

6.3V

20%

0.22UF

21

R5513

4.53K

1%

1/20W

MF

201

U5000.B1:12.7mm

C5512

2

1

X5R

0.22UF

20%

6.3V
0201

U5000.B2:12.7mm

21

R5512

NO_XNET_CONNECTION=1

1%

1/20W

MF

4.53K

201

45

86

86

201

21

R5510

2.2

MF

5%

1/20W

0201

2

1

C5510

10%

0.1UF

6.3V

CERM-X5R

45

2

1

R5546

201

5%

20K

1/20W
MF

0.22UF

20%

6.3V
X5R

OMIT_TABLE

C5526

1

0201

2

2

SSD:Y

1/20W

MF

1%

1

U5000.A7:10mm

201

4.53K

R5526

45

B2

A2

A1

B1

WCSP-4

CRITICAL

U5520

INA216A4YFFX

INA216_WCSP_4_INA216A4YFFX

SSD:Y

2

C5525

0201

1

OMIT_TABLE

X5R

6.3V

20%

0.22UF

1

1%
MF

2

201

SSD:Y

R5525

4.53K

1/20W

U5000.B7:12.7mm

45

1%

MF

1W

0.0005

CRITICAL

R5540

U5540.5:20mm

0612-2

1 2
3

4

3

1

6

4

5

2

SC70

INA210_SC70_INA211

INA211

U5540

CRITICAL

2

1

0201

6.3V
X5R

20%

0.22UF

C5540

21

R5541

4.53K

1%

1/20W

MF

201

U5000.B8:10mm

89

21

R5545

U5000.A8:10mm

1%

MF

4.53K

1/20W

201

2

1

C5545

0.22UF

20%

0201

6.3V
X5R

45

2

1

C5541

20% 6.3V
X5R 0201

0.22UF

45

49 48 45 44

49 48 45 44

89

89 50

49 48 34

49 48 45 44

49 48 45 44

49 48 45 44

49 48 45 44

49 48 45 44

89

49 48 45 44

49 48 45 44

89

89 50 49 48 34

89

89 50 49 48 34

89

89 88 87 86 81 80

TABLE_5_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

GND

OUT

IN-

IN+ REF

V+

OUT

OUT

GND

OUT

IN-

IN+ REF

V+

OUT

IN-

IN+

GND

OUT

OUT

OUT

OUT

GND

OUT

IN-

IN+ REF

V+

OUT

IN

IN

OUT

OUT

OUT

IN-

IN+

GND

OUT

GND

OUT

IN-

IN+ REF

V+

OUT

OUT

OUT

www.laptoprepairsecrets.com

EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93

SO-DIMM Proximity 4

Temperature Sensor T1 EMC1414: Near PSU Conn

SO-DIMM Prox 3 (TM2p)

SO-DIMM Prox 1 (TM0p)

SO-DIMM Proximity 1

Set trip point to 125 C.

RADAR 15366048

MLB PROX 1 (TM1P)

SoDIMM Prox 4 (TM3p)

SoDIMM Prox 2 (TM1p)

BLC PROX (Tb0p)

GPU Prox (TG0p)

Ambient (TA0p)

SNS T2: TEMP SENSOR IC

GPU Proximity

Ambient

NEED TO FIND LOCATION

BLC Proximity

SO-DIMM Proximity 3

SO-DIMM Proximity 2

I2C Address (EMC1414-1):

0x99 (Read)

0x98 (Write)

Note:

MLB PROX 0 (Tm0p)

will be used as MLB sensor.

Internal sensor of the EMC 1414

MLB Proximity

AC/DC (Tp2h)

MLB PROX 2 (Tm2p)

CPU Prox (TC0p)

CPU Proximity

AC/DC

Via connector to diode inside PSU

TEMP SENSOR T2 EMC1428: NEAR GPU VR

Make sure these caps are OK with U5600 vendor!

50 OF 93

56 OF 121

0.24.0

051-00673

=SMB_SNS1_SDA

=SMB_SNS1_SCL

=PP3V3_S0_SENSE

=PP3V3_S0_SENSE

=SMB_SNS2_SCL

=SMB_SNS2_SDA

TSNS_2_TRIPSET

TSNS_2_ALERT_L

TSNS_2_ADDR

TSNS_2_7_P

TSNS_2_7_P

TSNS_2_7_N

TSNS_2_7_N

TSNS_2_6_P

TSNS_2_6_P

TSNS_2_6_N

TSNS_2_6_N

TSNS_2_5_P

TSNS_2_5_P

TSNS_2_5_N

TSNS_2_5_N

TSNS_2_4_P

TSNS_2_4_P

TSNS_2_4_N

TSNS_2_4_N

TSNS_2_3_P

TSNS_2_3_N

TSNS_2_3_N

TSNS_2_2_P

TSNS_2_2_P

TSNS_2_2_N

TSNS_2_2_N

TSNS_2_1_P

TSNS_2_1_P

TSNS_2_1_N

TSNS_2_1_N

TSNS_1_ALERT_L

TSNS_1_2_P

MAKE_BASE=TRUE

TSNS_1_2_P

MAKE_BASE=TRUE

TSNS_1_2_N

TSNS_1_2_N

TSNS_1_1_P

TSNS_1_1_P

TSNS_1_1_N

TSNS_1_1_N

SNS_ACDC_P
SNS_ACDC_N

TSNS_1_3_N

TSNS_1_3_N

TSNS_1_3_P

TSNS_1_3_P

TSNS_2_3_P

SYNC_DATE=09/10/2014SYNC_MASTER=BRANCH_JERRYCHOW

SENSORS: Temperature Sensors

ALL372S0185372S0186 Alternate Temp Diode

NO_XNET_CONNECTION=1

Q5685.3:2MM

50V

+/-0.1PF

2.2PF

C0G-CERM

0402

C5685

1

2

NO_XNET_CONNECTION=1

50V

Q5680.3:2MM

2.2PF

+/-0.1PF
C0G-CERM 0402

C5680

1

2

NO_XNET_CONNECTION=1

C0G-CERM

Q5675.3:2MM

2.2PF

+/-0.1PF

0402

50V

C5675

1

2

NO_XNET_CONNECTION=1

2.2PF

Q5670.3:2MM

+/-0.1PF 50V

C0G-CERM

0402

C5670

1

2

NO_XNET_CONNECTION=1

0201

C0G-CERM

25V

2.2PF

+/-0.1PF

Q5605.3:2MM

C5605

1

2

2.2PF

+/-0.1PF
25V

Q5650.3:2MM

C0G-CERM

0201

C5650

1

2

Q5655.3:2MM

+/-0.1PF

2.2PF

25V

C0G-CERM

0201

C5655

1

2

+/-0.1PF

2.2PF

Q5660.3:2MM

25V

C0G-CERM

0201

C5660

1

2

PLACEMENT_NOTE=PLACE Q5604 UNDER CPU

DFN1006H4-3

BC846BLP

Q5604

1

3

2

PLACEMENT_NOTE=PLACE Q5660 NEAR BLC VR

DFN1006H4-3

BC846BLP

Q5660

1

3

2

PLACEMENT_NOTE=PLACE Q5655 NEAR BOTTOM OF BOARD

DFN1006H4-3

BC846BLP

Q5655

1

3

2

PLACEMENT_NOTE=PLACE Q5685 NEAR SO-DIMM CONNECTORS (BOTTOM RIGHT)

BC846BLP

DFN1006H4-3

Q5685

1

3

2

PLACEMENT_NOTE=PLACE Q5680 NEAR SO-DIMM CONNECTORS (BOTTOM LEFT)

BC846BLP

DFN1006H4-3

Q5680

1

3

2

PLACEMENT_NOTE=PLACE Q5675 NEAR SO-DIMM CONNECTORS (TOP RIGHT)

BC846BLP

DFN1006H4-3

Q5675

1

3

2

PLACEMENT_NOTE=PLACE Q5650 NEAR GPU AND GDDR5

DFN1006H4-3

BC846BLP

Q5650

1

3

2

PLACEMENT_NOTE=PLACE Q5670 NEAR SO-DIMM CONNECTORS (TOP LEFT)

BC846BLP

DFN1006H4-3

Q5670

1

3

2

SM

OMIT

SHORT_SM_BASE

XW5600

1

2

SM

OMIT

SHORT_SM_BASE

XW5601

1

2

NO_XNET_CONNECTION=1

U5650.15:10MM

0.0022UF

10%

50V

CERM

402

C5652

1 2

OMIT

SM

SHORT_SM_BASE

XW5602

1

2

NO_XNET_CONNECTION=1

0.0022UF

U5650.10:10MM

10%

50V

CERM

402

C5654

1 2

OMIT

SM

SHORT_SM_BASE

XW5603

1

2

OMIT

SM

SHORT_SM_BASE

XW5604

1

2

SM

OMIT

SHORT_SM_BASE

XW5605

1

2

NO_XNET_CONNECTION=1

0.0022UF

U5650.10:5MM

10%

50V

CERM

402

C5656

1 2

402-1

X5R

10V

10%

1UF

C5659

1

2

1%

6.81K

1/16W

MF-LF

402

R5650

1

2

47

47

10K

MF-LF

5%

402

1/16W

R5651

1

2

1/16W
MF-LF

20K

5%

402

R5652

1

2

EMC1428-7

CRITICAL

QFN

PLACEMENT_NOTE=PLACE U5650 NEAR GPU VR TO GET GPU VR PROX TEMP

EMC1428_QFN_EMC1428_7

U5650

7

2

4

9

14

1

3

10

15

8

13

12

11

6

17

5

16

60

60

FERR-220-OHM

0402

J6901.4:30MM

L5611

1 2

FERR-220-OHM

0402

J6901.5:30MM

L5610

1 2

PLACEMENT_NOTE=PLACE Q5605 NEAR CPU

DFN1006H4-3

BC846BLP

Q5605

1

3

2

10%

CERM

0.0022UF

L5610.2:10MM

50V

402

C5610

1

2

I655

I654

50V
CER

47PF

NOSTUFF

0402

5%

U5600.4:2MM

C5602

1

2

NOSTUFF

CER

U5600.5:2MM

50V

5%

47PF

0402

C5603

1

2

1UF

402-1

10%
10V
X5R

C5600

1

2

47

47

MF-LF

5%

1/16W

10K

402

R5600

1

2

NO_XNET_CONNECTION=1

402CERM

50V

10%

0.0022UF

C5601

1

2

EMC1414_MSOP10_MSOP_EMC1414_1_AIZL

EMC1414-1-AIZL

MSOP

J6901.4:30MM

PLACEMENT_NOTE=PLACE U5600 NEAR PSU CONNECTOR

U5600

83

5

2

4

6

10

9

7

1

89 50 49 48 34

89 50 49 48 34

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_ALT_ITEM

IN

BI

ALERT*

SYS_SHND*

SMCLK

SMDATA

TRIP/SET

NC

GND THRM_PAD

DP1
DN1

DP4/DN5

DN2/DP3

DP2/DN3

DN4/DP5

DN6/DP7

DP6/DN7

VDD

IN

IN

NC

IN

BI

GND

DN2/DP3

DP2/DN3

DN1

VDD

SMDATA

SMCLK

DP1

THERM*/ADDR

ALERT*

www.laptoprepairsecrets.com

SEE RADAR:12960082 J16/J17 CONNECT GATE OF FAN PWM FET TO PP3V42_G3H

SMC Fan 0 (System)

Add C6020 1000pF Cap, Change R6020 to 47K -- Radar 11661918 D8 Proto1 Fan Tach instability.

SMC Fan 1 (Unused)

Otherwise, this is simply a pass-FET.

518S0730

Note:

FET input.

The circuit for the PWM input to

level-shifter to protect the SMC.

This resembles an open-drain if

the fan acts as a non-inverting

when the SMC PWM goes low and Q6010

5V/12V inside the fan, otherwise

It is assumed there is a pull-up to

when Q6010 is on.

GND

Tach

12V DC

turns on, there would be 5V/12V
present on the SMC pin! Then by

at common and the SMC sinks current

definition, the drain of Q6010 is

there is a pull-up, going to a Hi-Z

See RADAR: 10565825- D7: Need scematic and PCB file of fan(All Vendors).

51 OF 93

VOLTAGE=12V
MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.5000

MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.5000

60 OF 121

0.24.0

051-00673

=PP3V3_G3H_SMC

SMC_FAN_0_TACH

PP12V_S0_FAN_0_FILT

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

FAN_0_TACH_FILT

FAN_0_TACH_FET

FAN_0_PWM_FILT

SMC_FAN_1_TACH

SMC_FAN_1_CTL

=PP3V3_S0_FAN

=PP12V_S0_FAN

FAN_0_PWM_FET

=PP3V3_S0_FAN

=PP3V3_G3H_SMC

SMC_FAN_0_CTL

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

FAN: System Fan

0402

100PF

50V

5%

C0G

C6021

1

2

C0G

50V

0402

5%

100PF

C6010

1

2

10%

X7R-1

1000PF

16V

0201

PLACE_NEAR=U5000.L13:5MM

C6020

1

2

16V

1206

4.7UF

10%

X7R-CERM

C6000

1

2

1/16W

402

47K

MF-LF

5%

R6020

1 2

BAS316DG

SOD323-SM

D6020

A

K

SOD

CRITICAL

Q6010

3

1

2

MF-LF

1/16W

5%

10K

402

R6010

1

2

44

5%
1/16W

47K

MF-LF
402

R6026

1

2

FERR-220-OHM

0402

CRITICAL

L6010

1 2

CRITICAL

FERR-220-OHM

0402

L6021

1 2

44

44

M-RT-SM

53780-8604

CRITICAL

J6000

5

6

1

2

3

4

44

20%
16V
X7R-CERM

0.01UF

0402

C6001

1

2

CRITICAL

0603

220-OHM-1.4A

L6000

1 2

89 51 45 44 89 51

89

89 51

89 51 45 44

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

D

S

G

OUT

OUT

IN

IN

www.laptoprepairsecrets.com

APPLE P/N 353S2456

4.5V POWER SUPPLY FOR CODEC

VD MUST BE LESS THAN OR EQUAL TO VL_HD

APPLE P/N 353S2592

AUDIO CODEC

DMICS 1 & 2

NC

DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA

SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS

DAC2/3 FSOUTPUTSE= 1.34VRMS

PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5

PLACE TP FOR ALL HDA SIGNALS NEAR CODEC

MAC SPKR AMP CNTRL

HP AMP CNTRL TWEETERS

WIN SPKR AMP CNTRL

WOOFERS

HP AMP/LINE OUT RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT

NC

NC

PLACE C6100 AS CLOSE TO PIN 9 AS POSSIBLE

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

DIFF FSINPUT= 2.45VRMS

NC

NC
NC

NC

NC
NC

52 OF 93

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000
VOLTAGE=5V

MIN_NECK_WIDTH=0.1000MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000MIN_LINE_WIDTH=0.1000

NO_TEST=1

NO_TEST=1
NO_TEST=1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500
VOLTAGE=4.5V

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000
VOLTAGE=5V

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
VOLTAGE=0V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

61 OF 121

0.24.0

051-00673

DP_INT_SPDIF_AUDIO

=PP1V8_S0_AUD_DIG

PP1V5_S0_AUD_DIG

GND_AUDIO_CODEC

TP_AUD_GPIO_1

PP1V5_S0_AUD_DIG

HDA_BIT_CLK

GND_AUDIO_CODEC

AUD_SENSE_A

AUD_GPIO_3

CS4206_FP

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

CS4206_FN

AUD_DMIC_SDA1

HDA_SDOUT

HDA_SYNC

CS4206_FLYC

AUD_LO1_L_P

GND_AUDIO_CODEC

Q6171_P_S

CS4206_FLYN

CS4206_FLYP

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

GND_AUDIO_HPAMP

PP5V_AUDIO_HPAMP

AUD_SPDIF_CHIP

=PP5V_S0_AUDIO

TP_AUD_HP_L
TP_AUD_HP_R

AUD_LI_P_L

AUD_LI_P_R

AUD_LI_COM

AUD_MIC_INP_R
AUD_MIC_INN_R

CS4206_VCOM

AUD_LO1_R_N

AUD_LO2_L_P
AUD_LO2_L_N

AUD_DMIC_CLK

Q6170_N_S

AUD_CODEC_MICBIAS

AUD_LO2_R_N

AUD_LO1_R_P

AUD_LO2_R_P

AUD_SPDIF_OUT

AUD_SDI_RHDA_SDIN0

=PP3V3_S0_AUDIO

Q6171_P_G

Q6171_N_G

Q6171_N_S

Q6170_N_G

Q6170_P_G

Q6170_P_S

AUD_MIC_INL_N

AUD_MIC_INL_P

CS4206_DMIC_SCL

PP5V_AUDIO_HPAMP

VBIAS_DAC

PP4V5_AUDIO_ANALOG4V5_REG_IN

4V5_REG_EN 4V5_NR

GND_AUDIO_DMIC

CS4206_VREF_ADC

AUD_LO1_L_N

CS4206_HPREF

GND_AUDIO_CODEC

HDA_RST_L

AUD_CODEC_MICBIAS

PP4V5_AUDIO_ANALOG

AUD_GPIO_2

SYNC_DATE=03/07/2013SYNC_MASTER=J17_DIRK

AUDIO: CODEC/REGULATORS

54

58 56 52

53 52

59 58

C6124

10%

402-1

X5R

1UF

10V

1

2

FERR-220-OHM

0402

L6111

1 2

FERR-220-OHM

0402

L6110

1 2

TPS71745

SON

CRITICAL

VR6101

4

2

6

5

3

1

C6122

1UF

10V

402-1

X5R

10%

2

1

SM

XW6111

1

2

5%

402

1/16W

0

MF-LF

R6120

1 2

11

89 59

89 58 55 54 52 38

53 52

89 58 55 54 52 38

58 56 52

11

5%
1/16W

0

MF-LF
402

R6105

1

2

59 54 53

10%

X5R

1UF

10V

402-1

C6105

1

2

11

10UF

CASE-B2-SM

20%
16V
POLY-TANT

C6103

1

2

59 54 53

59 55 53

59 55 53

59 54

59 54

59 55

59 55

40

59 56

59 56

CASE-B2-SM

POLY-TANT

20%
16V

CRITICAL

10UF

C6114

1

2

11

TANT

10%
20V

1UF

CRITICAL

CASE-P3-HF

C6113

1

2

10UF

C6108

2

POLY-TANT

CASE-B2-SM

20%

1

16V

1

6.3V

402-LF

20%

CERM

2.2UF

2

C6110

402-LF

6.3V

20%

2.2UF

C6109

1

2

CERM

1/16W

402

R6100

1

2

MF-LF

1%

2.67K

58 56 52

C6112

2.2UF

20%

6.3V

402-LF

CERM

1

2

11

20%

6.3V
CERM

2.2UF

402-LF

C6111

1

2

10%
10V

1UF

2

1

402-1

C6190

X5R

PLACE_NEAR=VR6102.1:12.5mm

TPS73115

4

1

2

5

SOT23-5

PLACE_NEAR=U6101.9:12.5mm

VR6102

3

5%
1/16W
MF-LF

22

402

R6104

1 2

MF-LF

R6103

1/16W

1%

402

100K

1

2

MF-LF

1/16W

402

100K

1%

R6111

1

2

100K

402

MF-LF

1/16W

1%

R6110

1

2

MF-LF

100K

402

1%

1/16W

R6109

1

2

402

100K

MF-LF

1%

1/16W

R6108

1

2

R6107

402

1%

100K

MF-LF

1/16W

1

2

402

1%

100K

MF-LF

1/16W

R6106

1

2

10%

X5R

0.47UF

0402

10V

C6104

1

2

10%

X5R

0.47UF

0402

10V

C6115

1

2

10%

X5R

10V

0.47UF

0402

C6106

1

2

5%

MF-LF

402

1/16W

22

R6101

1 2

10%

X5R

0.47UF

10V

C6102

1

2

0402

PLACE_NEAR=U6101.9:12.5mm

C6100

0.47UF

10V

0402

10%

X5R

1

2

X7R-CERM

10%

0.1UF

0402

16V

C6123

1

2

CRITICAL

SOT563

DEVEL_AUDIO

DMC2400UV

Q6171

6

2

1

MF-LF

5%

1/16W

402

22

R6102

1 2

MF-LF

1/16W

402

0

5%

DEVEL_AUDIO

R6173

1

2

R6172

0

402

MF-LF

1/16W

5%

DEVEL_AUDIO

1

2

CRITICAL

Q6171

DMC2400UV

DEVEL_AUDIO

SOT563

3

5

4

DEVEL_AUDIO

DMC2400UV

CRITICAL

SOT563

Q6170

6

2

1

DEVEL_AUDIO

5%
1/16W
MF-LF
402

0

R6170

1

2

DEVEL_AUDIO

DMC2400UV

CRITICAL

SOT563

Q6170

3

5

4

38

SM

XW6100

1

2

10UF

CRITICAL

10V
X5R-CERM
0402-1

20%

C6107

1

2

DEVEL_AUDIO

5%

0

402

1/16W
MF-LF

R6171

1

2

SM

XW6110

1

2

SOD-523

A K

D6100

BAT54XV2T1

38

54 52

38

53

20%

X5R-1

4.7UF

C6101

402

4V

1

2

PLACE_NEAR=U6101.9:12.5mm

48

11

9

24

CRITICAL

U6101

CS4206B

QFN

26

6

7

4

43
42

45

2

12

14
15

38
40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

19

8
5

13

47

10

49

25

46

29

28

41

44

3

1

27

54 52

56

89 52

59 58 56 52

52

59 58 56 52

59 58 56 52

59 58 56 52

59 58 56 52

53

59 58 56 52

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

IN

GND

EN

IN

NC

NR/FB

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

NC

GND

OUT

ENINNR/FB

N-CHN

G

S

D

NC

NC

P-CHN

S

D

G

N-CHN

G

S

D

P-CHN

S

D

G

OUT

NC

NC

OUT

IN

OUT

OUT

/SPDIF_OUT2

LINEOUT_R2+

LINEOUT_L2-

LINEOUT_L2+

VREF+_ADC

MICIN_R+

MICIN_R-

BITCLK

VL_IF

SDO

SDI

HPOUT_L

DMIC_SCL

DGND

SYNC

MICBIAS

MICIN_L-

MICIN_L+

LINEIN_L+

LINEIN_R+

VA

AGND

VCOM

HPREF

HPOUT_R

VA_HP

THRM_PAD

LINEOUT_L1+

SPDIF_IN

FLYN

FLYC

LINEIN_C-

SPDIF_OUT

LINEOUT_R2-

LINEOUT_R1+

LINEOUT_R1-

VHP_FILT-

GPIO3

VD VA_REF

FLYP

VBIAS_DAC

LINEOUT_L1-

RESET*

GPIO2

VHP_FILT+

GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2

SENSE_A

VL_HD

OUT

OUT

www.laptoprepairsecrets.com

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

NC NC

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

53 OF 93

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.5000
VOLTAGE=0V

62 OF 121

0.24.0

051-00673

GND_AUDIO_HPAMP

MAX97220_OUTR

MAX97220_BIAS

MAX97220_OUTL

MAX97220_C1N

MAX97220_C1P

Q6252_GATE

GND_AUDIO_HPAMP

MAX97220_INR_N

MUTE_CONTROL

MAX97220_INR_P

MAX97220_OUTL_ZOBEL

MAX97220_SHDN_LAUD_GPIO_2

AUD_LO1_L_C_N

AUD_LO1_R_C_P

AUD_LO1_L_P

AUD_LO1_L_N

MAX97220_INL_P

AUD_LO1_R_P

GND_AUDIO_HPAMP

MAX97220_INL_N

PP5V_AUDIO_HPAMP

PP5V_AUDIO_HPAMP

MAX97220_SHDN_L

MAX97220_OUTR_ZOBEL

AUD_LO1_R_N

MAX97220_INL_N

MUTE_SWITCH

GND_AUDIO_HPAMP

MAX97220_SHDN_L

AUD_LO1_L_C_P

MAX97220_INR_NAUD_LO1_R_C_N

MAX97220_INR_P

AUD_HP_PORT_REF

MAX97220_INL_P

MAX97220_OUTL

MAX97220_OUTR

MAX97220_PVSS

SYNC_DATE=11/18/2013

AUDIO: HEADPHONE AMP

SYNC_MASTER=J78_DAVID

NO_XNET_CONNECTION=1

5%

0402

C0G

50V

100PF

C6274

1

2

NO_XNET_CONNECTION=1

C0G

50V

5%

100PF

0402

C6272

1 2

NO_XNET_CONNECTION=1

C0G

5%
50V

100PF

0402

C6264

1

2

NO_XNET_CONNECTION=1

100PF

C0G

50V

5%

0402

C6262

1 2

NOSTUFF

1/16W
MF-LF

100K

5%

402

R6259

1

2

NOSTUFF

100K

1/16W
MF-LF

5%

402

R6258

1

2

NOSTUFF

100K

5%
1/16W
MF-LF

402

R6257

1

2

NOSTUFF

SOT563

SSM6N15AFEAP

CRITICAL

Q6252

3

5

4

NOSTUFF

SSM6N15AFEAP

SOT563

CRITICAL

Q6252

6

2

1

NOSTUFF

DMN2015UFDE

UDFN

Q6250

1

3

47

UDFN

DMN2015UFDE

NOSTUFF

Q6251

1

3

4 7

53 52

53 52

2.2UF

20%

X5R-CERM

25V

0402-1

C6255

1

2

2.2UF

X5R-CERM
0402-1

20%
25V

C6254

1

2

MF-LF

1/16W

26.1K

1%

402

R6271

1 2

1%

26.1K

1/16W
MF-LF

402

R6273

1 2

26.1K

1/16W

1%

MF-LF

402

R6263

1 2

1%

26.1K

1/16W

402

MF-LF

R6261

1 2

X7R-CERM

0.1UF

10%

0402

16V

C6258

1

2

X7R-CERM

16V

0.1UF

10%

0402

C6257

1

2

10%

0.1UF

0402

X7R-CERM

16V

C6250

1

2

NO_XNET_CONNECTION=1

402

MF-LF

1/16W

1%

19.6K

R6262

1 2

NO_XNET_CONNECTION=1

MF-LF

1%

1/16W

19.6K

402

R6264

1

2

NO_XNET_CONNECTION=1

1%

MF-LF

1/16W

402

19.6K

R6274

1

2

NO_XNET_CONNECTION=1

1/16W
MF-LF

1%

402

19.6K

R6272

1 2

NOSTUFF

0

5%

1/16W
MF-LF

402

R6256

1

2

NOSTUFF

0

5%
1/16W
MF-LF

402

R6255

1 2

402

MF-LF

2.0K

1/16W

5%

R6254

1

2

2.0K

1/16W
MF-LF

402

5%

R6253

1

2

52

MF-LF

100K

1/16W

402

5%

R6250

1

2

FERR-220-OHM

0402

L6250

1 2

X5R-CERM
0402-1

10V

20%

10UF

C6251

1

2

402

33

1/16W
MF-LF

5%

R6251

1

2

MF-LF
402

33

1/16W

5%

R6252

1

2

CASE-A

33UF

20%

TANT

CRITICAL

6.3V

C6271

1 2

33UF

CRITICAL

TANT

20%

6.3V

CASE-A

C6273

1 2

CASE-A

20%

33UF

6.3V
TANT

CRITICAL

C6263

1 2

CRITICAL

20%

TANT

6.3V

CASE-A

33UF

C6261

1 2

X5R

1UF

10V

10%

402-1

C6253

1

2

56 53

56 53

56 53

59 53

59 53

56 53

59 53

59 53

59 53

59 53

59 53

59 53

59 54 52

59 54 52

59 55 52

59 55 52

CRITICAL

TQFN

MAX97220AETE

U6250

11

4

2

14
15

8

7

12

10

3

1

5

6

16

13

9

17

402-1

10V

10%

1UF

X5R

C6256

1

2

402-1

10%

X5R

1UF

10V

C6252

1

2

53 52

53 52

53

59

59

53 52

53

53 52

53

59

59

56

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

G S

D

G S

D

S

D

G

S

D

G

NC

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

SHDN*

INR+
INR-

INL+

INL-

SVDD2

C1N

C1P

OUTR

OUTL

BIAS

SVDD

PVDD

THM_PAD

PVSS

SGND

PGND

www.laptoprepairsecrets.com

MAKE LAYOUT MORE LOGICAL

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

SPEAKER AMP GAIN = +12 DB
SPEAKER AMP RIN = 40K NOMINAL
FC_HPF, TWEETERS = ~847 HZ (4700 PF)
FC_HPF, WOOFERS = ~4 HZ (1.0 UF)

WOOFERS & TWEETERS ON UNDER MAC OS

ONLY WOOFERS ON UNDER WINDOWS

EDGE RATE

APPLE P/N 353S3163

LEFT CH SPEAKER AMP

PINS 14 & 15 ARE TEST PINS AND

+9 DB NOSTUFF 0 OHM

OFF NOSTUFF 0 OHM

ON 0 OHM NOSTUFF

CONTROL R6304 R6305

NC

SHOULD BE TIED TO GND

OUTPUT POLARITY FLIP TO

GAIN R6306 R6307

+12 DB NOSTUFF 47 KOHM
+15 DB NOSTUFF NOSTUFF
+18 DB 47 KOHM NOSTUFF
+24 DB 0 OHM NOSTUFF

AUD_RAMP_MONO NET:
HIGH = MONO OPERATION
LOW = STEREO OPERATION

54 OF 93

MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000

VOLTAGE=5V

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000

63 OF 121

0.24.0

051-00673

AUD_LAMP_OUTPR

AUD_LAMP_BOOTRP

AUD_LAMP_OUTNL

AUD_LAMP_OUTNR

AUD_LAMP_OUTPL

AUD_LAMP_BOOTLN

AUD_LAMP_BOOTLP

AUD_LAMP_BOOTRN

AUD_LAMP_AVDD

AUD_LAMP_MONO

=PP12V_S0_AUDIO_SPKRAMP

=PP3V3_S0_AUDIO

AUD_LAMP_LIN_P

AUD_LO1_L_P

AUD_LAMP_LINC_N

AUD_LAMP_LINC_P

AUD_SPKRAMP_WIN_SHDN_L

AUD_LAMP_MONO

AUD_SPKRAMP_MAC_SHDN_L

AUD_LO1_L_N

AUD_LO2_L_P

TP_AUD_LAMP_THERM

AUD_LAMP_EDGE

AUD_LAMP_EDGE

AUD_SPKRAMP_WIN_SHDN_LAUD_GPIO_3

AUD_CODEC_MICBIAS AUD_SPKRAMP_MAC_SHDN_L

AUD_LAMP_GAINAUD_LAMP_LIN_N

AUD_LAMP_RINC_P

AUD_LAMP_RIN_NAUD_LAMP_RINC_N

AUD_LAMP_RIN_P

AUD_LAMP_GAIN

AUD_LO2_L_N

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LWFR_OUT_N

AUD_LAMP_AVDD

AUD_LAMP_OUTNR

AUD_LAMP_OUTPR

SYNC_DATE=11/18/2013

AUDIO: LEFT SPKR AMP

SYNC_MASTER=J78_DAVID

4700PF

0805

NPO-C0G-CERM

50V

5%

C6310

1 2

MF-LF

1/16W

47K

402

5%

R6307

1

2

CRITICAL

20%
16V

220UF

ELEC
SM-CASE-C1-HF

C6307

1

2

20%
16V
ELEC

CRITICAL

SM-CASE-C1-HF

220UF

C6306

1

2

55 54

55 54

FERR-1000-OHM

0402

L6300

1 2

59 52

0402

FERR-1000-OHM

L6301

1 2

FERR-1000-OHM

0402

L6302

1 2

FERR-1000-OHM

0402

L6303

1 2

59 52

59 53 52

59 53 52

0402

FERR-1000-OHM

L6308

1 2

NO_XNET_CONNECTION=1

1000PF

0402

CERM

25V

CRITICAL

5%

C6324

1

2

NO_XNET_CONNECTION=1

0402

CERM

25V

CRITICAL

1000PF

5%

C6323

1

2

55 54

0402

C0G

50V

100PF

NOSTUFF

5%

C6312

1

2MF-LF

100K

1/16W

402

5%

R6301

1

2

55 54

0402

C0G

NOSTUFF

100PF

50V

5%

C6318

1

2MF-LF

1/16W

100K

402

5%

R6309

1

2

52

0

MF-LF

1/16W

402

5%

R6308

1 2

52

0

MF-LF

NOSTUFF

1/16W

402

5%

R6306

1

2

MF-LF

0

1/16W

402

5%

R6303

1

2

1/16W

0

MF-LF
402

5%

R6304

1

2

0

1/16W
MF-LF

NOSTUFF

402

5%

R6305

1

2

SSM3302

LFCSP

CRITICAL

U6300

7

24

6

1

25

30

10

21

12

11

19

20

16

13

18

4
5

2
3

26
27

28
29

313233

383940

343536

37

23

9

22

14
15

17

41

8

10%

603-1

1UF

X5R

25V

C6305

1

2

59 57

59 57

59 57

59 57

10%

X5R

0.1UF

25V

402

C6304

1

2

X5R

10%

1UF

25V

603-1

C6303

1

2

0.1UF

10%

X5R

25V

402

C6302

1

2

NO_XNET_CONNECTION=1

CERM

CRITICAL

0402

25V

1000PF

5%

C6322

1

2

NO_XNET_CONNECTION=1

CRITICAL

CERM
0402

25V

1000PF

5%

C6321

1

2

NO_XNET_CONNECTION=1

1000PF

5%

25V
CERM
0402

CRITICAL

C6320

1

2

NO_XNET_CONNECTION=1

CRITICAL

0402

CERM

25V

1000PF

5%

C6319

1

2

0.22UF

X5R
603

20%
25V

C6313

1 2

X5R
603

20%

0.22UF

25V

C6314

1 2

0.22UF

20%

X5R
603

25V

C6315

1 2

X5R

20%

603

0.22UF

25V

C6316

1 2

X5R
805

10%

10UF

25V

C6301

1

2

10%

X5R
805

10UF

25V

C6300

1

2

89 55

20%
10V

X5R-CERM

2.2UF

402

C6317

1

2

NO_XNET_CONNECTION=1

DLY5ATN111SQ2

CRITICAL

110-OHM-3A

L6307

1 2

34

NO_XNET_CONNECTION=1

CRITICAL

DLY5ATN111SQ2

110-OHM-3A

L6305

1 2

34

10%

X5R

0402

1UF

25V

C6309

1 2

0402

10%

X5R

1UF

25V

C6308

1 2

0805

NPO-C0G-CERM

4700PF

50V

5%

C6311

1 2

54

54

54

54

89 58 55 52 38

59

59

59

54

54

54

54

59

59

59 59

59

54

54

54

54

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

IN

IN

IN

IN

NC

NC

OUT

OUT

IN

IN

INR+

REGEN

VREG/AVDD

PGND

THRM_PAD

PVDD

THERM

NC

AGND

EDGEINL-

GAIN

INL+

BOOTL-

INR-

MONO

OUTR-

OUTL+

BOOTR+

OUTL-

SDNR*

OUTR+

BOOTR-

BOOTL+

TEST

SDNL*

OUT

OUT

OUT

OUT

IN

SYM_VER-1

SYM_VER-1

www.laptoprepairsecrets.com

FC_HPF, WOOFERS = ~4 HZ (1.0 UF)

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

MAKE LAYOUT MORE LOGICAL

OUTPUT POLARITY FLIP TO

SHOULD BE TIED TO GND

PINS 14 & 15 ARE TEST PINS AND

LOW = STEREO OPERATION

ON 0 OHM NOSTUFF

EDGE RATE

APPLE P/N 353S3163

RIGHT CH SPEAKER AMP

NC

+9 DB NOSTUFF 0 OHM

+15 DB NOSTUFF NOSTUFF

+24 DB 0 OHM NOSTUFF

CONTROL R6404 R6405

OFF NOSTUFF 0 OHM

HIGH = MONO OPERATION

AUD_RAMP_MONO NET:

WOOFERS & TWEETERS ON UNDER MAC OS

FC_HPF, TWEETERS = ~847 HZ (4700 PF)

SPEAKER AMP RIN = 40K NOMINAL

SPEAKER AMP GAIN = +12 DB

ONLY WOOFERS ON UNDER WINDOWS

+18 DB 47 KOHM NOSTUFF

+12 DB NOSTUFF 47 KOHM

GAIN R6406 R6407

55 OF 93

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2500

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
VOLTAGE=5V

64 OF 121

0.24.0

051-00673

AUD_RAMP_OUTNR

AUD_RAMP_OUTPR

AUD_RAMP_OUTPL

AUD_RAMP_OUTNL

AUD_RAMP_BOOTLP

AUD_RAMP_BOOTRN

AUD_RAMP_BOOTRP

AUD_RAMP_BOOTLN

AUD_RAMP_AVDD

AUD_SPKR_RTWT_OUT_P

AUD_RAMP_RINC_N AUD_RAMP_RIN_N

AUD_RAMP_RINC_P AUD_RAMP_RIN_P

AUD_RAMP_GAINAUD_RAMP_LINC_N AUD_RAMP_LIN_N

AUD_RAMP_LINC_P

AUD_LO2_R_P

=PP12V_S0_AUDIO_SPKRAMP

AUD_LO2_R_N

AUD_RAMP_EDGE

TP_AUD_RAMP_THERM

AUD_RAMP_EDGE

AUD_LO1_R_N

AUD_LO1_R_P

=PP3V3_S0_AUDIO

AUD_RAMP_MONO

AUD_SPKRAMP_MAC_SHDN_L

AUD_RAMP_MONO

AUD_SPKRAMP_WIN_SHDN_L

AUD_RAMP_GAIN

AUD_RAMP_LIN_P

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_RWFR_OUT_N

AUD_SPKR_RTWT_OUT_N

AUD_RAMP_AVDD

AUD_RAMP_OUTNR

AUD_RAMP_OUTPR

AUDIO: RIGHT SPKR AMP

SYNC_MASTER=J78_DAVID SYNC_DATE=11/18/2013

59 57

59 57

59 57

59 57

59 53 52

59 52

25V

1UF

X5R
603-1

10%

C6405

1

2

25V

1UF

10%

X5R
603-1

C6403

1

2

402

25V

0.1UF

10%

X5R

C6402

1

2

FERR-1000-OHM

0402

L6403

1 2

0402

FERR-1000-OHM

L6402

1 2

FERR-1000-OHM

0402

L6401

1 2

402

25V
X5R

10%

0.1UF

C6404

1

2

NO_XNET_CONNECTION=1

110-OHM-3A

CRITICAL

DLY5ATN111SQ2

L6407

1 2

34

0402

FERR-1000-OHM

L6400

1 2

NO_XNET_CONNECTION=1

CRITICAL

110-OHM-3A

DLY5ATN111SQ2

L6405

1 2

34

25V

1UF

0402

X5R

10%

C6409

1 2

25V

1UF

0402

10%

X5R

C6408

1 2

5%

4700PF

0805

NPO-C0G-CERM

50V

C6411

1 2

5%

NPO-C0G-CERM

4700PF

50V

0805

C6410

1 2

1/16W

5%

402

47K

MF-LF

R6407

1

2

CRITICAL

16V

POLY

SM

470UF

20%

C6406

1

2

NO_XNET_CONNECTION=1
CRITICAL

1000PF

25V

5%

CERM
0402

C6424

1

2

NO_XNET_CONNECTION=1

5%

1000PF

25V

0402

CERM

CRITICAL

C6423

1

2

25V

10UF

805

X5R

10%

C6400

1

2

5%

402

1/16W

NOSTUFF

MF-LF

0

R6406

1

2

5%

402

1/16W

0

MF-LF

R6403

1

2

5%

402

NOSTUFF

MF-LF

1/16W

0

R6405

1

2

5%

402

MF-LF

0

1/16W

R6404

1

2

25V
X5R

10%

805

10UF

C6401

1

2

54

54

402

2.2UF

X5R-CERM

10V

20%

C6417

1

2

CRITICAL

LFCSP

SSM3302

U6400

7

24

6

1

25

30

10

21

12

11

19

20

16

13

18

4
5

2
3

26
27

28
29

313233

383940

343536

37

23

9

22

14
15

17

41

8

X5R

25V

20%

603

0.22UF

C6414

1 2

25V

0.22UF

603

20%

X5R

C6413

1 2

25V

603

X5R

0.22UF

20%

C6416

1 2

59 52

59 53 52

603

0.22UF

25V
X5R

20%

C6415

1 2

NO_XNET_CONNECTION=1

CRITICAL

1000PF

5%

25V

0402

CERM

C6422

1

2

NO_XNET_CONNECTION=1

5%

1000PF

25V

0402

CERM

CRITICAL

C6420

1

2

NO_XNET_CONNECTION=1

5%

1000PF

25V

0402

CERM

CRITICAL

C6419

1

2

NO_XNET_CONNECTION=1

5%

1000PF

25V

0402

CERM

CRITICAL

C6421

1

2

89 54

55

55

55

59 59

59 59

55

59 59

59

55

55

89 58 54 52 38

55

55

55

59

55

55

55

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

IN

IN

SYM_VER-1

SYM_VER-1

NC

NC

IN

IN

INR+

REGEN

VREG/AVDD

PGND

THRM_PAD

PVDD

THERM

NC

AGND

EDGEINL-

GAIN

INL+

BOOTL-

INR-

MONO

OUTR-

OUTL+

BOOTR+

OUTL-

SDNR*

OUTR+

BOOTR-

BOOTL+

TEST

SDNL*

IN

IN

IN

www.laptoprepairsecrets.com

POLARITY

OPPOSIDE

INTENTIONALLY

MIKEY U6551 WRITE 0111 0010 0X72

MIKEY U6551 READ 0111 0011 0X73

I2C ADDRESSES

OFF: INPUT LOOKS LIKE 1M PULL-DOWN TO GND

HDET FUNCTION:

ON: INPUT LOOKS LIKE 1M PULL-UP TO 3V

I2C PULLUPS ON SOUTHBRIDGE PAGE

APN 353S3231WRITE: 0X72 READ: 0X73

MIKEY RECEIVER CKT

(SEE RADAR <RDAR://PROBLEM/6210118>)

NOISE ISSUE SEEN ON EARLY HEADSETS

R/C6750 FILTER TO ADDRESS OUT-OF-BAND

APPLE P/N 518S0687

56 OF 93

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.5000

VOLTAGE=0V

65 OF 121

0.24.0

051-00673

AUD_J1_HP_OUTL

AUD_J1_HP_OUTR

HS_MIC_BIAS

AUD_J1_MIC_BIAS

AUD_J1_PP3V3_S0

AUD_J1_TIPDET1_R

GND_AUDIO_CODEC

MAX97220_OUTR

AUD_HP_PORT_REF

MAX97220_OUTL

AUD_SPDIF_OUT

=I2C_CHS_SCL

GND_AUDIO_CODEC

=I2C_MIKEY_SCL

AUD_MIC_INL_N

AUD_MIC_INL_P

HS_HDET

HS_RX_BP

AUD_HS_MIC_RC_N

AUD_IPHS_SWITCH_EN

=I2C_CHS_SDA

AUD_HS_MIC_P

AUD_HS_MIC_N

AUD_HS_MIC_RC_P

AUD_J1_HP_PORT_REF

=I2C_MIKEY_SDA

=PP3V3_S0_AUDIO_DIG

PP4V5_AUDIO_ANALOG

AUD_J1_MIC_P

AUD_J1_TYPEDET_R

=PP3V3_S4_AUDIO_DIG

AUD_J1_TIPDET2_R

AUD_J1_MIC_N

AUD_I2C_INT_L

GND_AUDIO_CODEC

AUD_HS_MIC_P

AUD_HS_MIC_N

HS_SW_DET

HS_MIC_BIAS

AUD_TYPEDET_R

AUD_TIPDET2_R

AUD_TIPDET1_R

AUD_PORTD_DET_L

AUD_J1_GND_ANALOG

SYNC_DATE=11/18/2013SYNC_MASTER=J78_DAVID

AUDIO: Jack, Mikey, CHS Switch

FERR-120-OHM-2.0A

0402

CRITICAL

L6511

1 2

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6505

1 2

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6504

1 2

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6503

1 2

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6502

1 2

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6501

1 2

SOD882

ESDALC5-1BM2

NOSTUFF

DZ6500

1 2

10%

0.0082UF

X7R-CERM

CRITICAL

0402

25V

C6550

1

2

27PF

0402-1

CERM

50V

CRITICAL

5%

C6558

1

2

16V
X7R-CERM
0402

0.1UF

10%

C6560

1

2

X7R-CERM

10%
16V

0402

0.1UF

C6553

1 2

10%
16V

X7R-CERM

0402

0.1UF

C6552

1 2

FERR-120-OHM-2.0A

CRITICAL

0402

L6508

1 2

100K

MF

1/20W

201

5%

R6555

1

2

10K

MF

1/20W

201

5%

R6562

1

2

1/16W
MF-LF

0

402

5%

R6506

1 2

59 56

53

53

47

FERR-120-OHM-2.0A

CRITICAL

0402

L6503

1 2

47

53

0402

FERR-120-OHM-2.0A

CRITICAL

L6509

1 2

0402

FERR-1000-OHM

L6502

1 2

52

CRITICAL

FERR-120-OHM-2.0A

0402

L6507

1 2

NO_XNET_CONNECTION=1

54722-0224

F-ST-SM

J6500

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

NO_XNET_CONNECTION=1

NOSTUFF

1K

MF-LF

1/16W

402

5%

R6553

1

2

MF-LF

1/16W

0

402

5%

R6551

1 2

58

0402

FERR-1000-OHM

L6510

1 2

59 56

58

FERR-1000-OHM

0402

L6500

1 2

0402

FERR-1000-OHM

L6501

1 2

58

59 58 56 52

0402

FERR-1000-OHM

L6505

1 2

59 56

59 56

20%

X5R-CERM

10V

0402

4.7UF

CRITICAL

C6555

1

2

25V

10%

X7R

0.01UF

402

C6556

1

2

NO_XNET_CONNECTION=1

402

1/16W
MF-LF

5%

1K

R6554

1

2

1/16W
MF-LF

2.2K

402

5%

R6550

1 2

100K

MF

1/20W

201

5%

R6556

1

2

MQFN-RSV

CRITICAL

CD3285A0

U6551

7

8

12

14

15

9

16

11

5

6

1

13

4

10

3

2

47K

MF-LF

1/16W

NOSTUFF

402

5%

R6561

1 2

58

19

14

47

47

59 52

59 52

56

59 58 56 52

59

59

89

58 52

59

89

59

59 58 56 52

56

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

DGND

AVDD

BYPASS

DETECT

MICBIAS

AGND

SCL

SDA

INT*

ENABLE

HDET

CS

IN

IN

OUT

BI

IN

OUT

OUT

www.laptoprepairsecrets.com

TWEETER (FL)

WOOFER (BL) WOOFER (BR)

TWEETER (FR)

SPEAKER CABLE CONNECTORS

APPLE P/N 518S0862

57 OF 93

66 OF 121

0.24.0

051-00673

AUD_SPKR_VENDOR_ID_L AUD_SPKR_VENDOR_ID_R

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_RTWT_OUT_N

AUD_SPKR_RTWT_OUT_P

AUD_SPKR_RWFR_OUT_N

AUD_SPKR_RWFR_OUT_P

AUDIO: Spkr/Mic Conn.

SYNC_MASTER=J17_DIRK SYNC_DATE=03/07/2013

504050-0691

M-RT-SM

CRITICAL

J6602

7

8

1

2

3

4

5

6

504050-0691

M-RT-SM

CRITICAL

J6603

7

8

1

2

3

4

5

6

59 54

59 54

59 55

59 55

59 55

59 55

59

59 54

59 54

59

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

www.laptoprepairsecrets.com

TBT/DP Audio Enable

Target Display Mode Detect

NC

NC

AUD_TIPDET*_R 0 1 1

AUD_SENSE_A 1 20K/2.67K RDIV 5.11K/2.67K RDIV

PORT B DETECT(SPDIF DELEGATE)

IPHS HS Detect Debounce CKT

APN:376S1032

PLACE C6700 CLOSE TO Q6700 PIN 4

PORT D DETECT (HEADPHONES)

AUDIO CONNECTOR DETECT STATES

NOTHING SPDIF HEADPHONE

AUD_TYPEDET_R 1 1 0

AUD_OUTJACK_INSERT 0 1 1

58 OF 93

67 OF 121

0.24.0

051-00673

PP4V5_AUDIO_ANALOG

PP4V5_AUDIO_ANALOG

AUD_TYPEDET_R

AUD_TIPDET1_R

AUD_TIPDET2_R

AUD_SENSE_A

AUD_SENSE_A

DP_TBT_SEL

AUD_PORTD_DET_L

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

AUD_IP_PERIPHERAL_DET

GND_AUDIO_CODEC

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_TYPEDET_OD_INV

AUD_TYPEDET_OD

AUD_TIPDET_INV

AUD_PORTB_DET_L

AUD_OUTJACK_INSERT_L

AUD_LI_TIPDET

AUD_J1_DET_RC

AUD_J1_DET_RC

AUD_IP_PERPH_DET_R

AUD_IP_PERPH_DET_DB

AUD_PORTA_DET_L

AUD_OUTJACK_INSERT

AUDIO: Detects/Grounding

SYNC_MASTER=J17_DIRK SYNC_DATE=03/07/2013

SOT563

NTZD3158P

Q6740

6

2

1

SOT563

NTZD3158P

Q6740

3

5

4

58 56 52

58 56 52

10%

0.1UF

0402

X7R-CERM

16V

C6700

1

2

CRITICAL

SSM6N15AFEAP

SOT563

Q6800

3

5

4

CRITICAL

SSM6N15AFEAP

SOT563

Q6796

6

2

1

MF-LF

402

5%

47K

1/16W

R6743

1

2

CRITICAL

SSM6N15AFEAP

SOT563

Q6797

6

2

1

MF-LF

100K

5%
1/16W

402

R6703

1

2

402

MF-LF

1/16W

5%

100K

R6702

1

2

270K

5%
1/16W
MF-LF

402

R6701

1

2

56

DMC2400UV

SOT563

Q6700

3

5

4

SOT563

DMC2400UV

Q6700

6

2

1

CRITICAL

SSM6N15AFEAP

SOT563

Q6741

6

2

1

CRITICAL

SSM6N15AFEAP

SOT563

Q6741

3

5

4

CRITICAL

SSM6N15AFEAP

SOT563

Q6796

3

5

4

CRITICAL

SSM6N15AFEAP

SOT563

Q6797

3

5

4

1/16W

5%

402

MF-LF

47K

R6741

1

2

56

1/16W

5%

MF-LF

402

100K

R6791

1

2

47K

5%
1/16W
MF-LF

402

R6742

1

2

1%

39.2K

MF-LF
402

1/16W

R6731

1

2

5.11K

1/16W

402

MF-LF

1%

R6795

1

2

56

41 14

0402

FERR-1000-OHM

L6732

1 2

10K

1/16W
MF-LF

5%

402

R6730

1

2

MF-LF
402

20.0K

1/16W

1%

R6796

1

2

402CERM

20%

0.1UF

10V

C6791

1

2

5%

402

MF-LF

1/16W

47K

R6792

1 2

59 58 52

56

0402

FERR-1000-OHM

L6743

1 2

5%

MF-LF

1/16W

100K

402

R6744

1

2

59 58 52

16V

10%

NOSTUFF

0402

0.1UF

X7R-CERM

C6741

1

2

402

0

MF-LF

1/16W

5%

R6745

1 2

14

59 58 56 52

89 55 54 52 38

59 58 56 52

59 58 56 52

59 58 56 52

58

58

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

G

S

D

G

S

D

IN

IN

G S

D

G S

D

G S

D

IN

P-CHN

S

D

G

N-CHN

G

S

D

G S

D

G S

D

G S

D

G S

D

IN

OUT

IN

OUT

IN

NC

IN

OUT

www.laptoprepairsecrets.com

N/A

CONVERTER

FUNCTION CONVERTER

0x10 (16)

ENABLE/CONTROL

0X0C (DET C)

N/A

0X0B (11)

0X12 (18,LEFT)

0X0E (14,LEFT & RIGHT)

PIN COMPLEX

PIN COMPLEX MAC SHDN

Lynx POINT GPIO 3 (PERIPH DET)

Lynx POINT GPIO 16 Lynx POINT GPIO 5 (RCVR INT)

0X03 (3)
0X04 (4)

0X06 (6)

NC

N/A

VOLUME/MUTE

0X07 (7)

OTHER DETECT

EXTERNAL MIC

N/ASPDIF IN

INTERNAL MIC ARRAY

FUNCTION

PHYSICAL

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

N/A

FUNCTION

MULTIPLE SPKR VENDORS

HP/LINE OUT

SPDIF OUT

0X03 (3) 0X03 (3)

0X08 (8)

CODEC INPUT SIGNAL PATHS

0X04 (4) GPIO_3

0X0A (10,V24)

0x0F (15)

0X05 (5)

N/AN/A

MICBIAS

N/A

GPIO_20X0A (10,D)

MICBIAS

N/A

0X06 (6)

WIN SHDN DET ASSIGNMENT

N/A
N/A

ENABLE/CONTROL

N/A

CONVERTER

0X0D (13,V22,B,LEFT)

0X0D (DET B)

DET ASSIGNMENT

0X09 (DET A)

DET ASSIGNMENT

0X03 (3) GPIO_2 0X0A (DET D)

PIN COMPLEX

SECONDARY SPKRS (TWT)

PRIMARY SPKRS (WFR)

CODEC OUTPUT SIGNAL PATHS

PORT C DETECT(SPEAKER MISMATCH)

CIRCUIT THEORY OF OPERATION AVAILABLE IN <RDAR://PROBLEM/9776522>

59 OF 93

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

SPKROUT_DIFFPAIR SPKROUTSPKROUTDIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

AUDIO_DIFFPAIR AUDIOAUDIODIFF

68 OF 121

0.24.0

051-00673

GND_AUDIO_CODEC

AUD_SPKR_VENDOR_ID_R

=PP5V_S0_AUDIO

=PP5V_S0_AUDIO

AUD_SENSE_A

=PP5V_S0_AUDIO

AUD_SPKR_VENDOR_ID_L

SPKR_MATCH_DRV_R SPKR_MATCH_DRV

MAX9119_POS

MAX9119_OUT

MAX9119_NEG

AUD_PORTC_DET_L

AUD_LO1_L_C_P

AUD_LO1_L_N

AUD_LO1_L_P

AUD_LO1_L_C_N

AUD_LO1_R_P

AUD_LO1_R_C_N

AUD_LO1_R_C_P

AUD_LO1_R_N

AUD_RAMP_LINC_P

AUD_RAMP_LINC_N

AUD_RAMP_RIN_P

AUD_RAMP_RINC_P

AUD_RAMP_RINC_N

AUD_RAMP_LIN_P

AUD_RAMP_LIN_N

AUD_LAMP_LINC_P

AUD_LAMP_RINC_N

AUD_LAMP_LINC_N

AUD_RAMP_RIN_N

AUD_LAMP_RINC_P

AUD_LAMP_LIN_N

AUD_LAMP_LIN_P

AUD_LAMP_RIN_P

AUD_LAMP_RIN_N

MAX97220_INR_P

MAX97220_INR_N

MAX97220_INL_P

MAX97220_INL_N

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_RTWT_OUT_N

AUD_SPKR_RTWT_OUT_P

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_RWFR_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_HS_MIC_RC_N

AUD_HS_MIC_RC_P

AUD_J1_MIC_P

AUD_MIC_INL_N

AUD_MIC_INL_P

AUD_SPKR_LTWT_OUT_N

AUD_J1_MIC_N

AUD_HS_MIC_P

AUD_HS_MIC_N

AUD_LO2_R_P

AUD_LO2_R_N

AUD_LO2_L_P

AUD_LO2_L_N

*

Y

10 MM

0.2 MM

0.25 MM0.6 MM

0.2 MM

SPKROUTDIFF

AUDIODIFF

Y

* 0.1 MM 10 MM0.1 MM

0.1 MM0.1 MM

SPKROUTDIFF * SPKROUTDIFF

?

* 0.1 MMAUDIO

0.2 MMSPKROUT *

?

AUDIODIFF*AUDIODIFF

SYNC_MASTER=J78_DAVID SYNC_DATE=11/21/2013

AUDIO: Speaker ID

SPEAKERID

16V
X7R-CERM
0402

0.1UF

10%

C6810

1

2

SOT563

SSM6N15AFEAP

CRITICAL

Q6800

6

2

1

I329

I328

I327

I326

I325

I324

402

MF-LF

1/16W

1%

226K

SPEAKERID

R6814

1

2

37.4K

SPEAKERID

1%

402

1/16W
MF-LF

R6817

1 2

402

MF-LF

1/16W

1%

75K

SPEAKERID

R6815

1

2

10%

2.2UF

805

X7R-CERM

16V

SPEAKERID

C6811

1

2

SPEAKERID

MF-LF

402

10K

1/16W

1%

R6894

1

2

SPEAKERID

402

MF-LF

33

1/16W

5%

R6820

1 2

FERR-1000-OHM

SPEAKERID

0402

L6802

1 2

57 57

MAX9119EXK-T

CRITICAL

SC70-5

SPEAKERID

U6800

3

4

1

5

2

58 52

1%

402

MF-LF

SPEAKERID

100K

1/16W

R6816

1 2

402

SPEAKERID

MF-LF

1/16W

100K

1%

R6811

1

2

MF-LF

402

100K

1%

SPEAKERID

1/16W

R6810

1

2

1/16W

SPEAKERID

100K

1%

402

MF-LF

R6813

1

2

1/16W

SPEAKERID

100K

1%

MF-LF

402

R6812

1

2

I264

I263

I255

I254

I247

I246

I245

I244

I243

I242

I241

I240

I239

I238

I237

I236

I230

I229

I228

I227

I226

I225

I224

I223

I222

I221

I220

I219

I218

I217

I216

I215

I212

I211

I210

I209

I208

I207

I206

I205

I204

I203

58 56 52

89 59 52

89 59 52

89 59 52

53

54 53 52

54 53 52

53

55 53 52

53

53

55 53 52

55

55

55

55

55

55

55

54

54

54

55

54

54

54

54

54

53

53

53

53

57 55

57 55

57 55

57 54

57 54

57 55

57 54

56

56

56

56 52

56 52

57 54

56

56

56

55 52

55 52

54 52

54 52

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

G S

D

ININ

OUT

www.laptoprepairsecrets.com

<Rb>

<Ra>

518-0390

MLB to AC-DC Connector

518S0863

250mA max output

Vout = 3.425
(Switcher limit)

0.10 A (BUDGET)

MLB to AC-DC Supplemental Signal Connector

0.04 A (BUDGET)Max avg current:

Max peak current:

FILTER ADDED TO BURSTMODE_EN_L TO PASS SURGE RDAR://11059712

3.425V "G3Hot" Regulator

Vout = 1.25V * (1 + Ra / Rb)

60 OF 93

DIDT=TRUE

DIDT=TRUE

69 OF 121

0.24.0

051-00673

BURSTMODE_EN_R_L

PWR_BTN_R

SMC_ACDC_ID_R

SMC_ACDC_ID_R

SUP_P12VG3H_MR_L

PP12V_G3H_ACDC

SMC_ACDC_ID

PWR_BTN

SNS_ACDC_P

SNS_ACDC_N

PP12V_G3H_ACDC

BURSTMODE_EN_L

=PP3V3_S0_VRD

P3V42G3H_SHDN_L PP3V42_G3H_REG

P3V42G3H_FB

=PP12V_G3H_P3V42

P3V42G3H_SW

P3V42G3H_BOOST

PM_EPO_L

P3V42G3H_BIAS

=PP3V3_G3H_SSD

PM_EPO_SVR_R_L

PM_EPO_SVR_L

SYNC_MASTER=BRANCH_HCHENG SYNC_DATE=10/29/2014

PLATFORM POWER: Connectors / VReg G3Hot

X6S-CERM
0402

25V

2

1UF

10%

C6907

1

C6902

2

10%

X6S-CERM

25V

1

1UF

0402

16V
CERM
402

0.22UF

10%

C6963

1

2

NOSTUFF

C6962

1000PF

CERM

25V

0402

5%

1

2

1 2

CDPH4D19FHF-SM

33UH

L6961

402

1%
1/16W
MF-LF

R6964

1

2

200K

348K

1%

402

1

2

MF-LF

R6963

1/16W

5%

10K

MF

NOSTUFF

R6932

1/20W

201

2

1

MF

1 2

0

5%

201

1/20W

R6931

2

1

0402

C6920

10%

0.1UF

X6S

25V

CERM-X6S

6.3V

10UF

20%

C6966

0402

1

22

1

6.3V

20%

10UF

CERM-X6S

C6965

0402

1

R6950

1/16W

2

402

5%

MF-LF

0

NOSTUFF

2

1

R6930

201

MF

1/20W

5%

1M

0.1UF

C6930

2

CERM-X5R
0201

10%

1

6.3V

72 71 66 33

5

1

2

TC7SZ08FEAPE

SOT665

3

U6930

4

R6920

2

1

SMCREG:SUP

5%

0

MF-LF

1/16W

402

SOT23-5

1

3

SMCREG:SUP

TPS3847108DBV

2

U6920

4

5

SM

TANT

16V

C6908

1

2

20%

15UF

0402

1UF

25V
X6S-CERM

EMC

10%

C6945

1

2

X6S-CERM

EMC

0402

25V

1UF

10%

C6944

1

2

X6S-CERM

EMC

0402

25V

1UF

10%

C6943

1

2

1UF

EMC

25V
X6S-CERM
0402

10%

C6942

1

2

1UF

EMC

0402

X6S-CERM

25V

10%

C6941

1

2

25V
X6S-CERM

1UF

EMC

0402

10%

C6940

1

2

2

1

R6967

201

1/20W

5%

MF

0

X6S-CERM

20%

J6900.4:10MM

0603

16V

10UF

C6916

1

2

45

X7R-CERM

16V

PLACE_NEAR=R6916.1:3MM

0402

10%

0.1UF

C6910

1

2

402

6.8V-100PF

PLACE_NEAR=J6901.1:3MM

DEFAULT_CAPACITOR_100.000000pF_2_1

D6910

1

2

45

5%

402

1/16W
MF-LF

1K

PLACE_NEAR=J6901.1:3MM

R6916

1 2

16V

10%

0.1UF

PLACE_NEAR=R6910.1:3MM

0402

X7R-CERM

C6915

1

2

5%

402

1K

MF-LF

1/16W

PLACE_NEAR=J6901.7:3MM

R6910

1 2

50

402

6.8V-100PF

PLACE_NEAR=J6901.7:3MM

DEFAULT_CAPACITOR_100.000000pF_2_1

D6912

1

2

M-RT-SM

SILK_PART=PWRSIG

504050-0791

J6901

8

9

1

2

3

4

5

6

7

50

402

PLACE_NEAR=J6901.3:4MM

6.8V-100PF

D6911

1

2

DEFAULT_CAPACITOR_100.000000pF_2_1

402

PLACE_NEAR=J6901.3:30MM

R6913

1

2

10K

MF-LF

1/16W

5%

5%

402

MF-LF

1K

1/16W

PLACE_NEAR=J6901.3:3MM

1 2

R6914

0.01UF

0402

X7R-CERM

20%
16V

PLACE_NEAR=R6914.2:3MM

C6914

1

2

M-RT-TH

43045-1200

CRITICAL

J6900

1

2

3

4

5

6

7

8

9

10

11

12

16V
X6S-CERM
0603

20%

J6900.4:10MM

10UF

C6911

1

2

J6900.5:11MM

5%

1000PF

25V

0402

CERM

EMC

C6912

1

2

EMC

CERM

25V

5%

J6900.5:11MM

1000PF

C6913

1

2

0402

402

1%
1/16W

1

2

R6962

MF-LF

49.9K

402

MF-LF

2

1

150K

1%
1/16W

R6961

U6911

DFN

2

3

5

8 4

9

6

1

7

LT3470AED

CER-C0G
0402

50V

22PF

1

2

5%

C6964

60

60

89 60

45

89 60

89 85 65 61

89

89

89 71 66

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

OUT

A

B

Y

NC

VCC

MR*

GND

NC

RESET*

IN

OUT

OUT

OUT

THRM

PAD

FB

NC

GND

SHDN*

BIAS

VIN BOOST

SW

www.laptoprepairsecrets.com

VCC SENSE

ISUM_B

GT SENSE

ISUM_A

ISUM_C

SA SENSE

COMP A,B,C

61 OF 93

70 OF 121

0.24.0

051-00673

=PP1V0_S3_VCCST

FB_B

ISUMN_A

COMP_C

FB_A

VSS_SENSE_R

VSSGT_SENSE_R

COMP_C_L

COMP_B_L

VCC_SENSE

VSS_SENSE_R

FB_A_R_3

FB_A_R_2

ISEN1_A

ISEN2_A

ISEN3_A

COMP_A

NTC_A_R

PSYS

FB_C_L_3

FB_C_L_2

FB_C

FB_C_L_1

FB_B_L_3

FB_B_L_1

FB_B

PROG5

FB_C

VSSGT_SENSE_R

NTC_B_L

ISUMN_B_R

REG_CPUVCC_GT_IMON

ISUMP_C

ISUMN_C_R

=PP5V_S0_REG_CPUVCC_S0

REG_VCC_U7000

REG_VIN_U7000

VSS_SENSE

FB_A_R_4

VSS_SAIO_SENSE_R

FB_C_L_4

COMP_B

PWM1_A
PWM2_A

PWM3_A

PM_PGOOD_REG_CPUVCC_S0

MAKE_BASE=TRUE

REG_CPUVCC_PGOOD

ISUMP_B

ISUMN_B_R

ISEN1_B

VSS_SAIO_SENSE_R

=PP12V_S0_CPUCORE

ISUMN_A_L

ISEN2_B

ISEN2_A

ISUMP_A

PWM2_B

FCCM_B

ISUMN_B

REG_VCC_U7000

FCCM_A

FCCM_A_L

ISUMN_A_L

ISUMP_A

VR_HOT_L

REG_CPUVCC_PGOOD

PM_EN_REG_CPUVCC_S0_R

FCCM_B_R

PWM1_B

ISEN2_B

ISEN1_A

ISUMN_B_L_1

ISUMP_B

ISUMP_A_L

PP12V_S0_CPUCORE_FLT

REG_VCC_U7000

ISUMN_B_L_2

ISUMN_C_L_1

ISUMN_C_L_2

FB_B_L_2

VSS_SAIO_SENSE

VCCSA_SENSE

FB_B_L_4

VSSGT_SENSE

VCCGT_SENSE

=PP12V_S0_REG_CPUCORE

=PP3V3_S0_VRD

REG_VCC_U7000

ISEN3_A

ISUMN_A_R

ISEN1_B

SCLK

SDA

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

ALERT

ISUMN_C

PROG3

FCCM_C

NTC_B

FCCM_C_R

PWM_C

ISUMP_C

ISUMN_C_R

COMP_C

REG_CPUVCC_SA_IMON

NTC_A

CPU_PROCHOT_L

PM_EN_REG_CPUVCC_S0

FB_A

FB_A_R_1

COMP_A_R

COMP_A

COMP_B

REG_CPUVCC_IMON

PROG1

PROG4

PROG2

CPU & CHIPSET: CPU CORE VR

SYNC_DATE=10/29/2014SYNC_MASTER=BRANCH_HCHENG

2%
50V
C0G

220PF

C7029

1 2

0201

4.99K

R7058

1 2

MF

201

1%

1/20W

25V

2%

560PF

NPO-C0G

2

1

0201

C7030

2%

50V

NP0-C0G

56PF

C7019

1 2

0201

R7032

110K

1/20W

1%

MF

1

2

201

R7017

1K

21

201

1%

1/20W

MF

201

MF

1%

1/20W

21

1K

R7009

R7053

1/20W

1%

MF

4.64K

201

21

1

R7054

MF

1K

1%

1/20W

2

201

2%

C7031

NPO-C0G

25V

0201

1 2

560PF

1%

1/20W

MF

201

1 2

100K

R7051

R7050

7.15K

2

MF

1%

1/20W

1

201

C7028

NOSTUFF

0.1UF

1

2

X7R

6.3V

10%

0201

1

R7037

12.1K

1%
1/20W
MF
201

2

4700PF

10V
X7R

10%

2

201

1

C7027

1 2

560PF

NPO-C0G

25V

2%

0201

C7018

1/20W

MF

R7023

21

1%

2.49K

201

499

1 2

201

MF

1%

1/20W

R7020

25V

820PF

1

C7020

2

0201

X7R-CERM

10%

0201

C7012

X7R-CERM

820PF

10%
25V

1

2

1%

MF

201

21

1/20W

3.57K

R7012

100K

201

1%

MF

2

R7019

1/20W

1

1

1/20W

MF

201

7.15K

2

R7016

1%

21

R7011

MF

100K

1%

1/20W

201

MF-LF

1/16W

5%

0

R7002

402

2

1

1

C7002

2

0402-1

X7R

10%
25V

0.22UF

25V

10%

X6S

1.0UF

C7001

0402

1

2

NPO-COG

330PF

2

1

0201

2%
25V

C7032

0201

NPO-COG

25V

2%

2

1

330PF

C7033

2

1

2%

330PF

25V
NPO-COG
0201

C7021

NPO-COG

25V

1

2

330PF

2%

C7016

0201

C7022

0201

NPO-COG

25V

330PF

2%

1

2

C7011

2%

25V

NPO-COG

330PF

21

0201

C7044

2

X7R
0201

6.3V

10%

0.1UF

1

1

2

201

R7035

169K

1%
1/20W
MFMF

201

16.9K

2

1

1/20W

1%

R7034

40

29

2

49

LLP-THICKSTNCL

ISL95828HRTZ

18

43

27

37

38

39

28 1

31

33

32

35

3

4

10

9

8

7

13

12

11

48

47

46

15

14

17

16

23

21
22

19
20

25
26

24

45

41

42

U7000

6

5

30

36

44

34

X7R
402

21

10%
25V

C7014

0.0082UF

50V

68PF

C0G

5%

0201

21

C7015

68

0.0082UF

1

X7R

25V

2

402

C7034

10%

0201

2 1

50V
C0G

68PF

5%

C7035

2

1

0201

220KOHM-3%

RT7001

1

MF

1%
1/20W

2

2K

R7052

201

2K

MF

1%
1/20W

201

2

1

R7010

R7021

2

MF

2K

1

201

1%
1/20W

5%
1/20W
MF
201

2

1

10K

R7040

0.0082UF

21

C7008

25V
X7R

10%

402

0201

68PF

21

50V

5%

C0G

C7007

2

1

2%
25V

C7017

330PF

0201

NPO-COG

R7013

1K

1

1/20W

1%

201

2

MF

R7060

1%

1K

MF

201

21

1/20W

MF

365

1 2

201

1%

1/20W

R7061

0201

25V
X7R

10%

1 2

2200PF

C7036

2%
25V

C7041

1

NPO-COG

2

0201

330PF

2

1K

1%

1

1/20W

201

R7008

MF

0201

2

10%
25V

1

X7R

2200PF

C7003

201

2

1/20W

MF

1%

1

R7005

287

2%

2

1

25V

0201

NPO-COG

C7004

330PF

11K

R7006

NOSTUFF

1/20W

1%

MF

1

2

201

1

NOSTUFF

R7063

11K

1%
1/20W
MF
201

2

2

1

C7025

2%

330PF

25V
NPO-COG
0201

25V

0201

X7R

21

NOSTUFF

2200PF

10%

C7023

R7027

1/20W

1 2

MF

1%

249

201

NOSTUFF

201

MF

1/20W

1 2

1%

1K

R7029

NOSTUFF

201

MF

1%

2

1

1/20W

R7031

11K

2

SM

XW7000

1

PLACE_NEAR=U7000.45:2.5mm

R7039

49.9

1

1%

MF

2

1/20W

201

5%

PLACE_NEAR=U7000.43:2.5mm

R7045

201

1 2

10

MF

1/20W

R7042

PLACE_NEAR=U7000.44:2.5mm

0

1/20W

MF

1

5%

201

2

65 8

1

201

MF

10

2

R7074

1/20W

1%

63

63

8

2

MF

1%

10

1

201

1/20W

R7076

8

1%

1/20W

1 2

10

MF

R7071

201

45 44 6

8

8

R7036

1%

MF

1

201

1/20W

80.6K

2

34K

1%
1/20W

R7033

1

MF

2

201

201MF1/20W

0

21

R7062

5%

62

62

62

62

68

1 2

5%

1/20WMF

201

R7018

0

63

0

1/20W201 MF

1 2

5%

R7003

73 3

8

2

SSL0705M-SM

1

0.105UH-20%-31A-0.00032OHM

L7000

R7048

5%

MF

21

0

201

1/20W

201

75

1%

1 2

1/20W

MF

R7047

1

1%

1.00

MF

2

402

R7001

1/16W

89 12

6

6

45.3

PLACE_NEAR=R7039.2:2.5mm

1%

2

MF
201

1/20W

R7038

1

PLACE_NEAR=R7042.2:2.5mm

1/20W

R7041

NOSTUFF

100

201

1

2

MF

1%

MF

1/20W

201

1

2

1%

R7044

100

PLACE_NEAR=R7045.2:2.5mm

68

68 61

10%

2

25V

1

X7R
402

NOSTUFF

0.015UF

C7026

6.3V
X7R

2 1

0201

10%

0.1UF

C7024

NOSTUFF

R7090

0

1/20W

MF

2

201

5%

1

R7026

1

NOSTUFF

0

1/20W

5%

2

201

MF

10

MF

R7025

201

2

1/20W

1%

1

R7024

5%

1

MF

2

0

201

1/20W

62

62 61

0402

X7R

2

25V

10%

C7039

0.022UF

1

0402

2

25V
X7R

1

10%

0.022UF

C7037

2

1

C7038

0.022UF

0402

X7R

25V

10%

1/20W

5%

MF

1

2

201

0

R7064

NOSTUFF

C7040

1

10%

0201

2

NOSTUFF

0.1UF

6.3V
X7R

NOSTUFF

1

R7059

0

5%

1/20W

2

201

MF

10

1

1/20W

MF

2

201

1%

R7056

2

201

MF

5%

1

1/20W

0

R7055

10%

C7010

0.022UF

25V
X7R
0402

2

1

0.022UF

X7R

1

0402

10%
25V

2

C7009

1/20W

201

1

5%

0

MF

R7004

2

NOSTUFF

63

63 61

C7006

10%

6.3V

1

0.1UF

0201

X7R

2

0.1UF

6.3V

0201

X7R

10%

1

2

C7005

NOSTUFF

0

1/20W

1

MF

2

5%

201

NOSTUFF

R7007

1/20W

10

R7015

1 2

MF

201

1%

MF

201

1

5%

2

1/20W

R7014

0

1

390PF

C7013

25V

2%

2

0201

C0G

1

2

0201

220KOHM-3%

RT7000

61

61

61

61

61

61

62 61

62 61

62 61

61

61

61

61

61

48

61

89 68 65 63 62

61

61

61

61

63 61

61

63 61

61

89

61

63 61

62 61

61

61

62 61

61

63

61

62 61

89

61

89 68 65 63 62

89 85 65 60

62 61

63 61

68 61

61

61

48

72

61

61

61

48

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PWM3_A

PROG4

PROG3

PROG5

PROG2

PROG1

IMON_C

THRM_PAD

PSYS

RTN_C

FB_C

COMP_C

ISUMN_C

ISUMP_C

FCCM_C

PMW_C

NTC_B

IMON_B

RTN_B

FB_B

COMP_B

ISEN2_B

ISEN1_B

ISUMN_B

ISUMP_B

PWM2_B

PWM1_B

FCCM_B

SCLK

SDA

ALERT*

VR_ENABLE

VR_READY

VR_HOT*

NTC_A

IMON_A

RTN_A

FB_A

COMP_A

ISEN3_A

ISEN1_A
ISEN2_A

ISUMP_A

ISUMN_A

PWM1_A
PWM2_A

FCCM_A

VIN

VCC

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

CPU VCORE Phase 2

CPU VCORE OUTPUT DECOUPLING

CPU Phase 3

CPU VCC Regulator

EDC = 100A
TDC = 70A

CPU VCORE Phase 1

62 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE DIDT=TRUE

DIDT=TRUE

71 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:21 2015

REG_SNUBBER_CPUVCC_3

ISUMN_A

PP5V_S0_VRD_VCIN_A1

DSBL_A_1

PP5V_S0_VRD_VCIN_A3

BOOST_A_3

BOOST_A_1_RC

BOOST_A_2_RC

PHASE_A_3

BOOST_A_3_RC

PHASE_A_2

SW_A_2

DSBL_A_2

REG_CPUVCC_ISNS_2_N

REG_CPUVCC_ISNS_3_N

REG_SNUBBER_CPUVCC_1

REG_CPUVCC_ISNS_1_N

REG_CPUVCC_ISNS_3_N

REG_CPUVCC_ISNS_1_N

REG_CPUVCC_ISNS_2_N

ISUMP_A

ISUMP_A

REG_SNUBBER_CPUVCC_2

ISEN3_A

BOOST_A_1

FCCM_A

THWN_A_1

FCCM_A

THWN_A_2

PWM2_A

=PP5V_S0_REG_CPUVCC_S0

=PP5V_S0_REG_CPUVCC_S0

THWN_A_3

PWM3_A

FCCM_A

PWM1_A

ISUMN_A

REG_CPUVCC_ISNS_1_P

ISEN1_A

PPCPUVCC_S0_SENSE_2_1

REG_CPUVCC_ISNS_2_P

REG_CPUVCC_ISNS_2_N

PPCPUVCC_S0_SENSE_3_1

REG_CPUVCC_ISNS_3_P

REG_CPUVCC_ISNS_3_N

PPVCC_S0_CPU_REG

PPVCC_S0_CPU_REG

ISUMN_A

ISEN2_A

=PP12V_S0_REG_CPUCORE

PPVCC_S0_CPU_REG

REG_CPUVCC_ISNS_1_N

PPVCC_S0_CPU_REG

ISUMP_A

SW_A_3

DSBL_A_3

=PP12V_S0_REG_CPUCORE

PPCPUVCC_S0_SENSE_1_1PHASE_A_1

SW_A_1

=PP12V_S0_REG_CPUCORE

BOOST_A_2

=PP5V_S0_REG_CPUVCC_S0

CPU & CHIPSET: CPU CORE VR (VCC)

SYNC_DATE=02/11/2015SYNC_MASTER=J95_HARPER

0.0005

43

21

0612-2

1W

1%

MF

CRITICAL

R7150

43

21

0612-2

R7130

CRITICAL

1W
MF

1%

0.0005

CRITICAL

R7110

1W

1%

0.0005

MF

0612-2

1 2
3 4

MF
201

1/20W

1

2

1K

1%

R7159

201

MF

1%

1K

2

1

1/20W

R7139

1

R7119

1/20W

201

MF

2

1K

1%

MF

201

21

1/20W

1%

100K

R7162

R7161

100K

1/20W

MF

1%

21

201

2

201

MF

1/20W

1%

1

100K

R7160

1 2

1/20W

1%

MF

201

100K

R7142

R7141

100K

1%

2

1/20W

1

201

MF

100K

1%
1/20W
MF
201

1

2

R7140

201

100K

1%

1

2

1/20W
MF

R7120

100K

MF

1%

1/20W

21

201

R7122

201

R7121

100K

1 2

1/20W

1%

MF

25V

10%

X7R

0.22UF

C7136

0402-1

1

2

25V

0402-1

X7R

10%

0.22UF

C7156

1

2

C7116

0.22UF

10%

X7R

25V

1

2

0402-1

20%

C7167

1

2

0603

16V

10UF

X6S-CERM

10UF

20%
16V

X6S-CERM

2

C7147

1

0603

16V

20%

10UF

X6S-CERM

C7111

0603

2

1

2

8
9

1

30

5

16

7

27
33

3

29

28

12

32

4

6

24

MLP-THICKSTNCL

SIC625CD

Q7150

31

2

8
9

31

1

30

5

16

7

27
33

3

29

28

12

32

4

6

24

MLP-THICKSTNCL

Q7130

SIC625CD

2

8
9

31

1

30

5

16

7

27
33

3

29

28

12

32

4

6

24

MLP-THICKSTNCL

SIC625CD

Q7110

NOSTUFF

C7199

15UF

20%

TANT

16V

SM

2

1

2

16V

20%

TANT

NOSTUFF

SM

15UF

C7198

1

C7197

SM

NOSTUFF

TANT

15UF

20%
16V

2

1

MF-LF

1 2

402

1/16W

R7169

5%

10K

R7149

1 2

402

5%

1/16W

MF-LF

10K

R7129

1 2

402

5%

MF-LF

1/16W

10K

20%

1

2

16V

CRITICAL

C7196

68UF

POLY-TANT
CASE-D2E-SM

POLY-TANT

CRITICAL

20%

CASE-D2E-SM

16V

68UF

C7129

1

2

0402

X6S-CERM

EMC

25V

10%

1UF

CRITICAL

C7131

1

2

62 61

62 61

0402-1

X6S-CERM

10UF

4V

20%

C7194

1

2

10UF

20%
X6S-CERM

0402-1

4V

C7173

1

2

0402-1

20%
X6S-CERM

4V

10UF

C7192

1

2

20%

10UF

X6S-CERM
0402-1

4V

C7193

1

2

62 61

X6S-CERM

20%
4V

2

10UF

0402-1

1

C7190

0402-1

C7191

10UF

X6S-CERM

20%
4V

1

2

61

NOSTUFF

R7168

10K

21

402

MF-LF

1/16W

5%

X6S-CERM

C7168

1UF

10%
25V

1

2

0402

1/16W
MF-LF

402

R7167

5%

1

1 2

61

NOSTUFF

R7148

MF-LF

1/16W

5%

402

1

10K

2

10%

PP5V_S0_VRD_VCIN_A2

1UF

0402

25V

C7148

1

2

X6S-CERM

MF-LF

1/16W

5%

1

402

R7147

1 2

62 61

61

NO_XNET_CONNECTION=1

1/20W

1%

3.9

201

MF

2

R7158

1

62 61

62 61

61

R7138

NO_XNET_CONNECTION=1

1%

3.9

MF

1 2

201

1/20W

62 61

62 61

62 61

61

MF

R7118

201

3.9

1%

1 2

1/20W

NO_XNET_CONNECTION=1

R7127

1/16W

402

1

MF-LF

1

5%

2

0402

C7128

10%

1UF

X6S-CERM

25V

2

1

NOSTUFF

R7128

402

MF-LF

1/16W

5%

21

10K

CASE-D2E-SM

68UF

CRITICAL

C7172

20%
16V
POLY-TANT

1

2

CASE-D2E-SM

68UF

POLY-TANT

20%
16V

CRITICAL

1

2

C7171

CRITICAL

20%
16V

68UF

POLY-TANT
CASE-D2E-SM

1

2

C7170

C7150

16V

68UF

CRITICAL

20%

1

CASE-D2E-SM

POLY-TANT

2

POLY-TANT

68UF

20%

1

2

C7144

CRITICAL

CASE-D2E-SM

16V

CASE-D2E-SM

POLY-TANT

16V

68UF

20%

1

2

C7145

CRITICAL

CASE-D2E-SM

68UF

20%

CRITICAL

POLY-TANT

1

2

C7146

16V

C7130

POLY-TANT

68UF

16V

20%

CRITICAL

CASE-D2E-SM

1

2

CASE-D2E-SM

CRITICAL

68UF

20%
16V
POLY-TANT

1

2

C7126

CRITICAL

C7125

16V
POLY-TANT

20%

1

2

CASE-D2E-SM

68UF

POLY-TANT
SM

2.5V

20%

1

23

C7180

CRITICAL

470UF-0.0045OHM

NOSTUFF

470UF-0.0045OHM

POLY-TANT

2.5V

SM

CRITICAL

20%

C7181

1

23

C7182

CRITICAL

2.5V
POLY-TANT
SM

470UF-0.0045OHM

1

23

20%

470UF-0.0045OHM

CRITICAL

C7183

POLY-TANT

20%

2.5V

SM

1

23

NOSTUFF

CRITICAL

20%

2.5V

SM

POLY-TANT

470UF-0.0045OHM

C7184

1

23

470UF-0.0045OHM

20%

POLY-TANT

2.5V

CRITICAL

SM

C7185

1

23

CRITICAL

PIME104T-SM

L7150

1 2

0.22UH-20%-43A-0.64OHM

21

PIME104T-SM

0.22UH-20%-43A-0.64OHM

L7130

CRITICAL

PIME104T-SM

1 2

L7110

CRITICAL

0.22UH-20%-43A-0.64OHM

0402-1

10UF

X6S-CERM

4V

1

2

C7162

20%

10UF

0402-1

4V

20%
X6S-CERM

2

C7142

1

4V

2

X6S-CERM

20%

1

C7143

10UF

0402-1

1

C7122

0402-1

X6S-CERM

20%
4V

2

10UF

2

10UF

4V

20%

C7123

1

X6S-CERM
0402-1

C7163

20%

10UF

4V
0402-1

1

2

X6S-CERM

2.2

805

5%
1/8W

R7157

1

2

MF-LF

NOSTUFF

603

1/10W
MF-LF

5%

1

2

0

R7156

0.001UF

10%
X7R-CERM

C7157

0402

50V

NOSTUFF

1

2

89 62

R7137

2.2

1/8W
805

5%
MF-LF

NOSTUFF

1

2

603

MF-LF

1/10W

5%

0

1

2

R7136

C7137

1

0.001UF

50V

10%

0402

X7R-CERM

2

NOSTUFF

89 62

0402

1UF

10%
25V

EMC

CRITICAL

X6S-CERM

C7154

1

2

1UF

EMC

25V

10%

0402

X6S-CERM

C7134

1

2

CRITICAL

0402

25V

10%

1UF

X6S-CERM

1

2

EMC

CRITICAL

C7114

C7120

2

0402

25V

1

X6S-CERM

10%

1UF

CRITICAL

10%

X6S-CERM
0402

25V

1

2

CRITICAL

C7121

1UF

C7140

2

1

CRITICAL

1UF

10%
25V
X6S-CERM
0402

C7141

1UF

X6S-CERM

10%

0402

25V

CRITICAL

1

2

0402

25V

10%

X6S-CERM

C7159

1

2

1UF

CRITICAL

CRITICAL

X6S-CERM

10%
25V

1UF

0402

2

C7160

1

1UF

X6S-CERM

10%

0402

25V

C7152

1

2

CRITICAL

X6S-CERM

2

CRITICAL

10%

1UF

0402

25V

C7153

1

C7161

CRITICAL

X6S-CERM

1UF

10%
25V

0402

2

1

X6S-CERM

10%

1

CRITICAL

C7158

25V

0402

1UF

2

CRITICAL

10%

0402

25V
X6S-CERM

1UF

C7132

1

2

10%

X6S-CERM
0402

1UF

25V

C7133

1

2

CRITICAL

1UF

X6S-CERM

CRITICAL

0402

25V

10%

C7138

1

2

X6S-CERM

1UF

1

C7139

0402

10%
25V

2

CRITICAL

1UF

25V

10%

X6S-CERM
0402

CRITICAL

C7118

1

2

CRITICAL

0402

25V

1UF

C7119

X6S-CERM

10%

1

2

0402

10%

1UF

CRITICAL

X6S-CERM

C7113

1

2

25V

X6S-CERM

25V

0402

10%

1UF

CRITICAL

C7112

1

2

89 62

61

603

2

0

5%

MF-LF

1/10W

R7116

1

NOSTUFF

2.2

1/8W
805

5%
MF-LF

1

2

R7117

NOSTUFF

0.001UF

X7R-CERM
0402

10%
50V

1

2

C7117

X6S-CERM

10%

EMC

CRITICAL

25V
0402

1UF

C7155

1

2

CRITICAL

X6S-CERM

1UF

0402

25V

10%

EMC

C7115

1

2

62

62

62

62

62

89 68 65 63 62 61

89 68 65 63 62 61

62

62

89 68 65 63 62 61

62

89 62

89 68 65 63 62 61

89 68 65 63 62 61

89 68 65 63 62 61

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

VSWH1

GH

CGND

CGND

PGND

PGND

VDRV

VCIN

GL1

GL0

PHASE

VSWH0

BOOT

THWN

PWM

DSBL*

VIN1

VIN0

ZCD_EN*

VSWH1

GH

CGND

CGND

PGND

PGND

VDRV

VCIN

GL1

GL0

PHASE

VSWH0

BOOT

THWN

PWM

DSBL*

VIN1

VIN0

ZCD_EN*

VSWH1

GH

CGND

CGND

PGND

PGND

VDRV

VCIN

GL1

GL0

PHASE

VSWH0

BOOT

THWN

PWM

DSBL*

VIN1

VIN0

ZCD_EN*

IN

IN

IN

IN

NC

NC

IN

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

OUT

IN

www.laptoprepairsecrets.com

CPU VCCGT OUTPUT DECOUPLING

TDC = 37A

CPU VCCGT Phase 1

CPU VCCGT Regulator

EDC = 51A

CPU VCCGT Phase 2

63 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

72 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:21 2015

SW_B_2

REG_SNUBBER_CPUVCCGT_2

ISUMP_B

REG_SNUBBER_CPUVCCGT_1

ISUMP_B

SW_B_1

PP5V_S0_VRD_VCIN_B1

THWN_B_2

PWM2_B

DSBL_B_2

FCCM_B

THWN_B_1

BOOST_B_1

PWM1_B

DSBL_B_1

BOOST_B_1_RC

PHASE_B_1

PHASE_B_2

BOOST_B_2_RC

BOOST_B_2

=PP5V_S0_REG_CPUVCC_S0

FCCM_B

=PP5V_S0_REG_CPUVCC_S0

PPCPUVCCGT_S0_SENSE_2_1

PPVCCGT_S0_CPU_REG

REG_VCCGT_ISNS_2_P

ISEN2_B

REG_VCCGT_ISNS_2_N

PPVCCGT_S0_CPU_REG

=PP12V_S0_REG_CPUCORE

REG_VCCGT_ISNS_1_N

ISUMN_B

REG_VCCGT_ISNS_2_N

ISEN1_B

REG_VCCGT_ISNS_1_N

ISUMN_B

=PP12V_S0_REG_CPUCORE

REG_VCCGT_ISNS_1_P

PPVCCGT_S0_CPU_REG

PPCPUVCCGT_S0_SENSE_1_1

CPU & CHIPSET: CPU CORE VR (VCCGT)

SYNC_DATE=02/11/2015SYNC_MASTER=J95_HARPER

1W
MF

0612-2

12
34

CRITICAL

1%

0.0005

R7210

MF

1%
1W

CRITICAL

0612-2

1
3 4

2

0.0005

R7230

1

2

1K

1%

MF
201

1/20W

R7239

R7219

201

MF

1%

1K

2

1/20W

1

R7241

MF

1%

201

21

1/20W

100K

R7240

100K

MF
201

2

1/20W

1%

1

1%

1/20W

MF

100K

2

201

1

R7221

1

2

1/20W

1%

100K

201

MF

R7220

2

0402-1

10UF

20%
4V
X6S-CERM

C7290

1

C7293

0402-1

1

2

X7R

0.22UF

10%
25V

2

1

0402-1

C7216

0.22UF

X7R

10%
25V

1

C7247

X6S-CERM

0603

2

16V

20%

10UF

20%

C7127

10UF

2

1

16V

X6S-CERM

0603

2

8
9

31

1

30

5

16

7

27
33

3

29

28

12

32

4

6

24

MLP-THICKSTNCL

SIC625CD

Q7230

2

8
9

31

1

30

5

16

7

27
33

3

29

28

12

32

4

6

24

MLP-THICKSTNCL

Q7210

SIC625CD

NOSTUFF

1

C7299

20%

SM

2

16V
TANT

15UF

C7298

TANT

20%
16V

NOSTUFF

15UF

SM

2

1

1

402

1/16W

MF-LF

R7249

5%

10K

2

1 2

10K

MF-LF

1/16W

5%

R7229

402

NOSTUFF

R7233

2

1

5%

805

MF-LF

1/8W

2.2

R7232

5%

1/10W

2

1

0

603

MF-LF

C7215

CRITICAL

X6S-CERM

2

1

10%

0402

25V

1UF

NO_XNET_CONNECTION=1

1%

MF

201

1/20W

1 2

3.9

R7218

POLY-TANT

2

1

16V

68UF

20%

CRITICAL

C7245

CASE-D2E-SM

X6S-CERM

25V

CRITICAL

2

1

C7213

10%

0402

1UF

10%

2

1

C7231

CRITICAL

25V

EMC

1UF

X6S-CERM
0402

63 61

2

1

C7252

4V
0402-1

10UF

X6S-CERM

20%

2

1

10UF

20%
4V
X6S-CERM
0402-1

C7253

63 61

2

1

0402-1

20%

10UF

X6S-CERM

4V

C7294

0402-1

2

1

X6S-CERM

4V

20%

10UF

C7292

61

1/16W

21

5%

402

MF-LF

10K

R7248

NOSTUFF

1UF

0402

X6S-CERM

25V

2

1

10%

C7248

PP5V_S0_VRD_VCIN_B2

MF-LF

21

402

1/16W

1

5%

R7247

63 61

61

NO_XNET_CONNECTION=1

3.9

2

MF

1%

201

1/20W

1

R7238

63 61

63 61

63 61

61

1/16W

21

R7227

1

5%

MF-LF

402

2

1

X6S-CERM
0402

25V

C7228

1UF

10%

R7228

NOSTUFF

10K

MF-LF

402

1/16W

5%

1 2

CASE-D2E-SM

2

1

68UF

16V

20%

C7244

POLY-TANT

CRITICAL

CRITICAL

2

1

C7246

68UF

16V

CASE-D2E-SM

20%

POLY-TANT

C7230

POLY-TANT

CRITICAL

2

20%
16V

68UF

CASE-D2E-SM

1

C7226

2

16V

20%

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

1

POLY-TANT

16V

2

1

CRITICAL

CASE-D2E-SM

20%

C7225

68UF 68UF

POLY-TANT

2

1

16V

20%

C7224

CRITICAL

CASE-D2E-SM

68UF

20%

2

1

16V

C7210

CASE-D2E-SM

POLY-TANT

CRITICAL

NOSTUFF

23

1

C7280

SM

20%

2.5V

CRITICAL

POLY-TANT

470UF-0.0045OHM

3

1

CRITICAL

C7281

470UF-0.0045OHM

2

20%

2.5V
POLY-TANT
SM

3 2

1

C7282

SM

2.5V

20%

CRITICAL

POLY-TANT

470UF-0.0045OHM 470UF-0.0045OHM

CRITICAL

3 2

1

C7283

20%

SM

2.5V
POLY-TANT

NOSTUFF

2SM3

1

C7284

470UF-0.0045OHM

POLY-TANT

20%

2.5V

CRITICAL

NOSTUFF

CRITICAL

3 2

1

C7285

POLY-TANT
SM

2.5V

20%

470UF-0.0045OHM

CRITICAL

0.22UH-20%-43A-0.64OHM

L7230

21

PIME104T-SM

0.22UH-20%-43A-0.64OHM

L7210

1 2

PIME104T-SM

CRITICAL

C7242

2

0402-1

20%
4V
X6S-CERM

10UF

1

20%
X6S-CERM

0402-1

2

1

C7243

10UF

4V

0402-1

X6S-CERM

4V

20%

C7223

10UF

2

1

NOSTUFF

X6S-CERM

1UF

2

25V

1

10%

0402

C7291

89 63

2

10%

0402

X6S-CERM

EMC

25V

1UF

C7234

1

CRITICAL

1

2

CRITICAL

EMC

10%
25V

0402

X6S-CERM

1UF

C7214

C7220

1

10%

CRITICAL

1UF

2

25V
X6S-CERM
0402

2

CRITICAL

C7221

1UF

10%

0402

1

25V
X6S-CERM

0402

2

C7240

CRITICAL

X6S-CERM

1

10%

1UF

25V

2

1

10%

X6S-CERM

25V

0402

1UF

C7241

CRITICAL

X6S-CERM

2

1

25V

10%

1UF

0402

C7232

CRITICAL

CRITICAL

C7233

2

1

25V
X6S-CERM

1UF

10%

0402

C7238

2

1

0402

10%
25V
X6S-CERM

CRITICAL

1UF

X6S-CERM

2

CRITICAL

C7239

1

25V

10%

1UF

0402

2

1UF

C7219

10%

CRITICAL

1

25V

0402

X6S-CERM

2

0402

10%
25V
X6S-CERM

1

CRITICAL

C7212

1UF

89 63

61

R7216

0

2

5%
1/10W
MF-LF

603

1

NOSTUFF

2.2

805

2

1

5%
1/8W
MF-LF

R7217

C7217

0.001UF

X7R-CERM
0402

NOSTUFF

2

1

50V

10%

CRITICAL

X6S-CERM

2

1

C7255

EMC

0402

1UF

10%
25V

89 68 65 63 62 61

89 68 65 63 62 61

89 63

89 68 65 63 62 61

63

63

63

89 68 65 63 62 61

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

VSWH1

GH

CGND

CGND

PGND

PGND

VDRV

VCIN

GL1

GL0

PHASE

VSWH0

BOOT

THWN

PWM

DSBL*

VIN1

VIN0

ZCD_EN*

VSWH1

GH

CGND

CGND

PGND

PGND

VDRV

VCIN

GL1

GL0

PHASE

VSWH0

BOOT

THWN

PWM

DSBL*

VIN1

VIN0

ZCD_EN*

IN

IN

IN

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

OUT

IN

www.laptoprepairsecrets.com

Critical:

EDC = 20A

to sink heat

Need copper around Q7310

VDDQ (1.35V) S3 REGULATOR

TDC = 14A

<Ra>

<Rb>

Vout = 1.8 * (Rb / (Ra + Rb))

64 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

73 OF 121

0.24.0

051-00673

REG_VDDQS3_PGOOD

REG_PHASE_VDDQS3_L

=PP3V3_S4_PWRCTL

PM_PGOOD_REG_VDDQ_S3

MAKE_BASE=TRUE

REG_BOOT_VDDQS3_RC

REG_SNUBBER_VDDQS3

PM_EN_LDO_DDRVTT_S0

PM_EN_REG_VDDQ_S3

=PP12V_S5_REG_VDDQ_S3

PM_EN_LDO_DDR_VTT_S0_R

=PPVDDQ_S3_LDO_DDRVTT

REG_VDDQS3_PGOOD

PGND_REG_P1V5_S3

REG_VDDQS3_TRIP

REG_V5IN_U7300

REG_VDDQS3_MODE

PM_EN_REG_VDDQ_S3_R

REG_VDDQS3_REFIN

REG_VDDQS3_VDDQSNS

=PP5V_S4_REG_VDDQ_S3

LDO_DDRVTTS0_SNS

REG_VDDQS3_VTTREF

AGND_VDDQS3

PGND_REG_P1V5_S3

PPDDRVTT_S0_LDO

REG_UGATE_VDDQS3
REG_PHASE_VDDQS3

REG_BOOT_VDDQS3

REG_VDDQS3_VREF

REG_LGATE_VDDQS3

PPVDDQ_S3_REG

SYNC_DATE=10/29/2014SYNC_MASTER=BRANCH_HCHENG

CPU & CHIPSET: CPU VDDQ VR

1

2

CASE-D2-SM

20%
2V

C7362

470UF-0.006OHM

CRITICAL

POLY

1

2

CASE-D2-SM

C7361

470UF-0.006OHM

2V

20%

POLY

CRITICAL

1

2

CASE-D2-SM

C7360

POLY

470UF-0.006OHM

2V

20%

CRITICALCRITICAL

C7321

CASE-D2-SM

1

2

2V
POLY

470UF-0.006OHM

20%

C7320

470UF-0.006OHM

CRITICAL

2

1

CASE-D2-SM

POLY

2V

20%

C7323

10UF

6.3V

20%

CERM-X6S
0402

1

2

C7322

0402

10UF

20%

6.3V

1

2

CERM-X6S

4V

20%

22UF

0603-1

1

2

X6S

C7326

1

C7325

X6S

22UF

20%

4V

0603-1

2

2

1

0402

C7302

10UF

6.3V

20%

CERM-X6SCERM-X6S

C7301

10UF

20%

6.3V

1

2

0402

X6S-CERM

10%
16V

1

2

2.2UF

0603

C7300

MF

1

2

201

1%

16.5K

1/20W

R7330

0.36UH-20%-40A-0.00076OHM

PCME104T-SM

L7310

1 2

25V

10%

0402

X6S-CERM

1UF

C7345

1

2

0402

X6S-CERM

1UF

10%
25V

C7344

1

2

OMIT

SM

1

2

PLACE_NEAR=Q7310.9:5MM

XW7317

MF

L7310.2:10MM

1/20W

201

0

5%

R7310

1 2

201

5%

1/20W

0

MF

R7341

1 2

1/20W

0

5%

MF

201

R7342

1 2

Q7310.1:4MM

2

X6S-CERM

25V

EMC

1UF

0402

10%

C7346

1

X6S-CERM

1UF

Q7310.1:3MM

10%

0402

EMC

25V

C7347

1

2

60.4K

402

MF-LF

1%

1/16W

1

2

R7336

16V

20%

180UF

TH1

CRITICAL

POLY

1

2

C7311

CRITICAL

16V

20%

POLY

180UF

TH1

1

2

C7310

6

1UF

10%

0402

X6S-CERM

25V

C7343

1

2

1UF

0402

X6S-CERM

25V

C7342

1

2

10%

CRITICAL

SON5X6

CSD58872Q5D

Q7310

5

9

3

4

1

6
7
8

L7310.2:14MM

0402

2

1000PF

EMC

25V
CERM

5%

C7341

1

89

89

1/16W

20K

MF-LF
402

5%

R7340

1

2

72

2.2

5%

1/8W

R7300

2

1

MF-LF

805

0402

CERM

1000PF

L7310.2:14MM

EMC

5%
25V

C7340

1

2

72

10%

0.1UF

0402

16V

X7R-CERM

C7330

1

2

10%

0402

0.01UF

50V
X7R-CERM

C7331

1

2

MF-LF

1%

402

2

1/16W

49.9K

R7331

1

1K

MF-LF

1%
1/16W

402

R7335

1

2

10%

CERM

16V

C7327

1

2

402

0.22UF

SM

XW7300

1

2

U7300.21:4MM

OMIT

OMIT

SM

1 2

C7325.1:6MM

XW7325

5%

0

1

2

R7316

1/10W
MF-LF

603

0.1UF

0402

25V
X6S

10%

1

2

C7316

MF
603

1/10W

1%

R7317

1

2

0.499

NOSTUFF

25V
CERM
0402

5%

1000PF

NOSTUFF

C7317

1

2

CRITICAL

TPS51916

QFN

U7300

14

11

7

19

10

20

8

17
16

13

21

18

12 15

9

2

6

3

4

1

5

64

89 71 43 42

89

89

64

64

89

64

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

VIN

BG

TG

TGR

PGND

VSW

OUT

OUT

OUT

IN

GND PAD

PGND GND

VTT THRM

VLDOIN

VBST

DRVH

VTTREF

VTTSNS

VTT

VDDQSNS

PGOOD

DRVL

SW

TRIP

MODE

S3

VREF

S5

REFIN

V5IN

www.laptoprepairsecrets.com

To regulator:

<Rb>

<Ra>

Note:

<Rb>

Vout = 0.5 * (1 + Ra / Rb)

<Ra>

TDC = 5.5A

EDC = 5.5A

VCCIO (0.95V) S0 REGULATOR

(reg_phase_vccsas0)

NOTE: CONSIDER 1UH.

PLACE NEAR GPU POWER PINS

audio frequencies

prevent noise in the

a minimum load to

Regulator requires

65 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

75 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:22 2015

=PP3V3_S0_VRD

SNS_P0V95S0_CPU_XW_P

VSS_SAIO_SENSE

REG_P0V95S0_CPU_FSEL

PM_EN_REG_VCCIO_S0_CPU_R

REG_P0V95S0_CPU_FB

PM_EN_REG_VCCIO_S0

REG_P0V95S0_CPU_SREF

REG_P0V95S0_CPU_VO

REG_BOOT_P0V95S0_CPU_RC

REG_P0V95S0_CPU_OCSET

PM_PGOOD_REG_VCCIO_S0_CPU

REG_P0V95S0_CPU_OCSET_R

REG_UGATE_P0V95S0_CPU

REG_LGATE_P0V95S0_CPU

=PP5V_S0_REG_CPUVCC_S0

REG_VCC_CPU_UA660

REG_PVCC_CPU_UA660

REG_SNUBBER_P0V95S0_CPU

REG_PHASE_P0V95S0_CPU

PM_PGOOD_REG_VCCIO_S0_CPU

VCCIO_SENSE

AGND_P0V95S0_CPU

REG_P0V95S0_CPU_VO

REG_P0V95S0_CPU_VO_R

=PP12V_S0_REG_CPUCORE

SNS_P0V95S0_CPU_XW_N

REG_P0V95S0_CPU_OCSET

REG_P0V95S0_CPU_RTN

REG_BOOT_P0V95S0_CPU_RC_TGR

REG_BOOT_P0V95S0_CPU

PPVCCIO_S0_CPU_REG

CPU & CHIPSET: CPU VCCIO VR

SYNC_DATE=08/02/2014SYNC_MASTER=J78_MLB

VR_BULKCAP:FUTURE128S0381 CAP,470uF,0.0045OHM,2.5V,SM2 C7540,C7541

VR_BULKCAP:CURRENTC7540,C75412128S0358 CAP,470uF,0.006OHM,2V,D2

1

L7530

2

2.2UH-10A

IHLP2525EZ-SM

CER-X6S

2

1

0402

C7561

2.2UF

20%
10V

2

1

0402

C7560

10%
16V

1UF

CER-X6S

C7592

1UF

2

1

0402

25V

10%
X6S-CERM

25V

10%

1UF

0402

2

1

X6S-CERM

C7593

Q7530

3

5

SON5X6

6

8

7

1

9

CSD58872Q5D

4

3 2

20%

2.5V

SM

C7541

1

470UF-0.0045OHM

POLY-TANT

CRITICAL

OMIT_TABLE

CRITICAL

470UF-0.0045OHM

3

1

2.5V

2

SM

POLY-TANT

OMIT_TABLE

C7540

20%

C7591

68UF

CASE-D2E-SM

2

1

20%

CRITICAL

POLY-TANT

16V

C7535

68UF

2

1

CASE-D2E-SM

16V
POLY-TANT

20%

CRITICAL

C7530

POLY

16V

TH1

20%

2

1

CRITICAL

180UF

5%

1

R7502

2

MF

201

0

1/20W

C7555

2

50V

5%

0402

CERM

1

10PF

50V
CERM

5%

10PF

1

C7550

2

0402

XW7581

SM

1

OMIT

2

LA630.2:1MM

XW7580

SM

2

LA630.1:1MM

OMIT

1

CERM-X6S
0402

6.3V

1

20%

2

10UF

C7543

R7551

1

402

MF-LF

1%

2

1/16W

3.32K

MF-LF
402

1/16W

3.32K

2

1

1%

R7556

NO_XNET_CONNECTION=1

R7550

402

1/16W

2

1

MF-LF

1%

3.01K

MF-LF

2

1

1%

1/16W

3.01K

R7555

NO_XNET_CONNECTION=1

402

NO_XNET_CONNECTION=1

SM

XW7550

1

2PLACE_NEAR=XWA655.2:1MM

NO_XNET_CONNECTION=1

2

XW7555

SM

1

1

0.047UF

10%
X7R-CERM

0402

2

16V

C7565

72

0

5%

1/16W

2

1

402

R7562

MF-LF

3

16

UTQFN

CRITICAL

8

11

4

14

9

15

5

6

13

2

10

7

1

U7560

ISL95870

12

1

2

SM

XW7560

UA660.1:5MM

R7560

1

5%

2

MF-LF

805

10

1/8W

MF-LF
805

2.2

5%

2

1

1/8W

R7561

0

2

1

R7536

5%
1/10W
MF-LF

603

1

2

16V
0402

C7536

X7R-CERM

10%

0.1UF

NOSTUFF

2.2

1

5%

603

MF-LF

R7537

1/10W

2

X7R-CERM

0.001UF

C7537

NOSTUFF

2

1

10%

0402

50V

1000PF

0402

CERM

5%

2

1

25V

EMC

C7533

1000PF

2

1

25V

EMC

5%

C7534

CERM
0402

R7580

14.3K

1%

1/16W

2

1

MF-LF

402

RA680.2:3MM

402

10%

1

X7R

2

C7580

0.012UF

25V

R7581

1

2

402

1/16W

1%

14.3K

LA630.2:10MM

MF-LF

0402

C7538

2

CERM

25V

5%

1000PF

1

C7531

1

2

X6S-CERM
0402

10%
25V

1UF

C7532

1UF

1

2

10%
25V
X6S-CERM
0402

MF-LF

R7538

5%

2

1

603

200

1/10W

R7522

2

1

402

MF-LF

1/16W

5%

10K

C7542

0402

2

20%

1

10UF

6.3V
CERM-X6S

73 72 65

89 85 61 60

61 8

65

65

73 72 65

89 68 63 62 61

8

65

89 68 63 62 61

65

89

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_5_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

DRAWING

VIN

BG

TG

TGR

PGND

VSW

IN

FB

EN

PGNDGND

PVCCVCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

OUT

www.laptoprepairsecrets.com

(reg_phase_p5vs4)

DCR(L7650) = 6.2 MOHM (TYP) / 6.9 MOHM (MAX)DCR(L7610) = 11.2 MOHM (TYP) / 12.5 MOHM (MAX)

(reg_phase_p3v3s5)

Vout = 0.6 * (1 + Ra / Rb)

3V3 S5 FET NON SSD

<Ra>

(reg_p3v3s4_vout)

EDC = 12.46A

3.3V S5 Regulator

TDC = 9.4A

376S0983

5V S4 Regulator

Input: 2.4V to 5.5V

EDC = 6.5A

TDC = 5.9A

<Rb>

(reg_p5vs4_isen)

(reg_p5vs4_ocset)

<Rb>

(reg_p5vs4_vout)

Vout = 0.6 * (1 + Ra / Rb)

<Ra>

(reg_p3v3s4_isen)

(reg_p3v3s4_ocset)

76 OF 121

66 OF 93

0.24.0

051-00673

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUEDIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE DIDT=TRUE

REG_BOOT_P5VS4_RC

PM_EPO_L

SMC_PM_G2_EN

PM_EN_FET_P3V3_S5_NON_SSD MAKE_BASE=TRUE

PM_PGOOD_REG_P5V_S4

=PP3V3_S5_VRD

REG_P5VS4_VOUT_R

REG_PHASE_P3V3_S5_XW

REG_P5VS4_PGOOD

REG_P3V3S5_PGOOD

=PP12V_S5_FET_P12V_S5_NON_SSD

REG_BOOT_P3V3S5_RC

=PP3V3_S5_PWRCTL

PM_PGOOD_FET_P3V3_S5

FET_EN_P3V3_S5

FET_EN_P3V3_S5_G

REG_P3V3S5_VOUT_R

PP3V3_S5_FET_NON_SSD

PM_EN_FET_P3V3_S5_NON_SSD

=PP3V3_S5_SSD_PWRCTL

REG_P3V3S5_VOUT

P3V3_G3H_SSD_R

PM_EN_REG_P5V_S4

REG_P3V3S5_FSET

REG_P3V3S5_PGOOD

REG_P5VS4_FSET

REG_VCC2_U7600

REG_LGATE_P5VS4

REG_P5VS4_ISEN

PM_EN_REG_P5V_S4_R

=PP3V3_S5_SSD_PWRCTL

PM_EPO

PP3V3_G3H_DIV

=PP12V_G3H_FET_P12V_S5_SSD

=PP3V3_G3H_SSD

PM_EN_FET_P12V_S5_SSD

=PP3V3_G3H_SSD

PM_PGOOD_FET_P12V_S5_SSD_K

REG_P5VS4_FB

REG_VIN_U7600

REG_P5VS4_PGOOD

REG_P5VS4_VOUT

REG_P3V3S5_FB

PM_EN_FET_P12V_S5_SSD

PM_PGOOD_FET_P12V_S5_SSD

REG_P3V3S5_ISEN

REG_LGATE_P3V3S5

REG_UGATE_P5VS4

REG_TGR_P5VS5

REG_BOOT_P5VS4

REG_PHASE_P3V3S5_TGR

PP5V_S5_LDO

REG_VCC1_U7600

REG_SNUBBER_P5VS4

REG_BOOT_P3V3S5

=PP3V3_S5_NON_SSD

PM_EPO_L

REG_P3V3S5_PGOOD

REG_UGATE_P3V3S5

=PP12V_S5_FET_P3V3_S5_P5V_S4

REG_PHASE_P5VS4_XW

REG_PHASE_P3V3S5

PP3V3_S5_REG_SSD

REG_SNUBBER_P3V3S5

REG_P3V3S5_OCSET

REG_XW_PP3V3_S5_XW

REG_PHASE_P5VS4

PP5V_S4_REG

P5V_S4_REG_XW

REG_P5VS4_OCSET

PLATFORM POWER: 3.3V S5/5V S4 VR

SYNC_MASTER=J95_HARPER SYNC_DATE=02/11/2015

402

21

C7658

0.012UF

X7R

25V

10%

25V
X7R

2

0402

C7618

0.022UF

1

10%

71

21

402

0

R7698

MF-LF5%

NOSTUFF

1/16W

71 66

MF
201

1

1/20W

5%

100K

2

R7688

CER-X6S

20%
16V

10UF

C7663

0603

1

2

C7662

2

1

16V

20%

CER-X6S
0603

10UF

R7659

16.2K

1/16W

1%

MF-LF

402

2

1

1 2

16.2K

R7658

1/16W

1%

MF-LF

402

C7603

1.0UF

10%

X6S

1

0402

25V

2

1UF

C7602

2

1

0402

10%
16V
CER-X6S

0603

10V

20%

X6S-CERM

10UF

1

C7601

2

0402

10%

CER-X6S

C7600

1UF

16V

1

2

1

R7673

11.8K

1%
1/16W
MF-LF
402

2

1

2

402

11.8K

R7633

MF-LF

1/16W

1%

6.3V

10%

X6S

0.1UF

C7696

1

0201

2

C7695

0.1UF

1

2

6.3V

10%

X6S
0201

C7688

1.0UF

10%

2

0402

25V
X6S

1

6.3V

10UF

CERM-X6S

2

1

0402

C7623

20%

C7622

10UF

20%

CERM-X6S

2

1

0402

6.3V

KA

BAT54XV2T1

SOD-523

D7600

Q7690

CRITICAL

PQFN3.3X3.3

5

1 2 3

4

IRFHM831PBF

2.2UH-10A-12.5MOHM

PAB0705AR-SM

21

L7650

PCMB104E-SM

2.2UH-20%-0.0058OHM-16A

L7610

1 2

20%

6.3V

2

POLY

150UF

B1A-SM-1

1

C7646

20%

POLY

6.3V

150UF

B1A-SM-1

2

1

C7647

150UF

20%

B1A-SM-1

C7648

POLY

6.3V

2

1

C7649

150UF

2

6.3V
POLY

20%

B1A-SM-1

1

6.3V

20%

150UF

2

1

C7676

POLY
B1A-SM-1

POLY

6.3V

20%

150UF

2

1

B1A-SM-1

C7674

POLY

6.3V

150UF

20%

C7671

B1A-SM-1

2

1

B1A-SM-1

POLY

6.3V

150UF

20%

2

1

C7670

33

R7679

100K

1

1/16W

5%

402

2

MF-LF

72

71 66

60 33

Q7671

1

2

SOD

3

CRITICAL

74LVC1G32

SOT891

U7640

1

4

2

6

5 3

SLG5AP022-200030V

CRITICAL

U7620

1

9

6

8

2

3

4

7

5

TDFN

71 45 44

72 71 66 60 33

2

MF-LF

1

402

R7697

5%

1/16W

0

CRITICAL

SOT665

3

TC7SZ08FEAPE

5

1

2

U7630

4

2

402

1/16W

5%

MF-LF

1

R7640

20K

71

150K

R7692

1

2

1%

MF-LF
402

1/16W

57.6K

R7694

1

2

1%
1/16W
MF-LF
402

73 72

5%

1

402

2

MF-LF

1/16W

100K

R7691

C7694

X7R-CERM

0.1UF

1

2

0402

10%
16V

402

1

2

0

MF-LF

1/16W

5%

R7693

0.022UF

1

10%

X7R-CERM
0805

50V

2

C7692

47.0K

MF-LF

2

1/16W

402

1%

1

R7644

89

CSD58872Q5D

SON5X6

7

9

4

5

8

3

Q7650

6

1

1

EMC

C7685

25V
X6S-CERM

10%

0402

1UF

2

10%

0402

1UF

C7684

X6S-CERM

EMC

1

2

25V

SON5X6

4

5

9

8

7

Q7610

1

6

CSD58872Q5D

3

20%

POLY

TH1

2

1

16V

180UF

C7690

CRITICAL

X6S-CERM

C7644

0402

10%
25V

1

EMC

2

1UF

330UF

CASE-D3L-SM

C7621

6.3V

20%

2

1

POLY-TANT

CRITICAL

NOSTUFF

2

20%

6.3V

1

CRITICAL

330UF

POLY-TANT
CASE-D3L-SM

C7620

NOSTUFF

1

X6S-CERM

0402

EMC

10%

2

25V

1UF

C7691

SM

2

1

OMIT

XW7658

XW7659

1

2

SM

OMIT

XW7618

1

2

SM

OMIT

OMIT

XW7610

2

1

SM

MF

2

5% 1/20W

201

1

0

R7646

2

0

5%

MF
201

1/20W

R7650

1

L7650.2:3.8MM

L7610.1:6MM

R7610

1/20W

0

5%

2

1

MF

201

2

1

10%

0402

16V
X7R-CERM

0.01UF

C7673C7633

10%

0.01UF

2

0402

X7R-CERM

16V

1

TH1

180UF

POLY

CRITICAL

20%
16V

C7651

1

2

20%
16V
POLY

180UF

CRITICAL

TH1

C7650

1

2

CRITICAL

20%

1

16V

180UF

POLY

2

TH1

C7610

10%
25V

C7642

X6S-CERM

0402

1UF

2

1

EMC

1UF

0402

X6S-CERM

25V

C7643

10%

1

2

EMC

25V
X6S-CERM

C7683

1

0402

EMC

2

10%

1UF

C7682

10%

2

1UF

X6S-CERM
0402

1

EMC

25V

5%

L7650.2:4MM

2

1

C7681

EMC

25V
CERM

1000PF

0402

C7641

1

1000PF

25V

5%

2

EMC

CERM
0402

2

1

EMC

L7650.2:4MM

25V

5%

1000PF

CERM
0402

C7680

89 89

20K

R7680

1/16W

2

1

MF-LF
402

5%

72 33

1

1/10W

NOSTUFF

0.499

1%

MF

603

R7617

2

0.001UF

CERM

NOSTUFF

2

1

402

10%
50V

C7617

25V

0402

CERM

5%

2

1000PF

1

EMC

C7640

72

R7603

2

1

1

1/8W
MF-LF

5%

805

89

R7602

1

2

805

MF-LF

1/8W

5%

2.2

1

25V

2

0402

10%

0.1UF

C7616

X6S

1/10W

603

1

5%

MF-LF

2

0

R7616

1/16W
MF-LF

1

R7619

1%

402

2

16.2K

R7618

MF-LF

16.2K

1

402

1%

1/16W

2

10.0K

2

1

0.5%

MF

402

R7631

1/16W

R7632

2

1

402

1%

976

1/16W
MF-LF

1000PF

2

1

5%

CERM
0402

25V

C7632

MF-LF

2

1

1%

402

1/16W

45.3K

R7630

2

1

0402

25V
CERM

1000PF

5%

C7672

2

1

R7672

976

1/16W
MF-LF

1%

402

2

1

1%
1/16W

402

10K

R7671

MF-LF

MF-LF

1/16W

75K

2

1

R7670

402

1%

X7R-CERM

0.001UF

2

1

C7675

50V

NOSTUFF

0402

10%

NOSTUFF

1/10W

0.499

R7657

MF

2

1

603

1%

C7657

0.001UF

X7R-CERM

NOSTUFF

2

50V

10%

0402

1

25V

1

X6S
0402

10%

2

0.1UF

C7656

5%

0

1

2

MF-LF

1/10W

603

R7656

4

279

22

29

1

7

19

25

26

6

3

28

8

2412

21

15

2

18

20

23

10

11

14

QFN

16

13

CRITICAL

ISL62383CRTZ

U7600

5

17

66

89 67

66

66

89

89 73 72 33

66

89 66 33

66

89 66 33

89 71

89 71 66 60

89 71 66 60

66

71 66

89

66

89

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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REVISION

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D

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

OUT

G

S

D

OUT

IN

D

S

G

NC

NC

PAD

THRM

GND

G

PG

D

VCC

S

NC

ON

IN

IN

A

B

Y

OUT

OUT

NC

OUT

VIN

BG

TG

TGR

PGND

VSW

VIN

BG

TG

TGR

PGND

VSW

NC

OUT OUT

OUT

IN

OUT

PAD

FCCM

BOOT2

VIN

PHASE1

LGATE1

ISEN2

PGOOD2

FB1

FSET1

EN2

FSET2

THRM

PGND

EN1

FB2

VOUT2

VOUT1

ISEN1

OCSET1

OCSET2

LGATE2

PHASE2

BOOT1

UGATE1

LDO5

PGOOD1

VCC1

VCC2

UGATE2

www.laptoprepairsecrets.com

TDC = 6.7A

EDC = 13.85A

PCH 1V0 SUPPLY

<Rb>

<Ra>

<Ra>

Vout = 0.5V * (1 + Ra / Rb)

<Rb>

67 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

77 OF 121

0.24.0

051-00673

SNS_1V0_S5_P

MAKE_BASE=TRUE

PM_PGOOD_REG_P1V0_S5

SNS_1V0_S5_N

REG_P1V0S5_PGOOD

REG_P1V0S5_PGOOD

REG_BOOT_P1V0S5_RC

REG_P1V0S5_FSEL

REG_P1V0S5_OCSET

REG_P1V0S5_VO

REG_TGR_P1V0S5

=PP3V3_S5_VRD

REG_UGATE_P1V0S5

REG_LGATE_P1V0S5

REG_P1V0S5_SREF

SNS_GPU_PEX_IOVDD_XW_P

SNS_GPU_PEX_IOVDD_XW_N

REG_P1V0S5_FB

REG_P1V0S5_RTN

REG_VCC_U7700

PM_EN_REG_P1V0_S5

REG_BOOT_P1V0S5

=PP5V_S5_REG_P1V0

REG_SNUBBER_P1V0S5

AGND_P1V0S5

=PP12V_S5_REG_P1V0_S5

REG_PHASE_P1V0S5

P1V0_OCSET_R

REG_P1V0S5_OCSET
REG_P1V0S5_VO

PP1V0_S5_REG

REG_P1V0S5_VO_R

CPU & CHIPSET: PCH 1V0 VR

SYNC_MASTER=J95_HARPER SYNC_DATE=02/11/2015

MF-LF

1/16W

1%

4.99K

R7725

1

2

402

1%

4.99K

1

402

R7724

2

MF-LF

1/16W

PIMB103E-SM

1 2

1.0UH-20A-2.64M-OHM

L7720

2V

20%

POLY

2

1

NOSTUFF

CASE-D2-SM

470UF-0.006OHM

C7746

CRITICAL

POLY

2V

CRITICAL

20%

470UF-0.006OHM

C7743

CASE-D2-SM

2

1

2V

C7742

CRITICAL

POLY

20%

470UF-0.006OHM

CASE-D2-SM

2

1

2

1

0402

20%

C7745

10UF

4V
X6S

2

0402

1

C7744

X6S

10UF

20%
4V

402

CERM-X7R

21

16V

10%

0.082UF

C7740

1

0603

10UF

20%

X6S-CERM

2

10V

C7734

0603

C7733

X6S-CERM

10UF

20%
10V

1

2

R7716

1/16W
MF-LF

10.2K

1

2

402

1%

R7714

10.2K

1

2

402

1/16W

1%

MF-LF

C7790

1UF

2

1

0402

EMC

10%
25V
X6S-CERM

C7791

1UF

1

2

0402

X6S-CERM

EMC

25V

10%

1

Q7720

5

3

6
7
8

SON5X6

4

CSD58872Q5D

9

C7736

POLY-TANT
CASE-D2E-SM

68UF

16V

20%

1

2

CRITICAL

1

16V

20%

2

CRITICAL

C7750

68UF

POLY-TANT
CASE-D2E-SM

C7751

16V

20%

POLY

1

2

CRITICAL

TH1

180UF

SM

XW7714

1

2PLACE_NEAR=XW7716.2:1MM

NO_XNET_CONNECTION=1

XW7716

SM

1

2

NO_XNET_CONNECTION=1

5%

CERM

50V

10PF

0402

C7731

1

2

0402

CERM

5%
50V

10PF

C7730

1

2

89

15

X7R-CERM

0.1UF

0402

10%

1

2

C7735

16V

1

R7720

0

5%

402

MF-LF

1/16W

2

R7717

MF-LF

1%
1/16W

402

10.2K

1

2

1%

402

MF-LF

1/16W

10.2K

R7715

1

2 2

16V

0.047UF

C7732

X7R-CERM

10%

0402

1

1/16W
MF-LF

200

R7740

1

2

402

5%

MF-LF

1/10W

1

5%

1

2

R7723

603

NOSTUFF

R7719

1/8W

3.3

5%

1

2

805

MF-LF

72

15

72

SM

1 2

XW7704

UTQFN

2

10

15

7

8

123

6

5

1

16

9

14

4

11

13

U7700

ISL95870

CRITICAL

1/16W

5%

402

MF-LF

10K

1

2

R7722

CERM

5%

NOSTUFF

1

25V

2

0402

1000PF

C7739

XW7705

SM

1

2

X6S-CERM

25V

10%

EMC

Q7720.1:7MM

2

1

C7737

1UF

0402

XW7706

2

SM

1

2

0402

25V

5%

1

CERM

1000PF

C7741

C7738

X6S-CERM

25V

10%

1UF

EMC

0402

Q7720.1:6MM

2

1

R7718

NOSTUFF

0201

MF

0

5%
1/20W

1

2

67

67

67

67

89

66

89

89

67

67

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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D

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

VIN

BG

TG

TGR

PGND

VSW

OUT

IN

OUT

IN

IN

FB

EN

PGNDGND

PVCCVCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

www.laptoprepairsecrets.com

TDC = 10A

EDC = 11.1A

CPU VCCSA Regulator

68 OF 93

DIDT=TRUE

DIDT=TRUE

78 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:22 2015

ISUMN_C

PP5V_S0_VRD_VCIN_C

=PP5V_S0_REG_CPUVCC_S0

THWN_C

PWM_C

BOOST_C_RC

REG_SNUBBER_CPUVCCSA

SW_C

FCCM_C

=PP12V_S0_REG_CPUCORE

ISUMP_C

BOOST_C

PHASE_C

DSBL_C

PPCPUVCCSA_S0_SENSE_1

REG_VCCSA_ISNS_1_P

REG_VCCSA_ISNS_1_N

PPVCCSA_S0_CPU_REG

CPU & CHIPSET: CPU CORE VR (VCCSA)

SYNC_DATE=02/11/2015SYNC_MASTER=J95_HARPER

R7800

43

21

0612-2

CRITICAL

1W

1%

0.0005

MF

2

1

201

R7819

1K

1%
1/20W
MF

10%

X7R
0402-1

2

25V

1

0.22UF

C7816

X6S-CERM

0603

2

1

20%
16V

10UF

C7827

2

8
9

31

1

30

5

16

7

27
33

3

29

28

12

32

4

6

24

MLP-THICKSTNCL

SIC625CD

Q7810

PCME104T-SM

0.36UH-20%-40A-0.00076OHM

L7810

21

20%

15UF

C7899

1

2

16V
TANT
SM

NOSTUFF

R7829

5%

MF-LF

1/16W

10K

1 2

402

4V

2

1

0402-1

20%
X6S-CERM

10UF

C7890

C7891

0402-1

4V

20%

10UF

X6S-CERM

2

1

NOSTUFF

CRITICAL

470UF-0.0045OHM

POLY-TANT
SM

2.5V

20%

C7893

1

23

CRITICAL

470UF-0.0045OHM

SM

POLY-TANT

20%

2.5V

C7892

1

23

61

470UF-0.0045OHM

POLY-TANT
SM

CRITICAL

20%

2.5V

C7884

1

23

NOSTUFF

470UF-0.0045OHM

2.5V

SM

CRITICAL

POLY-TANT

20%

C7885

1

23

61

NOSTUFF

20%

C7832

10UF

0402-1

X6S-CERM

4V

1

2

NOSTUFF

10UF

C7833

2

0402-1

X6S-CERM

4V

20%

1

61

5%

NO_XNET_CONNECTION=1

201

0

21

MF

1/20W

R7818

402

1

1/16W

R7827

MF-LF

5%

1 2

0402

C7828

X6S-CERM

25V

2

10%

1UF

1

R7828

21

1/16W

MF-LF

5%

10K

402

NOSTUFF

C7825

16V

CRITICAL

68UF

POLY-TANT
CASE-D2E-SM

20%

1

2

POLY-TANT

CRITICAL

1

2

C7824

68UF

20%
16V

CASE-D2E-SM

68UF

CRITICAL

16V

20%

POLY-TANT
CASE-D2E-SM

C7810

1

2

C7822

10UF

X6S-CERM
0402-1

4V

20%

1

2

C7823

0402-1

X6S-CERM

10UF

4V

20%

1

2

X6S-CERM
0402

1UF

CRITICAL

EMC

10%
25V

C7814

1

2

X6S-CERM

25V

1UF

10%

0402

CRITICAL

C7820

1

2

25V
X6S-CERM
0402

1UF

10%

CRITICAL

C7821

1

2

0402

25V

1UF

10%

X6S-CERM

CRITICAL

C7818

1

2

C7819

CRITICAL

10%
25V

0402

X6S-CERM

1UF

1

2

X6S-CERM

1UF

10%
25V

0402

CRITICAL

C7813

1

2

0402

X6S-CERM

25V

1UF

CRITICAL

10%

C7812

1

2

89

61

1/10W

1

5%

2

603

MF-LF

0

R7816

2

2.2

NOSTUFF

1/8W
MF-LF

5%

805

R7817

1

NOSTUFF

X7R-CERM

2

C7817

0.001UF

10%
50V

0402

1

CRITICAL

1

1UF

0402

25V

EMC

10%
X6S-CERM

C7815

2

89 65 63 62 61

89 65 63 62 61

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

VSWH1

GH

CGND

CGND

PGND

PGND

VDRV

VCIN

GL1

GL0

PHASE

VSWH0

BOOT

THWN

PWM

DSBL*

VIN1

VIN0

ZCD_EN*

OUT

IN

OUT

NC

NC

OUT

IN

www.laptoprepairsecrets.com

OMIT/table L8100 due to late sourcing change, did not want footprint change

Add 152s1668 (Cyntec) directly for next program

PLACE C8114 NEAR HIGHER FREQUENCY CAPS

69 OF 93

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

81 OF 121

0.24.0

051-00673

BKLT_FAULT_INT_L

LED_RETURN_6_FB

LED_RETURN_5_FB

DP_INTPNL_ML_HPD_R

GND

GND

GND

PP5V_S0_BKLT_VDDD

PP3V3_S0_BKLT_VDDIO

PP12V_S0_BKLT_PWR_R

LED_RETURN_3_FB

BKLT_ISEN5_Q

BKLT_GD_RAIL

BKLT_GD7

BKLT_SNSP_R

BLC_LSYNC_R

BKLT_GNDD

BKLT_PLL_FILT_R

BKLT_PWM_IN

BKLT_GATE_R

BKLT_GATE
BKLT_SNSP

BKLT_PLL_FILT

BKLT_VSEN4

BKLT_VSEN7

BLC_LSYNC_R

BKLT_SNUBBER

BKLT_GNDA

PP12V_S0_BKLT_PWR

BKLT_GD2

BKLT_VSEN3

BKLT_GD4

BKLT_VSEN5

BKLT_GD5

BKLT_GD6

BKLT_VSEN6

BKLT_ISEN7_Q

BKLT_GD8

BKLT_VSEN8

BKLT_GD9

BKLT_VSEN9

BKLT_DIG_TEST

BKLT_ANG_TEST

BLC_VSYNC_R

BKLT_ISEN9_Q

BKLT_GD3

BLC_VSYNC

DP_INTPNL_ML_HPD_R

BKLT_SNSN_R

BKLT_VSEN1

BKLT_PLL_FILT

BKLT_FAULT_INT_R_L

BKLT_SNSN

BKLT_SNSN_R

BKLT_ISEN8_Q

BKLT_GNDA

BKLT_NC_TEST

BKLT_ISEN6_Q

BKLT_GND_BST_GD

BKLT_GNDA

=PP5V_S0_BKLT

BKLT_SNSN

BLC_VSYNC_R

TCON_BLC_EN

BKLT_GND_BST_GD

BKLT_GNDA

BKLT_GD_RAIL

BKLT_ISEN2_Q

BKLT_GD1

BKLT_ANG_TEST
BKLT_DIG_TEST

BKLT_GD_RAIL

BKLT_NC_TEST

BKLT_GNDD

TCON_BLC_EN

BKLT_GND_BST_GD

LED_RETURN_2_FB

BKLT_SNSP_R

BKLT_BST_FB_R

BKLT_SNSP

BKLT_ISEN4_Q

BKLT_GNDD

BKLT_GNDD

=PP3V3_S0_BKLT

BKLT_ISEN3_Q

PP12V_S0_BKLT_FILT

BKLT_SHUTDOWN

BKLT_ISEN1_Q

=I2C_BKLT_SDA
=I2C_BKLT_SCL

BKLT_VSEN2

LED_RETURN_1_FB

BKLT_PHASE

=PP3V3_S0_BKLT

LED_RETURN_7_FB

BKLT_BOOST

LED_RETURN_8_FB

LED_RETURN_4_FB

BKLT_PWM_IN

PP5V_S0_BKLT_VDDD

PP3V3_S0_BKLT_VDDIO

PP5V_S0_BKLT_VDDA

PP12V_S0_BKLT_PWR_R

PP5V_S0_BKLT_VDDA

BKLT_BST_FB

BKLT_BST_SHORT_FB

BKLT_BOOST

PP12V_S0_BKLT_PWR

BKLT_GATE_R

BKLT_PHASE

BKLT_SNSP_R

BKLT_SNSN_R

BKLT_SHUTDOWN

BKLT_EN_L

GND

TCON_BLC_EN

DP_INTPNL_ML_HPD

LED_RETURN_9_FB

=PP12V_S0_BKLT PP12V_S0_BKLT_PWR

PP12V_BKLT_FUSED

PP12V_S0_BKLT_FILT

BKLT_FAULT_INT_R_L

=PP5V_S0_BKLT

BLC_LSYNC

BKLT_EN_DIV

PP12V_BKLT_SNS

SYNC_MASTER=MLB_CTO SYNC_DATE=05/14/2014

DISPLAY: LCD Backlight Driver (LP8565)

R8102

107S0359 BOOST SENSE RESISTOR107S0229

F8100

740S0146740S0145 FUSE FOR BLC

LED SINK FET376S1204 376S1106

Q8211 TO Q8219

POWERLINE FET

Q8119

376S1067376S0845

371S0783371S0782 D8101 OUTPUT DIODE

371S0731 D8103371S0748 INPUT DIODE

138S1078 138S0810 BLC OUTPUT CAPS

C8106, C8108

126-0190 CRITICALC8109, C81182

BOOST POLYMER OUTPUT CAP

CRITICAL

IC,PLP8565A13,LED BCKLGHT CTRL,7X7 QFN56

U81001353S00079

IND,PWR,33UH,20%,10A,35MOHM CRITICAL152S1668 L81001

1 2

1206-1

0.005

1/4W

1%

R8132

MF

CRITICAL

DIRECTFET-MZ

IRF6643TRPBF

NOSTUFF

Q8120

1267

5

34

1206

100V

10%

2.2UF

X7S-CERM

C8108

1

2

1206

2.2UF

X7S-CERM

100V

10%

C8106

1

2

MF-LF

5%

0

1/16W

402

NOSTUFF

R8140

1 2

CER-C0G

470PF

5%
100V

0603

C8129

1

2

CER-C0G
0603

100V

5%

470PF

C8128

1

2

470PF

5%

0603

100V
CER-C0G

C8127

1

2

470PF

CER-C0G
0603

100V

5%

C8126

1

2

470PF

100V

0603

5%

CER-C0G

C8125

1

2

100V
CER-C0G
0603

5%

470PF

C8124

1

2

470PF

5%

0603

CER-C0G

100V

C8123

1

2

CER-C0G
0603

100V

5%

470PF

C8122

1

2

CER-C0G

470PF

5%
100V

0603

C8121

1

2

10V

22UF

X5R-CERM

20%

0603

C8131

1

2

22UF

20%
10V

X5R-CERM

0603

C8137

1

2

SHORT-1206

XW8109

12

CRITICAL

25V
X7R-CERM
1206-1

10UF

10%

C8103

1

2

CRITICAL

1206-1

10UF

25V
X7R-CERM

10%

C8102

1

2

33UH-20%-10A-0.0351OHM

IHLP6767GZ-IHLP4040DZ11-SM

OMIT_TABLE

L8100

1 2

5%
1/16W
MF-LF

402

0

R8191

1 2

6AMP-32V

0603-1

F8100

1 2

10%

X7R-CERM
0603

100V

1000PF

C8111

1

2

X7R-CERM

100V

1000PF

10%

0603

C8110

1

2

R8172

1/16W

402

0

MF-LF

5%

1 2

41 40

40

40

0

5%1/16WMF-LF 402

R8173

1 2

1%

MF

200K

2011/20W

R8106

1 2

MF

201

5%

1/20W

100K

R8105

1 2

0

4025%

1/16W

MF-LF

R8171

1 2

0

5% 402MF-LF 1/16W

R8170

1 2

XW8108

SM

12

MF

5%2011/20W

10K

R8182

1 2

MF

1/20W 201 5%

10K

R8181

1 2

MF

1/20W 5%201

10K

R8180

1 2

NOSTUFF

25V

10%

X6S
0402

0.1UF

C8145

1

2

NOSTUFF

402

MF-LF

5%

0

1/16W

R8139

1 2

25V

10%

0603

1UF

X7R

C8142

1

2

0.1UF

0402

X7R-CERM

10%
16V

C8144

1

2

0402

X7R-CERM

10%
16V

0.01UF

C8143

1

2

402

5%

MF-LF

1

1/16W

R8138

1 2

1%

MF
2512-LF

0.03

2W

R8102

1

2

MF 1/20W5%201

4.7K

R8124

1 2

TH-COMBO

100V

20%

15UF

CRITICAL

ELEC

OMIT_TABLE

C8118

1

2

TH-COMBO

15UF

CRITICAL

20%
100V

OMIT_TABLE

ELEC

C8109

1

2

IRF6645PBF

DIRECTFET-SJ

Q8121

1 2 6 7

5

3 4

0402

5%
25V
CERM

1000PF

C8141

1

2

0402

1000PF

CERM

5%
25V

C8140

1

2

SOD-323

SBR130S3

D8103

A

K

1/16W

5%

0

MF-LF

402

R8125

1 2

NOSTUFF

603

100V

10%

X7R

1000PF

C8130

1

2

CRITICAL

6.3X11-TH

ELEC

20%
35V

100UF

C8114

1

2

SM

XW8106

12

1/8W

5%

20

MF-LF
805

R8114

1

2

402

1

5%
1/16W
MF-LF

R8137

1 2

16V

0402

0.1UF

10%

X7R-CERM

C8139

1

2

X7R-CERM

0.01UF

10%
16V

0402

C8138

1

2

1%
1/16W

887K

MF-LF
402

R8113

1

2

CRITICAL

160-OHM-6A

1206

FB8108

1 2

1%

887K

MF-LF
402

1/16W

R8104

1

2

NOSTUFF

100PF

C0G-CERM

5%
100V

0603

C8113

1

2

5%

NOSTUFF

4.7

603

MF-LF

1/10W

R8123

1

2

C0G-CERM

100V

5%

100PF

0603

C8120

1

2

C0G-CERM

100PF

0603

100V

5%

C8119

1

2

NOSTUFF

BAT54XV2T1

SOD-523

D8102

A

K

10%
50V

4700PF

X7R-CERM
0402

C8116

1

2

330PF

402

50V

5%

COG

C8115

1

2

MF-LF

1/16W

5%

270K

402

R8111

1

2

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

MF

NOSTUFF

10K

1/20W 201 5%

R8120

1 2

MF

NOSTUFF

5%2011/20W

10K

R8121

1 2

FDMS6681Z

POWER56

Q8119

5

4

1

2

3

10%

0.01UF

X7R-CERM

0402

16V

C8101

1

2

70

70

70

0402

1%

MF

1/8W

R8101

1

2

NOSTUFF

330K

MF

10K

1/20W 201 5%

R8107

1 2

69 45 40

1%

MF

330K

0402

1/8W

R8103

1

2

0.1UF

25V

10%

0402

X6S

C8117

1

2

47

SM

XW8105

12

0

MF-LF

5%

1/8W

805

R8119

1

2

LP8565A13RWC

OMIT_TABLE

WQFN

U8100

32

3

10

31

36

37

33

34

30

1

43

35

41

6

2

12

15

14

16

18

17

19

21

20

22

25

24

26

27

29

28

45

44

46

48

47

49

52

51

53

55

54

56

23

50

13

7

8

39

9

11

57

40

42

5

4

38

47

VS-8TQ100SPBF

TO263

D8101

3 2

1

0.01UF

10%
16V

X7R-CERM

0402

C8135

1

2

69 45 40

CRITICAL

SSM3K15AMFVAP

SOD

NOSTUFF

Q8101

3

1

2

NOSTUFF

0402

X6S

25V

10%

C8171

1

2

0.1UF

1

402

1/16W

5%

MF-LF

R8134

1 2

1/16W

5%

1

MF-LF

402

R8131

1 2

1/16W

402

0

5%

MF-LF

1

2

R8122

147K

MF-LF

NOSTUFF

402

1/16W

1%

R8133

1 2

1%

MF

1/8W

0402

330K

R8112

1

2

X7R-CERM

10%

0402

16V

0.1UF

C8136

1

2

10%

0402

0.1UF

16V

X7R-CERM

C8133

1

2

10%

X7R-CERM

0402

16V

0.01UF

C8132

1

2

10%
25V

0603

1UF

X7R

C8134

1

2

14

70

70

69

69

69

69

70

69

69

69

69

69

69

69

69

69

69

70 69

69

69

69

69

69

69

69

69

69

69

69

69

69

89 69

69

69

69 45 40

69

69

69

69

69

69

69

69

69

70

69

69

69

69

89 69

69

69

70

69

89 69

70

70 69

70

70

69

69

69

69

69

69

70 69

70 69

69

69

69

69

70

89 70 69

69

69

89 69

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

S

G

D

IN

IN

IN

D

G

S

NC

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

S

D

G

IN

OUT

IN

IN

IN

PAD

LED7_HDR

LED7_GD

LED7_R

LED3_R

SYNC

UVLO_OVP

SDA
SCL

VING

BST_GD_RAIL

NC

ANALOG_TEST
DIGITAL_TEST

FILTER

PWM

BRT_SYNC

INT

BL_EN

HPD

SD BST_GD

BST_ISENSE_P

BST_ISENSE_N

BST_FB

LED1_HDR

BST_SHORT_FB

LED1_R

LED1_GD

LED2_GD

LED2_HDR

LED2_R

VDDA

VDDIO

VDDD

LED3_GD

LED3_HDR

LED4_HDR

LED4_GD

LED4_R

LED5_HDR

LED5_R

LED5_GD

LED6_GD

LED6_HDR

LED6_R

LED8_GD

LED8_R

LED8_HDR

LED9_GD

LED9_HDR

LED9_R

GND_BST_GD

THRM

LED_GND2

LED_GND1

GNDD

GNDA

IN

IN

D

S

G

www.laptoprepairsecrets.com

. .

82 OF 121

051-00673

0.24.0

70 OF 93

BKLT_ISEN2_Q

BKLT_GD2

LED_RETURN_3_FB

PP12V_S0_BKLT_PWR

BKLT_BOOST_2

LED_RETURN_8

BKLT_BOOST_1

LED_RETURN_4
LED_RETURN_6

LED_RETURN_2

LED_RETURN_3
LED_RETURN_1

LED_RETURN_5

LED_RETURN_7

LED_RETURN_9

BKLT_GD8

LED_RETURN_8_FB

LED_RETURN_2_FB

BKLT_ISEN8_Q

BKLT_VSEN5

LED_RETURN_4_FB

LED_RETURN_3

BKLT_BOOST_1

LED_RETURN_9_FB

BKLT_BOOST_2

BKLT_ISEN4_Q

BKLT_ISEN7_Q

BKLT_ISEN9_Q

LED_RETURN_4

LED_RETURN_5

LED_RETURN_1

LED_RETURN_2

LED_RETURN_1_FB

LED_RETURN_2_FB

LED_RETURN_3_FB

BKLT_BOOST

LED_RETURN_6_FB

LED_RETURN_8_FB

LED_RETURN_8

LED_RETURN_7
LED_RETURN_6

LED_RETURN_5_FB

LED_RETURN_9_FB

BKLT_ISEN3_Q

LED_RETURN_6_FB

LED_RETURN_7_FB

BKLT_VSEN9

LED_RETURN_9

BKLT_GD1

BKLT_GD6

BKLT_ISEN5_Q

BKLT_GD7

BKLT_VSEN8

BKLT_GD9

LED_RETURN_4_FB

BKLT_VSEN7

LED_RETURN_5_FB

BKLT_VSEN4

PP12V_S0_BKLT_PWR

BKLT_VSEN2

BKLT_VSEN1

BKLT_GD5

BKLT_VSEN6

BKLT_GD3

BKLT_ISEN6_Q

BKLT_GD4

LED_RETURN_1_FB

BKLT_ISEN1_Q

BKLT_VSEN3

LED_RETURN_7_FB

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

FB8201 TO FB8211155S0797 ALL155S0831

Short Protection FET376S1256 376S1073 ALL

SYNC_DATE=05/14/2014SYNC_MASTER=MLB_CTO

DISPLAY: Backlight Driver 2

100K

1/16W

5%

402

MF-LF

R8201

1

2

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

600-OHM-25%-0.5A-0.40OHM

0603

CRITICAL

FB8209

1 2

0603

600-OHM-25%-0.5A-0.40OHM

CRITICAL

FB8208

1 2

CRITICAL

0603

600-OHM-25%-0.5A-0.40OHM

FB8207

1 2

MLP-3.3X3.3

FDMC86106LZ

Q8212

5

4

1 2 3

FDMC86106LZ

MLP-3.3X3.3

Q8213

5

4

1 2 3

FDMC86106LZ

MLP-3.3X3.3

Q8214

5

4

1 2 3

TSOP

CRITICAL

SI3440DVT1GE3

Q8201

1

2

5

63

4

FDMC86106LZ

MLP-3.3X3.3

Q8215

5

4

1 2 3

FDMC86106LZ

MLP-3.3X3.3

Q8216

5

4

1 2 3

MLP-3.3X3.3

FDMC86106LZ

Q8217

5

4

1 2 3

MLP-3.3X3.3

FDMC86106LZ

Q8218

5

4

1 2 3

MLP-3.3X3.3

FDMC86106LZ

Q8219

5

4

1 2 3

FDMC86106LZ

MLP-3.3X3.3

Q8211

5

4

1 2 3

SI3440DVT1GE3

TSOP

CRITICAL

Q8204

1

2

5

63

4

CRITICAL

SI3440DVT1GE3

TSOP

Q8205

1

2

5

63

4

CRITICAL

TSOP

SI3440DVT1GE3

Q8206

1

2

5

63

4

SI3440DVT1GE3

CRITICAL

TSOP

Q8203

1

2

5

63

4

TSOP

CRITICAL

SI3440DVT1GE3

Q8207

1

2

5

63

4

SI3440DVT1GE3

TSOP

CRITICAL

Q8208

1

2

5

63

4

SI3440DVT1GE3

CRITICAL

TSOP

Q8209

1

2

5

63

4

600-OHM-25%-0.5A-0.40OHM

CRITICAL

0603

FB8201

1 2

CRITICAL

0603

600-OHM-25%-0.5A-0.40OHM

FB8202

1 2

600-OHM-25%-0.5A-0.40OHM

CRITICAL

0603

FB8203

1 2

600-OHM-25%-0.5A-0.40OHM

0603

CRITICAL

FB8211

1 2

0603

CRITICAL

600-OHM-25%-0.5A-0.40OHM

FB8210

1 2

600-OHM-25%-0.5A-0.40OHM

CRITICAL

0603

FB8204

1 2

CRITICAL

0603

600-OHM-25%-0.5A-0.40OHM

FB8206

1 2

CRITICAL

0603

600-OHM-25%-0.5A-0.40OHM

FB8205

1 2

TSOP

SI3440DVT1GE3

CRITICAL

Q8202

1

2

5

63

4

M-RT-SM

504050-1291

J8200

13

14

1

2

3

4

5

6

7

8

9

10

11

12

1%
1/16W
MF-LF

200K

402

R8210

1 2

MF-LF

1/16W

200K

1%

402

R8209

1 2

1%
1/16W
MF-LF

200K

402

R8208

1 2

MF-LF

1/16W

200K

1%

402

R8207

1 2

MF-LF

1/16W

1%

200K

402

R8206

1 2

1%

MF-LF

200K

402

R8205

1 2

1/16W

1%

1/16W

200K

402

MF-LF

R8204

1 2

402

1%
1/16W
MF-LF

200K

R8203

1 2

402

200K

MF-LF

1%

1/16W

R8202

1 2

70 69

70 69

70

70

70

70

70

70

70

70

70

70

70

70 69

70 69

69

70 69

70

70

70 69

70

70

70

70

70

70 69

70 69

70 69

69

70 69

70 69

70

70

70

70 69

70 69

70 69

70 69

69

70

69

70 69

69

70 69

69

70 69

69

69

69

70 69

69

70 69

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

S

D

G

www.laptoprepairsecrets.com

1.0V S3 FET (??A PK / ??A AVG)

RADAR://11420274 NEW MOSFET Q8450 TO AVOID 50A 100US PULSE ON 12V S0.

24.1 A (BUDGET)

Max peak current:

Input: 2.4V to 5.5V

7.533 A (BUDGET)

Max avg current:

SMC_PM_G2_EN PD on SMC page

20.4 A (BUDGET)Max avg current:

5V S0 FET

Max peak current:

Input: 2.4V to 5.5V

2.7 A (BUDGET)

3.9 A (BUDGET)

9.733 A (BUDGET)Max peak current:

Max avg current:

RADAR://10865139 U8470 ENSURES S5_PWRGD ISN'T ASSERTED AFTER HARD SHUTDOWN.

Input: 2.4V to 5.5V

12V S5 FET

376S1125

12V S0 FET

3.3V S0 FET (4.8A PK / 3.5A AVG)

3.3V S4 FET (2.7A PK / 2.0A AVG)

12V G3H ->S5 12V SSD FET

376S0983

71 OF 93

84 OF 121

0.24.0

051-00673

P3V3_S4_EN_G

=PP3V3_S4_PWRCTL

P3V3_S0_EN_G

PM_PGOOD_FET_P3V3_S0

=PP3V3_S5_FET_P3V3_S0

PP3V3_S0_FET

=PP3V3_S0_PWRCTL

=PP3V3_S4_PWRCTL

PM_EN_FET_P12V_S5

PM_EN_FET_P12V_S0

PGOOD_FET_P12V_S0

FET_EN_P12V_S5_R

FET_EN_P12V_S0_R

FET_EN_P12V_S0

=PP12V_S5_PWRCTL

PM_PGOOD_FET_P12V_S0

PM_EPO_R_L

PP3V3_U8480

PP3V3_G3H_DIV

PM_EN_FET_P5V_S0

PP5V_S0_FET

=PP12V_S5_PWRCTL

PM_PGOOD_P3V3_S4_FET

PP12V_S0_FET

FET_EN_P12V_S5

=PP12V_G3H_FET_P12V_S5

PP12V_S5_FET

PM_PGOOD_FET_P12V_S5

PM_EN_FET_P12V_S5_SSD

PM_EN_FET_P12V_S5

PM_EPO_L

P1V_S0_EN_G

PM_EN_FET_P1V0_S3

=PP12V_S5_PWRCTL

P5V_S0_EN_G

PM_PGOOD_FET_P5V_S0

=PP5V_S4_FET_P5V_S0

=PP3V3_S4_PWRCTL

=PP3V3_S4_PWRCTL

PM_EN_FET_P3V3_S0

=PP12V_G3H_FET_P12V_S0

=PP3V3_G3H_SSD

PM_EN_FET_P3V3_S4

PP1V0_S3_FET

PM_PGOOD_FET_P1V0_S3

=PP1V0_S5_FET_PP1V0_S3

=PP3V3_S5_FET_P3V3_S4

SMC_PM_G2_EN

=PP12V_S5_FET_PWRCTL

FET_EN_P12V_S5_SSD_R

FET_EN_P12V_S5_SSD

PM_PGOOD_FET_P12V_S5_SSD

=PP12V_G3H_FET_P12V_S5_SSD

PP3V3_S4_FET

=PP12V_S5_PWRCTL

PM_PGOOD_FET_P12V_S5_SSD_R

PP12V_S5_SSD_FET

PLATFORM POWER: FET-Controlled S0 and S4

SYNC_MASTER=J17_MAX SYNC_DATE=02/11/2013

NOSTUFF

R8499

0

1/4W

MF-LF

5%

1206

21

89

R8489

12

1/20W

201

MF

5%

0

R8497

1/16W

1%

66.5K

MF-LF

1

2

402

CRITICAL

Q8490

31

PQFN3.3X3.3

2

4

IRFHM831PBF

5

SLG5AP022-200030V

8

U8490

7

5

4

3

2

6

9

1

CRITICAL

TDFN

66

1

R8496

MF-LF

5%

2

1/16W

68K

402

NOSTUFF

R8495

MF-LF

1/16W

0

1 2

5%

402

0

5%

1 2

1/16W

MF-LF

402

R8494

NOSTUFF

402

5%

1

1/16W
MF-LF

2

R8491

100K

10%

0402

X7R-CERM

0.1UF

1

C8490

16V

2

R8493

5%

2

MF-LF
402

0

1

1/16W

X7R-CERM

C8492

0.022UF

10%
50V

0805

2

1

72

R8460

10K

MF-LF

5%

1

2

1/16W

402

5

Q8460

IRFH3702TRPBF

4

PQFN

1

CRITICAL

U8460

9

8

7

5

1

4

6

3

2

SLG5AP004

DFN

CRITICAL

2

X7R-CERM
0402

16V

1

10%

0.1UF

C8460

R8488

100K

2

1

MF

1/20W

5%

201

6.3V

C8480

0.1UF

1

10%

0201

CERM-X5R

2

R8486

2 1

0

5%

MF

201

1/20W

66 45 44

72 66 60 33

CRITICAL

4

5

3

1

2

U8480

SOT665

TC7SZ08FEAPE

CRITICAL

U8450

1

9

6

8

2

3

4

7

5

TDFN

SLG5AP036

MF-LF

5%

1/16W

0

1 2

402

R8454

72

72

2

1

C8421

X7R-CERM

16V

0402

10%

0.1UF

0.1UF

16V

2

1

10%

0402

X7R-CERM

C8440

0.1UF

10%
16V
X7R-CERM

C8400

1

2

0402

2

1

C8453

0805

0.022UF

50V
X7R-CERM

10%

43

5

7621

Q8450

IRF6717MTR1PBF

DIRECTFET-MX

CRITICAL

2

1

C8473

0.022UF

50V

10%

X7R
0402

2

1

1/16W

5%

MF-LF
402

0

R8473

MF-LF

2

1

R8453

5%

0

1/16W

402

CRITICAL

SLG5AP022-200030V

TDFN

5

7

4

3

2

8

6

9

1

U8470

1

R8420

2

5%
1/16W
MF-LF
402

22K

5%

22K

402

MF-LF

1/16W

R8440

1

2

R8452

1

2

1/16W

47.0K

402

1%

MF-LF

6

Q8470

5
3

4

7
8
2
1

CRITICAL

DIRECTFET_S3C

649135PBF

89

72

Q8420

IRFH3702TRPBF

1

4

5

PQFN

CRITICAL

U8420

1

9

6

8

2

3

7

5

CRITICAL

DFN

4

SLG5AP004

SLG5AP004

DFN

CRITICAL

5

7

4

3

2

8

6

9

1

U8400

SLG5AP004

CRITICAL

DFN

U8440

5

7

4

3

2

8

6

1

9

72

72

5%

MF-LF
402

1/16W

10K

1

2

R8400

IRFH3702TRPBF

PQFN

Q8400

5

4

1

CRITICAL

Q8440

5

PQFN

4

1

IRFH3702TRPBF

CRITICAL

2

1

C8470

16V
X7R-CERM
0402

10%

0.1UF

89

72

89

2

MF-LF

1/16W

100K

R8451

1

5%

402

2

1

C8450

0402

16V
X7R-CERM

10%

0.1UF

89 71 64 43 42

72

89

89

89 72

89 71 64 43 42

71

89 72 71

66

89 72 71

89

66

71

89 72 71

72

89

89 71 64 43 42

89 71 64 43 42

89

89 66 60

89

72 3

89

89

89 33

89 66

89

89 72 71

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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REVISION

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SHEET

PAGE TITLE

C

A

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2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

G

S

D

PAD

THRM

GND

G

PG

D

VCC

S

NC

ON

OUT

NC

IN

S

D

G

PAD

ON

S

VCC

D

NC

GND

THRM

PG

G

NC

IN

IN

A

B

Y

PAD

THRM

GND

G

PG

D

VCC

S

NC

ON

OUT

OUT

S

G

D

PAD

THRM

GND

G

PG

D

VCC

S

NC

ON

G

S

D

NC

NC

NC

OUT

IN

S

D

G

PAD

ON

S

VCC

D

NC

GND

THRM

PG

G

PAD

ON

S

VCC

D

NC

GND

THRM

PG

G

PAD

ON

S

VCC

D

NC

GND

THRM

PG

G

IN

IN

S

D

G

S

D

G

NC

OUT

IN

NC

OUT

www.laptoprepairsecrets.com

1. 12V_ACDC -> 3V42G3H -> 12V_S5/12V_S5_SSD -> 3V3_S5 -> 1V0_S5 -> 5V_S4/3V3_S4 -> 1V0_S3

AMD GPU:

System:

3. 3V3_S0 -> 0V95 -> 1V8 (VDD_CT) -> GPUCORE (VDDC) -> VDDCI -> FBVDDQ

Intel CPU:

2. 1V0_S3 -> VDDQ_S3 -> 12V_S0 -> 5V_S0 -> 3V3_S0 -> GPU Rails -> VCCIO_S0-> VCC_CPU_S0 (VCCGT & VCCSA)

Halt power sequencing at S5

S5 Enable

S0 CPU Sequencing

S0 Enables

Remove Q8500 to circumvent

0.0tau (RC delay, ms):

if there is no processor.

Note:

or short gate to source.

S4 USB Enable

S4 Enables

S4 TBT S4 Port Enable

S3 ENABLE

S0 GPU SEQUENCING

0.0

Power Sequencing requirements

72 OF 93

85 OF 121

0.24.0

051-00673

PM_EN_FET_P1V0_S3

PM_EN_REG_VDDQ_S3

PM_PGOOD_FET_P1V0_S3

PM_SLP_S3_L

PM_PGOOD_REG_P5V_S4

=TBTBPWRSW_EN

PM_EN_REG_P5V_S4

CPU_SKTOCC_L

PM_PGOOD_REG_PVDDCT_S0

PM_EN_REG_CPUVCC_S0

PM_PGOOD_REG_VCCIO_S0_CPU

PM_EN_FET_P3V3_S4

PM_PGOOD_REG_VDDQ_S3

PM_PGOOD_FET_P12V_S5

PM_EN_REG_P3V3_S5

MAKE_BASE=TRUE

PM_PGOOD_FET_P3V3_S5

PM_EN_REG_VCCIO_S0

PM_PGOOD_REG_GPU_VDDQ_S0

=PP3V3_S5_PWRCTL

PM_PGOOD_GPUCORE_VDDCI

PM_SLP_S5_L

=TBTAPWRSW_EN=PP3V3_S4_TBT

PM_PGOOD_REG_P5V_S4 PM_EN_USB_PWR

=PP3V3_S5_PWRCTL

PM_PGOOD_REG_P1V0_S5

=PP3V3_S5_PWRCTL

PM_EN_REG_P1V0_S5

=PP12V_S5_PWRCTL

PM_PGOOD_REG_P0V95_S0 PM_EN_REG_PVDDCT_S0

PM_EN_REG_GPUCORE_S0

PM_EN_S4_AND

=PP3V3_S5_PWRCTL

=TBT_S0_EN

CPU_SKTOCC

=PP3V3_S0_PWRCTL

PM_PGOOD_REG_GPU_VDDCI_S0_R

PM_PGOOD_FET_P3V3_S0

PM_PGOOD_REG_GPUCORE_S0

PM_EN_S4

PM_EN_S0_RDY

PM_EPO_L

PM_EN_FET_P12V_S0

=PP3V3_S5_PWRCTL

PM_EN_FET_P3V3_S0

PM_PGOOD_FET_P12V_S0 PM_EN_FET_P5V_S0

MAKE_BASE=TRUE

PM_PGOOD_REG_GPUCORE_S0_R

PM_SLP_S4_L

PM_EN_REG_P0V95_S0

PM_PGOOD_FET_P5V_S0

PM_EN_REG_GPU_VDDQ_S0

TP_PM_EN_REG_GPU_VDDCI_S0

PM_PGOOD_REG_GPU_VDDCI_S0

PLATFORM POWER: Regulator Enables

SYNC_MASTER=J78_KENNY SYNC_DATE=12/18/2013

R8530

1

402

0

1/16W

2

MF-LF

5%

U8500

7

12

11

14

13

TSSOP-HF

74LVC08

64

61 73 65

71 3

402

1

1/16W

5%

0

MF-LF

2

R8581

2

5%

1

0

R8533

402

MF-LF

1/16W

73 66 67

R8536

21

5%

0

1/16W

402

MF-LF

67

65

CKPLUS_WAIVE=UNCONNECTED_PINS

TSSOP-HF

14

8

9

7

U8600

10

74LVC08

CKPLUS_WAIVE=UNCONNECTED_PINS

90

5%

R8544

0

MF-LF

402

1/16W

21

R8543

1/16W

5%

0

1 2

MF-LF

402

NOSTUFF

MF-LF

1/16W

5%

R8542

0

402

1 2

82

NOSTUFF

R8541

MF-LF

0

5%

1 2

402

1/16W

86

TC7SZ08FEAPE

NOSTUFF

CRITICAL

SOT665

U8520

2

1

3

5

4

NOSTUFF

CERM-X5R

6.3V

0.1UF

C8581

10%

0201

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C8580

1

2

NOSTUFF

R8512

201

100K

5%
1/20W
MF

1

2

71

71 66 60 33

2

1

C8530

6.3V
CERM-X5R
402

10%

NOSTUFF

0.47UF

85

NOSTUFF

R8540

0

1/16W
MF-LF

402

5%

1 2

87 3 88

MF-LF

21

1/16W

5%

0

402

R8539

1/16W

2

0

5%

1

MF-LF

402

R8515

85 73

89 31 30 29 27 26 19

30

29

71

R8531

2

5%
1/16W
MF-LF

0

402

1

71

88

R8538

21

1/16W
MF-LF

0

402

5%

82

CRITICAL

1

SSM3K15AMFVAP

2

3

Q8500

PLACE_SIDE=BOTTOM

SOD

71

MF-LF

1/16W

5%

402

R8537

0

1 2

30 29

TSSOP-HF

PLACE_SIDE=BOTTOM

14

3

2

1

7

U8500

74LVC08

MF-LF

2

1

R8500

1/16W

5%

402

100K 10K

MF-LF

402

2

1

R8501

5%

1/16W

6

44 32 12

71

73 45 44 36 12 6

64

14

U8500

7

10

9

8

74LVC08

TSSOP-HF

87

66

33

402

1/16W

5%

MF-LF

R8511

1

2

5%

33

MF-LF
402

1/16W

R8510

1

2

6.3V

10%

402

2

1

C8520

NOSTUFF

0.47UF

CERM-X5R

43 42 72 66 33

402

MF-LF

2

1/16W

5%

0

R8520

1

71

72 66 33

44 12

14

6

5

7

74LVC08

TSSOP-HF

4

U8500

71

10%

6.3V

0.47UF

CERM-X5R

1

2

402

C8511

NOSTUFF

C8510

10%

6.3V

0.47UF

402

CERM-X5R

NOSTUFF

1

2

71

2

1

C8500

0402

X7R-CERM

16V

10%

0.1UF

MF-LF

2

1

402

1/16W

5%

33K

R8591

R8590

1/16W

2

1

68K

5%

MF-LF
402

71

89 73 72 66 33

89 73 72 66 33

89 73 72 66 33

89 71

89 73 72 66 33

89 71

89 73 72 66 33

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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REVISION

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R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

08

OUT

OUTIN

IN

IN OUT

IN

OUT

08

OUT

IN

IN

A

B

Y

OUT

IN

OUT

IN OUT

IN

IN

OUT

OUT

IN OUT

IN OUT

D

S

G

IN

OUT

08

IN

IN

OUT

IN

IN

08

OUT

OUT

OUTIN

OUT

IN

IN

08

IN

OUT

www.laptoprepairsecrets.com

5ms minimum after all rails are valid

Delay=10ms

To SMC, for 99ms delay

ALL_SYS_PWRGD must remain low for

RSMRST# is asserted when power good from regulator is de-asserted in the

To CPU

Note:

Resume Reset

THE IMAC J78 DESIGNS DOES NOT SUPPORT DEEP SX MODES SO BOTH DPWROK AND

Asserted at least 10 ms after all suspend well power is valid

Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8

Intel Doc# 29517 Maho Bay PDG, Section 22.13

To PCH

Second

event AC is lost. Power good de-assertion should happen quickly enough

To SMC

The SMC guarantees proper assertion and de-assertion of RSMRST# for

To PCH

to allow PCH to switch suspend well to battery without excessive loading

Power on:

RSMRST# signals are shorted together

Requirements:

From SMC

to meet Intel spec.

Method:

Power off or loss of AC:

Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V

normal operation via PM_DSW_PWRGD.

First

To PCH

PCH Power Goods

Third

ALL_SYS_PWRGD,PCH_PWROK & SYS_PWROK Generation

73 OF 93

86 OF 121

0.24.0

051-00673

PM_PCH_PWROK

PM_PCH_SYS_PWROK_R PM_PCH_SYS_PWROK

PM_PGOOD_REG_VCCIO_S0_CPU

SMC_DELAYED_PWRGD

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

PM_PGOOD_REG_GPU_VDDQ_S0

PM_PGOOD_FET_P3V3_S5

MAKE_BASE=TRUE

PM_PGOOD_FET_P3V3_S5 S5_PWRGD

PM_RSMRST_PCH_L_R PM_RSMRST_PCH_L

PM_DSW_PWRGD

PM_PGOOD_SLP_S3_GPU_VDDQ_S0

PM_SLP_S3_L

PM_PGOOD_REG_CPUVCC_S0

PM_VCCST_PWRGD

PM_PGOOD_ALL

PLATFORM POWER: PM Power Good

SYNC_DATE=10/09/2013SYNC_MASTER=J78_KENNY

5%

33

MF

2

PLACE_NEAR=U8600.11:7MM

1/20W

1

R8625

201

R8624

MF-LF

1/16W

5%

402

1 2

0

72 65

R8690

12

402

NOSTUFF

0

5%

MF-LF

1/16W

R8691

2

1/16W

402

MF-LF

0

5%

1

BYPASS=U8601::5MM

C8605

0.1UF

CERM

2

1

402

10V

20%

72 45 44 36 12 6

85 72

PLACE_SIDE=BOTTOM

5

4

1

2

3

U8601

74LVC1G08GW

SOT353

45 17 12

R8621

2

402

5%
1/16W
MF-LF

1

0

1/16W

0

R8622

402

5%

MF-LF

1

2

NOSTUFF

44 3

BYPASS=U8600::5MM

C8622

2

X5R
402

1

10%

6.3V

2.2UF

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC08

TSSOP-HF

11

CKPLUS_WAIVE=UNCONNECTED_PINS

U8600

12

13

14

7

PLACE_SIDE=BOTTOM

U8600

74LVC08

TSSOP-HF

6

14

5

4

7

2

10%

X7R-CERM

C8621

0.1UF

16V

1

0402

82 39 19 12

17 8

45 44 27

61 3

CERM

2

1

C8620

BYPASS=U8600::5MM

0.1UF

20%
10V

402

14

3

2

1

7

TSSOP-HF

74LVC08

CKPLUS_WAIVE=UNCONNECTED_PINS

CKPLUS_WAIVE=UNCONNECTED_PINS

U8600

21

R8635

MF-LF

1/16W

402

0

5%

17 12

73 72 66

45 44

73 72 66 44

89 73 72 66 33

89 73 72 66 33

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

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R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

IN

A

Y

B

OUT

OUT

08

08

OUT

OUT

IN

IN

08

OUT

IN

IN

IN OUT

www.laptoprepairsecrets.com

(NONE)

(NONE)

- =PP3V3_GPU_VDD33

Power aliases required by this page:

BOM options provided by this page:

Signal aliases required by this page:

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

Page Notes

POLARITY SWAPS INTENDED ON LANES,SEE NOTES AT DIFF PAIRS.
ALL LANES ARE ALSO REVERSED, SEE ALIASES ON CSA 112

POLARITY SWAPPED!

ALL LANES ARE REVERSED (SEE ALIASES ON CSA 112), SEE DIFF PAIRS FOR POLARITY SWAP INFO

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

POLARITY SWAPPED!

ALL LANES ARE REVERSED (SEE ALIASES ON CSA 112), SEE DIFF PAIRS FOR POLARITY SWAP INFO

74 OF 93

87 OF 121

0.24.0

051-00673

PEG_D2R_N<8>

PEG_R2D_C_N<10>

=PP0V95_S0_GPU_VDDC

PEG_R2D_C_P<14>

PEG_R2D_C_N<15>

PEG_R2D_C_N<13>

PEG_R2D_C_P<2>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_P<1>

PEG_R2D_C_N<14>

PEG_R2D_C_P<12>

PEG_R2D_C_N<3>

PEG_R2D_C_N<4>

PEG_R2D_C_P<4>

PEG_R2D_C_N<2>

PEG_R2D_C_P<0>

PEG_R2D_C_N<8>

PEG_D2R_N<6>

PEG_D2R_P<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_N<4>

PEG_D2R_N<2>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<2>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_R2D_C_N<7>

PEG_R2D_C_P<7>

PEG_R2D_C_N<6>

PEG_R2D_C_P<6>

PEG_D2R_P<15>

PEG_D2R_P<11>

PEG_D2R_P<10>

PEG_R2D_C_N<5>

PEG_R2D_C_P<5>

PEG_R2D_C_P<3>

PEG_R2D_C_P<13>

PEG_R2D_C_N<12>

PEG_R2D_C_N<11>

PEG_R2D_C_P<11>

PEG_R2D_C_P<10>

PEG_R2D_C_N<9>

GPU_RESET_L

PEG_R2D_P<15>

PEG_R2D_P<14>

PEG_R2D_P<13>

PEG_R2D_P<11>

PEG_R2D_P<9>

PEG_R2D_P<7>

PEG_R2D_P<6>

PEG_R2D_P<5>

PEG_R2D_P<4>

PEG_R2D_P<3>

PEG_R2D_P<2>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_R2D_N<13>

PEG_R2D_N<12>

PEG_R2D_N<11>

PEG_R2D_N<10>

PEG_R2D_N<9>

PEG_R2D_N<7>

PEG_R2D_N<6>

PEG_R2D_N<5>

PEG_R2D_N<4>

PEG_R2D_N<3>

PEG_R2D_N<2>

PEG_R2D_N<1>

PEG_D2R_C_P<13>

PEG_D2R_C_P<12>

PEG_D2R_C_P<11>

PEG_D2R_C_P<10>

PEG_D2R_C_P<9>

PEG_D2R_C_P<7>

PEG_D2R_C_P<6>

PEG_D2R_C_P<5>

PEG_D2R_C_P<4>

PEG_D2R_C_P<2>

PEG_D2R_C_P<1>

PEG_D2R_C_P<0>

PEG_D2R_C_N<13>

PEG_D2R_C_N<12>

PEG_D2R_C_N<11>

PEG_D2R_C_N<10>

PEG_D2R_C_N<9>

PEG_D2R_C_N<8>

PEG_D2R_C_N<7>

PEG_D2R_C_N<6>

PEG_D2R_C_N<5>

PEG_D2R_C_N<4>

PEG_D2R_C_N<2>

PEG_D2R_C_N<1>

PEG_R2D_C_P<9>

PEG_R2D_C_P<8>

PEG_R2D_P<8>

PEG_R2D_N<8>

PEG_R2D_P<10>

PEG_R2D_P<12>

PEG_D2R_C_N<0>

PEG_D2R_N<5>

PEG_D2R_C_P<3>

PEG_D2R_P<8>

PEG_D2R_N<9>

PEG_D2R_C_N<3>PEG_D2R_N<3>

PEG_D2R_P<3>

PEG_D2R_N<0>

PEG_D2R_P<0>

PEG_D2R_P<14>

PEG_D2R_N<14>

PEG_D2R_N<15>

PEG_D2R_P<13>

PEG_D2R_N<13>

PEG_D2R_N<12>

PEG_D2R_P<12>

PEG_D2R_C_N<15>

PEG_D2R_C_P<15>

PEG_D2R_C_N<14>

PEG_D2R_C_P<14>

PEG_D2R_N<10>

PEG_D2R_N<11>

PEG_D2R_C_P<8>

PEG_D2R_P<9>

PEG_R2D_P<0>

GPU_RESET_R_L

=PP0V95_S0_GPU_VDDC

PEG_R2D_P<1>

PEG_R2D_N<3>

PEG_R2D_N<0>

PEG_R2D_N<1>

PEG_R2D_P<2>

PEG_R2D_N<2>

PEG_R2D_P<3>

PEG_R2D_P<4>

PEG_R2D_N<4>

PEG_R2D_P<5>

PEG_R2D_N<5>

PEG_R2D_P<6>

PEG_R2D_N<6>

PEG_R2D_P<8>

PEG_R2D_N<8>

PEG_R2D_P<9>

PEG_R2D_N<10>

PEG_R2D_P<11>

PEG_R2D_N<11>

PEG_R2D_P<12>

PEG_R2D_N<13>

PEG_R2D_P<14>

PEG_R2D_N<14>

PEG_D2R_C_P<0>

PEG_D2R_C_N<0>

PEG_D2R_C_P<1>

PEG_D2R_C_N<1>

PEG_D2R_C_P<2>

PEG_D2R_C_N<2>

PEG_D2R_C_P<3>

PEG_D2R_C_N<3>

PEG_D2R_C_P<4>

PEG_D2R_C_N<4>

PEG_D2R_C_P<5>

PEG_D2R_C_N<5>

PEG_D2R_C_P<6>

PEG_D2R_C_N<6>

PEG_D2R_C_P<7>

PEG_D2R_C_N<7>

PEG_D2R_C_P<8>

PEG_D2R_C_N<8>

PEG_D2R_C_P<9>

PEG_D2R_C_N<9>

PEG_D2R_C_P<10>

PEG_D2R_C_N<10>

PEG_D2R_C_P<11>

PEG_D2R_C_N<11>

PEG_D2R_C_P<12>

PEG_D2R_C_N<12>

PEG_D2R_C_P<13>

PEG_D2R_C_N<13>

PEG_D2R_C_P<14>

PEG_D2R_C_N<14>

PEG_D2R_C_P<15>

PEG_D2R_C_N<15>

PEG_R2D_P<10>

PEG_R2D_P<7>

PEG_R2D_N<7>

GPU_WAKE_R_L

PEG_R2D_N<14>

PEG_R2D_N<15>

PEG_R2D_N<12>

PEG_R2D_N<9>

PEG_R2D_P<13>

PEG_R2D_P<15>

PEG_R2D_C_P<15>

=PP1V8_S0_GPU_VDD

PEG_R2D_N<15>

PEG_CLK100M_N

PEG_CLK100M_P

PEG_R2D_N<0>

=PP0V95_S0_GPU_VDDC

GFX: Emerald PCIe

SYNC_DATE=08/26/2013SYNC_MASTER=J95

MF
201

4.7K

1/20W

5%

R8786

1

2

90

90

90

90

X5R6.3V20% 0201

0.22UF

GND_VOID=TRUE

C8770

1 2

X5R6.3V

0.22UF

20% 0201

GND_VOID=TRUE

C8769

1 2

X5R6.3V

0.22UF

20% 0201

GND_VOID=TRUE

C8768

1 2

X5R6.3V 020120%

0.22UF

GND_VOID=TRUE

C8767

1 2

74

74

74

74

90

90

90

90

90

90

90

90

90

90

90

90

74

74

74

74

74

11

X5R6.3V

0.22UF

20% 0201

GND_VOID=TRUE

C8766

1 2

X5R6.3V

0.22UF

20% 0201

GND_VOID=TRUE

C8765

1 2

X5R6.3V

0.22UF

0201

GND_VOID=TRUE

20%

C8764

1 2

X5R6.3V20% 0201

GND_VOID=TRUE

0.22UF

C8763

1 2

0.22UF

20% X5R6.3V 0201

GND_VOID=TRUE

C8762

1 2

0.22UF

GND_VOID=TRUE

X5R6.3V20% 0201

C8760

1 2

0.22UF

GND_VOID=TRUE

X5R6.3V20% 0201

C8761

1 2

C8758

X5R6.3V20%

GND_VOID=TRUE

0.22UF

0201

1 2

X5R6.3V20%

0.22UF

GND_VOID=TRUE

0201

C8759

1 2

74

11

74

74

74

74

74

74

74

74

C8757

X5R6.3V20%

GND_VOID=TRUE

0.22UF

0201

1 2

0.22UF

6.3V 020120%

GND_VOID=TRUE

X5R

C8755

1 2

X5R6.3V 020120%

0.22UF

GND_VOID=TRUE

C8756

1 2

X5R6.3V 020120%

0.22UF

GND_VOID=TRUE

C8734

1 2

X5R6.3V20% 0201

GND_VOID=TRUE

0.22UF

C8735

1 2

X5R6.3V 020120%

0.22UF

GND_VOID=TRUE

C8733

1 2

6.3V

0.22UF

20% 0201

GND_VOID=TRUE

X5R

C8732

1 2

74

74

74

90

90

90

90

90

90

90

90

90

X5R6.3V

0.22UF

20% 0201

C8786

1 2

GND_VOID=TRUE

X5R6.3V20% 0201

C8785

2

GND_VOID=TRUE

0.22UF

1

X5R

GND_VOID=TRUE

0201

C8784

2

6.3V20%

1

0.22UF

X5R6.3V20% 0201

C8783

1 2

GND_VOID=TRUE

0.22UF

90

90

90

90

90

90

90

90

90

90

90

90

74

74

74

74

74

X5R6.3V20% 0201

C8782

1 2

GND_VOID=TRUE

0.22UF

6.3V20% 0201

C8781

1 2

GND_VOID=TRUE

0.22UF

X5R

X5R6.3V20% 0201

C8780

1 2

GND_VOID=TRUE

0.22UF

X5R6.3V20% 0201

C8779

1 2

GND_VOID=TRUE

0.22UF

X5R6.3V20% 0201

C8778

1 2

GND_VOID=TRUE

0.22UF

6.3V X5R20% 0201

C8777

1 2

GND_VOID=TRUE

0.22UF

X5R6.3V20% 0201

0.22UF

GND_VOID=TRUE

C8776

1 2

X5R6.3V20% 0201

GND_VOID=TRUE

C8775

1 2

0.22UF

GND_VOID=TRUE

20%

0.22UF

02016.3V X5R

C8774

1 2

X5R

0.22UF

6.3V20% 0201

GND_VOID=TRUE

C8773

1 2

GND_VOID=TRUE

X5R6.3V20%

0.22UF

0201

C8772

1 2

X5R6.3V20%

0.22UF

0201

GND_VOID=TRUE

C8771

1 2

GND_VOID=TRUE

X5R6.3V

0.22UF

0201

C8751

1 2

20%

X5R6.3V

GND_VOID=TRUE

20% 0201

0.22UF

C8750

1 2

6.3V

0.22UF

20% 0201

GND_VOID=TRUE

X5R

C8749

1 2

X5R

0.22UF

GND_VOID=TRUE

20% 02016.3V

C8748

1 2

0201X5R20%

GND_VOID=TRUE

0.22UF

6.3V

C8747

1 2

GND_VOID=TRUE

X5R6.3V 020120%

0.22UF

C8731

1 2

74

74

74

74

74

74

74

74

74

74

74

X5R6.3V

GND_VOID=TRUE

0.22UF

20% 0201

C8730

1 2

X5R6.3V20%

GND_VOID=TRUE

0201

0.22UF

C8729

1 2

X5R6.3V20% 0201

GND_VOID=TRUE

0.22UF

C8727

1 2

X5R6.3V 0201

0.22UF

GND_VOID=TRUE

20%

C8728

1 2

0.22UF

6.3V X5R 0201

GND_VOID=TRUE

20%

C8725

1 2

X5R6.3V 020120%

0.22UF

GND_VOID=TRUE

C8726

1 2

0.22UF

GND_VOID=TRUE

20% 02016.3V X5R

C8724

1 2

0.22UF

GND_VOID=TRUE

020120% 6.3V X5R

C8722

1 2

6.3V

GND_VOID=TRUE

0201

0.22UF

20% X5R

C8723

1 2

90

90

90

90

90

90

90

90

90

GND_VOID=TRUE

C8721

20%

0.22UF

0201X5R6.3V

1 2

C8720

X5R 0201

GND_VOID=TRUE

20% 6.3V

0.22UF

1 2

90

90

74

74

74

74

74

74

74

74

74

74

74

0.22UF

X5R6.3V20% 0201

GND_VOID=TRUE

C8746

1 2

6.3V20%

0.22UF

0201

GND_VOID=TRUE

X5R

C8745

1 2

X5R6.3V20%

0.22UF

0201

GND_VOID=TRUE

C8744

1 2

X5R6.3V20% 0201

GND_VOID=TRUE

0.22UF

C8743

1 2

X5R6.3V20% 0201

GND_VOID=TRUE

0.22UF

C8742

1 2

0.22UF

X5R6.3V20%

GND_VOID=TRUE

C8741

1 2

0201

X5R6.3V20%

0.22UF

0201

GND_VOID=TRUE

C8740

1 2

C8739

X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201

1 2

C8738

X5R6.3V20% 0201

GND_VOID=TRUE

0.22UF

1 2

C8737

X5R6.3V20% 0201

0.22UF

GND_VOID=TRUE

1 2

C8736

GND_VOID=TRUE

X5R6.3V20% 0201

0.22UF

1 2

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

0402

20%

6.3V
CERM-X6S

10UF

C8710

1

2

X6S-CERM

1UF

10%
10V

0402

C8708

1

2

1UF

10%
10V

0402

X6S-CERM

C8707

1

2

10%

1UF

10V

0402

X6S-CERM

C8706

1

2

10UF

20%

6.3V
CERM-X6S
0402

C8712

1

2

20%

6.3V
CERM-X6S

10UF

0402

C8711

1

2

C8705

X6S-CERM
0402

10%

1UF

10V

1

2

1UF

10%
10V
X6S-CERM
0402

C8704

1

2

1UF

0402

10%
10V
X6S-CERM

C8703

1

2

1UF

X6S-CERM

10%
10V

0402

C8702

2

1

10UF

6.3V
CERM-X6S

20%

0402

C8700

1

2

0402

1UF

10V

10%

X6S-CERM

C8701

1

2

1.69K

MF1%201 1/20W

R8702

12

201 MF1K1%1/20W

R8700

12

90 80

U43

M52

AK52

N43

N42

AK50

AA44

W42

AG42

AE44

AE43

AE42

AG43

AC43

AC42

AA43

AA42

R42

L48
L47

N48
N47

R45
R44

R48
R47

U48
U47

W45
W44

W48
W47

AA48
AA47

AC45
AC44

AC48
AC47

AE48
AE47

AG45
AG44

AG48
AG47

AJ48
AJ47

AL45
AL44

AL48
AL47

L53
L51

M50

N53
N51

P52
P50

R53
R51

U53
U51

V52
V50

W53
W51

Y52
Y50

AA53
AA51

AC53
AC51

AD52
AD50

AE53
AE51

AF52
AF50

AG53
AG51

AH52
AH50

AJ51
AJ53

AR48

AU48

AN48

AN47

L43

J47

W43

U42

U44

U8700

GPU_PCIE_CALR_TX

OMIT_TABLE

216-0857-001

BGA

GPU_PCIE_CALR_RX

201 1/20W MF5%

0

R8705

12

89 87

80 79 74

74

89 87

80 79 74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

89 82 81 80 79

74

89 87 80 79 74

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

IN

PCIEXPRESS

SYM 2 OF 10

PCIE_RX0P

PERST*

NC_VSS

VSS

VSS

PCIE_VDDC

PCIE_VDDC

PCIE_VDDC

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

PCIE_VDDC

PCIE_VDDC

PCIE_VDDC

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

BIF_VDDC
BIF_VDDC

BIF_VDDC

BIF_VDDC

PCIE_PVDD_2

PCIE_PVDD_1

PCIE_CALR_RX
PCIE_CALR_TX

PCIE_REFCLKP
PCIE_REFCLKN

PCIE_RX1P

PCIE_RX3N

PCIE_RX0N

PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

PCIE_RX10P

PCIE_RX7P
PCIE_RX7N

WAKE*

CLKREQ*

www.laptoprepairsecrets.com

GPU FB DECOUPLING

BOM options provided by this page:

GPU VDDCI DECOUPLING

(NONE)

(NONE)

Power aliases required by this page:

Signal aliases required by this page:

- =PPVCORE_GPU

- =PPVDDCI_GPU

- =PP1V5_GPU_FBVDDQ

Page Notes

PLACE ALL CAPS UNDER GPU

GPU VCORE DECOUPLING

75 OF 93

88 OF 121

0.24.0

051-00673

=PPVDDCI_S0_GPU

=PPVDDCI_S0_GPU

VSNS_GPU_VSS

VSNS_GPU_VDD

=PP1V35_S0_GPU_FBVDDQ

=PPGPUCORE_S0

=PPGPUCORE_S0

=PP1V35_S0_GPU_FBVDDQ

=PPVDDCI_S0_GPU

SNS_GPU_VDDCI_N

SNS_GPU_VDDCI_P

GFX: Emerald CORE/FB POWER

SYNC_MASTER=J94 SYNC_DATE=08/26/2013

0201

CERM-X6S

1UF

20%
4V

C88B3

1

2

0201

4V

CERM-X6S

20%

1UF

C88A2

1

2

0201

20%
4V

1UF

CERM-X6S

C88B4

1

2

0201

4V

CERM-X6S

20%

1UF

C88A3

1

2

1UF

20%

0201

4V

CERM-X6S

C88B5

1

2

CERM-X6S

20%
4V

1UF

0201

C88A4

1

2

0201

CERM-X6S

4V

20%

1UF

C88B6

1

2

0201

20%
4V

CERM-X6S

1UF

C88A5

1

2

CERM-X6S

0201

1UF

4V

20%

C88B7

1

2

4V

0201

CERM-X6S

20%

1UF

C88A6

1

2

1UF

CERM-X6S

4V

20%

0201

C88B8

1

2

CERM-X6S

1UF

0201

4V

20%

C88A7

1

2

0201

CERM-X6S

4V

20%

1UF

C88B9

1

2

4V

0201

1UF

20%

CERM-X6S

C88A8

1

2

0201

20%

1UF

4V

CERM-X6S

C88C0

1

2

CERM-X6S

1UF

0201

20%
4V

C88A9

1

2

0201

CERM-X6S

4V

20%

1UF

C88C1

1

2

1UF

20%

CERM-X6S

4V

0201

C88B0

1

2

1UF

0201

4V

20%

CERM-X6S

C88B1

1

2

0201

4V

1UF

20%

CERM-X6S

C88C2

1

2

0402

2V
X6S

15UF

20%

C88C3

1

2

0402

2V
X6S

15UF

20%

C88B2

1

2

0402

15UF

20%
2V

C88A1

1

2

X6S

0402

20%

15UF

X6S

2V

C8890

1

2

1UF

20%
4V

0201

CERM-X6S

C8880

1

2

4V

CERM-X6S

0201

20%

1UF

C8891

1

2

CERM-X6S

1UF

4V

20%

0201

C8892

1

2

20%
4V

CERM-X6S

0201

1UF

C8881

1

2

CERM-X6S

4V

0201

1UF

20%

C8893

1

2

1UF

4V

20%

0201

CERM-X6S

C8882

1

2

1UF

20%
4V

0201

CERM-X6S

C8894

1

2

CERM-X6S

1UF

4V

20%

0201

C8883

1

2

20%
4V

1UF

0201

CERM-X6S

C8895

1

2

20%
4V

0201

1UF

CERM-X6S

C8884

1

2

20%

CERM-X6S

1UF

4V

0201

C8896

1

2

20%
4V

0201

CERM-X6S

1UF

C8885

1

2

20%

CERM-X6S

4V

1UF

0201

C8897

1

2

4V

20%

CERM-X6S

1UF

0201

C8886

1

2

1UF

4V

20%

CERM-X6S

0201

C8898

1

2

4V

20%

0201

1UF

CERM-X6S

C8887

1

2

0201

4V

CERM-X6S

20%

1UF

C8888

1

2

20%
4V

CERM-X6S

0201

1UF

C8899

1

2

CERM-X6S

20%

1UF

4V

0201

C88A0

1

2

CERM-X6S

20%

1UF

4V

0201

C8889

1

2

20%

15UF

0402

2V
X6S

C8870

1

2

15UF

20%
2V
X6S
0402

C8871

1

2

X6S

20%
2V

0402

15UF

C8872

1

2

20%
2V

15UF

X6S
0402

C8873

1

2

20%
2V

15UF

X6S
0402

C8874

1

2

X6S

20%

0402

2V

15UF

C8875

1

2

15UF

X6S
0402

2V

20%

C8876

1

2

2V

15UF

20%

0402

X6S

C8877

1

2

0402

X6S

20%

15UF

2V

C8878

1

2

15UF

20%

0402

X6S

2V

C8879

1

2

20%

0201

1UF

CERM-X6S

4V

C8840

1

2

1UF

CERM-X6S

0201

20%
4V

C8850

1

2

CERM-X6S

0201

4V

20%

1UF

C8851

1

2

CERM-X6S

20%

0201

1UF

4V

C8852

1

2

CERM-X6S

0201

1UF

4V

20%

C8841

1

2

CERM-X6S

20%
4V

1UF

0201

C8842

1

2

20%
4V

CERM-X6S

0201

1UF

C8853

1

2

0201

1UF

20%

CERM-X6S

4V

C8854

1

2

CERM-X6S

1UF

0201

4V

20%

C8843

1

2

0201

1UF

20%

CERM-X6S

4V

C8844

1

2

CERM-X6S

0201

1UF

20%
4V

C8855

1

2

CERM-X6S

0201

20%

1UF

4V

C8856

1

2

1UF

4V

20%

0201

CERM-X6S

C8845

1

2

1UF

4V

20%

0201

C8846

1

2

CERM-X6S

CERM-X6S

0201

4V

20%

1UF

C8857

1

2

0201

1UF

4V

20%

C8858

1

2

CERM-X6S CERM-X6S

0201

1UF

20%
4V

C8859

1

2

1UF

CERM-X6S

20%

0201

4V

C8847

1

2

1UF

20%

CERM-X6S

4V

0201

C8848

1

2

CERM-X6S

0201

4V

1UF

20%

1

2

C8849

15UF

20%

0402

2V
X6S

C8860

1

2

15UF

20%

0402

X6S

2V

C8861

1

2

15UF

20%

0402

2V
X6S

C8862

1

2

20%

1UF

CERM-X6S

0201

4V

C8830

1

2

20%

CERM-X6S

4V

1UF

0201

C8820

1

2

20%

0201

CERM-X6S

4V

1UF

C8810

1

2

20%

1UF

CERM-X6S

4V

0201

C8831

1

2

4V

20%

1UF

CERM-X6S

0201

C8832

1

2

CERM-X6S

20%
4V

1UF

0201

C8821

1

2

CERM-X6S

0201

20%
4V

1UF

C8811

1

2

CERM-X6S

1UF

4V

20%

0201

C8822

1

2

CERM-X6S

20%

1UF

0201

4V

C8812

1

2

15UF

2V

0402

20%

X6S

C8863

1

2

15UF

20%
2V

0402

X6S

C8864

1

2

15UF

20%

X6S
0402

2V

C8865

1

2

15UF

20%

0402

X6S

2V

C8866

1

2

1UF

20%

0201

CERM-X6S

4V

C8833

1

2

CERM-X6S

1UF

0201

4V

C8834

1

2

20%

20%
4V

0201

CERM-X6S

1UF

C8823

1

2

1UF

20%
4V

CERM-X6S

0201

C8813

1

2

CERM-X6S

20%

1UF

0201

4V

C8824

1

2

20%

1UF

0201

CERM-X6S

4V

C8814

1

2

1UF

20%

CERM-X6S

0201

4V

C8835

1

2

CERM-X6S

20%

1UF

0201

4V

C8836

1

2

CERM-X6S

20%
4V

1UF

0201

C8825

1

2

CERM-X6S

0201

4V

20%

1UF

C8815

1

2

CERM-X6S

20%
4V

1UF

0201

C8826

1

2

CERM-X6S

0201

1UF

4V

20%

C8816

1

2

0201

CERM-X6S

20%
4V

1UF

C8800

1

2

0201

4V

CERM-X6S

20%

1UF

C8801

1

2

4V

CERM-X6S

0201

20%

1UF

C8802

1

2

CERM-X6S

1UF

4V

20%

0201

C8803

1

2

CERM-X6S

20%

0201

1UF

4V

C8804

1

2

1UF

CERM-X6S

0201

4V

20%

C8805

1

2

CERM-X6S

0201

1UF

4V

20%

C8806

1

2

15UF

20%
2V
X6S
0402

C8867

1

2

15UF

20%
2V
X6S
0402

C8868

1

2

15UF

20%

0402

X6S

2V

1

2

C8869

20%

1UF

CERM-X6S

0201

4V

C8837

1

2

20%

1UF

0201

4V

C8838

1

2

CERM-X6S

0201

CERM-X6S

4V

20%

1UF

C8827

1

2

4V

0201

CERM-X6S

20%

1UF

C8817

1

2

1UF

20%

CERM-X6S

4V

0201

C8828

1

2

1UF

20%

CERM-X6S

0201

4V

C8818

1

2

20%

1UF

CERM-X6S

0201

4V

C8839

1

2

CERM-X6S

4V

1UF

20%

0201

C8829

1

2

CERM-X6S

20%

1UF

4V

0201

C8819

1

2

CERM-X6S

1UF

0201

20%
4V

C8807

1

2

0201

1UF

20%

CERM-X6S

4V

C8808

1

2

20%

CERM-X6S

0201

4V

1UF

C8809

1

2

MF
201

5%

1

NOSTUFF

2

1/20W

100

R8810

5%

MF
201

R8815

2

NOSTUFF

1/20W

100

1

201

1/20W

5%

100

MF

R8805

1

2

NOSTUFF

1/20W

5%

MF
201

1

2

NOSTUFF

100

R8800

86

86

82

82

216-0857-001

BGA

OMIT_TABLE

U8700

AW15
AW16

AA12
AC12
AE12
AG12
AJ12
AL12
AN12
AR12
AU12
M13
M15
M17
M19
M21
M23
M25
M27
M29
M31
M33
M35
M37
M39
AW12
N12
R12
U12
W12
BB13
BC13
BE13

F7
G15
AE9

W7

AJ9

W11

AW11

AR7
AU9

L39

AW7

BA9

BC7

L11

J13

N9

J17

G19

J21

G23

J25

G27

J29

G31

J33

G35

J37
G39
G43

J41

L19

J9

L27

U9

AN9

R7
AC7
AG7

AG11

AR11

G6

BE6

BC11

AA9

L35

AL7

BGA

216-0857-001

U8700

AV18
AW18

AA15
AA16

AJ34
AA23
AA25
AA29
AA31
AA34
AA38
AA39

AC16
AC18

AE25

AC20
AC21
AC33
AC34
AC27
AC36
AC38

AE16
AE18
AA27
AE20

Y20
AA20
AE34

AJ27
AE36
AE38

AG16
AG18
AG21
AG20
AG27

AE29

AG34
AG33
AG36
AG38

AL16
AL34

AJ16

AJ23

AJ25

AJ29

AJ31

AJ38
AE23
AE31

AL27
AJ20
AL23
AL25
AL29
AL31
AL38
AL20

AJ39
AN15
AN18

AP20
AN23
AN25
AN29
AN31

AP34

AN39
AP15
AP18
AP21
AP23
AP25
AP29
AP31
AP33
AP36
AP39
AT15
AT18
AT21
AE21
AT25
AT29
AE33
AT33
AT36
AT39
R15
R18
AE15
R21
R36
R25
R29

AE39
R39
T16
T18
T21
T23
T25
T29
T31
T33
T36
T38
V16
V18
T20
V23
V25
V29
V31
T34
V36
V38
V15
Y16
Y27

Y29
Y31
Y34
Y38
V39

OMIT_TABLE

R33

AN36

AJ15

Y23
Y25

89 75

89 75

89 85 78 77 76 75

89 75

89 75

89 85 78 77 76 75

89 75

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

SYM 8 OF 10

POWER 2

VDDR1

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

VDDCI

VDDCI

FB_VDDCI

FB_VSSCI

POWER1

SYM 7 OF 10

FB_VSSC

FB_VDDC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

www.laptoprepairsecrets.com

- =PP1V35_GPU_S0_FB

NOTE:GDDR5 MODE H MAPPING

(NONE)

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V05_GPU_PEX_IOVDD

Power aliases required by this page:

(NONE)

Page Notes

76 OF 93

90 OF 121

0.24.0

051-00673

FB_A0_CKE_L

FB_A0_CLK_P

FB_B0_A<0>

FB_B0_A<1>

FB_B0_A<2>

FB_B0_A<3>

FB_A0_DBI_L<2>

FB_A0_DBI_L<3>

FB_A0_ABI_L

FB_A0_CAS_L

FB_A0_WE_L

FB_A0_DQ<4>

FB_A0_DQ<5>

FB_A0_DQ<3>

FB_A0_RAS_L

FB_A0_EDC<0>

FB_A0_EDC<3>

FB_A1_CKE_L

FB_A1_EDC<0>

FB_A1_EDC<1>

FB_A1_ABI_L

FB_B1_DBI_L<2>

FB_A1_RAS_L

FB_A0_A<0>

FB_A0_A<1>

FB_A0_A<2>

FB_A0_A<3>

FB_A0_A<5>

FB_A0_A<6>

FB_A0_A<7>

FB_A0_A<8>

FB_A0_CS_L

FB_A0_DBI_L<0>

FB_A0_DBI_L<1>

FB_A0_DQ<0>

FB_A0_DQ<1>

FB_A0_DQ<2>

FB_A0_DQ<6>

FB_A0_DQ<7>

FB_A0_DQ<8>

FB_A0_DQ<9>

FB_A0_DQ<10>

FB_A0_DQ<11>

FB_A0_DQ<12>

FB_A0_DQ<13>

FB_A0_DQ<14>

FB_A0_DQ<15>

FB_A0_DQ<16>

FB_A0_DQ<17>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<20>

FB_A0_DQ<21>

FB_A0_DQ<22>

FB_A0_DQ<23>

FB_A0_DQ<24>

FB_A0_DQ<25>

FB_A0_DQ<26>

FB_A0_DQ<27>

FB_A0_DQ<28>

FB_A0_DQ<29>

FB_A0_DQ<30>

FB_A0_DQ<31>

FB_A0_EDC<1>

FB_A0_EDC<2>

FB_A0_WCLK_N<0>

FB_A0_WCLK_N<1>

FB_A0_WCLK_P<0>

FB_A1_A<0>

FB_A1_A<1>

FB_A1_A<2>

FB_A1_A<3>

FB_A1_A<4>

FB_A1_A<5>

FB_A1_A<6>

FB_A1_A<7>

FB_A1_A<8>

FB_A1_CLK_N

FB_A1_CLK_P

FB_A1_CS_L

FB_A1_DBI_L<0>

FB_A1_DBI_L<1>

FB_A1_DBI_L<2>

FB_A1_DBI_L<3>

FB_A1_DQ<0>

FB_A1_DQ<1>

FB_A1_DQ<2>

FB_A1_DQ<3>

FB_A1_DQ<4>

FB_A1_DQ<5>

FB_A1_DQ<6>

FB_A1_DQ<7>

FB_A1_DQ<8>

FB_A1_DQ<9>

FB_A1_DQ<10>

FB_A1_DQ<11>

FB_A1_DQ<12>

FB_A1_DQ<13>

FB_A1_DQ<14>

FB_A1_DQ<15>

FB_A1_DQ<16>

FB_A1_DQ<17>

FB_A1_DQ<18>

FB_A1_DQ<19>

FB_A1_DQ<20>

FB_A1_DQ<21>

FB_A1_DQ<22>

FB_A1_DQ<23>

FB_A1_DQ<24>

FB_A1_DQ<25>

FB_A1_DQ<26>

FB_A1_DQ<27>

FB_A1_DQ<28>

FB_A1_DQ<29>

FB_A1_DQ<30>

FB_A1_DQ<31>

FB_A1_EDC<2>

FB_A1_EDC<3>

FB_A1_CAS_L

FB_A1_WCLK_N<0>

FB_A1_WCLK_N<1>

FB_A1_WCLK_P<0>

FB_A1_WCLK_P<1>

FB_A1_WE_L

FB_B0_A<4>

FB_B0_A<5>

FB_B0_A<6>

FB_B0_A<7>

FB_B0_A<8>

FB_B0_ABI_L

FB_B0_RAS_L

FB_B0_CKE_L

FB_B0_CLK_N

FB_B0_CLK_P

FB_B0_CS_L

FB_B0_DBI_L<0>

FB_B0_DBI_L<1>

FB_B0_DBI_L<2>

FB_B0_DBI_L<3>

FB_B0_DQ<0>

FB_B0_DQ<1>

FB_B0_DQ<2>

FB_B0_DQ<3>

FB_B0_DQ<4>

FB_B0_DQ<5>

FB_B0_DQ<6>

FB_B0_DQ<7>

FB_B0_DQ<8>

FB_B0_DQ<9>

FB_B0_DQ<10>

FB_B0_DQ<11>

FB_B0_DQ<12>

FB_B0_DQ<13>

FB_B0_DQ<14>

FB_B0_DQ<15>

FB_B0_DQ<16>

FB_B0_DQ<17>

FB_B0_DQ<18>

FB_B0_DQ<19>

FB_B0_DQ<20>

FB_B0_DQ<21>

FB_B0_DQ<22>

FB_B0_DQ<23>

FB_B0_DQ<24>

FB_B0_DQ<25>

FB_B0_DQ<26>

FB_B0_DQ<27>

FB_B0_DQ<28>

FB_B0_DQ<29>

FB_B0_DQ<30>

FB_B0_DQ<31>

FB_B0_EDC<0>

FB_B0_EDC<1>

FB_B0_EDC<2>

FB_B0_EDC<3>

FB_B0_CAS_L

FB_B0_WCLK_N<0>

FB_B0_WCLK_N<1>

FB_B0_WCLK_P<0>

FB_B0_WCLK_P<1>

FB_B0_WE_L

FB_B1_A<0>

FB_B1_A<1>

FB_B1_A<2>

FB_B1_A<3>

FB_B1_A<4>

FB_B1_A<5>

FB_B1_A<6>

FB_B1_A<7>

FB_B1_A<8>

FB_B1_ABI_L

FB_B1_RAS_L

FB_B1_CKE_L

FB_B1_CLK_N

FB_B1_CLK_P

FB_B1_CS_L

FB_B1_DBI_L<0>

FB_B1_DBI_L<1>

FB_B1_DBI_L<3>

FB_B1_DQ<0>

FB_B1_DQ<1>

FB_B1_DQ<2>

FB_B1_DQ<3>

FB_B1_DQ<4>

FB_B1_DQ<5>

FB_B1_DQ<6>

FB_B1_DQ<7>

FB_B1_DQ<8>

FB_B1_DQ<9>

FB_B1_DQ<10>

FB_B1_DQ<11>

FB_B1_DQ<12>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_B1_DQ<15>

FB_B1_DQ<16>

FB_B1_DQ<17>

FB_B1_DQ<18>

FB_B1_DQ<19>

FB_B1_DQ<20>

FB_B1_DQ<21>

FB_B1_DQ<22>

FB_B1_DQ<23>

FB_B1_DQ<24>

FB_B1_DQ<25>

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<28>

FB_B1_DQ<29>

FB_B1_DQ<30>

FB_B1_DQ<31>

FB_B1_EDC<0>

FB_B1_EDC<1>

FB_B1_EDC<2>

FB_B1_EDC<3>

FB_B1_CAS_L

FB_B1_WCLK_N<0>

FB_B1_WCLK_N<1>

FB_B1_WCLK_P<0>

FB_B1_WCLK_P<1>

FB_B1_WE_L

FB_B01_VREF

FB_B0_RESET_R_LFB_BX_RESET_R_LFB_BX_RESET_LFB_AX_RESET_R_LFB_AX_RESET_L

=PP1V35_S0_GPU_FBVDDQ=PP1V35_S0_GPU_FBVDDQ

FB_B01_CALRA

FB_A0_WCLK_P<1>

FB_A01_CALRA

FB_A01_VREF

FB_A0_RESET_R_L

FB_A0_CLK_N

FB_A0_A<4>

GFX: Emerald FRAME BUFFER

SYNC_MASTER=BRANCH_FIYIN SYNC_DATE=09/18/2014

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

2

1

R9055

NOSTUFF

100

1/20W

201

MF

1%

2

1

R9054

NOSTUFF

MF-LF

1/16W

40.2

402

1%

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

21

R9001

402

1%

MF-LF

1/16W

49.9

2

1

C9055

NOSTUFF

1UF

10V

0402

10%

X6S-CERM

77

2

1

C9000

402

50V

5%

CERM

120PF

78

21

402

MF-LF

1/16W

10

1%

R9002

NOSTUFF

R9000

120

2

1

201

MF

1/20W

1%

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

77

78

77

77

77

77

2

1

R9003

201

5.1K

1%
1/20W
MF

C9005

2

1

NOSTUFF

1UF

10V
X6S-CERM

10%

0402

2

1

R9005

NOSTUFF

1%

201

1/20W

100

MF

78

2

1

R9004

NOSTUFF

1/16W

40.2

MF-LF

1%

402

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

77

77

77

77

77

78

77

77

77

77

77

78

2

1

C9050

120PF

402

50V
CERM

5%

78

78

78

78

78

78

78

78

78

78

78

78

78

78

R9051

1/16W

21

402

1%

MF-LF

49.9

21

R9052

MF-LF

1/16W

402

1%

10

2

1

R9050

NOSTUFF

MF
201

1/20W

1%

120

2

1

R9053

201

1%
1/20W
MF

5.1K

BA12L7

BM8

BN9

BA3

BB2

E3

E1

V2

U3

AR6U11

AG6AL6

AU11

AN7

AJ7

AJ6

AW10

AW6

AR10

AU7

AN6

AN11

U7

W6

AA11

AC6

L6

N6

R6

N7

U6

W10

BL5

BE3

AV2

AN1

J1

P2

AA3

AF4

AE11

BL7

BM6

BK6

BN5

BK4

BJ3

BJ1

BH4

BH2

BG3

BF4

BF2

BD4

BD2

BC3

BB4

BA1

AY4

AY2

AW3

AU3

AU1

AT4

AT2

AR3

AP4

AP2

AN3

AM4

AM2

AL3

AK4

F2

G3

H2

H4

J3

K2

K4

L3

M2

M4

N1

N3

R3

T2

T4

U1

V4

W3

Y2

Y4

AB2

AB4

AC3

AD2

AD4

AE1

AE3

AF2

AG3

AH2

AH4

AJ1

BK8

BE1

AV4

AK2

F4

P4

AA1

AJ3

AL10

AU6

AA6

R10

BA7

BA6

J7

J6

AE7AE6

AG10AC10

AJ11AA7

U8700

BGA

216-0857-001

OMIT_TABLE

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

F41

L25

F35

M41

D26
C21

G11

C5

A5

B18

C17

C41

B42

H52

J53

L17

F27F31

G17

F19

L21

F23

F11

F13

F15

G13

F17

K19

L37

F33

G29

F29

K39

F39

G37

F37

G33

L33

A9

B14

A33

B38

C45

E51

B6

C7

B8

D8

C9

B10

D10

C11

B12

D12

A13

C13

C15

B16

D16

A17

D18

C19

B20

D20

B22

D22

C23

B24

D24

A25

C25

B26

C27

B28

D28

A29

D30

C31

B32

D32

C33

B34

D34

C35

B36

D36

A37

C37

C39

B40

D40

A41

D42

C43

B44

D44

B46

D46

C47

B48

D48

A49

C49

D50

E53

F50

F52

G51

D6

D14

A21

C29

B30

D38

A45

H50

F21

K15

K31

K35

G9

F9

G41

F25G25

K23K27

G21L29

U8700

BGA

216-0857-001

OMIT_TABLE

89 85 78 77 76 75 89 85 78 77 76 75

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

NC

IN

IN

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

NC

IN

IN

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

NC

IN

IN

IN

IN

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

NC

SYM 4 OF 10

MEMORY INTERFACE

BANK B

DQB0_17

DQB0_2

MVREFDB

CLKB1*

CLKB1

CKEB1

WEB1*

RASB1*

CASB1*

CSB1_1*

CSB1_0*

ADBIB1

DDBIB1_3

DDBIB1_2

DDBIB1_1

DDBIB1_0

EDCB1_3

EDCB1_2

EDCB1_1

EDCB1_0

WCKB1_1*

WCKB1_1

WCKB1_0*

WCKB1_0

MAB1_9

MAB1_8

MAB1_7

MAB1_6

MAB1_5

MAB1_4

MAB1_3

MAB1_2

MAB1_1

MAB1_0

DQB1_31

DQB1_30

DQB1_29

DQB1_28

DQB1_27

DQB1_26

DQB1_25

DQB1_24

DQB1_23

DQB1_22

DQB1_21

DQB1_20

DQB1_19

DQB1_18

DQB1_17

DQB1_16

DQB1_15

DQB1_14

DQB1_13

DQB1_12

DQB1_11

DQB1_10

DQB1_9

DQB1_8

DQB1_7

DQB1_6

DQB1_5

DQB1_4

DQB1_3

DQB1_2

DQB1_1

DQB1_0

DRAM_RSTB

MEM_CALRB

CLKB0*

CLKB0

CKEB0

WEB0*

RASB0*

CASB0*

CSB0_1*

CSB0_0*

ADBIB0

DDBIB0_3

DDBIB0_2

DDBIB0_1

DDBIB0_0

EDCB0_3

EDCB0_2

EDCB0_1

EDCB0_0

WCKB0_1*

WCKB0_1

WCKB0_0*

WCKB0_0

MAB0_9

MAB0_8

MAB0_7

MAB0_6

MAB0_5

MAB0_4

MAB0_3

MAB0_2

MAB0_1

MAB0_0

DQB0_31

DQB0_30

DQB0_29

DQB0_28

DQB0_27

DQB0_26

DQB0_25

DQB0_24

DQB0_23

DQB0_21

DQB0_20

DQB0_19

DQB0_18

DQB0_16

DQB0_15

DQB0_14

DQB0_13

DQB0_12

DQB0_11

DQB0_10

DQB0_9

DQB0_8

DQB0_7

DQB0_6

DQB0_5

DQB0_4

DQB0_3

DQB0_1

DQB0_0

DQB0_22

IN

BI

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

SYM 3 OF 10

MEMORY INTERFACE

BANK A

MAA1_9

MAA1_8

MAA1_7

MAA1_6

MAA1_5

MAA1_4

MAA1_3

MAA1_2

MAA1_1

MAA1_0

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13

DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9

WCKA0_0
WCKA0_0*

WCKA0_1
WCKA0_1*

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

ADBIA0

CSA0_0*
CSA0_1*

CASA0*
RASA0*
WEA0*

CKEA0

CLKA0
CLKA0*

MEM_CALRA

DRAM_RSTA

DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8

DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

WCKA1_0

WCKA1_0*

WCKA1_1

WCKA1_1*

EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIA1

CSA1_0*
CSA1_1*

CASA1*
RASA1*

WEA1*

CKEA1

CLKA1

CLKA1*

MVREFDA

DQA0_14

www.laptoprepairsecrets.com

MIRRORED

NORMAL

Signal aliases required by this page:

Power aliases required by this page:

- =PP1V35_S0_GPU_FBVDD

BOM options provided by this page:

(NONE)

Page Notes

77 OF 93

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.1000

92 OF 121

0.24.0

051-00673

=PP1V35_S0_GPU_FBVDDQ

FB_A1_VREFD1

FB_A0_VREFD0

FB_A0_VREFD1

FB_A1_VREFD0

FB_A1_CAS_L

FB_A1_RAS_L

FB_A1_DQ<25>

FB_A1_DQ<31>

FB_A1_DQ<9>

FB_A1_DQ<2>

FB_A1_DQ<3>

FB_A1_DQ<10>

FB_A1_DQ<11>

FB_A1_DQ<1>

FB_A1_DQ<6>

FB_A1_DQ<5>

FB_A1_DQ<4>

FB_A1_DQ<0>

FB_A1_CLK_N

FB_A1_CLK_P

FB_A0_A<3>

FB_A0_A<4>

FB_A0_A<5>

FB_A0_A<2>

FB_A0_DQ<28>

FB_A0_DQ<26>

FB_A0_DQ<25>

FB_A0_DQ<22>

FB_A0_DQ<2>

FB_A0_DQ<7>

FB_A0_DQ<5>

FB_A0_DQ<0>

FB_A0_DQ<17>

FB_A0_DQ<21>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<16>

FB_A1_WE_L

FB_A1_CS_L

FB_A1_CKE_L

FB_A1_DQ<14>

FB_A1_DQ<13>

FB_A1_DBI_L<1>

FB_A1_DQ<7>

FB_A1_DQ<15>

FB_AX_RESET_L

FB_A1_EDC<3>

=PP1V35_S0_GPU_FBVDDQ

FB_A1_A<5>

FB_A1_A<1>

FB_A0_VREFD1

FB_A0_VREFD0

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

FB_A1_VREFD0
FB_A1_VREFD1

=PP1V35_S0_GPU_FBVDDQ

FB_A0_DQ<9>

FB_A0_A<8>

FB_A0_DQ<6>

FB_AX_RESET_L

FB_A0_A<7>

FB_A0_DQ<31>

FB_A0_DQ<24>

FB_A0_DQ<10>

FB_A0_DQ<11>

FB_A0_WE_L

FB_A0_RAS_L

FB_A0_DQ<8>

FB_A0_DQ<13>

FB_A0_DQ<12>

FB_A0_DQ<1>

FB_A0_CS_L

FB_A0_CKE_L

FB_A0_CLK_N

FB_A0_CAS_L

FB_A0_A<1>

FB_A0_DQ<14>

FB_A0_A<0>

FB_A0_A<6>

FB_A1_A<8>

FB_A1_DQ<21>

FB_A1_DQ<16>

FB_A1_DQ<19>

FB_A1_DQ<12>

FB_A1_EDC<2>

FB_A1_DQ<20>

FB_A1_DQ<17>

FB_A1_DQ<29>

FB_A1_DQ<24>

FB_A1_DQ<28>

FB_A1_DQ<26>

FB_A1_DQ<30>

FB_A1_DQ<27>

FB_A1_ABI_L

FB_A1_DQ<23>

FB_A1_A<7>

FB_A1_A<4>

FB_A1_A<3>

FB_A1_A<0>

FB_A1_DQ<22>

FB_A1_WCLK_N<1>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<0>

FB_A1_DQ<18>

FB_A1_A<2>

FB_A1_EDC<0>

FB_A0_DQ<23>

FB_A0_DQ<3>

FB_A0_DQ<29>

FB_A0_DQ<20>

FB_A0_DQ<4>

FB_A1_EDC<1>

FB_A1_A<6>

FB_A0_DBI_L<1>

FB_A0_DBI_L<3>

FB_A0_DBI_L<2>

FB_A0_DBI_L<0>

FB_A0_DQ<30>

FB_A0_DQ<27>

FB_A1_WCLK_P<0>

FB_A0_DQ<15>

FB_A0_WCLK_N<1>

FB_A0_WCLK_P<1>

FB_A0_EDC<1>

FB_A0_EDC<0>

FB_A0_EDC<2>

FB_A0_EDC<3>

FB_A0_ABI_L

FB_A1_DBI_L<0>

FB_A1_DBI_L<2>

FB_A1_DBI_L<3>

FB_A1_DQ<8>

FB_A0_WCLK_P<0>

FB_A0_WCLK_N<0>

=PP1V35_S0_GPU_FBVDDQ

FB_A0_CLK_P

FB_A1_ZQ

FB_A1_VREFC

FB_A1_VREFC

FB_A1_SEN

FB_A1_MF

FB_A0_ZQ

FB_A0_VREFC

FB_A0_VREFC

FB_A0_SEN

FB_A0_MF

SYNC_DATE=09/18/2014

GDDR5 Frame Buffer A

SYNC_MASTER=BRANCH_FIYIN

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

4V
CERM-X6S
0201

0.1UF

10%

C9272

1

2

0.1UF

0201

10%
4V
CERM-X6S

C9268

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9273

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9269

1

2

0.1UF

4V
CERM-X6S
0201

10%

C9274

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9270

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9275

1

2

4V

0201

0.1UF

CERM-X6S

10%

C9271

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9266

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9267

1

2

76

76

76

76

76

76

76

76

76

77 76

76

76

76

76

76

76

76

76

76

76

76

4V
CERM-X6S
0201

0.1UF

10%

C9225

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9224

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9223

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9222

1

2

0.1UF

4V

0201

10%

CERM-X6S

C9221

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9220

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9219

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9218

1

2

4V

0201

0.1UF

10%

CERM-X6S

C9217

1

2

0.1UF

10%

CERM-X6S

4V

0201

C9216

1

2

76

76

76

76

76

77 76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

K4G10325FG-HC03

BGA

32MX32-1.5GHZ-MFH

OMIT_TABLE

U9250

C5
L11
L14

P11

R5

R10
C10
D11

G1

G4
G11
G14

L1
L4

B1

E10

F1

F3
F12
F14

G2

G13

H3

H12

K3
B3

K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

B12

P3
P12
P14

T1

T3
T12
T14
B14

D1

D3
D12
D14

E5

J14

A10

U10

B5
L5
L10
P10
T5
T10
B10
D10
G5
G10
H1
H14
K1
K14

A1
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
A3
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
A12
R11
R12
R14
U1
U3
U12
U14
A14
C1
C3
C4
C11
C12

BGA

K4G10325FG-HC03

32MX32-1.5GHZ-MFL

OMIT_TABLE

U9200

C5
C10
D11

G1

G4
G11
G14

L1

L4
L11
L14

P11

R5

R10

B1

B3
B12
B14

D1

D3
D12
D14

E5
E10

F1

F3
F12
F14

G2

G13

H3

H12

K3

K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

P3
P12
P14

T1

T3
T12
T14

J14
A10
U10

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

32MX32-1.5GHZ-MFL

K4G10325FG-HC03

OMIT_TABLE

BGA

U9200

K4
H5
H4
K5

J5

J4

H11
K10
K11
H10

L3

J12
J11

J3

G12

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

C2
C13
R13

R2

J1

A5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

K4G10325FG-HC03

BGA

32MX32-1.5GHZ-MFH

OMIT_TABLE

U9250

H4
K5
K4
H5

J5

J4

K11
H10
H11
K10

G3

J12
J11

J3

L12

P2

P13
D13

D2

U4
U2
T4
T2
N4
N2
M4
M2
U11
U13
T11
T13
N11
N13
M11
M13
A11
A13
B11
B13
E11
E13
F11
F13
A4
A2
B4
B2
E4
E2
F4
F2

R2
R13
C13

C2

J1

A5

U5

L3

J2

J10

P4

P5

D4

D5

G12

J13

MF

1/20W

60.4

201

1%

R9251

1

2

201

1/20W

60.4

1%

MF

R9252

1

2

MF

1/20W

201

60.4

1%

R9202

1

2

MF

1/20W

201

60.4

1%

R9201

1

2

NOSTUFF

4V

1.0UF

0201

20%
X6S

PLACE_NEAR=U9250.A10:8.4MM

C9283

1

2

NOSTUFF

5.49K

1/20W
201

MF

1%

PLACE_NEAR=U9250.A10:8.4MM

R9240

1

2

NOSTUFF

2.37K

MF

1/20W
201

1%

PLACE_NEAR=U9250.A10:8.4MM

R9239

1

2

4V
X6S

1.0UF

0201

20%

PLACE_NEAR=U9250.J14:8.4MM

C9281

1

2

5.49K

MF

1/20W
201

1%

PLACE_NEAR=U9250.J14:8.4MM

R9237

1

2

2.37K

MF

1/20W
201

1%

PLACE_NEAR=U9250.J14:8.4MM

R9236

1

2

4V
0201

20%
X6S

NOSTUFF

1.0UF

PLACE_NEAR=U9250.U10:8.4MM

C9241

1

2

201

1%
MF

1/20W

5.49K

NOSTUFF

PLACE_NEAR=U9250.U10:8.4MM

R9241

1

2

2.37K

MF

1%

201

1/20W

NOSTUFF

PLACE_NEAR=U9250.U10:8.4MM

R9238

1

2

5.49K

NOSTUFF

MF

1/20W
201

1%

PLACE_NEAR=U9200.U10:8.4MM

R9235

1

2

4V
X6S

NOSTUFF

1.0UF

0201

20%

PLACE_NEAR=U9200.U10:8.4MM

C9240

1

2

NOSTUFF

MF

1/20W
201

1%

2.37K

PLACE_NEAR=U9200.U10:8.4MM

R9234

1

2

0201

20%
X6S

4V

NOSTUFF

1.0UF

PLACE_NEAR=U9200.A10:8.4MM

C9233

1

2

5.49K

NOSTUFF

201

MF

1%
1/20W

PLACE_NEAR=U9200.A10:8.4MM

R9233

1

2

2.37K

NOSTUFF

MF

1/20W
201

1%

PLACE_NEAR=U9200.A10:8.4MM

R9232

1

2

1.0UF

X6S

4V
0201

20%

PLACE_NEAR=U9200.J14:8.4MM

C9231

1

2

201

5.49K

MF

1/20W

1%

PLACE_NEAR=U9200.J14:8.4MM

R9231

1

2

2.37K

MF

1/20W
201

1%

PLACE_NEAR=U9200.J14:8.4MM

R9230

1

2

MF

1%

201

1/20W

1K

R9254

1

2

4V
X6S

1.0UF

0201

20%

C9215

1

2

4V
X6S
0201

20%

1.0UF

C9214

1

2

0201

4V
X6S

1.0UF

20%

C9213

1

2

0201

4V
X6S

1.0UF

20%

C9212

1

2

1.0UF

4V
X6S

20%

0201

C9211

1

2

4V
X6S

1.0UF

0201

20%

C9210

1

2

20%
4V
X6S
0201

1.0UF

C9209

1

2

4V
X6S

1.0UF

0201

20%

C9208

1

2

0201

20%

X6S

1.0UF

4V

C9207

1

2

0201

4V
X6S

1.0UF

20%

C9206

1

2

4V
X6S

1.0UF

20%

0201

C9265

1

2

4V
X6S

1.0UF

0201

20%

C9264

1

2

4V
X6S

1.0UF

0201

20%

C9263

1

2

4V
X6S

1.0UF

0201

20%

C9262

1

2

4V
X6S

1.0UF

0201

20%

C9261

1

2

4V
X6S

1.0UF

0201

20%

C9260

1

2

4V
X6S

1.0UF

0201

20%

C9259

1

2

4V
X6S

1.0UF

0201

20%

C9258

1

2

4V
X6S

1.0UF

0201

20%

C9257

1

2

4V
X6S

1.0UF

0201

20%

C9256

1

2

PLACE_NEAR=U9250.J13:8.4MM

1/20W

1%

120

201

MF

R9250

1

2

201

MF

1%

PLACE_NEAR=U9250.J10:8.4MM

1/20W

1K

R9253

1

2

201

PLACE_NEAR=U9200.J13:8.4MM

120

MF

1/20W

1%

R9200

1

2

201

MF

1K

1/20W

1%

R9204

1

2

PLACE_NEAR=U9200.J10:8.4MM

1/20W

201

1K

MF

1%

R9203

1

2

X6S
0402

4.7UF

6.3V

20%

C9254

1

2

X6S
0402

4.7UF

6.3V

20%

C9253

1

2

0402

6.3V

10UF

20%

CERM-X6S

C9251

1

2

20%

10UF

0402

CERM-X6S

6.3V

C9250

1

2

X6S
0402

20%

4.7UF

6.3V

C9204

1

2

20%

0402

4.7UF

X6S

6.3V

C9203

1

2

20%

10UF

0402

CERM-X6S

6.3V

C9201

1

2

20%

10UF

0402

CERM-X6S

6.3V

C9200

1

2

89 85 78 77 76 75

77

77

77

77

89 85 78 77 76 75

77

77

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

77

77

89 85 78 77 76 75

89 85

78 77

76 75

77

77

77

77

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

NC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

(2 OF 2)

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

(2 OF 2)

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

(MF=0)

(1 OF 2)

NC

A12/RFU/NC

ZQ

WCK01

DQ24

DQ31

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7
A9/A1

DBI2*

WE*

BA2/A4
BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

NC

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

(1 OF 2)

(MF=1)

NC

DQ30

A12/RFU/NC

NC

DQ20

DQ18

RESET*

ABI*

A8/A7

BA3/A3

DBI1*
DBI2*
DBI0*
DBI3*

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ10

DQ15

DQ17

DQ21
DQ22

DQ29

DQ28

BA0/A2

ZQ

WE*

WCK23*

WCK23

RAS*

MF

EDC2

EDC1

DQ31

DQ27

DQ26

DQ25

DQ23

DQ19

DQ16

DQ14

DQ11

DQ9

CS*

CKE*

CK*

CAS*

BA2/A4

BA1/A5

A9/A1

CK

DQ24

DQ12
DQ13

DQ0

A10/A0

EDC0

EDC3

WCK01
WCK01*

SEN

A11/A6

www.laptoprepairsecrets.com

- =PP1V35_S0_GPU_FBVDD

(NONE)

Signal aliases required by this page:

Page Notes

(NONE)

Power aliases required by this page:

BOM options provided by this page:

MIRRORED

NORMAL

78 OF 93

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2500

93 OF 121

0.24.0

051-00673

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

FB_B0_EDC<0>

FB_B0_EDC<1>

FB_B0_ABI_L

FB_B0_EDC<2>

FB_B0_WCLK_P<0>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1>

FB_BX_RESET_L

FB_B0_DQ<6>

FB_B0_DQ<5>

FB_B0_DQ<7>

FB_B0_DQ<4>

FB_B0_DQ<9>

FB_B0_DQ<13>

=PP1V35_S0_GPU_FBVDDQ

FB_B0_DQ<26>

FB_B0_DQ<27>

FB_B0_DQ<24>

FB_B0_DQ<25>

FB_B0_DQ<21>

FB_B0_DQ<29>

FB_B0_A<7>

FB_B1_A<6>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1>

FB_B1_WCLK_N<1>

FB_B1_CAS_L

FB_B1_ABI_L

FB_B0_RAS_L

FB_B0_CS_L

FB_B1_DQ<13>

FB_B1_DQ<15>

FB_B1_EDC<2>

FB_B0_CKE_L

FB_B0_VREFD1

FB_B0_VREFD0

FB_B0_CAS_L

FB_B0_WCLK_N<1>

FB_B0_DQ<28>

FB_B0_A<2>

FB_B0_A<3>

FB_B0_WE_L

FB_B0_A<1>

FB_B0_CLK_N

FB_B0_CLK_P

FB_B0_DQ<16>

FB_B1_VREFD1

FB_B1_VREFD0

FB_B1_WCLK_P<0>

FB_B1_EDC<0>

FB_B1_A<0>

FB_B1_DQ<0>

FB_B1_DQ<16>

FB_B1_A<5>

FB_B1_A<4>

FB_B1_DQ<25>

FB_B1_DQ<29>

FB_B1_DQ<31>

FB_B1_DQ<17>

FB_B1_DQ<19>

FB_B1_DQ<18>

FB_B1_DQ<23>

FB_B1_RAS_L

FB_B1_A<2>

FB_B1_DQ<20>

FB_B1_DQ<22>

FB_B1_DQ<27>

FB_B1_DQ<30>

FB_B1_DQ<10>

FB_B1_DBI_L<2>

FB_B1_DBI_L<3>

FB_B1_DBI_L<1>

FB_B1_A<3>

FB_B1_A<7>

FB_BX_RESET_L

FB_B1_DQ<24>

FB_B1_A<8>

FB_B1_DQ<21>

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_S0_GPU_FBVDDQ

FB_B1_DQ<11>

FB_B1_DQ<12>

FB_B1_A<1>

FB_B1_EDC<3>

FB_B1_CKE_L

=PP1V35_S0_GPU_FBVDDQ

FB_B0_DQ<22>

FB_B0_DQ<19>

FB_B0_DQ<30>

FB_B0_A<5>

FB_B0_DQ<12>

FB_B0_A<4>

FB_B0_EDC<3>

FB_B0_A<6>

FB_B0_A<0>

FB_B1_DBI_L<0>

FB_B0_DQ<18>

FB_B0_DQ<20>

FB_B0_DQ<23>

FB_B0_DQ<31>

FB_B0_A<8>

FB_B1_DQ<9>

FB_B1_DQ<8>

FB_B1_DQ<6>

FB_B0_DBI_L<3>

FB_B0_DBI_L<1>

FB_B0_DBI_L<0>

FB_B0_DBI_L<2>

FB_B0_DQ<17>

FB_B1_CLK_P

FB_B1_CLK_N

FB_B1_CS_L

FB_B1_WE_L

=PP1V35_S0_GPU_FBVDDQ

FB_B0_DQ<3>

FB_B0_DQ<8>

FB_B0_DQ<11>

FB_B0_DQ<0>

FB_B0_DQ<2>

FB_B0_DQ<10>

FB_B0_DQ<14>

FB_B0_DQ<15>

FB_B0_DQ<1>

FB_B1_EDC<1>

FB_B1_DQ<14>

FB_B1_DQ<1>

FB_B1_DQ<3>

FB_B1_DQ<4>

FB_B1_DQ<5>

FB_B1_DQ<7>

FB_B1_DQ<2>

FB_B1_DQ<28>

FB_B1_DQ<26>

FB_B0_VREFD0

FB_B0_VREFD1

FB_B1_VREFD1FB_B1_VREFD0

FB_B1_ZQ

FB_B1_VREFC

FB_B1_VREFC

FB_B1_SEN

FB_B1_MF

FB_B0_ZQ

FB_B0_VREFC

FB_B0_VREFC

FB_B0_SEN

FB_B0_MF

SYNC_MASTER=BRANCH_FIYIN SYNC_DATE=09/18/2014

GDDR5 Frame Buffer B

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

4V
CERM-X6S
0201

0.1UF

10%

C9372

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9368

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9373

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9369

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9374

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9370

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9375

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9371

1

2

CERM-X6S

4V

0201

0.1UF

10%

C9366

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9367

1

2

76

76

76

76

76

76

76

76

76

78 76

76

76

76

76

76

76

76

76

76

76

76

4V
CERM-X6S
0201

0.1UF

10%

C9325

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9324

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9323

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9322

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9321

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9320

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9319

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9318

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9317

1

2

4V
CERM-X6S
0201

0.1UF

10%

C9316

1

2

76

76

76

76

76

201

120

PLACE_NEAR=U9300.J13:8.4MM

MF

1/20W

1%

R9300

1

2

78 76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

32MX32-1.5GHZ-MFL

K4G10325FG-HC03

BGA

OMIT_TABLE

U9300

C5
C10
D11

G1

G4
G11
G14

L1

L4
L11
L14

P11

R5

R10

B1

B3
B12
B14

D1

D3
D12
D14

E5
E10

F1

F3
F12
F14

G2

G13

H3

H12

K3

K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

P3
P12
P14

T1

T3
T12
T14

J14
A10
U10

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

32MX32-1.5GHZ-MFH

K4G10325FG-HC03

BGA

OMIT_TABLE

U9350

C5
L11
L14

P11

R5

R10
C10
D11

G1

G4
G11
G14

L1
L4

B1

E10

F1

F3
F12
F14

G2

G13

H3

H12

K3
B3

K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

B12

P3
P12
P14

T1

T3
T12
T14
B14

D1

D3
D12
D14

E5

J14

A10

U10

B5
L5
L10
P10
T5
T10
B10
D10
G5
G10
H1
H14
K1
K14

A1
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
A3
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
A12
R11
R12
R14
U1
U3
U12
U14
A14
C1
C3
C4
C11
C12

32MX32-1.5GHZ-MFL

K4G10325FG-HC03

OMIT_TABLE

BGA

U9300

K4
H5
H4
K5

J5

J4

H11
K10
K11
H10

L3

J12
J11

J3

G12

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

C2
C13
R13

R2

J1

A5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

K4G10325FG-HC03

BGA

OMIT_TABLE

32MX32-1.5GHZ-MFH

U9350

H4
K5
K4
H5

J5

J4

K11
H10
H11
K10

G3

J12
J11

J3

L12

P2

P13
D13

D2

U4
U2
T4
T2
N4
N2
M4
M2
U11
U13
T11
T13
N11
N13
M11
M13
A11
A13
B11
B13
E11
E13
F11
F13
A4
A2
B4
B2
E4
E2
F4
F2

R2
R13
C13

C2

J1

A5

U5

L3

J2

J10

P4

P5

D4

D5

G12

J13

1/20W

60.4

MF
201

1%

R9351

1

2

MF

1/20W

201

60.4

1%

R9352

1

2

60.4

MF

1/20W

201

1%

R9301

1

2

60.4

MF

1/20W

201

1%

R9302

1

2

PLACE_NEAR=U9350.A10:8.4MM

NOSTUFF

4V
X6S

1.0UF

0201

20%

C9383

1

2

NOSTUFF

PLACE_NEAR=U9350.A10:8.4MM

5.49K

MF

1/20W

201

1%

R9340

1

2

PLACE_NEAR=U9350.A10:8.4MM

2.37K

NOSTUFF

MF

1/20W

201

1%

R9339

1

2

PLACE_NEAR=U9350.J14:8.4MM

4V
X6S

1.0UF

0201

20%

C9381

1

2

PLACE_NEAR=U9350.J14:8.4MM

5.49K

MF

1/20W

201

1%

R9337

1

2

PLACE_NEAR=U9350.J14:8.4MM

201

MF

2.37K

1/20W

1%

R9336

1

2

PLACE_NEAR=U9350.U10:8.4MM

NOSTUFF

4V
X6S

1.0UF

0201

20%

C9341

1

2

PLACE_NEAR=U9350.U10:8.4MM

NOSTUFF

5.49K

MF

1/20W

201

1%

R9341

1

2

PLACE_NEAR=U9350.U10:8.4MM

2.37K

NOSTUFF

MF

1/20W

201

1%

R9338

1

2

PLACE_NEAR=U9300.U10:8.4MM

5.49K

NOSTUFF

MF

1/20W

201

1%

R9335

1

2

PLACE_NEAR=U9300.U10:8.4MM

NOSTUFF

4V
X6S

1.0UF

0201

20%

C9340

1

2

PLACE_NEAR=U9300.U10:8.4MM

2.37K

NOSTUFF

MF

1/20W

201

1%

R9334

1

2

PLACE_NEAR=U9300.A10:8.4MM

NOSTUFF

4V
X6S

1.0UF

0201

20%

C9333

1

2

PLACE_NEAR=U9300.A10:8.4MM

5.49K

NOSTUFF

MF

1/20W

201

1%

R9333

1

2

PLACE_NEAR=U9300.A10:8.4MM

2.37K

NOSTUFF

MF

1/20W

201

1%

R9332

1

2

PLACE_NEAR=U9300.J14:8.4MM

4V
X6S

1.0UF

0201

20%

C9331

1

2

PLACE_NEAR=U9300.J14:8.4MM

5.49K

MF

1/20W

201

1%

R9331

1

2

PLACE_NEAR=U9300.J14:8.4MM

2.37K

MF

1/20W

201

1%

R9330

1

2

1/20W

1K

MF

1%

201

R9354

1

2

4V
X6S

1.0UF

0201

20%

C9365

1

2

4V
X6S

1.0UF

0201

20%

C9364

1

2

4V
X6S

1.0UF

0201

20%

C9363

1

2

4V
X6S

1.0UF

0201

20%

C9362

1

2

4V
X6S

1.0UF

0201

20%

C9361

1

2

4V
X6S

1.0UF

0201

20%

C9360

1

2

4V
X6S

1.0UF

0201

20%

C9359

1

2

4V
X6S

1.0UF

0201

20%

C9358

1

2

4V
X6S

1.0UF

0201

20%

C9357

1

2

4V
X6S

1.0UF

0201

20%

C9356

1

2

4V
X6S

1.0UF

0201

20%

C9315

1

2

4V
X6S

1.0UF

0201

20%

C9314

1

2

20%
4V
X6S

1.0UF

0201

C9313

1

2

4V
X6S

1.0UF

0201

20%

C9312

1

2

4V
X6S

1.0UF

0201

20%

C9311

1

2

4V
X6S

1.0UF

0201

20%

C9310

1

2

4V
X6S

1.0UF

0201

20%

C9309

1

2

4V
X6S

1.0UF

0201

20%

C9308

1

2

4V
X6S

1.0UF

0201

20%

C9307

1

2

4V
X6S

1.0UF

0201

20%

C9306

1

2

MF

201

1%

1/20W

PLACE_NEAR=U9350.J13:8.4MM

120

R9350

1

2

1%

1/20W

PLACE_NEAR=U9350.J10:8.4MM

MF

201

1K

R9353

1

2

PLACE_NEAR=U9300.J10:8.4MM

MF

1/20W

201

1%

1K

R9303

1

2

MF

1%

201

1K

1/20W

R9304

1

2

X6S
0402

4.7UF

6.3V

20%

C9354

1

2

X6S
0402

4.7UF

6.3V

20%

C9353

1

2

6.3V
CERM-X6S
0402

10UF

20%

C9351

1

2

6.3V
CERM-X6S
0402

10UF

20%

C9350

1

2

X6S
0402

4.7UF

6.3V

20%

C9303

1

2

X6S
0402

4.7UF

6.3V

20%

C9304

1

2

0402

6.3V
CERM-X6S

10UF

20%

C9301

1

2

6.3V
CERM-X6S
0402

10UF

20%

C9300

1

2

76

76

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

89 85

78 77

76 75

78

78

78

78

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

89 85 78 77 76 75

78

78

78 78

78

78

78

78

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

NC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

(2 OF 2)

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

(2 OF 2)

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

(MF=0)

(1 OF 2)

NC

A12/RFU/NC

ZQ

WCK01

DQ24

DQ31

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7
A9/A1

DBI2*

WE*

BA2/A4
BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

NC

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

(1 OF 2)

(MF=1)

NC

DQ30

A12/RFU/NC

NC

DQ20

DQ18

RESET*

ABI*

A8/A7

BA3/A3

DBI1*
DBI2*
DBI0*
DBI3*

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ10

DQ15

DQ17

DQ21
DQ22

DQ29

DQ28

BA0/A2

ZQ

WE*

WCK23*

WCK23

RAS*

MF

EDC2

EDC1

DQ31

DQ27

DQ26

DQ25

DQ23

DQ19

DQ16

DQ14

DQ11

DQ9

CS*

CKE*

CK*

CAS*

BA2/A4

BA1/A5

A9/A1

CK

DQ24

DQ12
DQ13

DQ0

A10/A0

EDC0

EDC3

WCK01
WCK01*

SEN

A11/A6

BI

IN

www.laptoprepairsecrets.com

(NONE)

- J5:YES

- J31:YES

- =PP3V3_GPU_IFPX_PLLVDD

- =PP1V8_GPU_IFPA_IOVDD

- =PP1V8_GPU_DPLL

BOM options provided by this page:

- =PP3V3_GPU_IFPB_IOVDD

Power aliases required by this page:

Signal aliases required by this page:

- =PP1V05_GPU_IFPEF_IOVDD

- =PP1V05_GPU_IFPCD_IOVDD

- =PP3V3_GPU_VDD33

Page Notes

- =PP1V05_GPU_DPLL

79 OF 93

96 OF 121

0.24.0

051-00673

DP_INT_EG_SL_P<0>

DP_INT_EG_ML_AUX_N

DP_INT_EG_SL_P<3>

DP_INT_EG_SL_N<2>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_EG_DDC2DATA

DP_TBTSNK1_EG_DDC2CLK

DP_INT_EG_ML_P<2>

DP_INT_EG_ML_N<0>

DP_INT_EG_ML_P<0>

DP_INT_EG_SL_N<3>

DP_INT_EG_SL_P<2>

DP_INT_EG_SL_N<1>

DP_INT_EG_SL_P<1>

DP_INT_EG_SL_N<0>

DP_INT_EG_ML_AUX_N

DP_INT_EG_ML_AUX_P

DP_INT_EG_SL_AUX_N

DP_INT_EG_SL_AUX_P

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

GPU_DPEF_CALR

GPU_DPCD_CALR

DP_INT_EG_SL_AUX_P

GPU_DPAB_CALR

=PP0V95_S0_GPU_VDDC

=PP1V8_S0_GPU_VDD

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_N<3>

DP_TBTSNK1_AUX_C_P

DP_TBTSNK1_AUX_C_N

DP_TBTSNK0_EG_DDC1DATA

DP_TBTSNK0_AUX_C_P

DP_TBTSNK0_AUX_C_N

DP_TBTSNK0_EG_DDC1CLK

DP_INT_EG_ML_N<2>

DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<1>

DP_INT_EG_SL_AUX_N

DP_INT_EG_ML_AUX_P

DP_TBTSNK0_AUX_C_P

DP_TBTSNK0_AUX_C_N

DP_TBTSNK1_AUX_C_P

DP_TBTSNK1_AUX_C_N

SYNC_DATE=08/26/2013SYNC_MASTER=J94

GFX: Emerald IntDP/TBT DP

26

41

41

41

41

41

41

41

41

2

1

C9610

CERM-X6S

6.3V

0402

20%

10UF

2

1

10%
10V

0402

X6S-CERM

1UF

C9605

2

1

C9604

0402

1UF

10V

10%

X6S-CERM

2

1

C9600

0402

X6S-CERM

1UF

10V

10%

2

1

C9601

10%

X6S-CERM

1UF

0402

10V

2

1

C9602

10V
X6S-CERM
0402

1UF

10%

0402

2

1

C9603

X6S-CERM

1UF

10%
10V

2

1

R9620

1%
1/16W

150

402

MF-LF

2

1

R9610

1/16W
MF-LF

1%

150

402

1

R9600

1%

MF-LF

150

402

1/16W

2

100K

5%
1/20W

PLACE_NEAR=U8700.BN45:5MM

R9631

NOSTUFF

MF
201

2

1

31

31

NOSTUFF

1

R9632

PLACE_NEAR=U8700.BL37:5MM

100K

5%
1/20W
MF
201

2

1

NOSTUFF

201

2

PLACE_NEAR=U8700.BN37:5MM

100K

5%

MF

1/20W

R9633

1

100K

MF
201

1/20W

5%

2

PLACE_NEAR=U8700.BK30:5MM

NOSTUFF

R9636

1

NOSTUFF

R9637

100K

1/20W

5%

MF
201

2

PLACE_NEAR=U8700.BM30:5MM

1

NOSTUFF

5%
1/20W

100K

2

MF

PLACE_NEAR=U8700.BM22:5MM

201

R9635

201

MF

2

5%

1

PLACE_NEAR=U8700.BK22:5MM

1/20W

100K

NOSTUFF

R9634

31

79 26

79 26

31

40

79 41

79 41

79 40

79 40

79 26

79 26

26

26

26

26

26

26

26

26

NOSTUFF

2

1/20W

R9630

201

100K

1

5%

PLACE_NEAR=U8700.BL45:5MM

MF

2

1

C9613

10UF

20%

CERM-X6S

6.3V

0402

6.3V

2

1

C9612

0402

20%

CERM-X6S

10UF

2

1

C9611

0402

10UF

20%

6.3V
CERM-X6S

40

40

40

40

40

40

40

26

26

26

26

26

26

26

BN33

BN35

BB52
BB50

BM22

BE51

BC53
BC51

BD52

AJ42

BA49

AV50

BL45

BM46

BN45

OMIT_TABLE

216-0857-001

BGA

U8700

BL31
BN31

BN37

BL37

BE49

BE48

AR51

AR53

AJ43
AJ44

AL42
AN42
AN43
AN44
AR42
AR43

AW42

AU44

AW43

AU42
AU43
BA42
AR44

AW44

BM42

BM28

BN39

BL39

BM40

BM26

BK40

BK26

BN41

BN27

BL41

BL27

BN47

AW51

BL47

BL33

AW53

BM48

BM34

BK48

BK34

AV52

BN49

AU51

BL49

AU53

BM38

BK38

BM32

BK32

BF52

AY50

AY52

AT50

AT52

BK46

BF50

BD50

BE53

BM24

BK22

BN23

BL35

BL23

BM30

BK30

BN25

BL25

BK24

79 41

79 40

89 87 80 74

89 82 81 80 74

79 40

79 41

79 26

79 26

79 26

79 26

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

OUT

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

TMDP E/F

TMDP A/B

SYM 6 OF 10

TMDP C/D

DPAB_CALR

DPCD_CALR

DPEF_CALR

TX2P_DPA0P

TX2M_DPA0N

TX1P_DPA1P

TX1M_DPA1N

TX0P_DPA2P

TX0M_DPA2N

TXCAP_DPA3P

TXCAM_DPA3N

DDCAUX3P

DDCAUX3N

TX5P_DPB0P

TX5M_DPB0N

TX4P_DPB1P

TX4M_DPB1N

TX3P_DPB2P

TX3M_DPB2N

TXCBP_DPB3P

TXCBM_DPB3N

DDCAUX4P

DDCAUX4N

TX2P_DPC0P

TX2M_DPC0N

TX1P_DPC1P

TX1M_DPC1N

TX0P_DPC2P

TX0M_DPC2N

TXCCP_DPC3P

TXCCM_DPC3N

AUX1P

AUX1N

DDC1CLK

DDC1DATA

TX5P_DPD0P

TX5M_DPD0N

TX4P_DPD1P

TX4M_DPD1N

TX3P_DPD2P

TX3M_DPD2N

TXCDP_DPD3P

TXCDM_DPD3N

AUX2P

AUX2N

DDC2CLK

DDC2DATA

TXOUT_L3P
TXOUT_L3N

TX2P_L2P_DPE0P

TX2M_L2N_DPE0N

TX1P_L1P_DPE1P

TX1M_L1N_DPE1N

TX0P_L0P_DPE2P

TX0M_L0N_DPE2N

TXCEP_LP_DPE3P

TXCEM_LN_DPE3N

DDCAUX5P

DDCAUX5N

TXOUT_U3P

TXOUT_U3N

TX5P_U2P_DPF0P

TX5M_U2N_DPF0N

TX4P_U1P_DPF1P

TX4M_U1N_DPF1N

TX3P_U0P_DPF2P

TX3M_U0N_DPF2N

TXCFP_UP_DPF3P

TXCFM_UN_DPF3N

DDCAUX6P

DDCAUX6N

DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

www.laptoprepairsecrets.com

Signal aliases required by this page:

GPU JTAG PU/PD RESISTORS

BACO MODE, NOT USED

GPU Overtemp Masking

Power aliases required by this page:

- =PP1V05_GPU_PEX_IOVDD

- =PP1V05_GPU_PEX_PLLVDD

- =PP1V8_GPU

OVERTEMP CONDITIONS DURING POWER-UP

PROVIDES PROTECTION AGAINST FALSE

Y9700 ENOUGH CLEARANCE FROM

PLACE R9716,C9726,R9717,C9727
AWAY FROM HEATSINK BRACKET

GIVE R9718,R9719,C9728,C9729

(NONE)

(NONE)

BOM options provided by this page:

GPU CONFIG STRAPS - BOOT FROM EFI

U8700, GPU'S EDGE FOR REWORK

GPU ROM

1 = EMERALD
0 = NEPTUNE

NOTE: NC = AMETHYST

To PCH GPIO

80 OF 93

97 OF 121

0.24.0

051-00673

=PP1V8_S0_GPU_VDD

=PP0V95_S0_GPU_VDDC

=PP1V8_S0_GPU_VDD

GPU_CLKB_RC GPU_CLKA_RC

GFX_PS_3GFX_PS_1

GFX_PS_0

GFX_PS_2

=PP1V8_S0_GPU_VDD

GFX_PCH_THRMTRIP

GPU_RESET_L

GFX_SMC_CTF_R

=PP3V3_S0_GPU

GFX_SMC_ALERT_R

=PP1V8_S0_GPU_VDD

GPU_ROM_HOLD_L

GPU_ROM_WP_L

GPU_ROM_SCK_R

GPU_ROM_SI_R

=PP3V3_S0_GPU

SMC_GFX_THROTTLE_R_L

=PP3V3_S0_GPU

GPU_JTAG_TCK

GPU_JTAG_TSTEN

GPU_JTAG_TDO

GPU_JTAG_TDI

=PP3V3_S0_GPU

GPU_JTAG_TRST_L

GPU_JTAG_TMS

GPU_XTAL_RC

=PP1V8_S0_GPU_VDD

GPU_IS_EMERALD

GPU_ROM_CS_R_L

=PP3V3_S0_GPU

GPU_ROM_SO_RGPU_ROM_SO

GPU_ROM_SCK_R

DP_LINK_OK

GPU_ROM_SI_R

SMC_GFX_THROTTLE_L

GPU_FBVDDQ_ALTV_R

GPU_ROM_CS_R_L

GFX_OK_L

GFX_SMC_CTF_R

GFX_SMC_ALERT_R

GPU_VDDCI_ALTV_R

GPU_JTAG_TRST_L

GPU_JTAG_TCK

GPU_JTAG_TSTEN

SMC_GFX_THROTTLE_R_L

GPU_ROM_SO_R

GPU_ROM_SI

GFX_SMC_ALERT

GPU_VDDCI_ALTV

GPU_FBVDDQ_ALTV

GFX_SMC_CTF

GPU_ROM_CS_L

DP_LINK_OK_R

GFX_0K_R

DP_TBTSNK1_HPD

GENERICF_HPD5

GENERICG_HPD6

DP_INT_EG_SL_HPD

GPU_DIGON

GPU_VARY_BL

=PP3V3_S0_GPU

=PP1V8_S0_GPU_VDD

GFX_PS_1

GPU_TESTPG

GPU_XO_IN

GPU_OSC_27M_XTALIN

GPU_OSC_27M_XTALOUT

GPU_CLKTESTA

PP0V95_GPU_SPLLVDDC

GPU_TDIODE_P

GPU_GPIO28

GPU_TDIODE_N

GFX_PS_3

DP_INT_EG_ML_HPD

GFX_PS_0

VR_GPU_SVT

VR_GPU_SVC

GFX_SMBCLK_B

GFX_SMBDAT_B

VR_GPU_SVD

GFX_PS_2

PP1V8_GPU_SPLLPVDD

AGND_GPU_SPLLPVDD

=PP1V8_S0_GPU_VDD

PP1V8_GPU_MPLLPVDD

GPU_XO_IN2

DP_TBTSNK0_HPD

GPU_ROM_SCK

VR_GPU_VRDHOT_L

MAKE_BASE=TRUE

GPU_NEPTUNE_EMERALD_ID

GPU_PLL_ANALOGOUT

GPU_CLKTESTB

GPU_PLL_ANALOGIN

GPU_JTAG_TDI

GPU_JTAG_TMS

GPU_JTAG_TDO

SYNC_MASTER=J94 SYNC_DATE=08/26/2013

GFX: Emerald GPIOS,CLK,STRAPS

91 14

1

33

R9758

201MF1/20W5%

2

MF

1/20W

10K

5%

201

2

1

R9757

PLACE_NEAR=U1100.BA41:25MM

R9798

201

2

10K

1/20W5% MF

1

45 3

201MF

R9756

21

33

1/20W5%

45 3

47

47

5%

2

1

R9779

MF

1/20W

10K

201

44

2

1/20W

R9755

1

201MF5%

33

2

1

C9706

402

6.3V

0.68UF

10%

CERM

2

1

C9704

6.3V

402

CERM

0.68UF

10%

5%

2

1

R9728

201

1K

MF

1/20W

2

1

C9720

0402

6.3V

20%

10UF

CERM-X6S

C9732

2

1

0402

CERM-X6S

6.3V

20%

10UF

2

1

C9717

0402

CERM-X6S

10UF

20%

6.3V

1

5%

MF

10K

201

2

R9727

1/20W

1

2

1/20W

5%

10K

201

MF

R9724

R9732

5%

2

1

1/20W

NOSTUFF

201

10K

MF

U9701

NOSTUFF

2

M25P10A

UFDFPN8

94

3

8

1

7

5

6

NOSTUFF

10K

201

5%

2

1

R9731

1/20W
MF

NOSTUFF

R9733

5%

2

1

MF
201

1/20W

10K 10K

1/20W
201

R9734

NOSTUFF

1

5%

2

MF

CERM-X5R

6.3V

2

10%

NOSTUFF

C9731

0201

1

0.1UF

PLACE_NEAR=U9701.2:8MM

R9735

MF

NOSTUFF

21

1/20W5%

201

33

2

NOSTUFF

R9754

10K

5% MF1/20W 201

1

NOSTUFF

5% 1/20W MF 201

2

10K

R9753

1

R9746

33

1

201MF5%21/20W

5%

33

201

R9750

1 2

1/20W MF

NOSTUFF

R9748

33

1 2

5% MF1/20W 201

R9747

33

2

5%11/20W MF 201

R9740

1/20W MF5% 201

NOSTUFF

33

21

33

2

5% MF1/20W 201

NOSTUFF

1

R9739

1

33

2

5%

R9737

MF1/20W 201

PLACE_NEAR=U5000.F3:8MM

2

1

C9702

CERM

0.68UF

6.3V

402

10%

NOSTUFF

2

1

C9700

16V

10%

CERM-X7R

0.082UF

402

40

26

SHORT-0201

21

XW9700

1

TP9709

2

1

C9723

X6S-CERM
0402

10%

1UF

10V

1

TP9708

GPU_TS_A

81 81

5%

2

1

R9722

1/20W

10K

201

MF

16.2K

2

1

R9715

1%

201

MF

1/20W

NOSTUFF

201

2

1

R9717

MF

1%

NOSTUFF

1/20W

51.1

2

1

R9716

201

MF

51.1

1/20W

1%

NOSTUFF

0201

10%

2

1

C9727

NOSTUFF

X7R

6.3V

0.1UF

0201

C9726

2

1

0.1UF

NOSTUFF

X7R

6.3V

10%

5%

2

1

201

0

MF

1/20W

R9718

5%

18PF

0201

C0G

25V

2

1

C9729

5%

R9719

1/20W

1

MF

1M

201

2

NOSTUFF

1

5%

2

R9720

1/20W
MF
201

10K

5%

2

1

R9721

NOSTUFF

201

10K

1/20W
MF

0201

2

1

C9722

X7R

6.3V

10%

0.1UF

2

1

C9721

0402

10%

1UF

10V
X6S-CERM

2

1

C9718

0402

X6S-CERM

10V

1UF

10%

0201

2

1

C9719

10%

X7R

6.3V

0.1UF

0201

2

1

C9716

X7R

10%

0.1UF

6.3V

2

1

C9715

0402

X6S-CERM

10%

1UF

10V

2

1

C9714

6.3V
CERM-X6S

10UF

20%

0402

21

L9710

0402-LF

120-OHM-0.3A-EMI

21

L9707

120-OHM-0.3A-EMI

0402-LF

21

L9700

0402-LF

120-OHM-0.3A-EMI

201

NOSTUFF

5%

2

1

1/20W
MF

10K

R9713

NOSTUFF

5%
1/20W

2

1

201

MF

10K

R9714

5%

2

1

R9711

1K

201

1/20W
MF

NOSTUFF

5%

2

1

R9710

201

1/20W
MF

1K

82

82

82

1

TP9702

1

TP9701

TP9704

1

1

TP9705

1

TP9703

1

TP9700

2

0402

1UF

10V

10%

X6S-CERM

C9712

1

2

1

C9710

0402

10V

10%

X6S-CERM

1UF

BD29

AW49

BH50

BJ51

BJ53

BH52

BD39

BD37

BC39

BC37

AW36

AW34

AV36

AV34

AW47

AW20

AW21

BH45

BC19

BM20

AW25

AV23

AW23

BC15

BD15

AL53

AL51

BC21

J48

BC23

BD23

J45

BC43

G45

F45

F47

F43

G48

BG35

BG37

BE21

BH29

BH25

BE23

BH27

BH43

BE15

BE39

BE19

AV21

BG41

BC41

BE43

BG49

BH47
BG48

BG45

BM44

BC17

BD19

BD17

BE25

BD27

BH41

BG33

BK28

BD31

BC31

BE29

BH37

BG39

BC29

BH35

BE27

BG29

BN19

BH23

BK42

BL19

BG23

BC45

BE45

BD25

BC25

AW45

BC48

BC49

BK44

U8700

BGA

BG31

BH33
BH31

BC27

BA45

BK36

BD21

BG27

BE47

216-0857-001

AV20

BA53

BH39

BG25

OMIT_TABLE

BE17

BE41

1/20W

R9725

5%

2

1

201

MF

10K

1/20W

2

5%

1

10K

MF

R9726

201

0201

2

1

0.1UF

C9730

CERM-X5R

6.3V

10%

U9702

2

5

4

1

3

74LVC1G08GW

SOT353

4

Y9700

31

2

CRITICAL

2.50X2.00MM-SM

27.000MHZ-30PPM-18PF

45

90 74

2

1

R9706

3.24K

MF

1/20W

1%

201

NOSTUFF

2

1

R9707

201

4.75K

MF

1/20W

1%

2

1

R9705

4.75K

1/20W
MF
201

1%

C0G
0201

1

2

C9728

25V

5%

18PF

2

1

R9703

MF
201

2K

1%
1/20W

R9700

2

1

1/20W

1%

MF
201

8.45K

2

1

R9704

NOSTUFF

4.75K

MF

1/20W

1%

201

2

1

R9702

201

1%

MF

1/20W

8.45K

2

1

R9701

MF

1%
1/20W

201

2K

5% 1/20W 201MF

1 2

10K

R9797

89 82

81 80 79 74

89 87 79 74

89 82

81 80 79 74

80 80

80

80

89 82 81 80 79 74

80

45

89 88 87 86 81 80 49

80 44

89 82

81 80 79 74

80

80

89 88 87 86 81 80 49

80

89 88 87 86 81 80 49

80

80

80

80

89

88 87 86 81 80 49

80

80

89 82 81 80 79 74

80

89 88 87 86 81 80 49

80

80

80

85

80

80 45

80 44

86

80

80

80

80

80

89 88 87 86 81 80 49

89 82 81 80 79 74

80

80

41

80

80

89 82 81 80 79 74

26

82

80

80

80

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

NC

OUT

OUT

BI

IN

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

VSS

PAD

VCC

W*

THRM

Q

C

D

S*

HOLD*

NC

NC

NC

NC

IN

IN

TP

A

IN

OUT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

OUT

IN

OUT

A

A

A

A

A

A

JTAG

TSS FDO

GPIO

SYM 1 OF 10

PLLS XTAL

PX_EN

NC_PX_EN_1

JTAG_TRST*

GPIO_13

NC
NC

GPIO_6_TACH

GPIO_SVT

DDCVGACLK

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TSTEN*

GPIO_0

GPIO_2

GPIO_1

GPIO_3

GPIO_5_REGHOT_AC_BATT

GPIO_4

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_11
GPIO_12

GPIO_15

GPIO_17_THERMAL_INT

GPIO_16

GPIO_18_HPD3

GPIO_20

GPIO_19_CTF

GPIO_21

GPIO_22_ROMCSB

GPIO_29

GENERICA

GPIO_30

GENERICB
GENERICC
GENERICD

GENERICE_HPD4
GENERICF_HPD5

GENERICG_HPD6

HPD1

DIGON

VARY_BL

CEC

NC_IDSC_ANALOGOUT

NC_IDSC_PWM0

NC_IDSC_IL0

NC_IDSC_PWM1

NC_DSM_0

NC_IDSC_CMON

NC_DSM_1

NC_PS_4

VDDR3

VDDR3

VDDR3
VDDR3

VDD_CT

VDD_CT

VDD_CT

VDD_CT

MLPS_1
MLPS_2

SMBCLK
SMBDAT

SCL
SDA

GPIO_SVD

GPIO_SVC

DDCVGADATA

TEST_PG

NC

NC

NC
NC

NC

NC

NC

NC

XO_IN2

XO_IN

XTALIN

XTALOUT

SPLL_CLKTESTB

SPLL_CLKTESTA

PLL_ANALOG_OUT

PLL_ANALOG_IN

SPLL_PVDD

SPLL_PVSS

SPLL_VDDC

MPLL_PVDD
MPLL_PVDD

DPLUS

GPIO_28_FDO

DMINUS

TSVDD

TS_A

TSVSS

GPIO_10_ROMSCK

MLPS_3

GPIO_14_HPD2

MLPS_0

A

Y

B

OUT

IN

NC

NC

www.laptoprepairsecrets.com

NOTE:

2.2K PU TO PP3V3_S0 FOR SMB_SMC_GFX*_S* ON SMC SIDE.
CONNECTS TO SMC SMBUS 3.

Tg1p

GDDR5 TEMP SENSOR

PWR VR TEMP SENSOR

Tg2p

- =PP3V3_GPU_VDD33

- =PP1V05_GPU_PEX_IOVDD

Signal aliases required by this page:

BOM options provided by this page:

Page Notes

(NONE)

(NONE)

- =PP1V05_GPU_PEX_PLLVDD

Power aliases required by this page:

GPU Proximity

81 OF 93

99 OF 121

0.24.0

051-00673

TP_DVPDATA_3

TP_DVPDATA_2

TP_DVPDATA_4

TP_DVPDATA_6

TP_DVPDATA_0

TP_DVPDATA_1

TP_DVPDATA_9

TP_DVPDATA_8

TP_DVPDATA_7

GPU_GENLK_VSYNC

TP_DVPDATA_10

TP_DVPDATA_11

TP_DVPDATA_5

GFX_SMBALT_L

GFX_THM_DN3

GFX_THM_DP3

GPU_VSYNC

=PP3V3_S0_GPU

GPU_HSYNC

GPU_TDIODE_P

=PP3V3_S0_GPU

GPU_TDIODE_N

GFX_THM_DN2

PP1V8_GPU_LOCAL

GFX_THM_DP2

GPU_VREFG

GPU_SMB_DAT_R
GPU_SMB_CLK_R

GPU_THERM_L

GPU_RSET

AGND_GPU_AVSS

GPU_SMB_DAT

GPU_SMB_DAT

GPU_SMB_CLK

GPU_SMB_CLK

=PP1V8_S0_GPU_VDD

=PP1V8_S0_GPU_VDD

=PP3V3_S0_GPU

=PP1V8_S0_GPU_VDD

GFX: Emerald Gnds & Unused

SYNC_MASTER=J94 SYNC_DATE=08/26/2013

1

TP9912

1

TP9911

1

TP9910

1

TP9909

1

TP9908

1

TP9907

1

TP9906

1

TP9905

1

TP9904

1

TP9903

1

TP9902

1

TP9901

2

1

C9907

NOSTUFF

0.1UF

0201

10%

X7R

6.3V

2

1

C9909

NOSTUFF

10%

0402

X6S-CERM

10V

1UF

NOSTUFF

1

2

C9906

10%
10V

1UF

X6S-CERM
0402

NOSTUFF

2

1

C9903

10%
10V

1UF

X6S-CERM
0402

2

1

C9901

1UF

10V

10%

X6S-CERM
0402

1UF

2

1

C9900

10V
X6S-CERM

10%

0402

47

47

2 1

R9910

5%

1/20W

201

MF

0

2 1

R9909

5%01/20W

MF

201

2

1

R9907

10K

201

5%
MF

1/20W

2

1

R9908

201

NOSTUFF

MF

1/20W

5%

10K

21

XW9901

SM

21

C9911

50V

CERM

10%

402

0.0022UF

PLACE_NEAR=U9901.2:3MM

21

C9912

402

0.0022UF

50V

10%

CERM

PLACE_NEAR=U9901.4:3MM

2

3

1

Q9902

BC846BMXXH

SOT732-3

2

3

1

Q9901

SOT732-3

BC846BMXXH

21

XW9902

SM

1

7

9

10

6

4

2

5

38

U9901

CRITICAL

MSOP

EMC1414-1-AIZL

2

1

C9910

X5R

6.3V
0201-1

20%

1.0UF

CRITICAL

2

1

XW9905

SHORT-0201

2

1

R9904

NOSTUFF

499

1/20W

201

1%

MF

NOSTUFF

C9905

0.1UF

2

1

6.3V
X7R
0201

10%

2

1

R9906

5%

10K

1/20W

201

MF

2

1

R9905

MF

5%

201

1/20W

10K

NOSTUFF

MF

R9903

110

1/20W

2

1

201

1%

NOSTUFF

201

2

1

R9902

MF

1/20W

221

1%

NOSTUFF

21

201

MF

5%

1/20W

10K

R9900

21

XW9900

SHORT-0201

AR49

BA47

BK20

AW39

AW38

AV39

AV38

BC47

BC33

BD33

AM50

AP50

BN11

BL11

AU49

BD35

BC35

AN51

BL17

BN17

BK16

BM16

BL15

BN15

BK14

BM14

BL13

BN13

BK12

BM12

BG21

BH21

BG19

BH19

BG17

BH17

BG15

BH15

BG13

BH13

BG11

BH11

BG9

BK18

BM18

BH9

AN53

AM52 AP52

AR47

U8700

BGA

OMIT_TABLE

216-0857-001

AU45

AR45

BN21

BJ47

BL43

BN29

BN43

BM50

BJ49

BJ45

BJ43

BJ41

BJ39

BJ37

BJ35

BJ33

BJ31

BB29

BB27

BB25

BJ23

BJ21

BJ19

BJ17

BK52

BK50

BA43

BE35

BL21

BJ25

J27

Y36

Y33

Y21

AT23

Y18

J51

W5

W49

R43

AC11

W1

Y39

V33

V27

V21

Y15

U5

U49

U45

U10

BE7

T39

V34

T27

V20

T15

R5

R49

AW31

AV31

BG53

R38

R34

R20

AT27

R16

AA10

R1

BG51

BM36

N5

N49

N45

K37

L9

AL5

L49

K29

AU47

J11

L1

J39

AV29

J35

AV27

J31

BB39

K33

K25

J23

R9

J19

J15

AN10

L45

K52

K50

J5

J49

G53

N11

L15

G5

J43

AW29

G1

E9

E7

L5

E49

E47

E45

E43

E41

E39

E37

E35

E33

E31

E29

E27

E25

E23

E21

E19

E17

E15

E13

E11

D2

D52

E5

BK2

BJ9

BJ7

BJ5

BJ15

BJ13

BJ11

BE9

BH7

U8700

BGA

OMIT_TABLE

216-0857-001

BA11

AL43

OMIT_TABLE

216-0857-001

BGA

U8700

A11

L23

A15

L41

A19

L31
A23
K17
A27

BB23

A31

L13
A35
A39

BB19

A43

BG6

A47
B50

A7

K21

W9

AL11

AA18

AT31
AA21
AA33
AA36
AA45
AA49

AA5

AC1

AW27

AC15
AC25
AG23
AC29
AC39
BA51
AC49

AC5

T50

T52
BK10
AV25

R23
AE27
AG31
AC31

R31
AE45
AE49

AE5
AG1
AC9

AG15
AG25

AJ33
AG29
AG39

AW48

AG49

AG5

AU10

AG9
AL15
AJ18
AJ21
AL39
AJ36
AJ45
AJ49

AJ5

AB52

AL1
AL9
AL18
AL21
AC23
AL33
AL36
BL29
AL49
AW5
AJ10
AR9
AN16
AN21
AN27
AN33
AN38
BA48
AN5
AP16
AN20
AP27
AN34
AP38
AB50
AR1
AW9
AN45
BE31
AR5
AT16
AT20
R27
AT34
AT38
G49
AE10
D4
AN49
AU5
AV15
AV16
AV33
AW1
BC9
BB41
BE5
B4
BN7
BC6
BA5
R11
BC1
BM10
BE37
BC5
BB21
BB17
BJ27
BJ29
BB31
BB33
BB35
BB37
BE33
BM4
BB15
BG43
AW33
BG5
BL9
BG1
BE11

89 88 87 86 81 80 49

80

89 88 87 86 81 80 49

80

81

81

81

81

89 82 81 80 79 74

89 82 81 80 79 74

89 88 87 86 81 80 49

89 82 81 80 79 74

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TP

TP

TP

TP

TP

TP

TP

TP

TP

TP

TP

TP

IN

BI

GND

DN2/DP3

DP2/DN3

DN1

VDD

SMDATA

SMCLK

DP1

THERM*/ADDR

ALERT*

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

DAC1

DVP

SYM 5 OF 10

VDDR4
VDDR4

AVDD

VSS1DI

VDDR4
VDDR4

SWAPLOCKA
SWAPLOCKB
GENLK_CLK
GENLK_VSYNC

DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
MVP_DVOCNTL_0
MVP_DVOCNTL_1

VREFG

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

R

G

B

AVSSN

VSYNC
HSYNC

AVSSQ

RSET

VDD1DI

SYM 10 OF 10

GND 2

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSVSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

SYM 9 OF 10

GND 1

VSS
VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

www.laptoprepairsecrets.com

LOAD LINE = 1.5 MILLIOHMS

AVG = 154A

O/P= PPGPUCORE_S0_REG

PEAK = 195A

PLACE GND TP NEARBY

SVD

3V @ 200A

GPUCORE

IF RA185 IS NOSTUFF

0

1

0

1

GPUCORE

1.1 V

1.0 V
01DEFAULT-> 0.9 V
1

0

SVC

0.8 V

RA145 SHOULD BE STUFFED

152-0110

GPU CORE INPUT Filtering

VOUT = VCORE

ACCESS POINT FOR I2C
DEBUG HOOKUP

15MV = 1A

82 OF 93

0.24.0

101 OF 121

051-00673

MIN_LINE_WIDTH=0.1500
MIN_NECK_WIDTH=0.1000

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.1500

LAST_MODIFIED=Thu Feb 12 14:48:25 2015

=PP3V3_S0_REG_GPUCORE

REG_GPUCORE_ISNS_5_N_R

REG_GPUCORE_ISNS_6_N_R

REG_GPUCORE_ISNS_4_P_R

REG_GPUCORE_ISNS_6_P_R

PM_PGOOD_REG_GPUCORE_S0

=PP3V3_S0_REG_GPUCORE

VR_GPU_SYS_PWROK

VR_GPU_VRDHOT_L

VR_GPU_SVD

VR_GPU_IMON

REG_V18A_GPUCORE

VR_GPU_SVT

REG_GPUCORE_ISNS_6_N

REG_GPUCORE_ISNS_6_P

REG_GPUCORE_ISNS_5_P_R

=PP1V8_S0_GPU_VDD

REG_PWM_GPUCORE_2

REG_PWM_GPUCORE_4

VR_GPU_SVT_R

VR_GPU_RCSP

REG_GPUCORE_ISNS_5_P

VR_GPU_VSEN_R

=SMB_VR_GPU_SDA

VR_GPU_SVC

=PP12V_S0_REG_GPUCORE

VR_GPU_SYS_PWROK_L

VR_GPU_PHSFLT_L

TP_VR_GPU_SCL

=PP1V8_S0_GPU_VDD

VR_GPU_RESET_L

PM_PCH_PWROK

=PP5V_S0_VRD

VR_GPU_RCSP_R

VR_GPU_IMON_RG

=SMB_VR_GPU_SCL

VR_GPU_RRES

VR_GPU_ISEN_L2

REG_PWM_GPUCORE_5
REG_PWM_GPUCORE_6

REG_PWM_GPUCORE_3

REG_PWM_GPUCORE_1

VR_GPU_RCSM_L2

VR_GPU_RCSP_L2

VR_GPU_VAUXSEN

PP12V_S0_GPUCORE_FLT

=PP3V3_S0_REG_GPUCORE =PP1V8_S0_GPU_VDD

TP_VR_GPU_SDA

VSNS_GPU_VDD

=PP5V_S0_REG_GPUCORE

VR_GPU_VSEN_L

VR_GPU_ADDR_PROT

VR_GPU_IMON_R

VR_GPU_TSEN1_R

VR_GPU_TSEN_GND

PP12V_S0_GPUCORE_FLT

SMB_VR_GPU_SDA_R

VR_GPU_RGND

REG_GPUCORE_ISNS_1_P_R
REG_GPUCORE_ISNS_1_N_R

REG_GPUCORE_ISNS_2_N_R

REG_GPUCORE_ISNS_2_P_R

VR_GPU_SVC_R

VR_GPU_SVD_R

SMB_VR_GPU_SCL_R

VR_GPU_VINSEN

REG_GPUCORE_ISNS_5_N

REG_GPUCORE_ISNS_5_P_R

REG_GPUCORE_ISNS_4_N_R

REG_GPUCORE_ISNS_3_N_R

REG_GPUCORE_ISNS_3_P_R

REG_GPUCORE_ISNS_6_P_R
REG_GPUCORE_ISNS_6_N_R

PM_EN_REG_GPUCORE_S0

VR_GPU_RCSM

VR_GPU_RCSM_R

REG_GPUCORE_ISNS_2_P

REG_GPUCORE_ISNS_3_P

REG_GPUCORE_ISNS_1_N

REG_GPUCORE_ISNS_1_P

REG_GPUCORE_ISNS_4_N

REG_GPUCORE_ISNS_4_P

REG_GPUCORE_ISNS_3_N

REG_GPUCORE_ISNS_2_N

VSNS_GPU_VSS

VR_GPU_TSEN1

REG_GPUCORE_ISNS_5_N_R

SYNC_DATE=02/06/2014SYNC_MASTER=J78_NAT

GRAPHICS: GPU CORE VR

RA193

1/16W 5% MF-LF

21

402

0

5% MF-LF1/16W

RA192

402

21

0

RA190

0

1 2

201

5%

MF

1/20W

10%
10V

CA130

0402

1

2

X6S-CERM

1UF

CA135

10%

2

1

X6S-CERM

6.3V

0.47UF

0402

CERM-X6S

20%

1

2

CA136

10UF

6.3V

0402

2

1

0201

6.3V

10%

X6S

NOSTUFF

CA140

0.1UF

CA141

1

2

0201

6.3V

10%

0.1UF

X6S

NOSTUFF

NOSTUFF

0201

6.3V

10%

X6S

1

2

CA142

0.1UF

0201

CA143

X6S

0.1UF

10%

6.3V

1

2

1

CA132

1UF

CER-X6S

10%
16V

2

0402

41

UA100

111-4172PBF

24

QFN

19

18

11

47

45

43

39

46

44

42

40

30

25
26

28
29

3

2

7

20

22

21

13

1415

16

49

9

23

12

10
4

17

6

31

5

32

35

33

34

27

1

48

38

36
37

8

XWA107

SM

OMIT

1 2

74LVC1G00GF

SOT891

UA102

2

1

35

6

4

90

73 39 19 12

MF-LF

1/16W

402

1%

10K

RA125

1

2

2N7002TXG

SOT-523-3

1

2

QA102

3

1/20W

5%
MF

201

10K

NOSTUFF

RA151

1

2

10K

MF

5%

1/20W

201

RA153

1

2

5%

1/20W

NOSTUFF

10K

MF

201

RA152

1

2

1

201

MF

1/20W

10K

5%

RA150

2

INA331IDGK

MSOP

5

184

7

2

3

6

UA101

SOT523

DZA106

1

3

NOSTUFF

MMBZ5226BT-_-F

402

1/16W
MF-LF

0

5%

RA117

12

402

5%

0

MF-LF

1/16W

RA108

12

48

NOSTUFF

100K

1%

MF-LF

1/16W

402

RA109

1

2

0603

RTA107

1

2

47KOHM-1%

402

13K

MF-LF

1/16W

1%

RA107

1

2

RA191

1/16W

2

MF-LF402

0

5%

1

0.1UF

10%

X7R-CERM

0402

16V

CA126

1

2

47

47

5% 4021/16W

0

MF-LF

RA183

1 2

4025%

0

1/16W

RA182

1 2

MF-LF

1/16W 4025%

0

1 2

RA189

MF-LF

4025%

1 2

1/16W MF-LF

0

RA188

1

MF-LF5%

0

2

4021/16W

RA187

NOSTUFF

2

MF-LF5%

0

1/16W 402

1

RA186

NOSTUFF

75

5%

603

1 2

1/10W
MF-LF

RA105

MF

1/20W

10K

1%

201

RA104

1

2

80

80

402

NOSTUFF

1%
MF-LF

1/16W

4.99K

RA145

1

2

MF-LF

0

4021/16W 5%

PLACE_NEAR=UA100:10MM

RA185

1 2

75

75

NO_XNET_CONNECTION=1

1

OMIT

2

SM

XWA120

XWA130

OMIT

1

SM

2

NO_XNET_CONNECTION=1

72

80

80

0.001UF

402

50V

20%
CERM

1

2

CA122

1%

1

2

RA122

100K

1/20W
201

MF

1%
MF-LF

1/16W
402

4.99K

RA144

1

2

4.99K

1%
MF-LF

1/16W
402

RA143

1

2

0.1UF

10%

1

2

X7R-CERM

0402

CA125

16V

4025%1/16W

0

RA184

1 2

MF-LF

0.01UF

16V
CERM

20%

402

CA123

1

2

402

MF-LF

1/16W

RA123

1

2

845

1%

RA142

13K

1/16W

1%

402

MF-LF

1 2

1K

MF-LF

1%

402

1/16W

RA124

1

2

16V

20%

X7R-CERM

1

2

0402

CA124

0.01UF

RA140

402

1%

MF-LF

1/16W

12

13K

X7R-CERM

20%
16V

0.01UF

0402

1

2

CA121

1%
1/16W
MF-LF
402

1K

RA121

1

2

NO_XNET_CONNECTION=1

649

1% 402

1/16W MF-LF

RA102

12

NO_XNET_CONNECTION=1

1%

402

MF-LF

1/16W

1

2

5.90K

RA101

649

RA103

1%

MF-LF

12

402

NO_XNET_CONNECTION=1

1/16W

NO_XNET_CONNECTION=1

5%
50V

82PF

0402

CA101

1

2

CERM

3300PF

CA115

X7R-CERM

0402

10%
50V

1

2

NO_XNET_CONNECTION=1

1/16W

0.5%

603

MF-LF

1

2

RA120

7.5K

301

RA181

2

MF-LF1/16W 402

NOSTUFF

1%

1

402

301

2

MF-LF

1

NOSTUFF

1%1/16W

RA180

1%

1 2

4021/16W

301

MF-LF

NOSTUFF

RA179

MF-LF1% 402

1 2

301

1/16W

RA178

NOSTUFF

402

1 2

301

1%

RA177

1/16W MF-LF

1 2

402

301

1%1/16W

RA176

MF-LF

402

1

1%1/16W

RA175

2

MF-LF

301

RA174

1%

301

MF-LF

21

1/16W 402

RA170

402 MF-LF

1 2

301

1%1/16W

301

MF-LF

RA171

1% 402

1 2

1/16W

RA172

402

301

2

MF-LF

1

1%1/16W

RA173

1/16W MF-LF402

21

301

1%

X7R-CERM

0402

0.1UF

CA131

1

2

10%
16V

84

84

84

84

84

84

84

84

84

83

83

83

83

83

83

CRITICAL

SSL0705M-SM

0.105UH-20%-31A-0.00032OHM

LA100

1 2

83

83

83

89 82

82

82 82

89 82

82

89 82 81 80 79 74

89

84 83

89 82 81 80 79 74

89 84 83

84 83 82

89 82 89 82 81 80 79 74

89

84 83 82

82

82

82

72

82

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

IRTN5

SM_ALERT*

SV_ALERT*/SVT

SV_ADDR/VDDIO

EN_L2/INMODE/PWROK

SV_CLK/VIDSEL1

VRHOT_ICRIT*

IRTN1_L2

ADDR_PROT

SV_DIO/VIDSEL0

SM_CLK

SM_DIO

ISEN6

VRTN_L2

RCSM

RCSM_L2

IRTN2

VSEN
VRTN

ISEN1

ISEN2

ISEN3
IRTN3 VGD/TSEN2/VAUXSEN

VCC V18A

RCSP_L2

IRTN1

PWM1

PWM3

PWM2

PWM6

PWM4
PWM5

PWM1_L2

ISEN4

ISEN5

IRTN4

ISEN1_L2

IRTN6

TSEN1

VRDY1
VRDY2

THRM_PAD

EN

RRES

RCSP

VSEN_L2

VINSEN

NC

B

A

NC

IN

IN

G

D

S

V+

SHDN

OUT

RG

V-

REF

OUT

IN

BI

IN

IN

IN

IN

OUT

OUT

OUT

NC

NC

OUT

IN

IN

NC

OUT

IN

IN

OUT

IN

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

www.laptoprepairsecrets.com

GPU PHASE 2

GPU PHASE 3

GPU Phase 1

83 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

102 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:25 2015

PPGPUCORE_S0_SENSE_1

REG_PHSFLT_GPUCORE_3_L

REG_PWM_GPUCORE_3

REG_PWM_GPUCORE_2

REG_BOOST_GPUCORE_3

REG_SNUBBER_GPUCORE_3

REG_PHSFLT_GPUCORE_1_L

REG_PHSFLT_GPUCORE_2_L

PPGPUCORE_S0_REG

PPGPUCORE_S0_REG

REG_GPUCORE_ISNS_3_P

REG_GPUCORE_ISNS_2_N

REG_GPUCORE_ISNS_2_P

REG_GPUCORE_ISNS_1_N

REG_BOOST_GPUCORE_2

REG_GPUCORE_ISNS_1_P

REG_SNUBBER_GPUCORE_1

PPGPUCORE_S0_SENSE_2

PPGPUCORE_S0_SENSE_3

REG_SNUBBER_GPUCORE_2

REG_BOOST_GPUCORE_1

=PP5V_S0_VRD

REG_BOOST_GPUCORE_1_RC

REG_BOOST_GPUCORE_2_RC

VR_PHASE_GPUCORE_2

REG_BOOST_GPUCORE_3_RC

VR_PHASE_GPUCORE_3 PPGPUCORE_S0_REG

REG_GPUCORE_ISNS_3_N

=PP5V_S0_VRD

PP12V_S0_GPUCORE_FLT

VR_PHASE_GPUCORE_1

REG_PWM_GPUCORE_1

=PP5V_S0_VRD

GRAPHICS: GPU CORE VR (PHASES 1-3)

SYNC_MASTER=J78_NAT SYNC_DATE=02/13/2014

CA256

2

1

402

0.22UF

10%
16V
CERM

CA236

402

CERM

0.22UF

10%
16V

1

2

402

CA216

CERM

0.22UF

10%
16V

1

2

20%

CRITICAL

10V
X6S-CERM

CA265

0603

1

2

10UF

2

1

X6S-CERM

10UF

20%
10V

CRITICAL

CA245

0603

2

1

X6S-CERM

10UF

20%
10V

CA225

0603

CRITICAL

PIHA12087T

230NH-20%-40A-0.00065OHM

CRITICAL

LA250

1 2

LA230

PIHA12087T

CRITICAL

230NH-20%-40A-0.00065OHM

1 2

230NH-20%-40A-0.00065OHM

PIHA12087T

CRITICAL

LA210

1 2

CASED2-SM

POLY-TANT

20%
16V

CRITICAL

39UF

CA264

1

2

1

CASED2-SM

POLY-TANT

39UF

20%
16V

CRITICAL

CA244

2

39UF

CASED2-SM

POLY-TANT

CA224

20%
16V

1

2

CRITICAL

0402-1

4V
X6S-CERM

10UF

20%

CA262

1

2

0402-1

20%
4V
X6S-CERM

10UF

CA242

1

2

0402-1

20%

10UF

X6S-CERM

4V

CA243

1

2

0402-1

10UF

20%
4V
X6S-CERM

CA222

1

2

0402-1

4V
X6S-CERM

20%

10UF

CA223

1

2

0402-1

4V
X6S-CERM

10UF

20%

CA263

1

2

VR_GPU_PHSFLT_L

84 82

0

1/20W

MF

5%

201

RA269

12

1/20W

201

5%

MF

0

RA249

12

0

201

5%

MF

1/20W

RA229

12

82

7

5
32

1
2

30

16

4

29

25

22

21

18

20

3

28

27

26

24

6

23

31

PQFN-THICKSTNCL

UA250

IR3575M

CRITICAL

MF-LF

2.2

NOSTUFF

805

5%
1/8W

RA257

1

2

82

82

RA256

0

5%

1/10W

603

MF-LF

1

2

0.001UF

10%

0402

50V
X7R-CERM

NOSTUFF

CA257

1

2

RA250

0612-1

1%
MF

1W

0.0005

CRITICAL

1 2
3 4

89 84 83

82

7

5
32

1
2

30

16

4

29

25

22

21

18

20

3

28

27

26

24

6

23

31

PQFN-THICKSTNCL

UA230

IR3575M

CRITICAL

2.2

MF-LF
805

5%
1/8W

NOSTUFF

RA237

1

2

82

82

0

603

5%
1/10W
MF-LF

RA236

1

2

0402

0.001UF

50V

10%

NOSTUFF

X7R-CERM

CA237

1

2

0.0005

CRITICAL

0612-1

1%
MF

1W

RA230

1 2
3 4

89 84 83

7

5
32

1
2

30

16

4

29

25

22

21

18

20

3

28

27

26

24

6

23

31

PQFN-THICKSTNCL

UA210

IR3575M

CRITICAL

1UF

10%
25V

EMC

0402

X6S-CERM

CRITICAL

CA254

1

2

CRITICAL

EMC

1UF

X6S-CERM

25V

10%

0402

CA234

1

2

X6S-CERM
0402

1UF

10%
25V

CRITICAL

EMC

CA214

1

2

0402

10%

X6S-CERM

CRITICAL

25V

1UF

CA220

1

2

0402

X6S-CERM

25V

10%

1UF

CRITICAL

CA221

1

2

CRITICAL

X6S-CERM

10%
25V

1UF

0402

CA240

1

2

10%

CRITICAL

25V
X6S-CERM

1UF

0402

CA241

1

2

25V

10%

X6S-CERM

CRITICAL

1UF

0402

CA259

1

2

10%
25V

CRITICAL

X6S-CERM

1UF

0402

CA260

1

2

0402

25V

CRITICAL

10%

X6S-CERM

1UF

CA252

1

2

X6S-CERM

25V

10%

CRITICAL

1UF

0402

CA253

1

2

10%
25V
X6S-CERM

CRITICAL

1UF

0402

CA261

1

2

10%
25V
X6S-CERM

CRITICAL

1UF

0402

CA258

1

2

CRITICAL

10%

X6S-CERM

25V

1UF

0402

CA232

1

2

CRITICAL

25V
X6S-CERM

1UF

10%

0402

CA233

1

2

CRITICAL

X6S-CERM

10%

0402

25V

1UF

CA238

1

2

10%

X6S-CERM

25V

CRITICAL

1UF

0402

CA239

1

2

0402

X6S-CERM

CRITICAL

10%
25V

1UF

CA218

1

2

X6S-CERM

CRITICAL

10%
25V

1UF

0402

CA219

1

2

0402

CRITICAL

1UF

X6S-CERM

25V

10%

CA213

1

2

X6S-CERM

CRITICAL

10%
25V

1UF

0402

CA212

1

2

82

82

89 84 83

82

MF-LF

1/10W

5%

603

0

2

RA216

1

NOSTUFF

MF-LF
805

5%
1/8W

2.2

RA217

1

2

10%

0402

50V
X7R-CERM

0.001UF

NOSTUFF

CA217

1

2

180UF

CRITICAL

20%

TH1

POLY

16V

CA230

1

2

10%

EMC

CRITICAL

25V
X6S-CERM
0402

1UF

CA255

1

2

CRITICAL

1UF

0402

X6S-CERM

25V

10%

EMC

CA235

1

2

16V
TH1

CRITICAL

20%
POLY

180UF

CA210

1

2

CRITICAL

0612-1

0.0005

1W
MF

1%

RA210

1 2
3 4

1UF

0402

X6S-CERM

25V

CRITICAL

10%

EMC

CA215

1

2

CA295

180UF

20%

TH1

16V

CRITICAL

POLY

1

2

89 84 83 82

89 84 83 82

84 82

89 84 83 82

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

NC

IN

IN

NC

NC

TGND

VIN

SW

BOOST

PWM

BBRK*

LGND

VCC

VIN

VIN

VIN

VIN

PHSFLT*

REFIN

PGND

PGND

IOUT

CSIN+

CSIN-

GATEL

GATEL

SW

OUT

OUT

OUT

IN

NC

NC

NC

TGND

VIN

SW

BOOST

PWM

BBRK*

LGND

VCC

VIN

VIN

VIN

VIN

PHSFLT*

REFIN

PGND

PGND

IOUT

CSIN+

CSIN-

GATEL

GATEL

SW

OUT

OUT

OUT

NC

NC

NC

TGND

VIN

SW

BOOST

PWM

BBRK*

LGND

VCC

VIN

VIN

VIN

VIN

PHSFLT*

REFIN

PGND

PGND

IOUT

CSIN+

CSIN-

GATEL

GATEL

SW

OUT

OUT

OUT

IN

www.laptoprepairsecrets.com

GPU OUTPUT DECOUPLING

GPU PHASE 6

GPU PHASE 4

GPU PHASE 5

GPU PHASE 5,6 NOT NEEDED

FOR EMERALD

84 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

103 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:25 2015

PP12V_S0_GPUCORE_FLT

VR_PHASE_GPUCORE_4

=PP5V_S0_VRD

VR_GPU_PHSFLT_L

REG_BOOST_GPUCORE_6

REG_PWM_GPUCORE_5

REG_PHSFLT_GPUCORE_5_L

=PP5V_S0_VRD

REG_BOOST_GPUCORE_5

VR_PHASE_GPUCORE_6

REG_PWM_GPUCORE_4

REG_BOOST_GPUCORE_4_RC

REG_BOOST_GPUCORE_6_RC

VR_PHASE_GPUCORE_5

REG_BOOST_GPUCORE_5_RC

REG_BOOST_GPUCORE_4

REG_PHSFLT_GPUCORE_4_L

=PP5V_S0_VRD

PPGPUCORE_S0_REG

REG_PWM_GPUCORE_6

REG_GPUCORE_ISNS_4_N

PPGPUCORE_S0_REG

PPGPUCORE_S0_SENSE_6

PPGPUCORE_S0_SENSE_5

PPGPUCORE_S0_SENSE_4

PPGPUCORE_S0_REG

PPGPUCORE_S0_REG

REG_PHSFLT_GPUCORE_6_L

REG_SNUBBER_GPUCORE_5

REG_GPUCORE_ISNS_6_P

REG_GPUCORE_ISNS_6_N

REG_GPUCORE_ISNS_5_N

REG_GPUCORE_ISNS_4_P

REG_GPUCORE_ISNS_5_P

REG_SNUBBER_GPUCORE_6

REG_SNUBBER_GPUCORE_4

CAP,470UF,0.0045OHM,2.5V,TANT

VR_BULKCAP:FUTURECA385,CA386,CA387,CA388,CA389

5128S0381

VR_BULKCAP:CURRENT

128S0198 CAP,330UF,0.009OHM,2V,CASE-D2

CA380,CA381,CA382,CA383,CA384

5

VR_BULKCAP:CURRENT

CAP,330UF,0.009OHM,2V,CASE-D2

CA385,CA386,CA387,CA388,CA389

5128S0198

CAP,470UF,0.0045OHM,2.5V,TANT

VR_BULKCAP:FUTURECA380,CA381,CA382,CA383,CA384

5128S0381

GRAPHICS: GPU CORE VR (PHASES 4-6)

SYNC_MASTER=J78_NAT SYNC_DATE=02/13/2014

NOSTUFF

CA356

0.22UF

2

1

402

16V

10%

CERM

0.22UF

NOSTUFF

16V

1

402

CA336

CERM

10%

2

CA316

0.22UF

10%

402

1

2

CERM

16V

CA325

20%

10UF

2

X6S-CERM

10V

CRITICAL

1

0603

X6S-CERM

NOSTUFF

CRITICAL

10V

20%

10UF

CA345

0603

1

2

NOSTUFF

CRITICAL

10V
X6S-CERM

10UF

20%

CA365

0603

1

2

OMIT_TABLE

CA386

470UF-0.0045OHM

CRITICAL

2.5V

20%

POLY-TANT
SM

1

23

CA387

POLY-TANT

470UF-0.0045OHM

OMIT_TABLE

2.5V

20%

CRITICAL

SM

1

23

CA388

470UF-0.0045OHM

CRITICAL

OMIT_TABLE

POLY-TANT

2.5V

20%

SM

1

23

CA389

POLY-TANT

470UF-0.0045OHM

OMIT_TABLE

CRITICAL

2.5V

20%

SM

1

23

CA380

CRITICAL

OMIT_TABLE

3 2

1

SM

20%

POLY-TANT

2.5V

470UF-0.0045OHM

OMIT_TABLE

CA381

470UF-0.0045OHM

20%

2.5V

3 2

1

SM

POLY-TANT

CRITICAL

CA382

3 2

1

CRITICAL

20%

2.5V
POLY-TANT
SM

OMIT_TABLE

470UF-0.0045OHM

POLY-TANT

CA383

3 2

1

20%

2.5V

SM

CRITICAL

470UF-0.0045OHM

OMIT_TABLE OMIT_TABLE

2

1

20%

2.5V

SM

3

CA384

CRITICAL

POLY-TANT

470UF-0.0045OHM

OMIT_TABLE

CRITICAL

470UF-0.0045OHM

CA385

POLY-TANT

3 2

1

2.5V

SM

20%

NOSTUFF

21

CRITICAL

PIHA12087T

230NH-20%-40A-0.00065OHM

LA350

NOSTUFF

230NH-20%-40A-0.00065OHM

21

LA330

CRITICAL

PIHA12087T

21

LA310

CRITICAL

230NH-20%-40A-0.00065OHM

PIHA12087T

2

1

CA364

16V

20%

POLY-TANT
CASED2-SM

39UF

CRITICAL

2

1

CA344

CRITICAL

20%
16V

POLY-TANT

39UF

CASED2-SM

2

1

CA324

20%

POLY-TANT

CRITICAL

16V

39UF

CASED2-SM

2

1

CA362

20%

10UF

X6S-CERM

4V
0402-1

2

1

CA363

20%

10UF

X6S-CERM

4V
0402-1

2

1

CA343

4V
X6S-CERM

10UF

20%

0402-1

2

1

CA342

4V
X6S-CERM

10UF

20%

0402-1

2

1

CA323

4V
X6S-CERM

10UF

20%

0402-1

2

1

CA322

4V
X6S-CERM

10UF

20%

0402-1

NOSTUFF

1

201

MF

1/20W

5%

RA369

2

0

NOSTUFF

201

5%

1/20W

MF

RA349

2 1

0

83 82

2 1

RA329

0

1/20W

MF

5%

201

82

82

PQFN-THICKSTNCL

NOSTUFF

7

5
32

1
2

30

16

4

29

25

22

21

18

20

3

28

27

26

24

6

23

31

CRITICAL

UA350

IR3575M

NOSTUFF

7

5
32

1
2

30

16

4

29

25

22

21

18

20

3

28

27

26

24

6

23

31

PQFN-THICKSTNCL

UA330

CRITICAL

IR3575M

82

CRITICAL

24

23

7

5
32

1
2

30

16

4

29

25

22

21

18

20

3

28

27

26

6

31

PQFN-THICKSTNCL

UA310

IR3575M

NOSTUFF

2

1

RA356

1/10W

5%

603

MF-LF

0

NOSTUFF

2

1

RA336

1/10W

5%

603

MF-LF

0

MF-LF

1/10W

RA316

0

603

2

1

5%

5%

1

NOSTUFF

1/8W
805

2.2

MF-LF

2

RA357

0.001UF

1

NOSTUFF

10%
X7R-CERM

0402

50V

CA357

2

2

1

CA310

20%
16V
POLY

CRITICAL

180UF

TH1

2

1

CA312

0402

CRITICAL

25V

10%

1UF

X6S-CERM

NOSTUFF

43

21

RA350

0.0005

CRITICAL

1%

0612-1

1W
MF

2

1

CA313

0402

CRITICAL

25V

10%

1UF

X6S-CERM

2

1

CA318

0402

X6S-CERM

10%
25V

1UF

CRITICAL

0402

2

1

CA319

10%
25V

1UF

CRITICAL

X6S-CERM

82

89 84 83

82

2

1

CA320

0402

10%
25V

1UF

CRITICAL

X6S-CERM

2

1

CA321

0402

10%
25V

1UF

X6S-CERM

CRITICAL

2

1

CA315

0402

EMC

25V
X6S-CERM

10%

1UF

CRITICAL

2

1

CA314

EMC

10%

CRITICAL

25V
X6S-CERM
0402

1UF

2

1

CA335

0402

EMC

25V
X6S-CERM

10%

1UF

CRITICAL

2

1

CA354

X6S-CERM

10%
25V

EMC

0402

1UF

CRITICAL

2

1

CA360

25V

10%

X6S-CERM
0402

1UF

CRITICAL

2

1

CA361

0402

CRITICAL

25V

10%

X6S-CERM

1UF

2

1

CA340

0402

10%

1UF

CRITICAL

X6S-CERM

25V

2

1

CA341

0402

10%

1UF

CRITICAL

25V
X6S-CERM

2

1

CA332

10%

0402

CRITICAL

25V
X6S-CERM

1UF

2

1

CA333

0402

CRITICAL

10%

1UF

X6S-CERM

25V

2

1

CA338

0402

10%

1UF

25V
X6S-CERM

CRITICAL

2

1

CA339

0402

10%

1UF

CRITICAL

25V
X6S-CERM

2

1

0402

25V

10%

X6S-CERM

1UF

CRITICAL

CA352

2

1

CA353

CRITICAL

0402

25V

10%

X6S-CERM

1UF

2

1

CA358

1UF

CRITICAL

0402

25V

10%

X6S-CERM

2

1

CA359

0402

25V

10%

X6S-CERM

CRITICAL

1UF

NOSTUFF

43

21

RA330

MF

1W

0612-1

0.0005

1%

CRITICAL

82

82

89 84 83

2

1

CA334

EMC

10%

CRITICAL

25V
X6S-CERM
0402

1UF

0402

NOSTUFF

2

1

X7R-CERM

50V

10%

CA337

0.001UF

2.2

NOSTUFF

2

1

RA337

MF-LF

1/8W

5%

805

2

1

CA330

16V

20%

TH1

CRITICAL

POLY

180UF

82

82

89 84 83

2

1

RA317

2.2

MF-LF

NOSTUFF

805

5%
1/8W

2

1

CA317

X7R-CERM

10%
50V

0402

0.001UF

NOSTUFF

2

1

CA350

TH1

20%

180UF

POLY

16V

CRITICAL

43

21

RA310

CRITICAL

1%

0.0005

0612-1

1W
MF

2

1

CA355

EMC

10%

CRITICAL

25V
X6S-CERM
0402

1UF

83 82

89 84 83 82

89 84 83 82

89 84 83 82

89 84 83

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

NC

NC

IN

IN

IN

NC

NC

TGND

VIN

SW

BOOST

PWM

BBRK*

LGND

VCC

VIN

VIN

VIN

VIN

PHSFLT*

REFIN

PGND

PGND

IOUT

CSIN+

CSIN-

GATEL

GATEL

SW

NC

NC

TGND

VIN

SW

BOOST

PWM

BBRK*

LGND

VCC

VIN

VIN

VIN

VIN

PHSFLT*

REFIN

PGND

PGND

IOUT

CSIN+

CSIN-

GATEL

GATEL

SW

IN

NC

NC

NC

TGND

VIN

SW

BOOST

PWM

BBRK*

LGND

VCC

VIN

VIN

VIN

VIN

PHSFLT*

REFIN

PGND

PGND

IOUT

CSIN+

CSIN-

GATEL

GATEL

SW

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

www.laptoprepairsecrets.com

PIT: 1.35

To regulator:

audio frequencies

Regulator requires
a minimum load to
prevent noise in the

1

1.373 V

DEFAULT ->

<Rb> <Rb>

Vout = 0.5 * (1 + Ra / Rb)

PLACE NEAR GPU POWER PINS.

0
0
1

VID 1

1.5 V

1.35 V

1

1.6 V

<Ra> <Ra>

0

1

VID 0 GPU VDDQ

Note:

LEA: 1.35

XTA: 1.35/1.5

0

GPU VDDQ SUPPLY

VOUT = 1.5V / 1.35V

F = 500 KHZ

EDC = 12A

TDC = 9.5A

85 OF 93

DIDT=TRUEDIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

104 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:25 2015

REG_FBVDDQ_OCSET

REG_FBVDDQ_VO_R

REG_FBVDDQ_VO

REG_FBVDDQ_OCSET_R

PP1V5R1V35_S0_GPU_REGVRVDDQ_R

VR_PHASE_FBVDDQREG_PHASE_FBVDDQ

REG_LGATE_FBVDDQ

PM_PGOOD_REG_FBVDDQ_S0

FBVDDQ_ALTV1_R

FBVDDQ_ALTV0_R

AGND_FBVDDQ

REG_VCC_UA450

REG_VCC_UA450

REG_FBVDDQ_RTN_R

GPU_FBVDDQ_ALTV_R

=PP12V_S0_REG_FBVDDQ

REG_BOOT_FBVDDQ_RC

REG_UGATE_FBVDDQ

REG_BOOT_FBVDDQ

REG_PVCC_UA450

PM_EN_REG_GPU_VDDQ_S0_R

AGND_FBVDDQ

REG_FBVDDQ_FB

REG_FBVDDQ_SREF

REG_FBVDDQ_RTN

REG_FBVDDQ_VO

REG_FBVDDQ_OCSET

REG_FBVDDQ_SET0

REG_SNUBBER_FBVDDQ

PM_PGOOD_REG_GPU_VDDQ_S0

MAKE_BASE=TRUE

PM_EN_REG_GPU_VDDQ_S0

PM_PGOOD_REG_FBVDDQ_S0

REG_FBVDDQ_FSEL

REG_FBVDDQ_SET1

=PP1V35_S0_GPU_FBVDDQ

REG_FBVDDQ_FB_R

=PP3V3_S0_VRD

AGND_FBVDDQ

REG_FBVDDQ_SET1_R

=PP5V_S0_REG_FBVDDQ

GRAPHICS: GPU VDDQ VR

SYNC_MASTER=J78_MLB SYNC_DATE=02/20/2014

RA470, RA471114S0269 2 RES,3.4K,1%.1/16W,0402,SMD FB:4G_HYNIX

RA470, RA471RES,3.57K,1%.1/16W,0402,SMD114S0271 2 FB:4G_ELPIDA

1

2

CASE-D2-SM

CA416

470UF-0.006OHM

CRITICAL

2V

20%

POLY

470UF-0.006OHM

1

2

CASE-D2-SM

CA415

20%

CRITICAL

2V
POLY

1

470UF-0.006OHM

2

CASE-D2-SM

CA414

20%
2V
POLY

CRITICAL

4V

20%

10UF

CA418

2

1

0402-1

X6SX6S

4V

20%

0402-1

1

2

10UF

CA417

1

0603

16V

20%

10UF

2

CA404

X6S-CERM

2

1

0402

CA403

1UF

CER-X6S

10%
16V

X6S-CERM

10%

6.3V

0.33UF

0402

1

2

CA490

2

1

CA407

0402

1UF

25V
X6S-CERM

10%

1UF

2

1

CA422

0402

10%

X6S-CERM

25V

2

1

39UF

CRITICAL

CASED2-SM

16V

20%

CA425

POLY-TANT

2 1

RA402

201

5%

1/20W

MF

0

2

1

CA485

0402

50V

5%

10PF

CERM

2

1

CA470

5%

10PF

0402

CERM

50V

80

2 1

RA485

201

MF

5%

0

1/20W

2 1

RA484

MF

NOSTUFF

201

5%

1/20W

0

2

1

CA423

0402

1UF

25V
X6S-CERM

10%

2

1

RA472

2.0K

1%

MF-LF

1/16W

402

2

1

RA473

2.0K

402

MF-LF

1%
1/16W

2

1

RA478

402

MF-LF

1/16W

1%

274K

2

1

RA480

MF

201

NOSTUFF

10K

5%

1/20W

2

1

RA481

MF

10K

201

5%

1/20W

21

RA477

402

0

MF-LF

5%

1/16W

2

1

RA475

1%

MF-LF

402

26.1K

1/16W

RA474

4.99K

1/16W

2

1

1%

402

MF-LF

2

1

0402

1UF

25V
X6S-CERM

10%

CA408

2

1

RA476

402

5%
MF-LF

NOSTUFF

1/16W

0

72

5%

1/20W

RA482

1

FBVDDQ_DFLT:1V5

10K

MF

201

2

10K

2

1

RA483

FBVDDQ_DFLT:1V35

MF

201

5%

1/20W

2 1

XWA473

UA450.3:4MM

SM

2

1

RA470

3.40K

1%
1/16W
MF-LF

NO_XNET_CONNECTION=1

402

OMIT_TABLE

2

1

RA471

1/16W

1%

402

MF-LF

NO_XNET_CONNECTION=1

3.40K

OMIT_TABLE

2

1

0402

25V

10%

1UF

CA424

X6S-CERM

2

1

PLACE_NEAR=XWA471.2:1MM

SM

NO_XNET_CONNECTION=1

XWA470

2

1

XWA471

SM

NO_XNET_CONNECTION=1

UA450

19

12

5

6

17

7

9

8

4

20

16

14

2

11

1

3

13

10

15 18

ISL95870AH

CRITICAL

UTQFN

MF-LF

5%

2

1

805

10

1/8W

RA405

2

1

RA406

5%

805

MF-LF

1/8W

2.2

I41

2

1

RA413

MF-LF

5%

10K

1/16W
402

73 72

2

1

RA409

1/10W
MF-LF

NOSTUFF

2.2

5%

603

2

1

CA411

0.001UF

X7R-CERM

50V

NOSTUFF

10%

0402

CA413

1

2

5%

CERM
0402

25V

1000PF

1/16W

2

1

200

5%

RA412

MF-LF
402

2

1

MF-LF

1/10W

5%

0

603

RA407

2

1

0402

0.1UF

16V

10%

X7R-CERM

CA405

222120

18

7

6

26

312816

4

30

29

27

24

3

2

1

5

QA410

PQFN

IRF3575

32

25

23

2

0402

X6S-CERM

1

1UF

25V

EMC

10%

CA409

QA410.22:8MM

2

EMC

25V

10%

1UF

1

CA410

QA410.18:6MM

0402

X6S-CERM

2

1

CA401

CRITICAL

TH1

16V
POLY

180UF

20%

2

1

CA402

180UF

CRITICAL

16V

20%

POLY
TH1

2

1

CA406

20%
16V
POLY
TH1

CRITICAL

180UF

2

1

CA420

CRITICAL

180UF

20%
16V
POLY
TH1

2

1

CA421

0402

X6S-CERM

1UF

25V

10%

RA410.2:3MM

CA412

402

21

0.01UF

X7R

25V

10%

RA410

2.26K

1

402

2

1%

MF-LF

1/16W

1/16W

RA411

402

2

1

MF-LF

1%

2.26K

2

3

1W

1%

0.001

MF-3

RA400

4

1

0612

2

0.68UH-28A-0.00175OHM

PCME104T-SM

1

CRITICAL

LA410

1

2

CASE-D2-SM

CA419

470UF-0.006OHM

CRITICAL

POLY

20%
2V

85

85

89

85

85

85

85

89

85

85

85

85

89 78 77 76 75

89 65 61 60

85

89

TABLE_5_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

IN

IN

SREF

VID0

RTN

FSEL

SET0

PVCCVCC

BOOT

UGATE

LGATE

PHASE

PGNDGND

EN

VO

FB

OCSET

PGOOD

SET1

VID1

OUT

SW

NC
NC

NC

NC

NC

NC

GATEH

GATEL

PGND

VIN

NC

Q1S

www.laptoprepairsecrets.com

DEFAULT ->

111

VID 1

PLACE NEAR GPU POWER PINS

<Ra>

<Rb><Rb>

audio frequencies

Vout = 0.5 * (1 + Ra / Rb)

NEPTUNE

prevent noise in the

a minimum load to

Regulator requires

Note:

<Ra>

EDC = 24A

TDC = 23A

GPU VDDCI

0 1.000 V

VID 0

DEFAULT ->

To regulator:

VOUT = 0.875V

GPU VDDCI SUPPLY

0.850 V

1 1

VID 1

0

1

1.000 V

VID 0

AMETHYST

GPU VDDCI

0.900 V

86 OF 93

DIDT=TRUEDIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

105 OF 121

0.24.0

051-00673

REG_GPU_VDDCI_VO_R

PPVDDCI_S0_GPU_REGVR_PHASE_GPU_VDDCI

REG_SNUBBER_GPU_VDDCI

VRVDDCI_R

REG_GPU_VDDCI_OCSET_R

GPU_ISNS_VDDCI_N

REG_PHASE_GPU_VDDCI

REG_UGATE_GPU_VDDCI

REG_BOOT_GPU_VDDCI_RC

REG_PVCC_UA550

REG_VCC_UA550

REG_GPU_VDDCI_FB

PM_EN_GPU_VDDCI_S0_R

AGND_GPU_VDDCI

REG_LGATE_GPU_VDDCI

GPU_ISNS_VDDCI_P

PM_EN_REG_GPU_VDDCI_S0

REG_GPU_VDDCI_SET1

GPU_VDDCI_ALTV1

=PP12V_S0_REG_GPU_VDDCI

REG_VCC_UA550

SNS_GPU_VDDCI_XW_N SNS_GPU_VDDCI_XW_P

SNS_GPU_VDDCI_P

REG_GPU_VDDCI_VO

REG_GPU_VDDCI_SET1_R

REG_GPU_VDDCI_OCSET

REG_BOOT_GPU_VDDCI

=PP5V_S0_REG_VDDCI

SNS_GPU_VDDCI_N

REG_GPU_VDDCI_VO

REG_GPU_VDDCI_FSEL

AGND_GPU_VDDCI

GPU_VDDCI_ALTV0

AGND_GPU_VDDCI

GPU_VDDCI_ALTV_R

REG_GPU_VDDCI_OCSET

PM_PGOOD_REG_GPU_VDDCI_S0

REG_GPU_VDDCI_RTN

REG_GPU_VDDCI_SET0

REG_GPU_VDDCI_SREF

=PP3V3_S0_GPU

PM_PGOOD_REG_GPU_VDDCI_S0

SYNC_DATE=02/10/2015SYNC_MASTER=hcheng_j95

GRAPHICS: GPU VDDCI VR

116S0068 RA570,RA571RES,1.2K,04022 GPU_Emerald

1 RES,45.3K,0402 GPU_EmeraldRA575114S0378

1114S0363 RES,31.6K,0402 RA574 GPU_Neptune

114S0363 RES,31.6K,04021 RA574 GPU_Emerald

114S0231 RA570,RA5712 RES,1.4K,0402 GPU_Neptune

RES,1.3K,0402114S0228 2 RA570,RA571 GPU_AmethystP_XTA

114S0373 RES,40.2K,0402 RA5741 GPU_AmethystP_XTA

RES,22.1K,0402 RA5751114S0347 GPU_Neptune

RA575RES,22.1K,0402114S0347 1 GPU_AmethystP_XTA

2 RES,1.3K,0402114S0228 RA570,RA571 GPU_AmethystP_PROA

114S0347 RES,22.1K,04021 RA575 GPU_AmethystP_PROA

RES,48.7K,04021114S0382 RA574 GPU_AmethystP_PROA

CRITICAL

39UF

20%

16V
POLY-TANT
CASED2-SM

CA539

1

2

201

5%

1/20W

MF

0

RA502

12

0402

CERM

10PF

50V

5%

CA585

1

2

10PF

0402

CERM

5%
50V

CA570

1

2

1UF

CRITICAL

25V

10%

CA538

1

0402

X6S-CERM

2

180UF

POLY

16V
TH1

20%

CA506

1

2

1UF

10%
X6S-CERM

CRITICAL

0402

CA537

1

25V

2

CRITICAL

X6S-CERM
0402

1UF

10%
25V

CA528

1

2

0402

1UF

CRITICAL

25V

10%
X6S-CERM

CA527

1

2

80

NOSTUFF

RA585

0

1/20W

MF

5%

201

12

1/20W

MF

5%

0

201

RA584

12

49

49

SM

2 1

NO_XNET_CONNECTION=1

XWA581

SM

12

XWA580

NO_XNET_CONNECTION=1

16V

20%

180UF

POLY
TH1

CA520

1

2

201

10K

5%
MF

1/20W

RA580

1

2

NOSTUFF NOSTUFF

201

10K

5%
MF

1/20W

RA582

1

2

201

MF

10K

5%

RA581

1

2

1/20W

MF

10K

5%

1/20W

RA583

1

2

201

1UF

X6S-CERM

CRITICAL

0402

10%
25V

CA507

1

2

402

MF-LF

1%

1/16W

2.0K

RA572

1

2

MF-LF
402

1%
1/16W

RA573

1

2

2.0K

OMIT_TABLE

NO_XNET_CONNECTION=1

1.43K

1%

MF-LF

402

1/16W

RA570

1

2

OMIT_TABLE

NO_XNET_CONNECTION=1

402

MF-LF

1%
1/16W

1.43K

RA571

1

2

158K

1%
1/16W
MF-LF

RA578

1

2

402

OMIT_TABLE

22.1K

RA575

MF-LF

1%
1/16W

402

1

2

NOSTUFF

RA576

402

1/16W

5%

0

MF-LF

1

2

2

402

5%

0

MF-LF

1/16W

1

RA577

CA590

X5R

16V

0.033UF

10%

402

1

2

1/16W

OMIT_TABLE

31.6K

RA574

1

MF-LF

402

1%

2

90

UA550.3:5MM

SM

XWA573

12

18

17

16

2

UA550

10

13

3

1

14

4

8

9

7

19

6

5

12

11

ISL95870AH

CRITICAL

UTQFN

20

15

0402

10%

1UF

CRITICAL

X6S-CERM

25V

CA508

1

2

75

75

NO_XNET_CONNECTION=1

PLACE_NEAR=XWA571.2:1MM

SM

XWA570

1

2

NO_XNET_CONNECTION=1

SM

XWA571

1

2

805

10

5%

MF-LF

1/8W

RA505

1

2

2.2

1/8W
MF-LF

5%

805

RA506

1

2

PQFN

IRF3575

QA510

25

5
32

1
2

3
24
27
29
30

4

16

28

31

26

6
7

18

20

21

22

23

NOSTUFF

5%
MF-LF

2

1/10W

1

2.2

RA509

603

86 72

10%

0402

50V
X7R-CERM

1

2

CA511

NOSTUFF

0.001UF

QA510.22:4MM

0402

10%
X6S-CERM

EMC

1UF

25V

CA509

1

2

RA510

1/16W

1%

2.32K

402

1

2

MF-LF

X7R-CERM

10%
50V

RA510.2:3MM

0.01UF

CA512

1 2

0402

LA510

CRITICAL

1 2

PCME104T-SM

0.36UH-20%-40A-0.00076OHM

X6S-CERM

1UF

QA510.18:4MM

0402

EMC

25V

10%

CA510

1

2

1

43

2

MF

1W

1%

RA500

0.0005

0612-2

MF-LF

LA510.2:25MM

402

1%

1

2

2.32K

1/16W

RA511

0402

CERM

6.3V

20%

1

2

CA518

10UF

RA513

402

MF-LF

5%
1/16W

10K

1

2

25V

2

5%

0402

CERM

1000PF

CA513

1

0402

20%

6.3V
CERM

10UF

CA517

1

2

MF-LF

0

5%

1/10W

603

RA507

1

2

CRITICAL

POLY

2V

470UF-0.006OHM

CASE-D2-SM

2

1

20%

CA595

1

CRITICAL

20%

CASE-D2-SM

POLY

2V

2

NOSTUFF

CA594

470UF-0.006OHM

CRITICAL

CA593

2V

20%

1

470UF-0.006OHM

CASE-D2-SM

POLY

2

10%

0.1UF

16V
0402

X7R-CERM

2

CA505

1

CA592

CRITICAL

POLY

2V

20%

1

2

470UF-0.006OHM

CASE-D2-SM

2V

20%

POLY
CASE-D2-SM

2

1

CRITICAL

CA591

470UF-0.006OHM

NOSTUFF

1

2

2V

20%

CRITICAL

470UF-0.006OHM

CASE-D2-SM

POLY

CA597

2

1

0603

CA504

20%

10UF

X6S-CERM

16V

0402

16V
CER-X6S

1UF

10%

CA503

1

2

6.3V
CERM
0402

10UF

20%

CA596

1

2

16V

20%

180UF

TH1

POLY

CA502

1

2

89

86

86

89

86

86

86

89

86

86

86

86

86 72

89 88 87 81 80 49

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

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SHEET

PAGE TITLE

C

A

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2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

IN

OUT

OUT

IN

SREF

VID0

RTN

FSEL

SET0

PVCCVCC

BOOT

UGATE

LGATE

PHASE

PGNDGND

EN

VO

FB

OCSET

PGOOD

SET1

VID1

IN

IN

SW

NC
NC

NC

NC

NC

NC

GATEH

GATEL

PGND

VIN

NC

Q1S

OUT

www.laptoprepairsecrets.com

(reg_phase_vccsas0)

audio frequencies

NOTE: CONSIDER 1UH.

Vout = 0.5 * (1 + Ra / Rb)

<Ra>

PLACE NEAR GPU POWER PINS

prevent noise in the

a minimum load to

Regulator requires

To regulator:

<Rb>

4.3 A

Max peak current:

Max avg current:

GPU VDDC (0.95V) S0 REGULATOR

4.5 A

300 kHz

Switching freq:

<Rb>

<Ra>

Note:

87 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

106 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:26 2015

=PP12V_S0_REG_GPU_0V95

=PP3V3_S0_GPU

REG_P0V95S0_FSEL

REG_P0V95S0_RTN

REG_PHASE_P0V95S0

REG_VCC_UA660

REG_P0V95S0_VO_R

REG_PVCC_UA660

REG_P0V95S0_OCSET

REG_P0V95S0_FB

SNS_P0V95S0_XW_PSNS_P0V95S0_XW_N

=PP0V95_S0_GPU_VDDC

=PP5V_S0_REG_GPU_0V95

REG_UGATE_P0V95S0

REG_BOOT_P0V95S0_RC_TGR

REG_LGATE_P0V95S0

REG_P0V95S0_OCSET_R

REG_P0V95S0_VO

REG_P0V95S0_SREF

REG_SNUBBER_P0V95S0

PM_PGOOD_REG_P0V95_S0

PM_PGOOD_REG_P0V95_S0

REG_BOOT_P0V95S0_RC

REG_P0V95S0_OCSET

PM_EN_REG_P0V95_S0_R

PM_EN_REG_P0V95_S0

REG_P0V95S0_VO

REG_BOOT_P0V95S0

AGND_P0V95S0

PP0V95_S0_GPU_VDDC_REG

SYNC_DATE=08/02/2014SYNC_MASTER=J78_MLB

GRAPHICS: GPU 0V95 VR

CA640,CA641128S0381 VR_BULKCAP:FUTURE2 CAP,470uF,0.0045OHM,2.5V,SM

CA640,CA641 VR_BULKCAP:CURRENT2128S0358 CAP,470uF,0.006OHM,2V,D2

CA661

2

1

0402

2.2UF

CER-X6S

20%
10V16V

10%

CER-X6S

1UF

CA660

0402

1

2

LA630

1 2

IHLP2525EZ-SM

2.2UH-10A

2

1

0402

1UF

CA692

25V

10%
X6S-CERM

2

1

0402

25V

10%

1UF

X6S-CERM

CA693

8

7

6

1

3

9

5

SON5X6

QA630

4

CSD58872Q5D

OMIT_TABLE

CA641

CRITICAL

470UF-0.0045OHM

20%

2.5V
POLY-TANT

3 2

1

SM

OMIT_TABLE

CRITICAL

470UF-0.0045OHM

20%

CA640

3 2

1

2.5V

SM

POLY-TANT

POLY-TANT

2

1

16V

20%

CASE-D2E-SM

CA635

CRITICAL

68UF

2

1

CA630

CRITICAL

POLY

16V

TH1

20%

180UF

RA602

2 1

0

201

5%

1/20W

MF

CA655

10PF

2

1

50V

5%

0402

CERM

2

1

CA650

0402

10PF

50V
CERM

5%

OMIT

LA630.2:1MM

XWA681

2

1

SM

2

1

OMIT

SM

XWA680

LA630.1:1MM

2

1

CA643

10UF

20%

6.3V
CERM-X6S
0402

2

1

RA651

402

MF-LF

1/16W

1%

3.32K

RA656

2

1

1/16W
402

MF-LF

3.32K

1%

2

1

RA650

402

3.01K

MF-LF

1%

1/16W

NO_XNET_CONNECTION=1

402

MF-LF

1/16W

3.01K

RA655

NO_XNET_CONNECTION=1

1%

2

1

PLACE_NEAR=XWA655.2:1.1MM 2

1

SM

XWA650

NO_XNET_CONNECTION=1

XWA655

2

1

SM

NO_XNET_CONNECTION=1

2

0.047UF

CA665

1

X7R-CERM
0402

10%
16V

72

1

RA662

2

0

MF-LF

402

1/16W

5%

6

ISL95870

8

13

11

4

2

14

10

9

16

7

15

1

5

3 12

UA660

CRITICAL

UTQFN

2

1

XWA660

UA660.1:5MM

SM

805

2

1

RA660

5%

10

MF-LF

1/8W

2.2

805

2

1

RA661

MF-LF

5%
1/8W

MF-LF

1

0

5%

1/10W

2

603

RA636

1

X7R-CERM

16V

10%

0402

2

0.1UF

CA636

RA637

2

1

NOSTUFF

MF-LF

5%

2.2

1/10W
603

CA637

0.001UF

2

1

10%

0402

X7R-CERM

50V

NOSTUFF

2

1

CA633

5%
25V

1000PF

CERM

EMC

0402

2

1

CA634

25V

EMC

1000PF

5%
CERM

0402

RA680

2

1

402

14.3K

MF-LF

1%

1/16W

RA680.2:3MM

21

CA680

402

10%
25V
X7R

0.012UF

LA630.2:10MM

RA681

2

1

402

14.3K

MF-LF

1/16W

1%

2

1

CA638

0402

5%

1000PF

CERM

25V

1

2

X6S-CERM
0402

10%
25V

1UF

CA631 CA632

1

2

10%
25V

1UF

0402

X6S-CERM

RA638

MF-LF
603

2

1

5%
1/10W

200

1

2

RA622

MF-LF

1/16W
402

10K

5%

2

0402

CA642

10UF

1

20%

6.3V
CERM-X6S

87 72 3

89

89 88 86 81 80 49

87

89 80 79 74

89

87

87 72 3

87

87

89

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_5_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

DRAWING

VIN

BG

TG

TGR

PGND

VSW

IN

FB

EN

PGNDGND

PVCCVCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

OUT

www.laptoprepairsecrets.com

1.8V S0 Regulator

Switching freq:

3 A (BUDGET)

2.4 A (BUDGET)

? kHz

Max peak current:
OC trip point: ? A (nom)/? A (min)

<Ra>

<Rb>

VOUT = 0.6 * (1 + RA / RB)

Max avg current:

88 OF 93

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

107 OF 121

0.24.0

051-00673

LAST_MODIFIED=Thu Feb 12 14:48:26 2015

=PP12V_S0_REG_GPU_1V8

AGND_PVDDR

PP1V8_S0_GPU_VDD_REG

REG_RTCLK_PVDDR

REG_VSNSR_PVDDR

PM_PGOOD_REG_PVDDCT_S0

REG_COMP_PVDDR

RGCMPVDDR

=PP3V3_S0_GPU

PM_EN_REG_PVDDCT_S0

PM_EN_REG_PVDDCT_S0_R

REG_BOOT_PVDDR_R

REG_SSTR_PVDDR

REG_BOOT_PVDDR

REG_VSNS_PVDDR

REG_PHASE_PVDDR

SYNC_MASTER=J95_HARPER

GRAPHICS: GPU 1V8 VR

SYNC_DATE=02/11/2015

1/16W

127K

1%

RA710

402

2

1

MF-LF

2

1

CA706

CRITICAL

20%

POLY-TANT

16V

39UF

CASED2-SM

603

1/10W

5%

RA730

0

2

MF-LF

1

2 1

RA702

MF

0

1/20W

5%

201

2

1

CA705

X6S-CERM

1UF

10%
25V

0402

CA720

1

0402

20%

6.3V

10UF

CERM

2

UA700

TPS54622A

QFN-THICKSTNCL

CRITICAL

8

10

2

3

11
12

4

5

14

1

9

15

6

7

13

2

1

XWA770

SM

CA725

2

1

NOSTUFF

120PF

5%
50V
C0G-CERM
0402

2

1

CA723

2.5V

20%

CASE-B2S

POLY-TANT

210UF

2

1

RA722

MF-LF

1/16W

49.9

1%

402

2

1

CA704

25V

1UF

10%
X6S-CERM

0402

2

1

RA711

402

1%

10K

1/16W
MF-LF

72

2

1

RA714

1%
1/16W

402

MF

8.20K

2

1

CA714

10%

0.015UF

0402

X7R-CERM

16V

2

1

50V
402

5%

CERM

120PF

CA713

2

1

CA712

50V

10%

0402

4700PF

X7R-CERM

72

21

CA710

X5R

25V

0.1UF

402

10%

21

CRITICAL

PCMB053T-SM

2.2UH-20%-5.5A-0.035OHM

LA700

2

1

CA721

6.3V

20%

10UF

0402

CERM

10K

2

1

RA721

1/16W

1%

402

MF-LF

2

1

RA720

20.0K

1/16W

1%

402

MF-LF

2

1

CA703

0402

10%

EMC

1UF

X6S-CERM

25V

2

1

CA701

0402

X6S-CERM

25V

10%

1UF

2

1

CA702

EMC

X6S-CERM

25V

10%

1UF

0402

2

1

CA700

X6S-CERM

25V

1UF

10%

0402

89

89

89 87 86 81 80 49

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

DRAWING

VIN

GND

PVIN

PVIN

RT/CLK

PH
PH

BOOT

THRM_PAD

EN

PWRGD

SS/TR

VSENSE

COMP

OUT

IN

www.laptoprepairsecrets.com

FBVDDQ IS 1.5V

Enabled when system is in run

G3 Rails

Enabled when system is in run

CPU/PCH Rails (S0)

THIS IS 1.35V RAIL

THIS IS 1.35V RAIL

Enabled when system is in run or sleep

S4 Rails

Enabled when system has AC and is in run or sleep

S3 Rails

On with AC/DC plugged in

Ground/Common

Always on: Keeps the PCH RTC alive

S5 Rails

On when in S5

G3H Rails

S0 Rails

GPU Rails (S0)

Enabled when system is in run

Thunderbolt Rails (S0)

Enabled when Thunderbolt cable is plugged in

89 OF 93

111 OF 121

0.24.0

051-00673

PP12V_S0_HDD_SNS

=PP12V_S0_HDD_SNS_R

PP12V_S0_HDD_FET

=PP1V8_S0_CAMERA

=PP1V8_S0_GPU_VDD

=PPVDDCI_S0_GPU

=PPGPUCORE_S0_SNS

PP1V5R1V35_S0_GPU_REG
=PP1V35_S0_GPU_FBVDDQ

PP1V8_S0_GPU_VDD_REG

=PP1V8_S0_DP

=PPVCCGT_S0_SNS_CPU

MAKE_BASE=TRUE

PPHDD_S0

PP12V_S0_CPUCORE_FLT

MAKE_BASE=TRUE

=PP12V_S0_AUDIO_SPKRAMP

PP12V_S0_FET

=PP5V_S0_REG_VDDCI

=PP3V3_S0_SMC

=PP3V3_S0_CAMERA

=PP3V3_S0_SMBUS_SMC_2

=PP5V_S0_HDD_PWR

=PP1V8_S0_AUD_DIG

=PPHDD_S0_SNS_R

PPFBVDDQ_S0_GPU

MAKE_BASE=TRUE

=PP5V_S0_ISENSE

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_VRD

=PP5V_S0_HDD

PPVDDCI_S0_GPU

MAKE_BASE=TRUE

PPVDDCI_S0_GPU_REG

PP5V_S0

MAKE_BASE=TRUE

=PP5V_S0_CAMERA

PP3V3_S5_REG_SSD

=PP12V_S0_HDD_PWR

PPGPUCORE_S0_REGPPGPUCORE_S0

MAKE_BASE=TRUE

=PP5V_S0_BKLT

=PP5V_S0_AUDIO

PP5V_S0_FET

PP12V_S0_SNS_FBVDDQ

MAKE_BASE=TRUE

PP12V_S0_HDD

PP12V_S0

MAKE_BASE=TRUE

=PP12V_S0_SNS_FBVDDQ_R

=PP12V_S0_REG_GPU_1V8

=PP12V_S0_REG_CPUCORE

PP12V_S0_SNS_CPUCORE

=PP12V_S0_SNS_CPUCORE_R

PP12V_S0_CPUCORE_FLT

=PP12V_S0_REG_GPU_VDDCI

=PP12V_S0_HDD

=PP12V_S0_FAN
=PP12V_S0_SNS_GPUCORE_R

=PP12V_S0_CPUCORE

=PP12V_S0_LCD

=PP3V3_S0_BKLT

=PP3V3_S0_SMBUS_SMC_3

=PP3V3_S0_MEM_A_SPD

=PP5V_S0_REG_GPUCORE

PP5V_S0_HDD_FET

=PP3V3_S0_LED

=PP3V3_S0_GPU

PP3V3_S5_SSD

MAKE_BASE=TRUE

PPHDD_S0_SNS

PPVCCGT_S0_CPU_REG

MAKE_BASE=TRUE

PPVCCSA_S0_CPU

=PPVCCSA_S0_CPU

PPVCCSA_S0_CPU_REG

PP12V_S5_FET

=PP12V_S5_SNS

=PP12V_S5_PWRCTL

=PP12V_S5_REG_VDDQ_S3

=PPHV_SW_TBTAPWRSW
=PPHV_SW_TBTBPWRSW

MAKE_BASE=TRUE

PP12V_S0_CPUCORE

=PPGPUCORE_S0

PP3V3_G3

MAKE_BASE=TRUE

=PP3V3_G3_PCH_RTC

PP3V3_G3_RTC

=PP3V3_G3H_SSD

=PP3V3_G3H_T112

MAKE_BASE=TRUE

PP3V42_G3H

PP12V_ACDC

MAKE_BASE=TRUE

PP12V_S5_SSD_FET

=PP12V_S5_REG_P1V0_S5

MAKE_BASE=TRUE

PP12V_S5

=PP12V_S5_FET_P3V3_S5_P5V_S4

MAKE_BASE=TRUE

PPVCCIO_S0

PP5V_S4_REG

=PP5V_S4_FET_P5V_S0

=PP5V_S4_REG_VDDQ_S3

=PP5V_S4_USB

=PP3V3_S4_FET_ENET
=PP3V3_S4_PWRCTL

=PP3V3_S4_LED
=PP3V3_S4_MEMRESET

=PP3V3_S4_TBT

=PP3V3_S4_AP

=PP3V3_S4_TBTAPWRSW

=PP3V3_S4_SMC

=PP3V3_S4_PCH_VCC

MAKE_BASE=TRUE

PP3V3_S4_SSD_FET

MAKE_BASE=TRUE

PP3V3_S4_SSD

PP3V3_S4_FET_SSD

PPVSSD_S4_REG_SNS

PP3V3_S4_FET

=PP3V3_S4_TBTBPWRSW

=PPVSSD_S4_CONN

=PP1V0_S5_XDP
=PP1V0_S5_FET_PP1V0_S3

=PP1V0_S5_PCH_VCC

=PPDDRVTT_S0_MEM_B

PPDDRVTT_S0_LDO

=PPDDRVTT_S0_MEM_A

=PPVCCIO_S0_SNS_CPU_R

PPVCCIO_S0_CPU_REG

PPVCCIO_S0_CPU

MAKE_BASE=TRUE

=PPVCC_S0_CPU

=PPVSSD_S4_REG_SNS_R

PPVDDQ_S3_REG

PPVDDQ_S3_DDR

MAKE_BASE=TRUE

=PP5V_S0_REG_GPU_0V95

=PP3V3_TBTLC

PP0V95_S0_GPU_VDDC_REG

=PP3V3_S0_REG_GPUCORE

=PP3V3_S0_FAN

=PP3V3_S0_INTDPMUX

=PP3V3_S0_LED_SATA

=PP3V3_S0_SMBUS_SMC_0
=PP3V3_S0_SMBUS_SMC_1

=PP1V8_S0_GPU_PEX_IO

MAKE_BASE=TRUE

PP1V8_S0_MISC

PP3V3_TBTLC

MAKE_BASE=TRUE

PP12V_S0_SNS_GPU_AUX

=PP12V_S0_REG_GPU_0V95

MAKE_BASE=TRUE

PP12V_S0_GPU_AUX

=PP3V3_S5_NON_SSD

PP1V0_S5_REG

MAKE_BASE=TRUE

PPDDRVTT_S0

MAKE_BASE=TRUE

PP5V_S4

=PP3V3_S0_MEM_B_SPD
=PP3V3_S0_PCH_VCC

=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SDCARD

=PP3V3_S0_SMBUS

=PP3V3_S0_DP
=PP3V3_S0_ENET

=PP3V3_S0_SENSE

PP1V35_S3_CPU

MAKE_BASE=TRUE

PP5V_S0_HDD

MAKE_BASE=TRUE

PP12V_S0_FBVDDQ

MAKE_BASE=TRUE

=PP12V_S0_REG_FBVDDQ

PPVCC_S0_CPU

MAKE_BASE=TRUE

=PP1V0_S3_VCCST

=PP1V35_S3_SNS_R

=PPVDDQ_S3_LDO_DDRVTT

PP1V35_S3_SNS

=PPVDDQ_S3_CPU

=PP1V0_S3_SMC

=PP3V3_S0_ALS

=PPVDDQ_S3_MEMRESET

=PPVDDQ_S3_MEM_B

PPVDDQ_S3_SNS_DDR
=PPDDR_S3_MEMVREF

=PP5V_S0_REG_CPUVCC_S0
=PP5V_S0_REG_FBVDDQ

=PP5V_S0_VRD

=PP3V3_S4_SDCARD

PP3V3_S4

MAKE_BASE=TRUE

=PPVCCGT_S0_CPU

MAKE_BASE=TRUE

PPVCCGT_S0_CPU

PP3V3_S0_FET
=PP3V3_S0_AUDIO
=PP3V3_S0_AUDIO_DIG

PP3V3_S0

MAKE_BASE=TRUE

=PPVCCIO_S0_CPU

PPVCCIO_S0_SNS_CPU

=PPVDDQ_S3_MEM_A

=PPVDDQ_S3_SNS_DDR_R

PP3V3_ENET_FET
=PP3V3_ENET_PHY

PP3V3_ENET

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPVDDQ_S3

PP1V0_S3_CPU_VCCST

MAKE_BASE=TRUE

=PP1V0_S3_XDP
=PP1V0_S3_CPU

PP1V0_S3_FET

MAKE_BASE=TRUE

PP12V_G3H

PP12V_G3H_ACDC

PP3V42_G3H_REG

=PP3V3_G3H_SMC
=PP3V3_G3H_SMC_USBMUX
=PPVIN_G3H_SMCVREF

=PP12V_G3H_P3V42

=PP3V3_G3H_RTC_D

=PP3V3_G3H_BT

=PP12V_G3H_FET_P12V_S5_SSD

=PP12V_G3H_FET_P12V_S5

=PP12V_G3H_FET_P12V_S0

=PP3V3_S4_AUDIO_DIG

=PPVCC_S0_SNS_CPU

PPVCC_S0_CPU_REG

=PP0V95_S0_GPU_PCIEVDDC

=PP0V95_S0_GPU_VDDC

PP0V95_S0_GPU_VDDC

MAKE_BASE=TRUE

=PP12V_S0_BKLT

PP12V_G3H_SNS

=PP12V_G3H_SNS_R

=PP3V3_S5_PCH_VCC

=PP3V3_S5_ROM
=PP3V3_S5_VRD

=PP3V3_S5_RSTBUF

PP3V3_S5_FET_NON_SSD

MAKE_BASE=TRUE

PP5V_S5

MAKE_BASE=TRUE

PP12V_S5_SSD

PP5V_S5_LDO

=PP3V3_S5_SMC

=PP3V3_S5_FET_P3V3_S4

=PP3V3_S5_FET_P3V3_S0

=PP12V_S5_FET_PWRCTL

=PP12V_S5_FET_P12V_S5_NON_SSD

=PP5V_S5_REG_P1V0
=PP5V_S5_XDP

PP1V0_S5

MAKE_BASE=TRUE

=PP3V3_S5_SSD_PWRCTL

=PPVSSD_S5_FET_S4_SSD

=PP3V3_S5_SENSE

MAKE_BASE=TRUE

PP3V3_S5

=PP3V3_S5_LED

=PP3V3_S5_PWRCTL

MAKE_BASE=TRUE

PPHDD12_S0

=PP12V_S0_REG_GPUCORE

PP12V_S0_SNS_GPUCORE

MAKE_BASE=TRUE

PP12V_S0_GPUCORE

GND

MAKE_BASE=TRUE

SYNC_DATE=11/20/2013

Power Connectors/Aliases

SYNC_MASTER=J78_MLB

49

49

34

39 38

82 81 80 79 74

75

48

85

85 78 77 76 75

88

41

48

89 61

55 54

71

86

45

39 38

47

34

52

49

48

27

85 65 61 60

34

86

38

66

34

84 83

69

59 52

71

48

48

88

68 65 63 62 61

48

48

89 61

86

34

51

48

61

40

69

47

22 21

82

34

3

88 87 86 81 80 49

49

63

10 8

68

71

48

72 71

64

29

30

75

15 12

18

71 66 60

46

71

67

66

66

71

64

43 42

36

71 64 43 42

3

6

72 31 30 29 27 26 19

45 32

29

45

14 13

33

49

71

30

33

17

71

15 11

24 23

64

22 21

48

65

10 8

49

64

87

19

87

82

51

41 40

33

47

47

27 26

48

87

66

67

24 23

19 18 15 14 12 11

72 71

19

37

47

40 31

35

50 49 48 34

85

61 12

49

64

49

10 8

45

38

12

24 23

49

20

68 65 63 62 61

85

84 83 82

37

10 8

71

58 55 54 52 38

56

17 10 8 5

48

22 21

49

36

36 35

17

10 8 6

71

60

60

51 45 44

42

45

60

18

32

71 66

71

71

56

48

62

87 80 79 74

69

48

48

19 18 15 14 13 12

46 17

67 66

19

66

66

45 33

71

71

71 33

66

67

17

66 33

33

48

3

73 72 66 33

82

48

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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A

B

C

345678

D

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8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

GPU ALIASES

PEG aliases

GPU VDDCI PGOOD

90 OF 93

113 OF 121

0.24.0

051-00673

=PEG_R2D_C_N<15..0>

PEG_D2R_P<0..15>

MAKE_BASE=TRUE

=PEG_D2R_N<15..0>

=PEG_D2R_P<15..0>

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

=PEG_R2D_C_P<15..0>

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

TP_VR_GPU_RESET_L

TP_GPU_RESET_L

PM_EN_REG_GPU_VDDCI_S0

MAKE_BASE=TRUE

TP_PM_EN_REG_GPU_VDDCI_S0

VR_GPU_RESET_L

MAKE_BASE=TRUE

GPU_RESET_L

MAKE_BASE=TRUE

SYNC_DATE=12/05/2013SYNC_MASTER=J78_MLB

Signal Aliases

5

74

5

5

74 5

74

74

19

19

86

72

82

80 74

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

PCH Miscellaneous

PCH Clocks

CPU Reserved

91 OF 93

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

115 OF 121

0.24.0

051-00673

GPU_PLL_ANALOG_IN

MAKE_BASE=TRUE

TP_CLINK_DATA

TP_CLINK_CLK

TP_CLINK_RESET_L CLINK_RESAT_L

MAKE_BASE=TRUE

GPU_CB_REFCKN_OUT1

MAKE_BASE=TRUE

PEG_CLKREQ_L

NC_HDA_SDIN1

MAKE_BASE=TRUE

NC_PEG_CLKREQ_L

MAKE_BASE=TRUE

GPU_NEPTUNE_EMERALD_ID

MAKE_BASE=TRUE

NC_GPU_IS_AMETHYST

DP_INT_PIN_57

MAKE_BASE=TRUE

NC_DP_INT_PIN_55

TP_GPU_PLL_ANALOG_IN

MAKE_BASE=TRUE

NC_DP_INT_PIN_57

DP_INT_PIN_55

TP_HDA_SDIN1

TP_ITPXDP_CLK100MP

TP_ITPXDP_CLK100MN

ITPXDP_CLK100M_P

MAKE_BASE=TRUE

CPU_CFG<15..12> TP_CPU_CFG<15..12>

MAKE_BASE=TRUE

ITPXDP_CLK100M_N

MAKE_BASE=TRUE

CLINK_DATA

MAKE_BASE=TRUE

CLINK_CLK

MAKE_BASE=TRUE

TP_GPU_CB_REFCKN_OUT1

TP_GPU_CB_REFCKP_OUT1

MAKE_BASE=TRUE

GPU_CB_REFCKP_OUT1

PCH_2

MAKE_BASE=TRUE

PM_SLP_A_L

MAKE_BASE=TRUE

TP_TBT_MONDC1 TBT_MONDC1

MAKE_BASE=TRUE

TP_PCH_SLP_LAN_L PCH_SLP_LAN_L

MAKE_BASE=TRUE

TP_TBT_PCIE_RESET0_L TBT_PCIE_RESET0_L

MAKE_BASE=TRUE

TP_PCH_2

TP_PM_SLP_A_L

SYNC_DATE=12/05/2013

Unused Signal Aliases

SYNC_MASTER=J78_MLB

12

12

12

11

80 14

40

40

11

17 11

17 6

17 11

26

12

26

11

12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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345678

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PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

BGA Area Constraints

Fixed and Dielectric

General Physical Rule Definitions

General Spacing Definitions

Default

Board Stack-up

Top Signal 0.5 oz (Cu plated)

FINISHED BOARD THICKNESS: 1.94 MM

Plane 1 oz
Core

0.5 oz

Signal

Prepreg

Plane

Core

Core

Plane 1 oz

Plane

Prepreg

Signal

Signal

1 oz

0.076 MM

0.076 MM

Core 0.101 MM

Core

Plane 1 oz

1 ozPlane

0.071 MMPrepreg

0.071 MMPrepreg

0.5 oz (Cu plated)SignalBtm

Prepreg 0.115 MM

0.5 oz

0.101 MM

0.5 oz

0.115 MM

0.380 MM

0.5 oz

0.380 MM

1 oz

Prepreg

Signal

2

3

4

6

7

8

9

10

11

5

0.076 MM

Power and Common

GENERIC

BGA

J17 BOARD SPECIFIC PHYSICAL AND SPACING CONSTRAINTS

92 OF 93

120 OF 121

0.24.0

051-00673

0.1 MM0.190 MM

0.125 MM 0.085 MM =STANDARD85_OHM_DIFF YTOP,BOTTOM

0.190 MM 0.1 MM

0.085 MMY*85_OHM_DIFF =STANDARD0.121 MM

0.1 MM

*80_OHM_DIFF 0.136 MMY =STANDARD0.085 MM

0.190 MM

0.150 MM

0.085 MM =STANDARD0.185 MM68_OHM_DIFF TOP,BOTTOM Y

0.1 MM

=STANDARD0.171 MM68_OHM_DIFF * Y 0.085 MM

0.130 MM 0.1 MM

0.085 MM =STANDARDY 0.085 MM

=STANDARD

55_OHM_SE TOP,BOTTOM

=STANDARD

50_OHM_SE 0.100 MMISL5,ISL8

=STANDARD=STANDARD

Y =STANDARD0.085 MM

0.085 MM* Y

=STANDARD

50_OHM_SE

=STANDARD

=STANDARD0.090 MM

Y 0.085 MMTOP,BOTTOM 0.135 MM

=STANDARD =STANDARD

=STANDARD45_OHM_SE

0.126 MM

=STANDARD

Y

=STANDARD

45_OHM_SE ISL5,ISL8 0.085 MM =STANDARD

* 0.085 MMY

=STANDARD

42_OHM_SE 0.130 MM

=STANDARD

=STANDARD

=STANDARD39_OHM_SE

=STANDARD

0.175 MMYTOP,BOTTOM

=STANDARD

0.085 MM

16.2MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA,BGA_TBT,BGA_VRAM

0.1 MMY*

0 MM 0 MM

DEFAULT 0.070 MM 10 MM

10 MM

=DEFAULT

* Y =DEFAULTSTANDARD

=DEFAULT

=DEFAULT

=STANDARD

ISL5,ISL8 Y =STANDARD0.085 MM

=STANDARD

34_OHM_SE 0.205 MM

=STANDARDY

=STANDARD

0.085 MM0.220 MM

=STANDARD

34_OHM_SE TOP,BOTTOM

*

=STANDARD=STANDARD

Y39_OHM_SE 0.150 MM =STANDARD0.085 MM

TOP,BOTTOM

=STANDARD

0.085 MM

=STANDARD

42_OHM_SE Y 0.155 MM =STANDARD

45_OHM_SE 0.115 MM* Y 0.085 MM

=STANDARD=STANDARD

=STANDARD

* Y

=STANDARD

0.085 MM34_OHM_SE

=STANDARD

=STANDARD0.185 MM

*

1000

GND_P2MM =2:1_SPACING

=STANDARDGND_ISO *

8000

=2:1_SPACING*PWR_P2MM

1100

BGA_P1MM *

?

=STANDARD

0.075 MM0.075 MM =STANDARD*

=STANDARD

55_OHM_SE Y

=STANDARD

=1:1_SPACINGGENERIC_ISO *

?

STANDARD =DEFAULT

?

*

0.101 MMISL3,ISL101X_DIELECTRIC

?

ISL5,ISL842_OHM_SE =STANDARD0.085 MMY

=STANDARD

0.145 MM

=STANDARD

0.111 MMYTOP,BOTTOM 0.085 MM =STANDARD

0.200 MM

90_OHM_DIFF

0.1 MM

TOP,BOTTOM1X_DIELECTRIC 0.071 MM

?

0.076 MM*1X_DIELECTRIC

?

* 0.1 MM

?

DEFAULT

0.109 MM

0.1 MM

Y 0.085 MM90_OHM_DIFF * =STANDARD

0.200 MM

0.1 MM0.200 MM

0.086 MMY =STANDARD0.085 MM*100_OHM_DIFF

TOP,BOTTOM

0.1 MM0.185 MM

0.141 MMY =STANDARD0.085 MM80_OHM_DIFF

BGA_P1MM* * BGA

*

?

0.1 MM1:1_SPACING

0.080 MM0.080 MM =STANDARDY55_OHM_SE ISL5,ISL8

=STANDARD=STANDARD

=STANDARD=STANDARD

Y =STANDARD39_OHM_SE 0.165 MMISL5,ISL8 0.085 MM

0.1 MM

100_OHM_DIFF

0.230 MM

0.090 MM =STANDARD0.085 MMYTOP,BOTTOM

J95 RULE DEFINITIONS

SYNC_DATE=06/30/2014SYNC_MASTER=J78_MLB

TOP,BOTTOM Y50_OHM_SE 0.085 MM

=STANDARD=STANDARD

=STANDARD0.105 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

BOARD AREASBOARD LAYERS

BOARD UNITS

(MIL or MM)

ALLEGRO

VERSION

TABLE_BOARD_INFO

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_PHYSICAL_RULE_ITEM

www.laptoprepairsecrets.com

J17 BOARD SPECIFIC PHYSICAL AND SPACING CONSTRAINTS

BGA

GENERIC

Power and Common

0.076 MM

5

11

10

9

8

7

6

4

3

2

Signal
Prepreg

1 oz

0.380 MM

0.5 oz

0.380 MM

0.115 MM

0.5 oz

0.101 MM

0.5 oz

0.115 MMPrepreg

Btm Signal 0.5 oz (Cu plated)

Prepreg 0.071 MM

Prepreg 0.071 MM
Plane 1 oz

1 ozPlane

Core

0.101 MMCore

0.076 MM

0.076 MM

1 oz

Signal

Signal

Prepreg

Plane

1 ozPlane

Core

Core

Plane
Prepreg
Signal

0.5 oz

Core

1 ozPlane

FINISHED BOARD THICKNESS: 1.94 MM

0.5 oz (Cu plated)SignalTop

Board Stack-up

Default

General Spacing Definitions

General Physical Rule Definitions

Fixed and Dielectric

BGA Area Constraints

93 OF 93

121 OF 121

0.24.0

051-00673

0.085 MM =STANDARD0.150 MM39_OHM_SE Y

=STANDARD =STANDARD

*

0.105 MM =STANDARD

=STANDARD =STANDARD

0.085 MM50_OHM_SE YTOP,BOTTOM

SYNC_MASTER=J78_MLB SYNC_DATE=06/30/2014

J95 RULE DEFINITIONS

TOP,BOTTOM Y 0.085 MM =STANDARD0.090 MM

0.230 MM

100_OHM_DIFF

0.1 MM

0.085 MMISL5,ISL8 0.165 MM39_OHM_SE =STANDARDY

=STANDARD =STANDARD

=STANDARD =STANDARD

ISL5,ISL855_OHM_SE Y =STANDARD0.080 MM 0.080 MM

1:1_SPACING 0.1 MM

?

*

BGA** BGA_P1MM

80_OHM_DIFF 0.085 MM =STANDARDY 0.141 MM

0.185 MM 0.1 MM

TOP,BOTTOM

100_OHM_DIFF * 0.085 MM =STANDARDY 0.086 MM

0.200 MM 0.1 MM

0.200 MM

=STANDARD*90_OHM_DIFF 0.085 MMY

0.1 MM

0.109 MM

DEFAULT

?

0.1 MM*

?

1X_DIELECTRIC * 0.076 MM

?

0.071 MM1X_DIELECTRIC TOP,BOTTOM

0.1 MM

90_OHM_DIFF

0.200 MM

=STANDARD0.085 MMTOP,BOTTOM Y 0.111 MM

=STANDARD

0.145 MM

=STANDARD

Y 0.085 MM =STANDARD42_OHM_SE ISL5,ISL8

?

1X_DIELECTRIC ISL3,ISL10 0.101 MM

*

?

=DEFAULTSTANDARD

?

*GENERIC_ISO =1:1_SPACING

=STANDARD

Y55_OHM_SE

=STANDARD

* =STANDARD0.075 MM 0.075 MM

=STANDARD

?

*BGA_P1MM

1100

PWR_P2MM * =2:1_SPACING

8000

*GND_ISO =STANDARD

=2:1_SPACINGGND_P2MM

1000

*

0.185 MM =STANDARD

=STANDARD

34_OHM_SE 0.085 MM

=STANDARD

Y*

=STANDARD

=STANDARD =STANDARD

0.085 MMY* 0.115 MM45_OHM_SE

=STANDARD0.155 MMY42_OHM_SE

=STANDARD

0.085 MM

=STANDARD

TOP,BOTTOM

TOP,BOTTOM34_OHM_SE

=STANDARD

0.220 MM 0.085 MM

=STANDARD

Y =STANDARD

0.205 MM34_OHM_SE

=STANDARD

0.085 MM =STANDARDYISL5,ISL8

=STANDARD

=DEFAULT

=DEFAULT

STANDARD =DEFAULTY*

=DEFAULT

10 MM

10 MM0.070 MMDEFAULT

0 MM0 MM

* Y 0.1 MM

NO_TYPE,BGA,BGA_TBT,BGA_VRAMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM MM 16.2

0.085 MM

=STANDARD

TOP,BOTTOM Y 0.175 MM

=STANDARD

39_OHM_SE =STANDARD

=STANDARD

=STANDARD

0.130 MM42_OHM_SE

=STANDARD

Y 0.085 MM*

=STANDARD0.085 MMISL5,ISL845_OHM_SE

=STANDARD

Y

=STANDARD

0.126 MM

45_OHM_SE =STANDARD

=STANDARD=STANDARD

0.135 MMTOP,BOTTOM 0.085 MMY

0.090 MM =STANDARD

=STANDARD

50_OHM_SE

=STANDARD

Y* 0.085 MM

0.085 MM =STANDARDY

=STANDARD =STANDARD

ISL5,ISL8 0.100 MM50_OHM_SE

=STANDARD

TOP,BOTTOM55_OHM_SE

=STANDARD

0.085 MMY =STANDARD0.085 MM

0.1 MM0.130 MM

0.085 MMY*68_OHM_DIFF 0.171 MM =STANDARD

0.1 MM

YTOP,BOTTOM68_OHM_DIFF 0.185 MM =STANDARD0.085 MM

0.150 MM

0.190 MM

0.085 MM =STANDARDY 0.136 MM80_OHM_DIFF *

0.1 MM

0.121 MM =STANDARD85_OHM_DIFF * Y 0.085 MM

0.1 MM0.190 MM

TOP,BOTTOM Y85_OHM_DIFF =STANDARD0.085 MM0.125 MM

0.190 MM 0.1 MM

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II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

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2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

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BOARD UNITS

(MIL or MM)

ALLEGRO

VERSION

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