Apple iMac A1419 Schematic

J95 MLB SKL EMERALD

1 OF 93

LAST_MODIFICATION=Thu Feb 12 14:48:08 2015

CPU & CHIPSET: CPU CORE VR (VCC)

CPU & CHIPSET: PCH 1V0 VR

CPU & CHIPSET: CPU CORE VR (VCCSA)

DISPLAY: LCD Backlight Driver (LP8565)

DRAM: SO-DIMM Connector A Slot0

SMC: SMBus Connections

SMC: Controller Support

USB-A: EXTERNAL USB PORTS A & B

samihan_mlb_slk

samihan_mlb_slk

CAMERA: Controller Support

DEBUG: LEDs

BOM Configuration

SCHEM,K72,MLB ULTIMATE

HDD: SSD Temp Sense

01/30/2015

samihan_mlb_slk

DRAM: SO-DIMM CONNECTOR B SLOT1

DRAM: SO-DIMM Connector A Slot1

01/30/2015

01/30/2015

samihan_mlb_slk

TBT/DP: Host (1 of 2)

WIRELESS: Airport/Bluetooth

samihan_mlb_slk

35

01/30/2015

PLATFORM POWER: FET-Controlled S0 and S4

samihan_mlb_slk

AUDIO: Detects/Grounding

samihan_mlb_slk

samihan_mlb_slk

DRAM: VREF/VTT EN

6

TBT/DP: Connector A

samihan_mlb_slk

samihan_mlb_slk

67

69

68

64

65

66

63

62

61

60

56

55

54

53

52

51

50

47

46

45

44

43

42

41

40

39

38

37

35

34

33

32

30

29

28

27

26

25

24

23

22

20

19

18

16

15

14

13

11

10

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_skl

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/15/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

9

7

6

5

4

3

2

1

jerrychow_skl

jerrychow_skl

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

12/12/2014

12/12/2014

103

104

105

106

107

109

110

111

112

113

114

119

120

82

84

85

86

87

88

90

92

93

96

97

99

101

102

jerrychow_skl

jerrychow_skl

jerrychow_skl

jerrychow_skl

12/12/2014

12/12/2014

12/12/2014

12/12/2014

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

mlb_hsw_em

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

jerrychow_skl

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

01/30/2015

02/02/2015

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/12/2014

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

mlb_hsw_em

samihan_mlb_skl

samihan_mlb_skl

01/15/2015

01/15/2015

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

12/19/2014

01/30/2015

01/30/2015

01/30/2015

01/30/2015

70

71

72

73

75

77

78

81

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

01/30/2015

01/30/2015

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01/30/2015

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

74

73

72

71

70

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

41

40

39

38

37

36

34

33

32

31

30

29

28

27

26

25

23

22

21

20

19

18

17

16

15

14

12

11

10

9

8

7

5

4

1

J95 RULE DEFINITIONS

Unused Signal Aliases

Signal Aliases

GRAPHICS: GPU VDDCI VR

GRAPHICS: GPU VDDQ VR

GRAPHICS: GPU CORE VR (PHASES 4-6)

GRAPHICS: GPU CORE VR (PHASES 1-3)

GRAPHICS: GPU CORE VR

GFX: Emerald Gnds & Unused

GFX: Emerald GPIOS,CLK,STRAPS

GFX: Emerald IntDP/TBT DP

GDDR5 Frame Buffer B

GDDR5 Frame Buffer A

GFX: Emerald FRAME BUFFER

GFX: Emerald CORE/FB POWER

GFX: Emerald PCIe

PLATFORM POWER: PM Power Good

PLATFORM POWER: Regulator Enables

DISPLAY: Backlight Driver 2

PLATFORM POWER: 3.3V S5/5V S4 VR

CPU & CHIPSET: CPU VDDQ VR

CPU & CHIPSET: CPU CORE VR (VCCGT)

CPU & CHIPSET: CPU CORE VR

PLATFORM POWER: Connectors / VReg G3Hot

AUDIO: Speaker ID

Audio: Spkr/Mic Conn.

AUDIO: Jack, Mikey, CHS Switch

AUDIO: RIGHT SPKR AMP

AUDIO: LEFT SPKR AMP

AUDIO: HEADPHONE AMP

AUDIO: CODEC/REGULATORS

FAN: System Fan

CPU & CHIPSET: SPI and Debug Connector

SMC: Controller

USB-A: EXTERNAL USB PORTS C & D

DISPLAY: MUXing

DISPLAY: Support

CAMERA: Controller

SD CARD: Connector

ETHERNET: Support & Connector

ETHERNET: PHY (CAESAR IV)

SDD/HDD:SATA/SSD Connectors

Thunderbolt: Power Support

CPU & CHIPSET: Chipset Support

CPU & CHIPSET: XDP

CPU & CHIPSET: PCH Grounds

CPU & CHIPSET: Clocks/HDA/JTAG

CPU & CHIPSET: CPU Power

CPU & CHIPSET: CPU DMI/PEG/FDI/RSVD

SENSORS: Temperature Sensors

SENSORS: I and V Sense(Continued)

SENSORS: I and V Sense

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

TBT/DP: Host (2 of 2)

DRAM: ALIASES AND BITSWAPS

DRAM: SO-DIMM CONNECTOR B SLOT0

CPU & CHIPSET: Project Chipset Support

samihan_mlb_slk

CPU & CHIPSET: CPU VCCIO VR

J95 RULE DEFINITIONS

samihan_mlb_slk

GRAPHICS: GPU 1V8 VR

75

01/30/2015

samihan_mlb_slk

24

CPU & CHIPSET: CPU Ground

01/30/2015

01/30/2015

samihan_mlb_slk

TBT/DP: Connector B

TBT/DP: DDC Crossbar

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

Power Connectors/Aliases

GRAPHICS: GPU 0V95 VR

samihan_mlb_slk

13

samihan_mlb_slk

samihan_mlb_slk

CPU & CHIPSET: CPU Clock/Misc/JTAG/CFG

8

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

samihan_mlb_slk

2

3

CPU & CHIPSET: PCH RTC/DMI/PM/CPU_Misc

CPU & CHIPSET: PCH GPIO/Misc

CPU & CHIPSET: PCH Power/Decoupling

42

69

MECHANICAL: Holes/PD parts

CPU & CHIPSET: PCH PCI-E/USB

CPU & CHIPSET: CPU Decoupling

76

12

samihan_mlb_slk

CPU & CHIPSET: DDR3L Interfaces

SCHEM,MLB,SKYLAKE,EMERALD,J95

051-00673

2015-02-12

1 OF 121

0.24.0

LAST_MODIFIED=Thu Feb 12 14:48:08 2015

SCHEM,J95, mlb_skl_EM

TITLE=J95_skl_am
ABBREV=DRAWING

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

ECNREV DESCRIPTION OF REVISION

DRAWING TITLE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

CK
APPD

2 1

1245678

B

D

6 5 4 3

C

A

PAGE

C

A

D

DATE

R

SHEET

D

SIZEDRAWING NUMBER

BRANCH

7

B

3

II NOT TO REPRODUCE OR COPY IT

IV ALL RIGHTS RESERVED

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

SYNCCONTENTS

SYNCCONTENTSPAGE

<CSA>

PAGE

DATE

DATE

<CSA>

DRAWING

DRAWING

www.laptoprepairsecrets.com

CPU SOCKET

J95 ALTERNATES

J95 SCHEMATIC / PCB #'S

GPU and VRAM

CPUs

BOM Variants

.

BOM Groups

Programmable Parts

Bar Code Labels / EEEE #'s

ASICs

2 OF 93

2 OF 121

0.24.0

051-00673

J95_PROGPARTS SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG

311S0370

311S00004

Config. Logic GateALL

138S0750138S0855

4.7uF 0402ALL

J95_COMMON

COMMON,VR_BULKCAP:CURRENT,ALTERNATE,J95_PROGPARTS,GPU_AM_EM,GPU_Emerald,XDP,SPEAKERID,FBVDDQ_DFLT:1V5,SMCREG:SUP

PCBA,MLB SKL,EMERALD PROA,VRAM_HYNIX,2GB,J95

J95,MLB_CMNPTS,CPU:BEST,SSD:Y,GPU:EMERALD_PROA,FB:4G_HYNIX,EEEE:GHN4

639-00957

1

337S00114

CPU

CRITICAL

CPU,SKL,QH8E,ES,P0,4/2,2.2,95W,LGA1151

CPU:ULT

CPU,SKL,QHQF,ES2,Q0,2.6G,95W,LGA1151

CPU

CPU:CTO_2.6G

CRITICAL

337S00122

1

CPU,SKL,QH73,ES,P0,4/2,2.3,95W,LGA1151

CRITICAL1337S00113

CPU

CPU:CTO

XDP_CONN,T112,DEVEL_AUDIO

J95_DEVEL

BOM Configuration

SYNC_MASTER=J17_DINI SYNC_DATE=03/15/2013

378S0391 378S0390

DEGUG LEDSALL

311S00008

311S0271

AND GATEALL

376S00016

ALL MOSFET,P-CH,20V,1A

376S0644

SOCKET.MOLEX,LGA1151,H4

CRITICAL

U05001

511S00002

J95_COMMON

PCBA,MLB_SKL,COMMON PARTS,J95

685-00062

376S00015

XSTR,FET,DL NCH,60V

376S0610

ALL

138S1103

4.7uF 0402

138S0719

ALL

107S0240107S0255

Alt 1mOhm sense

ALL

107S00029107S00030

ALL

Alt 5mOhm sense

ALL197S0479

12MHZ CAM/NXP XTAL

197S0478

377S0126377S0147 ALL

USB Diode Array

CRITICALPCBF,MLB SKL EM,J95820-00291 1 J95PCB1

LABEL,MLB,2D EEEE_GHN5 EEEE:GKCV

CRITICAL825-7896

1

CPU,SKL,QH8F,ES2,P0,4/2,2.2GHZ,65W,LGA1151

CPU:BEST

CRITICAL

337S00121

1

CPU

CRITICAL

337S00124

1

U1100

IC,PCH-H,SKL,SUPRSKU,C0,QHPT,ES2,BG1151

343S0616

1

IC,BCM57766A1,ENET&SD,8X8

U3900

CRITICAL

353S3328

353S00095

2:4 Diff MUXALL

132S0448132S0447

ALL

0.1uF 0201

311S0377

AND GATEALL

311S0250

128S0220128S0398

ALL 3.3V INPUT CAP

341S3778 IC,CAMERA FLASH,V7230,J16/J17

1 U4202

CRITICAL CAMROM:PROG

J95,MLB_CMNPTS,CPU:CTO_2.6G,SSD:Y,GPU:EMERALD_PROA,FB:4G_HYNIX,EEEE:GKCT

639-01039 PCBA,MLB SKL,95W,EMERALD PROA,VRAM_HYNIX,2GB,J95

U9200,U9250,U9300,U9350 FB:4G_HYNIX4333S00043 CRITICAL

IC,HYN,GDDR5,4GBIT,64MX32,7GBPS,25NM

376S00001

376S0659

MOSFET,P-CH,20VALL

ALL372S0186

Alternate Temp Diode

372S0185

FB:4G_ELPIDA4333S00044 CRITICALU9200,U9250,U9300,U9350

IC,ELP,GDDR5,4GBIT,64MX32,7GBPS,25NM

825-7896

LABEL,MLB,2D EEEE:GHN4EEEE_GHN41

CRITICAL

SCH,MLB SKL EM,J95 CRITICAL051-00673 SCH11 J95

155S0830 155S0316

FERR BD,600 OHM,25,0.5A

ALL

138S0775138S0860

Single-source 1uF 402

ALL

138S0638 10uF Caps138S0681 ALL

341S3912

IC,ENETROM,ADESTO,V1,15,J78

U3990

341S00016

197S0480 ALL197S0481

25MHX PCH XTAL

CRITICALPCBA,MLB SKL EM COMMON PARTS,J95685-00062 CMNPTS MLB_CMNPTS1

985-00098

PCBA,DEV,MLB_SKL,J95

DEVELOPMENT,J95_DEVEL

LABEL,MLB,2D EEEE:GHN5EEEE_GHN5

CRITICAL825-7896

1

825-7896 CRITICAL

LABEL,MLB,2D1 EEEE:GKCTEEEE_GHN4

IC,SMC12-B1,40MHZ/50DMIPS,MCU,157BGA

338S1214

CRITICAL SMC:BLANK

1 U5000

341S00152

TBTROM:PROGCRITICAL

U28901

IC,T29,EPROM,FR,VTBD,POC,J95

335S0915

TBTROM:BLANK

1

CRITICAL

U2890

IC,SRL SPI FLASH ROM,4MBIT,50MHZ,USON8

335S0854

1

CRITICAL

U3990

CIVROM:BLANK

1-MBIT,SPI FLASH ROM SOIC, HF

341S3912

IC,ENET ROM,NUMONYX,V1.15,J16/J16G/J17

CIVROM:PROG

U3990

CRITICAL

1

341S00262

1

SMC:PROG

U5000

CRITICAL

IC,SMC-B1,EXTERNAL,VXXXX,POC-S,J78AM

335S0852

CRITICAL

U4202

CAMROM:BLANK

1

IC,FLASH,SPI,1MBIT,3V3

341S00058

CRITICAL BOOTROM:PROG

1 U5210

IC,EFI,V0174,J78

335S00006

U5210

CRITICAL BOOTROM:BLANK

1

IC,64 MBIT SPI SERIAL FLASH

338S1247 1

U2800

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

CRITICAL

J95,MLB_CMNPTS,CPU:BEST,SSD:Y,GPU:EMERALD_PROA,FB:4G_ELPIDA,EEEE:GHN5

639-00959 PCBA,MLB SKL,EMERALD PROA,VRAM_ELPIDA,2GB,J95

PCBA,MLB SKL,95W,EMERALD PROA,VRAM_ELPIDA,2GB,J95 J95,MLB_CMNPTS,CPU:CTO_2.6G,SSD:Y,GPU:EMERALD_PROA,FB:4G_ELPIDA,EEEE:GKCV639-01040

311S0657

311S00072

ALL Dual 2 INP AND GATE

1 CRITICAL

U8700

337S00077 GPU:EMERALD_PROA

IC,GPU,AMD,ES,EMERALD,PROA,128BIT,FCBGA1093

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_HEAD

BOM NUMBER BOM NAME BOM OPTIONS

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

www.laptoprepairsecrets.com

THIS LED IS DRIVEN BY GPU GPIOS:

GFX_OK_L LOW LIGHTS THE LED DIMLY

CPUVCC_S0_PWRGD Led

VIDEO ON Led

GPU GOOD Led

DP_LINK_OK HIGH LIGHTS THE LED FULLY

ALL_SYS_PWRGD Led

S5 Led

VCCIO_S0_PWRGD Led

P1V0_S3_PWRGD Led

3 OF 93

3 OF 121

0.24.0

051-00673

PM_PGOOD_REG_CPUVCC_S0

=PP3V3_S0_LED

=PP3V3_S4_LED

TCON_BLC_EN_LED

VIDEO_ON_DRAIN

VIDEO_ON_R

GPU_PRESENT_R

=PP3V3_S0_LED

GFX_OK_L

CPUVCC_S0_LED_R

DP_LINK_OK

GPU_PRESENT_DRAIN

=PP3V3_S4_LED

=PP3V3_S5_LED

CORE_VOLTAGES_ON

CORE_VOLTAGES_ON_R

ITS_PLUGGED_IN

ALL_SYS_PWRGD

P1V05_S0_LED_R

PM_PGOOD_FET_P1V0_S3

=PP3V3_S4_LED

VCCIO_S0_LED_R

VCCIO_S0_LED

PM_PGOOD_REG_P0V95_S0

P1V05_S0_LED

=PP3V3_S4_LED

CPUVCC_S0_LED

DEBUG: LEDs

SYNC_DATE=02/11/2013SYNC_MASTER=J17_MAX

4

5

3

Q0302

SOT-363

2N7002DW-X-G

CRITICAL

1

2N7002

SOT23-HF1

Q0304

3

2

2

1

3

Q0305

SOT23-HF1

2N7002

2

1

3

SOT23-HF1

2N7002

Q0306

72 71

K

A

CRITICAL

0805

GRN-6MCD-0.03A

LE0305

SILK_PART=5

2

1

R0307

402

1/16W

1K

MF-LF

5%

73 61

K

A

LE0306

SILK_PART=6

0805

GRN-6MCD-0.03A

CRITICAL

2

1

R0308

MF-LF
402

5%
1/16W

1K

87 72

CRITICAL

SILK_PART=7

0805

GRN-6MCD-0.03A

LE0307

A

K

1K

5%

MF-LF

1/16W

402

R0309

1

2

21

R0305

0402

1/16W

5.6K

1%

MF

80 45

2

1

R0306

0201

MF-LF

0.1%

5K

1/20W

2

1

C0303

0.1UF

NOSTUFF

10V
X5R-CERM

10%

0201

DEFAULT_CAPACITOR_100000pF_2_1

2

1

C0302

0201

10V

0.1UF

10%

DEFAULT_CAPACITOR_100000pF_2_1

X5R-CERM

NOSTUFF

2

1

3

Q0303

2N7002

SOT23-HF1

40

80 45

1

2

6

Q0302

CRITICAL

2N7002DW-X-G

SOT-363

K

A

LE0303

GRN-6MCD-0.03A

0805

SILK_PART=3

CRITICAL

2

1

R0303

MF-LF

1/16W

402

1K

5%

K

A

LE0301

GRN-6MCD-0.03A

CRITICAL

SILK_PART=1

0805

2

1

R0301

1K

1/16W

402

MF-LF

5%

K

A

LE0304

SILK_PART=4

GRN-6MCD-0.03A

0805

CRITICAL

73 44

2

1

R0304

1K

1/16W

402

MF-LF

5%

K

A

LE0302

GRN-6MCD-0.03A

0805

CRITICAL

SILK_PART=2

2

1

R0302

1K

MF-LF

1/16W

402

5%

89 3

89 3

89 3

89 3

89

89 3

89 3

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

S

D

G

D

S

G

D

S

G

D

S

G

IN

IN

IN

IN

D

S

G

IN

IN

S

D

G

IN

www.laptoprepairsecrets.com

APN: 860-00201

860-5675 (PLATED HOLE, 8.41mm pad Top, 8mm pad Bot)

EMERALD EMI FENCE

Display EMI Springs

APN: 870-00886

998-5527 (PLATED HOLES, 8MM DIA, 10MM PAD)

(998-5013. PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT)

T29 BUMPER

998-01489 (PLATED HOLES, 2.1MM INNER DIAMETER, 5.5MM PAD)

CPU Heatsink

4MM PLATED HOLES (998-4158)

HEATPIPE MTG HOLES

998-5014 (PLATED HOLES, 4MM DRILL, 8.5MM TOP, 8MM BOT)

SSD STANDOFF

X238D WIRELESS CARD MTG HOLES

APN: 860-00198

Rear Cover

Rear Cover

860-5674 (PCB STANDOFF)

GPU HEATSINK MOUNTING FEATURES

LOL Boss

4 OF 93

4 OF 121

0.24.0

051-00673

FENCE,GPU,EMERALD,90,J95

860-02579

1 GPU_EmeraldCRITICAL

SF0404

SYNC_DATE=02/11/2013SYNC_MASTER=J17_MAX

MECHANICAL: Holes/PD parts

1

2

2.8OD1.2ID-2.6H-SM

NUT0401

SF0403

1

SM

SPRING-FINGER-6.26H

1

SF0402

SM

SPRING-FINGER-6.26H

SF0401

SPRING-FINGER-6.26H

SM

1

NUT0402

STDOFF-7.14OD10H-TH-1.5-5.2

1

NUT0413

1

5.5OD2.65ID-6.5H-SM

CRITICAL

1

ZH0422

4P3R2P1-5P5B-NSP

ZH0421

1

4P3R2P1-5P5B-NSP

10.0R8.0

1

ZH0426

STDOFF-7P14OD16P45H-TH-1.5-5.2A

ZH0418

1

STDOFF-7P14OD16P45H-TH-1.5-5.2A

ZH0415

1

1

ZH0417

8P5R4P0-8P0B-NSP

ZH0416

1

8P5R4P0-8P0B-NSP

8P5R4P0-8P0B-NSP

ZH0414

1

8P5R4P0-8P0B-NSP

1

ZH0413

ZH0403

8P5R5-NSP

1

8P5R5-NSP

ZH0402

1

8P5R5-NSP

ZH0401

11

8P5R5-NSP

ZH0400

ZH0425

1

6P0R3P2-NSP6P0R3P2-NSP

ZH0424

1

6P0R3P2-NSP

ZH0423

1

6P0R3P2-NSP

ZH0420

1

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_5_HEAD

BOM OPTIONCRITICAL

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

to match Intel symbol.

Port D pins out of order

5 OF 93

051-00673

0.24.0

5 OF 121

=PPVCCIO_S0_CPU

=PEG_D2R_N<0>

DMI_S2N_P<3>

DMI_N2S_P<1>

CPU_EDP_RCOMP

=PEG_R2D_C_N<1>

DMI_N2S_N<3>

DMI_N2S_P<3>

DMI_N2S_P<2>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

=PEG_D2R_P<5>

=PEG_R2D_C_N<13>

=PEG_D2R_P<13>

=PEG_D2R_P<7>
=PEG_D2R_P<8>

=PEG_D2R_P<6>

DMI_S2N_P<1> =PEG_D2R_N<4>

=PEG_R2D_C_N<12>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<14>

=PEG_D2R_P<3>
=PEG_D2R_P<4>

=PEG_D2R_P<9>
=PEG_D2R_P<10>

=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>

=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>

=PEG_R2D_C_P<15>

DMI_N2S_P<0>

=PEG_D2R_P<14>

=PEG_D2R_P<11>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<2>

=PEG_D2R_N<3>

DMI_S2N_N<1>

=PEG_D2R_P<2>

=PEG_D2R_N<12>

=PEG_D2R_N<14>

=PEG_D2R_N<11>

DMI_S2N_N<0>

DMI_S2N_P<0>

=PEG_D2R_N<13>

=PEG_D2R_N<15>

=PEG_R2D_C_N<15>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<5>

=PEG_D2R_N<6>

=PEG_D2R_N<2>

=PEG_D2R_P<1>

=PEG_D2R_P<12>

=PEG_D2R_P<15>

=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>

=PEG_D2R_N<5>

=PEG_D2R_N<9>
=PEG_D2R_N<10>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<9>

=PEG_D2R_P<0>

DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<2>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>

=PEG_D2R_N<1>

CPU_PEG_RCOMP

=PPVCCIO_S0_CPU

SYNC_DATE=06/30/2014SYNC_MASTER=J78_MLB

CPU & CHIPSET: CPU DMI/PEG/FDI/RSVD

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

1/20W
MF
201

2

1

R0510

1%

24.9

PLACE_NEAR=U0500.L7:15MM

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

544753

LGA

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

SKYLAKE_S

OMIT_TABLE

U0500

C13D21

E22

A23

D23

C21

D22

B23

C23

B12
A12

E18

D19

E20

B18

D18

C19

D20

C11
B11

A14

B15

A16

B17

B14

C15

B16

C17

E12
D12

D14

M9

D10

C9

H10

G9

E10

D9

G10

F9

V3

U1

V2

A18

B13

544753

LGA

SKYLAKE_S

OMIT_TABLE

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

Y4
AA5
AB3
AC5

Y3
AA4
AB4
AC4

AC1
AD2
AE1
AF3

AC2
AD3
AE2
AF2

L7

B7
C6
D5
E4
F5
G4
H5
J4
K5
L4
M5
N4
P5
R4
T5
U4

B8
C7
D6
E5
F6
G5
H6
J5
K6
L5
M6
N5
P6
R5
T6
U5

A6
B5
C4
D3
E2
F3
G2
H3
J2
K3
L2
M3
N2
P3
R1
T3

A5
B4
C3
D2
E1
F2
G1
H2
J1
K2
L1
M2
N1
P2
R2
T2

1/20W
MF
201

2

1

R0530

1%

24.9

PLACE_NEAR=U0500.M9:15MM

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

89 17 10 8 5

89 17 10 8 5

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

DIGITAL DISPLAY INTERFACES

10 OF 11

EDP

DDI3_AUXP

DDI1_AUXN

DDI3_TXP[3]

DDI3_TXN[0]

DDI2_TXP[2]
DDI2_TXN[3]
DDI2_TXP[3]

DDI2_TXN[1]

DDI2_TXN[2]

EDP_RCOMP

EDP_AUXP

DDI1_TXP[3]

DDI1_TXP[0]

DDI1_TXN[3]

DDI1_TXN[1]

DDI1_TXN[0]

DDI2_TXP[0]

DDI2_TXN[0]

EDP_DISP_UTIL

DDI1_AUXP

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]

EDP_TXP[2]

EDP_TXN[2]

EDP_TXP[3]

EDP_TXN[3]

EDP_AUXN

DDI2_TXP[1]

DDI1_TXP[1]
DDI1_TXN[2]
DDI1_TXP[2]

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

DDI3_AUXN

DDI2_AUXN
DDI2_AUXP

DDI3_TXP[0]
DDI3_TXN[1]
DDI3_TXP[1]
DDI3_TXN[2]
DDI3_TXP[2]
DDI3_TXN[3]

DMI

PCI EXPRESS BASED INTERFACE SIGNALS

1 OF 11

DMI_TXP[3]

DMI_TXP[2]

DMI_TXN[0]

DMI_TXP[1]

DMI_TXP[0]

DMI_TXN[1]

DMI_RXP[3]

DMI_RXP[2]

DMI_RXN[0]
DMI_RXN[1]
DMI_RXN[2]

DMI_RXP[1]

DMI_RXP[0]

DMI_RXN[3]

PEG_TXP[15]

PEG_TXP[13]

PEG_TXP[12]

PEG_TXP[11]

PEG_TXP[9]

PEG_TXP[8]

PEG_TXP[6]

PEG_TXP[5]

PEG_TXP[3]

PEG_TXP[2]

PEG_TXP[1]

PEG_TXP[0]

PEG_TXN[15]

PEG_TXN[14]

PEG_TXN[13]

PEG_TXN[10]

PEG_TXN[9]

PEG_TXN[8]

PEG_TXN[7]

PEG_TXN[6]

PEG_TXN[5]

PEG_TXN[4]

PEG_TXN[3]

PEG_TXN[2]

PEG_TXN[1]

PEG_RXP[8]

PEG_RXP[1]

PEG_RXP[0]

PEG_RXN[15]

PEG_TXN[0]

PEG_RXP[15]

PEG_RXP[14]

PEG_RXP[13]

PEG_RXP[12]

PEG_RXP[11]

PEG_RXP[10]

PEG_RXP[9]

PEG_RXP[7]

PEG_RXP[6]

PEG_RXP[5]

PEG_RXP[4]

PEG_RXP[3]

PEG_RXP[2]

PEG_RXN[7]

PEG_RXN[2]

PEG_RXN[1]

PEG_RXN[0]

PEG_RXN[3]

PEG_RXN[8]

PEG_RXN[5]
PEG_RXN[6]

PEG_RXN[9]
PEG_RXN[10]
PEG_RXN[11]
PEG_RXN[12]
PEG_RXN[13]
PEG_RXN[14]

PEG_TXP[14]

PEG_TXP[10]

PEG_TXP[7]

PEG_TXP[4]

PEG_TXN[11]
PEG_TXN[12]

PEG_RXN[4]

PEG_RCOMP

DMI_TXN[2]
DMI_TXN[3]

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

DDR VTT CNTL Level Shifting Circuitry

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (default) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

R0624.2:

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION(default) 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED(default) 0 = ENABLED

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION(default) 0 = LANES REVERSED

R0623.1:

R0621.2:

6 OF 93

MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.6000

6 OF 121

0.24.0

051-00673

TP_CPU_RSVD_TP3

CPU_CFG<5>

CPU_CFG<18>
CPU_CFG<19>

CPU_VIDSOUT

PM_SYNC

CPU_PECI

TP_CPU_RSVD_TP8

TP_CPU_RSVD_TP7

TP_CPU_RSVD_TP5

TP_CPU_RSVD_TP12
TP_CPU_RSVD_TP13

CPU_PROCHOT_L

=PP1V0_S3_CPU

PM_DOWN

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

CPU_CFG<6>
CPU_CFG<7>

CPU_CFG<16>

CPU_VIDSCLK

XDP_BPM_L<3>

XDP_CPU_TMS

CPU_RESET_L

CPU_CFG<13>

DDR_VTT_CNTL

XDP_BPM_L<1>
XDP_BPM_L<2>

XDP_CPU_TCK

PROC_TRIGIN

XDP_CPU_TDI
XDP_CPU_TDO

CPU_CFG<1>

XDP_CPU_TRST_L

CPU_CFG<11>

CPU_CFG<0>

PROC_TRIGOUTPROC_TRIGOUT_R

XDP_BPM_L<0>

CPU_CFG<15>

CPU_CLK100M_PCI_P

CPU_CLK24M_SSC_P

CPU_CFG<3>
CPU_CFG<4>

CPU_CFG<2>

CPU_SKTOCC_L

TP_CPU_RSVD_TP10

=PP1V0_S3_CPU

CPU_VIDALERT_L

TP_CPU_RSVD_TP9

PM_EN_LDO_DDRVTT_S0_R

DDR_VTT_CNTL_3V3

PM_SLP_S3_L

CPU_PWRGD

CPU_VIDSOUT_R

DDR_VTT_CNTL

=PP3V3_S4_MEMRESET

TP_CPU_RSVD_TP14
TP_CPU_RSVD_TP15

TP_CPU_RSVD_TP6

TP_CPU_RSVD_TP4

CPU_BCLK100M_P

CPU_BCLK100M_N

CPU_PROCHOT_R_L

CPU_CATERR_L

CPU_VIDSCLK_R

CPU_CLK100M_PCI_N

CPU_CLK24M_SSC_N

PM_DOWN_R

TP_CPU_RSVD_TP1
TP_CPU_RSVD_TP2

PM_EN_LDO_DDRVTT_S0

CPU_THRMTRIP_L

CPU_VIDALERT_R_L

CPU_CFG<14>

CPU_CFG<9>
CPU_CFG<10>

CPU_CFG_RCOMP

CPU_CFG<17>

CPU_CFG<12>

CPU_CFG<8>

=PP1V0_S3_CPU

SYNC_MASTER=J78_MLB

CPU & CHIPSET: CPU Clock/Misc/JTAG/CFG

SYNC_DATE=06/30/2014

17

17

72

12

17 12

17

17

17

17 11

17

73 72 45

44 36 12

MF-LF

1/16W

402

R0633

0

5%

12

MF-LF

1/16W

402

1%

PLACE_NEAR=U0500.C39:38mm

1 2

499

R0603

MF-LF

1/16W

402

R0623

5%

2 1

PLACE_NEAR=U0500.E38:12.7mm

0

MF-LF

1/16W

402

2

0

1

R0625

5%

MF-LF

1/16W

402

1%

1

100

2

R0624

PLACE_NEAR=U0500.E40:12.7mm

MF-LF

1/16W

402

1%

PLACE_NEAR=R0603.2:1mm

2

1K

R0601

1

MF-LF

1/16W

402

51

5%

2

R0640

1

MF-LF

1/16W

402

PLACE_NEAR=R0604:5mm

NOSTUFF

R0606

1K

5%

1

2

64

MF-LF

1/16W

402

NOSTUFF

5%

12

R0632

0

MF-LF

1/16W

402

R0631

100K

1

2

5%

MF-LF

1/16W

402

R0630

2

NOSTUFF

100K

5%

1

Q0600

SSM6N37FEAP

4

5

3

SOT563

SSM6N37FEAP

Q0600

SOT563

1

2

6

17

17

17

91 17

17

91 17

91 17

91 17

17

17

17

17

17

17

17

17

17

17

17

17

MF-LF

1/16W

402

2

5%

1K

R0610

1

12

12

MF-LF

1/16W

402

33

R0605

2 1

5%

12

MF-LF

1/16W

402

PLACE_NEAR=U0500.D8:7MM

R0604

20

5%

12

17

17

61

61

61

MF-LF

1/16W

402

220

1

R0622

2

5%

MF-LF

1/16W

402

1%

PLACE_NEAR=U0500.E39:12.7mm

R0621

1

2

56.2

MF-LF

1/16W

402

R0642

2

1K

5%

PLACE_NEAR=U0500.F16:10mm

1

NOSTUFF

F35
F37

J13
J14

AW38

AW2

AV39

AV1

J8

J7

L12

J17

J11

AU9

C40

AU40

K8

J19

J15

D15

H12

H11

L10

B39

L8

AC37
AU10
AU39

AK27

K13

K12

AB37
AB38

AJ24

AC38

AJ25
AJ26
AJ27
AJ28

AK22

AK21

G34

G35

H34

H33

J33
J35
K32

L31

M32

L33

K11

K10

AJ29
AJ30

K34

LGA

544753

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

SKYLAKE_S

OMIT_TABLE

U0500

M11

D8

C39

OMIT_TABLE

F16

G16

U0500

SKYLAKE_S

LGA

544753

W4

D16
D17
G14
H14

D13

H15
F15

H18
G21
H20

E16

H17
G20
F20
F21
H19

G18
F18

J9

K9

W2
W1

G7

E8

B10

AB36

F11

G12
H13

F13

D1
B3

F12

E7

AB35

D11

E38
E40

AC36

W5

E39

E14
F14

F17

F19

H16

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

B9

F8

11

11

11

11

17 12

1

2

201

MF

R0690

1/20W

1%

49.9

PLACE_NEAR=U0500.M11:10mm

11

11

61 45 44

45

45 44 12

45

17 12

MF-LF

1/16W

402

PLACE_NEAR=U0500.F8:25mm

NOSTUFF

R0611

2

1

10K

5%

17

89 10 8 6

6

89 10 8 6

6

89

89 10 8 6

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

BI

OUT

IN

IN

OUT

IN

IN

IN

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

IN

OUT

SG

D

SG

D

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

OUT

IN

OUT

BI

OUT

BI

OUT

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

RESERVED

SYM 11 OF 11

RSVD

RSVD

RSVD

RSVD
RSVD

RSVD
RSVD

RSVD

RSVD

RSVD

RSVD

RSVD
RSVD

RSVD
RSVD

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_TP

RSVD

RSVD

RSVD_TP
RSVD_TP

RSVD

RSVD

RSVD
RSVD

RSVD

RSVD_TP

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_TP

RSVD_TP

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

THERMALPWR

2 OF 11

CLOCK

CFG[0]

BPM_2*

BPM_1*

BPM_0*

PROC_SELECT*

BPM_3*

PROC_PREQ*

PROC_TCK

PROC_TMS

PROC_TDI

PROC_TDO

DDR_VTT_CNTL

CFG[11]

CFG[10]

PCI_BCLKN
PCI_BCLKP

BCLKN

THERMTRIP*

PROC_TRST*

PECI

PM_SYNC

PM_DOWN

PROCPWRGD

SKTOCC*

CLK24N
CLK24P

PROC_TRIGOUT

BCLKP

CFG[2]
CFG[3]
CFG[4]
CFG[5]

CFG[7]
CFG[8]
CFG[9]

CFG[12]

CFG[17]
CFG[18]
CFG[19]

CFG[6]

CFG[14]
CFG[15]
CFG[16]

CFG[13]

CFG[1]

VIDSOUT

VIDSCK

VIDALERT*

CFG_RCOMP

PROC_TRIGIN

PROC_PRDY*

PROCHOT*

CATERR*

RESET*

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

OUT

IN

BI

www.laptoprepairsecrets.com

051-00673

0.24.0

7 OF 121

7 OF 937 OF 93

0.24.0

051-00673

7 OF 121

MEM_A_DQ<61>

MEM_B_DQ<40>

MEM_A_DQ<46>
MEM_A_DQ<47>

MEM_A_DQ<7>

MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>

MEM_A_DQ<55>

MEM_A_DQ<43>

MEM_B_DQ<55>

MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>

MEM_A_DQ<25>

MEM_A_CLK_N<1>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_B_BA<0>

MEM_A_CAS_L

MEM_B_CLK_N<1>

MEM_A_DQ<29>
MEM_A_DQ<30>

MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>

MEM_A_DQ<42>

MEM_A_DQ<44>

MEM_A_DQ<14>
MEM_A_DQ<15>

MEM_B_DQ<63>

MEM_B_DQ<54>

MEM_B_DQ<33>

MEM_A_DQS_P<3>

MEM_A_DQS_P<6>

MEM_A_DQS_N<1>
MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<0>

MEM_A_DQS_N<3>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

TP_DDR1_PAR

MEM_B_RAS_L

MEM_B_ODT<2>

MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_A<3>

MEM_B_DQ<41>

MEM_A_A<1>

MEM_A_RAS_L

MEM_B_CKE<3>

MEM_B_CS_L<0>

TP_DDR0_PAR

MEM_A_CKE<3>

MEM_A_CS_L<1>

MEM_A_CS_L<3>

MEM_A_ODT<2>

MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_DQS_P<2>

MEM_A_A<13>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_DQ<40>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_CLK_N<0>

MEM_A_CLK_N<3>

MEM_A_CKE<2>

MEM_A_CS_L<2>

MEM_A_DQS_P<0>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_DQS_P<1>

MEM_A_DQ<4>

MEM_A_DQ<0>

MEM_A_CLK_N<2>

MEM_B_DQ<36>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_CAS_L

MEM_B_DQS_P<0>

MEM_B_DQ<44>

MEM_B_DQ<11>
MEM_B_DQ<12>

CPU_DIMM_VREFCA

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<60>

MEM_A_DQ<58>

MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<48>

MEM_A_DQ<45>

MEM_A_DQ<41>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<8>

MEM_A_DQ<11>

MEM_A_DQ<16>

MEM_A_DQ<5>
MEM_A_DQ<6>

MEM_A_DQ<3>

MEM_A_DQ<12>

MEM_A_DQ<10>

MEM_A_DQ<19>
MEM_A_DQ<20>

MEM_A_DQ<1>
MEM_A_DQ<2>

MEM_B_DQ<8>

MEM_B_DQ<10>

MEM_B_DQ<13>
MEM_B_DQ<14>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<62>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<57>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<20>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<21>

MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>

MEM_B_DQ<17>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<2>

MEM_B_CKE<1>

MEM_B_CKE<2>

MEM_B_CLK_P<2>

MEM_B_CLK_P<3>

MEM_B_CLK_N<3>

MEM_B_CS_L<3>

MEM_B_CS_L<2>

MEM_B_CS_L<1>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ODT<3>

MEM_B_WE_L

MEM_B_A<0>
MEM_B_A<1>

MEM_B_A<7>
MEM_B_A<8>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<14>
MEM_B_A<15>

MEM_B_DQS_P<1>

MEM_B_DQS_P<6>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>

MEM_B_DQS_N<3>

MEM_B_DQS_N<5>

MEM_A_DQ<53>

MEM_A_DQ<59>

CPU_DIMMB_VREFDQCPU_DIMMA_VREFDQ

MEM_B_DQ<0>

MEM_B_DQ<6>

MEM_B_DQ<15>
MEM_B_DQ<16>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQS_P<7>

MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<4>
MEM_A_A<5>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CLK_P<2>

MEM_A_CKE<1>

MEM_A_CLK_P<1>

MEM_A_CLK_P<3>

MEM_A_ODT<3>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<57>

MEM_A_DQS_P<4>
MEM_A_DQS_P<5>

MEM_A_A<2>

MEM_A_DQS_N<7>

MEM_B_DQ<56>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>

MEM_B_DQS_N<2>

SYNC_DATE=06/30/2014SYNC_MASTER=J78_MLB

CPU & CHIPSET: DDR3L Interfaces

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

23

23

23

24 23

24 23

23

23

23

23

23

23

23

22 21

22 21

22 21

22 21

22 21

22 21

21

21

21

21

21

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

22 21

21

21

21

21

21

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

544753

SKYLAKE_S

OMIT_TABLE

LGA

U0500

AY25

AL18
AM18
AW28

AP16

AY29

AV29

AW29

AU29

AM21

AP21

AN21

AP20

AM20

AP22

AN20

AP19

AP17
AN15
AN17
AM15

AD34
AD35

AG35

AH35
AE35
AE34

AG34

AH34
AK35

AL35

AK32

AL32

AK34

AL34

AK31

AL31
AP35
AN35
AN32
AP32
AN34
AP34
AN31
AP31

AL29

AM29

AP29
AR29

AM28

AL28
AR28
AP28
AR12
AP12

AM13

AL13
AR13
AP13

AM12

AL12
AP10
AR10

AR7
AP7
AR9
AP9
AR6
AP6

AM10

AL10

AM7

AL7

AM9

AL9

AM6

AL6
AJ6
AJ7

AE6

AF7
AH7
AH6
AE7

AF6

AF34
AK33
AN33
AN29
AN13
AR8
AM8
AG6
AN26

AF35
AL33
AP33
AN28
AN12
AP8
AL8
AG7
AN25

AR25

AR26
AM26
AM25

AP26

AP25

AL25
AL26

AL19
AL22
AM22
AM23
AP23
AL23
AW26
AY26
AU26
AW27
AP18
AU27
AV27
AR15
AY28
AU28

AM16
AL16
AP15
AL15

AL20

AN18

AC39

AL17

AU37

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

OMIT_TABLE

LGA

544753

SKYLAKE_S

U0500

AT23

AY13
AV15
AW23

AY11

AY24

AW24

AV24

AV25

AV18

AY17

AV16

AU16

AW18

AW17

AW16

AT16

AW12
AU11
AV13
AV10

AE38
AE37
AG38
AG37
AE39
AE40
AG39
AG40

AJ38
AJ37
AL38
AL37
AJ40
AJ39
AL39

AL40
AN38
AN40
AR38
AR37
AN39
AN37
AR39
AR40

AW37

AU38
AV35

AW35

AV37

AT35

AU35

AY8

AW8

AV6
AU6
AU8
AV8

AW6

AY6
AY4
AV4
AT1
AT2
AV3

AW4

AT4
AT3
AP2

AM4

AP3

AM3

AP4

AM2

AP1

AM1

AK3
AH1
AK4
AH2
AH4
AK2
AH3
AK1

AF39
AK39
AP39
AU36
AW7
AU3
AN3
AJ3
AU32

AF38
AK38
AP38
AV36
AV7
AU2
AN2
AJ2
AV32

AU33

AT33

AW33

AV31
AU31
AV33

AW31

AY31

AW15
AU18
AU17
AV19
AT19
AU20
AV20
AU21
AT20
AT22
AY14
AU22
AV22
AV12
AV23
AU24

AW11
AU14
AU12
AY10

AY15

AW13

AC40

AV14

AB40

24

24

22

22

24

24

22

22

24

24

24

24

24

24

22

22

22

22

22

22

20

20 20

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

NCNC

NC

MEMORY CHANNEL DDR1

SYM 4 OF 11

DDR1_DQ[18]/DDR0_DQ[50]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_VREF_DQ

DDR1_ECC[7]

DDR1_ECC[3]

DDR1_ECC[2]

DDR1_ECC[1]

DDR1_ECC[0]

DDR1_DQ[62]

DDR1_DQ[61]

DDR1_ECC[4]
DDR1_ECC[5]
DDR1_ECC[6]

DDR1_DQ[63]

DDR1_DQ[47]/DDR1_DQ[31]

DDR1_DQ[46]/DDR1_DQ[30]

DDR1_DQ[45]/DDR1_DQ[29]

DDR1_DQ[44]/DDR1_DQ[28]

DDR1_DQ[43]/DDR1_DQ[27]

DDR1_DQ[42]/DDR1_DQ[26]

DDR1_DQ[41]/DDR1_DQ[25]

DDR1_DQ[57]

DDR1_DQ[56]

DDR1_DQ[55]

DDR1_DQ[54]

DDR1_DQ[53]

DDR1_DQ[52]

DDR1_DQ[51]

DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]

DDR1_DQ[50]

DDR1_DQ[49]

DDR1_DQ[48]

DDR1_DQ[40]/DDR1_DQ[24]

DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]

DDR1_DQ[39]/DDR1_DQ[23]

DDR1_DQ[38]/DDR1_DQ[22]

DDR1_DQ[37]/DDR1_DQ[21]

DDR1_DQ[36]/DDR1_DQ[20]

DDR1_DQ[35]/DDR1_DQ[19]

DDR1_DQ[34]/DDR1_DQ[18]

DDR1_DQ[33]/DDR1_DQ[17]

DDR1_DQ[28]/DDR0_DQ[60]

DDR1_DQ[26]/DDR0_DQ[58]

DDR1_DQ[23]/DDR0_DQ[55]

DDR1_DQ[22]/DDR0_DQ[54]

DDR1_DQ[20]/DDR0_DQ[52]

DDR1_DQ[25]/DDR0_DQ[57]

DDR1_DQ[24]/DDR0_DQ[56]

DDR1_DQ[21]/DDR0_DQ[53]

DDR1_DQ[9]/DDR0_DQ[25]

DDR1_DQ[8]/DDR0_DQ[24]

DDR1_DQ[7]/DDR0_DQ[23]

DDR1_DQ[6]/DDR0_DQ[22]

DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_DQ[2]/DDR0_DQ[18]
DDR1_DQ[3]/DDR0_DQ[19]
DDR1_DQ[4]/DDR0_DQ[20]

DDR1_DQ[19]/DDR0_DQ[51]

DDR1_ALERT*

DDR1_CKN[0]

DDR1_CKE[0]

DDR1_CKP[0]

DDR1_CKP[1]

DDR1_CKN[1]

DDR1_CKN[2]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKP[2]

DDR1_CKN[3]

DDR1_CS_3*

DDR1_CS_2*

DDR1_ODT[0]
DDR1_ODT[1]

DDR1_ODT[3]

DDR1_ODT[2]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_PAR

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[3]
DDR1_MA[4]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT*

DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSP[6]

DDR1_DQSP[8]

DDR1_DQSP[7]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSN[6]
DDR1_DQSN[7]
DDR1_DQSN[8]

DDR1_DQ[27]/DDR0_DQ[59]

DDR1_CS_1*

DDR1_RAS*/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE*/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS*/DDR1_CAB[1]/DDR1_MA[15]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_CS_0*

DDR1_CKP[3]
DDR1_CKE[3]

DDR1_DQ[17]/DDR0_DQ[49]

DDR1_DQ[16]/DDR0_DQ[48]

DDR1_DQ[15]/DDR0_DQ[31]

DDR1_DQ[14]/DDR0_DQ[30]

DDR1_DQ[13]/DDR0_DQ[29]

DDR1_DQ[12]/DDR0_DQ[28]

DDR1_DQ[11]/DDR0_DQ[27]

DDR1_DQ[10]/DDR0_DQ[26]

DDR1_DQ[5]/DDR0_DQ[21]

SYM 3 OF 11

MEMORY CHANNEL DDR0

DDR0_ALERT*

DDR0_ODT[2]
DDR0_ODT[3]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSN[8]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_CAS*/DDR0_CAB[1]/DDR0_MA[15]

DDR0_RAS*/DDR0_CAB[3]/DDR0_MA[16]

DDR0_DQ[46]/DDR1_DQ[14]

DDR0_CKE[3]

DDR0_CS_0*

DDR0_WE*/DDR0_CAB[2]/DDR0_MA[14]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQ[2]

DDR0_DQ[1]

DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

DDR0_DQ[61]/DDR1_DQ[45]

DDR_VREF_CA

DDR0_ECC[7]

DDR0_ECC[2]

DDR0_ECC[5]
DDR0_ECC[6]

DDR0_ECC[4]

DDR0_ECC[3]

DDR0_ECC[1]

DDR0_ECC[0]

DDR0_DQ[45]/DDR1_DQ[13]

DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]

DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]

DDR0_DQ[44]/DDR1_DQ[12]

DDR0_DQ[43]/DDR1_DQ[11]

DDR0_DQ[42]/DDR1_DQ[10]

DDR0_DQ[41]/DDR1_DQ[9]

DDR0_DQ[40]/DDR1_DQ[8]

DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]

DDR0_DQ[26]/DDR0_DQ[42]

DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]

DDR0_DQ[22]/DDR0_DQ[38]

DDR0_DQ[21]/DDR0_DQ[37]

DDR0_DQ[20]/DDR0_DQ[36]

DDR0_DQ[19]/DDR0_DQ[35]

DDR0_DQ[10]

DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]

DDR0_DQ[0]

DDR0_DQ[3]

DDR0_DQ[9]

DDR0_DQ[7]

DDR0_DQ[6]

DDR0_DQ[5]

DDR0_DQ[4]

DDR0_DQ[18]/DDR0_DQ[34]

DDR0_DQ[17]/DDR0_DQ[33]

DDR0_DQ[16]/DDR0_DQ[32]

DDR0_DQ[11]

DDR0_DQ[8]

DDR0_DQ[58]/DDR1_DQ[42]

DDR0_DQ[57]/DDR1_DQ[41]

DDR0_DQ[56]/DDR1_DQ[40]

DDR0_DQ[55]/DDR1_DQ[39]

DDR0_DQ[54]/DDR1_DQ[38]

DDR0_DQ[53]/DDR1_DQ[37]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[8]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT*

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

DDR0_MA[3]
DDR0_MA[4]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_PAR

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_ODT[0]
DDR0_ODT[1]

DDR0_CS_1*
DDR0_CS_2*
DDR0_CS_3*

DDR0_CKN[3]

DDR0_CKP[3]

DDR0_CKP[2]
DDR0_CKE[2]

DDR0_CKE[1]

DDR0_CKN[2]

DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CKE[0]

DDR0_CKP[0]

DDR0_CKN[0]

DDR0_VREF_DQ

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUTOUT

www.laptoprepairsecrets.com

8 OF 93

0.24.0

8 OF 121

051-00673

=PPVCCSA_S0_CPU

=PPVCCIO_S0_CPU

PM_VCCST_PWRGD

=PPVCC_S0_CPU

VCCSA_SENSE

PM_VCCST_PWRGD_CPU

=PPVCC_S0_CPU

=PPVDDQ_S3_CPU

=PP1V0_S3_CPU

VCCIO_SENSE

=PPVCCSA_S0_CPU

VSS_SAIO_SENSE

=PP1V0_S3_CPU

VSS_SENSE

VCCGT_SENSE

=PPVCCIO_S0_CPU

VCC_SENSE

=PPVCCGT_S0_CPU

=PPVCC_S0_CPU

=PPVDDQ_S3_CPU

=PPVCCGT_S0_CPU

VSSGT_SENSE

SYNC_DATE=06/30/2014SYNC_MASTER=J78_MLB

CPU & CHIPSET: CPU Power

1%

1

2

402

1/16W
MF-LF

2.8K

R0808

MF-LF

1/16W

1%

402

2

1

6.04K

R0807

5%

201

MF

100

2

1

1/20W

R0806

MF
201

2

1

100

R0805

1/20W

5%

5%

100

1

2

201

MF

R0804

1/20W

100

MF

5%

1

2

R0803

1/20W

201

MF

1

2

201

1/20W

5%

100

R0802

1/20W
MF
201

2

1

5%

100

R0801

MF

1/20W

2

1

201

5%

100

R0800

61

61

73 17

61

65 61

61

61

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

V33
V34

AE4

AF4

Y8

Y7

Y36

W34

W36
W37

LGA

OMIT_TABLE

SKYLAKE_S

544753

U0500

AA34
AA35
AA36
AA37
AA38
AB33
AB34
G36
G37
G38
G39
G40
H36
H38
H40
J36
J37
J38
J39
J40
K36
K38
K40
L34
L35
L36
L37
L38
L39
L40
M33
M34
M36
M38
M40
N34
N35
N36

N39
N40
P33
P34
P36
P38
P40
R34
R35
R36
R37
R38
R39
R40

F39

T33
T34
T36
T38
T40
U34
U35
U36
U37

U39
U40

V38
V40

W38

Y38

AJ23
AK11
AK14
AK24

M8

P8
T8

U8

W8

V4

AJ9

AA6
AA7
AB6
AB7
AB8
AC7
AC8

N7

P7

R7

AD5

T7

U7

V7

W7

Y6

V5
V6

F38

F36

V36

Y34

Y33

W35

U38

U2

N37
N38

SKYLAKE_S

H22

G29

A27

G26

AJ22

G24

B25

A26

H23

G23

544753

LGA

OMIT_TABLE

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

A25

A28
A29
A30

AJ12

AJ14

AJ17
AJ18
AJ19
AJ20
AJ21

B27
B29
B31
B32
B33
B34

B35
B36
B37
C25
C26
C27
C28
C29
C30
C32
C34
C36
D25
D27
D29
D31
D32
D33
D34
D35
D36
E24
E25
E26
E27

E30
E32
E34
E36
F23
F24
F25
F27
F29
F31
F32
F33

H25

J23

J25
J26
J27

J29
J30
J31
K16
K18
K20
K21
K23
K25
K27
K29M24

M26

M28

M30

C38

AT18

AT21
AU13
AU15
AU19
AU23
AV11
AV17

AW10
AW14

AW25

AY12
AY16
AY18
AY23

D38

AJ15

AJ13

F34

AJ11

J22

L25

L26

L27

L28

L29

L30

M13

M14

L22
L23
L24

L21

L20

L19

L18

L17

L16M16

M18

M20

M22

L15

L14

K31

E29

E28

J21

G25

H27

H32

AJ16

G32

J28

G30

AV21

H31

H29

G27
G28

J24

89 10 8

89 17 10 8 5

89 10 8

89 10 8

89

10 8

89 10 8 6

89 10 8

89

10

8 6

89 17 10 8 5

89 10 8

89 10 8

89 10 8

89 10 8

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

NC

SYM 6 OF 11

POWER

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCGT

VCCGT

VCCST

VCCST_PWRGD

VCCST

VSSGTX_SENSE

VCCGT

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCSA

VCCPLL_OC

VCCPLL

VCCIO

VCCIO

VCCIO

VCCGT

VCCGT

VSSGT_SENSE

VCCGT_SENSE

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT
VCCGT

VCCGT

VCCGT
VCCGT
VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT

VCCGT

VCCGT
VCCGT

VCCGT
VCCGT
VCCGT

VCCGT

VCCGT

VCCGT

VCCGT
VCCGT

VCCGT

VCCIO

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCSA_SENSE

VCCIO_SENSE

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VSS_SAIO_SENSE

VCCGT

SYM 5 OF 11

VCC

VDDQ

VDDQ

VDDQ

VCC

VCC

VCC

VCC
VCC

VCCVDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VDDQ
VDDQ

VDDQ

VDDQ

VCC_SENSE
VSS_SENSE

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

www.laptoprepairsecrets.com

Vinafix

0.24.0

051-00673

9 OF 121

9 OF 93

SYNC_MASTER=J78_MLB SYNC_DATE=06/30/2014

CPU & CHIPSET: CPU Ground

LGA

OMIT_TABLE

SKYLAKE_S

544753

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

A7
A11
A13
A15
A17
A24

AA3
AA8

AA33

AB5

AB39

AC3

AC6
AC33
AC34
AC35

AD1

AD4

AD6

AD7

AD8
AD33
AD36
AD37
AD38
AD39
AD40

AE3

AE5

AE8
AE33
AE36

AF1

AF5

AF8
AF33
AF36
AF37
AF40

AG1
AG2
AG3
AG4
AG5

AG8
AG33
AG36

AH5

AH8
AH33
AH36
AH37
AH38
AH39
AH40

AJ1
AJ4
AJ5

AJ8
AJ31
AJ32
AJ33
AJ34

AJ35
AJ36
AK5
AK6
AK7
AK8
AK9
AK10
AK12
AK13
AK15
AK16
AK17
AK18
AK19
AK20
AK23
AK25
AK26
AK28
AK29
AK30
AK36
AK37
AK40
AL1
AL2
AL3
AL4
AL5
AL11
AL14
AL21
AL24
AL27
AL30
AL36
AM5
AM11
AM14
AM17
AM19
AM24
AM27
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AM38
AM39
AM40
AN1
AN4
AN5
AN6
AN7
AN8
AN9
AN10

AY3

H8

G8

C2

B38

D40

A4

Y35

Y5

Y37

P35

G19

F22

W33

W6

V8

U33

U6

T39

T35

T4

T1

R33

R8

R6

R3

P39

P37

P4

P1

N33

N8

N6

N3

M39

M37

M35

M29

M27

M25

M23

M21

M17

M15

M12

M10

M7

M4

M1

L32

L13

L11

L9

L6

L3

K39

K37

K35

K33

K30

K28

K26

K24

K22

K19

K17

K15

K14

K7

K4

K1

J34

J32

J20

J18

J16

J12

J10

J6

J3

H39

H37

H35

H30

H28

H26

H24

H21

H9

H7

H4

H1

G33

G31

G22

G17

G15

G13

G11

G6

G3

F40

F30

F28

F26

F10

F7

F4

F1

E37

E35

E33

E31

E23

E21

M19

T37

U3

V1

V35
V37
V39
W3

E17

E9

E19

E15

E13

E11

LGA

SKYLAKE_S

544753

OMIT_TABLE

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

AR1

AT12
AT13

D7

AU25

LGA

OMIT_TABLE

SKYLAKE_S

544753

SKYLAKE_S_LGA1151_LGA_SKYLAKE_S_544753

U0500

AN11
AN14
AN16
AN19
AN22
AN23
AN24
AN27
AN30
AN36

AP5
AP11
AP14
AP24
AP27
AP30
AP36
AP37
AP40

AR2

AR3

AR4

AR5
AR11
AR14
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR27
AR30
AR31
AR32
AR33
AR34
AR35
AR36

AT5
AT6
AT7
AT8

AT9
AT10
AT11

AT14
AT15
AT17
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31

AT32
AT34
AT36
AT37
AT38
AT39
AT40
AU1
AU4
AU5
AU7

AU30
AU34
AV2
AV5
AV9
AV26
AV28
AV30
AV34
AV38
AW3
AW5
AW9
AW30
AW32
AW34
AW36
AY5
AY7
AY9
AY27
AY30
B6
B24
B26
B28
B30
C5
C8
C10
C12
C14
C16
C18
C20
C22
C24
C31
C33
C35
C37
D4

D24
D26
D28
D30
D37
D39
E3
E6

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

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A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GROUND

SYM 7 OF 11

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS

VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS

GROUND

SYM 9 OF 11

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS_NCTF

VSS_NCTF

VSS_NCTF
VSS_NCTF

VSS
VSS
VSS

GROUND

SYM 8 OF 11

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS

www.laptoprepairsecrets.com

Intel Recommendation:4x 22UF 0603 (top side outside cavity) Intel Recommendation:2x 22UF 0603 near top side cavity

Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

Memory (CPU VCCDDR) DECOUPLING

Apple Implementation: VCCST/VCCPLL: 1X 22UF 0603/2X 1UF 0402

CPU VCCSA / VCCST+VCCPLL DECOUPLING

Apple Implementation:(following Intel recommendation w/ 0603)
Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

CPU VCORE DECOUPLING

Intel Recommendation:12x 22UF 0805 (top side cavity)

6x 22UF 0603 (top side cavity)

5x 22UF 0805 (top side outside cavity)

1x 22UF 0805 (top side cavity)

ADDED CRITICAL PROPERTY TO CPU CORE DECOUPLING

4x 47UF 0805 (top side outside cavity)

Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

Intel Recommendation:9x 47UF 0805 (top side cavity)

Apple Implementation: 30x 22uF 0603

Layout Note: These caps should be placed symmetrically on Top and Bottom sides.

Apple Implementation:26x 22UF 0603

DUE TO ACOUSTICS CONCERNS

BULK CAPS ON CPU VREG PAGE 71

CPU GT DECOUPLING

Intel Recommendation:5x 22UF 0603 (top side cavity)

CPU VCCIO DECOUPLING

Layout Note: These caps should be placed on top side cavity.

Apple Implementation:9x 22UF 0603 (J78 carry over)

10 OF 93

10 OF 121

0.24.0

051-00673

=PPVCCGT_S0_CPU

=PPVCCIO_S0_CPU

=PPVCCSA_S0_CPU

=PPVCC_S0_CPU

=PPVDDQ_S3_CPU

=PP1V0_S3_CPU

CPU & CHIPSET: CPU Decoupling

SYNC_MASTER=J78_MLB SYNC_DATE=06/30/2014

2

1

CASE-D2-SM

C10B6

CRITICAL

POLY

470UF-0.006OHM

20%
2V

1

2

2V

20%

470UF-0.006OHM

POLY

C1099

CASE-D2-SM

CRITICAL

0402

1

X6S

1.0UF

10%
25V

C10C8

22

1

C10C6

0402

X6S

25V

10%

1.0UF

2

1

0402

C10C7

10%

1.0UF

X6S

25V

0402

2

1

X6S

25V

10%

1.0UF

C10C4

20%
4V
X6S

CRITICAL

C10B0

0603-1

1

2

22UF

4V

20%

X6S

CRITICAL

22UF

0603-1

1

2

C10B1

CRITICAL

X6S

20%
4V

C10B2

22UF

0603-1

1

2

X6S

CRITICAL

C10B3

4V

20%

22UF

0603-1

1

2

X6S

22UF

20%
4V

CRITICAL

C10B4

0603-1

1

2

X6S

4V

CRITICAL

22UF

20%

C10B5

0603-1

1

2

CRITICAL

C1040

22UF

20%

X6S

4V

0603-1

1

2

NOSTUFF

X6S

4V

20%

22UF

CRITICAL

C1041

NOSTUFF

0603-1

1

2

NOSTUFF

20%

X6S

CRITICAL

4V

22UF

0603-1

1

2

C1042

20%
4V
X6S

CRITICAL

C1050

22UF

0603-1

1

2

C1051

20%

X6S

CRITICAL

22UF

4V

0603-1

1

2

CRITICAL

22UF

20%
4V

C1052

X6S
0603-1

1

2

CRITICAL

20%
4V
X6S

22UF

0603-1

1

2

C1053

CRITICAL

C1054

22UF

X6S

4V

20%

0603-1

1

2

X6S

22UF

20%
4V

CRITICAL

C1055

0603-1

1

2

C1056

CRITICAL

4V
X6S

20%

22UF

0603-1

1

2

20%

22UF

CRITICAL

C1057

X6S

4V

0603-1

1

2

4V

CRITICAL

X6S

20%

C1058

22UF

0603-1

1

2

C10C9

22UF

0603-1

1

2

X6S

4V

20%

0603-1

C1070

2

1

CRITICAL

X6S

20%
4V

22UF

2

1

C1071

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1072

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1080

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1081

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1082

X6S

20%
4V

CRITICAL

0603-1

22UF

2

1

C1060

4V

20%

X6S

CRITICAL

22UF

0603-1

X6S

CRITICAL

2

1

C1061

4V

20%

22UF

0603-1

2

1

C1062

20%

22UF

X6S

CRITICAL

4V

0603-1

2

1

C1083

4V

CRITICAL

X6S

20%

22UF

0603-1

2

1

C1084

X6S

4V

20%

22UF

CRITICAL

0603-1

2

1

C1085

20%

X6S

CRITICAL

22UF

4V

0603-1

2

1

C1086

22UF

4V

CRITICAL

20%

0603-1

X6S

2

1

C1087

CRITICAL

X6S

22UF

20%
4V

0603-1

2

1

C1088

CRITICAL

X6S

22UF

20%
4V

0603-1

2

1

C1089

0603-1

CRITICAL

X6S

22UF

20%
4V

20%

2

1

C1073

4V

22UF

X6S

CRITICAL

0603-1

2

1

C1079

X6S
0603-1

20%

CRITICAL

4V

22UF

2

1

C1078

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1077

4V

20%

X6S
0603-1

22UF

CRITICAL

2

1

C1076

20%

22UF

X6S
0603-1

4V

CRITICAL

2

1

C1075

20%

22UF

X6S

CRITICAL

0603-1

4V

2

1

C1074

4V

20%

22UF

X6S
0603-1

CRITICAL

2

1

C1069

CRITICAL

22UF

20%
4V

0603-1

X6S

2

1

C1068

CRITICAL

22UF

20%
4V
X6S
0603-1

2

1

C1067

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1066

0603-1

CRITICAL

X6S

22UF

20%
4V

2

1

C1065

4V

20%

22UF

X6S

CRITICAL

0603-1

2

1

C1064

X6S

4V

20%

22UF

CRITICAL

0603-1

C1063

2

1

22UF

0603-1

X6S

20%
4V

CRITICAL

C10C0

22UF

2

1

4V

20%

X6S
0603-1

CRITICAL

C10C1

X6S
0603-1

22UF

CRITICAL

2

1

4V

20%

CRITICAL

4V

1

2

0603-1

C10C3

22UF

20%

X6S

0603-1

20%

C10C2

CRITICAL

X6S

2

1

4V

22UF

0603-1

2

1

C1025

4V

20%

22UF

X6S

CRITICAL

4V

20%

X6S
0603-1

C1024

1

2

CRITICAL

22UF

CRITICAL

4V

20%

22UF

X6S
0603-1

C1023

1

2

22UF

4V

20%

X6S
0603-1

CRITICAL

C1022

1

2

2

1

C1021

4V

20%

X6S
0603-1

CRITICAL

22UF

2

1

C1020

0603-1

CRITICAL

20%
4V
X6S

22UF

X6S

4V

20%

22UF

CRITICAL

0603-1

C1019

1

2

X6S

4V

20%

22UF

CRITICAL

0603-1

C1018

1

2

X6S

4V

0603-1

20%

22UF

CRITICAL

C1017

1

2

CRITICAL

4V

20%

22UF

X6S
0603-1

C1016

1

2

CRITICAL

4V

20%

22UF

0603-1

X6S

C1015

1

2

0603-1

CRITICAL

X6S

22UF

4V

20%

C1014

1

2

4V

20%

22UF

X6S

CRITICAL

C1013

1

2

0603-1

22UF

0603-1

CRITICAL

X6S

20%
4V

C1012

1

2

CRITICAL

X6S

22UF

4V

20%

0603-1

C1011

1

2

CRITICAL

C1000

0603-1

2

1

22UF

20%
4V
X6S

2

1

C1001

X6S

22UF

20%
4V

CRITICAL

0603-1

C1002

2

1

20%
4V

22UF

X6S
0603-1

CRITICAL

22UF

CRITICAL

C1003

20%
4V
X6S
0603-1

2

1

2

1

C1004

22UF

4V

20%

X6S

CRITICAL

0603-1

2

1

C1005

4V

20%

22UF

X6S
0603-1

CRITICAL

2

1

C1006

4V

22UF

X6S

CRITICAL

0603-1

20%

2

1

C1007

20%

22UF

0603-1

4V
X6S

CRITICAL

2

1

C1008

4V

20%

22UF

CRITICAL

0603-1

X6S

2

1

C1009

X6S

22UF

20%
4V

CRITICAL

0603-1

2

1

C1010

0603-1

CRITICAL

X6S

4V

22UF

20%

C10C5

22UF

1

20%

0603-1

X6S

4V

2

89 8

89 17 8 5

89 8

89 8

89 8

89 8 6

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

clkout for server only

24MHz SE output

direct 100MHz clock dif core ref clock from PCH to processor

direct 24MHz diff crystal ref clock from PCH to processor

11 OF 93

0.24.0

051-00673

11 OF 121

PEG_CLKREQ_L

AP_CLKREQ_PCH_L

SSD_CLKREQ_PCH_L

PEG_CLKREQ_L

PCH_JTAGX

=PP1V0_S5_PCH_VCC

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

PCIE_CLK100M_TBT_P

ITPXDP_CLK100M_P

TP_PCH_1

PCIE_CLK100M_AP_P

PEG_CLKREQ_L

PCIE_CLK100M_AP_N

TBT_PWR_EN_PCH

PCH_XTAL24_IN
PCH_XTAL24_OUT

PEG_CLK100M_P

PEG_CLK100M_N

PCH_DIFFCLK_BIASREF

ITPXDP_CLK100M_N

CPU_BCLK100M_N

CPU_BCLK100M_P

CPU_CLK24M_SSC_N

CPU_CLK24M_SSC_P

CPU_CLK100M_PCI_N

CPU_CLK100M_PCI_P

TBT_PWR_REQ_L

TBT_CLKREQ_L

SSD_CLKREQ_PCH_L

PCH_JTAGX

XDP_PCH_TMS

PCH_XTAL24_IN_R

PCH_XTAL24_OUT_R

PCH_ITP_PMODE

XDP_PCH_TCK

TP_PCH_2

HDA_SDIN0

HDA_RST_R_L

TP_HDA_SDIN1

HDA_SDOUT_R

HDA_BIT_CLK_R

HDA_SYNC

HDA_SYNC_R

HDA_RST_L

HDA_SDOUT

HDA_BIT_CLK

LPC_CLK24M_SMC

AP_CLKREQ_PCH_L

AP_CLKREQ_L

XDP_CPU_TCK

SSD_CLKREQ_L

PCH_JTAGX

SSD_CLKREQ_PCH_L

XDP_PCH_TDI

ENET_CLKREQ_L

AP_CLKREQ_PCH_L

SSD_CLKREQ_L

=PP1V0_S5_PCH_VCC

PCH_ITP_PMODE

XDP_PCH_TDO

PCIE_CLK100M_TBT_N

LPC_CLK24M_SMC_R

AP_CLKREQ_L

ENET_CLKREQ_L

TBT_CLKREQ_L

=PP3V3_S0_PCH_VCC

CPU & CHIPSET: Clocks/HDA/JTAG

SYNC_MASTER=J95_DEBORAH SYNC_DATE=10/20/2014

R1115

2

2.7K

1

0.1%

MF

1/16W

0402

PLACE_NEAR=U1100.E1:5MM

91 17

1

R1100

5% MF

10K

2

2011/20W

91 17

6

6

6

6

6

6

35 11

32 11

26 11

10K

R1101

1/20W2MF5% 201

1

33 11

17 11

17

10K

2011/20W5%

R1104

MF

1 2

17

17

17

2

201MF5%

R1105

1/20W

1

1K

MF

R1106

1/20W

201

5%

2

51

1

17 6

R1108

NOSTUFF

10K

1

1/20W 201

2

MF5%

35

35

32

10K

R1125

1

201

2

MF1/20W5%

19 14

27 14

R1121

402

21

MF-LF

0

5%

1/16W

1 2

402

0

1/16W
MF-LF

5%

R1116

32

R1114

100K

5% 201

21

MF1/20W

26

R1107

100K

5%

1 2

201MF1/20W

44

PLACE_NEAR=U1100.BC17:10MM

R1120

1

33

MF-LF

5%

1/16W

402

2

1

2

201

MF

5%

1M

1/20W

R1102

1

0201

2

25V
CER

10PF

5%

C1102

10PF

1

25V

5%

0201

2

C1101

CER

R1119

1

2

5%

0

1/20W
MF
0201

R1118

1

0

5%

2

0201

MF

1/20W

26

10K

R1113

1/20W 2015%

2

MF

1

1

24.000MHZ-20PPM-9.5PF-60OHM

1.60X1.20MM

2 4

3

Y1101

91 11

74

BB24

BD32

A5

R11

BC17

R2

Y5

U3

R4

P2

N2

W11

R7

E6

G4

L5

P1

W7

U2

R3

P3

N3

R8

D8

E5 E1

BD33

BB33

BA33

BC33

BB31

BC32

AT33

BD25

AT24

AR17

AV19

L2

J2

J1

G1

F1

G2

H2

U1100

FCBGA

SKL-PCH-H

A6

TBD

R13

U7

U5

L7

N7
N8

D7

D3
F2

D5

OMIT_TABLE

AW24

BC24

AW33

CRITICAL

W10

BE25

AR31

L1

52

0201

1

0

5%

MF

1/20W

R1117

2

AB13

AR2

AP2

AR3

CRITICAL

SKL-PCH-H

AM1

AJ33
AM43
AN42
AL42
AJ42

BA9

BC8

BB7

BD9

AT2

C1

D1
N29
N31

P24
P27
P29

P31
R24
R27
U13

W13

AE17
AF17

AG14

AN29
AR22

BD8

AG15

AN2

OMIT_TABLE

AM2

BD1
BE2

AR19

AN17

AN3

AP1

AJ38

TBD

U1100

BE7

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AH44

AJ35

FCBGA

52

52

52

74

52

R1110

1

PLACE_NEAR=U1100.BD9:5MM

33

MF 2011/20W

5%

2

1

201

5%

MF1/20W

33

2

R1109

PLACE_NEAR=U1100.BA9:5MM

1

2011/20W5%MF

R1112

2

33

PLACE_NEAR=U1100.BD8:7MM

1

MF

33

2011/20W

2

5%

PLACE_NEAR=U1100.BB7:6MM

R1111

33

33

91 11

11

11

91 11

11

89 15 11

11

11

91

91

18

11

11

11

11

33 11

89 15 11

17 11

32 11

35 11

26 11

89 19 18 15 14 12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

NC

NC

NC

NC

OUT

OUT

IN

OUT

NC

NC

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

CLOCK SIGNALS

PCI EXPRESS

CLOCKS & CONTROL

SYM 2 OF 12

/ESPI_CLK

XTAL24_IN

XTAL24_OUT

CLKOUT_SRC_P2

CLKOUT_SRC_N3
CLKOUT_SRC_P3

CLKOUT_SRC_N4
CLKOUT_SRC_P4

CLKOUT_SRC_P1

CLKOUT_SRC_N1

CLKOUT_SRC_N0
CLKOUT_SRC_P0

CLKOUT_SRC_P15

CLKOUT_SRC_N15

CLKOUT_SRC_P14

CLKOUT_SRC_N14

CLKOUT_SRC_P13

CLKOUT_SRC_N13

CLKOUT_SRC_P12

CLKOUT_SRC_N12

CLKOUT_SRC_P11

CLKOUT_SRC_N11

CLKOUT_SRC_P10

CLKOUT_SRC_N10

CLKOUT_SRC_P9

CLKOUT_SRC_N9

CLKOUT_SRC_P8

CLKOUT_SRC_N8

CLKOUT_SRC_P7

CLKOUT_SRC_N7

CLKOUT_SRC_P6

CLKOUT_SRC_N6

CLKOUT_SRC_P5

CLKOUT_SRC_N2

XCLK_BIASREF

GPP_A16/CLKOUT_48

CLKOUT_ITPXDP_N

CLKOUT_CPUBCLK_N

CLKOUT_CPUBCLK_P

CLKOUT_CPUNSSC_N
CLKOUT_CPUNSSC_P

GPP_A10/CLKOUT_LPC1

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

GPP_B7/SRCCLKREQ2*

GPP_H9/SRCCLKREQ15*

GPP_H7/SRCCLKREQ13*

GPP_H6/SRCCLKREQ12*

GPP_H5/SRCCLKREQ11*

GPP_H0/SRCCLKREQ6*

GPP_B6/SRCCLKREQ1*

GPP_B5/SRCCLKREQ0*

GPP_H8/SRCCLKREQ14*

GPP_H4/SRCCLKREQ10*

GPP_H3/SRCCLKREQ9*

GPP_H2/SRCCLKREQ8*

GPP_H1/SRCCLKREQ7*

GPP_B9/SRCCLKREQ4*

GPP_B8/SRCCLKREQ3*

GPP_B10/SRCCLKREQ5*

CLKOUT_SRC_N5

GPP_A9/CLKOUT_LPC0

OUT

JTAG

AUDIO

RSVD & TP PINS

SYM 1 OF 12

HDA_BCLK

DISPA_BCLK

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

TP1
TP2

ITP_PMODE

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAGX

RSVD

RSVD

HDA_SYNC

HDA_SDI1

HDA_SDI0

HDA_SDO

DISPA_SDI

DISPA_SDO

GPP_D5/I2S0_SFRM

GPP_D7/I2S0_RXD

GPP_D6/I2S0_TXD

GPP_D8/I2S0_SCLK

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

HDA_RST*

RSVD

OUT

OUT

IN

OUT

OUT

NC

NC

NC

NC

NC

OUT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

OUT

www.laptoprepairsecrets.com

BATLOW only in mobile package

PlACE R1217 NEAR TRACE T-POINT

12 OF 121

0.24.0

051-00673

12 OF 93

PCH_STRP_BOOT_LPC

LPC_SERIRQ

PCIE_WAKE_L

PCH_RCIN_TERM

PROC_TRIGIN_R

PM_SYNC_R

XDP_PCH_OBSDATA_B2

PCH_TRST_L

PCH_PRDY_L

PCH_SUSACK_L

PM_RSMRST_PCH_L

PCH_BATLOW_L

TP_PCH_SLP_WLAN_L

PM_PCH_SYS_PWROK

PM_SYSRST_L

LPC_PWRDWN_L

PCH_PECI

XDP_PCH_OBSDATA_A2

PROC_TRIGOUT

PCH_PROCPWRGD

LPC_AD_R<1>

LPC_AD_R<0>

PLT_RESET_L

PCH_SRTCRST_L

PCH_MEM_RESET_L

CPU_PECI

CPU_PWRGD

DMI_S2N_N<1>

DMI_S2N_P<0>

=PP1V0_S3_VCCST

=PP3V3_S0_PCH_VCC

DMI_N2S_N<3>

=PPVDDQ_S3_MEMRESET

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

SPI_IO_R<2>

SPI_IO_R<3>

SPI_MOSI_R

SPI_MISO

SPI_CS0_R_L

TP_CLINK_DATA

PCH_STRP_NOREBOOT

PCH_STRP_BOOT_LPC

DMI_N2S_N<0>

DMI_S2N_N<2>

DMI_N2S_P<3>

DMI_N2S_N<2>

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_N2S_P<2>

DMI_S2N_P<3>

DMI_N2S_P<0>

DMI_S2N_P<1>

DMI_S2N_P<2>

PROC_TRIGIN

PM_SYNC

=PP3V3_G3_PCH_RTC

PCH_SRTCRST_L
PCH_INTRUDER_L

RTC_RESET_L

PCH_STRP_GPP_B23

PM_SLP_S4_L

PM_CLK32K_SUSCLK_R

LPC_CLKRUN_L

PM_THRMTRIP_PCH_R_L

XDP_CPU_TRST_L

PM_THRMTRIP_L

PM_DOWN

SMC_RUNTIME_SCI_L

LPC_AD_R<2>

PCH_RCIN_TERM

PM_SLP_SUS_L

PCH_PECI

PCH_VRALERT_L

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

LPC_SERIRQ

LPC_FRAME_R_L

LPC_AD_R<3>

PCH_VRALERT_L

SMC_WAKE_SCI_L

TP_PCH_SLP_LAN_L

PM_SLP_SUS_L

TP_PM_SLP_A_L

PM_SLP_S3_L

PM_SLP_S5_L

DMI_S2N_N<3>

CPU_RESET_L

PCH_PREQ_L

PCH_STRP_GPP_B23

SPI_CLK_R

TP_PCH_GPP_A12

=PP3V3_S5_PCH_VCC

DMI_S2N_N<0>

PM_PWRBTN_L

PM_PCH_PWROK

TP_CLINK_RESET_L

PCH_PME_L

PCIE_WAKE_L

PM_ACPRESENT

PCH_PME_L

RTC_RESET_L

PCH_INTRUDER_L

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PM_ACPRESENT

TP_PCH_GPP_A12

PCH_BATLOW_L

PM_PWRBTN_L

LPC_CLKRUN_L

PCH_STRP_NOREBOOT

PM_RSMRST_PCH_L

MEM_RESET_L

PCH_SUSWARN_L

TP_CLINK_CLK

SYNC_DATE=10/20/2014SYNC_MASTER=J95_DEBORAH

CPU & CHIPSET: PCH RTC/DMI/PM/CPU_Misc

73 17 12

44

5%

3.0K

2

MF

1

2011/20W

R1211

NOSTUFF

5%

MF33201

1/20W1 2

R1225

36 32 19 12

44 19

72 44 12

72 44 32 12

45

73 72 45 44 36 12 6

44 18 17

73 45 17

82 73 39 19

19

73 17 12

44 17 12

R1286

0201

MF

1/20W

5%

0

2

1

44 12

45

17 6

1/16W

2

402

1K

MF-LF

1

5%

R1218

PLACE_NEAR=R1219.2:3MM

6

17 6

45

44 6

1

MF 0201

1/20W

2

0

5%

R1226

MF

1/20W

NOSTUFF

5%

21

13

201

R1217

1/20W 201

1 2

1K

5%

R1210

MF

18

18

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AY5

C29

AJ3

BC23
BD24

AT27

OMIT_TABLE

CRITICAL

FCBGA

U1100

AF41

SKL-PCH-H

G27

AT4

A30

A28

B30

B29

B28

C27

K29

E26

G24

N27

L29

E24

L27

B27

AE44

AJ4

AH2

AL2

AK1

AT3

AK2

AM3

TBD

AL3

1

5%

1/16W

33

402

MF-LF

2

PLACE_NEAR=U1100.AL2:12.7MM

R1228

17

17 6

17

6

6

1

R1212

1/20W

2

5% MF 201

100K

46

46

46

46 17

5

MF

100K

201

1

1/20W

R1213

5%

2

5

5

5

5

5

5

5

5

5

5

1/20W

R1214

1

100K

5%

2

MF 201

5

5

5

5

5

402

2

X5R

10V

10%

1UF

1

C1201C1200

10%
10V

402

X5R

1UF

1

2

R1200

MF

1

201

2

5%
1/20W

1M

R1215

MF

2

100K

2011/20W5%

1

NOSTUFF

44 14

1/20W

1%

560

MF

1 2

201

PLACE_NEAR=U1100.AL3:12.7MM

R1219

201

R1230

2

5% MF

1

1/20W

10K

24 23 22 21

1K

1/16W
MF-LF

1

2

402

5%

R1261

1

16V

10%
X7R-CERM

0.1UF

0402

2

C1261

1 2

5%

MF

0201

0

1/20W

R1271

21

402

1/16W

5%

R1216

PLACE_NEAR=U1100.AM3:12.7MM

33

MF-LF

1K

1/20W

R1206

201

2

5% MF

1

44 14

1

10K

5% MF

2

1/20W

R1231

201

10K

2

5% 201MF

1

R1234

1/20W

100K

2

5%

1

201MF1/20W

R1290

10K

R1204

2011/20W2MF

1

NOSTUFF

5%

MF

100K

R1237

1

5% 201

2

1/20W

5%

1K

2

R1203

201

1

MF1/20W

1/20W

5%

201

MF

1

2

100K

R1220

5%

MF

2

201

1/20W

R1201

1

20K

20K

1/20W
MF
201

1

R1202

5%

2

BC26

AT17

BC10

BB15

BD19

AN15

BE16

BB17

BD13

CRITICAL

TBD

FCBGA

BC14

AT13

BA17

BC15

BB13

BB10

BA11

BD14

AW15

BD15

BA13

AW11

AY1

BB27

BD17

AW22

BC18

BC13

BD23

AV11

U1100

SKL-PCH-H

BE11

AV15

AV22
AT19
BD16

AT22

AW1

BB19

OMIT_TABLE

BD11

AR15

AV13

BD10

AW17

BC9

5%

8.2K

201

2

R1236

1/20W

1

MF

10K

1/20W MF

2

5%

1

201

R1235

MF

R1233

5% 201

1 2

10K

1/20W

MF

2

5% 2011/20W

1

10K

R1232

46

46 17

2 1

R1229

402

MF-LF

5%

1/16W

33

PLACE_NEAR=U1100.AJ4:5MM

R1224

33

201MF1/20W

5%

1 2

44

44

44

44

2

201

5%

MF1/20W

1

33

R1221

R1222

1/20W

5%

201

1 2

33

MF

33

201

MF

5%

1 2

R1223

1/20W

6

17

17

AT31

AW31

BD31

BB29

BE30

BC29

BC31

AT29

AR29

AV29

BC27

BD28

BD27

AW27

AR24

FCBGA

CRITICAL

TBD

OMIT_TABLE

BD30

AV2

AV3

AW2

U1100

SKL-PCH-H

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

12

44 12

12

12

12

12

89 61

89 19 18 15 14 11

89

91

12

12

89 15

12

12

45 18 12

12

12

12

12

12

12

72 44 32 12

72 44 12

73 72 45 44 36 12 6

12

91

12

91

12

12

89 19 18 15 14 13

91

12

36 32 19 12

12

12

45 18 12

12

12

12

12

44 17 12

12

12

91

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

BI

IN

OUT

OUT

OUT

BI

IN

OUT

DMI

CPU/MISC

SYM 5 OF 12

PROCPWRGD

PM_DOWN

PM_SYNC

DMI_TXN0

DMI_TXP1

GPP_B3/CPU_GP2

THERMTRIP*

DMI_TXN1

PRDY*

PREQ*

GPP_B23/SML1ALERT*/PCHHOT*

PLTRST_PROC*

DMI_RXP3

DMI_RXP2

DMI_RXN3

DMI_RXN2

DMI_RXP1

DMI_RXN1

DMI_RXP0

DMI_RXN0

DMI_TXP3

DMI_TXN3

DMI_TXP2

DMI_TXN2

DMI_TXP0

PCH_TRIGIN

PCH_TRIGOUT

GPP_E3/CPU_GP0

GPP_B4/CPU_GP3

PECI

GPP_E7/CPU_GP1

CPU_TRST*

OUT

OUT

IN

IN

IN

NC

NC

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

NC

OUT

IN

/SX_EXIT_HOLDOFF*

RTC

ESPI/LPC

/SUSPWRDNACK

SYM 4 OF 12

SYSTEM POWER MANAGEMENT

GPD7/RSVD

SYS_RESET*

GPP_A15/SUSACK*

DSW_PWROK

GPP_A3/LAD2/ESPI_IO2

GPP_A2/LAD1/ESPI_IO1

GPP_A1/LAD0/ESPI_IO0

GPD2/LAN_WAKE*

GPP_B2/VRALERT*

GPP_A0/RCIN*/ESPI_ALERT1*

GPD8/SUSCLK

WAKE*

GPP_A14/SUS_STAT*/ESPI_RESET*

GPP_A8/CLKRUN*

GPD0/BATLOW*

GPP_B12/SLP_S0*

GPP_A12/BMBUSY*/ISH_GP6

GPD9/SLP_WLAN*

GPP_A11/PME*

GPP_B13/PLTRST*

SYS_PWROK

PCH_PWROK

GPD10/SLP_S5*

GPD5/SLP_S4*

GPD4/SLP_S3*

RTCX2

RTCX1

RSMRST*

INTRUDER*

RTCRST*

SRTCRST*

GPP_A5/LFRAME*/ESPI_CS0*

SLP_LAN*

SLP_SUS*

GPD6/SLP_A*

GPD11/LANPHYPC

GPP_A4/LAD3/ESPI_IO3

GPP_A7/PIRQA*/ESPI_ALERT0*

GPP_A6/SERIRQ/ESPI_CS1*

GPD1/ACPRESENT

GPD3/PWRBTN*

GPP_A13/SUSWARN*

DRAM_RESET*

BI

BI

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

BI

BI

BI

BI

OUT

BI

BI

GSPIC-LINK

SPI

SYM 3 OF 12

GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS*

GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

SPI0_CS1*

SPI0_CS2*

SPI0_MOSI

SPI0_MISO

SPI0_IO2

SPI0_IO3

CL_CLK

CL_DATA

GPP_B17/GSPI0_MISO

CL_RST*

SPI0_CS0*

SPI0_CLK

GPP_B15/GSPI0_CS*

GPP_B16/GSPI0_CLK

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USB2_ID HAS WEAK PULLUP

051-00673

0.24.0

13 OF 93

13 OF 121

PCIE_TBT_D2R_P<2>

TBT_POC_RESET_L

PCIE_RCOMPN

PCH_SATAXPCIE6_SATAGP6

USB_EXTC_OC_L
USB_EXTB_OC_L
USB_EXTD_OC_L

PCH_CAM_EXT_BOOT_R_L

SATA_HDD_D2R_N
SATA_HDD_D2R_P

SATA_HDD_R2D_C_P

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_N<0>
PCIE_SSD_R2D_P<0>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_N<1>

PCH_DEVSLP0

PCH_DEVSLP2

PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_D2R_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_D2R_N<3>
PCIE_TBT_D2R_P<3>

PCIE_AP_D2R_N
PCIE_AP_D2R_P

PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

PCH_SATAXPCIE0_SATAGP0

PCH_SATAXPCIE2_SATAGP2

PCH_SATAXPCIE1_SATAGP1

PCH_SATAXPCIE4_SATAGP4

PCH_SATAXPCIE3_SATAGP3

PCH_SATAXPCIE7_SATAGP7

PCH_SATAXPCIE5_SATAGP5

WOL_EN

PCH_CAM_EXT_BOOT_L

PCIE_RCOMPP

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_N<2>
PCIE_SSD_R2D_P<2>

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_N<3>
PCIE_SSD_R2D_P<3>

PCH_SATALED_L

SSD_PWR_EN

HDD_PWR_EN

PCH_SSD_RESET_L

SSD_BFH_L

SSD_SR_EN_L

PCH_DEVSLP1

PCH_SATALED_L

SSD_SR_EN_L

PCIE_SSD_R2D_P<1>

PCIE_TBT_R2D_C_N<2>

SDCONN_STATE_CHANGE

=PP3V3_S4_PCH_VCC

=PP3V3_S5_PCH_VCC

PCH_CAM_RESET

PCH_CAM_RESET_R

SATA_HDD_R2D_C_N

PCIE_TBT_R2D_C_N<3>
PCIE_TBT_R2D_C_P<3>

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCH_USB_RBIAS

PCH_USB_VBUSSENSE

PCH_USB2_ID

USB_EXTD_OC_L

USB_EXTC_OC_L

USB_EXTB_OC_L

USB3_EXTC_TX_P

USB3_EXTC_RX_F_P

USB3_EXTC_TX_N

USB3_EXTC_RX_F_N

USB3_EXTB_TX_P

USB3_EXTB_TX_N

USB3_EXTB_RX_F_N

USB3_EXTA_TX_N
USB3_EXTA_TX_P

USB3_EXTA_RX_F_P

USB3_EXTD_TX_P

USB3_EXTD_TX_N

USB3_EXTD_RX_F_P

USB3_EXTD_RX_F_N

USB_EXTA_N
USB_EXTA_P

USB3_EXTB_RX_F_P

USB_EXTA_OC_L

USB_EXTA_OC_L

USB3_EXTA_RX_F_N

USB_EXTC_P

USB_EXTB_P

USB_EXTB_N

USB_EXTC_N

USB_EXTD_N

USB_EXTD_P

USB_BT_N

USB_CAMERA_N
USB_CAMERA_P

USB_BT_P

CPU & CHIPSET: PCH PCI-E/USB

SYNC_MASTER=J95_DEBORAH SYNC_DATE=10/20/2014

5% MF

1 2

NOSTUFF

2011/20W

R1303

10K

26

33

33

33

33

33

33

33

33

32

32

32

32

NOSTUFF

1/20W5%

2

201

10K

MF

R1304

1

35

35

32

32

42 17 13

42 17 13

43 17 13

43 17 13

201

PLACE_NEAR=U1100.AG3:11.4MM

1%

MF

1

113

R1314

2

1/20W

R1315

2

1

1%

100

201

MF

1/20W

PLACE_NEAR=U1100.C17:11.4MM

AL7

AB3
AB2

V1

V2

AL8

AJ7

AE2

Y43

AG3

AG2

W43

G11

W44

C13
D13

OMIT_TABLE

B12

B8

B10

AG10

AG8

AF5

AA1

AJ8

C14

CRITICAL

U1100

AD42

H13

G13

B13

A14

E11

A9

A12

C8

B11

C11

A7

B7

AJ13

W3

AA2

AF3

AD7

W2

AF2

AC2

AE1

AD5

AD10

AD39

AD43

FCBGA

TBD

C15

B15

K13

B14

AC44

AD2

AD3

SKL-PCH-H

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

Y41

AJ11

K15

AC3

AG7

R1307

NOSTUFF

201

10K

MF5% 1/20W

2 1

43

43

43

43

5%

2

1/20W MF 201

1

10K

NOSTUFF

R1308

42

42

R1318

1K

5%

201

MF

1/20W

1

2

42

1/20W

10K

1 2

MF 201

R1317

5%

33 14

42

35

35

36 14

42

10K

R1310

1

MF 201

2

5% 1/20W

33 13

34 14

33 14

33 14

39

39

MF-LF

R1401

2

5%

1/16W

33

402

1

PLACE_NEAR=U1100.P44:10MM

R1402

MF-LF

1/16W

21

33

402 5%

PLACE_NEAR=U1100.U36:10MM

42

27

33

33

33

33

42

R1301

1K

1/16W

402

MF-LF

2

1

5%

42

33 17 13

17

17

17

17

17

17

17

17

42

17

17

17

B24

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AG35 AG43

AB39

AD31

AB33

AE45

B38

A41

H40

E45

E22

L22

E41

C38

F41

E42

A39

D43

D22

G19

OMIT_TABLE

FCBGA

CRITICAL

TBD

SKL-PCH-H

U1100

AG36

AG39

AG42

AD35

AD38

AB44

AB41
AB42

G15

A16
B16

G17

K17

B20

C20

E20

B21

K19

L19

C22

G22

B22
A23

K22

C23

B23

K24

L24

C24

G31
H31

C31

E29

C32
B32

L31

K31

C33

B33

G33
H33

B35
A35

G35
E35

C36
B36

D39
E37

B39

A40

K37
G37

G45
G44

L37
L39

H43
H44

N39
N38

K44
J45

H15

A21

B19

AC43

B18

C17

AA45

AB35

AA44

AD44

AB43
AB36

E17

F45

H42

B31

G29

L17

C19

33

33

33

33

33

33

42

33

33

43

26

26

26

26

26

26

26

43

26

26

26

26

26

26

26

26

43

43

43

42

42

43

43

38

38

43

201MF5%

21

10K

1/20W

R1316

43 17 13

42 17 13

43 17 13

14

33 17 13

33 13

37 14

89 14

89 19 18 15 14 12

14

42 17 13

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

NC

NC

NC

NC

NC

NC

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

OUT

BI

BI

IN

IN

IN

IN

USB2

USB3

SYM 7 OF 12

USB3_3_TXP

USB3_3_TXN

USB3_3_RXP

USB3_3_RXN

USB3_2_TXP

USB3_2_TXN

USB3_2_RXP

USB3_2_RXN

USB2_COMP

GPP_F18/USB2_OC7*

GPP_F17/USB2_OC6*

GPP_F16/USB2_OC5*

GPP_F15/USB2_OC4*

USB2N_2

USB2_VBUSSENSE

USB2_ID

GPP_E12/USB2_OC3*

GPP_E11/USB2_OC2*

GPP_E9/USB2_OC0*

GPP_E10/USB2_OC1*

USB2N_14
USB2P_14

USB2N_13
USB2P_13

USB2N_12
USB2P_12

USB2N_11
USB2P_11

USB2N_10
USB2P_10

USB2N_9

USB2P_9

USB2P_7

USB2N_7

USB2N_8

USB2P_1

USB2N_4

USB2P_3

USB2N_3

USB2P_5

USB2N_5

USB2P_4

USB2N_6

USB2P_6

USB2P_8

USB3_6_TXP

USB3_6_RXP

USB3_6_TXN

USB3_6_RXN

USB3_5_TXP

USB3_5_TXN

USB3_5_RXN
USB3_5_RXP

USB3_4_TXN
USB3_4_TXP

USB3_4_RXP

USB3_4_RXN

USB3_1_TXP

USB3_1_TXN

USB3_1_RXP

USB3_1_RXN

USB2P_2

USB2N_1

NC

NC

NC

NC

NC

NC

IN

IN

OUT

OUT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

BI

BI

IN

NC

OUT

NC

NC

NC

NC

NC

NC

NC

OUT

NC

NC

NC

NC

NC

NC

NC

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

NC

NC

NC

NC

OUT

OUT

IN

IN

NC

IN

IN

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SYM 8 OF 12

PCIE/SATA/USB3

PCIE10_TXP/SATA1A_TXP

PCIE10_TXN/SATA1A_TXN

PCIE10_RXP/SATA1A_RXP

PCIE9_TXP/SATA0A_TXP

PCIE9_TXN/SATA0A_TXN

PCIE14_TXP/SATA1B_TXP

PCIE15_RXN/SATA2_RXN

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP

PCIE10_RXN/SATA1A_RXN

PCIE13_RXN/SATA0B_RXN

PCIE13_TXN/SATA0B_TXN

PCIE13_RXP/SATA0B_RXP

PCIE13_TXP/SATA0B_TXP

PCIE14_RXN/SATA1B_RXN

PCIE14_RXP/SATA1B_RXP

PCIE14_TXN/SATA1B_TXN

PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_F5/DEVSLP3
GPP_F6/DEVSLP4

GPP_F8/DEVSLP6

GPP_F7/DEVSLP5

GPP_F9/DEVSLP7

GPP_E8/SATALED*

PCIE5_RXN
PCIE5_RXP

PCIE5_TXP

PCIE5_TXN

PCIE6_RXP

PCIE6_RXN

PCIE6_TXP

PCIE6_TXN

PCIE7_RXN
PCIE7_RXP

PCIE7_TXN
PCIE7_TXP

PCIE8_RXN

PCIE8_TXN

PCIE8_RXP

PCIE8_TXP

PCIE11_RXN
PCIE11_RXP

PCIE11_TXN
PCIE11_TXP

PCIE12_RXP

PCIE12_RXN

PCIE12_TXP

PCIE12_TXN

PCIE1_RXN/USB3_7_RXN
PCIE1_RXP/USB3_7_RXP

PCIE1_TXN/USB3_7_TXN
PCIE1_TXP/USB3_7_TXP

PCIE2_RXN/USB3_8_RXN
PCIE2_RXP/USB3_8_RXP

PCIE2_TXN/USB3_8_TXN
PCIE2_TXP/USB3_8_TXP

PCIE3_RXN/USB3_9_RXN
PCIE3_RXP/USB3_9_RXP

PCIE3_TXN/USB3_9_TXN
PCIE3_TXP/USB3_9_TXP

PCIE4_RXN/USB3_10_RXN

PCIE4_TXN/USB3_10_TXN

PCIE4_RXP/USB3_10_RXP

PCIE4_TXP/USB3_10_TXP

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E2/SATAXPCIE2/SATAGP2

GPP_E1/SATAXPCIE1/SATAGP1

GPP_F1/SATAXPCIE4/SATAGP4

GPP_F0/SATAXPCIE3/SATAGP3

GPP_F4/SATAXPCIE7/SATAGP7

GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6

GPP_F10/SCLOCK
GPP_F11/SLOAD

GPP_F13/SDATAOUT0

GPP_F12/SDATAOUT1

PCIE_RCOMPN

PCIE_RCOMPP

PCIE19_RXN
PCIE19_RXP

PCIE19_TXN
PCIE19_TXP

PCIE20_RXN
PCIE20_RXP

PCIE20_TXN
PCIE20_TXP

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

NC

NC

NC

NC

IN

NC

NC

NC

IN

IN

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

NC

NC

NC

NC

NC

www.laptoprepairsecrets.com

GPPI IS ON VCC3V3_PRIM

14 OF 121

14 OF 93

0.24.0

051-00673

JTAG_ISP_TDO

JTAG_TBT_TMS_PCH

SMC_RUNTIME_SCI_L

PCH_SMBALERT_L

SSD_BFH_L

PCH_CAM_RESET

DP_TBT_SEL

JTAG_ISP_TDI

ENET_LOW_PWR_PCH

ENET_MEDIA_SENSE

JTAG_ISP_TCK

TBT_PWR_REQ_L

AUD_IPHS_SWITCH_EN_PCH

WOL_EN

PCH_STRP_LPC_L

SMC_WAKE_SCI_L

HDD_PWR_EN

TBT_PWR_EN_PCH

SSD_PWR_EN

PCH_CAM_EXT_BOOT_L

TCON_RESET_R_L

TCON_RESET_R_L

SPIROM_USE_MLB

AUD_IPHS_SWITCH_EN_PCH

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

JTAG_ISP_TDO

TBT_CIO_PLUG_EVENT_R_L

DP_TBT_SEL

JTAG_TBT_TMS_PCH

JTAG_ISP_TCK

ENET_MEDIA_SENSE

SDCONN_OC_L

=PP3V3_S0_PCH_VCC

SDCONN_OC_L

SDCONN_STATE_CHANGE

BKLT_FAULT_INT_L

JTAG_ISP_TDI

PCH_EDP_HPD_PD

TCON_RESET_L

=PP3V3_S4_PCH_VCC

=PP3V3_S5_PCH_VCC

PCH_STRP_TOPBLK_SWP_L

ENET_LOW_PWR_PCH

PCH_BOARD_ID<1>

PCH_BOARD_ID<0>

PCH_BOARD_ID<2>

=PP3V3_S5_PCH_VCC

PCH_BOARD_ID<3>

SMBUS_PCH_DATA

PCH_STRP_LPC_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

SML_PCH_0_CLK
SML_PCH_0_DATA

SML_PCH_1_CLK

SML_PCH_1_DATA

GPU_NEPTUNE_EMERALD_ID

PCH_SSD_RESET_L

CPU & CHIPSET: PCH GPIO/Misc

SYNC_MASTER=J95_DEBORAH SYNC_DATE=10/20/2014

MF 201

1 2

100K

1/20W

R1404

5%

100K

1

MF1/20W 201

2

R1490

5%

19 14

MF 201

1

R1489

10K

1/20W

2

NOSTUFF

5%

10K

1

MF 2011/20W

2

R1412

5%

19 14

33

21

R1405

PLACE_NEAR=U1100.M45:10MM

1/16W

MF-LF

402

5%

2

10K

R1453

1/20W

1

201MF

NOSTUFF

5%

2011/20W MF

10K

R1417

21

5%

R1411

2 1

MF 201

10K

1/20W5%

19 14

58 41 14

19

1 2

MF1/20W 201

R1425

10K

5%

40

R1450

2011/20W MF

21

10K

5%

56

58

1/20W MF 201

21

R1421

10K

5%

37 14

BE21
BD18
BC22

AN24

SKL-PCH-H

AU41

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

AT44

BC19

BD26

AL27

AR27

AK44

AT43

AN43

AL43

TBD

FCBGA

U1100

BB22
BD21

BB43

BB39

AU44

AU43

AR45
AR39
AN44

AL44

AL35

AJ39

AK45

AJ43

AN36
AN38
AN41

AM44

AH43

AJ44

AL39

AL36

AR44

AG44

AR41

AR38

AT42

BD22

AY44

OMIT_TABLE

CRITICAL

AV43

BA41
AV44

BA40

AW42

AW44

BB41

AW45

1/20W 201

R1415

10K

1 2

MF5%

47

47

47

47

47

47

BD38

BE39

W39

W36

U1100

N44

M45

R35

L44

U35

Y44

R42

P43

N43

BD7

R39

U41

P44

N42

U42

M44

R43

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

W42

R41

R36

BE34

TBD

FCBGA

OMIT_TABLE

W35

U43

U36

T45

R44

U39

L43

BD34

AW35

BD35

BC35

BB36

BC36

BC38

BD36

AW4

AY2
AV4

BB3

BD6

BE5
BE6

T44

BC4

V44

BA4

BA35

BA5

BB38

SKL-PCH-H

CRITICAL

BD39

2

MF 201

1

R1414

10K

1/20W5%

201

2

R1451

MF1/20W

1

10K

5%

R1424

10K

MF 2011/20W

1 2

5%

35 14

69

R1416

201MF1/20W

2

100K

1

5%

19 14

19 14

19 14

46

91 80

5%

MF

1/20W

2

1

1K

R1440

NOSTUFF

201

R1443

2

1

1K

5%
1/20W
MF

NOSTUFF

201

R1442

1

2

1/20W
MF

NOSTUFF

1K

5%

201

1

1K

2

201

MF

1/20W

5%

NOSTUFF

R1441

45

37 13

1

R1429

2

201MF1/20W

10K

5%

201

MF

R1426

1

100K

1/20W

2

5%

201MF1/20W

21

10K

R1428

NOSTUFF

5%

2

1

201

MF

1/20W

10K

R1423

5%

R1422

2

1

201

10K

1/20W
MF

5%

1/20W

2

MF

1

201

R1427

10K

5%

MF

2 1

2011/20W

R1403

5%

10K

R1407

MF

10K

1

201

2

1/20W5%

1/20W

10K

R1406

2

MF

1

2015%

19 14

19 14

44 12

14

33 13

13

58 41 14

19 14

19 14

35 14

19 14

27 11

19 14

36 13

14

44 12

34 13

19 11

33 13

13

14

37 14

89 19 18 15 12 11

89 13

89 19 18 15 14 13 12

89 19 18 15 14 13 12

14

14

33 13

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

INTEGRATED SENSOR

GPPA/

GPPB

GPPC/SMLINK/I2C/UART

GPPD/INTEGRATED SENSOR/UART/I2C

SYM 6 OF 12

GPP_D9

GPP_D3

GPP_D2

GPP_D1

GPP_D0

GPP_B14/SPKR

GPP_B11

GPP_B1

GPP_A18/ISH_GP0

GPP_A17/ISH_GP7

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

GPP_D4/ISH_I2C2_SDA/I2C3_SDA

GPP_D21
GPP_D22

GPP_D16/ISH_UART0_CTS*

GPP_D15/ISH_UART0_RTS*

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

GPP_D12

GPP_D11

GPP_D10

GPP_C23/UART2_CTS*

GPP_C22/UART2_RTS*

GPP_C21/UART2_TXD

GPP_C19/I2C1_SCL

GPP_C20/UART2_RXD

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPP_C16/I2C0_SDA

GPP_C14/UART1_RTS*/ISH_UART1_RTS*

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C11/UART0_CTS*

GPP_C10/UART0_RTS*

GPP_C9/UART0_TXD

GPP_C8/UART0_RXD

GPP_C7/SML1DATA

GPP_C6/SML1CLK

GPP_C5/SML0ALERT*

GPP_C4/SML0DATA

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C1/SMBDATA

GPP_B0

GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_C0/SMBCLK

OUT

BI

BI

OUT

IN

BI

GPPH/I2C/INTEGRATED SENSOR

/SMLINK

GPPG

GPPF/

BACKLIGHTGPPI/DISPLAY

SYM 9 OF 12

GPP_F19/EDP_VDDEN

GPP_F14

GPP_F22
GPP_F23

GPP_I0/DDPB_HPD0

GPP_I2/DDPD_HPD2

GPP_I1/DDPC_HPD1

GPP_F21/EDP_BKLTCTL

GPP_I3/DDPE_HPD3

GPP_F20/EDP_BKLTEN GPP_G2/FAN_TACH_2

GPP_G1/FAN_TACH_1

GPP_G3/FAN_TACH_3

GPP_G5/FAN_TACH_5

GPP_G4/FAN_TACH_4

GPP_G6/FAN_TACH_6
GPP_G7/FAN_TACH_7

GPP_G11/FAN_PWM_3

GPP_G9/FAN_PWM_1

GPP_G10/FAN_PWM_2

GPP_G8/FAN_PWM_0

GPP_G12/GSXDOUT

GPP_G14/GSXDIN

GPP_G15/GSXSRESET*

GPP_G13/GSXSLOAD

GPP_G16/GSXCLK

GPP_G17/ADR_COMPLETE

GPP_G18/NMI*
GPP_G19/SMI*

GPP_G21

GPP_G20

GPP_G22
GPP_G23

GPP_I4/EDP_HPD

GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA

GPP_H10/SML2CLK
GPP_H11/SML2DATA
GPP_H12/SML2ALERT*

GPP_H13/SML3CLK
GPP_H14/SML3DATA
GPP_H15/SML3ALERT*

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H19/ISH_I2C0_SDA

GPP_H18/SML4ALERT*

GPP_H21/ISH_I2C1_SDA

GPP_H20/ISH_I2C0_SCL

GPP_H22/ISH_I2C1_SCL
GPP_H23

GPP_G0/FAN_TACH_0

IN

IN

OUT

IN

OUT

BI

IN

IN

IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

www.laptoprepairsecrets.com

placeholder for 2.2uH, .33ohm, 100mA inductor

VCCRTC: 1mA Max, 1mA Idle

VCCPGPPEF: 141mA Max, 0mA Idle

VCCPGPPBCH: 273mA Max, 0mA Idle

VCCPGPPA: 88mA Max, 0mA Idle

VCCPCIEPLL: 37mA Max, 0mA Idle

VCC: 6150mA Max, 0mA Idle

VCCHDAPLL: 8mA Max, 0mA Idle

VCCMPHY: 4090mA Max, 0mA Idle

VCCSPI: 13mA Max, 0mA Idle

VCCCLK5: 8mA Max, 0mA Idle

VCCDSW: 502mA Max, 2.06mA Idle

Current data from EDS (doc #546717, Rev 0.7).

VCCHDA: 75mA Max, 0mA Idle

VCCCLK2: 204mA Max, 0mA Idle

VCCCLK1: 35mA Max, 0mA Idle

NEED TO ADD 47UF BULK CAPS TO 1.0V AND 3.3V RAIL

VCCPRIM_3P3: 370mA Max, 0mA Idle

VCCMPHYPLL: 25mA Max, 0mA Idle

VCCPGPPG: 132mA Max, 0mA Idle

VCCRTCPRIM: 1mA Max, 0mA Idle

VCCPGPPG: 132mA Max, 0mA Idle

VCCPGPPD: 106mA Max, 0mA Idle

VCCAPLLEBB NOT IN EDS TABLE: 30mA Max, 0mA Idle

VCCCLK1: 35mA Max, 0mA Idle

placeholder for 2.2uH, .33ohm, 100mA inductor

placeholder for 2.2uH, .33ohm, 100mA inductor

VCCCLK4: 36mA Max, 0mA Idle

VCCCLK3: 58mA Max, 0mA Idle

051-00673

0.24.0

15 OF 121

15 OF 93

=PP1V0_S5_PCH_VCC

PP1V0_S5_PCH_VCC_CLK_F

PPVOUT_PCH_DCPDSW_1P0

=PP3V3_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

PP1V0_S5_PCH_VCC_CLK_F

PPVOUT_PCH_DCPRTC

=PP3V3_S5_PCH_VCC

PP1V0_S5_PCH_VCCUSB2HDA_PLL

=PP3V3_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

SNS_1V0_S5_N

=PP1V0_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

PP1V0_S5_PCH_VCCUSB2HDA_PLL

=PP3V3_S5_PCH_VCC

SNS_1V0_S5_P

PP1V0_S5_PCH_VCC_MPHYPCIE3_PLL

=PP3V3_S5_PCH_VCC

=PP3V3_G3_PCH_RTC

=PP3V3_S0_PCH_VCC

=PP3V3_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

=PP1V0_S5_PCH_VCC

PP1V0_S5_PCH_VCCUSB2HDA_PLL

PP1V0_S5_PCH_VCC_MPHYPCIE3_PLL

=PP1V0_S5_PCH_VCC

=PP3V3_S5_PCH_VCC

SYNC_DATE=10/20/2014SYNC_MASTER=J95_DEBORAH

CPU & CHIPSET: PCH Power/Decoupling

0603

L1503

2.2UH-20%-0.19A-0.221OHM

1 2

0603

1 2

2.2UH-20%-0.19A-0.221OHM

L1502

2.2UH-20%-0.19A-0.221OHM

21

0603

L1501

C1509

25V

20%

22UF

X5R

2

1

0805

C1508

0805

1

2

X5R

22UF

20%
25V

C1507

25V

20%

22UF

X5R

2

1

0805

C1506

25V

20%

22UF

X5R

2

1

0805

C1526

25V

20%

22UF

X5R

2

1

0805

C1525

0805

1

2

X5R

22UF

20%
25V

C1503

25V

20%

22UF

X5R

2

1

0805

0805

1

2

X5R

22UF

20%
25V

C1502

67

SM

NO_XNET_CONNECTION=1

1

2

XW1501

67

PLACE_NEAR=XW1501.2:1MM

XW1500

NO_XNET_CONNECTION=1

1

2

SM

BA20

AL41

CRITICAL

TBD

SKL-PCH-H

OMIT_TABLE

FCBGA

B43

AA23

AA28

BA24

AJ41

BA31

V28

BE4

BC44
BC45

BE3

AJ5
AL5

BE43

BE42

BE41

BA22

BA26

BB45

BA45

BC42

V26

AN19

AC17

AC28
AD15

AE23

Y25

AL22

AJ25

AN5
BD3

BA29

AD13

N17

V17

R17

K2

U20

R19

BA15

K3

AJ23

AJ20

AE26

AD41

BD40

A43

AC26

AC23

Y23

C45

C44

W15

U23
U25
U26

U21

U1100

AA26

AJ21

BYPASS=U1100.AJ5::3MM

2

1

C1539

10V
CERM

0.1UF

20%

402

BYPASS=U1100.BA20::3MM

2

1

0.1UF

20%
10V
CERM
402

C1538

C1537

0.1UF

2

1

BYPASS=U1100.BA22::3MM

CERM

10V

20%

402

C1536

2

1

BYPASS=U1100.BA45::5MM

402

CERM

10%

6.3V

1UF

BYPASS=U1100.BC44::1MM

C1535

0.1UF

2

1

CERM

10V

402

20%

2

1

C1534

CERM

0.1UF

402

20%
10V

BYPASS=U1100.BA31::1MM

0.1UF

BYPASS=U1100.AN19::1MM

C1533

2

1

10V

20%

CERM
402

402

C1531

0.1UF

20%
10V
CERM

2

1

BYPASS=U1100.R17::1MM

CERM

BYPASS=U1100.R19::5MM

2

1

C1532

402

10%

6.3V

1UF

BYPASS=U1100.V28::3MM

1

0.1UF

20%
10V

C1530

2

402

CERM

BYPASS=U1100.AD15::5MM

2

1

C1527

402

1UF

6.3V

10%

CERM

2

1

402

6.3V

10%

CERM

1UF

C1528

BYPASS=U1100.AL22::5MM

2

1

C1529

10%

1UF

BYPASS=U1100.AL22::5MM

402

CERM

6.3V

C1524

20%

2

1

BYPASS=U1100.AC28::1MM

0.1UF

CERM

10V

402

0.1UF

2

1

C1523

CERM

10V

20%

402

BYPASS=U1100.AC23::1MM

2

1

C1522

BYPASS=U1100.AA28::1MM

20%
10V
CERM

0.1UF

402

2

1

C1521

10V

20%

CERM
402

BYPASS=U1100.AA23::1MM

0.1UF

0.1UF

2

1

C1520

20%

402

10V
CERM

BYPASS=U1100.Y23::1MM

2

1

C1512

1UF

BYPASS=U1100.W15::1MM

6.3V

10%

402

CERM

0.1UF

20%

C1511

2

1

BYPASS=U1100.U21::1MM

402

CERM

10V

CERM

BYPASS=U1100.A43::5MM

2

1

C1513

1UF

10%

6.3V

402

402

BYPASS=U1100.BC42::1MM

2

1

C1514

CERM

10V

0.1UF

20%

BYPASS=U1100.BA20::5MM

2

1

C1519

1UF

10%

CERM

6.3V

402

C1515

2

1

20%
10V
CERM

0.1UF

BYPASS=U1100.AJ41::3MM

402

402

10V

0.1UF

C1516

BYPASS=U1100.AD41::3MM

2

1

CERM

20%

C1518

BYPASS=U1100.BA22::5MM

1

1UF

10%

2

CERM
402

6.3V

2

1

402

20%

CERM

10V

BYPASS=U1100.BA26::3MM

0.1UF

C1517

BYPASS=U1100.BA29::5MM

2

1

402

CERM

6.3V

10%

1UF

C1504

2

1

10V

0.1UF

402

CERM

20%

BYPASS=U1100.AN5::3MM

C1501

BYPASS=U1100.AD13::5MM

1

2

C1505

6.3V

10%

1UF

402

CERM

CERM

402

1UF

10%

6.3V

BYPASS=U1100.K2::5MM

C1510

1

2

89 15 11

15

89 19 18 15 14 13 12

89
19 18
15 14

13

12

15

89 19 18 15 14 13 12

15

89 19 18 15 14 13 12

89 15 11

89 15 11

89 19 18

15 14
13 12

15

89 19 18 15 14 13 12

15

89 19 18

15 14 13 12

89 12

89 19 18 14 12 11

89 19 18 15 14 13 12

89 15 11

89 15 11

89 15 11

15

15

89

15 11

89 19 18 15

14 13 12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

PRIMARY WELL

PCIE2/SATA2/PCIE3

ANALOG PLL USB3/

GPPD PRIMARY WELL

GPPE/GPPEF

RTC LOGIC PW/VRM

GPPG PRIMARY WELL

GPPA PRIMARY WELL

ANALOG PLL USB2/VRM

PRIMARY WELL HVCMOS

MOD PHY PRIMARY

GPPB/GPPC/GPPH

MIPI PLL

HD AUDIO POWER

CLOCK BUFFERS PRIMARY 1.0 V

THERMAL SENSOR PW

AUDIO PLL

SPI

RTC WELL SUPPLY

PRIMARY WELL

DEEP SX WELL

POWER

SYM 10 OF 12

PRIMARY WELL

PCIE PLL EBB PRIMARY

VCCSPI

VCCAPLLEBB_1P0

VCCPRIM_1P0 VCCMPHY_1P0

VCCMPHY_1P0

VCCMPHY_1P0

VCCMPHY_1P0

VCCDSW_3P3

VCCMIPIPLL_1P0
VCCMIPIPLL_1P0

VCCPRIM_1P0

VCCPRIM_1P0
VCCPRIM_1P0

VCCAMPHYPLL_1P0

VCCPGPPBCH

VCCPGPPG

VCCRTCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCCLK5

VCCHDA

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK2
VCCCLK2

VCCCLK1

VCCATS

DCPDSW_1P0

VCCPRIM_3P3

VCCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCPRIM_1P0

VCCHDAPLL_1P0

VCCMPHY_1P0

VCCPGPPBCH

VCCPGPPD
VCCPGPPD

DCPRTC

VCCRTC

VCCSPI

VCCSPI

VCCUSB2PLL_1P0

VCCUSB2PLL_1P0

VCCPRIM_3P3

VCCPGPPD

VCCPGPPD

VCCPRIM_3P3

VCCPGPPA

VCCPGPPEF
VCCPGPPEF

VCCDSW_3P3

VCCPRIM_1P0

VCCPRIM_1P0

VCCAMPHYPLL_1P0

www.laptoprepairsecrets.com

0.24.0

16 OF 93

16 OF 121

051-00673

SYNC_DATE=10/20/2014SYNC_MASTER=J95_DEBORAH

CPU & CHIPSET: PCH Grounds

CRITICAL

TBD

SKL-PCH-H

FCBGA

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

OMIT_TABLE

U1100

AB11
AB14
AB15
AB31
AB32
AB38

AC1
AC18
AC20
AC21
AC25
AC29
AC45

AD4

AD8
AD11
AD14
AD32
AD33
AD36

AE4
AE18
AE20
AE21
AE25
AE28
AE29
AE42

AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29

AG4
AG11
AG13
AG31
AG32
AG33
AG38

AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45

AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36

AK4
AK42

AL4
AL10
AL11
AL13
AL17
AL19
AL24
AL29

AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN4
AN7
AN8
AN10
AN11
AN22
AN27
AN31
AN39
AP4
AP11
AR5
AR7
AR9
AR33
AR34
AR42
AT9
AT10
AT15
AT36
AU1
AU7
AU35
AU36
AU39
AU45
AV6
AV17
AV24
AV27
AV31
AV33
AW9
AW13
AW19
AW29
AW37
AY38
AY45
BA1
BB1
BB11
BB16
BB21
BB25
BB30
BB34
BC1
BC2
BD2
BD43
BD44
BD45
BE9
BE14
BE18
BE23
BE28
BE32
BE37
BE40
BE44

FCBGA

CRITICAL

TBD

SKL-PCH-H

SKYLAKE_PCH_FCBGA837_FCBGA_SKL_PCH_H_TBD

OMIT_TABLE

U1100

A2
A3

A4
A18
A25
A32
A37
A42
A44

B1

B2

B3

B6
B25
B37
B40
B44
B45

C2

C4
C10
C28
C37
C42
D10
D12
D15
D16
D17
D19
D21
D24
D25
D27
D29
D30
D31
D33
D35
D36
D45
E13
E15
E31
E33

F8

F44

G9

G42

H3

H17
H19
H22
H24
H27
H29
H35

J3
J5

J7
J10
J11
J39

K4
K10
K27
K33
K36
K42
K43

L4

L8
L12
L13
L15
L41

M35
M42
N4
N5
N10
N15
N19
N22
N24
N35
N36
N41
P17
P19
P22
P45
R5
R10
R14
R22
R29
R33
R38
T1
T2
T4
T42
U4
U8
U10
U11
U14
U15
U17
U18
U28
U29
U31
U32
U33
U38
V3
V18
V20
V21
V23
V25
V29
V45
W4
W8
W14
W31
W32
W33
W38
Y17
Y18
Y20
Y21
Y26
Y28
Y29
AA4
AA17
AA18
AA20
AA21
AA25
AA29
AA42
AB4
AB5
AB7
AB8
AB10

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SYM 12 OF 12

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS

SYM 11 OF 12

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

www.laptoprepairsecrets.com

there is a horizontal mirroring for

WF: SB DPDG says HOOK1 is BP_PWRGD_RST#

PCH SIGNALS

PCH/XDP Signal Isolation Notes:

NOTE: This is a MERGED XDP: = Primary XDP with CPU & PCH JTAGs in a Dual-Scan-Chain

OBSDATA_B2

HOOK3

OBSDATA_C0

OBSFN_C1

TMS

CRB has no-stuff S3 pull-up on PREQ_L

OBSDATA_A1

HOOK2

To configure CPU and PCH JTAG in an ICT Daisy-Chain:

drive ICT_JTAG_DAISY_L to Ground.

OBSFN_D1

OBSFN_D0

OBSFN_A0

SDA

Connect Hook2 to CFG<0>

OBSDATA_A2
OBSDATA_A3

NOTE: TDI and TMS are terminated in CPU.

ICT CPU & PCH JTAG

Daisy-Chain Support (S0):

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_B1

OBSDATA_B0

PDG allows any value from 51 to 3K

support chipset debug.

ITPCLK/HOOK4

OBSDATA_C2

OBSFN_C1

OBSDATA_C0

OBSDATA_B3

PWRGD/HOOK0

XDP_PRESENT#

SCL

998-2516

ICT CPU & PCH JTAG

(as in CRB)

and pull-up to S0

Drive ICT_JTAG_DAISY to 5V and

signal destination (to minimize stub).

from PCH to J1850 and path to non-XDP

signal path needs to split between route

HOOK2

OBSDATA_C1

OBSDATA_A2

Secondary (PCH) Micro2-XDP

TP1847 = TRST_L

Primary Micro2-XDP

there is a horizontal mirroring for

use with 921-0133 Adapter Flex to

OBSDATA_D2

OBSFN_D1

Extra BPM Testpoints

OBSFN_B1

HOOK1

TRSTn

OBSFN_A1

OBSDATA_C1

OBSDATA_C3

use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout,

RESET#/HOOK6

OBSFN_C0

OBSDATA_D0

OBSDATA_C3

VCC_OBS_AB

OBSDATA_D0

VCC_OBS_CD

ITPCLK#/HOOK5

OBSDATA_A3

OBSDATA_A0

OBSFN_A1

OBSFN_B0

TCK0

DBR#/HOOK7

OBSDATA_D3

OBSDATA_D1

OBSFN_C0

OBSFN_A0

OBSDATA_A0
OBSDATA_A1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

OBSFN_B1

TDO

OBSFN_B0

XDP_PRESENT#

998-2516

OBSFN_D0

R187x and R189x should be placed where

HOOK1 ITPCLK#/HOOK5

RESET#/HOOK6

TCK1 TDI

VCC_OBS_CD

ITPCLK/HOOK4

SCL

SDA

HOOK3

VCC_OBS_AB

DBR#/HOOK7

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1

Test-Points:

TP1840 = TMS

TP1841 = TDI

TP1842 = TDO

TP1843 = TCK0

(TP1844 = TCK1)

TP1845 = DAISY
TP1846 = DAISY_L

NOTE: This is not the standard XDP pinout,

support chipset debug.

OBSDATA_C2

XDP SIGNALS

18 OF 121

17 OF 93

0.24.0

051-00673

PM_PCH_SYS_PWROK

XDP_BPM_L<2>

XDP_PCH_SATALED_L

XDP_CPU_TDO

XDP_CPU_TDO_PCH_TDI

XDP_PCH_SATAXPCIE7_SATAGP7

XDP_PCH_CPU_GP1

XDP_PCH_CPU_GP0

XDP_PCH_RSMRST_L

=SMBUS_XDP_SDA

XDP_PM_SYSRST_L

XDP_PCH_ITP_PMODE

=PP3V3_S5_ROM

PM_PWRBTN_L

CPU_RESET_L

PCH_ITP_PMODE

SPI_IO_R<2>

XDP_PCH_USB2_OC0_L

XDP_CPU_TDI

XDP_CPU_TDO

=SMBUS_XDP_SCL

XDP_PCH_TDO

XDP_PCH_SATAXPCIE3_SATAGP3

XDP_PCH_DEVSLP2

XDP_CPU_TCK

XDP_PCH_TDI

XDP_PCH_SATAXPCIE6_SATAGP6

XDP_PCH_SATAXPCIE4_SATAGP4

XDP_CPU_TDI_PCH_TDI XDP_PCH_TDI

=PPVCCIO_S0_CPU

=PP1V0_S3_XDP

XDP_CPU_TMS

XDP_CPU_PCH_TDO

XDP_CPU_TRST_L

XDP_CPU_TDO

XDP_PCH_SATAXPCIE1_SATAGP1

XDP_PCH_TCK_R_2

XDP_DBRESET_L

CPU_CFG<1>

CPU_CFG<0>

CPU_CFG<16>

XDP_PCH_TDO

=PP5V_S5_XDP

XDP_CPU_PCH_TCK

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

XDP_BPM_L<0>

XDP_CPU_PRDY_L

CPU_CFG<5>

XDP_CPU_TRST_L

XDP_CPU_PRESENT_L

XDP_BPM_L<3>

CPU_PWRGD

CPU_CFG<4>

XDP_PCH_DEVSLP1

CPU_CFG<11>

CPU_CFG<13>

XDP_CPURST_L

XDP_CPU_TMS

=SMBUS_XDP_SCL

ICT_JTAG_DAISY_L

XDP_PCH_SATAXPCIE0_SATAGP0

CPU_CFG<2>

XDP_CPU_PREQ_L

CPU_CFG<12>

ITPXDP_CLK100M_P

XDP_PCH_TCK

ICT_JTAG_DAISY

CPU_CFG<18>

=PP1V0_S5_XDP

XDP_CPU_TDI

XDP_VR_READY

CPU_CFG<14>

CPU_CFG_3_R

CPU_CFG<17>

CPU_CFG<19>

XDP_BPM_L<1>

CPU_CFG<3>

ITPXDP_CLK100M_N

XDP_PCH_USB2_OC1_L

XDP_PCH_DEVSLP0

=SMBUS_XDP_SDA

CPU_CFG<7>

XDP_CPU_PWRGD

CPU_CFG<15>

=PP1V0_S5_XDP

CPU_CFG<6>

PM_RSMRST_PCH_L

PM_VCCST_PWRGD

XDP_PCH_TDO
XDP_PCH_TDI

XDP_PCH_TMS

=PP1V0_S3_XDP

XDP_PCH_USB2_OC3_L

XDP_PCH_CPU_GP0

XDP_PCH_DEVSLP0

XDP_PCH_DEVSLP1
XDP_PCH_DEVSLP2

XDP_PCH_RSMRST_L

XDP_PCH_SATALED_L

XDP_PM_SYSRST_L

XDP_PCH_USB2_OC0_L

XDP_PCH_USB2_OC2_L

XDP_PCH_USB2_OC1_L

PCH_PREQ_L

PCH_PRDY_L

PCH_SATAXPCIE6_SATAGP6

PCH_SATAXPCIE7_SATAGP7

PCH_DEVSLP0

PCH_ITP_PMODE

PCH_SATALED_L

PM_RSMRST_PCH_L

PM_SYSRST_L

USB_EXTA_OC_L

USB_EXTC_OC_L

USB_EXTB_OC_L

USB_EXTD_OC_L

XDP_CPU_HOOK2_R

XDP_CPU_PWRBTN_L

SPI_MOSI_R

XDP_PCH_SATAXPCIE2_SATAGP2

XDP_CPU_PREQ_L

XDP_PRDY_L_R

XDP_PCH_PRDY_L_R

XDP_PREQ_L_R

XDP_PCH_PRDY_L

XDP_PCH_SATAXPCIE4_SATAGP4
XDP_PCH_SATAXPCIE5_SATAGP5

XDP_PCH_SATAXPCIE6_SATAGP6

XDP_PCH_SATAXPCIE3_SATAGP3

XDP_PCH_SATAXPCIE2_SATAGP2

XDP_PCH_PREQ_L

XDP_CPU_PRDY_L

PCH_SATAXPCIE2_SATAGP2

PCH_SATAXPCIE0_SATAGP0
PCH_SATAXPCIE1_SATAGP1

PCH_SATAXPCIE3_SATAGP3
PCH_SATAXPCIE4_SATAGP4

PCH_SATAXPCIE5_SATAGP5

XDP_PCH_OBSDATA_A2

PCH_DEVSLP1

PCH_DEVSLP2

XDP_PCH_OBSDATA_B2

XDP_PCH_SATAXPCIE1_SATAGP1

XDP_PCH_SATAXPCIE0_SATAGP0

XDP_PCH_PRDY_L

XDP_PCH_PREQ_L

XDP_PCH_PREQ_L_R

XDP_CPU_TCK

XDP_PCH_TCK

=PP1V0_S5_XDP

XDP_PCH_USB2_OC3_L

XDP_PCH_USB2_OC2_L

XDP_PCH_SATAXPCIE5_SATAGP5

XDP_PCH_CPU_GP1

XDP_PCH_ITP_PMODE

XDP_PCH_SATAXPCIE7_SATAGP7

SYNC_MASTER=J95_ANDREW

CPU & CHIPSET: XDP

SYNC_DATE=01/24/2015

6

6

20%

10V

XDP

0.1UF

CERM

C1898

402

1

2

XDP

20%

10V

0.1UF

CERM

C1899

402

1

2

0201

1/20W

5%

MF

2

0

PLACE_NEAR=U1100.AT4:28mm

R1852

1

R1850

0

PLACE_NEAR=U1100.AT3:28mm

02011/20W

5%

21

MF

2

1/20W

5%

1

0201

MF

NOSTUFF

0

R1851

PLACE_NEAR=R1850:10mm

NOSTUFF

0201MF

0

2

5%

1/20W

PLACE_NEAR=R1852:10mm

R1853

1

1

TP-P6

TP1847

TP-P6

1

TP1844

1

TP-P6

TP1842

TP1841

TP-P6

1

TP-P6

TP1840

1

6

0

MF

5%

1/20W

R1803

0201

21

NOSTUFF

NOSTUFF

5%
1/20W
MF
201

R1801

2.2K

1

2

5%
1/20W

PLACE_NEAR=U0500.F11:28mm

201

2

51

R1823

XDP

MF

1

5%

0

21

MF

1/20W

NOSTUFF

0201

R1829

R1837

1/20W

0

5%

0201

1

MF

2

NOSTUFF

R1843

0

5%

NOSTUFF

1/20W

21

MF

0201

1/20W

0

5%
MF

R1844

NOSTUFF

21

0201

5%

2.2K

MF
201

2

1

1/20W

R1836

3

1

2

DFN1006H4-3

Q1844

DMN32D2LFB4

201

2

1

MF

1/20W

5%

1M

R1854

3

2

DFN1006H4-3

1

Q1845

DMN32D2LFB4

17 11

R1847

201

MF
1%

21

1/20W

XDP

150

1

R1839

2

MF

201

5%

1/20W

XDP

1K

0201

MF

2

5%

1/20W

0

1

R1849

PLACE_NEAR=U0500.B10:28mm

PLACE_NEAR=U0500.B9:28mm

R1848

0201MF

5%

21

0

1/20W

5%

MF

R1838

0

1 2

1/20W

PLACE_NEAR=J1800.51:5MM

0201

0201

MF

1/20W5%

2

0

R1828

1

73 8

PLACE_NEAR=U0500.U2:16.5mm

1/20W

NOSTUFF

1K

21

R1891

5%

MF 201

0201MF

1/20W

5%

0

21

XDP

R1807

46 12

0

MF

R1826

21

5%

1/20W

0201

XDP

402

1

0.1UF

2

20%

C1805

10V

CERM

XDP

0

NOSTUFF

R1899

MF

0201

5%

1

1/20W

2

46 12

5%

XDP

1

1/20W

R1825

MF

2

0

0201

5%
1/16W
MF-LF

1

1K

402

2

NOSTUFF

R1898

17 11

2

201

MF

1

R1808

5%
1/20W

2.2K

17 11

73 17 12

XDP

1K

21

5%

1/20W

MF

201

PLACE_NEAR=U0500.AB35:16.5mm

R1806

42 13

42 13

43 13

43 13

R1834

OMIT

SHORT

21

402NONE NONE NONE

R1832

OMIT

NONENONE

2

NONE 402

1

SHORT

R1835

OMIT

SHORT

402

1 2

NONE NONE NONE

R1833

OMIT

NONE 402

1 2

NONE NONE

SHORT

44 18 12

73 17 12

12

12 6

6

OMIT

R1884

NONE NONE NONE

1 2

SHORT

402

13

13

13

13

13

13

13

13

91 11

91 11

17 11 6

DMN5L06VK-7

Q1840

2

1

6

SOT563

PLACE_NEAR=J1800.58:5.08MM

SOT563

DMN5L06VK-7

4

5

3

PLACE_NEAR=J1800.57:5.08MM

Q1840

DMN5L06VK-7

PLACE_NEAR=J1800.58:5.08MM

2

6

1

SOT563

Q1846

5

4

DMN5L06VK-7

3

PLACE_NEAR=J1800.57:6MM

SOT563

Q1846

2

201

51

R1862

1

XDP

MF

5%
1/20W

U1100.AR2:3.5mm

1/20W
MF

PLACE_NEAR=U1100.AN3:28mm

R1866

1

201

2

5%

XDP

51

47 17

MF

1/20W

1

2

51

5%

J1850.51:2.54mm

R1860

201

XDP

R1861

MF

51

5%

201

2

1

XDP

1/20W

U1100.AP2:4mm

47 17

R1887

OMIT

402NONENONENONE

1 2

SHORT

SHORT

R1886

OMIT

NONE 402NONE

1 2

NONE

R1882

OMIT

NONE

SHORT

NONE

1 2

402NONE

R1879

OMIT

NONE

SHORT

402

1 2

NONE NONE

R1878

OMIT

NONE

SHORT

NONE

1 2

NONE 402

R1875

OMIT

SHORT

402

1 2

NONE NONE NONE

2

R1874

OMIT

NONENONE 402NONE

1

SHORT

NONE

R1872

OMIT

2

402NONE

SHORT

1

NONE

R1873

OMIT

NONE

1 2

NONE 402NONE

SHORT

SHORT

OMIT

402NONENONE

1 2

R1883

NONE

R1880

SHORT

402

OMIT

1

NONENONE2NONE

R1881

SHORT

OMIT

NONE

2

402NONE1NONE

NONE

R1896

NONE

OMIT

402NONE

SHORT

1 2

R1897

402

OMIT

NONE

2

NONENONE

SHORT

1

R1894

SHORT

1

NONE

OMIT

NONE

2

402NONE

NONE

R1895

SHORT

NONE

OMIT

402

21

NONE

PLACE_NEAR=U1100.AT4:28mm

NONE

SHORT

OMIT

R1893

2

NONE

1

402NONE

NONE

PLACE_NEAR=U1100.AT3:28mm

1

SHORT

R1890

OMIT

402NONE2NONE

1/20W 201MF

R1804

5%

2

220

1

NOSTUFF

1

2

XDP

C1806

20%

402

10V

0.1UF

CERM

6

CERM

2

C1804

NOSTUFF

0.1UF

402

10V

20%

1

33 13

12

13

13

17 11

13

12

12

6

R1840

2

1

1M

5%
1/20W
MF
201

6

201

1/20W

5%

MF

2

1M

1

R1841

PLACE_NEAR=J1800.51:5.08mm

201

5%

2

MF

1M

1

R1842

1/20W

TP1845

1

TP-P6

PLACE_NEAR=J1800.51:5.08mm

1/20W

5%

2

201

1

MF

1K

R1845

TP-P6

1

TP1846

1

TP-P6

TP1843

DMN32D2LFB4

PLACE_NEAR=J1800.51:5.08mm

Q1842

2

1

3

DFN1006H4-3

6

2

1

3

Q1848

DFN1006H4-3

PLACE_NEAR=J1850.55:5.08mm

DMN32D2LFB4

17 6

17 6

TP1803

1

TP-P6

TP-P6

1

TP1802

6

6

XDP

1K

1/16W

5%

402

2

1

R1831

MF-LF

6

6

6

6

C1800

0.1UF

20%

2

1

10V

CERM

402

XDP

6

0.1UF

XDP

CERM
402

10V

1

C1801

2

20%

XDP_CONN

19

22

28

13

51

55

53

43

36

49

58

35

60

46

3

21

4

56

23

8

61

57

M-ST-SM

2

56

7

910

1112

1516

1718

20

27

2930

3132

33

3940

4142

45

47

50

54

62

6364

34

38

44

48

52

59

14

25

37

24

26

DF40RC-60DP-0.4V

1

J1850

CRITICAL

24

17

22

58

51

39

53

59

J1800

13

8

54

CRITICAL

M-ST-SM

30

25

63

48

60

49

62

61

38

35

34

31

29

23

21

19

15

12 11

7

5

3

1

14

64

16

9

37

56

32

52

18

26

44

33

20

42

46

6

4

2

50

43

41

45

36

DF40RC-60DP-0.4V

10

28 27

XDP_CONN

40

47

57

55

6

PLACE_NEAR=U0500.AB35:16.5mm

1 2

1K

R1800

5%

1/20W

MF

201

NOSTUFF

0201

0

1

R1802

2

XDP

5%

1/20W

MF

5%

NOSTUFF

2 1

R1824

1/20W

MF 201

51

PLACE_NEAR=J1800.51:5MM

12

XDP

51

R1820

201

1/20W

MF5%

201

MF

5%

1K

21

R1805

PLACE_NEAR=R1808.2:5MM

1/20W

NOSTUFF

17 6

17 6

17 12 6

6

18

17 11

73 45 12

44 12

0.1UF

C1881

XDP

10V

20%

402

CERM

1

2

402

1

2

CERM

10V

20%

0.1UF

C1880

XDP

47 17

47 17

91 6

91 6

11

17 11

91 6

91 6

6

6

12 6

6

17

17 6

17

17

17

17

17

17

89 46

17

17 6

17 6

17 11

17

17

17 11 6

17 11

17

17

17 11

89 10 8 5

89 17

17 6

17 12 6

17 6

17

89

17

17

17 11

89 17

17

17

89 17

89 17

17

17

17

17

17

17

17

17

17

17

17

17

17 6

17

17

17

17

17

17

17

17 6

17

17

17

17

89 17

17

17

17

17

17

17

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

TP

TP

TP

TP

TP

IN

GS

SYM_VER_3

D

GS

SYM_VER_3

D

NC

NC

OUT

NC

NCNC

NC

IN

OUT

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

BI

NC

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

NC

NC

IN

IN

OUT

D S

VER 5

G

D S

VER 5

G

DS

VER 5

G

DS

VER 5

G

IN

BI

NC

NC

NC

NC

NC

NC

IN

BI

BI

BI

BI

OUT

BI

IN

IN

IN

IN

TP

TP

TP

GS

SYM_VER_3

D

IN

GS

SYM_VER_3

D

IN

BI

TP

TP

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

BI

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

SMC controls strap enable to allow in-field control of strap setting.

PCH RTC Crystal

(APN: 998-6925)

COIN-CELL HOLDER

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH Reset Button

Place TP1901-TP1903 on bottom side

RTC Power Sources

18 OF 93

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

VOLTAGE=3.3V

19 OF 121

0.24.0

051-00673

PCH_CLK32K_RTCX1

RTC_RESET_L

PP3V3_G3_RTC_SW

SMC_ASSERT_RTCRST_R

PP3V3_G3_RTC

PP3V3_G3H_RTC_D_R

PCH_CLK32K_RTCX2_R

PPVBATT_G3_RTC_R

=PP3V3_G3H_RTC_D

HDA_SDOUT_R

PPVBATT_G3_RTC

=PP3V3_S0_PCH_VCC

PM_SYSRST_L

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S5_PCH_VCC

XDP_DBRESET_L

PCH_CLK32K_RTCX2

SMC_ASSERT_RTCRST

SPI_DESCRIPTOR_OVERRIDE_R

SYNC_DATE=09/10/2014SYNC_MASTER=BRANCH_SYEDKAR

CPU & CHIPSET: Chipset Support

C1931

CERM

0.1UF

20%
10V

402

1

2

R1941

5%

1

2

30K

1/16W
MF-LF
402

R1940

1K

5%

2

1/16W
MF-LF
402

1

BAT-HLDR-RCPT-J94-J95

J1900

SM

21

50V
C0G

5%

1

0402

PLACE_NEAR=Y1910.1:2MM

C1911

2

12PF

5%

50V

0402

PLACE_NEAR=Y1910.4:2MM

C1910

1 2

12PF

C0G

0.1UF

10V

20%

CERM

402

1

2

C1930

21

MF-LF

5%

1/16W

10K

402

R1930

SOT-23-HF

NTR4101P

CRITICAL

Q1930

3

1

2

44

2

NTR1P02L

SOT23-3-HF

Q1920

3

1

330

PLACE_NEAR=R1111.2:15MM

R1921

1/16W 4025% MF-LF

1 2

11

12

12

1/16W

402

MF-LF

5%

10M

R1911

1

2

402

5%

1K

1/16W
MF-LF

R1902

2 1

R1910

2

402

MF-LF

0

1/16W

5%

1

PLACE_NEAR=U1100.BD10:25.4MM

Y1910

41

SM-HF

32.768K-12.5PF

CRITICAL

PLACE_NEAR=U1100.BC9:25.4MM

1.4-SQ-NSP

TP1902

SM-PAD

1

OMIT

TP1900

1.97X2.02MM-NSP

SMT-PAD

OMIT

1

OMIT

SM-PAD

1

1.4-SQ-NSP

TP1903

1.97X2.02MM-NSP

SMT-PAD

OMIT

TP1901

1

D1900

SOT-363

BAT54DW-X-G

1

4

6

3

5

2

44 17 12

1/16W

402

MF-LF

5%

4.7K

R1995

1

2

1/16W

5%

402

MF-LF

0

OMIT

SILK_PART=SYS RESET

R1997

1

2

XDP

1/16W

402

5%

MF-LF

0

R1996

1 2

17

45 12

89

89

89 19 15 14 12 11

89 19 15 14 13 12

45

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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THE POSESSOR AGREES TO THE FOLLOWING:

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SHEET

PAGE TITLE

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A

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

S D

G

IN

D

G

S

OUT

OUT

IN

NC NC

NC NC

OUTIN

www.laptoprepairsecrets.com

GPIO Glitch Prevention

Platform Reset Connections

TBT_PWR_EN goes high for JTAG Programming

Unbuffered

TBT_LC can be on when S0 is off and vice-versa.

U2060 Supports I/Os powered when VCC = 0V

Isolation ensure no leakage to FR or PCH

Same as J45, J90,RR RefDesign

Buffered

19 OF 93

20 OF 121

0.24.0

051-00673

TBT_PWR_EN_PCH

JTAG_TBT_TCK_B

TBT_PWR_EN

JTAG_TBT_TCK

JTAG_ISP_TCK

LPC_PWRDWN_L

TBT_CIO_PLUG_EVENT_R_L

TBT_CIO_PLUG_EVENT_L

TBT_PWR_EN

SMC_LRESET_L

MAKE_BASE=TRUE

SSD_RESET_L

TP_VR_GPU_RESET_L

=PP3V3_TBTLC

JTAG_TBT_TMS

=PP3V3_S0_PCH_VCC

JTAG_TBT_TDO

TP_GPU_RESET_L

TBT_PCIE_RESET_L

ENET_SD_RESET_L

JTAG_TBT_TDI

JTAG_ISP_TDI

PLT_RST_BUF_GPU_L

PLT_RST_BUF_TBT_L

JTAG_TBT_TMS_PCH

=PP3V3_S5_RSTBUF

=PP3V3_S5_RSTBUF

=PP3V3_S0_RSTBUF

PLT_RST_BUF_SSD_L

=PP3V3_S0_PCH_VCC

JTAG_ISP_TDO

PLT_RST_BUF_L AP_RESET_L

MAKE_BASE=TRUE

PLT_RESET_L

=PP3V3_S5_RSTBUF

PCIE_WAKE_L

TBT_WAKE_L

=PP3V3_S4_TBT

AUD_IPHS_SWITCH_EN

ENET_LOW_PWR

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S5_PCH_VCC

PM_PCH_PWROK

PM_PCH_PWROK

ENET_LOW_PWR_PCH

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

CPU & CHIPSET: Project Chipset Support

26

26

26

5%

10K

201

MF

1/20W

R2063

1

2

5%
1/20W

201

10K

MF

R2062

1

2

14

14

26

2

1

C2013

0.1UF

10%
16V

0201

X5R-CERM

26 19

14

37 35

2

1

C2050

402

CERM

10V

0.1UF

20%

14

82 73 39 19 12

56

82 73 39 19 12

14

CERM-X5R

2

1

0201

0.1UF

10%

6.3V

C2075

2

1

0201

C2070

0.1UF

CERM-X5R

6.3V

10%

SOT1226

74LVC1G34GX

2 4

U2075

5

3

1

SOT891

1

5

U2070

6

74LVC2G34

2

74LVC2G34

CKPLUS_WAIVE=unconnected_pins

U2070

SOT891

2

5

3 4

14

MF-LF

402

1/16W

5%

R2095

1

1K

2

1/20W

0201

21

R2019

MF

5%

0

CERM

20%

402

10V

0.1UF

C2060

1

2

14

MF

1/20W

5%

10K

201

R2061

1

2

U2060

SN74AUP3G07DQER

7

X2SON

1

3

6

4

8

5

2

26 19

44 12

14 11

NO STUFF

2

0

5%

MF

1/20W

0201

R2071

1

2

1

CRITICAL

SOD

Q2070

3

R2070

1

10K

MF-LF

1/16W

5%

402

2

21

R2017

0201

5%

1/20W

MF

0

8

U2000

74LVC2G08GT/S505

5 3

7

4

6

2

1

SOT833

CRITICAL

74LVC2G08GT/S505

CRITICAL

U2050

SOT833

1

5

2

6

8

7

3

4

26

1/20W

100K

MF
201

5%

R2016

1

2

26

90

33

MF-LF

402

5%

1/16W

R2090

1 2

33

C2080

10V

402

0.1UF

CERM

20%

1

2

MC74VHC1G08

CRITICAL

SOT23-5-HF

4

1

U2080

3

2

5

MF-LF

1/16W

402

R2080

5%

100K

1

2

21

R2092

MF-LF

402

5%

33

1/16W

21

MF-LF

1/16W

402

R2091

33

5%

21

R2088

MF-LF

402

33

5%

1/16W

GPU_AM_EM

R2094

5%

1/16W

1

33

MF-LF

402

2

12

MF-LF

5%

1/16W

33

402

R2055

1 2

37

32

90

44

89

89 19 18 15 14 12 11

89 19

89 19

89

89 19 18 15 14 12 11

89 19

36 32 12 26

89 72 31 30 29 27 26

89 18 15 14 13 12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

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IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

IN

IN

OUT

OUTIN

IN

OUTIN

IN

OUT

IN

IN

NC

NC

Y

A

34

Y

A

34

OUT

IN

2Y2A

3A3Y

1A

VCC

1Y

GND

OUT

IN

IN

D

S

G

A2

B1

A1

VCC

B2

GND

Y2

Y1

08

A2

B1

A1

VCC

B2

GND

Y2

Y1

08

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

www.laptoprepairsecrets.com

of margining option.

VRef Dividers

Always used, regardless

22 OF 121

20 OF 93

051-00673

0.24.0

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3000

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3000

MEM_VREFCA_A_RC

=PPDDR_S3_MEMVREF

CPU_DIMMA_VREFDQ

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFDQ_A

CPU_DIMMB_VREFDQ

MEM_VREFDQ_A_RC

MEM_VREFDQ_B_RC

PPVREF_S3_MEM_VREFCACPU_DIMM_VREFCA

SYNC_DATE=03/10/2014SYNC_MASTER=J78_DAVID

DRAM: VREF/VTT EN

7

7

7

2

0201

MF

1/20W

1%

R2263

1 2

PLACE_NEAR=C2260.1:2MM

1%

0201

2

MF

1 2

PLACE_NEAR=C2240.1:2MM

R2243

1/20W

R2221

PLACE_NEAR=R2223.2:1.5MM

MF-LF

1/16W

402

1%

1K

1

2

PLACE_NEAR=R2221.2:1mm

MF-LF

402

1/16W

1%

1K

R2222

1

2

PLACE_NEAR=R2243.2:1mm

402

1%

1K

MF-LF

1/16W

R2241

1

2

R2220

1%

1/20W

MF

201

24.9

1 2

PLACE_NEAR=C2220.1:2mm

2

2

1%

0201

1/20W

MF

R2223

1

X5R-CERM

6.3V

10%

C2220

1

2

0201

0.022UF

MF-LF

1/16W

402

1%

1K

R2242

1

2

PLACE_NEAR=R2241.2:1mm

1%

1K

MF-LF

1/16W

402

1

2

R2261

PLACE_NEAR=R2263.2:1mm

24.9

1%

1/20W

MF

201

R2240

1 2

MF-LF

PLACE_NEAR=R2261.2:1mm

1K

1/16W

1%

402

1

2

R2262

24.9

1%

1/20W

MF

201

R2260

1 2

0.022UF

10%

6.3V

1

2

C2240

0201

X5R-CERM

0201

X5R-CERM

0.022UF

10%

6.3V

C2260

2

1

89

24 23

22 21

24 23 22 21

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

www.laptoprepairsecrets.com

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

P/N: 516S1019

Power aliases required by this page:

- =PPDDRVTT_S0_MEM_A

- =I2C_SODIMMA_SDA

BOM options provided by this page:

- =PPVDDQ_S3_MEM_A

- =PP1V5_S0_MEM_A

(NONE)

Page Notes

- =I2C_SODIMMA_SCL

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

21 OF 93

23 OF 121

0.24.0

051-00673

=PPDDRVTT_S0_MEM_A

MEM_A_A<5>

PPVREF_S3_MEM_VREFDQ_A

=MEM_A_DQ<22>

MEM_A_CKE<0>

=PPVDDQ_S3_MEM_A

MEM_A_BA<2>

MEM_A_CLK_N<0>

MEM_A_A<10>

MEM_A_CAS_L

=MEM_A_DQ<32>

=MEM_A_DQS_N<4>

=MEM_A_DQ<34>
=MEM_A_DQ<35>

=MEM_A_DQ<40>
=MEM_A_DQ<41>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQS_P<7>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

MEM_A_A<0>

=PPVDDQ_S3_MEM_A

=PPDDRVTT_S0_MEM_A

PPVREF_S3_MEM_VREFCA

MEM_DIMM0_SA<0>

MEM_DIMM0_SA<0>

MEM_DIMM0_SA<1>

MEM_DIMM0_SA<1>

MEM_EVENT_L

=PP3V3_S0_MEM_A_SPD

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<5>

MEM_A_CS_L<0>

MEM_A_RAS_L

MEM_A_CLK_N<1>

=MEM_A_DQS_N<3>

MEM_RESET_L

=MEM_A_DQS_N<0>

=MEM_A_DQ<31>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=MEM_A_DQ<62>
=MEM_A_DQ<63>

=MEM_A_DQ<53>

=MEM_A_DQ<60>
=MEM_A_DQ<61>

=MEM_A_DQ<52>

=MEM_A_DQ<45>

=MEM_A_DQ<44>

=MEM_A_DQ<47>

=MEM_A_DQ<36>
=MEM_A_DQ<37>

=MEM_A_DQ<38>
=MEM_A_DQ<39>

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CLK_P<1>

MEM_A_A<2>

MEM_A_A<6>
MEM_A_A<4>

MEM_A_A<11>
MEM_A_A<7>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

=MEM_A_DQ<30>

=MEM_A_DQS_P<3>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

=MEM_A_DQ<21>

=MEM_A_DQ<13>

=MEM_A_DQ<14>
=MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<12>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<4>
=MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_A<3>

=MEM_A_DQ<2>
=MEM_A_DQ<3>

=MEM_A_DQ<8>
=MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_P<2>

=MEM_A_DQ<24>
=MEM_A_DQ<25>

=MEM_A_DQ<19>

=MEM_A_DQ<26>

MEM_A_CLK_P<0>

MEM_A_A<1>

=MEM_A_DQ<33>

=MEM_A_DQS_P<4>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<48>
=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<56>
=MEM_A_DQ<57>

=MEM_A_DQ<58>
=MEM_A_DQ<59>

=PP3V3_S0_MEM_A_SPD

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<2>

MEM_A_WE_L

MEM_A_CS_L<1>

=MEM_A_DQ<27>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<0>
=MEM_A_DQ<1>

SYNC_DATE=10/30/2013SYNC_MASTER=J78_NAT

DRAM: SO-DIMM Connector A Slot0

SODIMM-P0.60-D8

F-ANG-SM-1

J2300

205

206

207

208

209

194

SODIMM-P0.60-D8

F-ANG-SM-1

CRITICAL

J2300

9897

9695

9291

90

86

89

85

107

8483

119

80

78

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

15
17

4
6

16
18

21
23

33
35

22
24

34
36

39
41

51
53

40
42

50
52

57
59

67
69

56
58

68
70

129
131

141
143

130
132

140
142

147
149

157
159

146
148

158
160

163
165

175
177

164
166

174
176

181
183

191
193

180
182

192

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

81 82

87 88

93 94

99 100

105 106

111 112

117 118

123 124

199

126

1 2
3

8

9

13 14

19 20

25 26

31 32

37 38

43 44

48

49

54

55

60

61

65 66

71 72

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

25 22

1UF

402

10V
X5R

10%

C2350

1

2

C2351

10V
402

1UF

X5R

10%

1

2

1UF

402

10V
X5R

10%

C2352

1

2

10V
402

1UF

X5R

10%

1

2

C2353

10V
CERM
402

20%

0.1UF

C2323

1

2

CERM
402

20%
10V

0.1UF

C2322

1

2

CERM

10V

20%

402

0.1UF

C2321

1

2

CERM
402

20%
10V

0.1UF

C2320

1

2

CERM
402

20%
10V

0.1UF

C2319

1

2

CERM
402

20%
10V

0.1UF

C2318

1

2

10V

20%

402

CERM

0.1UF

C2317

1

2

CERM
402

10V

20%

0.1UF

C2316

1

2

CERM
402

20%
10V

0.1UF

C2315

1

2

402

CERM

20%
10V

0.1UF

C2314

1

2

10V

20%

402

CERM

0.1UF

C2313

1

2

CERM
402

20%
10V

0.1UF

C2312

1

2

CERM

10V

20%

402

0.1UF

C2311

1

2

402

10V

20%
CERM

0.1UF

C2310

1

2

X5R
603

20%

10UF

6.3V

C2301

1

2

X5R
603

10UF

20%

6.3V

C2300

1

2

2.2UF

402-LF

CERM

20%

6.3V

C2340

1

2

R2340

MF-LF
402

5%
1/16W

10K

1

2

1/16W
402

MF-LF

5%

10K

R2341

1

2

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

7

22 7

22 7

22 7

22 7

22 7

7

7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

7

47 22

47

22

45 44 24 23 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

6.3V

2.2UF

CERM
402-LF

20%

C2335

1

2

CERM
402

20%
10V

0.1UF

C2336

1

2

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

7

25 22

25 22

25 22

25 22

25 22

7

7

22 7

22 7

7

7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

25 22

24 23 22 12

25 22

25 22

25 22

25 22

25 22

25 22

25 22

7

25 22

25 22

2.2UF

402-LF

20%
CERM

6.3V

C2330

1

2

402

20%
CERM

10V

0.1UF

C2331

1

2

25 22

25 22

89 22 21

22 20

89 22 21 89 22 21

89 22 21

24 23 22 20

21

21

21

21

89 22 21

89 22 21

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

BI

NC

NC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI BI

BI

www.laptoprepairsecrets.com

P/N: 516S1019

- =I2C_SODIMMA_SDA

- =PPDDRVTT_S0_MEM_A

Page Notes

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =I2C_SODIMMA_SCL

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

- =PPVDDQ_S3_MEM_A

Power aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

22 OF 93

24 OF 121

0.24.0

051-00673

=PP3V3_S0_MEM_A_SPD

=PP3V3_S0_MEM_A_SPD

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_A<3>

=MEM_A_DQ<54>
=MEM_A_DQ<55>

=MEM_A_DQS_P<0>

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQ<6>
=MEM_A_DQ<7>

=MEM_A_DQ<1>

=MEM_A_DQ<12>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

=MEM_A_DQ<21>

=MEM_A_DQ<22>
=MEM_A_DQ<23>

=MEM_A_DQ<28>
=MEM_A_DQ<29>

=MEM_A_DQS_P<3>

=MEM_A_DQ<30>

MEM_A_CKE<3>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<2>
MEM_A_A<0>

MEM_A_CLK_P<3>

MEM_A_ODT<3>

MEM_A_ODT<2>

MEM_A_BA<1>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQ<45>

=MEM_A_DQ<52>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DQS_P<7>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

=MEM_A_DQ<2>
=MEM_A_DQ<3>

=MEM_A_DQ<8>
=MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_P<2>

=MEM_A_DQ<24>
=MEM_A_DQ<25>

=MEM_A_DQ<19>

=MEM_A_DQ<26>

MEM_A_CKE<2>

MEM_A_A<5>

MEM_A_CLK_P<2>

MEM_A_A<1>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<48>

=MEM_A_DQS_P<6>

=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<56>
=MEM_A_DQ<57>

=MEM_A_DQ<58>
=MEM_A_DQ<59>

=PP3V3_S0_MEM_A_SPD

=PPDDRVTT_S0_MEM_A

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

MEM_RESET_L

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

MEM_A_CLK_N<2> MEM_A_CLK_N<3>

MEM_A_RAS_L

MEM_A_WE_L MEM_A_CS_L<2>
MEM_A_CAS_L

MEM_A_CS_L<3>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

MEM_EVENT_L

=MEM_A_DQ<27>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<0>

MEM_DIMM1_SA<1>

MEM_DIMM1_SA<1>

MEM_DIMM1_SA<0>

MEM_DIMM1_SA<0>

MEM_A_A<10>

=PPDDRVTT_S0_MEM_A

PPVREF_S3_MEM_VREFCA

PPVREF_S3_MEM_VREFDQ_A

SYNC_DATE=10/30/2013SYNC_MASTER=J78_NAT

DRAM: SO-DIMM Connector A Slot1

209

208

207

206

205

J2400

SODIMM-P0.60-D8

F-ANG-SM-1

113

204203

196195

190189

185

184

179

178

173

172

168167

162161

156155

151

150

145

144

139

138

134133

128127

7271

6665

61

60

55

54

49

48

4443

3837

3231

2625

2019

1413

9

8

3

21

126

199

124123

118117

112111

106105

10099

9493

8887

8281

7675

125

200
202201

197

121

114

30

110

120

116

122

77

198

186
188

169
171

152
154

135
137

62
64

45
47

27
29

10
12

194

192

182

180

193

191

183

181

176

174

166

164

177

175

165

163

160

158

148

146

159

157

149

147

142

140

132

130

143

141

131

129

70

68

58

56

69

67

59

57

52

50

42

40

53

51

41

39

36

34

24

22

35

33

23

21

18

16

6

4

17

15

7

5

187

170

153

136

63

46

28

11

7473

104

102

103

101

115

79

108

109

78
80

119

83 84

107

85

89

86

90

91 92

95 96
97 98

J2400

F-ANG-SM-1

SODIMM-P0.60-D8

CRITICAL

25 21

2

1

C2450

10V

1UF

402

X5R

10%

2

1

C2451

402

10V

1UF

X5R

10%

2

1

1UF

402

10V
X5R

10%

C2452

2

1

C2453

402

1UF

10V
X5R

10%

2

1

CERM
402

20%
10V

0.1UF

C2423

2

1

C2422

CERM
402

20%
10V

0.1UF

2

1

C2421

CERM
402

20%
10V

0.1UF

2

1

C2420

10V
CERM
402

0.1UF

20%

2

1

C2419

402

20%
10V
CERM

0.1UF

2

1

C2418

20%
10V

402

CERM

0.1UF

2

1

C2417

402

CERM

10V

20%

0.1UF

2

1

C2416

CERM
402

20%
10V

0.1UF

2

1

C2415

10V

20%

402

CERM

0.1UF

2

1

C2414

10V

20%

402

CERM

0.1UF

2

1

C2413

10V

20%

402

CERM

0.1UF

2

1

C2412

10V

20%

402

CERM

0.1UF

2

1

C2411

10V

20%

402

CERM

0.1UF

2

1

C2410

10V

20%

402

CERM

0.1UF

2

1

C2401

10UF

20%

6.3V
603

X5R

2

1

C2400

10UF

20%

6.3V
603

X5R

2

1

C2440

2.2UF

CERM
402-LF

20%

6.3V

2

1

R2440

402

5%
MF-LF

10K

1/16W

2

1

R2441

1/16W

5%

402

MF-LF

10K

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

7

21 7

21 7

21 7

21 7

21 7

7

7

21 7

21 7

21 7

21 7

21 7

21 7

21 7

7

47 21

47

21

45 44 24 23 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

2

1

C2435

20%

2.2UF

CERM

6.3V
402-LF

2

1

C2436

10V

20%

402

CERM

0.1UF

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

7

25 21

25 21

25 21

25 21

25 21

7

7

21 7

21 7

7

7

21 7

21 7

21 7

21 7

21 7

21 7

21 7

21 7

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

25 21

24 23 21 12

25 21

25 21

25 21

25 21

25 21

25 21

25 21

7

25 21

25 21

2

1

C2430

20%

402-LF

2.2UF

CERM

6.3V

2

1

C2431

10V

20%
CERM

402

0.1UF

25 21

25 21

89 22 21

89 22 21

89 22 21

89 22 21

89 22 21

89 22 21

22

22

22

22

89 22 21

24 23 21 20

21 20

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

BI

NC

NC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI BI

BI

www.laptoprepairsecrets.com

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Page Notes

Power aliases required by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

(NONE)

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V5_S0_MEM_B

- =PPDDRVTT_S0_MEM_B

- =PPVDDQ_S3_MEM_B

P/N: 516S1019

23 OF 93

VOLTAGE=0.675V

25 OF 121

0.24.0

051-00673

=PPDDRVTT_S0_MEM_B

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFCA

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

MEM_DIMM2_SA<1>

=MEM_B_DQ<0>

=MEM_B_DQ<16>

=MEM_B_DQ<18>

=MEM_B_DQ<27>

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<4>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_CS_L<0>MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CLK_N<1>MEM_B_CLK_N<0>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<2>

MEM_RESET_L

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

=PPVDDQ_S3_MEM_B

MEM_B_BA<2>

MEM_B_A<12>
MEM_B_A<9>

MEM_B_A<8>

=PPDDRVTT_S0_MEM_B

=PP3V3_S0_MEM_B_SPD

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50>
=MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42>
=MEM_B_DQ<43>

=MEM_B_DQ<40>
=MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32>
=MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_CKE<0>

=MEM_B_DQ<26>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<17>

=MEM_B_DQ<10>
=MEM_B_DQ<11>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62>
=MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQ<53>

=MEM_B_DQ<60>
=MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<47>

=PPVDDQ_S3_MEM_B

=MEM_B_DQ<36>
=MEM_B_DQ<37>

=MEM_B_DQ<38>
=MEM_B_DQ<39>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<6>
MEM_B_A<4>

MEM_B_A<11>
MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<13>

=MEM_B_DQ<14>
=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<1>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<4>
=MEM_B_DQ<5>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_A<10>
MEM_B_BA<0>

MEM_B_A<13>

=PP3V3_S0_MEM_B_SPD

=PP3V3_S0_MEM_B_SPD

SYNC_DATE=10/30/2013SYNC_MASTER=J78_NAT

DRAM: SO-DIMM CONNECTOR B SLOT0

24 7

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

47

24

25 24

25 24

24 22 21 12

25 24

25 24

25 24

25 24

25 24

10%
X5R

1UF

402

10V

C2550

1

2

25 24

25 24

25 24

25 24

6.3V

20%

402-LF

CERM

2.2UF

C2540

1

2

1/16W

5%

402

MF-LF

10K

R2540

1

2

1/16W

5%
MF-LF

10K

402

R2541

1

2

25 24

10%
X5R

402

10V

1UF

C2551

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

402

10%
X5R

1UF

10V

C2552

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

7

24 7

24 7

24 7

24 7

24 7

45 44 24 22 21

6.3V

2.2UF

CERM
402-LF

20%

C2535

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

C2536

CERM

0.1UF

20%

402

10V

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

25 24

F-ANG-SM-1

SODIMM-P0.60-D8

J2500

205

206

207

208

209

CRITICAL

SODIMM-P0.60-D8

F-ANG-SM-1

J2500

9897

9695

9291

90

86

89

85

107

8483

119

80

78

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

15
17

4
6

16
18

21
23

33
35

22
24

34
36

39
41

51
53

40
42

50
52

57
59

67
69

56
58

68
70

129
131

141
143

130
132

140
142

147
149

157
159

146
148

158
160

163
165

175
177

164
166

174
176

181
183

191
193

180
182

192
194

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

81 82

87 88

93 94

99 100

105 106

111 112

117 118

123 124

199

126

1 2
3

8

9

13 14

19 20

25 26

31 32

37 38

43 44

48

49

54

55

60

61

65 66

71 72

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

X5R
603

6.3V

10UF

20%

C2500

1

2

X5R
603

6.3V

20%

10UF

C2501

1

2

0.1UF

CERM
402

20%
10V

C2518

1

2

25 24

0.1UF

10V
402

CERM

20%

C2510

1

2

0.1UF

CERM
402

20%
10V

C2511

1

2

0.1UF

10V

20%

402

CERM

C2512

1

2

0.1UF

10V
CERM

20%

402

C2519

1

2

0.1UF

CERM
402

10V

20%

C2520

1

2

0.1UF

10V
CERM
402

20%

C2521

1

2

0.1UF

10V

20%

402

CERM

C2522

1

2

0.1UF

10V
CERM
402

20%

C2513

1

2

0.1UF

CERM
402

20%
10V

C2514

1

2

0.1UF

10V
402

CERM

20%

C2515

1

2

7

0.1UF

20%
CERM

402

10V

C2516

1

2

0.1UF

10V

20%

402

CERM

C2523

1

2

7

7

24 7

24 7

24 7

24 7

0.1UF

CERM

10V
402

20%

C2517

1

2

7

24 7

24 7

24 7

7

25 24

25 24

25 24

25 24

25 24

7

25 24

C2530

6.3V

20%
CERM

402-LF

2.2UF

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

24 7

20%

0.1UF

10V
402

CERM

C2531

1

2

25 24

25 24

25 24

25 24

25 24

25 24

25 24

24 7

7

7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

7

47

24

10%
X5R

10V
402

1UF

C2553

1

2

89 24 23

24 20

24 22 21 20

23

23

23

23

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NC

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

NC

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

www.laptoprepairsecrets.com

Page Notes

Signal aliases required by this page:

Power aliases required by this page:

- =PP1V5_S0_MEM_B

(NONE)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =I2C_SODIMMA_SCL

- =PPVDDQ_S3_MEM_B

- =PPDDRVTT_S0_MEM_B

P/N: 516S1019

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

24 OF 93

VOLTAGE=0.675V

26 OF 121

0.24.0

051-00673

=MEM_B_DQ<0>

=MEM_B_DQ<16>

=MEM_B_DQ<18>

=MEM_B_DQ<27>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<4>

MEM_B_CS_L<3>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_CLK_N<2>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<1>

MEM_B_BA<2>

MEM_B_A<12>
MEM_B_A<9>

MEM_B_A<8>

=PPDDRVTT_S0_MEM_B

=PP3V3_S0_MEM_B_SPD

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50>
=MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42>
=MEM_B_DQ<43>

=MEM_B_DQ<40>
=MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32>
=MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<2>

MEM_B_A<5>

MEM_B_CKE<2>

=MEM_B_DQ<26>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<17>

=MEM_B_DQ<10>
=MEM_B_DQ<11>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<1>

MEM_B_A<3>

MEM_B_A<10>
MEM_B_BA<0>

MEM_B_A<13>

=MEM_B_DQ<54>
=MEM_B_DQ<55>

=MEM_B_DQS_P<0>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<6>
=MEM_B_DQ<7>

=MEM_B_DQ<12>

=MEM_B_DQ<20>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

=MEM_B_DQ<13>

=MEM_B_DQ<21>

=MEM_B_DQ<22>
=MEM_B_DQ<23>

=MEM_B_DQ<28>
=MEM_B_DQ<29>

=MEM_B_DQS_P<3>

=MEM_B_DQ<30>

=PPVDDQ_S3_MEM_B

MEM_B_CKE<3>

MEM_B_A<15>
MEM_B_A<14>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<2>
MEM_B_A<0>

MEM_B_CLK_P<3>

MEM_B_ODT<3>

MEM_B_ODT<2>

MEM_B_BA<1>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<47>

=MEM_B_DQ<44>

=MEM_B_DQ<46>

=MEM_B_DQS_P<5>

=MEM_B_DQ<45>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<53>

=MEM_B_DQS_P<7>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

=MEM_B_DQ<31>

=MEM_B_DQS_N<0>

MEM_RESET_L

=MEM_B_DQS_N<3>

MEM_B_CLK_N<3>

MEM_B_RAS_L

MEM_B_CS_L<2>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<7>

MEM_EVENT_L

=PP3V3_S0_MEM_B_SPD

=PP3V3_S0_MEM_B_SPD

=PPVDDQ_S3_MEM_B

MEM_DIMM3_SA<1>

MEM_DIMM3_SA<1>

MEM_DIMM3_SA<0>

MEM_DIMM3_SA<0>

PPVREF_S3_MEM_VREFCA

=MEM_B_DQ<52>

=PPDDRVTT_S0_MEM_B

PPVREF_S3_MEM_VREFDQ_B

SYNC_MASTER=J78_NAT SYNC_DATE=10/30/2013

DRAM: SO-DIMM CONNECTOR B SLOT1

23 7

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

47

23

25 23

25 23

23 22 21 12

25 23

25 23

25 23

25 23

25 23

402

10V

1UF

X5R

10%

C2650

1

2

25 23

25 23

25 23

25 23

CERM
402-LF

20%

2.2UF

6.3V

C2640

1

2

1/16W

5%

402

MF-LF

10K

R2640

1

2

1/16W

5%

402

MF-LF

10K

R2641

1

2

25 23

1UF

402

10V
X5R

10%

C2651

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

1UF

402

10V
X5R

10%

C2652

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

7

23 7

23 7

23 7

23 7

23 7

45 44 23 22 21

2.2UF

CERM
402-LF

20%

6.3V

C2635

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

CERM
402

20%
10V

0.1UF

C2636

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

25 23

F-ANG-SM-1

SODIMM-P0.60-D8

J2600

205

206

207

208

209

SODIMM-P0.60-D8

F-ANG-SM-1

CRITICAL

J2600

9897

9695

9291

90

86

89

85

107

8483

119

80

78

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

15
17

4
6

16
18

21
23

33
35

22
24

34
36

39
41

51
53

40
42

50
52

57
59

67
69

56
58

68
70

129
131

141
143

130
132

140
142

147
149

157
159

146
148

158
160

163
165

175
177

164
166

174
176

181
183

191
193

180
182

192
194

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

81 82

87 88

93 94

99 100

105 106

111 112

117 118

123 124

199

126

1 2
3

8

9

13 14

19 20

25 26

31 32

37 38

43 44

48

49

54

55

60

61

65 66

71 72

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

20%

10UF

6.3V
603

X5R

C2600

1

2

10UF

20%

6.3V
603

X5R

C2601

1

2

10V

20%

402

CERM

0.1UF

C2618

1

2

25 23

10V

20%

402

CERM

0.1UF

C2610

1

2

10V

20%

402

CERM

C2611

1

2

0.1UF

10V

20%

402

CERM

0.1UF

C2612

1

2

CERM
402

20%
10V

0.1UF

C2619

1

2

CERM
402

10V

20%

0.1UF

C2620

1

2

402

20%
10V
CERM

0.1UF

C2621

1

2

CERM
402

20%
10V

0.1UF

C2622

1

2

CERM
402

20%
10V

0.1UF

C2613

1

2

CERM
402

20%
10V

0.1UF

C2614

1

2

CERM
402

20%
10V

0.1UF

C2615

1

2

7

CERM
402

20%
10V

0.1UF

C2616

1

2

CERM
402

20%
10V

0.1UF

C2623

1

2

7

7

23 7

23 7

23 7

23 7

CERM
402

20%
10V

0.1UF

C2617

1

2

7

23 7

23 7

23 7

7

25 23

25 23

25 23

25 23

25 23

7

25 23

2.2UF

20%
CERM

402-LF

6.3V

C2630

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

23 7

20%
10V
CERM
402

0.1UF

C2631

1

2

25 23

25 23

25 23

25 23

25 23

25 23

25 23

23 7

7

7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

7

47

23

10%

1UF

402

10V
X5R

C2653

1

2

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

89 24 23

24

24

24

24

23 22 21 20

89 24 23

23 20

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

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IN

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OUT

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NC

MTG HOLE

SYM 2 OF 2

SYM 1 OF 2

KEY

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

DQ1

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ11

DQ10

DQ17

DQS2
VSS_17

DQ24
DQ25

DQ19
VSS_19

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VTT_0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

DQ27
VSS_24

VSS_21

DQ18

VSS_14

DQ16

VSS_12

DM0

VSS_3

VSS_1

VREFDQ

DQ0

NC

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

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IN

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IN

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IN

www.laptoprepairsecrets.com

THERE ARE NO PIN SWAPS

25 OF 93

27 OF 121

0.24.0

051-00673

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>

=MEM_A_DQ<3>

=MEM_A_DQ<4>

=MEM_A_DQ<5>

=MEM_A_DQ<6>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQ<14>

=MEM_A_DQ<15>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<23>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<26>

=MEM_A_DQ<27>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQ<32>

=MEM_A_DQ<33>

=MEM_A_DQ<34>

=MEM_A_DQ<35>

=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<42>

=MEM_A_DQ<43>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQ<50>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_A_DQ<53>

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<58>

=MEM_A_DQ<59>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<0>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<3>

=MEM_A_DQS_P<4>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<6>

=MEM_A_DQS_P<7>

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<8>

=MEM_B_DQ<9>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<12>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<16>

=MEM_B_DQ<17>

=MEM_B_DQ<18>

=MEM_B_DQ<19>

=MEM_B_DQ<20>

=MEM_B_DQ<21>

=MEM_B_DQ<22>

=MEM_B_DQ<23>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<26>

=MEM_B_DQ<27>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQ<32>

=MEM_B_DQ<33>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

=MEM_B_DQ<40>

=MEM_B_DQ<41>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQ<46>

=MEM_B_DQ<47>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<58>

=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQ<62>

=MEM_B_DQ<63>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<4>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<0>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<3>

=MEM_B_DQS_P<4>

=MEM_B_DQS_P<5>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<7>

MEM_A_DQ<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MEM_A_DQ<3>

MAKE_BASE=TRUE

MEM_A_DQ<4>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MEM_A_DQ<8>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<9>

MEM_A_DQ<10>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<11>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<18>

MEM_A_DQ<19>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<25>

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<28>

MEM_A_DQ<29>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<30>

MEM_A_DQ<31>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<32>

MEM_A_DQ<33>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<34>

MEM_A_DQ<35>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<36>

MEM_A_DQ<37>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQ<47>

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MAKE_BASE=TRUE

MEM_A_DQ<50>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<51>

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<55>

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MEM_A_DQ<63>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<5>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_B_DQ<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<10>

MEM_B_DQ<11>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<12>

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQ<15>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<16>

MEM_B_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<19>

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<22>

MEM_B_DQ<23>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<24>

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<30>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<32>

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MEM_B_DQ<41>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<42>

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<47>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MEM_B_DQ<50>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<51>

MEM_B_DQ<52>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<53>

MEM_B_DQ<54>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<55>

MAKE_BASE=TRUE

MEM_B_DQ<56>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MEM_B_DQ<58>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<59>

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

=MEM_B_DQ<34>

SYNC_DATE=04/29/2013SYNC_MASTER=J16_IG

DRAM: ALIASES AND BITSWAPS

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24 23

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com

6 - PCIE_RST_2_N

0 - GPIO_13

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

7 - PCIE_RST_3_N

If strap != bit then security is enabled?

Used for straps in host mode

DEBUG: For monitoring current/voltage

SNK0 AC Coupling

SNK1 AC Coupling

(TBT_SPI_MISO)(TBT_SPI_MOSI)

(TBT_SPI_CLK)

depends on the code in the flash.

bit in the flash, so the active-level

Security strap setting is XORed with

(TBT_SPI_CS_L)

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

8 - GPIO_15
9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

11 - GPIO_0

5 - PCIE_RST_1_N

3 - GPIO_3

2 - GPIO_2

4 - GPIO_5

1 - GPIO_1

10 - GPIO_14

13 - GPIO_10

12 - GPIO_12

NOTE: The following pins require testpoints:

26 OF 93

28 OF 121

0.24.0

051-00673

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

TBT_CLK25M_IN

TBT_GPIO7

TBT_GPIO2

TBT_TMU_CLK_OUT

TBT_CLK25M_IN

TBT_CLK25M_OUT

TBT_CLK25M_OUTTBT_CLK25M_R

HDMITBTMUX_SEL_TBT

TBT_B_CONFIG2_BUF

TBT_WAKE_L

=TBT_BATLOW_L
TBTDP_AUXIO_EN

TP_TBT_THERM_DP

JTAG_TBT_TCK
JTAG_TBT_TDO

TBT_PCIE_RESET_L

JTAG_TBT_TDI
JTAG_TBT_TMS

PP3V3_TBTLC

=PP3V3_S4_TBT

TBTDP_AUXIO_EN

=TBT_BATLOW_L

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK1_AUX_C_N

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK0_AUX_C_N

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<3>

PP3V3_TBTLC

PCIE_TBT_R2D_C_N<0>

=PP3V3_S4_TBT

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CP<2>

TP_TBT_MONDC1

TP_TBT_MONDC0

TBTROM_WP_L

TBTROM_HOLD_L

TBT_TEST_PWR_GOOD

TBT_TEST_EN

TBT_SPI_MISO

TBT_RSENSE

TBT_PWR_ON_POC_RST_L

TBT_MONOBSP
TBT_MONOBSN

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR_L

TBT_DDC_XBAR_EN_L

TBT_DDC_XBAR_EN_L

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_N<0> TBT_B_HV_EN

TBT_B_HV_EN

TBT_B_DP_PWRDN

TBT_B_DP_PWRDN

TBT_B_D2R_P<1>

TBT_B_CIO_SEL

TBT_A_R2D_C_N<0>

TBT_A_HV_EN

TBT_A_DP_PWRDN

TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

PCIE_TBT_R2D_P<3>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_N<0>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_N<0>

DP_TBTSRC_HPD

DP_TBTSNK1_AUX_P

DP_TBTSNK1_AUX_P

DP_TBTSNK1_AUX_N

DP_TBTSNK1_AUX_N

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_AUX_P

DP_TBTSNK0_AUX_P
DP_TBTSNK0_AUX_N

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_HPD

DP_TBTPB_ML_C_P<3>
DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_HPD

DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_N<2>

DP_TBTPB_ML_C_P<1>

TBT_B_LSRX

HDMITBTMUX_SEL_TBT

TBT_B_CONFIG1_BUF

TBT_B_LSTX

DP_TBTSRC_HPD

TBT_B_D2R_N<0>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUX_C_P

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_ML_P<1>

TBT_PWR_EN

TBT_CIO_PLUG_EVENT_L

TBT_SPI_CLK

DP_TBTSNK1_AUX_C_P

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

TBT_DFT_STRAP_3

TBT_ROM_SECURITY_XOR

TBT_DFT_STRAP_1

PCIE_TBT_D2R_C_N<3>

TBT_RBIAS

TP_TBT_PCIE_RESET0_L

PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>

TBT_SPI_MOSI

PP3V3_TBTLC

DP_TBTSNK0_ML_P<0>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_AUX_N

TBT_B_D2R_P<0>

TBT_B_D2R_N<1>

TBT_A_HV_EN
TBT_A_CIO_SEL
TBT_A_DP_PWRDN

TBT_B_R2D_C_P<1>

DP_TBTSNK0_ML_P<2>
DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<1>
DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<0>

TP_DP_TBTSRC_ML_CP<3>

TP_DP_TBTSRC_ML_CP<1>
TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<2>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CN<2>

PP3V3_TBTLC

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

TBT_A_LSRX

TBT_A_LSTX

TBT_A_D2R_N<1>

TBT_A_D2R_P<1>

TBT_A_CONFIG2_BUF

TBT_A_CONFIG1_BUF

TBT_A_R2D_C_P<1>
TBT_A_R2D_C_N<1>

DP_TBTSNK1_ML_N<3>

TBT_SPI_CS_L

TBT/DP: Host (1 of 2)

SYNC_DATE=11/06/2014SYNC_MASTER=BRANCH_JERRYCHOW

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

21

C2847

10% 16V

0.1UF

X5R-CERM 0201

21

C2846

10% 16V

0.1UF

X5R-CERM 0201

21

C2844

16V10%

0.1UF

X5R-CERM 0201

21

C2845

16V10% X5R-CERM

0.1UF

0201

21

C2843

16V10% X5R-CERM

0.1UF

0201

2

1

R2891

MF

1/20W

201

3.3K

5%

21

C2842

16V10% X5R-CERM

0.1UF

0201

21

C2841

16V10% X5R-CERM

0.1UF

0201

21

C2840

16V10% X5R-CERM

0.1UF

0201

21

C2807

020110%

0.1UF

16V
X5R-CERM

21

C2806

020110%

0.1UF

16V
X5R-CERM

21

C2805

0201

0.1UF

10%

16V
X5R-CERM

21

C2804

0.1UF

10% X5R-CERM 0201

16V

2

1

R2892

MF

1/20W

201

3.3K

5%

21

C2803

10%

16V

0.1UF

X5R-CERM 0201

21

C2802

020110%

0.1UF

16V
X5R-CERM

21

C2800

020110%

0.1UF

16V
X5R-CERM

21

C2801

0.1UF

020110%

16V
X5R-CERM

2

1

R2851

201

1M

MF

1/20W

5%

21

R2850

0201

0

5%

1/20W

MF

21

C2850

0201

12PF

5%

25V

NP0-C0G

21

C2851

0201

5%

25V

NP0-C0G

12PF

3 1

4 2

Y2850

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

J4

L22

J24

L24

K5

U2

E16

P1

AB23

AA24

AA4

AB1

AB7

W8

R6

U6

W2

AA6

AD1

U20

AB21
AD21

W20

R4

AD17

AD9

AD5

AD19

AD11

AD7

P5

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

V3

M5
P7

N6

A22
B23

A20
B21

M1

D3

W24
U24

W22
U22

R24
N24

R22
N22

K3
K1

N8

J6

M3

A18
B19

A16
B17

J22

G24

E24

G22

E22

L4
L2

W18
W16

AC24

AD23

V1

AD3

AB3

T3

T1

F3P3

R2N2

M7

V7

T7

Y1

Y7

H5

L6

F1R8

Y3

AA2

T5

U8

AC2

J2

A14
B15

A12
B13

A10
B11

A8
B9

U4

H3
H1

E6
D5

E8
D7

E10

D9

E12
D11

AB5

G4
G2

E14
D13

D15

E18
D17

E20
D19

U2800

FALCON_RIDGE_1_FCBGA_FALCON

CRITICAL

OMIT_TABLE

FCBGA

FALCON RIDGE

W6

L8

AD15

AD13

2

1

R2832

1%

MF

1/20W

201

200K

1/20W

100K

R2879

2

5%

1

201

MF

2

5%

1

R2878

201

1/20W

MF

100K

2

1

R2882

MF

1/20W

201

5%

100K

2

1

R2884

5%

100K

MF

1/20W

201

2

1

R2829

10K

201

1/20W

MF

5%

2

1

R2881

MF

1/20W

201

5%

100K

2

1

R2862

MF

1/20W

201

10K

5%

2

1

R2867

MF

1/20W

201

10K

5%

NO STUFF

2

1

R2863

MF

1/20W

201

10K

5%

2

1

R2861

5%

10K

201

1/20W
MF

30 29 26

31 26

3

8

9

7

4

25

1

6

U2890

4MBIT

USON

W25X40CLXIG

OMIT_TABLE

CRITICAL

2

1

R2883

5%

201

1/20W
MF

100K

19

31 26

19

2

1

R2880

100K

MF

1/20W

201

5%

2

1

R2885

NO STUFF

5%

10K

201

1/20W

MF

2

1

R2886

NO STUFF

5%

201

1/20W
MF

10K

2

1

R2887

10K

201

MF

1/20W

5%

2

1

R2888

5%

10K

201

1/20W

MF

2

1

R2815

NONE

NOSTUFF

NONE
NONE

OMIT

0201

27

11

11

NO STUFF

2

1

R2899

MF

5%

1/20W

10K

201

11

19

27 26

30 26

30

30 26

29 26

29

29 26

29

29

29

29

29

19

19

19

19

30

30

30

30

30

30

30

19

30

30

29

29

79

79

2

1

C2890

BYPASS=U2890::2mm

1UF

10%

6.3V
CERM

402

79

79

79

79

79

79

79

79

21

C2839

0201

X5R-CERM

0.1UF

16V10%

21

C2838

0201

0.1UF

X5R-CERM

16V10%

21

C2837

10% 0201

0.1UF

X5R-CERM

16V

21

C2836

X5R-CERM

0201

0.1UF

16V10%

21

C2835

X5R-CERM

0.1UF

020116V10%

21

C2834

0.1UF

0201

X5R-CERM

16V10%

21

C2833

0201

0.1UF

X5R-CERM

16V10%

21

C2832

0.1UF

X5R-CERM

16V10% 0201

21

C2831

0201

0.1UF

X5R-CERM

16V10%

21

C2830

0201

0.1UF

X5R-CERM

16V10%

21

C2820

0201

0.1UF

X5R-CERM

16V10%

21

C2821

0201

0.1UF

X5R-CERM

16V10%

2

1

R2855

1%

1K

201

MF

1/20W

21

C2822

0201

X5R-CERM

10% 16V

0.1UF

21

C2823

0201

0.1UF

X5R-CERM

16V10%

21

C2824

0201

X5R-CERM

0.1UF

10% 16V

21

C2825

0201

0.1UF

X5R-CERM

16V10%

21

C2826

0201

0.1UF

X5R-CERM

10% 16V

21

C2827

0201

0.1UF

X5R-CERM

16V10%

21

C2828

0201

0.1UF

X5R-CERM

10% 16V

79

79

79

79

79

79

79

79

79

79

21

C2829

0.1UF

16V10% 0201

X5R-CERM

2

1

R2893

MF

1/20W

201

3.3K

5%

29

29

2

1

R2831

MF

1/20W

201

100K

5%

2

1

R2830

MF

1/20W

201

100K

5%

30

30

30

30

30

30

31

30

30

30

29

29

29

29

29

29

29

29

29

31

2

1

R2825

100

5%

MF

1/20W

201

80

80

2

1

R2890

MF

1/20W

201

3.3K

5%

26

26

26

26

26

89 27 26

89 72 31 30 29 27 26 19

30 29 26

31 26

89 27 26

89 72 31 30 29 27 26 19

41

41

91

27 26

31 26

30 26

30 26

29 26

29 26

41 26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

41 26

26

26

91

89 27 26

26

26

26

26

26

26

26

26

26

41

41

41

41

41

41

26

26

41

41

89 27 26

26

26

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

NC

NC

DISPLAY PORT

PORTS

SYM 1 OF 2

PCIE GEN2

MISC

PERP_3

PERN_0

TMS

TDI

PERST_OD_N

GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_AUX_P

PA_DPSRC_HPD

PA_CIO1_RX_P

PA_DPSRC_1_P

PA_DPSRC_3_P

PA_CIO0_TX_P/DPSRC_0_P

PA_CIO1_TX_P/DPSRC_2_P

PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE

PA_CIO0_RX_P

DPSNK1_0_P

DPSNK1_AUX_P

DPSNK1_HPD

DPSNK1_2_P

DPSNK1_3_P

DPSNK0_AUX_P

DPSNK0_HPD

DPSNK0_0_P

DPSNK0_1_P

DPSNK0_2_P

DPSNK0_3_P

EE_CS_N

TEST_PWR_GOOD

TEST_EN

TDO

TCK

EE_CLK

EE_DO

MONOBSP
MONOBSN

THERMDA

EE_DI

MONDC0
MONDC1

PWR_ON_POC_RSTN

PERN_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0

PB_AUX_P

PB_LSRX/CIO_3_LSOE

PB_LSTX/CIO_3_LSEO

PB_DPSRC_HPD

PB_DPSRC_3_P

PB_DPSRC_1_P

PB_CIO3_RX_P

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_11/PB_CIO_SEL/BYP1

GPIO_1/PB_HV_EN/BYP0

GPIO_14
GPIO_15

PB_CONFIG2/CIO_2_LSOE

PB_CONFIG1/CIO_2_LSEO

PB_CIO3_TX_P/DPSRC_2_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO2_RX_P

GPIO_9/SX_CTRL_OD*

GPIO_7_OD/CIO_SCL_OD

GPIO_6_OD/CIO_SDA_OD

GPIO_4/WAKE_OD_N

GPIO_3/FORCE_PWR

DPSRC_0_P

DPSRC_1_P

DPSRC_3_P

DPSRC_2_P

DPSRC_HPD_OD

GPIO_2/TMU_CLK_IN/AC_PRESENT

TMU_CLK_OUT

XTAL_25_IN

GPIO_17
GPIO_18
GPIO_19

RSVD_GND

GPIO_16/DEVICE_PCIE_RST_N

REFCLK_100_IN_P

PCIE_CLKREQ_OD_N

RBIAS

PETN_3

PETP_3

PETN_2

RSENSE

PETP_2

PETN_1

PETP_1

PETP_0
PETN_0

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

DPSNK0_0_N

DPSNK0_1_N

DPSNK0_2_N

DPSNK0_3_N

DPSNK0_AUX_N

DPSNK1_0_N

DPSNK1_2_N

DPSNK1_3_N

DPSNK1_AUX_N

DPSRC_0_N

DPSRC_1_N

DPSRC_2_N

DPSRC_3_N

GPIO_8/EN_CIO_PWR_N_OD

PA_AUX_N

PA_CIO0_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO1_RX_N

PA_CIO1_TX_N/DPSRC_2_N

PA_DPSRC_1_N

PA_DPSRC_3_N

PB_AUX_N

PB_CIO2_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO3_RX_N

PB_CIO3_TX_N/DPSRC_2_N

PB_DPSRC_1_N

PB_DPSRC_3_N

REFCLK_100_IN_N

XTAL_25_OUT

DPSRC_AUX_P
DPSRC_AUX_N

DPSNK1_1_N

DPSNK1_1_P

OUT

IN

DI/IO0

HOLD*

WP*

CLK

CS*

THRM_PADGND

DO/IO1

VCC

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

IN

IN

IN

IN

BI

BI

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

www.laptoprepairsecrets.com

U2940

TPS22920

Load Switch

1200 mA EDP

Push-pull output

Isolated to reduce noise from SVR

Part

Type

R(on)

@ 1.05V

Max Current = 4A (85C)

8 mOhm Typ

11.5 mOhm Max

1.05V TBT "CIO" Switch

25 mA EDP

1900 mA EDP

Internal switch not functional on RR.

Delay = 4.04ms nominal

TBT "POC" Power-up Reset

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

Vth = 2.508V nominal

SVR input to RR - 1100 mA EDP

100 mA EDP

EDP: 1.25 A

2.4 W (Single-Port)

3.1 W (Dual-Port)

Pull-up (S0) on PCH page

POC input to RR - 150 mA EDP

700 mA EDP

27 OF 93

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.5000

DIDT=TRUE
SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.5000

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.3800

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1800

MIN_LINE_WIDTH=0.4000

29 OF 121

0.24.0

051-00673

PP1V05_TBT

TBT_PWR_ON_POC_RST_L

TBTPOCRST_SENSE

=PP3V3_S0_PCH_GPIO

TBT_POC_RESET_L

TBT_PWR_REQ_L

=PP3V3_S0_PCH_GPIO

TBT_EN_CIO_PWR_L

=PP3V3_S4_TBT

PP1V05_TBT

P1V05TBT_SW

PP1V05_TBTRDV

PP3V3_TBTRDV PP3V3_S4_TBT_F

TBTPOCRST_MR_L

TBTPOCRST_CT

TBT_EN_CIO_PWR

SMC_DELAYED_PWRGD

PP1V05_TBTCIO

PP3V3_TBTLC

=PP3V3_S4_TBT

PP3V3_TBTLC

SYNC_MASTER=BRANCH_JERRYCHOW SYNC_DATE=09/10/2014

TBT/DP: Host (2 of 2)

20%

1.0UF

X5R

6.3V

0201-1

C2930

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2931

1

2

0201-1

20%

1.0UF

X5R

6.3V

C2932

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2902

1

2

1.0UF

X5R

6.3V

20%

0201-1

C2901

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2900

1

2

0201-1

20%

1.0UF

X5R

6.3V

C2905

1

2

20%

6.3V
X5R

0201-1

1.0UF

C2904

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2921

1

2

10UF

20%

0402-1

CERM-X5R

6.3V

C2920

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2903

1

2

FALCON_RIDGE_1_FCBGA_FALCON

OMIT_TABLE

CRITICAL

FCBGA

FALCON RIDGE

U2800

B5

A4
A6
B3

J8

K9

L14
M15
M17

P17
V19

J10
J12
K11
L10
M11
N10
N14
P11
P15
R10
R14
T11
T15
U10
U14
V11

G10
G12
G14
G16
G18
H19

H9

J18

K15
K17
K19

K7

L16
M19

P19
T19

U18

V15

V17
W12
W14

D1
E2
H11
N4
V5
W4

Y5

H13
H15
H17
H7
L18
N18
R18
W10

A2

A24

AA14
AA20
AA22

AA8
AB11
AB17
AC10
AC12
AC14
AC16
AC18
AC20
AC22

AC4
AC6
AC8

B1

B7
C10
C12
C14
C16
C18

C2
C20
C22
C24

C4

C6

C8
D21
D23

E4

F11
F13
F15
F17
F19
F21
F23

F5

F7

F9

G20
G6
G8
H21
H23
J14
J16
J20
K13
K21
K23
L12
L20
M13
M21
M23
M9
N12
N16
N20
P13
P21
P23
P9
R12
R16
R20
T13
T17
T21
T23
T9
U12
U16
V13
V21
V23
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y9

SOT563

DMN5L06VK-7

Q2945

3

5

4

SOT563

DMN5L06VK-7

Q2945

6

2

1

330PF

X7R

10%
16V

0201

C2995

1

2

1/20W

100K

201

MF

5%

R2992

1

2

TPS3895ADRY

USON

CRITICAL

U2990

5

1

2

3

4

6

14 11

X7R-CERM

10%
50V

0.001UF

0402

C2991

1

2

DMN32D2LFB4

DFN1006H4-3

Q2995

3

1

2

100K

5%
1/20W
MF
201

R2990

1

2

73 45 44

MF

201

100K

1/20W

5%

R2995

1

2

13

X5R

10%

0.1UF

25V

402

C2990

1

2

1/20W
MF
201

24.9K

1%

R2991

1

2

26

SHORT_SM_BASE

PLACE_NEAR=C2961.1:1MM

OMIT

SM

XW2960

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2950

1

2

CERM-X5R

6.3V

0402-1

10UF

20%

C2951

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2952

1

2

20%

10UF

0402-1

CERM-X5R

6.3V

C2953

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2961

1

2

0201-1

6.3V
X5R

1.0UF

20%

C2960

1

2

26

1.0UF

6.3V
X5R

0201-1

20%

C2970

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2980

1

2

1.0UF

0201-1

20%

X5R

6.3V

C2981

1

2

20%

X5R

6.3V

0201-1

1.0UF

C2940

1

2

CRITICAL

CSP

TPS22920

U2940

D1

D2

A2

B2

C2

A1

B1

C1

100K

201

MF

1/20W

5%

R2945

1

2

NSR1020MW2T1G

SOD-323

CRITICAL

D2920

A

K

6.3V

CERM-X5R

0402-1

10UF

20%

C2923

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2922

1

2

DEFAULT_INDUCTOR_680.000000nH_2_1

SM

680NH-30%-3.6A-35MOHM

CRITICAL

L2920

1 2

X5R

6.3V

1.0UF

20%

0201-1

C2910

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2911

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2906

1

2

27

89 27

89 27

89 72 31 30 29 27 26 19

27

31

31

31

89 27 26

89 72 31 30 29 27 26 19

89 27 26

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SYM 2 OF 2

VCC

GND

SVR_IND

SVR_AMON

VSS

SVR_VCC1P0

VCC1P0_RDV_DECAP

VCC3P3

VCC3P3_LC

VCC3P3_RDV_DECAP

VSS

VCC1P0_CIO

DS

VER 5

G

GS

D

VER 3

VCC

CT

SENSE_OUTENABLE

SENSE

GND

OUT

GS

SYM_VER_3

D

IN

IN OUT

IN

VIN

ON

GND

VOUT

NC

www.laptoprepairsecrets.com

Page Notes

- =TBT_RESET_L

Power aliases required by this page:

- =PP15V_TBT_REG (15V Boost Output)

TBTBST:Y - Stuffs 15V boost circuitry.

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP1V05_TBT_FET (1.05V FET Output)

Signal aliases required by this page:

- =TBT_CLKREQ_L

BOM options provided by this page:

28 OF 93

051-00673

0.24.0

30 OF 121

SYNC_DATE=10/09/2013SYNC_MASTER=J78_JERRY

Thunderbolt: Power Support

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

www.laptoprepairsecrets.com