Apple A1398 Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK APPD

DATE

2012-05-09

SCHEM,MLB,KEPLER,2PHASE,D2

FSB, 5/9/2012

Date

SyncPage

03/05/2012

01/13/2012

03/16/2012

01/13/2012

03/05/2012

01/13/2012

03/05/2012

01/13/2012

03/05/2012

01/13/2012

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

91 92 93 94 95 96 97 98 99

(.csa)

102

PCH Constraints 1

103

PCH Constraints 2

105

Thunderbolt Constraints

106

SMC Constraints

107

GPU (Kepler) CONSTRAINTS

108

Project Specific Constraints

109

PCB Rule Definitions

130

DEBUG SENSORS AND ADC

132

SMC12 SENSORS EXTENDED

Contents

D2_KEPLER

D2_CLEAN

D2_KEPLER

D2_SEAN

D2_KEPLER

Date

SyncPage

01/13/2012

03/15/2012

01/13/2012

03/05/2012

01/13/2012

D

C

B

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

(.csa)

54

High Side and CPU/AXG Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

KEYBOARD/TRACKPAD (1 OF 2)

58

KEYBOARD/TRACKPAD (2 OF 2)

59

DIGITAL ACCELEROMETER & GYRO

61

SPI ROM

62

AUDIO: CODEC/REGULATOR

63

AUDIO: HEADPHONE FILTER

64

AUDIO: IV SENSE

65

AUDIO: IV SENSE FILTER

66

AUDIO: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1V5R1V35V DDR3 SUPPLY

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPU VCCIO (1V0R1V05 S0) POWER SUPPLY

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

80

KEPLER PCI-E

81

KEPLER CORE/FB POWER

82

KEPLER FRAME BUFFER I/F

83

1V05 GPU / 1V35 FB POWER SUPPLY

84

GDDR5 Frame Buffer A

85

GDDR5 Frame Buffer B

86

KEPLER EDP/DP/GPIO

87

KEPLER GPIOS,CLK & STRAPS

88

KEPLER PEX PWR/GNDS

89

GFX IMVP VCore Regulator

90

eDP Display Connector

91

eDP Mux

92

eDP Muxed Graphics Support

94

Thunderbolt Connector A

96

Thunderbolt Connector B

97

LCD Backlight Driver (LP8545)

98

PCH VCCIO (1.05V) POWER SUPPLY

99

Power Sequencing EG/PCH S0

100

CPU Constraints

101

Memory Constraints

Contents

D2_SEAN

D2_KEPLER

D2_CARA

D2_KEPLER

D2_SEAN

D2_KEPLER

D2_SEAN

D2_KEPLER

D2_SEAN

D2_KEPLER

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

42 43 44 45

(.csa)

1

1 2 3 4 5 6 7 8 9

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

6

BOM Variants

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU POWER AND GND

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIe/CLK/LPC/SPI

19

PCH DMI/FDI/PM/Graphics

20

PCH PCI/USB/TP/RSVD

21

PCH GPIO/MISC/NCTF

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

Chipset Support

27

USB HUB & MUX

28

CPU Memory S3 Support

29

DDR3 SDRAM Bank A (1 OF 2)

30

DDR3 SDRAM Bank A (2 OF 2)

31

DDR3 SDRAM Bank B (1 OF 2)

32

DDR3 SDRAM Bank B (2 OF 2)

33

DDR3 Termination

34

DDR3/FRAMEBUF VREF MARGINING

35

X29/ALS/CAMERA CONNECTOR

36

Thunderbolt Host (1 of 2)

37

Thunderbolt Host (2 of 2)

38

Thunderbolt Power Support

44

RIO CONNECTOR

45

SSD CONNECTOR

46

USB 3.0 CONNECTORS

49

SMC41

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Voltage & Load Side Current Sensing

Contents

D2_KEPLER

D2_SEAN

D2_KEPLER

D2_CLEAN

D2_KEPLER

D2_CLEAN

D2_KEPLER

D2_SEAN

D

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

C

B

TABLE_TABLEOFCONTENTS_ITEM

Date

SyncPage

01/13/2012

03/05/2012

01/13/2012

03/19/2012

01/13/2012

03/19/2012

01/13/2012

03/05/2012

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

A

Schematic / PCB #’s

PART NUMBER

051-9589

820-3332

DRAWING

TITLE=MLB ABBREV=ABBREV

LAST_MODIFIED=Wed May 9 13:50:52 2012

QTY

1

DESCRIPTION

SCHEM,MLB,KEPLER_2PHASE,D2

PCBF,MLB,KEPLER_2PHASE,D2

REFERENCE DES

SCH1

PCB

CRITICAL

BOM OPTION

SIZE

A

D

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

3

SCHEM,MLB,KEPLER,2PHASE,D2

Apple Inc.

R

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

SHEET

1245678

4.18.0

1 OF 132

1 OF 99

8 7 6 5 4 3

12

2 DIMMS

RTC

PG 16

J2500,J2550

XDP CONN

J2900

J3100

DIMM

PG 26,28

PG 23

J6950

DC/BATT

PG 63

U6100

U4900

POWER SUPPLY

D

U8000

AMD WHISTLER

GRAPHICS

PG 73

INTEL CPU

2.X GHZ

IVY BRIDGE

PG 9

DDR3-1067/1333MHZ

D

GPIO

PG 19

FDI

PG 17

DMI

PG 17

SPI

CLOCK

U2700

CK5G05

PG 24

J4501

SATA

ODD

CONN

PG 41

J4500

SATA

C

HDD

CONN

PG 41

CLK

BUFFER

PG 16

SATA2.0/3(GB/S)

4 5

SATA

SATA2.0/3(GB/S)

PG 16

SATA2.0/3(GB/S)

2 3

SATA3.0/6(GB/S)

10

SATA3.0/6(GB/S)

INTEL

PANTHER-POINT

MOBILE

U1800

Misc

PG 19

SPI

PG 16

J5100

LPC

PG 16

PWR

DP OUT

U9320

DP MUX

XP25-5G

PG 83

J9400

MINI DP PORT

PG 84

U9370

B

DDC MUX

PG 83

RGB OUT

HDMI OUT

DVI OUT

LVDS OUT

TMDS OUT

PG 18

PCI

PG 18

JTAG

PG 16

PEG

PG 16

PCI-E

(UP TO 16 LINES)

PG 16

CTRL

PG 17

PG 18

USB

(UP TO 14 DEVICES)

SMB

PG 16

HDA

PG 16

10 11 1312 98654 73210

LCD PANEL

Boot ROM

PG 55

LPC + SPI CONN Port80,serial

PG 46

U3600

USB

HUB 2

PG 33

U3700

USB

HUB 1

PG 34

DIMM

PG 26,28

Ser

BSBB,0

Prt

U4900

J3402

J4501

J4610

(RESERVATION)

J5713

TRACKPAD/KEYBOARD

J3401

J4600

CAMERA

IR

EXTERNAL B

EXTERNAL C

BLUETOOTH

EXTERNAL A

SMC

PG 44

Fan

ADC

PG 31

PG 41

PG 33

PG 53

PG 31

PG 34

TEMP SENSOR

PG 44

POWER SENSE

PG 44

J5650,5660

FAN CONN AND CONTROL

PG 51

SMBUS

CONNECTION

PG 47

C

B

U9600

GMUX

PG 86

U4100

A

J3401

FW643

PG 38

AirPort

J4310PG 31

FIREWIRE

CONN

PG 40

U3900

J4000

GB

E-NET

BCM57765

PG 36

E-NET

CONN

PG 37

J3500

SDCARD READER

CONN

PG 37

6 3

LINE TIN

FILTER

PG 57

U6201

J6700,J6750

AUDIO CODEC

PG 56

HEADPHONE

FILTER

PG 58

AUDIO

CONN

PG 60

U6610,6620,6630

SPEATKER

AMP

PG 59

SPEATKER

PG 63

SYNC_MASTER=D2_KEPLER

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

2 OF 132

SHEET

2 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

B

A

J6900

AC

ADAPTER

IN

J6950

3S2P

(9 TO 12.6V)

GMUX

U9600

XP25-5

(PAGE 86)

SMC

U4900

(PAGE 44)

PANTHER-POINT

MOBILE

SLP_S5#(E4)

U1800

SLP_S4#(H7)

SLP_S3#(P12)

(PAGE 16~21)

P60

DELAY

RC

DCIN(16.5V)

PB16B

PB17A

PB17B

PB18A

PL32A

SMC_PM_G2_EN

D2 POWER SYSTEM ARCHITECTURE

PP18V5_DCIN_CONN

F6905 6A FUSE

PPVBATT_G3H_CONN

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

PM_ALL_GPU_PGOOD

R7978

PM_SLP_S3_L_R

P1V8S0_EN

P1V2S0_EN

CPUVTTS0_EN

P1V5CPU_EN

RC

DELAY

PM_SLP_S5_L

RC

DELAY

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

P5VS3_EN

DDRREG_EN

P3V3S3_EN

R7020

SMC_DCIN_ISENSE

SMC_RESET_L

P1V1GPU_EN

P3V3GPU_EN

GPUVCORE_EN

P3V3S5_EN

A

VIN

Q7055

CHGR_BGATE

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

U7000

ISL6259HRTZ

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 64)

R6990

VOUT

PPVBAT_G3H_CHGR_R

P1V0GPU_EN

P1V5FB_EN

BKLT_PLT_RST_L

&&

LCD_BKLT_NO

SMC_ADAPTER_EN&&PM_SLP_S3_L

PPVBAT_G3H

R7050

SMC_BATT_ISENSE

Q9806

BKLT_EN

Q4260

D6990

VIN

ISL6263C

U8900

A

CPUIMVP7_VR_ON

ENABLE

3.425V G3HOT

VOUT

PGOOD

PM6640

U6990

(PAGE 62)

SMC_GPU_ISENSE

GPUVCORE_PGOOD

U5410

VIN

VR_ON

A

CPU VCORE

ISL95831

U7400

PP3V42_G3H

VOUT

PGOOD

SMC_GPU_VSENSE

V

PPVCORE_GPU

A

SMC_CPU_ISENSE

CPUIMVP7_AXG_PGOOD

V

A

PPBUS_G3H

F7040

8A FUSE

PPBUS_G3H

PP5V_S3_GFXIMVP6_VDD

SMC_PBUS_VSENSE

GPUVCORE_EN

SMC_CPU_HI_ISENSE

V

Q5315

VDD

GPU VCORE

VR_ON

(PAGE 82)

R5388/U5388

(PAGE 67)

www.qdzbwx.com

SMC_CPU_DDR_VSENSE

PP3V3_S0

PP1V5_S0

PP1V05_S0

U5440

Q7880

VIN

EN1

1.003V(L/H)

EN2

1.503V(R/H)

ISL6236

U9500

(PAGE 85)

ENA

VOUT1

VOUT2

POK1

POK2

P5VS3_EN

P3V3S5_EN

VIN

LP8550

U9701

(PAGE 87)

PFWBOOST

PP1V0_S0GPU_REG

R5413

A

P1V0GPU_PGOOD

P1V5FB_PGOOD

VOUT

PP1V5_GPU_REG

SMC_GPU_1V8_ISENSE

VIN

EN1

5V

(L/H)

3.3V

EN2

(R/H)

TPS51125

U7201

(PAGE 65)

PGOOD

P5V3V3_PGOOD

PPVOUT_S0_LCDBKLT

P1V5CPU_EN

VREG5

VOUT1

VOUT2

DDRREG_EN

DDRVTT_EN

PP5V_S3

PP3V3_S5

VIN

ON

SLG5AP020

U7801

PP5V_S3_DDRREG

S5

S3

PP1V5_S3

G

PP3V3_S5

Q7870

Q7810

Q7830

P1V8_S0_EN

VIN

1.5V

0.75V

TPS51116

U7300

(PAGE 66)

P1V5S0FET_GATE

PP3V3_S0GPU

P3V3GPU_EN

PP3V3_S3

P3V3S3_EN

PP3V3_S0_FET

P3V3S0_EN

P1V2ENET_EN

Q7801

EN

VLDOIN

VOUT1

VOUT2

PGOOD

(PAGE 70)

EN

ISL8014A

U7720

PPVTT_S0_DDR_LDO

DDRREG_PGOOD

PP1V5_S3RS0

TPS22924

U4201

(PAGE 39)

EN

VIN

ISL8014A

U7760

(PAGE 70)

PPDDR_S3_REG

P1V8FB_EN

FW_PWR_EN

VOUT

PGOOD

VOUT

PGOOD

Q7860

PP5V_S0

P5VS0_EN

VIN

ON

SLG5AP020

U7880

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

PP3V3_FW_FWPHY

PP1V8_S0

P1V8S0_PGOOD

PP1V2_ENET

P1V2ENET_PGOOD

SMC_DDR_ISENSE

PP1V8_S0

Q7922

R7350

A

PP3V3_S0

G

P1V8GPUIFPXFET_GATE

PP3V3_ENET

Q7850

PP1V2_S0

P1V2S0_EN

6 3

SMC PWRGD

NCP303LSN

U5000

(PAGE 45)

PP5V_S0_CPUVTTS0

CPUVTTS0_EN

SMC_CPU_VSENSE

PPVCORE_S0_CPU

V

PP1V5_S3

4.5V

MAX8840

VIN

EN

U6200

PM_ALL_GPU_PGOOD

PP1V8_GPUIFPX

S0PGOOD_PWROK

PP3V3_S0

VOUT

P1V8S0_PGOOD

P5V3V3_PGOOD

V2MON

U7971

ISL88042IRTJJZ

V3MON

V4MON

(PAGE 72)

TRST = 200mS

SMC_RESET_L

VIN

1.05V

ISL95870

U7600

EN

(PAGE 70)

PP4V5_AUDIO_ANALOG

U7980

PP3V3_S0_PWRCTL

VCC

RST*

SMC AVREF SUPPLY

VIN

REF3333

(PAGE 45)

VOUT

PGOOD

RSMRST_PWRGD

SMC_ONOFF_L

VOUT

R7640

CPUVTTS0_PGOOD

PM_PCH_PWRGD

U2850

ALL_SYS_PWRGD

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

PP3V3_S5_AVREF_SMC

PPCPUVTT_S0

A

SMC_CPU_FSB_ISENSE

PANTHER_POINT

PS_PWRGD

U1800

(PAGE 16~21)

CPU

U1000

(PAGE 9~14)

SM_DRAMPWROK

VCCCPUPWRGD

SMC_TPAD_RST_L

SMC_ONOFF_L

(PAGE 39)

PWRBTN#

SYS_RERST#

RSMRST#

ACPRESENT

PLTRST#

PROCPWRGD

DRAMPWROK

RESET*

PP3V3_S5_SMC

TPS22924

U4202

EN

FW_PWR_EN

PM_PWRBTN_L

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

SMC

SYSRST(PA2)

P17(BTN_OUT)

RES*

SMC_ADAPTER_EN

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

SYNC_MASTER=D2_KEPLER

PAGE TITLE

H8S2117

U4900

(PAGE 45)

(P64)

RSMRST_OUT(P15)

IMVP_VR_ON(P16)

99ms DLY

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

U5001

PP1V0_FW_FWPHY

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

3 OF 132

SHEET

3 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

4 OF 132

SHEET

4 OF 99

124578

8 7 6 5 4 3

BOM Variants (continued on CSA 6)

BOM NUMBER

085-3726

085-4776

607-9546

685-0016

685-0017

639-3378

D

639-3379

639-3380

639-3381

639-3384

639-3385

639-3386

639-3387

639-2821

639-2825

639-2817

639-2815

639-2979

639-2980

639-2981

639-2982

639-3618

639-3619

639-3561

C

639-3620

639-3627

639-3562

639-3628

639-3629

PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2

PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2

PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V

PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W

PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y

PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40

PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43

PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44

PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45

PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C

PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1

PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4

PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN

PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW

PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H

PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D

PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F

PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G

PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN

PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR

PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4

PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV

PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM

PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5

PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY

PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT

BOM NAME

D2,MLB,KEPLER,DEV

D2,MLB,KEPLER,FSB DEV

D2,MLB,KEPLER_2PHASE,COMMON

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BOM OPTIONS

D2_DEVEL:ENG

D2_DEVEL:FSB

D2_COMMON,POSCAP_MYLAR_PAIR

PBUS_CAP:KEMET

PBUS_CAP:SANYO

BOM Groups

BOM GROUP

D2_COMMON

D2_COMMON1

D2_COMMON2

D2_PVB

D2_PROGPARTS

D2_DEVEL:ENG

D2_DEVEL:FSB

IVB_PPT_XDP

ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB

CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO

EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5

SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG

ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV

BOM OPTIONS

VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N

ALTERNATE,IVB_PPT_XDP

XDP_CONN,XDP_PCH

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Module Parts

B

PART NUMBER

337S4266

337S4267

337S4268

337S4269

337S4256

338S1113

333S0622

333S0623

333S0628

333S0625

333S0624

333S0629 CRITICAL

333S0630

333S0631

128S0264

128S0257

725-1614

A

725-1648

725-1568

725-1569 CRITICAL

725-1621 CRITICAL

806-2897

QTY

1

32

4

30

1

2

1

946-3819

825-7841

1

DESCRIPTION

IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA

IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA

IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA

PANTHER POINT,C1,SLJ8C,PRQ,BD82HM77

IC,GPU,NV GK107-GTX-PS-A2

IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP

IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM

IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

IC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX

IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG

CAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E

CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LF

INSULATOR,SHORT,REAR,MLB,D2

INSULATOR,TALL,REAR,MLB,D2

INSULATOR,CPU,D2

INSULATOR,GPU,D2

INSULATOR,PCH,D2

CAN,COVER,2,J5

TEXT,LABEL,MLB,D2

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

LBL,PART CONFIG,BOARDS,D2

REFERENCE DES

U1000

U1800

U8000

U3600

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

U8400,U8450,U8500,U8550

C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821

REAR_INSULATOR

CPU_INSULATOR

GPU_INSULATOR

PCH_INSULATOR

CAN_COVER1,CAN_COVER2

TEXT_LABEL

EDGE_BOND

CONFIG_LABEL

CRITICAL

CRITICAL825-7697

CRITICAL

BOM OPTION

CPU_IVY:2_3GHZ

CPU_IVY:2_6GHZ

CPU_IVY:2_7GHZ

TBTRTR:PRQ

2G_HYNIX_1600

2G_SAMSUNG_1600

2G_ELPIDA_1600

4G_HYNIX_1600

4G_SAMSUNG_1600

4G_ELPIDA_1600

FB_2G_HYNIX_A_DIE

FB_2G_SAMSUNG

PBUS_CAP:SANYO

PBUS_CAP:KEMET

PBUS_CAP:SANYO

PBUS_CAP:KEMET

PD Parts

Bar Code Labels / EEEE #’s (continued on CSA 6)

PART NUMBER

QTY

1

825-7563 CRITICAL

825-7563

825-7563 CRITICAL

825-7563

1

825-7563

1

825-7563

1

DESCRIPTION

LABEL,MLB/LIO,MBA

REFERENCE DES

[EEEE:DY3V]

[EEEE:DY3W]

[EEEE:DY3Y]

[EEEE:DY40]

[EEEE:DY43]

[EEEE:DY44]

[EEEE:DY45]

[EEEE:DY4C]

[EEEE:DRF1]

[EEEE:DRF4]

[EEEE:DRDN]

[EEEE:DRDW]

[EEEE:DT9H]

[EEEE:DT9D]

[EEEE:DT9F]

[EEEE:DT9G]

[EEEE:F0HN]

[EEEE:F0HR]

[EEEE:DYW4]

[EEEE:F0HV]

[EEEE:F0HM]

[EEEE:DYW5]

[EEEE:F0HY]

[EEEE:F0HT]

CRITICAL

CRITICAL825-7563

CRITICAL

CRITICAL825-7563

CRITICAL

CRITICAL825-7563

CRITICAL

Programmables

341S3584 CRITICAL

337S2983

341S3597

335S0865

335S0852

341S3565

337S4313

1

IC,TRKPD/KYBD CNTRLR,DVB,D2

IC,TP PSOC,QFN,BLANK

IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2

EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN

IC,GPU ROM,D2,BLANK

IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2

IC,MCU,H8S/2113,9X9MM,TLP-145V

U5701

U3690

U8701

U9100

CRITICAL

DRAM VREF Configs

BOM GROUP

VREF:PROD

VREF:ENG_M3

VREF:ENG_LDO

VREFDQ:M1_M3,VREFCA:LDO_DAC

VREFDQ:M1_DAC,VREFCA:LDO_DAC

BOM OPTIONS

VREFDQ:M1_M3,VREFCA:LDO

DRAM SPD Straps

BOM GROUP

RAM_4G_HYNIX_1600_S

RAM_1G_SAMSUNG_1600

RAM_4G_SAMSUNG_1600_S

RAM_1G_HYNIX_1600

RAM_4G_ELPIDA_1600_S

RAM_2G_SAMSUNG_1600

RAM_2G_SAMSUNG_1333

RAM_2G_HYNIX_1600

RAM_4G_SAMSUNG_1600

RAM_4G_HYNIX_1600

RAM_2G_ELPIDA_1600_S

RAM_2G_ELPIDA_1600

RAM_4G_ELPIDA_1600

RAM_2G_SAMSUNG_1600_S

RAM_2G_HYNIX_1600_S

2G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

2G_HYNIX_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

4G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

4G_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

2G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

BOM OPTIONS

RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

DEVELOPMENT/BASE BOM

PART NUMBER

085-3726

685-0016

QTY

1

D2 MLB KEPLER FSB DEVEL BOM

D2 MLB KEPLER 2PHASE BASE BOM

PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2

DESCRIPTION

D2 MLB KEPLER DEVEL BOM

REFERENCE DES

DEVEL

DEVEL_FSB

CRITICAL

CRITICAL085-4776

BASE CRITICAL607-9546 BASE_BOM

POSCAP_MYLAR

CRITICAL

SMC

341S3308

341S3309

1

IC,SMC,DEVELOPMENT-FSB,A3,D2

IC,SMC,PVB,A3,2.2F36,D2

U4900

CRITICAL

EFI ROM

341S3595

1

IC,EFI,ROM,FSB, D2

U6100

CRITICAL

BOM OPTION

EEEE:DY3V

EEEE:DY3W

EEEE:DY3Y

EEEE:DY40

EEEE:DY43

EEEE:DY44

EEEE:DY45

EEEE:DY4C

EEEE:DRF1

EEEE:DRF4

EEEE:DRDN

EEEE:DRDW

EEEE:DT9H

EEEE:DT9D

EEEE:DT9F

EEEE:DT9G

EEEE:F0HN

EEEE:F0HR

EEEE:DYW4

EEEE:F0HV

EEEE:F0HM

EEEE:DYW5

EEEE:F0HY

EEEE:F0HT

TPAD_PSOC:PROG

TPAD_PSOC:BLANK

TBTROM:PROG

TBTROM:BLANK

GPUROM:BLANK

DPMUXMCU:PROG

DPMUXMCU:BLANK

BOM OPTION

DEVEL_BOM

DEVEL_FSB_BOM

POSCAP_MYLAR_PAIR

SMC_PROG:FSB

SMC_PROG:PVB

BOOTROM_PROG:FSB

Alternate Parts

PART NUMBER

128S0257

353S3527

353S3526 353S3528

376S0855

376S0855 376S0613

376S1076

376S0977

376S1053

128S0311

138S0739 138S0706

197S0434 197S0343

197S0435 197S0343

197S0432

197S0453 197S0181

376S0975

371S0709

371S0713

377S0126 377S0066

377S0147

152S0461

376S1080 376S0820

107S0232

197S0466 197S0464

341S3564

ALTERNATE FOR PART NUMBER

BOM OPTION

128S0264

353S3528

376S0613

VREFDQ:M1_M3

376S0634

376S0796376S0903

376S0859

376S0604

128S0329

197S0431

197S0181197S0452

685-0016685-0017

376S1081

371S0652

371S0558

377S0066

152S1645

155S0583155S0667

107S0129

341S3565

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

SYNC_MASTER=D2_KEPLER

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

REF DES

ALL

6 3

12

COMMENTS:

Kemet alt to Sanyo

Pericom eDP MUX

TI eDP MUX

Diodes alt to Toshiba

Diodes alt to On Semi

Fairchild alt to Siliconix

Diodes alt to Toshiba

Diodes alt to Fairchild

NEC alt to Sanyo

Samsung alt to Murata

Epson Alt to TXC

NDK Alt to TXC

NDK Alt to Epson

Epson Alt to TXC

NDK Alt to TXC

Sanyo POSCAP/Mylar alt to Kemet

Toshiba alt to diodes

NXP alt to infineon

DDS alt to ST

New Semtech package

On Semi alt to Semtech

Cyntec alt to Vishay

Diodes alt to On Semi

Panasonic alt to TDK

Cyntec alt to TFT

Epson alt to NDK

Avnet eDP MUX alt to Renesas

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

5 OF 132

SHEET

5 OF 99

124578

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

A

SIZE

D

8 7 6 5 4 3

12

BOM Variants (continued from CSA 5)

BOM NUMBER

639-3382

639-3383

639-3445

639-3446

639-2818

D

639-2820

639-2823

639-2819

639-3632

639-3633

639-3630

639-3631

PCBA,2.3G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DY41

PCBA,2.3G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DY42

PCBA,2.3G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DYJ5

PCBA,2.3G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DYJ6

PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0

PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP

PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT

PCBA,2.6G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDQ

PCBA,2.7G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0JD

PCBA,2.7G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0J3

PCBA,2.7G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0J4

PCBA,2.7G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0JC

BOM NAME

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY41,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY42,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYJ5,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DYJ6,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDQ,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0JD,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0J4,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0JC,DEVEL_BOM,RAM_4G_ELPIDA_1600

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

C

Bar Code Labels / EEEE #’s (continued from CSA 5)

PART NUMBER

825-7563

825-7563 CRITICAL

825-7563

QTY

1

DESCRIPTION

LABEL,MLB/LIO,MBA

REFERENCE DES

[EEEE:DY41]

[EEEE:DY42]

[EEEE:DYJ5]

[EEEE:DYJ6]

[EEEE:DRF0]

[EEEE:DRDP]

[EEEE:DRDT]

[EEEE:DRDQ]

[EEEE:F0JD]

[EEEE:F0J3]

[EEEE:F0J4]

[EEEE:F0JC]

CRITICAL

CRITICAL825-7563

CRITICAL

CRITICAL825-7563

CRITICAL

BOM OPTION

EEEE:DY41

EEEE:DY42

EEEE:DYJ5

EEEE:DYJ6

EEEE:DRF0

EEEE:DRDP

EEEE:DRDT

EEEE:DRDQ

EEEE:F0JD

EEEE:F0J3

EEEE:F0J4

EEEE:F0JC

Elipda DQ’d Keeping for PRQ

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

BOM Variants

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

6 OF 132

SHEET

6 OF 99

124578

8 7 6 5 4 3

ICT Test Points

CPU NO_TESTs

Thunderbolt NO_TESTs

PCH ALIASES

TRUE

TP_CLINK_CLK TP_CLINK_DATA TP_CLINK_RESET_L

NO_TEST

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC NO_TESTs

NO_TEST

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

GPU NO_TESTs

NO_TEST

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

NO_TEST

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_TP_CPU_RSVD<65..62> NC_TP_CPU_RSVD<58..45> NC_TP_CPU_RSVD<43..32> NC_TP_CPU_RSVD<27..26> NC_TP_CPU_RSVD<24..15> NC_TP_CPU_RSVD<2..1> NC_TP_CPU_RSVD_NCTF<8..5>

NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA NC_PCH_LVDS_VBG

NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3 NC_PCI_AD<31..0> NC_PCI_C_BE_L<3..0> NC_PCI_GNT3_L NC_PCI_GNT2_L NC_PCI_GNT1_L NC_PCI_GNT0_L NC_PCI_PAR NC_PCI_RESET_L NC_PCI_PME_L NC_PCI_CLK33M_OUT3 NC_PCH_NV_RCOMP NC_NV_DQ<15..0> NC_NV_DQS<1..0> NC_NV_CE_L<3..0> NC_NV_ALE NC_NV_CLE NC_NV_RB_L NC_NV_WR_RE_L<1..0> NC_NV_WE_CK_L<1..0> NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_B_D2RN NC_SATA_B_D2RP NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP NC_SMC_P41

NC_DVPDATA<21..4> NC_DVPCNTL_M<1..0> NC_DVPDATA<2..0> NC_DVPDATA<2..0>

NC_TBT_XTAL25OUT NC_TBT_PCIE_RESET0_L NC_TBT_PCIE_RESET1_L NC_TBT_PCIE_RESET2_L NC_TBT_PCIE_RESET3_L NC_DP_TBTSRC_ML_CP<3..0> NC_DP_TBTSRC_ML_CN<3..0> NC_DP_TBTSRC_AUXCH_CP NC_DP_TBTSRC_AUXCH_CN

TP_LPC_DREQ0_L

NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP

NO_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TP_HDMI_CEC

TP_DP_IG_C_HPD TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_MLP<3..0>

18

TP_DP_IG_C_MLN<3..0>

18

TP_DP_IG_C_AUXP TP_DP_IG_C_AUXN

TP_DP_IG_D_HPD

18

TP_DP_IG_D_CTRL_CLK

18

TP_DP_IG_D_CTRL_DATA

18

TP_DP_IG_D_MLP<3..0>

18

TP_DP_IG_D_MLN<3..0>

18

TP_DP_IG_D_AUXP

18

TP_DP_IG_D_AUXN

18

TP_SDVO_TVCLKINN

18

TP_SDVO_TVCLKINP

18

TP_SDVO_STALLN

18

TP_SDVO_STALLP

18

TP_SDVO_INTN

18

TP_SDVO_INTP

TP_GPU_BUFRST_L TP_GPU_GSTATE<0> TP_GPU_GSTATE<1> TP_GPU_MIOA_D<9..0> TP_GPU_MIOA_DE

TP_LVDS_EG_BKL_PWM LVDS_IG_B_CLK_N

18

LVDS_IG_B_CLK_P

18

LVDS_IG_BKL_PWM

18

7

17

SMC_BS_ALRT_L

PCH_VSS_NCTF<1>

TRUE

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<7>

TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

NC NO_TESTs

NC_SMC_FAN_3_TACH NC_SMC_FAN_3_CTL NC_SMC_FAN_2_TACH NC_SMC_FAN_2_CTL NC_FW2_TPBP NC_FW2_TPBN NC_FW2_TPBIAS NC_FW2_TPAP NC_FW2_TPAN NC_FW0_TPBP NC_FW0_TPBN NC_FW0_TPAP NC_ESTARLDO_EN NC_ALS_GAIN NC_USB_HUB_PRTPWR2 NC_USB_HUB_PRTPWR3 NC_USB_HUB_PRTPWR4 NC_USB_HUB_OCS2 NC_USB_HUB_OCS3 NC_USB_HUB_OCS4 NC_SMC_XOSC1 NC_SMC_ODD_DETECT NC_SMC_SYS_LED NC_SMC_HIB_L NC_SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SCL NC_SMC_T25_EN_L NC_SMC_T25_ISENSE NC_ISNS_P1V5R1V35_CPUDDRP NC_ISNS_P1V5R1V35_CPUDDRN NC_ISNS_LCDBKLTP NC_ISNS_LCDBKLTN NC_ISNS_LCD_PANELP NC_ISNS_LCD_PANELN NC_ISNS_AIRPORTP NC_ISNS_AIRPORTN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_HPD NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA NC_DP_IG_C_MLP<3..0> NC_DP_IG_C_MLN<3..0> NC_DP_IG_C_AUXP NC_DP_IG_C_AUXN

NC_DP_IG_D_HPD NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA NC_DP_IG_D_MLP<3..0> NC_DP_IG_D_MLN<3..0> NC_DP_IG_D_AUXP NC_DP_IG_D_AUXN

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE

Functional / ICT Test

Apple Inc.

R

NO_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

I1759

I1760 I1761

I1763

I1762

I1764 I1766

I1765

I1768 I1767

I1769

I1770 I1771

I1773 I1772

I1774

I1775 I1776

I1777

I1779 I1778

I1780

I1781 I1782

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

J6950 - battery

PPVBAT_G3H_CONN SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L GND

J9000 - eDP

DP_INT_AUX_N DP_INT_AUX_P DP_INT_ML_N<0> DP_INT_ML_N<1> DP_INT_ML_N<2> DP_INT_ML_N<3> DP_INT_ML_P<0> DP_INT_ML_P<1> DP_INT_ML_P<2> DP_INT_ML_P<3> LCD_FSS LCD_HPD_CONN LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5VR3V3_SW_LCD PPVOUT_S0_LCDBKLT GND

NO_TEST=TRUE

TBT_A_D2R_C_P<1..0>

TRUE

TBT_A_D2R_C_N<1..0>

TRUE

TBT_A_D2R_P<1..0>

TRUE

TBT_A_D2R_N<1..0>

TRUE

TBT_A_R2D_C_P<1..0>

TRUE

TBT_A_R2D_C_N<1..0>

TRUE

TBT_A_R2D_P<1..0>

TRUE

TBT_A_R2D_N<1..0>

TRUE

TBT_B_D2R_C_P<1..0>

TRUE

TBT_B_D2R_C_N<1..0>

TRUE

TBT_B_D2R_P<1..0>

TRUE

TBT_B_D2R_N<1..0>

TRUE

TBT_B_R2D_C_P<1..0>

TRUE

TBT_B_R2D_C_N<1..0>

TRUE

TBT_B_R2D_P<1..0>

TRUE

TBT_B_R2D_N<1..0>

TRUE

DP_TBTSNK0_ML_C_P<3..0>

TRUE

DP_TBTSNK0_ML_C_N<3..0>

TRUE

DP_TBTSNK0_ML_P<3..0>

TRUE

DP_TBTSNK0_ML_N<3..0>

TRUE

DP_TBTSNK0_AUXCH_C_P

TRUE

DP_TBTSNK0_AUXCH_C_N

TRUE

DP_TBTSNK0_AUXCH_P

TRUE

DP_TBTSNK0_AUXCH_N

TRUE

DP_TBTSNK1_ML_C_P<3..0>

TRUE

DP_TBTSNK1_ML_C_N<3..0>

TRUE

DP_TBTSNK1_ML_P<3..0>

TRUE

DP_TBTSNK1_ML_N<3..0>

TRUE

DP_TBTSNK1_AUXCH_C_P

TRUE

DP_TBTSNK1_AUXCH_C_N

TRUE

DP_TBTSNK1_AUXCH_P

TRUE

DP_TBTSNK1_AUXCH_N

TRUE

NC_PCIE_5_D2RN NC_PCIE_5_D2RP NC_PCIE_5_R2D_CN NC_PCIE_5_R2D_CP

NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP

NC_PCIE_7_D2RN NC_PCIE_7_D2RP NC_PCIE_7_R2D_CN NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CP

NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN NC_PCIE_PE5_R2D_CP

NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RP NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CP

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN NC_PCIE_PE7_R2D_CP

NC_PCIE_PE8_D2RN NC_PCIE_PE8_D2RP NC_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CP

8X

60 61

41 44

60

8X GND

81 95

81 82

81

81 86

3X

81

81 86 99

16X GND

TP_CPU_RSVD<65..62> TP_CPU_RSVD<58..45> TP_CPU_RSVD<43..32> TP_CPU_RSVD<27..26> TP_CPU_RSVD<24..15> TP_CPU_RSVD<2..1> TP_CPU_RSVD_NCTF<8..5>

TP_CRT_IG_BLUE

18

TP_CRT_IG_GREEN

18

TP_CRT_IG_RED

18

TP_CRT_IG_DDC_CLK

18

TP_CRT_IG_DDC_DATA

18

TP_CRT_IG_HSYNC

18

TP_CRT_IG_VSYNC

18

TP_LVDS_IG_CTRL_CLK

18

TP_LVDS_IG_CTRL_DATA

18

TP_PCH_LVDS_VBG

18

TP_HDA_SDIN1

17

TP_HDA_SDIN2

17

TP_HDA_SDIN3

17

TP_PCI_AD<31..0> TP_PCI_C_BE_L<3..0> TP_PCI_GNT3_L TP_PCI_GNT2_L TP_PCI_GNT1_L TP_PCI_GNT0_L

84 93

TP_PCI_PAR

84 93

TP_PCI_RESET_L

7

35 84 93

TP_PCI_PME_L

19

7

35 84 93

TP_PCI_CLK33M_OUT3

19

7

35 84 93

TP_PCH_NV_RCOMP

35 84 93

TP_NV_DQ<15..0>

84 93

TP_NV_DQS<1..0>

84 93

TP_NV_CE_L<3..0>

85 93

TP_NV_ALE

85 93

TP_NV_CLE

35 85 93

TP_NV_RB_L

35 85 93

TP_NV_WR_RE_L<1..0>

7

35 85 93

TP_NV_WE_CK_L<1..0>

35 85 93

TP_PCIE_CLK100M_PE4N

17

85 93

TP_PCIE_CLK100M_PE4P

17

85 93

TP_PCIE_CLK100M_PE5N

35 77 95

TP_PCIE_CLK100M_PE5P

35 77 95

TP_PCIE_CLK100M_PE6N

35 95

TP_PCIE_CLK100M_PE6P

35 95

TP_PCIE_CLK100M_PE7N

35 83 95

TP_PCIE_CLK100M_PE7P

35 83 95

TP_PSOC_P1_3

49

35 95

TP_SATA_B_D2RN

35 95

TP_SATA_B_D2RP

35 77 95

TP_SATA_B_R2D_CN

35 77 95

TP_SATA_B_R2D_CP

35 95

TP_SATA_D_D2RN

17

35 95

TP_SATA_D_D2RP

17

35 83 95

TP_SATA_D_R2D_CN

17

35 83 95

TP_SATA_D_R2D_CP

17

35 95

TP_SATA_E_D2RN

17

35 95

TP_SATA_E_D2RP

17

TP_SATA_E_R2D_CN

17

TP_SATA_E_R2D_CP

17

TP_SATA_F_D2RN

17

TP_SATA_F_D2RP

17

TP_SATA_F_R2D_CN

17

TP_SATA_F_R2D_CP

17

TP_SMC_P41

TP_DVPDATA<21..4> TP_DVPCNTL_M<1..0> TP_DVPCNTL<2..0>

7

TP_DVPCNTL<2..0>

7

TP_TBT_XTAL25OUT

35

TP_TBT_PCIE_RESET0_L

35

TP_TBT_PCIE_RESET1_L

35

TP_TBT_PCIE_RESET2_L

35

TP_TBT_PCIE_RESET3_L

35

TP_DP_TBTSRC_ML_CP<3..0>

35

TP_DP_TBTSRC_ML_CN<3..0>

35

TP_DP_TBTSRC_AUXCH_CP

35

TP_DP_TBTSRC_AUXCH_CN

35

NC_LPC_DREQ0_L

MAKE_BASE=TRUE

17

TP_PCIE_CLK100M_PEBN

17

TP_PCIE_CLK100M_PEBP

17

J6701 - audio flex

AUD_HP_PORT_L

TRUE

AUD_HP_PORT_R

TRUE

AUD_SPDIF_OUT_JACK

TRUE

AUD_TIPDET_INV

TRUE

AUD_TYPEDET

TRUE

CH_HS_GND

TRUE

CH_HS_MIC

TRUE

PP3V3_S0

TRUE

US_HS_GND

TRUE

US_HS_MIC

TRUE

GND

TRUE

J6801 - 3-mic

CON_DMIC_CLK

TRUE

CON_DMIC_PWR

TRUE

CON_DMIC_SDA1

TRUE

CON_DMIC_SDA2

TRUE

GND

TRUE

J6802 - L speaker

SPKRCONN_L_ID

TRUE

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_SL_OUT_P

TRUE

GND

TRUE

J6803 - R speaker

SPKRCONN_R_ID

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

SPKRCONN_SR_OUT_P

TRUE

GND

TRUE

J6900 - DC PWR

ADAPTER_SENSE

TRUE

PP18V5_DCIN_FUSE

TRUE

TDM_ONEWIRE_MPM

TRUE

GND

TRUE

POWER RAILS

PM_SLP_S3_L

TRUE

PP0V75_S0_DDRVTT

TRUE

PP1V05_S0

TRUE

PP1V8_S0

TRUE

PP3V3_S0

TRUE

PP3V3_S0GPU

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

PP5V_S3

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PPDCIN_G3H

TRUE

PPVCORE_GPU

TRUE

PPVCORE_S0_CPU

TRUE

PPVTTDDR_S3

TRUE

TP_PCIE_5_D2RN

17

TP_PCIE_5_D2RP

17

TP_PCIE_5_R2D_CN

17

TP_PCIE_5_R2D_CP

17

TP_PCIE_6_D2RN

17

TP_PCIE_6_D2RP

17

TP_PCIE_6_R2D_CN

17

TP_PCIE_6_R2D_CP

17

TP_PCIE_7_D2RN

17

TP_PCIE_7_D2RP

17

TP_PCIE_7_R2D_CN

17

TP_PCIE_7_R2D_CP

17

TP_PCIE_8_D2RN

17

TP_PCIE_8_D2RP

17

TP_PCIE_8_R2D_CN

17

TP_PCIE_8_R2D_CP

17

TP_PCIE_PE5_D2RN TP_PCIE_PE5_D2RP TP_PCIE_PE5_R2D_CN TP_PCIE_PE5_R2D_CP

TP_PCIE_PE6_D2RN TP_PCIE_PE6_D2RP TP_PCIE_PE6_R2D_CN TP_PCIE_PE6_R2D_CP

TP_PCIE_PE7_D2RN TP_PCIE_PE7_D2RP TP_PCIE_PE7_R2D_CN TP_PCIE_PE7_R2D_CP

TP_PCIE_PE8_D2RN TP_PCIE_PE8_D2RP TP_PCIE_PE8_R2D_CN TP_PCIE_PE8_R2D_CP

53 54 58

53 58

59

58 59

4X

58

7 8

4X

58

2X GND

59

57 59 96

59

57 59 96

60

2X

60

2X GND

7

18 27 38 41 70

8

7 8

96

8

7 8

8

96

41 42

7 8

8

7 8

8

NC NO_TESTs

58

96

58

60

I1756

I1758 I1757

I1731

I1733 I1735

I1734

I1736 I1738

I1737 I1740

I1739

I1741

I1743

I1742

I1745 I1744

I1746 I1748

I1747

I1750 I1749

I1751

I1753 I1752

I1755

I1754

FUNC_TEST

Functional Test Points

FUNC_TEST

I1596 I1597

I1599 I1600

I1601

I1602 I1603

I1604

D

C

B

A

I1605 I1606

I1608

I1609 I1607

I1611

I1610

I1613

I1614 I1612

I1615

I1616

I1618

I1619 I1617

I1621

I1620 I1623

I1624

I1622 I1625

I1626 I1628

I1629

I1627 I1631

I1630

I1633 I1634

I1632

I1635

I1636

I1638

I1639 I1637

I1641

I1640 I1643

I1644

I1642 I1645

I1646 I1648

I1649

I1647 I1651

I1650

I1785

I1653 I1654

I1680

I1683

I1793

I1684

I1682 I1795

I1728

I1730

I1729

J3501 - airport

AP_CLKREQ_Q_L

TRUE

AP_RESET_CONN_L

TRUE

PCIE_AP_D2R_PI_N

TRUE

PCIE_AP_D2R_PI_P

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

PCIE_WAKE_L

TRUE

PP3V3_S3RS4_BT_F

TRUE

PP3V3_WLAN

TRUE

USB_BT_CONN_N

TRUE

USB_BT_CONN_P

TRUE

WIFI_EVENT_L

TRUE

GND

TRUE

J3502 - ALS camera

PP5V_S3_ALSCAMERA_F

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

USB_CAMERA_CONN_N

TRUE

USB_CAMERA_CONN_P

TRUE

GND

TRUE

J4400 - rio coax

HDMI_EG_CLK_C_N

TRUE

HDMI_EG_CLK_C_P

TRUE

HDMI_EG_DATA_C_N<0>

TRUE

HDMI_EG_DATA_C_N<1>

TRUE

HDMI_EG_DATA_C_N<2>

TRUE

HDMI_EG_DATA_C_P<0>

TRUE

HDMI_EG_DATA_C_P<1>

TRUE

HDMI_EG_DATA_C_P<2>

TRUE

PCIE_CLK100M_ENET_N

TRUE

PCIE_CLK100M_ENET_P

TRUE

PCIE_ENET_D2R_N

TRUE

PCIE_ENET_D2R_P

TRUE

PCIE_ENET_R2D_C_N

TRUE

PCIE_ENET_R2D_C_P

TRUE

USB3_EXTB_RX_N

TRUE

USB3_EXTB_RX_P

TRUE

USB3_EXTB_TX_C_N

TRUE

USB3_EXTB_TX_C_P

TRUE

USB_EXTB_N

TRUE

USB_EXTB_P

TRUE

GND

TRUE

J4410 - rio flex

ENET_CLKREQ_L

TRUE

ENET_RESET_L

TRUE

HDMI_EG_DDC_CLK

TRUE

HDMI_EG_DDC_DATA

TRUE

HDMI_HPD_L

TRUE

I2C_DPMUX_A_SCL

TRUE

I2C_DPMUX_A_SDA

TRUE

PM_SLP_S3_L

TRUE

PM_SLP_S4_L

TRUE

PP1V5_S0_RIO

TRUE

PP3V3_S3

TRUE

PP3V3_S4

TRUE

PP5V_S4

TRUE

SDCONN_STATE_CHANGE_RIO

TRUE

SD_PWR_EN

TRUE

USB_EXTB_OC_L

TRUE

GND

TRUE

J5050 - hall effect

PP3V42_G3H

TRUE

SMC_LID_R

TRUE

GND

TRUE

J5650 - left fan

FAN_LT_PWM

TRUE

FAN_LT_TACH

TRUE

PP5V_S0

TRUE

GND

TRUE

J5660 - right fan

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE

PP5V_S0

TRUE

GND

TRUE

J5815 - kbd backlight

KBDLED_ANODE1

TRUE

KBDLED_ANODE2

TRUE

SMC_KBDLED_PRESENT_L

TRUE

GND

TRUE

34

34 92

34 96

18 34

34

34 42

34 91

34 41 42

4X GND

34

7

41 44 94

7

41 44 94

34 91

38 77 95

17 38 92

19 38 91

38 97

26 38 91

19X GND

17 38

25

38 77

38 42 82

44

7

18 27 38 41 70

18 27 34 38 40 41 70

8

3X P3V3_S3

7 8

5X P5V_S4

8

25 38

9

38

24 38

10X GND

7 8

42

48

3X P5V_S0

7 8

5X GND

48

3X P5V_S0 5X GND

2X

50

2X

50

4X GND

I1685

I1686 I1687

I1689

I1688 I1691

I1690 I1692

I1694

I1693 I1695

I1799

I1800 I1697

I1797

I1798 I1817

I1818

I1652 I1655

I1656 I1658

I1659

I1657 I1661

I1660

I1663 I1664

I1662

I1665 I1666

I1668 I1669

I1667

I1671 I1670

I1673

I1674 I1672

I1675

I1676 I1678

I1679 I1677

I1681

I1802

I1803 I1696

I1698

I1699 I1700

I1702

I1701 I1703

I1704 I1705

I1707

I1706 I1708

I1709

I1710 I1712

I1711

I1713 I1715

I1714 I1717

I1716

I1718 I1720

I1719

I1722 I1721

I1723

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

J5100 - lpc + spi

LPCPLUS_GPIO LPCPLUS_RESET_L LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK33M_LPCPLUS LPC_FRAME_L LPC_PWRDWN_L LPC_SERIRQ PM_CLKRUN_L PP5V_S0 SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TX_L SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO SPI_ALT_MOSI TP_SMC_MD1 TP_SMC_TRST_L GND

J5700 - ipd flex

Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PP3V3_S4 PP5V_S5 PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA

GND

J5713 - keyboard

PP3V3_S4 PP3V42_G3H WS_CONTROL_KBD WS_KBD1 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD2 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD_ONOFF_L WS_LEFT_OPTION_KBD WS_LEFT_SHIFT_KBD GND

20 43

25 43

17 41 43 82 92

25 43 92

17 41 43 82 92

18 25 41 43

17 41 43

18 41 43

7 8

41 42 43 61

42 43

41 42 43

20 43 52

43

2X GND

49

7 8

49

7

41 44 94

7

41 44 94

2X GND

7 8

49

2X GND

PLACEABLE BEAD-PROBES FOR TBT

7

35 85 93

7

35 85 93

7

35 84 93

7

35 84 93

TBT_B_R2D_C_P<1> TBT_B_R2D_C_P<0> TBT_A_R2D_C_P<1> TBT_A_D2R_P<1> TBT_A_D2R_N<1>

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

BP0733

SIGNAL_MODEL=EMPTY

BP0734

SIGNAL_MODEL=EMPTY

BP0735

SIGNAL_MODEL=EMPTY

BP0731

SIGNAL_MODEL=EMPTY

BP0732

6 3

12

26

41

42

41

42

8

69 98

69

98

99

81 98

99

NC_HDMI_CEC

NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP

NC_SDVO_STALLN NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

NC_GPU_BUFRST_L NC_GPU_GSTATE<0> NC_GPU_GSTATE<1> NC_GPU_MIOA_D<9..0> NC_GPU_MIOA_DE

NC_LVDS_EG_BKL_PWM NC_LVDS_IG_B_CLKN NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM

NC_SMC_BS_ALRT_L

PCH_VSS_NCTF<15> PCH_VSS_NCTF<17> PCH_VSS_NCTF<19> PCH_VSS_NCTF<19> PCH_VSS_NCTF<21> PCH_VSS_NCTF<25> PCH_VSS_NCTF<27> PCH_VSS_NCTF<29>

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

7 OF 132

SHEET

7 OF 99

124578

D

C

B

7

A

SIZE

D

C

B

A

=PPBUS_G3H

60 61

G3H Rails

=PPVIN_S5_HS_COMPUTING_ISNS

46

=PPVIN_S5_HS_GPU_ISNS

46

=PPVIN_S5_HS_OTHER_ISNS

46

=PP18V5_DCIN_CONN

60

=PP18V5_DCIN_ISOL

60

=PP3V42_G3H_REG

60

=PP3V42_G3H_AUDIO

58

=PP3V42_G3H_TDM

60

=PP3V42_S3_HALL

42

For PCH RTC Power

=PPVRTC_G3_OUT

25

5V Rails

=PP5V_S5_LDO

63

=PP5V_SUS_FET

69

=PP5V_S4_REG

63

=PP5V_S3_FET

69

=PP5V_S0_FET

69

=PP5V_S0_P1V5_LDO

68

=PP3V3_S4_FET

69

=PP3V3_S4_TBT_R

36

=PP3V3_S4_RIO

38

=PP3V3_SUS_FET

69

=PP3V3_SUS_ROM

52

=PP3V3_SUS_PCH_VCC_SPI

21 23

8 7 6 5 4 3

3.3V Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPBUS_S0_LCDBKLT =PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPVIN_S5_HS_GPU_ISNS_R =PPVIN_SW_TBTBST =PPBUS_S0_VSENSE =PPBUS_G3H_T25_R

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_CPUAXG =PPVIN_S0_VCCSAS0 =PPVIN_S0_PCHVCCIOS0

PPVIN_S5_HS_GPU_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_S0_GFXIMVP

=PPVIN_S0GPU_P1V5P1V0

PPVIN_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_P5VP3V3 PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

=PPDCIN_S5_CHGR PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

=PPDCIN_S5_CHGR_ISOL =PPDCIN_S5_VSENSE

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_CHGR =PP3V42_G3H_ONEWIREPROT =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_5 =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3_SYSCLK

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PPVRTC_G3_PCH

PP5V_S5

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.1 MM

=PP5V_S5_P1V5S3RS0FET =PP5V_S5_P5VSUSFET =PP5V_S5_TPAD

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP5V_SUS_PCH

PP5V_S4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

=PP5V_S4_RIO =PP5V_S4_P5VS0FET =PP5V_S4_P5VS3FET =PP5V_S0_LCD

=PP5V_S3_LTUSB =PP5V_S4_ISNS =PP5V_S4_TPAD =PP5V_S4_AUDIO

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

=PP5V_S3_ISNS =PP5V_S3_ALSCAMERA =PP5V_S3_DDRREG =PP5V_S3_DEBUG_ADC_AVDD =PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_DEBUG_ISNS =PP5V_S3_MEMRESET PP5V_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

=PP5V_S0GPU_P1V0P1V35_GPU =PP5V_S0_AUDIO_XW =PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN_LT

=PP5V_S0_FAN_RT

=PP5V_S0_GFXIMVP

=PP5V_S0_KBDLED

=PP5V_S0_LPCPLUS =PP5V_S0_PCH =PP5V_S0_PCHVCCIOS0

=PP5V_S0_RMC =PP5V_S0_VCCSAS0 =PP5V_S0_VMON

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM

=PP3V3_S4_TPAD

=PP3V3_S4_SMC =PP3V3_S4_BT PP3V3_SUS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_PCH_VCCSUS_GPIO =PP3V3_SUS_PCH_GPIO =PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_CNTRL =PP3V3_SUS_SMC

MAKE_BASE=TRUE VOLTAGE=3.3V

VOLTAGE=12.8V MAKE_BASE=TRUE

VOLTAGE=18.5V MAKE_BASE=TRUE

VOLTAGE=3.42V MAKE_BASE=TRUE

VOLTAGE=5V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

VOLTAGE=12.8V MAKE_BASE=TRUE

7

61

45

7

86

46

9

37

45

65 66

64

67

66

62

87

80

74

63

7

43

41 42 78

61 70

60

70

44

40

49

42

25

17 18 21

7

69

49

23

38

69

81

40

49

53 59

99

34

64

98

27

7

74

9

86

65 66

67

48

80

50

43

23 25

87

98

62

70

7

25 42

34

68

21 23

17 18 19 20

21 23

70

42

49

=PP3V3_S5_REG

63

=PP3V3_S3_FET

69

=PP3V3_S0_FET

69

TBT RAILS

=PP3V3_TBTLC_FET

37

=PP1V05_TBTLC_FET

37

=PP1V05_TBTCIO_FET

37

=PP15V_TBT_REG

9

37

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_GPU_P3V3GPUFET =PP3V3_GPU_MISC_P3V3GPUMISCFET =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET

=PP3V3_S4_DPAPWRSW

=PP3V3_S4_DPBPWRSW =PP3V3_S4_P3V3S4FET =PP3V3_S5_CPU_VCCDDR =PP3V3_S5_P1V2P1V8 =PP3V3_S5_P1V5S0 =PP3V3_S5_P3V3SUSFET =PP3V3_S5_PCH

=PP3V3_S5_PCHPWRGD =PP3V3_S5_PCH_GPIO =PP3V3_S5_PCH_VCCDSW =PP3V3_S5_PWRCTL

=PP3V3_S5_SMCBATLOW =PP3V3_S5_SYSCLK

=PP3V3_S5_VMON =PP3V3_S5_XDP =PP3V3_S4_TBTAPWRSW =PP3V3_S4_TBTBPWRSW

PP3V3_S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

=PP3V3_S3_BT =PP3V3_S3_DPMUX_UC =PP3V3_S3_ISNS =PP3V3_S3_MEMRESET =PP3V3_S3_PCH_GPIO =PP3V3_S3_RIO =PP3V3_S3_SMBUS_SMC_2_S3 =PP3V3_S3_SMBUS_SMC_3 =PP3V3_S3_TPAD =PP3V3_S3_USBMUX =PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_GYRO =PP3V3_S3_SMS =PP3V3_S3_SDBUF

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 mm

=PP3V3_S0_AUDIO =PP3V3_S0_AUDIO_DIG =PP3V3_S0_BKL_VDDIO =PP3V3_S0_CPUTHMSNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_DPMUX =PP3V3_S0_DPMUXI2C =PP3V3_S0_DPMUX_UC =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_GPUTHMSNS =PP3V3_S0_HS_ISNS

=PP3V3_S0_IMVPISNS =PP3V3_S0_ISNS =PP3V3_S0_LCD

=PP3V3_S0_P1V8GPUFET =PP3V3_S0_P3V3TBTFET =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_VCC3_3_GPIO =PP3V3_S0_PCH_VCC3_3_HVCMOS =PP3V3_S0_PCH_VCC3_3_PCI =PP3V3_S0_PCH_VCC3_3_SATA =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF

=PP3V3_S0_SATAMUX =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_1_S0

=PP3V3_S0_SSD

=PP3V3_S0_SYSCLK

=PP3V3_S0_TBTI2C =PP3V3_S0_TBTPWRCTL =PP3V3_S0_TPAD =PP3V3_S0_VMON =PP3V3_S0_X29THMSNS =PP3V3_S0_XDP =PP3V3_S0_DDR3THMSNS =PP3V3_S0_SPKRTHMSNS

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM

=PP3V3_TBT_PCH_GPIO =PPVDDIO_TBT_CLK =PP3V3_TBTLC_RTR

PP1V05_TBTLC

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

=PP1V05_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PPHV_SW_TBTAPWRSW =PPHV_SW_TBTBPWRSW

VOLTAGE=3.3V MAKE_BASE=TRUE

VOLTAGE=1.05V MAKE_BASE=TRUE

VOLTAGE=15V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15 MM MAKE_BASE=TRUE

70

24

84

85

84

85

7

96

69

27

68

69

18

70

20

21 23

70

42

25

7

34

82

99

27

19 25

38

44

26

33

34

51

25

7

96

59

53 58

86

47

13

82 83

44

35 78 82

48

47

46

45 98 99

81

37

17 23

17 18 19 20 25 37

23

21 23

23

70 88

25

39

25 70

44

39

25

37

50

70

47

24

20

25

35 36 37

37

36

=PP1V8_S0_REG

68

4A max supply

=PP1V8_S0_CPU_VCCPLL_R

13 15

=PPDDR_S3_REG

64

=PPVIN_S3_MEM_ISNS

45

=PP1V5_S3RS0_FET_ISNS

69

=PP1V5_S0_REG

68

=PP1V5_S0_RIO_LDO

68

=PPVTT_S3_DDR_BUF

33 64

=PPVTT_S0_DDR_LDO

64

=PP1V05_SUS_LDO

68

=PPCPUVCCIO_S0_REG

67

=PPPCHVCCIO_S0_REG

87

=PP1V05_S0_P1V05TBTFET

37 99

1.8V/1.5V/1.2V/1.05V Rails

Defined here since TBT page does not know PBUS voltage

=PPBUS_SW_BKL

99

SMC_T25_EN_L

41

I1679

Backlight Rails

PP1V8_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V8R1V5_S0_PCH_VCCVRM =PP1V8_S0_AUDIO =PP1V8_S0_CPU_VCCPLL =PP1V8_S0_GPUFET

=PP1V8_S0_PCH_VCCTX_LVDS

=PP1V8_S0_PCH_VCC_DFTERM =PPVDDIO_S0_SBCLK =PP1V8_S0_P1V5_LDO

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_MEMRESET =PPDDR_S3_MEMVREF =PPVIN_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO =PPVIN_S3_MEM_ISNS_R

PP1V5R1V35_MEM

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5R1V35_S3_MEM_A =PP1V5R1V35_S3_MEM_B

PP1V5_S3RS0_CPUDDR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3RS0_VMON =PP1V5_S3_CPU_VCCDDR

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S0_AUDIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

PP1V5_S0_RIO

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP1V5_S0_RIO

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG PP1V05_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_CPU_VCCIO

=PPVCCIO_S0_XDP =PPVCCIO_S0_CPUIMVP =PPVCCIO_S0_SMC =PP1V05_S0_VMON =PP1V05_S0_RMC

PP1V05_PCHVCCIO_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MAKE_BASE=TRUE =PP1V05_S0_PCH_VCCIO_PLLPCIE =PP1V05_S0_PCH_VCCADPLL =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCIO_CLK =PP1V05_S0_PCH_VCCIO_USB =PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_PCH_VCCASW =PP1V05_S0_PCH_VCCIO_CLK =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCCIO_PLLUSB =PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI =PP1V05_S0_PCH_VCCDMI_FDI =PP1V05_S0_P1V05TBTFET_R

PPVIN_SW_TBTBST

VOLTAGE=12.8V

VOLTAGE=1.5V MAKE_BASE=TRUE

37

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_PWR

NC_SMC_T25_EN_L

PP1V05_S0_P1V05TBTFET

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

6 3

VOLTAGE=1.8V MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=12.6V

MAKE_BASE=TRUE

VOLTAGE=1.05V MAKE_BASE=TRUE

7

21

15

23

20 21 23

25

68

27

33

69

64

45

28 29

30 31

96

70

11 14 16 27

53

21 23 25

7

38

7

32

27

24

7

10 11 13 14 15

24

65

42

70

98

21

23

21 23

18

17 21 23

8

21 23

8

21 23

17 21 23

17 23

21 23

21

21 23

21

99

=PP3V3_S0GPU_FET

69 88

=PP3V3_S0GPU_MISC_FET

69

74

=PP1V05_S0GPU_REG

74

45

=PPVCORE_S0_CPU_REG

66

=PPVCORE_S0_AXG_REG

45 66

=PP1V5_S3_CPU_VCCDQ

13 16

=PP1V05_S0_CPU_VCCPQE

13 15

=PPVCCSA_S0_REG

62 99

86

7

TP_P1V8GPU_EN

=PP1V5R1V35_GPU_REG

=PP1V8_GPU_FET

88

=PPVCORE_GPU_REG

GND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.085MM VOLTAGE=0V

MAKE_BASE=TRUE

"GPU" Rails

PP3V3_S0GPU

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_GPU_IFPX_PLLVDD =PP3V3_S0_GFX3V3BIAS =PP3V3_GPU_VDD33

PP3V3_S0GPU_MISC

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_GPU_MISC

=P1V8GPU_EN

PP1V5R1V35_S0GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V35_GPU_FBVDDQ =PP1V35_GPU_S0_FB

TP_GPU_PGOOD2

MAKE_BASE=TRUE

PP1V0_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP1V0_GPU_DPLL =PP1V0_GPU_DP_AB =PP1V0_GPU_DP_CD =PP1V05_GPU_IFPCD_IOVDD =PP1V05_GPU_IFPEF_IOVDD =PP1V05_GPU_PEX_IOVDD =PP1V05_GPU_PEX_PLLVDD

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPVCORE_GPU

=PPVCORE_S0_GFX_REG

=LVDS_VCCA

Chipset "VCore" Rails

SYNC_MASTER=D2_KEPLER

PAGE TITLE

21

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

=PPVCORE_S0_CPU

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPVCORE_S0_CPU_VCCAXG

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCCSA_S0_REG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPVCCSA_S0_CPU

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

88

MAKE_BASE=TRUE VOLTAGE=1.5V

VOLTAGE=1.05V MAKE_BASE=TRUE

12

VOLTAGE=1.05V MAKE_BASE=TRUE

VOLTAGE=1.0V MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=1.25V

MAKE_BASE=TRUE VOLTAGE=1.05V

VOLTAGE=0.9V MAKE_BASE=TRUE

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

7

77

80

71 77 78 79

77

SYNC_DATE=01/13/2012

051-9589

4.18.0

8 OF 132

8 OF 99

124578

72 75 76

73

77

73 79

77 79

7

72 79

80

7

13 15 45 98

13 14 16

13 16

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

ZT0915

2.8R2.3

ZT0950

TH-NSP

SL-2.3X3.9-2.9X4.5

ZT0974

TH-NSP

D

C

SL-1.1X0.45-1.4x0.75

ZT0975

TH-NSP

SL-1.1X0.45-1.4x0.75

SH0920

STDOFF-4.5OD2.15H-SM

1

STDOFF-4.5OD2.15H-SM-1

SH0921

1

STDOFF-4.5OD2.15H-SM

STDOFF-4.9OD2.38H-SM-2

1

SH0950

SM

SHLD-J5-USB

B

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0931

SM

1

SH0934

SM

1

2.8OD1.2ID-1.35H-SM

A

SH0942

2.8OD1.2ID-1.35H-SM

1

Frame Holes

1

GND_BATT_CHGND

1

GND_CHASSIS_FAN

1

GND_CHASSIS_MLBCAN5

1

GND_CHASSIS_MLBCAN6

THERMAL MODULE STANDOFFS

SH0922

1

SH0946

1

SH0952

SM

SHLD-J5-CAN-FENCE-MDP-2

POGO PINS

SH0940

1

ZT0970

TH-NSP

GND_CHASSIS_MLBCAN1

GND_CHASSIS_MLBCAN2

GND_CHASSIS_MLBCAN3

GND

MAKE_BASE=TRUE

SH0927

1

SH0929

STDOFF-4.5OD2.15H-SM

1

SH0930

STDOFF-4.5OD2.15H-SM

1

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

SH0945

1

GND_CHASSIS_MLBCAN4

SH0926

STDOFF-4.5OD2.15H-SMSTDOFF-4.5OD2.15H-SM

1

SH0928

STDOFF-4.5OD2.15H-SM

1

SL-1.1X0.45-1.4x0.75

ZT0971

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0972

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0973

TH-NSP

1

SL-1.1X0.45-1.4x0.75

SH0925

STDOFF-4.5OD1.8H-SM

1

SH0923

STDOFF-4.5OD1.8H-SM

1

SH0924

STDOFF-4.5OD1.9H-SM

1

APN 806-2247

BR0901

1

SH0951

SM

MLB-MTG-BRKT-J5

TH

1

SHLD-J5-CAN-FENCE-MDP-1

POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0932

SM

1

SH0935

SM

1

SH0941

2.8OD1.2ID-1.35H-SM

1

SH0933

SM

1

SH0936

SM

1

SH0944

2.8OD1.2ID-1.35H-SM

1

Digital Ground

SH0943

2.8OD1.2ID-1.35H-SM

1

20

MLB_RAMCFG0

6 3

TBT_LSOE<3>

TBT_LSOE<2>

82

LVDS_IG_BKL_ON

18

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

18

MAKE_BASE=TRUE

17

82

PCIE_EXCARD_D2R_N

17

PCIE_EXCARD_D2R_P

17

PCIE_EXCARD_R2D_C_N

17

PCIE_EXCARD_R2D_C_P

17

PCIE_CLK100M_EXCARD_N

17 92

PCIE_CLK100M_EXCARD_P

17 92

17

POGO-2.3OD-5.5H-SM-LOW-FORCE

TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP

38

ZT0990

2.1SM2.0MM-CIR 2.1SM2.0MM-CIR

SMT-PAD-NSP

1

SH0937

SM

1

2.8OD1.2ID-1.35H-SM

MLB_RAMCFG3

20

MLB_RAMCFG2

R0910

1/20W

20

RAMCFG1:L

1

1K

5% MF

201

2

R0911

1/20W

1

1K

5% MF

201

2

MLB_RAMCFG1

RAMCFG0:L

T29 / GMUX JTAG Signals

EG_RESET_L

MAKE_BASE=TRUE

PEX_CLKREQ_L

MAKE_BASE=TRUE

PEG_CLKREQ_L

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_IG

MAKE_BASE=TRUE

DP_TBTSNK1_HPD_IG

MAKE_BASE=TRUE

TP_PCH_GPIO64_CLKOUTFLEX0 TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

SD_PWR_EN_PCH

MAKE_BASE=TRUE

SD_PWR_EN

7

MAKE_BASE=TRUE

TP_FW_PWR_EN

MAKE_BASE=TRUE

SMT GND TEST PONTS

SH0960

1

SH0961

1

RAMCFG2:L

R0912

1/20W

1

1K

5% MF

201

2

TBT_LSEO_LSOE3

MAKE_BASE=TRUE

TBT_LSEO_LSOE2

MAKE_BASE=TRUE

NO_TEST=TRUE

TBT_LSEO<3>

TBT_LSEO<2>

GMUX ALIASES

GPU_RESET_L

IG_BKLT_EN

IG_LCD_PWR_EN

EG_CLKREQ_IN_L

EG_CLKREQ_OUT_L

DPA_IG_HPD

DPB_IG_HPD

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

ENET_LOW_PWR_PCH

ENET_LOW_PWR

FW_PWR_EN

ZT0991

SMT-PAD-NSP SMT-PAD-NSP

1

RAMCFG3:L

1

R0913

1K

5%

1/20W

MF

201

2

NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P

NC_PCIE_CLK100M_EXCARD_N

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

TRUE MAKE_BASE=TRUE

DPLL_REF_CLKN

DPLL_REF_CLKP

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO66_CLKOUTFLEX2

NC_PCH_GPIO67_CLKOUTFLEX3

ZT0992

2.1SM2.0MM-CIR

1

ZT0993

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

8

71 78

82

78 82

82

18 82

11 89

20 24 25

25

=PP5V_S0_AUDIO_XW

CPU_VID<0..6>

MAKE_BASE=TRUE

MEMVTT_EN

27

MAKE_BASE=TRUE

NC_PEG_D2R_P<15..14>

MAKE_BASE=TRUE

NC_PEG_D2R_N<15..14>

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15..14>

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15..14>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

35 92

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>

35 92

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

35 92

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

35 92

MAKE_BASE=TRUE

PEG_D2R_P<7..0>

71 88 89

MAKE_BASE=TRUE

PEG_D2R_N<7..0>

71 88 89

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

71 89

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

71 89

MAKE_BASE=TRUE

TBT_D2R_P<3..2>

TBT_D2R_N<3..2>

TBT_R2D_C_P<3..2>

TBT_R2D_C_N<3..2>

DPMUX_UC_BOOT_TX

82

DPMUX_UC_BOOT_RX

82

PCIE_SSD_D2R_P<1..0>

39 92

MAKE_BASE=TRUE

PCIE_SSD_D2R_N<1..0>

39 92

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

39 92

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_N<1..0>

39 92

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_N

MAKE_BASE=TRUE

NC_PCH_FDI_DATA_N<7..0>

MAKE_BASE=TRUE

NC_PCH_FDI_DATA_P<7..0>

MAKE_BASE=TRUE

NC_PCH_FDI_FSYNC<1..0>

MAKE_BASE=TRUE

NC_PCH_FDI_LSYNC<1..0>

MAKE_BASE=TRUE

NC_CPU_FDI_DATA_N<7..0>

MAKE_BASE=TRUE

NC_CPU_FDI_DATA_P<7..0>

MAKE_BASE=TRUE

NC_CPU_FDI_FSYNC<1..0>

MAKE_BASE=TRUE

NC_CPU_FDI_LSYNC<1..0>

MAKE_BASE=TRUE

USB_BT_P

34 91

MAKE_BASE=TRUE

USB_BT_N

34 91

MAKE_BASE=TRUE

USB_TPAD_P

49 91

MAKE_BASE=TRUE

USB_TPAD_N

49 91

MAKE_BASE=TRUE

USB_SMC_P

41 91

MAKE_BASE=TRUE

USB_SMC_N

41 91

MAKE_BASE=TRUE

PU_USBHUB_DN4P

MAKE_BASE=TRUE

PU_USBHUB_DN4N

MAKE_BASE=TRUE

XW0902

SM

1 2

XW0903

SM

1 2

CPU signals

Unused PEG signals

NO_TEST=TRUE

T29 Signals Through PEG

GPU signals

UNUSED TBT PORTS

DPMUX TX & RX

SSD PCIE SIGNALS

UNUSED FDI SIGNALS

NO_TEST=TRUE

USB SIGNALS

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

PP5V_S0_AUDIO_AMP_R

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

CPUIMVP_VID<0..6>

=DDRVTT_EN

=PEG_D2R_P<15..14>

=PEG_D2R_N<15..14>

=PEG_R2D_C_P<15..14>

=PEG_R2D_C_N<15..14>

=PEG_D2R_P<11..8>

=PEG_D2R_N<11..8>

=PEG_R2D_C_P<11..8>

=PEG_R2D_C_N<11..8>

=PEG_D2R_P<7..0>

=PEG_D2R_N<7..0>

=PEG_R2D_C_P<7..0>

=PEG_R2D_C_N<7..0>

NC_TBT_D2RP<3..2>

MAKE_BASE=TRUE

NC_TBT_D2RN<3..2>

MAKE_BASE=TRUE

NC_TBT_R2D_CP<3..2>

MAKE_BASE=TRUE

NC_TBT_R2D_CN<3..2>

MAKE_BASE=TRUE

DPMUX_UC_TX

MAKE_BASE=TRUE

DPMUX_UC_RX

MAKE_BASE=TRUE

=PEG_D2R_P<13..12>

=PEG_D2R_N<13..12>

=PEG_R2D_C_P<13..12>

=PEG_R2D_C_N<13..12>

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

=FDI_DATA_N<7..0>

=FDI_DATA_P<7..0>

=FDI_FSYNC<1..0>

=FDI_LSYNC<1..0>

FDI_DATA_N<7..0>

FDI_DATA_P<7..0>

FDI_FSYNC<1..0>

FDI_LSYNC<1..0>

USBHUB_DN1_P

USBHUB_DN1_N

USBHUB_DN2_P

USBHUB_DN2_N

USBHUB_DN3_P

USBHUB_DN3_N

USBHUB_DN4_P

USBHUB_DN4_N

NO_TEST=TRUE

57

27 64

10

82

10

18

10 89

26

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

10

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

10

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

10

MAKE_BASE=TRUE

10

17 92

NC_USB3_EXTD_TX_P

MAKE_BASE=TRUE

NC_USB3_EXTD_TX_N

MAKE_BASE=TRUE

NC_USB3_EXTD_RX_P

MAKE_BASE=TRUE

NC_USB3_EXTD_RX_N

MAKE_BASE=TRUE

NC_USB_EXTD_EHCI_P

MAKE_BASE=TRUE

NC_USB_EXTD_EHCI_N

MAKE_BASE=TRUE

NC_USB3_EXTC_TX_P

MAKE_BASE=TRUE

NC_USB3_EXTC_TX_N

MAKE_BASE=TRUE

NC_USB3_EXTC_RX_P

MAKE_BASE=TRUE

NC_USB3_EXTC_RX_N

MAKE_BASE=TRUE

NC_USB_EXTC_P

MAKE_BASE=TRUE

NC_USB_EXTC_N

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_CLK_N

MAKE_BASE=TRUE

NC_LVDS_IG_A_CLK_P

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_N<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_P<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_DDC_CLK

MAKE_BASE=TRUE

NC_LVDS_IG_DDC_DATA

MAKE_BASE=TRUE

NC_PCIE_FW_D2RN

MAKE_BASE=TRUE

NC_PCIE_FW_D2RP

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CN

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CP

MAKE_BASE=TRUE

NC_SATA_ODD_D2R_N

MAKE_BASE=TRUE

NC_SATA_ODD_D2R_P

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_C_N

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_C_P

MAKE_BASE=TRUE

NC_DP_IG_MLP<3..0>

MAKE_BASE=TRUE

NC_DP_IG_MLN<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

TBTBST:N

=PPVIN_SW_TBTBST

8

37

UNUSED USB SIGNALS

NO_TEST=TRUE

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

I1187

I1188

I1189

I1190

I1192

I1191

USB3_EXTD_TX_P

USB3_EXTD_TX_N

USB3_EXTD_RX_P

USB3_EXTD_RX_N

USB_EXTD_EHCI_P

USB_EXTD_EHCI_N

USB3_EXTC_TX_P

USB3_EXTC_TX_N

USB3_EXTC_RX_P

USB3_EXTC_RX_N

USB_EXTC_P

USB_EXTC_N

Apple Inc.

R

CPU_VTTSELECT

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_B_DATA_N<2..0>

LVDS_IG_B_DATA_P<2..0>

LVDS_IG_DDC_CLK

LVDS_IG_DDC_DATA

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_B_MLN<3..0>

R0950

0

1 2

1/8W

MF-LF

5%

805

=PP15V_TBT_REG

19

19 91

Signal Aliases

18

8

37

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

9 OF 132

SHEET

9 OF 99

124578

18 91

18

18 91

18

17

17 91

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PP1V05_S0_CPU_VCCIO

1

OMIT_TABLE

AC10

AA10

N10

R10

R8

U10

N8 T9

R6

U8

N4 R4

P1

U6

N2

R2 P3

T5

V7

W8

AA8

U4

W2

V1 Y5

W6

W10

Y9

U2 W4

V3

AA6

AC8

AA2

AD9

AB3

AB7

AG2

AF1 AE6

AG6

AG4

AF3 AF7

AG8

AE4

AE2

AB1

AC2

AE8

DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3*

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX0* FDI0_TX1* FDI0_TX2* FDI0_TX3*

FDI1_TX0* FDI1_TX1* FDI1_TX2* FDI1_TX3*

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3

FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_LSYNC FDI0_LSYNC

EDP_TX0* EDP_TX1* EDP_TX2* EDP_TX3*

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_AUX EDP_AUX*

EDP_ICOMPO EDP_COMPIO

EDP_HPD*

DMI_S2N_N<0>

18 89

IN

DMI_S2N_N<1>

18 89

IN

DMI_S2N_N<2>

18 89

IN

DMI_S2N_N<3>

18 89

IN

DMI_S2N_P<0>

18 89

IN

DMI_S2N_P<1>

18 89

IN

DMI_S2N_P<2>

18 89

D

C

=PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

1

OMIT_TABLE

B

82

1

R1031

1K

5% 1/16W MF-LF

402

2

DP_INT_IG_HPD

IN

R1030

24.9

1% 1/16W MF-LF 402

2

PLACE_NEAR=U1000.AB1:12.7mm

IN

DMI_S2N_P<3>

18 89

IN

DMI_N2S_N<0>

18 89

OUT

DMI_N2S_N<1>

18 89

OUT

DMI_N2S_N<2>

18 89

OUT

DMI_N2S_N<3>

18 89

OUT

DMI_N2S_P<0>

18 89

OUT

DMI_N2S_P<1>

18 89

OUT

DMI_N2S_P<2>

18 89

OUT

DMI_N2S_P<3>

18 89

OUT

FDI_DATA_N<0>

9

89

OUT

FDI_DATA_N<1>

9

89

OUT

FDI_DATA_N<2>

9

89

OUT

FDI_DATA_N<3>

9

89

OUT

FDI_DATA_N<4>

9

89

OUT

FDI_DATA_N<5>

9

89

OUT

FDI_DATA_N<6>

9

89

OUT

FDI_DATA_N<7>

9

89

OUT

FDI_DATA_P<0>

9

89

OUT

FDI_DATA_P<1>

9

89

OUT

FDI_DATA_P<2>

9

89

OUT

FDI_DATA_P<3>

9

89

OUT

FDI_DATA_P<4>

9

89

OUT

FDI_DATA_P<5>

9

89

OUT

FDI_DATA_P<6>

9

89

OUT

FDI_DATA_P<7>

9

89

OUT

FDI_FSYNC<0>

9

89

IN

FDI_FSYNC<1>

9

89

IN

FDI_INT

18 89

IN

FDI_LSYNC<1>

9

89

IN

FDI_LSYNC<0>

9

89

IN

DP_INT_IG_ML_N<0>

82 89

OUT

DP_INT_IG_ML_N<1>

82 89

OUT

DP_INT_IG_ML_N<2>

82 89

OUT

DP_INT_IG_ML_N<3>

82 89

OUT

DP_INT_IG_ML_P<0>

82 89

OUT

DP_INT_IG_ML_P<1>

82 89

OUT

DP_INT_IG_ML_P<2>

82 89

OUT

DP_INT_IG_ML_P<3>

82 89

OUT

DP_INT_IG_AUX_P

82 89

BI

DP_INT_IG_AUX_N

82 89

BI

CPU_EDP_COMP

89

DP_INT_IG_HPD_L

D

3

Q1031

1

2N7002TXG

G

SOT-523-3

EDP:YES

S

2

U1000

IVY-BRIDGE

BGA

(1 OF 11)

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

DMI

PEG_RX10* PEG_RX11* PEG_RX12* PEG_RX13* PEG_RX14* PEG_RX15*

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*

EMBEDDED DISPLAY PORT

PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5* PEG_RX6* PEG_RX7* PEG_RX8* PEG_RX9*

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8* PEG_TX9*

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

G2

H1

F3

F23

H23 H21

H19

J20 G18

K17 F15

H15

H13 H11

J12

E8 G10

J8

F7

G22 K23

K21

F19 K19

H17

K15 G14

J16

K13 F11

K11 F9

H9

H7 G6

A22 B23

C18

D21 B19

E20 A14

D17

B15 E16

D13

A10 B11

D9

B7 E12

C22

D23

A18 B21

D19

F21 C14

B17

D15 F17

B13 C10

D11

B9 D7

F13

CPU_PEG_COMP

89

=PEG_D2R_N<0>

=PEG_D2R_N<1> =PEG_D2R_N<2>

=PEG_D2R_N<3> =PEG_D2R_N<4>

=PEG_D2R_N<5>

=PEG_D2R_N<6> =PEG_D2R_N<7>

=PEG_D2R_N<8>

=PEG_D2R_N<9> =PEG_D2R_N<10>

=PEG_D2R_N<11>

=PEG_D2R_N<12> =PEG_D2R_N<13>

=PEG_D2R_N<14> =PEG_D2R_N<15>

=PEG_D2R_P<0> =PEG_D2R_P<1>

=PEG_D2R_P<2>

=PEG_D2R_P<3> =PEG_D2R_P<4>

=PEG_D2R_P<5>

=PEG_D2R_P<6> =PEG_D2R_P<7>

=PEG_D2R_P<8> =PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_P<11> =PEG_D2R_P<12>

=PEG_D2R_P<13>

=PEG_D2R_P<14> =PEG_D2R_P<15>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1>

=PEG_R2D_C_N<2> =PEG_R2D_C_N<3>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<5> =PEG_R2D_C_N<6>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<8> =PEG_R2D_C_N<9>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<11> =PEG_R2D_C_N<12>

=PEG_R2D_C_N<13> =PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<2> =PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<7> =PEG_R2D_C_P<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<10> =PEG_R2D_C_P<11>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_P<15>

R1010

24.9

1% 1/16W MF-LF 402

2

9

IN

9

IN

9

SIGNAL_MODEL=EMPTY

IN

1

TP

BEAD-PROBE

SM

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

SIGNAL_MODEL=EMPTY

IN

1

TP

BEAD-PROBE

SM

9

IN

1

TP

BEAD-PROBE

SM

9

IN

9

SIGNAL_MODEL=EMPTY

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

8

10 11 13 14 15

BP1004

BP1011 BP1012

NOTE:

Intel is investigating processor driven VREF_DQ generation. This connection is to support the same.

10 24 89

24 89

10 24 89

24 89

PPCPU_MEM_VREFDQ_B

33 89

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PPCPU_MEM_VREFDQ_A

33 89

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

CPU_CFG<0>

CPU_CFG<1> CPU_CFG<2>

CPU_CFG<3> CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

CPU_CFG<8>

CPU_CFG<9> CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

CPU_CFG<16>

CPU_CFG<17>

B57

(IPU)

D57

(IPU)

B55

(IPU)

A54

(IPU)

A58

(IPU)

D55

(IPU)

C56

(IPU)

E54

(IPU)

J54

(IPU)

G56

(IPU)

CFG

F55

(IPU)

K55

(IPU)

F57

(IPU)

E58

(IPU)

H57

(IPU)

H55

(IPU)

D53

(IPU)

K57

(IPU)

G64

NC

BJ42

NC

BJ34

NC

BJ22

NC

BH43

NC

BH35

NC

BH25

NC

BH23

NC

BH21

NC

BH19

NC

BG62

NC

BG34

NC

BG26

NC

BG22

NC

BG4

(DDR_VREF1)

BF63

NC

BF43

NC

BF41

BF35 BF25

BF23

BF21 BF19

BE32

BE16

BD33

BD29

BD19 BD15

BD13

BC42 BC30

BC14

RSVD

BF3

(DDR_VREF0)

BE6

NC NC NC NC NC NC

NC NC NC NC NC NC NC NC NC NC NC

U1000

IVY-BRIDGE

BGA

(5 OF 11)

RESERVED

OMIT_TABLE

(THERMDA)

(THERMDC)

RSVD

BB57

BB43 BB25

BB17

BB15 BB13

BA48

BA16 AY45

AY41 AY17

AY15

AY13 AW50

AW46

AW42 AW14

AJ10

AJ6 AH5

AD5 AC6

AC4

AA4 P7

N6

M9 M5

L10

L6 L4

L2 K49

K47

K9 K7

K5

J50 J4

J2

H49 H47

H5 G52

G48

G4 F5

D49

D25 D3

C52

C24 C4

B53 B25

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

12

D

C

B

CPU_CFG<7>

10 24 89

CPU_CFG<6>

10 24 89

CPU_CFG<5>

10 24 89

CPU_CFG<4>

10 24 89

CPU_CFG<2>

10 24 89

A

CPU_CFG<4> should be pulled down to enable EDP

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

NOSTUFF

R1042

EDP:YES

1

R1044

1K

5%

1/16W

MF-LF

402

2

1

R1045

1K

5%

1/16W MF-LF

402

2

R1046

NOSTUFF

1

R1047

1K

5%

1/16W

MF-LF

402

2

CPU_CFG<16>

10 24 89

CPU_CFG<3>

10 24 89

CPU_CFG<1>

10 24 89

CPU_CFG<0>

10 24 89

NOSTUFF

These can be Placed close to J2500 and Only for debug access

R1040

NOSTUFF

1

1K

5% 1/16W MF-LF

402

2

R1041

NOSTUFF

1

R1043

1K

5% 1/16W MF-LF

402

1K

5% 1/16W MF-LF

402

2

PART NUMBER

116S0066

116S0090

NOSTUFF

1

2

R1049

1

1K

5% 1/16W MF-LF

402

2

QTY

1

DESCRIPTION

RES,MTL FILM,1/16W,1K,0402,SMD,LF

RES,MTL FILM,1/16W,10K,0402,SMD,LF

REFERENCE DES

R1031

CRITICAL

BOM OPTION

EDP:YES

EDP:NO

6 3

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

10 OF 132

SHEET

10 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

=PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

1

R1101

68

5%

1/16W

MF-LF

402

2

CPU_PROC_SEL_L

20 89

R1103

C

8

10 11 13 14 15

CPU_PROCHOT_L

41 42 65 89

BI

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

24 25

IN

=PP1V5_S3_CPU_VCCDDR

8

11 14 16 27

PLACE_NEAR=R1121.2:1mm

R1126

1/16W MF-LF

1

75

1%

402

2

R1120

PM_MEM_PWRGD

18 27 89

B

R1120 and R1121 are Intel recommended values

IN

=PP1V5_S3_CPU_VCCDDR

8

11 14 16 27

PLACE_NEAR=U1000.BJ44:2.54mm

R1130

1/16W MF-LF

1

1K

1%

402

2

56

12

5% 1/16W MF-LF

402

1

200

1% 1/16W MF-LF

402

R1121

2

130

1% 1/16W MF-LF

PLACE_NEAR=U1000.AY25:51.562mm

402

R1125

43.2

12

1% 1/16W MF-LF

402

12

PLACE_NEAR=U1000.BJ46:12.7mm

41 89

20 42 89

PLT_RESET_LS1V1_L

18 89

20 24 89

27

OUT

1

R1112

140

1% 1/16W MF-LF 402

2

PLACE_NEAR=U1000.BG46:12.7mm

OUT

BI

OUT

IN

PM_MEM_PWRGD_R

=MEM_RESET_L

CPU_DDR_VREF

1

R1113

25.5

1% 1/16W MF-LF 402

2

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

PM_SYNC

CPU_PWRGD

1

2

R1114

200

1% 1/16W MF-LF 402

NOSTUFF

1

R1100

1K

5%

1/20W

MF

201

2

CPU_SM_RCOMP<0>

89

CPU_SM_RCOMP<1>

89

CPU_SM_RCOMP<2>

89

PLACE_NEAR=U1000.BF45:12.7mm

1

2

R1104

51

5% 1/16W MF-LF 402

NOSTUFF

1

R1102

1K

5% 1/20W MF 201

2

NC

1

R1111

10K

5%

PLACE_NEAR=U1800.AY11:157mm

1/16W MF-LF 402

2

OMIT_TABLE

B59

PROC_DETECT*

AH9

PROC_SELECT*

H53

CATERR*

F53

PECI

H51

PROCHOT*

F51

THERMTRIP*

K51

RESET*

K53

PM_SYNC

C60

UNCOREPWRGOOD

AY25

SM_DRAMPWROK

BE24

SM_DRAMRST*

BJ44

SM_VREF

BJ46

SM_RCOMP0

BG46

SM_RCOMP1

BF45

SM_RCOMP2

U1000

IVY-BRIDGE

BGA

(2 OF 11)

THERMAL

PWR MGMT

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

CLOCKS

(IPU)

(IPD)

(IPU)

JTAG & BPM

(IPU)

BCLK_ITP

BCLK_ITP*

BCLK

BCLK*

PRDY* PREQ*

TRST*

DBR*

BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7*

TCK TMS

TDI TDO

AJ4 AJ2

K63 K65

D5

C6

J62

H65

J58

H59

H63

K61 K59

H61

C62

D61 E62

F63

D59 F61

F59 G60

DPLL_REF_CLKP

DPLL_REF_CLKN

ITPCPU_CLK100M_P

ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

XDP_CPU_TMS XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3> XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6> XDP_BPM_L<7>

9

89

IN

9

89

IN

17 89

IN

17 89

IN

17 89

IN

17 89

IN

24 89

OUT

24 89

IN

24 89

IN

24 89

IN

24 89

IN

24 89

IN

24 89

OUT

24 25 89

OUT

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

D

C

B

1

R1131

1K

PLACE_NEAR=U1000.BJ44:2.54mm

1% 1/16W MF-LF

402

PLACE_NEAR=U1000.BJ44:2.54mm

A

1

C1130

0.1UF

10%

16V

2

X7R-CERM

2

0402

SIZE

A

D

6 3

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

11 OF 132

SHEET

11 OF 99

124578

8 7 6 5 4 3

12

SA_CLK0

SA_CKE0

SA_CLK1

SA_CKE1

SA_CS0* SA_CS1*

SA_ODT0 SA_ODT1

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

BB31

BA32

BC18

AW34

AY33

BD17

BD41

BD45

BB41

BC46

AN8

AU6

BC6 BD9

BC50 BB55

BD59

AU60

AN6

AU8 BD5

BC10

BB51 BD55

BD61 AV61

BD27 BA28

BB27

AW26 BB23

BA24

AY21 BD21

BC22 BB21

AW38

AW22 BA20

BB45

BE20 AW18

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1> MEM_A_DQS_N<2>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4> MEM_A_DQS_N<5>

MEM_A_DQS_N<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_DQS_P<5>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_A<0> MEM_A_A<1>

MEM_A_A<2> MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8> MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<13> MEM_A_A<14>

MEM_A_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

28 32 90

29 32 90

28 32 90

29 32 90

28 32 90

29 32 90

28 29 90

28 29 32 90

SB_CLK0

SB_CKE0

SB_CLK1

SB_CKE1

SB_CS0* SB_CS1*

SB_ODT0 SB_ODT1

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BF33

BH33

BD25

BF37

BH37

BJ26

BE40

BH41

BG42

BH45

AN4

AW2

BH9 BF15

BF51 BH57

AY63

AN62

AN2

AW4 BF9

BH15

BH51 BF57

AY65 AN64

BF31 BH31

BB37

BC34 BF27

BB33

BH27 BG30

BH29 BF29

AY37

BJ30 AW30

BA40

BB29 BE28

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQS_N<0>

MEM_B_DQS_N<1> MEM_B_DQS_N<2>

MEM_B_DQS_N<3>

MEM_B_DQS_N<4> MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_P<3> MEM_B_DQS_P<4>

MEM_B_DQS_P<5>

MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1>

MEM_B_A<2> MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5> MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8> MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11> MEM_B_A<12>

MEM_B_A<13> MEM_B_A<14>

MEM_B_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

30 32 90

31 32 90

30 32 90

31 32 90

30 32 90

31 32 90

30 31 90

30 31 32 90

D

C

B

BF11 BJ10

BH11

BG10 BJ14

BG14

BF17 BJ18

BF13

BH13 BH17

BG18 BH49

BF47

BH53 BG50

BF49

BH47 BF53

BJ50

BF55 BH55

BJ58 BH59

BJ54

BG54 BG58

BF59

BA64 BC62

AU62

AW64 BA62

BC64 AU64

AW62

AR64 AT65

AL64

AM65 AR62

AT63

AL62 AM63

BJ38

BD37

AY29

BH39

BG38 BF39

AL4

AK3 AP3

AR2

AL2 AK1

AP1

AR4 AV3

AU4 BA4

BB1

AV1 AU2

BA2

BB3 BC2

BF7

BC4 BH7

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS* SB_RAS* SB_WE*

U1000

IVY-BRIDGE

BGA

(4 OF 11)

OMIT_TABLE

MEMORY CHANNEL B

SB_CLK0*

SB_CLK1*

SB_DQS0* SB_DQS1* SB_DQS2* SB_DQS3* SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7*

MEM_B_DQ<0>

30 31 90

BI

MEM_B_DQ<1>

30 31 90

BI

MEM_B_DQ<2>

30 31 90

BI

MEM_B_DQ<3>

30 31 90

BI

MEM_B_DQ<4>

30 31 90

BI

MEM_B_DQ<5>

30 31 90

BI

MEM_B_DQ<6>

30 31 90

BI

MEM_B_DQ<7>

30 31 90

BI

MEM_B_DQ<8>

30 31 90

BI

MEM_B_DQ<9>

30 31 90

BI

MEM_B_DQ<10>

30 31 90

BI

MEM_B_DQ<11>

30 31 90

BI

MEM_B_DQ<12>

30 31 90

BI

MEM_B_DQ<13>

30 31 90

BI

MEM_B_DQ<14>

30 31 90

BI

MEM_B_DQ<15>

30 31 90

BI

MEM_B_DQ<16>

30 31 90

BI

MEM_B_DQ<17>

30 31 90

BI

MEM_B_DQ<18>

30 31 90

BI

MEM_B_DQ<19>

30 31 90

BI

MEM_B_DQ<20>

30 31 90

BI

MEM_B_DQ<21>

30 31 90

BI

MEM_B_DQ<22>

30 31 90

BI

MEM_B_DQ<23>

30 31 90

BI

MEM_B_DQ<24>

30 31 90

BI

MEM_B_DQ<25>

30 31 90

BI

MEM_B_DQ<26>

30 31 90

BI

MEM_B_DQ<27>

30 31 90

BI

MEM_B_DQ<28>

30 31 90

BI

MEM_B_DQ<29>

30 31 90

BI

MEM_B_DQ<30>

30 31 90

BI

MEM_B_DQ<31>

30 31 90

BI

MEM_B_DQ<32>

30 31 90

BI

MEM_B_DQ<33>

30 31 90

BI

MEM_B_DQ<34>

30 31 90

BI

MEM_B_DQ<35>

30 31 90

BI

MEM_B_DQ<36>

30 31 90

BI

MEM_B_DQ<37>

30 31 90

BI

MEM_B_DQ<38>

30 31 90

BI

MEM_B_DQ<39>

30 31 90

BI

MEM_B_DQ<40>

30 31 90

BI

MEM_B_DQ<41>

30 31 90

BI

MEM_B_DQ<42>

30 31 90

BI

MEM_B_DQ<43>

30 31 90

BI

MEM_B_DQ<44>

30 31 90

BI

MEM_B_DQ<45>

30 31 90

BI

MEM_B_DQ<46>

30 31 90

BI

MEM_B_DQ<47>

30 31 90

BI

MEM_B_DQ<48>

30 31 90

BI

MEM_B_DQ<49>

30 31 90

BI

MEM_B_DQ<50>

30 31 90

BI

MEM_B_DQ<51>

30 31 90

BI

MEM_B_DQ<52>

30 31 90

BI

MEM_B_DQ<53>

30 31 90

BI

MEM_B_DQ<54>

30 31 90

BI

MEM_B_DQ<55>

30 31 90

BI

MEM_B_DQ<56>

30 31 90

BI

MEM_B_DQ<57>

30 31 90

BI

MEM_B_DQ<58>

30 31 90

BI

MEM_B_DQ<59>

30 31 90

BI

MEM_B_DQ<60>

30 31 90

BI

MEM_B_DQ<61>

30 31 90

BI

MEM_B_DQ<62>

30 31 90

BI

MEM_B_DQ<63>

30 31 90

BI

MEM_B_BA<0>

30 31 32 90

OUT

MEM_B_BA<1>

30 31 32 90

OUT

MEM_B_BA<2>

30 31 32 90

OUT

MEM_B_CAS_L

30 31 32 90

OUT

MEM_B_RAS_L

30 31 32 90

OUT

MEM_B_WE_L

30 31 32 90

OUT

AL10

AN10

AR10

AW12

AV11

BB11 BA12

BA10 BD11

BE12 BB49

AY49

BE52 BD51

BD49

BE48 BA52

AY51

BC54 AY53

AW54 AY55

BD53

BB53 BE56

BA56

BD57 BF61

BA60

BB61 BE60

BD63 BB59

BC58

AW58 AY59

AL60

AP61 AW60

AY57

AN60 AR60

BA36

BC38

BB19

BE44

BE36 BA44

AL6

AL8 AP7

AM5

AK7

AM9

AR8 AV7

AY5

AT5 AR6

AW6

AT9 BA6

BA8

BG6 AY9

AW8 BB7

BC8

BE4

BE8

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS* SA_RAS* SA_WE*

U1000

IVY-BRIDGE

BGA

(3 OF 11)

OMIT_TABLE

MEMORY CHANNEL A

SA_CLK0*

SA_CLK1*

SA_DQS0* SA_DQS1* SA_DQS2* SA_DQS3* SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7*

MEM_A_DQ<0>

28 29 90

BI

MEM_A_DQ<1>

28 29 90

BI

MEM_A_DQ<2>

28 29 90

BI

MEM_A_DQ<3>

28 29 90

BI

MEM_A_DQ<4>

28 29 90

D

C

B

BI

MEM_A_DQ<5>

28 29 90

BI

MEM_A_DQ<6>

28 29 90

BI

MEM_A_DQ<7>

28 29 90

BI

MEM_A_DQ<8>

28 29 90

BI

MEM_A_DQ<9>

28 29 90

BI

MEM_A_DQ<10>

28 29 90

BI

MEM_A_DQ<11>

28 29 90

BI

MEM_A_DQ<12>

28 29 90

BI

MEM_A_DQ<13>

28 29 90

BI

MEM_A_DQ<14>

28 29 90

BI

MEM_A_DQ<15>

28 29 90

BI

MEM_A_DQ<16>

28 29 90

BI

MEM_A_DQ<17>

28 29 90

BI

MEM_A_DQ<18>

28 29 90

BI

MEM_A_DQ<19>

28 29 90

BI

MEM_A_DQ<20>

28 29 90

BI

MEM_A_DQ<21>

28 29 90

BI

MEM_A_DQ<22>

28 29 90

BI

MEM_A_DQ<23>

28 29 90

BI

MEM_A_DQ<24>

28 29 90

BI

MEM_A_DQ<25>

28 29 90

BI

MEM_A_DQ<26>

28 29 90

BI

MEM_A_DQ<27>

28 29 90

BI

MEM_A_DQ<28>

28 29 90

BI

MEM_A_DQ<29>

28 29 90

BI

MEM_A_DQ<30>

28 29 90

BI

MEM_A_DQ<31>

28 29 90

BI

MEM_A_DQ<32>

28 29 90

BI

MEM_A_DQ<33>

28 29 90

BI

MEM_A_DQ<34>

28 29 90

BI

MEM_A_DQ<35>

28 29 90

BI

MEM_A_DQ<36>

28 29 90

BI

MEM_A_DQ<37>

28 29 90

BI

MEM_A_DQ<38>

28 29 90

BI

MEM_A_DQ<39>

28 29 90

BI

MEM_A_DQ<40>

28 29 90

BI

MEM_A_DQ<41>

28 29 90

BI

MEM_A_DQ<42>

28 29 90

BI

MEM_A_DQ<43>

28 29 90

BI

MEM_A_DQ<44>

28 29 90

BI

MEM_A_DQ<45>

28 29 90

BI

MEM_A_DQ<46>

28 29 90

BI

MEM_A_DQ<47>

28 29 90

BI

MEM_A_DQ<48>

28 29 90

BI

MEM_A_DQ<49>

28 29 90

BI

MEM_A_DQ<50>

28 29 90

BI

MEM_A_DQ<51>

28 29 90

BI

MEM_A_DQ<52>

28 29 90

BI

MEM_A_DQ<53>

28 29 90

BI

MEM_A_DQ<54>

28 29 90

BI

MEM_A_DQ<55>

28 29 90

BI

MEM_A_DQ<56>

28 29 90

BI

MEM_A_DQ<57>

28 29 90

BI

MEM_A_DQ<58>

28 29 90

BI

MEM_A_DQ<59>

28 29 90

BI

MEM_A_DQ<60>

28 29 90

BI

MEM_A_DQ<61>

28 29 90

BI

MEM_A_DQ<62>

28 29 90

BI

MEM_A_DQ<63>

28 29 90

BI

MEM_A_BA<0>

28 29 32 90

OUT

MEM_A_BA<1>

28 29 32 90

OUT

MEM_A_BA<2>

28 29 32 90

OUT

MEM_A_CAS_L

28 29 32 90

OUT

MEM_A_RAS_L

28 29 32 90

OUT

MEM_A_WE_L

28 29 32 90

OUT

A

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

12 OF 132

SHEET

12 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

PLACE_NEAR=U1000.B47:50.8mm

B

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.A46:50.8mm

PLACE_SIDE=BOTTOM

D

=PP3V3_S0_CPU_VCCIO_SEL

For Future Compatibility

1

R1320

10K

5% 1/16W MF-LF

=PPVCCSA_S0_CPU

8

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=R1310.1:2.54mm

1

R1300

75

1% 1/16W MF-LF 402

8

13 15 45 98

8

10 11 13 14 15

PLACE_SIDE=BOTTOM

2

402 1/16W

NOSTUFF

1 2

1/16W402

0

1 2

0

1 2

8

13 14

16

R1364

49.9

1%

1/20W

MF

201

R1365

49.9

1%

1/20W

MF

201

CPU_VIDSOUT

65 89

BI

CPU_VIDSCLK

65 89

OUT

CPU_VIDALERT_L

65 89

IN

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AW10:50.8mm

NOSTUFF

1

R1360

100

5% 1/16W MF-LF

402

2

65 89

OUT

65 89

OUT

65 89

OUT

65 89

OUT

67 89

OUT

67 89

OUT

1

R1361

100

5% 1/16W MF-LF

402

2

1

R1362

100

1% 1/16W MF-LF 402

R1363

100

1% 1/16W MF-LF 402

R1366

100

1%

NOSTUFF

1/16W MF-LF 402

2

PLACE_NEAR=U1000.F49:50.8mm

PLACE_NEAR=U1000.E50:50.8mm

PLACE_SIDE=BOTTOM

1

R1367

100

1% 1/16W MF-LF 402

2

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AU10:50.8mm

NOSTUFF

R1312

R1311

R1310

43

1

2

1

2

1

2

1

2

8

10 11 13 14 15

=PP1V05_S0_CPU_VCCIO

1

R1302

130

1% 1/16W MF-LF 402

2

MF-LF5%

5%402 1/16W MF-LF

5% MF-LF

PLACE_NEAR=U1000.B51:38mm

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_VCCAXG=PPVCORE_S0_CPU_VCCAXG

PLACE_SIDE=BOTTOM

NOSTUFF

R1370

49.9

1% 1/20W MF 201

62 89

OUT

R1371

PLACE_SIDE=BOTTOM

49.9

1%

NOSTUFF

1/20W MF 201

PLACE_NEAR=U1000.A50:2.54mm

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VIDALERT_L_R

=PPVCCSA_S0_CPU

1

R1368

100

1% 1/16W MF-LF 402

2

8

13 15 45 98

8

13 14 16

8 16

8

10 11 13 14 15

13

62 89

OUT

62 89

OUT

13 16

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

TP_CPU_VDDQSENSEP

TP_CPU_VDDQSENSEN

CPU_VCCSASENSE

TP_CPU_DIE_SENSE

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

R1314

VCCDQ

VCCPLL

VCCPQE

AJ8

AV23

AT23 AP23

AL23

AK65

AK63

AK61

AV21

AT21 AP21

AL21

BJ60

BJ6 BH61

BH5

BE64 BE2

BD65

BD1 F65

F1 E64

E2

B61 B5

A60

A6

A4

A62 A64

B3 B63

B65

BF1 BF65

BG2

BG64 BH1

BH3

BH63 BH65

BJ2 BJ4

BJ62

BJ64 C2

C64

D1 D65

CPU_VCCIO_SEL

TP_DC_TEST_A4

TP_DC_TEST_A62 DC_TEST_B63_A64

DC_TEST_B3_C2

DC_TEST_B65_C64

TP_DC_TEST_BF1

TP_DC_TEST_BF65 DC_TEST_BH1_BG2

DC_TEST_BG64_BH65

DC_TEST_BH3_BJ2

DC_TEST_BJ64_BH63

TP_DC_TEST_BJ4 TP_DC_TEST_BJ62

TP_DC_TEST_D1

TP_DC_TEST_D65

W17

W15 W12

U17 U15

U12

T16 T14

T11

N18

VCCSA

N16

N14

M17 M15

M12 M11

L18

L14

A50

VIDSOUT

D51

VIDSCLK

B51

VIDALERT*

AE10

VCCSA_VID0

AG10

VCCSA_VID1

B47

VCC_SENSE

A46

VSS_SENSE

F49

VAXG_SENSE

E50

VSSAXG_SENSE

AW10

VCCIO_SENSE

AU10

VSS_SENSE_VCCIO

AY19

VDDQ_SENSE

AW20

VSS_SENSE_VDDQ

K3

VCCSA_SENSE

F47

VCC_DIE_SENSE

D47

VCC_VAL_SENSE

C48

VSS_VAL_SENSE

B49

VAXG_VAL_SENSE

A48

VSSAXG_VAL_SENSE

1

R1313

10K

5% 1/16W MF-LF

402

5% 1/16W MF-LF 402

2

U1000

IVY-BRIDGE

BGA

(9 OF 11)

OMIT_TABLE

VCCIO_SEL

VSS_NCTF

DC_TEST_A4 DC_TEST_A62 DC_TEST_A64

DC_TEST_B3 DC_TEST_B63 DC_TEST_B65 DC_TEST_BF1

DC_TEST_BF65

DC_TEST_BG2

DC_TEST_BG64

DC_TEST_BH1 DC_TEST_BH3

DC_TEST_BH63 DC_TEST_BH65

DC_TEST_BJ2 DC_TEST_BJ4

DC_TEST_BJ62 DC_TEST_BJ64

DC_TEST_C2 DC_TEST_C64

DC_TEST_D1 DC_TEST_D65

402

2

=PP1V5_S3_CPU_VCCDQ

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

8

16

8

15

8

15

=PPVCORE_S0_CPU

8

13 15 45 98

R46 R42

R40

R36 R34

R29

R27 G38 R23

R21 N45

N43

N39 N37

N33

N30 N26

N24

N20 M46

M42 M40

M36

M34 M29

M27

M23 M21

L44

VCC VCC

L40 L38

L34 L32

L28

L26 L22

K45

K43 K41

K37

K35 K31

K29 K25

J44

J40 J38

J34

J32 J28

J26

H45 H43

H41 H37

U1000

IVY-BRIDGE

BGA

(6 OF 11)

CORE POWER

OMIT_TABLE

=PPVCORE_S0_CPU

H35 H31

H29

H25 G44

G40

G34

G32 G28

G26

F45 F43

F41

F37 F35

F31

F29 F25

E44 E40

E38

E34 E32

E28

E26 D45

D43

D41 D37

D35 D31

D29

C44 C40

C38

C34 C32

C28

C26 B45

B43 B41

B37

B35 B31

B29

A44 A40

A38

A34 A32

A28 A26

8

13 15 45 98

C

B

NOTE: Intel validation sense lines per doc 439028 rev1.0

HR_PPDG sections 6.2.1 and 6.3.1.

A

SYNC_MASTER=D2_KEPLER

PAGE TITLE

CPU POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

13 OF 132

SHEET

13 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

BJ56

BJ52 BJ48

BJ40

BJ32 BJ24

BJ20

BJ16

D

C

B

BJ12

BG60 BG56

BG52 BG48

BG44

BG36 BG28

BG24

BG20 BG16

BG12

BE62 BE58

BE54

BE50 BE46

BE42

BE38 BE34

BE30

BE26 BE22

BE18 BE14

BE10

BD35

BC60 BC56

BC52

BC48 BC44

BC40 BC36

BC32

BC28 BC26

BC24

BC20 BC16

BC12

BB65 BB63

BB47 BB39

BA58

BA54

BA50 BA46

BA42

BA38 BA34

BA30 BA26

BA22

BA18 BA14

AY61

AY11

AW56

AW52 AW48

AW44

AW40 AW36

AW32

AW28 AW24

BJ8

BG8 BF5

BD7

BD3

BB9

BB5

AY7

AY3

AY1

U1000

IVY-BRIDGE

BGA

(10 OF 11)

OMIT_TABLE

AW16

AV65 AV63

AV59

AV57 AV50

AV44

AV38 AV31

AV25

AV19 AV9

AV5 AU54

AU47

AU41 AU35

AU28

AU22 AU16

AU14

AT61 AT57

AT50 AT44

AT38

AT31 AT25

AT19

AT11 AT7

AT3

AT1 AR54

AR47 AR41

AR35

AR28 AR22

AP65

AP63 AP57

AP50

AP44

VSSVSS

AP38

AP31 AP25

AP19

AP17 AP15

AP12

AP11 AP9

AP5

AN54 AN47

AN41 AN35

AN28

AN22 AM61

AM7

AM3 AM1

AL57

AL50 AL44

AL38 AL31

AL25

AL19 AK16

AK14

AK11 AK9

AK5

AJ64 AJ62

AJ60 AJ57

AH7

AH3 AH1

AG57

AG17 AG15

AG12

AF65 AF63

AF61

AF11

AE57 AD16

AD14

AC64

AC62

AC60 AC57

AB11

AA57

AA17 AA15

AA12

U1000

IVY-BRIDGE

BGA

(11 OF 11)

AF9

AF5

AD7 AD3

AD1

AB9 AB5

Y65

Y63

Y61

Y7

Y3

Y1 W57

V16

V14 V11

V9

V5

U64

U62 U60

U57

T7

T3

T1

R57 R50

R44 R38

R31

R25 R19

R17

R15 R12

P65

P63 P61

P11

P9

P5

N54 N47

N41

N35 N28

N22

M57 M50

M44 M38

M31

M25 M19

M7

M3

M1

L64

L62 L60

L58 L54

L50

L46 L42

L36

L30 L24

OMIT_TABLE

A

6 3

L20

L16 L12

L8

K39 K33

K27

K1 J64

J60

J56 J52

J48 J46

J42

J36 J30

J24

J22 J18

J14

J10 J6

H39 H33

H27

H3 G62

G58

G54 G50

G46

G42 G36

G30 G24

G20

G16 G12

G8

VSSVSS

F39 F33

F27

E60 E56

E52 E48

E46

E42 E36

E30

E24 E22

E18

E14 E10

E6 E4

D63

D39 D33

D27

C58 C54

C50

C46 C42

C36 C30

C20

C16 C12

C8

B39 B33

B27

A56 A52

A42 A36

A30

A24 A20

A16

A12 A8

=PPVCORE_S0_CPU_VCCAXG

8

13 16

AH65

AH63 AH61

AH58

AH56 AG64

AG62

AG60 AF58

AF56

AE64 AE62

AE60 AD65

AD63

AD61 AD58

AD56

AB65 AB63

AB61

AB58 AB56

AA64 AA62

AA60

=PP1V5_S3_CPU_VCCDDR

VDDQ

BJ36

BJ28 BG40

BG32

BD47 BD43

BD39

BD31 BD23

BB35

AY47 AY43

AY39 AY35

AY31

AY27 AY23

AV46

AV42 AV40

AV36

AV34 AV29

AV27 AU45

AU43

AU39 AU37

AU33

AU30 AU26

AU24

AT46 AT42

AT40 AT36

AT34

AT29 AT27

AR45

AR43 AR39

AR37

AR33 AR30

AR26 AR24

AP46

AP42 AP40

AP36

AP34 AP29

AP27

AN45 AN43

AN39 AN37

AN33

AN30 AN26

AN24

AL46 AL42

AL40

AL36 AL34

AL29 AL27

U1000

IVY-BRIDGE

BGA

(8 OF 11)

OMIT_TABLE

Y58 Y56

W64

W62 W60

V65

V63

VAXG

V61

V58 V56

T65

T63 T61

T58

T56 R64

R62

R60 R55

R53 R48

N64

N62 N60

N58

N56 N52

N49

M65 M63

M61 M59

M55

M53 M48

L56

L52 L48

GRAPHIC CORE POWER

IO POWER DDR3

8

11 16 27

=PP1V05_S0_CPU_VCCIO =PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

AV55 AV53

AV48

AV17 AV15

AV12 AU58

AU56

AU52 AU49

AU20

AU18 AT55

AT53

AT48 AT17

AT15 AT12

AR58

AR56 AR52

AR49

AR20 AR18

AR16

AR14 AP55

AP53 AP48

AN58

AN56 AN52

AN49

U1000

IVY-BRIDGE

BGA

(7 OF11) IO POWER

OMIT_TABLE

AN20 AN18

AN16

AN14 AM11

AL55 AL53

AL48

AL17 AL15

AL12

AK58 AK56

AJ17

AJ15 AJ12

AH16

VCCIOVCCIO

AH14

AH11

AF16 AF14

AE17

AE15 AE12

AD11

AC17 AC15

AC12 AB16

AB14

Y16 Y14

Y11

8

10 11 13 14 15

PAGE TITLE

CPU POWER AND GND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

14 OF 132

SHEET

14 OF 99

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

CPU VCORE DECOUPLING

Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF) Apple Implementation: 8x 270uF 6mOhm, 0x 470uF 4mOhm , 16x 22uF 0402, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0402 (NOSTUFF)

=PPVCORE_S0_CPU

8

13 45 98

D

PLACEMENT_NOTE (C1600-C16C7):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1600

1UF

2

10% 10V X6S-CERM 0402

1

C1601

2

1UF

10% 10V X6S-CERM 0402

1

2

C1602

1UF

10% 10V X6S-CERM 0402

1

2

C1603

1UF

10% 10V X6S-CERM 0402

1

C1604

2

1UF

10% 10V X6S-CERM 0402

1

C1605

1UF

10% 10V

2

X6S-CERM 0402

1

2

C1606

1UF

10% 10V X6S-CERM 0402

1

C1607

1UF

2

10% 10V X6S-CERM 0402

1

C1608

2

1UF

10% 10V X6S-CERM 0402

1

C1609

1UF

10% 10V

2

X6S-CERM 0402

1

C1610

1UF

2

10% 10V X6S-CERM 0402

1

C1611

2

1UF

10% 10V X6S-CERM 0402

1

C1612

2

1UF

10% 10V X6S-CERM 0402

1

2

C1613

1UF

10% 10V X6S-CERM 0402

1

2

C1614

1UF

10% 10V X6S-CERM 0402

1

C1615

1UF

10% 10V

2

X6S-CERM 0402

1

C1616

1UF

10% 10V

2

X6S-CERM 0402

1

C1617

1UF

10% 10V

2

X6S-CERM 0402

1

C1618

2

1UF

10% 10V X6S-CERM 0402

1

C1619

2

1UF

10% 10V X6S-CERM 0402

D

NOSTUFF

1

C16A0

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C0

1UF

20% 4V

2

CERM-X6S 0201

PLACEMENT_NOTE (C1620-C1623): Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side. Place near U1000 on bottom side

Place near U1000 on bottom side

1

C1620

10UF

20% 4V

2

X6S 0402

C

PLACEMENT_NOTE (C1624-C16D5):

Place near inductors on bottom side.

CRITICAL

1

C1624

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16A1

2

NOSTUFF

1

C16C1

2

1

2

1

2

1UF

20% 4V CERM-X6S 0201

1UF

20% 4V CERM-X6S 0201

C1621

10UF

20% 4V X6S 0402

CRITICAL

C1625

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A2

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C2

1UF

20% 4V

2

CERM-X6S 0201

1

C1622

2

CRITICAL

1

C1626

2

10UF

20% 4V X6S 0402

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A3

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C3

1UF

20% 4V

2

CERM-X6S 0201

1

C1623

2

CRITICAL

1

C1627

2

10UF

20%

4V

X6S

0402

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A4

2

NOSTUFF

1

C16C4

2

1UF

20% 4V CERM-X6S 0201

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1628

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16A5

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C5

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

1

C1629

20UF

20% 2V

2

X6T-CERM 0402

1

2

1

2

NOSTUFF

C16A6

1UF

20% 4V CERM-X6S 0201

NOSTUFF

C16C6

1UF

20% 4V CERM-X6S 0201

CRITICAL

1

C1630

2

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A7

1UF

2

NOSTUFF

1

C16C7

1UF

2

20% 4V CERM-X6S 0201

1

2

CRITICAL

C1631

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A8

2

1UF

20% 4V CERM-X6S 0201

1

2

NOSTUFF CRITICAL

C1632

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A9

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF CRITICAL

1

C1633

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B0

1UF

2

20% 4V CERM-X6S 0201

CRITICAL

1

C1634

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B1

2

1UF

20% 4V CERM-X6S 0201

CRITICAL

1

C1635

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B2

2

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1690

20UF

20% 2V

2

X6T-CERM 0402

CRITICAL

1

C1636

20UF

20% 2V

2

X6T-CERM 0402

1

2

NOSTUFF

C16B3

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1691

20UF

20% 2V

2

X6T-CERM 0402

CRITICAL

1

C1637

20UF

20% 2V

2

X6T-CERM 0402

1

2

NOSTUFF

C16B4

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1698

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF CRITICAL

1

C1638

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B5

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

1

C1693

20UF

20% 2V

2

X6T-CERM 0402

CRITICAL

1

C1639

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B6

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

1

C1694

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D0

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B7

2

1UF

20% 4V CERM-X6S 0201

CRITICAL

1

C1695

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D1

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B8

2

1UF

20% 4V CERM-X6S 0201

1

C1696

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D2

20UF

2

20% 2V X6T-CERM 0402

NOSTUFF

1

C16B9

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

NOSTUFF CRITICAL

1

C1699

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D3

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D4

2

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16D5

20UF

20% 2V

2

X6T-CERM 0402

C

PLACEMENT_NOTE (C1640-C1645):

CRITICAL

1

C1640

270UF

20% 2V

2

TANT CASE-B2-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402 Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

PLACEMENT_NOTE (C1646-C1671):

Place on bottom side of U1000

Place on bottom side of U100.

=PP1V05_S0_CPU_VCCIO

8

10 11 13

B

14

Place on bottom side of U1000

1

C1646

1UF

10% 10V

2

X6S-CERM 0402

1

C1659

1UF

10% 10V

2

X6S-CERM 0402

1

C1647

2

1

C1660

2

CRITICAL

1

C1641

270UF

20% 2V

2

TANT CASE-B2-SM

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

1

2

1

2

CRITICAL

1

C1642

270UF

20% 2V

2

TANT CASE-B2-SM

C1648

1UF

10% 10V X6S-CERM 0402

C1661

1UF

10% 10V X6S-CERM 0402

1

2

1

C1662

2

1

2

C1649

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

CRITICAL

C1643

270UF

20% 2V TANT CASE-B2-SM

1

C1650

2

1

C1663

2

1

2

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

CRITICAL

C1644

270UF

20% 2V TANT CASE-B2-SM

1

C1651

1UF

10% 10V

2

X6S-CERM 0402

1

C1664

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1645

270UF

20% 2V

2

TANT CASE-B2-SM

1

2

1

C1665

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1688

270UF

20% 2V

2

TANT CASE-B2-SM

C1652

1UF

10% 10V X6S-CERM 0402

1

2

1

C1666

1UF

2

1

2

C1653

1UF

10% 10V X6S-CERM 0402

CRITICAL

C1689

270UF

20% 2V TANT CASE-B2-SM

1

C1654

2

1

C1667

2

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

1

C1655

1UF

10% 10V

2

X6S-CERM 0402

1

C1668

1UF

10% 10V

2

X6S-CERM 0402

1

2

1

C1669

1UF

2

C1656

1UF

10% 10V X6S-CERM 0402

1

2

1

C1670

2

C1657

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

1

2

1

C1671

2

C1658

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

=PP1V8_S0_CPU_VCCPLL

8

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

CPU VCCPLL DECOUPLING

R1600

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

1

2

C1685

1UF

10% 10V X6S-CERM 0402

1

C1686

1UF

10% 10V

2

X6S-CERM 0402

CPU VCCPLL Low pass filter

=PP1V8_S0_CPU_VCCPLL_R

PLACE_NEAR=U1000.AK61:5MM CRITICAL

1

C1687

220UF

20%

(Z = 1.2mm, place on short side behind CPU)

2.5V

2

TANT B16

8

13

B

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom side

1

C1672

10UF

20% 4V

2

X6S-CERM 0603

1

C1673

2

10UF

20% 4V X6S-CERM 0603

1

C1674

10UF

20% 4V

2

X6S-CERM 0603

1

C1675

2

10UF

20% 4V X6S-CERM 0603

1

C1676

10UF

20% 4V

2

X6S-CERM 0603

1

C1677

10UF

4V

2

20%

X6S-CERM 0603

1

C1678

2

10UF

20% 4V X6S-CERM 0603

1

C1679

2

10UF

20% 4V X6S-CERM 0603

1

C1680

10UF

20% 4V

2

X6S-CERM 0603

1

2

C1681

10UF

20% 4V X6S-CERM 0603

CRITICAL

1

C1682

330UF-6MOHM

20%

2.0V

23

A

POLY-TANT D15T-ECGLT-COMBO D15T-ECGLT-COMBO

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

1 2

1/4W

0603

1%

MF

=PP1V05_S0_CPU_VCCPQE

CRITICAL

1

C1683

330UF-6MOHM

20%

2.0V

23

POLY-TANT

1

C1684

1UF

10% 10V

2

X6S-CERM 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

8

13

6 3

SYNC_MASTER=D2_SEAN

PAGE TITLE

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

16 OF 132

SHEET

15 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

VAXG DECOUPLING

INTEL RECOMMENDATION: 2X 470UF 4MOHM, 2X 470UF 4MOHM (NOSTUFF), 6X 22UF 0805, 2X 22UF 0805 (NOSTUFF), 6X 10UF 0603, 2X 10UF 0603 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF) APPLE IMPLEMENTATION: 0X 470UF 4MOHM, 3X 330UF 9MOHM , 6X 22UF 0603, 2X 22UF 0603 (NOSTUFF), 6X 10UF 0402, 2X 10UF 0402 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)

=PPVCORE_S0_CPU_VCCAXG

8

13 14

D

PLACEMENT_NOTE (C1700-C1708):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1700

2

1UF

10% 10V X6S-CERM 0402

1

C1701

2

1UF

10% 10V X6S-CERM 0402

1

2

PLACEMENT_NOTE (C1718-C1723):

Place close to U1000 on bottom side

1

C1718

2

10UF

20% 4V X6S 0402

1

C1719

2

10UF

20% 4V X6S 0402

1

C1720

2

10UF

20% 4V X6S 0402

PLACEMENT_NOTE (C1726-C1731):

Place near inductors on bottom side.

1

C1726

2

22UF

20% 4V X6S 0603

1

C1727

2

22UF

20% 4V X6S 0603

1

2

PLACEMENT_NOTE (C1734-C1735):

C1702

1UF

10% 10V X6S-CERM 0402

C1728

22UF

20% 4V X6S 0603

1

2

1

C1721

10UF

2

1

2

C1703

1UF

10% 10V X6S-CERM 0402

20% 4V X6S 0402

C1729

22UF

20% 4V X6S 0603

1

C1704

2

1

C1722

2

1

2

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S 0402

C1730

22UF

20% 4V X6S 0603

1

C1705

2

1

C1723

2

1

2

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S 0402

C1731

22UF

20% 4V X6S 0603

1

2

1

C1724

2

C1706

1UF

10% 10V X6S-CERM 0402

NOSTUFF

10UF

20% 4V X6S 0402

NOSTUFF

1

C1732

22UF

20% 4V

2

X6S 0603

1

2

1

2

C1707

1UF

10% 10V X6S-CERM 0402

NOSTUFF

C1725

10UF

20% 4V X6S 0402

NOSTUFF

1

C1733

22UF

20% 4V

2

X6S 0603

1

C1708

2

1UF

10% 10V X6S-CERM 0402

NOSTUFF

1

C1709

1UF

2

10% 10V X6S-CERM 0402

NOSTUFF

1

C1710

1UF

10% 10V

2

X6S-CERM 0402

NOSTUFF

1

C1711

1UF

2

10% 10V X6S-CERM 0402

1

2

NOSTUFF

C1712

1UF

10% 10V X6S-CERM 0402

1

2

NOSTUFF

C1713

1UF

10% 10V X6S-CERM 0402

NOSTUFF

1

C1714

1UF

2

10% 10V X6S-CERM 0402

NOSTUFF

1

C1715

1UF

2

10% 10V X6S-CERM 0402

1

2

NOSTUFF

C1716

1UF

10% 10V X6S-CERM 0402

NOSTUFF

1

C1717

2

1UF

10% 10V X6S-CERM 0402

D

C

CRITICAL

1

C1734

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T

CRITICAL

1

C1735

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402 Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

=PP1V5_S3_CPU_VCCDDR

8

11 14 27

B

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1738

1UF

10% 10V

2

X6S-CERM 0402

Place close to U1000 on bottom side

1

C1748

10UF

20% 4V

2

X6S-CERM 0603

1

C1739

1UF

10% 10V

2

X6S-CERM 0402

1

C1749

10UF

20% 4V

2

X6S-CERM 0603

1

2

1

C1750

2

Place near inductors on bottom side

C1756

1

330UF-0.006OHM

20% 2V POLY

2

CASE-D2-SM

C1740

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S-CERM 0603

CRITICAL

1

C1737

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T

1

C1741

1UF

10% 10V

2

X6S-CERM 0402

1

C1751

10UF

20% 4V

2

X6S-CERM 0603

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

1

C1742

1UF

10% 10V

2

X6S-CERM 0402

1

C1752

10UF

20% 4V

2

X6S-CERM 0603

1

C1743

1UF

10% 10V

2

X6S-CERM 0402

1

C1753

10UF

20% 4V

2

X6S-CERM 0603

1

2

1

C1754

2

C1744

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S-CERM 0603

1

2

1

C1755

2

C1745

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S-CERM 0603

1

C1746

1UF

10% 10V

2

X6S-CERM 0402

1

C1747

2

1UF

10% 10V X6S-CERM 0402

=PPVCCSA_S0_CPU

8

13

CPU VCCSA DECOUPLING

Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402 Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

PLACEMENT_NOTE (C1758-C1762):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1758

1UF

10% 10V

2

X6S-CERM 0402

1

C1763

10UF

20% 4V

2

X6S-CERM 0603

CRITICAL

1

C1768

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T-ECGLT-COMBO

1

2

1

2

C1759

1UF

10% 10V X6S-CERM 0402

C1764

10UF

20% 4V X6S-CERM 0603

1

2

1

C1765

10UF

20% 4V

2

X6S-CERM 0603

C1760

1UF

10% 10V X6S-CERM 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

1

2

1

C1766

10UF

20% 4V

2

X6S-CERM 0603

C1761

1UF

10% 10V X6S-CERM 0402

1

C1762

1UF

10% 10V

2

X6S-CERM 0402

1

C1767

10UF

20% 4V

2

X6S-CERM 0603

C

B

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1700

0.010

1 2

1/4W

0603

1%

MF

=PP1V5_S3_CPU_VCCDQ

1

2

C1757

1UF

10% 10V X6S-CERM 0402

8

13

A

6 3

SYNC_MASTER=D2_SEAN

PAGE TITLE

CPU DECOUPLING-II

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

17 OF 132

SHEET

16 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

SYSCLK_CLK32K_RTC

25 91

IN

RTC_RESET_L

17

PCH_SRTCRST_L

17

PCH_INTRUDER_L

17

PCH_INTVRMEN_L

D

VSel strap not functional (VCCVRM = 1.8V)

C

17

HDA_BIT_CLK_R

17 92

HDA_SYNC_R

17 92

PCH_SPKR

17

HDA_RST_R_L

17 92

HDA_SDIN0

53 92

IN

TP_HDA_SDIN1

7

TP_HDA_SDIN2

7

TP_HDA_SDIN3

7

HDA_SDOUT_R

17 25 92

JTAG_ISP_TMS

20

OUT

ENET_MEDIA_SENSE_RDIV

17

IN

XDP_PCH_TCK

24

IN

XDP_PCH_TMS

24

IN

XDP_PCH_TDI

24

IN

XDP_PCH_TDO

24

OUT

SPI_CLK_R

43 92

OUT

SPI_CS0_R_L

43 92

OUT

TP_SPI_CS1_L

SPI_MOSI_R

43 92

OUT

SPI_MISO

43 92

IN

=PPVRTC_G3_PCH

1

330K

1/20W

1

R1801

1M

5%

5% 1/20W

MF

201

2

R1800

B

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

R1877 R1878

R1834 R1833

R1842 R1869 R1844 R1845 R1847

GPU:1P

R1814 R1815

R1843 R1846 R1848 R1853 R1854 R1855

R1879

A

A20

OMIT_TABLE

RTCX1

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34 G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201 201

MF

201

MF MF

201

MF

201

MF

201

MF

201

MF

RTCX2

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

(IPD-PLTRST#)

HDA_RST*

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_MOSI

SPI_MISO

17

PCH_SPKR PCH_SATALED_L

DP_AUXCH_ISOL SATARDRVR_EN

FW_CLKREQ_L AP_CLKREQ_L EXCARD_CLKREQ_L JTAG_DPMUXUC_TRST_L ENET_CLKREQ_L PEG_CLKREQ_L TBT_CLKREQ_L

SSD_CLKREQ_L PEGCLKRQA_L_GPIO47

SMBUS_PCH_ALERT_L USB_EXTB_SEL_XHCI USB_EXTD_SEL_XHCI

ENET_MEDIA_SENSE_RDIV

NC

8

18 21

1

20K

5%

MF

201

2

1

2

8

18 19 20

8

18 19 20 25 37

5% MF

5%

5% 5%

5%

5% 5%

5%

5% MF 5%

5%

5% 5%

5%

5% 5%

5%

1

R1803

20K

5% 1/20W MF 201

2

RTC_RESET_L PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L

1

C1803

1UF

10% 10V

2

X5R 402

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

R1802

1/20W

C1802

1UF

10% 10V X5R 402

4.7K

1 2

4.7K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

2 1

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V. If HDA = S0, must also ensure that signal cannot be high in S3.

PANTHERPOINT

(IPD-BOOT)

(IPD) (IPD) (IPD) (IPD)

(IPD-BOOT)

(IPD)

(IPU)

(IPD-BOOT)

(IPU)

U1800

MOBILE

FCBGA

(1 OF 10)

RTC

IHDA

JTAG

SPI

FWH4/LFRAME*

(IPU)

LDRQ1*/GPIO23

(IPU)

LPC

SATA

SATA3RCOMPO

SATA0GP/GPIO21 SATA1GP/GPIO19

(IPU)

LPC_AD_R<0>

17

LPC_AD_R<1>

17

LPC_AD_R<2>

17

LPC_AD_R<3>

17

LPC_FRAME_R_L

17

HDA_BIT_CLK_R

17 92

HDA_SYNC_R

17 92

HDA_RST_R_L

17 92

HDA_SDOUT_R

17 25 92

17

24 25

24

17

17 34

17

7

9

17 37

17 39

17

17 26

17

LDRQ0*

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED*

C38 A38

B37

C37

D36

E36

K36

V5

AM3 AM1

AP7

AP5

AM10 AM8

AP11 AP10

AD7

AD5

AH5 AH4

AB8

AB10

AF3 AF1

Y7

Y5 AD3

AD1

Y3

Y1 AB3

AB1

Y11

Y10

AB12

AB13 AH1

P3

V14 P1

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

(IPU)

SATAICOMPO SATAICOMPI

SATA3COMPI SATA3RBIAS

PLACE_NEAR=U1800.N34:1.27mm

PLACE_NEAR=U1800.L34:1.27mm

PLACE_NEAR=U1800.K34:1.27mm

PLACE_NEAR=U1800.A36:1.27mm

17 38

17

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_FRAME_R_L

TP_LPC_DREQ0_L TBT_PWR_EN_PCH

LPC_SERIRQ

SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P

SATA_ODD_D2R_N SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_C_D2RN TP_SATA_C_D2RP TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP

TP_SATA_D_D2RN TP_SATA_D_D2RP TP_SATA_D_R2D_CN TP_SATA_D_R2D_CP

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP

TP_SATA_F_D2RN TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

PCH_SATAICOMP

91

PCH_SATA3COMP

91

PCH_SATA3RBIAS

PCH_SATALED_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

33

R1860 R1861 R1862 R1863 R1864

R1810 R1811 R1812 R1813

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

17

7

25

OUT

39 91

IN

39 91

IN

39 91

OUT

39 91

OUT

9

91

IN

9

91

IN

9

91

OUT

9

91

OUT

7

17

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

ITPCPU_CLK100M_N

11 89

ITPCPU_CLK100M_P

11 89

=PP3V3_S0_PCH

1

R1820

10K

5% 1/20W MF 201

2

7

41 43

BI

=PP1V05_S0_PCH_VCCIO_SATA

PLACE_NEAR=U1800.Y11:2.54mm

1

R1830

37.4

1% 1/20W MF 201

2

=PP1V05_S0_PCH

1

R1831

49.9

1% 1/20W MF 201

2

PLACE_NEAR=U1800.AB12:2.54mm

PLACE_NEAR=U1800.AH1:2.54mm

1

R1832

750

1%

24

OUT OUT

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

1/20W MF

24

201

2

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

8

NO STUFF

R1841

0

1 2

5%

1/20W

MF

201

23

8

21 23

8

23

7

41 43 82 92

BI

7

41 43 82 92

BI

7

41 43 82 92

BI

7

41 43 82 92

BI

7

41 43 82 92

OUT

53 92

OUT

53 92

OUT

53 92

OUT

53 92

OUT

NO STUFF

R1840

0

1 2

5%

1/20W

MF

201

7

38 92

IN

7

38 92

IN

7

38 92

OUT

7

38 92

OUT

34 92

IN

34 92

IN

34 92

OUT

34 92

OUT

9

IN

9

IN

9

OUT

9

OUT

9

IN

9

IN

9

OUT

9

OUT

7

38 92

OUT

7

38 92

OUT

17 39

IN

9

92

9

92

17

34 92

OUT

34 92

OUT

17 34

IN

9

92

OUT

9

92

OUT

17

IN

7

17

OUT

39 92

OUT

39 92

OUT

7

17 38

IN

7

17

71 92

OUT

71 92

OUT

9

17

IN

35 92

OUT

35 92

OUT

17 37

IN

24 89

PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P

TP_PCIE_5_D2RN TP_PCIE_5_D2RP TP_PCIE_5_R2D_CN TP_PCIE_5_R2D_CP

TP_PCIE_6_D2RN TP_PCIE_6_D2RP TP_PCIE_6_R2D_CN TP_PCIE_6_R2D_CP

TP_PCIE_7_D2RN TP_PCIE_7_D2RP TP_PCIE_7_R2D_CN TP_PCIE_7_R2D_CP

TP_PCIE_8_D2RN TP_PCIE_8_D2RP TP_PCIE_8_R2D_CN TP_PCIE_8_R2D_CP

PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P

SSD_CLKREQ_L

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P

FW_CLKREQ_L

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P

JTAG_DPMUXUC_TRST_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN TP_PCIE_CLK100M_PEBP

PEGCLKRQB_L_GPIO56

PEG_CLK100M_N PEG_CLK100M_P

PEG_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

25 91

Unused clock terminations for FCIM Mode

10K 10K

10K

10K 10K

R1880

10K

GPU:2P

1 2

PCH_CLK96M_DOT_P

17 92

PCH_CLK96M_DOT_N

17 92

PCH_CLK100M_SATA_P

17 92

PCH_CLK100M_SATA_N

5%

1/20W

PEGCLKRQB_L_GPIO56PEGCLKRQB_L_GPIO56

201

MF

17 17

17 92

PCIE_CLK100M_PCH_P

17 92

PCIE_CLK100M_PCH_N

17 92

PCH_CLK14P3M_REFCLK

17 92

PCH_CLKIN_GNDP1

17

PCH_CLKIN_GNDN1

17

R1891 R1892

R1893 R1894

R1895 R1896

R1897

R1870 R1871

6 3

BG34 BJ34

AV32

AU32

BE34 BF34

BB32 AY32

BG36

BJ36

AV34 AU34

BF36

BE36

AY34 BB34

BG37

BH37 AY36

BB36

BJ38

BG38 AU36

AV36

BG40 BJ40

AY40

BB40

BE38 BC38

AW38

AY38

Y40

Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37

Y36

A8

Y43

Y45

L12

V45

V46

L14

AB42

AB40

E6

V40

V42

T13

V38 V37

K12

AK14 AK13

SYSCLK_CLK25M_SB

IN

1 2 1 2

1 2

1 2 1 2

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

Controlled by PCIECLKRQ5#

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1*/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ*/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

1/20W

5%

1/20W

MF

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(2 OF 10)

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

PCI-E*

C-LINK

CLOCKS

FLEX

CLOCKS

R1872

604

1 2

1% 1/16W MF-LF

402

201

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

(IPU/IPD)

CL_CLK1

CL_DATA1

CL_RST1*

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

(IPD-PWROK)

CLKOUTFLEX1/GPIO65

(IPD-PWROK)

CLKOUTFLEX2/GPIO66

(IPD-PWROK)

CLKOUTFLEX3/GPIO67

(IPD-PWROK)

SYSCLK_CLK25M_SB_R

1.8V -> 1.1V

1

R1873

1K

1% 1/20W MF 201

2

SYNC_MASTER=D2_KEPLER

PAGE TITLE

E12

H14 C9

A12

C8

G12

C13

E14 M16

M7

T11

P10

M10

AB37 AB38

AV22

AU22

AM12 AM13

BF18

BE18

BJ30 BG30

G24

E24

AK7 AK5

K45

H45

33MHz clocks must be matched within 5"

V47

V49

Y47

K43

F47

H47

K49

SMBUS_PCH_ALERT_L

SMBUS_PCH_CLK SMBUS_PCH_DATA

USB_EXTB_SEL_XHCI

SML_PCH_0_CLK SML_PCH_0_DATA

USB_EXTD_SEL_XHCI

SML_PCH_1_CLK SML_PCH_1_DATA

TP_CLINK_CLK

TP_CLINK_DATA

TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47

TP_PCIE_CLK100M_PEGAN TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

NC

=PP1V05_S0_PCH_VCCDIFFCLK

8

21 23

PLACE_NEAR=U1800.Y47:2.54mm

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

17 91

PCH SATA/PCIe/CLK/LPC/SPI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

17

44 92

OUT

44 92

BI

17 26

OUT

44 92

OUT

44 92

BI

17

OUT

44 92

OUT

44 92

BI

7

17

11 89

OUT

11 89

OUT

9

OUT

9

OUT

17 92

IN

17 92

IN

17

17 92

IN

17 92

IN

17 92

IN

17 92

IN

17 92

IN

25 92

IN

17 91

1

R1890

90.9

1%

1/20W

MF

201

2

9

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

18 OF 132

SHEET

17 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

B

R1905

10K

1/20W

=PP3V3_SUS_PCH_GPIO =PP1V05_S0_PCH_VCCIO_PCIE

PLACE_NEAR=U1800.BJ24:12.7mm

1

R1900

49.9

1%

5%

1/20W MF

MF

201

2

PLACE_NEAR=U1800.BH21:2.54mm

1

R1920

750

1% 1/20W MF 201

2

DMI_N2S_N<0>

10 89

IN

DMI_N2S_N<1>

10 89

IN

DMI_N2S_N<2>

10 89

IN

DMI_N2S_N<3>

10 89

IN

DMI_N2S_P<0>

10 89

IN

DMI_N2S_P<1>

10 89

IN

DMI_N2S_P<2>

10 89

IN

DMI_N2S_P<3>

10 89

IN

DMI_S2N_N<0>

10 89

OUT

DMI_S2N_N<1>

10 89

OUT

DMI_S2N_N<2>

10 89

OUT

DMI_S2N_N<3>

10 89

OUT

DMI_S2N_P<0>

10 89

OUT

DMI_S2N_P<1>

10 89

OUT

DMI_S2N_P<2>

10 89

OUT

DMI_S2N_P<3>

10 89

OUT

PCH_DMI_COMP

PCH_DMI2RBIAS

PCH_SUSACK_L

18

PM_SYSRST_L

25 41

IN

PM_PCH_SYS_PWROK

24 41 70

IN

PM_PCH_PWROK

25 70

IN

PM_PCH_APWROK

70

IN

PM_MEM_PWRGD

11 27 89

OUT

PM_RSMRST_L

70

IN

PCH_SUSWARN_L

18

PM_PWRBTN_L

18 24 41

IN

SMC_ADAPTER_EN

41 42 70

IN

PM_BATLOW_L

42

IN

PCH_RI_L

=PP3V3_SUS_PCH_GPIO

8

17 18 19 20

PCH_SUSWARN_L

18

8

R1983

10K

1/20W

17 18 19 20

1

5% MF

201

2

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK*

K3 B9

SYS_RESET*

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST*

K16

SUSWARN*/SUSPWRDNACK/GPIO30

E20

PWRBTN*

H20

ACPRESENT/GPIO31

(IPD-DeepS4/S5)

E10

BATLOW*/GPIO72

A10

RI*

R1986

0

12

PCH_SUSACK_L

5%

1/20W

MF

201

U1800

PANTHERPOINT

MOBILE

FCBGA

(3 OF 10)

DMI

(IPU)

MANAGEMENT

SYSTEM POWER

(IPU)

18

OMIT_TABLE

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

SLP_LAN*/GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12 BC10

AV14 BB10

A18

E22

N3

G8

N14

D10

H4

F4

G10 G16

AP14

K14

=FDI_DATA_N<0> =FDI_DATA_N<1> =FDI_DATA_N<2> =FDI_DATA_N<3> =FDI_DATA_N<4> =FDI_DATA_N<5> =FDI_DATA_N<6> =FDI_DATA_N<7>

=FDI_DATA_P<0> =FDI_DATA_P<1> =FDI_DATA_P<2> =FDI_DATA_P<3> =FDI_DATA_P<4> =FDI_DATA_P<5> =FDI_DATA_P<6> =FDI_DATA_P<7>

FDI_INT =FDI_FSYNC<0>

=FDI_FSYNC<1> =FDI_LSYNC<0>

=FDI_LSYNC<1>

PCH_DSWVRMEN PM_DSW_PWRGD PCIE_WAKE_L PM_CLKRUN_L LPC_PWRDWN_L PM_CLK32K_SUSCLK_R PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L TP_PM_SLP_A_L PM_SLP_SUS_L PM_SYNC MEM_VDD_SEL_1V5_L

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

10 89

OUT

9

OUT

9

OUT

9

OUT

9

OUT

7

IN

7

BI

7

OUT

42

OUT

18 41 70

OUT

7

OUT

7

OUT

18 70

OUT

11 89

OUT

18 64

OUT

18 34

18 41 43

25 41 43

18 27 34 38 40 41 70

18 27 38 41 70

PLACE_NEAR=U1800.AF37:2.54mm

=PPVRTC_G3_PCH

1

R1915

390K

5% 1/20W MF 201

2

41

IN

1

R1909

100K

5% 1/20W MF 201

2

R1950

2.37K

1/20W

8

17 21

LVDS_IG_BKL_ON

9

18

OUT

LVDS_IG_PANEL_PWR

9

18

OUT

LVDS_IG_BKL_PWM

7

OUT

LVDS_IG_DDC_CLK

9

OUT

LVDS_IG_DDC_DATA

9

OUT

TP_LVDS_IG_CTRL_CLK

7

TP_LVDS_IG_CTRL_DATA

7

PCH_LVDS_IBG TP_PCH_LVDS_VBG

1

1% MF

201

2

7

LVDS_IG_A_CLK_N

9

91

OUT

LVDS_IG_A_CLK_P

9

91

OUT

LVDS_IG_A_DATA_N<0>

9

91

OUT

LVDS_IG_A_DATA_N<1>

9

91

OUT

LVDS_IG_A_DATA_N<2>

9

91

OUT

LVDS_IG_A_DATA_N<3>

9

91

OUT

LVDS_IG_A_DATA_P<0>

9

91

OUT

LVDS_IG_A_DATA_P<1>

9

91

OUT

LVDS_IG_A_DATA_P<2>

9

91

OUT

LVDS_IG_A_DATA_P<3>

9

91

OUT

LVDS_IG_B_CLK_N

7

OUT

LVDS_IG_B_CLK_P

7

OUT

LVDS_IG_B_DATA_N<0>

9

91

OUT

LVDS_IG_B_DATA_N<1>

9

91

OUT

LVDS_IG_B_DATA_N<2>

9

91

OUT

LVDS_IG_B_DATA_N<3>

9

OUT

LVDS_IG_B_DATA_P<0>

9

91

OUT

LVDS_IG_B_DATA_P<1>

9

91

OUT

LVDS_IG_B_DATA_P<2>

9

91

OUT

LVDS_IG_B_DATA_P<3>

9

OUT

TP_CRT_IG_BLUE

7

TP_CRT_IG_GREEN

7

TP_CRT_IG_RED

7

TP_CRT_IG_DDC_CLK

7

TP_CRT_IG_DDC_DATA

7

TP_CRT_IG_HSYNC

7

TP_CRT_IG_VSYNC

7

PCH_DAC_IREF

PLACE_NEAR=U1800.T43:2.54mm

1

R1951

1K

5% 1/20W MF 201

2

J47 M45

P45

T40 K47

T45 P39

AF37 AF36

AE48 AE47

AK39 AK40

AN48 AM47 AK47 AJ48

AN47 AM49 AK49 AJ47

AF40 AF39

AH45 AH47 AF49 AF45

AH43 AH49 AF47 AF43

N48 P49 T49

T39 M40

M47 M49

T43 T42

L_BKLTEN L_VDD_EN

L_BKLTCTL

L_DDC_CLK L_DDC_DATA

(IPD-PLTRST#) L_CTRL_CLK L_CTRL_DATA

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK* LVDSA_CLK

LVDSA_DATA0* LVDSA_DATA1* LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK* LVDSB_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

U1800

PANTHERPOINT

MOBILE

FCBGA

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN DDPB_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPC_AUXN DDPC_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DDPD_AUXN DDPD_AUXP

(IPD) (IPD)

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

TP_SDVO_TVCLKINN TP_SDVO_TVCLKINP

TP_SDVO_STALLN TP_SDVO_STALLP

TP_SDVO_INTN TP_SDVO_INTP

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N DPA_IG_AUX_CH_P DPA_IG_HPD

TP_DP_IG_B_MLN<0> TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2> TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

DPB_IG_DDC_CLK DPB_IG_DDC_DATA

DPB_IG_AUX_CH_N DPB_IG_AUX_CH_P DPB_IG_HPD

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1> TP_DP_IG_C_MLP<1> TP_DP_IG_C_MLN<2> TP_DP_IG_C_MLP<2> TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXN TP_DP_IG_D_AUXP TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0> TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1> TP_DP_IG_D_MLP<1> TP_DP_IG_D_MLN<2> TP_DP_IG_D_MLP<2> TP_DP_IG_D_MLN<3> TP_DP_IG_D_MLP<3>

7

83

83 95

9

83

83 95

9

7

D

82

C

B

OMIT_TABLE

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO =PP3V3_S5_PCH

R1985 R1991

A

R1982 R1925

R1924 R1921 R1922 R1923

R1981 R1984

8.2K 10K

100K 100K 100K 100K

100K 100K

1 2

2 1 2 1 2 1 2 1

2 1 2 1

8

17 18 19 20

8

17 19 20 25 37

8

5%1K1/20W

1/20W

5%

1/20W

5%1K1/20W

5%

1/20W 1/20W 1/20W 1/20W

5%

1/20W

5% MF

1/20W

MF

MF MF5% MF5% MF

MF5%

PM_PWRBTN_L

201

PM_CLKRUN_L

201

MEM_VDD_SEL_1V5_L

201

PCIE_WAKE_L

201

MAKE_BASE=TRUE

PM_SLP_S3_L

201

PM_SLP_S4_L

201

PM_SLP_S5_L

201

PM_SLP_SUS_L

201

LVDS_IG_BKL_ON

201

LVDS_IG_PANEL_PWR

201

18 24 41

7

18 41 43

18 64

7

18 34

7

18 27 38 41 70

7

18 27 34 38 40 41 70

18 41 70

18 70

9

18

9

18

NOSTUFF

R1999

0

5%

1/20W

MF

201

12

=TBT_WAKE_L

35 42

IN

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH DMI/FDI/PM/Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9589

4.18.0

19 OF 132

18 OF 99

SIZE

A

D

8 7 6 5 4 3

12

OMIT_TABLE

BG26

NC NC NC NC NC NC NC NC NC NC

D

TP_PCH_TP23

NC NC NC NC NC NC NC NC NC NC

NC NC

NC

USB3_EXTA_RX_N

40 91

IN

USB3_EXTB_RX_N

7

38 91

IN

USB3_EXTC_RX_N

9

91

IN

USB3_EXTD_RX_N

9

C

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

R2010 R2011 R2012 R2013

B

R2054

=PP3V3_SUS_PCH_GPIO =PP3V3_S3_PCH_GPIO =PP3V3_S0_PCH_GPIO

R2016 R2017 R2018

R2030

R2014 R2031

A

R2033

R2069 R2060

R2061 R2062 R2068

R2067

10K 10K 10K

10K

10K 10K

10K

10K 10K 10K 10K

10K

1 2

NO STUFF

1 2

NO STUFF

1 2

1 2 1 2

2 1

8

17 18 20 25

8

25

8

17 18 19 20 25 37

JTAG_GMUX_TMS

MF

5%

1/20W 1/20W

5%

1/20W

5%

1/20W

Redundant to pull-up on audio page

5%

1/20W

5%

1/20W

Redundant to pull-up on audio page

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

201

BLC_I2C_MUX_SEL

201

MF5%

USE_HDD_OOB_L

MF

201

BLC_GPIO

MF

201

AUD_IP_PERIPHERAL_DET

MF

201

TBT_PWR_REQ_L

MF

201

AUD_I2C_INT_L

MF

201

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

201

MF

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

MF

201

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

MF

201

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

201

MF

AP_PWR_EN

MF

201

10K 10K 10K 10K

10K

1 2

1 2 1 2

NO STUFF

2 1

19

19 59

19 35

19 58

24 34 70

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

19 24

IN

40 91

IN

7

38 91

IN

9

91

IN

9

IN

40 91

OUT

38 91

OUT

9

91

OUT

9

OUT

40 91

OUT

38 91

OUT

9

91

OUT

9

OUT

MF

201

MF

201

MF

201

MF

201

19

OUT

19

OUT

19

OUT

MF

201

19

IN

19 59

IN

19 35

IN

19 58

IN

7

25 27

OUT

25 92

OUT

25

OUT

7

25

OUT

USB3_EXTA_RX_P USB3_EXTB_RX_P USB3_EXTC_RX_P USB3_EXTD_RX_P

USB3_EXTA_TX_N USB3_EXTB_TX_N USB3_EXTC_TX_N USB3_EXTD_TX_N

USB3_EXTA_TX_P USB3_EXTB_TX_P USB3_EXTC_TX_P USB3_EXTD_TX_P

PCI_INTA_L PCI_INTB_L PCI_INTC_L PCI_INTD_L

JTAG_GMUX_TMS BLC_I2C_MUX_SEL USE_HDD_OOB_L

TP_PCH_STRP_BBS1 TP_PCH_STRP_ESI_L PCH_STRP_TOPBLK_SWP_L

BLC_GPIO AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L AUD_I2C_INT_L

TP_PCI_PME_L

PLT_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3RN1

BC30

USB3RN2

BE32

USB3RN3

BJ32

USB3RN4

BC28

USB3RP1

BE30

USB3RP2

BF32

USB3RP3

BG32

USB3RP4

AV26

USB3TN1

BB26

USB3TN2

AU28

USB3TN3

AY30

USB3TN4

AU26

USB3TP1

AY26

USB3TP2

AV28

USB3TP3

AW30

USB3TP4

K40

PIRQA*

K38

PIRQB*

H38

PIRQC*

G38

PIRQD*

C46

REQ1*/GPIO50

C44

REQ2*/GPIO52

E40

REQ3*/GPIO54

D47

GNT1*/GPIO51

E42

GNT2*/GPIO53

F46

GNT3*/GPIO55

(IPU-PCIERST#)

G42

PIRQE*/GPIO2

G40

PIRQF*/GPIO3

C42

PIRQG*/GPIO4

D44

PIRQH*/GPIO5

K10

PME*

(IPU)

C6

PLTRST*

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

(IPD)

19 24 19 24

U1800

PANTHERPOINT

MOBILE

FCBGA

(5 OF 10)

USB

PCI

USBRBIAS*

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

6 3

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N USBP0P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP13N USBP13P

(IPD)

USBRBIAS

AY7 AV7

AU3

BG4

AT10 BC8

AU2

AT4 AT3

AT1

AY3 AT5

AV3

AV1 BB1

BA3

BB5 BB3

BB7 BE8

BD4

BF6

AV5 AV10

AT8

AY5

BA2

AT12 BF3

C24 A24

C25

B25

C26

A26

K28

H28

E28

D28

C28 A28

C29

B29

N28 M28

L30

K30

G30

E30

C30 A30

L32

K32

G32 E32

C32

A32

C33

B33

A14

K20 B17

C16

L16 A16

D14

C14

NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

NC

USB_EXTA_N USB_EXTA_P

USB_EXTB_XHCI_N USB_EXTB_XHCI_P

USB_EXTC_N USB_EXTC_P

USB_EXTD_XHCI_N USB_EXTD_XHCI_P

TP_USB_4N TP_USB_4P

TP_USB_SDN TP_USB_SDP

TP_USB_WLANN TP_USB_WLANP

USB_HUB_UP_N USB_HUB_UP_P

USB_CAMERA_N USB_CAMERA_P

USB_EXTB_EHCI_N USB_EXTB_EHCI_P

USB_EXTD_EHCI_N USB_EXTD_EHCI_P

TP_USB_BT_HSN TP_USB_BT_HSP

TP_USB_12N TP_USB_12P

TP_USB_13N TP_USB_13P

PCH_USB_RBIAS

91

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L XDP_DB2_PCH_GPIO10_AP_PWR_EN XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1K

R2020 R2021

1 2

1K

1 2

BI BI

5%

40 91

26 91

9

26 91

91

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Ext D (XHCI) (Mobiles: Trackpad?)

Unused

RSVD: SD

RSVD: WiFi

26 91

34 91

26 91

9

USB Hub (All LS/FS Devices)

Camera

Ext B (EHCI)

Ext D (EHCI)

RSVD: BT (HS)

Unused

IN IN IN IN IN IN

OUT

IN

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

MF

1/20W

201

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

201

MF5%

19 24

24

19 24

PLACE_NEAR=U1800.B33:2.54mm

1

R2070

22.6

1% 1/20W MF 201

2

19 24 19 24

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

PCH PCI/USB/TP/RSVD

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9589

4.18.0

20 OF 132

19 OF 99

SIZE

D

C

B

A

D

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

12

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

Systems with chip-down memory should add pull-downs on another page and set straps per software.

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

RAMCFG3:H

R2172

D

XDP_FC1_PCH_GPIO0

20 24

IN

FW_PME_L

20

IN

DPMUX_UC_IRQ

20 82

IN

SMC_RUNTIME_SCI_L

20 41

IN

TP_PCH_GPIO8

WOL_EN

20

OUT

XDP_FC0_PCH_GPIO15

24

IN

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

24

OUT

LPCPLUS_GPIO

7

20 43

BI

ODD_PWR_EN_L

20

OUT

TBT_GO2SX_BIDIR

20 35

SMC_WAKE_SCI_L

20 41

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

24

0

37

OUT

TBT_SW_RESET_L

R2180

1 2

C

OUT

TBT_SW_RESET_R_L

20

1/20W

5%

201

MF

XDP_DC1_PCH_GPIO35_MXM_GOOD

24

OUT

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

20 24

OUT

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

24

OUT

JTAG_ISP_TDO

20

IN

JTAG_ISP_TDI

20

OUT

FW_PWR_EN_PCH

20 25

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

24

OUT

SPIROM_USE_MLB

7

20 43 52

BI

(TBT_CIO_PLUG_EVENT_ISOL)

T7

BMBUSY*/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

(IPU-RSMRST#)

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

(IPU)

SATA4GP/GPIO16

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

(IPU-DeepS4/S5)

GPIO28

(IPU-RSMRST#)

STP_PCI*/GPIO34

GPIO35

SATA2GP/GPIO36

(IPD-PLTRST#)

SATA3GP/GPIO37

(IPD-PLTRST#)

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49/TEMP_ALERT*

GPIO57

VSS_NCTF_0 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13

BD49

BE49

BF49

U2

D40

T5

E8

E16

P8

K1

K4

V8

M5

N2

M3

V13

V3

D6

A4

A44

A45 A46

A5 A6

B3

B47 BD1

BE1

BF1

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(6 OF 10)

NCTF

(IPD-PLTRST#?)

CPU/MISC

GPIO

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

A20GATE

PECI

(IPD)

RCIN*

PROCPWRGD

THRMTRIP*

INIT3_3V*

(IPU)

DF_TVS

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11 AH10

AK10

P37

BG2 BG48

BH3

BH47 BJ4

BJ44

BJ45 BJ46

BJ5 BJ6

C2

C48 D1

D49

E1 E49

F1

F49

42

NC

MLB_RAMCFG3

9

MLB_RAMCFG2

9

MLB_RAMCFG1

9

MLB_RAMCFG0

9

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

PCH_INIT3V3_L

PCH_DF_TVS

NO STUFF

R2130

1/20W

20

1

1K

This has internal pull up and should not pulled low.

5%

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

MF

201

2

RAMCFG2:H RAMCFG1:H

1

R2173

10K

5%

5% 1/20W

MF

201

2

NO STUFF

43

390

0

1 2

R2170

R2140

R2156

R2174

CPU_PECI

1/20W

5%

201

MF

CPU_PWRGD

1/20W

5%

201

MF

PM_THRMTRIP_L

1/20W

5%

201

MF

1/20W

10K

RAMCFG0:H

1

R2175

10K

5%

5% 1/20W

MF

201

2

11 42 89

BI

11 24 89

OUT

11 42 89

ININ

R2178

1K

1/20W

201

=PP1V8_S0_PCH_VCC_DFTERM

1

R2179

2.2K

5% 1/20W MF 201

2

12

CPU_PROC_SEL_L

5%

DF_TVS:DMI & FDI Term Voltage

MF

Set to Vss when Low Set to Vcc when High

11 89

8

21 23

D

C

SIZE

B

A

D

B

JTAG Isolation due to glitch in and out of sleep

NOTE: TCK from PCH is Push-Pull CMOS NOTE: TMS/TDI from PCH is Open Drain NOTE: TDO from CR is Push-Pull CMOS

=PP3V3_S5_PCH_GPIO =PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

Stuff R2160 or R2574, not both

R2160 R2185 R2196 R2190

R2197 R2184

R2150 R2155

A

R2194 R2192 R2193

R2191 R2111

R2195 R2112 R2198

R2116

10K 10K 10K

100K

10K 10K

100K

10K

20K

100K

10K 10K

10K

NO STUFF

1 2

1 2 1 2

NO STUFF

1 2 1 2

1 2

1 2 1 2

1 2

2 1 2 1 2 1 2 1

2 1

8

17 18 19

8

17 18 19 20 25 37

1/20W

5%

1/20W

5%

1/20W

5%

Must stuff R2197 when R2180 NO STUFFed.

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

XDP_FC1_PCH_GPIO0

MF5%

201

FW_PME_L

201

MF

SMC_RUNTIME_SCI_L

201

MF

LPCPLUS_GPIO

MF

201

TBT_SW_RESET_R_L

201

MF

FW_PWR_EN_PCH

201

MF

PCH_A20GATE

MF5%

201

PCH_RCIN_L

201

WOL_EN

201

MF

TBT_GO2SX_BIDIR

201

MF

SPIROM_USE_MLB

201

MF5%

SMC_WAKE_SCI_L

MF

201

DPMUX_UC_IRQ

201

AUD_IPHS_SWITCH_EN_PCH

201

MF

ODD_PWR_EN_L

201

MF

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

201

MF

ENET_LOW_PWR_PCH

201

MF

20 24

20

20 41

7

20 43

20

20 25

20

20 35

7

20 43 52

20 41

20 82

24 25

20

20 24

9

24 25

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

JTAG_ISP_TMS

17

IN

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

JTAG_ISP_TDI

20

IN

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

20

OUT

1

R2186

2

1

R2188

10K

5% 1/20W MF 201

2

1

R2199

10K

2

10K

5% 1/20W MF 201

CRITICAL

Q2160

SSM6N15AFE

SOT563

D

6

CRITICAL

Q2160

SSM6N15AFE

SOT563

D

3

CRITICAL

Q2162

SSM3K15FV

SOD-VESM-HF

D

3

=PP3V3_TBT_PCH_GPIO

2

S G

1

5

S G

4

=PP3V3_TBT_PCH_GPIO

1

GS

2

1

R2163

10K

5% 1/20W MF 201

2

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

1

R2161

10K

5% 1/20W MF 201

2

JTAG_TBT_TDI

1

R2162

10K

5% 1/20W MF 201

2

JTAG_TBT_TDOJTAG_ISP_TDO

8

20

TBT_PWR_EN goes high for JTAG Programming

24

IN

35

OUT

8

20

35

OUT

8

20

35

IN

R2113

10K

1/20W

1

5%

MF

201

2

TBT_PWR_EN

25 35

IN

JTAG_ISP_TCK TBT_CIO_PLUG_EVENT

IN

1

2

6 3

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

R2166

10K

5% 1/20W MF 201

CRITICAL

1

A1

2

B1

5

A2

6

B2

8

VCC

U2100

SOT833

08

74LVC2G08GT

GND

4

1

C2113

0.1UF

10% 16V

2

X5R-CERM 0201

7

Y1

Y2

JTAG_TBT_TCK

3

TBT_CIO_PLUG_EVENT_ISOL Connects to PCH through current limiting 1K resistor R2574

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH GPIO/MISC/NCTF

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

35

OUT

24 35

OUT

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

21 OF 132

SHEET

20 OF 99

124578

8 7 6 5 4 3

12

D

OMIT_TABLE

AD49

VCCACLK pin left as NC per DG

=PP3V3_S5_PCH_VCCDSW

8

23

NC

TP_PPVOUT_PCH_DCPSUSBYP PP3V3_S0_PCH_VCC3_3_CLK_F

23

VCCAPLLDMI2 pin left as NC per DG

=PP1V05_S0_PCH_VCCIO_CLK

8

21 23

AL24 left as NC per DG

=PP1V05_S0_PCH_VCCASW

8

21 23

NC

C

PLACE_NEAR=U1800.N16:2.54mm

C2210

B

C2222

PCH output, for decoupling only

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

20% 10V

2

CERM

402

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

PLACE_NEAR=U1800.V16:2.54mm

20% 10V

2

CERM

402

PPVOUT_G3_PCH_DCPRTC =PP1V8R1V5_S0_PCH_VCCVRM

8

21

PP1V05_S0_PCH_VCCADPLLA_F

23

PP1V05_S0_PCH_VCCADPLLB_F

23

=PP1V05_S0_PCH_VCCIO_CLK

8

21 23

=PP1V05_S0_PCH_VCCDIFFCLK

8

17 23

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCSSC

8

23

PPVOUT_S0_PCH_DCPSST

=PP1V05_S0_PCH_V_PROC_IO

8

23

=PPVRTC_G3_PCH

8

17 18

C2231

PLACE_NEAR=U1800.A22:2.54mm

NC-ed per DG

1

1UF

10%

6.3V

2

CERM

402

NC NC

1

C2232

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U1800.A22:2.54mm

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3_5_CLK

BH23

VCCAPLLDMI2

AL29

VCCIO_14_PLLCLK

AL24

DCPSUS_3_CLK

AA19

VCCASW_1_CLK

AA21

VCCASW_2_CLK

AA24

VCCASW_3_CLK

AA26

VCCASW_4_CLK

AA27

VCCASW_5_CLK

AA29

VCCASW_6_CLK

AA31

VCCASW_7_CLK

AC26

VCCASW_8_CLK

AC27

VCCASW_9_CLK

AC29

VCCASW_10_CLK

AC31

VCCASW_11_CLK

AD29

VCCASW_12_CLK

AD31

VCCASW_13_CLK

W21

VCCASW_14_CLK

W23

VCCASW_15_CLK

W24

VCCASW_16_CLK

W26

VCCASW_17_CLK

W29

VCCASW_18_CLK

W31

VCCASW_19_CLK

W33

VCCASW_20_CLK

N16

DCPRTC

Y49

VCCVRM_4_CLK

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO_7_CLK

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS_1_CLK

V19

DCPSUS_2_CLK

BJ8

V_PROC_IO

A22

VCCRTC

1

C2233

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U1800.A22:2.54mm

U1800

PANTHERPOINT

MOBILE

FCBGA

(8 OF 10)

VCCSUS3_3_10_USB

USB

VCCSUS3_3_2_GPIO VCCSUS3_3_3_GPIO VCCSUS3_3_4_GPIO VCCSUS3_3_5_GPIO

CLK/MISC

PCI/GPIO/

VCCIO_6_PLLSATA3

SATAMISC

CPURTC

HDA

VCCIO_29_USB VCCIO_30_USB VCCIO_31_USB VCCIO_32_USB VCCIO_33_USB

VCCSUS3_3_7_USB VCCSUS3_3_8_USB VCCSUS3_3_9_USB

VCCSUS3_3_6_USB

VCCIO_34_PLLUSB

V5REF_SUS

DCPSUS_4_USB

VCCSUS3_3_1_USB

V5REF

VCC3_3_1_GPIO VCC3_3_8_GPIO

LPC

VCC3_3_4_GPIO

VCC3_3_2_SATA

VCCIO_5_PLLSATA

VCCIO_12_SATA3 VCCIO_13_SATA3

VCCAPLLSATA

VCCVRM_1_SATA

VCCIO_2_SATA VCCIO_3_SATA VCCIO_4_SATA

VCCASW_22_MISC VCCASW_23_MISC VCCASW_21_MISC

VCCSUSHDA

N26

=PP1V05_S0_PCH_VCCIO_USB

P26 P28 T27 T29

T23

=PP3V3_SUS_PCH_VCCSUS_USB

T24 V23 V24 P24

T26

=PP1V05_S0_PCH_VCCIO_PLLUSB

M26

=PP5V_SUS_PCH_V5REFSUS

AN23

AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14

AK1

AF11

AC16 AC17 AD17

T21 V21 T19

P32

NC-ed per DG

NC

=PP3V3_SUS_PCH_VCCSUS

=PP5V_S0_PCH_V5REF =PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCC3_3_SATA =PP1V05_S0_PCH_VCCIO_SATA

VCCAPLLSATA pin left as NC per DG

NC

=PP1V8R1V5_S0_PCH_VCCVRM =PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCASW

=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

8

23

8

23

8

23

8

23

8

23

8

23

8

23

8

17 21 23

8

21

8

17 21 23

8

21 23

8

23 25

=PP1V05_S0_PCH_VCC_CORE

8

23

1.44 A Max, 474mA Idle

=PP1V05_S0_PCH_VCCIO_PLLPCIE

8

TP_1V05_S0_PCH_VCCAPLLEXP =PP1V05_S0_PCH_VCCIO

8

23

=PP3V3_S0_PCH_VCC3_3_PCI

8

23

=PP1V8R1V5_S0_PCH_VCCVRM

8

21

VCCAFDIPLL pin left as NC per DG

=PP1V05_S0_PCH_VCCIO_PLLFDI

8

=PP1V05_S0_PCH_VCCDMI_FDI

8

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO_28_PLLPCIE

BJ22

VCCAPLLEXP

AN16

VCCIO_15_FDI

AN17

VCCIO_16_FDI

AN21

VCCIO_17_PCIE

AN26

VCCIO_18_PCIE

AN27

VCCIO_19_PCIE

AP21

VCCIO_20_PCIE

AP23

VCCIO_21_PCIE

AP24

VCCIO_22_PCIE

AP26

VCCIO_23_PCIE

AT24

VCCIO_24_PCIE

AN33

VCCIO_25_DP

AN34

VCCIO_26_DP

BH29

VCC3_3_3_PCIE

AP16

VCCVRM_2_FDI

BG6

NC

VCCAFDIPLL

AP17

VCCIO_27_PLLFDI

AU20

VCCDMI_2_FDI

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(7 OF 10)

VCC CORE

LVDS

VCC3_3_6_HVCMOS

VCC3_3_7_HVCMOS

HVCMOS

VCCIO

DMI CRT

FDI

DFT/SPI

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCCVRM_3_DMI

VCCDMI_1_DMI

VCCCLKDMI

VCCDFTERM VCCDFTERM VCCDFTERM VCCDFTERM

VCCSPI

U48

PP3V3_S0_PCH_VCCA_DAC_F

U47

CKPLUS_WAIVE=PwrTerm2Gnd

AK36

=LVDS_VCCA

AK37

PP1V8_S0_PCH_VCCTX_LVDS_F

AM37 AM38 AP36 AP37

=PP3V3_S0_PCH_VCC3_3_HVCMOS

V33

V34

AT16

=PP1V8R1V5_S0_PCH_VCCVRM

AT20

=PP1V05_S0_PCH_VCC_DMI

AB36

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V8_S0_PCH_VCC_DFTERM

AG16 AG17 AJ16 AJ17

V1

=PP3V3_SUS_PCH_VCC_SPI

23

8

23

8

23

8

21

8

23

8

20 23

8

23

D

C

B

A

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=03/19/2012SYNC_MASTER=D2_CLEAN

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

22 OF 132

SHEET

124578

4.18.0

21 OF 99

SIZE

A

D

8 7 6 5 4 3

B7

D3

D8

F3

VSS

PANTHERPOINT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

OMIT_TABLE

U1800

MOBILE

FCBGA

(10 OF 10)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8

BG29 N24 AJ3 AD47

B43 BE10 BG41

G14 H16

T36

BG22

BG24 C22

AP13

M14 AP3 AP1 BE16 BC16 BG28 BJ28

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

H5

AA17

AA2

AA3 AA33 AA34 AB11 AB14 AB39

AB4

D

C

B

AB43

AC19

AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD40 AD42 AD43 AD45 AD46

AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF42 AF46

AG19

AG31 AG48 AH11

AH36 AH39 AH40 AH42 AH46

AJ19 AJ21 AJ24 AJ33 AJ34 AK12

AB5

AB7

AC2

AD4

AD8

AE2

AE3

AF4

AF5

AF7

AF8

AG2

AH3

AH7

AK3

VSS

PANTHERPOINT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U1800

MOBILE

FCBGA

(9 OF 10)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV11 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AY12 AY22 AY28

A

OMIT_TABLE

AY42 AY46

BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB46 BC14 BC18

BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46

BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28

BF30 BF38 BF40

BG17 BG21 BG33 BG44

BH11 BH15 BH17 BH19

BH27 BH31 BH33 BH35 BH39 BH43

AY4

AY8 B11 B15 B19 B23 B27 B31

B35

B39

F45

BB4

BC2

BD5

BD3

BF8

BG8

H10

BH7

D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42

E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34

6 3

12

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

23 OF 132

SHEET

22 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

8

21

8

D

PLACE_NEAR=U1800.M26:2.54mm

8

C

8

B

8

A

8

17

=PP3V3_SUS_PCH_VCCSUS =PP5V_SUS_PCH

1 mA S0-S5

C2438

R2404

1/16W MF-LF

0.1UF

20% 10V

CERM

402

2

10

NC NC

5%

402

1

2

=PP1V8_S0_PCH_VCCTX_LVDS

PLACE_NEAR=U1800.AM37:2.54mm

=PP3V3_S0_PCH_VCCADAC

PLACE_NEAR=U1800.U48:2.54mm

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)

4

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

NO STUFF

L2407

0.1UH

1 2

0805

NO STUFF

C2400

22UF

X5R-CERM-1

PLACE_NEAR=U1800.AM37:2.54mm

PLACE_NEAR=U1800.U48:2.54mm

10UH-0.58A-0.35OHM

PLACE_NEAR=U1800.AM37:2.54mm

R2450

0

1 2

5%

1/20W

MF

201

C2450

10UF

PLACE_NEAR=U1800.U48:2.54mm

R2451

1

1 2

5% 1/16W MF-LF

402

R2490

0

1 2

R2491

1 2

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

0

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

CRITICAL

L2406

1 2

1098AS-SM

<1 mA S0-S5

21

NOSTUFF

1

C2406

0.01UF

20%

6.3V 603

20%

6.3V X5R 603

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V

10% 16V

2

X7R-CERM 0402

1

C2451

0.1UF

10% 16V

2

X7R-CERM 0402

PP1V05_S0_PCH_VCCADPLLA_R

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

PP1V05_S0_PCH_VCCADPLLB_R

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.05V

PLACE_NEAR=U1800.P34:2.54mm

NO STUFF

1

C2408

0.01UF

10% 16V

2

X7R-CERM 0402

PP3V3_S0_PCH_VCCA_DAC_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

C2455

0.01UF

10% 16V

2

X7R-CERM 0402

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.T38:2.54mm

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.BD47:2.54MM

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.BF47:2.54MM

PLACE_NEAR=U1800.AB36:2.54mm

1

2

CRITICAL

L2451

1 2

0603

C2453

10UF

CRITICAL

L2490

1 2

0603

CRITICAL

C2491

220UF

CRITICAL

L2491

1 2

0603

CRITICAL

C2493

220UF

R2415

0

1 2

5% 1/16W MF-LF

402

C2411

10UF

=PP3V3_S0_PCH

8

17

=PP5V_S0_PCH

8

25

1 mA

PP1V8_S0_PCH_VCCTX_LVDS_F

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

R2401

0

5% 1/20W MF 201

PLACE_NEAR=U1800.AM37:2.54MM

1

20%

6.3V 2

X5R 603

1

20%

2.5V

2

TANT

B16

1

20%

2.5V

2

TANT

B16

1

20%

6.3V 2

X5R 603

R2405

100

1/16W MF-LF

C2439

1UF

10% 10V X5R 402

21

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V

1

C2454

1UF

10% 10V

2

X5R 402

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

NO STUFF

1

C2492

1UF

10%

6.3V

2

CERM 402

PCH VCCADPLLB Filter (PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

NO STUFF

1

C2494

1UF

10%

6.3V

2

CERM 402

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.05V

2

5%

402

1

2

PCH V5REF Filter & Follower (PCH Reference for 5V Tolerance on PCI)

1

52

D2400

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

21

68 mA

21

69 mA

21

<1 mA

21

=PP3V3_S5_PCH_VCCDSW

8

21

=PP3V3_SUS_PCH_VCC_SPI

8

21

=PP3V3_SUS_PCH_VCCSUS_GPIO

8

21

PCH VCCSUS3_3 BYPASS (PCH SUSPEND USB 3.3V PWR)

=PP3V3_SUS_PCH_VCCSUS_USB

8

21

PLACE_NEAR=U1800.P24:2.54mm

C2499

0.1UF

PLACE_NEAR=U1800.T16:2.54mm

C2442

PLACE_NEAR=U1800.V1:2.54mm

C2476

PLACE_NEAR=U1800.P22:2.54mm

1

C2484

0.1UF

10% 16V

2

X7R-CERM 0402

PLACE_NEAR=U1800.V24:2.54mm

PCH VCCSUSHDA BYPASS

=PP3V3R1V5_S0_PCH_VCCSUSHDA

8

21 25

PLACE_NEAR=U1800.P32:2.54mm

=PP1V8_S0_PCH_VCC_DFTERM

8

20 21

PLACE_NEAR=U1800.AJ16:2.54mm

=PP1V05_S0_PCH_V_PROC_IO

8

21

C2416

PLACE_NEAR=U1800.BJ8:2.54mm

=PP1V05_S0_PCH_VCC_DMI

8

21

PLACE_NEAR=U1800.BJ8:2.54mm

PLACE_NEAR=U1800.AT20:2.54mm

20% 10V

CERM

402

1UF

10%

6.3V CERM

402

1UF

10%

6.3V CERM

402

4.7UF

6.3V

20% X5R

402

1

2

1

2

1

2

1

2

C2413

0.1UF

10% 16V X7R-CERM 0402

1

2

C2441

0.1UF

C2440

0.1UF

1

C2417

0.1UF

10% 16V

2

X7R-CERM 0402

C2419

CERM

1UF

6.3V CERM

=PP3V3_S0_PCH_VCC3_3_GPIO

8

21

PLACE_NEAR=U1800.T34:2.54mm

=PP3V3_S0_PCH_VCC3_3_HVCMOS

8

21

=PP3V3_S0_PCH_VCC3_3_PCI

8

21

=PP3V3_S0_PCH_VCC3_3_SATA

8

21

1

20% 10V

2

402

1

20% 10V

2

402

1

C2430

0.1UF

10% 16V

2

X7R-CERM 0402

1

10%

2

402

6 3

1

C2486

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U1800.AA16:2.54mm

C2424

0.1UF

PLACE_NEAR=U1800.V33:2.54mm

PLACE_NEAR=U1800.BH29:2.54mm

PLACE_NEAR=U1800.AJ2:2.54mm

X7R-CERM

C2421

0.1UF

X7R-CERM

C2423

0.1UF

X7R-CERM

=PP1V05_S0_PCH_VCCIO

8

21

PLACE_NEAR=U1800.AN27:2.54mm

=PP1V05_S0_PCH_VCCASW

8

21

PLACE_NEAR=U1800.AC27:2.54mm

PCH VCCCORE BYPASS (PCH 1.05V CORE PWR)

=PP1V05_S0_PCH_VCC_CORE

8

21

1

C2485

0.1UF

10% 25V

2

X5R 402

1

10% 16V

2

0402

1

10% 16V

2

0402

1

10% 16V

2

0402

C2401

10UF

PLACE_NEAR=U1800.AN27:2.54mm

PCH VCCIO BYPASS

PCH VCC3_3 BYPASS (PCH PCI 3.3V PWR)

PLACE_NEAR=U1800.AN27:2.54mm

C2420

22UF

X5R-CERM-1

PLACE_NEAR=U1800.AC27:2.54mm

PLACE_NEAR=U1800.AG26:2.54mm

PLACE_NEAR=U1800.AD21:2.54mm

SYNC_MASTER=D2_CLEAN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

=PP1V05_S0_PCH_VCCSSC

8

21

=PP1V05_S0_PCH_VCCDIFFCLK

8

17 21

=PP1V05_S0_PCH_VCCIO_CLK

8

21

=PP1V05_S0_PCH_VCCIO_SATA

8

17 21

PLACE_NEAR=U1800.AH13:2.54mm

PCH VCCIO BYPASS (PCH USB 1.05V PWR)

=PP1V05_S0_PCH_VCCIO_USB

8

21

1

C2429

6.3V

20% X5R

603

20%

603

1UF

10%

6.3V

2

CERM 402

PLACE_NEAR=U1800.AN27:2.54mm

1

C2428

22UF

20%

6.3V

2

X5R-CERM-1

603

PLACE_NEAR=U1800.AC27:2.54mm

C2460

10UF

20%

6.3V X5R 603

PLACE_NEAR=U1800.AG24:2.54mm

PCH DECOUPLING

Apple Inc.

R

PLACE_NEAR=U1800.AG33:2.54mm

PLACE_NEAR=U1800.AF34:2.54mm

PLACE_NEAR=U1800.AF17:2.54mm

1UF

10%

6.3V CERM 402

1UF

10%

6.3V CERM 402

1UF

10%

6.3V CERM 402

1UF

6.3V CERM

1

10%

2

402

1

2

1

2

1

2

C2444

PLACE_NEAR=U1800.AC17:2.54mm

PLACE_NEAR=U1800.P28:2.54mm

1

C2414

2

PLACE_NEAR=U1800.AN27:2.54mm

1

C2426

2

PLACE_NEAR=U1800.AC27:2.54mm

1

C2481

2

PLACE_NEAR=U1800.AJ27:2.54mm

1

C2475

1UF

10%

6.3V

2

CERM

402

1

C2434

1UF

10%

6.3V

2

CERM

402

1

C2469

1UF

10%

6.3V

2

CERM

402

1

C2452

1UF

10%

6.3V 2

CERM

402

1

C2446

1UF

10%

6.3V 2

CERM

402

1

C2407

1UF

10%

6.3V CERM 402

C2456

1UF

10%

6.3V CERM 402

C2482

1UF

10%

6.3V CERM 402

C2463

1UF

10%

6.3V

2

CERM 402

1

C2496

1UF

10%

6.3V

2

CERM 402

1

C2483

1UF

10%

6.3V

2

CERM 402

SYNC_DATE=03/19/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

24 OF 132

SHEET

23 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

=PPVCCIO_S0_XDP

8

24

=PP3V3_S0_XDP

8

XDP_CPU_PREQ_L

11 89

BI

XDP_CPU_PRDY_L

11 89

D

(R2560-R2563)

XDP_CPU:BPM

0

11 89

IN

11 89

IN

11 89

IN

11 89

IN

10 89

IN

10 89

IN

10 89

IN

10 89

IN

11 20 89

IN

18 24 41

OUT

10 24 89

OUT

18 41 70

OUT

XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_PWRGD

PM_PWRBTN_L

CPU_CFG<0>

PM_PCH_SYS_PWROK

R2560 R2561 R2562 R2563

R2564 R2565 R2566 R2567

PLACE_NEAR=U1000.C60:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

PLACE_NEAR=U1000.B57:2.54mm

R2500

R2502

R2501

R2504

1 2

0

1 2

0

1 2

0

1 2

(R2564-R2567)

XDP_CPU:CFG

0

1 2

0

1 2

0

1 2

0

1 2

XDP

1K

1 2

XDP

0

1 2

XDP

1K

1 2

XDP

330

1 2

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

C

XDP SIGNALS

XDP_DA0_USB_EXTA_OC_L

24

OUT

XDP_DA1_USB_EXTB_OC_L

24

OUT

XDP_DA2_USB_EXTC_OC_L

24

OUT

XDP_DA3_USB_EXTD_OC_L

24

OUT

XDP_DB0_USB_EXTB_OC_EHCI_L

24

OUT

XDP_DB1_USB_EXTD_OC_EHCI_L

24

OUT

XDP_DB2_AP_PWR_EN

24

IN

XDP_DB3_SDCONN_STATE_CHANGE

24

OUT

XDP_FC0

24

OUT

XDP_FC1

24

OUT

XDP_DC0_ISOLATE_CPU_MEM_L

24

IN

XDP_DC1_MXM_GOOD

24

IN

XDP_DC2_DP_AUXCH_ISOL

24

IN

XDP_DC3_SATARDRVR_EN

24

IN

XDP_DD0_DP_GPU_TBT_SEL

24

IN

XDP_DD1_JTAG_ISP_TCK

24

IN

XDP_DD2_AUD_IPHS_SWITCH_EN

24

IN

XDP_DD3_ENET_LOW_PWR

24

IN

B

PCH/XDP Signal Isolation Notes:

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3 doc id 404081. Initially, stuffing both 33 and 0 ohms and validate whether it is functional in that state, else add BOM options.

- For isolated GPIOs:

- ’Output’ non-XDP signals require pulls.

- ’Output’ PCH/XDP signals require pulls.

R252x, R253x, R257x and R259x should be placed where signal path needs to split between route from PCH to J2550 and path to non-XDP signal destination.

ALL_SYS_PWRGD

41 70

IN

PM_PWRBTN_L

18 24 41

OUT

PLACE_NEAR=J2550.39:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

R2584

R2585

R2520 R2521 R2522 R2523

R2524 R2525 R2526 R2527 R2528

R2529 R2530

R2531 R2532 R2533 R2534 R2535

R2536 R2537

(R2520-R2537)

33 33 33 33

33 33 33 33 33

33

33 33 33 33 33 33

33 33

XDP

1K

1 2

XDP

0

1 2

XDP

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

1 2

5%

1/20W

5%

5% 5%

5% MF

5%

5% MF

5%

5% 5%

5%

5% 5%

1/20W

MF

1/20W

MF

1/20W

MF MF

1/20W

MF

1/20W

MF

1/20W

MF

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

1/20W

MF

1/20W

MF

201

MF

201

MF

A

PCH SIGNALS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

201

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

201

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

201

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

201

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

201

201 201

201

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

201

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

201

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

201

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

201

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

201

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

201

24 44

17 24

IN

XDP_BPM_L<0>

11 89

IN

XDP_BPM_L<1>

11 89

IN

XDP_BPM_L<2>

11 89

IN

XDP_BPM_L<3>

11 89

IN

CPU_CFG<10>

10 89

IN

CPU_CFG<11>

10 89

IN

XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

XDP_CPU_PWRGD

89

XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0> XDP_VR_READY

=SMBUS_XDP_SDA

24 44

BI

=SMBUS_XDP_SCL

24 44

IN

XDP_CPU_TCK

11 24 89

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_FC0_PCH_GPIO15

XDP_FC1_PCH_GPIO0

XDP_DC1_PCH_GPIO35_MXM_GOOD

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

XDP_DA0_USB_EXTA_OC_L

24

XDP_DA1_USB_EXTB_OC_L

24

XDP_DA2_USB_EXTC_OC_L

24

XDP_DA3_USB_EXTD_OC_L

24

TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>

XDP_DB0_USB_EXTB_OC_EHCI_L

24

XDP_DB1_USB_EXTD_OC_EHCI_L

24

XDP_DB2_AP_PWR_EN

24

XDP_DB3_SDCONN_STATE_CHANGE

24

XDP_PCH_S5_PWRGD XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3

=SMBUS_XDP_SDA

BI

=SMBUS_XDP_SCL

IN

XDP_PCH_TCK

OUT

NO STUFF

R2540

1/16W MF-LF

1

1K

5%

402

2

IN IN IN IN

IN IN

OUT

IN IN

IN

OUT OUT OUT OUT OUT OUT

OUT OUT

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

TCK1 TCK0

C2500

19 24

X7R-CERM

19 24

19

NOTE: This is not the standard XDP pinout.

19 24

Use with 921-0133 Adapter Flex to

19 24

support chipset debug.

20

20 24

20

17 24

20

20 24

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

TCK1 TCK0

C2580

X7R-CERM

CPU Micro2-XDP

CRITICAL XDP_CONN

J2500

DF40RC-60DP-0.4V

M-ST-SM

62

2

4

6

10

20

30

40

SDA SCL

50

NC

60

998-2516

0.1UF

0402

XDP

1

10% 16V

2

PCH Micro2-XDP

CRITICAL XDP_CONN

J2550

DF40RC-60DP-0.4V

M-ST-SM

62

2 4

6

10

20

30

40

SDA SCL

0.1UF

0402

XDP

1

10% 16V

2

50

NC

60

998-2516

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

61

1

3

5 78

9 1112

1314

1516 1718

19

2122 2324

2526

2728 29

3132 3334

3536

3738 39

4142

4344 4546

4748

49 5152

5354 5556

5758

59

6364

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page TDO TRSTn TDI TMS XDP_PRESENT#

XDP

1

C2501

0.1UF

10% 16V

2

X7R-CERM 0402

=PP3V3_S5_XDP

61

1 3

5 78

9

1112 1314

1516

1718 19

2122

2324 2526

2728 29

3132

3334 3536

3738

39 4142

4344

4546 4748

49 5152

5354

5556 5758

59

6364

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page TDO TRSTn TDI TMS XDP_PRESENT#

XDP

1

C2581

0.1UF

10% 16V

2

X7R-CERM 0402

CPU_CFG<16> CPU_CFG<17>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_CPU_CLK100M_P

89

XDP_CPU_CLK100M_N

89

XDP_CPURST_L XDP_DBRESET_L

XDP_CPU_TDO XDP_CPU_TRST_L XDP_CPU_TDI XDP_CPU_TMS

PCH SIGNALS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

19 24

OUT

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

19 24

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

19 24

IN

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

19 24

OUT

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

17 24

IN

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

20 24

OUT

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

17 24

IN

XDP_FC1_PCH_GPIO0

OUT

8

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

20 24

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

20 24

OUT

XDP_FC0 XDP_FC1

XDP_DC0_ISOLATE_CPU_MEM_L XDP_DC1_MXM_GOOD

XDP_DC2_DP_AUXCH_ISOL XDP_DC3_SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1>

XDP_DD0_DP_GPU_TBT_SEL XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_EN XDP_DD3_ENET_LOW_PWR

TP_XDP_PCH_HOOK4 TP_XDP_PCH_HOOK5

XDPPCH_PLTRST_L XDP_DBRESET_L

XDP_PCH_TDO TP_XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

IN IN

OUT

IN OUT OUT OUT

10 89

10 24 89

10 89

11 24 25 89

11 24 89

R2515

R2516

R2505

24

IN

OUT

IN

OUT OUT

25

11 24 25 89

17 24

XDP_CPU_TDO

11 24 89

XDP_CPU_TDI

11 24 89

XDP_CPU_TMS

11 24 89

XDP_CPU_TCK

11 24 89

XDP_CPU_TRST_L

11 24 89

XDP

0

1K

R2574

PLACE_NEAR=R1841.1:2.54mm

1 2

5%

XDP

PLACE_NEAR=R1840.1:2.54mm

1 2

5%

PLACE_NEAR=U1000.G3:2.54mm

XDP

1 2

5%

R2590 R2591 R2596 R2597

R2573

R2570 R2572

0

1K

R2575 R2576 R2577

XDP_PCH_TDO

17 24

XDP_PCH_TDI

17 24

XDP_PCH_TMS

17 24

XDP_PCH_TCK

17 24

ITPXDP_CLK100M_P

1/20W

MF

ITPXDP_CLK100M_N

1/20W

MF

CPU_RESET_L

1/20W

MF

1 2

5%01/20W

1 2

5% MF

1 2

5% MF0201

1 2

5%

1 2

5%

1 2

5%

1 2

0

1 2

0

1 2

0

1 2

201

1K series R on PCH Support Page

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

R2510

R2511

R2512

R2513

R2514

1/20W

5%

5% 5%

51

17 89

IN

17 89

IN

11 25

IN

Non-XDP Signals

201

MF 1/20W

1/20W

201

MF

201

MF

201

MF

MF5%

201

201MF5%

1/20W

MF

AUD_IPHS_SWITCH_EN_PCH

1/20W

MF

1/20W

MF

R2550

R2551

R2552

R2556

51

CPU & PCH XDP

Apple Inc.

R

6 3

=PPVCCIO_S0_XDP

8

24

XDP

PLACE_NEAR=J2500.52:2.54mm

2 1

XDP

2 1

XDP

2 1

XDP

2 1

XDP

2 1

SDCONN_STATE_CHANGE

1/20W

5%

PLACE_NEAR=U1000.K61:2.54mm

1/20W

5%

PLACE_NEAR=U1000.H59:2.54mm

1/20W

5%

PLACE_NEAR=U1000.J58:2.54mm

1/20W

5%

PLACE_NEAR=U1000.H63:2.54mm

1/20W

5%

USB_EXTA_OC_L USB_EXTB_OC_L

AP_PWR_EN

SATARDRVR_EN

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

TBT_CIO_PLUG_EVENT_ISOL

JTAG_ISP_TCK

201

ENET_LOW_PWR_PCH

201

=PP1V05_SUS_PCH_JTAG

8

XDP

PLACE_NEAR=J2550.52:2.54mm

2 1

XDP

2 1

XDP

2 1

XDP

2 1

1/20W

5%

PLACE_NEAR=U1800.K5:2.54mm

1/20W

5%

PLACE_NEAR=U1800.H7:2.54mm

1/20W

5%

PLACE_NEAR=U1800.J3:2.54mm

1/20W

5%

201

MF

201

MF

201

MF

201

MF

201

MF

40

IN

7

38

IN

19 34 70

OUT

25

IN

17

OUT

27

OUT

17 25

OUT

20 20 24

IN

20 20 24

OUTOUT

20 25

OUT

9

20 25

OUT

201

MF

201

MF

201

MF

201

MF

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

25 OF 132

SHEET

24 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

GPIO Glitch Prevention

=PP3V3_S3_PCH_GPIO

8

19 25

CRITICAL

ENET_LOW_PWR_PCH

20 24

IN

PM_PCH_PWROK

18 25 70

IN

FW_PWR_EN_PCH

20

IN

D

=PP3V3_S3_PCH_GPIO

8

19 25

CRITICAL

TBT_PWR_EN_PCH

17

IN

LPC_PWRDWN_L

7

18 41 43

IN

AUD_IPHS_SWITCH_EN_PCH

20 24 39

IN

PM_PCH_PWROK

18 25 70

IN

U2650

1

A1

2

B1

5

A2

6

B2

U2652

1

A1

2

B1

5

A2

6

B2

8

VCC

SOT833

08

74LVC2G08GT

GND

4

8

VCC

SOT833

08

GND

74LVC2G08GT

4

C

1

C2650

0.1UF

20% 10V

2

CERM 402

7

Y1

Y2

Y1

Y2

ENET_LOW_PWR

3

FW_PWR_EN

1

C2652

0.1UF

20% 10V

2

CERM 402

7

TBT_PWR_EN

3

AUD_IPHS_SWITCH_EN

9 9

OUT

24

OUT

11 24 89

IN

SDCONN_STATE_CHANGE

9

OUT

20 35

OUT

58

OUT

SSM6N15FEAPE

SDCONN_STATE_CHANGE_SMC

42

OUT

PCH Reset Button

=PP3V3_S0_SB_PM

8

70

1

R2695

4.7K

XDP

R2696

XDP_DBRESET_L

1 2

5% 1/16W MF-LF

402

SDCONN_STATE_CHANGE ISOLATION

5

4

Y

U2630

470K

1/20W

3

1

5% MF

201

2

5

SDCONN_STATE_CHANGE_INV

S G

4

=PP3V3_S4_SMC

8

25 42

Q2640

SOT563

D

3

R2640

5% 1/16W MF-LF 402

2

0

OMIT

1

R2697

0

5% 1/16W MF-LF 402

2

SILK_PART=SYS RESET

CRITICAL

TC7SZ08AFEAPE

SOT665

2

A

1

SDCONN_STATE_CHANGE_RIO

B

SSM6N15FEAPE

PM_SYSRST_L

=PP3V3_S3_SDBUF

1

C2630

0.1UF

10%

6.3V

2

X5R 201

Q2640

SOT563

R2641

D

6

470K

1/20W

18 41

OUT

8

1

5% MF

201

2

S G

1

=PP3V3_S4_SMC

7

38

IN

8

25 42

=PP3V3_S0_RSTBUF

8

25

Platform Reset Connections

19 27

IN

PLT_RESET_L

MAKE_BASE=TRUE

C2680

0.1UF

20% 10V

CERM

402

Unbuffered

Buffered

1

U2680

2

1

2

CRITICAL

5

MC74VHC1G08

SC70-HF

3

4

MAKE_BASE=TRUE

1

2

PLT_RST_BUF_L

R2680

100K

5% 1/16W MF-LF 402

R2681

33

1 2

5% 1/16W MF-LF

402

R2671

0

1 2

5% 1/16W MF-LF

402

R2687

0

1 2

5% 1/16W MF-LF

402

R2686

0

1 2

5% 1/16W MF-LF

402

R2688

0

1 2

5% 1/16W MF-LF

402

LPC_RESET_L LPCPLUS_RESET_L

1/16W MF-LF

XDP

1/16W MF-LF

33

402

1K

402

MAKE_BASE=TRUE

SMC_LRESET_L

5%

PCA9557D_RESET_L

XDPPCH_PLTRST_L

5%

DPMUX_LRESET_L

0

SSD_RESET_L

5%

=ENET_RESET_L ENET_RESET_L

MAKE_BASE=TRUE

R2683

1 2

R2689

1 2

R2685

1 2

=TBT_RESET_L

Series R on Pg38, R3803

AP_RESET_L

R2693

0

1 2

5% 1/16W MF-LF

402

BKLT_PLT_RST_L

92

OUT

7

43

OUT

41

OUT

33

OUT

24

OUT

82

OUT

38

OUT

7

37

OUT

34

OUT

86

OUT

D

C

LPC 33MHz Clock Series Termination

LPC_CLK33M_SMC_R

19 92

IN

LPC_CLK33M_LPCPLUS_R

19

IN

LPC_CLK33M_DPMUX_UC_R

MAKE_BASE=TRUE

TP_PCI_CLK33M_OUT2

19

IN

PCH_CLK33M_PCIOUT

19

IN

B

System RTC Power Source & 32kHz / 25MHz Clock Generator

VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Ethernet power rail for XTAL circuit. VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

PLACE_NEAR=U1800.N52

PLACE_NEAR=U1800.P46

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

GreenClk 25MHz Power

Ethernet XTAL Power (Unused on 15" MBP) SB XTAL Power TBT XTAL Power

A

=PP3V3_S0_SYSCLK

8

=PPVDDIO_S0_SBCLK

8

=PPVDDIO_TBT_CLK

8

C2605

12PF

12

5%

50V

C0G-CERM

0402

C2606

12PF

1 2

5%

50V

C0G-CERM

0402

R2655

22

1 2

5%

1/20W

MF

R2656

PLACE_NEAR=U1800.P53

PLACE_NEAR=U1800.P48

201

R2657

22

1 2

5%

1/20W

MF

201

22

1 2

5%

1/20W

MF

201

R2659

22

1 2

5%

1/20W

MF

201

NO STUFF

R2607

1 2

NO STUFF

C2624

0.1UF

CERM

1

20% 10V

2

402

C2622

0.1UF

CERM

1

C2620

20% 10V

2

402

SYSCLK_CLK25M_X2

CRITICAL

13

Y2605

NC

24

SM-3.2X2.5MM

NC

25.000MHZ-12PF-20PPM

NOTE: 30 PPM crystal required

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

LPC_CLK33M_DPMUX_UC

PCH_CLK33M_PCIIN

8

0

5% 1/16W MF-LF

402

0.1UF

CERM

20% 10V

402

1

2

R2605

0

1 2

5% 1/16W MF-LF

402

1

2

SYSCLK_25M_B_GND

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

R2608

0

5% 1/16W MF-LF 402

SYSCLK_CLK25M_X1

=PPVBAT_G3_SYSCLK Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

=PP3V3_S5_SYSCLK Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5 No bypass necessary

OUT

C2602

1UF

10% 10V X5R

402-1

SYSCLK_CLK25M_X2_R

NO STUFF

1

R2606

1M

5% 1/16W MF-LF 402

2

6 3

41 92

7

82

17 92

43 92

1

2

5

VDD_25M

SLG3NB148A

CRITICAL

11

VDDIO_25M_A

CKPLUS_WAIVE=PwrTerm2Gnd

6

VDDIO_25M_B

14

VDDIO_25M_C

3

X2

4

X1

2

+V3.3A

U2600

TQFN

VDD_RTC_OUT

GND

71016

32KHZ_A

25MHZ_A 25MHZ_B 25MHZ_C

THRM

PAD

17

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 37

DP_AUXCH_ISOL

17 24

IN

13

VBAT and +V3.3A are internally ORed to

+3.42V

create VDD_RTC_OUT. +V3.3A should be first

available ~3.3V power to reduce VBAT draw.

12

SYSCLK_CLK32K_RTC

9

SYSCLK_CLK25M_SB

8

TP_SYSCLK_CLK25M_ENET

15

SYSCLK_CLK25M_TBT =PPVRTC_G3_OUT

1

For SB RTC Power

1

C2610

1UF

10%

6.3V

2

CERM 402

DP_AUXIO_EN INVERSION

R2630

10K

1 2

5%

1/20W

MF

201

D

Q2630

SOD-VESM-HF

SSM3K15FV

1

G S

NO STUFF

1

R2631

10K

5% 1/20W MF 201

2

8

3

2

OUT

DP_AUXIO_EN

C2639

0.1UF

10% 16V

X5R-CERM

0201

17 91

35 91

=PP3V3_S0_RSTBUF

8

25

Buffered CPU reset

CRITICAL

5

U2690

74LVC1G07

SC70

84 85

OUT

1

2

C2690

0.1UF

CERM

20% 10V

402

2

1

2

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

=PP3V3R1V5_S0_PCH_VCCSUSHDA

8

21 23

SPI_DESCRIPTOR_OVERRIDE_L

41 42

IN

NC

3

1

NC

SSM6N37FEAPE

4

PLT_RST_CPU_BUF_L

MAKE_BASE=TRUE

1

R2690

100K

5% 1/16W MF-LF 402

2

Q2620

SSM6N37FEAPE

SOT563

D

3

Q2620

SOT563

2

VTT pullup on CPU page

8

23

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

SG

1

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CPU_RESET_L

=PP5V_S0_PCH

1

R2620

100K

5% 1/20W MF 201

2

1

R2621

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

IPD = 9-50k

SYNC_DATE=01/13/2012

Chipset Support

Apple Inc.

R

OUT

17 92

OUT

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

26 OF 132

SHEET

25 OF 99

11 24

SIZE

B

A

D

124578

8 7 6 5 4 3

12

USBHUB2514B

USBHUB2513B

USBHUB2512B

NOSTUFF

1

R2723

10K

5% 1/16W MF-LF 402

2

49 96

BI

TO TP/KB

49 96

BI

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

TABLE_5_HEAD

TABLE_5_ITEM

8

26

C

B

BOM GROUP

HUB_ALLREM

HUB_1NONREM

USB MUX FOR LS/FS INTERNAL DEVICES

R2701

100

1 2

5% 1/16W MF-LF

402

1

R2706

10K

5% 1/16W MF-LF 402

2

1

C2702

0.1UF

10% 16V

2

X7R-CERM 0402

C2706

0.1UF

X7R-CERM

BYPASS=U2700.36::2MM

1

C2703

0.1UF

2

BYPASS=U2700.15::2MM

1

C2708

10% 16V

2

0402

0.1UF

X7R-CERM

USB_HUB_TEST

USB_HUB_RESET_L

26

USB_HUB_XTAL1 USB_HUB_XTAL2

USB_HUB_NONREM0

USB_HUB_NONREM1

USB_HUB_CFG_SEL0

USB_HUB_CFG_SEL1

1

R2707

10K

5% 1/16W MF-LF 402

2

10% 16V X7R-CERM 0402

10% 16V

0402

1

2

5

1015232936

VDD33

SYM VER 1

U2700

USB2513B

11

TEST

26

RESET*

33

XTALIN/CLKIN

32

XTALOUT

28

SUSP_IND/LOCAL_PWR/NON_REM0

22

SDA/SMBDATA/NON_REM1

24

SCL/SMBCLK/CFG_SEL0

25

HS_IND/CFG_SEL1

QFN

OMIT

CKPLUS_WAIVE=NdifPr_badTerm

THRM_PAD

PPUSB_HUB2_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

14

34

CRFILT

PLLFILT

USBDM_DN1/PRT_DIS_M1 USBDP_DN1/PRT_DIS_P1

USBDM_DN2/PRT_DIS_M2 USBDP_DN2/PRT_DIS_P2

USBDM_DN3/PRT_DIS_M3 USBDP_DN3/PRT_DIS_P3

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2* PRTPWR3/BC_EN3*

37

IPU IPU IPU IPU

OCS1* OCS2* OSC3*

RBIAS

VBUS_DET

USBDM_UP USBDP_UP

1

C2711

0.1UF

10% 16V

2

X7R-CERM 0402

1

USBHUB_DN1_N

2

USBHUB_DN1_P

3

USBHUB_DN2_N

4

USBHUB_DN2_P

6

USBHUB_DN3_N

7

USBHUB_DN3_P

8

USBHUB_DN4_N

NC

9

USBHUB_DN4_P

NC

12

TP_USB_HUB_PRTPWR1

16

NC_USB_HUB_PRTPWR2

18

NC_USB_HUB_PRTPWR3

20

NC_USB_HUB_PRTPWR4

NC

13

TP_USB_HUB_OCS1

17

NC_USB_HUB_OCS2

19

NC_USB_HUB_OCS3

21

NC_USB_HUB_OCS4

NC

35

USB_HUB_RBIAS

27

USB_HUB_VBUS_DET

30

USB_HUB_UP_N

31

USB_HUB_UP_P

PCH PORT 7 (EHCI1)

1

2

=PP3V3_S3_USB_HUB

8

D

C

26

1/16W MF-LF

10K

HUB_NONREM0_1

1

R2703

10K

5%

1/16W MF-LF 402

402

2

HUB_NONREM0_0

1

R2705

10K

5%

1/16W MF-LF 402

402

2

HUB_NONREM1_1

R2702

HUB_NONREM1_0

R2704

15" MBP USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION MBP OG USES 197S0284 FOR Y2700 TO SAVE COST

B

BYPASS=U27000.5::5MM

BYPASS=U2700.23::5MM

CRITICAL

1

C2709

18PF

5%

50V

2

C0G-CERM

0402

=PP3V3_S3_USB_RESET

8

C2700

4.7UF

20%

6.3V X5R 603

BYPASS=U2700.10::2MM

C2704

4.7UF

20%

6.3V X5R 603

CRITICAL

Y2700

SM-2

24.000MHZ-16PF

1 3

2 4

NC

R2700

1M

1 2

5% 1/16W MF-LF

402

CRITICAL

1

2

1

2

1

R2712

10K

5% 1/16W MF-LF 402

2

USB_HUB_RESET_L

C2701

1

0.1UF

10% 16V

2

X7R-CERM

0402

BYPASS=U2700.29::2MM

1

C2705

0.1UF

10% 16V

2

X7R-CERM

0402

BYPASS=U2700.5::2MM

BYPASS=U2650.23::2MM

CRITICAL

1

C2710

18PF

5% 50V

2

C0G-CERM 0402

26

HUB_2NONREM HUB_3NONREM

NON_REM 1 : NON_REM 0 STRAP PIN CFG 0 : 0 ALL PORTS ARE REMOVABLE

0 : 1 PORT 1 IS NON REMOVABLE 1 : 0 PORT 1&2 ARE NON REMOVABLE

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

1

C2714

1UF

10% 16V

2

X5R 402

BLUETOOTH FOR 15" MBP & MBP OG

TRACKPAD/KEYBOARD FOR 15" MBP & MBP OG

SMC DEBUG PORT FOR 15" MBP, IR for MBP OG

NC FOR 15" MBP, SMC DEBUG PORT FOR MBP OG

=PP3V3_S3_USB_HUB

1

R2708

10K

5% 1/16W MF-LF 402

2

C2712

1UF

10% 16V X5R 402

BI BI

9

26

9

26

BI BI

7

19 91

9

26

1

C2713

0.1UF

10% 16V

2

X7R-CERM 0402

CRITICAL

1

R2709

12K

1% 1/16W MF 402

2

1 : 1 PORT 1&2&3 ARE NON REMOVABLE

15" MBP ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B MBP OG ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

26

8

26

TO CONNECT TP/KB TO PCH XHCI NOSTUFF R5701 & R5702, STUFF R2720 & R2721

USB_EXTD_XHCI_N

19 91

BI

26

TO PCH XHCI

USB_EXTD_XHCI_P

19 91

BI

HUB_NONREM1_0,HUB_NONREM0_0 HUB_NONREM1_0,HUB_NONREM0_1 HUB_NONREM1_1,HUB_NONREM0_0 HUB_NONREM1_1,HUB_NONREM0_1

PART#

338S0824

338S0923

338S0983

USBHUB_DN3_N

9

USBHUB_DN3_P

9

USBHUB_DN4_N

9

USBHUB_DN4_P

9

USBHUB_DN2_N

9

USBHUB_DN2_P

9

BOM OPTIONS

BOM TABLE

DESCRIPTION

QTY

1

USB HUB 2514B

USB HUB 2513B

1

USB HUB 2512B

1

NOSTUFF

1

R2716

10K

5% 1/16W MF-LF 402

2

NOSTUFF

R2721

27

1 2

5% 1/16W MF-LF

402

NOSTUFF

1

R2717

10K

5% 1/16W MF-LF 402

2

1 2

REFERENCE DESIGNATOR(S)

NOSTUFF

R2720

27

5% 1/16W MF-LF

402

NOSTUFF

1

R2718

10K

5% 1/16W MF-LF 402

2

U2700

NOSTUFF

1

R2719

10K

5% 1/16W MF-LF 402

2

CRITICAL BOM OPTION

CRITICAL

NOSTUFF

1

R2722

10K

5% 1/16W MF-LF 402

2

USB_TPAD_R_N

USB_TPAD_R_P

=PP3V3_S3_USB_HUB

1

C2715

0.1UF

10% 16V

2

X7R-CERM

BYPASS=U2700.26::2MM

A

0402

USB XHCI/EHCI2 PORT MUX FOR EXT B

=PP3V3_S3_USBMUX

8

1

PCH PORT 9 (EHCI2)

PCH PORT 1 (XHCI)

C2760

0.1UF

20% 10V

2

CERM

19

BI

91 19 91

BI

19

BI

91 19 91

BI

USB_EXTB_EHCI_P USB_EXTB_EHCI_N

USB_EXTB_XHCI_P USB_EXTB_XHCI_N

402

5 4

7 6

8

6 3

M+ M-

U2760

PI3USB102ZLE D+ D-

9

VCC

TQFN

CRITICAL

GND

3

1

Y+

2

Y-

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

10

SELOE*

SEL=0 CHOOSE USB EHCI2 PORT SEL=1 CHOOSE USB XHCI PORT

USB_EXTB_P USB_EXTB_N

USB_EXTB_SEL_XHCI

7

38 91

BI

7

38 91

BI

17

IN

TO CONNECTOR

PCH GPIO60

SYNC_MASTER=D2_KEPLER

PAGE TITLE

USB HUB & MUX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

27 OF 132

SHEET

26 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PM_SLP_S4_L

7

18 34 38 40 41 70

IN

=PP3V3_S3_MEMRESET

8

C

ISOLATE_CPU_MEM_L

24

IN IN

=PP5V_S3_MEMRESET

8

27

CPUMEM_S0

B

NOSTUFF

C2817

0.047UF

10%

6.3V X5R 201

=MEM_RESET_L

11

IN

R2815

100K

1/16W MF-LF

402

1

2

1

5%

2

CRITICAL

CPUMEM_S0

Q2815

SSM6N15FEAPE

SOT563

D

6

MEMRESET_ISOL_LS5V_L

33

CPU_MEM_RESET_L

MAKE_BASE=TRUE

2

S G

1

CPUMEM_S0

R2801

CRITICAL

CPUMEM_S0

Q2800

SSM6N15FEAPE

SOT563

CPUMEM_S0

R2802

CRITICAL

CPUMEM_S0

Q2800

SSM6N15FEAPE

SOT563

CRITICAL

CPUMEM_S0

Q2815

SSM6N15FEAPE

5

S G

4

100K

1/16W MF-LF

5

100K

1/16W MF-LF

2

5%

402

5%

402

SOT563

1

2

3

D

SG

4

1

2

6

D

SG

1

D

3

CRITICAL

CPUMEM_S0

Q2805

SSM6N15FEAPE

P1V5CPU_EN_L

CRITICAL

CPUMEM_S0

Q2810

SSM6N15FEAPE

MEMVTT_EN_L

=PP1V5_S3_MEMRESET

CPUMEM_S0

1

R2816

1K

5% 1/16W MF-LF 402

2

SOT563

2

3

4

2

3

4

D

S G

D

S G

1

2

CPUMEM_S0

C2816

0.1UF

10% 16V X7R-CERM 0402

CPUMEM_S0

1

R2805

10K

5% 1/16W MF-LF 402

2

P1V5CPU_EN

6

D

SG

1

CRITICAL

CPUMEM_S0

Q2805

SSM6N15FEAPE

SOT563

5

PM_SLP_S3_L

CPUMEM_S0

1

R2810

10K

5% 1/16W MF-LF 402

2

MEMVTT_EN

6

D

SG

1

CRITICAL

CPUMEM_S0

Q2810

SSM6N15FEAPE

SOT563

5

PLT_RESET_L

8

MEM_RESET_L

69

OUT

7

18 38 41 70

9

OUT

19 25

IN

28 29 30 31

OUT

CPUMEM_S3

R2817

0

1 2

5% 1/16W MF-LF

402

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1 1 0 1 1 1 1 1 1 1

to

2 0 0 1 1 1 1 0 1

A

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1 5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

6 3

PART NUMBER

=PP1V5_S3_CPU_VCCDDR

8

11 14 16

OMIT_TABLE

114S0365

114S0376

QTY

DESCRIPTION

1

RES,MTL FILM,1/16W,33.2K,1,0402,SMD,LF

RES,MTL FILM,1/16W,43.2K,1,0402,SMD,LF

REFERENCE DES

1V5 S0 "PGOOD" for CPU

=PP3V3_S5_CPU_VCCDDR

8

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

1

R2822

10K

5%

R2820

27.4K

1/16W MF-LF

R2821

33.2K

1/16W MF-LF

1

1%

402

2

1

1%

402

2

P1V5_S0_DIV

C2820

4700PF

10% 100V CERM

402

1/16W MF-LF 402

2

PM_MEM_PWRGD_L

CRITICAL

3

Q2820

5

DMB53D0UV

SOT-563

1

2

4

CRITICAL

G

2

MEMVTT Clamp

Ensures CKE signals are held low in S3

=PPVTT_S0_VTTCLAMP

8

=PP5V_S3_MEMRESET

8

27

SSM6N15FEAPE

=DDRVTT_EN

9

64

IN

CPUMEM_S0

R2851

CRITICAL

CPUMEM_S0

Q2850

SOT563

5

100K

1/16W MF-LF

1

5%

402

2

D

SG

CRITICAL

CPUMEM_S0

SSM6N15FEAPE

VTTCLAMP_EN

NO STUFF

3

C2851

0.001UF

4

Q2850

SOT563

20% 50V

CERM

402

2

1

2

R2821

D

SG

6

1

PM_MEM_PWRGD

6 D

Q2820

DMB53D0UV

SOT-563

S 1

CPUMEM_S0

R2850

VTTCLAMP_L

CRITICAL

1

10

5% 1/10W MF-LF

603

2

SYNC_MASTER=D2_KEPLER

PAGE TITLE

BOM OPTION

PPDDR:1V5

PPDDR:1V35

11 18 89

OUT

75mA max load @ 0.75V 60mW max power

CPU Memory S3 Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

28 OF 132

SHEET

27 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

1

C2907

0.47UF

20%

4V

CERM-X5R-1

32 90

MEM_A_A<0>

12 28

29

90

MEM_A_A<1>

12 28

D

29 32

MEM_A_A<2>

32 90

MEM_A_A<3>

12 28

90

29

29 32

MEM_A_A<4>

12 28 32 90

MEM_A_A<5>

12 28

29

90

MEM_A_A<6>

12 28 29 32

MEM_A_A<7>

32 90

MEM_A_A<8>

12 28

29

90

MEM_A_A<9>

12 28 29 32

MEM_A_A<10>

12 28 29 32

32

90

MEM_A_A<11>

12 28

29

32 90

90

MEM_A_A<12>

12 28

29

90

MEM_A_A<13>

12 28 29 32

MEM_A_A<14>

12 28 29 32

90

MEM_A_A<15>

12 28 29 32

90

MEM_A_BA<0>

12 28 29 32

MEM_A_BA<1>

12 28 29 32

90

MEM_A_BA<2>

12 28 29 32

90

MEM_A_RAS_L

12 28 29 32

MEM_A_CAS_L

90

MEM_A_WE_L

12 28 29 32

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<0>

2

C

R2900

240

1% 1/20W MF 201

1

2

201

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A3

A10D8G9G3K2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

B2

28 29 33 89

K10M2M10

VDD

OMIT_TABLE

U2900

DDR3-1333

FBGA

(SYM VER 2)

VSS

J2L2N2F3A9D9F9

J10

B10C2E3

L10

N10

VDDQ

8

28 29

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

=PP1V5R1V35_S3_MEM_A

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5>

12 28 29 32 90

MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<1>

2

R2910

240

1% 1/20W MF 201

1

C2917

1

C2908

0.47UF 0.47UF

20%

4V

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFDQ

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<0>

DQ0

C8

MEM_A_DQ<6>

DQ1

C3

MEM_A_DQ<7>

DQ2

C9

MEM_A_DQ<5>

DQ3

E4

MEM_A_DQ<3>

E9

MEM_A_DQ<1>

D3

MEM_A_DQ<2>

E8

MEM_A_DQ<4>

C4

MEM_A_DQS_P<0>

DQS

D4

MEM_A_DQS_N<0>

DQS*

B8 A8

NC

H3

MEM_A_CS_L<0>

CS*

G10

MEM_A_CKE<0>

CKE

F8

MEM_A_CLK_P<0>

CK

G8

MEM_A_CLK_N<0>

CK*

A1

NC NC

A4

NC

A11

NC

F2

NC

F10

NC

C10

D10

C2909

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 29 90

12 28 32 90

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U2910

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

N10

VDDQ

8

28 29

E10J9E2

NF/TDQS*

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

1

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<2>

2

R2920

240

1% 1/20W MF 201

1

C2927

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A10D8G9G3K2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

B2

201

1

C2918

0.47UF

20%

4V

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<14>

DQ0

C8

MEM_A_DQ<9>

DQ1

C3

MEM_A_DQ<10>

DQ2

C9

MEM_A_DQ<15>

DQ3

E4

MEM_A_DQ<11>

E9

MEM_A_DQ<13>

D3

MEM_A_DQ<8>

E8

MEM_A_DQ<12>

C4

MEM_A_DQS_P<1>

DQS

D4

MEM_A_DQS_N<1>

B8 A8

NC NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

CK

G8

MEM_A_CLK_N<0>

A1 A4

NC

A11

NC

F2

NC

F10

NC

C2919

20% 4V

2

CERM-X5R-1 201201

90

27 28 29 30 31

12 28 29 32 90

12 29 90

12 28 32 90

D10

28 29 33 89

K10M2M10

VDD

OMIT_TABLE OMIT_TABLE

U2920

DDR3-1333

FBGA

(SYM VER 2)

VSS

J2L2N2F3A9D9F9

J10

B10C2E3

L10

N10

VDDQ

8

28 29

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C2928

0.47UF

CERM-X5R-1

NC

1

20%

4V

2

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<22>

C8

MEM_A_DQ<21>

C3

MEM_A_DQ<16>

C9

MEM_A_DQ<17>

E4

MEM_A_DQ<18>

E9

MEM_A_DQ<23>

D3

MEM_A_DQ<20>

E8

MEM_A_DQ<19>

C4

MEM_A_DQS_P<2>

D4

MEM_A_DQS_N<2>

B8 A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C2929

0.47UF

20% 4V

2

CERM-X5R-1 201

90

12 28 29 32 90

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32 27 28 29 30 31

MEM_A_A<2> MEM_A_A<3>

12 29 90

MEM_A_A<4>

12 29 90

MEM_A_A<5>

12 29 90

MEM_A_A<6>

12 29 90

MEM_A_A<7>

12 29 90

MEM_A_A<8>

12 29 90

MEM_A_A<9>

12 29 90

MEM_A_A<10>

12 29 90

MEM_A_A<11>

12 29 90

MEM_A_A<12>

12 29 90

MEM_A_A<13>

12

28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0>

12 28 32 90

MEM_A_BA<1>

12 28 32 90

MEM_A_BA<2>

12 28 32 90

MEM_A_RAS_L

12 28 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<3>

2

R2930

240

1% 1/20W MF 201

1

C2937

0.47UF

CERM-X5R-1

=PP1V5R1V35_S3_MEM_A

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

K10M2M10

B10C2E3

VDD

U2930

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

8

VDDQ

28 29

E10J9E2

NF/TDQS*

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

DQ0 DQ1 DQ2 DQ3

DQS

CK

C2938

0.47UF

20%

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<31>

C8

MEM_A_DQ<24>

C3

MEM_A_DQ<27>

C9

MEM_A_DQ<28>

E4

MEM_A_DQ<30>

E9

MEM_A_DQ<25>

D3

MEM_A_DQ<26>

E8

MEM_A_DQ<29>

C4

MEM_A_DQS_P<3>

D4

MEM_A_DQS_N<3>

B8 A8

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

C2939

0.47UF

20%

4V

2

CERM-X5R-1 201

D

27 28 29 30 31

12 29 90

12 28 32 90

C

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A10D8G9G3K2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

B2

201

C2947

CERM-X5R-1

90

MEM_A_A<0>

12 28 29 32

MEM_A_A<1>

90

MEM_A_A<2>

12 28 29 32

MEM_A_A<3>

12 28 29 32

90

MEM_A_A<4>

12 28 29 32

90

MEM_A_A<5>

12 28 29 32

MEM_A_A<6>

90

MEM_A_A<7>

12 28 29 32

MEM_A_A<8>

12 28 29 32

90

MEM_A_A<9>

12 28 29 32

B

90

MEM_A_A<10>

12 28 29 32

MEM_A_A<11>

32 90

MEM_A_A<12>

12 28

90

29

29 32

MEM_A_A<13>

12 28 32 90

MEM_A_A<14>

12 28

29

90

MEM_A_A<15>

12 28 29 32 90 29 32

MEM_A_BA<0>

12 28 32 90

MEM_A_BA<1>

12 28

29

90

MEM_A_BA<2>

12 28 29 32

90

MEM_A_RAS_L

12 28 29 32

MEM_A_CAS_L

90

MEM_A_WE_L

12 28 29 32

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<4>

2

R2940

240

1% 1/20W MF 201

1

28 29 33 89

K10M2M10

VDD

OMIT_TABLE

U2940

DDR3-1333

FBGA

(SYM VER 2)

VSS

J2L2N2F3A9D9F9

J10

B10C2E3

L10

N10

VDDQ

8

28 29

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

VREFCA

D10

1

C2948

0.47UF

4V

CERM-X5R-1

NC

2

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<32>

C8

MEM_A_DQ<33>

C3

MEM_A_DQ<34>

C9

MEM_A_DQ<35>

E4

MEM_A_DQ<36>

E9

MEM_A_DQ<37>

D3

MEM_A_DQ<38>

E8

MEM_A_DQ<39>

C4

MEM_A_DQS_P<4>

D4

MEM_A_DQS_N<4>

B8 A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C2949

0.47UF

20%20% 4V

2

CERM-X5R-1 201

90

12 28 29 32 90

12 28 29 32 27 28 29 30 31

12 29 90

12

28 29 32 90

12 28 29 32 90

MEM_A_BA<0>

12 28 32 90

MEM_A_BA<1>

12 28 32 90

MEM_A_BA<2>

12 28 32 90

MEM_A_RAS_L

12 28 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

2

R2950

240

1% 1/20W MF 201

1

C2957

0.47UF

CERM-X5R-1

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_A_ZQ<5>

=PP1V5R1V35_S3_MEM_A

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U2950

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

N10

VDDQ

8

28 29

E10J9E2

NF/TDQS*

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C2958

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C2959

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47>

MEM_A_DQS_P<5> MEM_A_DQS_N<5>

NC

MEM_A_CS_L<0> MEM_A_CKE<0>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

90

12 28 29 32 90

12 28 29 32 27 28 29 30 31

12 29 90

12

28 29 32 90

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28 32 90

2

R2960

1

240

1% 1/20W MF 201

C2967

0.47UF

20%

CERM-X5R-1

201

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_ODT<0> MEM_A_ZQ<6>

=PP1V5R1V35_S3_MEM_A

1

4V

2

A3

A10D8G9G3K2

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

B2

J2L2N2F3A9D9F9

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

1

C2968

0.47UF

20%

K10M2M10

B10C2E3

E10J9E2

FBGA

VDDQ

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

DQ0 DQ1 DQ2 DQ3

DQS

VDD

OMIT_TABLE OMIT_TABLE

U2960

DDR3-1333

(SYM VER 2)

CK*

NC

VSS

J10

L10

N10

VSSQ

B3D2B9

C10

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<48>

C8

MEM_A_DQ<49>

C3

MEM_A_DQ<50>

C9

MEM_A_DQ<51>

E4

MEM_A_DQ<52>

E9

MEM_A_DQ<53>

D3

MEM_A_DQ<54>

E8

MEM_A_DQ<55>

C4

MEM_A_DQS_P<6>

D4

MEM_A_DQS_N<6>

B8 A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

CK

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

4V

201

C2969

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 29 90

12 28 32 90

C2977

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5>

12 28 29 32 90

MEM_A_A<6>

12 28 29 32 90

MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<7>

2

R2970

240

1% 1/20W MF 201

1

0.47UF

=PP1V5R1V35_S3_MEM_A

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

VDD

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

K10M2M10

B10C2E3

E10J9E2

VDDQ

U2970

DDR3-1333

FBGA

(SYM VER 2)

VSS

B3D2B9

L10

N10

J10

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C2978

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C2979

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQS_P<7> MEM_A_DQS_N<7>

NC

MEM_A_CS_L<0> MEM_A_CKE<0>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

27 28 29 30 31

12 29 90

B

12 29 90

12 28 32 90

=PP1V5R1V35_S3_MEM_A

8

28 29

A

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2910

20% 10V

2

402

1

C2950

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C2911

2.2UF

C2951

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C2920

2.2UF

X5R-CERM

C2960

2.2UF

X5R-CERM

1

C2921

20% 10V

2

X5R-CERM

402

1

C2961

20% 10V

2

X5R-CERM

402

1

C2900

2.2UF

X5R-CERM X5R-CERM

C2940

2.2UF

X5R-CERM

C2901

20% 10V

2

402

1

C2941

20% 10V

2

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2.2UF

1

20% 10V

2

402

1

20% 10V

2

402

C2930

2.2UF

X5R-CERM

C2970

2.2UF

X5R-CERM

1

C2931

2.2UF

X5R-CERM

C2971

2.2UF

X5R-CERM

20% 10V

402

20% 10V

402

20% 10V

2

402

1

20% 10V

2

402

1

C2903

0.1UF

10%

6.3V

2

1

2

X5R 201

1

C2943

0.1UF

10%

6.3V

2

X5R 201

1

C2904

0.1UF

10%

6.3V

2

X5R 201

1

C2944

0.1UF

10%

6.3V

2

X5R 201

1

C2905

0.1UF

10%

6.3V

2

X5R 201

1

C2945

0.1UF

10%

6.3V

2

X5R 201

6 3

1

C2913

0.1UF

10%

6.3V

2

X5R 201

1

C2953

0.1UF

10%

6.3V

2

X5R 201

1

C2914

0.1UF

10%

6.3V

2

X5R 201

1

C2954

0.1UF

10%

6.3V

2

X5R 201

1

C2915

0.1UF

10%

6.3V

2

X5R 201

1

C2955

0.1UF

10%

6.3V

2

X5R 201

1

C2923

0.1UF

10%

6.3V

2

X5R 201

1

C2963

0.1UF

10%

6.3V

2

X5R 201

1

C2924

0.1UF

10%

6.3V

2

X5R 201

1

C2964

0.1UF

10%

6.3V

2

X5R 201

1

C2925

0.1UF

10%

6.3V

2

X5R 201

1

C2965

0.1UF

10%

6.3V

2

X5R 201

1

C2933

0.1UF

10%

6.3V

2

X5R 201

1

C2973

0.1UF

10%

6.3V

2

X5R 201

1

C2934

0.1UF

10%

6.3V

2

X5R 201

1

C2974

0.1UF

10%

6.3V

2

X5R 201

1

C2935

0.1UF

10%

6.3V

2

X5R 201

1

C2975

0.1UF

10%

6.3V

2

X5R 201

SYNC_MASTER=D2_KEPLER

PAGE TITLE

DDR3 SDRAM Bank A (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

29 OF 132

SHEET

28 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

=PP1V5R1V35_S3_MEM_A

8

28 29

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

=PP1V5R1V35_S3_MEM_A

8

28 29

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

=PP1V5R1V35_S3_MEM_A

12

8

28 29

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3000

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

VDDQ

B3D2B9

8

28 29

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

VREFCA

D10

1

C3008

0.47UF

20%

4V

CERM-X5R-1

NC

2

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<6>

C8

MEM_A_DQ<0>

C3

MEM_A_DQ<5>

C9

MEM_A_DQ<7>

E4

MEM_A_DQ<4>

E9

MEM_A_DQ<2>

D3

MEM_A_DQ<1>

E8

MEM_A_DQ<3>

C4

MEM_A_DQS_P<0>

D4

MEM_A_DQS_N<0>

B8 A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3009

0.47UF

20% 4V

2

CERM-X5R-1 201

C3017

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

90

27 28 29 30 31

MEM_A_A<2>

12 28 29 32 90

MEM_A_A<4>

12 28 90

MEM_A_A<3>

12 28 90

MEM_A_A<6>

12 28 90

MEM_A_A<5>

12 28 90

MEM_A_A<8>

12 28 90

MEM_A_A<7>

12 28 90

MEM_A_A<9>

12 28 90

MEM_A_A<10>

12 28 90

MEM_A_A<11>

12 28 90

MEM_A_A<12>

90

12 28

MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1>

12 28 29 32 90

MEM_A_BA<0>

12 29 32 90

MEM_A_BA<2>

12 29 32 90

MEM_A_RAS_L

12 28 29 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<9>

2

R3010

240

1% 1/20W MF 201 201

1

C3007

CERM-X5R-1

90

MEM_A_A<0>

12 28 29 32

90 12 28 29 32

12 28 29 32

90

90 12 28 29 32

90

12 28

29 32

90

12 28

29 32

12 28

29 32

90

90 12 28 29 32

90

12 28

29 32

90

12 28

29 32

90

12 28

29 32

12 28

29 32

90

29 32

12 28

32 90

12 28

29

90

12 28

29 32

32 90

12 28

29

90

12 28

29 32

12 28

29 32

90

12 29

32 90

2

1

MEM_A_A<1> MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_ODT<1> MEM_A_ZQ<8>

R3000

240

1% 1/20W MF 201

D

C

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

1

C3018

0.47UF

20%

K10M2M10

B10C2E3

E10J9E2

FBGA

VDDQ

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

DQ0 DQ1 DQ2 DQ3

DQS

VDD

OMIT_TABLE OMIT_TABLE

U3010

DDR3-1333

(SYM VER 2)

CK*

NC

VSS

L10

J10

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

N10

8

B3D2B9

28 29

VSSQ

C10

4V

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<9>

C8

MEM_A_DQ<14>

C3

MEM_A_DQ<15>

C9

MEM_A_DQ<10>

E4

MEM_A_DQ<12>

E9

MEM_A_DQ<8>

D3

MEM_A_DQ<13>

E8

MEM_A_DQ<11>

C4

MEM_A_DQS_P<1>

D4

MEM_A_DQS_N<1>

B8 A8

NC NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

CK

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

C3019

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90 12 28 29 32 90

12 28 90

12 29 32 90

C3027

0.47UF

20%

4V

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<10>

2

R3020

240

1% 1/20W MF

1

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

VDD

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

B10C2E3

E10J9E2

VDDQ

U3020

DDR3-1333

FBGA

(SYM VER 2)

VSS

B3D2B9

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_APP0V75_S3_MEM_VREFDQ_A

28 29 33 89 28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3028

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3029

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<23> MEM_A_DQ<18>

MEM_A_DQS_P<2> MEM_A_DQS_N<2>

NC

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

90

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32 27 28 29 30 31

MEM_A_A<4>

12 28 90

MEM_A_A<3>

12 28 90

MEM_A_A<6>

12 28 90

MEM_A_A<5>

12 28 90

MEM_A_A<8>

12 28 90

MEM_A_A<7>

12 28 90

MEM_A_A<9>

12 28 90

MEM_A_A<10>

12 28 90

MEM_A_A<11>

12 28 90

MEM_A_A<12>

12 28 90

MEM_A_A<13>

12

28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1>

12 29 32 90

MEM_A_BA<0>

12 29 32 90

MEM_A_BA<2>

12 29 32 90

MEM_A_RAS_L

12 29 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<11>

2

R3030

240

1% 1/20W MF 201

1

C3037

0.47UF

CERM-X5R-1

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3030

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

VDDQ

8

28 29

E10J9E2

DM/TDQS

NF/TDQS*

VSSQ

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

NC

CS* CKE

CK*

C10

DQ0 DQ1 DQ2 DQ3

DQS

CK

C3038

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11

VREFCA

N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

D10

1

C3039

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<24> MEM_A_DQ<31> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<29> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<30>

MEM_A_DQS_P<3> MEM_A_DQS_N<3>

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

D

27 28 29 30 31

12 28 90

12 29 32 90

C

C3047

CERM-X5R-1

90

MEM_A_A<0>

12 28 29 32

MEM_A_A<1>

90

MEM_A_A<2>

12 28 29 32

MEM_A_A<4>

12 28 29 32

90

MEM_A_A<3>

12 28 29 32

90

MEM_A_A<6>

12 28 29 32

MEM_A_A<5>

90

MEM_A_A<8>

12 28 29 32

MEM_A_A<7>

12 28 29 32

90

MEM_A_A<9>

12 28 29 32

B

90

MEM_A_A<10>

12 28 29 32

MEM_A_A<11>

32 90

MEM_A_A<12>

12 28

90

29

29 32

MEM_A_A<13>

12 28 32 90

MEM_A_A<14>

12 28

29

90

MEM_A_A<15>

12 28 29 32 90 29 32

MEM_A_BA<1>

12 28 32 90

MEM_A_BA<0>

12 28

29

90

MEM_A_BA<2>

12 28 29 32

32 90

MEM_A_RAS_L

12 28

29

90

MEM_A_CAS_L

12 28 29 32

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<12>

2

R3040

240

1% 1/20W

201

1

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

VDD

OMIT_TABLE

U3040

DDR3-1333

(SYM VER 2)

VSS

8

FBGA

28 29

J10

B10C2E3

L10

N10

VDDQ

E10J9E2

RESET*

DM/TDQS

NF/TDQS*

VSSQ

B3D2B9

VREFDQ

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3048

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3049

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36>

MEM_A_DQS_P<4> MEM_A_DQS_N<4>

NC

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 28 90

12 28

12 29 32 90

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<4>

12 28 29 32 90

MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7>

12 28 29 32 90

MEM_A_A<9>

12 28 29 32 90

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12>

90

MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0>

12 28 29 32 90

MEM_A_BA<2> MEM_A_RAS_L

12 28 29 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<13>

2

R3050

240

1% 1/20W MFMF 201

1

C3057

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3050

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

C3058

0.47UF

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<41>

C8

MEM_A_DQ<40>

C3

MEM_A_DQ<43>

C9

MEM_A_DQ<42>

E4

MEM_A_DQ<47>

E9

MEM_A_DQ<46>

D3

MEM_A_DQ<45>

E8

MEM_A_DQ<44>

C4

MEM_A_DQS_P<5>

D4

MEM_A_DQS_N<5>

B8 A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

20%

201

1

C3059

0.47UF

20%

4V

2

CERM-X5R-1 201

27 28 29 30

12 28 29 32 90

31 12 28

90 12 28

90

12 28 90

12 28

12 29 32 90

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32 90

MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6>

12 28 29 32 90

MEM_A_A<5> MEM_A_A<8>

12 28 29 32 90

MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12>

90

MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<14>

2

R3060

240

1% 1/20W

201

1

C3067

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3060

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3068

0.47UF

CERM-X5R-1

NC

20%

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<49>

C8

MEM_A_DQ<48>

C3

MEM_A_DQ<51>

C9

MEM_A_DQ<50>

E4

MEM_A_DQ<55>

E9

MEM_A_DQ<54>

D3

MEM_A_DQ<53>

E8

MEM_A_DQ<52>

C4

MEM_A_DQS_P<6>

D4

MEM_A_DQS_N<6>

B8 A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3069

0.47UF

20%

4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 28 90

12 29 32 90

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12

28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<15>

2

R3070

240

1% 1/20W MFMF 201

1

A

C3000

2.2UF

X5R-CERM

C3040

2.2UF

X5R-CERM

1

C3001

20% 10V

2

402

1

C3041

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C3010

20% 10V

2

402

1

C3050

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3011

2.2UF

X5R-CERM

C3051

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3020

2.2UF

X5R-CERM

C3060

2.2UF

X5R-CERM

1

C3021

20% 10V

2

402

1

C3061

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3030

2.2UF

X5R-CERM

C3070

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3031

2.2UF

X5R-CERM

C3071

2.2UF

X5R-CERM

1

C3003

2

1

2

0.1UF 0.1UF

10%

6.3V

2

X5R 201

1

C3043

0.1UF

10%

6.3V

2

X5R 201

20% 10V

402

20% 10V

402

1

C3004

10%

6.3V

2

X5R 201

1

C3044

0.1UF

10%

6.3V

2

X5R 201

1

C3005

0.1UF

10%

6.3V

2

X5R 201

1

C3045

0.1UF

10%

6.3V

2

X5R 201

1

C3013

0.1UF

10%

6.3V

2

X5R 201

1

C3053

0.1UF

10%

6.3V

2

X5R 201

1

C3014

0.1UF

10%

6.3V

2

X5R 201

1

C3054

0.1UF

10%

6.3V

2

X5R 201

1

C3015

0.1UF

10%

6.3V

2

X5R 201

1

C3055

0.1UF

10%

6.3V

2

X5R 201

1

C3023

0.1UF

10%

6.3V

2

X5R 201

1

C3063

0.1UF

10%

6.3V

2

X5R 201

1

C3024

0.1UF

10%

6.3V

2

X5R 201

1

C3064

0.1UF

10%

6.3V

2

X5R 201

1

C3025

0.1UF

10%

6.3V

2

X5R 201

1

C3065

0.1UF

10%

6.3V

2

X5R 201

1

C3033

0.1UF

10%

6.3V

2

X5R 201

1

C3073

0.1UF

10%

6.3V

2

X5R 201

1

C3034

0.1UF

10%

6.3V

2

X5R 201

1

C3074

0.1UF

10%

6.3V

2

X5R 201

1

C3035

0.1UF

10%

6.3V

2

X5R 201

1

C3075

0.1UF

10%

6.3V

2

X5R 201

6 3

C3077

0.47UF

1

20%

4V

2

A3

201

A10D8G9G3K2

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

B2

J2L2N2F3A9D9F9

SYNC_MASTER=D2_KEPLER

PAGE TITLE

K10M2M10

VDD

OMIT_TABLE

U3070

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

C3078

0.47UF

20%

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<57>

DQ0

C8

MEM_A_DQ<56>

DQ1

C3

MEM_A_DQ<59>

DQ2

C9

MEM_A_DQ<58>

DQ3

E4

MEM_A_DQ<63>

E9

MEM_A_DQ<62>

D3

MEM_A_DQ<61>

E8

MEM_A_DQ<60>

C4

MEM_A_DQS_P<7>

DQS

D4

MEM_A_DQS_N<7>

DQS*

B8 A8

NC

H3

MEM_A_CS_L<1>

CS*

G10

MEM_A_CKE<1>

CKE

F8

MEM_A_CLK_P<1>

CK

G8

MEM_A_CLK_N<1>

CK*

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C10

D10

SYNC_DATE=01/13/2012

DDR3 SDRAM Bank A (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

4V

2

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

30 OF 132

SHEET

29 OF 99

1

C3079

0.47UF

20% 4V

2

CERM-X5R-1 201

27 28 29 30 31

12 28 90

B

12 28 90

12 29 32 90

A

SIZE

D

124578

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

8

30 31

=PP1V5R1V35_S3_MEM_B

30 31 33 89

8

30 31

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

8

30 31

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

=PP1V5R1V35_S3_MEM_B

12

8

30 31

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3100

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

VDDQ

B3D2B9

8

30 31

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

VREFCA

D10

1

C3108

0.47UF

20%

4V

CERM-X5R-1

NC

2

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<6>

C8

MEM_B_DQ<1>

C3

MEM_B_DQ<3>

C9

MEM_B_DQ<5>

E4

MEM_B_DQ<2>

E9

MEM_B_DQ<4>

D3

MEM_B_DQ<7>

E8

MEM_B_DQ<0>

C4

MEM_B_DQS_P<0>

D4

MEM_B_DQS_N<0>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3109

0.47UF

20% 4V

2

CERM-X5R-1 201

C3117

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 31 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

32 90

MEM_B_A<11>

12 30

31

90

MEM_B_A<12>

12 30 31 32

MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<1>

2

R3110

240

1% 1/20W MF MF

1

C3107

CERM-X5R-1

32 90

MEM_B_A<0>

12 30

31

90

MEM_B_A<1>

12 30

D

31 32

MEM_B_A<2>

32 90

MEM_B_A<3>

12 30

90

31

31 32

MEM_B_A<4>

12 30 32 90

MEM_B_A<5>

12 30

31

90

MEM_B_A<6>

12 30 31 32

MEM_B_A<7>

32 90

MEM_B_A<8>

12 30

31

90

MEM_B_A<9>

12 30 31 32

MEM_B_A<10>

90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32

90

MEM_B_A<13>

12 30 31 32

90

MEM_B_A<14>

12 30 31 32

MEM_B_A<15>

12 30 31 32 90 90

MEM_B_BA<0>

12 30 31 32

MEM_B_BA<1>

12 30 31 32

90

MEM_B_BA<2>

12 30 31 32

90

MEM_B_RAS_L

12 30 31 32

MEM_B_CAS_L

90

MEM_B_WE_L MEM_B_WE_L

12 30 31 32

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<0>

2

C

R3100

240

1% 1/20W MF 201 201

1

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3110

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

N10

VDDQ

8

E10J9E2

NF/TDQS*

B3D2B9

30 31

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

1

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<2>

2

R3120

240

1% 1/20W

201

1

C3127

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3120

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

N10

VDDQ

B3D2B9

8

30 31

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3128

0.47UF

CERM-X5R-1

NC

1

20%

4V

2

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<18>

C8

MEM_B_DQ<20>

C3

MEM_B_DQ<19>

C9

MEM_B_DQ<16>

E4

MEM_B_DQ<23>

E9

MEM_B_DQ<21>

D3

MEM_B_DQ<22>

E8

MEM_B_DQ<17>

C4

MEM_B_DQS_P<2>

D4

MEM_B_DQS_N<2>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3129

0.47UF

20% 4V

2

CERM-X5R-1 201

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 31 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30

31 32 90

90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 32 90

MEM_B_RAS_L

12 30 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<3>

2

R3130

240

1% 1/20W MF 201

1

CERM-X5R-1

1

C3118

0.47UF

20%

4V

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<14>

DQ0

C8

MEM_B_DQ<9>

DQ1

C3

MEM_B_DQ<11>

DQ2

C9

MEM_B_DQ<13>

DQ3

E4

MEM_B_DQ<10>

E9

MEM_B_DQ<12>

D3

MEM_B_DQ<15>

E8

MEM_B_DQ<8>

C4

MEM_B_DQS_P<1>

DQS

D4

MEM_B_DQS_N<1>

B8 A8

NC NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

CK

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C3119

0.47UF

20% 4V

2

CERM-X5R-1 201

31 32 90

12 30 31 32 90

D10

C3137

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3130

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

VDDQ

8

E10J9E2

NF/TDQS*

B3D2B9

30 31

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3138

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3139

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_B_DQ<27> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<28> MEM_B_DQ<31> MEM_B_DQ<24>

MEM_B_DQS_P<3> MEM_B_DQS_N<3>

MEM_B_CS_L<0> MEM_B_CKE<0>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

D

27 28 29 30 31

12 31 90

12 30 32 90

C

C3147

CERM-X5R-1

32 90

MEM_B_A<0>

12 30

31

90

MEM_B_A<1>

12 30 31 32

MEM_B_A<2>

32 90

MEM_B_A<3>

12 30

90

31

31 32

MEM_B_A<4>

12 30 32 90

MEM_B_A<5>

12 30

31

90

MEM_B_A<6>

12 30 31 32

MEM_B_A<7>

32 90

MEM_B_A<8>

12 30

31

90

MEM_B_A<9>

12 30 31 32

B

90 12 30 31 32

12 30 31 32

90

90 12 30 31 32

90

12 30

31 32

12 30

31 32

90

12 30

31 32

12 30

31 32

90

90 12 30 31 32

90

12 30

31 32

90

12 30

31 32

12 30

32 90

2

1

MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_ODT<0> MEM_B_ZQ<4>

R3140

240

1% 1/20W

201

1

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

VDD

OMIT_TABLE

U3140

DDR3-1333

(SYM VER 2)

VSS

8

FBGA

30 31

J10

B10C2E3

L10

N10

VDDQ

E10J9E2

RESET*

DM/TDQS

NF/TDQS*

VSSQ

B3D2B9

VREFDQ

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3148

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3149

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39>

MEM_B_DQS_P<4> MEM_B_DQS_N<4>

NC

MEM_B_CS_L<0> MEM_B_CKE<0>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

12 31 90

31 32 90

12 30 31 32 90

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3> MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<5>

2

R3150

240

1% 1/20W MFMF 201

1

C3157

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3150

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

C3158

0.47UF

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<40>

C8

MEM_B_DQ<41>

C3

MEM_B_DQ<42>

C9

MEM_B_DQ<43>

E4

MEM_B_DQ<44>

E9

MEM_B_DQ<45>

D3

MEM_B_DQ<46>

E8

MEM_B_DQ<47>

C4

MEM_B_DQS_P<5>

D4

MEM_B_DQS_N<5>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

20%

201

1

C3159

0.47UF

20%

4V

2

CERM-X5R-1 201

31 32 90

12 30 31 32 90

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<6>

2

R3160

240

1% 1/20W MF 201

1

C3167

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3160

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3168

0.47UF

CERM-X5R-1

NC

20%

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<48>

C8

MEM_B_DQ<49>

C3

MEM_B_DQ<50>

C9

MEM_B_DQ<51>

E4

MEM_B_DQ<52>

E9

MEM_B_DQ<53>

D3

MEM_B_DQ<54>

E8

MEM_B_DQ<55>

C4

MEM_B_DQS_P<6>

D4

MEM_B_DQS_N<6>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3169

0.47UF

20%

4V

2

CERM-X5R-1 201

31 32 90

12 30 31 32 90

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<7>

2

R3170

240

1% 1/20W MF 201

1

A

C3100

2.2UF

X5R-CERM

C3140

2.2UF

X5R-CERM

1

C3101

20% 10V

2

402

1

C3141

20% 10V

2

402

1

2.2UF

20% 10V

2

X5R-CERM

402

1

2.2UF

20% 20% 10V

2

X5R-CERM

402

C3110

2.2UF

X5R-CERM

C3150

2.2UF

X5R-CERM

1

20% 10V

2

402

1

10V

2

402

C3111

2.2UF

X5R-CERM

C3151

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3120

2.2UF

X5R-CERM

C3160

2.2UF

X5R-CERM

1

C3121

20% 10V

2

402

1

C3161

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3130

2.2UF

X5R-CERM

C3170

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3131

2.2UF

X5R-CERM

C3171

2.2UF

X5R-CERM

1

C3103

20% 10V

402

20% 10V

402

0.1UF

10%

2

1

2

6.3V 6.3V

2

X5R 201

1

C3143

0.1UF

10%

6.3V

2

X5R 201

1

C3104

0.1UF

10%

2

X5R 201

1

C3144

0.1UF

10%

6.3V

2

X5R 201

1

C3105

0.1UF

10%

6.3V

2

X5R 201

1

C3145

0.1UF

10%

6.3V

2

X5R 201

1

C3113

0.1UF

10%

6.3V

2

X5R 201

1

C3153

0.1UF

10%

6.3V

2

X5R 201

1

C3114

0.1UF

10%

6.3V

2

X5R 201

1

C3154

0.1UF

10%

6.3V

2

X5R 201

1

C3115

0.1UF

10%

6.3V

2

X5R 201

1

C3155

0.1UF

10%

6.3V

2

X5R 201

1

C3123

0.1UF

10%

6.3V

2

X5R 201

1

C3163

0.1UF

10%

6.3V

2

X5R 201

1

C3124

0.1UF

10%

6.3V

2

X5R 201

1

C3164

0.1UF

10%

6.3V

2

X5R 201

1

C3125

0.1UF

10%

6.3V

2

X5R 201

1

C3165

0.1UF

10%

6.3V

2

X5R 201

1

C3133

0.1UF

10%

6.3V

2

X5R 201

1

C3173

0.1UF

10%

6.3V

2

X5R 201

1

C3134

0.1UF

10%

6.3V

2

X5R 201

1

C3174

0.1UF 0.1UF

10%

6.3V

2

X5R 201

1

2

1

2

C3135

0.1UF

10%

6.3V X5R 201

C3175

10%

6.3V X5R 201

6 3

C3177

0.47UF

1

20%

4V

2

A3

201

A10D8G9G3K2

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

B2

J2L2N2F3A9D9F9

SYNC_MASTER=D2_KEPLER

PAGE TITLE

K10M2M10

VDD

OMIT_TABLE

U3170

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

C3178

0.47UF

20%

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<56>

DQ0

C8

MEM_B_DQ<57>

DQ1

C3

MEM_B_DQ<58>

DQ2

C9

MEM_B_DQ<59>

DQ3

E4

MEM_B_DQ<60>

E9

MEM_B_DQ<61>

D3

MEM_B_DQ<62>

E8

MEM_B_DQ<63>

C4

MEM_B_DQS_P<7>

DQS

D4

MEM_B_DQS_N<7>

DQS*

B8 A8

NC

H3

MEM_B_CS_L<0>

CS*

G10

MEM_B_CKE<0>

CKE

F8

MEM_B_CLK_P<0>

CK

G8

MEM_B_CLK_N<0>

CK*

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C10

D10

SYNC_DATE=01/13/2012

DDR3 SDRAM Bank B (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

4V

2

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

31 OF 132

SHEET

30 OF 99

1

C3179

0.47UF

20% 4V

2

CERM-X5R-1 201

27 28 29 30 31

12 31 90

B

12 31 90

12 30 32 90

A

SIZE

D

124578

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

=PP1V5R1V35_S3_MEM_B

8

30 31

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

8

30 31

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

=PP1V5R1V35_S3_MEM_B

8

30 31

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

=PP1V5R1V35_S3_MEM_B

12

8

30 31

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3200

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

VDDQ

B3D2B9

8

30 31

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

VREFCA

D10

1

C3208

0.47UF

20%

4V

CERM-X5R-1

NC

2

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<1>

C8

MEM_B_DQ<6>

C3

MEM_B_DQ<5>

C9

MEM_B_DQ<3>

E4

MEM_B_DQ<0>

E9

MEM_B_DQ<7>

D3

MEM_B_DQ<4>

E8

MEM_B_DQ<2>

C4

MEM_B_DQS_P<0>

D4

MEM_B_DQS_N<0>

B8 A8

NC

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3209

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 30 31 32 90 12 30 31 32 90

12 30 90

12 31 32 90

C3217

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32

MEM_B_A<2> MEM_B_A<2> MEM_B_A<4> MEM_B_A<3>

12 30 31 32 90

MEM_B_A<6> MEM_B_A<5>

12 30 31 32 90

MEM_B_A<8> MEM_B_A<7> MEM_B_A<9> MEM_B_A<10>

12 30 31 32 90

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<1> MEM_B_BA<0> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<9>

2

R3210

240

1% 1/20W

201 201

1

C3207

CERM-X5R-1

90

MEM_B_A<0>

12 30 31 32

D

C

MEM_B_A<1>

90

MEM_B_A<2>

12 30 31 32

MEM_B_A<4>

12 30 31 32

90

MEM_B_A<3>

12 30 31 32

90

MEM_B_A<6>

12 30 31 32

MEM_B_A<5>

90

MEM_B_A<8>

12 30 31 32

MEM_B_A<7>

12 30 31 32

90

MEM_B_A<9>

12 30 31 32

90

MEM_B_A<10>

12 30 31 32

MEM_B_A<11>

32 90

MEM_B_A<12>

12 30

90

31

31 32

MEM_B_A<13>

12 30 32 90

MEM_B_A<14>

12 30

31

90

MEM_B_A<15>

12 30 31 32 90 31 32

MEM_B_BA<1>

12 30 32 90

MEM_B_BA<0>

12 30

31

90

MEM_B_BA<2>

12 30 31 32

32 90

MEM_B_RAS_L

12 30

31

90

MEM_B_CAS_L

12 30 31 32

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<8>

2

R3200

240

1% 1/20W MF MF 201

1

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3210

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

N10

VDDQ

8

E10J9E2

NF/TDQS*

B3D2B9

30 31

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

1

C3218

0.47UF

20%

4V

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<9>

DQ0

C8

MEM_B_DQ<14>

DQ1

C3

MEM_B_DQ<13>

DQ2

C9

MEM_B_DQ<11>

DQ3

E4

MEM_B_DQ<8>

E9

MEM_B_DQ<15>

D3

MEM_B_DQ<12>

E8

MEM_B_DQ<10>

C4

MEM_B_DQS_P<1>

DQS

D4

MEM_B_DQS_N<1>

B8 A8

NC NC

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

CK

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C3219

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 30 90

12 31 32 90

D10

C3227

0.47UF

20%

4V

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32

MEM_B_A<4> MEM_B_A<3> MEM_B_A<6> MEM_B_A<5> MEM_B_A<8> MEM_B_A<7> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<1> MEM_B_BA<0> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<10>

2

R3220

240

1% 1/20W MF MF

1

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3220

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

N10

VDDQ

B3D2B9

8

30 31

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3228

0.47UF

CERM-X5R-1

NC

20%

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<20>

C8

MEM_B_DQ<18>

C3

MEM_B_DQ<16>

C9

MEM_B_DQ<19>

E4

MEM_B_DQ<17>

E9

MEM_B_DQ<22>

D3

MEM_B_DQ<21>

E8

MEM_B_DQ<23>

C4

MEM_B_DQS_P<2>

D4

MEM_B_DQS_N<2>

B8 A8

NC

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3229

0.47UF

20%

4V

2

CERM-X5R-1 201

90

12 30 31 32 90

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 27 28 29 30 31

MEM_B_A<2> MEM_B_A<4>

12 30 90

MEM_B_A<3>

12 30 90

MEM_B_A<6>

12 30 90

MEM_B_A<5>

12 30 90

MEM_B_A<8>

12 30 90

MEM_B_A<7>

12 30 90

MEM_B_A<9>

12 30 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 90

MEM_B_A<12>

12 30 90

MEM_B_A<13>

12

30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<1>

12 31 32 90

MEM_B_BA<0>

12 31 32 90

MEM_B_BA<2>

12 31 32 90

MEM_B_RAS_L

12 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<11>

2

R3230

240

1% 1/20W

201

1

CERM-X5R-1

C3237

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3230

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

VDDQ

8

E10J9E2

NF/TDQS*

B3D2B9

30 31

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3238

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3239

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_B_DQ<25> MEM_B_DQ<27> MEM_B_DQ<29> MEM_B_DQ<26> MEM_B_DQ<24> MEM_B_DQ<31> MEM_B_DQ<28> MEM_B_DQ<30>

MEM_B_DQS_P<3> MEM_B_DQS_N<3>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

D

27 28 29 30 31

12 30 90

12 31 32 90

C

C3247

CERM-X5R-1

90

MEM_B_A<0>

12 30 31 32

MEM_B_A<1>

90

MEM_B_A<2>

12 30 31 32

MEM_B_A<4>

90

MEM_B_A<3>

12 30 31 32

MEM_B_A<6>

32 90

MEM_B_A<5>

12 30

31

90

MEM_B_A<8>

12 30 31 32

MEM_B_A<7>

12 30 31 32

90

MEM_B_A<9>

12 30 31 32

B

90

MEM_B_A<10>

12 30 31 32

MEM_B_A<11>

32 90

MEM_B_A<12>

12 30

90

31

31 32

MEM_B_A<13>

12 30 32 90

MEM_B_A<14>

12 30

31

90

MEM_B_A<15>

12 30 31 32 90 31 32

MEM_B_BA<1>

12 30 32 90

MEM_B_BA<0>

12 30

31

90

MEM_B_BA<2>

12 30 31 32

32 90

MEM_B_RAS_L

12 30

31

90

MEM_B_CAS_L

12 30 31 32

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<12>

2

R3240

240

1% 1/20W MF 201

1

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

VDD

OMIT_TABLE

U3240

DDR3-1333

(SYM VER 2)

VSS

8

FBGA

30 31

J10

B10C2E3

L10

N10

VDDQ

E10J9E2

RESET*

DM/TDQS

NF/TDQS*

VSSQ

B3D2B9

VREFDQ

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3248

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3249

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36>

MEM_B_DQS_P<4> MEM_B_DQS_N<4>

NC

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

12 30 90

12 31 32 90

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<4> MEM_B_A<3> MEM_B_A<6> MEM_B_A<5> MEM_B_A<8> MEM_B_A<7> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<1> MEM_B_BA<0> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<13>

2

R3250

240

1% 1/20W MF 201

1

C3257

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3250

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

C3258

0.47UF

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<41>

C8

MEM_B_DQ<40>

C3

MEM_B_DQ<43>

C9

MEM_B_DQ<42>

E4

MEM_B_DQ<47>

E9

MEM_B_DQ<46>

D3

MEM_B_DQ<45>

E8

MEM_B_DQ<44>

C4

MEM_B_DQS_P<5>

D4

MEM_B_DQS_N<5>

B8 A8

NC

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

20%

201

1

C3259

0.47UF

20%

4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 30 31 32 90 12 30 31 32 90

12 30 90

12 31 32 90

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32

MEM_B_A<2> MEM_B_A<2> MEM_B_A<4> MEM_B_A<3> MEM_B_A<6> MEM_B_A<5> MEM_B_A<8>

12 30 31 32 90

MEM_B_A<7> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<1> MEM_B_BA<0> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<14>

2

R3260

240

1% 1/20W MF

1

C3267

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3260

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3268

0.47UF

CERM-X5R-1

NC

20%

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<49>

C8

MEM_B_DQ<48>

C3

MEM_B_DQ<51>

C9

MEM_B_DQ<50>

E4

MEM_B_DQ<55>

E9

MEM_B_DQ<54>

D3

MEM_B_DQ<53>

E8

MEM_B_DQ<52>

C4

MEM_B_DQS_P<6>

D4

MEM_B_DQS_N<6>

B8 A8

NC

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3269

0.47UF

20%

4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 30 90

12 31 32 90

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32

MEM_B_A<4> MEM_B_A<3> MEM_B_A<6>

12 30

31 32 90

MEM_B_A<5> MEM_B_A<8> MEM_B_A<7> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

12

30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<1> MEM_B_BA<0>

12 30

31 32 90

MEM_B_BA<2> MEM_B_RAS_L

12 30

31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<1>

12 31 32 90

MEM_B_ZQ<15>

2

R3270

240

1% 1/20W MF 201201

1

A

C3200

2.2UF

X5R-CERM

C3240

2.2UF

X5R-CERM

1

C3201

20% 10V

2

402

1

C3241

20% 10V

2

402

1

2.2UF

20% 10V

2

X5R-CERM

402

1

2.2UF

20% 20% 10V

2

X5R-CERM

402

C3210

2.2UF

X5R-CERM

C3250

2.2UF

X5R-CERM

1

20% 10V

2

402

1

10V

2

402

C3211

2.2UF

X5R-CERM

C3251

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3220

2.2UF

X5R-CERM

C3260

2.2UF

X5R-CERM

1

C3221

20% 10V

2

402

1

C3261

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3230

2.2UF

X5R-CERM

C3270

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3231

2.2UF

X5R-CERM

C3271

2.2UF

X5R-CERM

1

C3203

20% 10V

402

20% 10V

402

0.1UF

10%

2

1

2

6.3V 6.3V

2

X5R 201

1

C3243

0.1UF

10%

6.3V

2

X5R 201

1

C3204

0.1UF

10%

2

X5R 201

1

C3244

0.1UF

10%

6.3V

2

X5R 201

1

C3205

0.1UF

10%

6.3V

2

X5R 201

1

C3245

0.1UF

10%

6.3V

2

X5R 201

1

C3213

0.1UF

10%

6.3V

2

X5R 201

1

C3253

0.1UF

10%

6.3V

2

X5R 201

1

C3214

0.1UF

10%

6.3V

2

X5R 201

1

C3254

0.1UF

10%

6.3V

2

X5R 201

1

C3215

0.1UF

10%

6.3V

2

X5R 201

1

C3255

0.1UF

10%

6.3V

2

X5R 201

1

C3223

0.1UF

10%

6.3V

2

X5R 201

1

C3263

0.1UF

10%

6.3V

2

X5R 201

1

C3224

0.1UF

10%

6.3V

2

X5R 201

1

C3264

0.1UF

10%

6.3V

2

X5R 201

1

C3225

0.1UF

10%

6.3V

2

X5R 201

1

C3265

0.1UF

10%

6.3V

2

X5R 201

1

C3233

0.1UF

10%

6.3V

2

X5R 201

1

C3273

0.1UF

10%

6.3V

2

X5R 201

1

C3234

0.1UF

10%

6.3V

2

X5R 201

1

C3274

0.1UF 0.1UF

10%

6.3V

2

X5R 201

1

2

1

2

C3235

0.1UF

10%

6.3V X5R 201

C3275

10%

6.3V X5R 201

6 3

C3277

0.47UF

1

20%

4V

2

A3

201

A10D8G9G3K2

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

B2

J2L2N2F3A9D9F9

SYNC_MASTER=D2_KEPLER

PAGE TITLE

K10M2M10

VDD

OMIT_TABLE

U3270

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

C3278

0.47UF

20%

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<57>

DQ0

C8

MEM_B_DQ<56>

DQ1

C3

MEM_B_DQ<59>

DQ2

C9

MEM_B_DQ<58>

DQ3

E4

MEM_B_DQ<63>

E9

MEM_B_DQ<62>

D3

MEM_B_DQ<61>

E8

MEM_B_DQ<60>

C4

MEM_B_DQS_P<7>

DQS

D4

MEM_B_DQS_N<7>

DQS*

B8 A8

NC

H3

MEM_B_CS_L<1>

CS*

G10

MEM_B_CKE<1>

CKE

F8

MEM_B_CLK_P<1>

CK

G8

MEM_B_CLK_N<1>

CK*

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C10

D10

SYNC_DATE=01/13/2012

DDR3 SDRAM Bank B (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

4V

2

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

32 OF 132

SHEET

31 OF 99

1

C3279

0.47UF

20% 4V

2

CERM-X5R-1 201

27 28 29 30 31

12 30 90

B

12 30 90

12 31 32 90

A

SIZE

D

124578

8 7 6 5 4 3

12

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

=PP0V75_S0_MEM_VTT_A

12 29 90

MEM_A_CS_L<1>

IN

12 28 90

MEM_A_CKE<0>

IN

MEM_A_A<0>

12 28 29 90

IN

12 28 29 90

MEM_A_A<7>

IN

12 28 29 90

MEM_A_A<5>

IN

MEM_A_BA<0>

12 28 29 90

IN

MEM_A_ODT<0>

12 28 90

IN

MEM_A_A<15>

12 28 29 90

D

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 29 90

IN

12 28 29 90

IN

12 28 29 90

IN

12 28 90

IN

12 28 29 90

IN

MEM_A_BA<1> MEM_A_A<14>

MEM_A_A<8>

MEM_A_A<12> MEM_A_A<9> MEM_A_BA<2> MEM_A_ODT<1> MEM_A_A<4> MEM_A_RAS_L MEM_A_A<1> MEM_A_WE_L MEM_A_A<6> MEM_A_A<2> MEM_A_A<3>

MEM_A_A<13> MEM_A_CKE<1> MEM_A_A<10> MEM_A_CAS_L MEM_A_CS_L<0> MEM_A_A<11>

RP3305 RP3301 RP3302 RP3306 RP3303 RP3302 RP3301 RP3305

RP3303 RP3307 RP3306

RP3305 RP3306 RP3302 RP3304 RP3303 RP3304 RP3307 RP3302 RP3303 RP3307 RP3305

RP3307 RP3304 RP3304 RP3301 RP3301 RP3306

C

8

36 36 36 36 36 36

36 36

36 36 36 36 36 36 36 36 36 36 36

36 36 36 36 36 36

1 8 4 5 2 7 2 7 1 8 1 8 2 7 2 7

2 7 3 6 1 8

3 6 4 5 3 6 3 6 4 5 1 8 2 7 4 5 3 6 1 8 4 5

4 5 2 7 4 5 3 6 1 8 3 6

5%

1/32W

5%

1/32W 1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5% 5%361/32W

1/32W

5%

1/32W

5%

1/32W 1/32W

5%

1/32W 1/32W

5%

1/32W

5% 5%

1/32W 1/32W

5% 5%

1/32W 1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5% 5%

1/32W 1/32W

5% 5%

1/32W

4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201

4X0201 4X0201 4X0201

4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201 4X0201

4X0201 4X0201 4X0201 4X0201 4X0201 4X0201

1

C3300

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3302

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3304

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3306

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3308

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3310

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3303

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3305

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3307

0.47UF

20% 4V

2

CERM-X5R-1 201

D

C

=PP0V75_S0_MEM_VTT_B

12 30 90

MEM_B_ODT<0>

IN

12 30 31 90

MEM_B_A<13>

IN

12 30 31 90

MEM_B_A<15>

IN

12 30 31 90

MEM_B_A<11>

IN

MEM_B_CAS_L

12 30 31 90

IN

MEM_B_A<1>

12 30 31 90

MEM Clock Termination

Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM

R3350

30

CERM

1 2

5%

1/20W

1

MF

2

1

2

1

2

1

2

201

R3351

30

1 2

5%

1/20W

MF

201

R3355

30

1 2

5%

1/20W

MF

201

R3356

30

1 2

5%

1/20W

MF

201

R3360

30

1 2

5%

1/20W

MF

201

R3361

30

1 2

5%

1/20W

MF

201

R3365

30

1 2

5%

1/20W

MF

201

R3366

30

1 2

5%

1/20W

MF

201

5%

25V 201

5%

25V 201

5%

25V 201

5%

25V 201

MEM_A_CLK0_TERM_R

MEM_A_CLK1_TERM_R

MEM_B_CLK0_TERM_R

MEM_B_CLK1_TERM_R

MEM_A_CLK_N<0>

12 28 90

IN

C3350

PLACE_NEAR=U2900.F7:3.2mm

MEM_A_CLK_P<0>

12 28 90

B

IN

MEM_A_CLK_N<1>

12 29 90

IN

PLACE_NEAR=U3000.F7:3.2mm

MEM_A_CLK_P<1>

12 29 90

IN

MEM_B_CLK_N<0>

12 30 90

IN

PLACE_NEAR=U3170.F7:3.2mm

MEM_B_CLK_P<0>

12 30 90

IN

3.3PF

C3355

3.3PF

C3360

3.3PF

A

MEM_B_CLK_N<1>

12 31 90

IN

C3365

PLACE_NEAR=U3270.F7:3.2mm

MEM_B_CLK_P<1>

12 31 90

IN

3.3PF

C3351

0.1UF

1 2

10%

6.3V X5R 201

C3356

0.1UF

1 2

10%

6.3V X5R 201

C3361

0.1UF

1 2

10%

6.3V X5R 201

C3366

0.1UF

1 2

10%

6.3V X5R 201

IN

12 30 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 30 31 90

IN

12 31 90

IN

12 31 90

IN

12 30 31 90

IN

MEM_B_CS_L<0> MEM_B_A<14> MEM_B_A<0> MEM_B_BA<2> MEM_B_BA<1> MEM_B_A<4> MEM_B_CS_L<1> MEM_B_A<6> MEM_B_A<12> MEM_B_A<9> MEM_B_CKE<0> MEM_B_A<7> MEM_B_A<5> MEM_B_A<3> MEM_B_A<2> MEM_B_A<8>

MEM_B_BA<0> MEM_B_A<10>

MEM_B_RAS_L

MEM_B_ODT<1> MEM_B_CKE<1> MEM_B_WE_L

RP3322 RP3325

RP3328 RP3325

RP3320 RP3326 RP3330 RP3320 RP3330 RP3330 RP3324 RP3326 RP3324 RP3326 RP3322 RP3326 RP3330 RP3324 RP3324 RP3325

RP3320 RP3320 RP3322

RP3328 RP3328 RP3322

6 3

8

36 36

36 36 36 36 36 36 36 36 36 36 36

36 36 36

36 36

36

2 7 1 8

1 8 2 7

2 7 3 6

2 7 4 5 2 7 3 6 1 8 3 6 4 5 2 7 1 8 3 6 3 6 1 8 4 5 3 6 2 7 4 5

4 5 1 8 1 8

4 5 3 6 4 5

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%361/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

1/32W

5%

4X0201

SYNC_MASTER=D2_KEPLER

PAGE TITLE

1

C3320

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3322

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3324

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3326

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3328

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3330

0.47UF

20% 4V

2

CERM-X5R-1 201

DDR3 Termination

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

C3323

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3325

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C3327

0.47UF

20% 4V

2

CERM-X5R-1 201

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

33 OF 132

SHEET

32 OF 99

124578

SIZE

B

A

D

8 7 6 5 4 3

12

NOTE: Must not enable more than two SO-DIMM margining

=PP3V3_S3_VREFMRGN

8

OMIT

R3418

SHORT

1 2

D

R3419

1 2

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

- =PPDDR_S3_MEMVREF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

C

B

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

DDRVREF_DAC - Stuffs Apple margining circuit. VREFDQ:LDO - LDO outputs sent to DQ inputs. VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs. VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs. VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs. VREFCA:LDO - LDO outputs sent to CA inputs. VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

=PPDDR_S3_MEMVREF

8

33

VREFDQ:M1_M3

SSM6N15FEAPE

27 33

PPCPU_MEM_VREFDQ_A

10 89

MEMRESET_ISOL_LS5V_L

=PPDDR_S3_MEMVREF

8

33

2

1

VREFDQ:M1_M3

SSM6N15FEAPE

27 33

PPCPU_MEM_VREFDQ_B

10 89

MEMRESET_ISOL_LS5V_L

5

4

CRITICAL

Q3420

S G

CRITICAL

Q3420

S G

NONE NONE NONE

402

OMIT

SHORT

NONE NONE NONE

402

SOT563

D

6

D

3

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

=I2C_VREFDACS_SCL

44

IN

=I2C_VREFDACS_SDA

44

BI

Addr=0x98(WR)/0x99(RD)

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

Addr=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

44

IN

=I2C_PCA9557D_SDA

44

BI

PCA9557D_RESET_L

25

IN

RST* on ’platform reset’ so that system watchdog will disable margining.

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

PLACE_NEAR=Q3420.6:2mm

VREFDQ:M1_M3

1

C3420

0.1UF

10% 16V

2

X7R-CERM 0402

PLACE_NEAR=R3421.2:1mm

PLACE_NEAR=Q3420.3:2mm

VREFDQ:M1_M3

1

C3440

0.1UF

10% 16V

2

X7R-CERM 0402

PLACE_NEAR=R3441.2:1mm

DDRVREF_DAC

C3400

2.2UF

402-LF

DDRVREF_DAC

6.3V CERM

20%

1

2

DDRVREF_DAC

1

C3401

0.1UF

20% 10V

2

CERM 402

6

SCL

7

SDA

9

A0

10

A1

1

C3402

0.1UF

20% 10V

2

CERM

402

3

A0

4

A1

5

A2

1

SCL

2

SDA

PLACE_NEAR=Q3420.6:1mm

VREFDQ:M1_M3

1

R3421

1K

1% 1/16W MF-LF 402

2

PP0V75_S3_MEM_VREFDQ_A

VREFDQ:M1_M3

1

R3422

1K

1% 1/16W MF-LF 402

2

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step

PLACE_NEAR=Q3420.3:1mm

VREFDQ:M1_M3

R3441

1K

1% 1/16W MF-LF 402

PP0V75_S3_MEM_VREFDQ_B

VREFDQ:M1_M3

1

R3442

1K

1% 1/16W MF-LF 402

2

THRM

PAD

17

8

VDD

MSOP

DAC5574

GND

3

16

VCC

U3401

PCA9557

QFN

GND

8

CRITICAL DDRVREF_DAC

U3400

VOUTA

VOUTB

VOUTC

VOUTD

CRITICAL DDRVREF_DAC

(OD)

P0 P1 P2 P3 P4 P5 P6 P7

RESET*

28 29 33 89

30 31 33 89

1

2

4

5

NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable both at the same time!

6

7 9

10 11

12

13 14

15

VREFMRGN_SODIMMA_DQ

VREFMRGN_SODIMMB_DQ

VREFMRGN_SODIMMS_CA

VREFMRGN_MEMVREG_FBVREF

NC

VREFMRGN_DQ_SODIMMA_EN VREFMRGN_DQ_SODIMMB_EN VREFMRGN_CA_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN VREFMRGN_MEMVREG_EN VREFMRGN_FRAMEBUF_EN

NC

DDRVREF_DAC

R3416

1/16W MF-LF

1

0

5%

402

2

VREFMRGN_MEMVREG_FBVREF_R

DDRVREF_DAC

1

R3413

100K

5% 1/16W MF-LF 402

2

DDRVREF_DAC

1

R3415

100K

5% 1/16W MF-LF 402

2

DDRVREF_DAC

1

R3401

100K

5% 1/16W MF-LF 402

2

DDRVREF_DAC

1

R3402

100K

5% 1/16W MF-LF 402

2

DDRVREF_DAC

1

R3407

100K

5% 1/16W MF-LF 402

2

DDRVREF_DAC

1

R3408

100K

5% 1/16W MF-LF 402

2

A2

A3

DDRVREF_DAC

C3403

0.1UF

20% 10V

CERM

402

C3404

0.1UF

20% 10V

CERM

402

DDRVREF_DAC

C3405

0.1UF

CERM

1

2

1

2

20% 10V

402

VREFMRGN_FRAMEBUF_BUF

NC

DDRVREF_DAC

B1

U3404

MAX4253

V+

CRITICAL

UCSP

A1

A4

V-

B4

VREFMRGN_FRAMEBUF_BUF_R

NC

1

2

A2

A3

C2

C3

A2

A3

C2

C3

C2

C3

DDRVREF_DAC

1

R3417

0

5% 1/16W MF-LF 402

2

B1

V+

V-

B4

B1

V+

V-

B4

NC

B1

V+

V-

B4

B1

V+

V-

B4

NC

B1

V+

V-

B4

buffers at once or VRef source may be overloaded.

VREFDQ:LDO_DAC

R3403

200

1 2

1% 1/16W MF-LF

402

VREFDQ:LDO_DAC

R3404

133

1 2

1% 1/16W MF-LF

402

VREFDQ:LDO_DAC

R3405

200

1 2

1% 1/16W MF-LF

402

VREFDQ:LDO_DAC

R3406

133

1 2

1% 1/16W MF-LF

402

VREFCA:LDO_DAC

R3409

200

1 2

1% 1/16W MF-LF

402

VREFCA:LDO_DAC

R3410

133

1 2

1% 1/16W MF-LF

402

VREFCA:LDO_DAC

R3411

200

1 2

1% 1/16W MF-LF

402

VREFCA:LDO_DAC

R3412

133

1 2

1% 1/16W MF-LF

402

DDRREG_FB

Required zero ohm resistors when no VREF margining circuit stuffed

DESCRIPTION

CRITICAL

DDRVREF_DAC

U3402

MAX4253

UCSP

A1

A4

CRITICAL

NC

DDRVREF_DAC

U3402

MAX4253

UCSP

C1

C4

CRITICAL

DDRVREF_DAC

U3403

MAX4253

UCSP

A1

A4

CRITICAL

NC

DDRVREF_DAC

U3403

MAX4253

UCSP

C1

C4

CRITICAL DDRVREF_DAC

U3404

MAX4253

UCSP

C1

C4

=PPVTT_S3_DDR_BUF

8

64

10mA max load

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_MEMVREG_BUF

PLACE_NEAR=R7320.2:1mm

PART NUMBER

116S0004

PART NUMBER

114S0218

114S0171

QTY

2

4

2

DDRVREF_DAC

R3414

33.2K

1 2

1% 1/16W MF-LF

402

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,1K,1%,0402,SM,LF

RES,MTL FILM,332,1%,0402,SM,LF

PLACE_NEAR=J2900.1:2.54mm

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3403.2:1mm

PLACE_NEAR=J3100.1:2.54mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3405.2:1mm

PLACE_NEAR=J2900.126:2.54mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3409.2:1mm

PLACE_NEAR=J3100.126:2.54mm

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3411.2:1mm

64

OUT

REFERENCE DES

R3403,R3405

R3409,R3411

REFERENCE DES

R3421,R3422,R3441,R3442

R3404,R3406

CRITICAL

28 29 33 89

30 31 33 89

28 29 89

30 31 89

D

C

B

BOM OPTION

VREFDQ:LDO

VREFCA:LDO

BOM OPTION

VREFDQ:M1_DAC

A

DAC Channel: PCA9557D Pin: Nominal value Margined target: DAC range: VRef current: DAC step size:

MEM A VREF DQ MEM B VREF DQ

A 1

B 2

0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced)

7.69mV / step @ output

MEM A VREF CA

C 3

MEM B VREF CA

C 4

MEM VREG

D 5

GPU Frame Buffer (1.8V, 70% VRef)

D 6

1.267V (DAC: 0x8B)

1.000V - 2.000V (+/- 500mV)

0.000V - 3.000V (0x00 - 0x74) +61uA - -61uA (- = sourced)

8.59mV / step @ output

1.056V - 1.442V (+/- 180mV)

0.000V - 3.300V (0x00 - 0xFF) +6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

DDR3/FRAMEBUF VREF MARGINING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

34 OF 132

SHEET

33 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

OMIT_TABLE

L3570

1 2

0.6NH+/-0.1NH-0.85A

NOSTUFF

1

C3570

0.1UF

10%

D

16V

2

X5R-CERM 0201

0201

PCIE_AP_R2D_PI_P

92

1

2

NOSTUFF

C3571

0.1UF

10% 16V X5R-CERM 0201

PLACE_NEAR=J3501.15:2.54MM

C3531

1 2

10%

PCIE_AP_R2D_C_P

0.1UF

0402X7R-CERM

16V

17 92

IN

PART NUMBER

117S0002

QTY

4

DESCRIPTION

RES, 0OHM, 0201

REFERENCE DES

L3570,L3571,L3573,L3574

CRITICAL

12

BOM OPTION

D

L3571

WIFI_EVENT_L

PCIE_AP_R2D_P

7

92

CRITICAL

514S0335

J3501

SSD-K99

F-RT-SM1

C

1 2 3 4 5 6 7 8 9 10 11 12

13 14 15 16 17 18

19 20 21

PP3V3_S3RS4_BT_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

B

PART NUMBER

OMIT

CRITICAL

J3502

CCR20-6K710S

F-RT-SM

8

6

5

4

3

A

2

1

7

QTY

1

DESCRIPTION

CONN,HDR,TWIN-AX,P=0.4MM,6P,HF

=I2C_ALS_SDA =I2C_ALS_SCL PP5V_S3_ALSCAMERA_F

7

USB_CAMERA_CONN_N

7

91

USB_CAMERA_CONN_P

7

91

IN

PCIE_AP_R2D_N

7

41 42

PCIE_AP_D2R_PI_P

7

92

PCIE_AP_D2R_PI_N

7

92

PCIE_WAKE_L

1

C3532

0.01UF

10% 16V X7R-CERM 0402

PLACE_NEAR=J3501.27:2.54MM

2

REFERENCE DES

J3502

BTPWR:S4

L3505

FERR-120-OHM-1.5A

BTPWR:S3

FERR-120-OHM-1.5A

12

0402-LF

L3506

12

0402-LF

CRITICAL

44

BI

44

IN

NOSTUFF

1

C3572

0.1UF

10% 16V

2

X5R-CERM 0201

1

C3574

0.1UF

10% 16V

2

X5R-CERM 0201

PCIE_CLK100M_AP_CONN_P

7

96

PCIE_CLK100M_AP_CONN_N

7

96

7

18

OUT

=PP3V3_S4_BT

=PP3V3_S3_BT

CRITICAL518S0767

PLACE_NEAR=J3502.3:2.54MM

1

2

1 2

0.6NH+/-0.1NH-0.85A

L3573

1 2

0.6NH+/-0.1NH-0.85A

C3576

0.1UF

10% 16V X5R-CERM 0201

0201

NOSTUFF

1 2

0.6NH+/-0.1NH-0.85A

NOSTUFF

8

BOM OPTION

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

CRITICAL

L3507

90-OHM DLP0NS

SYM_VER-1

4 3

0201

OMIT_TABLE

L3574

0201

OMIT_TABLE

PLACE_NEAR=J3501.11:2.54MM

ALS CAMERA

21

USB_CAMERA_N

USB_CAMERA_P

PCIE_AP_R2D_PI_N

92

PCIE_AP_D2R_P

1

2

CRITICAL

L3501

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

7

91

7

91

NOSTUFF

1

C3573

0.1UF

10% 16V

2

X5R-CERM 0201

NOSTUFF

C3575

0.1UF

10% 16V X5R-CERM 0201

PCIE_AP_D2R_N

NOSTUFF

1

C3577

0.1UF

10% 16V

2

X5R-CERM 0201

21

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

USB_BT_CONN_N USB_BT_CONN_P

BI

AIRPORT

BLUETOOTH

6 3

1 2

10%

OUT

IN

19 91

C3530

17 92

1

R3515

15K

1% 1/20W MF 201

2

PM_SLP_S4_L

275 mA peak 206 mA nominal max

PLACE_NEAR=J3501.17:2.54MM

0.1UF

16V

AP_RESET_CONN_L

7

AP_CLKREQ_Q_L

7

PCIE_AP_R2D_C_N

0402X7R-CERM

NOSTUFF

1

R3517

15K

1% 1/20W MF 201

2

NOSTUFFNOSTUFF

1

R3516

15K

1% 1/20W MF 201

2

BTPWR:S4

R3511

0

1 2

5%

1/20W

MF

201

17 92

IN

7

42

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PLACE_NEAR=J3501.29:2.54MM

17 92

IN

17 92

IN

BTPWR:S3

1

R3518

0

5%

1/20W

MF

201

2

BTMUX_SEL

NOSTUFF

1

C3511

0.01UF

10% 16V

2

X7R-CERM

0402

PLACE_NEAR=J3502.6:2.54MM

FERR-120-OHM-1.5A

1

2

1A PEAK

FERR-120-OHM-3A

PP3V3_WLAN

1

C3522

0.1uF

20% 10V

2

CERM

402

1

Y+

2

Y-

U3510

PI3USB102ZLE

CRITICAL

10

SEL OE*

L3508

0402-LF

C3552

0.1uF

20% 10V CERM 402

155S0367

L3504

1 2

9

VCC

TQFN

GND

3

12

PP3V3_WLAN_F

0603

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

1

C3521

0.1uF

20% 10V

2

CERM

402

PLACE_NEAR=J3501.29:2.54MM

PP3V3_S3RS4_BT_F

1

C3510

0.1UF

10%

6.3V

2

X5R 201

5

USB_BT_WAKE_P

91

M+

4

USB_BT_WAKE_N

91

M-

7

USB_BT_P

D+

6

USB_BT_N

D-

8

SEL OUTPUT

L USB_BT_WAKE H USB_BT

=PP5V_S3_ALSCAMERA

CURRENT SENSE

34 99

IN

7

34

BTPWR:S4

1

R3512

9

91

BI BI

15K

1%

9

91

1/20W MF 201

2

8

OUT

PP3V3_WLAN_R

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

NOSTUFF

1

R3514

15K

1% 1/20W MF 201

2

NOSTUFF

1

R3513

15K

1% 1/20W MF 201

2

3V S3 WLAN FET

CRITICAL

Q3550

DFN2563-6

D

G

3

P3V3WLAN_SS

3

D

G S

DMP2018LFK

P-TYPE

14 mOhm Typ 20 mOhm Max

1 A (EDP)

2

S

1

=BT_WAKE_L

2

MOSFET

CHANNEL

RDS(ON) @ 2.5V

LOADING

DMP2018LFK

4

C3550

0.1UF

1 2

10% 16V

X7R-CERM

0402

SIGNAL_MODEL=EMPTY

BTPWR:S4

Q3510

SSM3K15FV

SOD-VESM-HF

1

Supervisor & CLKFREG # Isolation

Delay = 130 ms +/- 20%

PP3V3_WLAN_F

1

R3553

2

100K

1% 1/16W MF-LF 402

1

R3554

232K

1% 1/16W MF-LF 402

2

P3V3WLAN_VMON

1

R3555

100K

1% 1/16W MF-LF 402

2

=PP3V3_S3_WLAN

1

2

5%

=PP3V3_S3_WLAN

1

DLY

MR*

EN

OUT

(OD)

GND

5

R3551

10K

5% 1/16W MF-LF 402

3

6 8

PM_WLAN_EN_L

1

C3540

0.1uF

20% 10V

2

CERM 402

1

C3551

0.033UF

10% 16V

2

X5R 402

R3550

33K

1 2

1/16W MF-LF

402

42

OUT

34 99

CRITICAL

VDD

U3540

SLG4AP041V

TDFN

2

SENSE

+

-

VREF

4

RESET*

7

IN

THRM

PAD

9

SYNC_MASTER=D2_KEPLER

PAGE TITLE

X29/ALS/CAMERA CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8

34

8

34

IN

AP_RESET_L

AP_PWR_EN

AP_CLKREQ_L

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

35 OF 132

SHEET

34 OF 99

124578

70

IN

OUT

4.18.0

25

19 24 70

17

SIZE

C

B

A

D

8 7 6 5 4 3

12

NO_TEST=TRUE

NO_TEST=TRUE NO_TEST=TRUE

NO_TEST=TRUE

AB9

PERP_0

AA10

PERN_0

AA12

PERP_1

AB13

PERN_1

AB15 AA16

AA18 AB19

R6

J2

AD23

AC24

W18

W16

Y7

R4

P5

AD3

W4

V1

AB3

AA6

R2

N4

AB5

E14

D13

E16 D15

E18

D17

E20

D19

A6

B5

U6

E6

D5

E8

D7

E10

D9

E12

D11

A4 B3

T5

G24

E24

G22

E22

K1

G4

L24

J24

L22 J22

N2

J6

A16

B17

A18 B19

F3 F1

H1

G2

M3 L2 H3 L4

RECEIVE

PERP_2 PERN_2

PERP_3 PERN_3

PERST_N

PWR_ON_POC_RSTN

MONDC0 MONDC1

MONOBS_P MONOBS_N

THERMDA

EE_DI EE_DO EE_CS_N

EEPROM

EE_CLK

TDI TMS TCK TDO TEST_EN TEST_PWR_GOOD

DPSNK0_3_P DPSNK0_3_N

DPSNK0_2_P DPSNK0_2_N

DPSNK0_1_P DPSNK0_1_N

DPSNK0_0_P DPSNK0_0_N

DPSNK0_AUX_P DPSNK0_AUX_N

DPSNK0_HPD

DPSNK1_3_P DPSNK1_3_N

DPSNK1_2_P DPSNK1_2_N

DPSNK1_1_P DPSNK1_1_N

DPSNK1_0_P DPSNK1_0_N

DPSNK1_AUX_P DPSNK1_AUX_N

DPSNK1_HPD

PA_CIO0_TX_P/DP_SRC_0_P PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_RX_P PA_CIO0_RX_N

PA_CONFIG1/CIO_0_LSEO PA_CONFIG2/CIO_0_LSOE

PA_CIO1_TX_P/DP_SRC_2_P PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_RX_P PA_CIO1_RX_N

PA_LSTX/CIO_1_LSEO PA_LSRX/CIO_1_LSOE

PA_DPSRC_1_P PA_DPSRC_1_N

PA_DPSRC_3_P PA_DPSRC_3_N

PA_AUX_P PA_AUX_N

PA_DPSRC_HPD

GPIO_0/PA_HV_EN/BYP0 GPIO_10/PA_CIO_SEL/BYP1 GPIO_12/PA_DP_PWRDN/BYP2

0201

1/20W

0.1UF

10% 16V

1 2

X5R-CERM

16V10%

16V

X5R-CERM

10%

16V

10%

X5R-CERM

16V

X5R-CERM

10%

16V

X5R-CERM

10%

16V

X5R-CERM

10%

X5R-CERM

16V

X5R-CERM

10%

92

0201

92

0201

92

0201

92

0201

92

0201

92

0201

92

0201

92

0201

37

IN

PCIE_TBT_R2D_P<0> PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<1> PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<2> PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<3> PCIE_TBT_R2D_N<3>

TBT_PCIE_RESET_L

TBT_PWR_ON_POC_RST_L

1

OMIT

R3615

NOSTUFF

NONE NONE NONE 0201

1

R3629

0

5% 1/20W MF 201

2

OUT

100K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

1

2

1

2

1

2

1

0

5%

MF

201

2

82

R3630

82

OUT

R3631

TP_TBT_MONDC0 TP_TBT_MONDC1

DEBUG: For monitoring current/voltage

TBT_MONOBSP TBT_MONOBSN

DEBUG: For monitoring clock

TP_TBT_THERM_DP

47

Use AA8 GND ball for THERM_DN

TBT_SPI_MOSI

93

TBT_SPI_MISO

93

TBT_SPI_CS_L

93

TBT_SPI_CLK

93

JTAG_TBT_TDI

20

IN

JTAG_TBT_TMS

20

IN

JTAG_TBT_TCK

20

IN

JTAG_TBT_TDO

20

OUT

TBT_TEST_EN TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

7

35 95

DP_TBTSNK0_ML_N<3>

7

35 95

DP_TBTSNK0_ML_P<2>

7

35 95

DP_TBTSNK0_ML_N<2>

7

35 95

DP_TBTSNK0_ML_P<1>

7

35 95

DP_TBTSNK0_ML_N<1>

7

35 95

DP_TBTSNK0_ML_P<0>

7

35 95

DP_TBTSNK0_ML_N<0>

7

35 95

DP_TBTSNK0_AUXCH_P

7

35 95

DP_TBTSNK0_AUXCH_N

7

35 95

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_P<3>

7

35 95

DP_TBTSNK1_ML_N<3>

7

35 95

DP_TBTSNK1_ML_P<2>

7

35 95

DP_TBTSNK1_ML_N<2>

7

35 95

DP_TBTSNK1_ML_P<1>

7

35 95

DP_TBTSNK1_ML_N<1>

7

35 95

DP_TBTSNK1_ML_P<0>

7

35 95

DP_TBTSNK1_ML_N<0>

7

35 95

DP_TBTSNK1_AUXCH_P

7

35 95

DP_TBTSNK1_AUXCH_N

7

35 95

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

7

84 93

OUT

TBT_A_R2D_C_N<0>

7

84 93

OUT

TBT_A_D2R_P<0>

7

84 93

IN

TBT_A_D2R_N<0>

7

84 93

IN

TBT_A_CONFIG1_BUF

82 84

OUT

TBT_A_CONFIG2_RC

84

IN

TBT_A_R2D_C_P<1>

7

84 93

OUT

TBT_A_R2D_C_N<1>

7

84 93

OUT

TBT_A_D2R_P<1>

7

84 93

IN

TBT_A_D2R_N<1>

7

84 93

IN

TBT_A_LSTX

84

OUT

TBT_A_LSRX

84

IN

DP_TBTPA_ML_C_P<1>

84 93

OUT

DP_TBTPA_ML_C_N<1>

84 93

OUT

DP_TBTPA_ML_C_P<3>

84 93

OUT

DP_TBTPA_ML_C_N<3>

84 93

OUT

DP_TBTPA_AUXCH_C_P

84 93

BI

DP_TBTPA_AUXCH_C_N

84 93

BI

DP_TBTPA_HPD

35 84

IN

TBT_A_HV_EN

35 37 84

OUT

TBT_A_CIO_SEL

84

OUT

TBT_A_DP_PWRDN

35 84

OUT

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

PCIE_TBT_R2D_C_P<0>

9

92

IN

PCIE_TBT_R2D_C_N<0>

9

92

IN

PCIE_TBT_R2D_C_P<1>

9

92

IN

PCIE_TBT_R2D_C_N<1>

9

92

IN

PCIE_TBT_R2D_C_P<2>

9

92

D

=PP3V3_S4_TBT

35 36 37

1

R3610

47K

5%

1/20W

MF

201

2

37

IN

=PP3V3_TBTLC_RTR

1

3.3K

1/20W

1

R3691

3.3K

5%

5% 1/20W

MF

201

2

R3690

(TBT_SPI_MOSI)

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

TBTROM_WP_L

C

TBTROM_HOLD_L

8

C3690

35 36 37

1UF

10%

6.3V CERM

402

1

2

5

6

1

3

7

8

VCC

D

U3690

M95256-RMC6XG

MLP

C

S*

W*

HOLD*

VSS

4

CRITICAL OMIT_TABLE

THM PAD

9

92

9

92

9

92

2

Q

IN

PCIE_TBT_R2D_C_N<2>

IN

PCIE_TBT_R2D_C_P<3>

IN

PCIE_TBT_R2D_C_N<3>

IN

(TBT_SPI_MISO)

R3692

3.3K

1/20W

1

5% MF

201

2

1

R3693

3.3K

5% 1/20W MF 201

2

C3600

C3601

C3602

C3603

C3604

C3605

C3606

C3607

NO STUFF

C3610

0.1UF

X5R-CERM

R3625

SNK0 AC Coupling

DP_TBTSNK0_ML_C_P<0>

7

77 95

IN

DP_TBTSNK0_ML_C_N<0>

7

77 95

IN

DP_TBTSNK0_ML_C_P<1>

7

77 95

IN

DP_TBTSNK0_ML_C_N<1>

7

77 95

IN

B

7

77 95

IN

7

77 95

IN

7

77 95

IN

7

77 95

IN

7

83 95

BI

7

83 95

BI

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

C3620

C3621

C3622

C3623

C3624

C3625

C3626

C3627

C3628

C3629

0.1UF

1 2

10% 16V X5R-CERM

10% X5R-CERM

X5R-CERM

10% X5R-CERM

X5R-CERM

10% X5R-CERM

0201

16V

0201

16V10%

0201

16V

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V10%

0201

16V

0201

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_AUXCH_N

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

SNK1 AC Coupling

DP_TBTSNK1_ML_C_P<0>

7

77 95

IN

DP_TBTSNK1_ML_C_N<0>

7

77 95

IN

DP_TBTSNK1_ML_C_P<1>

7

77 95

IN

DP_TBTSNK1_ML_C_N<1>

7

77 95

IN

DP_TBTSNK1_ML_C_P<2>

7

77 95

A

IN

7

77 95

IN

7

77 95

IN

7

77 95

IN

7

83 95

BI

7

83 95

BI

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

C3630

C3631

C3632

C3633

C3634

C3635

C3636

C3637

C3638

C3639

0.1UF

1 2

10% X5R-CERM

X5R-CERM

10% X5R-CERM

X5R-CERM

16V

0201

16V

0201

16V10%

0201

16V

0201

16V

0201

16V

0201

16V

0201

16V

0201

16V

0201

16V10%

0201

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_AUXCH_N

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

CRITICAL

OMIT_TABLE

U3600

CACTUSRIDGE4C

FCBGA

(SYM 1 OF 2)

JTAG/TEST PORT

SINK PORT 0SINK PORT 1

PORT0PORT1

PETP_0 PETN_0

PETP_1 PETN_1

PETP_2

TRANSMIT

PETN_2

PCIE GEN2

PETP_3 PETN_3

RSENSE

RBIAS

PCIE_RST_0_N PCIE_RST_1_N PCIE_RST_2_N PCIE_RST_3_N

MISC

PCIE RESET

PCIE_CLKREQ_OD_N

EN_LC_PWR

REFCLK_100_IN_P REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

CLOCKS

TMU_CLK_OUT

TMU_CLK_IN

DPSRC_3_P DPSRC_3_N

DPSRC_2_P DPSRC_2_N

DPSRC_1_P DPSRC_1_N

DPSRC_0_P DPSRC_0_N

SOURCE PORT 0

DPSRC_AUX_P

DISPLAYPORT

GPIO_5/CIO_PLUG_EVENT

GPIO_8/EN_CIO_PWR_OD*

PB_CIO2_TX_P/DP_SRC_0_P PB_CIO2_TX_N/DP_SRC_0_N

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DP_SRC_2_P PB_CIO3_TX_N/DP_SRC_2_N

PORT3 PORT2

PORTS

DPSRC_AUX_N

DPSRC_HPD_OD

GPIO_2/GO2SX

(FORCE_PWR)

GPIO_4/WAKE_N_OD

GPIO_6/CIO_SDA_OD GPIO_7/CIO_SCL_OD

GPIO_9/OK2GO2SX_OD*

PB_LSTX/CIO_3_LSEO PB_LSRX/CIO_3_LSOE

GPIO_3

GPIO_14 GPIO_15

PB_CIO2_RX_P PB_CIO2_RX_N

PB_CIO3_RX_P PB_CIO3_RX_N

PB_DPSRC_1_P PB_DPSRC_1_N

PB_DPSRC_3_P PB_DPSRC_3_N

PB_AUX_P PB_AUX_N

PB_DPSRC_HPD

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

AD5

PCIE_TBT_D2R_C_P<0>

92

AD7

PCIE_TBT_D2R_C_N<0>

92

AD9

PCIE_TBT_D2R_C_P<1>

92

AD11

PCIE_TBT_D2R_C_N<1>

92

AD13

PCIE_TBT_D2R_C_P<2>

92

AD15

PCIE_TBT_D2R_C_N<2>

92

AD17

PCIE_TBT_D2R_C_P<3>

92

AD19

PCIE_TBT_D2R_C_N<3>

92

U20

TBT_RSENSE

W20

TBT_RBIAS

U4

NC

Not used in host mode.

N6

TP_TBT_PCIE_RESET0_L

T1

TP_TBT_PCIE_RESET1_L

Y5

TP_TBT_PCIE_RESET2_L

U2

TP_TBT_PCIE_RESET3_L

W6

=TBT_CLKREQ_L

K5

TBT_EN_LC_PWR

PCIE_CLK100M_TBT_P

AB21 AD21

PCIE_CLK100M_TBT_N

AA24

SYSCLK_CLK25M_TBT_R

91

AB23

TP_TBT_XTAL25OUT

AA4

TBT_TMU_CLK_OUT

Y3

TBT_TMU_CLK_IN

A14

TP_DP_TBTSRC_ML_CP<3>

B15

TP_DP_TBTSRC_ML_CN<3>

A12

TP_DP_TBTSRC_ML_CP<2>

B13

TP_DP_TBTSRC_ML_CN<2>

A10

TP_DP_TBTSRC_ML_CP<1>

B11

TP_DP_TBTSRC_ML_CN<1>

A8

TP_DP_TBTSRC_ML_CP<0>

B9

TP_DP_TBTSRC_ML_CN<0>

C2

TP_DP_TBTSRC_AUXCH_CP

D3

TP_DP_TBTSRC_AUXCH_CN

V3

DP_TBTSRC_HPD

Y1

TBT_GO2SX_BIDIR

W2

TBT_PWR_EN

J4

=TBT_WAKE_L

AA2

TBT_CIO_PLUG_EVENT

AB1

=I2C_TBTRTR_SDA

AC2

=I2C_TBTRTR_SCL

P3

(TBT_EN_CIO_PWR_L)

M5

TBT_GPIO_9

35

T3

TBT_GPIO_14

V5

TBT_DDC_XBAR_EN_L

R24

TBT_B_R2D_C_P<0>

N24

TBT_B_R2D_C_N<0>

R22

TBT_B_D2R_P<0>

N22

TBT_B_D2R_N<0>

P1

TBT_B_CONFIG1_BUF

H5

TBT_B_CONFIG2_RC

W24

TBT_B_R2D_C_P<1>

U24

TBT_B_R2D_C_N<1>

W22

TBT_B_D2R_P<1>

U22

TBT_B_D2R_N<1>

L6

TBT_B_LSTX

G6

TBT_B_LSRX

A20

DP_TBTPB_ML_C_P<1>

B21

DP_TBTPB_ML_C_N<1>

A22

DP_TBTPB_ML_C_P<3>

B23

DP_TBTPB_ML_C_N<3>

D1

DP_TBTPB_AUXCH_C_P

E2

DP_TBTPB_AUXCH_C_N

K3

DP_TBTPB_HPD

M1

TBT_B_HV_EN TBT_B_CIO_SEL TBT_B_DP_PWRDN

6 3

NO_TEST=TRUE

NO_TEST=TRUE NO_TEST=TRUE

NO_TEST=TRUE

C3640

C3641

C3642

C3643

C3644

C3645

C3646

C3647

1

R3655

1K

1% 1/20W MF 201

2

7

OUT

IN IN

7

BI

IN OUT OUT

BI

IN

35

OUT

OUT OUT

IN

OUT

IN

OUT OUT

IN

OUT

IN

OUT OUT

BI

IN

OUT OUT OUT

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

37

17 92

20

20 25

18 42

20

44

TBT_EN_CIO_PWR_L

35 82

7

85 93

7

85 93

7

85 93

7

85 93

82 85

85

7

85 93

7

85 93

7

85 93

7

85 93

85

85 93

35 85

35 37 85

85

35 85

PCIE_TBT_D2R_P<0>

16V

X5R-CERM

10%

PCIE_TBT_D2R_N<0>

X5R-CERM

16V10%

PCIE_TBT_D2R_P<1>

16V

X5R-CERM

10%

PCIE_TBT_D2R_N<1>

16V

X5R-CERM

10%

PCIE_TBT_D2R_P<2>

X5R-CERM

10%

16V

PCIE_TBT_D2R_N<2>

10% 16V

X5R-CERM

PCIE_TBT_D2R_P<3>

16V

X5R-CERM

10%

PCIE_TBT_D2R_N<3>

X5R-CERM

10% 16V

OUT

1

R3697

100K

5% 1/20W MF 201

2

1

R3681

0

5% 1/20W MF 201

2

R3632

100K

TBT_PWR_REQ_L

MAKE_BASE=TRUE

37

NO STUFF

5%

1/20W

MF

201

9

92

0201

R3699

1/20W

1

2

10K

201

1

R3698

10K

2

5% MF

35 78 82

OUT

9

92

OUT

9

92

OUT

9

92

OUT

9

92

OUT

9

92

OUT

9

92

OUT

9

92

OUT

=PP3V3_TBTLC_RTR

5% 1/20W MF 201

1

R3696

1K

5% 1/20W MF 201

2

CR HPD INPUTS (S4) FORWARDED TO GMUX (S0)

19

37

OUT

=PP3V3_S0_DPMUX_UC

8

=PP3V3_S0_DPMUX_UC

8

SYNC_MASTER=D2_KEPLER

PAGE TITLE

8

35 36 37

R3695

806

1 2

SYSCLK_CLK25M_TBT

1%

Divides 3.3V to 1.8V

1/20W

MF

201

=PP3V3_S0_DPMUX_UC

8

35 78 82

DP_TBTPB_HPD

35 85

IN

NOSTUFF

1 2

=PP3V3_S0_DPMUX_UC

8

35 78 82

DP_TBTPA_HPD

35 84

IN

NOSTUFF

1 2

R3642

1/20W

R3643

1/20W

=PP3V3_S4_TBT

35 36 37

TBT_A_DP_PWRDN

35 84

TBT_B_DP_PWRDN

35 85

TBT_A_HV_EN

35 37 84

TBT_B_HV_EN

35 37 85

=PP3V3_TBTLC_RTR

8

35 36 37

TBT_DDC_XBAR_EN_L

35 82

TBT_GPIO_9

35

TBT_GPIO_14

35

1K

DP_TBTPB_HPD_BUF_EN

5%

MF

201

1K

DP_TBTPA_HPD_BUF_EN

5%

MF

201

5

A Y

OE

2

A Y

OE

8

VCC

GND

4

7

8

VCC

GND

4

1

Thunderbolt Host (1 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

R3685

10K

5%

1/20W

MF

201

R3688

10K

5%

1/20W

MF

201

25 91

IN

R3680

1/20W

R3683

1/20W

NOSTUFF

U3610

74LVC2G126GT/S500

SOT833

DP_TBTPB_HPD_BUF

3

NOSTUFF

U3610

74LVC2G126GT/S500

SOT833

DP_TBTPA_HPD_BUF

6

R3645

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

1

R3686

10K

5% 1/20W MF 201

2

1

R3687

10K

5% 1/20W MF 201

2

1

10K

5% MF

201

2

NO STUFF

1

5% MF

201

2

R3644

100K

1/20W

100K

1/20W

201

R3682

10K

5% 1/20W MF 201

2

1

5%

MF

201

2

1

5%

MF

2

10K

SYNC_DATE=01/13/2012

051-9589

4.18.0

36 OF 132

35 OF 99

D

C

B

82

OUT

82

OUT

A

SIZE

D

8 7 6 5 4 3

=PP1V05_TBTLC_RTR

8

???? mW (Single Port) 250 mW (Dual Port)

D

EDP: 1600 mA

C3700

10UF

6.3V

CERM-X5R

0402-1

C3701

10UF

6.3V

CERM-X5R

0402-1

1

C3710

20%

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C3715

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C3711

2

1

C3716

2

1.0UF

20% 10V X5R-CERM 0201-1

1.0UF

20% 10V X5R-CERM 0201-1

1

C3712

2

1

C3717

2

1.0UF

20% 10V X5R-CERM 0201-1

1.0UF

20% 10V X5R-CERM 0201-1

1

C3713

2

1.0UF

20% 10V X5R-CERM 0201-1

C

B

A

1

C3714

2

1.0UF

20% 10V X5R-CERM 0201-1

AA14 AA20

AA22

AB11

AB17

AC10

AC12 AC14

AC16

AC18 AC20

AC22

J10 J12

J14

J16

J8

K17

T15 U14

V7 W8

G10

G12

G14 G16

G18

H19 K19

M19 P19

T19

V15 V19

W12

W14

G8

H9

AD1 K13

K9

L12 L16

L8

M13 M17

M9

N12 N16

N8 P13

P17

P9 R12

R16

R8 T13

T17

T9 U12

U16

U8

V9

A2

A24

AA8

AB7

AC4 AC6

AC8

B1

B7

C10 C12

C14

C16 C18

C20

VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0_DPAUX VCC1P0_DPAUX

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

CRITICAL

OMIT_TABLE

U3600

CACTUSRIDGE4C

FCBGA

(SYM 2 OF 2)

VCCGND

VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0

VCC3P3 VCC3P3 VCC3P3

VCC3P3_CIO VCC3P3_CIO VCC3P3_CIO

VCC3P3_DP VCC3P3_DP VCC3P3_DP VCC3P3_DP

VCC3P3_DPAUX

VCC3P3_POC

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

K11 K15

L10

L14 M11

M15

N10 N14

P11 P15

R10

R14 T11

U10

V11 W10

M7 P7

T7

L18 N18

R18

H11

H13 H15

H17

H7

PP3V3_S4_TBT

K7

C22 C24

C4

C6 C8

D21 D23

E4

F11 F13

F15

F17 F19

F21

F23 F5

F7 F9

G20

H21 H23

J18

J20 K21

K23

L20 M21

M23 N20

P21

P23 R20

T21

T23 U18

V13

V17 V21

V23 Y11

Y13

Y15 Y17

Y19

Y21 Y23

Y9

C3740

1.0UF

20% 10V

X5R-CERM

0201-1

C3770

1.0UF

20% 10V

X5R-CERM

0201-1

VOLTAGE=3.3V MAKE_BASE=TRUE

C3790

1.0UF

20% 10V

X5R-CERM

0201-1

1

2

1

2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM

35 37

1

2

C3741

1.0UF

20% 10V

X5R-CERM

0201-1

C3771

1.0UF

20% 10V

X5R-CERM

0201-1

=PP3V3_S4_TBT EDP: 10 mA

1

2

1

2

C3742

1.0UF

X5R-CERM

0201-1

C3772

1.0UF

X5R-CERM

0201-1

R3790

1 2

20% 10V

1/16W MF-LF

1

2

1

2

0

5%

402

1

C3743

1.0UF

20% 10V

2

X5R-CERM

0201-1

1

C3773

1.0UF

20% 20% 10V

2

X5R-CERM

0201-1

=PP3V3_S4_TBT_R

C3744

1.0UF

X5R-CERM

0201-1

C3774

1.0UF

X5R-CERM

0201-1

1

C3745

1.0UF

20% 10V

2

1

10V

2

8

20% 10V

X5R-CERM

0201-1

=PP3V3_TBTLC_RTR

??? mW (Single-Port) 250 mW (Dual-Port) EDP: 240 mA

1

C3760

10UF

20%

6.3V

2

CERM-X5R 0402-1

=PP1V05_TBTCIO_RTR ???? mW (Single-Port) 2700 mW (Dual-Port) EDP: 1100 mA

1

C3705

10UF

20%

6.3V

2

CERM-X5R 0402-1

8

35 37

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Thunderbolt Host (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8

6 3

12

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

37 OF 132

SHEET

36 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP15V_TBT_REG (15V Boost Output)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

- =PP3V3_TBTLC_FET (3.3V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP1V05_TBTLC_FET (1.05V FET Output)

Signal aliases required by this page:

- =TBT_CLKREQ_L

D

- =TBT_RESET_L

BOM options provided by this page: TBTBST:Y - Stuffs 15V boost circuitry.

TBT_A_HV_EN

35 84

IN

TBT_B_HV_EN

35 85

IN

C

=PP3V3_S0_TBTPWRCTL

8

Q3840

SSM3K15FV

SOD-VESM-HF

TBT_EN_LC_PWR

35

IN

Platform (PCIe) Reset

=TBT_RESET_L

25

IN

TBT_CLKREQ_L

17

OUT

Pull-ups provided by SB page.

D

3

TBTBST_PWREN_L

Q3805

SSM6N37FEAPE

SOT563

6

D

2

SG

1

TBTBST:YTBTBST:Y

Q3805

SSM6N37FEAPE

SOT563

5

Supervisor & CLKREQ# Isolation

1

C3800

0.1UF

10% 16V

2

X5R-CERM

0201

1

R3840

1

10K

5%

GS

1/20W MF 201

2

3

6 8

U3800

SLG4AP016V

DLY

MR*

EN OUT

(OD)

GND

5

VDD

TDFN

1

CRITICAL

SENSE

+

-

0.7V

RESET*

THRM

PAD

9

2

4

7

IN

=PPVIN_SW_TBTBST

8 9

8-13V Input Changes required for 2S.

TBTBST:Y

R3881

330K

1/16W MF-LF

3

D

SG

4

=PP3V3_TBTLC_RTR

1

R3807

100K

5% 1/20W MF 201

2

PP1V05_TBTLC

TBT_PCIE_RESET_L

DLY = 60 ms +/- 20%

=TBT_CLKREQ_L TBT_CLKREQ_ISOL_L

MAKE_BASE=TRUE

5%

402

TBTBST:Y

1

2

R3880

470K

1/16W MF-LF

402

TBTBST:Y

1

R3892

73.2K

1% 1/16W MF-LF 402

2

8

35 36 37

8

5%

<R2>

1

2

OUT

1

2

TBTBST:Y

C3890

35

IN

TBTBST:Y

C3880

0.1UF

10% 25V X5R 402

TBTBST_PWREN_DIV_L

TBTBST:Y

1

2.2UF

20% 10V X5R-CERM 402

C3891

2.2UF

20% 10V

2

X5R-CERM 402

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

CRITICAL TBTBST:Y

Q3880

SI8409DB

4

TBTBST:Y

1

C3892

2.2UF

2

BGA

SGD

1

20% 10V X5R-CERM 402

SI8409DB: Vds(max): -30V Vgs(max): +/-12V Vgs(th): -1.4V Rds(on): 46mOhm @ 4.5V Vgs Id(max): 3.7A @ 70C

PPVIN_SW_TBTBST

8

MIN_LINE_WIDTH=0.5 mm

2 3

MIN_NECK_WIDTH=0.25 mm Voltage not specified here,

add property on another page.

TBTBST:Y

1

C3887

68PF

5% 50V

2

COG-CERM 0402

TBTBST_VC_RC

1

C3893

0.0033UF

10% 50V

2

X7R-CERM 0402

TBTBST:Y

R3893

49.9K

1/16W MF-LF

TBTBST:Y

R3894

28.7K

TBTBST:Y

1

1%

402

2

1/16W MF-LF

402

Thunderbolt 15V Boost Regulator

CRITICAL TBTBST:Y

L3895

3.3UH-6.5A

R3891

200K

1/16W MF-LF

<R1>

1

1%

2

1

TBTBST:Y

C3860

10UF

20% 25V X5R-CERM

1

0603

1%

402

2

TBTBST_EN_UVLO

TBTBST_INTVCC

TBTBST_VC

TBTBST_RT

TBTBST_SS

TBTBST:Y

1

C3894

0.33UF

10%

6.3V

2

CERM-X5R 402

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

TBTBST:Y

6

D

Q3888

SSM6N37FEAPE

SOT563

Max Vgs: 10V

2

S G

TBTBST_SHDN_DIV

TBTBST:Y

1

R3887

330K

5% 1/16W MF-LF 402

2

1

C3861

2

TBTBST:Y

10UF

20% 25V X5R-CERM 0603

1

2

25

EN/UVLO

28

INTVCC

30

VC

33

RT

32

SS

34

SYNC

42324

SGND shorted to GND inside package, no XW necessary.

TBTBST:Y

1

R3888

330K

5% 1/16W MF-LF 402

2

TBTBST:Y

3

D

Q3888

SSM6N37FEAPE

SOT563

5

S G

4

VIN

SGND

27

37

1 2

PIMB063T-SM

8

CRITICAL TBTBST:Y

U3890

LT3957

QFN

1213141516

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

9

202138

SW

SNS1

SNS2

NC

FBX

GND

17

SMC_DELAYED_PWRGD

TBTBST_SNS1

TBTBST:Y

R3889

1/20W

6

3

1 2 10

NC

35 36

31

TBTBST_SNS2

TBTBST_VSNS

TBTBST:Y

1

C3888

10PF

5% 50V

2

C0G-CERM 0402

TBTBST_FBX

NO STUFF

1

C3889

100PF

5% 50V

2

CERM 402

XW3895

TBTBST:Y

R3895

TBTBST:Y

R3896

Vout = 1.6V * (1 + Ra / Rb)

IN

0

5% MF

201

137K

1/16W MF-LF

<Ra>

15.8K

1/16W MF-LF

<Rb>

41 42 70

1

1 2

2

3

SM

12

PLACE_NEAR=C3895.1:2 mm

1

1%

402

2

TBTBST:Y

1

2

1

1%

C3896

402

2

CRITICAL TBTBST:Y

D3895

PDS540XF

PWRDI5

C3895

10UF

10% 25V X5R 1206-2

TBTBST:Y

20%

25V

POLY-TANT

CASE-D3L

33UF-0.06OHM

1

2

1

2

NO STUFF

C3897

10UF

10% 25V X5R 805

=PP15V_TBT_REG

8 9

Vout = 15.47V Max Current = 2A? Freq = 300KHz

TBTBST:Y

1

C3899

0.001UF

10% 50V

2

X7R-CERM 0402

D

C

TBT "POC" Power-up Reset

B

3.3V TBT "LC" Switch

U3810

=PP3V3_S0_P3V3TBTFET

8

R3811

36.5K

1

1 2

2

1

R3816

0

5%

1/20W

MF

201

2

=PP1V05_S0_P1V05TBTFET

8

37 99

C3810

1UF

20%

6.3V X5R

0201

TBT_EN_LC_ISOL

TBT_EN_LC_1V05

A

1/20W

201

1% MF

C3815

TBT_EN_LC_3V3

C3811

1UF

20%

6.3V X5R

0201

NOSTUFF

C3816

1UF

6.3V CERM

1

1UF

10%

6.3V 2

CERM

402

A2 B2

1

C2

2

1

10%

2

402

A2 B2

C2

TPS22924

VIN

CRITICAL

ON

CSP

VOUT

GND

C1

=PP3V3_TBTLC_FET

A1

Max Current = 2A (85C)

B1

Part

Type

R(on) @ 2.5V

1.05V TBT "LC" Switch

U3815

TPS22924

CSP

VOUT

VIN

CRITICAL

ON

GND

C1

C3816 must be 10% RC guarantees minimum 5ms to reach 0.5V

=PP1V05_TBTLC_FET

A1

Max Current = 2A (85C)

B1

Part Type R(on)

@ 1.0V

8

U3815

8

U3810

TPS22924C

Load Switch

18.3 mOhm Typ 24 mOhm Max

TPS22924C Load Switch

20.3 mOhm Typ

28.6 mOhm Max

35

TBT_EN_CIO_PWR_L

IN

TBTPOCRST_CT

1

C3831

2

=PP1V05_S0_P1V05TBTFET

8

37 99

=PP3V3_TBTLC_RTR

8

35 36 37

Q3825

SSM6N37FEAPE

SOT563

2

6 3

Intel investigating whether RC is sufficient.

=PP3V3_S4_TBT

35 36

1

CRITICAL

VDD

SENSE

U3830

TPS3808

QFN

CT

GND

5

0.0047UF

10% 25V CERM 0402

C3830

0.1UF

10% 25V X5R 402

3

1

2

1.05V TBT "CIO" Switch

U3820

1

C3820

1UF

2

A2 B2 C2

D2

20%

6.3V X5R 0201

TPS22920

CSP

VOUT

VIN

CRITICAL

ON

GND

D1

1

R3820

100K

5% 1/20W MF 201

2

TBT_EN_CIO_PWR

6

D

SG

1

62

RESET*

4

MR*

THRM

PAD

7

TPS3808G25 Vt = 2.33V +/- 2% Delay = 27.3ms

=PP1V05_TBTCIO_FET

A1

Max Current = 4A (85C)

B1 C1

Pull-up: R3610

TBT_PWR_ON_POC_RST_L

TBTPOCRST_MR_L

1

C3825

330PF

10% 16V

2

X7R-CERM 0201

U3820

Part Type R(on)

@ 1.05V

35

OUT

Q3825

SSM6N37FEAPE

8

TPS22920 Load Switch 8 mOhm Typ

11.5 mOhm Max

SOT563

D

3

=PP3V3_S0_PCH_GPIO

1

R3830

100K

5

S G

4

5% 1/20W MF 201

2

TBT_SW_RESET_L

IN

8

17 18 19 20 25

20

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Thunderbolt Power Support

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

Apple Inc.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

38 OF 132

SHEET

37 OF 99

124578

SIZE

B

A

D

8 7 6 5 4 3

12

D

J4400

20525-130E-01

SIGNAL_MODEL=EMPTY

BEAD-PROBE

BP4405

SIGNAL_MODEL=EMPTY

BEAD-PROBE

BP4406

SIGNAL_MODEL=EMPTY

BEAD-PROBE

BP4401

BEAD-PROBE

BP4402

SIGNAL_MODEL=EMPTY

516S0853

J4410

AXK732327G

F-ST-SM

33

C

25

17

9 7

25

24

=ENET_RESET_L

IN

ENET_CLKREQ_L

7

OUT

SD_PWR_EN

IN

SDCONN_STATE_CHANGE_RIO

7

OUT

USB_EXTB_OC_L

7

OUT

=PP1V5_S0_RIO

8

=PP3V3_S3_RIO

8

=PP3V3_S4_RIO

8

=I2C_HDMIRDRV_SCL

44

=I2C_HDMIRDRV_SDA

44

=PP5V_S4_RIO

8

1 3 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32

2 4

10

20

30

34

PM_SLP_S3_L PM_SLP_S4_L HDMI_EG_DDC_CLK HDMI_EG_DDC_DATA HDMI_HPD_L

7

IN

7

IN

77

7

IN

77

7

BI

82 42

7

OUT

1

TP

SM

91 19

1

TP

SM

91 19

7

91 19

7

70 41 27 18

70 41 40 34 27 18

IN IN

OUT OUT

USB3_EXTB_TX_P USB3_EXTB_TX_N

USB3_EXTB_RX_P USB3_EXTB_RX_N

C4402

0.1UF

X5R-CERM

12

1/20W

GND_VOID=TRUE

15PF

25V

GND_VOID=TRUE

12

1/20W

GND_VOID=TRUE

15PF

25V

GND_VOID=TRUE

C4401

1 2

10%

0201

1 2

201

1%

MF

C4403

1 2

201

1%

MF

C4404

1 2

NP0-CERM 02015%

0.1UF

X5R-CERM

16V

R4403

R4404

GND_VOID=TRUE

0201

0201NP0-CERM5%

1 2

10%

16V

SIGNAL_MODEL=EMPTY

BEAD-PROBE

BP4403

BEAD-PROBE

BP4404

SIGNAL_MODEL=EMPTY

1

TP

SM

1

91 26

TP

SM

TP

SM

TP

SM

7

91 26

7

95 77

7

95 77

7

1 1

95 77

7

95 77

7

95 77

7

95 77

7

95 77

7

95 77

7

92 17

7

92 17

7

92 17

7

92 17

7

92 17

7

92 17

7

BI BI

IN IN

OUT OUT

IN IN

USB_EXTB_P USB_EXTB_N

USB3_EXTB_TX_C_P

97

7

USB3_EXTB_TX_C_N

97

7

USB3_EXTB_RX_RC_P

97

USB3_EXTB_RX_RC_N

97

HDMI_EG_DATA_C_P<0> HDMI_EG_DATA_C_N<0>

HDMI_EG_DATA_C_P<1> HDMI_EG_DATA_C_N<1>

HDMI_EG_DATA_C_P<2> HDMI_EG_DATA_C_N<2>

HDMI_EG_CLK_C_P HDMI_EG_CLK_C_N

PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N

PCIE_ENET_D2R_P PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N

GND_VOID=TRUE GND_VOID=TRUE

B

31

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

33 34 35 36 37 38 39 40 41

32

F-RT-SM

1 2 3 4 5 6 7 8 9

D

C

B

518S0829

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

RIO CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

44 OF 132

SHEET

38 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

69 70

CRITICAL

R4599

0.005

1% 1W MF

0612

2 1 4 3

=PP3V3_S0_SSD

ISNS_SSD_P ISNS_SSD_N

=PP3V3_S0_SATAMUX

8

OUT OUT

1

R4505

100K

5% 1/16W MF-LF 402

2

SATAMUX_EN_L

1

R4510

10K

5% 1/20W MF 201

2

97 99

U4510

CBTL02043ABQ

3

A0_P

4

A0_N

7

A1_P

8

A1_N

9

SEL

2

XSD

1610

VDD

VQFN

CRITICAL

VSS

5

11

20

353S3361

21

THRM

PAD

B0_P B0_N

B1_P B1_N

C0_P C0_N

C1_P C1_N

1

2

C4505

0.1UF

20% 10V CERM 402

19 18

17 16

15 14

13 12

1

C4514

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U4510.10:2 mm

PLACE_NEAR=U4510.6:2 mm

PCIE_SSD_R2D_MUX_IN_P

92

PCIE_SSD_R2D_MUX_IN_N

92

SATA_SSD_R2D_MUX_IN_P

91

SATA_SSD_R2D_MUX_IN_N

91

1

C4519

0.01UF

20% 16V

2

X7R-CERM 0402

PCIE_SSD_D2R_MUX_OUT_P

PCIE_SSD_D2R_MUX_OUT_N

92

SATA_SSD_D2R_MUX_OUT_P

91

SATA_SSD_D2R_MUX_OUT_N

91

C4513

C4512

R4518

5%

R4517

5%

0.1UF

C4516

C4515

C4511

C4510

GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

1 2

1/20W

1 2

1/20W

1 2

0.01UF

MF0201

MF

10%

0

201

16V

X5R-CERM

16V

X5R-CERM

GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

1 2

PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_R2D_C_P<0>

0201

PCIE_SSD_R2D_C_N<0>

0201

X7R25V

10% 402

10% X7R25V

10% 25V X7R

OUT

IN

SATA_HDD_D2R_P

SATA_HDD_D2R_N

402

SATA_HDD_R2D_C_P

402

SATA_HDD_R2D_C_N

402

SIGNAL_MODEL=EMPTY

1

TP

BEAD-PROBE

9

SM

92

SIGNAL_MODEL=EMPTY

1

TP

SM

92

17 91

OUT

17 91

OUT

17 91

IN

17 91

IN

BEAD-PROBE

SIGNAL_MODEL=EMPTY

1

TP

SM

BP4501

BP4502

BEAD-PROBE

BP4503

PLACE_NEAR=J4501.9:3mm

CRITICAL

L4500

PP3V3_S0_SSD_FLT

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=3.3V

FERR-26-OHM-6A

0603

1

C4501

0.1UF

20% 10V

2

CERM 402

PP3V3_S0_SSD_R

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=3.3V

1

C4502

0.1UF

20% 10V

2

CERM 402

514S0393

C

B

CRITICAL

J4501

SSD-J5

F-RT-SM

1 2 3 4

GND_VOID=TRUE

5

GND_VOID=TRUE

6 7

GND_VOID=TRUE

8

GND_VOID=TRUE

9 10

GND_VOID=TRUE

11

GND_VOID=TRUE

12 13

GND_VOID=TRUE

14

GND_VOID=TRUE

15 16 17 18

19 20 21 22 23 24 25 26

27 28 29 30 31 32 33 34 35

Per PCIe spec, only TX side should have AC cap

GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

R4526

PCIE_SSD_D2R_C_P<1>

92

PCIE_SSD_D2R_C_N<1>

92 92

SATA_SSD_D2R_P

91

SATA_SSD_D2R_N

91

PCIE_SSD_R2D_P<1>

92

PCIE_SSD_R2D_N<1>

92

SATA_SSD_R2D_P

91

SATA_SSD_R2D_N

91

R4525

0.1UF

C4520

X5R-CERM

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

SSD_CLKREQ_L SSD_RESET_L SATA_PCIE_SEL SMC_OOB1_RX_L SMC_OOB1_TX_L SSD_P3V3S0_EN

1 2

1/20W

5%

C4521

1 2

5%

X5R-CERM

10%

0

MF

0.1UF

16V

1/20W

201

1 2

0201

IN IN

OUT

IN

17 92

17

25

0

MF

10%

PCIE_SSD_D2R_P<1>

201

PCIE_SSD_D2R_N<1>

PCIE_SSD_R2D_C_P<1>

16V

PCIE_SSD_R2D_C_N<1>

R4520

0

1 2

5%

1/20W

MF

201

0201

OUT

IN

=P3V3S0_EN

9

92

9

92

9

92

9

92

IN

D

C

B

PCIE/SATA GUMSTICK2 CONNECTOR

A

SYNC_MASTER=D2_KEPLER

PAGE TITLE

SSD CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

45 OF 132

SHEET

39 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

USB Port Power Switch

D

Left USB Port A

=PP5V_S3_LTUSB

8

PM_SLP_S4_L

7

18 27 34 38 41 70

1

R4690

5.1K

5% 1/16W MF-LF

402

C4692

0.47UF

0402

2

USB_PWR_EN

CRITICAL

1

2

220UF-35MOHM

CASE-B2-SM1

10% 10V X5R

C4696

POLY-TANT

6.3V

1

20%

2

24

OUT

USB_EXTA_OC_L

C4690

10UF

6.3V

1

C4691

0.1UF

20% X5R

603

20% 10V

2

CERM 402

CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX

C

USB/SMC Debug Mux

=PP3V42_G3H_SMCUSBMUX

8

SMC_DEBUG_YES

SMC_DEBUGPRT_RX_L

41 42

IN

SMC_DEBUGPRT_TX_L

41 42

OUT

USB_EXTA_P

19 91

BI

USB_EXTA_N

19 91

BI

B

C4650

0.1UF

CERM

1

20% 10V

2

402

5

4

7

6

8

9

VCC

M+ M-

U4650

PI3USB102ZLE

TQFN

D+

CRITICAL

D-

SMC_DEBUG_YES

GND

3

1

Y+

2

Y-

10

SELOE*

SMC_DEBUG_NO

R4651

1 2

5%

1/20W

MF

201

0

SMC_DEBUG_YES

1

R4650

10K

5% 1/16W MF-LF 402

2

SMC_DEBUGPRT_EN_L

SEL=0 Choose SMC SEL=1 Choose USB

SMC_DEBUG_NO

R4652

0

1 2

5%

1/20W

MF

201

CRITICAL

U4600

TPS2557DRB

2

IN_0

3

IN_1

8

FAULT*

4

EN

GND

1

SON

IN

THRM

PAD

9

OUT1 OUT2

ILIM

41

6 7

5

USB_ILIM

R4601

22.1K

1/20W

USB_ILIM_R

R4600

22.1K

1/16W MF-LF

19 91

IN

19 91

IN

1

1% MF

201

2

1

1%

402

2

NO_TEST=TRUE

USB3_EXTA_TX_N

USB3_EXTA_TX_P

NO_TEST=TRUE

1

C4695

10UF

20%

6.3V 2

X5R 603

SIGNAL_MODEL=EMPTY

BEAD-PROBE

BP4606

SM

C4610

1

C4611

1

SM

BP4608

BEAD-PROBE

SIGNAL_MODEL=EMPTY

PP5V_S3_LTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

NO_TEST=TRUE

OUT

USB3_EXTA_RX_N

USB3_EXTA_RX_P

NO_TEST=TRUE

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

19 91

USB_EXTA_MUXED_N

91

USB_EXTA_MUXED_P

91

1 2

16V

10%

X5R-CERM

1 2

16V

10%

X5R-CERM

12

1/20W

GND_VOID=TRUE

15PF

25V

GND_VOID=TRUE

12

1/20W

GND_VOID=TRUE

15PF

25V

5% 0201NP0-CERM

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

BP4605

SM

1

0201

1

0201

SM

BP4607

BEAD-PROBE

SIGNAL_MODEL=EMPTY

C4605

0.01UF

X7R-CERM

1 2

1%

1 2

NP0-CERM 02015%

1 2

1%

1 2

MF

C4613

MF

C4612

20% 16V

0402

R4613

201

R4612

201

1

2

CRITICAL

L4605

FERR-120-OHM-3A

1 2

0603

CRITICAL

L4600

90-OHM-50MA

TCM0605-1

SYM_VER-1

1

2 3

PP5V_S3_LTUSB_A_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

4

USB_LT1_N

91

USB_LT1_P

91

NO_TEST=TRUE

We can add protection to 5V if we want, but leaving NC for now

Place L4605 and L4615 at connector pin

5 4

2 3

IOIONC

NC

6

VBUS

1

GND

D4600

RCLAMP0502N

SLP1210N6

CRITICAL

SIGNAL_MODEL=EMPTY

BEAD-PROBE

BP4602

SM

1

NO_TEST=TRUE

D4610

ESD0P2RF-02LS

TSSLP-2-1

D4612

ESD0P2RF-02LS

TSSLP-2-1

2

1

2

1

BEAD-PROBE

BP4604

SM

1

CRITICALCRITICAL

2

D4611

ESD0P2RF-02LS

TSSLP-2-1

1

CRITICALCRITICAL

2

D4613

ESD0P2RF-02LS

TSSLP-2-1

1

USB3_EXTA_RX_RC_N

97

USB3_EXTA_RX_RC_P

97

USB3_EXTA_TX_C_N

97

USB3_EXTA_TX_C_P

97

1 2 3

4 5 6

7 8 9 10 11 12 13

14 15 16 17 18

514-0804 CRITICAL

J4600

USB3.0-J5

F-RT-TH

VBUS DD+ GND STDA_SSRXSTDA_SSRX+ GND_DRAIN STDA_SSTXSTDA_SSTX+ SHLD SHLD SHLD SHLD

C

B

A

SYNC_MASTER=D2_KEPLER

PAGE TITLE

USB 3.0 CONNECTORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

46 OF 132

SHEET

40 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

D

LPC_AD<0>

7

17 43 82 92

BI

LPC_AD<1>

7

17 43 82 92

BI

LPC_AD<2>

7

17 43 82 92

BI

LPC_AD<3>

7

17 43 82 92

BI

LPC_CLK33M_SMC

25 92

IN

LPC_FRAME_L

7

17 43 82 92

IN

SMC_LRESET_L

25

IN

LPC_SERIRQ

7

17 43

BI

PM_CLKRUN_L

7

18 43

OUT

LPC_PWRDWN_L

7

18 25 43

IN

SMC_RUNTIME_SCI_L

20

OUT

SMC_WAKE_SCI_L

20

OUT

SMBUS_SMC_0_S0_SCL

44 94

BI

SMBUS_SMC_0_S0_SDA

44 94

BI

SMBUS_SMC_1_S0_SCL

44 94

BI

SMBUS_SMC_1_S0_SDA

44 94

BI

SMBUS_SMC_2_S3_SCL

7

44 94

BI

SMBUS_SMC_2_S3_SDA

7

44 94

C

B

BI

44 94

BI

44 94

BI

42

BI

42

BI

7

44

BI

7

44

BI

48

OUT

48

IN

48

OUT

48

IN

50

OUT

8

OUT

60

BI

60

BI

42

IN

42

IN

42

BI

42

OUT

42

IN

42

IN

42

IN

42

IN

42 70

OUT

42 49

IN

42

OUT

42 51

IN

42 60

IN

42

IN

7

18 27 38 70

IN

7

18 27 34 38 40 70

IN

18 70

IN

42 49

IN

7

42 43

IN

7

42 43

OUT

9

91

BI

9

91

BI

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_4_ASF_SCL SMBUS_SMC_4_ASF_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

SMC_FAN_0_CTL SMC_FAN_0_TACH SMC_FAN_1_CTL SMC_FAN_1_TACH TP_SMC_MPM5_LED_PWR TP_SMC_MPM5_LED_CHG

SMC_SYS_KBDLED SMC_T25_EN_L SYS_TDM_ONEWIRE SYS_ONEWIRE HISIDE_ISENSE_OC SMC_ODD_DETECT

CPU_PECI_R SMC_PECI_L

SMC_BIL_BUTTON_L SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_S4_WAKESRC_EN

SMC_LID

ENET_ASF_GPIO SMS_INT_L SMC_BC_ACOK G3_POWERON_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L

SMC_RX_L SMC_TX_L

USB_SMC_N USB_SMC_P

(OD) (OD)

(OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD)

A12

N12 N11 M11

L12

J12

NC NC

B13

LPC0AD0

A13

LPC0AD1

C12

LPC0AD2

D11

LPC0AD3

H12

LPC0CLK

D12

LPC0FRAME*

C13

LPC0RESET*

H13

LPC0SERIRQ

G11

LPC0CLKRUN*

F13

LPC0PD*

F12

LPC0SCI*

B12

PK5

E10

I2C0SCL

D13

I2C0SDA

M4

I2C1SCL

N2

I2C1SDA

N8

I2C2SCL

M8

I2C2SDA

L8

I2C3SCL

K8

I2C3SDA

N7

I2C4SCL

M7

I2C4SDA

N4

I2C5SCL

N3

I2C5SDA

H11

PM6/FAN0PWM0

L13

PM7/FAN0TACH0

C11

PK6/FAN0PWM1 PK7/FAN0TACH1

G3

PN2/FAN0PWM2

D10

PN3/FAN0TACH2

L11

PN4/FAN0PWM3 PN5/FAN0TACH3 PN6/FAN0PWM4 PN7/FAN0TACH4

J4

PH2/FAN0PWM5

J2

PH3/FAN0TACH5

C4

PECI0RX

C6

PECI0TX

M13

PP0/IRQ116 PP1/IRQ117

M5

PP2/IRQ118 PP3/IRQ119

J13

PP4/IRQ120

L5

PP5/IRQ121

D8

PP6/IRQ122

K6

PP7/IRQ123

D4

PQ0/IRQ124

E4

PQ1/IRQ125

F5

PQ2/IRQ126

N5

PQ3/IRQ127

N6

PQ4/IRQ128

K5

PQ5/IRQ129

M6

PQ6/IRQ130

L6

PQ7/IRQ131

L3

U0RX

M1

U0TX

E13

USB0DM

E12

USB0DP

U4900

LM4FSXAH5BB

BGA

(1 OF 2)

OMIT_TABLE

T3CCP1/PJ5/C2T3CCP0/PJ4/C2+

SSI0CLK/PA2 SSI0FSS/PA3

SSI1CLK/PF2 SSI1FSS/PF3

WT0CCP0/PG4 WT0CCP1/PG5

WT2CCP0/PH0 WT2CCP1/PH1

WT3CCP0/PH4 WT3CCP1/PH5 WT4CCP0/PH6 WT4CCP1/PH7

WT5CCP1/PM3

AIN00 AIN01 AIN02 AIN03 AIN04 AIN05 AIN06 AIN07 AIN08 AIN09 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 AIN17 AIN18 AIN19 AIN20 AIN21 AIN22 AIN23

PC5/C1+

SSI0RX/PA4 SSI0TX/PA5

U1RX/B0

U1TX/PB1 T0CCP0/PB6 T0CCP1/PB7

SSI1RX/PF0 SSI1TX/PF1

T1CCP0/PJ0 T1CCP1/PJ1 T2CCP0/PJ2 T2CCP1/PJ3

C0C0+ C1-

PF4 PF5

E2 E1 F2 F1 B3 A3 B4 A4 B5 A5 B6 A6 C1 C2 B1 B2 G2 G1 H1 H2 B7 A7 B8 A8

K2 K1 L2 L1 C5 D5

M2 M3 L4 N1

F11 E11 F4 F3

M9 N9 L10 K10 L9 K9

K7 L7

K3 K4

J3 H4 H3 G4

C9 B9 A9 C8

H10

SMC_ADC0 SMC_ADC1 SMC_ADC2 SMC_ADC3 SMC_ADC4 SMC_ADC5 SMC_ADC6 SMC_ADC7 SMC_ADC8 SMC_ADC9 SMC_ADC10 SMC_ADC11 SMC_ADC12 SMC_ADC13 SMC_ADC14 SMC_ADC15 SMC_ADC16 SMC_ADC17 SMC_ADC18 SMC_ADC19 SMC_ADC20 SMC_ADC21 SMC_ADC22 SMC_ADC23

CPU_PROCHOT_L

SMC_VCCIO_CPU_DIV2

SMC_S5_PWRGD_VIN

SPI_DESCRIPTOR_OVERRIDE_L

(OD)

CPU_CATERR_L

CPU_THRMTRIP_3V3

SMC_PM_G2_EN PM_DSW_PWRGD

SMC_DELAYED_PWRGD

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L

SMC_GFX_THROTTLE_L

SPI_SMC_MISO SPI_SMC_MOSI SPI_SMC_CLK SPI_SMC_CS_L

PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L

SMC_GFX_OVERTEMP

ALL_SYS_PWRGD

SMC_THRMTRIP

(OD) (OD)

SMC_ADAPTER_EN

SMC_OOB1_RX_L SMC_OOB1_TX_L

IR_RX_OUT_RC

SMC_BATLOW_L

SMC_PROCHOT

SMC_SYS_LED

S5_PWRGD

PM_PWRBTN_L PM_SYSRST_L MEM_EVENT_L

BDV_BKL_PWM

42

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN

OUT

IN IN

OUT OUT OUT OUT

IN OUT OUT

BI

IN OUT OUT OUT

IN

OUT

IN

IN OUT

OUT OUT

BI

OUT

IN OUT

OUT

42

11 42 65 89

25 42

11 89

42

42 70

18

37 42 70

42

40 42

42

78

42

70

18 24 70

40

42 78

24 70

42

18 24

18 25

42

18 42 70

39

39 42

42

42 70

=PP3V3_S5_SMC

8

42 78

C4902

X5R-CERM

NO STUFF

1

C4910

1UF

10% 25V

2

X5R 402

1UF

0603-1

12

L4901

30-OHM-1.7A

1 2

C4905

0.1UF

20% 10V CERM 402

C4909

0.1UF

20% 10V CERM 402

1

2

C4906

0.1UF

20% 10V CERM 402

1

R4902

1M

5% 1/20W MF 201

SMC_RESET_L

7

42 43 61

IN

WIFI_EVENT_L

7

34 42

BI

NC_SMC_HIB_L

7

SMC_CLK32K

42

IN

NC_SMC_XOSC1

7

SMC_EXTAL

42

SMC_XTAL

2

(OD)

SMC_WAKE_L

G10 C10

B11 N13 M12

M10

N10

G12

G13

1

20% 10V

2

C4903

2

1

C4907

2

0.1UF

20% 10V CERM 402

0.1UF

20% 10V CERM 402

1

2

1

2

C4904

0.1UF

20% 10V CERM 402

C4908

0.1UF

20% 10V CERM 402

1

2

1

2

K12

D7 E6 E8 E9

F10

J7 J9

J10

1

C4911

1UF

10% 25V

2

X5R 402

1

C4912

1UF

10% 25V

2

X5R 402

1

C4913

2

0.1UF

20% 10V CERM 402

1

C4914

0.1UF

20% 10V

2

CERM 402

1

2

C4915

0.1UF

20% 10V CERM 402

1

C4916

0.1UF

20% 10V

2

CERM 402

1

C4917

0.1UF

20% 10V

2

CERM 402

PP1V2_S5_SMC_VDDC

42

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.2V

K13

J1 J6

D6

0402

U4900

LM4FSXAH5BB

(2 OF 2)

RST*

OMIT_TABLE

PK4/RTCCLK WAKE* HIB*

XOSC0 XOSC1

OSC0 OSC1

VBAT

VDD

VDDC

BGA

SWCLK/TCK SWDIO/TMS

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=3.3V

A10 A11

SWO/TDO

B10

TDI

A2

NC

D3

VDDA

D2

VREFA+

D1

VREFA-

C3

42 45 46 99

E3

GNDA

A1 C7 D9 E5 F9 H5 H9

GND

J5 J8 J11 K11

NC

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

1

C4901

0.1UF

20% 10V

2

CERM 402

SMC_TCK SMC_TMS SMC_TDO SMC_TDI

XW4900

PLACE_NEAR=U4900.A1:4MM

1

C4920

0.01UF

10% 10V

2

X5R-CERM 0201

D

7

42 43

7

42 43

7

42 43

7

42 43

7

42 42

SM

12

1

C4921

1UF

10%

6.3V

2

CERM 402

C

B

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

A

If SMS interrupt is not used, pull up to SMC rail.

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

SMC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

49 OF 132

SHEET

41 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

CPU_PROCHOT_L

BI

PM_THRMTRIP_L_R

OUT

99

IN

R5058

3.3K

1 2

5%

1/20W

MF

201

8

OUT

NC_ENET_ASF_GPIO

MAKE_BASE=TRUE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NC_MEM_EVENT_L

MAKE_BASE=TRUE

NC_SMC_ODD_DETECT

MAKE_BASE=TRUE

NC_IR_RX_OUT_RC

MAKE_BASE=TRUE

3

D

S G

4

PM_THRMTRIP_L

8

25 42

18

6

D

S G

1

3

D

S G

4

Q5057

SSM6N15FEAPE

SOT563

5

SMC_GFX_OVERTEMP

OUT

7

41

Q5059

SSM6N15FEAPE

SOT563

2

SMC_PROCHOT

Q5059

SSM6N15FEAPE

SOT563

5

SMC_THRMTRIP

11 20 89

IN

From SMC

41 78

IN

SMC12 PECI SUPPORT

1

G S

CPU_PECI_R

=PPVCCIO_S0_SMC

3

D

2

1

R5031

330

5% 1/16W MF-LF 402

2

R5034

1 2

43

5% 1/16W MF-LF

402

SMC_PECI_L

SSM3K15AMFVAPE

R5032

0

1 2

5% 1/16W MF-LF

402

41

IN

CRITICAL

Q5030

VESM

SMC_PECI_L_R

OMIT

1

R5033

NOSTUFF

NONE NONE NONE 402

2

41 11 20 89

OUT

To SMC

SMC12 SPI SUPPORT

41 42

IN

OUT

R5022

SPI_SMC_MOSI SPI_MLB_MOSI

IN

SPI_SMC_CLK SPI_MLB_CLK

IN

SPI_SMC_CS_L SPI_MLB_CS_L

IN

SMC_OOB1_TX_L

39 41

SMC_PME_S4_DARK_L

41 42

SMC_ONOFF_L

41 42 49

G3_POWERON_L

41

SMC_LID

41 42 49

SMC_TX_L

7

41 43

SMC_RX_L

7

41 43

SMC_DEBUGPRT_TX_L

40 41

SMC_DEBUGPRT_RX_L

40 41

SMC_TMS

7

41 43

SMC_TDO

7

41 43

SMC_TDI

7

41 43

SMC_TCK

7

41 43

SMC_BIL_BUTTON_L

41

SMC_BC_ACOK

41 42 60

SMC_S5_PWRGD_VIN

41

SMS_INT_L

41 51

CPU_THRMTRIP_3V3

41 42

SPI_DESCRIPTOR_OVERRIDE_L

25 41

SMC_ROMBOOT

7

43

SMC_THRMTRIP

41 42

SMC_DELAYED_PWRGD

37 41 70

SMC_PM_G2_EN

41 70

SMC_ADAPTER_EN

18 41 70

SMC_S4_WAKESRC_EN

41 70

WIFI_EVENT_L

7

34 41

1 2

R5024

1 2

1

R5088

1K

5% 1/20W MF 201

2

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

33

5% 1/16W MF-LF

402

33

5% 1/16W MF-LF

402

NOSTUFF

R5086

R5091 R5098 R5085 R5090

R5089

R

R5021

12

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U6100.5:1MM

R5023

33

1 2

PLACE_NEAR=U6100.6:1MM

5% 1/16W MF-LF

402

PLACE_NEAR=U6100.1:1MM

10K

100K 100K

10K

100K

10K

100K 100K

10K 10K

100K

10K

100K

10K

100K

10K 10K 10K 10K

10K 470K 100K

10K 100K

10K

1 2

1 2 1 2

34

1 2

R5068 R5069 R5070 R5072 R5071 R5073 R5074 R5075 R5076 R5077 R5078 R5079 R5080 R5081 R5087 R5092 R5093 R5094 R5095

SMC Support

Apple Inc.

8

25 42

NO STUFF

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

1 2

PP3V3_WLAN

7

=PP3V3_S4_SMC

5%

8

42

CPU_PECI

From/To CPU/PCH

SPI_MLB_MISOSPI_SMC_MISO

=PP3V3_S5_SMC

8

41 42 78

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W 1/20W

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

MF

1/20W

MF5%

1/20W

MF5%

MF

1/20W

MF

1/20W

MF

1/20W

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

50 OF 132

SHEET

42 OF 99

124578

BI

43 52 41

IN

43 52 41

OUT

43 52 41

OUT

43 52 41

OUT

MF MF

MF5%

MF MF5%

MF

MF MF

MF5% MF5%

MF

MF MF

MF

MF MF

MF

MF MF

201

201 201

201

4.18.0

D

C

201 201

201

201 201

201

201 201

201

201 201

201

201 201

201

201 201

B

A

SIZE

D

SMC Reset "Button", Supervisor & AVREF Supply

R5027

47

=PP3V3_S5_SMC

8

41

42 78

D

49

41 42 49

C

B

A

PART NUMBER

1 2

1/16W MF-LF

Mac Mini: 5V

Mobiles: 3.42V

SMC_TPAD_RST_L

IN

SMC_ONOFF_L

IN

SMC_MANUAL_RST_L OMIT

1

R5001

0

5% 1/10W MF-LF 603

2

SILK_PART=SMC_RST

5%

402

PP3V42_G3H_SMC_SPVSR

1

C5027

4.7UF

20%

6.3V

2

X5R 402

=PPVIN_S5_SMCVREF

8

C5020

0.47UF

10%

6.3V

CERM-X5R

402

1

C5001

0.01UF

10% 16V

2

X7R-CERM

0402

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.42V

1

2

6

MR1*

7

MR2*

4

DELAY

1

V+

U5010

VREF-3.3V-VDET-3.0V

DFN

(IPU)

SN0903048

(IPU)

CRITICAL

GND

2

3

VIN

RESET*

REFOUT

THRM

PAD

9

PLACEMENT_NOTE=Place R5001 on BOTTOM side

MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard.

NOTE: Internal pull-ups are to VIN, not V+.

Debug Power "Buttons"

PLACE_SIDE=TOP

R5016

SILK_PART=PWR_BTN

OMIT

1/10W MF-LF

1

0

5%

603

2

SMC_ONOFF_L

OMIT

1

R5015

0

PLACE_SIDE=BOTTOM 5% 1/10W MF-LF 603

2

SILK_PART=PWR_BTN

41 42 49

OUT

SMC Crystal Circuit

41

SMC_XTAL

SMC_EXTAL

1 2

1%

1/20W

MF

201

1

2

SMC_XTAL_R

CRITICAL

Y5010

3.2X2.5MM-SM-1

12.000MHZ-30PPM-10PF

C5010

12PF

5% 50V C0G-CERM 0402

1 3

2 4

NC

1

2

R5010

2.49K

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

Hall Effect pads

APN: 998-3029

OMIT_TABLE

HALL-SENSOR-MLB-PADS-K99

J5050

SM

1

NC NC

2 3 4 5

QTY

DESCRIPTION

SUBASSY,PCBA HALL EFFECT,K99

8 7 6

=PP3V42_S3_HALL

7

NCNC

SMC_LID_R

R5050

0

1 2

5% 1/16W MF-LF

402

REFERENCE DES

1

R5000

100K

5% 1/16W MF-LF

402

2

R5028

0

1 2

5%

1/20W

MF

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

C5026

0.01UF

10% 16V X7R-CERM 0402

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

201

PP1V2_S5_SMC_VDDC

41

SMC_ADC23

41 42

5

8

C5025

10uF

6.3V

SMC_RESET_R_L

1

20%

2

X5R 603

1

2

ENG PACKAGE REQUIRES 1.2V ON SMC_ADC23 PIN

=PPVCCIO_S0_SMC

8

42

SMC_VCCIO_CPU_DIV2

41

C5011

12PF

5% 50V C0G-CERM 0402

1

C5050

0.001UF

10% 50V

2

X7R-CERM 0402

HDMI HPD ESD PROTECTION

41

OUT

SMC_LID

41 42 49

CRITICAL

CRITICAL1 J5050607-6811

=CHGR_ACOK

45 61

HISIDE_ISENSE_OC

41

SMC_ADC0

41

SMC_ADC1

41

SMC_ADC2

SMC_RESET_L

7

41

NOSTUFF

C5028

1000PF

25V

NP0-C0G

402

41 45 46 99

SMC_PACKAGE:ENG

1

R5099

0

5% 1/16W MF-LF 402

2

1

R5097

100K

1% 1/20W MF 201

2

1

R5096

100K

1% 1/20W MF 201

2

OUT

1

5%

2

7

41 43 61

18

41

41 42

41

41 42

IN

SMC_ADC3

SMC_ADC4

SMC_ADC5

SMC_ADC6

SMC_ADC7

SMC_ADC8

SMC_ADC9

SMC_ADC10

SMC_ADC11

SMC_ADC12

SMC_ADC13

SMC_ADC14

SMC_ADC15

SMC_ADC16

SMC_ADC17

SMC_ADC18

SMC_ADC19

SMC_ADC20

SMC_ADC21

SMC_ADC22

SMC_ADC23

SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_4_ASF_SDA

BDV_BKL_PWM

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

PM_CLK32K_SUSCLK_R

PLACE_NEAR=U1800.N14:5.1mm

Inversion now taking place on RIO

=PP3V3_S4_SMC

1

R5059

100K

5% 1/20W MF 201

R5057

SMC_DP_HPD_L

1 2

1/20W

1K for ESD protection

2

1K

5% MF

201

HDMI_HPD_L

BOM OPTION

1 2

8

25 42

7

38 82

IN

=PP3V3_S5_SMCBATLOW

8

SMC_BATLOW_L

41 70

IN

SMC_BC_ACOK

MAKE_BASE=TRUE

NC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_CHGR_BMON_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

SMC_P1V5MEM_ISENSE

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUE

SMC_GFX_VSENSE

MAKE_BASE=TRUE

SMC_CPU_SA_ISENSE

MAKE_BASE=TRUE

SMC_GPU_CORE_VSENSE

MAKE_BASE=TRUE

SMC_GPU_CORE_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_VSENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_CPU_GFX_ISENSE

MAKE_BASE=TRUE

SMC_GPU_P1V35_ISENSE

MAKE_BASE=TRUE

SMC_CPU_SA_VSENSE

MAKE_BASE=TRUE

SMC_PCH_CORE_ISENSE

MAKE_BASE=TRUE

SMC_X29_ISENSE

MAKE_BASE=TRUE

SMC_TBT_ISENSE_R

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_BDV_BKL_PWM

MAKE_BASE=TRUE

SDCONN_STATE_CHANGE_SMC

=TBT_WAKE_L

R5012

22

SMC_CLK32K

5%

1/20W

MF

201

IN

=PSOC_WAKE_L

=BT_WAKE_L

49 41

34

41 42 60

45

46

45

46

45

99

46

45

99

46

99

7

25

18 35

CPU_THRMTRIP_3V3

41 42

OUT

BATLOW# ISOLATION

1

R5040

100K

1/20W

5%

MF

201

2

Q5040

SSM3K15FV

SOD-VESM-HF

3

D

R5041

1 2

ENET_ASF_GPIO

41

SMC_SYS_LED

41

MEM_EVENT_L

41

SMC_ODD_DETECT

41

IR_RX_OUT_RC

41

ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD

SMC_PACKAGE:PROD

R5013

0

1 2

1/16W MF-LF

41

OUT

CRITICAL

MMBT3904LP-7

5%

402

Q5058

DFN1006-3

SMC_TBT_ISENSE

3

2

1

R5082

100K

5% 1/20W MF 201

2

=PP3V3_SUS_SMC

1

GS

Internal 20K pull-up on PM_BATLOW_L in PCH.

PM_BATLOW_L

2

0

5%

NOSTUFF

1/16W MF-LF

402

11 41 65 89

20

PM_THRMTRIP_B_L

1

=PP3V3_S4_SMC

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

6 3

8 7 6 5 4 3

12

D

=PP3V3_S5_LPCPLUS

8

=PP5V_S0_LPCPLUS

8

LPC_AD<0>

7

17 41 82 92

BI

LPC_AD<1>

7

17 41 82 92

BI

SPI_ALT_MOSI

7

43

IN

SPI_ALT_MISO

7

43

OUT

LPC_FRAME_L

7

17 41 82 92

IN

PM_CLKRUN_L

7

18 41

OUT

SMC_TMS

7

41 42

OUT

LPCPLUS_RESET_L

7

25

IN

SMC_TDO

7

41 42

OUT

TP_SMC_TRST_L

7

TP_SMC_MD1

7

SMC_TX_L

7

41 42

IN

C

LPC+SPI Connector

CRITICAL

LPCPLUS_CONN:YES

J5100

55909-0374

M-ST-SM

31

32

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

33

34

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SPIROM_USE_MLB SPI_ALT_CLK

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L LPCPLUS_GPIO

7

25 92

IN

7

17 41 82 92

BI

7

17 41 82 92

BI

7

20 52

BI

7

43

IN

7

43

IN

7

17 41

BI

7

18 25 41

IN

7

41 42

OUT

7

41 42

OUT

7

41 42 61

OUT

7

42

OUT

7

41 42

OUT

7

20

BI

D

C

516S0573

SPI Bus Series Termination

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK

33

5%

PLACE_NEAR=R5125.2:5mm

1/16W MF-LF

402

SPI_ALT_CS_L

PLACE_NEAR=J5100.14:5mm PLACE_NEAR=J5100.12:5mm PLACE_NEAR=J5100.9:5mm PLACE_NEAR=J5100.11:5mm

SPI_MLB_CS_L

SPI_MLB_CLK

33

5%

PLACE_NEAR=R5127.2:5mm

1/16W MF-LF

402

LPCPLUS_R:YES

1

R5126

33

5% 1/16W MF-LF 402

2

R5121

1 2

LPCPLUS_R:YES

1

R5128

12

5% 1/16W MF-LF 402

2

SPI_CS0_R_L

17 92

IN

B

17 92

PLACE_NEAR=U1800.AY1:5mm

17 92

PLACE_NEAR=U1800.BA2:5mm

SPI_CLK_R

IN

SPI_MOSI_R

IN

SPI_MISO SPI_MLB_MISO

OUT

PLACE_NEAR=U1800.AV3:5mm

R5112

15

1 2

5% 1/16W MF-LF

402

R5111

15

1 2

5% 1/16W MF-LF

402

R5110

15

1 2

5% 1/16W MF-LF

402

SPI_CS0_L

92

SPI_CLK

92

SPI_MOSI SPI_MLB_MOSI

92

R5123

1 2

60.4

1% 1/16W MF-LF

402

LPCPLUS_R:YES

1

R5127

33

5% 1/16W MF-LF 402

2

R5122

1 2

PLACE_NEAR=U6100.2:5mm

33

1/16W MF-LF

402

5%

LPCPLUS_R:YES

1

R5125

33

5% 1/16W MF-LF 402

2

R5120

1 2

PLACE_NEAR=R5126.2:5mm

7

43

7

43

7

43

7

43

42 52

OUT

42 52

OUT

42 52

OUT

42 52 17 92

IN

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

LPC+SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

51 OF 132

SHEET

43 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH SMBus "0" Connections

=PP3V3_S0_SMBUS_PCH

8

44

1

Panther Point

U1800

(MASTER)

SMBUS_PCH_CLK

17 92

D

MAKE_BASE=TRUE

SMBUS_PCH_DATA

17 92

MAKE_BASE=TRUE

R5200

1/16W MF-LF

VRef DACs

(Write: 0x98 Read: 0x99)

U3300

=I2C_VREFDACS_SCL

33

=I2C_VREFDACS_SDA

33

Margin Control

(Write: 0x30 Read: 0x31)

U3301

=I2C_PCA9557D_SCL

33

=I2C_PCA9557D_SDA

33

Audio

U6751 & U6750

Mikey (WRITE: 0X72 READ: 0X73)

C

China HS (WRITE: 0X76 READ: 0X77)

=I2C_MIKEY_SCL

58

=I2C_MIKEY_SDA

58

XDP Connectors

J2500 & J2550

(MASTER)

=SMBUS_XDP_SCL

24

=SMBUS_XDP_SDA

24

R5201

1K

5%

1/16W MF-LF 402

402

2

TBT

U3600

(WRITE: 0xFE READ: 0xFF)

=I2C_TBTRTR_SCL

=I2C_TBTRTR_SDA

35

SMC

U4900

(MASTER) SMB_0_S0_CLK

SMB_0_S0_DATA

SMC

U4900

(MASTER)

SMB_2_S3_CLK

(WRITE: 0X30/31 READ: 0X32/33)

51

SMC "0" SMBus Connections

=PP3V3_S0_SMBUS_SMC_0_S0

8

R5250

4.7K

1/16W MF-LF

94

SMBUS_SMC_0_S0_SCL

41

MAKE_BASE=TRUE

94

SMBUS_SMC_0_S0_SDA

41

MAKE_BASE=TRUE

SMC "2" SMBUS CONNECTIONS

NOTE: SMC RMT bus remains powered and may be active in S3 state

=PP3V3_S3_SMBUS_SMC_2_S3

8

R5270

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMS

U5920

=I2C_SMC_SMS_SCL

=I2C_SMC_SMS_SDA

1

5%

402

2

1

1K

5% 5% 1/16W MF-LF

402

2

1

R5251

4.7K

5% 1/16W MF-LF 402

2

1

R5271

1K

1/16W MF-LF 402

2

GPU Temp (Ext)

EMC1414-A: U5550

(Write: 0x98 Read: 0x99) =SMBUS_GPUTHMSNS_SCL

=SMBUS_GPUTHMSNS_SDA

GPU Temp (Int)

GK107: U8000

(Write: 0x9E Read: 0x9F)

VBIOS may overwrite as 0x82/0x83

GPU_SMB_CLK_R

GPU_SMB_DAT_R

Trackpad

(Write: 0x90 Read: 0x91) =I2C_TPAD_SCL

=I2C_TPAD_SDASMB_2_S3_DATA

=I2C_ALS_SCL

=I2C_ALS_SDA

J5800

J3502

ALS

(Write: 0x72 Read: 0x73)

GYRO

(WRITE: 0XD0 READ: 0XD1)

U5940

=I2C_SMC_GYRO_SCL

=I2C_SMC_GYRO_SDA

SMC

U4900

(MASTER)

47

78

SMB_5_CLK

SMB_5_DATA

SMC

U4900

49

34

51

(MASTER) SMB_3_CLK

SMB_3_DATA

SMC "5" SMBUS CONNECTIONS

=PP3V42_G3H_SMBUS_SMC_5

8

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

SMC "3" SMBUS CONNECTIONS

=PP3V3_S3_SMBUS_SMC_3

8

94

SMBUS_SMC_3_SCL

41

MAKE_BASE=TRUE

94

SMBUS_SMC_3_SDA

41

MAKE_BASE=TRUE

R5280

2.0K

1/16W MF-LF

R5290

4.7K

1/16W MF-LF

1

R5281

2.0K

5%

5% 1/16W MF-LF

402

2

Battery Charger

ISL6258 - U7000

(Write: 0x12 Read: 0x13) =SMBUS_CHGR_SCL

=SMBUS_CHGR_SDA

61

D

Battery

(Write: 0x16 Read: 0x17) =SMBUS_BATT_SCL

=SMBUS_BATT_SDA

The bus formerly known as "Battery B"

1

R5291

4.7K

5%

1/16W MF-LF 402

402

2

DEBUG SENSOR ADC A

(Write: 0x10 Read: 0x11) =I2C_SMC_ADCS_SCL

=I2C_SMC_ADCS_SDA

J6950

UD100

60

98

C

B

Panther Point

SML_PCH_0_CLK

17 92

MAKE_BASE=TRUE

SML_PCH_0_DATA

17 92

MAKE_BASE=TRUE

Panther Point

A

(Write: 0x88 Read: 0x89)

SML_PCH_1_CLK

17 92

MAKE_BASE=TRUE

SML_PCH_1_DATA

17 92

MAKE_BASE=TRUE

SMLink 1 is slave port to access PCH & CPU via PECI.

U1800

(MASTER)

U1800

PCH "SMLink 0" Connections

=PP3V3_S0_SMBUS_PCH

8

44

1

8.2K

1/16W MF-LF

1

R5211

8.2K

5%

5% 1/16W MF-LF

402

2

R5210

PCH "SMLink 1" Connections

=PP3V3_S0_SMBUS_PCH

8

44

NO STUFF

R5220

8.2K

1/16W MF-LF

NO STUFF

1

R5221

8.2K

5%

1/16W MF-LF 402

402

2

R5223

0

5% 1/16W MF-LF

402

1 2

R5222

0

5% 1/16W MF-LF

402

SMC "1" SMBUS CONNECTIONS

=PP3V3_S0_SMBUS_SMC_1_S0

8

1

SMC

U4900

(MASTER) SMB_1_S0_CLK

SMB_1_S0_DATA

94

SMBUS_SMC_1_S0_SCL

41

MAKE_BASE=TRUE

94

SMBUS_SMC_1_S0_SDA

41

MAKE_BASE=TRUE

R5260

1/16W MF-LF

R5261

1K

5%

402

2

CPU/DDR3/PCH/AIRFLOW TEMP

5% 1/16W MF-LF 402

EMC1414-A: U5570

(Write: 0x98 Read: 0x99) =I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

47

X29 TEMP

TMP105: U5523

(WRITE: 0X92 READ: 0X93) =I2C_X29THMSNS_SCL

=I2C_X29THMSNS_SDA

47

6 3

8

44

DPMUX IC

U9100

(MASTER)

=I2C_DPMUX_A_SCL

82

=I2C_DPMUX_A_SDA

82

8

44

DPMUX IC

U9100

(MASTER)

=I2C_DPMUX_UC_SCL

82

=I2C_DPMUX_UC_SDA

82

=PP3V3_S0_DPMUXI2C

R5236

R5234

4.7K

MF-LF

402

4.7K

1/20W

1

5%

2

HDMI REDRIVER SMBUS CONNECTION

1

R5237

4.7K

5%

5% 1/20W

MF

201

MF 201

2

I2C_DPMUX_A_SCL

7

MAKE_BASE=TRUE

I2C_DPMUX_A_SDA

7

MAKE_BASE=TRUE

LED BACKLIGHT SMBUS CONNECTION

1

R5235

4.7K

5% 1/16W1/16W MF-LF 402

2

I2C_DPMUX_UC_SCL

MAKE_BASE=TRUE

I2C_DPMUX_UC_SDA

MAKE_BASE=TRUE

SYNC_MASTER=D2_KEPLER

PAGE TITLE

SMBus Connections

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

HDMI Redriver (on RIO)

J4410 -> U9700

(WRITE: 0xCC READ: 0xCD)

=I2C_HDMIRDRV_SCL

=I2C_HDMIRDRV_SDA

LED BACKLIGHT

U9700

(WRITE: 0x58 READ: 0x59)

=I2C_BKL_1_SCL

=I2C_BKL_1_SDA

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

52 OF 132

SHEET

44 OF 99

124578

38

86

4.18.0

SIZE

B

A

D

8 7 6 5 4 3

PBUS Voltage Sense Enable & Filter

Enables PBUS VSense divider when in S0.

=PBUSVSENS_EN

70

IN

=PPBUS_S0_VSENSE

8

R5301

100K

1/16W MF-LF

1

1%

402

2

CRITICAL

Q5300

NTUD3169CZ

SOT-963

N-CHANNEL

D

G

2

1

5

4

PBUSVSENS_EN_L_DIV

G

P-CHANNEL

S

D

S

6

PBUSVSENS_EN_L

3

PBUS_S0_VSENSE

1

R5302

100K

1% 1/16W MF-LF

402

2

R5303

R5304

PLACE_NEAR=U4900.L8:5MM

27.4K

1/16W MF-LF

5.49K

1/16W MF-LF

1

1%

402

2

1

1%

402

2

PLACE_NEAR=U4900.L8:5MM

RTHEVENIN = 4573 Ohms

SMC_PBUS_VSENSE

PLACE_NEAR=U4900.L8:5MM

1

C5304

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC Key VP0R

SMC_ADC5

42

OUT

41 42 45 46 99

GFXIMVP6_IMON

80

IN

EDP:50A

Vimon=3x50A*(0.2/R8915)*R8912=1V

GPU VCore Load Side Current Sense / Filter

=PP3V3_S0_ISNS

8

45 98

99

SENSOR_NONPROD:Y

CRITICAL

U5310

OPA2333

8

GPUVCORE_INV

SENSOR_NONPROD:Y

1

R5309

499K

1% 1/16W MF-LF 402

2

3

2

SIGNAL_MODEL=EMPTY

V+ V-

THRM

4

9

SENSOR_NONPROD:Y

R5307

1M

1 2

1% 1/16W MF-LF

402

DFN

1

GPUVCORE_IOUT

Gain: 3.004x

PLACE_NEAR=U4900.N11:5mm

SENSOR_NONPROD:Y

CRITICAL

1

C5310

0.1UF

20% 10V

2

CERM 402

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.N11:5mm

R5308

4.53K

1 2

1%

1/20W

MF

201

NOSTUFF

R5310

4.53K

1 2

1/20W

201

12

1%

MF

SMC Key IG0C

SMC_GPU_CORE_ISENSE

SENSOR_NONPROD:Y

1

C5308

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

SMC_ADC15

PLACE_NEAR=U4900.N11:5mm

42

OUT

D

DC-In Voltage Sense Enable & Filter

=CHGR_ACOK NOSTUFF

1

R5315

0

Enables DC-In VSense

5%

divider when AC present.

1/20W MF 201

2

C

1

R5316

0

Enables DC-In VSense

5% 1/20W

divider when SUS present.

MF 201

2

PM_SUS_EN

=PPDCIN_S5_VSENSE

8

42 61

IN

DCINVSENS_EN

70

IN

1

R5311

100K

1% 1/16W MF-LF

402

2

CRITICAL

Q5310

NTUD3169CZ

SOT-963

N-CHANNEL

D

G

2

1

5

4

PDCINVSENS_EN_L_DIV

G

P-CHANNEL

S

D

S

6

DCINVSENS_EN_L

3

DCIN_S5_VSENSE

1

R5312

100K

1% 1/16W MF-LF

402

2

R5313

30.9K

PLACE_NEAR=U4900.N9:5MM

R5314

5.36K

1

PLACE_NEAR=U4900.N9:5MM

1%

1/16W

Divider set for Vin max of 22.32V

MF-LF

RTHEVENIN = 4567 Ohms

402

2

SMC_DCIN_VSENSE

PLACE_NEAR=U4900.N9:5MM

1

C5314

0.22UF

1%

2

20%

6.3V

2

X5R 402

GND_SMC_AVSS

1/16W MF-LF

402

SMC KEY VD0R

SMC_ADC3

42

OUT

41 42 45 46 99

CPU Vcore Voltage Sense / Filter

SMC Key VC0C

OUT

SMC_ADC0

42

=PPVCORE_S0_CPU

8

13 15 98

B

XW5320

SM

1 2

PLACE_NEAR=R7510.2:5 MM

PLACE_NEAR=U4900.N10:5MM

CPUVSENSE_IN

R5320

4.53K

1 2

1% 1/16W MF-LF

402

SMC_CPU_VSENSE

PLACE_NEAR=U4900.N10:5MM

1

C5320

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

41 42 45 46 99

EDP:21.329A

Vi=Voltage across R7640=0.02139V

CPUVCCIOS0_CS_P

67 96

IN

CPUVCCIOS0_CS_N

67 96

IN

EDP:6A

Vi=Voltage across R7140=0.006V

VCCSAS0_CS_P

62 96

IN

VCCSAS0_CS_N

62 96

IN

SENSOR_NONPROD:Y

R5324

6.49K

1 2

=PP3V3_S0_ISNS

8

45 98 99

R5364

1.82K

1 2

CPU 1.05V VCCIO Current Sense / Filter

SENSOR_NONPROD:Y

R5323

6.49K

1 2

1% 1/16W MF-LF

402

1/16W MF-LF

1%

402

96

CPUVCCIOISNS_R_P

96

CPUVCCIOISNS_R_N

SENSOR_NONPROD:Y

1

R5325

1M

1% 1/16W MF-LF 402

2

5

6

SENSOR_NONPROD:Y

THRM

9

NC

R5326

1M

1 2

1% 1/16W MF-LF

402

SENSOR_NONPROD:Y

CRITICAL

U5310

OPA2333

8

DFN

V+

7

V-

4

NC NC

SIGNAL_MODEL=EMPTY

CPU SA Current Sense / Filter

CRITICAL

U5360

OPA2333

8

DFN

V+

1

V-

THRM

4

9

R5366

1M

1 2

1% 1/16W MF-LF

402

SIGNAL_MODEL=EMPTY

1 2

1% 1/16W MF-LF

402

R5363

1.82K

1% 1/16W MF-LF

402

96

VCCSAISNS_R_P

96

VCCSAISNS_R_N

1

R5365

1M

2

1% 1/16W MF-LF 402

3

2

ISENSE_CPUVCCIO_IOUT

Gain: 154x

ISENSE_SA_IOUT

GAIN:549X

PLACE_NEAR=U4900.L12:5mm

SENSOR_NONPROD:Y

R5327

4.53K

1 2

1% 1/16W MF-LF

402

1

C5360

0.1UF

20% 10V

2

X7R-CERM 0402

PLACE_NEAR=U4900.M10:5mm

R5367

4.53K

1 2

1% 1/16W MF-LF

402

SMC_CPUVCCIO_ISENSE

SENSOR_NONPROD:Y

1

C5327

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC_CPU_SA_ISENSE

1

C5367

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC Key IC1C

SMC_ADC11

PLACE_NEAR=U4900.L12:5mm

41 42 45 46 99

SMC Key IC2C

PLACE_NEAR=U4900.M10:5mm

41 42 45 46 99

OUT

SMC_ADC13

42

OUT

42

C

B

GFX Vcore Voltage Sense / Filter

=PPVCORE_S0_AXG_REG

8

66

XW5330

SM

1 2

PLACE_NEAR=R7550.2:5 MM

GFXVSENSE_IN

PLACE_NEAR=U4900.N12:5MM

R5330

4.53K

1 2

1% 1/16W MF-LF

402

SMC_GFX_VSENSE

PLACE_NEAR=U4900.N12:5MM

1

C5330

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

GPU Vcore Voltage Sense / Filter

A

=PPVCORE_GPU_REG

8

XW5335

SM

1 2

PLACE_NEAR=R8940.1:5 MM

GPUVSENSE_IN

PLACE_NEAR=U4900.L10:5MM

R5335

4.53K

1 2

1% 1/16W MF-LF

402

SMC_GPU_CORE_VSENSE

PLACE_NEAR=U4900.L10:5MM

1

C5335

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC Key VN0C

SMC_ADC12

OUT

41 42 45 46 99

SMC KEY VG0C

SMC_ADC14

OUT

41 42 45 46 99

PART NUMBER

42

116S0114

117S0008

QTY

1

DDR3 1.5V DRAM ONLY CURRENT SENSE / FILTER

EDP CURRENT:8A

=PPVIN_S3_MEM_ISNS_R

8

IN

42

=PPVIN_S3_MEM_ISNS

8

OUT

R5360

0.003

CRITICAL

4

0612

MF 1W 1%

123

ISNS_1V5_MEM_P

96

ISNS_1V5_MEM_N

96

R5373

7.32K

1 2

1% 1/16W MF-LF

402

R5374

7.32K

1 2

1% 1/16W MF-LF

402

ISNS_1V5_MEM_R_P

96

ISNS_1V5_MEM_R_N

96

1

R5375

1M

1% 1/16W MF-LF 402

2

5

6

8

V+ V-

THRM

4

9

NC

R5376

1M

1 2

1% 1/16W MF-LF

SIGNAL_MODEL=EMPTY

402

Gain: 182x

CRITICAL

U5360

OPA2333

DFN

7

NC NC

ISENSE_P1V5MEM_IOUT

GAIN:136.6X

6 3

DESCRIPTION

RES,MTL FILM,100K,5,1/16W,0402,SMD,LF

RES,MF,1/20W,100K OHM,5,0201,SMD

PLACE_NEAR=U4900.N13:5mm

R5377

4.53K

1 2

1% 1/16W MF-LF

402

REFERENCE DES

SMC KEY IM0C

SMC_ADC10

SMC_P1V5MEM_ISENSE

1

C5377

PLACE_NEAR=U4900.N13:5mm

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

41 42 45 46 99

CRITICAL

C5327

C5308

42

OUT

SYNC_MASTER=D2_SEAN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

BOM OPTION

SENSOR_NONPROD:N

SYNC_DATE=03/05/2012

Voltage & Load Side Current Sensing

Apple Inc.

R

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

53 OF 132

SHEET

45 OF 99

4.18.0

SIZE

A

D

124578

8 7 6 5 4 3

12

COMPUTING High Side Current Sense / Filter

=PP3V3_S0_HS_ISNS

8

46

C5401

1

2

6

HS_COMPUTING_IOUT

1

0.1UF

20% 10V CERM 402

PLACE_NEAR=U4900.N8:5MM

R5403

4.53K

1 2

1% 1/16W MF-LF

402

EDP Current:20.1A

=PPVIN_S5_HS_COMPUTING_ISNS

8

OUT

R5400

4

0612

ISNS_HS_COMPUTING_N

96

MF 1W

D

Power Drop across R5400 at EDP becomes 1.21W

=PPVIN_S5_HS_COMPUTING_ISNS_R

8

IN

0.003

CRITICAL

1%

ISNS_HS_COMPUTING_P

96

123

5

4

Gain:50x

IN-

3 V+

U5400

INA213

SC70

CRITICAL

GND

2

OUT

REFIN+

SMC Key IC0R SMC_ADC8

SMC_CPU_HI_ISENSE

PLACE_NEAR=U4900.N8:5MM

C5403

1

0.22UF

20%

6.3V X5R

2

402

GND_SMC_AVSS

42

OUT

41 42 45 46 99

GRAPHICS High Side Current Sense / Filter

=PP3V3_S0_HS_ISNS

8

46

C5411

1

0.1UF

20%

EDP Current:4.9A

=PPVIN_S5_HS_GPU_ISNS

8

OUT

=PPVIN_S5_HS_GPU_ISNS_R

8

IN

R5410

0.003

CRITICAL

3

V+

U5410

4

0612

MF 1W 1%

123

ISNS_HS_GPU_N

96

ISNS_HS_GPU_P

96

Gain:200x

INA210

5

SC70

IN-

4

CRITICAL

GND

2

OUT

REFIN+

10V CERM

2

402

6

HS_GPU_IOUT

1

PLACE_NEAR=U4900.K9:5MM

R5413

4.53K

1 2

1% 1/16W MF-LF

402

C

SMC Key IG0R SMC_ADC2

SMC_GPU_HI_ISENSE

PLACE_NEAR=U4900.K9:5MM

C5413

1

0.22UF

20%

6.3V X5R

2

402

GND_SMC_AVSS

OUT

41 42 45 46 99

42

PLACE_NEAR=R7510.3:5MM

CPUIMVP_ISNS1_P

65 66 97

IN

PLACE_NEAR=R7520.3:5MM

CPUIMVP_ISNS2_P

65 66 97

IN

PLACE_NEAR=R7530.3:5MM

CPUIMVP_ISNS3_P

65 66 97

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7510.4:5MM

CPUIMVP_ISNS1_N

66 97

IN

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

PLACE_NEAR=R7520.4:5MM

SENSOR_NONPROD:Y

CPUIMVP_ISNS2_N

66 97

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7530.4:5MM

SENSOR_NONPROD:Y

CPUIMVP_ISNS3_N

66 97

IN

SIGNAL_MODEL=EMPTY

Sense R is R7510, R7520 & R7530 Individual Sense R is 0.75mOhm

(Effective Sense R is 0.25mOhm due to summing of the 3 phases)

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

R5456

5.23K

1 2

SENSOR_NONPROD:Y

1 2

EDP: 94A TDP :45A

0.5%

1/16W

MF

402

R5457

5.23K

0.5%

1/16W

MF

402

R5458

5.23K

0.5%

1/16W

MF

402

R5470

5.23K

1 2

1/16W

R5471

5.23K

1 2

1/16W

R5472

1 2

SIGNAL_MODEL=EMPTY

CPUIMVP_ISNS_P

96

CPUIMVP_ISNS_N

0.5%

MF

402

0.5% MF

402

5.23K

0.5%

1/16W

MF

402

CPU VCore Load Side Current Sense / Filter

=PP3V3_S0_IMVPISNS

8

R5452

3.48K

1 2

1% 1/16W MF-LF

402

R5453

3.48K

1 2

1% 1/16W MF-LF

402

SENSOR_NONPROD:Y

46

CPUIMVP_ISUM_R_P

97

CPUIMVP_ISUM_R_N

97

1

R5454

732K

1% 1/16W MF-LF 402

2

1

+

3

-

SENSOR_NONPROD:Y

R5455

732K

1 2

1% 1/16W MF-LF

402

SENSOR_NONPROD:Y

CRITICAL

U5450

OPA333DCKG4

5

SC70-5

V+

4

V-

2

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

SIGNAL_MODEL=EMPTY

1

2

CPUIMVP_ISUM_IOUT

SENSOR_NONPROD:Y

PLACE_NEAR=U5450.5:3MM

C5450

0.1UF

20% 10V X7R-CERM 0402

SENSOR_NONPROD:Y

R5451

4.53K

1 2

Gain:140x

Scale: 28.55A / V Max VOut: 3.3V at 94.2A

PLACE_NEAR=U4900.M11:5MM

1% 1/16W MF-LF

1

402

2

SMC Key IC0C SMC_ADC1

SMC_CPU_ISENSE

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.M11:5MM

C5451

0.22UF

20%

6.3V X5R 402

GND_SMC_AVSS

41 42 45 46 99

D

42

OUT

C

OTHER High Side Current Sense / Filter

=PP3V3_S0_HS_ISNS

8

46

R5433

4.53K

1 2

1% 1/16W MF-LF

402

SMC Key IO0R SMC_ADC9

SMC_OTHER_HI_ISENSE

PLACE_NEAR=U4900.L7:5MM

C5433

1

0.22UF

20%

6.3V X5R

2

402

GND_SMC_AVSS

41 42 45 46 99

PLACE_NEAR=R7560.3:5MM

CPUIMVP_ISNS2G_P

66 97

IN

SIGNAL_MODEL=EMPTY

42

OUT

PLACE_NEAR=R7550.3:5MM

CPUIMVP_ISNS1G_P

66 96

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7550.4:5MM

CPUIMVP_ISNS1G_N

66 96

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7560.4:5MM

CPUIMVP_ISNS2G_N

66 97

IN

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

R5468

5.23K

1 2

0.5%

1/16W

MF

402

SENSOR_NONPROD:Y

R5466

5.23K

1 2

0.5%

1/16W

MF

402

SENSOR_NONPROD:Y

R5467

5.23K

1 2

0.5%

1/16W

SENSOR_NONPROD:Y

R5469

5.23K

1 2

0.5%

1/16W

C5431

EDP Current:12.546A

=PPVIN_S5_HS_OTHER_ISNS

8

OUT

=PPVIN_S5_HS_OTHER_ISNS_R

8

IN

R5430

0.005

CRITICAL

0612

MF 1W 1%

4

ISNS_HS_OTHER_N

96

ISNS_HS_OTHER_P

96

123

Gain:50x

3 V+

U5430

INA213

5

SC70

IN-

4

CRITICAL

GND

2

OUT

REFIN+

1

0.1UF

20% 10V CERM

2

402

6

HS_OTHER_IOUT

PLACE_NEAR=U4900.L7:5MM

1

B

CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER

R5423

45.3K

CHGR_BMON

61

IN

From charger

A

1 2

1/16W MF-LF

SMC_CHGR_BMON_INSENSE_R

1%

402 402

C5421

1

0.022UF

10% 16V X5R-X7R-CERM

2

0402

GND_SMC_AVSS

41 42 45 46 99

R5420

0

1 2

5% 1/16W MF-LF

SMC_CHGR_BMON_ISENSE

IPBR SMC_ADC7

OUT

42

DC-IN (AMON) Current Sense Filter

EDP Current:4.6A

IN

PLACE_NEAR=U4900.K10:5MM

CHGR_AMON

R5441

45.3K

1 2

1% 1/16W MF-LF

402

SMC_DCIN_ISENSE

PLACE_NEAR=U4900.K10:5MM

1

C5441

0.0022UF

10% 50V

2

CERM 402

GND_SMC_AVSS

SMC Key ID0R SMC_ADC4

OUT

41 42 45 46 99

42 61

6 3

GFX/IG VCore Load Side Current Sense / Filter

=PP3V3_S0_IMVPISNS

8

46

SENSOR_NONPROD:Y

+

-

R5465

1 2

V+

V-

732K

1/16W MF-LF

402

CRITICAL

U5460

OPA333DCKG4

5

SC70-5

4

CPUIMVP_ISUMG_IOUT

2

1%

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

CPUIMVP_ISNS1G_R_P

CPUIMVP_ISNS1G_R_N

MF

402

MF

402

SENSE R IS R7550, R7560, 0.75MOHM EDP: 33A TDP: 21.5A

PART NUMBER

R5462

5.49K

1 2

97

1% 1/16W MF-LF

402

SENSOR_NONPROD:Y

R5463

5.49K

1 2

1% 1/16W MF-LF

402

116S0114

CPUIMVP_ISUMG_R_P

CPUIMVP_ISUMG_R_N

SENSOR_NONPROD:Y

1

R5464

732K

1% 1/16W MF-LF 402

2

QTY

2

1

3

SENSOR_NONPROD:Y

SIGNAL_MODEL=EMPTY

DESCRIPTION

RES,MTL FILM,100K,5,1/16W,0402,SMD,LF

SENSOR_NONPROD:Y

PLACE_NEAR=U5460.5:3MM

1

C5460

0.1UF

20% 10V

2

X7R-CERM 0402

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.M13:5MM

R5461

4.53K

1 2

1% 1/16W MF-LF

402

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.M13:5MM

1

C5461

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

Gain:90.31x

REFERENCE DES

C5451,C5461

SYNC_MASTER=D2_SEAN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

High Side and CPU/AXG Current Sensing

R

CRITICAL

Apple Inc.

SMC Key IN0C

SMC_ADC18

SMC_CPU_GFX_ISENSE

41 42 45 46 99

BOM OPTION

SENSOR_NONPROD:N

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

54 OF 132

SHEET

46 OF 99

124578

4.18.0

42

OUT

B

A

SIZE

D

8 7 6 5 4 3

12

GPU PROXIMITY/GPU DIE/LEFT FIN STACK/RIGHT FIN STACK

R5550

47

=PP3V3_S0_GPUTHMSNS

8

77 96

D

Detect GPU Die Temperature

BI

TG0D

77 96

BI

GPUTHMSNS_D_P

96

GPUTHMSNS_D_N

96

Placement note:

PLACE Q5501 ON TOP SIDE CLOSE TO THE LEFT FIN STACK

CRITICAL

Q5501

BC846BMXXH

SOT732-3

2

1

3

Th2H

LEFT FIN STACK TEMPERATURE

CRITICAL

BC846BMXXH

PLACE Q5503 ON BOTTOM SIDE NEAR RIGHT FIN STACK

3

Q5503

SOT732-3

2

Th1H

Placement note:

1

RIGHT FIN STACK TEMPERATURE

DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY

R5570

C

TM0P

DDR3 PROXIMITY TEMPERATURE

Q5506

SOT732-3

3

2

CRITICAL

Placement note:

PLACE Q5503 ON TOP SIDE NEAR DDR3

Ta0P

AIRFLOW PROXIMITY TEMPERATURE

CRITICAL

Q5502

SOT732-3

2

1

3

BC846BMXXH

Placement note:

B

PLACE Q5502 ON TOP SIDE CLOSE TO BOARD EDGE

BC846BMXXH

=PP3V3_S0_CPUTHMSNS

8

DDR3THMSNS_D1_P

96

1

DDR3THMSNS_D1_N

96

Q5504

SOT732-3

3

2

CRITICAL

BC846BMXXH

TP0P

PCH PROXIMITY TEMPERATURE

Placement note:

PLACE Q5504 ON TOP SIDE UNDER PCH

1

47

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U5570.2:5mm

PLACE_NEAR=U5570.3:5mm

SIGNAL_MODEL=EMPTY

0.0022uF

CPUTHMSNS_D2_P

96

SIGNAL_MODEL=EMPTY

CPUTHMSNS_D2_N

96

PLACE_NEAR=U5570.4:5mm PLACE_NEAR=U5570.5:5mm

1 2

5% 1/16W MF-LF

402

GPU_TDIODE_P

SIGNAL_MODEL=EMPTY

GPU_TDIODE_N

SIGNAL_MODEL=EMPTY

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

C5571

10% 50V

2

CERM

402

C5590

0.0022uF

10% 50V

CERM

402

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PLACE_NEAR=U5550.2:5mm

PLACE_NEAR=U5550.3:5mm

C5551

0.0022uF

C5552

0.0022uF

PLACE_NEAR=U5550.4:5mm

PLACE_NEAR=U5550.5:5mm

1

2

1

10% 50V

2

CERM

402

1

10% 50V

2

CERM

402

U5570

EMC1414-A-AIA

2

DP1

DN1

4

DP2/DN3

5

DN2/DP3

GND

6

EMC1414-A-AIA

2

DP1

DN1

4

DP2/DN3

5

DN2/DP3

GND

6

1

VDD

DFN

THERM*/ADDR

THRM_PAD

11

7

CPUTHMSNS_THM_L

83

CPUTHMSNS_ALERT_L

ALERT*

9

SMDATA

10

SMCLK

TC0P

Placement note:

PLACE U5570 ON TOP SIDE UNDER CPU

Write Address: 0x98 Read Address: 0x99

1

VDD

U5550

DFN

THERM*/ADDR

THRM_PAD

Write Address: 0x98 Read Address: 0x99

1

C5570

0.1UF

20% 10V

2

X7R-CERM 0402

7

GPUTHMSNS_THM_L

83

ALERT*

SMDATA

11

GPUTHMSNS_ALERT_L

9

10

SMCLK

TG0P

GPU PROXIMITY TEMPERATURE

Placement note:

PLACE U5550 ON TOP SIDE UNDER GPU

1

R5571

10K

5% 1/16W MF-LF

402

2

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

CPU PROXIMITY TEMPERATURE

1

C5550

0.1UF

20% 10V X7R-CERM 0402

R5551

1/16W MF-LF

2

=SMBUS_GPUTHMSNS_SDA

=SMBUS_GPUTHMSNS_SCL

1

R5572

10K

5% 1/16W MF-LF 402

2

44

BI

44

BI

10K

1

R5552

10K

5%

5% 1/16W MF-LF

402

2

44

BI

44

BI

THSP

TP_TBT_THERM_DP

35

BI

PLACE_NEAR=U3600.B1:2mm

Use GND pin B1 on U3600 for N leg

1 2

XW5520

SM

TBT DIE

PLACE_SIDE=BOTTOM

97

TBT_THERMD_P

97

MAKE_BASE=TRUE

TBT_THERMD_N

NOSTUFF

1

R5520

10K

5% 1/16W MF-LF 402

2

D

C

B

TW0P

=I2C_X29THMSNS_SDA

44

BI

=I2C_X29THMSNS_SCL

44

BI

A

6 3

X29 PROXIMITY

=PP3V3_S0_X29THMSNS

8

PLACE_NEAR=J3501

PLACE_SIDE=BOTTOM

A1

B1

Placement note:

PLACE U5523 ON BOTTOM NEAR X29 CONN

SDA

SCL

C1

V+

U5523

TMP105

WCSP-6

CRITICAL

GNDS

A2

ALERT

1

2

X29THMSNS_A0

C2

A0

B2

NC

1

C5523

R5522

0.1uF 10K

20%

5%

10V

1/16W

CERM

MF-LF

402

2

WRITE ADDRESS: 0X92 READ ADDRESS: 0X93

SYNC_MASTER=D2_SEAN

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

55 OF 132

SHEET

47 OF 99

SIZE

A

D

124578

8 7 6 5 4 3

12

D

C

=PP5V_S0_FAN_LT

8

=PP3V3_S0_FAN_LT

8

SMC_FAN_0_TACH

41 41

OUT OUT

R5651

100K

5% 1/16W MF-LF

402

41

IN

1

2

Left Fan

R5655

47K

1 2

1/16W MF-LF

402

5

G

S D

4

7

5%

Q5660

2N7002DW-X-G

SOT-363

3

7

FAN_LT_TACH

FAN_LT_PWM

R5650

47K

1/16W MF-LF

=PP5V_S0_FAN_RT

8

=PP3V3_S0_FAN_RT

8

1

5%

402

2

CRITICAL

J5650

FF14A-5C-R11DL-B-3H

NC NC

F-RT-SM

6

NC

1 2 3 4 5

7

NC

518S0769 518S0769

41

SMC_FAN_1_TACH

SMC_FAN_1_CTLSMC_FAN_0_CTL

IN

R5661

100K

1/16W MF-LF

5%

402

1

2

1

Right Fan

R5665

47K

1 2

5% 1/16W MF-LF

402

2

Q5660

G

2N7002DW-X-G

SOT-363

S D

6

FAN_RT_TACH

7

FAN_RT_PWM

7

R5660

1/16W MF-LF

47K

1

5%

402

2

CRITICAL

J5660

FF14A-5C-R11DL-B-3H

F-RT-SM

6

NC

1 2 3 4 5

7

NC

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Fan Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

56 OF 132

SHEET

48 OF 99

124578

8 7 6 5 4 3

IC

P-TYPE 12V

29 mOhm @4.5V

16 mA (EDP)

49

TMP102

3V3 LDO

PSOC

18V BOOSTER

=PP5V_S4_TPAD

8

PP5V_S5RS4_CUMULUS

49

PSOC USB CONTROLLER

- USB INTERFACES TO MLB

- SPI HOST TO Z2

- TRACKPAD PICK BUTTONS

PLACE_SIDE=BOTTOM

=PP3V3_S4_TPAD

8

49

D

=PSOC_WAKE_L

42

OUT

PICKB_L

7

49

BUTTON_DISABLE

49

Z2_HOST_INTN

7

49

WS_LEFT_SHIFT_KEY

49

WS_LEFT_OPTION_KEY

49

WS_CONTROL_KEY

49

Z2_KEY_ACT_L

7

49

TPAD_VBUS_EN

70

IN

PSOC_MISO

7

49

PSOC_F_CS_L

7

49

PSOC_MOSI

7

49

PSOC_SCLK

7

49

Z2_MISO

7

C

49

Z2_CS_L

7

49

Z2_MOSI

7

49

Z2_SCLK

7

49

TP_PSOC_SCL TP_PSOC_SDA TP_PSOC_P1_3

7

TP_ISSP_SCLK_P1_1

ISSP SCLK/I2C SCL

USB_TPAD_P

9

91

USB_TPAD_N

9

91

R5704

1.5

2 1

5% 1/16W MF-LF

402

NC

NC NC

R5701

24

1 2

5%

1/20W

MF

201

R5702

24

1 2

5%

1/20W

MF

201

PP3V3_S3_PSOC

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

1

R5703

220K

5%

1/20W

MF

201

2

P2_5

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_7

15

96

USB_TPAD_R_P

26

96

USB_TPAD_R_N

26

B

All RC values are TBD

5V TRACKPAD S4 FET

=PP5V_S5_TPAD

8

TPAD_5V_FET

Q5721

SSM3K15FV

SOD-VESM-HF

1

SSM6N15FEAPE

SMC_LID

G S

Q5701

SOT563

=P5VS4_TPAD_EN

70

IN

BUTTON_DISABLE

A

49

41 42

IN

TPAD_5V_FET

3

D

2

R5721

220K

1/20W

1

5% MF

201

2

P5VCUMULUS_EN_L

TPAD Buttons Disable

PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

6

D

THE TPAD BUTTONS WILL BE DISABLE

2

WHEN THE LID IS CLOSED

SG

1

LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V

- KEYBOARD SCANNER

BYPASS=U5701.49:50:5 mm

1

2

51

P0_3

P0_5

P0_1

CRITICAL

CY8C24794

(SYM-VER2)

50

VSS

P0_7

OMIT

U5701

MLF

VDD

P0_4

P0_6

55

P2_7

337S2983

P7_0

P7_7

VSS

VDD

D+

D-

P1_1

P1_3

P1_5

20

21

24

235722 49

19

1

C5702

100PF

5% 25V

2

NP0-CERM 0201

BYPASS=U5701.22:19:5 mm

TPAD_5V_FET

R5722

3.3K

1 2

5%

1/20W

MF

201

C5722

0.033UF

1

10% 16V

2

X5R 402

BYPASS=U5701.49:50:8 mm

C5704

100PF

5% 25V NP0-CERM 0201

45544653475248

P0_2

P0_0

P1_0

25182617271628

1

C5705

0.1UF

10%

6.3V

2

X5R 201

WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18

435644

421 412 403 394 385 376 367 358 349 3310 3211 3112 3013 2914

C5703

0.1UF

10%

6.3V X5R 201

WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3

WS_KBD4 WS_KBD5 WS_KBD6

Z2_CLKIN TP_P7_7

P2_4

P2_6

P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0

THRML

PAD

P1_2

P1_4

P1_6

TP_ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

1

2

BYPASS=U5701.22:19:8 mm

TPAD_5V_NO_FET

R5720

0

1 2

5% 1/16W MF-LF

402

TPAD_5V_FET

CRITICAL

Q5720

SIA413DJ

SC70-6L

S

4 7

D

G

TPAD_5V_FET

3

C5723

0.01UF

P5VCUMULUS_SS

1 2

10% 10V X5R 201

BOM GROUP

TPAD_5V:LDO_S4 TPAD_5V:LDO_S5

BYPASS=U5701.49:50:11 mm

1

C5706

4.7UF

20%

6.3V

2

X5R 402

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

49

(PP3V3_S3_PSOC)

1

C5701

4.7UF

20%

6.3V

2

X5R 402

BYPASS=U5701.22:19:11 mm

5V TPAD FET

MOSFET SiA413

CHANNEL

RDS(ON)

LOADING

1

PP5V_S5RS4_CUMULUS

VOLTAGE=5V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM

BOM Options available to CSA 5

TPAD_5V:SW_S4 Original implementation off PP5V_S4 TPAD_5V:LDO_S4 PP5V_S5 LDO power in S4 only TPAD_5V:LDO_S5 PP5V_S5 LDO power

PIN NAME

V+

VDD VOUT VDD

VIN

=PP3V3_S4_TPAD

8

49

10UA 80UA 60MA (MAX) 60MA (MAX)

8MA (TYP)

14MA (MAX)

4MA (MAX)

TPAD_5V_SW_S4

PLACE_NEAR=J5800.18:3MM

L5700

FERR-120-OHM-1.5A

1 2

0402-LF

TPAD_5V_SW_S4

1

C5700

0.1UF

10% 10V

2

X5R-CERM 0201

TPAD_5V_LDO

PLACE_NEAR=J5800.18:3MM

L5707

FERR-120-OHM-1.5A

1 2

0402-LF

TPAD_5V_LDO

1

C5707

0.1UF

10% 10V

2

X5R-CERM 0201

Caps Lock LED Drive

=PP3V3_S4_TPAD

8

WS_KBD15_C

BOM OPTIONS

TPAD_5V_SW_S4TPAD_5V:SW_S4

TPAD_5V_FET,TPAD_5V_LDO

TPAD_5V_NO_FET,TPAD_5V_LDO

CURRENT

R_SNS

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

R5708

0

1 2

5%

1/20W

MF

201

PP5V_S4_CUMULUS

VOLTAGE=5V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM

PLACE_NEAR=J5800.18:3MM

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

PLACE_NEAR=J5800.18:3MM

=PP3V3_S4_TPAD

8

49

WS_LEFT_SHIFT_KBD

7

49

WS_LEFT_OPTION_KBD

7

49

WS_CONTROL_KBD

7

49

CAPS:EXT

1

R5730

10K

5% 1/20W MF 201

2

CAPS:EXT

1

R5731

10K

5% 1/20W MF 201

2

CAPS:EXT

1

R5732

10K

5% 1/20W MF 201

2

CAPS:EXT

1

R5733

20K

5% 1/20W MF 201

2

V_SNS POWER

0.0255 V

0.204 V

0.6 V

0.012 V

0.021 V

0.0188 V

NOSTUFF

1

C5708

0.1UF

10%

6.3V

2

X5R 201

0.255E-6 W

16.32E-6 W 36E-3 W

0.72E-3 W 96E-6 W

294E-6 W

75.2E-6 W

PP3V3_TPAD_CONN

VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM

Z2_CS_L

7

49

Z2_MOSI

7

49

Z2_MISO

7

49

Z2_SCLK

7

49

Z2_HOST_INTN

7

49

Z2_CLKIN

7

49

R5700

220K

5%

1/20W

MF

201

IPD Flex Connector

CRITICAL

1 34 56 78 9 1112 1314 1516 1718 19 2122

NC

516S0689

J5700

55560-0228

M-ST-SM

2

NC NC

10

NC

20

1

2

SMC Manual Reset & Isolation

Keys ANDed with PSoC power to isolate when PSoC is not powered.

No IPD on OE input pin PP3V3_S4 (symbol error).

=PP3V42_G3H_TPAD

8

49

10

VDD

U5750

SLG4AP021

CAPS:EXT

R5740

8

1/20W

7

1

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

GND

10K

TQFN

5

5% MF

201

THRM

PAD

11

1

2

CAP_COMP_H

SSM3K15AMFVAPE

CAP_COMP_L

OUT_1

OUT_2

OUT_3

OUT_ALL#

CAPS:EXT CRITICAL

Q5734

9

8

7

6

CAPS:EXT

R5738

10K

1/20W

VESM

1

G S

201

WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KEY

WS_CONTROL_KEY

Pull-up in U5010.

SMC_TPAD_RST_L

1

5% MF

2

D

CAPS:EXT

1

R5734

20K

5% 1/20W MF 201

2

CAP_VREF_L

CAP_VREF_H

CAPS:EXT

1

R5735

10K

5% 1/20W MF 201

2

4

OE

(IPD)

1

IN_1

(IPD)

2

IN_2

(IPD)

3

IN_3

(IPD)

CAPS:EXT

LM393ADGKR

6 5

2 3

V+

U5730

MSOP

GND

4

Z2_KEY_ACT_L

PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK =I2C_TPAD_SDA =I2C_TPAD_SCL

1

C5750

0.1UF

10% 16V

2

X7R-CERM 0402

WS_KBD15_C

Z 1 0

CAPS:EXT

1

R5736

10K

5%

1/20W

MF

201

2

CAP_COMP_L_INV

3

2

41 42

OUT

49

OUT

CAPS:EXT

R5737

CAPS:EXT

R5739

7

49

7

49

7

49

7

49

7

49

7

49

44

WS_KBD15_C

49

WS_KBD16N

49

SMC_ONOFF_L

PLACEMENT_NOTE=NEAR J5713

42

CAP_COMP_H

1 0 1

1

2

G

6

1

113

1%

1/20W

MF

201

2

1

113

1%

1/20W

MF

201

2

G

1

Keyboard Connector

=PP3V3_S4_TPAD

8

49

=PP3V42_G3H_TPAD

8

49

WS_KBD1

7

49

WS_KBD2

7

49

WS_KBD3

7

49

WS_KBD4

7

49

WS_KBD5

7

49

WS_KBD6

7

49

WS_KBD7

7

49

WS_KBD8

7

49

WS_KBD9

7

49

WS_KBD10

7

49

CAPS:INT

R5714

56.2

1 2

1% 1/16W MF-LF

402

R5715

10K

1 2

1%

1/16W MF-LF

402

R5710

1K

1 2

5%

1/16W

1

C5710

0.1UF

20% 10V

CERM

402

MF-LF

402

2

CAP_COMP_L

1 1 0

CAPS:EXT

S

Q5736

NTZD3152P

SOT-563-HF

D

CAP_SOURCE

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

WS_KBD15_CAP

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

CAP_SINK

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

3

D

CAPS:EXT

Q5738

DMN3730UFB4

S

DFN1006H4-3

2

SYNC_MASTER=D2_KEPLER

PAGE TITLE

7

49

KEYBOARD/TRACKPAD (1 OF 2)

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

WS_KBD11

7

49

WS_KBD12

7

49

WS_KBD13

7

49

WS_KBD14

7

49

WS_KBD15_CAP

7

49

WS_KBD16_NUM

7

WS_KBD17

7

49

WS_KBD18

7

49

WS_KBD19

7

49

WS_KBD20

7

49

WS_KBD21

7

49

WS_KBD22

7

49

WS_KBD23

7

49

WS_KBD_ONOFF_L

7

WS_LEFT_SHIFT_KBD

7

49

WS_LEFT_OPTION_KBD

7

49

WS_CONTROL_KBD

7

49

Q5736

off

on

off

Apple Inc.

Q5738

off off

on

6 3

12

32

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

31

FF14A-30C-R11DL-B-3H

F-RT-SM

J5713

CRITICAL

518S0752

LED Current

none

source

sink

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

57 OF 132

SHEET

49 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PP3V3_S0_TPAD

8

1

R5853

470K

5% 1/16W MF-LF 402

2

SMC_SYS_KBDLED

41 50

OUT

1

R5854

4.7K

5% 1/16W MF-LF 402

D

2

SMC_KBDLED_PRESENT_L

7

J5815 PIN 4 IS GROUNDED

ON KEYBOARD BACKLIGHT FLEX

CRITICAL

J5815

AA07A-S010-VA1

F-ST-SM

12 11

1

2

34 56 78

10

9

13 14

12

KBDLED_ANODE2

NC

KBDLED_ANODE1

D

7

50

7

50

516S0899

Keyboard Backlight Connector

C

Keyboard Backlight Driver & Detection

SIZE

B

A

D

B

A

To detect Keyboard backlight, SMC will tristate and read SMC_SYS_KBDLED:

If LOW, keyboard backlight present If HIGH, keyboard backlight not present

R5853 always stuffed, R5854 only grounded when KB BL flex connected.

SMC_SYS_KBDLED

41 50

IN

NOSTUFF

1

R5857

10K

5% 1/16W MF-LF 402

2

SMC_SYS_KBDLED_FILTER

NOSTUFF

1

C5859

10UF

20% 10V

2

X5R 0603

NOSTUFF

1

R5858

120K

5% 1/16W MF-LF 402

2

NOSTUFF

1

R5859

100K

5% 1/16W MF-LF 402

2

=PP5V_S0_KBDLED

8

CRITICAL

15UH-20%-740MA-0.42OHM

SMC_SYS_KBDLED_ANALOG

15UH-20%-740MA-0.42OHM

L5850

1 2

VLF403212MT-SM

1

C5850

1UF

10% 10V

2

X5R 402-1

L5860

1 2

VLF403212MT-SM

1

C5860

1UF

10% 10V

2

X5R 402-1

CRITICAL

R5856

0

1 2

5% 1/16W MF-LF

402

KBDLED_SW1

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE

R5866

1 2

5% 1/16W MF-LF

402

KBDLED_SW2

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE

0

NOSTUFF

SMC_SYS_KBDLED_R

353S3472

8

OMIT_TABLE

CTRL

U5850

1

VIN

LT3591

3

SW

4

SW

U5860

1

VIN

LT3591

3

SW

4

SW

GND

DFN

2

CTRL

DFN

2

LED

CAP

PAD

9

353S3472

8

OMIT_TABLE

LED

CAP

PAD

9

7

5

6

7

5

6

KBDLED_ANODE1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=35V

KBDLED_ANODE2

7

50

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=35V

KBDLED_CAP1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

KBDLED_CAP2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

10

1 2

1% 1/16W MF-LF

402

10

1 2

1% 1/16W MF-LF

402

R5855

R5865

KBD_BL:SANDWICH

CRITICAL

1

C5855

1.0UF

10% 50V

2

X5R 0603

KBD_BL:SANDWICH

CRITICAL

1

C5865

1.0UF

10% 50V

2

X5R 0603

KBD_BL:SANDWICH

CRITICAL

1

C5856

1.0UF

10% 50V

2

X5R 0603

KBD_BL:SANDWICH

CRITICAL

1

C5866

1.0UF

10% 50V

2

X5R 0603

KBD_BL:TBONE

CRITICAL

1

C5857

1.0UF

10% 50V

2

X7R 0805

KBD_BL:TBONE

CRITICAL

1

C5867

1.0UF

10% 50V

2

X7R 0805

KBD_BL:TBONE

CRITICAL

1

C5858

1.0UF

10% 50V

2

X7R 0805

KBD_BL:TBONE

CRITICAL

1

C5868

1.0UF

10% 50V

2

X7R 0805

PART NUMBER

6 3

353S1612

QTY

DESCRIPTION

2

IC,DC/DC CVTR,BOOST,WHITE LED,1MHZ,DFN8

REFERENCE DES

U5850,U5860

SYNC_MASTER=D2_KEPLER

PAGE TITLE

CRITICAL

KEYBOARD/TRACKPAD (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

BOM OPTION

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

58 OF 132

SHEET

50 OF 99

124578

8 7 6 5 4 3

=PP3V3_S3_SMS

8

D

BYPASS=U5920.14:13:8 mm

C5926

10UF

41 42

OUT

BYPASS=U5920.14:13:8 mm

SMS

20%

6.3V X5R 603

SMS_INT_L TP_SMS_INT2

SMS

1

C5922

0.1UF

10%

6.3V

2

X5R 201

PLACEMENT_NOTE=See schematic for orientation.

SMS

1

R5924

10K

5%

1/20W

MF

201

2

Desired orientation when placed on board bottom-side (view thru top):

+Y

+X

2

NC

3

NC

10

RESERVED

15

11

INT1CSSDA/SDI/SDO

9

INT2

+Z (dn)

SMS

14

VDD

VDD_IO

U5920

LIS331DLH

LGA

CRITICAL

GND

5

121316

Front of system

1

SDO

SCL/SPC

338S0687

8

SMS_I2C_SEL

7

SMS_ADDR_SELECT

6

I2C_SMC_SMS_SDA_R

4

I2C_SMC_SMS_SCL_R

R5920

1/20W

SMS

10K

NOSTUFF

1

5%

MF

201

2

R5925

1/20W

SMS

R5921

1/20W

1

10K

5%

MF

201

2

1

5%

MF

201

2

SMS

R5923

0

1 2

R5922

1 2

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd) SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

1/20W

SMS

1/20W

5%

MF

201

0

5%

MF

201

=I2C_SMC_SMS_SDA

=I2C_SMC_SMS_SCL

44

BI

44

IN

C

Circle indicates pin 1 location when placed in correct orientation

12

D

C

=PP3V3_S3_GYRO

8

GYRO

1

C5940

0.1UF

10%

6.3V

2

GYRO

1

R5944

10K

5% 1/20W MF 201

2

CS PU = I2C

INT ARE PUSH-PULL

B

TP_IRQ_GYRO_INT2_L TP_GYRO_SYNC

TP_IRQ_GYRO_INT1_L

PLLFILT_GYRO1

GYRO_CS

PLLFILT_GYRO GYRO

1

C5942

0.47UF

10%

6.3V

2

CERM-X5R 402

GYRO

1

R5945

10K

5% 1/20W MF 201

2

GYRO

1

C5945

0.01UF

10% 10V

2

X5R-CERM 0201

GYRO

14

5 6 8

7

RES/VDD

AP3GDL8B

CS DRDY/

INT2

DEN

INT1 PLLFILT

15

16

VDD_IO

VDD

U5940

LGA

SDA_SDI_SDO

CRITICAL

GND

13

1

SCL_SPC

SDO_SA0

RES0 RES1 RES2 RES3

X5R 201

338S0927 = 8KHZ

2

I2C_SMC_GYRO_SCL_R

3

I2C_SMC_GYRO_SDA_R

4

9 10 11 12

A

6 3

GYRO

1

C5941

0.1UF

10%

6.3V

2

X5R 201

GYRO

1

C5943

10UF

20%

6.3V

2

CERM-X5R 0402-1

GYRO

R5946

1 2

1/20W

GYRO

R5947

1 2

1/20W

0

5%

MF

201

0

5%

MF

201

GYRO

(WRITE: 0XD0 READ: 0XD1)

=I2C_SMC_GYRO_SCL

=I2C_SMC_GYRO_SDA

44

IN

B

44

BI

SIZE

A

D

SYNC_MASTER=D2_KEPLER

PAGE TITLE

DIGITAL ACCELEROMETER & GYRO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

59 OF 132

SHEET

51 OF 99

124578

8 7 6 5 4 3

12

D

C

=PP3V3_SUS_ROM

8

1

R6101

3.3K

5% 1/16W MF-LF 402

2

42 43 42 43

42 43

7

20 43

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

SPI_MLB_CLK

IN IN

SPI_MLB_CS_L

IN

SPI_WP_L SPIROM_USE_MLB

IN

C6100

0.1UF

CERM

20% 10V

402

1

2

6

SCK

1

CE*

3

WP*

7

HOLD*

8

CRITICAL

VDD

U6100

64MBIT

SOIC

SST25VF064C

OMIT

VSS

4

SI

SO

5

SPI_MLB_MOSI

2

SPI_MLB_MISO

42 43

OUT

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=D2_KEPLER

PAGE TITLE

SPI ROM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

61 OF 132

SHEET

52 OF 99

124578

8 7 6 5 4 3

AUDIO CODEC

L6201

FERR-22-OHM-1A-0.065-OHM

8

IN

=PP1V5_S0_AUDIO

1 2

0201

D

GND_AUDIO_CODEC

53 54 58 59

PP4V5_AUDIO_ANALOG

53 58 59

IN

AUD_DMIC_SDA1

59

IN

AUD_DMIC_SDA2

59

IN

TP_XCVR_ADC_RSTN

GPIO3 = SPKR AMP SHDN CONTROL

57

OUT

59

IN

8

53 58

IN

AUD_GPIO_3

AUD_SENSE_A

=PP3V3_S0_AUDIO_DIG

C6216

1UF

10% 10V X5R 402-1

C

HDA_BIT_CLK

17 92

IN

HDA_SYNC

17 92

IN

HDA_SDIN0

17 92

IN

HDA_SDOUT

17 92

OUT

HDA_RST_L

17 92

IN

B

58

7

OUT

R6211

22

1 2

5%

1/20W

MF

201

AUD_SPDIF_OUT_JACK

U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL

1

2

1

C6226

0.1UF

10%

6.3V

2

X5R 201

R6220

33

1 2

5% 1/16W MF-LF

402

1

C6211

0.1UF

10%

6.3V

2

X5R 201

CRITICAL

C6221

15UF

1

2

1

2

C6210

4.7UF

20% 4V X5R-1 402

R6210

2.67K

1% 1/20W MF 201

AUD_SDI_R

92

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V

1

20%

4V

2

X5R

0402

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

C6222

15UF

TP_AUD_SPDIF_IN AUD_SPDIF_OUT

0402

20%

4V

X5R

CRITICAL

1

C6220

15UF

20% 4V

2

X5R 0402

1

2

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_FP CS4206_FN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_FLYP CS4206_FLYC

1

C6223

2

CS4206_FLYN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

GND_AUDIO_CODEC

53 54 58 59

C6219

10UF

20% 16V

TANT-POLY

2012-LLP

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

15UF

20% 4V X5R 0402

1

2

VBIAS_DAC

APPLE P/N 353S2355

29

44 41

2

12

14 15

13

45 43 42

3

1

6

10

8 5

11

47 48

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.15MM VOLTAGE=0V

9

VA_REF

VD

VBIAS_DAC

VHP_FILT+ VHP_FILT-

GPIO0/DMIC_SDA1 GPIO1/DMIC_SDA2 GPIO2 GPIO3

U6201

CS4206B

/SPDIF_OUT2

SENSE_A

FLYP FLYC FLYN

VL_HD

CRITICAL

VL_IF

BITCLK

SYNC

SDI SDO

RESET*

SPDIF_IN SPDIF_OUT

THRM_PAD

DGND

7

49

24

46

VA_HP

QFN

LINEOUT_L1+ LINEOUT_L1LINEOUT_R1+ LINEOUT_R1-

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-

AGND

26

25 VA

HPOUT_L HPOUT_R

HPREF

MICBIAS

VCOM

LINEIN_L+ LINEIN_CLINEIN_R+

MICIN_L+ MICIN_LMICIN_R+ MICIN_R-

VREF+_ADC

DMIC_SCL

C6218

0.1UF

X7R-CERM

1

10% 16V

2

0402

38 40

39

35 34 36 37

31 30 32 33

16

CS4206_VCOM

28

21

22

23

18 17 19 20

27

AUD_DMIC_CLK_R

4

C6224

1UF

TANT

0603-SM

1

C6217

10UF

20% 16V

2

TANT-POLY 2012-LLP

MIN_LINE_WIDTH=0.3MM

1

20% 16V

2

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_VREF_ADC

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

1

C6225

10UF

20% 16V

2

TANT-POLY 2012-LLP

R6241

0

1 2

5% 1/16W MF-LF

402

MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

NC

CRITICAL

C6214

0.1UF

X5R-CERM

0201

10% 16V

1

2

AUD_DMIC_CLK

CRITICAL

1

C6213

10UF

20% 10V

2

X5R-CERM 0402-1

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

PP5V_AUDIO_HPAMP

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

AUD_HP_PORT_L AUD_HP_PORT_R

AUD_HP_PORT_REF

AUD_LO1_L_P AUD_LO1_L_N AUD_LO1_R_P AUD_LO1_R_N

AUD_LO2_L_P AUD_LO2_L_N AUD_LO2_R_P AUD_LO2_R_N

TP_AUD_CODEC_MICBIAS

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

NC_AUD_LI_P_L NC_AUD_LI_REF NC_AUD_LI_P_R

AUD_MIC_INL_P

AUD_MIC_INL_N

59

OUT

53

53 58 59

IN

53 54 58 59

7

54 58

OUT

7

54 58

OUT

58

IN

57 96

OUT

57 96

OUT

57 96

OUT

57 96

OUT

57 96

OUT

57 96

OUT

57 96

OUT

57 96

OUT

NC NC NC

58 96

IN

58 96

IN

TP_AUD_MIC_INP_R

TP_AUD_MIC_INN_R

LFT SUBWOOFER AMP. SIG. SOURCE

RT. SUBWOOFER AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

EXT MIC CODEC INPUT

12

D

C

B

15" MBP: PLACE XW6201 NEAR 5V SOURCE

XW6201

SM

1 2

8

53 58

IN

PP5V_S4_AUDIO_XW

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V

=PP5V_S4_AUDIO

8

59

IN

A

=PP3V3_S0_AUDIO_DIG

L6202

FERR-22-OHM-1A-0.065-OHM

1 2

0201

L6200

FERR-22-OHM-1A-0.065-OHM

1 2

0201

R6200

2.2K

1 2

5%

1/20W

1

MF

201

2

PP5V_AUDIO_HPAMP

4V5_REG_IN

4V5_REG_EN

C6200

1UF

10% 10V X5R 402

4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM VOLTAGE=5V

53

1

2

6

4

C6201

1UF

10% 10V X5R 402

U6200

IN

EN

TPS71745

SON

CRITICAL

GND

2

OUT

NR/FB

NC

XW6200

1 2

1

3

4V5_NR

5

SM

CRITICAL

C6202

0.1UF

10% 20% 16V

X5R-CERM

0201

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

6 3

1

2

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

CRITICAL

1

C6203

1.0UF

10V

2

X5R-CERM 0201-1

GND_AUDIO_CODEC

OUT

53 58 59

53 54 58 59

NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS

SYNC_MASTER=D2_CARA

PAGE TITLE

SYNC_DATE=03/16/2012

AUDIO: CODEC/REGULATOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

62 OF 132

SHEET

53 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

D

C

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

AUD_HP_PORT_L

7

53 58

7

53 58

IN

B

AUD_HP_ZOBEL_L

NC

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

GND_AUDIO_CODEC

53 58 59

IN

AUD_HP_ZOBEL_R

NC

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_R

7

53 58

7

53 58

IN

CRITICAL

C6300

0.1UF

R6300

R6310

1/20W

CRITICAL

C6310

0.1UF

6.3V

10% X5R

201

6.3V

1/20W

39

5% MF

201

1

10%

2

X5R 201

1

39

5% MF

201

2

1

2

1

2

1

R6302

10K

1% 1/20W MF 201

2

1

R6312

10K

1% 1/20W MF 201

2

A

6 3

OUT

B

OUT

SIZE

A

D

SYNC_MASTER=D2_CARA

PAGE TITLE

AUDIO: HEADPHONE FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/16/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

63 OF 132

SHEET

54 OF 99

124578

8 7 6 5 4 3

12

D

C

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=D2_CARA

PAGE TITLE

AUDIO: IV SENSE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=03/16/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

64 OF 132

SHEET

55 OF 99

124578

8 7 6 5 4 3

12

D

C

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=D2_CARA

PAGE TITLE

AUDIO: IV SENSE FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=03/16/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

65 OF 132

SHEET

56 OF 99

124578

8 7 6 5 4 3

PP5V_S0_AUDIO_AMP_L

9

57

CRITICAL

L6610

FERR-1000-OHM

IN

AUD_LO2_R_N

1 2

96

0402

L6611

FERR-1000-OHM

1 2

96

0402

CRITICAL

AUD_LO2_R_P

FERR-1000-OHM

1 2

CRITICAL

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

NO_TEST=TRUE

CRITICAL

L6620

FERR-1000-OHM

1 2

L6621

96

0402

AUD_GPIO_3

53

IN

96

0402

AUD_SPKRAMP_RIN_N

NO_TEST=TRUE

CRITICAL

AUD_SPKRAMP_RIN_P

NO_TEST=TRUE

53 96

AUD_LO2_L_P

IN

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

APN: 353S2888 & 353S2958

D

GAIN = +3 DB 1ST ORDER FC (L&R) = NOM 569 HZ 1ST ORDER FC (SUB) = NOM 9 HZ

53 96

AUD_LO2_L_N

IN

AUD_SPKRAMP_SHUTDOWN_L

57

53 96

C

53 96

IN

C6614

0.01UF

1 2

10% 50V

X7R-CERM

0402

CRITICAL

FERR-1000-OHM

1 2

57

CRITICAL

C6624

0.01UF

1 2

10% 50V

X7R-CERM

0402

C6613

0.01UF

1 2

X7R-CERM

9

10% 50V

0402

96

NO_TEST=TRUE

NO_TEST=TRUE SPKRAMP_LIN_P SPKRAMP_LIN_N

L6601

0402

CRITICAL

PP5V_S0_AUDIO_AMP_R

CRITICAL

C6623

0.01UF

1 2

10% 50V

X7R-CERM

0402

AUD_SPKRAMP_SHUTDOWN_L

57

96

SPKRAMP_RIN_N

96

NO_TEST=TRUE

NOSTUFF

PP5V_S0_AUDIO_AMP_R

9

57

CRITICAL

1

CRITICAL

L6630

FERR-1000-OHM

53 96

IN

AUD_LO1_R_N

AUD_LO1_R_P

1 2

0402

CRITICAL

L6631

FERR-1000-OHM

1 2

96

0402

AUD_SPKRAMP_RSUBIN_P

96

NO_TEST=TRUE

AUD_SPKRAMP_RSUBIN_N

NO_TEST=TRUE

CRITICAL

C6633

0.22UF

CRITICAL

C6634

0.22UF

1 2

10% 16V

CERM

402

1 2

10% 16V

CERM

402

RSUBIN_N

RSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_SHUTDOWN_L TP_SWR_GAIN

57

C6635

2

47UF

20%

6.3V POLY-TANT 2012-LLP

CRITICAL

1

C6632

47UF

20%

6.3V

2

POLY-TANT 2012-LLP

C2

CRITICAL

VDD

U6630

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

C1

OUT+ OUT-

GAIN

EDGE

C3

B3

A3

B2

PLACE_NEAR=U6630.C2

1

C6631

0.1UF

10% 16V

2

X5R-CERM 0201

SPKRCONN_SR_OUT_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

1

C6612

47UF

20%

6.3V

2

TANT-POLY

CASE-A4

1

R6600

100K

5% 1/16W MF-LF

402

2

C6622

47UF

20%

6.3V

POLY-TANT

2012-LLP

CRITICAL

NO_TEST=TRUE

SPKRAMP_RIN_P

1

R6601

100K

5%

1/20W

MF

201

2

PLACE_NEAR=U6610.A1

1

C6611

0.1UF

SPKR_L_GAIN

R6610

B1 C1

C3

SPKR_R_GAIN

R6620

100K

1/16W MF-LF

100K

2

402

1/16W MF-LF

5%

402

10% 16V X7R-CERM 0402

1

2

1

5%

2

PLACE_NEAR=U6620.A1

1

C6621

0.1UF

10% 16V

2

X5R-CERM 0201

7

OUT

7

OUT

59 96

SPKRCONN_L_OUT_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_N

A1

CRITICAL

PVDD

U6610

MAX98300

WLP

A3

IN+

B3

IN-

C2

B2

NC

OUT+ OUT-

GAINSHDN*

B1 C1

C3

PGND

A2

1

A1

U6620

MAX98300

IN+ IN-

NC

PVDD

WLP

CRITICAL

OUT+ OUT-

GAINSHDN*

2

A3 B3

C2

B2

PGND

A2

B

12

SPKRCONN_L_OUT_N

7

59 96

OUT

7

59 96

OUT

7

59 96

OUT

D

7

59 96

C

B

9

57

CRITICAL

L6640

FERR-1000-OHM

53 96

IN

AUD_LO1_L_P

AUD_LO1_L_N

1 2

0402

CRITICAL

L6641

FERR-1000-OHM

1 2

0402

AUD_SPKRAMP_LSUBIN_P

96

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_N

96 57

NO_TEST=TRUE

CRITICAL

C6643

0.22UF

1 2

CRITICAL

C6644

0.22UF

1 2

10% 16V

CERM

402

NO_TEST=TRUE

10% 16V

CERM

402

NO_TEST=TRUE

LSUBIN_P

LSUBIN_N

AUD_SPKRAMP_SHUTDOWN_L

A

6 3

PP5V_S0_AUDIO_AMP_L

CRITICAL

1

C6645

47UF

20%

6.3V

2

POLY-TANT 2012-LLP

CRITICAL

1

C6642

47UF

20%

6.3V

2

POLY-TANT 2012-LLP

PLACE_NEAR=U6640.C2

1

C6641

0.1UF

10% 16V

C2

CRITICAL

VDD

U6640

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

C1

OUT+ OUT-

GAIN

EDGE

C3

B3

A3

B2

TP_SWL_GAIN

2

X7R-CERM 0402

SPKRCONN_SL_OUT_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SL_OUT_N

7

59 96

OUT

7

59 96

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SYNC_MASTER=D2_CARA

PAGE TITLE

OUT

AUDIO: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/16/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

66 OF 132

SHEET

57 OF 99

SIZE

A

D

124578

I2C PULLUPS ON SOUTHBRIDGE PAGE

=I2C_MIKEY_SCL

44

IN

=I2C_MIKEY_SDA

44

BI

D

AUD_I2C_INT_L

19

OUT

AUD_IPHS_SWITCH_EN

25

IN

AUD_PORTA_DET_L

59

IN

C

8 7 6 5 4 3

PP4V5_AUDIO_ANALOG

53 59

=PP3V3_S0_AUDIO_DIG

8

53 58

R6758

33

1 2

5%

1/20W

MF

201

R6761

1 2

GND_AUDIO_CODEC

53 54 58 59

AUD_MIC_INL_P

53 96

OUT

AUD_MIC_INL_N

53 96

OUT

R6757

1 2

NOSTUFF

47K

5%

1/20W

MF

201

33

1/20W

201

5% MF

R6762

10K

1/20W

HS_HDET

201

5% MF

1

2

NO_TEST=TRUE

C6752

C6753

1

C6795

1.0UF

20% 10V

2

X5R-CERM 0201-1

58

MIKEY

CRITICAL

0.1UF

1 2

10%

6.3V X5R 201

MIKEY

CRITICAL

0.1UF

1 2

10%

6.3V X5R 201

1

5% MF

201

2

HS_MIC_LO_RC

1

C6755

1.0UF

20% 10V

2

X5R-CERM 0201-1

HS_MIC_HI_RC

MIKEY

CRITICAL

1

C6750

6800PF

10% 10V

2

X5R-X7R-CERM 0201

1

C6794

1.0UF

20% 10V

2

X5R-CERM 0201-1

AUDIO_SCL

AUDIO_SDA

1

R6755

100K

5%

1/20W

MF

201

2

NO_TEST=TRUE

MIKEY

R6756

100K

1/20W

R/C6750 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS (SEE RADAR # 6210118)

AVDD

U6751

CD3282A1

WCSP

C3

SCL

B3

SDA

D3

INT*

A3

ENABLE

A1

HDET

B2

CS

DGND

C2

MIKEY

R6759

1 2

1/20W

PORT B LEFT(HEADSET MIC)

HP=80HZ, LP=10.63KHZ

MIKEY 1A APN:353S2640 MIKEY ADDRESS: WRITE=72H, READ=73H

A2

C1

AGND

D2

5%

1/20W

MF

201

HS_MIC_BIAS

B1

HS_SW_DET

D1

HS_RX_BP

1

C6756

0.01UF

10% 10V

2

X5R-CERM 0201

MICBIAS

DETECT

BYPASS

MIKEY

R6750

2.2K

1 2

0

5% MF

201

GND_AUDIO_CODEC

53 54 58 59

=PP3V42_G3H_AUDIO

8

NO_TEST=TRUE

MIKEY

R6754

1/20W

MIKEY

CRITICAL

1

C6758

27PF

5% 25V

2

NP0-C0G 0201

R6760

47K

5%

1/20W

MF

201

NOSTUFF

1K

5% MF

201

1

2

FERR-22-OHM-1A-0.065-OHM

1

2

R6751

1K

5%

1/20W

MF

201

NO_TEST=TRUE

GND_AUDIO_CODEC

53 54 58 59

53

L6754

1 2

0201

12

1

C6751

10UF

20% 10V

2

X5R-CERM 0402-1

AUD_HP_PORT_REF

1

C6793

1.0UF

20% 10V

2

X5R-CERM 0201-1

NO_TEST=TRUE

R6752

2.2K

1 2

1%

1/20W

MF

201

1

C6791

10UF

20% 10V

2

X5R-CERM 0402-1

XW6751

SM

1 2

PLACE_NEAR=U6750.D1

GND_AUDIO_CODEC

53 54 58 59

1

C6792

1.0UF

20% 10V

2

X5R-CERM 0201-1

R6753

2.2K

1 2

1%

1/20W

MF

201

1

C6790

1.0UF

20% 10V

2

X5R-CERM 0201-1

GND_AUDIO_CODEC

53 54 58 59

CHS_CLAMPI

CHS_CLAMPO

NO_TEST=TRUE

58

IN

58

BI

AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM VOLTAGE=3.42V

PP3V42_GH3_AUDIO_LC

HS_MIC_HI HS_MIC_LO

AUDIO_SCL AUDIO_SDA

US_HS_GND

IN

CH_HS_GND

IN

PLACE_NEAR=U6750.A1

1

C6754

0.1UF

10% 16V

2

X5R-CERM 0201

A1

VDD

U6750

TS3A8235YFP

WCSP

CRITICAL

D4

RAMPI

D3

RAMPO

C4

CLAMPI

B4

CLAMPO

D2 B1

MIC

D1

REF

A3

SCL

A4

SDA

A2

ADDR

GND2

GND1

C2B2B3

GND

C3

MIC1 MIC2

FERR-33-OHM-0.8A-0.09-OHM

US_HS_MIC

7

58

OUT

7

58

OUT

C1

FERR-33-OHM-0.8A-0.09-OHM

CH_HS_MIC

7

53 54

IN

59

OUT

53 58

7

53

OUT

1 2

US_HS_GND

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.06MM

CH_HS_GND

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.06MM

CRITICAL

L6703

1 2

0201

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.1MM

AUD_CONN_TIPDET_INV

=PP3V3_S0_AUDIO_DIG

8

AUD_SPDIF_OUT_JACK

CRITICAL

L6701

0201

CRITICAL

L6700

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6702

120-OHM-25%-1.3A

1 2

0402

AUD_CONN_SLEEVE

CRITICAL

L6704

120-OHM-25%-1.3A

1 2

0402

AUD_CONN_MIC

AUD_CONN_SLEEVE_XW

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_CONN_MIC_XW

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

APN:510S0009

CRITICAL

J6701

51138-0274

F-ST-SM

22 21

1

2 3 4 5 6 7 8

10

9

11 12 13 14 15 16 17 18 19

20

23 24

12

D

C

CRITICAL

L6705

120-OHM-25%-1.3A

AUD_HP_PORT_R

7

53 54

B

IN

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.1MM

I2C ADDRESSES

MIKEY U6751 READ 0111 0011 0X73 MIKEY U6751 WRITE 0111 0010 0X72 CHS U6750 READ 0111 0111 0X77 CHS U6750 WRITE 0111 0110 0X76

59

AUD_TYPEDET

7

OUT

A

6 3

1 2

CRITICAL

L6706

FERR-470-OHM

1 2

0201

0402

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

AUD_CONN_TYPEDET

SYNC_MASTER=D2_CARA

PAGE TITLE

AUDIO: JACK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/16/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

67 OF 132

SHEET

58 OF 99

124578

SIZE

B

A

D

8 7 6 5 4 3

12

CODEC OUTPUT SIGNAL PATHS

FUNCTION HP/LINE OUT TWEETERS SUB SPDIF OUT

VOLUME 0X02 (2) 0X02 (2) 0X04 (4) 0X03 (3) N/A

CONVERTER

0X04 (4)

0X08 (8)

CODEC INPUT SIGNAL PATHS

D

FUNCTION DMIC 1 DMIC2 SPDIF IN HEADSET MIC

CONVERTER 0X06 (6) 0X05 (5) 0X07 (7) 0X06 (6)

SYSTEM INT AND GPIO LINES

59 53

OUT

FUNCTION MIKEY ENABLE MIKEY INTERRUPT PERIPHERAL DETECT

AUD_SENSE_A

INT

PIRQ H PIRQ F

C

59

IN

GND_AUDIO_CODEC

59 58 54 53

PP4V5_AUDIO_ANALOG

59 58 53

B

=PP3V3_S0_AUDIO

59

8

1

R6866

475K

1% 1/20W MF 201

2

R6892

IN

AUD_CONN_TIPDET_INV

58

A

NOM R6892-C6860 FC = 106Hz SSM6N15FE Vth = 0.8V to 1.5V SSM6N15FE IGSS = +/-1uA FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3)

1.5K

1 2

1% 1/16W MF-LF

402

AUD_TIPDET_INV

7

1

C6860

1UF

10%

2

APN:376S0613

Q6803

SSM6N15FEAPE

25V 402X5R

PIN COMPLEX 0X09 (9,A) 0X0B (11)

0X10 (16)

PIN COMPLEX 0X0E (D,E) 0X12 (12,C) 0X0F (15) N/A 0X0D (13,V22,B,LEFT)

GPIO SATA4GP/GPIO 16 GPIO 5 GPIO 3

MUTE CONTROL

N/A

GPIO_30X0A (10)0X03 (03) N/A

VREF

3V3 N/A MIKEY MIKEY

PORT B DETECT(SPDIF DELEGATE)

1

2

AUD_PORTA_DET_L

6

SOT563

2

D

SG

1

AUD_TYPEDET_OD_INV

R6867

0

1 2

5% 1/16W MF-LF

402

AUD_OUTJACK_INSERT_L

R6802

100K

12

5%

1/20W

MF

201

R6803

100K

12

5%

1/20W

MF

201

1

R6865

47K

5% 1/20W MF 201

2

Q6897

AUD_TIPDET_FET1

6

D

SOT563

2

SG

1

FERR-33-OHM-0.8A-0.09-OHM

CRITICAL

L6801

1 2

0201

59 58 54 53

DET ASSIGNMENT 0X09 (B) N/AGPIO_3 N/A 0X0C (A)

DET ASSIGNMENT N/A3V3 0X0C (12,C)

R6896

20.0K

1% 1/16W MF-LF 402

SSM6N15FEAPESSM6N15FEAPE

Q6800

DMC2400UV

SOT563

AUD_IP_PERIPHERAL_DET

EXTRACTION NOTIFICATION

Q6897

SSM6N15FEAPE

AUD_TIPDET_FET2

SOT563

5

1

C6891

1UF

25V

10%

2

402X5R

GND_AUDIO_CODEC

PORT A DETECT (HEADPHONES)

1

R6895

39.2K

1% 1/16W MF-LF 402

2

AUD_PORTB_DET_L

58

3

SOT563

5

Q6800

DMC2400UV

SOT563

6

D

N-CHN

S

1

D

SG

4

AUD_TYPEDET_OD

P-CHN

G

2

Q6896

AUD_OUTJACK_INSERT_L

3

D

SG

4

3

D

G

S

4

AUD_TYPEDET_OD

19

OUT

=PP3V3_S0_AUDIO

59

8

53

OUT

53

OUT

53

OUT

NC

59

OUT

PP4V5_AUDIO_ANALOG

1

R6801

150K

1% 1/20W MF 201

2

5

AUD_TYPEDET

PP4V5_AUDIO_ANALOG

C6800

59

IN

GND_AUDIO_CODEC

59

OUT

R6885

CON_DMIC_PWR

7

0

1 2

5% 1/16W MF-LF

402

R6884

0

AUD_DMIC_SDA1 CON_DMIC_SDA1

AUD_DMIC_SDA2

AUD_DMIC_CLK

59 53

8

59

7

IN IN

IN

1

0.1UF

PLACE_NEAR=Q6800.4

10%

6.3V 2

X5R 201

=PP5V_S4_AUDIO

59 53

8

1 2

=PP5V_S4_AUDIO

SPEAKERID

R6810

SPKRCONN_L_ID

R6812

SPEAKERID

58

7

59 58 53

59 58 54 53

SPEAKERID

R6814

SPEAKERID

R6815

90.9K

5% 1/16W MF-LF

402

R6886

R6883

100K

1/16W

MF-LF

100K

1/16W

MF-LF

274K

1/16W MF-LF

402

1/16W MF-LF

402

7

0

1 2

5% 1/16W MF-LF

402

0

1 2

5% 1/16W MF-LF

402

1

1%

402

2

1

1%

402

2

1

1%

2

1

1%

2

CON_DMIC_SDA2

7

CON_DMIC_CLK

7

Alternate Parts

PART NUMBER

353S3452 353S1286

ALTERNATE FOR PART NUMBER

BOM OPTION

SPEAKERID

1

R6811

100K

1% 1/16W MF-LF 402

2

SPKRCONN_R_ID

1

R6813

100K

1% 1/16W MF-LF 402

2

SPEAKERID

CRITICAL SPEAKERID

1

C6811

4.7UF

20% 10V

2

X5R-CERM 0402

=PP5V_S4_AUDIO

59 53

8

MCP6514_POS

MCP6514_NEG

REF DES

U6800

COMMENTS:

MAXIM ALT TO MICROCHIP

6 3

3-MIC CONNECTOR

CRITICAL

J6801

FF14A-5C-R11DL-B-3H

NC

59

7

3

4

SPEAKERID

F-RT-SM

6

1 2 3 4 5

7

SPEAKERID

R6816

100K

1 2

1% 1/16W MF-LF

402

R6817

45.3K

1 2

1% 1/16W MF-LF

402

SPEAKERID CRITICAL

U6800

5

MCP6541T SC70-5

2

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SPEAKERID

1

C6810

0.1UF

10%

6.3V

2

X5R 201

1

MCP6514_OUT

SPEAKER CONNECTOR

HP=80HZ

APN: 518S0627

7

IN

7

IN

59

7

IN

7

IN

7

IN

7

IN

7

IN

59

7

IN

7

IN

7

IN

FERR-1000-OHM

SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N

SPKRCONN_L_ID

SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N

SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N

SPKRCONN_R_ID

SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N

SPEAKERID

L6802

1 2

0402

SPKR_MATCH_DRV_R

PORT C DETECT(SPEAKER MISMATCH)

59 53

SPEAKERID

R6820

33

1 2

5% 1/16W MF-LF

402

59 58 54 53

96 57

AUDIO CONNECTOR DETECT STATES

AUD_J1_TYPEDET_R 1 1 0

AUD_J1_TIPDET_R 0 1 1

AUD_OUTJACK_INSERT_L 1 0 0

AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV

NOTHING SPDIF HEADPHONE

SYNC_MASTER=D2_CARA

PAGE TITLE

AUDIO: JACK TRANSLATORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

78171-6006

AUD_SENSE_A

OUT

AUD_PORTC_DET_L

NC

SPEAKERID

Q6896

SSM6N15FEAPE

SPKR_MATCH_DRV

GND_AUDIO_CODEC

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

CRITICAL

J6802

M-RT-SM

7

1 2 3 4 5 6

8

CRITICAL

J6803

M-RT-SM

7

1 2 3 4 5 6

8

SPEAKERID

1

R6894

10K

1% 1/16W MF-LF

402

2

D

SOT563

2

SG

SYNC_DATE=03/16/2012

051-9589

4.18.0

68 OF 132

59 OF 99

D

C

6

B

1

A

SIZE

D

8 7 6 5 4 3

12

MagSafe DC Power Jack

PP18V5_DCIN_FUSE

CRITICAL

J6900

WTB-PWR-M82

D

M-RT-SM

518S0508

1 2 3 4 5 6

C

7

MIN_LINE_WIDTH=1MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

TDM_ONEWIRE_MPM

7

C6900

0.1UF

ADAPTER_SENSE

7

1-Wire OverVoltage Protection

1

C6905

0.01UF

20% 50V

2

CERM 0603

SMC_BC_ACOK_VCC

1

CERM

20% 10V

2

402

1

VCC

U6900

MAX9940

SC70-5

5

EXT INT

CRITICAL

NC

GND

2

3

4

NC

The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is

connected.

R6929

2.0K

1/16W MF-LF

5%

402

CRITICAL

F6905

6AMP-32V-0.0095OHM

1 2

0603

CRITICAL

U6901

TC7SZ08FEAPE

SOT665

4

1

2

SYS_ONEWIRE

Y

=PP18V5_DCIN_ISOL

8

=PP18V5_DCIN_CONN

8

苹果笔记本维修交流群群号：325742634

TDM LEVEL SHIFT

D

=PP3V42_G3H_ONEWIREPROT

1

C6908

0.1UF

20%

PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

10V

2

CERM

5

3

BI

402

2

SMC_BC_ACOK

A

1

B

41

Q6910

SI5419DU

POWERPAK

D

1

DCIN_ISOL_GATE_R

8

41 42

IN

41

BI

1

R6912

22.1K

1% 1/20W MF 201

2

5A

S

5

G

1

C6912

4

0.047UF

10% 25V

2

X5R 0402

R6911

10K

1 2

1/20W

201

TDM:MPM

1

R6977

22

5%

1/20W

MF

201

2

TDM:MLB

R6976

SYS_TDM_ONEWIRE

Input impedance of 22.1K meets sparkitecture requirements for 15" MBP design only

1

R6910

100K

5% 1/20W MF 201

2

5% MF

1 2

When input voltage is 2V the FET will be off blocking the leakage path and 22.1K can be properly detected.

When input voltage is at 16V+, FET will conduct and power charger and 3.42V reg

22

1/20W

201

5% MF

=PP3V42_G3H_TDM

8

TDM_ONEWIRE_MLB

TDM:MLB

R6975

2.21K

1/20W

TDM_RX_D

TDM_RX

1

1% MF

201

2

IN_A

4

IN_B1

7

IN_B2

TDM:MLB

VDD

U6970

SLG4AP030

TDFN

CRITICAL

GND

5

1

6

OUT_C

3

OUT_D1

8

OUT_D2

THRM

PAD

9

TDM_PD_BASE_R

K

A

TDM:MLB

1

R6973

24.9K

1% 1/20W MF 201

2

TDM:MLB

1

R6974

6.34K

1% 1/20W MF 201

2

TDM:MLB CRITICAL

D6970

DDZ9694T

SOD523

TDM_PD_BASE

TDM:MLB

1

R6972

54.9

1% 1/20W MF 201

2

DCIN_ISOL_GATE

K

D6910

6.8V Zener

GDZT2R6.8

A

GDZ-0201

LAYOUT NOTE:

Q0220 NEEDS 10 SQ CM

OF 1 OZ CU FOR THERMAL

TDM:MLB CRITICAL

MMBT2222AM3T5G

Q6971

SOT723

3

1

2

1

TDM:MLB

1

R6971

12.1

1% 1/8W MF-LF 805

2

TDM:MLB CRITICAL

Q6970

ZXTN619MA

DFN

3

TDM_PD_DS

1

2

TDM:MLB

R6970

12.1

1% 1/8W MF-LF 805

C

1

2

BAT30CWFILM

C6993

4.7UF

X5R-CERM

0603

CRITICAL

D6905

SOT-323

1

2

1

10% 35V

2

3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

NOSTUFF

1

C6996

4.7UF

10% 35V

2

X5R-CERM

0603

NOSTUFF

C6997

4.7UF

X5R-CERM

0603

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

6

3

BOOST

1

10% 35V

2

VIN

U6990

LT3470AED

8 4

SHDN*

CRITICAL

7

NC

DFN

GND

SW

BIAS

FB

THRM

PAD

5

9

2

1

P3V42G3H_BOOST

DIDT=TRUE

1

C6994

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

P3V42G3H_FB

0.22UF

10% 10V

CERM

402

2

33UH-20%-0.39A-0.435OHM

1

C6995

22PF

5% 50V

2

NP0-C0G-CERM 0201

CRITICAL

1 2

Vout = 1.25V * (1 + Ra / Rb)

L6995

DP418C-SM

<Ra>

R6995

348K

1/20W

<Rb>

R6996

200K

1/20W

1

1%

MF

201

1

2

1

1%

MF

201

2

=PP3V42_G3H_REG

Vout = 3.425V 100MA MAX OUTPUT (Switcher limit)

C6999

22UF

20%

6.3V X5R-CERM-1 603

苹果笔记本维修交流群群号：325742634

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8

SYNC_DATE=01/13/2012

DC-In & Battery Connectors

Apple Inc.

R

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

69 OF 132

SHEET

60 OF 99

4.18.0

SIZE

B

A

D

124578

R6920

47

1 2

1%

1/3W

MF

1 2

C6990

X5R-CERM

1

3

805

R6905

10

5%

1/8W

MF-LF

805

10% 35V

0603

2

B

BATTERY CONNECTOR

518-0376

CRITICAL

J6950

BAT-J5

F-ST-TH

POS POS POS POS

NC NC

SCL SDA

SYS_DETECT

NEG NEG NEG NEG

=PPBUS_G3H

8

61

112 213 314 415 516 617 718 819 920 1021 1122

PPVBAT_G3H_CONN

7

61

=SMBUS_BATT_SCL =SMBUS_BATT_SDA SYS_DETECT_L

7

C6950

0.1UF

CRITICAL

D6950

1

C6960

10% 25V X5R 402

1UF

2

603-1

RCLAMP2402B

1

10% 25V

2

X5R

SC-75

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

1

C6991

4.7UF4.7UF

2

X5R-CERM

PP18V5_DCIN_CONN_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

NOSTUFF

1

C6992

4.7UF

10% 35V

2

44

1

R6950

10K

5% 1/16W MF-LF 402

2

X5R-CERM

0603

10% 35V

A

6 3

8 7 6 5 4 3

CRITICAL

Q7080

IRF9395TRPBF

DIRECTFET-MC

NC

415

879

C7085

0.1UF

10% 25V X5R 402

SOT-323

Inrush Limiter

1

R7085

470K

1% 1/16W MF-LF

402

2

3

CHGR_DCIN_D_R

61

12

13 11

10

18 17

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

1

R7086

332K

1% 1/16W MF-LF

402

2

R7001

4.7

1 2

1/16W MF-LF

402

VDD VHST SMB_RST_N SCL

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG CSOP CSON

(AGND)

R7005

20

1 2

5% 1/16W MF-LF

402

PP5V1_CHGR_VDDP

61

MIN_LINE_WIDTH=0.2 mm

5%

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

19

20

VDDP

DCIN

CRITICAL

SGATE

U7000

AGATE

TQFN

CSIP CSIN

BOOT

ISL6259

UGATE PHASE

LGATE

BGATE

AMON

20V/V

BMON

36V/V

ACOK

(OD)

THRM_PAD

PGND

353S2392

22

29

XW7000

SM

1 2

PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm

(CHGR_AGATE)

(CHGR_DCIN)

C7001

2

CHGR_DCIN

61

26

CHGR_SGATE

1

CHGR_AGATE

28

CHGR_CSI_P

94

27

CHGR_CSI_N

94

25

CHGR_BOOT

24

CHGR_UGATE

23

CHGR_PHASE

21

CHGR_LGATE

MIN_LINE_WIDTH=0.6 mm

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

S

D

G

6

1

1UF

10% 10V

2

X5R 402

FROM ADAPTER

=PPDCIN_S5_CHGR

8

D

=PPDCIN_S5_CHGR_ISOL

8

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V Sparkitecture impedance is set by R6912 in 15" MBP

=PP3V42_G3H_CHGR

8

70

1

C

1

2

1

2

B

R7012

1/16W MF-LF

R7010

130K

1% 1/16W MF-LF 402

R7011

40.2K

1% 1/16W MF-LF 402

1

1K

1%

402

2

SMC_RESET_L

IN

1

R7015

330K

5% 1/16W MF-LF 402

2

CHGR_VCOMP_R

1

R7042

0

5% 1/16W MF-LF 402

2

CHGR_VNEG_R

1

C7016

470PF

10% 50V

2

CERM 0402

C7002

C7015

220PF

X7R-CERM

0402

R7016

3.01K

1/16W MF-LF

1UF

10% 10V X5R 402

GND_CHGR_AGND

R7000

1 2

5% 1/16W MF-LF

402

1

10% 50V

2

1

1%

402

2

61

0

44

IN

44

BI

70

IN

94

1

2

1

2

CRITICAL

D7005

BAT30CWFILM

1

2

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5.1V

NO STUFF

1

R7002

100K

5% 1/16W MF-LF 402

2

CHGR_RST_L =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA CHGR_VFRQ CHGR_CELL

CHGR_ACIN

CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N

C7050

1UF

10% 16V X5R 402

2

S

3

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

OUT OUT OUT

NC

10

D

G

(CHGR_SGATE)

46

42 45

NC

NO STUFF

For EMC

1

C7080

4.7UF

10% 25V

2

X5R-CERM 0603

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

1

C7020

0.047UF

10% 10V

2

X5R-CERM 0402

C7022

0.1UF

10% 25V X5R 402

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

1

C7021

0.1UF

10% 25V

2

X5R 402

1

C7025

0.22UF

10% 10V

2

CERM 402

PLACE_NEAR=U7000.25:2mm

4

Reverse-Current Protection

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

1

R7080

100K

5% 1/16W MF-LF 402

2

1

R7081

62K

5% 1/16W MF-LF 402

2

R7021

10

1 2

5% 1/16W MF-LF

402

R7022

10

1 2

5% 1/16W MF-LF

402

5

1 2 3

4

CRITICAL

Q7035

R7051 R7052

96

G

RJK0305DPB

LFPAK-HF

2.2

0

CHGR_ICOMP_RC

1

2

C7042

0.068UF

10% 10V X5R-CERM 0402

C7011

0.01UF

X7R-CERM

0402

10% 16V

1

C7000

1UF

10% 10V

2

X5R 402-1

C7005

0.22UF

X5R-CERM

0603-1

1

10% 50V

2

61

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

C7026

0.001UF

X7R-CERM

0402

1

10% 50V

2

61

CHGR_CSI_R_P

CHGR_CSI_R_N

5

CRITICAL

D

S

1 2 3

1 2

CHGR_DCIN_D_R

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

Q7030

RJK0332DPB-01

LFPAK-SM

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_CSO_R_P

96

1/16W MF-LF

5%

CHGR_CSO_R_N

96

1/16W MF-LF

5%

(PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

CHGR_5V:LDO

R7092

1 2

MF-LF

1/16W

CRITICAL

214

R7020

0.020

0.5% 1W MF-LF 0612

3

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

Max Current = 8A (L7030 limit) f = 400 kHz

402

MIN_NECK_WIDTH=0.25 mm

402

C7090

X5R-CERM

MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

1

4.7UF

10% 35V

2

0805

0

5%

NC

1

2

CRITICAL

4.7UH-20%-14.5A-9MOHM

L7030

1 2

PIME173T-SM

152S1466

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

CRITICAL

R7050

0.005

1% 1W MF

0612

2 1 4 3

6

VIN

U7090

LT3470A

DFN

8 4

SHDN*

CRITICAL

7

NC

GND

5

CRITICAL

C7030

10UF

20% 35V TANT-POLY CASE-D2-SM

CRITICAL

1

C7031

10UF

20% 35V

2

TANT-POLY CASE-D2-SM

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.6V

For Erp Lot6 spec

P5V1_BOOST

DIDT=TRUE

3

BOOST

THRM

PAD

BIAS

9

SW

2

1

FB

C7094

0.22UF

P5V1_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

P5V1_FB

Vout = 1.25V * (1 + Ra / Rb)

CRITICAL

1

C7032

10UF

20% 35V

2

TANT-POLY CASE-D2-SM

C7055

1UF

603-1

1

2

10% 25V X5R

CRITICAL

1

C7033

10UF

20% 35V

2

TANT-POLY CASE-D2-SM

OMIT_TABLE CRITICAL

C7040

68UF

20% 16V POLY-TANT CASE-D2E-SM

1

C7056

2

X7R-CERM

0.1UF

0402

10% 10V

CERM

402

10% 16V

1

2

33UH-20%-0.39A-0.435OHM

1 2

P5V1_BIAS

1

C7095

22PF

5% 50V

2

NP0-C0G-CERM 0201

CRITICAL

1

C7034

10UF

20% 35V

2

TANT-POLY CASE-D2-SM

8AMP-32V-0.006OHM

1

C7045

0.001UF

10% 50V

2

X7R-CERM 0402

1

C7057

0.01UF

10%

X7R-CERM

0402

16V

2

CRITICAL

L7095

DP418C-SM

CRITICAL

F7040

1 2

CRITICAL

F7041

1 2

1

2

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

<Ra>

R7095

681K

<Rb>

R7096

200K

CRITICAL

1

C7035

1UF

10% 35V

2

X5R 603

0603

1 2 3

1%

1/20W

MF

201

1%

1/20W

MF

201

CRITICAL

Q7055

SI7137DP

S

G

4

NO STUFF

CRITICAL

R7055

0.001

2 1 4 3

(P5V1_BIAS)

CHGR_5V:LDO

1 2

MF-LF

CRITICAL

1

C7098

10UF

1

20% 10V

2

X5R 0603

2

1

2

CRITICAL

1

C7036

1UF

10% 35V

2

X5R 603

CRITICAL

1

C7099

10UF

20% 10V

2

X5R

Vout = 5.50V

0603

100MA MAX OUTPUT (Switcher limit)

1

C7037

0.001UF

10% 50V

2

X7R-CERM 0402

TO SYSTEM

=PPBUS_G3H

SO-8

0612

1% 1W MF

TO/FROM BATTERY

D

PPVBAT_G3H_CONN

5

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

MF-LF

R7091

0

5%

1/16W

12

NOSTUFF

R7090

0

1 2

402

5%

1/16W

PP5V1_CHGR_VDDP

402

CHGR_DCIN

60

8

7

60

61

D

C

B

A

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

70 OF 132

SHEET

61 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

SIZE

D

C

B

A

D

=PPVIN_S0_VCCSAS0

8

=PP5V_S0_VCCSAS0

8

1

R7101

2.2

5% 1/16W MF-LF

402

EN

FB

SREF

VO

OCSET

PGOOD

4

RTN

FSEL

8

SET0

9

SET1

6

VID0

5

VID1

2

19

VCC

U7100

ISL95870AH

CRITICAL

(ENDIAN SWAP)

GND

3

XW7100

SM

1 2

PLACE_NEAR=U7100.3:1mm

PP5V_S0_VCCSAS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

C

IN

2

SM

1

CPU_VCCSASENSE

VCCSAS0_RTN

89 13

XW7101

B

R7153

1.62K

1 2

1% 1/16W MF-LF

402

R7151

1.62K

1 2

1/16W MF-LF

1

C7106

10PF

5% 50V

2

C0G-CERM 0402

1%

402

C7103

0.022UF

10% 16V

X5R-X7R-CERM

0402

1

R7154

4.64K

1% 1/16W MF-LF 402

2

1

R7152

4.64K

1% 1/16W MF-LF 402

2

1

C7105

10PF

5% 50V

2

C0G-CERM 0402

1

2

1

R7147

41.2K

1% 1/16W MF-LF 402

2

1

R7148

52.3K

1% 1/16W MF-LF 402

2

R7150

82.5K

1 2

1% 1/16W MF-LF

402

VCCSAS0_SET_R

1

R7149

499K

1% 1/16W MF-LF 402

2

70

1

2

IN

OUT

C7102

2.2UF

10% 16V X5R 603

R7103

1/16W MF-LF

89 13

0

5%

402

IN IN

=PVCCSA_EN

CPU_VCCSASENSE_DIV

VCCSAS0_SREF

VCCSAS0_VO

VCCSAS0_OCSET

PVCCSA_PGOOD

VCCSAS0_RTN_DIV

VCCSAS0_FSEL

VCCSAS0_SET0

VCCSAS0_SET1

1

2

CPU_VCCSA_VID<1> CPU_VCCSA_VID<0>

VCCSAS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

10

7

12

11

14

13

INTEL TABLE:

VID1 VID0 Voltage

0 0 0.9V

1 0 0.8V

0 1 0.725V

1 1 0.675V

fb = (R7151+R7152)/R7152 = 1.349 and Vref = 0.5; VID1=1, VIC0=1:

Vout<1,1> = Vref x fb; VID1=0, VID0=1:

Vout<0,1> = Vref x (1+R7147 / (R7148 + R7149 )) x fb VID1=1, VID0=0

Vout<1,0> = Vref x (1+ (R7147 + R7148) / R7149 )) x fb VID1=0, VID0=0

Vout<0,0> = Vref x (1+ (R7147 / (R7148 + R7149 // R7150 )) x fb

UTQFN

20

PVCC

PGND

2

1

2

BOOT

UGATE

PHASE

LGATE

C7101

10UF

20% 10V X5R 603

1815

17

16

1

VCCSAS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

VCCSAS0_VBST

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

VCCSAS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

VCCSAS0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

VCCSAS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

(VCCSAS0_OCSET)

(VCCSAS0_VO)

R7130

1/10W MF-LF

CRITICAL

C7119

2

10UF

X5R-CERM

376S0944

1

C7130

1

0.22UF

0

5%

603

10% 10V

2

CERM 402

2

1

6

1

20% 25V

2

0603

CRITICAL

Q7100

RJK0222DNS

HWSON

7

CRITICAL

1

C7120

10UF

20% 25V

2

X5R-CERM

0603

CRITICAL

L7100

1.0UH-7A

1 2

PIMB053T-SM

152S1302

3 4 5

96 45

C7140

1000PF

5%

25V

NP0-C0G

402

96 45

12

R7141

1.5K

1/16W MF-LF

1

1%

402

2

A

6 3

PLACE_NEAR=Q7100.2:1.5mm

1

C7121

0.1UF

10% 16V

2

X7R-CERM

0402

PPVCCSA_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

VCCSAS0_CS_P

VCCSAS0_CS_N

1

R7142

1.5K

1% 1/16W MF-LF 402

2

1

C7122

1000PF

5% 25V

2

NP0-C0G 402

CRITICAL

R7140

0.001

1%

1W MF-1 0612

2 1 4 3

OCP = R7141 x 8.5uA / R7140 OCP = 8.5A

=PPVCCSA_S0_REG

6A Max Output f = 300 kHz

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

System Agent Supply

Apple Inc.

R

99

8

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

71 OF 132

SHEET

62 OF 99

124578

8 7 6 5 4 3

12

D

VOUT = 5.0V 11A MAX OUTPUT F = 400 KHZ

C

CRITICAL

C7254

150UF

20%

6.3V

POLY-TANT

CASE-B2-SM

B

=PP5V_S4_REG

63

=PPVIN_S5_P5VP3V3

8

CRITICAL CRITICAL CRITICAL CRITICAL

1

C7240

68UF

20% 16V

2

POLY-TANT

CASE-D2E-SM

=PP5V_S4_REG

63

8 8

CRITICAL

1

2

NOSTUFF

1

C7253

150UF

20%

6.3V

2

POLY-TANT CASE-B2-SM

CRITICAL

C7252

330UF

POLY-TANT

CASE-D3L-SM

1

2

1

2

1

20%

6.3V

2

P5VS4_VFB1_R

R7220

40.2K

1% 1/16W MF-LF 402

R7221

10K

1% 1/16W MF-LF 402

1

C7271

0.001UF

10% 50V

2

X7R-CERM 0402

CRITICAL

C7250

10UF

XW7222

20% 10V X5R 805

XW7220

1

2

PLACE_NEAR=L7220.1:3MM

2

SM

1

PLACE_NEAR=L7220.1:3MM

2

SM

1

C7242

68UF

20% 16V

2

POLY-TANT

CASE-D2E-SM

1

152S0688

CRITICAL

L7220

1.0UH-21A-0.006OHM

PCMB103T-1R0MS

2

P5VS4_VSW

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

NO STUFF

1

R7299

1

5% 1/10W MF-LF 603

2

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

PLACE_NEAR=L7220.2:3MM

2

XW7221

SM

1

P5VS4_CSP1_R

1

C7241

2

1UF

10% 25V X5R 603-1

NO STUFF

C7299

0.0033UF

X7R-CERM

1

C7270

0.001UF

10% 50V

2

X7R-CERM 0402

CRITICAL

CSD58872Q5D

VIN

1

VSW

6 7 8

PGND

1

10% 50V

2

0402

Q7220

SON5X6

9

TG

TGR

BG

R7256

3.92K

1/16W MF-LF

3

4

5

1

1%

402

2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

1

C7224

0.1UF

10% 50V

2

X7R 603-1

P5VS4_TG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

C7218

0.1UF

1 2

10% 16V

X7R-CERM

0402

R7247

3.24K

1 2

1% 1/16W MF-LF

402

1

C7200

1UF

10% 25V

2

X5R

603-1

SKIP_5V3V3:INAUDIBLE

SKIP_5V3V3:AUDIBLE

R7200

1

R7244

1

5% 1/16W MF-LF

402

2

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

1

2

1

C7237

150PF

5%

50V

2

C0G-CERM

0402

1

0

5%

1/20W

MF

201

2

70

IN

70

OUT

R7237

10K

1% 1/16W MF-LF 402

P5VS4_COMP1_R

1

C7236

4700PF

10% 100V

2

CERM 402

(P5VP3V3_VREF2)

8

1

R7201

0

5%

1/20W

MF

201

2

P5VP3V3_SKIPSEL

P5VS4_VBST

DIDT=TRUE

P5VS4_DRVH

DIDT=TRUE

P5VS4_LL

DIDT=TRUE

P5VS4_DRVL

DIDT=TRUE

P5VS4_CSP1 P5VS4_CSN1

P5VS4_VFB1 P5VS4_COMP1

=P5VS4_EN P5VS4_PGOOD

R7236

12.1K

1/16W MF-LF

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

=PP5V_S5_LDO

VOUT = 5V 100MA MAX OUTPUT

1

C7205

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

1

10K

1% 1/16W MF-LF

402

2

1

2

10UF

20%

6.3V

2

X5R 603

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

R7263

0

1 2

5% 1/16W MF-LF

402

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

R7206

249K

1/16W MF-LF

402

1

C7239

47PF

5% 50V

2

CERM 402

P5VP3V3_VREG3

P5VP3V3_VREF2

2

23

29

VIN

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

1

32

30

DRVL1

7

CSP1

8

11

MODE

9

VFB1 VFB2

10

4 5

VREG5

CRITICAL

U7201

QFN

GND

1

1%

402

2

28

XW7200

PLACE_NEAR=U7200.28:1MM

2

SM

1

22

VREG3

TPS51980

THRM_PAD

33

PGOOD2PGOOD1

13

VREF2

VBST2VBST1

DRVH2DRVH1

DRVL2

CSP2 CSN2CSN1

COMP2COMP1

C7201

0.22UF

10% 10V

CERM

402

=P5VS5_EN

12

EN

P3V3S5_VBST

26

DIDT=TRUE

P3V3S5_DRVH

24

DIDT=TRUE

P3V3S5_LL

25

SW2SW1

DIDT=TRUE

P3V3S5_DRVL

27

DIDT=TRUE

P3V3S5_CSP2

18

P3V3S5_CSN2

17

P3V3S5_RF

3

RF

EN2EN1

16 15

21

20

P3V3S5_VFB2 P3V3S5_COMP2

=P3V3S5_EN P3V3S5_PGOOD

1

R7238

12.1K

1% 1/16W MF-LF 402

2

P3V3S5_COMP2_R

(P5VP3V3_VREF2)

1

2

GATE_NODE=TRUE

C7238

1

C7203

2.2UF

20% 10V

2

X5R-CERM 402

IN

SWITCH_NODE=TRUE

GATE_NODE=TRUE

IN

OUT

4700PF

100V CERM

70

R7239

10%

402

P3V3S5_TG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

1

1%

2

8

C7264

0.1UF

C7288

0.1UF

1 2

10% 16V

X7R-CERM

0402

R7246

1.43K

1 2

1% 1/16W MF-LF

402

603-1

10% 50V X7R

1

2

1

6

1

R7216

3.83K

1% 1/16W MF-LF 402

2

P3V3S5_CSP2_R

2

3 4 5

CRITICAL

Q7260

RJK0214DPA

WPAK2

7

P3V3S5_SNUBR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

NO STUFF

1

C7298

0.001UF

10% 50V

2

X7R-CERM 0402

C7280

POLY-TANT

CASE-D2E-SM

NO STUFF

68UF

20% 16V

152S0754

1.0UH-22A

R7298

10

1/10W MF-LF

603

OMIT_TABLEOMIT_TABLEOMIT_TABLE OMIT_TABLE

1

2

CRITICAL

L7260

PCMC063T-SM

1

5%

2

XW7260

C7282

68UF

20% 16V

POLY-TANT

CASE-D2E-SM

12

PLACE_NEAR=L7260.1:3MM

2

SM

1

C7281

1UF

10% 25V

2

X5R 603-1

=PP3V3_S5_REG

VOUT = 3.3V 10A MAX OUTPUT F = 400 KHZ

1

C7290

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=L7260.2:3MM

2

XW7262

SM

1

PLACE_NEAR=L7260.2:3MM

P3V3S5_VFB2_R

2

XW7261

SM

1

C7272

0.001UF

X7R-CERM

10% 50V

0402

1

2

R7260

R7261

C7283

0.001UF

10% 50V X7R-CERM 0402

1

2

23.2K

1/16W MF-LF

402

10K

1/16W MF-LF

402

CRITICAL

C7293

POLY-TANT

CASE-B2-SM

CRITICAL

1

C7292

330UF

20%

6.3V

2

POLY-TANT CASE-D3L-SM

1

1%

2

1

1%

2

150UF

6.3V

D

1

C

20%

2

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

5V / 3.3V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

72 OF 132

SHEET

63 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PPVIN_S0_DDRREG_LDO

8

=PP5V_S3_DDRREG

8

1

C7300

10UF

20% 10V

2

X5R 603

C

=DDRVTT_EN

9

27

IN

=DDRREG_EN

70

IN

OMIT_TABLE

1

2

1

2

IN

R7315

20.0K

1% 1/16W MF-LF 402

OMIT_TABLE

R7316

100K

1% 1/16W MF-LF 402

18

1

C7316

2

0.01UF

10% 16V X7R-CERM 0402

1

R7317

200K

2

1

C7315

0.1UF

10% 16V

2

X7R-CERM

0402

NOSTUFF

1

R7319

150K

1% 1/16W MF-LF

402

1

G S

2

3

D

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

2

VOLTAGE=0V

DDRREG_P1V35_L

Q7319

SSM3K15FV

SOD-VESM-HF

NOSTUFF

B

MEM_VDD_SEL_1V5_L

(VTT Enable)

(VDDQ/VTTREF Enable)

DDRREG_1V8_VREF

33

1% 1/16W MF-LF 402

DDRREG_FB

DDRREG_MODE

DDRREG_TRIP

1

R7318

61.9K

1% 1/16W MF-LF 402

2

1

C7301

10UF

20% 10V

2

X5R 603

2

VLDOIN

12 15

V5IN

S3 S5

VREF

REFIN

MODE TRIP

PGND

10

U7300

TPS51916

CRITICAL

GND

7

17

16

6

8

19

18

QFN

VTT

4

VBST DRVH

DRVL

PGOOD

VDDQSNS

VTTSNS

VTTREF

THRM

PADGND

21

XW7300

SW

VTT

2

SM

1

DDR3 (1V5R1V35 S3) REGULATOR

=PPVIN_S3_DDRREG

8

CRITICAL

1

C7330

68UF

20% 16V

2

POLY-TANT

CASE-D2E-SM

(DDRREG_DRVH)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

=PPVTT_S3_DDR_BUF

C7350

0.22UF

10% 10V

CERM

402

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

C7360, C7361 close to memory

1

2

88

OUT

XW7360

SM

1 2

PLACE_NEAR=C7361.1:3mm

8

33

C7360

10UF

PLACE_NEAR=C3101.1:1mm

6.3V

20% X5R

603

(DDRREG_LL)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

1

C7361

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=C3101.1:3mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

14 13

11 20

9

8

3 1

5

DDRREG_VBST

DDRREG_DRVH

GATE_NODE=TRUE

DDRREG_LL

SWITCH_NODE=TRUE

DDRREG_DRVL

GATE_NODE=TRUE

DDRREG_PGOOD

DDRREG_VDDQSNS

=PPVTT_S0_DDR_LDO

DDRREG_VTTSNS

10mA max load

PLACE_NEAR=U7300.7:1mm

OMIT_TABLEOMIT_TABLE

CRITICAL

C7331

POLY-TANT

CASE-D2E-SM

R7330

1

1 2

5% 1/16W MF-LF

402

C7325

0.1UF

1 2

10% 50V X7R

603-1

68UF

20% 16V

1

2

DDRREG_DRVH_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

1

C7332

1UF

10% 25V

2

X5R 603-1

1

C7333

0.001UF

10% 50V

2

X7R-CERM 0402

CSD58872Q5D

TG

3

TGR

4

BG

5

CRITICAL

Q7330

SON5X6

1

C7334

1UF

10% 25V

2

X5R 603-1

VIN

1

VSW

6 7 8

DDRREG_VSW

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

PGND

9

MIN_NECK_WIDTH=0.17 mm

CRITICAL

L7330

0.68UH-18A-3.3MOHM

1 2

PCMB103T

152S0905

CRITICAL

1

C7340

270UF

20% 2V

2

TANT CASE-B4-SM

CRITICAL

C7341

270UF

CASE-B4-SM

=PPDDR_S3_REG

Vout = 1.5V 18A max output

1

C7346

0.001UF

10% 50V

2

X7R-CERM

1

C7345

10UF

20%

2V

TANT

20%

6.3V

2

X5R 603

0402

2

XW7301

SM

PLACE_NEAR=C7340.1:1MM

1

(Q7335 limit) f = 400 kHz

8

D

C

B

PART NUMBER

114S0343

114S0342

114S0411

114S0389

QTY

1

DESCRIPTION

RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF

RES,MTL FILM,1/16W,19.6K,1,0402,SMD,LF

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

RES,MTL FILM,1/16W,57.6K,1,0402,SMD,LF

A

REFERENCE DES

R7315

R7316

6 3

CRITICAL

BOM OPTION

PPDDR:1V5

PPDDR:1V35

PPDDR:1V5

PPDDR:1V35

SYNC_MASTER=D2_KEPLER

PAGE TITLE

1V5R1V35V DDR3 SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

73 OF 132

SHEET

64 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

97 66 46

C

97 66 46

66

B

1

C7403

2

65

2.2UF

20% 10V X6S-CERM 0402

=PP5V_S0_CPUIMVP

R7402

182K

1 2

1%

1/20W

66

MF

201

66

NO STUFF

1

C7414

100PF

5% 25V

2

NP0-CERM 0201

D

R7401

10

PP5V_S0_CPUIMVP_VCC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

C

1

R7468

5.76K

1% 1/20W MF 201

2

1

CRITICAL

R7469

100KOHM

0402

B

2

1

R7466

5.76K

1% 1/20W MF 201

2

1

2

CRITICAL

R7467

100KOHM

0402

=PPVCCIO_S0_CPUIMVP

8

70

IN

89 13

BI

89 13

IN

89 13

OUT

NO STUFF

1

R7464

200K

1% 1/20W MF 201

2

1

R7465

200K

1% 1/20W MF 201

2

PLACE_NEAR=U7400.18:2mm

CPUIMVP_VR_ON

CPU_VIDSOUT CPU_VIDSCLK CPU_VIDALERT_L

1

R7462

301K

1% 1/20W MF 201

2

1

R7463

137K

1% 1/20W MF 201

2

R7479

54.9

1/20W

1

R7480

130

1%

1/20W MF

MF

201

2

PLACE_NEAR=U7400.16:2mm

89 42 41 11

1

R7460

301K

1% 1/20W MF 201

2

1

R7461

137K

1% 1/20W MF 201

2

66

66 65

70

88

CPUIMVP_NTC CPUIMVP_NTCG

CPUIMVP_SLEW

CPUIMVP_AXG_PWM2

OUT

CPUIMVP_PWM3

OUT

CPUIMVP_ISUM3P

IN

CPU_PROCHOT_L

OUT

CPUIMVP_PGOOD

OUT

CPUIMVP_AXG_PGOOD

OUT

CPUIMVP_IMAXA CPUIMVP_IMAXB

C7401

2.2UF

X6S-CERM

1

20% 10V

2

0402

13

DRVPWMB

37

DRVPWMA

45

CSPA3

4

VRHOT*

24

POKA

12

POKB

47

EN

21

VDIO

23

CLK

22

ALERT*

39

THERMA

40

THERMB

38

SR

35

IMAXA

36

IMAXB

8

CSPBAVE

AGND

5

1 2

462919

VCC

VDDA

U7400

MAX15119GTM

QFN

CRITICAL

GNDSB

GNDSA

2

7

20

5% 1/16W MF-LF

402

49

THRM

VDDB

TONB

TONA

BSTA1

DHA1 LXA1 DLA1

CSPA1

CSPAAVE

CSNA

CSPA2 BSTA2

DHA2 LXA2 DLA2

BSTB

CSPB2

CSPB1

CSNB

PAD

PGNDA

30

66

FBA

DHB LXB DLB

FBB

PGNDB

17

XW7400

1

48

25

27

26 28 42

41 43 3

44 34 32 33 31

14 16 15 18

11 9 10 6

SM

CPUIMVP_TONB

CPUIMVP_TONA

CPUIMVP_BOOT1 CPUIMVP_UGATE1 CPUIMVP_PHASE1 CPUIMVP_LGATE1 CPUIMVP_ISUM1P

CPUIMVP_ISUM CPUIMVP_ISUMN CPUIMVP_FBA

CPUIMVP_ISUM2P CPUIMVP_BOOT2 CPUIMVP_UGATE2 CPUIMVP_PHASE2 CPUIMVP_LGATE2

CPUIMVP_BOOT1G CPUIMVP_UGATE1G CPUIMVP_PHASE1G CPUIMVP_LGATE1G

CPUIMVP_FBB

1

12

2

1

C7402

2.2UF

20% 10V

2

X6S-CERM 0402

PLACE_NEAR=U7400.24:2mm PLACE_NEAR=U7400.15:2mm

R7403

182K

1 2

1%

1/20W

MF

201

NO STUFF

C7418

100PF

5% 25V NP0-CERM 0201

1

2

NO STUFF

C7419

100PF

5% 25V NP0-CERM 0201

OUT OUT OUT OUT

1

2

NO STUFF

C7415

100PF

5% 25V NP0-CERM 0201

66

8

=PPVIN_S0_CPUIMVP

66

8

SIGNAL_MODEL=EMPTY

R7406

300

1 2

1

C7416

100PF

5% 25V

2

NP0-CERM 0201

NO STUFF

OUT

66

OUT

CPUIMVP_ISUM3P

NO STUFF

1

C7417

100PF

5% 25V

2

NP0-CERM 0201

SIGNAL_MODEL=EMPTY

66

C7408

150PF

1 2

X7R-CERM

0201

66 65

CPUIMVP_ISUM_R

10% 25V

NO STUFF

C7409

470PF

1 2

10% 16V

X5R-X7R-CERM

0201

SIGNAL_MODEL=EMPTY

NO STUFF

1

C7410

100PF

5% 25V

2

NP0-CERM 0201

NO STUFF

R7409

40.2K

1 2

1%

1/20W

MF

201

R7410

1

1 2

5%

1/20W

MF

201

CPUIMVP_ISNS1_P

1%

1/20W

MF

201

R7407

300

1 2

CPUIMVP_ISNS2_P

1%

1/20W

MF

201

SIGNAL_MODEL=EMPTY

R7408

300

1 2

CPUIMVP_ISNS3_P

1%

1/20W

MF

201

SIGNAL_MODEL=EMPTY

CPUIMVP_ISUMG2P

CPUIMVP_ISUMG1P

CPUIMVP_ISUMGN

IN

GND_CPUIMVP_SGND PLACE_NEAR=Q7510.1:7mm PLACE_NEAR=Q7550.1:6mm

CPUIMVP_ISUMG_AVEP

66

IN

A

6 3

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

SIGNAL_MODEL=EMPTY

1

C7440

2

1

C7441

1000PF

10% 16V

2

X7R-CERM 0201

SIGNAL_MODEL=EMPTY

1000PF

10% 16V X7R-CERM 0201

CPU_AXG_SENSE_R

NO STUFF

1

C7442

1000PF

10% 16V

2

X7R-CERM 0201

NO STUFF

1

C7443

1000PF

10% 16V

2

X7R-CERM 0201

SIGNAL_MODEL=EMPTY

R7440

10

1 2

1%

1/20W

MF

201

R7441

10

1 2

1%

1/20W

MF

201

CPU_AXG_SENSE_N

CPU_VCCSENSE_NCPU_VCCSENSE_R

C7473

100PF

1 2

5%

25V

89 13

IN

CPUIMVP_FBA

65

89 13

IN

CPUIMVP_FBB

65

R7412

12.1K

1 2

1%

1/20W

MF

201

NP0-CERM

0201

CPUIMVP_FBA_R

R7422

1 2

16.2K

1%

1/20W

MF

201

SIGNAL_MODEL=EMPTY

1

C7412

1000PF

10% 16V

2

X7R-CERM 0201

SIGNAL_MODEL=EMPTY

C7422

1000PF

X7R-CERM

0201

CPUIMVP_FBB_R

SYNC_MASTER=D2_SEAN

PAGE TITLE

10% 16V

R7413

10

1 2

1%

1/20W

MF

201

1

2

R7423

10

1 2

1%

1/20W

MF

201

CPU IMVP7 & AXG VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

IN

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

74 OF 132

SHEET

65 OF 99

89 13

A

SIZE

D

124578

8 7 6 5 4 3

=PPVIN_S0_CPUIMVP

65

8

5

6

G

D

S

4

NC

128

D

S

5

3

CRITICAL

Q7510

IRF6802SDTRPBF

DIRECTFET-SA

0.36UH-20%-36A-0.00108OHM

NOSTUFF

R7512

1/10W

NC

MF-LF

7

CRITICAL

Q7515

649135PBF

DIRECTFET_S3C

376S1011

2.2

5%

603

1 2

1

2

6

1

2

C7511

0.22UF

10% 16V CERM 402

376S1010

1

4

PHASE 1

CPUIMVP_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

D

CPUIMVP_BOOT1

65

IN

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1

65

IN

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1

65

IN

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1

65

IN

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

R7511

0

5% 1/16W MF-LF

402

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

1

2

L7510

PIMS103T-SM

152S1538

OMIT_TABLE

CRITICAL

1

C7513

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

PPVCORE_S0_CPU_PH1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V

97 65 46

CPUIMVP_PH1_SNUB

DIDT=TRUE NOSTUFF

1

C7512

0.001UF

10% 50V

2

X7R-CERM 0402

CRITICAL

1

C7514

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CPUIMVP_ISNS1_P

1

2

NOSTUFF

CRITICAL

C7515

10UF

20% 16V X6S-CERM 0603

R7513

46.4

1/20W

CRITICAL

0.00075

1 2 3 4

1

1%

MF

201

2

1

2

R7510

1% 1W MF

0612

97 46

NOSTUFF

CRITICAL

C7516

10UF

20% 16V X6S-CERM 0603

1

2

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS1_N

1

R7514

10

1% 1/20W MF 201

2

CPUIMVP_ISUMN

CPUIMVP_ISUM1P

PHASE 3

=PP5V_S0_CPUIMVP

66 65

8

C

1

R7547

10K

5% 1/16W MF-LF 402

2

65

IN

CPUIMVP_PWM3 CPUIMVP_SKIP

66

2

6

PWN

SKIP*

5

VDD

U7541

MAX17491

TQFN

CRITICAL

THRM

GND

3

PAD

BST

DH

LX

DL

9

1

C7541

1UF

10% 16V

2

X6S-CERM 0402

1

8

7

4

CPUIMVP_BOOT3

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE3

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE3

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE3

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

AXG PHASE 1

=PPVIN_S0_CPUAXG

8

R7556

0

1 2

CPUIMVP_BOOT1G

65

IN

MIN_LINE_WIDTH=0.25 MM

B

66 65

A

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_UGATE1G

65

IN

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1G

65

IN

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1G

65

IN

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

=PP5V_S0_CPUIMVP

8

1

R7540

10K

5% 1/16W MF-LF 402

2

DIDT=TRUE GATE_NODE=TRUE

CPUIMVP_AXG_PWM2

65

IN

CPUIMVP_SKIP

66

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

1/16W MF-LF

5%

402

CPUIMVP_BOOT1G_R

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

0.22UF

U7542

MAX17491

2

PWN

CRITICAL

6

SKIP*

GND

3

C7551

CERM

5

VDD

TQFN

10% 16V

402

THRM

PAD

7

8

376S1010

1

2

D

G

S

CRITICAL

Q7550

IRF6802SDTRPBF

DIRECTFET-SA

3

NC

128

7

CRITICAL

D

Q7551

S

356

1

C7540

1UF

10% 16V

2

X6S-CERM 0402

CPUIMVP_BOOT2G

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE2G

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE2G

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2G

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

649135PBF

DIRECTFET_S3C

376S1011

DIDT=TRUE

G

4

1

BST

8

DH

7

LX

4

DL

9

0.36UH-20%-36A-0.00108OHM

1

2

1

2

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

OMIT_TABLE

CRITICAL

1

C7554

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

L7550

1 2

PIMS103T-SM

NOSTUFF

152S1538

R7552

2.2

5% 1/10W MF-LF 603

CPUIMVP_AXG1_SNUB

C7552

0.001UF

10% 50V X7R-CERM 0402

NOSTUFF

DIDT=TRUE

CPUIMVP_BOOT2G_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

R7535

3.3

1/16W MF-LF

NOSTUFF

CRITICAL

1

C7555

10UF

20% 16V

2

X6S-CERM 0603

PPVCORE_S0_AXG1_L

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

DIDT=TRUE

1

5%

402

2

C7530

0.22UF

10% 16V CERM 402

THESE TWO CAPS ARE FOR EMC

1

C7517

1UF

10% 16V X6S-CERM 0402

CPUIMVP_BOOT3_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

R7531

1/16W MF-LF

3.3

402

1

2

1

5%

2

CRITICAL

C7556

10UF

20% 16V X6S-CERM 0603

1

C7581

330PF

10% 16V

2

X7R-CERM 0201

DIDT=TRUE

R7553

46.4

1/20W

2

201

C7518

1% MF

0.001UF

10% 50V X7R-CERM 0402

1

C7531

0.22UF

10% 16V

2

CERM 402

1

C7557

1UF

10% 16V

2

X6S-CERM 0402

CRITICAL

R7550

0.00075

1% 1W MF

0612

2 1 4 3

96 46 96 66 46

1

2

1

C7519

0.001UF

10% 50V

2

X7R-CERM 0402

8 66

65

66 65

65

376S1014

THESE TWO CAPS ARE FOR EMC

1

C7558

0.001UF

10% 50V

2

X7R-CERM 0402

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS1G_NCPUIMVP_ISNS1G_P

1

R7554

10

1% 1/20W MF 201

2

CPUIMVP_ISUMGN

CPUIMVP_ISUMG1P

IN

1

2

4

1

2

C7584

330PF

10% 16V X7R-CERM 0201

CPUIMVP_BOOT2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE2

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CRITICAL

Q7530

649136PBF

S1

G

3

128

D

G

S

356

C7559

0.001UF

10% 50V X7R-CERM 0402

PHASE 2

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

1

C7533

2

0.36UH-20%-36A-0.00108OHM

NOSTUFF

1

R7532

2.2

5% 1/10W MF-LF

603

2

D

S

CPUIMVP_PHASE3_L

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

7

CRITICAL

Q7535

1 2 5 64

649135PBF

DIRECTFET_S3C

376S1011

AXG PHASE 2

66 45

8

66 65

65

CPUIMVP_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

1

R7521

0

5% 1/16W MF-LF

402

2

CRITICAL

68UF

20% 16V POLY-TANT CASE-D2E-SM

CRITICAL

L7530

1 2

PIMS103T-SM

152S1538

CPUIMVP_PH3_SNUB

DIDT=TRUE

NOSTUFF

1

C7532

0.001UF

10% 50V

2

X7R-CERM 0402

376S1010

DIDT=TRUE

1

C7521

2

OMIT_TABLEOMIT_TABLE

CRITICAL

1

C7534

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

PPVCORE_S0_CPU_PH3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V

97 65 46

G

1

G

4

CPUIMVP_ISUMGN

66 65

376S1010

0.22UF

10% 16V CERM 402

CRITICAL

1

C7535

10UF

20% 16V

2

X6S-CERM 0603

CPUIMVP_ISNS3_P

5

6

CRITICAL

Q7550

D

IRF6802SDTRPBF

DIRECTFET-SA

S

4

NC

128

7

CRITICAL

D

Q7561

649135PBF

DIRECTFET_S3C

S

5

6

3

G

2

G

4

1

2

R7533

46.4

1%

1/20W

MF

201

376S1011

R7563

7

D

S

3

NC

128

D

S

356

CRITICAL

C7536

10UF

20% 16V X6S-CERM 0603

CRITICAL

R7530

0.00075

1 2 3 4

1

R7582

2

200

1/20W

201

NOSTUFF

R7565

1/20W

0612

8

NC

1% 1W MF

1% MF

201

46.4

1/20W

0

5%

MF

CRITICAL

Q7510

IRF6802SDTRPBF

DIRECTFET-SA

CRITICALCRITICAL

0.36UH-20%-36A-0.00108OHM

NOSTUFF

R7522

2.2

5% 1/10W MF-LF

603

7

CRITICAL

Q7525

649135PBF

DIRECTFET_S3C

376S1011

1

C7537

1UF

10% 16V

2

X6S-CERM 0402

L7520

1 2

PIMS103T-SM

152S1538

1

2

THESE TWO CAPS ARE FOR EMC

1

C7538

0.001UF

10% 50V

2

X7R-CERM 0402

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS3_N

97 46

1

R7534

2

10

1% 1/20W MF 201

2

CPUIMVP_ISUMN

1%

MF

201

CPUIMVP_ISUM3P

0.36UH-20%-36A-0.00108OHM

NOSTUFF

1

R7587

2.2

5% 1/10W MF-LF 603

2

CPUIMVP_ISNS1G_P

1

R7564

200

1000PF

0201

1

10% 16V

2

1% 1/20W MF 201

2

CPUIMVP_ISUMG_AVEP

1

R7566

0

5% 1/20W MF 201

2

CPUIMVP_ISUMG_AVE_RP

1

2

1

2

1

2

C7568

X7R-CERM

CRITICAL

1

C7523

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

PPVCORE_S0_CPU_PH2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V

CPUIMVP_PH2_SNUB

DIDT=TRUE NOSTUFF

1

C7522

0.001UF

10% 50V

2

X7R-CERM 0402

Additonal Input Bulk Caps

1

C7539

1

0.001UF

10% 50V

2

X7R-CERM

2

0402

66 65

1

C7583

330PF

10% 16V

2

X7R-CERM 0201

65

CRITICAL

1

C7560

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

L7560

1 2

PIMS103T-SM

152S1538

CPUIMVP_AXG2_SNUB

DIDT=TRUE

NOSTUFF

C7569

330PF

10% 16V X7R-CERM 0201

OMIT_TABLEOMIT_TABLEOMIT_TABLE

CRITICAL

1

C7524

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

97 65 46

OMIT_TABLE

CRITICAL

C7570

68UF

20% 16V POLY-TANT CASE-D2E-SM

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

96 66 46

65

1

2

CPUIMVP_ISNS2_P

OMIT_TABLE

CRITICAL

1

C7571

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

66

8

OMIT_TABLEOMIT_TABLE

CRITICAL

1

C7561

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

PPVCORE_S0_AXG2_L

CPUIMVP_ISNS2G_P

97 46

NOSTUFF

1

C7587

0.001UF

10% 50V

2

X7R-CERM 0402

SYNC_MASTER=D2_SEAN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

NOSTUFF

CRITICAL

C7525

10UF

20% 16V X6S-CERM 0603

R7523

46.4

1/20W

CRITICAL

0.00075

1 2 3 4

1

1%

MF

201

2

1

2

R7520

1% 1W MF

0612

97 46

CRITICAL

C7526

10UF

20% 16V X6S-CERM 0603

1

C7527

1UF

10% 16V

2

X6S-CERM 0402

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS2_N

1

R7524

10

1% 1/20W MF 201

2

CPUIMVP_ISUMN

CPUIMVP_ISUM2P

CRITICAL

1

C7562

2

NOSTUFF

10UF

20% 16V X6S-CERM 0603

R7561

46.4

1/20W

CRITICAL

1

C7572

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

1% MF

201

0.00075

1 2 3 4

1

2

NOSTUFF

CRITICAL

1

C7563

10UF

20% 16V

2

X6S-CERM 0603

CRITICAL

R7560

1% 1W MF

0612

1

2

1

R7562

10

1% 1/20W MF 201

2

1

2

CRITICAL

C7574

15UF

20% 16V TANT SM

C7567

1

2

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS2G_N

330PF

10% 16V X7R-CERM 0201

CPUIMVP_ISUMG2P

CPU IMVP7 & AXG VCore Output

Apple Inc.

R

1

C7582

330PF

10% 16V

2

X7R-CERM 0201

1

2

THESE TWO CAPS ARE FOR EMC

C7564

1UF

10% 16V X6S-CERM 0402

CPUIMVP_ISUMGN

6 3

12

THESE TWO CAPS ARE FOR EMC

1

C7528

0.001UF

10% 50V

2

X7R-CERM 0402

65

(D SIZE)

OMIT_TABLEOMIT_TABLE

CRITICAL

C7575

68UF

20% 16V POLY-TANT CASE-D2E-SM

CRITICAL

1

C7573

15UF

20% 16V

2

TANT SM

1

2

C7565

0.001UF

10% 50V X7R-CERM 0402

CRITICAL

1

C7578

15UF

20% 16V

2

TANT SM

97 46

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

75 OF 132

SHEET

66 OF 99

124578

1

C7529

0.001UF

10% 50V

2

X7R-CERM 0402

8

66 65

(B SIZE)

CRITICAL

1

C7576

15UF

20% 16V

2

TANT SM

1

C7566

0.001UF

10% 50V

2

X7R-CERM 0402

66 45

8

66 65

65

SYNC_DATE=03/05/2012

4.18.0

D

66

C

B

A

SIZE

D

8 7 6 5 4 3

12

D

CPU VCCIO (1V0R1V05 S0) REGULATOR

PART NUMBER

114S0260

114S0264

QTY

2

DESCRIPTION

RES,MTL FILM,1/16W,2.74K,1,0402,SMD,LF

RES,MTL FILM,1/16W,3.01K,1,0402,SMD,LF

C

CPU_VCCIOSENSE_P

13 89

CPU_VCCIOSENSE_N

13 89

OMIT_TABLE

B

REFERENCE DES

1

1/16W MF-LF

1

1%

402

2

1

1%

402

2

R7604

3.01K

R7605

2.74K

CRITICAL

R7605,R7645

Vout = 0.5V * (1 + Ra / Rb)

R7644

3.01K

1% 1/16W MF-LF 402

OMIT_TABLE

R7645

2.74K

1% 1/16W MF-LF 402

1

C7604

10PF

C0G-CERM

0402

1

C7605

5%

50V

10PF

5% 50V

2

C0G-CERM 0402

BOM OPTION

PPCPUVCCIO:SNB

PPCPUVCCIO:IVB

70

IN

70

OUT

C7602

2.2UF

10% 16V X5R 603

1

C7603

0.047UF

10% 16V

2

X7R-CERM 0402

8

PP5V_S0_CPUVCCIOS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

=CPUVCCIOS0_EN

CPUVCCIOS0_FB

CPUVCCIOS0_SREF

CPUVCCIOS0_VO

CPUVCCIOS0_OCSET

CPUVCCIOS0_PGOOD

CPUVCCIOS0_RTN

CPUVCCIOS0_FSEL

1

R7603

1

0

5% 1/16W MF-LF

2

402

2

CPUVCCIOS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

=PPVIN_S0_CPUVCCIOS0 =PP5V_S0_CPUVCCIOS0

R7601

3

6

4

8

7

9

2

5

2.2

5% 1/16W MF-LF

402

ISL95870

EN

CRITICAL

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

XW7600

SM

1 2

PLACE_NEAR=U7600.1:1mm

1

2

13

VCC

U7600

UTQFN

GND

1

PVCC

PGND

CPUVCCIOS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm

CPUVCCIOS0_VBST

12

11

10

15

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

R7630

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

CPUVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

1/10W MF-LF

1

C7630

1

1UF

0

5%

603

10% 16V

2

X5R 402

2

376S0959

2 3 7

1

6

4 5

CRITICAL

Q7630

SIZ710DT

POWERPAK-6X3.7

8

R7641

1.87K

1

C7601

10UF

20% 10V

2

X5R 603

14

BOOT

UGATE

PHASE

LGATE

16

(CPUVCCIOS0_OCSET)

OMIT_TABLE OMIT_TABLE

C7625

1UF

10% 25V X5R 402

CRITICAL

C7620

68UF

20% 16V

POLY-TANT

CASE-D2E-SM

CRITICAL

L7630

0.82UH-20%-13A-0.0067OHM

1 2

IHLP2525CZ-SM

152S1238

1

1% 1/16W MF-LF

C7640

402

2

1000PF

12

5%

25V

NP0-C0G

402

CRITICAL

1

C7621

2

POLY-TANT

CASE-D2E-SM

PPCPUVCCIO_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.0V

CPUVCCIOS0_CS_P

45 96

CPUVCCIOS0_CS_N

45 96

1

R7642

1.87K

1% 1/16W MF-LF 402

2

68UF

1

C7622

1000PF

2

5% 25V

2

NP0-C0G 402

PLACE_NEAR=Q7630.1:1.5mm

CRITICAL

R7640

0.001

1%

1W MF-1 0612

1 2 3 4

PLACE_NEAR=L7630.2:1.5mm

C7623

1000PF

NP0-C0G

C

=PPCPUVCCIO_S0_REG

270UF

TANT

1

20%

2V

2

VOUT = 1.05V 9A MAX OUTPUT f = 300 kHz

CRITICAL

C7649

1

5%

25V

2

402

CRITICAL

1

C7648

270UF

20% 2V

2

TANT CASE-B4-SM

CASE-B4-SM

8

20% 16V

B

(CPUVCCIOS0_VO)

OCP = R7641 x 8.5uA / R7640 OCP = 10.3A

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

CPU VCCIO (1V0R1V05 S0) POWER SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

76 OF 132

SHEET

67 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

1.8V S0 Regulator

=PP3V3_S5_P1V2P1V8

8

1

C7724

1000PF

5%

25V

2

NP0-C0G

402

=P1V8S0_EN

70

IN

OUT

P1V8S0_PGOOD

D

CRITICAL

C7720

22UF

6.3V

X6S-CERM

0805

1

20%

2

5

EN

7

PG

4

SYNCH

SGND

9

10

1

2

VIN

OMIT_TABLE

U7720

ISL8014A

QFN

CRITICAL

PGND

11

12

3

VDD

THRM_PAD

17

VFB

LX LX

NC

PART NUMBER

14

P1V8S0_SW

SWITCH_NODE=TRUE

15

DIDT=TRUE

8

P1V8S0_FB

16

NC

6

NC

13

NC

353S3739

QTY

1

152S1302

L7720

1.0UH-7A

PIMB053T-SM

1 2

CRITICAL

Vout = 0.8V * (1 + Ra / Rb)

C

1.5V S0 Regulator

=PP3V3_S5_P1V5S0

8

CRITICAL

1

VIN

U7710

ISL8009B

DFN

353S2535

2

3

EN

POR

SKIP

GND

CRITICAL

7

THRM_PAD

9

LX

VFB

RSI

=P1V5S0_EN

70

IN

P1V5S0_PGOOD

70

OUT

C7750

22UF

20%

6.3V

2

CERM 805

8

6

54

1V5_S0_SW

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

1V5_S0_FB

B

DESCRIPTION

IC,ISL8014A,SYNC BUCK REG,4A 1MHZ,QFN16

1

R7720

113K

1% 1/16W MF-LF

402

2

<Ra>

1

R7721

90.9K

1%

1/16W MF-LF

402

2

<Rb>

CRITICAL

L7770

2.2UH-3A

1 2

PCMB042T-IHLP1616BZ

152S0691

Vout = 0.8V * (1 + Ra / Rb)

C7776

47PF

1

5%

50V

2

CERM

402

REFERENCE DES

U7720

1

C7723

47PF

5% 50V

2

CERM 402

1

R7780

100K

1% 1/16W MF-LF 402

2

<Ra>

1

R7781

113K

1% 1/16W MF-LF 402

2

<Rb>

CRITICAL

1

C7721

22UF

20%

6.3V

2

X6S-CERM 0805

CRITICAL

C7722

22UF

X6S-CERM

Vout = 1.508V

Max Current = 1.5A

Freq = 1.6MHZ

CRITICAL

1

C7771

22UF

20%

6.3V

2

CERM 805

=PP1V8_S0_REG

Vout = 1.794V Max Current = 4A Freq = 1 MHz

1

20%

6.3V 2

0805

BOM OPTION

=PP1V5_S0_REG

8

D

1.05V SUS LDO

Panther Point-M requires JTAG pull-ups to be powered at 1.05V in Sus. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V Sus, which burns 100mW in all S-states.

CRITICAL

XDP_PCH

U7740

=PP3V3_SUS_P1V05SUSLDO

8

XDP_PCH

1

C7740

1UF

10%

6.3V 2

CERM

402

8

TPS720105

SON

4

BIAS

6

IN

3

EN

OUT

NC

THRM

PADGND

5

7

=PP1V05_SUS_LDO

Vout = 1.05V

1

Max Current = 0.35A

2

NC

XDP_PCH

1

C7741

2.2UF

10%

6.3V

2

X5R 402

8

C

B

1.5V S0 LDO (RIO)

1

2

1

2

P1V5S0:REG

R7735

1 2

P1V5S0:LDO

R7734

1 2

P1V5S0:LDO

1

C7732

4.7UF

20% 4V

2

X5R-1 402

0

5% 1/16W MF-LF

402

1/16W MF-LF

402

0

5%

=PP1V5_S0_RIO_LDO

Vout = 1.563V Max Current = 0.5A

Over 1.5V to compensate for flex loss

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

77 OF 132

SHEET

68 OF 99

124578

SIZE

A

D

=PP5V_S0_P1V5_LDO

8

=PP1V8_S0_P1V5_LDO

8 8

P1V5S0:LDO

R7730

P1V5S0:LDO

C7731

1.0UF

0201-MUR

A

1/16W MF-LF

20%

6.3V X5R

5%

402

P1V5S0:LDO

1

0

2

1

2

P1V5S0:LDO

R7733

1/20W

C7730

1.0UF

6.3V

0201-MUR

1

100

5% MF

201

2

PP5V_S0_P1V5_LDO_BIAS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

PP1V8_S0_P1V5_LDO

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

P1V5S0_LDO_SS

P1V5S0:LDO

1

C7733

20% X5R

2.2NF

10% 10V

2

X5R-CERM 0201

P1V5S0:LDO

R7738

100K

1/20W

1

IN0

2

IN1

5 8

EN FB

SS

1

5% MF

201

2

P1V5S0_LDO_PGOOD

CRITICAL

4

P1V5S0:LDO

BIAS

U7730

TPS74701

SON

THRML_PAD

GND

6

11

OUT0 OUT1

PP1V5_S0_LDO

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=1.5V

9 10

P1V5S0_LDO_FB

37

PG

P1V5S0:LDO

R7736

4.22K

1/20W

<Ra>

P1V5S0:LDO

R7737

4.42K

1/20W

<Rb>

1% MF

201

1% MF

201

Vout = 0.8V * (1 + Ra / Rb)

6 3

8 7 6 5 4 3

R7803

0

1 2

5%

4 7

SIA427DJ

4 7

376S0945

CRITICAL

Q7800

SIA427DJ

S

3

CRITICAL

Q7810

SIA427DJ

4 7

CRITICAL

Q7850

SC70-6L

S

G

3

SC70-6L

G

SC70-6L

S

3

C7850

0.01UF

1 2

X7R-CERM

C7800

0.01UF

1 2

G

10% 16V

0402

X7R-CERM

C7810

1 2

D

10% 16V

0402

0.01UF

10% 16V

X7R-CERM

0402

D

1

3.3V S4 FET

=PP3V3_S4_P3V3S4FET

8

1

D

=P3V3S4_EN

70

IN

SSM6N15FEAPE

SOT563

2

SG

1

6

D

Q7802

R7802

220K

5% 1/16W MF-LF

402

2

P3V3S4_EN_L

1

C7809

0.033UF

R7800

47K

5% 1/16W MF-LF

402

1

10% 16V

2

X5R 402

2

P3V3S3_S4

3.3V S3 FET

=PP3V3_S3_P3V3S3FET

8

R7810

47K

5% 1/16W MF-LF

402

C7811

0.033UF

1

10% 16V

2

X5R 402

P3V3S3_SS

1

6

D

Q7812

SSM6N15FEAPE

SOT563

2

SG

=P3V3S3_EN

70

IN

1

R7812

100K

5% 1/16W MF-LF

402

2

P3V3S3_EN_L

1 2

5V S3 FET

C

70

IN

=P5VS3_EN

=PP5V_S4_P5VS3FET

8

Q7852

SSM6N15FEAPE

R7850

47K

5% 1/16W MF-LF

402

C7851

0.033UF

1

10% 16V

2

X5R 402

P5VS3_SS

1

6

D

SOT563

2

SG

1

R7852

100K

1/16W MF-LF

5%

402

2

P5VS3_EN_L

1 2

1

1/16W MF-LF

402

NOSTUFF

=PP3V3_S4_FET

=PP3V3_S3_FET

=PP5V_S3_FET

MOSFET

CHANNEL

RDS(ON)

LOADING

MOSFET

CHANNEL

RDS(ON)

LOADING

MOSFET

CHANNEL

RDS(ON)

LOADING

8

3.3V S4 FET

3.3V S3 FET

8

5V S3 FET

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

0.7? A (EDP)

8

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

3 A (EDP)

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

3 A (EDP)

5V_SUS FET INPUT FILTER

=PP5V_S5_P5VSUSFET

8

PLACE_NEAR=Q7840.4:5mm

39 70

IN

=P3V3S0_EN

70

R7843

0

1 2

5% 1/16W MF-LF

402

70

IN

8

=P3V3SUS_EN

NO STUFF

C7843

2.2UF

20% 10V

X5R-CERM

402

=P5VSUS_EN

=PP3V3_S0_P3V3S0FET

Q7812

SSM6N15FEAPE

=PP3V3_S5_P3V3SUSFET

8

Q7802

SSM6N15FEAPE

SOT563

5

PP5V_S5_P5VSUSFET_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.1 MM

1

VOLTAGE=5V

Q7842

2

SSM3K15FV

SOD-VESM-HF

1

G S

3

D

SOT563

5

SG

4

3

2

R7832

R7822

100K

5% 1/16W MF-LF

402

R7842

220K

1/16W MF-LF

402

1

47K

5% 1/16W MF-LF

402

2

P3V3S0_EN_L

3

D

SG

4

D

1.5V S3/S0 FET

=PPVIN_S3_P1V5S3RS0_FET

=PP5V_S5_P1V5S3RS0FET

8

1

C7801

0.1UF

20% 10V

2

CERM

402

P1V5CPU_EN

27

IN

B

NO STUFF

1

C7802

1UF

10% 10V

2

X5R

402

=PP3V3_GPU_MISC_P3V3GPUMISCFET

8

2

3

A

Q7882

SSM3K15FV

SOD-VESM-HF

=P3V3GPU_MISC_EN

88

IN

ON

SHDN*

R7882

1

G S

1

VCC

U7801

SLG5AP020

TDFN

CRITICAL

THRM

GND

PAD

4

1

51K

5% 1/16W MF-LF

402

2

P3V3GPU_MISC_EN_L

3

D

2

9

8

5

D

G

S

PG

7

P1V5S3RS0FET_GATE

6

8

R7801

1 2

1/16W MF-LF

402

P1V5S3RS0_RAMP_DONE

0

5%

3.3V S0 GPU MISC FET

0.47UF

X6S-CERM

R7880

1K

1 2

5% 1/16W MF-LF

402

6.3V 0402

1

10%

2

C7881

P1V5S3RS0FET_GATE_R

P3V3GPU_MISC_SS

IN

70

=PP3V3_GPU_P3V3GPUFET

8

=P3V3GPU_EN

=PP5V_S4_P5VS0FET

8

=P5VS0_EN

IN

Q7872

SSM3K15FV

SOD-VESM-HF

Q7865

SSM3K15FV

SOD-VESM-HF

R7872

1

G S

R7862

1

G S

220K

1

51K

5% 1/16W MF-LF

402

2

P3V3GPU_EN_L

3

D

2

1

5%

1/16W MF-LF

402

2

P5V0S0_EN_L

3

D

2

1.5V S3/S0 FET

APN 376S0651

5

CRITICAL

D

Q7801

4

G

88

OUT

CRITICAL

Q7880

SIA427DJ

SC70-6L

S

4 7

G

3

C7880

0.01UF

1 2

10% 16V

X7R-CERM

0402

SI7108DN

PWRPK-1212-8-HF

S

1 2 3

PP1V5_S3RS0_FET

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V

=PP3V3_S0GPU_MISC_FET

1

D

MOSFET

CHANNEL

RDS(ON)

LOADING

MOSFET

CHANNEL

RDS(ON)

LOADING

XW7805

SM

1 2

=PP1V5_S3RS0_FET_ISNS

NC_ISNS_P1V5R1V35_CPUDDRN

NC_ISNS_P1V5R1V35_CPUDDRP

8

3.3V S0 MISC GPU FET

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

0.5A (EDP)

SI7108DN

N-TYPE

6 mOhm @4.5V

5 A (EDP)

8

7

98

OUT

7

98

OUT

88

3.3V S0 GPU FET

3.3V SUS FET

1

2

P3V3SUS_EN_L

5V SUS FET

1

5%

2

P5VSUS_EN_L

3.3V S0 FET

C7871

0.33UF

6.3V

X6S-CERM

0402

R7870

1K

1 2

5% 1/16W MF-LF

402

5.0V S0 FET

C7861

0.033UF

R7860

10K

1 2

5% 1/16W MF-LF

402

R7820

12K

1 2

5% 1/16W MF-LF

402

R7840

3.3K

1 2

5% 1/16W MF-LF

402

C7831

0.033UF

R7830

33K

1 2

5% 1/16W MF-LF

402

1

10%

2

10% 16V X5R 402

C7821

0.033UF

C7841

0.033UF

1

2

10% 16V X5R 402

1

10% 16V

2

X5R 402

P3V3GPU_SS

P5V0S0_SS

1

2

1

2

P3V3SUS_SS

P5VSUS_SS

P3V3S0_SS

4 7

1 2 3

4 7

1 2 3

CRITICAL

Q7870

SIA427DJ

SC70-6L

S

3

CRITICAL

Q7860

SI7615DN

PWRPK-1212-8

S

G

4

CRITICAL

Q7820

SIA427DJ

SC70-6L

S

D

1

=PP3V3_SUS_FET

G

3

CRITICAL

Q7840

SIA413DJ

SC70-6L

S

C7820

0.01UF

1 2

10% 16V

X7R-CERM

0402

D

1

MOSFET

CHANNEL

RDS(ON)

LOADING

=PP5V_SUS_FET

G

3

C7840

0.01UF

1 2

10% 16V

X7R-CERM

0402

CRITICAL

Q7830

SI7615DN

PWRPK-1212-8

S

D

5

G

4

C7830

0.01UF

1 2

10% 16V

X7R-CERM

0402

=PP3V3_S0GPU_FET

1

D

G

C7870

0.01UF

1 2

10% 16V

X7R-CERM

0402

=PP5V_S0_FET

D

5

C7860

0.01UF

1

2

10% 16V

X7R-CERM

0402

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

MOSFET

CHANNEL

RDS(ON)

LOADING

=PP3V3_S0_FET

MOSFET

CHANNEL

RDS(ON)

LOADING

MOSFET

CHANNEL

RDS(ON)

LOADING

MOSFET

CHANNEL

RDS(ON)

LOADING

Apple Inc.

R

8

3.3V SUS FET

8

5V SUS FET

8

3.3V S0 FET

8

88

3.3V S0 GPU FET

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

0.11A (EDP)

8

5.0V S0 FET

SI7615DN

P-TYPE 20V/12V

5.5 MOHM @4.5V

5 A (EDP)

Power FETs

6 3

12

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

100? mA (EDP)

SiA413

P-TYPE 12V

29 mOhm @4.5V

2 mA (EDP)

SI7615DN

P-TYPE 20V/12V

5.5 mOhm @4.5V

5.6 A (EDP)

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=01/13/2012

4.18.0

78 OF 132

69 OF 99

SIZE

D

C

B

A

D

8 7 6 5 4 3

S5 Rail Enables & PGOOD

=P5VS5_EN

63

OUT

SMC_PM_G2_EN

41 42

IN

MAKE_BASE=TRUE

PLACE_NEAR=U7201.21:7mm

D

=PP3V42_G3H_PWRCTL

8

24 41 70

ALL_SYS_PWRGD

PLACE_NEAR=U7201.20:7mm

P3V3S5_PGOOD

63

R7941

100K

R7974

0

1 2

5% 1/16W MF-LF

402

5% 1/16W MF-LF

402

PLACE_NEAR=U7400.7:5mm

R7940

100

1 2

5% 1/16W MF-LF

402

1

2

S5_PWRGD

MAKE_BASE=TRUE

CPUVCORE ENABLE

P3V3S5_EN

MAKE_BASE=TRUE

1

C7942

0.0033UF

10% 50V

2

X7R-CERM 0402

NO STUFF

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

SMC-->PM_DSW_PWRGD

41

OUT

CPUIMVP_VR_ON

=P3V3S5_EN

63

OUT

=PP3V3_S5_PWRCTL

8

70

PLACE_NEAR=U7940.1:2.3mm

SMC_S4_WAKESRC_EN

41 42

IN

70

65

OUT

SMC_BATLOW_L:100K pull up on SMC page

41 42

C

PM_SLP_SUS_L:100K pull down on PCH page

=PP3V3_S5_VMON

=PP3V3_S0_VMON

8

70

1

R7951

15.0K

1% 1/16W MF-LF 402

2

1

R7952

7.15K

1% 1/16W MF-LF 402

2

8

70

B

8

70

8

VMON_3V3_DIV

=PP1V5_S3RS0_VMON

PP1V5_S3RS0

=PP1V05_S0_VMON

R7953

1K

1 2

5% 1/16W MF-LF

402

R7954

1K

1 2

5% 1/16W MF-LF

402

R7955

1K

VMON_Q4_BASE

1 2

5%

1/16W MF-LF

402

Worst-Case Thresholds:

Q2: 0.XXXV Q3: 0.640V

3.3V w/Divider: 2.345V Q4: 0.660V

R7956

150K

1/16W MF-LF

VMON_Q2_BASE

VMON_Q3_BASE

S0 Rail PGOOD (BJT Version)

1

1%

402

2

S0PGD_C

6

4

CRITICAL

3

S0PGD_BJT_GND_R

R7957

100

5% 1/16W MF-LF

402

Q1

353S2809

1

2

5

Q2

8

NC

7

Q3

2

NC

1

Q4

ALL_SYS_PWRGD

Q7950

ASMCC0179

DFN2015H4-8

88

=PP3V3_S0_PWRCTL

8

=PP3V3_SUS_CNTRL

8

70

No stuff C7931, 12ms Min delay time

U7930 Sense input threhold is 3.07V

Sus_PGOOD_CT

R7967

S0 Rail PGOOD Circuitry

(ISL Version in development)

Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

=PP5V_S0_VMON

8

S0PGOOD_ISL

A

S0PGOOD_ISL

R7960

6.04K

R7961

15.0K

1/16W

70

1% 1/16W MF-LF

402

1%

MF-LF

402

=PP1V5_S3RS0_VMON

8

1

S0PGOOD_ISL

R7970

2

P5V_DIV_VMON

1

R7971

2

OMIT_TABLE

1/16W

1/16W MF-LF

10K

MF-LF

402

10K

402

8

70

1

1%

2

1

1%

2

=PP1V05_S0_VMON

S0PGOOD_ISL

P1V5_DIV_VMON

S0PGOOD_ISL

R7972

6.04K

1/16W MF-LF

R7973

15.0K

1/16W

1%

402

1%

MF-LF

402

=PP3V3_S0_VMON

8

70

S0PGOOD_ISL

C7960

1

2

P1V05_VID_VMON

1

2

0.1UF

X7R-CERM

0402

1

20% 10V

2

3

V2MON

5

V3MON

6

P1V5S0_PGOOD from U7710

S0PGOOD_ISL

2

7

VDD

U7960

ISL88042IRTEZ

TDFN

(IPU)

CRITICAL

RST*V4MON

GND

THRM_PAD

4

9

353S2310

MR*

68

IN

68

IN

63

IN

67

IN

87

IN

62

IN

1

NC

8

ALL_SYS_PWRGD_R

P1V5S0_PGOOD

P1V8S0_PGOOD

P5VS4_PGOOD

CPUVCCIOS0_PGOOD

PCHVCCIOS0_PGOOD

PVCCSA_PGOOD

S0PGOOD_ISL

1 2

R7962

330

1 2

5% 1/16W MF-LF

402

R7968

100

5% 1/16W MF-LF

402

R7965

100

5% 1/16W MF-LF

402

R7969

100

5% 1/16W MF-LF

402

R7966

100

1 2

1/16W MF-LF

R7964

100

1 2

1/16W MF-LF

R7963

100

1 2

1/16W MF-LF

ALL_SYS_PWRGD

5%

402

5%

402

5%

402

1/16W MF-LF

10K

24 41 70

5%

402

18

8

70

1

2

1

2

State

Run (S0)

Sleep (S3AC)

Sleep (S3)

Deep Sleep (dS4AC)

Deep Sleep (dS4)

Deep Sleep (dS5AC)

Deep Sleep (dS5)

Battery Off (G3HotAC)

Battery Off (G3Hot)

1

C7970

0.1uF

20% 10V

2

CERM

402

MAKE_BASE=TRUE

3.3V/5.0V Sus ENABLE

=PP3V3_S5_PWRCTL

8

PLACE_NEAR=U7940.1:2.3mm

SMC_BATLOW_L

IN

PM_SLP_SUS_L

IN

3.3V SUS Detect

=PP3V3_S5_PWRCTL

PLACE_NEAR=U7930.6:2.3mm

CRITICAL

SENSE

TPS3808G33DBVRG4

4

CT

C7931

0.001UF

20% 50V CERM 402

NO STUFF

PART NUMBER

114S0315

114S0323

24 41 70

OUT

PM_SLP_S5_L:100K pull down on PCH page

C7940

0.1uF

CERM

6

VDD

RESET*

U7930

SOT23-6

GND

2

QTY

Mobile System Power State Table

X 1 0 1 0 1 0

SMC_PM_G2_ENABLE

1 1 1 1 1 1 1 0 01

SMC_ADAPTER_EN

toggle 3Hz

3.3V S4 ENABLE

PM_SLP_S5_L

18 41

IN

20% 10V

402

MR*

1

2

C7930

0.1uF

20% 10V

CERM

402

15

PM_RSMRST_L

3

SUS_PGOOD_MR_L

1

3

6

1

2

5

VCC

U7940

74AUP1G3208

SOT891

A

B

C

GND

2

1

2

PM_RSMRST_L goes to U1800.C21

4

Y

NO STUFF

R7917

0

1 2

5% 1/16W MF-LF

402

NOSTUFF

R7930

0

5% 1/20W MF 201

1

R7933

100K

5% 1/16W MF-LF

402

2

DESCRIPTION

1

RES,MTL FILM,1/16W,10K,1,0402,SMD,LF

RES,MTL FILM,1/16W,12.4K,1,0402,SMD,LF

SMC_S4_WAKESRC_EN

6

2

1

NC

5

PM_SUS_EN

1 1 1 1 1 0 0 0 0 0

U7970

74LVC1G32

SOT891

4

3

NC

PM_SUS_EN

45

MAKE_BASE=TRUE

Could stuff to satisfy

PCH power down timing t235

=PP3V3_SUS_CNTRL

18

OUT

8

PM_SLP_S5_L

1 1 1 0 0 0 0

P5V3V3_S4_EN

MAKE_BASE=TRUE

1 1 1 0 0 0 0 00 00

NOSTUFF

R7915

0

1 2

5% 1/16W MF-LF

402

PM_SLP_S3_L:100K pull down in PCH page

=P5VSUS_EN

=P3V3SUS_EN

=PP3V3_S5_PCHPWRGD

24 41 70

65

8

=PP3V3_S0_SB_PM

8

25

ALL_SYS_PWRGD

IN

CPUIMVP_PGOOD

IN

70

REFERENCE DES

R7971

SMC_ADAPTER_EN

18 41 42

IN IN

7

PM_SLP_S4_L1PM_SLP_S3_L

1 1 1 0 0 0 0 0 0

7

18 27 38 41 70

=P5VS4_TPAD_EN

=P3V3S4_EN

=TBTAPWRSW_EN

=TBTBPWRSW_EN

PM_SLP_S3_L

IN

0 0 0 0 0 0 0

49

OUT

69

OUT

84

OUT

85

OUT

S0 ENABLE

R7978

1 2

PM_SLP_S4_L:100K pull down in PCH page

R7975

0

1 2

5%

1/20W

MF

201

100

5% 1/16W MF-LF

402

18 27 34 38 40 41

MAKE_BASE=TRUE

P5VS4_EN

NO STUFF

1

C7975

0.47UF

10%

6.3V

2

CERM-X5R 402

(PM_SLP_S3_R_L)

2

IN

R7987

33K

5% 1/16W

1

MF-LF

402

PLACE_NEAR=U7100.15:6mm

CHGR VFRQ Generation

=PP3V42_G3H_CHGR

8 61

G S

R7950

D

1/16W MF-LF

R7931

100K

5% 1/16W MF-LF

1 2

402

CHGR_VFRQ

3

2

1

1K

5%

402

2

1

A

U7950

2

B

SMC_DELAYED_PWRGD

37 41 42

PVCCSA_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7100.15:6mm

61

OUT

1

C7987

0.47UF

10%

6.3V

2

CERM-X5R 402

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

1

C7950

0.1UF

20% 10V

2

CERM 402

74LVC2G08GT

8

SOT833

7

Y

08

4

69

OUT

69

OUT

CRITICAL

Q7931

SSM3K15FV

SOD-VESM-HF

1

PLACE_NEAR=U1800.p12:7mm

BOM OPTION

PPDDR:1V5

PPDDR:1V35

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up

on open-drain AP_PWR_EN signal.

AC_EN_L

NO STUFF

6

SOT563

D

2

SG

1

R7929

1/16W MF-LF

402

1

0

5%

2

7

18 27 38 41 70

Q7920

SSM6N15FEAPE

PM_SLP_S4_L

=P5VS4_EN

63

OUT

2

5%

1

402

PLACE_NEAR=U7600.3:6mm

CPUVCCIOS0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7600.3:6mm

1

C7981

0.47UF

2

1/16W MF-LF

10%

6.3V CERM-X5R 402

PCH S0 PWRGD

CKPLUS_WAIVE=UNCONNECTED_PINS

PM_S0_PGOOD

CKPLUS_WAIVE=UNCONNECTED_PINS

Q7920

SSM6N15FEAPE

PM_SLP_S3_L

2

1

PLACE_NEAR=U7300.16:6mm

1

2

R7981

20K

5

A

U7950

6

B

1 2

SOT563

5

5V, 3.3V, DDR S3 ENABLE

2

74LVC2G08GT

SOT833

3

Y

D

3

4

2

R7985

20K

5% 1/16W MF-LF

1

402

PLACE_NEAR=U7760.4:6mm

PCHVCCIOS0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7760.4:6mm

1

C7985

1UF

10%

6.3V

2

CERM-X5R 402

SYS_PWROK_R

Q7925

SSM3K15FV

SOD-VESM-HF

1

GS

R7911

5.1K

5% 1/16W MF-LF

402

C7910

0.47UF

10%

6.3V CERM-X5R 402

8

08

4

R7948

0

5% 1/16W MF-LF

402

3

2

D

SG

R7912

0

5% 1/16W

MF-LF

1

402

PLACE_NEAR=Q7812.2:6mm

NO STUFF

1

C7912

0.47UF

10%

6.3V

2

CERM-X5R 402

2

1

PM_SLP_S3_R_L

MAKE_BASE=TRUE

R7988

10K

5%

1/16W MF-LF

1 2

402

P1V5S0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7710.2:6mm

1

C7988

0.47UF

10%

6.3V

2

CERM-X5R 402

R7949

1K

1 2

5% 1/16W MF-LF

402

R7913

0

5% 1/16W MF-LF

402

PLACE_NEAR=Q7842.2:6MM

NO STUFF

1

C7913

0.47UF

10%

6.3V

2

CERM-X5R 402

2

R7986

5.1K

5% 1/16W MF-LF

1

402

PLACE_NEAR=U7720.5:6mm

P1V8S0_EN

MAKE_BASE=TRUE

PM_PCH_SYS_PWROK

1

2

PM_PCH_APWROK

PM_PCH_PWROK

MAKE_BASE=TRUE

PM_WLAN_EN_L

AP_PWR_EN

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Power Control 1/ENABLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

PLACE_NEAR=U5701.4:6MM

R7914

3.3K

5%

1/20W

201

1 2

P5VS3_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

NO STUFF

1

C7914

0.47UF

10%

6.3V

2

CERM-X5R 402

PLACE_NEAR=U7720.5:6mm

C7986

0.47UF

10%

6.3V X6S-CERM 0402

MF

6 3

TPAD_VBUS_EN

=P5VS0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=TBT_S0_EN

=P1V8S0_EN

=P1V5S0_EN

=PCHVCCIOS0_EN

=CPUVCCIOS0_EN

=PVCCSA_EN

OUT

34

OUT

19 24 34

IN

12

=P5VS3_EN

=P3V3S3_EN

=DDRREG_EN

18 24 41

18

18 25

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

79 OF 132

SHEET

70 OF 99

124578

49

OUT

69

OUT

69

OUT

64

OUT

69

OUT

39 69

OUT

45

OUT

84 85

OUT

68

OUT

68

OUT

87

OUT

67

OUT

62

OUT

D

C

B

A

SIZE

D

Power aliases required by this page:

- =PP3V3_GPU_VDD33

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

C

89

8 7 6 5 4 3

Page Notes

71 88 89 71 89

71 88 89

71 89

0.22UF

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_C_P<1>

PEG_R2D_C_N<1>

PEG_R2D_C_P<2>

PEG_R2D_C_N<2>

PEG_R2D_C_P<3>

PEG_R2D_C_N<3>

PEG_R2D_C_P<4>

PEG_R2D_C_N<4>

PEG_R2D_C_P<5>

PEG_R2D_C_N<5>

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<7>

C8020

GND_VOID=TRUE

C8021

GND_VOID=TRUE

C8022

GND_VOID=TRUE

C8023

GND_VOID=TRUE

C8024

GND_VOID=TRUE

C8025

GND_VOID=TRUE

C8026

GND_VOID=TRUE

C8027

GND_VOID=TRUE

C8028

GND_VOID=TRUE

C8029

GND_VOID=TRUE

C8030

GND_VOID=TRUE

C8031

GND_VOID=TRUE

C8032

GND_VOID=TRUE

C8033

GND_VOID=TRUE

C8034

GND_VOID=TRUE

C8035

GND_VOID=TRUE

0.22UF

1 2

20%

6.3V

X6S-CERM 0201

6.3V X6S-CERM

PEG_R2D_P<0>

PEG_R2D_N<0>

0201

PEG_R2D_P<1>

0201

PEG_R2D_N<1>

0201

PEG_R2D_P<2>

0201

PEG_R2D_N<2>

0201

PEG_R2D_P<3>

0201

PEG_R2D_N<3>

0201

PEG_R2D_P<4>

0201

PEG_R2D_N<4>

0201

PEG_R2D_P<5>

0201

PEG_R2D_N<5>

0201

PEG_R2D_P<6>

0201

PEG_R2D_N<6>

0201

PEG_R2D_P<7>

0201

PEG_R2D_N<7>

0201

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

PEG_R2D_P<0> PEG_R2D_N<0>

PEG_R2D_P<1> PEG_R2D_N<1>

PEG_R2D_P<2> PEG_R2D_N<2>

PEG_R2D_P<3> PEG_R2D_N<3>

PEG_R2D_P<4> PEG_R2D_N<4>

PEG_R2D_P<5> PEG_R2D_N<5>

PEG_R2D_P<6> PEG_R2D_N<6>

PEG_R2D_P<7> PEG_R2D_N<7>

12

OMIT_TABLE

U8000

NV-GK107

BGA

AN12 AM12

PEX_RX0*

AN14

PEX_RX1

AM14

PEX_RX1*

AP14

PEX_RX2

AP15

PEX_RX2*

AN15

PEX_RX3

AM15

PEX_RX3*

AN17

PEX_RX4

AM17

PEX_RX4*

AP17

PEX_RX5

AP18

PEX_RX5*

AN18

PEX_RX6

AM18

PEX_RX6*

AN20

PEX_RX7

AM20

PEX_RX7*

AP20 AP21

AN21 AM21

AN23 AM23

AP23 AP24

PEX_RX8 PEX_RX8*

PEX_RX9 PEX_RX9*

PEX_RX10 PEX_RX10*

PEX_RX11 PEX_RX11*

NC NC

(1 OF 10)

PEX_TX0PEX_RX0

PEX_TX0*

PEX_TX1

PEX_TX1*

PEX_TX2

PEX_TX2*

PEX_TX3

PEX_TX3*

PEX_TX4

PEX_TX4*

PEX_TX5

PEX_TX5*

PEX_TX6

PEX_TX6*

PEX_TX7

PEX_TX7*

PEX_TX8

PEX_TX8*

PEX_TX9

PEX_TX9*

PEX_TX10

PEX_TX10*

PEX_TX11

PEX_TX11*

AK14 AJ14

AH14 AG14

AK15 AJ15

AL16 AK16

AK17 AJ17

AH17 AG17

AK18 AJ18

AL19 AK19

AK20 AJ20

AH20 AG20

AK21 AJ21

AL22 AK22

PEG_D2R_C_P<0> PEG_D2R_C_N<0>

PEG_D2R_C_P<1> PEG_D2R_C_N<1>

PEG_D2R_C_P<2> PEG_D2R_C_N<2>

PEG_D2R_C_P<3> PEG_D2R_C_N<3>

PEG_D2R_C_P<4> PEG_D2R_C_N<4>

PEG_D2R_C_P<5> PEG_D2R_C_N<5>

PEG_D2R_C_P<6> PEG_D2R_C_N<6>

PEG_D2R_C_P<7> PEG_D2R_C_N<7>

NC NC

=PP3V3_GPU_VDD33

8

77 78 79

PEX_CLKREQ_L_R

71 78

71 89

1

R8001

10K

1% 1/20W MF 201

2

D

C

AN24 AM24

AN26 AM26

AP26 AP27

AN27 AM27

AL13 AK13

AJ12

AK12

AJ11

PEX_RX12 PEX_RX12*

PEX_RX13 PEX_RX13*

PEX_RX14 PEX_RX14*

PEX_RX15 PEX_RX15*

PEX_REFCLK PEX_REFCLK*

PEX_RST*

PEX_CLKREQ*

PEX_WAKE*

PEX_TX12*

PEX_TX13*

PEX_TX14*

PEX_TX15*

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT*

PEX_TERMP

PEX_SVDD_3V3

NC NC

B

0.22UF

PEG_D2R_C_P<0>

71 89

PEG_D2R_C_N<0>

71 89

PEG_D2R_C_P<1>

71 89

PEG_D2R_C_N<1>

71 89

PEG_D2R_C_P<2>

71 89

PEG_D2R_C_N<2>

71 89

PEG_D2R_C_P<3>

71 89

PEG_D2R_C_N<3>

71 89

PEG_D2R_C_P<4>

71 89

PEG_D2R_C_N<4>

71 89

PEG_D2R_C_P<5>

A

71 89

PEG_D2R_C_N<5>

71 89

PEG_D2R_C_P<6>

71 89

PEG_D2R_C_N<6>

71 89

PEG_D2R_C_P<7>

71 89

PEG_D2R_C_N<7>

71 89

C8055

GND_VOID=TRUE

C8056

GND_VOID=TRUE

C8057

GND_VOID=TRUE

C8058

GND_VOID=TRUE

C8059

GND_VOID=TRUE

C8060

GND_VOID=TRUE

C8061

GND_VOID=TRUE

C8062

GND_VOID=TRUE

C8063

GND_VOID=TRUE

C8064

GND_VOID=TRUE

C8065

GND_VOID=TRUE

C8066

GND_VOID=TRUE

C8067

GND_VOID=TRUE

C8068

GND_VOID=TRUE

C8069

GND_VOID=TRUE

C8070

GND_VOID=TRUE

0.22UF

1 2

20%

6.3V X6S-CERM

PEG_D2R_P<0>

0201

PEG_D2R_N<0>

0201

PEG_D2R_P<1>

0201

PEG_D2R_N<1>

0201

PEG_D2R_P<2>

0201

PEG_D2R_N<2>

0201

PEG_D2R_P<3>

0201

PEG_D2R_N<3>

0201

PEG_D2R_P<4>

0201

PEG_D2R_N<4>

0201

PEG_D2R_P<5>

0201

PEG_D2R_N<5>

0201

PEG_D2R_P<6>

0201

PEG_D2R_N<6>

0201

PEG_D2R_P<7>

0201

PEG_D2R_N<7>

0201

9

88 89

OUT

9

88 89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

88 89

OUT

9

88 89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

88 89

OUT

9

88 89

OUT

78

9

IN

GPU_RESET_L

71 78

OUT

17 92

IN

17 92

IN

1 2

PEX_CLKREQ_L_R

PEG_CLK100M_P PEG_CLK100M_N

R8000

0

1/20W

5%MF

NC NC

GPU_RESET_R_L

201

NC

6 3

AK23

PEX_TX12

PEX_TX13

PEX_TX14

PEX_TX15

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NC

AJ23

NC

AH23

NC

AG23

NC

AK24

NC

AJ24

NC

AL25

NC

AK25

NC

PEX_TSTCLK_O_P

92 95

AJ26

95

AK26

PEX_TSTCLK_O_N

92

AP29

GPU_PEX_TERMP

AG12

PP3V3_GPU_PEX_PLL_HVDD

NOSTUFF

R8002

200

1 2

1/20W

201

R8005

2.49K

1 2

1%

1/20W

MF

201

79

1%

MF

KEPLER PCI-E

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

80 OF 132

SHEET

71 OF 99

124578

SIZE

B

A

D

8 7 6 5 4 3

1

C8166

10UF

20% 4V

2

X6S-CERM 0402-1

1

C8177

10UF

20% 4V

2

X6S-CERM 0402-1

CRITICAL

1

C8189

1UF

20% 4V

2

CERM-X6S 0201

Page Notes

1

C8167

10UF

20% 4V

2

X6S-CERM 0402-1

OMIT_TABLE

VDD

U8000

NV-GK107

BGA

(10 OF 10)

XVDD

VDD

V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22

U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8 W2 W3 W4 W5 W7 W8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

8

72 79

=PPVCORE_GPU

8

72 79

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NOSTUFF

1

C8161

47UF

20% 4V

2

X6S 0805

CRITICAL

1

C8145

20UF

20% 2V

2

X6T-CERM 0402

1

C8168

10UF

20% 4V

2

X6S-CERM 0402-1

1

C8178

10UF

20% 4V

2

X6S-CERM 0402-1

NOSTUFF CRITICAL

1

C8198

22UF

20% 4V

2

X6S-CERM 0603

CRITICAL

1

C8146

20UF

20% 2V

2

X6T-CERM 0402

1

C8169

10UF

20% 4V

2

X6S-CERM 0402-1

1

C8179

10UF

20% 4V

2

X6S-CERM 0402-1

NOSTUFF CRITICAL

1

C8199

22UF

20% 4V

2

X6S-CERM 0603

CRITICAL

1

C8147

20UF

20% 2V

2

X6T-CERM 0402

1

C8170

10UF

20% 4V

2

X6S-CERM 0402-1

1

C8180

10UF

20% 4V

2

X6S-CERM 0402-1

CRITICAL

1

C8162

20UF

20% 2V

2

X6T-CERM 0402

CRITICAL

1

C8148

20UF

20% 2V

2

X6T-CERM 0402

1

C8171

10UF

20% 4V

2

X6S-CERM 0402-1

1

C8181

10UF

20% 4V

2

X6S-CERM 0402-1

CRITICAL

1

C8163

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF CRITICAL

1

C8149

20UF

20% 2V

2

X6T-CERM 0402

1

C8172

10UF

20% 4V

2

X6S-CERM 0402-1

1

C8184

10UF

20% 4V

2

X6S-CERM 0402-1

EDP = 30 A

CRITICAL

1

C8164

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF CRITICAL

1

C8150

20UF

20% 2V

2

X6T-CERM 0402

1

C8173

10UF

20% 4V

2

X6S-CERM 0402-1

1

C8185

10UF

20% 4V

2

X6S-CERM 0402-1

CRITICAL

1

C8165

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF CRITICAL

1

C8151

20UF

20% 2V

2

X6T-CERM 0402

1

C8174

10UF

20% 4V

2

X6S-CERM 0402-1

CRITICAL

1

C8186

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF CRITICAL

1

C8182

20UF

20% 2V

2

X6T-CERM 0402

1

C8175

10UF

20% 4V

2

X6S-CERM 0402-1

CRITICAL

1

C8187

1UF

20% 4V

2

CERM-X6S 0201

=PPVCORE_GPU =PPVCORE_GPU

8

72 79

OMIT_TABLE

U8000

B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16

NV-GK107

BGA

(7 OF 10)

FBVDDQFBVDDQ

8

72 75 76

D

AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27

H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33

Y27

=PP1V35_GPU_FBVDDQ=PP1V35_GPU_FBVDDQ

8

72 75 76

C

AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23

M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15

Power aliases required by this page:

- =PPVCORE_GPU

- =PP1V35_GPU_FBVDDQ

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

NOSTUFF CRITICAL

1

C8183

20UF

20% 2V

2

X6T-CERM 0402

1

C8176

10UF

20% 4V

2

X6S-CERM 0402-1

CRITICAL

1

C8188

1UF

20% 4V

2

CERM-X6S 0201

12

D

C

B

=PP1V35_GPU_FBVDDQ

8

72 75 76

GPU FB DE-COUPLING

CRITICAL

1

C8190

1UF

20% 4V

2

CERM-X6S 0201

1

C8191

2

0.1UF

10%

6.3V X6S 0201

1

2

C8192

0.1UF

10%

6.3V X6S 0201

1

2

C8193

0.1UF

10%

6.3V X6S 0201

1

C8194

2

0.1UF

10%

6.3V X6S 0201

1

2

C8195

0.1UF

10%

6.3V X6S 0201

1

C8196

1000PF

10% 16V

2

X7R-CERM 0201

1

C8197

2

1000PF

10% 16V X7R-CERM 0201

B

EDP = 6500 MA

1

C8125

20UF

20% 2V

2

X6T-CERM 0402

1

C8105

4.7UF

20%

6.3V

2

X6S 0402

A

1

C8115

0.1UF

10%

6.3V

2

X6S 0201

1

C8106

2

1

C8118

2

4.7UF

20%

6.3V X6S 0402

0.1UF

10%

6.3V X6S 0201

1

2

1

2

C8107

4.7UF

20%

6.3V X6S 0402

C8119

0.1UF

10%

6.3V X6S 0201

1

C8126

2

1

C8108

2

1

C8120

2

20UF

20% 2V X6T-CERM 0402

4.7UF

20%

6.3V X6S 0402

0.1UF

10%

6.3V X6S 0201

1

C8127

2

1

C8109

2

1

C8121

2

20UF

20% 2V X6T-CERM 0402

4.7UF

20%

6.3V X6S 0402

0.1UF

10%

6.3V X6S 0201

1

C8128

2

1

C8110

2

1

C8122

2

20UF

20% 2V X6T-CERM 0402

4.7UF

20%

6.3V X6S 0402

0.1UF

10%

6.3V X6S 0201

1

C8101

10UF

2

1

C8111

1UF

2

1

C8123

0.1UF

2

20% 4V X6S-CERM 0402-1

20% 4V CERM-X6S 0201

10%

6.3V X6S 0201

1

2

1

2

1

2

C8102

10UF

20% 4V X6S-CERM 0402-1

C8112

1UF

20% 4V CERM-X6S 0201

C8124

0.1UF

10%

6.3V X6S 0201

1

C8103

10UF

2

1

C8113

1UF

2

20% 4V X6S-CERM 0402-1

20% 4V CERM-X6S 0201

6 3

1

2

1

2

C8104

10UF

20% 4V X6S-CERM 0402-1

C8114

1UF

20% 4V CERM-X6S 0201

GPU VCORE DE-COUPLING

NOTE: ATLEAST 2 GND VIAS & 2 POWER VIAS PER CAP

SYNC_MASTER=D2_SEAN

PAGE TITLE

KEPLER CORE/FB POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

81 OF 132

SHEET

72 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

NOTE:GDDR5 MODE H MAPPING

OMIT_TABLE

U8000

NV-GK107

BGA

(3 OF 10)

FB_A0_DQ<0>

95 75

BI

FB_A0_DQ<1>

95 75

BI

FB_A0_DQ<2>

95 75

BI

FB_A0_DQ<3>

95 75

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

FB_A0_DQ<4> FB_A0_DQ<5> FB_A0_DQ<6> FB_A0_DQ<7> FB_A0_DQ<8> FB_A0_DQ<9> FB_A0_DQ<10> FB_A0_DQ<11> FB_A0_DQ<12> FB_A0_DQ<13> FB_A0_DQ<14> FB_A0_DQ<15> FB_A0_DQ<16> FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<19> FB_A0_DQ<20> FB_A0_DQ<21> FB_A0_DQ<22> FB_A0_DQ<23> FB_A0_DQ<24> FB_A0_DQ<25> FB_A0_DQ<26> FB_A0_DQ<27> FB_A0_DQ<28> FB_A0_DQ<29> FB_A0_DQ<30> FB_A0_DQ<31> FB_A1_DQ<0> FB_A1_DQ<1> FB_A1_DQ<2> FB_A1_DQ<3> FB_A1_DQ<4> FB_A1_DQ<5> FB_A1_DQ<6> FB_A1_DQ<7> FB_A1_DQ<8> FB_A1_DQ<9> FB_A1_DQ<10> FB_A1_DQ<11> FB_A1_DQ<12> FB_A1_DQ<13> FB_A1_DQ<14> FB_A1_DQ<15> FB_A1_DQ<16> FB_A1_DQ<17> FB_A1_DQ<18> FB_A1_DQ<19> FB_A1_DQ<20> FB_A1_DQ<21> FB_A1_DQ<22> FB_A1_DQ<23> FB_A1_DQ<24> FB_A1_DQ<25> FB_A1_DQ<26> FB_A1_DQ<27> FB_A1_DQ<28> FB_A1_DQ<29> FB_A1_DQ<30> FB_A1_DQ<31>

FB_A0_WCLK_P<0> FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>

FB_A1_WCLK_P<0> FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1> FB_A1_WCLK_N<1>

D

C

B

A

L28 M29 L29 M28 N31 P29 R29 P28 J28 H29

J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32

L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33

K31 L30

H34 J34

AG30 AG31

AJ34 AK34

J30

NC

J31

NC

J32

NC

J33

NC

AH31

NC

AJ31

NC

AJ32

NC

AJ33

NC

MEM INTERFACE A

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_WCK01 FBA_WCK01*

FBA_WCK23 FBA_WCK23*

FBA_WCK45 FBA_WCK45*

FBA_WCK67 FBA_WCK67*

FBA_WCKB01 FBA_WCKB01*

FBA_WCKB23 FBA_WCKB23*

FBA_WCKB45 FBA_WCKB45*

FBA_WCKB67 FBA_WCKB67*

FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_CLK0*

FBA_CLK1*

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FB_DLL_AVDD

FBA_PLL_AVDD

FBA_DEBUG FBA_DEBUG

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

FBA_CMD_RFU FBA_CMD_RFU

FB_VDDQ_SENSE

FB_GND_SENSE

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9

FBA_CLK0

FBA_CLK1

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FB_CLAMP

U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33

V31

R30 R31 AB31 AC31

P30 F31 F34 M32 AD31 AL29 AM32 AF34

M30 H30 E34 M34 AF30 AK31 AM34 AF32

M31 G31 E33 M33

AE31 AK30 AN33 AF33

K27 U27

R28 AC28

J27 H27 H25

E1

R32 AC32

F1

F2

FB_A0_CS_L FB_A0_A<3> FB_A0_A<2> FB_A0_A<4> FB_A0_A<5> FB_A0_WE_L FB_A0_A<7> FB_A0_A<6> FB_A0_ABI_L FB_A0_A<8> FB_A0_A<0> FB_A0_A<1> FB_A0_RAS_L FB_A0_RESET_L FB_A0_CKE_L FB_A0_CAS_L FB_A1_CS_L FB_A1_A<3> FB_A1_A<2> FB_A1_A<4> FB_A1_A<5> FB_A1_WE_L FB_A1_A<7> FB_A1_A<6> FB_A1_ABI_L FB_A1_A<8> FB_A1_A<0> FB_A1_A<1> FB_A1_RAS_L FB_A1_RESET_L FB_A1_CKE_L FB_A1_CAS_L

FB_A0_CLK_P FB_A0_CLK_N FB_A1_CLK_P FB_A1_CLK_N

NC NC NC NC NC NC NC NC

PP1V05_GPU_FB_DLL_AVDD PP1V05_GPU_FB_PLL_AVDD

FB_CAL_PD_VDDQ FB_CAL_PU_GND FB_CAL_TERM_GND

FB_CLAMP

82

NC NC

GPU_FBVDDQ_SENSE

GPU_FBGND_SENSE

FB_CAL_PU_GND

73

PLACE_NEAR=U8000.H27:8.4MM

FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<3> FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3>

FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3> FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3>

73

1 2

60.4

10K

1 2

1%

MF

PLACE CLOSE TO BGA

95 75 73

73

GPU_FBA_DEBUG0 GPU_FBA_DEBUG1

R8201

1/20W

1% MF

R8261

1/20W

201

1

R8204

40.2

1% 1/20W MF 201

2

FB_A0_RESET_L

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75 73

OUT

95 75 73

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75 73

OUT

95 75 73

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

OUT

95 75

BI

95 75

BI

95 75

BI

95 75

BI

95 75

BI

95 75

BI

95 75

BI

95 75

BI

95 75

IN

95 75

IN

95 75

IN

95 75

IN

95 75

IN

95 75

IN

95 75

IN

95 75

IN

PLACE_NEAR=U8000.H25:8.4MM

201

=PP1V35_GPU_S0_FB

1

R8205

40.2

1%

PLACE_NEAR=U8000.J27:8.4MM 1/20W MF 201

2

FB_CAL_PD_VDDQ

1

R8250

10K

1% 1/20W MF 201

2

FB_A0_CKE_L

1

R8252

10K

1% 1/20W MF 201

2

FB VREF GEN (TEST ONLY)

1

2

73

8

73

FB_A1_RESET_L

95 75 73

=PP1V35_GPU_S0_FB

NOSTUFF

1

R8258

1.33K

1% 1/20W MF 201

2

NOSTUFF

1

R8259

1.33K

1% 1/20W MF 201

2

PLACE_NEAR=U8000.H26:8.4MM

=PP1V35_GPU_S0_FB

1

R8203

60.4

1% 1/20W MF 201

R8202

60.4

1% 1/20W MF 201

2

FB_A1_CKE_L

95 75 73

1

R8253

10K

1% 1/20W MF 201

2

73

8

PLACE_NEAR=U8000.H26:8.4MM

FB_VREF

73

NOSTUFF

1

C8260

0.1UF

10%

6.3V

2

X6S 0201

1

R8270

100

5% 1/20W MF 201

2

1

R8271

100

5% 1/20W MF 201

2

1

R8251

10K

1% 1/20W MF 201

2

73

8

OUT

Power aliases required by this page:

- =PP1V35_GPU_S0_FB

- =PP1V05_GPU_PEX_IOVDD

OMIT_TABLE

U8000

NV-GK107

BGA

(4 OF 10)

MEM INTRERFACE B

FB_B0_DQ<0>

95 76

BI

FB_B0_DQ<1>

95 76

BI

FB_B0_DQ<2>

95 76

95 75 73

BI

FB_B0_DQ<3>

95 76

BI

FB_B0_DQ<4>

95 76

BI

FB_B0_DQ<5>

95 76

BI

FB_B0_DQ<6>

95 76

BI

FB_B0_DQ<7>

95 76

BI

FB_B0_DQ<8>

95 76

BI

FB_B0_DQ<9>

95 76

BI

FB_B0_DQ<10>

95 76

BI

FB_B0_DQ<11>

95 76

BI

FB_B0_DQ<12>

95 76

BI

FB_B0_DQ<13>

95 76

BI

FB_B0_DQ<14>

95 76

BI

FB_B0_DQ<15>

95 76

BI

FB_B0_DQ<16>

95 76

BI

FB_B0_DQ<17>

95 76

BI

FB_B0_DQ<18>

95 76

BI

FB_B0_DQ<19>

95 76

BI

FB_B0_DQ<20>

95 76

BI

FB_B0_DQ<21>

95 76

BI

FB_B0_DQ<22>

95 76

BI

FB_B0_DQ<23>

95 76

BI

FB_B0_DQ<24>

95 76

BI

FB_B0_DQ<25>

95 76

BI

FB_B0_DQ<26>

95 76

BI

FB_B0_DQ<27>

95 76

BI

FB_B0_DQ<28>

95 76

BI

FB_B0_DQ<29>

95 76

BI

FB_B0_DQ<30>

95 76

BI

FB_B0_DQ<31>

95 76

BI

FB_B1_DQ<0>

95 76

BI

FB_B1_DQ<1>

95 76

BI

FB_B1_DQ<2>

95 76

BI

FB_B1_DQ<3>

95 76

BI

FB_B1_DQ<4>

95 76

BI

FB_B1_DQ<5>

95 76

BI

FB_B1_DQ<6>

95 76

BI

FB_B1_DQ<7>

95 76

BI

FB_B1_DQ<8>

95 76

BI

FB_B1_DQ<9>

95 76

BI

FB_B1_DQ<10>

95 76

BI

FB_B1_DQ<11>

95 76

BI

FB_B1_DQ<12>

95 76

BI

FB_B1_DQ<13>

95 76

BI

FB_B1_DQ<14>

95 76

BI

FB_B1_DQ<15>

95 76

BI

FB_B1_DQ<16>

95 76

BI

FB_B1_DQ<17>

95 76

BI

FB_B1_DQ<18>

95 76

BI

FB_B1_DQ<19>

95 76

BI

FB_B1_DQ<20>

95 76

BI

FB_B1_DQ<21>

95 76

BI

FB_B1_DQ<22>

95 76

BI

FB_B1_DQ<23>

95 76

BI

FB_B1_DQ<24>

95 76

BI

FB_B1_DQ<25>

95 76

BI

FB_B1_DQ<26>

95 76

BI

FB_B1_DQ<27>

95 76

BI

FB_B1_DQ<28>

95 76

BI

FB_B1_DQ<29>

95 76

BI

FB_B1_DQ<30>

95 76

BI

FB_B1_DQ<31>

95 76

BI

OUT OUT

FB_B0_WCLK_P<0> FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>

FB_B1_WCLK_P<0> FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>

95 76

97 74

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

F8

FBB_WCK01

E8

FBB_WCK01*

A5

FBB_WCK23

A6

FBB_WCK23*

D24

FBB_WCK45

D25

FBB_WCK45*

B27

FBB_WCK67

C27

FBB_WCK67*

D6

F26 E26

A26 A27

D7

C6 B6

FBB_WCKB01 FBB_WCKB01*

FBB_WCKB23 FBB_WCKB23*

FBB_WCKB45 FBB_WCKB45*

FBB_WCKB67 FBB_WCKB67*

NC NC

FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_CLK0*

FBB_CLK1*

FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

FBB_PLL_AVDD

FBB_DEBUG0 FBB_DEBUG1

FBB_CMD_RFU0 FBB_CMD_RFU1

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9

FBB_CLK0

FBB_CLK1

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FB_VREF

D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17

E17

D12 E12 E20 F20

E11 E3 A3 C9 F23 F27 C30 A24

D9

NC

E4

NC

B2

NC

A9

NC

D22

NC

D28

NC

A30

NC

B23

NC

D10 D5 C3 B9

E23 E28 B30 A23

H17

PP1V05_GPU_FB_PLL_AVDD

73

G14

GPU_FBB_DEBUG0

G20

GPU_FBB_DEBUG1

H26

FB_VREF

C12

NC

C20

NC

GPU_FBB_DEBUG0

73

GPU_FBB_DEBUG1

FB_B0_CS_L FB_B0_A<3> FB_B0_A<2> FB_B0_A<4> FB_B0_A<5> FB_B0_WE_L FB_B0_A<7> FB_B0_A<6> FB_B0_ABI_L FB_B0_A<8> FB_B0_A<0> FB_B0_A<1> FB_B0_RAS_L FB_B0_RESET_L FB_B0_CKE_L FB_B0_CAS_L FB_B1_CS_L FB_B1_A<3> FB_B1_A<2> FB_B1_A<4> FB_B1_A<5> FB_B1_WE_L FB_B1_A<7> FB_B1_A<6> FB_B1_ABI_L FB_B1_A<8> FB_B1_A<0> FB_B1_A<1> FB_B1_RAS_L FB_B1_RESET_L FB_B1_CKE_L FB_B1_CAS_L

FB_B0_CLK_P FB_B0_CLK_N FB_B1_CLK_P FB_B1_CLK_N

FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<2> FB_B0_DBI_L<3> FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3>

FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3> FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3>

73

1

R8206

60.4

1% 1/20W MF 201

2

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT OUT OUT

BI BI BI BI BI BI BI BI

IN IN IN IN IN IN IN IN

73

=PP1V35_GPU_S0_FB

1

R8207

60.4

1% 1/20W MF 201

2

95 76

8 73

95 76

79

95 76

95 76 73

95 76

=PP1V05_GPU_PEX_IOVDD

95 76

79 73

8

95 76

95 76 73

95 76

1

C8206

1UF

20% 4V

2

CERM-X6S 0201

73

8

=PP1V05_GPU_PEX_IOVDD

FB PLL & DLL VDD

95 76 73

76 75

1

C8207

0.1UF

10%

6.3V

2

X6S 0201

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

L8201

FERR-220-OHM-2A

1 2

0603

CRITICAL

ESR = 0.05OHM

L8202

FERR-220-OHM-2A

1 2

0603

CRITICAL

ESR = 0.05OHM

FB_B0_RESET_L

1

2

FB_B0_CKE_L

1

R8256

10K

1% 1/20W MF 201

2

MEM VREFC & VREFD SWITCH

FB_SW_LEG

OUT

SYNC_MASTER=D2_SEAN

PAGE TITLE

KEPLER FRAME BUFFER I/F

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

Page Notes

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C8201

20UF

20% 2V

2

X6T-CERM 0402

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C8208

20UF

20% 2V

2

X6T-CERM 0402

95 76 73

R8254

10K

1% 1/20W MF 201

3

D

2

1

2

FB_B1_RESET_L

95 76 73

Q8265

SSM3K15FV

SOD-VESM-HF

1

GS

GPU_ALT_VREF

6 3

12

PP1V05_GPU_FB_PLL_AVDD

1

C8202

2

1UF

20% 4V CERM-X6S 0201

1

C8203

0.1UF

10%

6.3V

2

X6S 0201

PP1V05_GPU_FB_DLL_AVDD

C8204

1UF

20% 4V CERM-X6S 0201

1

2

C8205

0.1UF

10%

6.3V X6S 0201

1

R8255

10K

1% 1/20W MF 201

2

FB_B1_CKE_L

1

R8257

10K

1% 1/20W MF 201

2

IN

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

82 OF 132

SHEET

73 OF 99

124578

78

4.18.0

D

73

C

95 76 73

B

A

SIZE

D

8 7 6 5 4 3

=PPVIN_S0GPU_P1V5P1V0

74

=PP5V_S0GPU_P1V0P1V35_GPU

74

8

UTQFN

PVCC

PGND

1

C8371

10UF

20% 10V

2

X6S-CERM 0603

20

1815

BOOT

17

UGATE

16

PHASE

1

LGATE

2

1

R8351

2.2

5% 1/16W MF-LF

402

EN

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

SET0

SET1

VID0

VID1

XW8350

2

19

VCC

U8350

ISL95870AH

CRITICAL

GND

3

SM

1 2

PP5V_S0GPU_P1V35_GPU

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

D

R8363

1/20W

=P1V35FB_EN

GPUFB_SENSE_DIV

GPUFB_SREF

GPUFB_VO

GPUFB_OCSET

GPUFB_PGOOD

GPUFB_RTN_DIV

GPUFB_FSEL

GPUFB_SET0

GPUFB_SET1

1

0

5%

MF

201

2

78

GPUFB_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

IN

FBVDD_ALTVO

10

7

12

11

14

4

13

8

9

6

5

PLACE_NEAR=U8350.1:1mm

88

1

2

IN

OUT

C8372

2.2UF

10% 16V X6S-CERM 0603

NOSTUFF

R8381

1.62K

IN

GPU_FBVDDQ_SENSE

VOLTAGE=1.35V

GPU_FBGND_SENSE

VOLTAGE=0V

73 97

97 73

C

1 2

R8353

1.62K

1 2

1%

1/20W

MF

201

1

C8376

10PF

5% 50V

2

COG-CERM 0201-1

1/20W

201

1% MF

C8373

0.01UF

10% 16V

X7R-CERM

0402

NOSTUFF

1

R8354

4.64K

1% 1/20W MF 201

2

NOSTUFF

1

R8352

4.64K

1% 1/20W MF 201

2

1

C8365

10PF

5% 50V

2

COG-CERM 0201-1

1

2

1

R8367

301K

1% 1/20W MF 201

2

1

R8368

150K

1% 1/20W MF 201

2

R8350

0

1 2

5%

1/20W

MF

201

GPUFB_SET_R

1

R8349

27K

1% 1/20W MF 201

2

8

GPUFB_BOOT_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

GPUFB_VBST

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

GPUFB_DRVH_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

GPUFB_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

DIDT=TRUE

GPUFB_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

R8359

1/16W MF-LF

OMIT_TABLE

CRITICAL

1

C8356

68UF

1

C8355

1

0.1UF

0

5%

402

10% 16V

2

X7R-CERM 0402

2

POLY-TANT

CASE-D2E-SM

20% 16V

2

PLACE_NEAR=Q8360.1:1.5MM

1

C8358

1000PF

5% 25V

2

NP0-C0G 402

1

2

C8362

1UF

10% 25V X5R 603-1

GPU FB SUPPLY

VOUT = 1.5V / 1.35V 13A MAX OUTPUT F = 500 KHZ

R8389

GPUFB_DRVH

1

12

5% 1/16W MF-LF

402

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

1

6

2 3 7

4 5

Q8360

SIZ710DT

CRITICAL

0.68UH-25A-5.5MOHM

8

CRITICAL

L8360

1 2

PCMC063T-SM

PP1V5R1V35_GPU_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

GPUFB_CS_P

99 96

XW8352

GPUFB_GPU_OCSET_R

R8371

4.75K

SM

1/20W

1% MF

201

CRITICAL

R8380

0.002

1% 1W MF

0612

1 2 3 4

PLACE_NEAR=L8360.2:1.5MM

C8361

1000PF

25V

NP0-C0G

GPUFB_CS_N

99 96

2

10% 16V

0201

1

12

1

2

XW8351

SM

GPUFB_GPU_VO_R

R8372

4.75K

1% 1/20W MF 201

1

C8370

2

1000PF

X7R-CERM

402

CRITICAL

1

C8360

1

5%

2

270UF

20%

2V

TANT

CASE-B4-SM

PLACE_NEAR=L8360.2:3MM

2

PLACE_NEAR=L8360.2:3MM

GPIO(16) VID1 VID0 FBVDD

376S0959

POWERPAK-6X3.7

0 0 1.5V

1 0 1.35V

12

=PP1V5R1V35_GPU_REG

CRITICAL

C8363

270UF

20%

2V

TANT

CASE-B4-SM

D

8

1

2

C

=PPVIN_S0GPU_P1V5P1V0

74

8

=PP5V_S0GPU_P1V0P1V35_GPU

74

P1V05_GPU_PEX_IOVDD_SNS_P

97 79

IN

VOLTAGE=1.05V

P1V05_GPU_PEX_IOVDD_SNS_N

97 79

IN

VOLTAGE=0V

B

1

R8304

3.01K

1% 1/16W MF-LF

402

2

<Ra>

1

R8306

2.74K

1% 1/16W

C8304

MF-LF

10PF

402

<Rb>

5%

2

50V

C0G-CERM

0402

A

1

R8305

3.01K

1% 1/16W MF-LF 402

2

<Ra>

1

R8307

2.74K

1%

1

1/16W MF-LF 402

2

1

<Rb>

2

C8305

10PF

5% 50V C0G-CERM 0402

1

C8303

2

88

C8302

0.047UF

10% 16V X7R-CERM 0402

IN

OUT

2.2UF

10% 16V X5R 603

PP5V_S0GPU_P1V05_GPU

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

1

2

Vout = 0.5V * (1 + Ra / Rb)

8

=P1V05_GPU_EN

P1V05_GPU_FB

P1V05_GPU_SREF

P1V05_GPU_VO

P1V05_GPU_OCSET

P1V05_S0GPU_PGOOD

P1V05_GPU_RTN

P1V05_GPU_FSEL

NOSTUFF

1

R8303

0

5% 1/20W MF 201

2

P1V05_GPU_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

OMIT_TABLE

CRITICAL

1

R8301

2.2

5% 1/16W MF-LF

402

2

VCC

U8310

ISL95870

3

EN

CRITICAL

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

GND

XW8300

SM

1 2

PLACE_NEAR=U8310.1:1mm

13

1

UTQFN

PVCC

PGND

1

C8301

10UF

20% 10V

2

X5R 603

14

BOOT

UGATE

PHASE

LGATE

12

11

10

15

P1V05_GPU_VBST P1V05_GPU_DRVH_R

P1V05_GPU_LL

P1V05_GPU_DRVL

16

P1V05_GPU_BOOT_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

R8325

1/16W MF-LF

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

DIDT=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

2.2

402

1

C8345

1

0.1UF

10%

5%

16V

2

X7R-CERM 0402

2

R8346

1

MIN_LINE_WIDTH=0.6 mm

12

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

5%

DIDT=TRUE

1/16W MF-LF

402

P1V05_GPU_DRVH

C8307

68UF

POLY-TANT

CASE-D2E-SM

376S1038

Q8310

CSD58873Q3D

CRITICAL

3

TG

4

TGR

5

BG

Q3D

20% 16V

2

1

VIN

6 7

VSW

8

P1V05_GPU_LL_FET

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

PGND

9

6 3

PLACE_NEAR=Q8310.1:1.5MM

1

C8308

1000PF

5% 25V

2

NP0-C0G 402

CRITICAL

L8310

2.2UH-14A

1 2 IHLP2525CZ-SM1

XW8302

P1V05_GPU_OCSET_R

SM

R8321

2.74K

1/20W

201

1

C8312

1UF

10% 25V

2

X5R 603-1

P1V05_S0GPU_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

P1V05_GPU_CS_P

98 96

P1V05_GPU_CS_N

98 96

2

1

1% MF

C8320

2

1000PF

12

10% 16V

X7R-CERM

0201

CRITICAL

1 2 3 4

2

XW8301

SM

1

P1V05_GPU_VO_R

1

R8322

2.74K

1% 1/20W MF 201

2

GPU 1V05 SUPPLY

R8345

0.003

1%

1W MF

0612

CRITICAL

C8310

1

CASE-B4-SM

2

PLACE_NEAR=L8310.2:3MM

270UF

TANT

C8309

1000PF

5%

25V

NP0-C0G

402

PLACE_NEAR=L8310.2:1.5MM

SYNC_MASTER=D2_SEAN

PAGE TITLE

1V05 GPU / 1V35 FB POWER SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

20%

2V

2

=PP1V05_S0GPU_REG

8

VOUT = 1.05V

5.3A MAX OUTPUT F = 500 KHZ

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

83 OF 132

SHEET

74 OF 99

124578

SIZE

B

A

D

Power aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

Signal aliases required by this page: (NONE)

BOM options provided by this page:

CK TERMINATION - A0

D

FB_A0_CLK_P FB_A0_CLK_N

73 75 95

PLACE_NEAR=U8400.J12:8.4MM

CK TERMINATION - A1

95 73 75

C

PLACE_NEAR=U8450.J12:8.4MM

=PP1V35_GPU_FBVDDQ

8

72

75 76

1

2

1

2

1

B

2

1

2

1

2

1

2

A

1

2

8 7 6 5 4 3

Page Notes

U8400

C8400

4.7UF

20%

6.3V X6S 0402

C8403

4.7UF

20%

6.3V X6S 0402

C8406

1UF

20% 4V CERM-X6S 0201

C8410

1UF

20% 4V CERM-X6S 0201

C8414

1UF

20% 4V CERM-X6S 0201

C8418

0.1UF

10%

6.3V X6S 0201

C8422

0.1UF

10%

6.3V X6S 0201

R8401

40.2

1 2

1%

1/20W

MF

201

R8400

120

1/20W

201

R8451

40.2

1 2

1%

1/20W

MF

201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1% MF

2

C8401

4.7UF

20%

6.3V X6S 0402

C8404

4.7UF

20%

6.3V X6S 0402

C8407

1UF

20% 4V CERM-X6S 0201

C8411

1UF

20% 4V CERM-X6S 0201

C8415

1UF

20% 4V CERM-X6S 0201

C8419

0.1UF

10%

6.3V X6S 0201

C8423

0.1UF

10%

6.3V X6S 0201

FBA0_CK_MID

R8404

120

1/20W

FBA1_CK_MIDFB_A1_CLK_P

1

2

PLACE_NEAR=U8400.J11:8.4MM

R8402

40.2

1 2

1%

1/20W

MF

201

1

C8490

0.01UF

10% 10V

2

X7R-CERM

PLACE_NEAR=U8400.J11:8.4MM

0201

1

R8403

1% MF

201

2

PLACE_NEAR=U8450.J11:8.4MM

1 2

C8491

0.01UF

10% 10V X7R-CERM 0201

1

C8402

4.7UF

20%

6.3V

2

X6S 0402

1

C8405

4.7UF

20%

6.3V

2

X6S 0402

1

C8408 1UF

20% 4V

2

CERM-X6S 0201

1

C8412 1UF

20% 4V

2

CERM-X6S 0201

1

C8416

0.1UF

10%

6.3V

2

X6S 0201

1

C8420

0.1UF

10%

6.3V

2

X6S 0201

1

C8424

0.1UF

10%

6.3V

2

X6S 0201

75

120

1/20W

201

R8452

FB_A1_CLK_N

40.2

1%

1/20W

MF

201

PLACE_NEAR=U8450.J11:8.4MM

1

C8409

1UF

20% 4V

2

CERM-X6S 0201

1

C8413

1UF

20% 4V

2

CERM-X6S 0201

1

C8417

0.1UF

10%

6.3V

2

X6S 0201

1

C8421

0.1UF

10%

6.3V

2

X6S 0201

1

C8425

0.1UF

10%

6.3V

2

X6S 0201

FB_A0_VREFC FB_A0_VREFD

32MX32-1.25GHZ-MFL

VSS

VSSQ

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

H11 K10 K11 H10

J12 J11 G12 L12

J13

J10

C13 R13

K4 H5 H4 K5 J3

L3 G3

J1

J2

J4

C2

R2

D4 D5

P4 P5

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

CK CK* CS* WE* CAS* RAS*

MFZQ(MF=0) SEN RESET*

ABI*

EDC0 EDC1 EDC2 EDC3

WCK01 WCK01*

WCK23 WCK23*

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_A0_VREFD

75

PLACE_NEAR=U8400.A10:8.4MM

FB_A0_A<2>

73 95

IN

FB_A0_A<5>

73 95

IN

FB_A0_A<4>

73 95

IN

FB_A0_A<3>

73 95

IN

FB_A0_A<7>

73 95

IN

FB_A0_A<1>

73 95

IN

FB_A0_A<0>

73 95

73 75 95

1

1% MF

2

73 75 95

IN

73 95

IN

73 95

IN

73 75 95

IN

73 75 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

IN

73 95

IN

73 95

IN

73 95

IN

32MX32-1.25GHZ-MFL

C5 C10 D11

G1

G4 G11 G14

VDD

L1

L4 L11 L14 P11

R5 R10

B1

B3 B12 B14

D1

D3 D12 D14

E5 E10

F1

F3 F12 F14

G2 G13

VDDQ

H3 H12

K3 K12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

VREFC

A10

VREFD

U10

FB_A0_A<6> FB_A0_CKE_L

FB_A0_CLK_P FB_A0_CLK_N FB_A0_CS_L FB_A0_WE_L FB_A0_CAS_L FB_A0_RAS_L FB_A0_ZQ FB_A0_MF FB_A0_SEN FB_A0_RESET_L

FB_A0_ABI_L

FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3>

FB_A0_WCLK_P<0> FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>

U8400

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

BGA

H5GQ1H24AFR-T2C

D2

C8431 820PF

10% 25V X7R-CERM 0201

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5 J5

NC

U5

1

R8430

549

1% 1/20W MF 201

2

PLACE_NEAR=U8400.J14:8.4MM

1

R8431

1.33K

1% 1/20W MF 201

2

NC

PLACE_NEAR=U8400.J14:8.4MM

(1 OF 2)

OMIT_TABLE

=PP1V35_GPU_FBVDDQ

8

72 75 76

FB_A0_VREFC

75 75

1

2

PLACE_NEAR=U8400.J14:8.4MM

PLACE CLOSE TO U8400

=PP1V35_GPU_FBVDDQ

8

72 75 76

PLACE_NEAR=U8400.U10:8.4MM

R8432

1

549

1% 1/20W MF 201

2

1

C8432

820PF

10% 25V

2

X7R-CERM 0201

1

C8433

820PF

10% 25V

2

X7R-CERM 0201

PLACE_NEAR=U8400.U10:8.4MM

R8433

1.33K

1% 1/20W MF 201

2

PLACE_NEAR=U8400.U10:8.4MM

FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<3>

FB_A0_DQ<0> FB_A0_DQ<1> FB_A0_DQ<2> FB_A0_DQ<3> FB_A0_DQ<4> FB_A0_DQ<5> FB_A0_DQ<6> FB_A0_DQ<7> FB_A0_DQ<8> FB_A0_DQ<9> FB_A0_DQ<10> FB_A0_DQ<11> FB_A0_DQ<12> FB_A0_DQ<13> FB_A0_DQ<14> FB_A0_DQ<15> FB_A0_DQ<16> FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<19> FB_A0_DQ<20> FB_A0_DQ<21> FB_A0_DQ<22> FB_A0_DQ<23> FB_A0_DQ<24> FB_A0_DQ<25> FB_A0_DQ<26> FB_A0_DQ<27> FB_A0_DQ<28> FB_A0_DQ<29> FB_A0_DQ<30> FB_A0_DQ<31>

FB_A0_A<8>

PLACE_NEAR=U8400.J14:8.4MM

1

R8434 931

1% 1/20W MF 201

2

FB_SW_LEG

PLACE_NEAR=U8400.U10:8.4MM

1

R8435 931

1% 1/20W MF 201

2

FB_SW_LEG

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

IN

=PP1V35_GPU_FBVDDQ

8

72 75 76

1

C8450

4.7UF

20%

6.3V

2

X6S 0402

1

C8453

4.7UF

20%

6.3V

2

X6S 0402

1

C8456

73 75 76

IN IN

73 75

IN

76

1UF

20% 4V

2

CERM-X6S 0201

1

C8460

1UF

20% 4V

2

CERM-X6S 0201

1

C8464

1UF

20% 4V

2

CERM-X6S 0201

1

C8468

0.1UF

10%

6.3V

2

X6S 0201

1

C8472

0.1UF

10%

6.3V

2

X6S 0201

R8450

120

1/20W

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1% MF

201

2

C8451

4.7UF

20%

6.3V X6S 0402

C8454

4.7UF

20%

6.3V X6S 0402

C8457

1UF

20% 4V CERM-X6S 0201

C8461

1UF

20% 4V CERM-X6S 0201

C8465

1UF

20% 4V CERM-X6S 0201

C8469

0.1UF

10%

6.3V X6S 0201

C8473

0.1UF

10%

6.3V X6S 0201

R8454

120

1/20W

201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1% MF

2

C8452

4.7UF

20%

6.3V X6S 0402

C8455

4.7UF

20%

6.3V X6S 0402

C8458

1UF

20% 4V CERM-X6S 0201

C8462

1UF

20% 4V CERM-X6S 0201

C8466

0.1UF

10%

6.3V X6S 0201

C8470

0.1UF

10%

6.3V X6S 0201

C8474

0.1UF

10%

6.3V X6S 0201

FB_A1_VREFC

75

FB_A1_VREFD

75

R8453

120

1/20W

201

1

C8459

1UF

20% 4V

2

CERM-X6S 0201

1

C8463

1UF

20% 4V

2

CERM-X6S 0201

1

C8467

0.1UF

10%

6.3V

2

X6S 0201

1

C8471

0.1UF

10%

6.3V

2

X6S 0201

1

C8475

0.1UF

10%

6.3V

2

X6S 0201

1

1% MF

2

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 75 95

IN

73 75 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

IN

73 95

IN

73 95

IN

73 95

IN

32MX32-1.25GHZ-MFL

C5 C10 D11

G1

G4 G11 G14

VDD

L1

L4 L11 L14 P11

R5 R10

B1

B3 B12 B14

D1

D3 D12 D14

E5 E10

F1

F3 F12 F14

G2 G13

VDDQ

H3 H12

K3 K12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

VREFC

A10

VREFD

U10

6 3

FB_A1_A<2> FB_A1_A<5> FB_A1_A<4> FB_A1_A<3>

FB_A1_A<7> FB_A1_A<1> FB_A1_A<0> FB_A1_A<6> FB_A1_CKE_L

FB_A1_CLK_P FB_A1_CLK_N FB_A1_CS_L FB_A1_WE_L FB_A1_CAS_L

FB_A1_RAS_L FB_A1_ZQ FB_A1_MF FB_A1_SEN

FB_A1_RESET_L

FB_A1_ABI_L

FB_A1_EDC<0>

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A1_EDC<3>

FB_A1_WCLK_P<0>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

U8450

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

VSSQ

VSS

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

32MX32-1.25GHZ-MFL

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

J1

MFZQ(MF=0)

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

U8450

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT_TABLE

PLACE_NEAR=U8450.A10:8.4MM

D2

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5

NC

J5

NC

U5

NC

=PP1V35_GPU_FBVDDQ

8

72 75 76

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3>

FB_A1_DQ<0> FB_A1_DQ<1> FB_A1_DQ<2> FB_A1_DQ<3> FB_A1_DQ<4> FB_A1_DQ<5> FB_A1_DQ<6> FB_A1_DQ<7> FB_A1_DQ<8> FB_A1_DQ<9> FB_A1_DQ<10> FB_A1_DQ<11> FB_A1_DQ<12> FB_A1_DQ<13> FB_A1_DQ<14> FB_A1_DQ<15> FB_A1_DQ<16> FB_A1_DQ<17> FB_A1_DQ<18> FB_A1_DQ<19> FB_A1_DQ<20> FB_A1_DQ<21> FB_A1_DQ<22> FB_A1_DQ<23> FB_A1_DQ<24> FB_A1_DQ<25> FB_A1_DQ<26> FB_A1_DQ<27> FB_A1_DQ<28> FB_A1_DQ<29> FB_A1_DQ<30> FB_A1_DQ<31>

FB_A1_A<8>

FB_A1_VREFC

1

C8481

820PF

10% 25V

2

X7R-CERM 0201

PLACE_NEAR=U8450.J14:8.4MM

PLACE CLOSE TO U8450

=PP1V35_GPU_FBVDDQ

8

72 75 76

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_A1_VREFD

75

1

C8482

820PF

10% 25V

2

X7R-CERM 0201

PLACE_NEAR=U8450.U10:8.4MM

SYNC_MASTER=D2_SEAN

PAGE TITLE

1

C8483

820PF

10% 25V

2

X7R-CERM 0201

GDDR5 Frame Buffer A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

1

R8480

549

1%

PLACE_NEAR=U8450.J14:8.4MM

1/20W MF 201

2

PLACE_NEAR=U8450.J14:8.4MM

1

R8481

1.33K

1% 1/20W MF 201

2

PLACE_NEAR=U8450.U10:8.4MM

R8482

1

549

1% 1/20W MF 201

2

PLACE_NEAR=U8450.U10:8.4MM

1

R8483

1.33K

1% 1/20W MF 201

2

PLACE_NEAR=U8450.J14:8.4MM

1

R8484 931

1% 1/20W MF 201

2

FB_SW_LEG

PLACE_NEAR=U8450.U10:8.4MM

1

R8485 931

1% 1/20W MF 201

2

FB_SW_LEG

12

73 95

73 75 76

IN

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

84 OF 132

SHEET

75 OF 99

124578

SIZE

D

C

B

A

D

Power aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

Signal aliases required by this page: (NONE)

BOM options provided by this page:

(NONE)

CK TERMINATION - B0

D

FB_B0_CLK_P

73 76 95

PLACE_NEAR=U8500.J12:8.4MM

CK TERMINATION - B1

FB_B1_CLK_P

95 73 76

C

PLACE_NEAR=U8550.J12:8.4MM

=PP1V35_GPU_FBVDDQ

8

72

75 76

1

2

1

2

1

B

A

2

1

2

1

2

1

2

1

2

8 7 6 5 4 3

Page Notes

U8500

1 2

C8500

4.7UF

20%

6.3V X6S 0402

C8503

4.7UF

20%

6.3V X6S 0402

C8506

1UF

20% 4V CERM-X6S 0201

C8510

1UF

20% 4V CERM-X6S 0201

C8514

1UF

20% 4V CERM-X6S 0201

C8518

0.1UF

10%

6.3V X6S 0201

C8522

0.1UF

10%

6.3V X6S 0201

R8501

40.2

1 2

1%

1/20W

MF

201

R8500

120

1%

1/20W

MF

201

R8551

40.2

1%

1/20W

MF

201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

FBB0_CK_MID

1

2

FBB1_CK_MID

C8501

4.7UF

20%

6.3V X6S 0402

C8504

4.7UF

20%

6.3V X6S 0402

C8507

1UF

20% 4V CERM-X6S 0201

C8511

1UF

20% 4V CERM-X6S 0201

C8515

1UF

20% 4V CERM-X6S 0201

C8519

0.1UF

10%

6.3V X6S 0201

C8523

0.1UF

10%

6.3V X6S 0201

PLACE_NEAR=U8500.J11:8.4MM

1 2

1

C8590

0.01UF

10% 10V

2

X7R-CERM

PLACE_NEAR=U8500.J11:8.4MM

0201

1

R8504

120

1%

1/20W

MF

201

2

PLACE_NEAR=U8550.J11:8.4MM

R8552

40.2

1 2

1/20W

1

C8591

0.01UF

10% 10V

2

X7R-CERM 0201

1

C8502

4.7UF

20%

6.3V

2

X6S 0402

1

C8505

4.7UF

20%

6.3V

2

X6S 0402

1

C8508 1UF

20% 4V

2

CERM-X6S 0201

1

C8512 1UF

20% 4V

2

CERM-X6S 0201

1

C8516

0.1UF

10%

6.3V

2

X6S 0201

1

C8520

0.1UF

10%

6.3V

2

X6S 0201

1

C8524

0.1UF

10%

6.3V

2

X6S 0201

FB_B0_VREFC

76

FB_B0_VREFD

76

R8502

FB_B0_CLK_N

40.2

1%

1/20W

MF

201

1

R8503

120

1%

1/20W

MF

201

2

FB_B1_CLK_N

1% MF

201

PLACE_NEAR=U8550.J11:8.4MM

1

C8509

1UF

20% 4V

2

CERM-X6S 0201

1

C8513

1UF

20% 4V

2

CERM-X6S 0201

1

C8517

0.1UF

10%

6.3V

2

X6S 0201

1

C8521

0.1UF

10%

6.3V

2

X6S 0201

1

C8525

0.1UF

10%

6.3V

2

X6S 0201

73 76 95

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 76 95

IN

73 76 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

IN

73 95

IN

73 95

IN

73 95

IN

32MX32-1.25GHZ-MFL

C5 C10 D11

G1

G4 G11 G14

VDD

L1

L4 L11 L14 P11

R5 R10

B1

B3 B12 B14

D1

D3 D12 D14

E5 E10

F1

F3 F12 F14

G2 G13

VDDQ

H3 H12

K3 K12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

VREFC

A10

VREFD

U10

FB_B0_A<2> FB_B0_A<5> FB_B0_A<4> FB_B0_A<3>

FB_B0_A<7> FB_B0_A<1> FB_B0_A<0> FB_B0_A<6> FB_B0_CKE_L

FB_B0_CLK_P FB_B0_CLK_N FB_B0_CS_L FB_B0_WE_L FB_B0_CAS_L FB_B0_RAS_L FB_B0_ZQ FB_B0_MF FB_B0_SEN FB_B0_RESET_L

FB_B0_ABI_L

FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3>

FB_B0_WCLK_P<0> FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>

U8500

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

VSS

VSSQ

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

H11 K10 K11 H10

J12 J11 G12 L12

J13

J10

C13 R13

K4 H5 H4 K5 J3

L3 G3

J1

J2

J4

C2

R2

D4 D5

P4 P5

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

CK CK* CS* WE* CAS* RAS*

MFZQ(MF=0) SEN RESET*

ABI*

EDC0 EDC1 EDC2 EDC3

WCK01 WCK01*

WCK23 WCK23*

PLACE_NEAR=U8500.A10:8.4MM

32MX32-1.25GHZ-MFL

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_B0_VREFD

76

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT_TABLE

=PP1V35_GPU_FBVDDQ

8

72 75 76

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_B0_VREFC

76

1

C8531 820PF

10% 25V

2

X7R-CERM 0201

PLACE_NEAR=U8500.J14:8.4MM

PLACE CLOSE TO U8500

=PP1V35_GPU_FBVDDQ

8

72 75 76

1

C8532 820PF

10% 25V

2

X7R-CERM 0201

PLACE_NEAR=U8500.U10:8.4MM

1

C8533

820PF

10% 25V

2

X7R-CERM 0201

D2

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5 J5

NC

U5

PLACE_NEAR=U8500.J14:8.4MM

1

R8530

549

1% 1/20W MF 201

2

PLACE_NEAR=U8500.J14:8.4MM

1

R8531

1.33K

1% 1/20W MF 201

2

PLACE_NEAR=U8500.U10:8.4MM

1

R8532

549

1% 1/20W MF 201

2

PLACE_NEAR=U8500.U10:8.4MM

1

R8533

1.33K

1% 1/20W MF 201

2

FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<2> FB_B0_DBI_L<3>

FB_B0_DQ<0> FB_B0_DQ<1> FB_B0_DQ<2> FB_B0_DQ<3> FB_B0_DQ<4> FB_B0_DQ<5> FB_B0_DQ<6> FB_B0_DQ<7> FB_B0_DQ<8> FB_B0_DQ<9> FB_B0_DQ<10> FB_B0_DQ<11> FB_B0_DQ<12> FB_B0_DQ<13> FB_B0_DQ<14> FB_B0_DQ<15> FB_B0_DQ<16> FB_B0_DQ<17> FB_B0_DQ<18> FB_B0_DQ<19> FB_B0_DQ<20> FB_B0_DQ<21> FB_B0_DQ<22> FB_B0_DQ<23> FB_B0_DQ<24> FB_B0_DQ<25> FB_B0_DQ<26> FB_B0_DQ<27> FB_B0_DQ<28> FB_B0_DQ<29> FB_B0_DQ<30> FB_B0_DQ<31>

NC

FB_B0_A<8>

NC

1

R8534 931

1% 1/20W MF 201

2

FB_SW_LEG

PLACE_NEAR=U8500.J14:8.4MM

1

R8535 931

1% 1/20W MF 201

2

FB_SW_LEG

PLACE_NEAR=U8500.U10:8.4MM

73 75 76

IN

73 75 76

IN

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

IN

=PP1V35_GPU_FBVDDQ

8

72 75 76

1

C8550

4.7UF

20%

6.3V

2

X6S 0402

1

C8553

4.7UF

20%

6.3V

2

X6S 0402

1

C8556

1UF

20% 4V

2

CERM-X6S 0201

1

C8560

1UF

20% 4V

2

CERM-X6S 0201

1

C8564

1UF

20% 4V

2

CERM-X6S 0201

1

C8568

0.1UF

10%

6.3V

2

X6S 0201

1

C8572

0.1UF

10%

6.3V

2

X6S 0201

R8550

120

1/20W

201

1% MF

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

C8551

4.7UF

20%

6.3V X6S 0402

C8554

4.7UF

20%

6.3V X6S 0402

C8557

1UF

20% 4V CERM-X6S 0201

C8561

1UF

20% 4V CERM-X6S 0201

C8565

1UF

20% 4V CERM-X6S 0201

C8569

0.1UF

10%

6.3V X6S 0201

C8573

0.1UF

10%

6.3V X6S 0201

R8554

120

1/20W

201

1

1% MF

2

1

C8552

4.7UF

20%

6.3V

2

X6S 0402

1

C8555

4.7UF

20%

6.3V

2

X6S 0402

1

C8558

1UF

20% 4V

2

CERM-X6S 0201

1

C8562

1UF

20% 4V

2

CERM-X6S 0201

1

C8566

0.1UF

10%

6.3V

2

X6S 0201

1

C8570

0.1UF

10%

6.3V

2

X6S 0201

1

C8574

0.1UF

10%

6.3V

2

X6S 0201

76

R8553

1/20W

1

2

1

2

1

2

1

2

1

2

FB_B1_VREFC FB_B1_VREFD

1

120

1% MF

201

2

C8559

1UF

20% 4V CERM-X6S 0201

C8563

1UF

20% 4V CERM-X6S 0201

C8567

0.1UF

10%

6.3V X6S 0201

C8571

0.1UF

10%

6.3V X6S 0201

C8575

0.1UF

10%

6.3V X6S 0201

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 76 95

IN

73 76 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

IN

73 95

BI

73 95

BI

73 95

BI

73 95

BI

73 95

IN

73 95

IN

73 95

IN

73 95

IN

32MX32-1.25GHZ-MFL

C5 C10 D11

G1

G4 G11 G14

VDD

L1

L4 L11 L14 P11

R5 R10

B1

B3 B12 B14

D1

D3 D12 D14

E5 E10

F1

F3 F12 F14

G2 G13

VDDQ

H3 H12

K3 K12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

VREFC

A10

VREFD

U10

6 3

FB_B1_A<2> FB_B1_A<5> FB_B1_A<4> FB_B1_A<3>

FB_B1_A<7> FB_B1_A<1> FB_B1_A<0> FB_B1_A<6> FB_B1_CKE_L

FB_B1_CLK_P FB_B1_CLK_N

FB_B1_CS_L FB_B1_WE_L FB_B1_CAS_L FB_B1_RAS_L FB_B1_ZQ FB_B1_MF FB_B1_SEN FB_B1_RESET_L

FB_B1_ABI_L

FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3>

FB_B1_WCLK_P<0> FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>

U8550

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

VSSQ

VSS

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

32MX32-1.25GHZ-MFL

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

J1

MFZQ(MF=0)

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

U8550

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT_TABLE

PLACE_NEAR=U8550.J14:8.4MM

PLACE_NEAR=U8550.A10:8.4MM

D2

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5

NC

J5

NC

U5

NC

=PP1V35_GPU_FBVDDQ

8

72 75 76

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_B1_VREFC

76

1

2

C8581

820PF

10% 25V X7R-CERM 0201

FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3>

FB_B1_DQ<0> FB_B1_DQ<1> FB_B1_DQ<2> FB_B1_DQ<3> FB_B1_DQ<4> FB_B1_DQ<5> FB_B1_DQ<6> FB_B1_DQ<7> FB_B1_DQ<8> FB_B1_DQ<9> FB_B1_DQ<10> FB_B1_DQ<11> FB_B1_DQ<12> FB_B1_DQ<13> FB_B1_DQ<14> FB_B1_DQ<15> FB_B1_DQ<16> FB_B1_DQ<17> FB_B1_DQ<18> FB_B1_DQ<19> FB_B1_DQ<20> FB_B1_DQ<21> FB_B1_DQ<22> FB_B1_DQ<23> FB_B1_DQ<24> FB_B1_DQ<25> FB_B1_DQ<26> FB_B1_DQ<27> FB_B1_DQ<28> FB_B1_DQ<29> FB_B1_DQ<30> FB_B1_DQ<31>

FB_B1_A<8>

PLACE CLOSE TO U8550

=PP1V35_GPU_FBVDDQ

8

72 75 76

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_B1_VREFD

76

1

C8582

820PF

10% 25V

2

X7R-CERM 0201

PLACE_NEAR=U8550.U10:8.4MM

SYNC_MASTER=D2_SEAN

PAGE TITLE

1

C8583

820PF

10% 25V

2

X7R-CERM 0201

GDDR5 Frame Buffer B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

PLACE_NEAR=U8550.J14:8.4MM

1

R8580

549

1% 1/20W MF 201

2

PLACE_NEAR=U8550.J14:8.4MM

R8582

549

1% 1/20W MF 201

R8583

1.33K

1% 1/20W MF 201

PLACE_NEAR=U8550.J14:8.4MM

1

R8584 931

1% 1/20W MF 201

2

FB_SW_LEG

1

2

1

R8581

1.33K

1% 1/20W MF 201

2

PLACE_NEAR=U8550.U10:8.4MM

1

2

PLACE_NEAR=U8550.U10:8.4MM

1

2

12

73 95

73 75 76

IN

PLACE_NEAR=U8550.U10:8.4MM

R8585 931

1% 1/20W MF 201

FB_SW_LEG

73 75 76

IN

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

85 OF 132

SHEET

76 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

PD FOR AUX CHANNELS (FOR NVIDIA)

77 82 95

1

R8615

100K

1% 1/20W MF 201

2

D

NO STUFF

1

R8627

100K

1% 1/20W MF 201

2

1

R8616

100K

1% 1/20W MF 201

2

NO STUFF

1

R8628

100K

1% 1/20W MF 201

2

77 83 95

C

=PP3V3_GPU_IFPX_PLLVDD

IFPX PLLVDD

B

=PP1V05_GPU_IFPCD_IOVDD

IFP CD IOVDD

=PP1V05_GPU_IFPEF_IOVDD

IFP EF IOVDD

A

DP_INT_EG_AUX_P DP_INT_EG_AUX_N

DP_TBTSNK0_EG_AUXCH_P DP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK1_EG_AUXCH_P DP_TBTSNK1_EG_AUXCH_N

HDMI_EG_DDC_CLK_Q HDMI_EG_DDC_DATA_Q

CRITICAL

L8604

330-OHM-1.2A

1 2

0603

1

C8613

2

10UF

20% 10V X6S-CERM 0603

1

C8619

4.7UF

10%

6.3V

2

X6S-CERM 0603

L8605

FERR-220-OHM-2A

1 2

0603

CRITICAL

ESR = 0.05OHM

L8606

FERR-220-OHM-2A

1 2

0603

CRITICAL

ESR = 0.05OHM

1

C8633

4.7UF

20%

6.3V

2

X6S 0402

1

R8613

100K

1% 1/20W MF 201

2

1

R8618

100K

1% 1/20W MF 201

2

1

R8623

4.7K

1% 1/20W MF 201

2

PP3V3_GPU_IFPX_PLLVDD

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

C8612

0.1UF

20% 16V

2

X6S-CERM 0201

1

2

C8610

10UF

20% 10V X6S-CERM 0603

77 83 95

77

=PP3V3_GPU_VDD33

8

71 77 78 79

1

2

1

R8614

100K

1% 1/20W MF 201

2

1

R8617

100K

1% 1/20W MF 201

2

C8611

1UF

10% 25V X6S-CERM 0402

PLACE BELOW GPU NEAR DISPLAY SECTION

1

C8634

4.7UF

20%

6.3V

2

X6S 0402

1

C8615

1UF

2

1

C8625

4.7UF

2

1

C8629

10UF

2

10% 25V X6S-CERM 0402

20%

6.3V X6S 0402

20% 4V X6S-CERM 0402-1

1

C8616

1UF

10% 25V

2

X6S-CERM 0402

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

1

C8626

1UF

20% 4V

2

CERM-X6S 0201

1

C8655

10UF

20% 4V

2

X6S-CERM 0402-1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

1

C8630

1UF

20% 4V

2

CERM-X6S 0201

1

C8635

1UF

20% 4V

2

CERM-X6S 0201

1

C8617

2

PP1V05_GPU_IFPCD_IOVDD

1

C8627

0.1UF

20% 16V

2

X6S-CERM 0201

1

C8656

1UF

20% 4V

2

CERM-X6S 0201

PP1V05_GPU_IFPEF_IOVDD

1

C8631

0.1UF

20% 16V

2

X6S-CERM 0201 0201

1

C8636

1UF

20% 4V

2

CERM-X6S 0201

1

R8624

4.7K

1% 1/20W MF 201

2

1

0.1UF

20% 16V X6S-CERM 0201 0201

C8618

0.1UF

20% 16V

2

X6S-CERM

1

C8628

0.1UF

20% 16V

2

X6S-CERM 0201

1

C8657

0.1UF

20% 16V

2

X6S-CERM 0201 0201

1

C8632

0.1UF

20% 16V

2

X6S-CERM

1

C8637

0.1UF

20% 16V

2

X6S-CERM 0201

77

1

C8658

0.1UF

20% 16V

2

X6S-CERM

83

78

83

77

1

C8638

0.1UF

20% 16V

2

X6S-CERM 0201

PP1V8_GPU_IFPA_IOVDD

77

PP3V3_GPU_IFPB_IOVDD

77

PP1V05_GPU_IFPCD_IOVDD

77

PP1V05_GPU_IFPCD_IOVDD

77

PP1V05_GPU_IFPEF_IOVDD

77

PP1V05_GPU_IFPEF_IOVDD

77

PP1V05_GPU_IFPAB_PLLVDD

77

PP3V3_GPU_IFPX_PLLVDD

77

IFPC_RSET

77

PP3V3_GPU_IFPX_PLLVDD

77

IFPD_RSET

77

PP3V3_GPU_IFPX_PLLVDD

77

IFPEF_RSET

77

DPA_EG_DDC_CLK

OUT

DPA_EG_DDC_DATA

BI

GPU_SSC_SMB_CLK GPU_SSC_SMB_DAT

GPU_SMB_CLK

OUT

GPU_SMB_DAT

BI

DPB_EG_DDC_CLK

OUT

DPB_EG_DDC_DATA

BI

DDC MAPPING

--------------------I2CA -> IFPE

I2CB -> IFPF I2CC -> SSC CLK GEN

1

2

77

DAC_AVDD

R8600

10K

1% 1/20W MF 201

OMIT_TABLE

CRITICAL

U8000

NV-GK107

BGA

AG8 AM6 AG9 AF6 AG6 AC7 AC8

AH8 AJ8

NC

AF7 AF8

AG7 AN2

AB8 AD6

R4 R5

R2 R3

T4 T3

R7 R6

AG10

AP9

NC

AP8

NC

(5 OF 10) IFPA_IOVDD IFPB_IOVDD IFPC_IOVDD IFPD_IOVDD IFPE_IOVDD IFPF_IOVDD

IFPAB_PLLVDD IFPAB_RSET

IFPC_PLLVDD IFPC_RSET

IFPD_PLLVDD IFPD_RSET

IFPEF_PLLVDD IFPEF_RSET

I2CA_SCL I2CA_SDA

IFPC_AUX_I2CW_SCL

IFPC_AUX_I2CW_SDA* I2CC_SCL I2CC_SDA

I2CS_SCL I2CS_SDA

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA*

I2CB_SCL I2CB_SDA

IFPE_AUX_I2CY_SCL

IFPE_AUX_I2CY_SDA*

IFPF_AUX_I2CZ_SCL

IFPF_AUX_I2CZ_SDA*

DACA_VDD DACA_RED

DACA_VREF DACA_RSET

IFPA_TXC

IFPA_TXC*

IFPA_TXD0

IFPA_TXD0*

IFPA_TXD1

IFPA_TXD1*

IFPA_TXD2

IFPA_TXD2*

IFPA_TXD3

IFPA_TXD3*

IFPB_TXC

IFPB_TXC*

IFPB_TXD4

IFPB_TXD4*

IFPB_TXD5

IFPB_TXD5*

IFPB_TXD6

IFPB_TXD6*

IFPB_TXD7

IFPB_TXD7*

IFPC_L0

IFPC_L0*

IFPC_L1

IFPC_L1*

IFPC_L2

IFPC_L2*

IFPC_L3

IFPC_L3*

IFPD_L0

IFPD_L0*

IFPD_L1

IFPD_L1*

IFPD_L2

IFPD_L2*

IFPD_L3

IFPD_L3*

IFPE_L0

IFPE_L0*

IFPE_L1

IFPE_L1*

IFPE_L2

IFPE_L2*

IFPE_L3

IFPE_L3*

IFPF_L0

IFPF_L0*

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L2*

IFPF_L3

IFPF_L3*

DACA_GREEN

DACA_BLUE

DACA_HSYNC DACA_VSYNC

CEC

AN6

AP3 AN3 AN5 AM5 AL6 AK6 AJ6 AH6

AJ9 AH9

AP6 AP5 AM7 AL7 AN8 AM8 AK8 AL8

AG3 AG2

AK1 AJ1 AJ3 AJ2 AH3 AH4 AG5 AG4

AK3 AK2

AM1 AM2 AM3 AM4 AL3 AL4 AK4 AK5

AB3 AB4

AD2 AD3 AD1 AC1 AC2 AC3 AC4 AC5

AF3 AF2

AE3 AE4 AF4 AF5 AD4 AD5 AG1 AF1

AK9 AL10 AL9

AM9 AN9

L3

NC NC

NC NC NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC

77

NC NC NC

NC NC

NC

DISABLE PHY A & B FOR 15" MBP

=PP3V3_GPU_VDD33

79

8

71

77 78

1

R8625

4.7K

1% 1/20W MF 201

2

HDMI_EG_DDC_CLK_Q HDMI_EG_DDC_DATA_Q

77

HDMI_EG_DATA_C_P<2> HDMI_EG_DATA_C_N<2> HDMI_EG_DATA_C_P<1> HDMI_EG_DATA_C_N<1> HDMI_EG_DATA_C_P<0> HDMI_EG_DATA_C_N<0>

HDMI_EG_CLK_C_P HDMI_EG_CLK_C_N

DP_INT_EG_AUX_P DP_INT_EG_AUX_N

DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0> DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1> DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2> DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3>

DP_TBTSNK0_EG_AUXCH_P DP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK0_ML_C_P<0> DP_TBTSNK0_ML_C_N<0> DP_TBTSNK0_ML_C_P<1> DP_TBTSNK0_ML_C_N<1> DP_TBTSNK0_ML_C_P<2> DP_TBTSNK0_ML_C_N<2> DP_TBTSNK0_ML_C_P<3> DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK1_EG_AUXCH_P DP_TBTSNK1_EG_AUXCH_N

DP_TBTSNK1_ML_C_P<0> DP_TBTSNK1_ML_C_N<0> DP_TBTSNK1_ML_C_P<1> DP_TBTSNK1_ML_C_N<1> DP_TBTSNK1_ML_C_P<2> DP_TBTSNK1_ML_C_N<2> DP_TBTSNK1_ML_C_P<3> DP_TBTSNK1_ML_C_N<3>

1

R8626

4.7K

1% 1/20W MF 201

2

71 77 78 79

PP1V8_GPU_IFPA_IOVDD

=PP3V3_GPU_VDD33

8

95 38 7

OUT

95 7

OUT

38 7

OUT

38 95

7

OUT

38 95

7

38 95

OUT

7

38 95

OUT

7

38 95

OUT

7

38 95

OUT

77 82 95

BI

77 82 95

BI

82 95

OUT

82 95

OUT

82 95

OUT

82 95

OUT

82 95

OUT

82 95

OUT

82 95

OUT

82 95

OUT

77 83 95

BI

77 83 95

BI

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

77 83 95

BI

77 83 95

BI

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

7

35 95

OUT

=PP3V3_GPU_VDD33

8

71 77 78 79

=PP3V3_GPU_MISC

8

77

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

R8601

10K

1% 1/20W MF 201

2

5

S G

4

DDC 3.3V/5V LEVEL TRANSLATOR

2

S G

1

PP3V3_GPU_IFPB_IOVDD

SSM6N37FEAPE

SOT563

Q8600

D

HDMI_EG_DDC_CLK

3

SSM6N37FEAPE

SOT563

Q8600

HDMI_EG_DDC_DATA

D

6

PLACE_NEAR=U8000.J1:5MM

GPU 3V3 VDD

1

C8640

10UF

20% 10V

2

X6S-CERM 0603

1

C8645

4.7UF

20%

6.3V

2

X6S 0402

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

R8602

10K

1% 1/20W MF 201

2

IFPC_RSET

PLACE_NEAR=U8000.AF8:5MM

1

R8621

1K

1% 1/20W MF 201

2

OUT

R8609

40.2K

1 2

0.1%

1/20W

MF

0201

78 95

IN

78 95

OUT

GPU_OSC_27M_XTAL_BUFFOUT_R

77

77 95

78

1

C8641

1UF

10% 25V

2

X6S-CERM

1

C8646

4.7UF

20%

6.3V

2

X6S 0402

PP1V05_GPU_IFPAB_PLLVDD

77

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

1

R8603

10K

1% 1/20W MF 201

2

IFPD_RSET

PLACE_NEAR=U8000.AN2:5MM

1

2

7

38

Note: PP3v3_GPU_MISC and pp3v3_GPU_VDD33 have to be isolated from each other

=PP3V3_GPU_MISC

8

77

=PP3V3_GPU_VDD33

8

71 77 78

79

7

38

BI

GPU_ROM_CS_L

78

OUT

GPU_ROM_SCLK

78

OUT

GPU_ROM_SI

78

IN

GPU_ROM_SO

78

OUT

MULTI_STRAP_REF

GPU_TESTMODE

77

PP1V05_GPU_SP_PLLVDD

77 79

PP1V05_GPU_PLLVDD

77

PP1V05_GPU_VID_PLLVDD

77

GPU_OSC_27M_XTALIN GPU_OSC_27M_XTALOUT

GPU_OSC_27M_SSIN

IN

GPU_MLS_STRAP0

IN

GPU_MLS_STRAP1

IN

GPU_MLS_STRAP2

IN

GPU_MLS_STRAP3

IN

GPU_MLS_STRAP4

IN

=PP1V05_GPU_PEX_PLLVDD

8

79

1

C8642

1UF

10% 25V

2

X6S-CERM 04020402

1

C8649

0.1UF

20% 16V

2

X6S-CERM 0201

1

C8643

0.1UF

20% 16V

2

X6S-CERM 0201 0201

1

C8650

0.1UF

20% 16V

2

X6S-CERM 0201

R8606

1K

1% 1/20W MF 201

GPU_TESTMODE

1

R8608

10K

1% 1/20W MF 201

2

PD FOR RSET

77 77 77

J8 K8 L8

VDD33

M8

H6

ROM_CS*

H4

ROM_SCLK

H5

ROM_SI

H7

ROM_SO

J1

MULTI_STRAP_REF0_GND

AK11

TESTMODE

AE8

SP_PLLVDD

AD8

PLLVDD

AD7

VID_PLLVDD

H3

XTAL_IN

H2

XTAL_OUT

J4

XTAL_OUTBUFF

H1

XTAL_SSIN

J2

STRAP0

J7

STRAP1

J6

STRAP2

J5

STRAP3

J3

STRAP4

1

C8644

0.1UF

20% 16V

2

X6S-CERM

IFPEF_RSET

PLACE_NEAR=U8000.AD6:5MM

1

R8607

1K

1% 1/20W MF 201

2

OMIT_TABLE

U8000

NV-GK107

BGA

(6 OF 10)

L8607

FERR-220-OHM-2A

1 2

0603

CRITICAL

ESR = 0.05OHM

77

Power aliases required by this page:

- =PP3V3_GPU_IFPB_IOVDD

- =PP1V8_GPU_IFPA_IOVDD

- =PP1V8_GPU_DPLL

- =PP1V05_GPU_DPLL

- =PP3V3_GPU_IFPX_PLLVDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

- J31:YES

- D2:YES

PP1V05_GPU_SP_PLLVDD

77 79

MAKE_BASE=TRUE

Page Notes

- =PP1V05_GPU_IFPCD_IOVDD

- =PP1V05_GPU_IFPEF_IOVDD

- =PP3V3_GPU_VDD33

GPU_OSC_27M_XTAL_BUFFOUT_R

PLACE_NEAR=U8000.J4:8.4MM

1

R8611

10K

1% 1/20W MF 201

2

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST*

THERMDP THERMDN

P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 N4 P2 R8 M6 R1 P3 P4 P1

AM10 AM11 AP12 AP11 AN11

K3 K4

GPU_GPIO_0 GPU_GPIO_1 GPU_GPIO_2 GPU_GPIO_3 GPU_GPIO_4 GPU_GPIO_5 GPU_GPIO_6 GPU_GPIO_7 GPU_GPIO_8 GPU_GPIO_9 GPU_GPIO_10 GPU_GPIO_11 GPU_GPIO_12 GPU_GPIO_13 GPU_GPIO_14 GPU_GPIO_15 GPU_GPIO_16 GPU_GPIO_17 GPU_GPIO_18 GPU_GPIO_19 GPU_GPIO_20 GPU_GPIO_21

GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TMS GPU_JTAG_TRST_L

GPU_TDIODE_P GPU_TDIODE_N

GPU PLL VDD

MIN_LINE_WIDTH=0.41 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

1

C8651

20UF

20% 2V

2

X6T-CERM 0402

SYNC_MASTER=D2_SEAN

PAGE TITLE

1

C8652

1UF

2

20% 4V CERM-X6S 0201

1

2

KEPLER EDP/DP/GPIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

12

PP1V05_GPU_VID_PLLVDD

GPU_OSC_27M_SSIN

77

PLACE_NEAR=U8000.H1:8.4MM

1

R8612

10K

1% 1/20W MF 201

2

78

IN

78

IN

78

OUT

78

IN

78

IN

47 96

IN

47 96

OUT

PP1V05_GPU_PLLVDD

C8653

0.1UF

20% 16V X6S-CERM X6S-CERM 0201

1

C8654

0.1UF

20% 16V

2

0201

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

86 OF 132

SHEET

77 OF 99

124578

D

77

77 95

78

BI

78

BI

78

BI

C

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

78

BI

B

77

A

SIZE

D

C

B

A

GPU_GPIO_0

77

GPU_GPIO_1

77

GPU_GPIO_2

77

GPU_GPIO_3

77

GPU_GPIO_4

77

GPU_GPIO_5

77

GPU_GPIO_6

77

GPU_GPIO_7

77

GPU_GPIO_8

77

GPU_GPIO_9

77

GPU_GPIO_10

77

GPU_GPIO_11

77

GPU_GPIO_12

77

GPU_GPIO_13

77

=PP3V3_GPU_VDD33

8

71 77

78 79

=PP3V3_GPU_VDD33

8

71 77

78 79

=PP3V3_GPU_VDD33

8

71 77

78 79

=PP3V3_GPU_VDD33

8

71 77

78 79

8 7 6 5 4 3

GPU internal Temp isolation

Native Func

GP

CONFIG STRAPS - MLPS

=PP3V3_GPU_VDD33

71 77 78 79

1

R8700

45.3K

1%

1/20W

MF 201

2

GPU_MLS_STRAP0

1

R8701

5.62K

1% 1/20W MF 201

2

NOSTUFF

1

R8702

3.24K

1% 1/20W MF 201

2

GPU_MLS_STRAP1

1

R8703

45.3K

1%

1/20W

MF 201

2

NOSTUFF

1

R8704

15K

1% 1/20W MF 201

2

GPU_MLS_STRAP2

1

R8705

30K

1% 1/20W MF 201

2

1

R8706

20K

1% 1/20W MF 201

2

GPU_MLS_STRAP3

1

R8707

5.62K

1% 1/20W MF 201

2

77

OUT

=PP3V3_GPU_VDD33

71 77 78 79

77

OUT

=PP3V3_GPU_VDD33

71 77 78 79

77

OUT

=PP3V3_GPU_VDD33

71 77 78 79

77

OUT

GPIOs

GFXIMVP_VID<4>

MAKE_BASE=TRUE

GFXIMVP_VID<3>

MAKE_BASE=TRUE

GFXIMVP_PSI_R_L

MAKE_BASE=TRUE

EG_LCD_PWR_EN

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

GFXIMVP_VID<1>

MAKE_BASE=TRUE

GFXIMVP_VID<2>

MAKE_BASE=TRUE

FB_CLAMP_TOGGLE_REQ_L

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

GPU_ALT_VREF

MAKE_BASE=TRUE

GFXIMVP_VID<0>

MAKE_BASE=TRUE

HDMI_EG_HPD

MAKE_BASE=TRUE

GFXIMVP_VID<5>

MAKE_BASE=TRUE

80

78 82

80

78 82

78

73

80

82

80

GPU_GPIO_14

77

GPU_GPIO_15

77

GPU_GPIO_16

77

GPU_GPIO_17

77

GPU_GPIO_18

77

GPU_GPIO_19

77

GPU_GPIO_20

77

GPU_GPIO_21

77

PEX_CLKREQ_L_R EG_CLKREQ_IN_L

71

PART NUMBER

118S0013

8

NOSTUFF

1

R8708

3.24K

1% 1/20W MF 201

2

77

OUT

118S0414

118S0230

R8795

QTY

1

Native Func

GP

GPIOs

0

1 2

DESCRIPTION

RES, 10KOHM, 0201

RES,5.1KOHM, 0201

RES,MF,24.9KOHM,1,1/20W,0201

5%

1/20W

DP_EXTA_CA_DET_EG

MAKE_BASE=TRUE

DP_EXTB_CA_DET_EG

MAKE_BASE=TRUE

FBVDD_ALTVO

MAKE_BASE=TRUE

DP_INT_EG_HPD

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_EG

MAKE_BASE=TRUE

DP_TBTSNK1_HPD_EG

MAKE_BASE=TRUE

NC_GPU_GPIO_20_RSVD

MAKE_BASE=TRUE

NC_GPU_GPIO_21_RSVD

MAKE_BASE=TRUE

MF

201

REFERENCE DES

NO_TEST=TRUE

R8711

82

74 78

82

9

82

OUT

Straps for GK107. GF108 support has been removed.

77

CRITICAL

GPU_MLS_STRAP4

1

R8709

45.3K

1%

1/20W

MF 201

2

GPU_ROM_SI

77 78

8

NOSTUFF

1

R8710

3.24K

1% 1/20W MF 201

2

GPU_ROM_SI

1

R8711

25.5K

1% 1/20W MF 201

2

OMIT_TABLE

8

1

R8712

10K

1% 1/20W MF 201

2

GPU_ROM_SO

NOSTUFF

1

R8713

10K

1% 1/20W MF 201

2

77 78

OUT

77 78

OUT

GPU_ROM:YES

GPU_ROM_SO

77 78

GPU_ROM:YES

STRAP NOTES:

CURRENTLY STUFFED FOR GF108a/GK107-GTX STUFF R8704 FOR THICK DIE STUFF R8705 FOR THIN DIE

71 77 78 79

R8723

33

1 2

5%

1/20W

MF

201

R8726

33

1 2

5%

1/20W

MF

201

=PP3V3_GPU_VDD33

8

R8752

10K

1/20W

=PP3V3_GPU_VDD33

8

71 77 78 79

GPU_ROM_SI_R

GPU_ROM_SO_R

8

71 77 78 79

8

41 42

1

VOLTAGE=3.3V MIN_LINE_WIDTH=0.2 MM

5%

MIN_NECK_WIDTH=0.1 MM

MF

201

2

GPU overtemp masking

=PP3V3_GPU_VDD33 =PP3V3_S5_SMC

PP3V3_GPU_OVERTEMP

SMC_GFX_OVERTEMP_Q

Q8701

SSM3K15FV

8

1

R8714

24.9K

1% 1/20W MF 201

2

GPU_ROM_SCLK

NOSTUFF

1

R8715

34.8K

1% 1/20W MF 201

2

77 78

OUT

SMC_GFX_OVERTEMP_R_L

78

IN

SOD-VESM-HF

GPU_RESET_L

1

G S

3

D

2

OMIT_TABLE

5

SI

MX25L1005CMI-12G

2

SO

THRM

PAD

R8756

0

5%

1/20W

MF

201

2

1

NC

GPU GC6 ROM

GPU_ROM:YES

8

VCC

U8701

1MBIT

USON

SCLK

CRITICAL

9

1

2

08

5

GND

4

NOSTUFF

1

R8757

0

5% 1/20W MF 201

2

U8702

74LVC1G08

6

SOT891

4

SMC_GFX_OVERTEMP

3

NC

CS* WP*

HOLD*

R8720

1/20W

6

1

3

7

10K

5%

MF

201

1

2

GPU_ROM:YES

GPU_ROM_SCLK_R

GPU_ROM_CS_L_R

GPU_ROM_WP_L

78 41

OUT

42

R8721

1/20W

1

0

5%

MF

201

2

71 77 78 79

GPU_SMB_DAT

BI

71 77 78 79

GPU_SMB_CLK

OUT

BOM OPTION

FB_2G_SAMSUNG

FB_2G_HYNIX_M_DIE

FB_2G_HYNIX_A_DIE

GPU_ROM:YES

1

C8721

0.1UF

10%

6.3V

2

X6S 0201

R8724

33

1 2

1/20W

201

5%

1 2

NO STUFF

1

R8722

0

5% 1/20W MF 201

2

=PP3V3_GPU_VDD33

8

10K

R8755

1 2

1/20WMF201

5%

=PP3V3_GPU_VDD33

8

10K

R8754

1 2

5%

1/20W

Die Rev

GPU_ROM_SCLK GPU_ROM:YES

MF

R8725

GPU_ROM_CS_L

33

5%

GPU_ROM:YES

1/20W

MF

201

=PP3V3_GPU_VDD33

8

71 77 78 79

78

R8792

10K

1/20W

2

SOT563

S G

1

R8780

0

1 2

5%

1/20WMF201

NOSTUFF

5

S G

4

R8781

1 2

SOT563

0

5%

NOSTUFF

1/20W

MF

201

Strap

77 78

77

R8793

1/20W

10K

0x1 0x0 0x4

1

5%

MF

201

2

D-DIE M-DIE A-DIE

SMC_GFX_OVERTEMP_R_L

SMC_GFX_THROTTLE_R_L

1

5%

MF

201

2

Q8702

SSM6N37FEAPE

D

6

Q8702

SSM6N37FEAPE

D

3

201

MF

R8796

R8794

1/20W

NOSTUFF

6 3

GPU_SMB_DAT_R

GPU_SMB_CLK_R

1

10K

5%

1/20W

MF

201

2

1

10K

5%

MF

201

2

R8797

NO STUFF

R8790

10K

1/20W

201

1/20W

5%

MF

10K

12

TP_GPU_JTAG_TCK

MAKE_BASE=TRUE

TP_GPU_JTAG_TDI

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

44

BI

Note: PU to non GPU_S0 3v3 source

=PP3V3_S0_DPMUX_UC

8

35 82

FB_CLAMP_TOGGLE_REQ_L

78 82

44

IN

Unused signals

NOSTUFF

GC6 SUPPORT

R8753

10K

12

5%

1/20W

MF

201

GPU_JTAG_TCK

GPU_JTAG_TDI

GPU_JTAG_TDO

GPU_JTAG_TMS

77

GPU_JTAG_TRST_L

77

R8751

10K

1/20W

77

NOSTUFF

1

5% MF

201

2

R8758

10K

1/20W

1

5% MF

201

D

2

C

GPU XTAL 27 MHZ

GPU_OSC_27M_XTALIN

CRITICAL

Y8700

2.50X2.00MM-SM

27MHZ-30PPM-18PF-60OHM

1 3

1

2

1

5%

MF

201

2

R8798 R8799

0

NO STUFF

1 2

2 4

C8700

18PF

NC

5% 5% 25V NP0-C0G-CERM 0201

NC

1/20W

5%

1/20W

5%

GPU_OSC_27M_XTALOUT

1

C8701

18PF

25V

2

NP0-C0G-CERM 0201

SMC_GFX_OVERTEMP

MF

201

SMC_GFX_THROTTLE_L

MF

201

EG_LCD_PWR_EN

EG_BKLT_EN

FBVDD_ALTVO

1

2

NOSTUFF

R8791

1/20W

10K

1

5%

MF

201

2

SYNC_MASTER=D2_SEAN

PAGE TITLE

KEPLER GPIOS,CLK & STRAPS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

77 95

OUT

77 95

IN

B

41 42 78

OUT

41

BI

78 82

OUT

78 82

OUT

74 78

OUT

SIZE

A

D

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

87 OF 132

SHEET

78 OF 99

124578

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

OMIT_TABLE

U8000

NV-GK107

BGA

NC NC NC NC NC NC NC NC NC NC NC NC NC NC

GND_OPT GND_OPT

VDD_SENSE

GND_SENSE

BUFRST*

PLACE_NEAR=C8803.1:2MM

1

C8803

20UF

20% 2V

2

X6T-CERM 0402

(2 OF 10)

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_PLLVDD

PEX_PLL_HVDD

XW8804

SM

1 2

1

2

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AG26

AH12

PLACE XW8800 & XW8804 CLOSE TO C8803

P1V05_GPU_PEX_IOVDD_SNS_P

C8804

20UF

20% 2V X6T-CERM 0402

P8

NC

AC6

NC

AJ28

NC

AJ4

NC

AJ5

D

=PPVCORE_GPU

72

8

1

R8810

100

5% 1/20W MF 201

2

C

97 80

B

GPUVCORE_SENSE_P

OUT

GPUVCORE_SENSE_N

OUT

=PP1V05_GPU_PEX_IOVDD

79 73

8

1

R8811

100

5% 1/20W MF 201

2

NC NC NC NC NC NC NC NC NC NC

GPU_BUFRSTN

1

R8800

10K

1% 1/20W MF 201

2

AL11

C15 D19 D20 D23 D26 H31

V32

C16 W32

T8

L4

L5

L2

1

2

C8805

4.7UF

20%

6.3V X6S 0402

=PP1V05_GPU_PEX_IOVDD

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_GPU_PEX_PLLVDD

1

C8826

4.7UF

20%

6.3V

2

X6S 0402

GND_GPU_PEX_PLLVDD

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_GPU_PEX_PLL_HVDD

71

1

C8822

4.7UF

20%

6.3V

2

X6S 0402

GND_GPU_PEX_PLL_HVDD

OUT

79 73

8

79 73

8

1

C8823

4.7UF

20%

6.3V

2

X6S 0402

97 74

=PP1V05_GPU_PEX_PLLVDD

8 77 79

1

C8827

4.7UF

20%

6.3V

2

X6S 0402

1

2

1

C8824

1UF

20% 4V

2

CERM-X6S 0201

C8828

1UF

20% 4V CERM-X6S 0201

1

C8829

0.1UF

10%

6.3V

2

X6S 0201

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

1

2

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

FERR-220-OHM-2A

1 2

ESR = 0.05OHM

R8803

1 2

1/10W MF-LF

C8825

0.1UF

10%

6.3V X6S 0201

L8804

0603

CRITICAL

0

5%

603

XW8802

SM

1 2

R8802

0

1 2

5% 1/16W MF-LF

402

XW8803

SM

1 2

1

C8830

20UF

20% 2V

2

XW8801

SM

1 2

X6T-CERM 0402

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

=PP1V05_GPU_PEX_PLLVDD

=PP3V3_GPU_VDD33

1

C8800

20UF

20% 2V

2

X6T-CERM 0402

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

1

C8831

4.7UF

20%

6.3V

2

X6S 0402

79 77

8

EDP = 2000 MA

1

C8801

20UF

20% 2V

2

X6T-CERM 0402

GPU SP PLLVDD

1

C8832

1UF

20% 4V

2

CERM-X6S 0201

GND_GPU_SP_PLLVDD

78 77 71

1

C8802

4.7UF

20%

6.3V

2

X6S 0402

1

2

C8833

1UF

20% 4V CERM-X6S 0201

1

C8834

0.1UF

20% 16V

2

X6S-CERM 0201

1

C8835

0.1UF

20% 16V

2

X6S-CERM 0201

PP1V05_GPU_SP_PLLVDD

1

C8836

0.1UF

20% 16V

2

X6S-CERM 0201

1

2

C8837

0.1UF

20% 16V X6S-CERM 0201

AG11

A2

A33 AA13 AA15 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19

AB2 AB21 AB23 AB28 AB30 AB32

AB5

AB7 AC13 AC15 AC17 AC18 AC20 AC22

AE2 AE28 AE30 AE32 AE33

AE5

AE7 AH10 AH13 AH16 AH19

AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33

AH5

AH7

AJ7 AK10

77

OMIT_TABLE

U8000

NV-GK107

BGA

(8 OF 10)

GND

AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22 AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28

- =PP3V3_GPU_VDD33

- =PP1V05_GPU_PEX_IOVDD

- =PP1V05_GPU_PEX_PLLVDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

NV-GK107

C7

D2 D31 D33 E10 E22 E25

E5

E7 F28

F7 G10 G13 G16 G19

G2 G22 G25 G28

G3 G30 G32 G33

G5

G7

K2 K28 K30 K32 K33

K5

K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19

N2 N21 N23 N28 N30 N32 N33

N5

OMIT_TABLE

U8000

BGA

(9 OF 10)

GND

N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11

D

C

B

XW8800

SM

1 2

PLACE_NEAR=C8803.2:2MM

1

C8815

10UF

20% 4V

2

X6S-CERM 0402-1

A

1

C8809

10UF

20% 4V

2

X6S-CERM 0402-1

P1V05_GPU_PEX_IOVDD_SNS_N

1

C8816

2

1

C8810

2

1UF

20% 4V CERM-X6S 0201

1UF

20% 4V CERM-X6S 0201

1

2

1

2

C8817

0.1UF

10%

6.3V X6S 0201

C8811

0.1UF

10%

6.3V X6S 0201

1

C8818

2

1

C8819

2

100PF

5% 25V NP0-CERM 0201

100PF

5% 25V NP0-CERM 0201

97 74

OUT

PEX IOVDD & PEX IOVDDQ

1

C8812

2

1

C8806

2

10UF

20% 4V X6S-CERM 0402-1

10UF

20% 4V X6S-CERM 0402-1

1

C8813

2

1

C8807

2

1UF

20% 4V CERM-X6S 0201

1UF

20% 4V CERM-X6S 0201

1

C8814

2

1

C8808

2

0.1UF

10%

6.3V X6S 0201

0.1UF

10%

6.3V X6S 0201

1

C8821

100PF

5% 25V

2

NP0-CERM 0201

1

C8820

100PF

5% 25V

2

NP0-CERM 0201

6 3

SYNC_MASTER=D2_SEAN

PAGE TITLE

KEPLER PEX PWR/GNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

88 OF 132

SHEET

79 OF 99

124578

SIZE

A

D

C

B

8 7 6 5 4 3

(GND_GFXIMVP_AGND)

R8940

1 2

R8918

30.1K

1 2

1

C8916

560PF

10% 50V

2

X7R-CERM

0201

GFXIMVP_COMP_R

1

2

1

2

1

R8913

8.06K

1%

1/20W

MF

201

2

SIGNAL_MODEL=EMPTY

1

R8915

301

1%

1/20W

MF

201

2

NOSTUFF

R8917

49.9

1% 1/20W MF 201

GFXIMVP_FB_GND_R

NOSTUFF

C8941

5600PF

10% 10V CERM 201

147K

1%

1/20W

MF

201

1%

1/20W

MF

201

1

C8917

330PF

10% 16V

2

X7R-CERM 0201

NP0-C0G-CERM

1

R8916

49.9

1% 1/20W MF 201

2

GFXIMVP_FB_SNS_R

SIGNAL_MODEL=EMPTY

1

C8940

3300PF

10% 10V

2

X7R 201

NOSTUFF

C8918

22PF

0201

12

=PPVIN_S0_GFXIMVP

8

80

C8928

0.001UF

7

G

2

128

D

G

356

1

G

4

C8911

0.1UF

10%

6.3V X6S 0201

8

Q8930

D

IRF6802SDTRPBF

DIRECTFET-SA

S

3

S

L8930

0.2UH-20%-24A-0.003OHM

1 2

NCNC

PIMB063T-SM

7

CRITICAL

Q8931

649135PBF

DIRECTFET_S3C

376S1011

=PPVIN_S0_GFXIMVP

5

6

Q8930

D

IRF6802SDTRPBF

G

DIRECTFET-SA

S

4

0.2UH-20%-24A-0.003OHM

NCNC

128

D

S

356

1 2

7

CRITICAL

Q8961

649135PBF

DIRECTFET_S3C

376S1011

CRITICAL

L8960

PIMB063T-SM

80

1

10%

2

X6S

GFXIMVP_ISUMP_C

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM DIDT=TRUE

GFXIMVP_BOOT2_R

C8930

0.22UF

10% 16V

CERM

1

R8960

0

5% 1/10W MF-LF 603

2

R8910

1.24K

1 2

402

PLACE_NEAR=Q8931.3:1mm

C8965

0.22UF

1%

1/20W

MF

201

1

R8930

0

5% 1/10W MF-LF 603

2

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM DIDT=TRUE

GFXIMVP_BOOT1_R

1

2

XW8930

SM

12

1

10% 16V

2

CERM

402

PLACE_NEAR=Q8961.3:1mm

XW8931

SM

1

C8910

5600PF

10% 10V

2

CERM 201

NOSTUFF

R8911

1.15K

1 2

1%

1/20W

MF

201

4

12

GFXIMVP_ISUMN

1

2

=PP5V_S0_GFXIMVP

8

R8901

1 2

5%

1/20W

MF

201

GFXIMVP_RBIAS GFXIMVP_NTC GPUVCORE_PGOOD

88

OUT

GFXIMVP_VR_TT_L

80

1

R8914

5.11K

1% 1/20W MF 201

2

1

5%

50V

2

1

C8919

1000PF

10% 16V

2

X7R-CERM 0201

GFXIMVP_VID<0>

78 80

IN

GFXIMVP_VID<1>

78 80

IN

GFXIMVP_VID<2>

78 80

IN

GFXIMVP_VID<3>

78 80

IN

GFXIMVP_VID<4>

78 80

IN

GFXIMVP_VID<5>

78 80

IN

GFXIMVP_VID<6>

80

GFXIMVP_PSI_L

80

GFXIMVP_DPSLP_EN

80

=GPUVCORE_EN

88

IN

GFXIMVP_VW GFXIMVP_COMP GFXIMVP_FB2

GFXIMVP_FB

79 97

IN

79 97

IN

GPUVCORE_SENSE_P GPUVCORE_SENSE_N

SIGNAL_MODEL=EMPTY

C8915

1000PF

10% 16V

X7R-CERM

0201

1

2

CKPLUS_WAIVE=PdifPr_badTerm

GFXIMVP6_IMON

45

OUT

SIGNAL_MODEL=EMPTY

1

C8914

1000PF

10% 16V

2

X7R-CERM 0201

PLACE_NEAR=Q8900.25:1mm

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

1

PP5V_S0_GFXIMVP_VDD

PLACE_NEAR=Q8900.16:1mm

1

R8912

10K

1%

1/20W

MF

201

2

C8902

1UF

10% 25V

X6S-CERM

0402

1UF

X6S-CERM

0402

10% 25V

3

5

1

4

40

31 32 33 34 35 36 37

2

39

38

6

7

9 8

12

13

18

1

2

RBIAS

NTC

PGOOD

VR_TT*

CLK_EN*

VID0 VID1 VID2 VID3 VID4 VID5 VID6

PSI*

DPRSLPVR

VR_ON

VW

COMP

FB2

FB

VSEN

RTN

IMON

C8901

SIGNAL_MODEL=EMPTY

1

C8913

0.1UF

10%

6.3V

2

X6S 0201

GND_GFXIMVP_AGND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

1

2

U8900

ISL62882C

25

16

VCCP

TQFN

353S3679

THRM

PAD

41

1

R8900

10

5% 1/20W MF 201

MIN_LINE_WIDTH=0.6MM

2

MIN_NECK_WIDTH=0.2MM VOLTAGE=12.8V

PPVIN_S0_GFXIMVP_R

PLACE_NEAR=Q8900.17:1mm

1

C8900

0.22UF

10% 25V

2

X7R 0402

17

VINVDD

XW8900

Line Width & DIDT on all DIDT nets

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM DIDT=TRUE

GFXIMVP_BOOT2

30

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1

PHASE1

LGATE1A

LGATE1B

VSSP1

ISEN1

ISUM+

ISUM-

GATE_NODE=TRUE

GFXIMVP_UGATE2

29

SWITCH_NODE=TRUE

GFXIMVP_PHASE2

28

GATE_NODE=TRUE

GFXIMVP_LGATE2

26

GFXIMVP_VSSP2

27

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

GFXIMVP_ISEN2

10

GFXIMVP_BOOT1

19

GATE_NODE=TRUE

GFXIMVP_UGATE1

20

SWITCH_NODE=TRUE

GFXIMVP_PHASE1

21

GATE_NODE=TRUE

GFXIMVP_LGATE1

23

24

NC

GFXIMVP_VSSP1

22

GFXIMVP_ISEN1

11

GFXIMVP_ISUMP

15

80

GFXIMVP_ISUMN_R

14

SM

PLACE_NEAR=U8900.41:1mm

12

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

NOSTUFF

C8912

0.1UF

6.3V 0201

1

10% 50V

2

X7R-CERM

0402

PPVCORE_S0_GFX_PH2

PPVCORE_S0_GFX_PH1

C8927

0.001UF

10% 50V

X7R-CERM

0402

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

R8931

10K

1%

1/20W

MF

201

R8932

10K

1%

1/20W

MF

201

8

80

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

GFXIMVP_ISNS1_P GFXIMVP_ISNS1_N

97 80 97

R8961

1/20W

R8962

1/20W

CRITICAL

1

C8926

2

POLY-TANT

CASE-D2E-SM

1

R8933

1K

1%

1/20W

MF

201

2

C8931

0.22UF

1

1 2

X6S-CERM

2

GFXIMVP_ISNS1_N

1

R8963

10K

1%

1/20W

MF

201

2

1

10K

1% MF

201

2

GFXIMVP_ISNS2_N

68UF

R8998

0.00075

1

2

20%

6.3V 0201

1K

1% MF

201

C8966

0.22UF

1 2

6.3V

X6S-CERM

0201

1

20% 16V

2

1% 1W MF

0612

12 34

80 97 97

1

2

R8999

0.00075

1% 1W MF

0612

1 2 3 4

1

2

20%

CRITICAL

C8920

68UF

POLY-TANT

CASE-D2E-SM

GFXIMVP_ISNS2_NGFXIMVP_ISNS2_P

R8934

1.00

1% 1/20W MF 201

GFXIMVP_ISUMN GFXIMVP_ISUMP

80 97

1

R8964

1.00

1% 1/20W MF 201

2

GFXIMVP_ISUMN GFXIMVP_ISUMP

OMIT_TABLE OMIT_TABLEOMIT_TABLEOMIT_TABLE

CRITICAL

1

C8921

2

POLY-TANT

CASE-D2E-SM

68UF

80

20% 16V 16V

80 97

CRITICAL

1

C8922

68UF

POLY-TANT

CASE-D2E-SM

20% 16V

20%

2

25A max per phase

CRITICAL

1

C8961

270UF

20% 2V

2

TANT CASE-B2-SM

80

1

2

1

C8923

1UF

10% 25V

2

X6S-CERM

0402

=PPVCORE_S0_GFX_REG

CRITICAL

1

C8962

270UF

20% 2V

2

TANT CASE-B2-SM

C8924

1UF

X6S-CERM

0402

CRITICAL

1

C8963

270UF

20% 2V

2

TANT CASE-B2-SM

CRITICAL

1

10% 25V

2

C8925

15UF

TANT

1

20% 16V

2

SM

D

8

CRITICAL

1

C8964

270UF

20% 2V

2

TANT CASE-B2-SM

C

B

NOSTUFF

10K

1/20W

201

10K

1/20W

1

1% MF

2

1

1% MF

201

2

GPU VCORE VID STRAPS

DEFAULT = 0.9 V

10K

201

10K

1/20W

1% MF

201

1

2

1% MF

R8946

1

2

NOSTUFF

R8953

NOSTUFF

R8945

1/20W

R8952

10K

1/20W

1% MF

201

10K

1% MF

201

1

R8947

2

1

R8954

2

10K

1%

1/20W

MF

201

NOSTUFF

10K

1/20W

201

1

2

1% MF

R8948

1

2

10K

1%

1/20W

MF

201

NOSTUFF

R8955

10K

1/20W

1% MF

201

1

R8949

2

1

2

NOSTUFF

10K

1/20W

201

R8956

10K

1/20W

Stuff option for GPIO control

1

1% MF

2

1

1% MF

201

2

R8981 = PSI Control R8982 = VID6 control (old connection) R8982 = DPSLP Control

R8981

0

1 2

5%

1/20W

MF

201

NOSTUFF

GFXIMVP_PSI_R_L

78

IN

R8982

0

1 2

5%

1/20W

MF

201

NOSTUFF

R8983

0

1 2

5%

1/20W

MF

201

GFXIMVP_PSI_L

GFXIMVP_VID<6>

GFXIMVP_DPSLP_EN

80

=PP3V3_S0_GFX3V3BIAS

8

80

GFXIMVP_VR_TT_L

80

GFXIMVP_PSI_L

80

GFXIMVP_DPSLP_EN

80

NOSTUFF

1

R8970

499

1% 1/20W MF 201

2

1

R8971

100K

5% 1/20W MF 201

2

NOSTUFF

1

R8972

100K

5% 1/20W MF 201

2

6 3

NOSTUFF

1

R8974

100K

5% 1/20W MF 201

2

Do not config

PSI_L = HIGH & DPSLP_EN = HIGH

1

R8973

100K

5% 1/20W MF 201

2

SYNC_MASTER=D2_SEAN

PAGE TITLE

GFX IMVP VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

89 OF 132

SHEET

80 OF 99

124578

SIZE

A

D

=PP3V3_S0_GFX3V3BIAS

8

80

NOSTUFF

1

R8943

GFXIMVP_VID<0>

78 80

GFXIMVP_VID<1>

78 80

GFXIMVP_VID<2>

78 80

GFXIMVP_VID<3>

78 80

GFXIMVP_VID<4>

A

78 80

GFXIMVP_VID<5>

78 80

GFXIMVP_VID<6>

80

R8950

10K

1/20W

1% MF

201

10K

201

2

1

1% MF

2

R8944

R8951

8 7 6 5 4 3

12

D

LCD PANEL INTERFACE (eDP)

PPVOUT_S0_LCDBKLT

7

86 99

LED_RETURN_6

7

86

LED_RETURN_5

7

86

LED_RETURN_4

7

86

LED_RETURN_3

7

86

LED_RETURN_2

7

86

81

CRITICAL

L9000

FERR-220-OHM

1 2

0805

C9002

0.001UF

X7R-CERM

LED_RETURN_1

7

LCD_HPD_CONN

7

LCD_FSS

DP_INT_AUX_P

7

81 95

DP_INT_AUX_N

7

81 95

DP_INT_ML_P<0>

7

81 95

DP_INT_ML_N<0>

7

81 95

DP_INT_ML_P<1>

7

81 95

DP_INT_ML_N<1>

7

81 95

DP_INT_ML_P<2>

7

81 95

DP_INT_ML_N<2>

7

81 95

DP_INT_ML_P<3>

7

81 95

DP_INT_ML_N<3>

7

81 95

1

10% 50V

2

0402

PP5VR3V3_SW_LCD

7

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

C9000

1000PF

1 2

SM

NC_ISNS_LCD_PANELN

NC_ISNS_LCD_PANELP

0

5%

FL9000

15OHM-100MA-8.5GHZ

DLP0NS

SYM_VER-2

1 2

FL9002

15OHM-100MA-8.5GHZ

DLP0NS

SYM_VER-2

1 2

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

1/20W

CRITICAL

MF

201

15OHM-100MA-8.5GHZ

DLP0NS

SYM_VER-2

1 2

34

CRITICAL

FL9001

15OHM-100MA-8.5GHZ

DLP0NS

SYM_VER-2

1 2

34

CRITICAL

FL9003

C9001

0.1UF

7

98

OUT

X7R-CERM

7

OUT

0402

98

34

1

10% 16V

2

LCD_HPD

82

OUT

7

82

OUT

DP_INT_AUX_C_P

82 95

BI

DP_INT_AUX_C_N

82 95

BI

DP_INT_ML_C_P<0>

82 95

C

82

=PP5V_S0_LCD

8

B

LCD_PWR_EN

IN

1

R9010

10K

5% 1/16W MF-LF

402

2

CRITICAL

U9000

FPF1009

MFET-2X2-8IN

ON

C9009

0.1UF

X7R-CERM

2

VIN_1

3

VIN_2

1

10% 16V

2

0402

GND

617

VOUT_1

VOUT_2

THRM

PAD

4

5

IN

DP_INT_ML_C_N<0>

82 95

IN

DP_INT_ML_C_P<1>

82 95

IN

DP_INT_ML_C_N<1>

82 95

IN

DP_INT_ML_C_P<2>

82 95

IN

DP_INT_ML_C_N<2>

82 95

IN

DP_INT_ML_C_P<3> DP_INT_ML_F_P<3>

82 95

IN

DP_INT_ML_C_N<3>

82 95

IN

1

C9011

0.1UF

10% 16V

2

X7R-CERM 0402

C9028

C9029

C9020

C9021

C9022

C9023

C9024

C9025

C9026

C9027

PP5VR3V3_SW_LCD_ISNS

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

1

C9012

10UF

20%

6.3V

2

X5R 603

0.1UF

1 2

10% X5R-CERM

X5R-CERM

10% X5R-CERM

R9000

16V 0201

DP_INT_ML_F_P<0>

95 16V 0201

DP_INT_ML_F_N<0>

95 16V 0201

DP_INT_ML_F_P<1>

95 16V 0201

DP_INT_ML_F_N<1>

95 16V10% 0201

DP_INT_ML_F_P<2>

95 16V 0201

DP_INT_ML_F_N<2>

95 16V 0201

DP_INT_ML_F_N<3>

95 16V 0201

XW9020

1 2

100V

603-1

NC

1

10%

2

X7R

CRITICAL

J9000

20525-130E-01

F-RT-SM

31

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

33 34 35 36 37 38 39 40 41

32

518S0829

D

C

B

SIGNAL_MODEL=EMPTY

7

81 95

=PP3V3_S0_LCD

8

LCD Panel HPD & AUX strapping

DP_INT_AUX_N

7

81 95

DP_INT_AUX_PLCD_HPD_CONN

7

1

R9001

1M

5% 1/20W MF 201

2

81 95

7

81

A

1

R9003

1M

5% 1/20W MF 201

2

1

R9002

1M

5% 1/20W MF 201

2

SIGNAL_MODEL=EMPTY

7

81 95

SIGNAL_MODEL=EMPTY

7

81 95

SIGNAL_MODEL=EMPTY

7

81 95

SIGNAL_MODEL=EMPTY

7

81 95

SIGNAL_MODEL=EMPTY

7

81 95

SIGNAL_MODEL=EMPTY

7

81 95

SIGNAL_MODEL=EMPTY

7

81 95

BP9000

BEAD-PROBE

DP_INT_ML_P<0>

BP9001

BEAD-PROBE

DP_INT_ML_N<0>

BP9002

BEAD-PROBE

DP_INT_ML_P<1>

BP9003

BEAD-PROBE

DP_INT_ML_N<1>

BP9004

BEAD-PROBE

DP_INT_ML_P<2>

BP9005

BEAD-PROBE

DP_INT_ML_N<2>

BP9006

BEAD-PROBE

DP_INT_ML_P<3>

BP9007

BEAD-PROBE

DP_INT_ML_N<3>

6 3

SM

R9011

1 SM

1

SM

1

SM

1

SM

1

SM

1

SM

1

SM

1

1M

1 2

5%

1/20W

MF

201

R9013

1M

1 2

1/20W

201

R9015

1 2

1/20W

R9017

1M

1 2

1/20W

201

R9012

1M

1 2

5%

1/20W

MF

201

5% MF

R9014

1M

1 2

5%

1/20W

MF

1M

201

5% MF

201

5% MF

R9016

1M

1 2

5%

1/20W

MF

201

R9018

1M

1 2

5%

1/20W

MF

201

SYNC_MASTER=D2_KEPLER PAGE TITLE

eDP Display Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

90 OF 132

SHEET

81 OF 99

SIZE

A

D

124578

8 7 6 5 4 3

=PP3V3_S0_DPMUX

8

83

Q9190

DPMUX_UC_MD2

SSM3K15FV

TP_DPMUX_UC_P10 TP_DPMUX_UC_P11 TP_DPMUX_UC_P12 TP_DPMUX_UC_P13

D

82 88

OUT

82 88

OUT

82 88

OUT

82 88

OUT

82 88

OUT

9

82

OUT

9

82

OUT

73

OUT

7

17 41 43 92

BI

7

17 41 43 92

BI

7

17 41 43 92

BI

7

17 41 43 92

BI

7

17 41 43 92

IN

25 82

IN

25

IN

7

81

IN

C

9

82

OUT

9

82

IN

TP_DPMUX_UC_P14 TP_DPMUX_UC_P15 TP_DPMUX_UC_P16 TP_DPMUX_UC_P17

EG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_EN EG_RAIL5_EN EG_CLKREQ_OUT_L EG_RESET_L FB_CLAMP

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L DPMUX_LRESET_L LPC_CLK33M_DPMUX_UC

TP_DPMUX_UC_P37

TP_DPMUX_UC_P40 TP_DPMUX_UC_P41 TP_DPMUX_UC_P42 LCD_FSS LCD_MUX_SEL

82

TP_DPMUX_UC_P45 TP_DPMUX_UC_P46 TP_DPMUX_UC_P47

DPMUX_UC_TX DPMUX_UC_RX TP_DPMUX_UC_P52

B12

P10/WUE0*

A13

P11/WUE1*

A12

P12/WUE2*

B13

P13/WUE3*

D11

P14/WUE4*

C13

P15/WUE5*

C12

P16/WUE6*

D10

P17/WUE7*

D13

P20

E11

P21

D12

P22

F11

P23

E13

P24

E12

P25

F13

P26

E10

P27

A9

P30/LAD0

D9

P31/LAD1

C8

P32/LAD2

B7

P33/LAD3

A8

P34/LFRAM*

D8

P35/LRESET*

D7

P36/LCLK

D6

P37/SERIRQ

D4

P40/TMI0/TCMCYI0

A5

P41/TMO0/TCMCKI0/TCMMCI0

B4

P42/TCMCYI1

A1

P43/TMI1/TCMCKI1/TCMMCI1

C2

P44/TMO1/PWMU2B/TCMCYI2

B2

P45/PWMU3B/TCMCKI2/TCMMCI2

C1

P46/PWMU4B

C3

P47/PWMU5B

G2

P50/FTXD

F3

P51/FRXD

E4

P52/SCL0

CONNECT I2C TO LCD BKLT IC

N3

PA0/KIN8*/SDA1

N1

PA1/KIN9*/SCL1

M3

PA2/KIN10*/PS2AC

M2

PA3/KIN11*/PS2AD

N2

PA4/KIN12*/PS2BC

L1

PA5/KIN13*/PS2BD

K3

PA6/KIN14*/PS2CC

L2

PA7/KIN15*/PS2CD

B8

PB0/LSMI*

C9

PB1/LSCI

B9

PB2/RI*/PWMU0B

A10

PB3/DCD*/PWMU1B

C10

PB4/DSR*/FSIDO

B10

PB5/DTR*/FSIDI

C11

PB6/CTS*/FSICK

A11

PB7/RTS*/FSISS

G11

PC0/TIOCA0/WUE8*

G13

PC1/TIOCB0/WUE9*

F12

PC2/TIOCC0/TCLKA/WUE10*

H13

PC3/TIOCD0/TCLKB/WUE11*

G10

PC4/TIOCA1/WUE12*

G12

PC5/TIOCB1/TCLKC/WUE13*

H11

PC6/TIOCA2/WUE14*

J13

PC7/TIOCB2/TCLKD/WUE15*

M10

PD0/AN8

N9

PD1/AN9

K10

PD2/AN10

L8

PD3/AN11

M9

PD4/SSO

N8

PD5/SSI

K9

PD6/SSCK

L7

PD7/SCS

PP3V3_S0_DPMUX_UC_R

82

DPMUX_UC_TX

9

82

DPMUX_UC_RX

9

82

DPMUX_UC_RESET_L

82

DPMUX_UC_MD1

82

78

82

=I2C_DPMUX_UC_SDA =I2C_DPMUX_UC_SCL DPMUX_UC_IRQ DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED FB_CLAMP_TOGGLE_REQ_L

TP_DPA_EG_HPD TP_DPB_EG_HPD DP_TBTSNK0_HPD_EG DP_TBTSNK1_HPD_EG DP_EXTA_CA_DET_EG DP_EXTB_CA_DET_EG HDMI_EG_HPD DP_INT_EG_HPD

LCD_PWR_EN LCD_BKLT_EN TP_DPMUX_UC_PC2 TP_DPMUX_UC_PC3 LCD_MUX_EN TP_LCD_MUX_REQ LCD_BKLT_PWM DP_DDC_MUX_CROSSBAR_L

TP_DPA_IG_HPD TP_DPB_IG_HPD DP_TBTSNK0_HPD_IG DP_TBTSNK1_HPD_IG TP_DP_EXTA_CA_DET_IG TP_DP_EXTB_CA_DET_IG TP_HDMI_IG_HPD DP_INT_IG_HPD

44

BI

44

OUT

20

OUT

78 82

OUT

78 82

OUT

78

OUT

78

B

PU OFFPAGE

OUT

78

OUT

78 82

OUT

81 82

OUT

82 86

OUT

82 86

OUT

83

OUT

9

OUT

9

OUT

10 82

OUT

A

U9100

R4F2113NLG

TLP-145V

SYM 1 OF 3

OMIT_TABLE

U9100

R4F2113NLG

TLP-145V

SYM 2 OF 3

OMIT_TABLE

PG0/EXIRQ8*/TMIX/SDAA PG1/EXIRQ9*/TMIY/SCLA

J9100

1909782

M-RT-SM

7

1 2 3 4 5 6

8

P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7

P80/PME* P81/GA20

P96/EXCL

PECI

L13 K12 K11 J12 K13 J10 J11 H12

N10 M11 L10 N11 N12 M13 N13 L12

A7 B6 C7 D5 A6 B5 C6

J4 G3 H2 G1 H4 G4 F4 F1

K1 J3 K2 J1 K4 H3

K5 N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 A4 B3

P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4* P65/KIN5* P66/KIN6*

P67/IRQ7*/KIN7*

P82/CLKRUN*

P83/LPCPD* P84/IRQ3*/TXD1 P85/IRQ4*/RXD1 P86/IRQ5*/SCK1

P90/IRQ2* P91/IRQ1*

P92/IRQ0* P93/IRQ12* P94/IRQ13* P95/IRQ14*

P97/SDA0/IRQ15*

PE0/EXEXCL

PE1/ETCK PE2/ETDI PE3/ETDO PE4/ETMS

PE5/ETRST*

PF0/IRQ8*/PWMU0A PF1/IRQ9*/PWMU1A

PF2/IRQ10*/TMOY

PF3/IRQ11*/TMOX PF4/PWMU2A/EXDSR PF5/PWMU3A/EXDTR PF6/PWMU4A/EXCTS PF7/PWMU5A/EXRTS

PG2/EXIRQ10*/SDAB PG3/EXIRQ11*/SCLB PG4/EXIRQ12*/SDAC PG5/EXIRQ13*/SCLC PG6/EXIRQ14*/SDAD PG7/EXIRQ15*/SCLD

PH0/IRQ6*

PH1/EXIRQ7*

PEVREF

DPMUX_DEBUG

DPMUX UC DEBUG HEADER

DP_EXTA_MUX_EN DP_EXTA_MUX_SEL_EG TP_DPMUX_UC_P62 TP_DPMUX_UC_P63 DP_EXTB_MUX_EN DP_EXTB_MUX_SEL_EG TP_DPMUX_UC_P66 TP_DPMUX_UC_P67

DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED

TP_DPMUX_UC_P80 TP_DPMUX_UC_P81 TP_DPMUX_UC_P82 TP_DPMUX_UC_P83 DPMUX_UC_BOOT_TX DPMUX_UC_BOOT_RX TP_LCD_IRQ

DP_TBTPB_HPD_BUF DP_TBTSNK0_HPD DP_TBTSNK1_HPD DP_A_CA_DET_BUF DP_B_CA_DET_BUF TP_DPMUX_UC_P96 TBT_DDC_XBAR_EN_L

DPMUX_UC_CLK32K DPMUX_UC_TCK DPMUX_UC_TDI DPMUX_UC_TDO DPMUX_UC_TMS DPMUX_UC_TRST_L

EG_LCD_PWR_EN EG_BKLT_EN PM_ALL_GPU_PGOOD EG_CLKREQ_IN_L GPU_PGOOD4 GPU_PGOOD3 GPU_PGOOD2 GPU_PGOOD1

=I2C_DPMUX_A_SDA =I2C_DPMUX_A_SCL DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_UC_UNUSED DPMUX_LRESET_L HDMI_HPD_BUF LCD_HPD

IG_LCD_PWR_EN IG_BKLT_EN DPMUX_UC_PECI DPMUX_UC_PEVREF

DPMUX_UC_XTAL_R

35 84

IN

83

OUT

83

OUT

83

OUT

83

OUT

82

=PP3V3_S3_DPMUX_UC

8

82

=PP3V3_S0_DPMUX_UC

8

35 78 82

82

9

OUT

9

IN

35

IN IN IN IN IN IN

IN

DPMUX:XTAL

82

IN IN IN IN IN IN IN IN

BI

OUT

82

IN IN IN

IN IN

82

35 78 82

82

35

25 82

82

35

C9140

15PF

5% 25V NPO

0201

78

88

9

78

88

44

25 82

82

81

9

=PP3V3_S0_DPMUX_UC

8

TBT_A_CONFIG1_BUF

DPMUX_UC_RESET_LDP_TBTPA_HPD_BUF

DPMUX_LRESET_L

DPMUX:XTAL

R9151

0

1 2

5%

1/20W

MF

201

DPMUX:XTAL

Y9100

2.50X2.00MM-SM

20MHZ-30PPM-12PF-50OHM

1 3

1

2 4

NC

2

Q9110

SSM6N37FEAPE

SOT563

D

3

DPMUX_UC_MD1

82

R9100

0

1 2

5% 1/16W MF-LF

402

1

C9100

0.1UF

20% 10V

2

X7R-CERM

0402

NOSTUFF

R9102

0

1 2

5% 1/16W MF-LF

402

DPMUX_UC_XTAL DPMUX_UC_EXTAL

DPMUX:HOCO

DPMUX:XTAL

1

C9141

15PF

5% 25V

NC

2

NPO 0201

DPMUX UC PULL-UPS

DPMUX_UC_NMI

82

DPMUX_UC_TRST_L

82

DPMUX_UC_MD1

82

DPMUX_UC_MD2

82

DPMUX_UC_CLK32K

82

DPMUX_UC_TCK

82

DPMUX_UC_TDI

82

DPMUX_UC_TDO

82

DPMUX_UC_TMS

82

EG_CLKREQ_OUT_L

9

82

DPMUX_UC_RESET_L

82

HDMI HPD INVERSION & ISOLATION

HDMI_HPD_L

7

38 42

IN

CA_DET ISOLATION

1 2

5

S G

DP_A_CA_DET_BUF

4

SOD-VESM-HF

R9101

0

1 2

5% 1/16W MF-LF

402

PP3V3_S0_DPMUX_UC_R

82

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

1

C9101

0.1UF

20%

10V

2

X7R-CERM

0402

1

R9150

10K

5%

1/20W

MF

201

2

1

NC

R9160

100K

5%

1/20W

MF

201

PP3V3_S3_DPMUX_UC_R

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

C9102

0.1UF

X7R-CERM

0402

D3

A3 A2

6

A

U9110

B

NC

3

5

OUT

3

D

1

G S

2

1

C9103

0.1UF

20% 10V

2

M12

AVCC

X7R-CERM

B1M1H10

VCC

0402

20% 10V

VCC

R4F2113NLG

SYM 3 OF 3

RES*

XTAL

OMIT_TABLE

EXTAL

VSS

D2

R9110 R9111 R9112 R9113 R9114 R9115 R9116 R9117 R9118 R9119 R9140

=PP3V3_S0_DPMUX_UC

74LVC1G00GF

SOT891

4

82

35 85

1

2

E1

VCL

VCC

U9100

TLP-145V

VSS

L3

F10C5B11

10K

100K

TBT_B_CONFIG1_BUF

IN

1 2

35 78 82

DPMUX_UC_VCL

L11

J2

VBAT

AVREF

C4

MDCKN

D1

MD1

H1

MD2

E3

NMI

E5

NC

AVSS

L9

=PP3V3_S0_DPMUX_UC

8

35 78 82

1 2

NOSTUFF

HDMI_HPD_BUF

=PP3V3_S0_DPMUX_UC

8

82

1

C9104

0.1UF

20% 10V

2

X7R-CERM 0402

C9105

0.47UF

6.3V

X6S-CERM

0402

DPMUX_UC_MD1 DPMUX_UC_MD2

DPMUX_UC_NMI

NC

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

5% MF

1/20W

5%

1/20W

5%

1/20W

5% MF

PU on PCH Page

1/20W

5%

1/20W

8

35 78 82

82

Q9110

SSM6N37FEAPE

SOT563

D

6

1

C9150

B2 B1

D2 D1

E2 E1

F2 F1

H2 H1

J1

C2

0.1UF

20% 10V

2

X7R-CERM 0402

DP_INT_ML_C_P<0> DP_INT_ML_C_N<0>

DP_INT_ML_C_P<1> DP_INT_ML_C_N<1>

DP_INT_ML_C_P<2> DP_INT_ML_C_N<2>

DP_INT_ML_C_P<3> DP_INT_ML_C_N<3>

DP_INT_AUX_C_P DP_INT_AUX_C_N

DPMUX_HPD_PD

DP 2:1 ANALOG MUX

A2

B4

DIN1_0+

A4

DIN1_0-

B5

DIN1_1+

A5

DIN1_1-

B6

DIN1_2+

A6

DIN1_2-

A8

DIN1_3+

A9

DIN1_3-

H9

DAUX1+

J9

DAUX1-

H8 J8

J2

B8 B9

D8 D9

E8 E9

F8 F9

H6 J6

H5 J5

H3

A1

B7

DDC_CLK1 DDC_DAT1

HPD_1

DIN2_0+ DIN2_0-

DIN2_1+ DIN2_1-

DIN2_2+ DIN2_2-

DIN2_3+ DIN2_3-

DAUX2+ DAUX2-

DDC_CLK2 DDC_DAT2

HPD_2

GPU_SEL

XSD*

NC NC

NC

NC NC

NC

82

DP_INT_IG_ML_P<0> DP_INT_IG_ML_N<0>

DP_INT_IG_ML_P<1> DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<2> DP_INT_IG_ML_N<2>

DP_INT_IG_ML_P<3> DP_INT_IG_ML_N<3>

DP_INT_IG_AUX_P DP_INT_IG_AUX_N

DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0>

DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3>

DP_INT_EG_AUX_P DP_INT_EG_AUX_N

LCD_MUX_SEL

LCD_MUX_EN

10 89

IN

10 89

IN

10 89

IN

10 89

IN

10 89

IN

10 89

IN

10 89

IN IN

10 89

BI

10 89

BI

77 95

IN

77 95

IN

77 95

IN

77 95

IN

77 95

IN

77 95

IN

77 95

1

10%

2

IN

77 95

IN

77 95

BI

77 95

BI

82

J4

VDD

U9150

CBTL06142EEE

TFBGA

CRITICAL

DOUT_0+ DOUT_0-

DOUT_1+ DOUT_1-

DOUT_2+ DOUT_2-

DOUT_3+ DOUT_3-

DDC_AUX_SEL

GND

B3C8G8H4H7

HPDIN

GND

G2

AUX+ AUX-

DPMUX UC PULL-DOWNS

1 2

NOSTUFF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

NOSTUFF

5%

1/20W

5%

1/20W

5%

NOSTUFF

5% MF

1/20W

NOSTUFF

5%

1/20W

NOSTUFF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

PD on LCD Page

DPMUX_UC_RESET_L

82

EG_RAIL1_EN

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF5%

MF

201

82 88

EG_RAIL2_EN

82 88

EG_RAIL3_EN

82 88

EG_RAIL4_EN

82 88

EG_RAIL5_EN

82 88

LCD_PWR_EN

81 82

LCD_BKLT_EN

82 86

LCD_BKLT_PWM

82 86

DPMUX_UC_NMI

82

DPMUX_UC_MD1

82

DPMUX_UC_MD2

82

DPMUX_UC_PECI

82

DPMUX_UC_PEVREF

82

DPMUX_UC_UNUSED

82

EG_RESET_L

9

82

DPA_IG_HPD

9

18

DP_TBTSNK0_HPD_EG

78 82

DPB_IG_HPD

9

18

DP_TBTSNK1_HPD_EG

78 82

DP_INT_IG_HPD

10 82

DP_INT_EG_HPD

78 82

R9120 R9121 R9122 R9123 R9124 R9125 R9126 R9127 R9128 R9129 R9130 R9131 R9132 R9133 R9134 R9135 R9136 R9137 R9138 R9139 R9145 R9146

10K

100K

SYNC_MASTER=D2_SEAN

PAGE TITLE

eDP Mux

R9161

100K

2

S G

1

1 2

5%

1/20W

MF

201

DP_B_CA_DET_BUF

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

82

OUT

PROPRIETARY PROPERTY OF APPLE INC.

Apple Inc.

R

6 3

MF

MF5%

MF

MF5%

MF

1

C9151

0.1UF

20% 10V

2

X7R-CERM 0402

R9162

100K

1 2

1%

1/20W

201

12

OUT OUT

BI BI

MF

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

91 OF 132

SHEET

82 OF 99

124578

81 95

81 95 10 89

81 95

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

DP A & DP B AUX MUX DP A & DP B DDC MUX

=PP3V3_S0_DPMUX

8

82

1

C9200

0.1UF

20% 10V

2

X7R-CERM 0402

13

VCC

U9200

TS3DS10224

IN

7

BI

7

BI

DP_EXTA_MUX_EN

DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N

82 83

35 95

C

IN

7

BI

7

BI

DP_EXTB_MUX_EN

DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

82 83

35 95

16

ENA

INA+ INA-

SAI

ENB

INB+ INB-

SBI

QFN

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0+ OUTB0-

SBO

PAD

GND

THRM

5

21

1 2

14

10

3 4

12 11

20

DP_TBTSNK0_EG_AUXCH_P

19

DP_TBTSNK0_EG_AUXCH_N

18

DPA_IG_AUX_CH_P

17

DPA_IG_AUX_CH_N

15

DP_EXTA_MUX_SEL_EG

6

DP_TBTSNK1_EG_AUXCH_P

7

DP_TBTSNK1_EG_AUXCH_N

8

DPB_IG_AUX_CH_P

9

DPB_IG_AUX_CH_N

DP_EXTB_MUX_SEL_EG

77 95

BI

77 95

BI

18 95

BI

18 95

BI

82 83

IN

77 95

BI

77 95

BI

18 95

BI

18 95

BI

82 83

IN

R9220

1

470K

1% MF

201

2

R9230

1

470K

1% 1/20W MF 201

2

84

85

OUT

BI

OUT

BI

R9240

1

470K

1% 1/20W MF 201

2

82 83

DP_TBTPA_DDC_CLK DP_TBTPA_DDC_DATA

82 83

DP_TBTPB_DDC_CLK DP_TBTPB_DDC_DATA

82

R9250

1

470K

1% 1/20W1/20W MF 201

2

DP_EXTA_MUX_EN

IN

DP_EXTB_MUX_EN

IN

DP_DDC_MUX_CROSSBAR_L

IN

R9210

10K

1/16W MF-LF

1

5%

402

2

14

U9210

TS3DS10224

16

ENA

1

INA+

2

INA-

SAI

10

ENB

3

INB+

4

INB-

12 11

SBI

QFN

1

C9210

0.1UF

20% 10V

2

X7R-CERM 0402

13

VCC

20

OUTA1+

19

OUTA1-

18

OUTA0+

17

OUTA0-

15

SAO

6

OUTB1+

7

OUTB1-

8

OUTB0+

9

OUTB0-

SBO

PAD

GND

THRM

5

21

R9251

1

470K

1% 1/20W MF 201

2

DPA_EG_DDC_CLK DPA_EG_DDC_DATA

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

DP_EXTA_MUX_SEL_EG

DPB_EG_DDC_CLK DPB_EG_DDC_DATA

DPB_IG_DDC_CLK DPB_IG_DDC_DATA

DP_EXTB_MUX_SEL_EG

R9252

1

470K

1% 1/20W MF 201

2

R9253

1

470K

1% 1/20W MF 201

2

77

IN

77

BI

18

IN

18

BI

82 83

IN

77

IN

77

BI

18

IN

18

BI

82 83

IN

R9254

1

470K

1% 1/20W MF 201

2

C

MUX TRUTH TABLE

SAI/SBI SAO SBO | INA INB

0 0 0 OUTB0 OUTA0

B

0 0 1 OUTB1 OUTA0 0 1 0 OUTB0 OUTA1 0 1 1 OUTB1 OUTA1

1 0 0 OUTA0 OUTB0 1 0 1 OUTA0 OUTB1 1 1 0 OUTA1 OUTB0 1 1 1 OUTA1 OUTB1

A

6 3

SYNC_MASTER=D2_SEAN

PAGE TITLE

eDP Muxed Graphics Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

92 OF 132

SHEET

83 OF 99

124578

SIZE

B

A

D

8 7 6 5 4 3

PP3V3_SW_TBTAPWR

84

12

1

C9420

3.3V/HV Power MUX

V3P3 must be S4 to support wake from Thunderbolt devices.

=PP3V3_S4_TBTAPWRSW

D

8

CRITICAL

C9487

100UF

20%

6.3V

POLY-TANT

CASE-B2-SM

=PPHV_SW_TBTAPWRSW

8

18.9V Max

C9480

X5R-CERM-1

1

C9415

4.7UF

10% 25V

2

X5R-CERM 0603

IN

1

22UF

20%

6.3V 2

603

=TBTAPWRSW_EN

TBT_A_HV_EN

=TBT_S0_EN

C9410

0.1UF

2

10% 25V X5R 402

C9481

0.1UF

10% 16V X5R-CERM 0201

1

2

1

2

70

35 37

70 85

1

C

For 12V systems:

PART NUMBER

118S0145

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT_A_D2R_P<0>

7

35 93

OUT

TBT_A_D2R_N<0>

7

35 93

OUT

DP_TBTPA_ML_C_P<3>

35 93

IN

DP_TBTPA_ML_C_N<3>

35 93

IN

7

OUT

7

OUT

TBT_A_D2R_P<1> TBT_A_D2R_N<1>

B

QTY

2

DESCRIPTION

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

GND_VOID=TRUE

(Both C’s)

C9474

C9475

C9476

C9477

0.47UF

C9478

C9479

GND_VOID=TRUE

(Both C’s)

0.47UF

84 93

1 2

0.22UF

1 2

Nominal Min Max IV3P3 1100mA 1030mA 1200mA IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CRITICAL

U9410

CD3210A0RGP

QFN

RSVD

5

11 10

17

EN

HV_EN

S0

ISET_V3P3

GND

123

4

TBTHV:P15V

R9413

22.6K

18

V3P3OUT

12

OUT

14

1516

RSVD

8

ISET_S0

9

ISET_S3

THRM

PAD

13

21

TBTHV:P15V

1

R9414

22.6K

1%

1/20W

MF

201

2

REFERENCE DES

1

C9485

0.1UF

16V

2

X5R-CERM

0201

TBTAPWRSW_ISET_V3P3

TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

12V: See below

TBTAPWRSW_ISET_S3_R TBTAPWRSW_ISET_S0_R

1% 1/20W MF 201

ILIM = 40000 / RISET

1

2

CRITICAL

R9410,R9413

R9411,R9414

TBT_A_D2R_C_P<0>

7

4V

20%

201

CERM-X5R-1

4V

20%

201

CERM-X5R-1

1 2

20% X5R

1 2

20% X5R

TBT_A_BIAS

84

GND_VOID=TRUE

4V

20%

201

CERM-X5R-1

20%

4V

201

CERM-X5R-1

DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N

6.3V 0201

R9498

2.2K

1/20W

93

TBT_A_D2R_C_N<0>

7

93

GND_VOID=TRUE

R9494

SIGNAL_MODEL=EMPTY

DP_TBTPA_ML_P<3>

93

DP_TBTPA_ML_N<3>

93

TBT: Unused

1

R9499

2.2K

5%

5% 1/20W

MF

201

2

GND_VOID=TRUE

TBT_A_D2R_C_P<1> TBT_A_D2R_C_N<1>

1

C9498

30PF

C0G-NP0

0402

1

C9499

5%

50V

30PF

5% 50V

2

C0G-NP0 0402

PP3V3_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

PPHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTHV:P15V

R9410

22.6K

1/20W

201

1% MF

1

C9411

0.1UF

10% 25V

2

X5R 402

1

2

TBTHV:P15V

1

R9411

22.6K

2

C9486

10UF

20%10%

6.3V CERM-X5R 0402

Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.

BOM OPTION

TBTHV:P12V

GND_VOID=TRUE

1

R9495

1K

5%

MF

2

5% 1/20W MF 201

2

SIGNAL_MODEL=EMPTY

R9478

1/20W

201

R9479

D9498

BAR90-02LRH

D9499

BAR90-02LRH

84

1

R9412

36.5K

2

<RV3P3>

470K

1 2

470K

1 2

CRITICAL

GND_VOID=TRUE

A K

CRITICAL

L9498

0603

SIGNAL_MODEL=EMPTY

CRITICAL

L9499

0603

SIGNAL_MODEL=EMPTY

1% 1/20W MF 201

TSLP-2-7

1% 1/20W MF 201

SIGNAL_MODEL=TBTPIN

(Both D’s)

650NH-5%-0.430MA-0.52OHM

C9400

0.01UF

X7R-CERM

GND_VOID=TRUE

12

GND_VOID=TRUE

10% 50V

0402

5% MF

93

CRITICAL

L9400

FERR-120-OHM-3A

1 2

1

2

1/20W

TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

0603

1

C9401

0.01UF

10% 50V

2

X7R-CERM 0402

201

35 93

BI

35 93

BI

35 93

IN

35 93

IN

84

PP3V3RHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

TBT Dir

DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

TBT_A_LSRX

35

OUT

Y = B

DP Dir

35

25 85

0201

83

0201

6.3V 0201

BI

83

35 82

OUT

35

OUT

1

C9460

0.1UF

10% 16V

2

X5R-CERM 0201

CRITICAL

U9460

74AUP1T97

SOT891

C9430

C9431

C9432

C9433

4

Y A

5

VCC

GND

2

0.1UF

0.22UF

1 2

10% 16V X5R-CERM

1 2

10% 16V X5R-CERM

1 2

20% X5R

1 2

20% X5R

3

1

B

6

C

Thunderbolt Connector A

R9401

12

1 2

5%

1/20W

MF

201

B2 B4 B6

B10 B12

B16 B18 B20

514-0803

For J9400 TBT SMT pads (3, 5, 17 & 19):

S16

SHIELD PINS

J9400

MDP-D2

F-RT-TH

HPD CONFIG1 CONFIG2 GND2 ML_LANE3P ML_LANE3N GND4 AUX_CHP AUX_CHN DP_PWR

PORT B

SHIELD PINS

S21

S22

S14

S15

ML_LANE0P ML_LANE0N

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

S19

S20

S12

S13

GND0

GND1

GND3

RETURN

S17

S18

B1 B3 B5 B7B8 B9 B11 B13B14 B15 B17 B19

0.1UF

10% 16V

2

X5R-CERM

0201

SIGNAL_MODEL=TBT_MUX

TBT_A_CIO_SEL

IN

DP_AUXIO_EN

IN

DP_TBTPA_AUXCH_N

93

DP_TBTPA_AUXCH_P

93

DP_TBTPA_DDC_DATA DP_TBTPA_DDC_CLK

IN

TBT_A_CONFIG1_BUF

DP_TBTPA_ML_P<1>

93

DP_TBTPA_ML_N<1>

93

TBT_A_LSTX

IN

TBT_A_LSRX_UNBUFPP3V3_SW_TBTAPWR

TBT_A_DP_PWRDN

IN

DP_TBTPA_HPD

DP Dir

1

C9421

0.1UF

X5R-CERM

TBT Dir

TBT: TX_0

1

R9427

10% 16V

2

0201

2

1

R9426

1M

5%

1/20W

MF

201

2

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

GND_VOID=TRUE

C9405

(0-18.9V)

7

93

7

93

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

7

93

7

93 93

TBT: TX_1

10K

5% 1/20W MF 201

CBTL05023

1

BIASIN

2

AUXIO_EN

7

AUX-

8

AUX+

4

DDC_DAT

5

DDC_CLK

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

6

DP_PD

HPDOUT

1

0.01UF

10% 25V

2

X5R-CERM

0201

TBT_A_R2D_P<0> TBT_A_R2D_N<0> TBTACONN_7_C

GND_VOID=TRUE

C9406

0.01UF

TBT_A_R2D_P<1> TBT_A_R2D_N<1>

3

15

VDD

CRITICAL

U9420

HVQFN

GND

9

21

10% 25V

X5R-CERM

0201

BIASOUT

AUXIOAUXIO+

CA_DET

DPMLO+ DPMLO-

THMPAD

1

2

1

R9429

100K

5%

1/20W

MF

201

2

24

23

22

1816

19

20

1712

HPD

1

25

R9428

100K

5% 1/20W MF 201

2

(Both C’s)

C9470

0.22UF

C9471

0.22UF

GND_VOID=TRUE

1

R9470

470K

5% 1/20W MF 201

2

(Both C’s)

C9472

0.22UF

C9473

0.22UF

GND_VOID=TRUE

1

R9472

470K

5% 1/20W MF 201

2

470k R’s for ESD protection on AC-coupled signals.

TBT_A_BIAS

VOLTAGE=3.3V

1

C9425

0.1UF

10% 16V

2

X5R-CERM 0201

DP_A_AUXCH_DDC_N DP_A_AUXCH_DDC_P TBT: RX_1 Bias Sink

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1> TBT: LSX_A_R2P/P2R (P/N)

TBT_A_HPD

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1

R9471

470K

5% 1/20W MF 201

2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1

R9473

470K

5% 1/20W MF 201

2

20% X5R

6.3V 0201

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

84

84 93

84

84 93

84

84 93

D

C

7

35 93

IN

7

35 93

IN

B

7

35 93

IN

7

35 93

IN

TBT_A_HPD

A

84

35

OUT

TBT_A_CONFIG1_RC

TBT_A_CONFIG2_RC

R9452

1/20W

SIZE

A

D

SYNC_MASTER=D2_KEPLER

1

C9402

0.01UF

10% 16V

2

X5R-CERM

1

R9451

1M

5%

5% 1/20W

MF

201

2

C9494

330PF

X7R-CERM

0201

1

C9495

10% 16V

330PF

10% 16V

2

X7R-CERM 0201

1

R9441

100K

5% 1/20W MF 201

2

0201

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

PAGE TITLE

Thunderbolt Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

94 OF 132

SHEET

84 OF 99

124578

8 7 6 5 4 3

PP3V3_SW_TBTBPWR

85

12

V3P3 must be S4 to support wake from Thunderbolt devices.

=PP3V3_S4_TBTBPWRSW

D

8

CRITICAL

C9687

100UF

20%

6.3V

POLY-TANT

CASE-B2-SM

=PPHV_SW_TBTBPWRSW

8

18V Max

1

C9680

2

X5R-CERM-1

1

C9615

4.7UF

10% 25V

2

X5R-CERM 0603

70

IN

35 37

IN

70 84

IN

C

For 12V systems:

PART NUMBER

118S0145

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT_B_D2R_P<0>

7

35 93

OUT

TBT_B_D2R_N<0>

7

35 93

OUT

DP_TBTPB_ML_C_P<3>

35 93

IN

DP_TBTPB_ML_C_N<3>

35 93

IN

7

OUT

7

OUT

TBT_B_D2R_P<1> TBT_B_D2R_N<1>

B

QTY

2

1

22UF

20%

6.3V 2

2

603

C9610

0.1UF

10% 25V X5R 402

=TBTBPWRSW_EN

TBT_B_HV_EN

=TBT_S0_EN

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

C9674

C9675

C9676

C9677

3.3V/HV Power MUX

Nominal Min Max IV3P3 1100mA 1030mA 1200mA

C9681

0.1UF

10% 16V X5R-CERM 0201

1

2

DESCRIPTION

GND_VOID=TRUE

(Both C’s)

1 2

0.47UF

1 2

0.47UF

C9678

0.22UF

C9679

0.22UF

GND_VOID=TRUE

(Both C’s)

1 2

0.47UF

1 2

0.47UF

85 93

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CRITICAL

U9610

CD3210A0RGP

QFN

RSVD

5

11 10

17

EN

HV_EN

S0

ISET_V3P3

GND

123

4

TBTHV:P15V

R9613

22.6K

<RHVS3>

V3P3OUT

OUT

RSVD

ISET_S0

ISET_S3

THRM

PAD

13

1%

1/20W

MF

201

21

1

2

18

12

14

C9685

X5R-CERM

1516

8

9

TBTHV:P15V

1

R9614

22.6K

1% 1/20W MF 201

2

<RHVS0>

REFERENCE DES

R9610,R9613

R9611,R9614

TBT_B_D2R_C_P<0>

7

2.2K

1/20W

93

TBT_B_D2R_C_N<0>

7

93

DP_TBTPB_ML_P<3>

93

DP_TBTPB_ML_N<3>

93

TBT: Unused

1

R9699

2.2K

5%

5% 1/20W

MF

201

2

GND_VOID=TRUE

TBT_B_D2R_C_P<1> TBT_B_D2R_C_N<1>

C9698

30PF

5%

50V

C0G-NP0

0402

20%

4V

CERM-X5R-1

201

20%

CERM-X5R-14V201

1 2

20% X5R

1 2

20% X5R

TBT_B_BIAS

85

GND_VOID=TRUE

20%

4V

CERM-X5R-1

201

20%

CERM-X5R-14V201

DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N

6.3V 0201

R9698

1

0.1UF

10% 16V

0201

2

TBTBPWRSW_ISET_V3P3

TBTBPWRSW_ISET_S0

TBTBPWRSW_ISET_S3

12V: See below

TBTBPWRSW_ISET_S3_R TBTBPWRSW_ISET_S0_R

ILIM = 40000 / RISET

CRITICAL

GND_VOID=TRUE

R9694

SIGNAL_MODEL=EMPTY

1

C9699

30PF

5% 50V

2

C0G-NP0 0402

PP3V3_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

PPHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTHV:P15V

R9610

22.6K

1/20W

201

1% MF

1

C9611

0.1UF

10% 25V

2

X5R 402

1

2

TBTHV:P15V

1

R9611

22.6K

2

C9686

10UF

20%

6.3V CERM-X5R 0402

Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.

BOM OPTION

TBTHV:P12V

GND_VOID=TRUE

1

R9695

1K

5%

MF

2

5% 1/20W MF 201

2

SIGNAL_MODEL=EMPTY

R9678

1/20W

201

R9679

D9698

BAR90-02LRH

D9699

BAR90-02LRH

85

1

R9612

36.5K

2

<RV3P3>

470K

1 2

470K

1 2

CRITICAL

GND_VOID=TRUE

A K

CRITICAL

L9698

0603

SIGNAL_MODEL=EMPTY

CRITICAL

L9699

0603

SIGNAL_MODEL=EMPTY

1% 1/20W MF 201

TSLP-2-7

1% 1/20W MF 201

SIGNAL_MODEL=TBTPIN

(Both D’s)

650NH-5%-0.430MA-0.52OHM

C9600

0.01UF

X7R-CERM

GND_VOID=TRUE

12

GND_VOID=TRUE

10% 50V

0402

5% MF

93

CRITICAL

L9600

FERR-120-OHM-3A

1 2

1

2

1/20W

TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

0603

1

C9601

0.01UF

10% 50V

2

X7R-CERM 0402

201

35 93

BI

35 93

BI

35 93

IN

35 93

IN

85

PP3V3RHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

TBT Dir

C9620

0.1UF

10% 16V

X5R-CERM

0201

SIGNAL_MODEL=TBT_MUX

TBT_B_CIO_SEL

35

IN

DP_AUXIO_EN

25 84

IN

83

BI

83

IN

35 82

OUT

35

IN

35

IN

35

OUT

DP_TBTPB_AUXCH_N

93

DP_TBTPB_AUXCH_P

93

DP_TBTPB_DDC_DATA DP_TBTPB_DDC_CLK

TBT_B_CONFIG1_BUF

DP_TBTPB_ML_P<1>

93

DP_TBTPB_ML_N<1>

93

TBT_B_LSTX

TBT_B_DP_PWRDN

DP_TBTPB_HPD

5

VCC

GND

2

0.1UF

0.22UF

1 2

16V10% 0201

X5R-CERM

1 2

16V10% 0201

X5R-CERM

1 2

6.3V

20% X5R

0201

1 2

6.3V

20% X5R

0201

3

1

B

6

C

CRITICAL

U9660

74AUP1T97

SOT891

C9630

C9631

C9632

C9633

4

Y A

DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_C_P

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

PP3V3_SW_TBTBPWR TBT_B_LSRX_UNBUF

TBT_B_LSRX

35

OUT

Y = B

1

C9660

0.1UF

10% 16V

2

X5R-CERM 0201

Thunderbolt Connector B

R9601

12

1 2

5%

1/20W

MF

DP Dir

201

A2 A4 A6

A10 A12

A16 A18 A20

514-0803

For J9600 TBT SMT pads (3, 5, 17 & 19):

S5

SHIELD PINS

J9400

MDP-D2

F-RT-TH

HPD CONFIG1 CONFIG2 GND2 ML_LANE3P ML_LANE3N GND4 AUX_CHP AUX_CHN DP_PWR

PORT A

SHIELD PINS

S10

S11

ML_LANE0P ML_LANE0N

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

S9

S1

S2S3S4

GND0

GND1

GND3

RETURN

S6S7S8

A1 A3 A5 A7A8 A9 A11 A13A14 A15 A17 A19

DP Dir

1

C9621

0.1UF

2

X5R-CERM

0201

(0-18.9V)

TBT Dir

TBT: TX_0

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

1

10% 16V

2

1

R9626

1M

5%

1/20W

MF

201

2

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

93

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

93

1

R9627

10K

5% 1/20W MF 201

2

1

BIASIN

2

AUXIO_EN

7

AUX-

8

AUX+

4

DDC_DAT

5

DDC_CLK

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

6

DP_PD

HPDOUT

TBT_B_R2D_P<0>

7

TBT_B_R2D_N<0>

7

TBTBCONN_7_C

GND_VOID=TRUE

TBT_B_R2D_P<1>

7

TBT_B_R2D_N<1>

7

3

VDD

CRITICAL

U9620

CBTL05023

HVQFN

GND

9

GND_VOID=TRUE

C9605

0.01UF

X5R-CERM

C9606

0.01UF

X5R-CERM

0201

10% 25V

0201

15

21

10% 25V

1

R9629

100K

5%

1/20W

MF

201

2

24

BIASOUT

23

AUXIO-

22

AUXIO+

1816

CA_DET

19

DPMLO+

20

DPMLO-

1712

HPD

THMPAD

25

1

2

1

R9628

100K

5% 1/20W MF 201

2

C9670

C9671

GND_VOID=TRUE

1

R9670

1

470K

5% 1/20W

2

MF 201

2

C9672

C9673

GND_VOID=TRUE

1

R9672

470K

5% 1/20W MF 201

2

470k R’s for ESD protection on AC-coupled signals.

TBT_B_BIAS

VOLTAGE=3.3V

1

C9625

0.1UF

10% 16V

2

X5R-CERM 0201

DP_B_AUXCH_DDC_N DP_B_AUXCH_DDC_P TBT: RX_1 Bias Sink

TBT_B_CONFIG1_RC

DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1> TBT: LSX_A_R2P/P2R (P/N)

TBT_B_HPD

GND_VOID=TRUE

(Both C’s)

1 2

GND_VOID=TRUE

1

R9671

470K

5% 1/20W MF 201

2

GND_VOID=TRUE

(Both C’s)

1 2

GND_VOID=TRUE

1

R9673

470K

5% 1/20W MF 201

2

20% X5R

0.22UF

6.3V 0201

85

85 93

85

85 93

85

TBT_B_R2D_C_P<0> TBT_B_R2D_C_N<0>

DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1>

85 93

D

C

7

35 93

IN

7

35 93

IN

B

7

35 93

IN

7

35 93

IN

TBT_B_HPD

A

85

35

OUT

TBT_B_CONFIG1_RC

TBT_B_CONFIG2_RC

R9652

1/20W

SIZE

A

D

SYNC_MASTER=D2_KEPLER

1

C9602

0.01UF

10% 16V

2

X5R-CERM

1

R9651

1M

5%

5% 1/20W

MF

201

2

C9694

330PF

X7R-CERM

0201

1

C9695

10% 16V

330PF

10% 16V

2

X7R-CERM 0201

1

R9641

100K

5% 1/20W MF 201

2

0201

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

PAGE TITLE

Thunderbolt Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

96 OF 132

SHEET

85 OF 99

124578

8 7 6 5 4 3

3AMP-32V-467

=PPBUS_S0_LCDBKLT

D

8

1 2

82

IN

C

25

IN

=I2C_BKL_1_SCL

44

=I2C_BKL_1_SDA

44

PPBUS_S0_LCDBKLT_PWR

86

B

LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST CIRCUIT

8

F9700

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm

603-HF

BOTTOM

LCD_BKLT_EN

BKLT_PLT_RST_L

R9753 AND R9757 NEED TO BE 402 PACK FOR LAB ACCESS

R9753

R9757

82

IN

VOLTAGE=12.6V

1

R9788

301K

1% 1/16W MF-LF 402

2

LCDBKLT_EN_DIV

1

R9789

147K

1% 1/16W MF-LF 402

2

LCDBKLT_EN_L

Q9707

SSM6N15FEAPE

SOT563

LCD_BKLT_PWM

D

5

SG

SSM6N15FEAPE

1 2

R9731

1 2

301K

1% 1/16W MF-LF

402

0.1UF

X7R-CERM

0402

1

10% 16V

2

C9782

3

4

LCDBKLT_DISABLE

Q9707

SOT563

2

5%

1/16W0MF-LF

5%01/16W MF-LF

R9715

100K

1% 1/16W MF-LF

402

1 2

R9704

1 2

CRITICAL

Q9706

FDC638APZ_SBMS001

SSOT6-HF

4

3

6

D

SG

1

402

0

5% 1/16W MF-LF

402

PPBUS S0 LCDBkLT FET

MOSFET CHANNEL RDS(ON) LOADING

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

1 2 5 6

PPBUS_S0_LCDBKLT_PWR

86

8

=PP3V3_S0_BKL_VDDIO

8

NO STUFF

1

C9704

33PF

5% 50V

2

C0G-CERM 0402

FDC638APZ P-TYPE 43 mOhm @4.5V

0.715 A (EDP)

THERE IS A SENSE RESISTOR BETWEEN PPBUS_SW_LCDBKLT_PWR AND PPBUS_SW_BKL ON THE SENSOR PAGE

PLACE_NEAR=L9710.1:5MM

PLACE_NEAR=U9701.22:3MM

1

2

BKLT_EN

(EEPROM should set EN_I_RES=1)

1

R9714

15.4K

1/16W MF-LF

1%

402

I_LED=23.96MA I_LED=369/Riset

2

99

CRITICAL

1

C9712

10UF

10% 25V

2

X5R 805

PLACE_NEAR=U9701.22:5MM

C9714

0.01UF

10% 16V X7R-CERM 0402

1

C9710

2

1UF

10% 25V X5R 603-1

BKL_ISET BKL_SCL BKL_SDA

LVDS_BKL_PWM_RC

TP_BKL_FAULT

1

R9716

12.7K

1% 1/16W MF-LF

402

2

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

=PP5V_S0_BKL

8

22

U9701

LLP

LP8545SQX-EXTJ

CRITICAL

GND_S

9

15

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

23

VIN

SW

FB

OUT1

OUT2

OUT3SCLK

OUT4

OUT5

OUT6

VSYNC

THRM

PAD

GND_L

25

(APN: 353S3376)

PWM RES = 9+3

XW9710

24

21

12

13

14

16

17

18

19

SM

1 2

PLACE_NEAR=L9710.1:3MM

1

C9713

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U9701.8:3MM

1

C9711

0.1UF

10% 16V

2

X7R-CERM 0402

8

VDDIO VLDO

6

GD

R9765

10K

5% 1/16W MF-LF 402

5

FSET

20

FILTER

3

ISET

10

11

SDA

2

PWM

7

FAULT

4

EN

GND_SW

1

BKL_SGND

PLACE_NEAR=U9701.9:10MM

BKL_FSET

BKL_FLT

1

2

FPWM=19.2KHZ details in spec

PLACE XW9710 AWAY FROM U9701.1 AND U9701.15 ADD VIAS IN TPAD OF U9701

NEED VALUE CHANGES FOR 55V AND 96 LEDS !!!

*L9710, Q9701, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.

CRITICAL

22UH-20%-2.4A-0.105OHM

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

BKL_SW

L9710

1 2

DEM8030C-SM

152S1527

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

BKL_FET_CNTL

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPBUS_S0_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=50V

SWITCH_NODE=TRUE

5

4

1 2 3

BKL_FB BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 BKL_ISEN4 BKL_ISEN5 BKL_ISEN6 BKL_VSYNC_R

1

R9755

10K

5% 1/16W MF-LF 402

2

PLACE_NEAR=L9710.2:3MM

CRITICAL

Q9701

SI7812DN

PWRPK-1212-8

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

CRITICAL

D9701

POWERDI-123

A K

DFLS2100

R9708

63.4K

1/16W MF-LF

R9709

59.0K

1/16W MF-LF

PLACE_NEAR=U9701.12:10MM

PLACE_NEAR=U9701.13:10MM

PLACE_NEAR=U9701.14:10MM

PLACE_NEAR=U9701.16:10MM

PLACE_NEAR=U9701.17:10MM

PLACE_NEAR=U9701.18:10MM

C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719 C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE

PLACE_NEAR=D9701.2:5MM

CRITICAL

1

C9718

2.2UF

10% 100V

2

X7R-CERM 1210

PLACE_NEAR=D9701.2:3MM

1%

402

1%

402

1

2

1

2

D_BKL:DEV

R9717

1 2

D_BKL:DEV

R9718

1 2

D_BKL:DEV

R9719

1 2

D_BKL:DEV

R9720

1 2

D_BKL:DEV

R9721

1 2

D_BKL:DEV

R9722

1 2

CRITICAL

1

C9715

2.2UF

10% 100V

2

X7R-CERM 1210

PLACE_NEAR=D9701.2:3MM

10.2

0.1%

1/16W

TF

402

10.2

0.1%

1/16W

TF

402

10.2

0.1%

1/16W

TF

402

10.2

0.1%

1/16W

TF

402

10.2

0.1%

1/16W

TF

402

10.2

0.1%

1/16W

TF

402

CRITICAL

1

C9716

2.2UF

10% 100V

2

X7R-CERM 1210

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

PLACE_NEAR=D9701.2:5MM

CRITICAL

1

C9719

2.2UF

10% 100V

2

X7R-CERM 1210

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

1

C9717

1000PF

10% 100V

2

X7R-CERM 0603

PLACE_NEAR=R9708.1:5MM

7

OUT

7

OUT

7

OUT

7

OUT

12

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=55V

81

7

81

7

D

99 81

7

C

B

PART NUMBER

A

116S0004

QTY

6

DESCRIPTION

RES, 0OHM, 0402

6 3

REFERENCE DES

R9717,R9718,R9719,R9720,R9721,R9722

CRITICAL

BOM OPTION

D_BKL:PROD

SYNC_MASTER=D2_KEPLER

PAGE TITLE

LCD Backlight Driver (LP8545)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

97 OF 132

SHEET

86 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

PCH VCCIO (1.05V S0) REGULATOR

=PPVIN_S0_PCHVCCIOS0

8

=PP5V_S0_PCHVCCIOS0

XW9801

SM

=PPPCHVCCIO_S0_REG

8

87

1 2

PLACE_NEAR=U1800.BJ8:1MM

PCH_VCCIOSENSE_P

97

C

IN

OUT

2.2UF

1

10% 16V

2

X5R 603

PP5V_S0_PCHVCCIOS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

XW9802

SM

1 2

PLACE_NEAR=U1800.BJ6:1MM

B

PCH_VCCIOSENSE_N

97

R9804

3.01K

1/16W MF-LF

R9805

2.74K

1/16W MF-LF

Vout = 0.5V * (1 + Ra / Rb)

1

R9844

3.01K

1%

1/16W MF-LF 402

402

2

1

R9845

2.74K

1%

1/16W MF-LF 402

402

2

1

C9804

10PF

C0G-CERM

0402

1

C9805

5%

50V

10PF

5% 50V

2

C0G-CERM 0402

1

2

70

C9802

C9803

0.047UF

10% 16V X7R-CERM 0402

8

=PCHVCCIOS0_EN

PCHVCCIOS0_FB

PCHVCCIOS0_SREF

PCHVCCIOS0_VO

PCHVCCIOS0_OCSET

PCHVCCIOS0_PGOOD

PCHVCCIOS0_RTN

PCHVCCIOS0_FSEL

1

R9803

0

5% 1/16W MF-LF 402

2

PCHVCCIOS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

R9801

3

EN

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

1

2.2

5% 1/16W MF-LF

402

2

13

VCC

U9800

ISL95870

UTQFN

CRITICAL

GND

1

XW9800

SM

1 2

PLACE_NEAR=U9800.1:1mm

PVCC

PGND

1

C9801

2

14

BOOT

UGATE

PHASE

LGATE

16

10UF

20% 10V X5R 603

12

11

10

15

PCHVCCIOS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

R9830

PCHVCCIOS0_VBST

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

PCHVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

PCHVCCIOS0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

PCHVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

(PCHVCCIOS0_OCSET)

(PCHVCCIOS0_VO)

1

C9830

1

1UF

1/10W MF-LF

0

5%

603

10% 16V

2

X5R 402

2

1

6

3 4 5

OCP = R9841 x 8.5uA / R9840 OCP = 14.4A

OMIT_TABLE OMIT_TABLE

CRITICAL

C9820

POLY-TANT

CASE-D2E-SM

2

68UF

376S0953

CRITICAL

1

20% 16V

C9821

2

POLY-TANT

CASE-D2E-SM

CRITICAL

Q9830

RJK0214DPA

WPAK2

0.68UH-20%-23A-0.0034OHM

7

1

R9841

2.0K

1% 1/16W MF-LF

402

2

68UF

20% 16V

C9840

1000PF

5%

25V

NP0-C0G

402

1

C9822

1000PF

5% 25V

2

NP0-C0G 402

PLACE_NEAR=Q9830.1:1.5mm

CRITICAL

L9830

1 2

PIMB103T

152S1651

PCHVCCIOS0_CS_P

97 99

PCHVCCIOS0_CS_N

97 99

12

1

R9842

2.0K

1% 1/16W MF-LF 402

2

PPPCHVCCIO_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

CRITICAL

R9840

0.001

1%

1W MF-1 0612

2 1 4 3

PLACE_NEAR=L9830.2:1.5mm

C9823

1000PF

NP0-C0G

C

=PPPCHVCCIO_S0_REG

270UF

TANT

1

20%

2V

2

Vout = 1.05V 12A MAX OUTPUT f = 300 kHz

CRITICAL

C9849

1

5%

25V

2

402

CRITICAL

1

C9848

270UF

20% 2V

2

TANT CASE-B4-SM

CASE-B4-SM

8

87

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH VCCIO (1.05V) POWER SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

98 OF 132

SHEET

87 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

=PP3V3_S0_PWRCTL

8

70 88

GPU Rail Sequencing

KEPLER GPU REQUIRES RAILS TO COME up in the following order:

1) GPU_3.3V

D

EG_RAIL1_EN

82

EG_RAIL2_EN

82

EG_RAIL3_EN

82

EG_RAIL4_EN

82

EG_RAIL5_EN

82

2) IFPX IOVDD - 1.8V

3) GPUVCORE

4) FBVDDQ/GDDR5 1.35V

5) PEXVDD/Q

OR IFPY IOVDD - 1.05V

P3V3GPU_EN

MAKE_BASE=TRUE

P1V8GPU_EN

MAKE_BASE=TRUE

GPUVCORE_EN

MAKE_BASE=TRUE

P1V35GPUFB_EN

MAKE_BASE=TRUE

P1V05_S0GPU_EN

MAKE_BASE=TRUE

=P3V3GPU_MISC_EN

=P3V3GPU_EN

=P1V8GPU_EN

=GPUVCORE_EN

=P1V35FB_EN

=P1V05_GPU_EN

69

OUT

69

OUT

8

OUT

80

OUT

74

OUT

74

OUT

69

8

IN

8

IN

80

IN

74

IN

74

IN

=PP3V3_S0GPU_FET

=PP1V8_GPU_FET

GPUVCORE_PGOOD

MAKE_BASE=TRUE

GPUFB_PGOOD

MAKE_BASE=TRUE

P1V05_S0GPU_PGOOD

MAKE_BASE=TRUE

GPU_PGOOD1

GPU_PGOOD2

GPU_PGOOD3

GPU_PGOOD4

PM_ALL_GPU_PGOOD

NOTE: NO PU ON 3V3 AND 1V8 PGOODS SINCE THEY ARE SYNTHETIC.

NOTE 2: CHECK IF 1V8 IS READ AS LOGIC HIGH BY GMUX

EXT GPU PWRGD Pullup

1

R9900

100K

5% 1/20W MF 201

2

1

2

R9901

100K

5% 1/20W MF 201

1

2

R9902

100K

5% 1/20W MF 201

OUT

Unused PGOOD signal

=PP3V3_S0_PWRCTL

8

70 88

82

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

NO STUFF

R9991

10K

1/16W MF-LF

402

5%

1

2

CPUIMVP_AXG_PGOOD

DDRREG_PGOOD

P1V5S3RS0_RAMP_DONE

65

IN

64

IN

69

IN

D

NOTE: 1V8 MAY NOT BE REQUIRED FOR KEPLER IF THERE IS NO LVDS

C

1

R9910

82

5% 1/20W MF 201

2

NOSTUFF

PEG_R2D_P<0>

PEG_R2D_N<0>

71 89

1

R9915

82

5% 1/20W MF 201

2

NOSTUFF

PEG_R2D_P<5>

PEG_R2D_N<5>

71 89

C

1

R9913

82

5% 1/20W MF 201

2

NOSTUFF

PEG_R2D_P<3>

PEG_R2D_N<3>

71 89

1

R9917

82

5% 1/20W MF 201

2

NOSTUFF

PEG_R2D_P<7>

PEG_R2D_N<7>

71 89

PLACE R9910 - R9917 CLOSE TO U8000

SIZE

B

A

D

B

A

PCIE TEST STRUCTURES (FOR LAB USE)

1

R9920

82

5% 1/20W MF 201

2

NOSTUFF

PEG_D2R_P<0>

PEG_D2R_N<0>

9

71 89

1

R9924

82

5% 1/20W MF 201

2

NOSTUFF

9

71 89

1

R9927

82

5% 1/20W MF 201

2

NOSTUFF

PLACE R9920 - R9927 CLOSE TO U1000

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<7>

PEG_D2R_N<7>

9

71 89

9

71 89

9

71 89

SYNC_MASTER=D2_KEPLER

9

71 89

PAGE TITLE

Power Sequencing EG/PCH S0

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

99 OF 132

SHEET

88 OF 99

124578

8 7 6 5 4 3

12

CPU Signal Constraints

LAYER

CPU_50S

CPU_55S

CPU_27P4S

ALLOW ROUTE ON LAYER?

=50_OHM_SE

*

=27P4_OHM_SE

*

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

LAYER

D

SPACING_RULE_SET

CPU_AGTL

CPU_8MIL

CPU_COMP

CPU_ITP

CPU_VCCSENSE

Most CPU signals with impedance requirements are 50-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.

LINE-TO-LINE SPACING

*

* ?

SOURCE: IVB PLATFORM DG , Tables 205-207

=STANDARD

8 MIL

20 MIL

=2:1_SPACING

25 MIL

MINIMUM LINE WIDTH

=50_OHM_SE

=55_OHM_SE

=27P4_OHM_SE

WEIGHT

?*

?

?*

MINIMUM NECK WIDTH

=50_OHM_SE

=55_OHM_SE=55_OHM_SE

=27P4_OHM_SE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

CPU_AGTL

CPU_VID

CPU_VREF

MAXIMUM NECK LENGTH

=50_OHM_SE

=55_OHM_SE

=27P4_OHM_SE

LINE-TO-LINE SPACING

LAYER

TOP,BOTTOM

=2x_DIELECTRIC

*

* ?

PCI-Express

PCIE_85D

SPACING_RULE_SET

PCIE

CLK_PCIE

LAYER

*

ALLOW ROUTE ON LAYER?

=85_OHM_DIFF

=90_OHM_DIFF

LINE-TO-LINE SPACING

15 MIL

20 MIL

MINIMUM LINE WIDTH

=85_OHM_DIFF

=90_OHM_DIFF

WEIGHT

?

?*

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=85_OHM_DIFF

SPACING_RULE_SET

PCIE

MAXIMUM NECK LENGTH

=85_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFFCLK_PCIE_90D

LAYER

TOP,BOTTOM

LINE-TO-LINE SPACING

C

PEG

LAYER

PEG_80D

SPACING_RULE_SET

PEG_RXRX

PEG_TXTX

PEG_TXRX

*

LAYER

* ?

*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PEG_D2RPEG_D2R PEG_R2DPEG_R2D

PEG_D2R PEG_R2D

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF

LINE-TO-LINE SPACING

=4X_DIELECTRIC

=10X_DIELECTRIC

AREA_TYPE

* * *

MINIMUM LINE WIDTH

=80_OHM_DIFF

WEIGHT

? ?

SPACING_RULE_SET

PEG_RXRX PEG_TXTX PEG_TXRX

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=80_OHM_DIFF=80_OHM_DIFF

B

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

7 MIL

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

0.457 MM

12 MIL

DIFFPAIR PRIMARY GAP

?

TABLE_SPACING_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=85_OHM_DIFF =85_OHM_DIFF

=90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

15 MIL

DIFFPAIR PRIMARY GAP

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=80_OHM_DIFF

=STANDARD

7 MIL

=90_OHM_DIFF

=80_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

DMI_S2N DMI_S2N

DMI_N2S DMI_N2S

FDI_DATA

FDI_FSYNC

FDI_LSYNC

FDI_INT DMI_CLK100M

I125

DMI_CLK100M

I126

DP_INT_ML

I127

DP_INT_ML

I128

DP_INT_AUX

I129

DP_INT_AUX

I131

CPU_EDP_COMP

I132

CPU_PEG_COMP

I130

I133

XDP_CLK_CPU XDP_CLK_CPU

XDP_CLK_PCH

XDP_CLK_PCH DPLL_REF_CLK120M

I138

DPLL_REF_CLK120M CLK_PCIE

I139

XDP_TDI CPU_50S

XDP_TDO CPU_50S

XDP_TMS CPU_50S XDP_TCK CPU_ITP

XDP_TRST_L

XDP_BPM CPU_50S XDP_BPM_L

XDP_BDRESET_L

I134

XDP_PRDY_L

I135

XDP_PREQ_L

I136

CPU_CATERR_L

CPU_PROC_SEL_L

I115

CPU_PECI

CPU_PROCHOT_L

XDP_CPU_PWRGD PM_THRMTRIP_L

PM_MEM_PWRGD CPU_PWRGD

I150

CPU_SM_RCOMP

I120

I121

I122

I123

CPU_VCCSASENSE

I137

CPU_MEM_VREF

I140

CPU_MEM_VREF

I141

PHYSICAL

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85DFDI_DATA CPU_50S

CPU_50S

CPU_50S CLK_PCIE_90D

CLK_PCIE_90D

DP_85D DP_85D

DP_85D

CPU_27P4S CPU_27P4S

CPU_50S

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D

CPU_50S

CPU_50S CPU_ITP CPU_50S

CPU_50S

CPU_50S CPU_50S

CPU_50SPM_SYNC

CPU_50S CPU_50S

CPU_27P4S

CPU_50S CPU_50S

CPU_50S CPU_55S

CPU_27P4S

CPU_27P4S CPU_27P4S

CPU_27P4S

CPU_27P4S CPU_27P4S

CPU_27P4S

CPU_50S

NET_TYPE

SPACING

PCIE PCIE

PCIE

PCIE CPU_AGTL

CPU_AGTL

CPU_AGTL CLK_PCIE

CLK_PCIE

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

CPU_COMP CPU_COMP

CPU_ITPCPU_CFG

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

CPU_ITP

CPU_ITP CPU_ITP

CPU_ITP

CPU_AGTL

CPU_AGTL CPU_VIDCPU_50S

CPU_AGTL

CPU_ITP CPU_8MIL

CPU_AGTL

CPU_AGTL CPU_AGTL

CPU_COMP

CPU_VID CPU_VID

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSECPU_VCCSENSE CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSECPU_VCCSENSE CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSECPU_VCCSENSE

CPU_AGTL

CPU_VREF CPU_VREF

DMI_S2N_P<3:0> DMI_S2N_N<3:0> DMI_N2S_P<3:0> DMI_N2S_N<3:0> FDI_DATA_P<7:0> FDI_DATA_N<7:0>

FDI_FSYNC<1..0>

FDI_LSYNC<1..0>

FDI_INT

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

DP_INT_IG_ML_P<3:0> DP_INT_IG_ML_N<3:0>

DP_INT_IG_AUX_P DP_INT_IG_AUX_N CPU_EDP_COMP CPU_PEG_COMP CPU_CFG<17..0> ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N DPLL_REF_CLKP DPLL_REF_CLKN

XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L<3..0> XDP_BPM_L<7..4> XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L

CPU_CATERR_L CPU_PROC_SEL_L CPU_PECI

CPU_PROCHOT_L XDP_CPU_PWRGD

PM_THRMTRIP_L PM_SYNC PM_MEM_PWRGD

CPU_PWRGD CPU_SM_RCOMP<2..0>

CPU_VIDSOUT

CPU_VIDSCLK CPU_VIDALERT_L

CPU_VCCSA_VID<1..0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

CPU_VCCSASENSE

PPCPU_MEM_VREFDQ_A

PPCPU_MEM_VREFDQ_B

10 18

9

10

9

10

9

10

9

10

10 18

11 17

10 82

10

10 24

11 17

17 24

9

11

9

11

11 24

11 24 25

11 24

11 41

11 20

11 20 42

11 41 42 65

24

11 20 42

11 18

11 18 27

11 20 24

11

13 65

13 62

13 65

13 67

13 65

13

13 62

10 33

D

C

B

CPU_MEM_VREF

I144

CPU_MEM_VREF

I145

CPU_MEM_VREF

I146

CPU_MEM_VREF

I147

XDP_CLK_ITP

I148

XDP_CLK_ITP

I149

CLK_PCIE_90D

PEG_80D PEG_80D

CPU_VREF

CPU_VREF CPU_VREF

CPU_VREF

CLK_PCIE

PEG_R2D PEG_R2D

PEG_R2DPEG_R2D PEG_R2D

PEG_D2RPEG_80DPEG_D2R

PEG_D2RPEG_80D PEG_D2RPEG_80D

PEG_D2RPEG_80D

A

6 3

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFCA_B

XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N

PEG_R2D_P<7..0> PEG_R2D_N<7..0> PEG_R2D_C_P<7..0> PEG_R2D_C_N<7..0> PEG_D2R_P<7..0> PEG_D2R_N<7..0> PEG_D2R_C_P<7..0> PEG_D2R_C_N<7..0>

28 29 33

30 31 33

28 29 33

30 31 33

24

71 88

9

71

9

71

9

71 88

9

71 88

71

SYNC_MASTER=D2_KEPLER

PAGE TITLE

CPU Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

100 OF 132

SHEET

89 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

Memory Bus Constraints

LAYER

MEM_37S MEM_40S MEM_72D MEM_50S

ALLOW ROUTE ON LAYER?

* * =STANDARD =STANDARD * =72_OHM_DIFF

=50_OHM_SE

*

MEM_85D

D

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD MEM_CMD2MEM

MEM_DATA2DATA

MEM_DATA2MEM

MEM_DQS2MEM

MEM_2OTHER MEM_DQBL2BL MEM_DQCH2CH

LAYER

* * * * * * * * * * *

LINE-TO-LINE SPACING

=4:1_SPACING

=3:1_SPACING =2.5:1_SPACING =1.5:1_SPACING

=3:1_SPACING =1.5:1_SPACING

=3:1_SPACING

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

MEM_CTRL MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*

DDR3 (Memory Down):

DQ signals should be matched within 0.508mm of associated DQS pair

.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement. DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm]. CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm. CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs. A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs. DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric. Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

SOURCE: Chief River SFF Platform DG, Rev 0.7 (#460452), Section 2.6.3

MEM_*

MEM_CTRL

MEM_*

* *

25 MILS 16 MILS 25 MILS

AREA_TYPE

*

AREA_TYPE

* *

AREA_TYPE

*

AREA_TYPE

MINIMUM LINE WIDTH

=37_OHM_SE=37_OHM_SE

=85_OHM_DIFF

WEIGHT

? ? ? ? ? ? ? ? ? ? ?

SPACING_RULE_SET

MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

SPACING_RULE_SET

MEM_DQS2MEM

SPACING_RULE_SET

MEM_2OTHER

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=37_OHM_SE=37_OHM_SE

=40_OHM_SE =40_OHM_SE=40_OHM_SE=40_OHM_SE

=72_OHM_DIFF=72_OHM_DIFF

=50_OHM_SE=50_OHM_SE

=85_OHM_DIFF

NET_SPACING_TYPE1 NET_SPACING_TYPE2

=72_OHM_DIFF

=50_OHM_SE

=85_OHM_DIFF

MEM_CMD MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DQ_BYTE* MEM_*_DQ_BYTE* MEM_A_DQ_BYTE*

MEM_A_DQ_BYTE* MEM_B_DQ_BYTE* MEM_B_DQ_BYTE* MEM_A_DQ_BYTE* MEM_B_DQ_BYTE*

MEM_*

MEM_CMD

MEM_* =SAME

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

=72_OHM_DIFF =72_OHM_DIFF

=STANDARD =STANDARD

=85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF

MEM_CMD2MEM MEM_CMD2CMD

MEM_DATA2MEM

MEM_DQBL2BL MEM_DQBL2BL MEM_DQCH2CH

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

* *

AREA_TYPE

* * * * *

SPACING_RULE_SET

MEM_DATA2DATA

B

A

6 3

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK MEM_A_CLK

MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL1

I101

MEM_A_CNTL

I102

MEM_A_CNTL MEM_A_CNTL1

I103

MEM_A_CNTL

I104

MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD

MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4

I105

MEM_A_DQS0

I106

MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7

MEM_B_CLK MEM_B_CLK

MEM_B_CNTL

MEM_B_CNTL1

I110

MEM_B_CNTL0

I111

MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL0

I109

MEM_B_CMD

I108

MEM_B_CMD6

I107

MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD

MEM_B_DQ_BYTE2

MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7

NET_TYPE

PHYSICAL

MEM_72D

MEM_37S MEM_37S MEM_37S MEM_37S

MEM_37S MEM_37S MEM_37S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_CMD

MEM_50S MEM_50S MEM_50S

MEM_50SMEM_A_DQ_BYTE5

MEM_50SMEM_A_DQ_BYTE7 MEM_A_DQ_BYTE7

MEM_85D MEM_85D MEM_85D MEM_85D

MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D

MEM_85D

MEM_72D MEM_CLK MEM_72D

MEM_37S

MEM_37S MEM_37S

MEM_37S MEM_37S MEM_37S

MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_CMD

MEM_40S MEM_CMD

MEM_50SMEM_B_DQ_BYTE5 MEM_B_DQ_BYTE5

MEM_85D

MEM_85D MEM_85D

MEM_85D

MEM_85D MEM_85D

MEM_CLK MEM_CLKMEM_72D

MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL

MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD

MEM_A_DQ_BYTE0MEM_A_DQ_BYTE0 MEM_50S

MEM_A_DQ_BYTE4MEM_50S MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6MEM_50SMEM_A_DQ_BYTE6

MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQSMEM_85D MEM_DQSMEM_85D MEM_DQSMEM_85D MEM_DQSMEM_85D MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CTRL MEM_CTRL

MEM_CTRL MEM_CTRL MEM_CTRL

MEM_CMDMEM_40S

MEM_B_DQ_BYTE0MEM_50SMEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1MEM_50SMEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2MEM_50S MEM_B_DQ_BYTE3MEM_50SMEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4MEM_50SMEM_B_DQ_BYTE4

MEM_B_DQ_BYTE6MEM_50SMEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7MEM_50SMEM_B_DQ_BYTE7

MEM_DQS MEM_DQSMEM_85D MEM_DQSMEM_85D MEM_DQS MEM_DQSMEM_85D MEM_DQSMEM_85D MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQS MEM_DQSMEM_85D MEM_DQSMEM_85D MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQS

SPACING

MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0>

MEM_A_CKE<3..0> MEM_A_CS_L<3..2> MEM_A_CS_L<1> MEM_A_CS_L<0>

MEM_A_ODT<3..2> MEM_A_ODT<1> MEM_A_ODT<0> MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56>

MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0>

MEM_B_CKE<3..2> MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CS_L<3..0> MEM_B_ODT<3..1> MEM_B_ODT<0>

MEM_B_A<15..7> MEM_B_A<6> MEM_B_A<5..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56>

MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

12 28 29 32

12 29 32

12 28 32

12 29 32

12 28 32

12 28 29 32

12 28 29

12 30 31 32

12 31 32

12 30 32

12 30 31 32

12 31 32

12 30 32

12 30 31 32

12 30 31

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

101 OF 132

SHEET

90 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

Digital Video Signal Constraints

LAYER

PCH_DP_90D

LVDS_85D

SPACING_RULE_SET

PCH_DISPLAYPORT

LVDS

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

D

LAYER

ISL3,ISL4,ISL9,ISL10

*

ALLOW ROUTE ON LAYER?

=90_OHM_DIFF

LINE-TO-LINE SPACING

=4:1_SPACING

MINIMUM LINE WIDTH

=90_OHM_DIFF

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=90_OHM_DIFF

SPACING_RULE_SET

PCH_DISPLAYPORT

LVDS

MAXIMUM NECK LENGTH

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF

LINE-TO-LINE SPACING

=4:1_SPACING

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

=90_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LVDS_IG_A_CLK

LVDS_IG_A_DATA LVDS_IG_A_DATA

LVDS_IG_A_DATA3

PHYSICAL

LVDS_85D

LVDS_85D LVDS_85D

LVDS_85D

NET_TYPE

LVDS

LVDS LVDS

LVDS

SPACING

LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3>

12

9

18

9

18

9

18

9

18

9

18

9

18

D

SATA Interface Constraints

SATA_90D

SATA_37SE

SATA_50SE

SPACING_RULE_SET

SATA

LAYER

ISL3,ISL4,ISL9,ISL10

*

ALLOW ROUTE ON LAYER?

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

LINE-TO-LINE SPACING

SATA_ICOMP

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

MINIMUM LINE WIDTH

=90_OHM_DIFF =90_OHM_DIFF

WEIGHT

=5:1_SPACING

15 MIL

C

USB 2.0 Interface Constraints

LAYER

PCH_USB_RBIAS

USB_85D

SPACING_RULE_SET

USB

LAYER

ISL3,ISL4,ISL9,ISL10

USB_RBIAS

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

USB 3.0 INTERFACE CONSTRAINTS

SPACING_RULE_SET

B

USB3

SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+

System Clock Signal Constraints

CLK_SLOW_55S

CLK_25M_55S

SPACING_RULE_SET

CLK_SLOW

CLK_25M =5x_DIELECTRIC

*

LAYER

ISL3,ISL4,ISL9,ISL10

LAYER

* *

LAYER

* *

ALLOW ROUTE ON LAYER?

=85_OHM_DIFF

MINIMUM LINE WIDTH

LINE-TO-LINE SPACING

=4:1_SPACING

15 MIL

LINE-TO-LINE SPACING

=5:1_SPACING

ALLOW ROUTE ON LAYER?

LINE-TO-LINE SPACING

=2x_DIELECTRIC

=STANDARD=STANDARD

=85_OHM_DIFF

WEIGHT

MINIMUM LINE WIDTH

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

A

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=STANDARD

=85_OHM_DIFF

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

LINE-TO-LINE SPACING

=5:1_SPACING

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4:1_SPACING

LINE-TO-LINE SPACING

=5:1_SPACING

DIFFPAIR PRIMARY GAP

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

=37_OHM_SE=37_OHM_SE

=50_OHM_SE=50_OHM_SE

SPACING_RULE_SET

SATA

MINIMUM NECK WIDTH

=STANDARD

=85_OHM_DIFF

SPACING_RULE_SET

USB

SPACING_RULE_SET

USB3

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

=85_OHM_DIFF=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LVDS_85D LVDS_85D

SATA_90D SATA_90D

SATA_90D

SATA_90D SATA_90D

SATA_90D

SATA_90D SATA_90D

SATA_90D

SATA_90D SATA_90D

SATA_90D

SATA_90D SATA_90D

SATA_90D

SATA_90D SATA_90D

SATA_90D

SATA_50SE SATA_37SE

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

PCH_USB_RBIAS USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

I232

I233 I234

I235

I218

I219

I213

I236 I237

I260

I259

I238 I239

I245 I244

I247

I246 I248

I249

I220 I221

I222

I223 I224

I225 I226

I227

I230 I229

I228

I231

LVDS_IG_B_DATA LVDS_IG_B_DATA

SATA_HDD_R2D

SATA_HDD_D2R

SATA_HDD_R2D

SATA_HDD_D2R

SATA_HDD_R2D

SATA_ODD_R2D

SATA_ODD_D2R

PCH_SATA3_ICOMP PCH_SATA_ICOMP

USB_HUB1_UP

USB_HUB2_UP

USB_EXTA

USB_EXTB

USB_EXTC

USB_CAMERA

USB_BT

USB_TPAD

USB_IR

PCH_USB_RBIAS USB_T29A

USB_EXTA

USB_CAMERA

USB_EXTA

USB3_EXTB_TX

USB3_EXTB_RX

USB3_EXTC_TX

USB3_EXTC_RX

USB3_EXTA_TX

USB3_EXTA_RX

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SYSCLK_CLK32K_RTC

I256

SYSCLK_CLK25M_SB

I255 I254

SYSCLK_CLK25M_ENET

I253

I252

SYSCLK_CLK25M_TBT

I251

I250

PHYSICAL

CLK_SLOW_55S CLK_SLOW

CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S

NET_TYPE

LVDS LVDS

SATA SATA

SATA

SATA SATA

SATA

SATA SATA

SATA

SATA SATA

SATA

SATA SATA

SATA

SATA SATA

SATA

SATA_ICOMP SATA_ICOMP

USB

USB USB

USB

USB USB

USB

USB USB

USB

USB USB

USB

USB USB

USB

USB USB

USB

USB_RBIAS USB

USB

USB USB

USB

USB USB3

USB3

USB3 USB3

USB3

USB3 USB3

USB3

USB3 USB3

SPACING

CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M

6 3

LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_SSD_D2R_MUX_OUT_P SATA_SSD_D2R_MUX_OUT_N SATA_SSD_R2D_MUX_IN_P SATA_SSD_R2D_MUX_IN_N SATA_SSD_D2R_P SATA_SSD_D2R_N SATA_SSD_R2D_P SATA_SSD_R2D_N

SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P

SATA_ODD_D2R_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N

PCH_SATA3COMP

PCH_SATAICOMP

USB_EXTB_XHCI_P

USB_EXTB_XHCI_N

USB_EXTB_EHCI_P

USB_EXTB_EHCI_N

USB_HUB_UP_P

USB_HUB_UP_N

USB_EXTA_P

USB_EXTA_N

USB_EXTB_P

USB_EXTB_N

USB_EXTC_P

USB_EXTC_N

USB_CAMERA_CONN_P

USB_CAMERA_CONN_N

USB_BT_P

USB_BT_N

USB_BT_CONN_P

USB_BT_CONN_N

USB_BT_WAKE_P

USB_BT_WAKE_N

USB_TPAD_P

USB_TPAD_N

USB_SMC_P

USB_SMC_N

PCH_USB_RBIAS

USB_EXTD_XHCI_P

USB_EXTD_XHCI_N

USB_EXTA_MUXED_P

USB_EXTA_MUXED_N

USB_CAMERA_P

USB_CAMERA_N

USB_LT1_P

USB_LT1_N

USB3_EXTB_TX_P

USB3_EXTB_TX_N

USB3_EXTB_RX_P

USB3_EXTB_RX_N

USB3_EXTC_TX_P

USB3_EXTC_TX_N

USB3_EXTC_RX_P

USB3_EXTC_RX_N

USB3_EXTA_TX_P

USB3_EXTA_TX_N

USB3_EXTA_RX_P

USB3_EXTA_RX_N

SYSCLK_CLK32K_RTC SYSCLK_CLK25M_SB

SYSCLK_CLK25M_SB_R SYSCLK_CLK25M_ENET SYSCLK_CLK25M_ENET_R SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT_R

9

17 39

39

9

17

19 26

19 40

7

9

7

9

7

34

9

19

19 26

40

19 34

40

19 38

7

9

19 40

17 25

17

25 35

35

18

17

26 38

19

34

49

41

19 38

19

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

102 OF 132

SHEET

91 OF 99

124578

SIZE

C

B

A

D

8 7 6 5 4 3

LPC Bus Constraints

LAYER

LPC_50S

CLK_LPC_50S

SPACING_RULE_SET

LAYER

LPC

CLK_LPC

D

SMBus Interface Constraints

LAYER

SMB_50S

SPACING_RULE_SET

LAYER

SMB

HD Audio Interface Constraints

LAYER

HDA_50S

SPACING_RULE_SET

LAYER

HDA

SIO Signal Constraints

LAYER

CLK_SLOW_55S

ALLOW ROUTE ON LAYER?

*

=50_OHM_SE

*

LINE-TO-LINE SPACING

* ?

ALLOW ROUTE ON LAYER?

*

LINE-TO-LINE SPACING

*

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=50_OHM_SE

LINE-TO-LINE SPACING

*

=2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=55_OHM_SE =55_OHM_SE

C

*

LINE-TO-LINE SPACING

ALLOW ROUTE ON LAYER?

LINE-TO-LINE SPACING

SPACING_RULE_SET

LAYER

CLK_SLOW

SPI Interface Constraints

LAYER

SPI_55S

SPACING_RULE_SET

SPI

LAYER

B

A

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE

=50_OHM_SE=50_OHM_SE =50_OHM_SE

6 MIL

8 MIL

MINIMUM LINE WIDTH

WEIGHT

?*

MINIMUM NECK WIDTH

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

8 MIL

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

8 MIL

TABLE_SPACING_RULE_ITEM

?

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

6 3

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD

LPC_FRAME_L LPC_RESET_L

PCH_LPC_CLK0

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA

SMBUS_PCH_1_CLK

SMBUS_PCH_1_DATA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

SPI_CLK

SPI_MOSI

SPI_MISO

PCIE_ENET_R2D

PCIE_ENET_D2R

PCIE_AP_R2D

PCIE_AP_D2R

I275 I276

PCIE_AP_D2R

I278

I277

PCIE_TBT_D2R

PCIE_TBT_R2D

PCIE_TBT_D2R

PCIE_TBT_R2D

PCIE_TBT_D2R

I271

I273

PCIE_TBT_R2D

I274 I272

PCIE_CLK100M

I253

I254

PCIE_CLK100M_TBT_

I262

I261

I255

I257

PCIE_CLK100M_TBT_

I256

I259

I258

I260

PCIE_CLK100M 1:1_DIFFPAIR

I279

I280

PCIE_CLK100M

PCIE_CLK100M_ENET

PCIE_CLK100M_AP

PCIE_CLK100M_FW

I281 I282

PCIE_CLK100M_EXCARD

PCIE_TBT_R2D

I263

PCIE_TBT_R2D

I264

PCIE_TBT_R2D

I265

PCIE_TBT_R2D

I267

PCIE_TBT_D2R

I266

PCIE_TBT_D2R

I268

PCIE_TBT_D2R

I270

PCIE_TBT_D2R

I269

PHYSICAL

LPC_50S

LPC_50S LPC_50S

CLK_LPC_50S

CLK_LPC_50S CLK_LPC_50S

SMB_50S

SMB_50S SMB_50S

SMB_50S

HDA_50S

HDA_50S HDA_50S

HDA_50S

HDA_50S HDA_50S

HDA_50S

HDA_50S HDA_50S

SPI_55S

SPI_55S SPI_55S

SPI_55S

SPI_55S SPI_55SSPI_CS0

SPI_55S

PCIE_85D

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85D PCIE_85D

PCIE_85D

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D

CPU_50S CPU_50S

1:1_DIFFPAIR CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE_90D

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85D PCIE_85D

PCIE_85D

PCIE_85D PCIE_85D

NET_TYPE

LPC

LPC LPC

CLK_LPC

CLK_LPC CLK_LPC

SMB

SMB SMB

SMB

HDA

HDA HDA

HDA

HDA HDA

HDA

HDA HDA

SPI

SPI SPI

SPI

SPI SPI

SPI

PCIE

PCIE PCIE

PCIE

PCIE PCIE

PCIE

PCIE PCIE

PCIE

PCIE PCIE

SPACING

PCIE PCIE

PCIE

PCIE PCIE

PCIE

PCIE PCIE

PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIE CLK_PCIE

PCIE PCIE

PCIE

PCIE PCIE

PCIE

PCIE PCIE

LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS

SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R

SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L

PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N

PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N

PCIE_AP_D2R_PI_P PCIE_AP_D2R_PI_N PCIE_AP_R2D_PI_P PCIE_AP_R2D_PI_N

PCIE_SSD_D2R_MUX_OUT_P PCIE_SSD_D2R_MUX_OUT_N PCIE_SSD_R2D_C_P<1..0> PCIE_SSD_R2D_C_N<1..0> PCIE_SSD_D2R_P<1..0> PCIE_SSD_D2R_N<1..0> PCIE_SSD_R2D_MUX_IN_P PCIE_SSD_R2D_MUX_IN_N

PCIE_SSD_D2R_C_P<1> PCIE_SSD_D2R_C_N<1> PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_N<1> PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN

PEX_TSTCLK_O_P

PEX_TSTCLK_O_N

PEG_CLK100M_P

PEG_CLK100M_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

PCIE_TBT_R2D_C_P<3..0>

PCIE_TBT_R2D_C_N<3..0>

PCIE_TBT_R2D_P<3..0>

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_D2R_P<3..0>

PCIE_TBT_D2R_N<3..0>

PCIE_TBT_D2R_C_P<3..0>

PCIE_TBT_D2R_C_N<3..0>

7

17 41 43 82

7

17 41 43 82

25

19 25

25 41

7

25 43

17 44

17 53

17

17 53

17

17 53

53

17 53

17 25

17 43

43

17 43

43

17 43

43

7

17 38

7

17 38

7

17 38

7

17 38

7

34

7

34

17 34

7

34

7

34

39

9

39

17

17 35

17

17 25

71 95

17 71

7

17 34

9

17 39

9

35

9

35

39

17 38

17

35

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

12

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

103 OF 132

SHEET

92 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

LAYER

TBT_SPI_55S

SPACING_RULE_SET

TBT_SPI

D

Thunderbolt/DP Connector Signal Constraints

LAYER

TBTDP_80D

TBTDP_85D

TBTDP_100D

SPACING_RULE_SET

TBTDP

NOTE: Thunderbolt high-speed nets are NOT directly assigned to TBTDP_*D physical rules. TABLE_PHYSICAL_ASSIGNMENT symbols must be used to create the assignments. Proper differential impedance depends on mDP connector used. For 514-0637: R2D nets (SMT pins) = 80D, D2R nets (TH pins) = 100D

LAYER

ALLOW ROUTE ON LAYER?

=55_OHM_SE =55_OHM_SE

*

LINE-TO-LINE SPACING

ALLOW ROUTE ON LAYER?

*

=80_OHM_DIFF

=85_OHM_DIFF

*

=100_OHM_DIFF

LINE-TO-LINE SPACING

* ?

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

=2x_DIELECTRIC

=5x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

?*

MINIMUM LINE WIDTH

=80_OHM_DIFF

=100_OHM_DIFF

WEIGHT

MINIMUM NECK WIDTH

=55_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=80_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

C

TBTDP

MAXIMUM NECK LENGTH

=55_OHM_SE

MAXIMUM NECK LENGTH

=80_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF =80_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

LINE-TO-LINE SPACING

=7x_DIELECTRIC

WEIGHT

12

Thunderbolt/DP Net Properties

ELECTRICAL_CONSTRAINT_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

DP_TBTPA_ML

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=85_OHM_DIFF=85_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TBT_A_D2R TBT_A_D2R

TBT_A_AUXCH

TBT_B_R2D

DP_TBTPB_ML

TBT_B_D2R TBTDP_85D

TBT_B_AUXCH

TBT_B_D2R

PHYSICAL

TBTDP_85DTBT_A_R2D TBTDP_85DTBT_A_R2D

TBTDP_85D TBTDP_85D

DP_85D

DP_85D DP_85D

DP_85D

TBTDP_85D TBTDP_85D

DP_85D

DP_85D DP_85D

DP_85D

DP_85D TBTDP_85D

TBTDP_85D

TBTDP_85DTBT_B_R2D

TBTDP_85D TBTDP_85D

TBTDP_85D

DP_85D

DP_85D DP_85D

DP_85D

DP_85D DP_85D

TBTDP_85D

DP_85D

DP_85D DP_85D

DP_85D

DP_85D DP_85D

TBTDP_85D TBTDP_85D

NET_TYPE

SPACING

TBTDP TBTDP

DISPLAYPORTDP_TBTPA_ML

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

TBTDP TBTDP

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT TBTDP

TBTDP

TBTDP TBTDP

TBTDP

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

TBTDP

TBTDP TBTDP

TBTDP

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

TBTDP TBTDP

TBT_A_R2D_C_P<1..0> TBT_A_R2D_C_N<1..0> TBT_A_R2D_P<1..0> TBT_A_R2D_N<1..0>

DP_TBTPA_ML_C_P<3..1:2> DP_TBTPA_ML_C_N<3..1:2> DP_TBTPA_ML_P<3..1:2> DP_TBTPA_ML_N<3..1:2> DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

TBT_A_D2R_C_P<1..0> TBT_A_D2R_C_N<1..0> TBT_A_D2R_P<1..0> TBT_A_D2R_N<1..0>

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

TBT_B_R2D_C_P<1..0> TBT_B_R2D_C_N<1..0> TBT_B_R2D_P<1..0> TBT_B_R2D_N<1..0>

DP_TBTPB_ML_C_P<3..1:2> DP_TBTPB_ML_C_N<3..1:2> DP_TBTPB_ML_P<3..1:2> DP_TBTPB_ML_N<3..1:2> DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

TBT_B_D2R_C_P<1..0> TBT_B_D2R_C_N<1..0> TBT_B_D2R_P<1..0> TBT_B_D2R_N<1..0>

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

7

35 84

7

35 84

7

84

7

84

35 84

84

7

84

7

84

7

35 84

7

35 84

84

7

35 85

7

35 85

7

85

7

85

35 85

85

Only used on dual-port hosts.

7

85

7

85

7

35 85

7

35 85

85

D

C

Thunderbolt IC Net Properties

ELECTRICAL_CONSTRAINT_SET

TBT_SPI_CLK TBT_SPI_MOSI

B

TBT_SPI_MISO

TBT_SPI_CS_L

A

6 3

PHYSICAL

DP_85D DP_85D

DP_85D

TBT_SPI_55S TBT_SPI_55S

TBT_SPI_55S

NET_TYPE

SPACING

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

TBT_SPI TBT_SPI

TBT_SPI

DP_TBTSRC_ML_C_P<3..0> DP_TBTSRC_ML_C_N<3..0> DP_TBTSRC_AUXCH_C_P DP_TBTSRC_AUXCH_C_N

TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L

Only used on hosts supporting Thunderbolt video-in

35

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Thunderbolt Constraints

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

Apple Inc.

R

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

105 OF 132

SHEET

93 OF 99

124578

SIZE

B

A

D

8 7 6 5 4 3

12

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

1TO1_DIFFPAIR

LAYER

ALLOW ROUTE ON LAYER?

*

MINIMUM LINE WIDTH

=STANDARD=STANDARD

MINIMUM NECK WIDTH

=STANDARD =STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

D

C

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA SMBUS_SMC_5_SCL

SMBUS_SMC_5_SDA

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

SMB_50S SMB_50S

SMB_50S

SMB_50S SMB_50S

SMB_50S

SMB_50S SMB_50S

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI

CHGR_CSO

1TO1_DIFFPAIR

PHYSICAL

NET_TYPE

SMB SMB

SMB

SMB SMB

SMB

SMB SMB

SPACING

SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_5_SCL SMBUS_SMC_5_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

CHGR_CSI_P CHGR_CSI_N

CHGR_CSO_P CHGR_CSO_N

7

41 44

61

41 44

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

106 OF 132

SHEET

94 OF 99

124578

8 7 6 5 4 3

GDDR5 Frame Buffer Signal Constraints

LAYER

GDDR5_45R50SE

GDDR5_80D

SPACING_RULE_SET

GDDR5_CLK GDDR5_CMD

D

GDDR5_DATA

GDDR5_EDC

Digital Video Signal Constraints

DP_85D

HDMI_90D

SPACING_RULE_SET

DISPLAYPORT

HDMI

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES. SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

LAYER

ALLOW ROUTE ON LAYER?

*

=50_OHM_SE

=45_OHM_SE

*

=80_OHM_DIFF

*

LINE-TO-LINE SPACING

=5x_DIELECTRIC

*

=3x_DIELECTRIC

*

=3x_DIELECTRIC

* *

=5x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=85_OHM_DIFF

*

=90_OHM_DIFF

LINE-TO-LINE SPACING

* ?

*

MINIMUM LINE WIDTH

=50_OHM_SE

=80_OHM_DIFF

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=3x_DIELECTRIC

WEIGHT

? ? ? ?

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=50_OHM_SE =45_OHM_SE=45_OHM_SEGDDR5_45SE

=80_OHM_DIFF

SPACING_RULE_SET

MINIMUM NECK WIDTH

=85_OHM_DIFF

SPACING_RULE_SET

C

MAXIMUM NECK LENGTH

12.7 MM

=45_OHM_SE

=80_OHM_DIFF

LAYER

GDDR5_CLK GDDR5_CMD

TOP,BOTTOM TOP,BOTTOM

GDDR5_DATA?TOP,BOTTOM

GDDR5_EDC

DISPLAYPORT

HDMI

TOP,BOTTOM

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=STANDARD

LINE-TO-LINE SPACING

=5x_DIELECTRIC =4x_DIELECTRIC =5x_DIELECTRIC =5x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=80_OHM_DIFF=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

=STANDARD =STANDARD=STANDARD

=85_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

GDDR5 FB A Net Properties

ELECTRICAL_CONSTRAINT_SET

I453 I454

FB_A1_CLK GDDR5_80D

I452 I451

FB_A0_CMD

I450

FB_A1_CMD GDDR5_CMD

I448

FB_A0_CMD

I449

FB_A1_CMD

I447

FB_A0_CMD

I446

FB_A1_CMD GDDR5_CMD

I445

FB_A0_CMD GDDR5_CMD

I444

FB_A1_CMD

I442

FB_A0_CMD

I443

FB_A1_CMD

I440

FB_A0_CMD_R

I441

FB_A1_CMD_R

I439

FB_A0_CMD

I437 I438

FB_A0_EDC0 GDDR5_45SE

I435

FB_A0_EDC1 GDDR5_45SE

I436

FB_A0_EDC2 GDDR5_45SE

I402

FB_A0_EDC3 GDDR5_45SE

I400

FB_A1_EDC0 GDDR5_45SE

I401 I398

FB_A1_EDC2 GDDR5_45SE

I399 I397

FB_A0_DBI_L0

I395

FB_A0_DBI_L1

I396

FB_A0_DBI_L2

I394

FB_A0_DBI_L3

I392

FB_A1_DBI_L0

I393

FB_A1_DBI_L1

I390

FB_A1_DBI_L2

I391

FB_A1_DBI_L3

I389

FB_A0_WCLK0

I388

FB_A0_WCLK0

I387

FB_A0_WCLK1

I385

FB_A0_WCLK1

I386

FB_A1_WCLK0

I384

FB_A1_WCLK0

I383

FB_A1_WCLK1

I382

FB_A1_WCLK1

I380

FB_A0_DQ_BYTE0

I381

FB_A0_DQ_BYTE1

I379

FB_A0_DQ_BYTE2

I378

FB_A0_DQ_BYTE3

I377

FB_A1_DQ_BYTE0

I376

FB_A1_DQ_BYTE1

I375

FB_A1_DQ_BYTE2

I374

FB_A1_DQ_BYTE3

I373

FB_A0_CMD_R

I372

FB_A1_CMD_R

I371

PHYSICAL

GDDR5_80DFB_A0_CLK

GDDR5_80DFB_A1_CLK GDDR5_CLK GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE

GDDR5_45SEFB_A1_EDC1

GDDR5_45SEFB_A1_EDC3

GDDR5_45SE

GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_DATA GDDR5_45SE

GDDR5_80D GDDR5_80D GDDR5_CMD GDDR5_80D GDDR5_80D

GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_45SE GDDR5_DATA

GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_45SE

NET_TYPE

SPACING

GDDR5_CLKGDDR5_80DFB_A0_CLK GDDR5_CLK GDDR5_CLK

GDDR5_CMD

GDDR5_CMD GDDR5_CMD GDDR5_CMD

GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMDFB_A1_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATAGDDR5_45SE GDDR5_DATA GDDR5_DATAGDDR5_45SE GDDR5_DATA GDDR5_DATA

GDDR5_DATA GDDR5_DATAGDDR5_45SE GDDR5_CMD

GDDR5_CMD GDDR5_CMD GDDR5_CMDGDDR5_80D GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_DATA GDDR5_DATA

GDDR5_DATA

GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE

GDDR5_CMD GDDR5_CMD

FB_A0_CLK_P FB_A0_CLK_N FB_A1_CLK_P FB_A1_CLK_N FB_A0_A<8..0> FB_A1_A<8..0> FB_A0_ABI_L FB_A1_ABI_L FB_A0_RAS_L FB_A1_RAS_L FB_A0_CAS_L FB_A1_CAS_L FB_A0_WE_L FB_A1_WE_L FB_A0_CKE_L FB_A1_CKE_L FB_A0_CS_L FB_A1_CS_L FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3> FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3> FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<3> FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3> FB_A0_WCLK_P<0> FB_A0_WCLK_N<0> FB_A0_WCLK_P<1> FB_A0_WCLK_N<1> FB_A1_WCLK_P<0> FB_A1_WCLK_N<0> FB_A1_WCLK_P<1> FB_A1_WCLK_N<1> FB_A0_DQ<7..0> FB_A0_DQ<15..8> FB_A0_DQ<23..16> FB_A0_DQ<31..24> FB_A1_DQ<7..0> FB_A1_DQ<15..8> FB_A1_DQ<23..16> FB_A1_DQ<31..24> FB_A0_RESET_L FB_A1_RESET_L

GDDR5 FB B Net Properties

ELECTRICAL_CONSTRAINT_SET

73 75

I473

FB_B0_CLK

I474

FB_B1_CLK

I472

FB_B1_CLK

I470

FB_B0_CMD

I471

I468

FB_B0_CMD

I469

FB_B1_CMD

I467

FB_B0_CMD

I466

FB_B1_CMD

I465

FB_B0_CMD

I464

FB_B1_CMD GDDR5_CMD

I463

FB_B0_CMD

I462

FB_B1_CMD

I460

FB_B0_CMD_R

I461

FB_B1_CMD_R

I459

I457

FB_B1_CMD

I458

I455

FB_B0_EDC1

I456

FB_B0_EDC2

I434

I433

FB_B1_EDC0

I432

FB_B1_EDC1

I430

FB_B1_EDC2

I431

FB_B1_EDC3

I429

FB_B0_DBI_L0

I428

FB_B0_DBI_L1

I427

FB_B0_DBI_L2

I426

FB_B0_DBI_L3

I424

FB_B1_DBI_L0

I425

FB_B1_DBI_L1

I423

FB_B1_DBI_L2

I422

FB_B1_DBI_L3

I421

FB_B0_WCLK0

I420

FB_B0_WCLK0

I419

FB_B0_WCLK1

I418

FB_B0_WCLK1

I417

FB_B1_WCLK0

I416

FB_B1_WCLK0

I414

FB_B1_WCLK1

I415

FB_B1_WCLK1

I412

FB_B0_DQ_BYTE0

I413

FB_B0_DQ_BYTE1

I411

FB_B0_DQ_BYTE2

I410

FB_B0_DQ_BYTE3

I409

FB_B1_DQ_BYTE0

I408

FB_B1_DQ_BYTE1

I407

FB_B1_DQ_BYTE2

I406

FB_B1_DQ_BYTE3

I404

FB_B0_CMD_R

I405

FB_B1_CMD_R

I403

NET_TYPE

PHYSICAL

GDDR5_80D GDDR5_CLKFB_B0_CLK GDDR5_80D GDDR5_CLK GDDR5_80D GDDR5_CLK GDDR5_80D GDDR5_CLK GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SEFB_B0_EDC0 GDDR5_45SE GDDR5_45SE GDDR5_45SEFB_B0_EDC3 GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE

GDDR5_45SE

GDDR5_45SE GDDR5_45SE GDDR5_45SE

GDDR5_80D

GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA

GDDR5_45SE

GDDR5_45SE GDDR5_45SE GDDR5_45SE

SPACING

GDDR5_CMD GDDR5_CMDFB_B1_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD

GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMDFB_B0_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATAGDDR5_45SE GDDR5_DATA GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMDGDDR5_80D GDDR5_CMDGDDR5_80D GDDR5_CMD GDDR5_CMDGDDR5_80D GDDR5_CMDGDDR5_80D GDDR5_CMDGDDR5_80D GDDR5_CMDGDDR5_80D GDDR5_CMDGDDR5_80D

GDDR5_DATA

GDDR5_DATAGDDR5_45SE GDDR5_DATA GDDR5_DATAGDDR5_45SE GDDR5_DATA GDDR5_CMD GDDR5_CMD

FB_B0_CLK_P FB_B0_CLK_N FB_B1_CLK_P FB_B1_CLK_N FB_B0_A<8..0> FB_B1_A<8..0> FB_B0_ABI_L FB_B1_ABI_L FB_B0_RAS_L FB_B1_RAS_L FB_B0_CAS_L FB_B1_CAS_L FB_B0_WE_L FB_B1_WE_L FB_B0_CKE_L FB_B1_CKE_L FB_B0_CS_L FB_B1_CS_L FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3> FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3> FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<2> FB_B0_DBI_L<3> FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3> FB_B0_WCLK_P<0> FB_B0_WCLK_N<0> FB_B0_WCLK_P<1> FB_B0_WCLK_N<1> FB_B1_WCLK_P<0> FB_B1_WCLK_N<0> FB_B1_WCLK_P<1> FB_B1_WCLK_N<1> FB_B0_DQ<7..0> FB_B0_DQ<15..8> FB_B0_DQ<23..16> FB_B0_DQ<31..24> FB_B1_DQ<7..0> FB_B1_DQ<15..8> FB_B1_DQ<23..16> FB_B1_DQ<31..24> FB_B0_RESET_L FB_B1_RESET_L

73 76

73

73 76

12

D

C

76

MUXGFX & DP AUX MUX NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

DP_INT_ML

B

A

DP_INT_AUXCH

DP_INT_AUXCH DP_85D

I347

I348

I349 I350

DP_INT_ML

I341

I342

DP_INT_ML

I343

I344

DP_INT_ML

I345

I346

DP_INT_AUXCH DP_85D

I333 I334

I336

I335

DP_INT_AUXCH DP_85D

I338

I337

I339 I340

TBT_A_AUXCH DISPLAYPORT

I351 I352

TBT_B_AUXCH

I353

I354

DP_INT_ML

I355

I356

DP_INT_ML

I363 I364

TBT_A_AUXCH DISPLAYPORT

I357

I358 I359

I361

DP_INT_ML

I360

I362

DP_INT_ML

I365 I366

DP_85D

DP_85D DP_85D

DP_85D DP_85DDP_INT_AUXCH

DP_85D

DP_85D DP_85D

DP_85D

DP_85DDP_INT_AUXCH DP_85D

DP_85D DP_85DDP_INT_AUXCH

DP_85D DP_85D

DP_85D

DP_85D DP_85D

DP_85D

DP_85D DP_85D

DP_85D

DP_85D DP_85D

DP_85D

DP_85D DP_85D

DP_85D

6 3

PHYSICAL

NET_TYPE

SPACING

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DISPLAYPORTTBT_B_AUXCH DISPLAYPORT

DISPLAYPORT

DISPLAYPORT DISPLAYPORT

DISPLAYPORT

DP_INT_ML_C_P<3..0> DP_INT_ML_C_N<3..0> DP_INT_AUX_C_P DP_INT_AUX_C_N DP_INT_AUX_P DP_INT_AUX_N DP_INT_EG_AUX_P DP_INT_EG_AUX_N DP_INT_ML_P<3..0> DP_INT_ML_N<3..0> DP_INT_ML_F_P<3..0> DP_INT_ML_F_N<3..0> DP_INT_EG_ML_P<3..0> DP_INT_EG_ML_N<3..0> DPA_IG_AUX_CH_P DPA_IG_AUX_CH_N DPB_IG_AUX_CH_P DPB_IG_AUX_CH_N DP_TBTSNK0_EG_AUXCH_P DP_TBTSNK0_EG_AUXCH_N DP_TBTSNK1_EG_AUXCH_P DP_TBTSNK1_EG_AUXCH_N DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK0_ML_C_P<3..0> DP_TBTSNK0_ML_C_N<3..0> DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N DP_TBTSNK0_ML_P<3..0> DP_TBTSNK0_ML_N<3..0> DP_TBTSNK1_ML_P<3..0> DP_TBTSNK1_ML_N<3..0>

81 82

7

77 82

7

81

77 82

18 83

77 83

7

81

35 83

35 77

35

Kepler Net Properties

ELECTRICAL_CONSTRAINT_SET

GPU_CLK27M GPU_CLK27M

GPU_CLK27M

HDMI_DATA

HDMI_CLK

PHYSICAL

CLK_SLOW_55S CLK_SLOW_55S

CLK_SLOW_55S

1:1_DIFFPAIR

HDMI_90D

HDMI_90D HDMI_90D

HDMI_90D

NET_TYPE

CLK_SLOW CLK_SLOW

CLK_SLOW

HDMI

HDMI HDMI

HDMI

SPACING

GPU_OSC_27M_XTALIN GPU_OSC_27M_XTALOUT GPU_OSC_27M_XTAL_BUFFOUT

GPU_OSC_27M_SSIN

PEX_TSTCLK_O_P PEX_TSTCLK_O_N

HDMI_EG_DATA_C_P<2..0> HDMI_EG_DATA_C_N<2..0> HDMI_EG_CLK_C_P HDMI_EG_CLK_C_N

SYNC_MASTER=D2_KEPLER

PAGE TITLE

GPU (Kepler) CONSTRAINTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

77 78

77

71 92

7

38 77

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

107 OF 132

SHEET

95 OF 99

124578

SIZE

B

A

D

8 7 6 5 4 3

12

SENSE_1TO1_55S

THERM_1TO1_55S

DIFFPAIR

AUDIODIFF

THERM_55S_CPUIMVPISNS1

D

SPACING_RULE_SET

SENSE

THERM

AUDIO

SPACING_RULE_SET

GND

SPACING_RULE_SET

GND_P2MM

PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND

C

GND

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_85D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

CPU_27P4S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

LAYER

*

LAYER

*

LAYER

*

LAYER

*

MEM_CLK

MEM_CMD

MEM_*_DQ_BYTE*

MEM_DQS

LAYER

*

TOP

BOTTOM

ALLOW ROUTE ON LAYER?

=1:1_DIFFPAIR

LINE-TO-LINE SPACING

ALLOW ROUTE ON LAYER?

=2:1_SPACING

=STANDARD

0.20 MM

AREA_TYPE

MINIMUM LINE WIDTH

0.1 MM

=55_OHM_SE =55_OHM_SE

WEIGHT

?

WEIGHT

1000

SPACING_RULE_SET

*

GND_P2MM

GND_P2MMMEM_CTRL

GND_P2MM

MINIMUM LINE WIDTH

B

Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

NET_PHYSICAL_TYPE

LVDS_85D

DP_85D

SATA_90D

CLK_PCIE_90D 100_DIFF_BGA

Memory Constraint Relaxations

A

AREA_TYPE

PHYSICAL_RULE_SET

BGA

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

LAYER

BOTTOM

TOP

LVDS_85D

100_DIFF_BGA

ALLOW ROUTE ON LAYER?

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE=55_OHM_SE

=55_OHM_SE

0.1 MM

=55_OHM_SE

MAXIMUM NECK LENGTH

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_COMP GND_P2MM

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE

SATA

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LVDS

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

0.09 MMMEM_40S

0.09 MM 100 MILMEM_72D

0.09 MM

0.1 MM

0.23 MM 100 MIL

MINIMUM NECK WIDTH

0.127 MM

0.1 MM

MAXIMUM NECK LENGTH

=55_OHM_SE

=55_OHM_SE=55_OHM_SE

=1:1_DIFFPAIR

10 MM

100 MIL

100 MILMEM_37S

100 MILMEM_85D

10 mm

500 MILUSB_85D

6.35 MMMEM_72D

6.35 MMMEM_85D

DIFFPAIR PRIMARY GAP

GND

GNDUSB

SB_POWER

GND

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR=1:1_DIFFPAIR

=1:1_DIFFPAIR

0.2 MM0.2 MM

GND_P2MM

GND_P2MMCLK_PCIE

GND_P2MM

PWR_P2MMSB_POWERCLK_PCIE

PWR_P2MM

GND_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR THERM_1TO1_55S

SENSE_DIFFPAIR

SENSE_DIFFPAIR THERM_1TO1_55S

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR_42

SENSE_DIFFPAIR SENSE_1TO1_55S

AUDIO_DIFFPAIR

I343 I344

AUDIO_DIFFPAIR

I345 I346

AUDIO_DIFFPAIR

I348

I347

AUDIO_DIFFPAIR

I350

I349

AUDIO_DIFFPAIR

I351 I352

AUDIO_DIFFPAIR

I353

I354

AUDIO_DIFFPAIR

I355

I356

AUDIO_DIFFPAIR

I417

AUDIO_DIFFPAIR

I418

AUDIO_DIFFPAIR

I361 I362

AUDIO_DIFFPAIR

I397

I398

AUDIO_DIFFPAIR

I399

I400

AUDIO_DIFFPAIR

I401

I402

AUDIO_DIFFPAIR

I403 I404

AUDIO_DIFFPAIR

I405

I406

AUDIO_DIFFPAIR

I407

I408

PHYSICAL

THERM_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

AUDIODIFF

NET_TYPE

SPACING

THERM

SENSE

AUDIO

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

DDR3THMSNS_D1_P DDR3THMSNS_D1_N

GPUTHMSNS_D_P GPUTHMSNS_D_N

GPU_TDIODE_P GPU_TDIODE_N

VCCSAS0_CS_P VCCSAS0_CS_N VCCSAISNS_R_P VCCSAISNS_R_N ISNS_1V5_MEM_R_P ISNS_1V5_MEM_R_N CPUVCCIOS0_CS_P

CPUVCCIOS0_CS_N CPUVCCIOISNS_R_P CPUVCCIOISNS_R_N GPUISENS_N GPUISENS_P

ISNS_1V5_MEM_N ISNS_1V5_MEM_P

ISNS_AIRPORT_N

ISNS_AIRPORT_N ISNS_AIRPORT_P

ISNS_AIRPORT_P

ISNS_AIRPORT_R_N ISNS_AIRPORT_R_P

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

GPUFB_CS_P

GPUFB_CS_N

ISNS_PP1V0_S0GPU_R_P

ISNS_PP1V0_S0GPU_R_N

ISNS_PP1V8_S0GPU_P

ISNS_PP1V8_S0GPU_N

ISNS_PP1V8_S0GPU_R_P

ISNS_PP1V8_S0GPU_R_N

P1V05_GPU_CS_P

P1V05_GPU_CS_N

ISNS_PP1V5_S0GPU_R_P

ISNS_PP1V5_S0GPU_R_N

CPUIMVP_ISNS1G_P

CPUIMVP_ISNS1G_N

CPUIMVP_ISNS1G_R_P

CPUIMVP_ISNS1G_R_N

ISNS_HS_OTHER_P

ISNS_HS_OTHER_N

ISNS_HS_GPU_P

ISNS_HS_GPU_N

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

CPUIMVP_ISNS_P

CPUIMVP_ISNS_N

ADC1_VSENSE_P

ADC1_VSENSE_N

ADC2_VSENSE_P

ADC2_VSENSE_N

ADC2_ISENSE_P

ADC2_ISENSE_N

ADC2_ISENSE_P

ADC2_ISENSE_N

SPKR_R_RSENSE_P

SPKR_R_RSENSE_N

SPKR_L_RSENSE_P

SPKR_L_RSENSE_N

AUD_LO1_L_P

AUD_LO1_L_N

AUD_LO1_R_P

AUD_LO1_R_N

AUD_LO2_L_P

AUD_LO2_L_N

AUD_LO2_R_P

AUD_LO2_R_N

AUD_MIC_INL_P

AUD_MIC_INL_N

AUD_SPKRAMP_LIN_P

AUD_SPKRAMP_LIN_N

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

AUD_SPKRAMP_LSUBIN_P

AUD_SPKRAMP_LSUBIN_N

AUD_SPKRAMP_RSUBIN_P

AUD_SPKRAMP_RSUBIN_N

LSPKR_INTIV_RSENSE_P

LSPKR_INTIV_RSENSE_N

RSPKR_INTIV_RSENSE_P

RSPKR_INTIV_RSENSE_N

LSPKR_INTIV_P

LSPKR_INTIV_N

RSPKR_INTIV_P

RSPKR_INTIV_N

ISNS_TBT_N

ISNS_TBT_P

ISNS_TBT_R_N

ISNS_TBT_R_P

47

47 77

45 62

45

45 67

45

96

99

74 99

98

74 98

99

46 66

46

96

53 57

53 58

57

99

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

0.1 MM 0.1 MM

AREA_TYPE

SPACING_RULE_SET

*

SPACING_RULE_SET

*

SPACING_RULE_SET

*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

6 3

D2 Specific Net PropertiesD2 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

(USB_EXTA) (USB_EXTA)

(USB_EXTA)

AUDIO_DIFFPAIR

I367 I368

AUDIO_DIFFPAIR

I381 I382

I358 I357

I387

I388 I390

I389

I391 I392

I360

I359

I393

I394 I396

I395

I409 I410

I411

I412

I414

I413 I415

I416

I363 I364

I365 I366

I371

I372 I376

I375

I378 I379

I386

I385

PCIE_CLK100M_AP

AUDIO_DIFFPAIR

PHYSICAL

CLK_PCIE_90D

CLK_PCIE_90D 1TO1_DIFFPAIR

1TO1_DIFFPAIR 1TO1_DIFFPAIR

1TO1_DIFFPAIR

USB_85D

AUDIODIFF

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

DIFFPAIR DIFFPAIR

DIFFPAIR

AUDIODIFF

USB_85D

NET_TYPE

SPACING

CLK_PCIE

USB

AUDIO

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

AUDIO AUDIO

AUDIO

USB

SB_POWER

GND

SYNC_MASTER=D2_CLEAN

PAGE TITLE

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N

USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N

USB2_LT1_P USB2_LT1_N

CONN_USB2_BT_P CONN_USB2_BT_N

USB_LT2_P USB_LT2_N

SPKRAMP_LIN_P

SPKRAMP_LIN_N SPKRAMP_RIN_P

SPKRAMP_RIN_N SSM2375SL_P

SSM2375SL_N

SSM2375SR_P SSM2375SR_N

SPKRCONN_SL_OUT_P_R SPKRCONN_SL_OUT_N_R SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N LSPKR_VSENSE_FILT_P LSPKR_VSENSE_FILT_N RSPKR_VSENSE_FILT_P RSPKR_VSENSE_FILT_N SPKRCONN_SR_OUT_P_R SPKRCONN_SR_OUT_N_R SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N LSPKR_ISENSE_FILT_P LSPKR_ISENSE_FILT_N RSPKR_ISENSE_FILT_P RSPKR_ISENSE_FILT_N

RSUBIN_P RSUBIN_N

LSUBIN_P LSUBIN_N

SSM4321SR_P SSM4321SR_N SSM4321SL_P SSM4321SL_N

LSPKR_VSENSE_IN_P LSPKR_VSENSE_IN_N RSPKR_VSENSE_IN_P RSPKR_VSENSE_IN_N LSPKR_ISENSE_RDIVIDE_P LSPKR_ISENSE_RDIVIDE_N RSPKR_ISENSE_RDIVIDE_P RSPKR_ISENSE_RDIVIDE_N LSPKR_VSENSE_RDIVIDE_P LSPKR_VSENSE_RDIVIDE_N RSPKR_VSENSE_RDIVIDE_P RSPKR_VSENSE_RDIVIDE_N

USB_TPAD_R_P USB_TPAD_R_N

PP3V3_S5

PP3V3_S0 PP1V5_S3RS0_CPUDDR

GND

Project Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

7

34

7

34

61 47

61

57

7

57 59

7

57 59

7

57 59

7

57 59

7

57 59

7

57 59

7

57 59

7

57 59

57

26 49

7 8

8

SYNC_DATE=03/15/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

108 OF 132

SHEET

96 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

15" MBP BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

STANDARD =DEFAULT=DEFAULT

D

55_OHM_SE

50_OHM_SE

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

50_OHM_SE

LAYER

45_OHM_SE

TOP,BOTTOM

45_OHM_SE

LAYER

40_OHM_SE

TOP,BOTTOM

ALLOW ROUTE ON LAYER?

* *

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

* =STANDARD=STANDARDY

ALLOW ROUTE ON LAYER?

40_OHM_SE

LAYER

37_OHM_SE

TOP,BOTTOM

37_OHM_SE =STANDARD

C

LAYER

ALLOW ROUTE ON LAYER?

* =STANDARD

ALLOW ROUTE ON LAYER?

27P4_OHM_SEYTOP,BOTTOM 27P4_OHM_SE

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

72_OHM_DIFF 72_OHM_DIFF 72_OHM_DIFF 72_OHM_DIFF

LAYER

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

80_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

ALLOW ROUTE ON LAYER?

* N

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

ALLOW ROUTE ON LAYER?

* =STANDARD=STANDARD

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

ALLOW ROUTE ON LAYER?

*

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

*

ALLOW ROUTE ON LAYER?

=100_OHM_DIFF

LAYER

ISL3,ISL4

ISL9,ISL10

B

A

80_OHM_DIFF 80_OHM_DIFF 80_OHM_DIFF

85_OHM_DIFF 85_OHM_DIFF 85_OHM_DIFF 85_OHM_DIFF

90_OHM_DIFF 90_OHM_DIFF 90_OHM_DIFF 90_OHM_DIFF

100_OHM_DIFF 100_OHM_DIFF 100_OHM_DIFF 100_OHM_DIFF

100_DIFF_BGA 100_DIFF_BGA 100_DIFF_BGA

MINIMUM LINE WIDTH

Y

MINIMUM NECK WIDTH

=50_OHM_SE

Y

Y Y*

Y Y

Y

MINIMUM LINE WIDTH

0.090 MM

0.076 MM 0.076 MM

MINIMUM LINE WIDTH

0.090 MM

0.070 MM

MINIMUM LINE WIDTH

0.116 MM 0.116 MM

MINIMUM NECK WIDTH

0.090 MM

MINIMUM NECK WIDTH

0.090 MM

0.070 MM

MINIMUM NECK WIDTH

0.085 MM 0.085 MM

MINIMUM LINE WIDTH

Y

0.145 MM 0.095 MM

Y*

MINIMUM LINE WIDTH

Y Y =STANDARD

0.165 MM

0.120 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM0.105 MM

MINIMUM NECK WIDTH

0.095 MM

0.090 MM

MINIMUM NECK WIDTH

0.265 MM 0.095 MM

Y*

N Y Y Y

N* Y Y Y

Y Y Y

N Y Y Y

0.190 MM

MINIMUM LINE WIDTH

=STANDARD

0.124 MM

0.140 MM

MINIMUM LINE WIDTH

=STANDARD

0.096 MM

0.120 MM

MINIMUM LINE WIDTH

=STANDARD

0.089 MM

0.110 MM

MINIMUM LINE WIDTH

=STANDARD

0.081 MM

0.099 MM

MINIMUM LINE WIDTH

=STANDARD

0.065 MM

0.079 MM

MINIMUM LINE WIDTH

0.1 MM

MINIMUM NECK WIDTH

=STANDARD =STANDARD

0.124 MM

0.140 MM

MINIMUM NECK WIDTH

=STANDARD =STANDARD

0.096 MM

0.120 MM

MINIMUM NECK WIDTH

=STANDARD

0.089 MM

0.110 MM

MINIMUM NECK WIDTH

=STANDARD =STANDARD

0.081 MM

0.090 MM

MINIMUM NECK WIDTH

=STANDARD =STANDARD

0.065 MM

0.079 MM

MINIMUM NECK WIDTH

=100_OHM_DIFF Y Y

0.075 MM

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

1:1_DIFFPAIR

LAYER

* Y

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

=STANDARD

MINIMUM NECK WIDTH

=STANDARD

BOARD AREAS

NO_TYPE,BGA

MAXIMUM NECK LENGTH

10 MM=50_OHM_SE 10 MM

MAXIMUM NECK LENGTH

=STANDARD55_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

=DEFAULT

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

0.200 MM 0.200 MM

0.120 MM 0.120 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.126 MM

0.160 MM

DIFFPAIR PRIMARY GAP

0.180 MM

0.180 MM 0.180 MM

DIFFPAIR PRIMARY GAP

0.200 MM

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

0.125 MM 0.125 MM

0.125 MM

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

TABLE_BOARD_INFO

MM

0 MM0 MM

=DEFAULT

=STANDARD

=STANDARD=STANDARD

=STANDARD

=STANDARD=STANDARD

0.200 MM0.200 MM

=STANDARD

0.126 MM

0.126 MM0.126 MM

0.160 MM

=STANDARD=STANDARD

0.180 MM

0.180 MM0.180 MM

0.200 MM

0.200 MM0.200 MM

0.200 MM

=STANDARD=STANDARD

0.200 MM0.200 MM

0.125 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

ALLEGRO VERSION

16.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

**

SPACING_RULE_SET

DEFAULT STANDARD BGA_P1MM BGA_P2MM

P072_SPACE

LAYER

* * * * *

15" MBP Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

AUDIO_DIFFPAIR

I1

I2

SENSE_DIFFPAIR_42

I3 I4

SENSE_DIFFPAIR

I5

I6

SENSE_DIFFPAIR

I7

I8

SENSE_DIFFPAIR

I9 I10

I11 I12

I13

I14

SENSE_DIFFPAIR THERM_1TO1_55S

I15

I16

SENSE_DIFFPAIR THERM_1TO1_55S

I17 I18

SENSE_DIFFPAIR THERM_1TO1_55S

I19

I20

SENSE_DIFFPAIR THERM_1TO1_55S

I21

I22 I23

I24

I26 I25

SENSE_DIFFPAIR

I28

I27

SENSE_DIFFPAIR

I30

I29

I32 I31

SENSE_DIFFPAIR

I67

SENSE_DIFFPAIR

I68

I54

I53

I55 I56

SENSE_DIFFPAIR THERM_1TO1_55S

I33

I34

SENSE_DIFFPAIR THERM_1TO1_55S

I35

I36 I37

I38

I39 I40

I57

SENSE_DIFFPAIR

I58

SENSE_DIFFPAIR

I59

SENSE_DIFFPAIR

I60

I41

I42 I43

I44 I45

I46

I47 I48

I49

I50 I70

I69

I61

I62

AREA_TYPE

BGA

LINE-TO-LINE SPACING

0.1 MM

=DEFAULT

0.1 MM

0.2 MM

0.071 MM

AUDIODIFF

THERM_55S_CPUIMVPISNS1

THERM_1TO1_55S

THERM_55S_CPUIMVPISNS1

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

40_OHM_SE

THERM_1TO1_55S

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

USB_85D USB_85D

USB_85D

SPACING_RULE_SET

P072_SPACE

PHYSICAL

WEIGHT

NET_TYPE

? ? ? ? ?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AUDIO

THERM

USB3 USB3

USB3

USB3 USB3

USB3

USB3 USB3

USB3

CLK_25M

SPACING

ADC1_ISENSE_P ADC1_ISENSE_N

CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N

CPUIMVP_ISNS2G_P CPUIMVP_ISNS2G_N

CPUIMVP_ISNS2_P

CPUIMVP_ISNS2_N CPUIMVP_ISNS3_P

CPUIMVP_ISNS3_N

CPUIMVP_ISUM_R_P CPUIMVP_ISUM_R_N

CPUIMVP_ISUMG_R_P

CPUIMVP_ISUMG_R_N GFXIMVP_ISNS1_P

GFXIMVP_ISNS1_N GFXIMVP_ISNS2_P

GFXIMVP_ISNS2_N

ISNS_CPU_DDR_R_P ISNS_CPU_DDR_R_N

ISNS_LCD_PANEL_P

ISNS_LCD_PANEL_N ISNS_P1V5R1V35_CPUDDR_P

ISNS_P1V5R1V35_CPUDDR_N

ISNS_SSD_P ISNS_SSD_N

ISNS_SSD_R_P ISNS_SSD_R_N

PCHVCCIOS0_CS_P

PCHVCCIOS0_CS_N PCH_VCCIOSENSE_P

PCH_VCCIOSENSE_N

GPUVCORE_SENSE_P GPUVCORE_SENSE_N

GPU_FBVDDQ_SENSE

GPU_FBGND_SENSE P1V05_GPU_PEX_IOVDD_SNS_P

P1V05_GPU_PEX_IOVDD_SNS_N

SPKRL_THMSNS_D2_P SPKRL_THMSNS_D2_N

SPKR_THMSNS_D2_P

SPKR_THMSNS_D2_N TBT_THERMD_P

TBT_THERMD_N

X29THMSNS_D2_P X29THMSNS_D2_N

VDDCIS0_CS_P VDDCIS0_CS_N

GFXIMVP6_VSEN_P

GFXIMVP6_VSEN_N

USB3_EXTA_TX_F_P USB3_EXTA_TX_F_N USB3_EXTA_RX_F_P USB3_EXTA_RX_F_N USB3_EXTA_TX_C_P USB3_EXTA_TX_C_N USB3_EXTB_TX_C_P USB3_EXTB_TX_C_N USB3_EXTB_RX_RC_P USB3_EXTB_RX_RC_N USB3_EXTA_RX_RC_P USB3_EXTA_RX_RC_N

P1V5_GPU_VSNS P1V0S0_VSNS

40

7

38

40

46 65 66

46 66

46 65 66

46 66

46 65 66

46 66

46

80

98

39 99

99

87 99

87

79 80

73 74

74 79

47

38

BOARD UNITS (MIL or MM)

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

6 3

Stackup-Defined Spacing Rules

Note: Outer dielectric is 0.058 mm nominal, Inner dielectric is 0.053 mm nominal.

SPACING_RULE_SET

1:1_SPACING 2:1_SPACING 3:1_SPACING 4:1_SPACING 5:1_SPACING 1:1_SPACING 2:1_SPACING 3:1_SPACING 4:1_SPACING 5:1_SPACING 1:1_SPACING 2:1_SPACING 3:1_SPACING 4:1_SPACING 5:1_SPACING

SPACING_RULE_SET

1x_DIELECTRIC 2x_DIELECTRIC 3x_DIELECTRIC 4x_DIELECTRIC 5x_DIELECTRIC 1x_DIELECTRIC 2x_DIELECTRIC 3x_DIELECTRIC 4x_DIELECTRIC 5x_DIELECTRIC 1X_DIELECTRIC 2x_DIELECTRIC 3x_DIELECTRIC 4x_DIELECTRIC 5x_DIELECTRIC

LAYER

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

LINE-TO-LINE SPACING

0.058 MM

0.116 MM

0.174 MM

0.232 MM

0.290 MM

0.053 MM

0.106 MM

0.159 MM

0.212 MM

0.265 MM

0.101 MM

0.202 MM

0.303 MM

0.404 MM

0.505 MM

LAYER

LINE-TO-LINE SPACING

0.058 MM

0.116 MM

0.174 MM

0.232 MM

0.290 MM

0.053 MM

0.106 MM

0.159 MM

0.212 MM

0.265 MM

0.101 MM

0.202 MM

0.303 MM

0.404 MM

0.505 MM

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

D

C

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

B

SIZE

A

D

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

109 OF 132

SHEET

97 OF 99

124578

8 7 6 5 4 3

GPU 1.0V CURRENT SENSE

=PP5V_S3_DEBUG_ISNS

98

8

EDP Current: 2.846A

SENSOR_NONPROD:Y

P1V05_GPU_CS_P

96 74

P1V05_GPU_CS_N

D

96 74

SENSOR_NONPROD:Y

RD040

4.22K

1 2

1% 1/16W MF-LF

402

RD041

4.22K

1 2

1% 1/16W MF-LF

402

ISNS_PP1V0_S0GPU_R_P

96

ISNS_PP1V0_S0GPU_R_N

96

SENSOR_NONPROD:Y

1

RD042

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

3

2

SENSOR_NONPROD:Y

RD043

1 2

1/16W MF-LF

402

V+ V-

THRM

9

1M

SIGNAL_MODEL=EMPTY

1%

GAIN: 237X

SENSOR_NONPROD:Y

UD080

OPA2333

8

DFN

1

4

SENSOR_NONPROD:Y

1

CD043

0.1UF

20% 10V

2

X7R-CERM 0402

1V0_GPU_IOUT

PLACE_NEAR=UD000. 3:5MM

RD044

4.53K

1 2

1% 1/16W MF-LF

402

PLACE_NEAR=UD000.4:5MM

SENSOR_NONPROD:Y

ADC_CH4

SENSOR_NONPROD:Y

1

CD042

0.22UF

10% 16V

2

CERM 402

IG2C

=PP5V_S3_DEBUG_ADC_AVDD

98

8

SENSOR_NONPROD:Y

RD003

10

1 2

5% 1/16W MF-LF

402

PP5V_S3_DEBUG_ADC_AVDD_FILT

SENSOR_NONPROD:Y

1

CD007

0.1UF

20% 10V

2

CERM 402

ADC_CH1

98

ADC_CH2

98

ADC_CH3

98

ADC_CH4

98

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

1

2

SENSOR_NONPROD:Y

CD001

10UF

20%

6.3V X5R 603

22

CH0

NC

23

CH1

24

CH2

1

CH3

2

CH4

3

CH5

NC

4

CH6

NC

5

CH7

NC

6

COM

12

13

UD000

LTC2309

SENSOR_NONPROD:Y

GND

9

1011181920

21

DVDDAVDD

QFN

REFCOMP

THRM

PP5V_S3_DEBUG_ADC_DVDD_FILT

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

14

AD0

15

AD1

17

SDA

ADC_SDA

16

ADC_SCL

SCL

7

VREF

8

PAD

25

SENSOR_NONPROD:Y

1

CD002

0.1UF

20% 10V

2

CERM 402

SENSOR_NONPROD:Y

ADC_VREF

ADC_REFCOMP

SENSOR_NONPROD:Y

1

CD004

0.1UF

20% 10V

2

CERM 402

1

2

RD007

33

1 2

5% 1/16W MF-LF

402

SENSOR_NONPROD:Y

CD012

10UF

20%

6.3V X5R 603

PLACE_NEAR=U4900.F1:10mm

SENSOR_NONPROD:Y

RD002

33

1 2

5% 1/16W MF-LF

402

SENSOR_NONPROD:Y

1

CD000

10UF

20%

6.3V

2

X5R 603

RD018

10

1 2

5% 1/16W MF-LF

402

=I2C_SMC_ADCS_SDA

PLACE_NEAR=U4900.E4:10mm

=I2C_SMC_ADCS_SCL

=PP5V_S3_DEBUG_ADC_DVDD

SENSOR_NONPROD:Y

1

CD006

2.2UF

20%

6.3V

2

CERM 402-LF

12

8

D

44

BI

44

IN

CPU DDR CURRENT SENSE

=PP5V_S3_DEBUG_ISNS

98

8

C

EDP CURRENT: 5.0A

NC_ISNS_P1V5R1V35_CPUDDRP

69

7

IN

NC_ISNS_P1V5R1V35_CPUDDRN

69

7

IN

SENSOR_NONPROD:Y

LD000

120OHM-0.3A

11K

0.1%

11K

0.1%

MF

402

MF

402

CD010

1UF

1 2

10% 16V X5R 402

1

2

1

2

1 2

0402

CPU_VCORE_C

SENSOR_NONPROD:Y

1

RD001

1.00K

0.1% 1/16W MF 402

2

SENSOR_NONPROD:Y

1

RD006

1.00K

0.1% 1/16W MF 402

2

1V05_S0_RMC_DIV

SENSOR_NONPROD:Y

=PP5V_S0_RMC

8

SENSOR_NONPROD:Y

RD011

1

2

SENSOR_NONPROD:Y

RD004

1

2

PLACE_NEAR=RD305.1:5MM

1/16W

PLACE_NEAR=CD010.1:2MM

XWD000

SM

12

8

IN

=PPVCORE_S0_CPU

45 15 13

B

=PP1V05_S0_RMC

8

PPVCORE_S0_RMC

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.1V

SENSOR_NONPROD:Y

RD000

100

1 2

5% 1/16W MF-LF

402

PP1V05_S0_RMC_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

SENSOR_NONPROD:Y

CD003

10UF

20%

6.3V

CERM-X5R

0402

SENSOR_NONPROD:Y

CD005

A

0.1UF

X7R-CERM

10% 16V

0402

1

CD009

10UF

20%

6.3V

2

CERM-X5R 0402

RD005

1 2

SENSOR_NONPROD:Y

10.2

0.1%

1/16W

TF

402

PP5V_S0_RMC_FLT

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

NO_TEST=TRUE

CPU_VCORE_RMC_DIV

NO_TEST=TRUE

SENSOR_NONPROD:Y

1

CD008

0.1UF

10% 16V

2

X7R-CERM 0402

3

4

SENSOR_NONPROD:Y

PLACE_NEAR=RD305.1:5MM

RD008

10

1 2

5% 1/16W MF-LF

402

RD009

10.2

1 2

0.1%

1/16W

TF

402

DD000

SOD-523

A K

BAT54XV2T1

+

-

SENSOR_NONPROD:Y

UD001

OPA365

5

SOT23

V+

V-

2

1

COMP_CPU_VCORE_RMC

NO_TEST=TRUE

SENSOR_NONPROD:Y

DD001

SOD-523

A K

BAT54XV2T1

CPU_VCORE_RMCP

CPU_VCORE_RMCN

NO_TEST=TRUE

SENSOR_NONPROD:Y

1

CD018

0.1UF

10% 16V

2

X7R-CERM 0402

3

+

4

-

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

RD021

1K

1 2

1% 1/16W MF-LF

402

99 45

EDP CURRENT: 1.0A

81

7

81

7

SENSOR_NONPROD:Y

UD002

OPA365

5

SOT23

V+

V-

2

RD081

7.68K

1 2

1% 1/16W MF-LF

402

RD082

7.68K

1 2

1% 1/16W MF-LF

402

ISNS_CPU_DDR_R_P

97

ISNS_CPU_DDR_R_N

97

SENSOR_NONPROD:Y

1

RD083

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

LCD PANEL CURRENT SENSE

=PP3V3_S0_ISNS

8

NC_ISNS_LCD_PANELN

IN

NC_ISNS_LCD_PANELP

IN

1

VSNS_CPU_VCORE_RMC_OUT

NO_TEST=TRUE

5

IN-

4

IN+ REF

SENSOR_NONPROD:Y

RD020

4.53K

1 2

1% 1/16W MF-LF

402

1

3

SENSOR_NONPROD:Y

RD084

1M

1 2

1% 1/16W MF-LF

402

3

V+

UD070

INA214

SC70

GND

2

SENSOR_NONPROD:Y

5

+

V+

V-

-

2

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

6

OUT

1

GAIN: 100X

ADC_CH1

SENSOR_NONPROD:Y

1

CD020

0.22UF

10% 10V

2

CERM 402

UD082

OPA333DCKG4

SC70-5

4

1

2

LCD_DRV_IOUT

SYNC_MASTER=D2_SEAN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SENSOR_NONPROD:Y

1

CD082

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=UD000.4:5MM

ISNS_CPU_DDR_IOUT

Gain: 130x

SENSOR_NONPROD:Y

CD070

0.1UF

20% 10V CERM 402

1 2

SENSOR_NONPROD:Y

VCRP

98

OUT

R

RD085

SENSOR_NONPROD:Y

4.53K

1 2

1% 1/16W MF-LF

402

PLACE_NEAR=UD000.4:5MM

PLACE_NEAR=UD000.22:5MM

RD071

SENSOR_NONPROD:Y

4.53K

1% 1/16W MF-LF

402

1

2

CD071

0.22UF

20%

6.3V X5R 402

SENSOR_NONPROD:Y

1

CD081

0.22UF

20%

6.3V

2

X5R 402

PLACE_NEAR=UD000.22:5MM

DEBUG SENSORS AND ADC

Apple Inc.

IC3C

ADC_CH2

ADC_CH3

98

ILDC

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

130 OF 132

SHEET

124578

98

SYNC_DATE=03/05/2012

4.18.0

98 OF 99

SIZE

C

B

A

D

8 7 6 5 4 3

12

LCD BKLT Current Sense

=PP5V_S3_ISNS

8

99

EDP Current: 0.715A

=PPBUS_SW_BKL

8

NC_ISNS_LCDBKLTN

2

D

86

XWD200

PPBUS_SW_LCDBKLT_PWR

7

SM

NC_ISNS_LCDBKLTP

7

1

5

4

SENSOR_NONPROD:Y

3

V+

UD200

INA214

SC70

IN-

OUT

IN+ REF

GND

2

GAIN: 100X

SSD CURRENT SENSE

Sense Resistor 0.005 Ohm EDP CURRENT: 5A

ISNS_SSD_P

39 97

ISNS_SSD_N

39 97

C

Sense Resistor 0.005 Ohm EDP Current: 1.06A

PP3V3_WLAN_R

34

XWD235

PP3V3_WLAN_F

34

B

2

SM

1

RD260

7.68K

1 2

1% 1/16W MF-LF

402

RD261

7.68K

1 2

1% 1/16W MF-LF

402

NC_ISNS_AIRPORTP

7

NC_ISNS_AIRPORTN

7

ISNS_SSD_R_P

97

ISNS_SSD_R_N

97

X29 AIRPORT CURRENT SENSE

RD230

SENSOR_NONPROD:Y

2.61K

1 2

1% 1/16W MF-LF

402

RD231

2.61K

1 2

1% 1/16W MF-LF

402

PART NUMBER

ISNS_AIRPORT_R_P

96

ISNS_AIRPORT_R_N

96

SENSOR_NONPROD:Y

116S0114

6

LCDBKLT_IOUT

1

RD262

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

=PP3V3_S3_ISNS

8

QTY

4

1

CD200

0.1UF

SENSOR_NONPROD:Y

20% 10V

2

CERM 402

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.G1:5MM

RD201

4.53K

1 2

=PP3V3_S0_ISNS

1

RD232

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

RES,MTL FILM,100K,5,1/16W,0402,SMD,LF

1% 1/16W MF-LF

402

1

2

1

+

3

-

RD263

1M

1 2

SIGNAL_MODEL=EMPTY

1% 1/16W MF-LF

402

SENSOR_NONPROD:Y

1

3

RD233

1M

1 2

1% 1/16W MF-LF

402

DESCRIPTION

SMC_LCDBKLT_ISENSE

SENSOR_NONPROD:Y

CD201

0.22UF

PLACE_NEAR=U4900.G1:5MM

20%

6.3V X5R 402

GND_SMC_AVSS

UD240 OPA333DCKG4

5

SC70-5

V+

4

V-

2

UD230 OPA333DCKG4

5

+

SC70-5

V+

V-

-

2

GAIN: 383X

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

IBLC

SMC_ADC17

ISNS_SSD_IOUT

GAIN: 130X

4

ISNS_AIRPORT_IOUT

REFERENCE DES

42

41 42 45 46 99

1

CD258

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U4900.A3:5MM

SENSOR_NONPROD:Y

1

CD230

0.1UF

20% 10V

2

CERM 402

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.B8:5MM

CD201,CD222,CD231

RD264

4.53K

1 2

1% 1/16W MF-LF

402

RD234

4.53K

1 2

1% 1/16W MF-LF

402

CRITICAL

SMC_SSD_ISENSE

SMC_ADC22

SMC_X29_ISENSE

SENSOR_NONPROD:Y

1

CD231

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

37

IHDC

SMC_ADC6

42

1

CD240

0.22UF

PLACE_NEAR=U4900.A3:5MM

20%

6.3V

2

X5R 402

GND_SMC_AVSS

IAPC

42

PLACE_NEAR=U4900.B8:5MM

41 42 45 46 99

BOM OPTION

SENSOR_NONPROD:N

SENSE RESISTOR 0.001 OHM EDP CURRENT: 3.0 A

=PP1V05_S0_P1V05TBTFET_R

8

=PP1V05_S0_P1V05TBTFET

8

41 42 45 46 99

www.qdzbwx.com

CRITICAL

RD259

0.001

0612

214

1% 1W MF

ISNS_TBT_P

96

3

ISNS_TBT_N

96

=PP3V3_S0_ISNS

8

45 98 99

EDP CURRENT:6.0A

87 97

IN

87 97

IN

EDP Current: 7.8A Rsense(R8380)=0.002 Ohm

GPUFB_CS_P

74 96

GPUFB_CS_N

74 96

PCH VCORE CURRENT SENSE

PCHVCCIOS0_CS_N

PCHVCCIOS0_CS_P

TBT (T29) CURRENT SENSE

=PP3V3_S0_ISNS

8

45 98 99

RD251

931

1 2

1%

1/20W

MF

201

RD252

931

1%

1/20W

MF

201

ISNS_TBT_R_P

ISNS_TBT_R_N

1

RD253

1M

1% 1/20W MF 201

2

1

3

RD254

1M

1 2

1%

1/20W

MF

201

5

+

V+

V-

-

2

GPU FB (1.35V/1.5V) CURRENT SENSE

=PP5V_S3_ISNS

8

99

RD281

7.68K

1 2

1% 1/16W MF-LF

402

RD282

7.68K

1 2

1% 1/16W MF-LF

402

SENSOR_NONPROD:Y

5

IN-

4

ISNS_PP1V5_S0GPU_R_P

96

ISNS_PP1V5_S0GPU_R_N

96

1

RD283

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

3 V+

UD220

INA210

SC70

CRITICAL

GND

2

Gain:200x

OUT

3

2

THRM

9

RD284

1M

1 2

1%

SIGNAL_MODEL=EMPTY

1/16W MF-LF

402

CD221

1

0.1UF

20% 10V CERM

2

402

6

PCH_CORE_IOUT

1

REFIN+

UD250

OPA333DCKG4

SC70-5

4

UD280

OPA2333

8

DFN

V+

1

V-

4

SENSOR_NONPROD:Y

1

CD251

0.1UF

20% 10V

2

CERM 402

ISNS_TBT_IOUT

GAIN: 1074.11X

1

CD282

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U4900.H2:5MM

P1V5_S0GPU_IOUT

Gain: 130x

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.A7:5mm

PLACE_NEAR=UD4900.A8:5MM

RD285

4.53K

1 2

1% 1/16W MF-LF

402

RD223

4.53K

1 2

1% 1/16W MF-LF

402

RD255

4.53K

1 2

1% 1/16W MF-LF

402

PLACE_NEAR=U4900.A8:5MM

SMC_GPU_P1V35_ISENSE

1

CD281

0.22UF

20%

6.3V

PLACE_NEAR=U4900.H2:5MM

2

X5R 402

GND_SMC_AVSS

SMC_PCH_CORE_ISENSE

SENSOR_NONPROD:Y

CD222

1

0.22UF

20%

6.3V

PLACE_NEAR=U4900.A7:5MM

X5R

2

402

GND_SMC_AVSS

IHSC

SMC_ADC23

SMC_TBT_ISENSE

1

CD250

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

IG3C

SMC_ADC19

42

41 42 45 46 99

ISBC

SMC_ADC21

41 42 45 46 99

D

42

41 42 45 46 99

C

B

42

LCD BKLT Voltage Sense

CPU VCCSA VOLTAGE SENSE

PLACE_NEAR=R7140.1:2MM

XWD245

SM

12

=PPVCCSA_S0_REG

8

A

62

VCCSA_VSENSE_IN

RD214

4.53K

1 2

1/16W MF-LF

402

PLACE_NEAR=U4900.7:5MM

1%

1

CD211

0.22UF

PLACE_NEAR=U4900.B7:5MM

20%

6.3V

2

X5R 402

SMC_CPU_SA_VSENSE

VC2C

SMC_ADC20

42

PPVOUT_S0_LCDBKLT

7

81 86

6 3

XWD250

SM

1 2

VOUT_S0_LCDBKLT_XW

1

RD256

100K

1% 1/16W MF-LF 402

2

VOUT_S0_LCDBKLT_DIV

1

RD257

4.64K

1% 1/16W MF-LF 402

2

PLACE_NEAR=U4900.G2:5MM

RD258

4.53K

1 2

1% 1/16W MF-LF

402

VBLC

SMC_ADC16

SMC_LCDBKLT_VSENSE

1

CD252

0.22UF

PLACE_NEAR=U4900.G2:5MM

20%

6.3V

2

X5R 402

GND_SMC_AVSS

42

41 42 45 46 99

SYNC_MASTER=D2_KEPLER

PAGE TITLE

SMC12 SENSORS EXTENDED

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

132 OF 132

SHEET

99 OF 99

124578

SIZE

A

D

Apple A1398 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual