Apple A1398 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D

C

B

7

SCHEM,MLB,X425

08/06/2014 PROTO1A

Sync

Date

MASTER

05/30/2014

10/31/2012

10/31/2012

02/18/2014

12/18/2012

12/18/2012

12/18/2012

12/18/2012

12/18/2012

12/18/2012

12/18/2012

12/18/2012

02/18/2014

12/18/2012

12/18/2012

12/18/2012

10/31/2012

12/18/2012

01/14/2013

07/01/2014

01/14/2014

10/31/2012

10/31/2012

10/31/2012

10/31/2012

10/31/2012

01/14/2013

01/14/2013

06/24/2014

06/24/2014

06/24/2014

11/16/2012

01/15/2014

02/18/2014

06/24/2014

06/24/2014

10/31/2012

02/18/2014

05/30/2014

01/15/2014

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

Page Page

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

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15

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17

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18

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19

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20

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23

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25

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26

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27

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28

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30

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31

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32

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33

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34

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35

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36

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41

TABLE_TABLEOFCONTENTS_ITEM

1

Table of Contents

2

BOM Configuration

3

BOM Configuration

4

PD Parts

5

CPU DMI/PEG/FDI/RSVD

6

CPU Clock/Misc/JTAG/CFG

7

CPU DDR3 Interfaces

8

CPU Power

9

CPU Ground

10

CPU Decoupling

11

PCH RTC/HDA/JTAG/SATA/CLK

12

PCH DMI/FDI/PM/GFX/PCI

13

PCH PCI-E/USB

14

PCH GPIO/MISC/NCTF

15

PCH Power

16

PCH Grounds

17

PCH DECOUPLING

18

CPU & PCH XDP

19

Chipset Support

20

Project Chipset Support

21

CPU Memory S3 Support

22

DDR3 VREF MARGINING

23

DDR3 SDRAM Bank A (1 OF 2)

24

DDR3 SDRAM Bank A (2 OF 2)

25

DDR3 SDRAM Bank B (1 OF 2)

26

DDR3 SDRAM Bank B (2 OF 2)

27

DDR3 Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

Thunderbolt Mobile Support

32

Thunderbolt Connector A

33

Thunderbolt Connector B

34

DDC Crossbar

35

X87 CONNECTOR

37

SSD Connector

39

Camera 1 of 2

40

Camera 2 of 2

46

USB 3.0 CONNECTORS

48

KEYBOARD/TRACKPAD (1 OF 2)

49

KEYBOARD/TRACKPAD (2 OF 2)

50

SMC

Contents

MASTER

CLEAN_X305

J15_MLB

J15_MLB

CLEAN_X305_PEG

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

CLEAN_X305_PEG

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

J15_MLB

J15_REFERENCE

J15_REFERENCE

CLEAN_X305G

CLEAN_X305

J15_MLB

J15_MLB

J15_MLB

J15_MLB

J15_MLB

T29_RR

T29_RR

CLEAN_X305

CLEAN_X305

CLEAN_X305

J15_REFERENCE

CLEAN_X305

CLEAN_X305_PEG

CLEAN_X305

CLEAN_X305

J15_MLB

CLEAN_X305_PEG

CLEAN_X305

CLEAN_X305

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

(.csa)

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

High Side Voltage and Current Sensing

55

Load Side Voltage and Current Sensing

56

Debug Sensors

58

Thermal Sensors

60

Fan Connectors

61

SPI Debug Connector

62

AUDIO:CODEC, ANALOG

63

AUDIO:CODEC, DIGITAL

64

AUDIO: SPEAKER AMP

65

AUDIO: JACK

66

AUDIO: JACK TRANSLATORS

70

DC-In & Battery Connectors

71

PBus Supply & Battery Charger

72

CPU VR12.5 VCC Regulator IC

73

CPU VR12.5 VCC Power Stage

74

1.35V DDR3L SUPPLY

75

5V / 3.3V Power Supply

76

1V05V POWER SUPPLY

77

LCD/KBD Backlight Driver

78

Misc Power Supplies

79

X249 Boost Power Supply

80

Power FETs

81

Power Control 1/ENABLE

83

eDP Display Connector

95

RIO Connectors

100

Power Aliases

102

Signal Aliases

104

Functional Test Points

105

NC & No Test

110

PCB Rule Definitions

111

CPU Constraints

112

PCH Constraints 1

113

PCH Constraints 2

114

Memory Constraints

115

Thunderbolt Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

Contents

3456

REV ECN

DESCRIPTION OF REVISION

12

CK
APPD

DATE

<ECODATE>

D

C

B

Sync

CLEAN_X305

CLEAN_X305

CHANG_J45

CLEAN_X305_PEG

CLEAN_X305_PEG

CLEAN_X305

CHANG_J45

J15_MLB

CLEAN_X305_PEG

JOE_J45

JOE_J45

JOE_J45

CLEAN_X305

CLEAN_X305

CLEAN_X305_PEG

CLEAN_X305

CLEAN_X305_PEG

J15_MLB

CLEAN_X305

CLEAN_X305_PEG

CLEAN_X305_PEG

CLEAN_X305_PEG

CLEAN_X305

CLEAN_X305

CLEAN_X305_PEG

CLEAN_X305

CLEAN_X305_PEG

CLEAN_X305G

CLEAN_X305

J15_MLB

J15_MLB

J15_MLB

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

SIDLE_J45

SIDLE_J45

SIDLE_J45

SIDLE_J45

Date

06/24/2014

05/30/2014

11/26/2012

02/18/2014

02/18/2014

01/14/2014

11/26/2012

10/31/2012

02/18/2014

07/30/2013

07/30/2013

07/30/2013

06/24/2014

06/24/2014

02/18/2014

01/15/2014

02/24/2014

10/31/2012

01/15/2014

02/18/2014

02/18/2014

02/19/2014

01/15/2014

05/30/2014

02/18/2014

05/30/2014

02/18/2014

01/14/2014

05/30/2014

10/31/2012

10/31/2012

10/31/2012

12/10/2012

02/18/2014

12/10/2012

02/18/2014

12/10/2012

12/10/2012

12/10/2012

12/10/2012

12/10/2012

<ECN><REV>

<ECO_DESCRIPTION>

A

ALIASES RESOLVED

Schematic / PCB #’s

PART NUMBER

051-00330

820-00138

DRAWING

TITLE=MLB
ABBREV=ABBREV

LAST_MODIFIED=Wed Aug 6 13:00:04 2014

QTY

8 7 6 5 4 2 1

DESCRIPTION

SCHEM,MLB,X305

PCBF,MLB,X305

REFERENCE DES

SCH1

PCB1

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

w w w . c h i n a f i x . c o m

DRAWING TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

3

<PART_DESCRIPTION>

Apple Inc.

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

1 OF 118

SHEET

1 OF 82

SIZE

A

D

8 7 6 5 4 3

BOM Variants

BOM NUMBER

685-00039
985-00043
639-00534
639-00535

BOM NAME

COMMON PARTS,MLB,X425

DEV,MLB,X425
PCBA,MLB,CTO,16G-HYN,X425
PCBA,MLB,CTO,16G-MIC,X425

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:HYNIX_1866

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1866

BOM OPTIONS
X425_COMMON

X425_DEVEL:ENG

D

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

X425 BOM Groups

BOM GROUP

X425_COMMON
X425_COMMON1
X425_COMMON2

X425_PVT
X425_PROGPARTS
X425_DEVEL:ENG
X425_DEVEL:DVT
X425_DEVEL:PVT

XDP_DEBUG

BOM OPTIONS

ALTERNATE,COMMON,X425_COMMON1,X425_COMMON2,X425_PROGPARTS

CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CPUPEG:X8X8,S2_PWR:S0,SMC_SUSACK:YES

EDP:YES,XDP,SSD_PWR_EN:GPIO,CAM_WAKE:NO,SAMCONN,APCLKRQ:ISOL,DDRREG_PGD:N,CRW_SPRT,WLAN_SW:SIL

BKLT:PROD,SENSOR_NONPROD:N

SMC_PROG:BASE,BOOTROM_PROG:PROTO1A,TBTROM:PROG

ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,SENSOR_NONPROD:Y,SENSOR_NONPROD_R,BKLT:ENG,DBGLED,X249:BOOST

ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,DBGLED

XDP_DEBUG

XDP_CONN,XDP_PCH

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

12

D

Module Parts

PART NUMBER

337S00057
337S00058
337S00059

337S4542

QTY

1
1
1
1
1

1
333S0700
333S0802
333S0719

C

333S0802 CRITICAL
333S0719 CRITICAL

1

16
16
32
32

DESCRIPTION

CRW,SR1ZW,PRQ,C0,2.2,47W,4+3E,1.2,6M,BGA

CRW,SR1ZX,PRQ,C0,2.5,47W,4+3E,1.2,6M,BGA

CRW,SR1ZY,PRQ,C0,2.8,47W,4+3E,1.2,6M,BGA

IC,QEWV,LPT-M,HM87,C2,SR199,PRQ,FCBGA

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA

IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA

IC,SDRAM,25NM,512MX8,DDR3L-1866,78B FBGA

IC,SDRAM,4GBIT,DDR3-1866,V80A,78B,FBGA

IC,SDRAM,25NM,512MX8,DDR3L-1866,78B FBGA

IC,SDRAM,4GBIT,DDR3-1866,V80A,78B,FBGA

REFERENCE DES

U0500
U0500
U0500
U1100
U2800
U3900
U4000

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL338S1247
CRITICAL338S1264
CRITICAL
CRITICAL
CRITICAL

BOM OPTION

CPU_CRW:BETTER

CPU_CRW:BEST

CPU_CRW:CTO

HYNIX_1866_S

MICRON_1866_S

HYNIX_1866

MICRON_1866

C

B

DRAM SPD Straps

BOM GROUP

RAM:HYNIX_1866_S

RAM:MICRON_1866_S

RAM:HYNIX_1866

RAM:MICRON_1866

BOM OPTIONS

HYNIX_1866_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

MICRON_1866_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

HYNIX_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

MICRON_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

B

w w w . c h i n a f i x . c o m

COMMON/DEVEL BOM

A

PART NUMBER

685-00039
985-00043

QTY

1

1

DESCRIPTION

COMMON PARTS,MLB,X425

DEV,MLB,X425

6 3

REFERENCE DES

BASE

DEVEL

CRITICAL

CRITICAL
CRITICAL

BOM OPTION

BASE_BOM

DEVEL_BOM

SYNC_MASTER=CLEAN_X305

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

2 OF 118

SHEET

2 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

Programmables - All builds

335S0915

341S00133

IC,SERIAL SPI FLASH ROM,4MBIT,50MHZ,USON

1

T29,FALCON RIDGE(VXXXX)PROTO 1A,X425

1

U2890
U2890

CRITICAL
CRITICAL

12

TBTROM:BLANK

TBTROM:PROG

D

C

SMC

338S1214

341S00125

EFI ROM

335S00007
335S00006
341S00131

IC,SMC-B1,40MHZ/50DMIPS,SCPL FW,157BGA

1

IC,SMC-B1,EXT (V2.24A31) PROTO 1A,X425

1

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

1

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

1

IC,EFI ROM (VXXXX) PROTO 1A,X425

1

U5000
U5000

U6100
U6100
U6100

CRITICAL
CRITICAL

CRITICAL
CRITICAL
CRITICAL

SMC_PROG:BLANK

SMC_PROG:BASE

BOOTROM_BLANK:WIN

BOOTROM_BLANK:MAC

BOOTROM_PROG:PROTO1A

Alternate Parts

PART NUMBER

376S1053 376S0604
128S0311 128S0329
138S0739 138S0706

197S0478
371S0713 371S0558

155S0667
376S1217 376S0855

376S1089

138S0803

138S0732 138S0715
128S0364 128S0264

311S0649 311S0541
376S00014
740S00003
377S0155
377S0184

ALTERNATE FOR
PART NUMBER

197S0480197S0481
197S0479

152S1645152S0461
376S0820376S1080
155S00008

376S0855376S1129
376S1128
128S0376128S0371
138S0639
138S0674138S0843
138S0811138S0846
127S0162127S0164

333S0700333S0704

376S0761
740S0135
377S00011
377S00011

BOM OPTION

REF DES

ALL
ALL
ALL
ALL
ALL

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

COMMENTS:

Diodes alt to Fairchild

NEC alt to Sanyo

Samsung alt to Murata

Epson Alt to NDK

NDK Alt to Epson
DDS alt to STALL

Cyntec alt to Vishay

Diodes alt to On Semi

Panasonic alt to TDK

Toshiba alt to Diodes

NXP alt to Diodes

NXP alt to Diodes

Kemet alt to Sanyo

Samsung alt to Murata

Samsung alt to Murata

Samsung alt to Murata

Rohm alt to Vishay

Rohm alt to Vishay

Kemet alt to Sanyo

ELPIDA to HYNIX

ON alt to Toshiba

Toshiba alt to Vishay

AEM alt to Tyco

On Semi alt to Infineon

Infineon alt to Infineon

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

D

C

B

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=J15_MLB

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

3 OF 118

SHEET

3 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

ZT0415

2.8R2.3

ZT0450

TH-NSP

SL-2.3X3.9-2.9X4.5

D

|
|
|
|
|
|
|
|
|
|
|
|

-----------------------

SH0427

5.0OD1.85ID-2.35H-SM

1

SH0429

5.0OD1.85ID-2.35H-SM

1

C

1

GND

1

GND

MAKE_BASE=TRUE

X425 THERMAL MODULE STANDOFF

860-00173

Frame Holes

SH0426

5.0OD1.85ID-2.35H-SM

1

SH0428

5.0OD1.85ID-2.35H-SM

1

-----------------------

GND

GND

GND

GND

ZT0470

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0471

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0472

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0473

TH-NSP

1

SL-1.1X0.45-1.4x0.75

860-00184

|
|
|
|
|
|
|
|
|
|
|
|

OMIT_TABLE

SH0425

STDOFF-4.5OD1.8H-SM

1

OMIT_TABLE

SH0423

STDOFF-4.5OD1.8H-SM

1

-----------------------

|
|
|
|
|
|
|
|
|
|
|
|

-----------------------

860-00167

SH0424

4.5OD1.9H-SM-X304

1

|
|
|
|
|
|
|
|
|
|
|
|

PART NUMBER

860-00184

QTY

2

DESCRIPTION

STANDOFF,THERMAL/FAN,W/O MYLAR,X305

REFERENCE DES

SH0423,SH0425

CRITICAL

CRITICAL

BOM OPTION

D

C

5.0OD2.9ID-2.38H

806-9391

1

SH0450

SM

SHLD-MLB-USB-J45

B

POGO-2.3OD-5.5H-SM-LOW-FORCE

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0431

1

SH0434

1

817-00335

SH0446

1

SM

SM

817-00336

5.0OD2.9ID-2.38H-FD2

806-00452

1

SH0451

SM

SHLD-FENCE-MLB-T29-X305

X425 POGO PINS

POGO-2.3OD-5.5H-SM-LOW-FORCE

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0432

1

SH0435

1

SH0445

1

SM

SM

APN 806-2247

BR0401

MLB-MTG-BRKT-J5

TH

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0433

SM

1

w w w . c h i n a f i x . c o m

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0437

SM

1

X425 StAND OFF

860-1448

PART NUMBER

946-3819

QTY

1

DESCRIPTION

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

SMT GND TEST PONTS

ZT0490

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

ZT0491

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

REFERENCE DES

EDGE_BOND

ZT0492

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

CRITICAL

CRITICAL

BOM OPTION

RIO FLEX BRACKET BOSS (860-00166)

SH0480

3.5OD1.85ID-2.0H

1

SH0481

3.5OD1.85ID-2.0H

1

B

SH0440

2.9OD1.2ID-1.35H-SM

A

1

2

SH0441

2.9OD1.2ID-1.35H-SM

1

2

SH0443

2.9OD1.2ID-1.35H-SM

1

2

SH0444

2.9OD1.2ID-1.35H-SM

1

2

SH0460

2.9OD1.2ID-1.35H-SM

1

2

SH0461

2.9OD1.2ID-1.35H-SM

1

2

SH0462

2.9OD1.2ID-1.35H-SM

1

2

SH0465

2.9OD1.2ID-1.35H-SM

1

2

SH0466

2.9OD1.2ID-1.35H-SM

1

2

SH0467

2.9OD1.2ID-1.35H-SM

1

2

SH0470

2.9OD1.2ID-1.35H-SM

1

2

SH0471

2.9OD1.2ID-1.35H-SM

1

2

SH0472

2.9OD1.2ID-1.35H-SM

1

2

SH0473

2.9OD1.2ID-1.35H-SM

1

2

2.9OD1.2ID-1.35H-SM

6 3

SH0474

1

2

SYNC_MASTER=J15_MLB

PAGE TITLE

PD Parts

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

4 OF 118

SHEET

4 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

PPVCOMP_S0_CPU

OMIT_TABLE

U0500

HASWELL

BGA

DMI_S2N_N<0>

12 75

IN

DMI_S2N_N<1>

12 73 75

IN

DMI_S2N_N<2>

12 73 75

IN

DMI_S2N_N<3>

12 73 75

IN

DMI_S2N_P<0>

12 75

D

IN

12 73 75

IN

12 73 75

IN

12 73 75

IN

12 75

OUT

12 73 75

OUT

12 73 75

OUT

12 73 75

OUT

12 75

OUT

12 73 75

OUT

12 73 75

OUT

12 73 75

OUT

12 75

IN

12 75

IN

DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

FDI_CSYNC

FDI_INT

AB2
AB3
AC3
AC1

AB1
AB4
AC4
AC2

AF2
AF4
AG4
AG2

AF1
AF3
AG3
AG1

F11

F12

DMI_RX0*
DMI_RX1*
DMI_RX2*
DMI_RX3*

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

DMI_TX0*
DMI_TX1*
DMI_TX2*
DMI_TX3*

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

FDI_CSYNC

DISP_INT

C

B

SYM 1 OF 12

PEG_RCOMP

PEG_RX0*
PEG_RX1*
PEG_RX2*
PEG_RX3*
PEG_RX4*
PEG_RX5*
PEG_RX6*
PEG_RX7*

DMI

PEG_RX8*

PEG_RX9*
PEG_RX10*
PEG_RX11*
PEG_RX12*
PEG_RX13*
PEG_RX14*
PEG_RX15*

PEG_RX0
PEG_RX1

FDI

PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8

PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

PEG_TX0*
PEG_TX1*
PEG_TX2*
PEG_TX3*
PEG_TX4*
PEG_TX5*
PEG_TX6*
PEG_TX7*
PEG_TX8*

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TX9*

PEG_TX10*
PEG_TX11*
PEG_TX12*
PEG_TX13*
PEG_TX14*
PEG_TX15*

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

AH6

E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2

F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1

B6
C5
E6
D4
G4
E3
J5
G3
J3
J2
T6
R6
R2
R4
T4
T1

C6
B5
D6
E4
G5
E2
J6
G2
J4
J1
T5
R5
R1
R3
T3
T2

CPU_PEG_RCOMP

75

PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_N<1>
PCIE_TBT_D2R_N<2>
PCIE_TBT_D2R_N<3>
TP_PEG_D2RN<12>
TP_PEG_D2RN<13>
TP_PEG_D2RN<14>
TP_PEG_D2RN<15>

PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_P<2>
PCIE_SSD_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_P<1>
PCIE_TBT_D2R_P<2>
PCIE_TBT_D2R_P<3>
TP_PEG_D2RP<12>
TP_PEG_D2RP<13>
TP_PEG_D2RP<14>
TP_PEG_D2RP<15>

PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
PCIE_TBT_R2D_C_N<0>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_R2D_C_N<3>
TP_PEG_R2D_CN<12>
TP_PEG_R2D_CN<13>
TP_PEG_R2D_CN<14>
TP_PEG_R2D_CN<15>

PCIE_SSD_R2D_C_P<0>
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_R2D_C_P<2>
PCIE_SSD_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
PCIE_TBT_R2D_C_P<0>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_C_P<3>
TP_PEG_R2D_CP<12>
TP_PEG_R2D_CP<13>
TP_PEG_R2D_CP<14>
TP_PEG_R2D_CP<15>

1

R0510

24.9

1%
1/16W
MF-LF
402

2

35 71 75

IN

35 71 75

IN

35 71 75

IN

35 71 75

IN

71

IN

71

IN

71

IN

71

IN

28 71 75

IN

28 71 75

IN

28 71 75

IN

28 71 75

IN

71

IN

71

IN

71

IN

71

IN

35 71 75

IN

35 71 75

IN

35 71 75

IN

35 71 75

IN

71

IN

71

IN

71

IN

71

IN

28 71 75

IN

28 71 75

IN

28 71 75

IN

28 71 75

IN

71

IN

71

IN

71

IN

71

IN

35 71 75

OUT

35 71 75

OUT

35 71 75

OUT

35 71 75

OUT

71

OUT

71

OUT

71

OUT

71

OUT

28 71 75

OUT

28 71 75

OUT

28 71 75

OUT

28 71 75

OUT

71

OUT

71

OUT

71

OUT

71

OUT

35 71 75

OUT

35 71 75

OUT

35 71 75

OUT

35 71 75

OUT

71

OUT

71

OUT

71

OUT

71

OUT

28 71 75

OUT

28 71 75

OUT

28 71 75

OUT

28 71 75

OUT

71

OUT

71

OUT

71

OUT

71

OUT

5 8

OMIT_TABLE

U0500

HASWELL

BGA

DP_TBTSNK0_ML_C_N<0>

28 71 75

DP_TBTSNK0_ML_C_P<0>

28 71 75

DP_TBTSNK0_ML_C_N<1>

28 71 75

DP_TBTSNK0_ML_C_P<1>

28 71 75

DP_TBTSNK0_ML_C_N<2>

28 71 75

DP_TBTSNK0_ML_C_P<2>

28 71 75

DP_TBTSNK0_ML_C_N<3>

28 71 75

DP_TBTSNK0_ML_C_P<3>

28 71 75

DP_TBTSNK1_ML_C_N<0>

28 71 75

DP_TBTSNK1_ML_C_P<0>

28 71 75

DP_TBTSNK1_ML_C_N<1>

28 71 75

DP_TBTSNK1_ML_C_P<1>

28 71 75

DP_TBTSNK1_ML_C_N<2>

28 71 75

DP_TBTSNK1_ML_C_P<2>

28 71 75

DP_TBTSNK1_ML_C_N<3>

28 71 75

DP_TBTSNK1_ML_C_P<3>

28 71 75

TP_DP_IG_D_MLN<2>

71

TP_DP_IG_D_MLP<2>

71

HDMI_CLK_N

69 71 72 75

HDMI_CLK_P

69 71 72 75

TP_DP_IG_D_MLN<0>

71

TP_DP_IG_D_MLP<0>

71

TP_DP_IG_D_MLN<1>

71

TP_DP_IG_D_MLP<1>

71

Port D pins out of order
to match Intel symbol.

C25
D25
A25
B25
C24
D24
A24
B24

C21
D21
A21
B21
C20
D20
A20
B20

C16
D16
A16
B16

C17
D17
A17
B17

DDIB_TXN0
DDIB_TXP0
DDIB_TXN1
DDIB_TXP1
DDIB_TXN2
DDIB_TXP2
DDIB_TXN3
DDIB_TXP3

DDIC_TXN0
DDIC_TXP0
DDIC_TXN1
DDIC_TXP1
DDIC_TXN2
DDIC_TXP2
DDIC_TXN3
DDIC_TXP3

DDID_TXN2
DDID_TXP2
DDID_TXN3
DDID_TXP3

DDID_TXN0
DDID_TXP0
DDID_TXN1
DDID_TXP1

SYM 10 OF 12

EDP_AUXN
EDP_AUXP

EDP_HPD

EDP_TXN0

EDP

EDP_TXN1

EDP_TXP0
EDP_TXP1

EDP_RCOMP

EDP_DISP_UTIL

DIGITAL DISPLAY INTERFACES

FDI_TXN0
FDI_TXP0

FDI

FDI_TXN1
FDI_TXP1

F15
F14
E14

C14
A12

D14
B12

AG6
E12

C12
D12
A14
B14

OMIT_TABLE

U0500

HASWELL

TP0500
TP0510

TP0520
TP0530

TP0521

TP

TP-P6

TP

TP-P6

TP

TP-P6

TP

TP-P6

TP

TP-P6

BGA

CPU_DC_A3_B3

5

CPU_DC_A4

1

CPU_DC_A51

1

CPU_DC_A52_B52

5

CPU_DC_A53_B53

5

CPU_DC_B2_C3

5

CPU_DC_A3_B3

5 5

CPU_DC_A52_B52

5

CPU_DC_A53_B53

5

CPU_DC_B54_C54

5

1

CPU_DC_BC1
CPU_DC_BC54

1

CPU_DC_BD1_BE1

5

CPU_DC_BD54_BE54

5

CPU_DC_BD1_BE1

5

CPU_DC_BE2_BF2

5

CPU_DC_BE3_BF3

5

CPU_DC_BE52_BF52

5

CPU_DC_BE53_BF53

5

CPU_DC_BD54_BE54

5

CPU_DC_BE2_BF2

5

CPU_DC_BE3_BF3

5

CPU_DC_BF4

1

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE

TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

A51
A52
A53

B52
B53
B54

BC1

BC54

BD1

BD54

BE1
BE2

BE3
BE52
BE53
BE54

BF2

BF3

BF4

A3
A4

B2
B3

SYM 12 OF 12

RESERVED

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

RSVD132
RSVD133
RSVD134
RSVD135
RSVD136
RSVD137
RSVD138
RSVD139

NO_TESTNO_TEST

BF51
BF52
BF53

C1
C2
C3

C54
D1

D54

CPU Daisy-Chain Strategy:

Each corner of CPU has two testpoints.
Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP’s on each corner.

AN35
AN37
AF9
AE9
G14
G17
AD45
AG45

PPVCCIO_S0_CPU

1

R0531

10k

5%
1/16W
MF-LF
402

2

DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P
DP_IG_A_HPD_L

DP_INT_ML_C_N<0>
DP_INT_ML_C_N<1>

DP_INT_ML_C_P<0>
DP_INT_ML_C_P<1>

CPU_EDP_RCOMP

75

TP_EDP_DISP_UTIL

DP_INT_ML_C_N<2>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<3>
DP_INT_ML_C_P<3>

CPU_DC_BF51
CPU_DC_BE52_BF52

TRUE

CPU_DC_BE53_BF53

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_B54_C54

TRUE

CPU_DC_D1

CPU_DC_D54

NC
NC
NC
NC
NC
NC
NC
NC

6 8

10 18 58

68 71 75

68 71 75

20

68 71 75

68 71 75

68 71 75

68 71 75

PPVCOMP_S0_CPU

1

R0530

24.9

1%
1/16W
MF-LF
402

2

68 71 75

68 71 75

68 71 75

68 71 75

5

5

5

5

5

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

D

5 8

C

TP0531

TP0501
TP0511

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=CLEAN_X305_PEG

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=02/18/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

5 OF 118

SHEET

5 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

OMIT_TABLE

D

PPVCCIO_S0_CPU

5 8

10 18 58

1

R0601

62

5%
1/16W
MF-LF

402

2

R0603

56

1%
1/16W
MF-LF

402

3.32K

1/16W
MF-LF

2 1

5%
1/16W
MF-LF

402

1

2

1

1%

402

2

CPU_PROCHOT_L

41 42 58 75

BI

PP1V35_S3RS0_CPUDDR

8

10 21 66 67 70 82

R0620

PLACE_NEAR=R0621.2:1mm

PM_MEM_PWRGD

12 21 75

IN

PLACE_NEAR=U0500.AP48:51.562mm

1.82K

R0621

C

CPU_CATERR_L

41 75

OUT

CPU_PECI

14 42 75

BI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

14 42 75

OUT

PM_SYNC

12 75

IN

CPU_PWRGD

14 18 75

IN

CPU_RESET_L

14

IN

CPU_CLK135M_DPLLREF_N

11 75

IN

CPU_CLK135M_DPLLREF_P

11 75

IN

CPU_CLK135M_DPLLSS_N

11 75

IN

CPU_CLK135M_DPLLSS_P

11 75

IN

DMI_CLK100M_CPU_N

11 75

IN

DMI_CLK100M_CPU_P

11 75

IN

PLACE_NEAR=U0500.F50:157mm

R0611

10K

1/16W
MF-LF

1

5%

402

2

C51

NC

PROC_DETECT*

G50

CATERR*

G51

PECI

E50

PROCHOT*

D53

THERMTRIP*

D52

PM_SYNC

F50

PWRGOOD

AP48

SM_DRAMPWROK

L54

PLTRSTIN*

AC6

DPLL_REF_CLKN

AE6

DPLL_REF_CLKP

V6

SSC_DPLL_REF_CLKN

Y6

SSC_DPLL_REF_CLKP

AB6

BCLKN

AA6

BCLKP

U0500

HASWELL

BGA

SYM 2 OF 12

THERMAL

PWR

CLOCK

DDR3

JTAG

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SM_DRAMRST*

(IPU)

PRDY*

(IPU)

PREQ*

(IPD)
(IPU)
(IPU)

TRST*

(IPU)

DBR*

(IPU)

BPM0*

(IPU)

BPM1*

(IPU)

BPM2*

(IPU)

BPM3*

(IPU)

BPM4*

(IPU)

BPM5*
BPM6*

(IPU)

BPM7*

(IPU)

TCK
TMS

TDI
TDO

BB51
BB53
BB52

BE51

N53
N52

N54
M51
M53

N49
M49

F53

R51
R50
P49
N50
R49
P53
U51
P51

CPU_SM_RCOMP<0>

75

CPU_SM_RCOMP<1>

75

75

CPU_SM_RCOMP<2>
CPU_MEM_RESET_L

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPUPCH_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

PLACE_NEAR=U0500.BB52:12.7mm

21

OUT

18 72 75

OUT

18 72 75

IN

18 72 75

IN

18 72 75

IN

18 72 75

IN

18 72 75

IN

18 72 75

OUT

18 19 75

OUT

18 75

BI

18 75

BI

18 75

BI

18 75

BI

18 75

BI

18 75

BI

18 75

BI

18 75

BI

PLACE_NEAR=U0500.BB53:12.7mm

PLACE_NEAR=U0500.BB51:12.7mm

1

R0614

100

1%
1/16W
MF-LF
402

2

1

R0613

75

1%
1/16W
MF-LF
402

2

1

R0612

100

1%
1/16W
MF-LF
402

2

D

C

B

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

These can be placed close to

J1800 and only for debug access

NOSTUFF

R0649

1/16W
MF-LF

NOSTUFF

1

1K

5%

402

R0648

1/16W

2

MF-LF

NOSTUFF

1

1

R0643

1K

1K

5%

5%

1/16W
MF-LF
402

402

2

2

NOSTUFF

R0641

1/16W
MF-LF

A

NOSTUFF

R0647

1/16W
MF-LF

1

1K

5%

402

2

CPUCFG6_PD

R0646

1/16W
MF-LF

1K

402

5%

1

2

CPUCFG5_PD

1

R0645

1K

5%
1/16W
MF-LF
402

2

EDP:YES

R0644

1/16W
MF-LF

1K

5%

402

1K

5%

402

1

2

1

2

CPU_CFG<16>
CPU_CFG<9>
CPU_CFG<3>
CPU_CFG<1>
CPU_CFG<0>

NOSTUFF

1

R0640

1K

5%
1/16W
MF-LF
402

2

CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<2>

NOSTUFF

1

R0642

1K

5%
1/16W
MF-LF
402

2

6

18 75

6

18 75

6

18 72 75

6

18 75

6

18 75

6

18 75

6

18 75

6

18 75

6

18 75

6

18 75

BOM GROUP

CPUPEG:X8X8

CPUPEG:X8X4X4

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

OMIT_TABLE

U0500

HASWELL

BGA

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

SYM 11 OF 12

RESERVED

CFG_RCOMP

(IPU)

(IPU)

RSVD_TP17
RSVD_TP18

TP_CPU_RSVD_TP23
TP_CPU_RSVD_TP24

TP_CPU_RSVD_TP25
TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP27
TP_CPU_RSVD_TP28
CPU_TESTLO_F21

1

R0680

49.9

1/16W
MF-LF

1%

402

2

PPVCC_S0_CPU

8

10 46 59 70 72

TP_CPU_RSVD_TP35
TP_CPU_RSVD_TP36

TP_CPU_RSVD_TP37
TP_CPU_RSVD_TP38

TP_CPU_RSVD_TP39
CPU_TESTLO_F20

1

R0685

49.9

1%
1/16W
MF-LF

402

2

w w w . c h i n a f i x . c o m

CPU_CFG<0>

6

18 75

CPU_CFG<1>

6

18 75

CPU_CFG<2>

6

18 75

CPU_CFG<3>

6

18 72 75

CPU_CFG<4>

6

18 75

CPU_CFG<5>

6

18 75

CPU_CFG<6>

6

18 75

CPU_CFG<7>

6

18 75

CPU_CFG<8>

18 75

CPU_CFG<9>

6

18 75

CPU_CFG<10>

18 75

CPU_CFG<11>

18 75

CPU_CFG<12>

18 75

CPU_CFG<13>

18 75

CPU_CFG<14>

18 75

CPU_CFG<15>

18 75

BE4

RSVD_TP23

BD3

RSVD_TP24

F6

RSVD_TP25

G6

RSVD_TP26

G21

RSVD_TP27

G24

RSVD_TP28

F21

TESTLO_F21

G19

VSS_G19

F51

VSS_F51

F52

VSS_F52

F22

VCC_F22

L52

RSVD_TP35

L53

RSVD_TP36

L51

RSVD_TP37

F24

RSVD_TP38

F25

RSVD_TP39

F20

TESTLO_F20

AG49

CFG0

AD49

CFG1

AC49

CFG2

AE49

CFG3

Y50

CFG4

AB49

CFG5

V51

CFG6

W51

CFG7

Y49

CFG8

Y54

CFG9

Y53

CFG10

W53

CFG11

U53

CFG12

V54

CFG13

R53

CFG14

R52

CFG15

L49

RSVD50
RSVD51

E5

RSVD52

NC
NC
NC

BOM OPTIONS

CPUCFG5_PD

CPUCFG6_PD,CPUCFG5_PD

RSVD_TP1
RSVD_TP2
RSVD_TP3
RSVD_TP4

CFG16
CFG18
CFG17
CFG19

RSVD92
RSVD93
RSVD94
RSVD95

RSVD9
RSVD10
RSVD11

RSVD41
RSVD42

RSVD16

VSS_H54
VSS_H53

VSS_H51
VSS_H52

RSVD47
RSVD48
RSVD49

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

F1
E1
A5
A6

R54

Y52
V53
Y51
V52

B50
AH49
AM48
AU27

AU26
BD4
BC4

AL6
F8

F16

G12
G10

H54
H53

H51
H52

N51L50
G53
H50

TP_CPU_RSVD_TP1
TP_CPU_RSVD_TP2
TP_CPU_RSVD_TP3
TP_CPU_RSVD_TP4

CPU_CFG_RCOMP
CPU_CFG<16>

CPU_CFG<18>
CPU_CFG<17>
CPU_CFG<19>

NC
NC
NC
NC

NC
NC
NC

NC
NC

NC

TP_CPU_RSVD_TP17
TP_CPU_RSVD_TP18

TP_CPU_RSVD_TP47
TP_CPU_RSVD_TP48
TP_CPU_RSVD_TP49

6

18 75

18 75

18 75

18 75

1

R0690

49.9

1%
1/16W
MF-LF
402

2

6 3

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

CPU Clock/Misc/JTAG/CFG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

<SCH_NUM>

<E4LABEL>

<BRANCH>
6 OF 118

6 OF 82

SIZE

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

MEM_A_DQ<0>

23 24 78

BI

MEM_A_DQ<1>

23 24 78

BI

MEM_A_DQ<2>

23 24 78

BI

MEM_A_DQ<3>

23 24 78

BI

MEM_A_DQ<4>

23 24 78

BI

MEM_A_DQ<5>

23 24 78

BI

MEM_A_DQ<6>

23 24 78

BI

MEM_A_DQ<7>

23 24 78

BI

MEM_A_DQ<8>

23 24 78

D

C

B

BI

MEM_A_DQ<9>

23 24 78

BI

MEM_A_DQ<10>

23 24 78

BI

MEM_A_DQ<11>

23 24 78

BI

MEM_A_DQ<12>

23 24 78

BI

MEM_A_DQ<13>

23 24 78

BI

MEM_A_DQ<14>

23 24 78

BI

MEM_A_DQ<15>

23 24 78

BI

MEM_A_DQ<16>

23 24 78

BI

MEM_A_DQ<17>

23 24 78

BI

MEM_A_DQ<18>

23 24 78

BI

MEM_A_DQ<19>

23 24 78

BI

MEM_A_DQ<20>

23 24 78

BI

MEM_A_DQ<21>

23 24 78

BI

MEM_A_DQ<22>

23 24 78

BI

MEM_A_DQ<23>

23 24 78

BI

MEM_A_DQ<24>

23 24 78

BI

MEM_A_DQ<25>

23 24 78

BI

MEM_A_DQ<26>

23 24 78

BI

MEM_A_DQ<27>

23 24 78

BI

MEM_A_DQ<28>

23 24 78

BI

MEM_A_DQ<29>

23 24 78

BI

MEM_A_DQ<30>

23 24 78

BI

MEM_A_DQ<31>

23 24 78

BI

MEM_A_DQ<32>

23 24 78

BI

MEM_A_DQ<33>

23 24 78

BI

MEM_A_DQ<34>

23 24 78

BI

MEM_A_DQ<35>

23 24 78

BI

MEM_A_DQ<36>

23 24 78

BI

MEM_A_DQ<37>

23 24 78

BI

MEM_A_DQ<38>

23 24 78

BI

MEM_A_DQ<39>

23 24 78

BI

MEM_A_DQ<40>

23 24 78

BI

MEM_A_DQ<41>

23 24 78

BI

MEM_A_DQ<42>

23 24 78

BI

MEM_A_DQ<43>

23 24 78

BI

MEM_A_DQ<44>

23 24 78

BI

MEM_A_DQ<45>

23 24 78

BI

MEM_A_DQ<46>

23 24 78

BI

MEM_A_DQ<47>

23 24 78

BI

MEM_A_DQ<48>

23 24 78

BI

MEM_A_DQ<49>

23 24 78

BI

MEM_A_DQ<50>

23 24 78

BI

MEM_A_DQ<51>

23 24 78

BI

MEM_A_DQ<52>

23 24 78

BI

MEM_A_DQ<53>

23 24 78

BI

MEM_A_DQ<54>

23 24 78

BI

MEM_A_DQ<55>

23 24 78

BI

MEM_A_DQ<56>

23 24 78

BI

MEM_A_DQ<57>

23 24 78

BI

MEM_A_DQ<58>

23 24 78

BI

MEM_A_DQ<59>

23 24 78

BI

MEM_A_DQ<60>

23 24 78

BI

MEM_A_DQ<61>

23 24 78

BI

MEM_A_DQ<62>

23 24 78

BI

MEM_A_DQ<63>

23 24 78

BI

CPU_DIMM_VREFCA

22

OUT

CPU_DIMMA_VREFDQ

22 75

OUT

CPU_DIMMB_VREFDQ

22 75

OUT

AH54

SA_DQ0

AH52

SA_DQ1

AK51

SA_DQ2

AK54

SA_DQ3

AH53

SA_DQ4

AH51

SA_DQ5

AK52

SA_DQ6

AK53

SA_DQ7

AN54

SA_DQ8

AN52

SA_DQ9

AR51

SA_DQ10

AR53

SA_DQ11

AN53

SA_DQ12

AN51

SA_DQ13

AR52

SA_DQ14

AR54

SA_DQ15

AV52

SA_DQ16

AV53

SA_DQ17

AY52

SA_DQ18

AY51

SA_DQ19

AV51

SA_DQ20

AV54

SA_DQ21

AY54

SA_DQ22

AY53

SA_DQ23

AY47

SA_DQ24

AY49

SA_DQ25

BA47

SA_DQ26

BA45

SA_DQ27

AY45

SA_DQ28

AY43

SA_DQ29

BA49

SA_DQ30

BA43

SA_DQ31

BF14

SA_DQ32

BC14

SA_DQ33

BC11

SA_DQ34

BF11

SA_DQ35

BE14

SA_DQ36

BD14

SA_DQ37

BD11

SA_DQ38

BE11

SA_DQ39

BC9

SA_DQ40

BE9

SA_DQ41

BE6

SA_DQ42

BC6

SA_DQ43

BD9

SA_DQ44

BF9

SA_DQ45

BE5

SA_DQ46

BD6

SA_DQ47

BB4

SA_DQ48

BC2

SA_DQ49

AW3

SA_DQ50

AW2

SA_DQ51

BB3

SA_DQ52

BB2

SA_DQ53

AW4

SA_DQ54

AW1

SA_DQ55

AU3

SA_DQ56

AU1

SA_DQ57

AR1

SA_DQ58

AR4

SA_DQ59

AU2

SA_DQ60

AU4

SA_DQ61

AR2

SA_DQ62

AR3

SA_DQ63

AM6

SM_VREF

AR6

SA_DIMM_VREFDQ

AN6

SB_DIMM_VREFDQ

BC53

NC

RSVD25

U0500

HASWELL

BGA

SYM 3 OF 12

MEMORY CHANNEL A

VSS_BC21

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

RSVD160

SA_CKN0
SA_CKP0
SA_CKE0

SA_CKN1
SA_CKP1
SA_CKE1

SA_CKN2
SA_CKP2
SA_CKE2

SA_CKN3
SA_CKP3
SA_CKE3

SA_CS0*
SA_CS1*
SA_CS2*
SA_CS3*

SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3

SA_BS0
SA_BS1
SA_BS2

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

RSVD161

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
RSVD162

RSVD163
RSVD164
RSVD165
RSVD166
RSVD167
RSVD168
RSVD169
RSVD170

BD31

BE25
BF25
BE34

BD25
BC25
BF34

BE23
BF23
BC34

BD23
BC23
BD34

BE16
BC17
BE17
BD16

BC16
BF16
BF17
BD17

BC20
BD21
BD32

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CKE<0>

MEM_A_CLK_N<1>
MEM_A_CLK_P<1>
MEM_A_CKE<1>

NC
NC
NC

NC
NC
NC

MEM_A_CS_L<0>
MEM_A_CS_L<1>

NC
NC

MEM_A_ODT<0>
MEM_A_ODT<1>

NC
NC

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT

23 27 78

23 27 78

23 27 78

24 27 78

24 27 78

24 27 78

23 27 78

24 27 78

23 27 78

24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

BC21

BF20
BF21
BE21

BD28
BD27
BF28
BE28
BF32
BC27
BF27
BC28
BE27
BC32
BD20
BF31
BC31
BE20
BE32
BE31

AJ52
AP53
AW52
AY46
BD12
BE7
BA3
AT2
AW39

AJ53
AP52
AW53
BA46
BE12
BD7
BA2
AT3
AW40

BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39

MEM_A_RAS_L
MEM_A_WE_L
MEM_A_CAS_L

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

NC

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

NC

NC
NC NC
NC
NC
NC
NC
NC
NC

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

25 26 78

BI

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10

AU8
BA8
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AM1
AM4
AK2
AK3

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13

SB_DQ15

SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

OMIT_TABLE

U0500

HASWELL

BGA

SYM 4 OF 12

MEMORY CHANNEL B

RSVD171

SB_CKN0
SB_CKP0
SB_CKE0

SB_CKN1
SB_CKP1
SB_CKE1

SB_CKN2
SB_CKP2
SB_CKE2

SB_CKN3
SB_CKP3
SB_CKE3SB_DQ14

SB_CS0*SB_DQ16
SB_CS1*SB_DQ17
SB_CS2*SB_DQ18
SB_CS3*SB_DQ19

SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3

SB_BS0
SB_BS1
SB_BS2

VSS_AU30

SB_RAS*

SB_WE*

SB_CAS*

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

RSVD172

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
RSVD173

RSVD174
RSVD175
RSVD176
RSVD177
RSVD178
RSVD179
RSVD180
RSVD181

AY36

AW27
AV27
AU36

AW26
AV26
AU35

BA26
AY26
AV35

BA27
AY27
AV36

BA20
AY19
AU19
AW20

AY20
BA19
AV19
AW19

AY23
BA23
BA36

AU30

AV23
AW23
AV20

BA30
AW30
AY30
AV30
AW32
AY32
AT30
AV32
BA32
AU32
AU23
AY35
AW35
AU20
AW36
BA35

AD52
AU46
BD48
BD43
AW16
AW10
AW8
AL2
BE38

AD53
AV46
BE48
BE43
AW15
AW12
AW6
AL3
BD38

BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37

NCNC

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<0>

MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<1>

NC
NC
NC

NC
NC
NC

MEM_B_CS_L<0>
MEM_B_CS_L<1>

NC
NC

MEM_B_ODT<0>
MEM_B_ODT<1>

NC
NC

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_WE_L
MEM_B_CAS_L

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

NC

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

NC

NC

NC
NC
NC
NC
NC
NC

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

25 27 78

25 27 78

25 27 78

26 27 78

26 27 78

26 27 78

25 27 78

26 27 78

25 27 78

26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

D

C

B

w w w . c h i n a f i x . c o m

A

6 3

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

CPU DDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

<SCH_NUM>

REVISION

<E4LABEL>

<E4LABEL>

BRANCH

<BRANCH>

<BRANCH>

PAGE

7 OF 1187 OF 118

SHEET

7 OF 827 OF 82

124578

SIZE

A

D

D

C

B

A

H37

H36

H34

H33

BGA

U0500

HASWELL

SYM 6 OF 12

OMIT_TABLE

AB8

AC46

AB46

AB45

8 7 6 5 4 3

PP1V35_S3RS0_CPUDDR

6

10 21 66 67 70 82

PPVCC_S0_CPU

6 8

10 46 59 70 72

1

R0860

H38

POWER

AC47

H39

AC8

H40

AC9

H42

AD46

H43

AD8

H45

AE46

H46

AE47

AE8

AF8

H9H8H48

AG46

J10

AG8

J14

AH46

J19

AH47

J24

AH8

J29

AJ45

J33

AJ46

J36

AK46

J37

AK47

J38

AK8

J39

AL45

J40

AL46

J42

AL8

NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.

Max load: 300mA

58 75

IN

58 75

OUT

58 75

BI

K45

K44

K43

K40

K38

J9J8J48

J46

J45

J43

AM9

AM8

AL9

AM46

AM47

AN10

AN12

AN13

AN14

AN15

AN16

PPVCCIO_S0_CPU

5 6

10 18 58

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

L39

L38

L37

K9K8K48

K46

AN25

AN24

AN23

AN21

AN20

AN19

AN17

L40

AN26

L42

AN27

R0800

L44

L43

AN30

AN29

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

CPU_VCCSENSE_P

58 75

OUT

PPVCOMP_S0_CPU

5

1

75

1%
1/16W
MF-LF

402

R0810

2

1/16W

R0811

0

5%

1/16W
MF-LF

402

L47

L46

MF-LF

21

R0812

1/16W
MF-LF

M40

M39

M38

M37

L8

w w w . c h i n a f i x . c o m

AN41

AN40

AN39

AN38

AN36

AN34

AN32

1

R0802

110

1%
1/16W
MF-LF
402

2

43

21

5%

402

0

21

5%

402

M45

M44

M43

M42

VCCVCC

AN8

AN46

AN45

AN44

AN43

AN42

R0802.2:
R0810.2:
R0800.2:

N37

M9M8M46

AN9

AP10

N38

AP12

Max load: 300mA

PLACE_NEAR=U0500.J50:2.54mm
PLACE_NEAR=U0500.J53:38mm
PLACE_NEAR=R0810.1:2.54mm

N46

N44

N43

N42

N40

N39

AP20

AP19

AP18

AP17

AP16

AP15

AP14

AP13

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

P8

P46

P45

N9N8N47

AP24

AP23

AP22

AP21

R46

AP25

AP26

AP27

R9R8R47

AP29

T45

AP30

T46

AP31

U46

AP32

1/16W
MF-LF

U47

AP33

100

U8

AP34

5%

402

2

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

CPU_PWR_DEBUG

18

IN

TP_CPU_RSVD_TP75
TP_CPU_RSVD_TP76
TP_CPU_IVR_ERROR
TP_CPU_RSVD_TP78

Y8

Y46

Y45

W8

W47

W46

V8

V46

V45

U9

AP35

AP36

AP37

AP38

AP39

AP40

AP41

AP42

AP43

AP44

A27

AP46

A28

AP47

A31

AP8

A32

AP9

A34

AR35

B27

AR37

B28

AR39

B31

AR41

B32

AR43

B34

AR45

B36

AR46

B38

H30

B39

H31

6 3

B42

H32

12

PPVCC_S0_CPU

VCC

FC_D5
FC_D3

B43
B45
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29

D5
D3

Connections are required
for BDW CPU support.

PP1V05_S0_CPU_VCCST
CPU_VCCST_PWRGD

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

J17

AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33

AN31

AN22
AN18

AN33

AR49

AM49

AN49
AJ49
AG50
AK49
AJ50
AP49
AB50
AP50
AD50
AM50

AA46
AA47

J21
J26
J31

C50
AH9
D51
F17
AK6

J12

J53
J52
J50

B51
F19
E52
V49
U49

W49
V50

A36
A38
A39
A42
A43
A45
A46
A48

AA8
AA9

L6
M6

W9

RSVD64
RSVD65
RSVD66
RSVD67

VDDQ

RSVD68
VCC_L6
VCC_M6
RSVD69
RSVD70

VCC_SENSE
RSVD71
VCCIO_OUT
FC_F17
VCOMP_OUT
RSVD72
RSVD73
RSVD79(VSS)
RSVD74

VIDALERT*
VIDSCLK
VIDSOUT

VSS_B51
PWR_DEBUG*
VSS_E52
RSVD75
RSVD76
IVR_ERROR
IST_TRIGGER
VSS_V50(RSVD)
VSS_AN49(RSVD)
VSS_AJ49(RSVD)
VSS_AG50(RSVD)
VSS_AK49(RSVD)
VSS_AJ50(RSVD)
VSS_AP49(RSVD)
VSS_AB50(RSVD)
VSS_AP50(RSVD)
VSS_AD50(RSVD)
VSS_AM50(RSVD)

VCC

NC
NC
NC
NC

NC

NC
NC

NC

NC

NC
NC
NC
NC

U0500

HASWELL

BGA

SYM 5 OF 12

OMIT_TABLE

6 8

10 46 59 70 72

CPU Power

Apple Inc.

10 19

19

IN

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

8 OF 118

SHEET

8 OF 82

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

OMIT_TABLE

A11
A15
A19
A22
A26

D

C

B

A30
A33
A37
A40
A44
AA1
AA2
AA3
AA4

AA48

AA5
AA7

AB5
AB51
AB52
AB53
AB54

AB7

AB9
AC48

AC5
AC50

AC7
AD48
AD51
AD54

AD7

AD9

AE1

AE2

AE3

AE4
AE48

AE5
AE50

AE7

AF5

AF6

AF7
AG48

AG5
AG51
AG52
AG53
AG54

AG7

AG9

AH1

AH2

AH3

AH4
AH48

AH5
AH50

AH7

U0500

HASWELL

BGA

SYM 7 OF 12

GROUND

AJ48
AJ51
AJ54
AK48
AK5
AK50
AK7
AK9
AL1
AL4
AL48
AL5
AL7
AM5
AM51
AM52
AM53
AM54
AM7
AN1
AN2
AN3
AN4
AN48
AN5
AN50
AN7
AP51
AP54
AP7

VSSVSS

AR12
AR14
AR16
AR18
AR20
AR24
AR26
AR48
AR5
AR50
AR7
AR8
AR9
AT1
AT10
AT12
AT15
AT16
AT18
AT20
AT22
AT25
AT26
AT29
AT33
AT35
AT37
AT39
AT4

AT40
AT42
AT43
AT45
AT46
AT47
AT49

AT5
AT50
AT51
AT52
AT53
AT54

AT6

AT8

AT9
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42

AU5

AU9

AV1
AV13
AV18

AV2
AV22
AV25
AV29

AV3
AV33

AV4
AV42

AV5
AV50

AV9
AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49

AW5
AW50
AW51
AW54

AW9
AY13
AY22
AY25
AY29
AY33
AY37
AY42

OMIT_TABLE

U0500

HASWELL

BGA

SYM 8 OF 12

GROUND

VSS VSS

AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9

D

C

B

CPU_VCCSENSE_N

Y9Y7Y48

W7

W54

W52

W50

W48

V9V7V48

U7U6U54

U52

U50

U5

U48

C33

VSS

C37

U4U3U2U1T48

C40

C44

C49

C52

C8

D15

D11

D19

D22

D26

D30

D33

C4

D37

D40

D44

D49

D8

E11

E15

E16

E17

E19

G18

AR22

AB48

VSS_P9(RSVD)

VSS_G18(RSVD)

VSS_AB48(RSVD)

VSS_AR22(RSVD)

E25

E24

E22

E21

E20

E26

E30

A49

E33

E37

E40

B4A8A50

E44

BA1

E49

BA54

E51

BB1

E53

BB54

E8

BD2

F2

BF49

BD53

VSS_NCTF

F3

F26

BF5

F30

BF50

F33

BF6

F37

C53

G1

F54

E54

D2

F5

F4

F49

F44

F40

G11

G13

R7

R48P9P7P6P54

P52

P50

P5

P48

P4P3P2

P1

N7

N48

M7

M54

M52

M50

M48

L9L7L48

K7

K6K5K4

K3

K2K1J7

J54

J51

J49

J44

H7

H49

H44

G9G8G7

G54

G52

G49

G44

G40

G37

G33

G30

G26

G25

G23

G20

VSS

BGA

U0500

HASWELL

OMIT_TABLE

SYM 9 OF 12

w w w . c h i n a f i x . c o m

A

C30

C26

C22

C19

C15

C11

BC10

BC12

BC15

BC18

BC22

BC26

BC3

BC30

BC33

BC36

BC38

BC41

BC43

BC46

BC48

BC5

BC50

BC52

BC7

BD10

BD15

BD18

BD36

BD41

BD46

BD5

BD51

BE10

BE15

BE36

BE41

BE46

BF10

BF12

BF15

BF18

BF22

BF26

BF30

BF33

BF36

BF38

BF41

BF43

BF46

BF48

BF7

D50

VSS_SENSE

G16

1

R0960

100

PLACE_NEAR=U0500.D50:50.8mm

5%
1/16W

PLACE_SIDE=BOTTOM

MF-LF
402

2

6 3

58 75

OUT

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

CPU Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

9 OF 118

SHEET

9 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

CPU VCORE Decoupling

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)
Apple Implementation: 8x 210uF(2x nostuff) 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

PPVCC_S0_CPU

6 8

46 59 70 72

D

C

PLACEMENT_NOTE (C1000-C1019):
Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1000

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

PLACEMENT_NOTE (C1020-C1023):
Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

1

C1020

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

PLACEMENT_NOTE (C1024-C1045):
Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

CRITICAL

1

C1024

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1001

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C1021

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1025

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1002

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C1022

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1026

20UF

20%
4V

2

X5R-CERM
0402-2

PLACEMENT_NOTE (C1046-C1067):
Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

CRITICAL

1

C1046

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1047

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1048

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1003

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C1023

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1027

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1049

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1004

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C109A

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1028

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1050

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1005

1UF

10%
10V

2

X6S-CERM
0402

1

C1006

1UF

10%
10V

2

X6S-CERM
0402

1

C1007

1UF

10%
10V

2

X6S-CERM
0402

CAPs for Acoustic control (C109A-C102D)
NO STUFF

1

C109B

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

2

1

2

CRITICAL

C1029

20UF

20%
4V
X5R-CERM
0402-2

CRITICAL

C1051

20UF

20%
4V
X5R-CERM
0402-2

NO STUFF

1

C109C

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF
CRITICAL

1

C1030

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1052

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C109D

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1031

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1053

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C109E

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1008

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1032

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1054

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C109F

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1009

1UF

10%
10V

2

X6S-CERM

0402

NO STUFF
CRITICAL

1

C1033

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1055

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C101A

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1010

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1034

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1056

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C101B

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1011

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

NO STUFF
CRITICAL

1

C1035

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1057

20UF

20%
4V

2

X5R-CERM
0402-2

1

C101C

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1012

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

2

NO STUFF

CRITICAL

1

C1036

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1058

20UF

20%
4V

2

X5R-CERM
0402-2

C101D

20UF

20%
4V
X5R-CERM
0402-2

1

C1013

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

2

NO STUFF

CRITICAL

1

C1037

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1059

20UF

20%
4V

2

X5R-CERM
0402-2

C101E

20UF

20%
4V
X5R-CERM
0402-2

1

C1014

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C101F

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1038

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1060

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1015

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C102A

20UF

20%

4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1039

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1061

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1016

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C102B

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1040

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1062

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1017

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C102C

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1041

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1063

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1018

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C102D

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

CRITICAL

1

C1042

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1064

20UF

20%
4V

2

X5R-CERM
0402-2

1

C1019

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1043

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1065

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1044

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1066

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1045

20UF

20%
4V

2

X5R-CERM
0402-2

CRITICAL

1

C1067

20UF

20%
4V

2

X5R-CERM
0402-2

D

C

PLACEMENT_NOTE (C1068-C1076:

CRITICAL

1

C1068

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1069

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1070

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

NO STUFF

CRITICAL

1

C1071

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1072

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

NO STUFF
CRITICAL

1

C1073

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1074

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1075

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1076

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1077

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CAPs for Acoustic control (C102E-C103F)

NO STUFF

1

C102E

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C102F

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C103A

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C103B

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C103C

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C103D

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C103E

20UF

20%
4V

2

X5R-CERM
0402-2

NO STUFF

1

C103F

20UF

20%
4V

2

X5R-CERM
0402-2

CPU VDDQ Decoupling

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402
Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

PP1V35_S3RS0_CPUDDR

6 8

21 66 67

70 82

B

PLACEMENT_NOTE (C1080-C1089):
Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U100.

Place on bottom side of U0500

1

C1080

1UF

10%
10V

2

X6S-CERM
0402

1

C1081

1UF

10%
10V

2

X6S-CERM
0402

1

C1082

1UF

10%
10V

2

X6S-CERM
0402

PLACEMENT_NOTE (C1090-C1097):
Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

1

C1090

10UF

20%
4V

2

X6S
0402

1

C1091

10UF

20%
4V

2

X6S
0402

1

C1092

10UF

20%
4V

2

X6S
0402

1

C1083

1UF

10%
10V

2

X6S-CERM
0402

1

C1093

10UF

20%
4V

2

X6S
0402

1

C1084

1UF

10%
10V

2

X6S-CERM
0402

1

C1094

10UF

20%
4V

2

X6S
0402

1

C1085

1UF

10%
10V

2

X6S-CERM
0402

1

C1095

10UF

20%
4V

2

X6S
0402

1

C1086

1UF

10%
10V

2

X6S-CERM
0402

1

C1096

10UF

20%
4V

2

X6S
0402

1

C1087

1UF

10%
10V

2

X6S-CERM
0402

1

C1097

10UF

20%
4V

2

X6S
0402

1

C1088

1UF

10%
10V

2

X6S-CERM
0402

1

C1089

1UF

10%
10V

2

X6S-CERM

0402

B

PLACEMENT_NOTE (C1098-C1099):

CRITICAL

1

C1098

330UF-6MOHM

20%

2.0V

3 2

POLY-TANT
D15T-ECGLT-COMBO

CRITICAL

1

C1099

330UF-6MOHM

20%

2.0V

3 2

POLY-TANT
D15T-ECGLT-COMBO

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

w w w . c h i n a f i x . c o m

CPU VCCIO Decoupling

A

PPVCCIO_S0_CPU

5 6 8

18 58

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)
Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

1

C1079

0.01UF

10%
16V

2

X7R-CERM
0402

PP1V05_S0

14 15 17 18 42 62 67 70 72

6 3

BDW_SPRT

R1080

0

5%
1/10W
MF-LF

603

CPU VCCST Decoupling

Intel recommendation: 1x 0.1uF 0402, 1x 4.7uF 0805
Apple Implementation: 1x 0.1uF 0201, 1x 4.7uF 0402

21

PP1V05_S0_CPU_VCCST

8

19

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

PLACE_NEAR=U0500.D5:12.7mm

BDW_SPRT

1

C108A

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=U0500.D5:25.4mm

BDW_SPRT

1

C108B

4.7UF

20%

6.3V

2

X5R
402

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

10 OF 118

SHEET

10 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

D

PPVRTC_G3H

1

R1101

1M

5%
1/20W
MF
201

2

R1102

C1102

1

R1100

330K

5%

1/20W

MF

201

2

C

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.
PEG-attached (CPU) PCIe devices must use one set,
while PCH-attached PCIe devices use the other set.
If 2 or less devices are attached to PEG the
CLKOUT_PEG outputs can be used for those devices.

20K

1/20W

201

1UF

10%
10V
X5R
402

12 15 19 70

1

1

R1103

20K

5%
MF

2

1

2

5%
1/20W
MF
201

2

PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
RTC_RESET_L

1

C1103

1UF

10%
10V

2

X5R
402

B

PP3V3_SUS
PP3V3_S0

R1177
R1176
R1178

R1134
R1133

R1143
R1142

A

R1169
R1144
R1145
R1147
R1114
R1115

R1146
R1148

R1179

4.7K
10K

4.7K
10K

10K
10K

10K
10K
10K
10K
10K
10K
10K

10K
10K

10K

12 13 14 15 17 50 64 66 67 70
67 68 70 72 82

12 13 14 15 17 19 20 29 33 35
44 45 46 47 48 49 51 52 55 66

21

5% 201

21
21

5% MF

21
21

5% 201MF

21

5% 201MF

21
21
21
21
21

12

21

5%

21

5% 201MF

21

5% 201MF

21

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.

1/20W
1/20W
1/20W

1/20W
1/20W

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

1/20W
1/20W

1/20W

MF
MF 2015%

MF 2015%

MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 201

MF 2015%

HDA_BIT_CLK

52 77

OUT

HDA_SYNC

52 77

OUT

HDA_RST_L

52 77

OUT

HDA_SDOUT

52 77

OUT

11 77

11 77

11 77

11

PCH_SPKR
DP_TBT_SEL
PCH_SATALED_L

201

DP_AUXCH_ISOL_L
XDP_DC1_SATARDRVR_EN

SSD_CLKREQ_L
XDP_DD2_ENETSD_CLKREQ_L
AP_CLKREQ_L
CAMERA_CLKREQ_L
TBT_CLKREQ_L
PCH_CLKRQ5_L_GPIO44
PEG_CLKREQ_L
PCH_CLKRQ7_L_GPIO46

ENET_CLKREQ_L
PCH_PEGCLKRQB_L_GPIO56

ENET_MEDIA_SENSE_RDIV

R1110
R1111

R1112

R1113

11

11 71

11

18

11 18

11 35

11 18

18 34

11 36

11 28

11

11 71

11

11 71

11

11 71

12

OMIT_TABLE

SATALED*

TP9
TP8

BC8
BE8
AW8
AY8

BC10
BE10
AV10
AW10

BB9
BD9
AY13
AW13

BC12
BE12
AR13
AT13

BD13
BB13
AV15
AW15

BC14
BE14
AP15
AR15

AY5

AP3

AT1
AU2

BD4

BA2
BB2

NC_SATA_A_D2RN
NC_SATA_A_D2RP
NC_SATA_A_R2D_CN
NC_SATA_A_R2D_CP

NC_SATA_B_D2RN
NC_SATA_B_D2RP
NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP

NC_SATA_ODD_D2RN
NC_SATA_ODD_D2RP
NC_SATA_ODD_R2D_CN
NC_SATA_ODD_R2D_CP

NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP

TP_PCIE_ENET_D2RN
TP_PCIE_ENET_D2RP
TP_PCIE_ENET_R2D_CN
TP_PCIE_ENET_R2D_CP

NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP

76

PCH_SATA_RCOMP

PCH_SATALED_L

XDP_DC0_DP_AUXCH_ISOL_L
XDP_DC1_SATARDRVR_EN

NC
NC

IN

IN
OUT
OUT

IN

IN
OUT
OUT

73

73

73

73

73

73

73

73

73

73

73

73

11

OUT
OUT

SYSCLK_CLK32K_RTC

19 76

IN

PCH_SRTCRST_L

11 77

PCH_INTRUDER_L

11 77

PCH_INTVRMEN_L

11 77

RTC_RESET_L

11

33

33

33

21

77

HDA_BIT_CLK_R

MF 2015%

1/20W

PLACE_NEAR=U1100.B25:1.27mm

21

77

HDA_SYNC_R

1/20W

5% 201MF

PLACE_NEAR=U1100.A22:1.27mm

PCH_SPKR

11

21

77

HDA_RST_R_L

MF 2015%

1/20W

PLACE_NEAR=U1100.C24:1.27mm

HDA_SDIN0

52 77

IN

NC_HDA_SDIN1

73

NC_HDA_SDIN2

73

NC_HDA_SDIN3

73

21

19 77

HDA_SDOUT_R

1/20W33MF

PLACE_NEAR=U1100.A24:1.27mm

DP_TBT_SEL

11 71

OUT

ENET_MEDIA_SENSE_RDIV

11 71

IN

XDP_PCH_TCK

18 72

IN

XDP_PCH_TMS

18 72

IN

XDP_PCH_TDI

18 72

IN

XDP_PCH_TDO

18 72

OUT

2015%

B5
B4

NC

B9

A8

G10

D9

B25

A22

AL10

C24

L22
K22
G22
F22

A24

B17
C22

AB3

AD1

AE2

AD3

F8

NC

C26

NC

AB6

NC

RTCX1
RTCX2

SRTCRST*

INTRUDER*

INTVRMEN

RTCRST*

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST*

HDA_SDI0
HDA_SDI1
HDA_SDI2
HDA_SDI3

HDA_SDO

(IPD-DOCKEN#?)

DOCKEN*/GPIO33
HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TP25
TP22
TP20

LYNXPOINT

(IPD-boot)

(IPD-PLTRST#)

(IPD)
(IPD)
(IPD)
(IPD)

(IPD-boot)

(IPD)

(IPU)

(IPU)

U1100

MOBILE

FCBGA

(1 OF 11)

RTC

AZALIA

JTAG

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2

SATA_RXN3
SATA_RXP3
SATA_TXN3

SATA

SATA_TXP3

SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1

SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2

SATA_RCOMP

SATA0GP/GPIO21
SATA1GP/GPIO19

(IPU-PLTRST#)

SATA_IREF

OMIT_TABLE

TP19
TP18

AB35
AB36

AF6

Y39
Y38

U4

AF39
AF40

AJ40
AJ39

AF35
AF36

AY24
AW24

AR24
AT24

H33
G33

BE6
BC6

F45

D17

AM43
AL44

C40
F38
F36
F39

AM45

AD39
AD38

AN44

NC_PCIE_CLK100M_ENETN
NC_PCIE_CLK100M_ENETP

ENET_CLKREQ_L

NC_PCIE_CLK100M_PEGBN
NC_PCIE_CLK100M_PEGBP

PCH_PEGCLKRQB_L_GPIO56

DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P

CPU_CLK135M_DPLLSS_N
CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLREF_N
CPU_CLK135M_DPLLREF_P

77

PCIE_CLK100M_PCH_N

77

PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN
PCH_CLKIN_GNDP

PCH_CLK96M_DOT_N

77

77

PCH_CLK96M_DOT_P

77

PCH_CLK100M_SATA_N

77

PCH_CLK100M_SATA_P

77

PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN

76

SYSCLK_CLK25M_SB_R

NC

NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3
PP1V5_S0

NC
NC

PCH_DIFFCLK_BIASREF

PLACE_NEAR=U1100.AN44:2.54mm

R1190

7.5K

1/20W

201

PCIE_CLK100M_SSD_N

35 77

OUT

PCIE_CLK100M_SSD_P

35 77

OUT

SSD_CLKREQ_L

11 35

IN

NC_PCIE_CLK100M_ENETSDN

73

OUT

NC_PCIE_CLK100M_ENETSDP

73

OUT

XDP_DD2_ENETSD_CLKREQ_L

11 18

IN

PCIE_CLK100M_AP_N

34 77

OUT

PCIE_CLK100M_AP_P

34 77

OUT

XDP_DD3_AP_CLKREQ_L

18

IN

PCIE_CLK100M_CAMERA_N

37 77

OUT

PCIE_CLK100M_CAMERA_P

37 77

OUT

CAMERA_CLKREQ_L

11 36

IN

NC_PCIE_CLK100M_GPUN

73

NC_PCIE_CLK100M_GPUP

73

TBT_CLKREQ_L

11 28

IN

NC_PCIE_CLK100M_PE5N

73

NC_PCIE_CLK100M_PE5P

73

PCH_CLKRQ5_L_GPIO44

11

NC_PCIE_CLK100M_SWN

73

NC_PCIE_CLK100M_SWP

73

PEG_CLKREQ_L

11 71

IN

PCIE_CLK100M_TBT_N

28 77

OUT

PCIE_CLK100M_TBT_P

28 77

OUT

PCH_CLKRQ7_L_GPIO46

11

NC_ITPXDP_CLK100MN

73 75

OUT

NC_ITPXDP_CLK100MP

73 75

OUT

w w w . c h i n a f i x . c o m

LPC_CLK33M_SMC_R

19 77

OUT

NC_LPC_CLK33M_LPCPLUS_R

73 77

OUT

NC_PCI_CLK33M_OUT2

73

NC_PCI_CLK33M_OUT3

73

PCH_CLK33M_PCIOUT

19 77

OUT

Y43

CLKOUT_PCIE_N0

Y45

CLKOUT_PCIE_P0

AB1

PCIECLKRQ0*/GPIO73

AA44

CLKOUT_PCIE_N1

AA42

CLKOUT_PCIE_P1

AF1

PCIECLKRQ1*/GPIO18

AB43

CLKOUT_PCIE_N2

AB45

CLKOUT_PCIE_P2

AF3

PCIECLKRQ2*/GPIO20/SMI*

AD43

CLKOUT_PCIE_N3

AD45

CLKOUT_PCIE_P3

T3

PCIECLKRQ3*/GPIO25

AF43

CLKOUT_PCIE_N4

AF45

CLKOUT_PCIE_P4

V3

PCIECLKRQ4*/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P5

AA2

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

AB40

CLKOUT_PCIE_N6

AB39

CLKOUT_PCIE_P6

AE4

PCIECLKRQ6*/GPIO45

AJ44

CLKOUT_PCIE_N7

AJ42

CLKOUT_PCIE_P7

Y3

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

AH43

CLKOUT_ITPXDP_N

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

U1100

LYNXPOINT

MOBILE

FCBGA

(2 OF 11)

(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)

(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ*/GPIO56

CLOCKS

CLKIN_33MHZLOOPBACK

CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67

DIFFCLK_BIASREF

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKOUT_DPNS_N
CLKOUT_DPNS_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND_N
CLKIN_GND_P

CLKIN_DOT96_N
CLKIN_DOT96_P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

ICLK_IREF

6 3

SATA Port assignments:

73 76

73 76

Primary HDD/SSD (SATA only)

73 76

73 76

73 76

73 76

Secondary HDD/SSD (SATA only)

73 76

73 76

Reserved: ODD

Unused

PCIe:
Reserved: Ethernet
(if not combo w/SD Card)

Unused

PLACE_NEAR=U1100.AY5:2.54mm

18

11 18

73

73

11 71

IN

73

73

11

6

75

OUT

6

75

OUT

6

75

OUT

6

75

OUT

6

75

OUT

6

75

OUT

R1196
R1195

R1171
R1170

R1192
R1191

R1194
R1193

R1197

IN

73

73

73

73

11 12 13 15 17 19 52 64 67 69
70 72

12
1%
MF

Unused clock terminations for FCIM Mode

10K
10K

10K
10K

10K
10K

10K
10K

10K

19 77

PP1V5_S0

R1130

7.5K

1/20W

201

PP1V5_S0

1

1%
MF

2

11 12 13 15 17 19 52 64 67 69
70 72

NOTE: ENET pair only used if SD Card Reader is USB3.

21
21

21
21

5% 201MF

21
21

21
21

21

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W
1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF5%

1/20W

MF 2015%

1/20W

1.5V -> 1.1V

R1173

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

201

R1172

340

1%

1/16W

1

MF-LF

402

1K

1%

1/20W

MF

201

2

11 12 13 15 17 19 52 64 67 69
70 72

21

SYSCLK_CLK25M_SB

PCH RTC/HDA/JTAG/SATA/CLK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

19 76

IN

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

11 OF 118

SHEET

11 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

DMI_N2S_N<0>

5

75

IN

DMI_N2S_N<1>

5

73 75

IN

DMI_N2S_N<2>

5

73 75

IN

DMI_N2S_N<3>

5

73 75

IN

DMI_N2S_P<0>

5

75

IN

DMI_N2S_P<1>

5

73 75

IN

DMI_N2S_P<2>

5

73 75

IN

DMI_N2S_P<3>

5

73 75

IN

DMI_S2N_N<0>

5

75

OUT

DMI_S2N_N<1>

5

73 75

D

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

1

R1200

7.5K

1%

1/20W

MF

201

43

OUT

IN

R1286

1/20W

0201

2

1

0

5%
MF

2

PLACE_NEAR=U1100.AY17:12.7mm

PP3V3_SUS

11 13 14 15 17 50 64 66 67 70

NO STUFF

1

R1205

C

1/20W

10K

R1287

5%
MF

201

2

10K

1/20W

5%
MF

201

SMC_SUSACK:NO

1

43

2

OUT

5

73 75

OUT

5

73 75

OUT

5

75

OUT

5

73 75

OUT

5

73 75

OUT

5

73 75

OUT

19 41 72 77

IN

18 19 41 72 77

IN

12 19 72 77

IN

12 19 72 77

IN

6

21 75

OUT

67 72 77

IN

12 18 41 77

IN

41 42

IN

12 30 41 43

IN

DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

PCH_DMI_RCOMP

PCH_SUSACK_L
PM_SYSRST_L
PM_PCH_SYS_PWROK
PM_PCH_PWROK
PM_PCH_PWROK
PM_MEM_PWRGD
PM_RSMRST_L
PCH_SUSWARN_L
PM_PWRBTN_L
SMC_ADAPTER_EN
PM_BATLOW_L

PCH_RI_L

TP_PCH_SLP_S0_L
TP_PCH_SLP_WLAN_L

AW22

DMI_RXN0

AR20

DMI_RXN1

AP17

DMI_RXN2

AV20

DMI_RXN3

AY22

DMI_RXP0

AP20

DMI_RXP1

AR17

DMI_RXP2

AW20

DMI_RXP3

BD21

DMI_TXN0

BE20

DMI_TXN1

BD17

DMI_TXN2

BE18

DMI_TXN3

BB21

DMI_TXP0

BC20

DMI_TXP1

BB17

DMI_TXP2

BC18

DMI_TXP3

BE16

DMI_IREF

AW17

TP12

NC

AV17

TP7

NC

AY17

DMI_RCOMP

R6

SUSACK*

AM1

SYS_RESET*

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

(OD)

J2

RSMRST*

J4

SUSWARN*/SUSPWRNACK/GPIO30

K1

PWRBTN*

E6

ACPRESENT/GPIO31

(IPD-DeepSx)

K7

BATLOW*/GPIO72

N4

RI*

AB10

TP21

D2

SLP_WLAN*/GPIO29

(IPU)

(IPU)

U1100

LYNXPOINT

MOBILE

FCBGA

(4 OF 11)

DMI

MANAGEMENT

SYSTEM POWER

FDI_CSYNC

FDI

FDI_RCOMP

(IPD-DeepSx)

SUS_STAT*/GPIO61

SUSCLK/GPIO62
(IPU-RSMRST#)

SLP_S5*/GPIO63

FDI_RXN0
FDI_RXN1

FDI_RXP0
FDI_RXP1

TP16

TP15
TP10

FDI_INT

FDI_IREF

TP17
TP13

DSWVRMEN

DPWROK

WAKE*

CLKRUN*

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

SLP_LAN*

TP5

AJ35
AL35

AJ36
AL36

AV43
AY45
AV45
AW44

AL39
AL40

AT45

AU42
AU44

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3
F1

AY3

G5

NC
NC

NC
NC

NC
NC
NC
NC

FDI_CSYNC
FDI_INT

NC
NC

PCH_FDI_RCOMP

77

PCH_DSWVRMEN
PM_DSW_PWRGD
PCIE_WAKE_L
PM_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L
PM_SLP_SUS_L
PM_SYNC
TP_PCH_SLP_LAN_L

5

75

OUT

5

75

OUT

R1210

PLACE_NEAR=U1100.AR44:12.7mm

12 34 36 72 77

IN

12 41

BI

20 41

OUT

42

OUT

12 41 67

OUT

12 21 34 38 41 67 69 72

OUT

12 21 41 67 72

OUT

12 45 66 67

OUT

6

75

OUT

7.5K

1/20W

1%
MF

201

PP1V5_S0

1

2

PPVRTC_G3H

1

R1215

330K

5%
1/20W
MF
201

2

41 72 77

IN

1

R1209

100K

5%
1/20W
MF
201

2

11 12 13 15 17 19 52 64 67 69
70 72

11 15 19 70

D

C

T45

OMIT_TABLE

U44
V45

M43
M45

N42
N44

U40
U39

N36

K36

G36

H20
L20
K17
M20

A12
B13
C12

C10
A10
AL6

VGA_BLUE
VGA_GREEN
VGA_RED

VGA_DDC_CLK
VGA_DDC_DATA

VGA_HSYNC
VGA_VSYNC

DAC_IREF
VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA*
PIRQB*
PIRQC*
PIRQD*

GPIO50
GPIO52
GPIO54

GPIO51
GPIO53
GPIO55

NC
NC
NC

VGA DAC Disabled per SB
DG v1.0 (Table 12-18).

B

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

PP3V3_S5
PP3V3_S0

R1239
R1240
R1291
R1216

R1217
R1218

R1230
R1214

R1231

A

R1233
R1225
R1224

R1221
R1222
R1223

R1281
R1284

3.0K
10K
10K
10K

100K

10K
10K

100K

10K

10K

1K

100K
100K
100K
100K

100K
100K

NO STUFF

NO STUFF

14 15 17 18 19 21 31 32 34 61
64 66 67 70 71 72 82

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52 55
70 72 82

21

5%

12

5%

21

5%

21
21
21

21

Redundant to pull-up on audio page

21
21

Redundant to pull-up on audio page

21

21

5%

12

5%

12

5%

12

5%

12

5%

12

5%

12

5%

1/20W

1/20W

1/20W

1/20W
1/20W
1/20W

1/20W

1/20W
1/20W

1/20W

1/20W

1/20W
1/20W
1/20W
1/20W

1/20W
1/20W

66 67 68

PM_PWRBTN_L

MF

201

PM_BATLOW_L

MF

201

PM_CLKRUN_L

MF

201

ENET_LOW_PWR_PCH

MF

2015%

AUD_IPHS_SWITCH_EN_PCH

MF

2015%

BT_PWRRST_L

MF

2015%

SDCONN_OC_L

MF

2015%

AUD_IP_PERIPHERAL_DET

MF

2015%

TBT_PWR_REQ_L

MF

2015%

AUD_I2C_INT_L

MF

2015%

PCIE_WAKE_L

MF

201

PM_SLP_S3_L

MF

201

PM_SLP_S4_L

MF

201

PM_SLP_S5_L

MF

201

PM_SLP_SUS_L

MF

201

EDP_IG_BKL_ON

MF

201

EDP_IG_PANEL_PWR

MF

201

R1260
R1261
R1262
R1263

10K
10K
10K
10K

12 18 41 77

12 30 41 43

12 41

12 71

12 71

12 71

12 71

12 71

12 29

12 71

12 34 36 72 77

12 21 41 67 72

12 21 34 38 41 67 69 72

12 41 67

12 45 66 67

12 63 71 72

12 68 71 72

21

1/20W

21

1/20W

21

1/20W

21

1/20W

EDP_IG_BKL_PWM

63 71

OUT

EDP_IG_BKL_ON

12 63 71 72

OUT

EDP_IG_PANEL_PWR

12 68 71 72

OUT

PCI_INTA_L

MF

2015%

PCI_INTB_L

MF

2015%

PCI_INTC_L

MF

2015%

PCI_INTD_L

MF

2015%

ENET_LOW_PWR_PCH

12 71

OUT

AUD_IPHS_SWITCH_EN_PCH

12 71

OUT

BT_PWRRST_L

12 71

OUT

TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L

43

IN

w w w . c h i n a f i x . c o m

NC
NC

NC
NC

6 3

U1100

LYNXPOINT

MOBILE

FCBGA

(5 OF 11)

CRT

EDP

PCI

(IPU-PWROK&PCIRST#)

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DISPLAY

PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5

DDPB_AUXN
DDPC_AUXN
DDPD_AUXN

DDPB_AUXP
DDPC_AUXP
DDPD_AUXP

DDPB_HPD
DDPC_HPD
DDPD_HPD

(IPU)

PLTRST*

PME*

R40
R39

R35
R36

N40
N38

H45
K43
J42

H43
K45
J44

K40
K38
H39

G17
F17
L15
M15

AD10

Y11

DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA

HDMI_DDC_CLK
HDMI_DDC_DATA

DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_N
NC_DP_IG_D_AUXCHN

DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_P
NC_DP_IG_D_AUXCHP

DP_TBTSNK0_HPD
DP_TBTSNK1_HPD
HDMI_HPD

SDCONN_OC_L
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L

NC_PCI_PME_L

PLT_RESET_L

33 71

33 71

33 71

33 71

69 71 72

69 71 72

28 71 75

28 71 75

73

28 71 75

28 71 75

73

28 71

28 71

20 69 71 72

12 71

IN

12 71

IN

12 29

IN

12 71

IN

73

18 20 21 72

OUT

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

SYNC_DATE=12/18/2012

PCH DMI/FDI/PM/GFX/PCI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

12 OF 118

SHEET

12 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

FCBGA

USB3 Port Assignments:

Unused

D

PCIe/USB3 Port Assignments:

SD Card Reader
(& Ethernet if combo)

PCIe Port Assignments:

AirPort

Camera

SSD (Gumstick)
Lane 0
(PCIe-only)
Or PCIe switch if TBT/SSD

SSD (Gumstick)

C

B

Lane 1
(PCIe-only)
Or PCIe switch if TBT/SSD

SSD (Gumstick)
Lane 2
(PCIe-only)
Or PCIe switch if TBT/SSD

SSD (Gumstick)
Lane 3
(PCIe-only)
Or PCIe switch if TBT/SSD

PP1V5_S0

11 12 15 17 19 52 64 67 69 70
72

1

R1300

7.5K

1%
1/20W
MF
201

2

PLACE_NEAR=U1100.BD29:12.7mm

NC_USB3_SPARE_D2RN

73

NC_USB3_SPARE_D2RP

73

NC_USB3_SPARE_R2D_CN

73

NC_USB3_SPARE_R2D_CP

73

USB3_SD_D2R_N

20 69 72 77

IN

USB3_SD_D2R_P

20 69 72 77

IN

USB3_SD_R2D_C_N

20 69 72 77

OUT

USB3_SD_R2D_C_P

20 69 72 77

OUT

PCIE_AP_D2R_N

34 77

IN

PCIE_AP_D2R_P

34 77

IN

PCIE_AP_R2D_C_N

34 77

OUT

PCIE_AP_R2D_C_P

34 77

OUT

PCIE_CAMERA_D2R_N

37 77

IN

PCIE_CAMERA_D2R_P

37 77

IN

PCIE_CAMERA_R2D_C_N

37 77

OUT

PCIE_CAMERA_R2D_C_P

37 77

OUT

NC_PCIE_SSD_D2RN<0>

71

IN

NC_PCIE_SSD_D2RP<0>

71

IN

NC_PCIE_SSD_R2D_CN<0>

71

OUT

NC_PCIE_SSD_R2D_CP<0>

71

OUT

NC_PCIE_SSD_D2RN<1>

71

IN

NC_PCIE_SSD_D2RP<1>

71

IN

NC_PCIE_SSD_R2D_CN<1>

71

OUT

NC_PCIE_SSD_R2D_CP<1>

71

OUT

NC_PCIE_SSD_D2RN<2>

71

IN

NC_PCIE_SSD_D2RP<2>

71

IN

NC_PCIE_SSD_R2D_CN<2>

71

OUT

NC_PCIE_SSD_R2D_CP<2>

71

OUT

NC_PCIE_SSD_D2RN<3>

71

IN

NC_PCIE_SSD_D2RP<3>

71

IN

NC_PCIE_SSD_R2D_CN<3>

71

OUT

NC_PCIE_SSD_R2D_CP<3>

71

OUT

PCH_PCIE_RCOMP

NC
NC

AW31
AY31

BE32
BC32

AT31
AR31

BD33
BB33

AW33
AY33

BE34
BC34

AT33
AR33

BE36
BC36

AW36
AV36

BD37
BB37

AY38
AW38

BC38
BE38

AT40
AT39

BE40
BC40

AN38
AN39

BD42
BD41

BE30

BC30
BB29

BD29

PERN1_USB3RN3
PERP1_USB3RP3

PETN1_USB3TN3
PETP1_USB3TP3

PERN2_USB3RN4
PERP2_USB3RP4

PETN2_USB3TN4
PETP2_USB3TP4

PERN3
PERP3

PETN3
PETP3

PERN4
PERP4

PETN4
PETP4

PERN5
PERP5

PETN5
PETP5

PERN6
PERP6

PETN6
PETP6

PERN7
PERP7

PETN7
PETP7

PERN8
PERP8

PETN8
PETP8

PCIE_IREF

TP11
TP6

PCIE_RCOMP

(9 OF 11)

PCI-E

USB

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43

OC6*/GPIO10
OC7*/GPIO14

USBRBIAS*

USBRBIAS

OC5*/GPIO9

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB2N8
USB2P8

USB2N9
USB2P9

USB2N10
USB2P10

USB2N11
USB2P11

USB2N12
USB2P12

USB2N13
USB2P13

(IPD)

USB3RN1
USB3RP1
USB3TN1
USB3TP1

USB3RN2
USB3RP2
USB3TN2
USB3TP2

USB3RN5
USB3RP5
USB3TN5
USB3TP5

USB3RN6
USB3RP6
USB3TN6
USB3TP6

TP24
TP23

B37
D37

A38
C38

A36
C36

A34
C34

B33
D33

F31
G31

K31
L31

G29
H29

A32
C32

A30
C30

B29
D29

A28
C28

G26
F26

F24
G24

AR26
AP26
BE24
BD23

AW26
AV26
BD25
BC24

AW29
AV29
BE26
BC26

AR29
AP29
BD27
BE28

K24
K26

M33
L33

P3
V1
U2
P1
M3
T1
N2
M1

USB_EXTA_N
USB_EXTA_P

NC_USB_EXTCN
NC_USB_EXTCP

NC_USB_SDN
NC_USB_SDP

NC_USB_WLANN
NC_USB_WLANP

NC_USB_4N
NC_USB_4P

NC_USB_PSOCN
NC_USB_PSOCP

NC_USB_6N
NC_USB_6P

NC_USB_7N
NC_USB_7P

USB_EXTB_N
USB_EXTB_P

NC_USB_EXTDN
NC_USB_EXTDP

TP_USB_CAMERAN
TP_USB_CAMERAP

USB_BT_N
USB_BT_P

NC_USB_IRN
NC_USB_IRP

USB_TPAD_N
USB_TPAD_P

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N
USB3_EXTB_D2R_P
USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P

NC_USB3_EXTC_D2RN
NC_USB3_EXTC_D2RP
NC_USB3_EXTC_R2D_CN
NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_D2RN
NC_USB3_EXTD_D2RP
NC_USB3_EXTD_R2D_CN
NC_USB3_EXTD_R2D_CP

76

PCH_USB_RBIAS

NC
NC

XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTC_OC_L
XDP_DA2_SSD_PWR_EN
XDP_DA3_CAMERA_PWR_EN
XDP_DB0_USB_EXTB_OC_L
XDP_DB1_USB_EXTD_OC_L
XDP_DB2_SD_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE_L

73 76

73 76

73

73

73

73

73

73

73 76

73 76

73 76

73 76

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

38 76

38 76

73 76

73 76

69 72 76

69 72 76

73 76

73 76

34 76

34 76

73 76

73 76

39 72 76

39 72 76

38 76

38 76

38 76

38 76

69 72 76

69 72 76

69 76

69 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

OUT
OUT

OUT

USB Port Assignments:

Ext A (LS/FS/HS)

Ext C (LS/FS/HS)

Reserved: SD (HS)

Reserved: WiFi (HS)

Unused

Reserved: PSOC (Legacy Trackpad)

Unused

Unused

Ext B (LS/FS/HS)

Ext D (LS/FS/HS)

Reserved: Camera

BT

IR

Trackpad
USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

Ext C (SS)

Ext D (SS)

PLACE_NEAR=U1100.K24:11.4mm

1

R1370

22.6

1%
1/20W
MF
201

13 18

IN

13 18

IN

18

18

13 18

IN

13 18

IN

18

13 18

IN

2

12

D

C

B

OMIT_TABLE

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST*

TD_IREF

TP1
TP2
TP4
TP3

N7

R10
U11

N8

U8
R7

H6

K6
N11

AF11

AF10

AF7

BA45
BC45
BE43
BE44
AY43

PCH_SMBALERT_L
SMBUS_PCH_CLK

SMBUS_PCH_DATA

PCH_SML0ALERT_L
SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L
SML_PCH_1_CLK

SML_PCH_1_DATA

NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

NC
NC
NC
NC

PCH_TD_IREF

13

OUT

BI

13

OUT

BI

13

IN
BI

73

73

73

1

R1380

8.2K

1%
1/20W
MF
201

2

18 44 69 71 72 77

18 44 69 71 72 77

44 77

44 77

44 77

44 77

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

PCH PCI-E/USB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

13 OF 118

SHEET

13 OF 82

124578

SIZE

A

D

LPC_AD<0>

41 77

BI

LPC_AD<1>

41 77

BI

LPC_AD<2>

41 77

BI

LPC_AD<3>

41 77

BI

LPC_FRAME_L

41 77

OUT

PP3V3_SUS
PP3V3_SUS
PP3V3_S3
PP3V3_S3RS0_CAMERA
PP3V3_S0

R1350
R1351
R1360

A

R1361
R1362
R1368
R1320
R1321
R1367
R1369

R1392
R1393

R1353
R1354
R1355

10K
10K
10K

10K
10K
10K
10K
10K
10K
10K

1K
1K

10K
10K
10K

11 12 13 14 15 17 50 64 66 67
70

11 12 13 14 15 17 50 64 66 67
70

20 21 44 46 47 66 69 70 72

36 47 70
67 68 70 72 82

11 12 14 15 17 19 20 29 33 35
44 45 46 47 48 49 51 52 55 66

21

1/20W

5% 201MF

21

1/20W

21

1/20W

5%

21

1/20W

21

1/20W

21

1/20W

21

1/20W

5% 201MF

21

1/20W

5% 201MF

12

1/20W

5% 201MF

21

1/20W

21

1/20W

5% 201MF

21

1/20W

5% 201MF

21

1/20W

5% 201MF

21

1/20W

5% 201MF

21

1/20W

5% 201MF

MF 2015%

MF 201
MF 2015%
MF 2015%
MF 2015%

MF 2015%

LPC_SERIRQ
TBT_PWR_EN_PCH
XDP_DA0_USB_EXTA_OC_L

XDP_DA1_USB_EXTC_OC_L
SSD_PWR_EN
CAMERA_PWR_EN
XDP_DB0_USB_EXTB_OC_L
XDP_DB1_USB_EXTD_OC_L
SD_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE_L

SPI_IO<2>
SPI_IO<3>

PCH_SMBALERT_L
PCH_SML0ALERT_L
PCH_SML1ALERT_L

R1340
R1341
R1342
R1343

R1344

33
33
33

33

13 41

13 20

13 18

13 18

18 66

18 36

13 18

13 18

18 69 72

13 18

13 50 77

13 50 77

13

13

13

21

1/20W

21
21

5%

21

21

5% 201MF

1/20W
1/20W

1/20W

MF 2015%
MF 201
MF

w w w . c h i n a f i x . c o m

201MF5%

2015%331/20W

73

13 20

OUT

13 41

BI

50 77

OUT

50 77

OUT

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

LPC_FRAME_R_L
NC_LPC_DREQ0_L

TBT_PWR_EN_PCH
LPC_SERIRQ

SPI_CLK_R
SPI_CS0_R_L
TP_SPI_CS1_L
TP_SPI_CS2_L
SPI_MOSI_R

50 77

BI

SPI_MISO

50 77

BI

SPI_IO<2>

13 50 77

BI

SPI_IO<3>

13 50 77

BI

A20
C20
A18
C18

B21

D21
G20

AL11

AJ11

AJ7

AL7

AJ10

AH1

AH3

AJ4

AJ2

(IPU)

LAD0
LAD1

(IPU)
(IPU)

LAD2
LAD3

(IPU)

LFRAME*

LDRQ0*

(IPU)

LDRQ1*/GPIO23

(IPU-LDRQ1#?)

SERIRQ

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_CS2*

SPI_MOSI

SPI_MISO

SPI_IO2

(IPU)

SPI_IO3

(IPU)

U1100

LYNXPOINT

(3 OF 11)

(IPU)

(IPU)

(IPU)

(IPD)

(IPU)

SMBALERT*/GPIO11

MOBILE

FCBGA

SML0ALERT*/GPIO60

LPC

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

(IPU/IPD)

(IPU/IPD)

C-LINK

SPI

SML1CLK/GPIO58

SML1DATA/GPIO75

6 3

8 7 6 5 4 3

Pull-up/down on chipset support page (depends on TBT controller)
Falcon Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.
Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.

D

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

RAMCFG2:H

R1473

10K

1/20W

201

5%
MF

1

2

RAMCFG1:H

1

R1474

10K

5%
1/20W
MF
201

2

RAMCFG0:H

R1475

10K

1/20W

18 20 20

C

IN IN

BOM GROUP

RAMCFG_SLOT

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.

RAMCFG3:H

1

1

R1472

10K

5%

5%

1/20W
MF

MF

201

201

2

2

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

BOM OPTIONS

TBT_CIO_PLUG_EVENT_L

20 28

IN

FW_PME_L

14 71

IN

DPMUX_UC_IRQ

14 71

IN

SMC_RUNTIME_SCI_L

14 41

IN

XDP_FC0_HDD_PWR_EN

18

OUT

WOL_EN

14 71

OUT

MEM_VDD_SEL_1V5_L

14 71

OUT

XDP_DD0_SSD_PCIE_SEL_L

14 18

IN

LPCPLUS_GPIO

14 71

BI

JTAG_TBT_TMS_PCH

14 20

OUT

TBT_GO2SX_BIDIR

14 71

BI

SMC_WAKE_SCI_L

14 41

ISOLATE_CPU_MEM_L

21

OUT

TBT_POC_RESET_L

29

OUT

XDP_FC1_GPU_GOOD

18

OUT

XDP_DC2_ODD_PWR_EN_L

14 18

OUT

XDP_DC3_JTAG_ISP_TCK

18

OUT

JTAG_ISP_TDO

14 20

IN

JTAG_ISP_TDI

14 20

OUT

FW_PWR_EN_PCH

14 71

OUT

XDP_DD1_MLB_RAMCFG1
SPIROM_USE_MLB

14 50 72

BI

MLB_RAMCFG3

20

MLB_RAMCFG2

20

SD_SEL_PCIE_L_USB_H
MLB_RAMCFG0

20

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

AT8

BMBUSY*/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

(IPU-RSMRST#)

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

(IPU-Boot/SATA4GP?)

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

(IPU-DeepSx)

GPIO28

GPIO34

GPIO35/NMI*

SATA2GP/GPIO36

(IPD-PLTRST#)

SATA3GP/GPIO37

(IPD-PLTRST#)

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49

(IPU-Boot/SATA5GP?)

GPIO57

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

(IPU-Boot?)

TACH7/GPIO71

(IPU-Boot?)

VSS

AB11

AD11

BE41

K13

AN2

C14

BB4

Y10

R11

AN6

AP1

AT3

AK1

AT7

AM3

AN4

AK3

U12

C16

D13

G13

H15

BE5
C45

A5

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

(6 OF 11)

FCBGA

GPIO

(IPD)

PROCPWRGD

CPU/MISC

THRMTRIP*

PLTRST_PROC*

TP14

PECI

RCIN*

VSS

VSS

AN10

AY1

AT6

AV3

AV1

AU4

N10

A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

42 77

CPU_RESET_L

PART NUMBER

117S0201

14

14 77

OUT

PP1V05_S0

BDW_SPRT

1

R1457

1K

5%
1/16W
MF-LF
402

2

R1470

R1440
R1456

6

QTY

1

DESCRIPTION

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

0

390

NO STUFF

CRW_SPRT

21

CPU_PECI

5%

1/20W

MF43201

21

CPU_PWRGD

1/20W

5%
MF

0201

21

PM_THRMTRIP_L

5%

1/20W

201

MF

REFERENCE DES

10 15 17 18 42 62 67 70 72

BI

OUT

ININ

R1456

6

42 75

6

18 75

6

42 75

CRITICAL

12

D

BOM OPTION

BDW_SPRT

C

SIZE

B

A

D

B

PP3V3_S5
PP3V3_SUS
PP3V3_S0

R1485
R1411
R1496
R1494
R1489
R1495
R1490
R1412
R1492

A

R1491
R1498
R1413
R1486
R1499
R1484
R1493

R1450
R1455

10K
20K
10K
10K

10K
100K
100K

10K

10K

10K

10K

10K

10K

10K

10K
100K

10K

10K

12 15 17 18 19 21 31 32 34 61
64 66 67 70 71 72 82

11 12 13 15 17 50 64 66 67 70
66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52 55

NOTE: GPIO0 pull-up/down on project-specific page

21

5% 201

1/20W

12

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

12

5% 201

1/20W

21

5% 201

1/20W

12

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

12

5% 201

1/20W

12

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

NOTE: GPIO70 pull-up/down on project-specific page

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

FW_PME_L

MF

DPMUX_UC_IRQ

MF

SMC_RUNTIME_SCI_L

MF

WOL_EN

MF

MEM_VDD_SEL_1V5_L

MF

XDP_DD0_SSD_PCIE_SEL_L

MF

LPCPLUS_GPIO

MF

JTAG_TBT_TMS_PCH

MF

TBT_GO2SX_BIDIR

MF

SMC_WAKE_SCI_L

MF

XDP_DC2_ODD_PWR_EN_L

MF

JTAG_ISP_TCK

MF

JTAG_ISP_TDO

MF

JTAG_ISP_TDI

MF

FW_PWR_EN_PCH

MF

SPIROM_USE_MLB

MF

PCH_A20GATE

MF

PCH_RCIN_L

MF

14 71

14 71

14 41

14 71

14 71

14 18

14 71

14 20

14 71

14 41

14 18

18 20

14 20

14 20

14 71

14 50 72

14

14 77

w w w . c h i n a f i x . c o m

6 3

SYNC_MASTER=CLEAN_X305_PEG

PAGE TITLE

PCH GPIO/MISC/NCTF

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/18/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

14 OF 118

SHEET

14 OF 82

124578

8 7 6 5 4 3

12

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

VCC: 1.312 A Max, 130mA Idle

D

R1550

5.11

1%
1/20W
MF-LF

201

PLACE_NEAR=U1100.U14:2.54mm

21

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

VCCASW: 670mA Max, 34mA Idle

Powered in DeepSx

C1550

1UF

6.3V
CERM

PLACE_NEAR=R1550.1:2.54mm

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

1

10%

2

402

C

Y26
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24

U14

U18

U20

U22

U24

V18

V20

V22

V24

Y18

Y20

Y22
AA18

VCC

DCPSUSBYP

VCCASW

FCBGA

(7 OF 11)

CORE

CRT

VCCADACBG3_3

FDI

HVCMOS

USB3

PCIE/DMI

SATA

VCCMPHY

VCCADAC1_5

VCCVRM

VCCIO

VCC3_3

DCPSUS1

VCCSUS3_3

DCPSUS3

VCCIO

VCCVRM

VCCVRM

VCCIO

VCCVRM

VCCIO

VCCIO

VSS

P45

P43

M31

BB44

AN34
AN35

R30
R32

Y12

AJ30
AJ32

AJ26
AJ28

AK20

AK26
AK28

BE22

AK18

AN11

AK22

AM18
AM20
AM22
AP22
AR22
AT22

CKPLUS_WAIVE=PwrTerm2Gnd

VGA DAC Disabled per SB
DG v1.0 (Table 12-18).

CKPLUS_WAIVE=PwrTerm2Gnd

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP1V05_S0
VCCIO: 3629mA Max, 264mA Idle

PP3V3_S0
VCC3_3: 133mA Max, 3mA Idle

NC

PP3V3_SUS
VCCSUS3_3: 261mA Max, 6mA Idle

NC
NC

PP1V05_S0
VCCIO: 3629mA Max, 264mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

11 12 13 15 17 19 52 64 67 69

70 72

10 14 15 17 18 42 62 67 70 72

66 67 68 70 72 82
11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 50 64 66 67

70

10 14 15 17 18 42 62 67 70 72

11 12 13 15 17 19 52 64 67 69

70 72

11 12 13 15 17 19 52 64 67 69

70 72

11 12 13 15 17 19 52 64 67 69

70 72

D

C

B

A

Current data from LPT EDS (doc #486708, Rev 1.0).

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
70

VCCSUS3_3: 261mA Max, 6mA Idle

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

??mA Max, ??mA Idle

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

VCC3_3: 133mA Max, 3mA Idle

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

VCCIO: 3629mA Max, 264mA Idle

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

VCCVRM: 183mA Max, 68mA Idle

PP1V05_S0_PCH_VCC_CLK_F

17

??mA Max, ??mA Idle

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

VCCCLK: 306mA Max, 89mA Idle

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

VCCCLK3_3: 55mA Max, 11mA Idle

w w w . c h i n a f i x . c o m

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

VCCCLK: 306mA Max, 89mA Idle

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

VCCCLK: 306mA Max, 89mA Idle

R24

R26

VCCSUS3_3

R28

U26

M24

VSS

U35

VCCUSBPLL

L24

VCC3_3

V28

VCCIO

V30

Y30

Y35

AF34

AP45

Y32

M29

L29

L26

M26

U32

V32

AD34

AA30
AA32

AD35

AG30
AG32

AD36

AE30
AE32

DCPSUS2

VCCVRM

VCC

VCCCLK

VCCCLK3_3

VCCCLK

NC

FCBGA

(8 OF 11)

USB

CLK/MISC

GPIO/LPC

HDARTCCPUSPI

THERMAL

VCCSUS3_3

VCCDSW3_3

DCPSST

VCC3_3

VCCIO

VCCSUSHDA

VCCSUS3_3

VCCRTC

DCPRTC

V_PROC_IO

VCCSPI

VCCASW

VCCVRM

VCC3_3

VCC

R20
R22

A16

AA14

AE14
AF12
AG14

U36U30

A26

K8

A6

P14
P16

AJ12
AJ14

AD12

P18
P20

L17

R18

AW40

AK30
AK32

PP3V3_SUS
VCCSUS3_3: 261mA Max, 6mA Idle

PP3V3_S5
15 mA Max, 1mA Idle

PPVOUT_S0_PCH_DCPSST

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PP3V3_S0
VCC3_3: 133mA Max, 3mA Idle

PP1V05_S0
VCCIO: 3629mA Max, 264mA Idle

PP1V5_S0
10mA Max, 1mA Idle

PP3V3_SUS
VCCSUS3_3: 261mA Max, 6mA Idle

11 12 13 14 15 17 50 64 66 67

70

12 14 17 18 19 21 31 32 34 61
64 66 67 70 71 72 82

BYPASS=U1100.AA14::6.35mm

55 66 67 68 70 72 82
11 12 13 14 15 17 19 20 29
33 35 44 45 46 47 48 49 51 52

10 14 15 17 18 42 62 67 70

72

11 12 13 15 17 19 52 64 67 69
70 72

11 12 13 14 15 17 50 64 66 67

70

6uA Max (3.0V, room temperature)

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PP1V05_S0
4mA Max, 2mA Idle

PP3V3_SUS
22mA Max, 1mA Idle

NOTE: Pin name is VCC but really is 3.3V
PP3V3_S0

??mA Max, ??mA Idle

PP1V05_S0
VCCASW: 670mA Max, 34mA Idle

PP1V05_S0
VCCASW: 670mA Max, 34mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP3V3_S0
VCC3_3: 133mA Max, 3mA Idle

BYPASS=U1100.P14::6.35mm

10 14 15 17 18 42 62 67 70 72

11 12 13 14 15 17 50 64 66 67
70

66 67 68 70 72 82
11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52 55

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

11 12 13 15 17 19 52 64 67 69

70 72

66 67 68 70 72 82
11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52 55

1

C1580

0.1UF

20%
10V

2

CERM
402

1

C1590

0.1UF

20%
10V

2

CERM
402

C1533

0.1UF

6 3

PPVRTC_G3H

1

1

C1532

0.1UF

20%
10V

CERM

402

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

20%
10V

2

CERM

402

BYPASS=U1100.A6::6.35mm

1

C1531

1UF

10%

6.3V

2

2

CERM
402

BYPASS=U1100.A6::6.35mm

BYPASS=U1100.A6::6.35mm

PCH Power

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

11 12 19 70

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

15 OF 118

SHEET

15 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

VSS

K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8

D

C

AL34
AL38

AL8
AM14
AM24
AM26
AM28
AM30
AM32
AM16
AN36

D

C

AN40
AN42

AN8
AP13
AP24
AP31
AP43

AR2
AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38

D42
AV13
AV22
AV24
AV31
AV33
BB25
AV40

AV6

AW2

F43
AY10
AY15
AY20
AY26
AY29

AY7

B11

B15

VSS

U1100

LYNXPOINT

MOBILE

FCBGA

(10 OF 11)

VSS

AA16
AA20
AA22
AA28

AA4
AB12
AB34
AB38

AB8

AC2
AC44
AD14
AD16

B

w w w . c h i n a f i x . c o m

A

AD18
AD30
AD32
AD40

AD6

AD8
AE16
AE28
AF38

AF8
AG16

AG2
AG26
AG28
AG44
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38

AJ6

AJ8
AK14
AK24
AK43
AK45
AL12

AL2
BC22
BB42

U1100

LYNXPOINT

MOBILE

FCBGA

(11 OF 11)

VSS

6 3

B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29

VSSVSS

F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

PCH Grounds

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

16 OF 118

SHEET

16 OF 82

SIZE

B

A

D

124578

OMIT_TABLE

8 7 6 5 4 3

12

PCH VCCCLK3_3 BYPASS
PCH VCCDSW3_3 BYPASS
(PCH 3.3V DSW PWR)

PP3V3_S5

12 14 15 18 19 21 31 32 34 61
64 66 67 70 71 72 82

BYPASS=U1100.A16::6.35mm

D

C

B

PCH VCCSPI BYPASS
(PCH 3.3V SPI PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
70

BYPASS=U1100.AD12::6.35mm

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
70

BYPASS=U1100.R20::6.35mm

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND USB PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
70

BYPASS=U1100.R26::6.35mm

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND RTC PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
70

BYPASS=U1100.K8::6.35mm

PCH VCCSUSHDA BYPASS
(PCH 3.3V/1.5V HDA PWR)

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

BYPASS=U1100.A26::6.35mm

C1700

0.1UF

20%
10V

CERM

402

C1702

1UF

10%

6.3V
CERM

402

C1704

0.1UF

20%
10V

CERM

402

C1706

0.1UF

20%
10V

CERM

402

C1708

1UF

10%

6.3V
CERM

402

C1710

0.1UF

20%
10V

CERM

402

1

2

BYPASS=U1100.L26::6.35mm

1

2

1

2

1

2

1

2

1

2

C1720

BYPASS=U1100.L29::6.35mm

(PCH 3.3V CLK PWR)

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

C1721

1UF

6.3V
CERM

10%

402

1

2

1

1UF

10%

6.3V
2

CERM

402

BYPASS=U1100.M29::6.35mm

PCH VCC3_3 BYPASS
(PCH 3.3V HVCMOS PWR)

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

PCH VCC3_3 BYPASS
(PCH 3.3V GPIO/LPC PWR)

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

PCH VCC3_3 BYPASS
(PCH 3.3V USB2 PWR)

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

PCH VCC3_3 BYPASS
(PCH 3.3V THERMAL PWR)

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

PCH VCC BYPASS
(PCH 3.3V FUSE PWR)

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

PCH VCCVRM BYPASS
(PCH 1.5V VCCVRM PWR)

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

183mA Max, 68mA Idle

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

w w w . c h i n a f i x . c o m

1

1UF

10%

6.3V
CERM

402

2

C1723

1UF

6.3V
CERM

C1726

0.1UF

CERM

C1728

0.01UF

X7R-CERM

0402

C1730

0.1UF

CERM

C1732

0.1UF

CERM

C1734

1UF

6.3V
CERM

C1740

10UF

6.3V

C1722

BYPASS=U1100.U32::6.35mm

BYPASS=U1100.R30::6.35mm

BYPASS=U1100.AE14::6.35mm

BYPASS=U1100.L24::6.35mm

BYPASS=U1100.AK30::6.35mm

BYPASS=U1100.P18::6.35mm

BYPASS=U1100.AF34::12.7mm

10%

402

20%
10V

402

10%
16V

20%
10V

402

20%
10V

402

10%

402

20%
X5R

603

1

2

1

2

1

2

1

2

1

2

1

2

1

2

PART NUMBER

QTY

113S0022 1

PCH VCCASW BYPASS
(PCH 1.05V ME CORE PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

670mA Max, 34mA Idle

C1750

22UF

X5R-CERM-1

PLACE_NEAR=U1100.V20:2.54mm

PLACE_NEAR=U1100.V20:2.54mm

PCH VCC BYPASS
(PCH 1.05V CORE PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

BYPASS=U1100.AG18::12.7mm

PCH VCCIO BYPASS
(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

BYPASS=U1100.AK18::12.7mm

PCH VCCUSBPLL BYPASS
(PCH 1.05V USB2 PLL PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

PCH VCCIO BYPASS
(PCH 1.05V FDI PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

BYPASS=U1100.AN34::6.35mm

PCH VCCIO BYPASS
(PCH 1.05V USB2 PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

PCH V_PROC_IO BYPASS
(PCH 1.05V CPU I/F PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

PLACE_NEAR=U1100.V20:2.54mm

Not documented in EDS!

C1755

10UF

BYPASS=U1100.AA24::6.35mm

BYPASS=U1100.AK18::6.35mm

BYPASS=U1100.U35::6.35mm

BYPASS=U1100.U30::6.35mm

BYPASS=U1100.AD20::6.35mm

C1760

10UF

BYPASS=U1100.AK22::6.35mm

C1785

BYPASS=U1100.AJ12::12.7mm

BYPASS=U1100.AJ12::6.35mm

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

??mA Max, ??mA Idle

DESCRIPTION

RES,FF,0 OHM,(020OHM MAX),2A,0603

BYPASS=U1100.AJ12::6.35mm

1

20%

6.3V
2

603

1

20%

6.3V

2

X5R
603

1

20%

6.3V

2

X5R
603

1

C1770

1UF

10%

6.3V

2

CERM

402

1

C1772

1UF

10%

6.3V

2

CERM

402

1

C1774

0.1UF

20%
10V

2

CERM

402

1

1UF

10%

6.3V
2

CERM

402

R1790

REFERENCE DES

L1790

1

C1751

1UF

10%

6.3V

2

CERM
402

1

C1756

1UF

10%

6.3V

2

CERM
402

BYPASS=U1100.AE18::6.35mm

1

C1761

1UF

10%

6.3V

2

CERM
402

BYPASS=U1100.AK20::6.35mm

1

C1786

0.1UF

20%
10V

2

CERM
402

1

5%
1/16W
MF-LF

402

1

C1752

1UF

10%

6.3V

2

CERM
402

1

C1757

1UF

10%

6.3V

2

CERM
402

1

C1762

1UF

10%

6.3V

2

CERM
402

BYPASS=U1100.AM18::6.35mm

1

C1787

0.1UF

20%
10V

2

CERM
402

21

PP1V05_S0_PCH_VCC_CLK_R

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

CRITICAL

1

C1758

1UF

10%

6.3V

2

CERM
402

1

C1763

1UF

10%

6.3V

2

CERM
402

4.7UH-170MA-0.321OHM

BOM OPTION

BYPASS=U1100.AP45::12.7mm

1

C1764

1UF

10%

6.3V

2

CERM
402

PCH VCCCLK BYPASS
(PCH 1.05V SSC100 PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

BYPASS=U1100.AE30::6.35mm

PCH VCCCLK BYPASS
(PCH 1.05V DIFFCLK PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

PCH VCCCLK BYPASS
(PCH 1.05V DIFFCLK135 PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

PCH VCCCLK BYPASS
(PCH 1.05V SSC PWR)

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

CRITICAL

OMIT_TABLE

L1790

21

0603

NO STUFF

C1790

10UF

20%

6.3V
X5R
603

BYPASS=U1100.AP45::6.35mm

C1776

1UF

10%

6.3V
CERM

402

BYPASS=U1100.AG30::6.35mm

BYPASS=U1100.AD35::6.35mm

BYPASS=U1100.AD34::6.35mm

BYPASS=U1100.AA30::6.35mm

PCH CLK VCC BYPASS
(PCH 1.05V CLK PLL PWR)

PP1V05_S0_PCH_VCC_CLK_F

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1791

1UF

10%
10V

2

2

X5R
402

1

2

C1777

1UF

6.3V
CERM

C1778

1UF

6.3V
CERM

C1780

1UF

6.3V
CERM

C1782

1UF

6.3V
CERM

10%
402

10%
402

10%

402

10%

402

D

1

2

1

2

1

2

C

B

1

2

15

A

Current data from LPT EDS (doc #486708, Rev 1.0).

6 3

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

17 OF 118

SHEET

17 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

IN

IN

OUT
OUT

IN

6

18 72 75

OUT

OUT

OUT

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

51

51

51

12 20 21 72

11 18 72

11 18 72

11 18 72

6

18 72 75

6

18 72 75

6

72 75

6

72 75

PP1V05_SUS

64 70

51

51

51

51

XDP

21

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

MF

MF

MF

D

C

B

MF

MF

MF

MF

PPVCCIO_S0_CPU

5 6 8

XDP

C1804

0.1UF

6.3V

CERM-X5R

0201

10%

10 58

1

R1830

150

5%
1/16W
MF-LF
402

2

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

TCK1
TCK0

XDP

1

1

R1831

1K

5%

2

1/16W
MF-LF
402

2

C1800

0.1UF

CERM-X5R

Extra BPM Testpoints

XDP_BPM_L<2>

6

75

IN

XDP_BPM_L<3>

6

75

IN

XDP_BPM_L<4>

6

75

IN

XDP_BPM_L<5>

6

75

IN

XDP_BPM_L<6>

6

75

IN

XDP_BPM_L<7>

6

75

D

C

IN

6

14 75

IN

12 41 77

OUT

12 19 41 72 77

OUT

6

18 72 75

OUT

CPU_PWRGD

PM_PWRBTN_L

PM_PCH_SYS_PWROK

XDP_CPU_TCK

1

TP

TP1802

TP-P6

1

TP

TP1803

TP-P6

1

TP

TP1804

TP-P6

1

TP

TP1805

TP-P6

1

TP

TP1806

TP-P6

1

TP

TP1807

TP-P6

PLACE_NEAR=U0500.F50:2.54mm

PLACE_NEAR=U5000.J3:2.54mm

R1800

R1802

R1804

PP1V05_S0

10 14 15 17 18 42 62 67 70 72

XDP_CPU_PREQ_L

6

72 75

BI

XDP_CPU_PRDY_L

6

72 75

IN

CPU_CFG<0>

6

75

IN

CPU_CFG<1>

6

75

IN

CPU_CFG<2>

6

75

IN

CPU_CFG<3>

6

72 75

IN

XDP_BPM_L<0>

6

75

IN

XDP_BPM_L<1>

6

75

IN

CPU_CFG<4>

6

75

IN

CPU_CFG<5>

6

75

IN

CPU_CFG<6>

6

75

XDP

1K

0

0

21

5% 201

XDP

21

5%

XDP

21

5%

1/20W

1/20W

MF

0201

MF

402

MF-LF1/16W

IN

CPU_CFG<7>

6

75

IN

XDP_CPU_VCCST_PWRGD
XDP_CPU_PWRBTN_L

CPU_PWR_DEBUG

8

OUT

XDP_SYS_PWROK

SMBUS_PCH_DATA

13 44 69 71 72 77

BI

SMBUS_PCH_CLK

13 44 69 71 72 77

IN

XDP_PCH_TCK

11 18 72

OUT

XDP_CPU_PRESENT_L

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

PCH/XDP Signals

XDP_DA0_USB_EXTA_OC_L

13 38

OUT

XDP_DA2_SSD_PWR_EN

IN

XDP_DA3_CAMERA_PWR_EN

13

IN

XDP_DB0_USB_EXTB_OC_L

13

OUT

XDP_DB2_SD_PWR_EN

13

B

IN

XDP_DB3_SDCONN_STATE_CHANGE_L

13

OUT

XDP_DC0_DP_AUXCH_ISOL_L

11

IN

XDP_DC1_SATARDRVR_EN

11 18

IN

XDP_DC2_ODD_PWR_EN_L

IN

XDP_DC3_JTAG_ISP_TCK

14

IN

XDP_DD0_SSD_PCIE_SEL_L

14 35

OUT

XDP_DD1_MLB_RAMCFG1

OUT

XDP_DD2_ENETSD_CLKREQ_L

11 18

OUT

XDP_DD3_AP_CLKREQ_L

11

OUT

R1890
R1895
R1893
R1894
R1896
R1897

R1872

MAKE_BASE=TRUE
MAKE_BASE=TRUE

R1875
R1876

MAKE_BASE=TRUE
MAKE_BASE=TRUE

R1879

(All 10 R’s)

SHORT
SHORT
SHORT
SHORT
SHORT
SHORT

SHORT

SHORT
SHORT

SHORT

OMIT

21
21
21

NONENONE NONE

21

NONE NONE NONE

21

NONE NONENONE

21

NONE NONENONE

21

NONE

NONE NONE

21

NONE

NONE NONE

21

21

NONE NONE NONE

Non-XDP Signals

NONENONENONE
NONENONENONE

NONENONENONE

SSD_PWR_EN

201

CAMERA_PWR_EN

201

USB_EXTB_OC_L

201

SD_PWR_EN

201

SDCONN_STATE_CHANGE_L

201

DP_AUXCH_ISOL_L

201

XDP_DC1_SATARDRVR_EN
XDP_DC2_ODD_PWR_EN_L
JTAG_ISP_TCK

201

SSD_PCIE_SEL_L

201

XDP_DD1_MLB_RAMCFG1
XDP_DD2_ENETSD_CLKREQ_L
AP_CLKREQ_L

201

USB_EXTA_OC_L

201

IN

13 66 13

OUT
OUT

IN

13 69 72

OUT

20

IN

11

OUT

11 18

OUT

14 18 14 18

OUT

14 20

OUT

IN

14 18 20 14 18 20

IN

11 18

IN

11 34

IN

PCH/XDP Signal Isolation Notes:
’Output’ non-XDP signals require pulls.

’Output’ PCH/XDP signals require pulls.

R187x and R189x should be placed where
signal path needs to split between route
from PCH to J1850 and path to non-XDP
signal destination (to minimize stub).

w w w . c h i n a f i x . c o m

Merged (CPU/PCH) Micro2-XDP

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

SDA
SCL

XDP

10%

6.3V
0201

DF40RC-60DP-0.4V

1

2

CRITICAL
XDP_CONN

J1800

M-ST-SM1

62

61

1

8 7

9

10
12 11
14 13
16 15
18 17
20219
22 21
24 23
26 25
28 27
30329
32 31
34 33
36 35
38 37
40439
42 41
44 43
46 45
48 47
50549
52 51
54 53
56 55
58 57
60659

64 63

518S0847

CPU JTAG Isolation

PP5V_S0

19 37 49 58 59 62 63 66 67 70
71 72

PP3V3_S5

12 14 15 17 19 21 31 32 34 61
64 66 67 70 71 72 82

1

C1845

0.1UF

10%
16V

2

19 41 58 67 72

IN

X5R-CERM

ALL_SYS_PWRGD

0201

74LVC1G07GF

2

A

1

NC NC

6

VCC

U1845

SOT891

GND

3

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

NC
NC

XDP_CPURST_L
XDP_DBRESET_L

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

75

IN

6

19 75

OUT

R1805

XDP_TRST_L

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=J1800.51:28mm

CRITICAL

Q1840

DMN5L06VK-7

SOT563

XDP

VER 5

3

CRITICAL

Q1840

DMN5L06VK-7

SOT563

XDP

VER 5

PLACE_NEAR=J1800.53:28mm

6

CRITICAL

Q1842

DMN5L06VK-7

SOT563

XDP

VER 5

PLACE_NEAR=J1800.55:28mm

3

CRITICAL

Q1842

DMN5L06VK-7

SOT563

XDP

1

R1845

330K

5%
1/20W
MF
201

2

Y

4

5

NCNC

PLACE_NEAR=J1800.57:28mm

XDP_JTAG_CPU_ISOL_L

VER 5

6

XDP_CPU_TDO

6

18 72 75

XDP_CPU_TCK

6

18 72 75

XDP_CPUPCH_TRST_L

6

18 72 75

PLACE_NEAR=U0500.M49:28mm

PLACE_NEAR=U0500.N54:28mm

PLACE_NEAR=U0500.M53:28mm

R1820
R1823

R1824

TDI and TMS are terminated in CPU.

XDP

1K

21

PLT_RESET_L

5% 201

1/20W

PLACE_NEAR=U0500.AG7:2.54mm

MF

XDP_PCH_TDO

XDP_PCH_TDI
XDP_PCH_TMS

5

G

SD

4

2

G

SD

1

5

G

SD

4

2

G

SD

1

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

XDP_PCH_TDO

11 18 72

XDP_PCH_TDI

11 18 72

XDP_PCH_TMS

11 18 72

XDP_PCH_TCK

11 18 72

PLACE_NEAR=U1100.AD3:28mm

PLACE_NEAR=U1100.AE2:28mm

PLACE_NEAR=U1100.AD1:28mm

PLACE_NEAR=U1100.AB3:28mm

R1860
R1861

R1862
R1866

Unused PCH/XDP Signals

XDP_DA1_USB_EXTC_OC_L

13

BI

XDP_DB1_USB_EXTD_OC_L

13

A

BI

XDP_FC0_HDD_PWR_EN

14

BI

XDP_FC1_GPU_GOOD

14

BI

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1810
TP1811
TP1812
TP1813

6 3

SYNC_MASTER=J15_MLB

PAGE TITLE

CPU & PCH XDP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

18 OF 118

SHEET

18 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH Reset Button

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

XDP

XDP_DBRESET_L

6

18 75

IN

D

R1996

1/16W
MF-LF

1

R1995

1K

5%
1/16W
MF-LF
402

2

0

21

5%

402

PM_SYSRST_L

OMIT

1

R1997

0

5%
1/16W
MF-LF
402

2

SILK_PART=SYS RESET

OUT

12 41 72 77

D

PP3V42_G3H

19 35 38 39 41 42 43 44 50
56 57 65 67 70 72

52 55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29
33 35 44 45 46 47 48 49 51

ALL_SYS_PWRGD

18 41 58 67 72

IN

CPUVR_PGOOD

IN

SMC_DELAYED_PWRGD

29 30 41 42

C

IN

NOTE: ALL_SYS_PWRGD must remain low until at
least 5ms after all rails are valid.

R1950

2.0K

1/16W
MF-LF

1

5%

402

2

PCH PWROK Generation

BYPASS=U1950::5MM

1

C1950

0.1UF

20%

1

A

U1950

2

B

10V

2

CERM
402

74LVC2G08GT/S505

8

SOT833

7

Y

08

4

R1947

PM_S0_PGOOD

1/20W

0201

NO STUFF

2

1

R1948

0

0

5%

5%

1/20W
MF

MF

0201

1

2

WF: Do we need this?

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

8

SOT833

5

A

3

SYS_PWROK_R

Y

U1950

6

B

PLACE_NEAR=U1100.AD7:7MM

08

4

CKPLUS_WAIVE=UNCONNECTED_PINS

PCH 33MHz Clocks

R1955

22

LPC_CLK33M_SMC_R

11 77 41 77

IN

PCH_CLK33M_PCIOUT

11 77

IN

PLACE_NEAR=U1100.D44:6.35mm

PLACE_NEAR=U1100.A40:6.35mm

B

System RTC Power Source & 32kHz / 25MHz Clock Generator

VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_B: Camera power rail for XTAL circuit.
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

72 82

GreenClk 25MHz Power

SB XTAL Power
Camera XTAL Power
TBT XTAL Power

NOTE: SLG3NB148A provides slow rising
edge on 25MHZ_B when powered from

1.2V VDDIO. Falcon Ridge also
complicates VDD_25M power, forcing
at least S4. Both issues to be
addressed in upcoming part
(SLG3NB148C).

A

PP3V3_S5

12 14 15 17 18 19 21
31 32 34 61 64 66 67 70 71

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

PP1V2_CAM_XTALPCIEVDD

36

PP3V3_TBTLC

20 28 29 70

C1905

12PF

2 1

5%
50V
C0G

0402

C1906

12PF

5%
50V
C0G

0402

SYSCLK_CLK25M_X2

CRITICAL

31

21

SYSCLK_CLK25M_X1

NOTE: 30 PPM crystal required

21

5%

1/20W

MF

201

R1959

22

21

5%

1/20W

MF

201

1

CERM

C1920

20%
10V

402

0.1UF

2

C1924

0.1UF

42

Y1905

NC

3.2X2.5MM-SM

NC

25.000MHZ-20PPM-12PF-85C

LPC_CLK33M_SMC

PCH_CLK33M_PCIIN

PP3V42_G3H

19 35 38 39 41 42 43 44 50 56
57 65 67 70 72

Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)

PP3V3_S5

12 14 15 17 18 19 21 31 32 34
61 64 66 67 70 71 72 82

Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5
No bypass necessary

1

C1922

0.1UF

20%
10V

CERM

402

R1905

1/16W
MF-LF

20%
10V

2

CERM

402

0

21

5%

402

SYSCLK_CLK25M_X2_R

NO STUFF

1

R1906

1M

5%
1/16W
MF-LF
402

2

OUT

11 77

OUT

1

C1902

2

1

w w w . c h i n a f i x . c o m

1UF

10%
10V

2

X5R

402-1

6 3

R1949

1K

5%
1/16W
MF-LF

402

11

VIOE_25M_A

6

VIOE_25M_B

14

VIOE_25M_C

3

X2

4

X1

PM_PCH_PWROK
PM_PCH_PWROK

MAKE_BASE=TRUE

21

PM_PCH_SYS_PWROK

5

NC

VDD

U1900

SLG3NB148CV

TQFN

CRITICAL

32.768K

THRM

GND

PAD

17216107

OUT
OUT

OUT

13

VBAT and +V3.3A are
internally ORed to

VG3HOT

create VDD_RTC_OUT.
+V3.3A should be first

available ~3.3V power
to reduce VBAT draw.

25M_A
25M_B
25M_C

VOUT

12

9
8
15

1

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB
SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_TBT
PPVRTC_G3H

For SB RTC Power

1

C1910

1UF

10%

6.3V

2

CERM
402

12 19 72 77

12 19 72 77

12 18 41 72 77 58

11 12 15 70

VCCST (1.05V S0) PWRGD

PP3V3_S5

12 14 15 17 18 19 21 31 32 34
61 64 66 67 70 71 72 82

PM_PCH_PWROK

12 19 72 77

BDW_SPRT

C1930

0.1UF

X5R-CERM

0201

10%
16V

1

2

NC

BDW_SPRT

CRITICAL

U1930

74AUP1G09

6

SOT891

VCC

2

1

5

4

YA

B

NC

GND

3

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

Q1920

DMN5L06VK-7

PP1V5_S0

11 12 13 15 17 19 52 64 67 69
70 72

DMN5L06VK-7

SPI_DESCRIPTOR_OVERRIDE_L

41 42

11 76

OUT

11 76

OUT

37 76

OUT

28 76

OUT

IN

PP1V05_S0_CPU_VCCST

BDW_SPRT

1

R1930

10K

5%
1/20W
MF
201

2

CPU_VCCST_PWRGD

SOT563

VER 5

3

5

G

SD

4

Q1920

SOT563

VER 3

2

8

10

8

OUT

PP5V_S0

18 37 49 58 59 62 63 66 67 70
71 72

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

6

D

SG

1

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

Chipset Support

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

R1921

1K

5%
1/20W
MF
201

2

HDA_SDOUT_R

IPD = 9-50k

Apple Inc.

1

R1920

100K

5%
1/20W
MF
201

2

SYNC_DATE=12/18/2012

11 77

OUT

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

19 OF 118

SHEET

19 OF 82

SIZE

C

B

A

D

124578

8 7 6 5 4 3

12

RIO SD Card Reader Support

PP3V3_S4

34 39 40 42 43 46 47 65 66 67
69 70 71 72

1

R2041

470K

5%
1/20W

1

R2040

D

SMC_PME_S4_DARK_L

28 41 42 43

OUT

PP3V3_S3

13 21 44 46 47 66 69 70 72

SDCONN_STATE_CHANGE_L

18

OUT

To/From PCH

Flexible I/O Aliases

SD Card Reader is always USB3 in this implementaton.

USB3_SD_D2R_P

13 20 69 72 77 13 20 69 72 77

OUT

USB3_SD_D2R_N

13 20 69 72 77

OUT

C

USB3_SD_R2D_C_P

13 20 69 72 77

IN

USB3_SD_R2D_C_N

13 20 69 72 77

IN

Flexible I/O Configuration Strap

Must pull signal correctly even if always USB or PCIe

52 55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29
33 35 44 45 46 47 48 49 51

R2030

SD_SEL_PCIE_L_USB_H

14

OUT

DMN5L06VK-7

C2030

0.1UF

10%

6.3V

CERM-X5R

0201

1

100K

5%

1/20W

MF

201

2

Q2040

SOT563

VER 5

3

4

Y

1

2

USB3_SD_D2R_P

MAKE_BASE=TRUE

USB3_SD_D2R_N

MAKE_BASE=TRUE

USB3_SD_R2D_C_P

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

MAKE_BASE=TRUE

5

SMC_PME_SDCONN

G

SD

4

CRITICAL

U2030

TC7SZ08FEAPE

SOT665

5

2

A

1

B

3

RIO_SDCONN_STATE_CHANGE_L

IN

13 20 69 72 77

IN

13 20 69 72 77

OUT

13 20 69 72 77

OUT

470K

1/20W

Q2040

DMN5L06VK-7

5%

SOT563

VER 5

MF

201

2

6

From RIO Connector

G

SD

MF
201

2

2

1

69 72

IN

14 20 28 14 20 28

LCD HPD Inverter

(Pull-Up on CPU Page)

DP_IG_A_HPD_L

3

D

G

LCD_HPD

68

IN

1

Q2010

DMN32D2LFB4

S

DFN1006H4-3

SYM_VER_1

2

5

OUT

HDMI HPD pull-down

HDMI_HPD

12 69 71 72

OUT

1

R2010

100K

5%

1/20W

MF

201

2

Falcon Ridge Support

RR output is open-drain, no isolation necessary

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

TBT_CIO_PLUG_EVENT_L

IN

MAKE_BASE=TRUE

R2075

10K

1/20W

1

5%
MF

201

2

TBT_CIO_PLUG_EVENT_L

OUT

Platform Reset Connections

Unbuffered

Buffered

1

U2080

2

1

2

CRITICAL

5

MC74VHC1G08

SC70-HF

4

3

PLT_RST_BUF_L

MAKE_BASE=TRUE

1

R2080

100K

5%
1/16W
MF-LF
402

2

RAM Configuration Straps

MLB_RAMCFG3

14

OUT

MLB_RAMCFG2

14

OUT

XDP_DD1_MLB_RAMCFG1

14 18

OUT

MLB_RAMCFG0

14

OUT

RAMCFG0:L

R2002

1/20W

1

1

1K

5%
MF

201

2

2

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

12 18 21 72

IN

PLT_RESET_L

MAKE_BASE=TRUE

C2080

0.1UF

20%
10V

CERM

402

GPIO Glitch Prevention

55 66 67 68 70 72 82

PP3V3_S0

11 12 13 14 15 17 19 20 29 33
35 44 45 46 47 48 49 51 52

R2091

0

21

5%
1/16W
MF-LF

402

R2087

0

21

5%
1/16W
MF-LF

402

RAMCFG1:L

R2011

1K

5%
1/20W
MF
201

R2083

33

5%
1/16W
MF-LF

402

R2085

0

5%
1/16W
MF-LF

402

R2088

0

5%
1/16W
MF-LF

402

RAMCFG2:L

R2012

21

SMC_LRESET_L

21

SSD_RESET_L

CAM_PCIE_RESET_L

21

AP_RESET_L

TBT_PCIE_RESET_L

RAMCFG3:L

1

1

1K

5%

1/20W

MF

201

2

2

R2013

1K

5%
1/20W
MF
201

41

OUT

D

35

OUT

36

OUT

34

OUT

28

OUT

C

B

GS3 Connector Support

DEVSLP not supported on LPT-H

SSD_DEVSLP

35

OUT

1

R2070

10K

5%

1/20W

MF

201

2

A

Falcon Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

U2060 supports I/O’s powered when VCC=0V

PP3V3_TBTLC

19 28 29 70

49 51 52 55 66 67 68 70

PP3V3_S0

11 12 13 14 15 17 19 20
29 33 35 44 45 46 47 48
72 82

0.1UF

X5R-CERM

0201

16V

1

10%

2

1

2

3

C2060

JTAG_TBT_TMS_PCH

14

IN

JTAG_ISP_TDO

14

OUT

JTAG_ISP_TDI JTAG_TBT_TDI

14

IN

To/From PCH
(Pull-ups on PCH page)

w w w . c h i n a f i x . c o m

R2061

8

VCC

U2060

SN74AUP3G07DQER

X2SON

1A

3Y 3A

2A 2Y

GND

4

1/20W

1Y

CRITICAL

10K

7

6

5

1

1

R2062

10K

5%

5%

1/20W
MF

MF

201

201

2

2

1

R2063

10K

5%
1/20W
MF
201

2

Pull-up values TBD

JTAG_TBT_TMS

JTAG_TBT_TDO

To/From RR

28

OUT

28

IN

28

OUT

6 3

TBT_PWR_EN must be high for JTAG Programming

20 28

IN

14 18

IN
IN

12 41

IN

TBT_PWR_EN
JTAG_ISP_TCK
TBT_PWR_EN_PCH
LPC_PWRDWN_L

1

C2013

0.1UF

10%
16V

2

X5R-CERM
0201

7

3

JTAG_TBT_TCK

TBT_PWR_EN

Y1

Y2

SYNC_DATE=01/14/2013

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

U2000

1

A1

2

B1

5

A2

6

B2

SOT833

8

VCC

08

GND

4

74LVC2G08GT/S505

CRITICAL

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

Project Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

124578

28

OUT

20 28 13

OUT

<SCH_NUM>

<E4LABEL>

<BRANCH>

20 OF 118

20 OF 82

SIZE

B

A

D

8 7 6 5 4 3

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

CPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PM_SLP_S4_L

12 34 38 41 67 69 72

IN

CRITICAL

PP3V3_S3

13 20 44 46 47 66 69 70 72

DMN5L06VK-7

C

ISOLATE_CPU_MEM_L

14 12 41 67 72

IN IN

PP5V_S3

21 37 60 66 67 70 72

CPUMEM:S0

1

R2115

100K

5%
1/16W
MF-LF

402

2

CRITICAL

CPUMEM:S0

Q2115

DMN5L06VK-7

SOT563

VER 5

B

MEMRESET_ISOL_LS5V_L

22

OUT

CPU_MEM_RESET_L

6

21

IN

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

1 0 1 1 1 1 1 1 1

to

2 0 0 1 1 1 1 0 1

A

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1
5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NO STUFF

C2117

0.047UF

10%

6.3V
X5R
201

CPU_MEM_RESET_L

MAKE_BASE=TRUE

6

1

2

2

G

SD

1

CRITICAL

CPUMEM:S0

Q2115

DMN5L06VK-7

5

G

S D

4

CPUMEM:S3

R2117

5%
1/16W
MF-LF

402

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2100

SOT563

VER 3

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2100

DMN5L06VK-7

SOT563

VER 3

SOT563

VER 5

3

0

21

R2101

100K

1/16W
MF-LF

402

5

R2102

100K

1/16W
MF-LF

402

2

CPUMEM:S0

1

R2116

1K

5%
1/16W
MF-LF
402

2

1

5%

2

3

D

SG

1

5%

2

6

D

SG

CPUVDDQ_EN_L

4

MEMVTT_EN_L

1

CPUMEM:S0

Q2105

DMN5L06VK-7

SOT563

VER 3

CRITICAL
CPUMEM:S0

Q2110

DMN5L06VK-7

SOT563

VER 3

PP1V35_S3

CPUMEM:S0

1

C2116

0.1UF

20%
10V

2

CERM
402

2

3

D

S G

4

2

3

D

S G

4

w w w . c h i n a f i x . c o m

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

6 3

CPUMEM:S0

1

R2105

10K

5%
1/16W
MF-LF
402

2

CPUVDDQ_EN

6

D

SG

1

CRITICAL

5

PM_SLP_S3_L

CPUMEM:S0

1

R2110

10K

5%
1/16W
MF-LF
402

2

MEMVTT_EN

6

1

5

PLT_RESET_L

MEM_RESET_L

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2105

DMN5L06VK-7

SOT563

VER 3

D

SG

Q2110

DMN5L06VK-7

SOT563

VER 3

46 60 66 70 72

OUT

OUT

IN

OUT

66

21 60 71

12 18 20 72

23 24 25 26

PP1V35_S3RS0_CPUDDR

6 8

10 66 67 70 82

R2120

27.4K

1/16W
MF-LF

R2121

43.2K

1/16W
MF-LF

MEM S0 "PGOOD" for CPU

PP3V3_S5

12 14 15 17 18 19 31 32 34 61
64 66 67 70 71 72 82

1%

402

1%

402

1

2

MEMPWR_DIV

1

2

C2120

0.047UF

X5R-CERM

1

10%
10V

2

0402

5

1

R2122

10K

5%
1/16W
MF-LF
402

2

PM_MEM_PWRGD_L

3

CRITICAL

Q2120

DMB53D0UV

SOT-563

4

MEMVTT Clamp

Ensures CKE signals are held low in S3

PP5V_S3

21 37 60 66 67 70 72

DMN5L06VK-7

MEMVTT_EN

21 60 71

IN

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2150

SOT563

VER 3

R2151

100K

5

1/16W
MF-LF

5%

402

1

2

3

D

SG

4

DMN5L06VK-7

VTTCLAMP_EN

NO STUFF

0.001UF

27 60 70 72

CRITICAL

CPUMEM:S0

Q2150

SOT563

C2151

20%
50V

CERM

402

PPVTT_S0_DDR

VER 3

2

1

2

G

2

6

D

SG

1

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM:S0

VTTCLAMP_L

PM_MEM_PWRGD

6

CRITICAL

D

Q2120

DMB53D0UV

SOT-563

S

1

1

R2150

10

5%
1/10W
MF-LF

603

2

SYNC_MASTER=CLEAN_X305G

PAGE TITLE

75mA max load @ 0.75V
60mW max power

6

12 75

OUT

CPU Memory S3 Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

SYNC_DATE=07/01/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

21 OF 118

SHEET

21 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

D

CPU-Based Margining

NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
DDR3L (1.35V) 6.99mV per step
LPDDR3 (1.2V) ?.??mV per step

MEMRESET_ISOL_LS5V_L

21

IN

CPU_DIMMA_VREFDQ

7

75

IN

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

C

CPU_DIMMB_VREFDQ

7

75

IN

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

CPU_DIMM_VREFCA

7

IN

NOTE: CPU has single output for VREFCA.
Connected to 4 DRAMs.

MIN_NECK_WIDTH=0.2 mm

B

CRITICAL

Q2220

DMN5L06VK-7

2

SOT563

G

VER 5

S D

1

CRITICAL

Q2220

DMN5L06VK-7

5

G

S D

4

CRITICAL

Q2260

DMN5L06VK-7

2

G

S D

1

CRITICAL

Q2260

DMN5L06VK-7

5

G

S D

4

6

CPU_MEM_VREFDQ_A_ISOL

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

SOT563

VER 5

3

CPU_MEM_VREFDQ_B_ISOL

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

SOT563

VER 5

6

CPU_MEM_VREFCA_ISOL

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

SOT563

VER 5

3

VRef Dividers

Always used, regardless
of margining option.

R2223

2

21

1%

PLACE_NEAR=R2221.2:1mm

1/20W

MF

0201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_A_RC

R2243

2

21

1%

PLACE_NEAR=R2241.2:1mm

1/20W

MF

0201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

2

21

1%

PLACE_NEAR=R2261.2:1mm

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFCA_RC

R2222

1/20W

R2220

24.9

1%

1/20W

MF

201

R2242

1/20W

R2240

24.9

1%

1/20W

MF

201

R2262

1/20W

R2260

24.9

1%

1/20W

MF

201

201

201

201

1

1K

1%
MF

2

21

1

1K

1%
MF

2

21

1

1K

1%
MF

2

21

PP1V35_S3_MEM

1

R2221

1K

1%
1/20W
MF
201

2

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

R2241

1K

1%
1/20W
MF
201

2

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

R2261

1K

1%
1/20W
MF
201

2

PP0V75_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3 mmMIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

23 24 25 26 46 70 78

23 24 71 75 78

C

25 26 71 75

23 24 25 26 71 75 78

B

A

DAC Channel:

PCA9557D Pin:

Nominal value

Margined target:

DAC range:

VRef current:

DAC step size:

MEM A VREF DQ

A

1

MEM B VREF DQ

LPDDR3 (1.2V)

0.600V (DAC: 0x2E.5)

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

+73uA - -73uA (- = sourced)

6.36mV / step @ output

w w w . c h i n a f i x . c o m

MEM A VREF CA

B

2

C

3

DDR3L (1.35V)

0.675V (DAC: 0x34)

0.337V - 1.013V (+/- 337.5mV)

0.000V - 1.354V (0x00 - 0x69)

+82uA - -82uA (- = sourced)

6.36mV / step @ output

MEM B VREF CA

C

4

MEM VREG

D

LPDDR3 (1.2V)

1.200V (DAC: 0x5D)

0.800V - 1.600V (+/- 400mV)

0.000V - 2.397V (0x00 - 0xBA)

+21uA - -21uA (- = sourced)

4.28mV / step @ output

5

DDR3L (1.35V)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

0.000V - 2.694V (0x00 - 0xD1)

+25uA - -25uA (- = sourced)

3.53mV / step @ output

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

6 3

SYNC_MASTER=CLEAN_X305

PAGE TITLE

DDR3 VREF MARGINING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/14/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

22 OF 118

SHEET

22 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

C2307

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 78

MEM_A_A<1>

7

23 24

D

27 78

MEM_A_A<2>

7

23 24

27 78

MEM_A_A<3>

7

23 24

27 78

MEM_A_A<4>

7

23 24

27 78

MEM_A_A<5>

7

23 24

27 78

MEM_A_A<6>

7

23 24

27 78

MEM_A_A<7>

7

23 24

27 78

MEM_A_A<8>

7

23 24

27 78

MEM_A_A<9>

7

23 24

27 78

MEM_A_A<10>

7

23 24

27 78

MEM_A_A<11>

7

23 24

27 78

MEM_A_A<12>

7

23 24

27 78

MEM_A_A<13>

7

23 24

27 78

MEM_A_A<14>

7

23 24

27 78

MEM_A_A<15>

7

23 24

27 78

MEM_A_BA<0>

7

23 24

27 78

MEM_A_BA<1>

7

23 24

27 78

MEM_A_BA<2>

7

23 24

27 78

MEM_A_RAS_L

7

23 24

27 78

MEM_A_CAS_L

7

23 24

27 78

MEM_A_WE_L

7

23 24

27 78

MEM_A_ODT<0>

7

23 27

78

MEM_A_ZQ<0>

2

C

R2300

240

1%
1/20W
MF
201

1

22 23 24 25 26 71 75 78

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2300

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 46 70
78

B10

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

N10

L10

C2

VDDQ

E3

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

CERM-X5R-1

MEM_A_A<0>

7

MEM_A_A<1>

7
78

MEM_A_A<2>

7

MEM_A_A<3>

7
27 78

MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>

7
27 78

MEM_A_A<7>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
78

MEM_A_A<11>

7
24 27

MEM_A_A<12>

7
24 27
78

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<0>

7
27 78

MEM_A_BA<1>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<0>

7

MEM_A_ZQ<1>

2

R2310

240

1%
1/20W
MF
201

1

C2317

0.47UF

1

1

C2308

0.047UF

10%

6.3V

J9

X5R

H2

201

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<0>

DQ0

C8

MEM_A_DQ<6>

DQ1

C3

MEM_A_DQ<7>

DQ2

C9

MEM_A_DQ<5>

DQ3

E4

MEM_A_DQ<3>

E9

MEM_A_DQ<1>

D3

MEM_A_DQ<2>

E8

MEM_A_DQ<4>

C4

MEM_A_DQS_P<0>

DQS

D4

MEM_A_DQS_N<0>

DQS*

B8
A8

NC

H3

MEM_A_CS_L<0>

CS*

G10

MEM_A_CKE<0>

CKE

F8

MEM_A_CLK_P<0>

CK

G8

MEM_A_CLK_N<0>

CK*

A1

NC NC

A4

NC

A11

NC

NC

F2

NC

F10

NC

D10

C10

C2309

0.047UF

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

7

24 78

7

24 78

23 24

23 24

23 24

23 24

23 24
27 78

23

23

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24

23

78
7
23 27

23

23 24 27 78

23 24 27 78

23 27 78

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2310

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

J2

B2

A2

1

1

C2318

0.047UF

10%

6.3V
X5R

H2

201

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<14>

C8

MEM_A_DQ<9>

C3

MEM_A_DQ<10>

C9

MEM_A_DQ<15>

E4

MEM_A_DQ<11>

E9

MEM_A_DQ<13>

D3

MEM_A_DQ<8>

E8

MEM_A_DQ<12>

C4

MEM_A_DQS_P<1>

D4

MEM_A_DQS_N<1>

B8
A8

NC NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1
A4

NC

A11

NC

F2

NC

F10

NC

C2319

0.047UF

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 78

23

23

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24

23

78
7
23 27

23

23 24 27 78

23 24 27 78

23 27 78

D10

C2327

CERM-X5R-1

MEM_A_A<0>

7

MEM_A_A<1>

7
78

MEM_A_A<2>

7

MEM_A_A<3>

7
27 78

MEM_A_A<4>

7
27 78

MEM_A_A<5>

7
27 78

MEM_A_A<6>

7
27 78

MEM_A_A<7>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
78

MEM_A_A<11>

7
24 27

MEM_A_A<12>

7
24 27
78

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<0>

7
27 78

MEM_A_BA<1>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<0>

7

MEM_A_ZQ<2>

2

R2320

240

1%
1/20W
MF
201

1

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2320

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2328

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<22>

C8

MEM_A_DQ<21>

C3

MEM_A_DQ<16>

C9

MEM_A_DQ<17>

E4

MEM_A_DQ<18>

E9

MEM_A_DQ<23>

D3

MEM_A_DQ<20>

E8

MEM_A_DQ<19>

C4

MEM_A_DQS_P<2>

D4

MEM_A_DQS_N<2>

B8
A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

1

CERM-X5R-1

MEM_A_A<0>

7

MEM_A_A<1>

7
78

MEM_A_A<2>

7

MEM_A_A<3>

7
27 78

MEM_A_A<4>

7
27 78

MEM_A_A<5>

7
27 78

MEM_A_A<6>

7
27 78

MEM_A_A<7>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
78

MEM_A_A<11>

7
24 27

MEM_A_A<12>

7
24 27
78

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<0>

7
27 78

MEM_A_BA<1>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<0>

7

MEM_A_ZQ<3>

2

R2330

240

1%
1/20W
MF
201

1

C2337

0.47UF

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2329

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 78

23

23

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24
78
27

23

23
7

23 27 78

23

7

23 24 27 78

23 24 27 78

23 27 78

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2330

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2338

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<31>

C8

MEM_A_DQ<24>

C3

MEM_A_DQ<27>

C9

MEM_A_DQ<28>

E4

MEM_A_DQ<30>

E9

MEM_A_DQ<25>

D3

MEM_A_DQ<26>

E8

MEM_A_DQ<29>

C4

MEM_A_DQS_P<3>

D4

MEM_A_DQS_N<3>

B8
A8

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

1

C2339

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

D

21 23 24 25 26

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

23 27

78
7

23 27

78

7

23 27

78
7

23 27

78

C

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

1

C2347

0.47UF

20%

4V

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 78

MEM_A_A<1>

7

23 24

27 78

MEM_A_A<2>

7

23 24

27 78

MEM_A_A<3>

7

23 24

27 78

MEM_A_A<4>

7

23 24

27 78

MEM_A_A<5>

7

23 24

27 78

MEM_A_A<6>

7

23 24

27 78

MEM_A_A<7>

7

23 24

27 78

MEM_A_A<8>

7

23 24

27 78

MEM_A_A<9>

7

23 24

27 78

B

MEM_A_A<10>

7

23 24

27 78

MEM_A_A<11>

7

23 24

27 78

MEM_A_A<12>

7

23 24

27 78

MEM_A_A<13>

7

23 24

27 78

MEM_A_A<14>

7

23 24

27 78

MEM_A_A<15>

7

23 24

27 78

MEM_A_BA<0>

7

23 24

27 78

MEM_A_BA<1>

7

23 24

27 78

MEM_A_BA<2>

7

23 24

27 78

MEM_A_RAS_L

7

23 24

27 78

MEM_A_CAS_L

7

23 24

27 78

MEM_A_WE_L

7

23 24

27 78

MEM_A_ODT<0>

7

23 27

78

MEM_A_ZQ<4>

2

R2340

240

1%
1/20W
MF
201

1

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

22 23 24 25 26 71 75 78

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2340

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 46 70
78

B10

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

N10

L10

C2

VDDQ

E3

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2348

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2349

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>

NC

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 78

23

23

7

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24
78
27

23

23
7

23 27 78

23

7

23 24 27 78

23 24 27 78

23 27 78

7

7
78

7

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
78

7
24 27

7
24 27
78

7

7

7
27 78

7
27 78

7
24 27
78

7
24 27 78

7

7

7

2

R2350

240

1%
1/20W
MF
201

1

C2357

0.47UF

20%

CERM-X5R-1

201

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_ODT<0>
MEM_A_ZQ<5>

PP1V35_S3_MEM

1

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

w w w . c h i n a f i x . c o m

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2350

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2358

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<40>

C8

MEM_A_DQ<41>

C3

MEM_A_DQ<42>

C9

MEM_A_DQ<43>

E4

MEM_A_DQ<44>

E9

MEM_A_DQ<45>

D3

MEM_A_DQ<46>

E8

MEM_A_DQ<47>

C4

MEM_A_DQS_P<5>

D4

MEM_A_DQS_N<5>

B8
A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

J2

B2

A2

MEM_A_A<0>

7

MEM_A_A<1>

7
78

MEM_A_A<2>

7

MEM_A_A<3>

7
27 78

MEM_A_A<4>

7
27 78

MEM_A_A<5>

7
27 78

MEM_A_A<6>

7
27 78

MEM_A_A<7>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
78

MEM_A_A<11>

7
24 27

MEM_A_A<12>

24 78

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<0>

7
27 78

MEM_A_BA<1>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<0>

7

C2367

CERM-X5R-1

1

1

C2359

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 78

23

7
24 78

7

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24
78
27

23

23
7

23 27 78

23

7

23 24 27 78

23 24 27 78

23 27 78

MEM_A_ZQ<6>

2

R2360

240

1%
1/20W
MF
201

1

22 23 24 25 26 71 75 78

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2360

DDR3-1333

(SYM VER 2)

VSS

F3N2L2

22 23 24 25 26 46 70
78

M10

M2

FBGA

F9D9A9

J10

L10

N10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2368

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<48>

C8

MEM_A_DQ<49>

C3

MEM_A_DQ<50>

C9

MEM_A_DQ<51>

E4

MEM_A_DQ<52>

E9

MEM_A_DQ<53>

D3

MEM_A_DQ<54>

E8

MEM_A_DQ<55>

C4

MEM_A_DQS_P<6>

D4

MEM_A_DQS_N<6>

B8
A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

1

CERM-X5R-1

MEM_A_A<0>

7

MEM_A_A<1>

7
78

MEM_A_A<2>

7

MEM_A_A<3>

7
27 78

MEM_A_A<4>

7
27 78

MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
78

MEM_A_A<11>

7
24 27

MEM_A_A<12>

7
24 27
78

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<0>

7
27 78

MEM_A_BA<1>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<0>

7

MEM_A_ZQ<7>

2

R2370

240

1%
1/20W
MF
201

1

C2377

0.47UF

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2369

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

7

24 78

7

24 78

23 24

23 24

23 24

23 24
27 78

23

23

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24
78
27

23

23
7

23 27 78

23

7

23 24 27 78

23 24 27 78

23 27 78

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2370

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2378

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<56>

C8

MEM_A_DQ<57>

C3

MEM_A_DQ<58>

C9

MEM_A_DQ<59>

E4

MEM_A_DQ<60>

E9

MEM_A_DQ<61>

D3

MEM_A_DQ<62>

E8

MEM_A_DQ<63>

C4

MEM_A_DQS_P<7>

D4

MEM_A_DQS_N<7>

B8
A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

1

1

C2379

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

21 23 24 25 26

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

7

24 78

B

7

24 78

7

24 78

7

24 78

7

23 27

78
7

23 27

78

7

23 27

78
7

23 27

78

A

PP1V35_S3_MEM

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2300

C2340

C2301

2.2UF

X5R-CERM

C2341

2.2UF

X5R-CERM

22 23 24 25 26 46 70 78

1

C2310

2.2UF

20%
10V

2

X5R-CERM

402

1

C2350

2.2UF

20%
10V

2

X5R-CERM

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

SIZE

A

D

SYNC_MASTER=J15_MLB

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2320

2.2UF

X5R-CERM

C2360

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2321

2.2UF

X5R-CERM

C2361

2.2UF

X5R-CERM

1

C2330

20%
10V

2

402

1

C2370

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2331

2.2UF

2

1

2

X5R-CERM

C2371

2.2UF

X5R-CERM

20%
10V

402

20%
10V

402

20%
10V

402

20%
10V

402

1

C2311

20%
10V

2

402

1

C2351

20%
10V

2

402

1

1

C2303

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

1

1

C2343

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

1

C2304

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2344

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2305

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2345

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2313

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2353

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2314

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2354

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2315

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2355

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2323

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2363

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2324

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2364

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2325

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2365

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2333

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2373

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2334

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2374

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2335

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2375

0.1UF

10%

6.3V

2

CERM-X5R
0201

PAGE TITLE

DDR3 SDRAM Bank A (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

23 OF 118

SHEET

23 OF 82

124578

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

1

C2407

0.47UF

20%

4V

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 78

MEM_A_A<1>

7

23 24

D

27 78

MEM_A_A<2>

7

23 24

27 78

MEM_A_A<4>

7

23 24

27 78

MEM_A_A<3>

7

23 24

27 78

MEM_A_A<6>

7

23 24

27 78

MEM_A_A<5>

7

23 24

27 78

MEM_A_A<8>

7

23 24

27 78

MEM_A_A<7>

7

23 24

27 78

MEM_A_A<9>

7

23 24

27 78

MEM_A_A<10>

7

23 24

27 78

MEM_A_A<11>

7

23 24

27 78

MEM_A_A<12>

7

23 24

27 78

MEM_A_A<13>

7

23 24

27 78

MEM_A_A<14>

7

23 24

27 78

MEM_A_A<15>

7

23 24

27 78

MEM_A_BA<1>

7

23 24

27 78

MEM_A_BA<0>

7

23 24

27 78

MEM_A_BA<2>

7

23 24

27 78

MEM_A_RAS_L

7

23 24

27 78

MEM_A_CAS_L

7

23 24

27 78

MEM_A_WE_L

7

23 24

27 78

MEM_A_ODT<1>

7

24 27

78

MEM_A_ZQ<8>

2

C

R2400

240

1%
1/20W
MF
201

1

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

22 23 24 25 26 71 75 78

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2400

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 46 70
78

B10

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

N10

L10

C2

VDDQ

E3

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2408

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2409

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<6>
MEM_A_DQ<0>
MEM_A_DQ<5>
MEM_A_DQ<7>
MEM_A_DQ<4>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<3>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

NC

MEM_A_CS_L<1>
MEM_A_CKE<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

7
23 78

7

7
78

78
7
24 27

7
78

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 78

23

23 78

23 24 27 78

23 24 27 78

23 24 27 78

24 27

23 24

23

24 27

23 24 27 78

23 24 27 78

24 27 78

7

7
78

7

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
78

7
24 27

7

7

7

7
27 78

7
24 27
78

7

7

7

2

R2410

240

1%
1/20W
MF
201

1

C2417

0.47UF

CERM-X5R-1

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_BA<1>
MEM_A_BA<0>
MEM_A_BA<2>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_ODT<1>
MEM_A_ZQ<9>

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2410

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

J2

B2

A2

MEM_A_A<0>

7

MEM_A_A<1>

7
78

7

MEM_A_A<4>

7
27 78

MEM_A_A<3>

7
27 78

MEM_A_A<6>

7
27 78

MEM_A_A<5>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<7>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
27 78

MEM_A_A<11>

23

78

MEM_A_A<12>

7
24 27

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<1>

7
27 78

MEM_A_BA<0>

7
78

MEM_A_BA<2>

7
24 27

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<1>

7

MEM_A_ZQ<10>

2

R2420

240

1%
1/20W
MF
201

1

C2427

CERM-X5R-1

1

1

C2418

0.047UF

10%

6.3V
X5R

H2

201

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<9>

C8

MEM_A_DQ<14>

C3

MEM_A_DQ<15>

C9

MEM_A_DQ<10>

E4

MEM_A_DQ<12>

E9

MEM_A_DQ<8>

D3

MEM_A_DQ<13>

E8

MEM_A_DQ<11>

C4

MEM_A_DQS_P<1>

D4

MEM_A_DQS_N<1>

B8
A8

NC NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C2419

0.047UF

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24

78
7

23

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24
27 78

23

24 27 78

23

7

23 24 27 78

23 24 27 78

24 27 78

D10

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78 22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2420

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2428

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<21>

C8

MEM_A_DQ<22>

C3

MEM_A_DQ<17>

C9

MEM_A_DQ<16>

E4

MEM_A_DQ<19>

E9

MEM_A_DQ<20>

D3

MEM_A_DQ<23>

E8

MEM_A_DQ<18>

C4

MEM_A_DQS_P<2>

D4

MEM_A_DQS_N<2>

B8
A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

1

CERM-X5R-1

MEM_A_A<0>

7

MEM_A_A<1>

7
78

MEM_A_A<2>MEM_A_A<2>

7

MEM_A_A<4>

7
27 78

MEM_A_A<3>

7
27 78

MEM_A_A<6>

7
27 78

MEM_A_A<5>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<7>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
78

MEM_A_A<11>

7
24 27

MEM_A_A<12>

7
24 27
78

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<1>

7
27 78

MEM_A_BA<0>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<1>

7

MEM_A_ZQ<11>

2

R2430

240

1%
1/20W
MF
201

1

C2437

0.47UF

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2429

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 78

23

23

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24

23

78
7
24 27

23

23 24 27 78

23 24 27 78

24 27 78

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2430

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2438

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<24>

C8

MEM_A_DQ<31>

C3

MEM_A_DQ<28>

C9

MEM_A_DQ<27>

E4

MEM_A_DQ<29>

E9

MEM_A_DQ<26>

D3

MEM_A_DQ<25>

E8

MEM_A_DQ<30>

C4

MEM_A_DQS_P<3>

D4

MEM_A_DQS_N<3>

B8
A8

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

1

C2439

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

D

21 23 24 25 26

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

24 27

78
7

24 27

78

7

24 27

78
7

24 27

78

C

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

1

C2447

0.47UF

20%

4V

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 78

MEM_A_A<1>

7

23 24

27 78

MEM_A_A<2>

7

23 24

27 78

MEM_A_A<4>

7

23 24

27 78

MEM_A_A<3>

7

23 24

27 78

MEM_A_A<6>

7

23 24

27 78

MEM_A_A<5>

7

23 24

27 78

MEM_A_A<8>

7

23 24

27 78

MEM_A_A<7>

7

23 24

27 78

MEM_A_A<9>

7

23 24

27 78

B

MEM_A_A<10>

7

23 24

27 78

MEM_A_A<11>

7

23 24

27 78

MEM_A_A<12>

7

23 24

27 78

MEM_A_A<13>

7

23 24

27 78

MEM_A_A<14>

7

23 24

27 78

MEM_A_A<15>

7

23 24

27 78

MEM_A_BA<1>

7

23 24

27 78

MEM_A_BA<0>

7

23 24

27 78

MEM_A_BA<2>

7

23 24

27 78

MEM_A_RAS_L

7

23 24

27 78

MEM_A_CAS_L

7

23 24

27 78

MEM_A_WE_L

7

23 24

27 78

MEM_A_ODT<1>

7

24 27

78

MEM_A_ZQ<12>

2

R2440

240

1%
1/20W
MF
201

1

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

22 23 24 25 26 71 75 78

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2440

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 46 70
78

B10

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

N10

L10

C2

VDDQ

E3

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2448

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2449

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>

NC

MEM_A_CS_L<1>
MEM_A_CKE<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

7

23 78

23 24

23 24

23 24

23 24

7

23 78

7

23 78

23 24
27 78

23

7
23 78

7

23 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24

7

24 27

78

23
7
24 27 78
7

24 27
78

23 24 27 78

23 24 27 78

24 27 78

7

7
78

7

7
27 78

7
27 78

7
27 78

7
27 78

7
78

7
24 27

7

7

7

7
27 78

78
7
24 27

7

7

7

2

R2450

240

1%
1/20W
MF
201

1

C2457

0.47UF

20%

CERM-X5R-1

201

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_BA<1>
MEM_A_BA<0>
MEM_A_BA<2>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_ODT<1>
MEM_A_ZQ<13>

PP1V35_S3_MEM

1

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

w w w . c h i n a f i x . c o m

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78 22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2450

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2458

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<41>

C8

MEM_A_DQ<40>

C3

MEM_A_DQ<43>

C9

MEM_A_DQ<42>

E4

MEM_A_DQ<47>

E9

MEM_A_DQ<46>

D3

MEM_A_DQ<45>

E8

MEM_A_DQ<44>

C4

MEM_A_DQS_P<5>

D4

MEM_A_DQS_N<5>

B8
A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

J2

B2

A2

1

1

C2459

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

23 24 27 78

25 26
21 23 24

23 24 27 78

23 24

23 24

7

23 78

23 24

7

23 78

23 24

23 24

23 24

27 78

23
24

23
7
23 78

7

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24

78
27

23

24
7

24 27 78

23

7

23 24 27 78

23 24 27 78

24 27 78

C2467

CERM-X5R-1

MEM_A_A<0>

7
23 24 27 78

MEM_A_A<1>

7

MEM_A_A<2>

7

MEM_A_A<4>

7
27 78

MEM_A_A<3>

7
27 78

MEM_A_A<6>
MEM_A_A<5>

7
27 78

MEM_A_A<8>
MEM_A_A<7>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
27 78

MEM_A_A<11>

7
78

MEM_A_A<12>

7
24 27

MEM_A_A<13>
MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<1>

7
27 78

MEM_A_BA<0>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<1>

7

MEM_A_ZQ<14>

2

R2460

240

1%
1/20W
MF
201

1

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2460

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2468

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<49>

C8

MEM_A_DQ<48>

C3

MEM_A_DQ<51>

C9

MEM_A_DQ<50>

E4

MEM_A_DQ<55>

E9

MEM_A_DQ<54>

D3

MEM_A_DQ<53>

E8

MEM_A_DQ<52>

C4

MEM_A_DQS_P<6>

D4

MEM_A_DQS_N<6>

B8
A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

1

MEM_A_A<0>

7

MEM_A_A<1>

7
78

MEM_A_A<2>

7

MEM_A_A<4>

7
27 78

MEM_A_A<3>

7
27 78

MEM_A_A<6>

7
27 78

MEM_A_A<5>

7
27 78

MEM_A_A<8>

7
27 78

MEM_A_A<7>

7
27 78

MEM_A_A<9>

7
27 78

MEM_A_A<10>

7
27 78

MEM_A_A<11>

7
24 27
78

MEM_A_A<12>

7
24 27
78

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<1>

7
27 78

MEM_A_BA<0>

7
27 78

MEM_A_BA<2>

7
24 27
78

MEM_A_RAS_L

7
24 27 78

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<1>

7

MEM_A_ZQ<15>

2

R2470

240

1%
1/20W
MF
201

1

C2477

0.47UF

CERM-X5R-1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2469

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

23 24 27 78

23 24 27

23 24 27 78

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23

23

23 24 27 78

23 24 27 78

23 24 27 78

23 24

23 24
78
27

23

24
7

24 27 78

23

7

23 24 27 78

23 24 27 78

24 27 78

PP0V75_S3_MEM_VREFDQ_A

22 23 24 71 75 78

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2470

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2478

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<57>

C8

MEM_A_DQ<56>

C3

MEM_A_DQ<59>

C9

MEM_A_DQ<58>

E4

MEM_A_DQ<63>

E9

MEM_A_DQ<62>

D3

MEM_A_DQ<61>

E8

MEM_A_DQ<60>

C4

MEM_A_DQS_P<7>

D4

MEM_A_DQS_N<7>

B8
A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

1

1

C2479

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

21 23 24 25 26

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

7

23 78

B

7

23 78

7

23 78

7

23 78

7

24 27

78
7

24 27

78

7

24 27

78
7

24 27

78

A

PP1V35_S3_MEM

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2400

C2440

C2401

2.2UF

X5R-CERM

C2441

2.2UF

X5R-CERM

22 23 24 25 26 46 70 78

1

C2410

2.2UF

20%
10V

2

X5R-CERM

402

1

C2450

2.2UF

20%
10V

2

X5R-CERM

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

SIZE

A

D

SYNC_MASTER=J15_MLB

1

C2411

20%
10V

2

402

1

C2451

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2420

2.2UF

X5R-CERM

C2460

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2421

2.2UF

X5R-CERM

C2461

2.2UF

X5R-CERM

1

C2430

20%
10V

2

402

1

C2470

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2431

20%
10V

2

402

1

C2471

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

1

C2403

20%
10V

402

20%
10V

402

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

1

1

C2443

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

1

C2404

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2444

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2405

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2445

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2413

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2453

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2414

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2454

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2415

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2455

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2423

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2463

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2424

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2464

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2425

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2465

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2433

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2473

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2434

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2474

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2435

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2475

0.1UF

10%

6.3V

2

CERM-X5R
0201

PAGE TITLE

DDR3 SDRAM Bank A (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

24 OF 118

SHEET

24 OF 82

124578

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

1

C2507

0.47UF

20%

4V

CERM-X5R-1

MEM_B_A<0>

7

25 26

27 78

MEM_B_A<1>

7

25 26

D

27 78

MEM_B_A<2>

7

25 26

27 78

MEM_B_A<3>

7

25 26

27 78

MEM_B_A<4>

7

25 26

27 78

MEM_B_A<5>

7

25 26

27 78

MEM_B_A<6>

7

25 26

27 78

MEM_B_A<7>

7

25 26

27 78

MEM_B_A<8>

7

25 26

27 78

MEM_B_A<9>

7

25 26

27 78

MEM_B_A<10>

7

25 26

27 78

MEM_B_A<11>

7

25 26

27 78

MEM_B_A<12>

7

25 26

27 78

MEM_B_A<13>

7

25 26

27 78

MEM_B_A<14>

7

25 26

27 78

MEM_B_A<15>

7

25 26

27 78

MEM_B_BA<0>

7

25 26

27 78

MEM_B_BA<1>

7

25 26

27 78

MEM_B_BA<2>

7

25 26

27 78

MEM_B_RAS_L

7

25 26

27 78

MEM_B_CAS_L

7

25 26

27 78

MEM_B_WE_L MEM_B_WE_L

7

25 26

27 78

MEM_B_ODT<0>

7

25 27

78

MEM_B_ZQ<0>

2

C

R2500

240

1%
1/20W
MF
201

1

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

22 23 24 25 26 71 75 78

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2500

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 46 70
78

B10

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

N10

L10

C2

VDDQ

E3

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2508

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2509

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<6>
MEM_B_DQ<1>
MEM_B_DQ<3>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<4>
MEM_B_DQ<7>
MEM_B_DQ<0>

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

NC

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

25 26 27 78

25 26 27

25 26 27 78

25 26

25 26

7

26 78

25 26

25 26

25 26

25 26

25 26

27 78

25
26

25

25 26 27 78

25 26 27 78

25 26 27 78

25 26

25 26
78
27

25

25
7

25 27 78

25

7

25 26 27 78

25 26 27 78

25 27 78

7

7
78

7

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
78

7
26 27

7

7

7

7
27 78

7
27 78

7
26 27
78

7
26 27 78

7

7

7

2

1

C2517

0.47UF

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_ODT<0>
MEM_B_ZQ<1>

R2510

240

1%
1/20W
MF
201

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2510

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

J2

B2

A2

1

1

C2518

0.047UF

10%

6.3V
X5R

H2

201

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<14>

C8

MEM_B_DQ<9>

C3

MEM_B_DQ<11>

C9

MEM_B_DQ<13>

E4

MEM_B_DQ<10>

E9

MEM_B_DQ<12>

D3

MEM_B_DQ<15>

E8

MEM_B_DQ<8>

C4

MEM_B_DQS_P<1>

D4

MEM_B_DQS_N<1>

B8
A8

NC NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C2519

0.047UF

10%

6.3V

2

2

X5R
201

25 26 27 78

25 26 27

25 26 27 78

25 26

25 26

25 26

25 26

25 26

25 26

25 26

25 26
27 78

25

25

25 26 27 78

25 26 27 78

25 26 27 78

25 26

25 26
78
27

25

25
7

25 27 78

25

7

25 26 27 78

25 26 27 78

25 27 78

D10

C2527

CERM-X5R-1

MEM_B_A<0>

7

MEM_B_A<1>

7
78

MEM_B_A<2>

7

MEM_B_A<3>

7
27 78

MEM_B_A<4>

7
27 78

MEM_B_A<5>

7
27 78

MEM_B_A<6>

7
27 78

MEM_B_A<7>

7
27 78

MEM_B_A<8>

7
27 78

MEM_B_A<9>

7
27 78

MEM_B_A<10>

7
78

MEM_B_A<11>

7
26 27

MEM_B_A<12>

7
26 27
78

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<0>

7
27 78

MEM_B_BA<1>

7
27 78

MEM_B_BA<2>

7
26 27
78

MEM_B_RAS_L

7
26 27 78

MEM_B_CAS_L

7

7

MEM_B_ODT<0>

7

MEM_B_ZQ<2>

2

R2520

240

1%
1/20W
MF
201

1

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2520

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2528

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<18>

C8

MEM_B_DQ<20>

C3

MEM_B_DQ<19>

C9

MEM_B_DQ<16>

E4

MEM_B_DQ<23>

E9

MEM_B_DQ<21>

D3

MEM_B_DQ<22>

E8

MEM_B_DQ<17>

C4

MEM_B_DQS_P<2>

D4

MEM_B_DQS_N<2>

B8
A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

1

CERM-X5R-1

MEM_B_A<0>

7

MEM_B_A<1>

7
78

MEM_B_A<2>

7

MEM_B_A<3>

7
27 78

MEM_B_A<4>

7
27 78

MEM_B_A<5>
MEM_B_A<6>

7
27 78

MEM_B_A<7>

7
27 78

MEM_B_A<8>

7
27 78

MEM_B_A<9>

7
27 78

MEM_B_A<10>

7
78

MEM_B_A<11>

7
26 27

MEM_B_A<12>

7
26 27
78

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<0>

7
27 78

MEM_B_BA<1>

7
27 78

MEM_B_BA<2>
MEM_B_RAS_L

MEM_B_CAS_L

7

MEM_B_WE_L

7

MEM_B_ODT<0>

7

MEM_B_ZQ<3>

2

R2530

240

1%
1/20W
MF
201

1

C2537

0.47UF

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2529

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

25 26 27 78

25 26 27

25 26 27 78

25 26

25 26

7

26 78

25 26

25 26

25 26

25 26

25 26
27 78

25

25

25 26 27 78

25 26 27 78

25 26 27 78

25 26

25 26

7

25 27 78

7

25 27

78

25 26 27 78

25 26 27 78

25 27 78

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2530

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2538

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<27>

C8

MEM_B_DQ<25>

C3

MEM_B_DQ<26>

C9

MEM_B_DQ<29>

E4

MEM_B_DQ<30>

E9

MEM_B_DQ<28>

D3

MEM_B_DQ<31>

E8

MEM_B_DQ<24>

C4

MEM_B_DQS_P<3>

D4

MEM_B_DQS_N<3>

B8
A8

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

1

C2539

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

D

21 23 24 25 26

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

25 27

78
7

25 27

78

7

25 27

78
7

25 27

78

C

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

1

C2547

0.47UF

20%

4V

CERM-X5R-1

MEM_B_A<0>

7

25 26

27 78

MEM_B_A<1>

7

25 26

27 78

MEM_B_A<2>

7

25 26

27 78

MEM_B_A<3>

7

25 26

27 78

MEM_B_A<4>

7

25 26

27 78

MEM_B_A<5>

7

25 26

27 78

MEM_B_A<6>

7

25 26

27 78

MEM_B_A<7>

7

25 26

27 78

MEM_B_A<8>

7

25 26

27 78

MEM_B_A<9>

7

25 26

27 78

B

MEM_B_A<10>

7

25 26

27 78

MEM_B_A<11>

7

25 26

27 78

MEM_B_A<12>

7

25 26

27 78

MEM_B_A<13>

7

25 26

27 78

MEM_B_A<14>

7

25 26

27 78

MEM_B_A<15>

7

25 26

27 78

MEM_B_BA<0>

7

25 26

27 78

MEM_B_BA<1>

7

25 26

27 78

MEM_B_BA<2>

7

25 26

27 78

MEM_B_RAS_L

7

25 26

27 78

MEM_B_CAS_L

7

25 26

27 78

MEM_B_WE_L

7

25 26

27 78

MEM_B_ODT<0>

7

25 27

78

MEM_B_ZQ<4>

2

R2540

240

1%
1/20W
MF
201

1

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

22 23 24 25 26 71 75 78

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2540

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 46 70
78

B10

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

N10

L10

C2

VDDQ

E3

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2548

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2549

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>

MEM_B_DQS_P<4>
MEM_B_DQS_N<4>

NC

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

25 26 27 78

25 26 27

25 26 27 78

7

26 78

25 26

25 26

25 26

25 26

25 26

25 26

25 26
27 78

25

25

7

25 26 27 78

25 26 27 78

25 26 27 78

25 26

25 26
78
27

25

25
7

25 27 78

25

7

25 26 27 78

25 26 27 78

25 27 78

7

7
78

7

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
27 78

7
78

7
26 27

7
26 27
78

7

7

7
27 78

7
27 78

7
26 27
78

7
26 27 78

7

7

7

2

R2550

240

1%
1/20W
MF
201

1

C2557

0.47UF

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_ODT<0>
MEM_B_ZQ<5>

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

w w w . c h i n a f i x . c o m

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2550

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2558

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<40>

C8

MEM_B_DQ<41>

C3

MEM_B_DQ<42>

C9

MEM_B_DQ<43>

E4

MEM_B_DQ<44>

E9

MEM_B_DQ<45>

D3

MEM_B_DQ<46>

E8

MEM_B_DQ<47>

C4

MEM_B_DQS_P<5>

D4

MEM_B_DQS_N<5>

B8
A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

J2

B2

A2

1

1

C2559

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

25 26 27 78

25 26 27

25 26 27 78

25 26

25 26

25 26

25 26

25 26

25 26

25 26

25 26
27 78

25

25

25 26 27 78

25 26 27 78

25 26 27 78

25 26

25 26
78
27

25

25
7

25 27 78

25

7

25 26 27 78

25 26 27 78

25 27 78

C2567

CERM-X5R-1

MEM_B_A<0>

7

MEM_B_A<1>

7
78

MEM_B_A<2>

7

MEM_B_A<3>

7
27 78

MEM_B_A<4>

7
27 78

MEM_B_A<5>

7
27 78

MEM_B_A<6>

7
27 78

MEM_B_A<7>

7
27 78

MEM_B_A<8>

7
27 78

MEM_B_A<9>

7
27 78

MEM_B_A<10>

7
78

MEM_B_A<11>

7
26 27

MEM_B_A<12>

7
26 27
78

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<0>

7
27 78

MEM_B_BA<1>

7
27 78

MEM_B_BA<2>

7
26 27
78

MEM_B_RAS_L

7
26 27 78

MEM_B_CAS_L

7

MEM_B_WE_L

7

MEM_B_ODT<0>

7

MEM_B_ZQ<6>

2

R2560

240

1%
1/20W
MF
201

1

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2560

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2568

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<48>

C8

MEM_B_DQ<49>

C3

MEM_B_DQ<50>

C9

MEM_B_DQ<51>

E4

MEM_B_DQ<52>

E9

MEM_B_DQ<53>

D3

MEM_B_DQ<54>

E8

MEM_B_DQ<55>

C4

MEM_B_DQS_P<6>

D4

MEM_B_DQS_N<6>

B8
A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

PP1V35_S3_MEM

1

CERM-X5R-1

MEM_B_A<0>

7

MEM_B_A<1>

7
78

MEM_B_A<2>

7

MEM_B_A<3>

7
27 78

MEM_B_A<4>

7
27 78

MEM_B_A<5>

7
27 78

MEM_B_A<6>

7
27 78

MEM_B_A<7>

7
27 78

MEM_B_A<8>

7
27 78

MEM_B_A<9>

7
27 78

MEM_B_A<10>

7
78

MEM_B_A<11>

7
26 27

MEM_B_A<12>

7
26 27
78

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<0>

7
27 78

MEM_B_BA<1>

7
27 78

MEM_B_BA<2>

7
26 27
78

MEM_B_RAS_L

7
26 27 78

MEM_B_CAS_L

7

MEM_B_WE_L

7

MEM_B_ODT<0>

7

MEM_B_ZQ<7>

2

R2570

240

1%
1/20W
MF
201

1

C2577

0.47UF

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2569

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

25 26 27 78

25 26 27

25 26 27 78

25 26

25 26

25 26

25 26

25 26

25 26

25 26

25 26
27 78

25

25

25 26 27 78

25 26 27 78

25 26 27 78

25 26

25 26
78
27

25

25
7

25 27 78

25

7

25 26 27 78

25 26 27 78

25 27 78

PP0V75_S3_MEM_VREFDQ_B

22 25 26 71 75

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70
78

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2570

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2578

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<56>

C8

MEM_B_DQ<57>

C3

MEM_B_DQ<58>

C9

MEM_B_DQ<59>

E4

MEM_B_DQ<60>

E9

MEM_B_DQ<61>

D3

MEM_B_DQ<62>

E8

MEM_B_DQ<63>

C4

MEM_B_DQS_P<7>

D4

MEM_B_DQS_N<7>

B8
A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

1

1

C2579

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

21 23 24 25 26

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

7

26 78

B

7

26 78

7

26 78

7

26 78

7

25 27

78
7

25 27

78

7

25 27

78
7

25 27

78

PP1V35_S3_MEM

22 23 24 25 26 46 70 78

A

C2500

2.2UF

X5R-CERM

C2540

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2501

2.2UF

X5R-CERM

C2541

2.2UF

X5R-CERM

1

C2510

20%
10V

2

402

1

C2550

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2511

20%
10V

2

402

1

C2551

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2520

2.2UF

X5R-CERM

C2560

2.2UF

X5R-CERM

1

C2521

20%
10V

2

402

1

C2561

20%
10V

2

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2530

20%
10V

2

402

1

C2570

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2531

20%
10V

2

402

1

C2571

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

1

C2503

20%
10V

402

20%
10V

402

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

1

1

C2543

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

1

C2504

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2544

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2505

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2545

0.1UF

10%

6.3V

2

CERM-X5R
0201

6 3

1

C2513

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2553

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2514

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2554

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2515

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2555

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2523

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2563

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2524

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2564

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2525

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2565

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2533

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2573

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2534

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2574

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2535

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2575

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_MASTER=J15_MLB

PAGE TITLE

DDR3 SDRAM Bank B (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

25 OF 118

SHEET

25 OF 82

124578

SIZE

A

D