Apple A1297 K17 Schematics

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

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BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

SCHEM,ANGEL_ISLAND,MLB,K17

Rev.A 02/23/10

ALIASES RESOLVED

1 OF 103

1 OF 132

2009-05-19

03/26/2009

48

45

K20A_MLB

Front Flex Support

03/26/2009

47

44

K20A_MLB

PROJECT SPECIFIC CONNS

06/09/2009

46

43

K17_WFERRY

External USB Connectors

03/26/2009

45

42

K20A_MLB

SATA Connectors

07/08/2009

43

41

K18_MLB

FireWire Ports

03/26/2009

42

40

K20A_MLB

FireWire Port Power

03/26/2009

41

39

K20A_MLB

FireWire LLC/PHY (FW643)

06/09/2009

40

38

K17_WFERRY

Ethernet Connector

10/28/2009

39

37

K18_MLB

Ethernet PHY (Caesar II/IV)

10/09/2009

37

36

K18_MLB

USB HUB 2

10/07/2009

36

35

K18_MLB

USB HUB 1

06/09/2009

35

34

K17_WFERRY

ExpressCard Connector

06/19/2009

34

33

K18_MLB

X16/ALS/CAMERA CONNECTOR

06/09/2009

33

32

K17_WFERRY

FSB/DDR3/FRAMEBUF Vref Margining

10/14/2009

32

31

K18_MLB

CPU Memory S3 Support

06/09/2009

31

30

K17_WFERRY

DDR3 SO-DIMM Connector B

06/19/2009

30

29

K18_MLB

DDR3 Byte/Bit Swaps

05/13/2009

29

28

K17_REF

DDR3 SO-DIMM Connector A

06/17/2009

28

27

K17_REF

Chipset Support

05/19/2009

27

26

K17_REF

Clock (CK505)

06/22/2009

26

25

K18_MLB

eXtended Debug Port (XDP)

06/09/2009

25

24

K17_WFERRY

CPU/PCH GFX Decoupling

06/09/2009

24

23

K17_WFERRY

PCH Non-GFX Decoupling

03/26/2009

23

22

T22_MLB

PCH Grounds

10/02/2009

22

21

K18_MLB

PCH Power

11/13/2009

21

20

K18_MLB

PCH MISC

10/07/2009

20

19

K18_MLB

PCH PCI/FlashCache/USB

06/09/2009

19

18

K17_WFERRY

PCH DMI/FDI/Graphics

08/24/2009

18

17

K17_REF

PCH SATA/PCIE/CLK/LPC/SPI

06/24/2009

17

16

K17_REF

CPU Non-GFX Decoupling (2 of 2)

06/09/2009

16

15

K17_WFERRY

CPU Non-GFX Decoupling (1 of 2)

04/29/2009

15

14

K17_REF

CPU Grounds

06/09/2009

14

13

K17_WFERRY

CPU Power (2 of 2)

06/09/2009

13

12

K17_WFERRY

CPU Power (1 of 2)

04/29/2009

12

11

K17_REF

CPU DDR3 Interfaces

10/14/2009

11

10

K18_MLB

CPU Clock/Misc/JTAG

06/09/2009

10

9

K17_WFERRY

CPU DMI/PEG/FDI/RSVD

06/17/2009

9

8

K17_REF

Signal Aliases

(MASTER)

8

7

(MASTER)

Power Aliases

06/17/2009

7

6

K17_REF

Functional / ICT Test

06/09/2009

5

K17_WFERRY

BOM Configuration

03/26/2009

4

K20A_MLB

Revision History

03/26/2009

3

K20A_MLB

Revision History

03/26/2009

2

K20A_MLB

Revision History

90

K20A_MLB

98

03/26/2009

LCD Backlight Support

89

K17_VEMURI

97

12/16/2009

LCD Backlight Driver (MC34845)

88

K17_REF

96

06/24/2009

Graphics MUX (GMUX)

87

K17_REF

95

06/17/2009

1.05V GPU / 1V8 FB Power Supply

86

K20A_MLB

94

03/26/2009

DisplayPort Connector

85

K17_REF

93

06/17/2009

Muxed Graphics Support

84

K20A_MLB

90

03/26/2009

LVDS Display Connector

83

K17_WFERRY

89

06/09/2009

GPU (GT216) CORE SUPPLY

82

K18_MLB

88

06/29/2009

NV GT216 VIDEO INTERFACES

81

K18_MLB

87

07/01/2009

GT216 GPIOS & STRAPS

80

K18_MLB

86

06/29/2009

NV GT216 GPIO/MIO/MISC

79

GT216

85

03/26/2009

GDDR3 Frame Buffer B (Top)

78

GT216

84

03/26/2009

GDDR3 Frame Buffer A (Top)

77

K18_MLB

82

06/29/2009

NV GT216 FRAME BUFFER I/F

76

GT216

81

03/26/2009

NV GT216 CORE/FB POWER

75

K18_MLB

80

06/29/2009

NV GT216 PCI-E

74

K17_WFERRY

79

06/09/2009

Power Control

73

K17_WFERRY

78

06/09/2009

Power FETs

72

K17_WFERRY

77

06/09/2009

Misc Power Supplies

71

T22_MLB

76

03/26/2009

CPUVTT (1.05V) Power Supply

70

T22_MLB

75

03/26/2009

GFX IMVP VCore Regulator

69

K18_POWER

74

06/29/2009

CPU IMVP VCore Regulator

68

K17_REF

73

06/24/2009

1.5V DDR3 Supply

67

K20A_MLB

72

03/26/2009

5V / 3.3V Power Supply

66

K17_REF

70

04/29/2009

PBus Supply & Battery Charger

65

K17_REF

69

04/29/2009

DC-In & Battery Connectors

64

K17_REF

68

05/30/2009

AUDIO: JACK TRANSLATORS

63

K17_LENGO

67

11/24/2009

AUDIO: JACKS

62

K17_REF

66

05/30/2009

AUDIO:SPEAKER AMP

61

K17_REF

65

05/30/2009

AUDIO: HEADPHONE OUT

60

K17_REF

63

05/30/2009

AUDIO: LINE IN

59

K17_REF

62

05/30/2009

AUDIO:CODEC

58

K17_WFERRY

61

06/09/2009

SPI ROM

57

K17_CHENGD

60

07/08/2009

DEBUG SENSORS AND ADC

56

K20A_MLB

59

03/26/2009

Sudden Motion Sensor (SMS)

55

K17_WFERRY

58

06/09/2009

WELLSPRING 2

54

K17_WFERRY

57

06/09/2009

WELLSPRING 1

53

K20A_MLB

56

03/26/2009

Fan Connectors

52

K17_CHENGD

55

07/08/2009

Thermal Sensors

51

K17_CHENGD

54

06/04/2009

Current Sensing

50

K17_REF

53

06/17/2009

Current & Voltage Sensing

49

K17_WFERRY

52

05/20/2009

K17 SMBus Connections

48

T22_MLB

51

03/30/2009

LPC+SPI Debug Connector

47

K17_REF

50

06/17/2009

SMC Support

05/20/2009

K17_WFERRY

132

103

T57 Card Connector

06/17/2009

K17_REF

122

102

Current Sensing

06/17/2009

K17_REF

121

101

Ibex Peak-M Power Aliases

06/09/2009

K17_WFERRY

109

100

PCB Rule Definitions

06/17/2009

K17_REF

108

99

Project Specific Constraints

06/09/2009

K17_WFERRY

107

98

GPU (GT216) CONSTRAINTS

06/09/2009

K17_WFERRY

106

97

SMC Constraints

06/09/2009

K17_WFERRY

105

96

FireWire Constraints

06/09/2009

K17_WFERRY

104

95

Ethernet Constraints

06/17/2009

K17_REF

103

94

PCH Constraints 2

06/09/2009

K17_WFERRY

102

93

PCH Constraints 1

06/09/2009

K17_WFERRY

101

92

Memory Constraints

SCHEM,TREASURE_ISLAND,MLB,K17

Page

(.csa)

Date

SyncContents

06/09/2009

K17_WFERRY

100

91

CPU Constraints

Sync

Date

(.csa)

Page Contents

PCBF,ANGEL_ISLAND,MLB,K17

820-2849

1

CRITICAL

PCB

04/01/2008

1

K20_MLB

Table of Contents

SCHEM,ANGEL_ISLAND,MLB,K17

051-8503 CRITICAL

SCH

1

LAST_MODIFIED=Tue Feb 23 21:52:40 2010

TITLE=MLB

ABBREV=DRAWING

(.csa)

Sync

Date

ContentsPage

46

K17_WFERRY

49

06/09/2009

SMC

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

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B

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345678

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8 7 5 4 2 1

Bluetooth

PWR

IBEX PEAK-MPCH

Conns

Audio

POWER SUPPLY

PG 28

J3400

GB

Amps

U6200

J6950

U6100

USB

DC/BATT

SPI

TEMP SENSOR

FanADC

B,0 BSB

CONN

Boot ROM

Amp

U4900

U2600

PG 25

DDR3-1067/1333MHZ

2 UDIMMs

J2900

DIMM

PG 28,30

U8000

INTEL CPU

ARRANDALE

2.X GHZ

NV GT216

PRAPHICS

PG 9

PG 73

RTC

LPC

CLK

DMIFDI

PG 17

GPIO

PG 20 PG 18 PG 18

0 1

CTRL

BUFFER

SATA

PG 17

RGB OUT

PG 20

PG 17

PG 56

PG 17

SMC

Prt

PG 44

Ser

J5100

U4900

PG 51

FAN CONN AND CONTROL

J5650,5660

POWER SENSE

PG 44

PG 63

LPC Conn

Port80,serial

PG 46

8 9

13121011

J3401 J3401 J3401

USB

PG 33 PG 52

J5713

TRACKPAD/

KEYBOARD

(UP TO 14 DEVICES)

PG 19

J4600,J4610,4720

EXTERNAL

Connectors

SMB

PG 41

SMB

PG 17

PG 47

DIMM’s

2

HDA

TMDS OUT

PG 18

PG 17

Codec

PG 57

SpeakerLine In

PG 60PG 59

Amp

Line Out

U6610,6620,6630,6640,6650

U6500

HEADPHONE

Amp

J6780,6781,6782,6700,6750

PG 61

PCI

PCI-E

PG 19

3 4 5 6 7

JTAG

(UP TO 16 LINES)

PG 17

PCI-E

PG 17 PG 17

PEG

E-NET

J3500

EXPRESSCARD

CONN

PG 34

U3900

J4000

BCM5764M

PG 35

E-NET

Conn

PG 36

PG 37

U4100

PG 39

AirPort

FW643

Mini PCI-E

J4310

Conn

Misc

XDP CONN

E-NET

IR

INTEL

U1800

PG 17

PG 33

SPI

CAMERA

PG 33

U2700

CLOCK CK505

P8 26

1.05V/3GHZ.

J4500

Conn

HD

P8 40

SATA

P8 40

ODD

Conn

SATA

J4501

HDMI OUT

DVI OUT

DP OUT

LVDS OUT

CONN

J9000

DISPLAY PORT

PG 84

LVDS CONN

PG 71

J9400

PG 85

XP25-5

GMUX

U9600

SYNC_DATE=03/26/2009

Revision History

SYNC_MASTER=K20A_MLB

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

C

A

D

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Apple Inc.

PAGE

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A

B

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345678

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8 7 5 4 2 1

ADAPTER

P1V1GPU_EN

1.8V(R/H)

POK2

POK1

SMC_DCIN_ISENSE

K17 POWER SYSTEM ARCHITECTURE

A

PBUS SUPPLY/

VIN

R7020

VIN

VOUT

8A FUSE

DDRREG_EN

(PAGE 66)

PP5V_S0_FET

P1V5DDR_EN

Q7860

P5VS0_EN

PP3V3_S5

VOUT2

3.3V

EN2

(PAGE 65)

PP5V_S3

P1V8FB_PGOOD

S5 S3

PP5V_S3_DDRREG

DDRREG_PGOOD

ON

VOUT

SLG5AP020

ISL8009B

U7760

(PAGE 70)

PP1V2_GMUX_FET

P1V2GMUX_EN

PP1V2_ENET

Q7850

PM_ALL_GPU_PGOOD

U7980

EN

VIN

P1V2ENET_EN

VOUT

ISL8009B

U7710

(PAGE 70)

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

VIN

ISL8014

U7720

(PAGE 70)

PP3V3_FW_FET

Q4291

Q7830

P1V8S0_PGOOD

FW_PWR_EN

P1V8_S0_EN

PP3V3_S0_FET

A

PPVCORE_S0_GFX

V

P3V3S0_EN

EN

PP1V8_S0

P3V3S3_EN

P1V5_EXP_S0_EN

PP3V3_ENET

PP1V5_EXP_S0

Q7922

Q7810

PGOOD

VOUT

Q3810

P3V3S5_PGOOD

P3V3GPU_EN

PP3V3_S0_GPU

OUT

EN

VIN

PP3V3_S3

Q7870

PPVOUT_S0_LCDBKLT

U7300

TPS51116

U7801

PGOOD

PP1V5_S0

VOUT2

PP3V3_S5

EN1

VOUT1

(L/H)

5V

VIN

TPS51980

BKLT_PLT_RST_L

P3V3S5_EN

P5VS3_PGOOD

LCD_BKLT_EN

BKLT_EN

APP001

PGOOD1 PGOOD2

&&

VIN

GFX_DPRSLPVR

VR_ON

PFWBOOST

VOUT

GFXIMVP_ISENSE

TPS51981

SMC_GFX_VSENSE

V

R7540

DPRSLPVR

(PAGE 68)

U7500

Q4260

A

GFXIMVP_PGOOD

PGOOD

GFX_VR_EN

(PAGE 70)

SMC_ADAPTER_EN&&PM_SLP_S3_L

VOUT

PM_SLP_S5_L

Q9806

DDRREG_EN

P3V3S3_EN

SLP_S3#(P12)

PM_SLP_S4_L

P5VS3_EN

SLP_S4#(H7)

(PAGE 87)

PM_SLP_S3_L

U9700

ENA

P5VS3_EN

U7201

LTC1872

P1V1GPU_PGOOD

ISL6236

U9500

(PAGE 85)

(R/H)

PP1V8_S0GPU

PPVTT_S0_DDR_LDO

A

SMC_DDR_ISENSE

R7350

R5388

A

CPUIMVP_VR_ON

(PAGE 67)

SMC_CPU_DDR_VSENSE

U5440

V

PP1V5_S3

U7400

PPDDR_S3_REG

SMC_GPU_1V8_ISENSE

0.75V

DDRVTT_EN

1.103V(L/H)

VOUT1

PP1V1_S0GPU

VIN

VOUT2

1.5V

VR_ON

ISL9522

VOUT

VOUT1

EN1

P1V8FB_EN

PPVBAT_G3H_CHGR_R

VIN

R5413

U7790

VIN

1.05V AUX

VOUT

VIN

R7050

SMC_CPU_VSENSE

PPVCORE_S0_CPU

CPUIMVP_GOOD

CPU VCORE

VIN

GPUVCORE_EN

SMC_CPU_HI_ISENSE

GPUVCORE_PGOOD

SMC_CPU_FSB_ISENSE

PPCPUVTT_S0

R7640

U7600

TPS51513

CPUVTTS0_EN

CPUVTTS0_PGOOD

(PAGE 69)

A

1.05V

PP5V_S0_CPUVTTS0

(PAGE 45)

VIN

VOUT

EN

PGOOD

SMC_GPU_ISENSE

ISL6263C

GPU VCORE

PP5V_S3_GPUVCORE

VDD

F7041

SMC_GPU_VSENSE

PPVCORE_GPU

V

U5410

PGOOD

(PAGE 81)

A

PP3V42_G3H

PBUSVSENS_EN

P3V3S0_EN

DELAY

CPUVTTS0_EN

P5VS0_EN

RC

DELAY

P1V2GMUX_EN

P1V5DDR_EN

RC

P1V8S0_EN

PM_SLP_S3_L_R

R7978

(PAGE 17~22)

CPU

PWRGD(P12)

RSMRST_IN(P13)

PM_SLP_S5_L PM_SLP_S4_L

U1800

IBEX_PEAK_M

SLP_S5#(E4)

RC

DELAY

RC

P3V3S5_EN

SMC_PM_G2_EN

(PAGE 44)

(PAGE 86)

XP25-5

PL32A

CHGR_BGATE

(6 TO 8.4V)

PPVBATT_G3H_CONN

SMC_PBUS_VSENSE

(PAGE 64)

BATTERY CHARGER

V

PPBUS_G3H

SMC_BATT_ISENSE

ISL6259HRTZ

IN

VOUT

PM_ALL_GPU_PGOOD

TRST = 200mS

(PAGE 72)

ISL88042IRTEZ

U7971

ADJ1

PM_SLP_S3_L

SLP_S5_L(P95)

IMVP_VR_ON(P16)

99ms DLY

RSMRST_OUT(P15)

(P64)

PM_MEM_PWRGD

CPU_PWRGD

ACPRESENT

RSMRST#

IBEX PEAK M

SMC AVREF SUPPLY

U1800

(PAGE 17~22)

SM_DRAMPWROK

VCCCPUPWRGD

(PAGE 9~14)

RSMRST_PWRGD

SMC_ONOFF_L

SLP_S4_L(P94)

SLP_S3_L(P93)

S0PGOOD_PWROK

PP1V5_S0

PP1V05_S0

PP3V3_S0_PWRCTL

P1V8S0_PGOOD

P5VS3_PGOOD

ALL_SYS_PWRGD

SMC

Q7055

RC

PM_PCH_PWRGD

PS_PWRGD

PROCPWRGD

PLTRST#

SYS_RERST#

DRAMPWROK

PM_RSMRST_L

SMC_ADAPTER_EN

PLT_RERST_L

PWR_BUTTON(P90)

PWRBTN#

IMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

U1000

PM_PWRBTN_L

RES*

P17(BTN_OUT)

RESET*

SYSRST(PA2)

SMC_RESET_L

U2850

VR5020

VOUT

SMC_TPAD_RST_L

SMC_ONOFF_L

(PAGE 44)

U4900

U5001

PP3V3_S5_AVREF_SMC

3.425V G3HOT

ENABLE

(PAGE 45)

VIN

NCP303LSN

SMC PWRGD

U5000

U6990

(PAGE 63)

R6905

F7040

F6905 6A FUSE

DCIN(16.5V)

PPDCIN_G3H_OR_PBUS_R

VLDOIN

J6900

AC

U8900

U9600

PB16B

P1V1GPU_EN

GPUVCORE_ENEG_RAIL3_EN

Q5315

SMC_RESET_L

EG_RAIL4_EN

EG_RAIL1_EN EG_RAIL2_EN

SMC

LT3470A

PB18A

PB17B

EN2

P1V8_S0GPU_EN

P3V3GPU_EN

GMUX

PB17A

P60

U4900

DELAY

RST*

VCC

ADJ2

RC

DELAY

VR_ON

PGOOD

A

U7000

2S4P

J6950

PP3V3_S0

PPVBAT_G3H_CHGR_REG

SMC_CPU_ISENSE

SYNC_MASTER=K20A_MLB

Revision History

SYNC_DATE=03/26/2009

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8 7 5 4 2 1

02/23/10

csa. 5 Added K17_PVT BOM group

MLB_TI_IMVP65

Rev. A:

(For changes prior to Rev. A, refer to earlier schematics)

csa. 121 Changed ARB_ONLY sense Rs to XWs

csa. 74 Updated Symbol for U7400; new VPN is TPS51983

SYNC_DATE=03/26/2009

Revision History

SYNC_MASTER=K20A_MLB

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8 7 5 4 2 1

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants

Bar Code Labels / EEEE #’s

K17 BOM GROUPS

Alternate Parts

Module Parts

[EEEE_DCMT]

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE_DCMT

CRITICAL

1

826-4393

[EEEE_DCMV]

EEEE_DCMV

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL826-4393

1

PCBA,2.66GHZ,512HYN_VRAM,K17

K17_COMMON,CPU_2_66GHZ,FB_512_HYNIX,EEEE_DCMQ,K17_PVT

639-0970

BCM5764M,DCI,GMUX_VSYNC,CPUPOC_IMAX_40_50,PCH_NAND_3V3,CPUMEM_S0,EXT_HP_AMP,VFRQ_SLPS3,SMC_DEBUG_YES,DPMUX_EN_PLD,FB1V35,USBHUB_2061

K17_COMMON1

341S2616

IC,TP PSOC,K17,K18

U5701

1

CRITICAL

TPAD_PROG

U4800

CRITICAL

1

341S2384

IR,ENCORE II, CY7C63833-LFXC

IC,EFI ROM,K17

BOOTROM_PROG

1

U6100

CRITICAL341T0244

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

CRITICAL

BOOTROM_BLANK

1

U6100

335S0610

IC,SMC,K17

SMC_PROG

CRITICAL

1

U4900

341T0229

337S3849

1

CRITICAL

U1800

IBEX (HM55),SLGZS,PRQ,B3

343S0493

1

CRITICAL

U3900

BCM5764M

IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN

338S0753

1

CRITICAL

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

U4100

1

J3100

516S0805 CRITICAL

CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC

CPU_2_66GHZ

1

U1000

CRITICAL337S3848

ARD,SLBPE,PRQ,2.66,35W,C2,4M,BGA

CPU_2_4GHZ

CRITICAL

U1000

1

337S3846

ARD,SLBNA,PRQ,2.40,35W,C2,3M,BGA

CRITICAL

U8000

1

337S3839

IC,GPU,NV GT216 LP++,969BGA,40NM,A03

IC,SGRAM,GDDR3,32MX32,1GHZ,D-DIE,136 FBGA

U8400,U8450,U8500,U8550

VRAM_512_SAMSUNG

4

333S0533 CRITICAL

SMC_OSC_YES

U5010

197S0350 CRITICAL

1

OSC,XTAL,32.768KHZ,9-3.6V,12P SOIC,HF

U8400,U8450,U8500,U8550

VRAM_512_HYNIX

333S0535

4

CRITICAL

IC,SDRAM,GDDR3,32MX32,900MHZ,TIVA,HF

CPU_2_53GHZ

CRITICAL

1

U1000

337S3847

ARD,SLBPF,PRQ,2.53,35W,C2,3M,BGA

085-1425

K17_DEVEL_ENG

K17 MLB DEVELOPMENT

ALL

Murata alt to Samsung

138S0603 138S0602

152S0896 152S0518

ALL

MAG LAYERS ALT TO CYNTEC

155S0457 155S0329

ALL

MAG LAYERS ALT TO MURATA

516S0805516S0806

ALL

FOXCONN ALT TO MOLEX

138S0602138S0612

Taiyo Yuden alt to Samsung

ALL

353S2603

ALL

353S2805

Fairchild 8 in alt to 6 in wafer

127S0060

ALL

127S0111

Rohm alt to Kemet

NEC/TOKIN alt to Sanyo

128S0218128S0299

ALL

152S0915 152S0796

ALL

MAG LAYERS ALT TO CYNTEC

Delta alt to TDK Magnetics

ALL

157S0058 157S0055

U9600

GMUX_PROG

1

341S2568 CRITICAL

IC,CPLD,LATTICE,132CSBGA,K17MLB

338S0563

IC,SMC,HS8/2117,9MMX9MM,TLP

SMC_BLANK

CRITICAL

1

U4900

ALL

337S3839337S3808

GT216 A02 alt to A03 part

ALL

376S0887 376S0749

Fairchild alt to Vishay

U3990

1

CRITICAL341S2731

IC,1MBIT,SPI FLASH K17/K18

336S0025

GMUX_5K_BLANK

U9600

1

CRITICAL

IC,XP2-5,HF,CPLD,BLANK

EEEE_DCMR

[EEEE_DCMR]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

826-4393

XDP,XDP_CONN,XDP_CPU_BPM,XDP_NORMAL,XDP_PCH

CALPELLA_XDP

VRAM4,VRAM_512_HYNIX

FB_512_HYNIX

VRAM4,VRAM_512_SAMSUNG

FB_512_SAMSUNG

EEEE_DCMQ

[EEEE_DCMQ]

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM

K17_PVT

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

K17_PROGPARTS

ARB_ONLY,CALPELLA_XDP,DEBUG_ADC,LPCPLUS,VREFMRGN,GMUX_JTAG_CONN,EFI_DEBUG,BMON_ENG,SMC_OSC_YES

K17_DEVEL_ENG

GPUVID_0P90V,BKLT_PWR_PBUS,DP_ESD,DP_CA_DET_EG_PLD,SMC_EXCARD_NOT,GPU_SS_INT,RDRV_8515_A2,GMUXPLL_3V3,HUB1_2NONREM,HUB2_2NONREM,RAIL_MON

K17_COMMON2

ALTERNATE,COMMON,K17_COMMON1,K17_COMMON2,K17_PROGPARTS

K17_COMMON

PCBA,2.53GHZ,512HYN_VRAM,K17

K17_COMMON,CPU_2_53GHZ,FB_512_HYNIX,EEEE_DCMR,K17_PVT

639-0971

PCBA,2.66GHZ,512SAM_VRAM,K17

K17_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,EEEE_DCMT,K17_PVT

639-0972

PCBA,2.53GHZ,512SAM_VRAM,K17

K17_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,EEEE_DCMV,K17_PVT

639-0973

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

BOM Configuration

5 OF 132 5 OF 103

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

J3500 (EXPRESS CARD CONN)

J6782 (RIGHT & SUB SPEAKER)

J5660 (RIGHT FAN CONN)

J3401, J3402 (AIRPORT/BT/CAMERA CONN)

per Fan

4 TPs

J5650 (LEFT FAN CONN)

J4800 (FRONT CABLE CONN)

4 TPs

5 TPs

FUNC_TEST

4 TPs

NO_TEST

NC NO_TESTs

2 TP needed

J6900 (DC POWER CONN)

J6950 (MAIN BATT CONN)

J6995 (BAT LED CONN)

5 TPs

2 TPs

5 TPs

J5800 (IPD FLEX CONN)

CPU NO_TESTs

NO_TEST

2 TPs

J5815 (KBD BACKLIGHT CONN)

4 TPs

3 TPs

FUNC_TEST

ICT Test Points

NO_TEST

6 TPs

NC NO_TESTs

3 TPs

USB PORTS

per Fan

J5713 (KEY BOARD CONN)

NO_TEST

NC NO_TESTs

J9000 (LVDS CONN)

J4501 (SATA HDD CONN)

FUNC_TEST

J4500 (SATA ODD CONN)

J6780 (MIC CONN)

J6781 (LEFT SPEAKER)

3 TPs

2 TPs

POWER RAILS

FUNC_TEST

NC NO_TESTs

Functional Test Points

I1000 I1001 I1002

I1003

I1004

I1005

I1006

I1007

I1008

I1009

I1010 I1011 I1012

I1013

I1014

I1015 I1016 I1017 I1018 I1019 I1020

I1021

I1022

I1024

I1025

I1026

I1027

I1028

I1029

I1031

I1032

I1033

I1034

I1035

I1038 I1039 I1040

I1042 I1043 I1044

I1046 I1047 I1048

I1050

I1051

I1052

I1053

I1054

I1055

I1056

I1057

I1058

I1059

I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1067 I1068 I1069

I1070

I1071

I1072

I1073

I1074

I1075 I1076 I1077

I1078

I1079

I1080

I1081

I1082 I1083 I1084

I1085 I1086 I1087

I1088

I1089

I1090 I1091

I1092 I1093 I1094

I1095 I1096

I1097

I1098

I1099 I1100 I1101

I1102

I1103

I1104 I1105

I1106

I1107

I1108 I1109 I1110 I1111 I1112 I1113 I1114 I1115

I1116

I1117

I1118 I1119 I1120

I1121

I1122

I1123 I1124 I1125

I1126

I1127

I1128 I1129 I1130

I1131 I1132

I1134

I1135

I1136

I1137

I1140

I1141

I1142

I1143

I1145 I1146

I1148

I1149

I1150

I1151 I1152

I1156

I1160 I1161

I1273

I1288

I1296

I1297

I1436 I1437

I1438 I1439

I1440

I1441 I1442

I1443

I1444 I1445

I1446

I1447 I1448

I1449

I1450

I1451

I557

I558

I559

I600

I602 I603

I604

I605

I606

I607

I610

I611

I612

I614

I618

I625

I626

I627

I636

I637

I638

I639

I640

I709

I714

I720 I722

I723

I724

I725 I726 I727

I728

I729

I730

I731

I732

I733

I734

I735 I736 I737

I738

I739

I740 I741 I742 I743 I744 I751 I752

I756

I761 I762 I763 I764 I765

I766

I767

I768

I769

I770

I771

I772

I774

I985

I986

I987

I988

I989 I990

I991

I992

I993

I994

I995 I996 I997 I998

Functional / ICT Test

SYNC_DATE=06/17/2009

SYNC_MASTER=K17_REF

NC_FW643_TDI NC_FW643_TDI

MAKE_BASE=TRUE

TRUE

NC_FW643_AVREG

MAKE_BASE=TRUE

TRUE

USB_LT3_N

TRUE

WS_KBD20

WS_KBD19

TRUE

PP5V_S3_RTUSB_C_F

TRUE

NC_PCH_LVDS_VBG

NC_HDA_SDIN2 NC_HDA_SDIN3

TRUE

NC_HDA_SDIN3

MAKE_BASE=TRUE

TP_PCI_AD<31..0> TP_PCI_C_BE_L<3..0>

NC_PCI_GNT2_L

NC_PCI_PME_L

PP3V3_S3_BT_F

TRUE

PCH_VSS_NCTF<1>

TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

PCIE_CLK100M_EXCARD_CONN_P

PLT_RESET_SWITCH_L

TRUE

SMBUS_PCH_CLK

PP3V3_S0

TRUE

PPVCORE_S0_CPU

TRUE

CONN_USB2_BT_P

SMBUS_SMC_A_S3_SCL

TRUE

INT_MIC_SHIELD

PP1V05_S0GPU

TRUE

PP1V8_S0GPU_ISNS

TRUE

PPVCORE_GPU

TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PP1V5_S0_EXCARD_SWITCH

TRUE

PP3V3_S3

TRUE

EXCARD_CLKREQ_CONN_L

TRUE

FAN_LT_PWM

TRUE

MAKE_BASE=TRUE

NC_SMC_P92TP_SMC_P92

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_DDC_DATA

TRUE

PPVOUT_S0_LCDBKLT

TRUE

INT_MIC_N

TRUE

INT_MIC_P

TRUE MAKE_BASE=TRUE

NC_PCI_GNT1_L

NC_LVDS_EG_BKL_PWM

TP_LVDS_EG_B_CLK_P

TP_LVDS_EG_B_CLK_N

TP_LVDS_IG_B_CLKN

NC_PCH_NC2

NC_PCH_NC1

NC_PCI_GNT2_L

MAKE_BASE=TRUE

TRUE

SMC_ONOFF_L

WS_KBD17

TRUE

EXCARD_CPUSB_L

TRUE

PPVP_FW

TRUE

NC_USB_EXTDP

MAKE_BASE=TRUE

PCH_VSS_NCTF<9>

TRUE

PCIE_EXCARD_D2R_N

SATA_HDD_R2D_P

TRUE

NC_PCIE_PE5_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CP

TRUE

NC_PCIE_PE6_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE6_D2RP

MAKE_BASE=TRUE

NC_PCIE_PE7_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE6_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE7_R2D_CP

MAKE_BASE=TRUE

NC_PCIE_PE7_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_D2RN

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CP

NC_PCIE_PE5_D2RN

NC_PCIE_PE5_R2D_CN

NC_PCIE_PE5_D2RP

NC_PCIE_PE6_R2D_CN

NC_PCIE_PE6_D2RP

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP

NC_PCIE_PE6_D2RN

NC_PCIE_PE7_R2D_CP

NC_PCIE_PE7_R2D_CN

NC_PCIE_PE8_R2D_CP

NC_PCIE_PE8_R2D_CN

NC_PCIE_PE8_D2RP

NC_PCIE_PE8_D2RN

TRUE

PP5V_S0

TRUE

USB_CAMERA_CONN_P

TRUE

PP5V_S3_RTUSB_B_F

PP5V_S0_HDD_FLT

TRUE

ISSP_SDATA_P1_0

NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE

LVDS_CONN_A_DATA_P<0>

TP_CPU_RSVD_NCTF<8..5>

NC_CRT_IG_BLUE

NC_CRT_IG_RED

NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_DATA

TRUE

WS_KBD9 WS_KBD10

TRUE

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_VSYNC

TRUE

WS_KBD12

WS_KBD22

TRUE

PP3V3_S3

TRUE

WS_KBD21

USB2_LT1_P

TRUE

SATA_HDD_R2D_N

TRUE

LED_RETURN_3

TRUE

LVDS_CONN_B_DATA_P<1>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<27..26>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<58..45>

PP3V42_G3H

TRUE

PP18V5_S3

TRUE

PPDCIN_G3H

PPCPUVTT_S0

TRUE

WS_KBD14

USB_LT2_N

TRUE

PM_CLKRUN_L

TRUE

LPC_AD<0..3>

TRUE

LVDS_CONN_B_DATA_N<0>

PP5V_SW_ODD

TRUE

USB_CAMERA_CONN_N

LPC_CLK33M_LPCPLUS

TRUE

PCIE_AP_D2R_N

PP5V_S3_RTUSB_A_F

TRUE TRUE

USB2_LT1_N

TRUE

LPCPLUS_RESET_L

TRUE

SPI_ALT_MISO

TRUE

WS_KBD2

WS_KBD1

TRUE

LED_RETURN_5

TRUE

WS_KBD8

TRUE

WS_KBD3

TRUE

WS_KBD13

TRUE

WS_KBD11

TRUE

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_A_CLK_F_P

TRUE

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<1>

TRUE TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_CLK_F_N LED_RETURN_1

TRUE

LED_RETURN_2

TRUE

LED_RETURN_4

TRUE

SMC_ODD_DETECT

TRUE

SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N

TRUE

PP5V_S3_IR_R

TRUE

WS_KBD23

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD7

SMC_RESET_L

TRUE

SPI_ALT_MOSI

TP_CPU_RSVD<2..1>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<2..1>

TP_CPU_RSVD<24..15>

TP_CPU_RSVD<27..26>

TP_CPU_RSVD<43..32>

TP_CPU_RSVD<58..45>

TP_CPU_RSVD<65..62>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD_NCTF<8..5>

TRUE

WS_LEFT_OPTION_KBD

LVDS_CONN_B_DATA_N<2>

TRUE

LVDS_CONN_A_DATA_N<2>

PP3V3_SW_LCD

TRUE

LVDS_CONN_BKL_SYNC

TRUE

PM_SYSRST_L

SMC_TCK

TRUE

LPC_PWRDWN_L

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_CLK

TRUE

SPIROM_USE_MLB

TRUE

SMC_TX_L

TRUE

SMC_MD1

SMC_TRST_L

TRUE

SMC_TDO

TRUE

SMC_TMS

TRUE

LPC_FRAME_L

TRUE

PPVTTDDR_S3 PP1V8_GPUIFPX

TRUE

USB_LT3_P

TRUE

WS_KBD18

TRUE

SMC_RX_L

LPCPLUS_GPIO

TRUE TRUE

ISSP_SCLK_P1_1

NC_LVDS_IG_CTRL_CLK

TRUE

SYS_LED_ANODE

TRUE

KBDLED_ANODE

TRUE

SMC_KDBLED_PRESENT_L

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

NC_SMC_FAN_2_TACH

TRUE

NC_SMC_FAN_2_CTL

TRUE

NC_FW2_TPBN

NC_FW2_TPBP

TRUE

NC_FW2_TPBIAS

TRUE

NC_FW2_TPAP

TRUE TRUE

NC_FW2_TPAN

TRUE

NC_FW0_TPBN

NC_FW0_TPBP

TRUE

NC_FW0_TPAP NC_ESTARLDO_EN

TRUE

NC_ALS_GAIN

TRUE

NC_DP_IG_C_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_CTRL_CLK

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_MLN<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

NC_DP_IG_D_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_HPD

NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLP<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLN<3..0>TP_DP_IG_D_MLN<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXPNC_DP_IG_D_AUXP

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXN

NC_SDVO_TVCLKINP

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTNNC_SDVO_INTN

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTP

TRUE

MAKE_BASE=TRUE

NC_PCH_SSTNC_PCH_SST

TRUE

MAKE_BASE=TRUE

NC_PCH_NC1

TRUE

MAKE_BASE=TRUE

NC_PCH_NC5

MAKE_BASE=TRUE

TRUE

NC_PCH_TP19

TRUE

MAKE_BASE=TRUE

NC_PCH_NC3

TRUE

MAKE_BASE=TRUE

NC_PCH_NC2

TRUE

MAKE_BASE=TRUE

NC_PCH_NC4

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

TRUE

NC_PCH_TP15

MAKE_BASE=TRUE

TRUE

NC_PCH_TP16

MAKE_BASE=TRUE

TRUE

NC_PCH_TP17

MAKE_BASE=TRUE

TRUE

NC_PCH_TP18

MAKE_BASE=TRUE

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP9

MAKE_BASE=TRUE

TRUE

NC_PCH_TP12

MAKE_BASE=TRUE

TRUE

NC_PCH_TP11

MAKE_BASE=TRUE

TRUE

NC_PCH_TP13

MAKE_BASE=TRUE

TRUE

NC_PCH_TP8

NC_USB_6N

NC_USB_7N NC_USB_7P

NC_HDA_SDIN1

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN2

NC_PCI_GNT3_L

NC_PCI_GNT0_L

TRUE MAKE_BASE=TRUE

NC_PCI_GNT0_L

NC_PCI_GNT1_L

NC_PCI_PAR

MAKE_BASE=TRUE

TRUE

NC_PCI_PAR

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

NC_PCI_RESET_L

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK33M_OUT3NC_PCI_CLK33M_OUT3

TP_NV_DQS<1..0>

MAKE_BASE=TRUE

TRUE

NC_NV_DQ<15..0>TP_NV_DQ<15..0>

TP_NV_CE_L<3..0>

TRUE

NC_NV_ALE

MAKE_BASE=TRUE

NC_NV_ALE

NC_NV_CLE

TRUE MAKE_BASE=TRUE

NC_NV_CLE NC_NV_RB_L

NC_PCIE_CLK100M_PE4N

TRUE

NC_NV_WE_CK_L<1..0>

MAKE_BASE=TRUE

TP_NV_WE_CK_L<1..0>

TRUE

NC_NV_WR_RE_L<1..0>

MAKE_BASE=TRUE

TP_NV_WR_RE_L<1..0>

NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N

TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE5P

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P

NC_SATA_C_D2RP

NC_PSOC_P1_3 NC_SATA_C_D2RN

NC_SATA_C_R2D_CP

NC_SATA_C_R2D_CN

NC_SATA_D_R2D_CN

NC_SATA_D_D2RP

NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_R2D_CNNC_SATA_SSD2_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_D2RPNC_SATA_SSD2_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCH_TP1

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

TRUE

MAKE_BASE=TRUE

NC_PCH_TP5

TRUE

MAKE_BASE=TRUE

NC_PCH_TP4

TRUE

MAKE_BASE=TRUE

PP3V3_S5

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_USB_6N

MAKE_BASE=TRUE

TRUE

NC_USB_MINIP

NC_USB_EXTDP

NC_USB_EXTDN

TRUE MAKE_BASE=TRUE

NC_PCI_AD<31..0>

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_CTRL_DATA

NC_CRT_IG_GREEN

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD<24..15>

NC_TP_CPU_RSVD<43..32>

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7P

NC_SDVO_STALLN

NC_PCH_TP17

NC_PCH_TP14

NC_PCH_TP12

NC_PCH_TP2

NC_PCH_TP9

NC_PCH_TP15

NC_FW643_AVREG

TRUE MAKE_BASE=TRUE

NC_NV_CE_L<3..0>

MAKE_BASE=TRUE

TRUE

NC_NV_DQS<1..0>

NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18

NC_PCH_TP16

NC_PCH_TP13

NC_PCH_TP11

NC_PCH_TP8

NC_PCH_TP3

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_AUXP

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_MLP<3..0>

NC_DP_IG_C_HPD

NC_SMC_FAN_3_CTL

TRUE

NC_SMC_FAN_3_TACH

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RP

PCH_VSS_NCTF<2>

TRUE TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<7>

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<15>

TRUE

NC_PCH_TP1

NC_NV_RB_L

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RP

TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CN

NC_SATA_SSD2_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_D2RN

NC_SATA_D_R2D_CP

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_CONN_A_DATA_N<0>

NC_PCIE_PE7_D2RN

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE6_R2D_CP

TRUE

NC_PCIE_PE6_R2D_CP

MAKE_BASE=TRUE

NC_USB_6P

NC_USB_MINIP

NC_USB_MININ

NC_SATA_SSD2_R2D_CP

TRUE

SPKRAMP_LFE_OUT_P

TRUE

SPKRAMP_LFE_OUT_N

TRUE

SPKRAMP_FR_OUT_P

TRUE

SPKRAMP_FR_OUT_N SPKRAMP_BR_OUT_P

TRUE TRUE

SPKRAMP_BR_OUT_N

TRUE

SPKRAMP_BL_OUT_P SPKRAMP_BL_OUT_N

TRUE

SATA_ODD_R2D_N

LED_RETURN_6

TRUE

SATA_HDD_D2R_UF_P

TRUE

SATA_HDD_D2R_UF_N

PP1V8_S0

TRUE

PM_SLP_S3_L

TRUE

NC_USB_EXTDN

MAKE_BASE=TRUE

TRUE

NC_USB_7N

TRUE

WS_LEFT_SHIFT_KBD

NC_TP_CPU_RSVD<65..62>

MAKE_BASE=TRUE

TRUE

USB_LT2_P

TRUE

WS_KBD15_CAP

TRUE

SMC_NMI

MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_CLK

TRUE

NC_PCI_GNT3_L

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCI_RESET_L

TRUE

PP3V3_S0

TRUE

PP3V3_WLAN

TRUE

AP_RESET_CONN_L

TRUE

SMC_LID_R

TRUE

IR_RX_OUT

TRUE

PP5V_S3

TRUE

PP3V42_G3H

TRUE

PPBUS_CPU_IMVP_ISNS

TRUE

PPBUS_G3H

PP5V_S0

TRUE

AP_CLKREQ_Q_L

TRUE

SMBUS_PCH_DATA

TRUE TRUE

PP3V3_S0_EXCARD_SWITCH

USB2_EXCARD_CONN_N

TRUE TRUE

USB2_EXCARD_CONN_P

TRUE

EXCARD_CPPE_L

PCIE_EXCARD_D2R_P

TRUE

PCIE_EXCARD_R2D_P

TRUE

PCIE_EXCARD_R2D_N

TRUE

PCIE_CLK100M_EXCARD_CONN_N

TRUE

PP3V3_S3

TPAD_GND_F

TRUE TRUE

Z2_CS_L

TRUE

Z2_DEBUG3

TRUE

Z2_MISO

TRUE

Z2_BOOT_CFG1

TRUE

Z2_BOOST_EN

Z2_CLKIN

TRUE

Z2_KEY_ACT_L

TRUE

Z2_RESET

TRUE

PICKB_L

TRUE

PSOC_F_CS_L

PSOC_MISO

TRUE

PSOC_MOSI

TRUE

PSOC_SCLK

TRUE

SMBUS_SMC_A_S3_SCL

TRUE TRUE

SMBUS_SMC_A_S3_SDA

TRUE

ADAPTER_SENSE PP18V5_DCIN_FUSE

TRUE

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SDA SMC_BS_ALRT_L

TRUE

PP3V42_G3H

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMC_BIL_BUTTON_L

TRUE

CONN_USB2_BT_N

SMBUS_SMC_A_S3_SDA

TRUE

PP1V0_FW

TRUE

NC_CRT_IG_RED

TRUE MAKE_BASE=TRUE

TRUE

NC_CRT_IG_DDC_CLK

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_DATANC_CRT_IG_DDC_DATA

NC_CRT_IG_GREEN

TRUE

SMC_TDI

TRUE

WS_KBD4

WS_KBD16_NUM

TRUE

PP3V42_G3H_LIDSWITCH_R

TRUE

LCD_BKLT_PWM

TRUE

NC_PCIE_PE5_D2RN

MAKE_BASE=TRUE

TRUE

SATA_ODD_R2D_P

NC_PCH_TP6

NC_PCH_TP7

NC_PCH_TP5 NC_PCH_TP4

NC_PCH_TP3

TRUE

MAKE_BASE=TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<19>

TRUE TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<21> PCH_VSS_NCTF<25>

TRUE TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<29>

MAKE_BASE=TRUE

TRUE

NC_USB_6P

FAN_RT_PWM

TRUE

FAN_LT_TACH

FAN_RT_TACH

TRUE

SPKRAMP_FL_OUT_N

MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUE

NC_DP_IG_D_AUXN

TP_DP_IG_D_MLP<3..0>

NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

PP18V5_S3

TRUE

WS_KBD5 WS_KBD6

TRUE

SYS_LED_ANODE_R

TRUE

LVDS_DDC_CLK

TRUE

PP3V3_S0GPU

TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_DE

TP_GPU_MIOA_D<9..0>

NC_SDVO_INTP

NC_GPU_BUFRST_L TP_GPU_GSTATE<0> TP_GPU_GSTATE<1>

TP_GPU_MIOA_DE

TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

TRUE MAKE_BASE=TRUE

NC_LVDS_EG_BKL_PWM

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_LVDS_EG_B_CLKP

TRUE MAKE_BASE=TRUE

NC_LVDS_EG_B_CLKN

TRUE

NC_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<1>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<0>

MAKE_BASE=TRUE

TRUE

NC_GPU_BUFRST_L

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLP

NC_SDVO_STALLN

TRUE MAKE_BASE=TRUE

PP3V3_S3_EXCARD_SWITCH

TRUE

WS_CONTROL_KBD

PCIE_WAKE_L

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_R2D_N

TRUE

SPKRAMP_FL_OUT_P

PCIE_WAKE_L

TRUE

PP1V2_S0

MAKE_BASE=TRUE

TRUE

NC_USB_7P

TRUE

NC_USB_MININ

MAKE_BASE=TRUE

NC_USB_WMP

TRUE

MAKE_BASE=TRUE

NC_USB_WMP

TRUE

MAKE_BASE=TRUE

NC_USB_WMNNC_USB_WMN

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

7 OF 132 6 OF 103

6

39

6

39

6

39

44 99

54

44

6

18

6

17

6

17

6

17

6

19

6

19

33

20 94

84 85 98

34 99

34

17 25 26 28 30 32 34 42 48 49 64 94

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

7

12 15 50 69

33 99

6

33 46 49 55 97

63

7

51 75 77 80 82

7 8

51 76 77 78 79

7

50 76 83

7

51 87

46 47

33

34

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

34

53

46 47

84 98

84 85

57 84 89

63 99

6

19

6

81 82

8

18 93

6

20

6

20

6

19

46 47 54

54

34

7

40 41

6

20 94

17 34 94

42 93

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6 7 8

23 42

48 53 55 69

70 71 73 87

102

33 99

43

42

54

6

18

6

18

84 85 98

6

18

6

18

6

18

6

18

6

18

54

6

18

6

18

54

6 7

17 20 31

32 33 34 35

36 49 50 51

54 55 56 72

74 88

102 103

54

43 99

42 93

84 89

84 85 98

6 7

17 21 23 43 45 46 47 48 49 50 51 54 65 66 74

6

55

7

65 66

7

10 12 13 15 25 26 40 71 74

101

54

43 99

18 46 48

17 46 48 88 94

84 85 98

42 57

33 99

27 48 94

17 33 94

43

43 99

27 48 88 94

48

54

84 89

54

84 85 98

84 98

84 85 98

84 98

84 89

42 46

42 99

45

54

46 47 48 66

48

9

54

84 85 98

84

8

84

18 27 46

46 47 48

18 46 48

17 46 48

48

20 48 58

43 46 47 48

46 48

46 47 48

17 46 48 88 94

7

32 68

7

73 82

44 99

54

43 46 47 48

20 48

54

6

18

45 47

55

33 99

46 47

39 41

39 41 96

46 47

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

19

6

19

6

19

6

17

6

17

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

19

6

17

19

6

17

6

17

6

20

6

20

6

20

6

17

6

20

6

20

6

20

6

17

6

54

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

20

6

20

6

20

6

20

6

20

6

20

7

31 35

49 50 51

58 72 73

74 84

86 99

101

6

20

6

93

6

19

6

18

6

18

9

6

20

6

18

6

20

6

20

6

20

6

20

6

20

6

20

6

39

19

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

20

6

18

6

18

6

18

46 47

6

17

6

17

20 94

6

20

6

19

6

17

6

17

6

17

6

17

6

20

6

54

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

84 85 98

6

17

6

17

6

17

6

19

6

93

6

93

6

17

62 63 99

42 93

84 89

42 99

7

12 16 72 73 88

101

18 31 46 74 86

6

19

54

43 99

54

46 48

6

18

6

19

6

19

6 7 8

25 26 27 28 30 34 37 40 42 47

48 49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

33

45

7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

7

50 69

7 8

40 50 66 67 68 70 71 83 87

6 7 8

23 42 48 53 55 69 70 71 73 87

102

33

17 25 26 28 30 32 34 42 48 49

64 94 34

34 99

34

17 34 94

34 94

34 99

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

55

54 55

55

54 55

6

33 46 49 55 97

6

33 46 49 55 97

65

65 66

6

46 49 65 66 97

6

46 49 65 66 97

6 7

17 21 23 43

45 46 47 48 49 50 51 54

65 66 74

6

46 49 65 66 97

6

46 49 65 66 97

46 47 65

33 99

6

33 46 49 55 97

7

40 72

6

18

6

18

6

18

6

18

6

18

46 47 48

54

45

88 89

6

17

42 93

6

20

6

20

6

20

6

20

6

20

20 94

6

20 94

6

20 94

6

19

53

62 63 99

6

18

6

18

6

18

6

18

6

17

19

6

18

6

55

54

45

84 85

7

73 75 80 81 82 83 85

80 81

6

18

6

75

80 81

81

80 81

8

18 93

8

18

6

75

6

18

6

18

34

54

6

18 27 33 34

33 99

33 94

17 33 94

33 94

62 63 99

6

18 27 33 34

7

73 88

6

19

6

93

6 6

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

C

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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345678

D

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8 7 5 4 2 1

"G3Hot" (Always-Present) Rails

Chipset "VCore" Rails

2A max supply

5V Rails

? mA

ENET Rails

"GPU" Rails

"FW" (FireWire) RailsDDR Rails

1.5V/1.05V Rails

3.3V/1.8V Rails

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Power Aliases

PP3V3_S5

PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5

PP5V_S0

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 MM

PP5V_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

PP1V05_S0GPU_ISNS_R

PP1V8_S0GPU_ISNS_R

VOLTAGE=1.05V

PP1V05_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS_R

PP1V5_S3

PP1V5_S3RS0

PPCPUDDR_ISNS

PP3V3_S5

PPVTTDDR_S3

PP1V5_S0

PP1V5_S3

PP1V5_S3 PP1V5_S3

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP0V75_S0_DDRVTT

PP1V2_S0

PP1V5_S0 PP1V5_S0

PP1V5_S0

PP1V2_S0

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V5_S0

PP3V3_S5

PP1V8_S0

PP3V42_G3H

PP1V8_S0 PP1V8_S0

PP1V8_S0

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0

PP1V0_FW

MIN_NECK_WIDTH=0.2 MM

PPVIN_FW_FWPHY

VOLTAGE=1.0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PP3V3_S5

PPBUS_G3H

PPBUS_FW_FWBOOST

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=6V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=10V

MAKE_BASE=TRUE

PP10V_FW

MIN_LINE_WIDTH=0.4 MM

PPVP_FW

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=10V

MAKE_BASE=TRUE

PP1V0_FW

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S0GPU

PP1V8_GPUIFPX

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0GPU_ISNS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.25V

PP1V8_S0GPU_ISNS_R

PPVCORE_GPU

VOLTAGE=1.2V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0GPU

PPBUS_FW_FWBOOST

PP10V_FW

PPVP_FW

PP3V3_FW_FWPHY

PP1V0_FW

PPVIN_FW_FWPHY

PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU

PP3V3_S0GPU

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS

PP1V05_S0GPU_ISNS_R

PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU

PP1V05_S0GPU

PPVCORE_GPU

PPBUS_G3H

PP3V3_FW_FWPHY

PPBUS_FW_FWBOOST

PPVP_FW

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP10V_FW

PP1V05_S5

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V

PPVCORE_S0_CPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_ENET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.2V

PP1V2_ENET

PP1V05_S5

PPCPUVTT_S0

PP1V05_S5

PPCPUVTT_S0

PPCPUVTT_S0 PPCPUVTT_S0

PPCPUVTT_S0

PPVCORE_S0_GFX

PPVCORE_S0_CPU_VCAP0

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU_VCAP1

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU_VCAP2

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PP3V3_ENET

PP1V2_ENET

PP1V2_ENET PP1V2_ENET

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM

PPBUS_CPU_IMVP_ISNS

PPDCIN_G3H

PP3V42_G3H PP3V42_G3H PP3V42_G3H

PP3V42_G3H

PP5V_S5

PP3V42_G3H

PP3V42_G3H PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM

PP3V42_G3H

VOLTAGE=3.42V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPDCIN_G3H

PP3V3_S5

PP3V42_G3H

PPVCORE_S0_CPU_VCAP2

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU_VCAP0

PPVCORE_S0_GFX

PP5V_S0_ISNS_R

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

PP5V_S3_ISNS_R

PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0

PP5V_S0

PP5V_S0_ISNS_R

PP5V_S5

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S5

PPBUS_CPU_IMVP_ISNS

PP5V_S3_ISNS_R

PP3V42_G3H

PP5V_S0

MAKE_BASE=TRUE

PPVCORE_S0_GFX

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

PPBUS_G3H

MIN_LINE_WIDTH=0.4 MM VOLTAGE=6V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

PPBUS_CPU_IMVP_ISNS

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PP5V_S3_ISNS_R

PP5V_S5

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3

MIN_NECK_WIDTH=0.25 mm

PP5V_S3

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PP5V_S3 PP5V_S3

PPBUS_G3H

PP3V42_G3H

PP3V3_S5 PP3V3_S5

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_G3H

PP3V3_S5

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

PP5V_S5

PP3V3_S5_ISNS_R

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S5_ISNS_R

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S3

PPCPUVTT_S0

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V5_S3

MIN_LINE_WIDTH=0.3 MM

PPVTTDDR_S3

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

VOLTAGE=0.75V MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

PPCPUDDR_ISNS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S3RS0

PP3V3_S3_ISNS_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

PP3V3_S3_ISNS_R

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM

PP3V3_S3_ISNS_R

PP3V3_S0

MIN_LINE_WIDTH=0.5 mm

PP3V3_S3

MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

8 OF 132 7 OF 103

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101

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72 73 74 84 86 99

101

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101

6 7

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101 6 7

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101 6 7

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101

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58 72 73 74 84 86 99

101

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23 42 48 53 55 69 70 71 73 87

102

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102

7

51 87

6 7

51 87

7

51 87

6 7

51 87

7

28 30 31 68 73

7

57 73

7

57 73

7

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7

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6 7

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101

6 7

32 68

7

34 42 59 72 74 99

7

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7

28 30 31 68 73

7

28 30 31 68 73

7

28 30 31 68 73

7

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7

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7

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7

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7

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6 7

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6 7

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7

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7

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7

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6 7

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7

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101

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101

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101

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50 51 54 65 66 74

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101

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101

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101

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7

39 40 72

6 7

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101

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101

6 7 8

40 50 66 67 68 70 71 83

87

7

40 72

7 8

40 72

6 7

40 41

6 7

40 72

6 7

73 75 80 81 82

83 85

6 7

73 82

6 7 8

51 76 77 78

79

6 7

51 87

6 7

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6 7

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7

40 72

7 8

40 72

7 8

40 72

6 7

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6 7

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7

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7

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7

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7

39 40 72

6 7

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83 85 6 7

73 75 80 81 82

83 85 6 7

73 75 80 81 82

83 85

6 7

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83 85

6 7

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83 85

6 7

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6 7

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6 7 8

51 76 77 78

79 6 7 8

51 76 77 78

79

6 7

73 82

6 7 8

51 76 77 78 79

6 7 8

51 76 77 78

79

6 7 8

51 76 77 78

79

7

51 87

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

51 75 77 80 82

6 7

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6 7

50 76 83

6 7 8

40 50 66 67 68 70 71 83

87

7

39 40 41

7

40 72

6 7

40 41

7

39 40 41

7 8

40 72

7

17 72

6 7

12 15 50 69

7

27 37 74

7

37 72 73

7

17 72

6 7

10 12 13 15 25 26 40 71 74

101

7

17 72

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40

71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40

71

74

101

7

13 24 50 70

7

12 16

7

12 16

7

13 24

7

27 37 74

7

27 37 74

7

37 72 73

7

37 72 73

6 7

65 66

6 7

50 69

6 7

65 66

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

7

23 57 67 73

102

7

23 57 67 73

102

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74 6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43

45 46 47 48 49 50 51 54 65 66

74

6 7

65 66

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

7

13 24

7

12 16

7

12 16

7

13 24 50

70

7

73

102

7

51 67

6 7 8

23 42 48 53 55

69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

6 7 8

23 42 48 53 55 69 70 71 73 87

102

7

73

102

7

73

102

7

23 57 67 73

102

7

23 57 67 73

102

7

23 57 67 73

102

6 7

50 69

7

51 67

6 7

17 21 23 43

45 46 47

48 49 50

51 54 65

66 74

6 7 8

23 42 48 53 55 69 70 71 73 87

102

7

13 24 50 70

6 7

12 15 50 69

6 7

12 15 50

69

6 7 8

40 50 66 67 68 70 71 83

87

6 7

50 69

7

51 67

7

23 57 67 73

102

6 7

31 33 43

44 45 47 51 55

68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7

31 33 43 44 45 47 51 55 68 73 83

103

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7 8

40 50 66 67 68 70 71 83

87

6 7

17 21 23 43 45 46 47 48 49

50 51 54 65 66 74

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101 6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

6 7 8

40

50 66 67

68 70 71

83 87

6 7 8

40 50 66 67 68 70 71 83

87 6 7 8

40 50 66 67 68 70 71 83

87

6 7

31 35 49 50 51 58

72

73 74 84 86 99

101

6 7

31 35 49 50 51 58 72 73 74 84 86 99

101

7

23 57 67 73

102

7

23 57 67 73

102

7

51 67

7

51

67

7

51 67

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54 55 56 72 74 88

102 103

6 7 17 20 31 32 33 34 35 36 49 50 51 54 55 56 72 74 88

102 103

6 7

10 12 13 15 25 26 40 71 74

101

7

28 30 31 68 73

6 7

32 68

7

28 30 31 68

7

13 16 31 57

7

57 73

7

73

102

7

73

102

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72 73 74 81 84 85 86 88 99

101

7

73

102

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84

85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84

85 86 88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70

71 72 73 74 81 84 85 86 88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52

53 55 59 63 64 69 70 71 72 73 74 81 84

85

86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59

63 64 69 70 71 72 73 74 81 84 85 86 88

99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86

88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59

63 64 69 70 71 72 73 74 81 84 85 86 88

99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72

73

74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59

63 64 69 70 71 72 73 74 81 84 85 86 88

99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69

70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26

27 28

30

34 37 40 42 47 48 49 52 53 55 59 63 64

69

70 71 72 73 74 81 84 85 86 88 99

101

6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 52 53 55 59 63 64 69 70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49 52

53 55 59 63

64 69 70 71 72 73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84

85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86

88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101 6 7 8

25 26 27 28 30 34 37 40 42 47 48 49

52

53 55 59 63 64 69 70 71 72 73 74 81 84

85

86 88 99

101

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

6 7

17

20 31 32 33 34 35 36 49 50 51 54 55 56

72 74 88

102 103

6 7

17 20 31 32 33 34 35 36 49 50 51 54

55 56 72 74 88

102 103

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

** PEG LANES REVERSED. ARD STRAP REQ’D. **

TM Hole

Bosses for Flex Protector Bracket

GMUX ALIASES

Right CPU

GPU signals

Left CPU

Digital Ground

TM Hole

CPU signals

TM Hole

Bottom Left GPU

Frame Holes

Top GPU Right

AUDIO ALIASES

Thermal Module Holes

It will be removed from the design after proto1.

Per WF: R0914 can’t be stuffed, it will break CPU IMON Calculation.

USB Hub Aliases

Rev. A NCs

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0980

1

2 1

XW0900

SM

XW0901

2 1

SM

R0900

21

10

MF-LF

402

1%

1/16W

21

R0901

10

MF-LF

402

1%

1/16W

1

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

1

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0983

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0984

ZT0987

1

STDOFF-4.5OD.98H-1.1-3.48-TH

1

3R2P5

ZT0960

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0930

1

ZT0934

STDOFF-4.0OD3.0H-SM

1

ZT0931

STDOFF-4.0OD3.0H-SM

1

ZT0932

3R2P5

1

ZT0971

3R2P5

1

SM

SH0913

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0910

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0914

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0911

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0900

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0903

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0902

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0919

SM

1

SH0917

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0916

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

SH0918

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0920

SM

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0921

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0922

SM

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0923

ZT0957

4.0OD1.65H-M1.6X0.35

1

ZT0958

4.0OD1.65H-M1.6X0.35

1

SH0901

2.0DIA-TALL-EMI-MLB-M97-M98

SM

3R2P5

ZT0915

1

SH0924

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0930

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0931

1

SH0932

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0933

SM

1

SH0935

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0934

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

ZT0940

3R2P5

1

ZT0970

3R2P5

2 1

XW0902

SM

R0904

MF-LF

5%

1/10W

BKLT_PWR_PBUS

0

603

21

MF-LF

5%

0

BKLT_PWR_FW10V

603

1/10W

R0903

1 2

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0912

21

3.0K

5%

R0902

402

MF-LF

1/16W

1 2

402

1/16W

GMUX_VSYNC

R0906

MF-LF

5%

0

1 2

R0907

5%

0

PANEL_VSYNC

402

MF-LF

1/16W

Signal Aliases

SYNC_MASTER=K17_REF

SYNC_DATE=06/17/2009

NC_ISNS_PVTTS0PCH_P

NC_ISNS_PVTTS0PCH_NNC_ISNS_PVTTS0PCH_N

MAKE_BASE=TRUE

NC_ISNS_PVTTS0PCH_P

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_P

NC_ISNS_P3V3S0MPCH_N

NC_ISNS_P3V3S0MPCH_P

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_N

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_PNC_ISNS_P1V05S0PCH_P

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_N

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_N

USB_EXCARD_N USB_EXCARD_P

USB_EXTC_OC_L

EXCARD_OC_L

MAKE_BASE=TRUE

USB_EXCARD_P

MAKE_BASE=TRUE

USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXTC_OC_L

MAKE_BASE=TRUE

EXCARD_OC_L

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

NC_LVDS_IG_A_DATAN<3>

NC_LVDS_IG_B_DATAP<3>

TP_LVDS_IG_B_CLKN TP_LVDS_IG_BKL_PWMTP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_XTALOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

NC_LVDS_IG_A_DATAP<3>

=PEG_D2R_N<0..15>

=PEG_D2R_P<0..15>

BKL_SYNC BKL_SYNC

MAKE_BASE=TRUE

DP_IG_ML_P<3..0>

MAKE_BASE=TRUE

DP_IG_ML_N<3..0>

MAKE_BASE=TRUE

DP_IG_B_ML_P<3..0>

=PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_GPU_XTALOUT

NC_LVDS_IG_B_DATAN<3>

LVDS_CONN_BKL_SYNC

GMUX_VSYNC

GND

PP3V3_S0

MAKE_BASE=TRUE

PP3V3_S0

PM_ENET_EN

LCD_BKLT_EN

MAKE_BASE=TRUE

PEG_CLKREQ_L PEG_CLKREQ_L

MAKE_BASE=TRUE

PEX_CLKREQ_L PEX_CLKREQ_L

CPU_VID<0..6>

MAKE_BASE=TRUE

MEMVTT_EN

MIN_LINE_WIDTH=0.5 mm

PP5V_S0_AUDIO_AMP_R

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP5V_S0

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

GFX_VID<0..6>

GFXIMVP_VID<0..6>

CPUIMVP_VID<0..6>

FW643_WAKE_L

MAKE_BASE=TRUE

MEMVTT_EN

PP1V8_S0GPU_ISNS

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

GND

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

EG_RESET_L

MAKE_BASE=TRUE

EG_RESET_L

TP_LVDS_MUX_SEL_EGTP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

PEG_R2D_C_P<15..0>

MAKE_BASE=TRUE

PEG_R2D_C_N<15..0>

MAKE_BASE=TRUE

PPVIN_S0_LCDBKLT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=6V

PPVIN_S0_LCDBKLT

PP10V_FW

PPBUS_G3H

PM_ENET_EN

MAKE_BASE=TRUE

=PEG_R2D_C_N<0..15>

PEG_D2R_N<15..0>

MAKE_BASE=TRUE

PEG_D2R_P<15..0>

MAKE_BASE=TRUE

DP_IG_B_ML_N<3..0> DP_IG_AUX_CH_PDP_IG_AUX_CH_P

MAKE_BASE=TRUE

DP_IG_HPD

MAKE_BASE=TRUE

DP_IG_HPD

DP_IG_DDC_DATADP_IG_DDC_DATA

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

TP_SATA_EXTA_D2R_N

MAKE_BASE=TRUE

TP_SATA_EXTA_D2R_N

DP_IG_DDC_CLKDP_IG_DDC_CLK

MAKE_BASE=TRUE

TP_SATA_EXTA_R2D_C_P

MAKE_BASE=TRUE

TP_SATA_EXTA_R2D_C_P

TP_SATA_EXTA_D2R_P TP_SATA_EXTA_R2D_C_N

MAKE_BASE=TRUE

TP_SATA_EXTA_R2D_C_N

FW_PLUG_DET_L

FW643_WAKE_L

MIN_LINE_WIDTH=0.5 mm

PP5V_S0_AUDIO_AMP_L

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MAKE_BASE=TRUE

FW_PLUG_DET_L

GND

MAKE_BASE=TRUE

GND GND

GND

MAKE_BASE=TRUE

TP_SATA_EXTA_D2R_P

LCD_BKLT_EN

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

CPU_CFG<3>

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

GND

9 OF 132 8 OF 103

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

99

102

8

50 99

8

50 99

8

50 99

8

50 99

8

34 36 93

8

34 36 93

8

35 44

8

34 36 47

8

34 36 93

8

34 36 93

8

35 44

8

34 36 47

8

32 78

8

12 91

8

18 93

8

18 93

6 8

18 93

6 8

18

6 8

18

6 8

18 93

6 8

18 93

6 8

18 93

8

80

8

18 93

8

18 93

8

18 93

8

85 93

18

9

8

12 91

8

18 93

8

18 93

8

80

8

18 93

6

84

88

6 7 8

25 26 27 28

30 34 37 40 42 47

48 49 52 53

55 59 63 64

69 70 71 72

73 74 81 84

85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

8

88 90

8

17 88

8

17 88

8

75 88

8

75 88

12 15 91

8

31 68

62

59 61

6 7

23 42 48 53 55 69 70 71 73 87

102

8

18 88

8

18 88

13 91

70

69

8

39 40

8

31 68

6 7

51 76 77 78 79

8

32 78

8

32 79

8

74 83 87 88

8

74 83 87 88

8

75 88

8

75 88

8

88

8

88

8

18 88

75 91

8

90

8

90

7

40 72

6 7

40 50 66 67 68 70 71 83

87

8

72 74

9

75 91

9

75 91

18

8

18 85 93

8

18 85 93

8

18 85

8

18 85

8

18 81 85

8

18 81 85

8

18 85 93

8

18 85 93

8

17 93

8

17 93

8

18 81 85

8

18 81 85

8

17 93

8

17 93

8

17 93

8

17 93

8

17 93

8

20 40

8

39 40

62

8

20 40

8

17 93

8

88 90

8

18 88

9

25 91

8

32 79

www.vinafix.vn

IN IN IN IN

IN

OUT

IN IN

IN

IN IN

IN

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

IN

FDI_TX1

DMI_RX0*

DMI_TX2*

DMI_RX1*

PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5*

PEG_RX7*

PEG_RX6*

PEG_RX9*

PEG_RX8*

PEG_RX10*

PEG_RX12*

PEG_RX11*

PEG_RX13* PEG_RX14* PEG_RX15*

PEG_RX0 PEG_RX1

PEG_RX3

PEG_RX2

PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9

PEG_RX11

PEG_RX10

PEG_RX13

PEG_RX12

PEG_RX15

PEG_RX14

PEG_TX0* PEG_TX1* PEG_TX2*

PEG_TX4*

PEG_TX3*

PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8*

PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*

PEG_TX0 PEG_TX1

PEG_TX3

PEG_TX2

PEG_TX5

PEG_TX4

PEG_TX6

PEG_TX8

PEG_TX7

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

DMI_RX2

DMI_RX0 DMI_RX1

DMI_RX3

DMI_TX0* DMI_TX1*

DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_TX1*

FDI_TX0*

FDI_TX2* FDI_TX3*

FDI_TX5*

FDI_TX4*

FDI_TX6* FDI_TX7*

FDI_TX0

FDI_TX3

FDI_TX2

FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0

FDI_INT

FDI_LSYNC1

PEG_ICOMPI PEG_ICOMPO

PEG_RBIAS

PEG_RCOMPO

DMI_RX3*

DMI_RX2*

(SYM 1 OF 11)

FLEXIBLE DISPLAY INTERFACE

DMI

PCI EXPRESS -- GRAPHICS

RSVD37

RSVD36

RSVD33

RSVD32

RSVD_NCTF5

RSVD_NCTF6

RSVD_NCTF8

RSVD_NCTF7

RSVD27

RSVD24

RSVD26

RSVD23

RSVD22

RSVD21

RSVD20

RSVD19

RSVD18

RSVD17

RSVD16

RSVD15

RSVD_TP0

CFG17

CFG16

CFG15

CFG14

CFG13

CFG11 CFG12

CFG10

CFG9

CFG8

CFG7

CFG6

CFG5

CFG3 CFG4

CFG2

CFG1

CFG0

DC_TEST_A5

DC_TEST_A69 DC_TEST_A68

DC_TEST_A71

DC_TEST_C3

DC_TEST_C69

DC_TEST_C71

DC_TEST_E1

DC_TEST_E71

DC_TEST_BR1

DC_TEST_BR71

DC_TEST_BT3 DC_TEST_BT1

DC_TEST_BT69

DC_TEST_BV1

DC_TEST_BT71

DC_TEST_BV3

DC_TEST_BV68

DC_TEST_BV5

DC_TEST_BV71 DC_TEST_BV69

RSVD64 RSVD65

RSVD62 RSVD63

RSVD_TP1

RSVD_TP2

RSVD57 RSVD58

RSVD56

RSVD54 RSVD55

RSVD52 RSVD53

RSVD51

RSVD50

RSVD49

RSVD48

RSVD46 RSVD47

RSVD45

RSVD_NCTF1

RSVD_NCTF2

RSVD39

RSVD_NCTF3

RSVD38

RSVD34

RSVD_NCTF4

RSVD35

(SYM 5 OF 11)

RESERVED

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic.

WF: RSVD nets with arrows have offpage marks on CRB schematic.

CFG3: PCIe Lane Reversal 1 = Normal Operation 0 = Lanes Reversed

and level-shifted for

NOTE: HPD must be inverted

eDP_TX<3> eDP_TX<2> eDP_TX<1> eDP_TX<0>

eDP_TX#<0>

eDP_TX#<1>

eDP_TX#<2>

eDP_TX#<3>

eDP_HPD# eDP_AUX

eDP_AUX#

Auburndale (1.05V).

(eDP) pins

Embedded DisplayPort

(Auburndale only):

CFG4: Display Port Presence 1 = eDP Disabled 0 = Embedded Display Port Enabled

CFG0: PCIe Configuration Select 1 = Single PEG 0 = Bifurcation Enabled

(IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

18 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

75 91

8

2

1

R1012

750

MF-LF

1/16W

402

1%

2

1

R1010

1/16W

1%

49.9

402

MF-LF

25 91

8

25 91

A31

B30

L30

J30

B35

D36

B33

A34

G32

H32

A38

B37

D40

B39

M32

N32

J20

L20

G21

F21

M24

N24

N26

M25

L28

N28

B32

D33

L38

N38

N40

L40

D26

B25

B26

A27

D29

B28

H24

K24

H25

G25

G28

J28

P34

M34

H34

G34

B14

D15

A17

B16

D19

B18

A20

B19

D22

B21

B23

A24

G38

J38

G40

F40

D12 B11

A13

B12

W8

W10

U7

U6

R7

R8

N10

N9

P1

R2

M4

N2

N7

N5

L2

K1

AB2

AA1

AB5

AC9

AC7

F10

J11

J13

G13

K15

M15

H17

G17

J4

J2

K8

K9

J8

J6

F7

F9

U1000

BGA

OMIT

ARRANDALE

AP2 AN7

AU1

A6

C5

E3 F1

BR5

BT5

BV6 BV8

BE71

BE69

AU2

AV4

AT67

AU69

AR69

AT70

AU71

AK69

AM66

AR71

AK66

AH66

AP66

AN69

AK71

AV69

R64

R66

AA69

AA71

AC71

AC69

W64

W66

B9

A10

B7

D8

BB69

AY69

AW70

AV71

V2

U1

T2

T4

E71 E1 C71 C69 C3

BV71 BV69 BV68 BV5 BV3 BV1 BT71 BT69 BT3 BT1 BR71 BR1

A71 A69 A68 A5

AG2

AF4

AG7

AT2

AJ2

AK4

AK2

AK1

AB7

AF6

AF8

AD1

AE2

AC4

AC2

AH1

AM2

AL4

U1000

BGA

ARRANDALE

OMIT

52 99

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

CPU DMI/PEG/FDI/RSVD

CPU_CFG<0>

CPU_CFG<2>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10> =PEG_R2D_C_N<11>

CPU_CFG<1>

CPU_CFG<4>

CPU_CFG<3>

CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16>

TP_CPU_RSVD<15>

TP_CPU_RSVD<19>

TP_CPU_RSVD<26>

TP_CPU_RSVD<24>

TP_CPU_RSVD<27> NC_TP_CPU_RSVD_NCTF<7>

NC_TP_CPU_RSVD_NCTF<8> NC_TP_CPU_RSVD_NCTF<6>

NC_TP_CPU_RSVD_NCTF<5>

TP_CPU_RSVD<2> TP_CPU_RSVD<1>

TP_CPU_RSVD<64>

TP_CPU_RSVD<55>

TP_CPU_RSVD<54>

TP_CPU_RSVD<56> TP_CPU_RSVD<57>

TP_CPU_RSVD<45> TP_CPU_RSVD<46> TP_CPU_RSVD<47> TP_CPU_RSVD<48> TP_CPU_RSVD<49> TP_CPU_RSVD<50>

TP_CPU_RSVD<58>

TP_CPU_RSVD<52> TP_CPU_RSVD<53>

TP_CPU_RSVD<51>

NC_TP_CPU_RSVD<42>

NC_TP_CPU_RSVD<40>

NC_TP_CPU_RSVD<32> NC_TP_CPU_RSVD<33>

NC_TP_CPU_RSVD<36> NC_TP_CPU_RSVD<37>

NC_TP_CPU_RSVD<41>

NC_TP_CPU_RSVD<43>

NC_TP_CPU_RSVD<34>

NC_TP_CPU_RSVD<38> NC_TP_CPU_RSVD<39>

NC_TP_CPU_RSVD<35>

TP_CPU_TEST_BR1

TP_CPU_TEST_E1

TP_CPU_TEST_E71

TP_CPU_TEST_C3

TP_CPU_TEST_A5

TP_CPU_TEST_A68

CPU_TEST_C71_A71 CPU_TEST_C69_A69

FDI_LSYNC<1>

FDI_LSYNC<0>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

FDI_DATA_P<7>

FDI_DATA_P<6>

FDI_DATA_P<5>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_P<0>

FDI_DATA_N<6> FDI_DATA_N<7>

FDI_DATA_N<5>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<1> FDI_DATA_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<0>

DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<0> DMI_S2N_P<1>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0> CPU_PEG_COMP

CPU_PEG_RBIAS

PEG_D2R_N<15>

PEG_D2R_N<11> PEG_D2R_N<10>

PEG_D2R_N<13>

PEG_D2R_N<14>

PEG_D2R_N<12>

PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<9>

PEG_D2R_N<7>

PEG_D2R_N<1> PEG_D2R_N<0>

PEG_D2R_N<2>

PEG_D2R_N<4>

PEG_D2R_P<12> PEG_D2R_P<11>

PEG_D2R_P<13>

PEG_D2R_P<14>

PEG_D2R_P<15>

PEG_D2R_P<7> PEG_D2R_P<6>

PEG_D2R_P<9>

PEG_D2R_P<10>

PEG_D2R_P<8>

PEG_D2R_P<1>

PEG_D2R_P<2>

PEG_D2R_P<3>

PEG_D2R_P<5> PEG_D2R_P<4>

=PEG_R2D_C_N<1> =PEG_R2D_C_N<2>

PEG_D2R_P<0>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<3> =PEG_R2D_C_N<4>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<12>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<5>

=PEG_R2D_C_P<2> =PEG_R2D_C_P<3>

=PEG_R2D_C_P<9> =PEG_R2D_C_P<10> =PEG_R2D_C_P<11>

=PEG_R2D_C_P<7> =PEG_R2D_C_P<8>

=PEG_R2D_C_P<15>

=PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14>

PEG_D2R_N<5>

PEG_D2R_N<3>

TP_CPU_RSVD<21>

TP_CPU_RSVD<23>

TP_CPU_RSVD<22>

TP_CPU_RSVD<20>

TP_CPU_RSVD<65>

TP_CPU_TEST_BR71

TP_CPU_RSVD<18>

TP_CPU_RSVD_TP0

CPU_CFG<17>

CPU_CFG<11>

CPU_CFG<10>

CPU_TEST_BV1_BT1 CPU_TEST_BT71_BT69

CPU_TEST_BV3_BT3

TP_CPU_TEST_BV5

TP_CPU_RSVD<17>

TP_CPU_RSVD<16>

TP_CPU_TEST_BV68

CPU_TEST_BV71_BV69

CPU_THERMD_P CPU_THERMD_N

10 OF 132

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OUT

IN IN

IN

OUT

BI

OUT

IN

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT OUT OUT

IN

OUT OUT OUT OUT

IN

BCLK_ITP

BCLK_ITP*

PEG_CLK

SM_RCOMP2

PM_EXT_TS1*

PRDY* PREQ*

THERMTRIP*

COMP1

COMP2

COMP3

COMP0

PROC_DETECT

PROCHOT*

PECI

CATERR*

RSTIN*

TAPPWRGOOD

VTTPWRGOOD

VCCPWRGOOD_0

SM_DRAMPWROK

VCCPWRGOOD_1

PM_SYNC

RESET_OBS*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

TDO_M

DBR*

TDI_M

TDO

TDI

BCLK*

BCLK

TRST*

TMS

TCK

PM_EXT_TS0*

SM_RCOMP1

SM_RCOMP0

PEG_CLK*

DPLL_REF_SSCLK

DPLL_REF_SSCLK*

SM_DRAMRST*

PWR MANAGEMENTTHERMAL

JTAG & MBP

(SYM 2 OF 11)

MISC

DDR3

MISC

CLOCKS

IN

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPU) (IPU)

(IPU)

(IPD)

(IPU) (IPU)

(IPU)

(GND)

(IPU)

(IPD)

(IPU)

31

47 91

2

1

R1126

750

1/16W

1%

402

MF-LF

21

R1125

1.5K

1%

402

1/16W MF-LF

27

18 31 91

71 91

17 93

25 91

20 91

47 69 91

18 91

20 47 91

2

1

R1102

NO STUFF

402

1/16W MF-LF

5%

68

2

1

R1101

5%

68

MF-LF

1/16W

402

2

1

R1100

MF-LF

1/16W 402

1%

49.9

17 93

2

1

R1112

49.9

MF-LF

402

1%

1/16W

2

1

R1113

1% MF-LF

1/16W 402

49.9

2

1

R1110

20

MF-LF

1/16W

402

1%

2

1

R1111

20

1%

402

1/16W MF-LF

25 91

25

17 91

25

25 91

25 27 91

25 91

17 91

25 91

2

1

R1162

1%

100

MF-LF

1/16W

402

2

1

R1160

1%

MF-LF

1/16W

402

130

2

1

R1161

1%

24.9

402

1/16W MF-LF

2

1

R1150

MF-LF

5%

402

10K

1/16W

2

1

R1151

1/16W MF-LF

5%

402

10K

20 91

2

1

R1170

5%

51

MF-LF

1/16W

402

20 25 91

2

1

R1103

1K

5% MF-LF

402

1/16W

H15

AM7

Y67

P69

N65

N17

T70

T71

P71

T69

T67

Y70

BV40

BP39

BV33

BJ12

AM5

G3

N70

N67

M71

U69

U71

M17

AV64

AV66

J21

L21

N19

W4

Y2

W71

AD71 AC70 AD69 AE66

N61

M69

K69

J64

K62

K65

J62

J67

J69

J70

K71

AK8

AK7

U1000

OMIT

BGA

ARRANDALE

20 91

2

1

R1120

402

1K

5% MF-LF

1/16W

25 91

CPU Clock/Misc/JTAG

SYNC_MASTER=K18_MLB

SYNC_DATE=10/14/2009

PM_MEM_PWRGD

PPCPUVTT_S0

CPU_COMP3 CPU_COMP2

XDP_DBRESET_L

JTAG_CPU_TDO

XDP_CPUPWRGD

PM_SYNC

FSB_CPURST_L

CPU_COMP0

CPU_PROCHOT_L

CPU_PECI

PM_THRMTRIP_L

CPU_CATERR_L

XDP_BPM_L<6>

XDP_BPM_L<4>

PPCPUVTT_S0

PM_EXT_TS_L<0>

GFX_CLK120M_DPLLSS_N

CPU_MEM_RESET_L CPU_SM_RCOMP0

CPU_PWRGD

CPUVTTS0_PGOOD

CPU_SM_RCOMP2

CPU_SM_RCOMP1

PM_EXT_TS_L<1>

GFX_CLK120M_DPLLSS_P

FSB_CLK133M_ITP_N

FSB_CLK133M_CPU_N FSB_CLK133M_ITP_P

PCIE_CLK100M_CPU_P

XDP_PRDY_L XDP_PREQ_L

CPU_COMP1

PLT_RESET_LS1V1_L

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<0>

JTAG_GMCH_TDI

FSB_CLK133M_CPU_P

XDP_TMS

XDP_TCK

PCIE_CLK100M_CPU_N

PLT_RST_BUF_L

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

JTAG_GMCH_TDO

JTAG_CPU_TDI

XDP_TRST_L

TP_CPU_SKTOCC_L

11 OF 132 10 OF 103

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10 12 13 15 25 26 40 71 74

101

91

6 7

10 12 13 15 25 26 40 71 74

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BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI

BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SA_RAS* SA_WE*

SA_CAS*

SA_BS2

SA_BS1

SA_BS0

SA_DQ62 SA_DQ63

SA_DQ60 SA_DQ61

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ54

SA_DQ56

SA_DQ55

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44 SA_DQ45

SA_DQ41 SA_DQ42 SA_DQ43

SA_DQ40

SA_DQ39

SA_DQ37

SA_DQ36

SA_DQ38

SA_DQ35

SA_DQ34

SA_DQ32

SA_DQ31

SA_DQ33

SA_DQ30

SA_DQ29

SA_DQ28

SA_DQ27

SA_DQ26

SA_DQ24 SA_DQ25

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ13

SA_DQ15

SA_DQ14

SA_DQ12

SA_DQ11

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5 SA_DQ6

SA_DQ3 SA_DQ4

SA_DQ1 SA_DQ2

SA_DQ0

SA_MA15

SA_MA14

SA_MA13

SA_MA12

SA_MA11

SA_MA10

SA_MA9

SA_MA7 SA_MA8

SA_MA6

SA_MA5

SA_MA4

SA_MA3

SA_MA2

SA_MA1

SA_MA0

SA_DQS7

SA_DQS6

SA_DQS4 SA_DQS5

SA_DQS3

SA_DQS1 SA_DQS2

SA_DQS0

SA_DQS7*

SA_DQS6*

SA_DQS5*

SA_DQS4*

SA_DQS3*

SA_DQS2*

SA_DQS1*

SA_DQS0*

SA_DM7

SA_DM6

SA_DM5

SA_DM4

SA_DM3

SA_DM2

SA_DM1

SA_DM0

SA_ODT1

SA_ODT0

SA_CS1*

SA_CS0*

SA_CK1*

SA_CKE1

SA_CKE0

SA_CK1

SA_CK0

SA_CK0*

(SYM 3 OF 11)

DDR SYSTEM MEMORY A

SB_DQ0 SB_CK0 SB_DQ1

SB_CK0*

SB_DQ2

SB_CKE0

SB_DQ3 SB_DQ4

SB_CK1

SB_DQ5

SB_CK1*

SB_DQ6 SB_DQ7

SB_CKE1 SB_DQ8 SB_DQ9

SB_CS0* SB_DQ10 SB_CS1* SB_DQ11 SB_DQ12 SB_ODT0 SB_DQ13 SB_ODT1 SB_DQ14 SB_DQ15

SB_DM0

SB_DQ16

SB_DM1

SB_DQ17

SB_DM2

SB_DQ18

SB_DM3

SB_DQ19

SB_DM4

SB_DQ20

SB_DM5

SB_DQ21

SB_DM6

SB_DQ22

SB_DM7 SB_DQ23 SB_DQ24

SB_DQS0*

SB_DQ25

SB_DQS1*

SB_DQ26

SB_DQS2*

SB_DQ27

SB_DQS3*

SB_DQ28

SB_DQS4*

SB_DQ29

SB_DQS5*

SB_DQ30

SB_DQS6*

SB_DQ31

SB_DQS7* SB_DQ32 SB_DQ33 SB_DQS0 SB_DQ34 SB_DQS1 SB_DQ35 SB_DQS2 SB_DQ36 SB_DQS3 SB_DQ37 SB_DQS4 SB_DQ38 SB_DQS5 SB_DQ39 SB_DQS6 SB_DQ40 SB_DQS7 SB_DQ41 SB_DQ42

SB_MA0

SB_DQ43

SB_MA1

SB_DQ44

SB_MA2

SB_DQ45

SB_MA3

SB_DQ46

SB_MA4

SB_DQ47

SB_MA5

SB_DQ48

SB_MA6

SB_DQ49

SB_MA7

SB_DQ50

SB_MA8

SB_DQ51

SB_MA9 SB_DQ52 SB_MA10 SB_DQ53 SB_MA11 SB_DQ54 SB_MA12 SB_DQ55 SB_MA13 SB_DQ56 SB_MA14 SB_DQ57 SB_MA15 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS* SB_RAS* SB_WE*

DDR SYSTEM MEMORY B

(SYM 4 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

29 92

28 29 92

29 92

28 92

29 92

28 29 92

29 92

28 29 92

29 92

28 92

28 29 92

29 92

28 92

29 92

29 30 92

29 92

30 92

29 30 92

29 92

29 30 92

29 92

29 30 92

29 92

30 92

OMIT

BGA

ARRANDALE

U1000

BT38 BH38 BF21

BK43

BM34 BP35

BK36 BH36

BF20

BK24

BH40 BJ47

BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59

AT8 AT6

BK5

BH13

BF9 BF6 BK7 BN8

BN11

BN9 BG17 BK15

BB5

BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21

BB9

BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47

AV7

BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57

AV6

BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66

BE6

BJ66 BF65 AY64 BC70

BE8 BF11 BE11

AY7

AY5

BJ5

BJ7

BL13

BN13

BN21

BL21

BK44

BH44

BH51

BK51

BM60

BP58

BE64

BE62

BT36 BP33

BH34 BH30 BJ28 BF40 BN28 BN25

BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28

BF43 BL47

BL38 BF38

BGA

ARRANDALE

OMIT

U1000

BV43 BV41 BV24

BU46

BU33 BV34

BV38 BU39

BT26

BT24

BP46 BT43

BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67

BA2 AW2

BR6 BR8 BJ4 BK2

BU9 BV10 BR10 BT12 BT15 BV15

BD1

BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19

BE4

BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54

AY1

BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60

BC2

BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67

BF2

BK70 BK67 BD71 BD69

BH2

BG4

BG1

BD4

BE2

BN4

BM3

BV13

BU12

BT17

BT19

BT50

BT52

BU56

BV55

BV62

BU63

BJ69

BG69

BT34 BP30

BU42 BU26 BT29 BT45 BV26 BU23

BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27

BV45 BU49

BT40 BT41

CPU DDR3 Interfaces

SYNC_MASTER=K17_REF

SYNC_DATE=04/29/2009

MEM_B_DQ<27>

MEM_B_DQ<0>

MEM_B_CLK_P<0>

MEM_B_DQ<1>

MEM_B_CLK_N<0>

MEM_B_DQ<2>

MEM_B_CKE<0>

MEM_B_DQ<3> MEM_B_DQ<4>

MEM_B_CLK_P<1>

MEM_B_DQ<5>

MEM_B_CLK_N<1>

MEM_B_DQ<6> MEM_B_DQ<7>

MEM_B_CKE<1> MEM_B_DQ<8> MEM_B_DQ<9>

MEM_B_CS_L<0> MEM_B_DQ<10>

MEM_B_CS_L<1> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_ODT<0> MEM_B_DQ<13> MEM_B_ODT<1> MEM_B_DQ<14> MEM_B_DQ<15>

MEM_B_DM<0> MEM_B_DQ<16>

MEM_B_DM<1> MEM_B_DQ<17>

MEM_B_DM<2> MEM_B_DQ<18>

MEM_B_DM<3> MEM_B_DQ<19>

MEM_B_DM<4> MEM_B_DQ<20>

MEM_B_DM<5> MEM_B_DQ<21>

MEM_B_DM<6> MEM_B_DQ<22>

MEM_B_DM<7> MEM_B_DQ<23> MEM_B_DQ<24>

MEM_B_DQS_N<0> MEM_B_DQ<25>

MEM_B_DQS_N<1> MEM_B_DQ<26>

MEM_B_DQS_N<2>

MEM_B_DQS_N<3> MEM_B_DQ<28>

MEM_B_DQS_N<4> MEM_B_DQ<29>

MEM_B_DQS_N<5> MEM_B_DQ<30>

MEM_B_DQS_N<6> MEM_B_DQ<31>

MEM_B_DQS_N<7> MEM_B_DQ<32> MEM_B_DQ<33>

MEM_B_DQS_P<0> MEM_B_DQ<34>

MEM_B_DQS_P<1> MEM_B_DQ<35>

MEM_B_DQS_P<2> MEM_B_DQ<36>

MEM_B_DQS_P<3> MEM_B_DQ<37>

MEM_B_DQS_P<4> MEM_B_DQ<38>

MEM_B_DQS_P<5> MEM_B_DQ<39>

MEM_B_DQS_P<6> MEM_B_DQ<40>

MEM_B_DQS_P<7> MEM_B_DQ<41> MEM_B_DQ<42>

MEM_B_A<0> MEM_B_DQ<43>

MEM_B_A<1> MEM_B_DQ<44>

MEM_B_A<2> MEM_B_DQ<45>

MEM_B_A<3> MEM_B_DQ<46>

MEM_B_A<4> MEM_B_DQ<47>

MEM_B_A<5> MEM_B_DQ<48>

MEM_B_A<6> MEM_B_DQ<49>

MEM_B_A<7> MEM_B_DQ<50>

MEM_B_A<8> MEM_B_DQ<51>

MEM_B_A<9> MEM_B_DQ<52>

MEM_B_A<10> MEM_B_DQ<53>

MEM_B_A<11> MEM_B_DQ<54>

MEM_B_A<12> MEM_B_DQ<55>

MEM_B_A<13> MEM_B_DQ<56>

MEM_B_A<14> MEM_B_DQ<57>

MEM_B_A<15> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L

MEM_A_CLK_P<0>

MEM_A_DQ<4>

MEM_A_CS_L<1>

MEM_A_A<2>

MEM_A_CLK_N<0>

MEM_A_RAS_L MEM_A_WE_L

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<60> MEM_A_DQ<61>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<54>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<44> MEM_A_DQ<45>

MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<38>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<33>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<13>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5> MEM_A_DQ<6>

MEM_A_DQ<3>

MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<0>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<7> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<4> MEM_A_DQS_P<5>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CLK_N<1> MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CLK_P<1>

12 OF 132 11 OF 103

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OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT

IN

OUT

VCAP0_15

VCAP0_17

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5

VCC_7

VCC_6

VCC_9

VCC_10

VCC_12

VCC_11

VCC_14

VCC_13

VCC_15

VCC_17

VCC_16

VCC_18 VCC_19 VCC_20 VCC_21 VCC_22

VCC_25

VCC_24

VCC_23

VCC_26 VCC_27

VCC_29 VCC_30

VCC_28

VCC_32

VCC_31

VCC_34

VCC_33

VCC_35

VCC_37

VCC_36

VCC_38

VCC_40

VCC_39

VCC_42

VCC_41

VCC_43 VCC_44 VCC_45 VCC_46 VCC_47

VCC_50

VCC_49

VCC_51 VCC_52 VCC_53

VCC_55

VCC_54

VCC_56

VCC_58

VCC_57

VCC_60

VCC_59

VCC_62

VCC_61

VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78

VCC_81

VCC_79 VCC_80

VCC_83

VCC_82

VCC_84 VCC_85 VCC_86 VCC_87

VCC_89

VCC_88

VCAP0_1 VCAP0_2

VCAP0_4

VCAP0_3

VCAP0_5 VCAP0_6 VCAP0_7 VCAP0_8 VCAP0_9

VCAP0_12

VCAP0_10 VCAP0_11

VCAP0_14

VCAP0_16

VCAP0_19

VCAP0_18

VCAP0_20 VCAP0_21 VCAP0_22 VCAP0_23 VCAP0_24 VCAP0_25 VCAP0_26 VCAP0_27

VCAP1_2

VCAP1_1

VCAP1_5

VCAP1_3 VCAP1_4

VCAP1_7

VCAP1_6

VCAP1_8

VCAP1_10

VCAP1_9

VCAP1_13

VCAP1_11 VCAP1_12

VCAP1_15

VCAP1_14

VCAP1_18

VCAP1_17

VCAP1_16

VCAP1_20

VCAP1_19

VCAP1_23

VCAP1_21 VCAP1_22

VCAP1_24 VCAP1_25

VCAP1_27

VCAP1_26

VCAP0_13

VCC_8

VCC_48

(SYM 8 OF 11)

CPU CORE SUPPLY

POWER

VSS_SENSE_VTT

VTT_SENSE

VSS_SENSE

VCC_SENSE

ISENSE

VID2 VID3 VID4

PSI*

VTT0_9

VTT0_22

VTT0_24

VTT0_23

VTT0_26

VTT0_25

VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34

VTT0_36

VTT0_35

VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 VTT0_45 VTT0_46 VTT0_47 VTT0_48 VTT0_49 VTT0_50 VTT0_51 VTT0_52 VTT0_53 VTT0_54 VTT0_55 VTT0_56 VTT0_57 VTT0_58 VTT0_59

VTT0_62

VTT0_60 VTT0_61

VTT0_63 VTT0_64 VTT0_65

VTT0_67

VTT0_66

VTT0_68

VTT0_70

VTT0_69

VTT0_72

VTT0_71

VTT0_73

VTT0_4

VTT0_6

VTT0_5

VTT0_7 VTT0_8

VTT0_10 VTT0_11

VTT0_13

VTT0_12

VTT0_16

VTT0_15

VTT0_14

VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21

VID5 VID6

VTT_SELECT1

PROC_DPRSLPVR

VTT0_1 VTT0_2 VTT0_3

VID1

VID0

VCCPLL1 VCCPLL2

VCCPLL4

VCCPLL3

VCCPLL5

VDDQ_CK1 VDDQ_CK2

1.8V

(SYM 6 OF 11)

1.1V RAIL POWER

CPU VIDS

SENSE LINES

POWER

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VTT_SELECT: 1 = 1.05V, 0 = 1.1V

Do not connect to power supply,

Arrandale: 1.05V

(Controlled by VTT_SELECT pin)

Clarksfield: 1.1V

but provide bypass caps on PCB.

NOTE: VCAP1 is sourced by CPU

NOTE: VCAP0 is sourced by CPU Do not connect to power supply, but provide bypass caps on PCB.

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

91

15 69 91

71 91

50 69 91

2

1

R1301

1/16W

1%

100

402

MF-LF

PLACE_NEAR=U1000.F63:25.4MM

69 91

2

1

R1300

1/16W

1%

100

402

MF-LF

PLACE_NEAR=U1000.F64:25.4MM

2

1

R1305

1%

402

MF-LF

10

1/16W

PLACE_NEAR=U1000.N13:25.4MM

2

1

R1306

10

1/16W

1%

402

MF-LF

PLACE_NEAR=U1000.R12:25.4MM

AF42

A43

A47

A50

A54

A57

B42

B46

B49

B53

B56

AF44

B60

D43

D45

D47

D48

D50

D52

D54

D55

D57

AF46

D59

E42

E46

E50

E53

E57

E60

F55

G44

G51

AF48

G55

G60

H44

H51

H60

J55

K44

K51

K60

L55

AF50

M44

M51

M60

N42

N44

N48

N51

N55

P60

R41

AF51

R44

R48

R51

R55

U41

U44

U48

U51

U55

W41

AF53

W44

W48

W51

W55

AA41

AA44

AA48

AA51

AA55

AB41

AF55

AB44

AB48

AB51

AB55

AD41

AD44

AD48

AD51

AD55

AF41

AF57

AY39

AY42

AY46

BB37

BB41

BB44

BD37

AK39

AK42

AK46

AL39

AL42

AL46

AN39

AN42

BD41

AN46

AR37

AR41

AR44

AU37

AU41

AU44

AW39

AW42

AW46

BD44

AY50

AY53

AY57

BB48

BB51

BB55

BD48

AK50

AK53

AK57

AL50

AL53

AL57

AN50

AN53

BD51

AN57

AR48

AR51

AR55

AU48

AU51

AU55

AW50

AW53

AW57

BD55

U1000

OMIT

BGA

ARRANDALE

N13

AN1

AW35

AW60

AN9

AY10

R23

R24

AY60

R26

R28

R30

R32

R33

R35

U23

U24

U26

U28

BB59

U30

U32

U33

U35

W23

W24

W26

W28

W30

W32

BB60

W33

W35

AD30

AD32

AD33

AD35

AD37

AD39

AF30

AF32

BD59

AF33

AF35

AF37

AF39

AK33

AK35

AL12

AL14

AL15

AL17

BD60

AL59

AL60

AM10

AN12

AN14

AN15

AN17

AN33

AN35

AN59

BF59

AN60

AR12

AR59

AR60

AU12

AU59

AU60

AW12

AW14

AW33

BF60

R12

F63

D66

D64

B63

A62

D62

D61

A61

BB12

BB14

R37

R39

U37

W37

W39

F64

F68

F66

A41

U1000

ARRANDALE

BGA

OMIT

CPU Power (1 of 2)

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

CPU_VCCSENSE_P

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU

CPU_VID<0>

TP_CPU_VTT_SELECT

CPU_VID<6>

CPU_VID<5>

CPU_PSI_L

CPU_VID<4>

CPU_VCCSENSE_N

PP1V8_S0

PP1V5_S3_CPU_VCCDDR_CLK

MIN_LINE_WIDTH=0.4mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V

PPVCORE_S0_CPU_VCAP0

CPU_VTTSENSE_N

CPU_VTTSENSE_P

PPCPUVTT_S0

PM_DPRSLPVR

CPUIMVP_IMON

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

13 OF 132 12 OF 103

7

16

6 7

12 15 50 69

6 7

12 15 50 69

6 7

16 72 73 88

101

16

7

16

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15 25 26 40 71 74

101

www.vinafix.vn

VAXG35

VTT1_7

VTT1_9 VTT1_10

VTT1_8

VTT1_5

VAXG3

VAXG2

VAXG1

VSSAXG_SENSE

VAXG_SENSE

VCAP2_19

VCAP2_17 VCAP2_18

VCAP2_16

VCAP2_14 VCAP2_15

VCAP2_12 VCAP2_13

VCAP2_11

VCAP2_10

VCAP2_9

VCAP2_8

VCAP2_6 VCAP2_7

VCAP2_5

VCAP2_4

VCAP2_3

VCAP2_1 VCAP2_2

VTT1_11

VTT1_6

VTT1_4

VTT1_3

VTT1_2

VTT1_1

VAXG37

VAXG36

VAXG33 VAXG34

VAXG32

VAXG31

VAXG30

VAXG27

VAXG29

VAXG28

VAXG25 VAXG26

VAXG23 VAXG24

VAXG22

VAXG20 VAXG21

VAXG19

VAXG17 VAXG18

VAXG14

VAXG16

VAXG15

VAXG13

VAXG12

VAXG11

VAXG10

VAXG9

VAXG8

VAXG7

VAXG6

VAXG5

VAXG4

VTT1_21

VTT1_20

VTT1_18 VTT1_19

VTT1_17

VTT1_16

VTT1_15

VTT1_14

VTT1_13

VTT1_12

VTT0_DDR9

VTT0_DDR8

VTT0_DDR7

VTT0_DDR6

VTT0_DDR5

VTT0_DDR4

VTT0_DDR3

VTT0_DDR2

VTT0_DDR1

VTT0_DDR

VDDQ36

VDDQ35

VDDQ34

VDDQ33

VDDQ31 VDDQ32

VDDQ30

VDDQ29

VDDQ28

VDDQ27

VDDQ26

VDDQ24 VDDQ25

VDDQ23

VDDQ21 VDDQ22

VDDQ20

VDDQ19

VDDQ18

VDDQ17

VDDQ16

VDDQ15

VDDQ13 VDDQ14

VDDQ12

VDDQ11

VDDQ10

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

GFX_IMON

VDDQ1

GFX_DPRSLPVR

GFX_VR_EN

GFX_VID6

GFX_VID5

GFX_VID4

GFX_VID3

GFX_VID2

GFX_VID1

GFX_VID0

(SYM 7 OF 11)

POWER

PEG & DMI

LINES

SENSE

GRAPHICS VIDS

GRAPHICS

DDR3 -1.5 V RAILS

OUT

OUT OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Do not connect to power supply, but provide bypass caps on PCB.

NOTE: VCAP2 is sourced by CPU

OMIT

ARRANDALE

BGA

U1000

AL71

AL69

AF71 AG67 AG70 AH71 AN71 AM67 AM70

AH69

AN32

AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10

AN30

AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15

AN28

AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17

AN26 AN24 AN23 AN21 AN19 AL32

AF12

AK62

AB60 AB59 AA60 AA59

W60 W59 U60 U59 R60 R59

AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59

BU40

BG43 BF16 BF15 BD35 BD33 BD32 BD30 BD28 BD26 BD24

BU35

BD23 BD21 BD19 BD17 BD15 BB35 BB33 BB32 BB30 BB28

BU28

BB26 BB24 BB23 BB21 BB19 BB17 BB15

BN38 BM25 BL30 BJ38 BH32 BH28

AF10

AW32 AW30 AW28 AW26 AW24 AW23 AW21 AW19 AW17 AW15

W21

R19 R17

AD15 AD14 AD12 AB12 AA12 W17 W15 W14

W19

W12 R15

U21 U19 U17 U15 U14 U12 R21

8

91

PLACE_NEAR=U1000.AF10:25.4MM

402

1%

100

1/16W MF-LF

R1401

1

2

MF-LF

402

1/16W

4.7K

5%

R1405

1

2

70 91

PLACE_NEAR=U1000.AF12:25.4MM

100

1/16W

1%

402

MF-LF

R1400

1

2

70 91

8

91

8

91

8

91

8

91

8

91

8

91

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

CPU Power (2 of 2)

PPVCORE_S0_GFX

PPCPUVTT_S0

PPVCORE_S0_CPU_VCAP2

GFX_VID<3>

GFX_VID<5> GFX_VID<6>

GFX_VID<0> GFX_VID<1>

GFX_VSENSE_N

PPVCORE_S0_GFX

GFX_VSENSE_P

GFXIMVP_IMON

GFX_VID<2>

GFX_DPRSLPVR

GFX_VR_EN

GFX_VID<4>

PPCPUVTT_S0

PP1V1R1V05_S0_CPU_VTT0_DDR

PPCPUDDR_ISNS

14 OF 132 13 OF 103

7

13 24 50 70

6 7

10 12 13 15 25 26 40 71 74

101

7

24

7

13 24 50 70

6 7

10 12 13 15 25 26 40 71 74

101

15

7

16 31 57

www.vinafix.vn

VSS77

VSS11

VSS16

VSS110 VSS111

VSS113

VSS112

VSS114

VSS116

VSS115

VSS118

VSS117

VSS119

VSS121

VSS120

VSS122

VSS124

VSS123

VSS125 VSS126 VSS127 VSS128 VSS129

VSS131

VSS130

VSS133

VSS132

VSS134

VSS136

VSS135

VSS137 VSS138 VSS139

VSS141

VSS140

VSS142 VSS143 VSS144

VSS147

VSS145 VSS146

VSS149

VSS148

VSS150

VSS1 VSS2 VSS3

VSS5

VSS4

VSS6 VSS7 VSS8

VSS10

VSS9

VSS13

VSS12

VSS14 VSS15

VSS17 VSS18 VSS19 VSS20 VSS21

VSS23

VSS22

VSS25

VSS24

VSS26

VSS28

VSS27

VSS29 VSS30 VSS31

VSS33

VSS32

VSS34 VSS35 VSS36

VSS39

VSS37 VSS38

VSS41

VSS40

VSS43

VSS42

VSS44

VSS46

VSS45

VSS47

VSS49

VSS48

VSS51

VSS50

VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62

VSS64

VSS63

VSS66

VSS65

VSS67

VSS69

VSS68

VSS71

VSS70

VSS72 VSS73 VSS74 VSS75

VSS76

VSS80

VSS78 VSS79

VSS82

VSS81

VSS85

VSS83 VSS84

VSS87

VSS86

VSS90

VSS88 VSS89

VSS92

VSS91

VSS93

VSS95

VSS94

VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106

VSS108

VSS107

VSS109

(SYM 9 OF 11)

VSS215 VSS216

VSS214

VSS213

VSS212

VSS210 VSS211

VSS207 VSS208 VSS209

VSS205 VSS206

VSS204

VSS203

VSS202

VSS200 VSS201

VSS199

VSS197 VSS198

VSS195 VSS196

VSS194

VSS192 VSS193

VSS190 VSS191

VSS189

VSS187 VSS188

VSS185

VSS184

VSS186

VSS182 VSS183

VSS181

VSS180

VSS179

VSS177 VSS178

VSS176

VSS175

VSS174

VSS172 VSS173

VSS171

VSS169 VSS170

VSS166 VSS167 VSS168

VSS164 VSS165

VSS163

VSS162

VSS161

VSS159 VSS160

VSS158

VSS156 VSS157

VSS154 VSS155

VSS153

VSS152

VSS151

VSS227

VSS226

VSS228

VSS230

VSS229

VSS231

VSS239 VSS240

VSS232 VSS233 VSS234 VSS235 VSS236

VSS238

VSS237

VSS241

VSS250 VSS251

VSS249

VSS247

VSS242 VSS243

VSS246

VSS245

VSS244

VSS248

VSS261

VSS260

VSS259

VSS253

VSS252

VSS254

VSS256

VSS255

VSS257 VSS258

VSS270 VSS271

VSS268

VSS264

VSS263

VSS262

VSS265 VSS266 VSS267

VSS269

VSS272

VSS280 VSS281

VSS273 VSS274

VSS276

VSS275

VSS277 VSS278 VSS279

VSS282

VSS292

VSS290 VSS291

VSS288

VSS284

VSS283

VSS286

VSS285

VSS287

VSS289

VSS294

VSS293

VSS296

VSS295

VSS297 VSS298 VSS299 VSS300

VSS217 VSS218

VSS220

VSS219

VSS222

VSS221

VSS223

VSS225

VSS224

(SYM 10 OF 11)

VSS358

VSS363

VSS301

VSS429

VSS428

VSS427

VSS426

VSS423

VSS425

VSS424

VSS421 VSS422

VSS420

VSS418 VSS419

VSS416 VSS417

VSS414

VSS413

VSS415

VSS411 VSS412

VSS408 VSS409 VSS410

VSS406 VSS407

VSS405

VSS403 VSS404

VSS400

VSS402

VSS401

VSS398 VSS399

VSS397

VSS396

VSS395

VSS393 VSS394

VSS392

VSS391

VSS390

VSS388 VSS389

VSS387

VSS385 VSS386

VSS383 VSS384

VSS382

VSS380 VSS381

VSS377

VSS379

VSS378

VSS375 VSS376

VSS372 VSS373 VSS374

VSS371

VSS370

VSS367

VSS369

VSS368

VSS366

VSS365

VSS364

VSS362

VSS360 VSS361

VSS357

VSS359

VSS355 VSS356

VSS352 VSS353 VSS354

VSS351

VSS350

VSS347

VSS349

VSS348

VSS345 VSS346

VSS342

VSS344

VSS343

VSS340 VSS341

VSS339

VSS337 VSS338

VSS334 VSS335 VSS336

VSS332 VSS333

VSS330 VSS331

VSS329

VSS327 VSS328

VSS326

VSS325

VSS324

VSS322 VSS323

VSS321

VSS319 VSS320

VSS318

VSS317

VSS316

VSS314 VSS315

VSS313

VSS312

VSS311

VSS309 VSS310

VSS308

VSS307

VSS306

VSS305

VSS304

VSS303

VSS302

VSS432 VSS433

VSS431

VSS430

(SYM 11 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AY4

AY8

AY12

AY14

AY15

AY17

AY19

AY21

AY23

AY24

BU25

AY26

AY28

AY30

AY32

AY33

AY35

AY37

AY41

AY44

AY48

BU32

AY51

AY55

AY59

AY62

AY66

AY71

BA70

BB1

BB7

BB39

BU37

BB42

BB46

BB50

BB53

BB57

BB62

BB71

BD14

BD39

BD42

BU44

BD46

BD50

BD53

BD57

BE1

BE9

BE65

BE70

BF8

BF13

BU48

BF30

BF62

BG36

BG51

BH15

BH20

BH24

BH47

BH55

BH57

BU51

BH70

BJ1

BJ9

BJ21

BJ64

BK10

BK34

BK53

BK60

BK63

BU55

BL20

BL28

BL40

BL48

BL55

BL57

BM17

BM24

BM32

BM44

BU58

BM51

BM70

BN6

BN64

AR21

BP42

AR23

AR24

AR26

AR28

AR30

AR32

AR33

AR35

AR39

AR42

BU7

AR46

AR50

AR53

AR57

AR62

AT10

AT64

AU4

AU14

AU15

BU11

AU17

AU19

AU21

AU23

AU24

AU26

AU28

AU30

AU32

AU33

BU14

AU35

AU39

AU42

AU46

AU50

AU53

AU57

AU62

AU70

AV1

BU18

AV9

AW37

AW41

AW44

AW48

AW51

AW55

AW59

AW62

AW67

BU21

BU62

U1000

BGA

ARRANDALE

OMIT

AA30

AA32

AA33

AA35

AA37

AA39

AA42

AA46

AA50

AA53

AA57

AA62

AA64

AA66

AB9

AB14

AB15

AB17

AB19

AB21

AB23

AB24

AB26

AB28

AB30

AB32

AB33

AB35

AB37

AB39

AB42

AB46

AB50

AB53

AB57

AB62

AB70

AC1

AC5

AC10

AC64

AC67

AD4

AD42

AD46

AD50

AD53

AD57

AD62

AE64

AE70

AF1

AF62

AF69

AG6

AG9

AG64

AH4

AH15

AH17

AH19

AH21

C68

AH23

E5

AH39

AH24

A64

BN1

AH26

A66

AH41

AH28

E68

BN71

AH30

E69

AH42

AH32

F71

BR3

AH33

H71

AH44

AH35

R14

BR68

AH37

BL1

AH46

BL71

BR69

AH48

BT68

AH50

BV64

AH51

BV66

AH53

AH55

AH57

AH62

AJ70

AK15

AK17

AK19

AK21

AK23

AK24

AK26

AK28

AK30

AK32

AK37

AK41

AK44

AK48

AK51

AK55

AK64

AK70

AL1

AL33

AL35

AL37

AL41

AL44

AL48

AL51

AL55

AL62

AM8

AM64

AN4

AN5

AN37

AN41

AN44

AN48

AN51

AN55

AN62

AP64

AP70

AR1

AR4

AR14

AR15

AR17

AR19

U1000

OMIT

BGA

ARRANDALE

B40

A8

A12

A15

A19

A22

A26

A29

A33

A36

A40

A45

A48

A52

A55

A59

B44

B48

B51

B55

B58

B62

B65

D6

D10

D13

D17

D20

D24

D27

D31

D34

D38

D41

E12

E16

E30

E33

E37

F4

F20

F28

F47

F48

F61

G15

G20

G24

G30

G43

G47

G48

G53

G57

G70

H1

H36

H43

H53

J9

J40

J47

J48

J57

J65

K4

K6

K11

K17

K25

K32

K34

K36

K43

K53

K64

L13

L47

L48

L57

L70

M1

M36

M42

M53

N15

N21

N30

N46

N50

N53

N57

N63

P4

R5

R42

R46

R50

R53

R57

R62

R70

T1

U4

U9

U39

U42

U46

U50

U53

U57

U62

U64

V70

W1

W6

W42

W46

W50

W53

W57

W62

W69

AA4

AA14

AA15

AA17

AA19

AA21

AA23

AA24

AA26

AA28

U1000

OMIT

BGA

ARRANDALE

CPU Grounds

SYNC_MASTER=K17_REF

SYNC_DATE=04/29/2009

15 OF 132 14 OF 103

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OUT OUT OUT OUT OUT OUT OUT OUT OUT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1664-C1687):

3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402

VTT (CPU Uncore) DECOUPLING

PLACEMENT_NOTE (C1625-C1634):

PLACEMENT_NOTE (C1653-C1656):

VTT0_DDR DECOUPLING

Instead call out appropriate BOM GROUP defined in tables above.

IMAX @ 900mV

22.5

40A

VID[2:0] = Reserved (111) VID[5:3] = GPU Gain Setting (See below)

NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.

18

CPU Gain Setting

90A

70A

20A 30A

001

Intel recommends all option straps should be provided in layout

CPU Power On Configuration (POC) Straps

Equivalent Gain

45 30

15

12.857 10

PSI# = Reserved (0)

DPRSLPVR = 1 - IMVP-6.5 compliant controller

VID[6] = Reserved (0)

000

111

110

101

100

011

010

50A 60A

PLACEMENT_NOTE (C1635-C1648):

PLACEMENT_NOTE (C1695-C1697):

PLACEMENT_NOTE (C1657-C1663):

3x 1uF 0402

PLACEMENT_NOTE (C1600-C1624):

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form Factor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

CPU VCore HF and Bulk Decoupling

3x 470uF 4.5mOhm, 1x 330uF, 15x 22uF 0603, 25x 1uF 0402

MF-LF

1/16W

5%

402

1K

R1600

1

2

Place near inductors on bottom side.

NO STUFF

C1641

22UF

20%

6.3V

2

X5R-CERM 603

1

MF-LF

1/16W

5%

402

1K

R1602

1

2

MF-LF

1/16W

5%

402

1K

R1601

1

2

MF-LF

1/16W

5%

402

1K

CPUPOC3U

R1603

1

2

MF-LF

1/16W

5%

402

1K

NO STUFF

R1606

1

2

MF-LF

1/16W

5%

402

1K

R1607

1

2

5%

402

1K

CPUPOC4U

MF-LF

1/16W

R1604

1

2

MF-LF

1/16W

5%

402

1K

CPUPOC5U

R1605

1

2

MF-LF

402

1K

5%

1/16W

R1616

1

2

1K

402

5% 1/16W MF-LF

NO STUFF

R1617

1

2

MF-LF

1/16W

5%

1K

CPUPOC5D

402

R1615

1

2

MF-LF

1/16W

CPUPOC4D

402

5%

1K

R1614

1

2

NO STUFF

5%

1K

1/16W MF-LF

402

R1612

1

2

MF-LF

1/16W

5%

402

1K

CPUPOC3D

R1613

1

2

NO STUFF

MF-LF

402

1K

1/16W

5%

R1610

1

2

MF-LF

1/16W

5%

402

1K

NO STUFF

R1611

1

2

1K

402

5% 1/16W MF-LF

NO STUFF

R1608

1

2

1K

5% 1/16W MF-LF

402

R1618

1

2

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

12 69 91

6.3V X5R-CERM 603

Place near inductors on bottom side.

1

2

22UF

20%

C1635

NO STUFF

1UF

Place on bottom side of U1000..

10% X5R

16V 402

1

2

C1600 C1607

2

1

402

16V X5R

1UF

10%

C1606

1UF

402

2

1

16V X5R

10%

C1605

2

1

402

16V X5R

1UF

10%

C1604

1UF

2

1

402

16V X5R

10%

C1611

2

1

402

16V X5R

1UF

10%

C1610

2

1

402

16V X5R

1UF

10%

C1609

2

1

402

16V X5R

1UF

10%

C1608

2

1

402

16V X5R

1UF

10%

C1624

2

1

402

16V X5R

1UF

10%

C1623

2

1

402

16V X5R

10%

1UF

C1622

2

1

402

16V X5R

1UF

10%

C1621

2

1

402

16V X5R

1UF

10%

C1601

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000..

C1620

2

1

402

16V X5R

1UF

10%

C1619

16V 402

2

1

X5R

1UF

10%

C1618

2

1

402

16V X5R

1UF

10%

C1617

2

1

402

16V X5R

1UF

10%

2

1

402

16V X5R

1UF

10%

C1616C1615

2

1

402

16V X5R

1UF

10%

C1614

2

1

402

16V X5R

1UF

10%

C1613

2

1

402

16V X5R

1UF

10%

C1612

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

1UF

C1675

1

2

402

X5R

10V

10%

C1674

Place on bottom side of U1000.

1UF

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1687

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1686

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1673

1

2

402

X5R

10V

10%

1UF

Place on bottom side of U1000.

C1685

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1672

1

2

10% 402

X5R

10V

Place on bottom side of U1000.

1UF

C1671

1

2

402

X5R

10% 10V

Place on bottom side of U1000.

1UF

C1684

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1683

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1670

1

2

10% X5R

402

10V

C1682

402

Place on bottom side of U1000.

1UF

1

2

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1669

1

2

402

X5R

10V

10%

C1681

Place on bottom side of U1000.

1UF

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1668

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1680

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1667

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1666

1

2

402

X5R

10V

10%

6.3V

22UF

603

Place near inductors on bottom side.

1

2

C1643

X5R-CERM

20%

Place on bottom side of U1000.

1UF

C1679

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1678

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

C1665

1

2

402

X5R

10V

1UF

10%

Place on bottom side of U1000.

1UF

C1677

1

2

402

X5R

10% 10V

10V

C1664

Place on bottom side of U1000.

1UF

1

2

10% X5R

402

2

1

Place on bottom side of U1000.

1UF

C1676

402

X5R

10% 10V

Place on bottom side of U1000.

1UF

C1697

1

2

402

X5R

10V

10%

Place on bottom side of U1000.

1UF

C1696

1

2

402

X5R

10V

10%

20%

603

6.3V

Place near inductors on bottom side.

1

2

X5R-CERM

C1644

22UF

Place on bottom side of U1000.

1UF

C1695

1

2

402

X5R

10V

10%

21

L1695

0603

30-OHM-5A

C1633

2

1

22UF

603

X5R-CERM

6.3V

20%

Place near U1000 on bottom side.

22UF

C1629

6.3V

2

1

603

X5R-CERM

20%

X5R-CERM

6.3V

20%

2

1

C1626

22UF

603

Place near U1000 on bottom side.

NO STUFF

C1637

Place near inductors on bottom side.

2

1

603

6.3V X5R-CERM

22UF

20%

C1638

Place near inductors on bottom side.

2

1

603

6.3V

20%

22UF

X5R-CERM

Place near inductors on bottom side.

2

1

603

6.3V X5R-CERM

20%

C1640

22UF

20%

Place near inductors on bottom side.

2

1

603

C1645

X5R-CERM

6.3V

22UF

20%

22UF

Place near inductors on bottom side.

2

1

X5R-CERM

6.3V 603

C1647

C1691

1

2

22UF

6.3V 603

X5R-CERM

20%

2

1

C1694

22UF

20%

6.3V X5R-CERM 603

20%

6.3V X5R-CERM 603

2

1

C1698

22UF

C1699

1

2

603

X5R-CERM

6.3V

20%

NO STUFF

C16A0

1

2

CASE-B2

11V ELEC

62UF

20%

NO STUFF

CASE-B2

ELEC

20%

C16A1

11V

62UF

1

2

C16A2

NO STUFF

1

2

CASE-B2

11V ELEC

62UF

20%

NO STUFF

C16A3

1

2

CASE-B2

11V ELEC

62UF

20%

NO STUFF

C16A4

1

2

CASE-B2

11V ELEC

62UF

20%

C1649

3 2

1

D2T-SM2

POLY-TANT

2.0V

20%

330UF

C1627

603

6.3V

20%

2

22UF

X5R-CERM

Place near U1000 on bottom side.

1

C1602

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000..

1

NO STUFF

C1628

22UF

X5R-CERM

20%

Place near U1000 on bottom side.

2

6.3V 603

C1603

Place on bottom side of U1000..

2

1

402

16V X5R

1UF

10%

X5R-CERM 603

Place near inductors on bottom side.

C1639

1

22UF

20%

6.3V

2

NO STUFF

C1634

2

1

22UF

X5R-CERM

6.3V

20% 603

20%

6.3V X5R-CERM 603

Place near inductors on bottom side.

C1646

1

2

22UF

NO STUFF

NO STUFF 22UF

603

X5R-CERM

6.3V

Place near U1000 on bottom side.

1

2

C1630

20%

NO STUFF

22UF

6.3V X5R-CERM 603

2

Place near U1000 on bottom side.

C1631

1

20%

22UF

C1648

NO STUFF

2

1

6.3V X5R-CERM 603

NO STUFF

C1632

22UF

6.3V X5R-CERM 603

20%

Place near U1000 on bottom side.

1

2

D2T-SM

POLY-TANT

C1650

1

23

2.0V

20%

470UF-4MOHM 470UF-4MOHM

C1651

D2T-SM

20%

2.0V POLY-TANT

1

23

D2T-SM

2.0V POLY-TANT

20%

C1652

1

23

470UF-4MOHM

X5R-CERM

22UF

C1653

6.3V

Place on bottom side of U1000.

603

20%

1

2

Place on bottom side of U1000.

X5R-CERM 603

20%

6.3V

C1654

1

2

22UF

Place on bottom side of U1000.

X5R-CERM 603

20%

6.3V

C1655

1

2

22UF

Place on bottom side of U1000.

X5R-CERM 603

20%

6.3V

1

2

22UF

C1656

Place on bottom side of U1000..

603

X5R

10UF

20%

6.3V

C1663

1

2

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

C1662

1

2

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

C1661

1

2

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

C1660

1

2

603

X5R

10UF

6.3V

20%

Place on bottom side of U1000..

C1659

1

2

X5R 603

10UF

6.3V

20%

Place on bottom side of U1000..

C1658

1

2

10UF

603

6.3V

20%

Place on bottom side of U1000..

X5R

C1657

1

2

C1688

330UF

D2T-SM2

20%

2.0V POLY-TANT

3 2

1

D2T-SM2

POLY-TANT

2.0V

20%

330UF

C1689

1

23

330UF

D2T-SM2

POLY-TANT

2.0V

20%

C1690

1

23

SYNC_MASTER=K17_WFERRY

CPU Non-GFX Decoupling (1 of 2)

SYNC_DATE=06/09/2009

CPUPOC_IMAX_0_20

CPUPOC3D,CPUPOC4D,CPUPOC5U

CPUPOC_IMAX_20_30

CPUPOC3D,CPUPOC4U,CPUPOC5D

CPUPOC_IMAX_DIS

CPUPOC3D,CPUPOC4D,CPUPOC5D

CPUPOC3U,CPUPOC4U,CPUPOC5U

CPUPOC_IMAX_70_90

CPUPOC3U,CPUPOC4D,CPUPOC5U

CPUPOC_IMAX_50_60

CPUPOC3U,CPUPOC4U,CPUPOC5D

CPUPOC_IMAX_60_70

CPUPOC3D,CPUPOC4U,CPUPOC5U

CPUPOC_IMAX_30_40 CPUPOC_IMAX_40_50

CPUPOC3U,CPUPOC4D,CPUPOC5D

PPVCORE_S0_CPU

PP1V1R1V05_S0_CPU_VTT0_DDR

VOLTAGE=1.1V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

CPU_PSI_L

PM_DPRSLPVR

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PPCPUVTT_S0

CPU_VID<5> CPU_VID<6>

PPCPUVTT_S0

16 OF 132 15 OF 103

6 7

12 50 69

13

6 7

10 12 13 15 25 26 40 71 74

101

6 7

10 12 13 15

25 26 40 71 74

101

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VCAP1 (CPU BSC Package) DECOUPLING

12x 1uF 0402

PLACEMENT_NOTE (C1712-C1723):

Memory (CPU VCCDDR) DECOUPLING

5x 1uF 0402

NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines.

1x 1uF 0402

actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F

DDR Clock (CPU VDDQ_CK) DECOUPLING

1x 22uF 0805, 1x 4.7uF 0603

PLL (CPU VCCSFR) DECOUPLING

NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs. 2x330uF on CSA73. DG recommends 2x 22uF at SO_DIMM not provided. Decoupling caps at SO-DIMMs on CSA 29 and CSA 31.

PLACEMENT_NOTE (C1700-C1711):

12x 1uF 0402

VCAP0 (CPU BSC Package) DECOUPLING

10V 402

1UF

10% X5R

C1745

1

2

1UF

X5R

10%

402

10V

C1744

1

2

10V 402

1UF

10% X5R

C1743

1

2

1UF

X5R

10%

402

10V

C1742

1

2

10V 402

1UF

10% X5R

C1741

1

2

1UF

10% X5R

402

10V

C1740

1

2

X5R 402

1UF

10% 10V

C1739

1

2

1UF

X5R

10%

402

10V

C1738

1

2

10V 402

1UF

10% X5R

1

2

C1737

1UF

X5R

10%

402

10V

C1736

1

2

10V 402

1UF

10% X5R

C1735

1

2

1UF

X5R

10%

402

10V

C1753

1

2

10V 402

1UF

10% X5R

C1752

1

2

1UF

10% X5R

402

10V

C1751

1

2

X5R 402

1UF

10% 10V

C1750

1

2

1UF

X5R

10%

402

10V

C1749

1

2

402

X5R

10V

1UF

10%

C1748

1

2

1UF

X5R

10%

402

10V

C1747

1

2

402

10V

1UF

10% X5R

C1746

1

2

21

L1734

0603

30-OHM-5A

C1723

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1722

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1721

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1720

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1719

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1718

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1717

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1716

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1715

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1714

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1713

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1712

2

1

402

Place on bottom side of U1000.

16V X5R

1UF

10%

C1711

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1710

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1709

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1708

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1707

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1706

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1705

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1704

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1703

2

1

402

16V X5R

1UF

10%

Place on bottom side of U1000.

C1702

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1701

2

1

402

1UF

16V X5R

10%

Place on bottom side of U1000.

C1700

1UF

2

1

402

16V X5R

10%

Place on bottom side of U1000.

1UF

10V X5R 402

1

2

10%

C1728

X5R 402

10V

C1727

1

2

1UF

10%

10V 402

1UF

10% X5R

C1726

1

2

1UF

10% 10V

402

X5R

C1725

1

2

X5R

1UF

10%

402

10V

C1724

1

2

X5R-CERM 603

10%

6.3V

4.7UF

C1733

1

2

805

CERM-X5R

22uF

6.3V

20%

C1732

1

2

10V 402

10% X5R

1UF

C1734

1

2

POLY-TANT

2.0V

20%

D2T-SM2

330UF

C1729

1

23

SYNC_DATE=06/24/2009

CPU Non-GFX Decoupling (2 of 2)

SYNC_MASTER=K17_REF

PPCPUDDR_ISNS

PP1V8_S0

PP1V5_S3_CPU_VCCDDR_CLK

PPCPUDDR_ISNS

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU_VCAP0

17 OF 132 16 OF 103

7

13 16 31 57

6 7

12 72 73 88

101

12

7

13 16 31 57

7

12

7

12

www.vinafix.vn

IN

OUT

IN

BI BI BI BI

OUT

BI

IN

IN OUT OUT

IN

IN OUT OUT

IN IN

OUT

OUT OUT

OUT

IN

OUT

OUT OUT

IN

OUT OUT

IN

OUT OUT

OUT

IN

OUT

IN

IN IN

IN

OUT

BI

OUT

BI

IN IN OUT OUT

FWH4/LFRAME*

SATA1GP/GPIO19

INTVRMEN

SATAICOMPI

SATAICOMPO

SATA0TXN

SATA0RXN

SATA0TXP

SATA0RXP

SATA1TXP

SATA1RXP

SATA1RXN

SATA1TXN

SATA2TXN

SATA2RXN

SATA2TXP

SATA2RXP

SATA5TXN

SATA5RXN

SATA4TXN

SATA4RXN

SATA3TXN

SATA3RXN

SATA5TXP

SATA5RXP

SATA4TXP

SATA4RXP

SATA3TXP

SATA3RXP

FWH1/LAD1

LDRQ0*

LDRQ1*/GPIO23

SERIRQ

FWH3/LAD3

FWH2/LAD2

FWH0/LAD0

SATALED*

SATA0GP/GPIO21

HDA_SYNC

SPKR

SPI_MISO

SPI_MOSI

SPI_CS1*

SPI_CS0*

SPI_CLK

JTAG_TDO

JTAG_RST*

JTAG_TDI

JTAG_TMS

JTAG_TCK

HDA_DOCK_RST*/GPIO13

HDA_DOCK_EN*/GPIO33

HDA_SDO

HDA_SDIN2 HDA_SDIN3

HDA_SDIN1

HDA_SDIN0

HDA_RST*

HDA_BCLK

INTRUDER*

SRTCRST*

RTCRST*

RTCX2

RTCX1

(1 OF 10)

RTC

LPC

IHDAJTAG

SPI

SATA

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

PEG_A_CLKRQ*/GPIO47

CL_RST1*

CL_DATA1

CL_CLK1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_PCIE0N CLKOUT_PCIE0P

CLKOUT_PCIE1N

CLKOUT_PCIE2N

PCIECLKRQ1*/GPIO18

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE4P

CLKOUT_PCIE5P

CLKOUT_PCIE5N

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

PEG_B_CLKRQ*/GPIO56

PETP8

PETN8

PERP8

PERN8

PETP7

PETN7

PERP7

PERN7

PETP6

PERP6 PETN6

PETP5

PERN6

PERP5

PERN5

PETN5

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP2

PERP2 PETN2

PETP1

PERN2

PERP1

PERN1

PETN1

SMBCLK

SMBALERT*/GPIO11

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

REFCLK14IN

CLKOUT_PCIE1P

PCIECLKRQ0*/GPIO73

FROM CLK BUFFER

(2 OF 10)

SMBUS

C-LINKPEG

CLOCK

FLEX

PCI-E*

OUT OUT

IN

OUT

BI

OUT

IN

IN IN

OUT OUT

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CLKOUTFLEX3 also supports 48 MHz.

Default: 24.576 MHz (unsupported)

Default: 48 MHz

Default: 0V

All 4 CLKOUTFLEX outputs support

(IPD)

port multipliers

support FIS-based

(IPU)

Unused

(IPD)

Not available on

eSATA

SSD

ODD

HDD

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

Default: 14.31818 MHz

33.333 MHz and 14.31818 MHz,

Unused

(IPU/NO)

Only ports 4 & 5

(IPD)

(IPU)

some IbexPeak SKUs

(IPU)

27

59 94

17 25

48 94

17 25

48 94

6

46 48 88 94

6

46 48 88 94

6

46 48 88 94

6

46 48 88 94

6

46 48 88 94

6

46 48

42 93

37 94

6

33 94

6

33 94

39 94

37 94

33 94

39 94

37 94

17 37

37 94

33 94

17 25 33

39 94

17 25 40

10 91

75 94

8

17 88

10 93

26 93

27 93

27

49 94

6

25 26 28 30

32 34 42 48 49

64 94

6

25 26 28 30

32 34 42 48 49 64

94

6

34 94

6

34 94

R1800

330K

402

MF-LF

1/16W

5%

1

2

R1801

1/16W MF-LF

1M

402

5%

1

2

R1802

5%

20K

402

1/16W MF-LF

1

2

R1803

2

20K

402

5% 1/16W MF-LF

1

X5R

10V

2

10%

1UF

402

C1803

1

2

10V X5R 402

1UF

10%

C1802

1

R1830

1%

402

MF-LF

37.4

1/16W

1

2

R1820

10K

1/16W

5% MF-LF

402

1

2

J4

BA2

AY1

AV1

AK11

P1

A16

IBEX_PEAK_M

FCBGA

OMIT

U1800

D33 B33 C32 A32

C34

A30

H32 J30

C30

G30 F30 E32 F32

B29

D29

A14

M3

K1

J2

K3

A34 F34

C14

B13 D13

Y9

AK7 AK6

AK9

V1

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF15

AF16

T3

AB9

AV3

AY3

D17

AU30

FCBGA

OMIT

IBEX_PEAK_M

U1800

T13

T11

T9

AP3 AP1

AW24 BA24

F18 E18

J42

AH13 AH12

AN4 AN2

AT1 AT3

AK48 AK47

AM43 AM45

AM47 AM48

AH42 AH41

AM51 AM53

AJ50 AJ52

AD43 AD45

AK53 AK51

T45

P43

T42

N50

P9

U4

N4

A8

M9

H6

H1

P13

BG30

AW30

BA32

BF33

BA34

AT34

BG34

BJ30

BA30

AT30

BB32

BH33

AW34

AU34

BJ34

BF29

BC30

AU32

BD32

BG32

BC34

AU36

BG36

BH29

BD30

AV32

BE32

BJ32

BD34

AV36

BJ36

P41

B9

H14 C8

J14

C6 G8

M14

E10 G12

AF38

AH51 AH53

34 94

17 34

R1890

MF-LF

1/16W

402

1%

90.9

1

2

R1810

MF-LF

1/16W

5%

402

33

1 2

R1811

33

402

5% 1/16W MF-LF

1 2

R1812

33

402

5% 1/16W MF-LF

1 2

R1813

402

MF-LF

1/16W

5%

33

1 2

59 94

49 94

8

93

8

93

8

93

8

93

17 46

17 37

17 25 42

17 25

17

103

6

17 46

R1853

10K

MF-LF

4025%

1/16W

1 2

R1854

10K

5%

1/16W

402

MF-LF

1 2

R1855

10K

MF-LF

402

1/16W

5%

1 2

R1852

402

10K

MF-LF1/16W

5%

1 2

R1851

1/16W

402

MF-LF

10K

5%

1 2

MF-LF

402

R1850

1/16W

10K

5%

1 2

R1880

10K

402

MF-LF1/16W

5%

1 2

R1860

100K

21

5%

1/16W

402

MF-LF

R1870

10K

MF-LF

402

1/16W

5%

1 2

R1871

10K

MF-LF

402

1/16W

5%

1 2

R1872

10K

402

MF-LF1/16W

5%

1 2

R1898

402

10K

5%

1/16W MF-LF

1 2

R1897

1/16W

5% 402

MF-LF

10K

1 2

R1896

MF-LF

5%

1/16W

402

10K

1 2

R1895

10K

MF-LF

402

1/16W

5%

1 2

MF-LF

R1840

1/16W

5% 402

10K

1 2

MF-LF

R1841

10K

402

1/16W

5%

1 2

1/16W

R1816

10K

5% 402

MF-LF

1 2

1/16W

R1815

5% 402

MF-LF

10K

21

R1828

1/16W

402

51

MF-LF

5%

1

2

R1826

XDP_PCH

402

1/16W MF-LF

5%

51

1

2

R1827

XDP_PCH

5% MF-LF

1/16W 402

51

1

2

R1825

XDP_PCH

51

MF-LF

402

1/16W

5%

1

2

1 2

402

2.2K

5%

1/16W MF-LF

R1899

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_DATE=08/24/2009

SYNC_MASTER=K17_REF

SPI_CS0_R_L

NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN

NC_PCIE_PE6_D2RN

PP1V05_S0_PCH

PCH_INTRUDER_L

SATA_ODD_D2R_N SATA_ODD_D2R_P

TP_SPI_CS1_L

SPI_MISO

HDA_SDOUT_R

HDA_RST_L

HDA_RST_R_L

HDA_SDOUT

HDA_SDOUT_R

HDA_SYNC

HDA_SYNC_R

HDA_BIT_CLK

HDA_BIT_CLK_R

TP_SATA_EXTA_R2D_C_N

NC_SATA_C_D2RN

TP_LPC_DREQ0_L

PCH_SML0ALERT_L SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_N

NC_PCIE_PE8_D2RP

NC_PCIE_PE7_R2D_CP

SMBUS_PCH_CLK SMBUS_PCH_DATA

PCH_CLK33M_PCIIN

PCH_CLK25M_XTALIN PCH_CLK25M_XTALOUT

HDA_BIT_CLK_R

NC_SATA_SSD2_D2RP

PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P

SMC_WAKE_SCI_L

NC_PCIE_PE6_R2D_CP

NC_PCIE_PE6_D2RP

FW_CLKREQ_L

NC_PCIE_CLK100M_PE4N

PCIE_EXCARD_D2R_P

NC_PCIE_CLK100M_PE5N

NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CP

NC_SATA_SSD2_D2RN

TP_PCIE_CLK100M_PEBP

PCH_INTVRMEN_L

PCIE_CLK100M_EXCARD_P

NC_PCIE_PE8_D2RN

BRCRYPT_RESET

MLB_RAM_VENDOR

PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

MLB_RAM_SIZE

PP1V05_S0_PCH

PCH_CLK96M_DOT_P

TP_CLINK_RESET_L

TP_CLINK_DATA

TP_CLINK_CLK

PCH_CLK100M_SATA_N

PCIE_EXCARD_R2D_C_P

NC_PCIE_PE6_R2D_CN

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN

NC_PCIE_PE8_R2D_CP

NC_PCIE_CLK100M_PE4P

PCIE_CLK100M_EXCARD_N

LPC_SERIRQ

SATA_HDD_R2D_C_P

SML_PCH_1_CLK SML_PCH_1_DATA

TP_SATA_EXTA_D2R_N

NC_SATA_D_R2D_CN

PCH_PEB_CLKREQ_L

ENET_CLKREQ_L

PCIE_CLK100M_AP_P

PCH_PE4_CLKREQ_L

TP_PCIE_CLK100M_PEBN

PCH_INTVRMEN_L

HDA_RST_R_L

NC_HDA_SDIN1 NC_HDA_SDIN2

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

SPI_DESCRIPTOR_OVERRIDE_L ENET_ENERGY_DET

JTAG_PCH_TCK JTAG_PCH_TMS

SATARDRVR_A_EN

PCH_SPKR

HDA_SYNC_R

SATA_ODD_R2D_C_N

NC_SATA_D_R2D_CP

TP_SATA_EXTA_D2R_P

TP_PCH_SATALED_L

PCH_INTRUDER_L

NC_HDA_SDIN3

LPC_AD<2> LPC_AD<3>

LPC_FRAME_L

SATA_HDD_R2D_C_N

SATA_ODD_R2D_C_P

NC_SATA_C_R2D_CN

NC_SATA_D_D2RN

TP_SATA_EXTA_R2D_C_P

GFX_CLK120M_DPLLSS_P

PCH_CLK96M_DOT_N

GFX_CLK120M_DPLLSS_N

PCIE_CLK100M_CPU_P

FSB_CLK133M_PCH_P

FSB_CLK133M_PCH_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

PCIE_CLK100M_CPU_N

PEG_CLK100M_P

PEG_CLK100M_N

PEG_CLKREQ_L

NC_SATA_C_D2RP

SATARDRVR_A_EN

AP_CLKREQ_L

PCH_SML1ALERT_L

ARB_DETECT

MLB_RAM_VENDOR

JTAG_PCH_TDO JTAG_PCH_TCK

JTAG_PCH_TMS

PCH_SRTCRST_L

SATARDRVR_B_EN

AP_CLKREQ_L

BRCRYPT_PWR_EN

NC_PCIE_CLK100M_PE5P

EXCARD_CLKREQ_L

BRCRYPT_RESET

PEG_CLKREQ_L

SMC_WAKE_SCI_L

EXCARD_CLKREQ_L

FW_CLKREQ_L

NC_PCIE_PE5_R2D_CP

PCH_SATAICOMP

NC_SATA_C_R2D_CP

NC_SATA_D_D2RP

TP_LPC_DREQ1_L

PP3V3_S0_PCH

LPC_AD<0> LPC_AD<1>

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_N

PCIE_FW_D2R_P

JTAG_PCH_TDI

NC_PCIE_PE8_R2D_CN

PCH_XCLK_RCOMP

ARB_DETECT

PCH_SML0ALERT_L

BRCRYPT_PWR_EN

PCH_PEB_CLKREQ_L

PCH_PE4_CLKREQ_L

RTC_RESET_L

SATA_HDD_D2R_P

SATA_HDD_D2R_N

PCIE_FW_D2R_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

RTC_RESET_L

HDA_SDIN0

PCH_SRTCRST_L

MLB_RAM_SIZE

PP3V42_G3H

PCH_SPKR

PP3V3_S5_PCH

JTAG_PCH_TDI JTAG_PCH_TDO TP_JTAG_PCH_TRST_L

PP3V3_S3 PP3V3_S0_PCH

SPI_MOSI_R

SPI_CLK_R

PP1V05_S5

ENET_CLKREQ_L

SATARDRVR_B_EN

ENET_ENERGY_DET

SPI_DESCRIPTOR_OVERRIDE_L

18 OF 132 17 OF 103

6

17 18 21 23 24

101

17

17 94

6

17

6

17 94

6

17

6

17

103

17

17 18 21 23 24

101

6

17

17 94

6

17

17 94

6

17

6 6

6

17 25 42

17 25 33

17

17 25

17

6

17

103

8

17 88

17 46

17 34

17 25 40

6

17 18 19 20 21 23 24

101

17 25

6

17

103

17

6 7

21 23 43 45

46 47 48 49 50 51

54 65 66 74

17

18 19 20 21 23

101

6 7

20 31 32 33 34 35 36 49 50 51 54 55

56 72 74 88

102 103

17 18 19 20 21 23 24

101

7

72

17 37

17 25

17 37

17 46

www.vinafix.vn

IN IN

IN

OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT OUT

OUT

OUT OUT

OUT

OUT BI

BI BI

IN

OUT OUT

OUT

BI

OUT OUT

OUT

IN

BI

OUT

BI

OUT

IN

FDI_RXN0

DMI3RXN

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUS_PWR_ACK/GPIO30

RSMRST*

LAN_RST*

DRAMPWROK

MEPWROK

PWROK

SYS_PWROK

SYS_RESET*

SLP_M*

SLP_S4*

SLP_S3*

SUSCLK/GPIO62

SLP_S5*/GPIO63

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

WAKE*

DMI_ZCOMP DMI_IRCOMP

FDI_FSYNC1

FDI_FSYNC0

FDI_LSYNC0 FDI_LSYNC1

DMI3TXP

DMI2TXP

DMI0TXP DMI1TXP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

DMI3RXP

DMI2RXP

DMI0RXP DMI1RXP

FDI_INT

FDI_RXP7

FDI_RXP6

FDI_RXP5

FDI_RXP4

FDI_RXP1 FDI_RXP2 FDI_RXP3

FDI_RXP0

FDI_RXN7

FDI_RXN6

FDI_RXN5

FDI_RXN4

FDI_RXN3

FDI_RXN2

FDI_RXN1

DMI2RXN

DMI1RXN

DMI0RXN

SLP_LAN*

PMSYNCH

TP23

(3 OF 10)

DMI

FDI

SYSTEM POWER

MANAGEMENT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

CRT_IRTN

DAC_IREF

CRT_VSYNC

CRT_HSYNC

CRT_DDC_CLK CRT_DDC_DATA

CRT_RED

CRT_GREEN

CRT_BLUE

DDPD_3N DDPD_3P

DDPD_2P

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0N DDPD_0P

DDPD_HPD

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3P

DDPC_2P DDPC_3N

DDPC_2N

DDPC_1P

DDPC_1N

DDPC_0N DDPC_0P

DDPC_HPD

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3N

DDPB_2P

DDPB_3P

DDPB_2N

DDPB_1P

DDPB_0P DDPB_1N

DDPB_0N

DDPB_HPD

SDVO_CTRLDATA

SDVO_CTRLCLK

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

LVDSB_DATA0

LVDSB_DATA3*

LVDSB_DATA2*

LVDSB_CLK

LVDSB_CLK*

LVDSA_DATA3

LVDSA_DATA1 LVDSA_DATA2

LVDSA_DATA3*

LVDSA_DATA1*

LVDSA_DATA0*

LVDSA_CLK

LVDSA_CLK*

LVD_VREFH

LVD_IBG LVD_VBG

L_CTRL_DATA

L_CTRL_CLK

L_DDC_DATA

L_DDC_CLK

L_BKLTCTL

L_BKLTEN L_VDD_EN

LVD_VREFL

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXP

DDPB_AUXN

DDPC_AUXN DDPC_AUXP

DDPD_AUXN DDPD_AUXP

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA0

LVDSA_DATA2*

DIGITAL DISPLAY INTERFACE

CRT

LVDS

(4 OF 10)

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

0.5% recommended, Intel okay with 5% when CRTDAC not used.

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

88 93

6 8

93

6 8

93

88 93

8

93

88 93

8

93

88 93

8

93

88 93

8

93

8

88

8

88

6 8

85

2

1

R1950

1/16W MF-LF 402

1%

2.37K

8

85 93

8

85 93

8

85

8

81 85

8

81 85

8

2

1

R1951

1K

402

MF-LF

1/16W

5%

2

1

R1900

402

1% 1/16W MF-LF

49.9

6

18 27 33 34

6

18 46 48

47 94

46 47

31 43 46 47 73 74

6

31 46 74 86

10 91

18

10 31 91

18 46

25 46

46 47 74

18 46

27

6

27 46

J12

N2

T6

M6

F3

P8

M1

E4

H7

P12

K8

F6

C16

F14

B17

P5

BJ10

K5

A10

BD12

BB14

BD14

AW16

BG16

BC16

BF17

BB18

BC12

BA14

BE14

BA16

BJ16

BD16

BH17

BA18

BG14

BJ12

BJ14

BH13

BF13

D9

BH25 BF25

BD18

BE18

BG20

BJ20

BC20

BD20

BA20

AW20

BH21

BF21

BG22

BJ22

BD22

BE22

BD24

BC24

Y1

A6

P7

U1800

IBEX_PEAK_M

FCBGA

OMIT

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

BG46

BJ46

BG48

BJ48

BH45

BF45

T53

T51

AT53

AT51

AU52

AU50

AT49

AT48

AY53

AY51

AP48 AP47

AV47

AV48

AY48

AY49

BA52

BA50

BB47

BB48

AV53 AV51

AT42

AT43

AP41

AP39

T47

Y45

AB48

V48

AB46

T48

Y48

AT38

U52

U50

BD46

BC46

BD36

BE36

BH37

BF37

BG38

BJ38

BG40

BJ40

AV40

AB49

Y49

BD44

BE44

BA36

BB36

BC38

BD38

BH41

BF41

BD40

BE40

AU38

BJ44

BG44

BA38

AW38

BA40

BB40

BG42

BJ42

BC42

BD42

AD48

Y51

AD53

AB51

Y53

AB53

V53

V51

AA52

U1800

FCBGA

IBEX_PEAK_M

OMIT

6

18 46 48

2

1

R1905

1/16W

1%

10K

402

MF-LF

2

1

R1920

10K

402

1/16W MF-LF

5%

2

1

R1921

5% MF-LF

1/16W 402

10K

2

1

R1930

10K

402

1/16W MF-LF

5%

2

1

R1931

5% MF-LF

1/16W 402

10K

2

1

R1925

10K

402

1/16W MF-LF

5%

2

1

R1906

10K

402

1/16W MF-LF

5%

PCH DMI/FDI/Graphics

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

PCH_DAC_IREF

NC_LVDS_IG_B_DATAP<3>

LVDS_IG_B_DATA_P<2>

FDI_DATA_P<3>

FDI_DATA_N<7>

FDI_FSYNC<0> FDI_FSYNC<1>

NC_SDVO_TVCLKINN

LVDS_IG_A_DATA_P<1>

FDI_LSYNC<1>

PM_SYNC

NC_DP_IG_C_AUXN

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_CTRL_CLK

DP_IG_B_ML_P<3>

DP_IG_B_ML_N<3>

NC_LVDS_IG_B_DATAN<3>

PM_SLP_S3_L

PP3V3_S5_PCH PP1V05_S0_PCH

DP_IG_B_ML_N<1>

NC_DP_IG_C_MLP<2>

NC_SDVO_STALLN NC_SDVO_STALLP

NC_CRT_IG_HSYNC

NC_CRT_IG_DDC_DATA

NC_CRT_IG_DDC_CLK

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<0>

NC_LVDS_IG_A_DATAP<3>

TP_LVDS_IG_B_CLKN

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

NC_DP_IG_D_AUXP

NC_DP_IG_D_AUXN

NC_DP_IG_C_AUXP

DP_IG_AUX_CH_N DP_IG_AUX_CH_P

NC_SDVO_INTP

NC_SDVO_INTN

LVDS_IG_PANEL_PWR

LVDS_IG_DDC_DATA NC_LVDS_IG_CTRL_CLK

NC_LVDS_IG_CTRL_DATA

NC_PCH_LVDS_VBG

DP_IG_DDC_CLK DP_IG_DDC_DATA

DP_IG_HPD DP_IG_B_ML_N<0>

DP_IG_B_ML_P<0>

DP_IG_B_ML_P<2>

NC_DP_IG_C_MLP<0>

NC_DP_IG_C_MLN<0>

NC_DP_IG_C_MLN<1> NC_DP_IG_C_MLP<1> NC_DP_IG_C_MLN<2>

NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_HPD

NC_DP_IG_D_MLN<1>

NC_DP_IG_D_MLN<2> NC_DP_IG_D_MLP<2>

NC_DP_IG_D_MLP<3>

NC_DP_IG_D_MLN<3>

TP_PM_SLP_DSW_L

FDI_DATA_N<1>

FDI_DATA_N<4>

FDI_DATA_N<6>

FDI_DATA_P<5>

FDI_DATA_P<7>

FDI_INT

TP_PM_SLP_M_L

FDI_DATA_N<0>

NC_CRT_IG_VSYNC

LPC_PWRDWN_L

MAKE_BASE=TRUE

PCH_LVDS_IBG

PM_BATLOW_L

SMC_ADAPTER_EN

PM_SUS_PWR_ACK PM_PWRBTN_L

PM_RSMRST_L

PM_MEM_PWRGD

PM_SYSRST_L

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<0> DMI_N2S_N<1>

TP_SLP_LAN_L

FDI_LSYNC<0>

PM_CLKRUN_L

PCIE_WAKE_L

FDI_DATA_P<2>

FDI_DATA_P<0>

DMI_N2S_P<0>

DMI_N2S_P<3>

FDI_DATA_N<5>

FDI_DATA_P<4>

FDI_DATA_P<6>

PM_CLK32K_SUSCLK

PM_SLP_S4_L

PM_SLP_S5_L

NC_CRT_IG_RED

PM_CLKRUN_L

PM_SUS_PWR_ACK

PP3V3_S0_PCH

PM_BATLOW_L PCIE_WAKE_L

PP3V3_S5_PCH

PM_RSMRST_L

PM_PCH_PWRGD

PCH_LAN_RST_L

NC_DP_IG_D_MLP<1>

DMI_S2N_P<1>

DMI_S2N_N<1>

LVDS_IG_DDC_CLK

PCH_RI_L

TP_LVDS_IG_BKL_PWM

NC_SDVO_TVCLKINP

NC_DP_IG_D_MLN<0> NC_DP_IG_D_MLP<0>

DP_IG_B_ML_P<1>

LVDS_IG_A_DATA_P<0>

NC_LVDS_IG_A_DATAN<3>

FDI_DATA_P<1>

FDI_DATA_N<3>

FDI_DATA_N<2>

NC_DP_IG_C_MLP<3>

NC_DP_IG_C_MLN<3>

TP_LVDS_IG_B_CLKP

NC_DP_IG_C_HPD

LVDS_IG_A_DATA_N<1>

LVDS_IG_BKL_ON

DP_IG_B_ML_N<2>

LVDS_IG_A_DATA_P<2>

DMI_S2N_P<0>

PCH_DMI_COMP

19 OF 132 18 OF 103

6

17 18 19 20 21 23

101

17 21 23 24

101

6

18 46 48

6

18 46 48

18

17 19 20 21 23 24

101

18 46

6

18 27 33 34

17 18 19 20 21 23

101

18 46

6

www.vinafix.vn

BI

OUT OUT

OUT

IN

OC7*/GPIO14

OC6*/GPIO10

OC5*/GPIO9

OC4*/GPIO43

OC3*/GPIO42

OC1*/GPIO40

OC0*/GPIO59

USBRBIAS

USBRBIAS*

USBP13N

USBP12N

USBP11N

USBP10N

USBP9N

USBP8N

USBP7N

USBP6N

USBP5N

USBP4N

USBP3N

USBP2N

USBP1N

USBP0N

USBP13P

USBP12P

USBP11P

USBP10P

USBP8P

USBP9P

USBP7P

USBP6P

USBP5P

USBP4P

USBP3P

USBP2P

USBP1P

USBP0P

AD2

NV_WE_CK1*

NV_WE_CK0*

NV_WR1_RE*

NV_RB*

NV_WR0_RE*

NV_RCOMP

NV_CLE

NV_ALE

NV_DQ15/NV_IO15

NV_DQ13/NV_IO13 NV_DQ14/NV_IO14

NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12

NV_DQ8/NV_IO8 NV_DQ9/NV_IO9

NV_DQ7/NV_IO7

NV_DQ6/NV_IO6

NV_DQ5/NV_IO5

NV_DQ3/NV_IO3 NV_DQ4/NV_IO4

NV_DQ1/NV_IO1 NV_DQ2/NV_IO2

NV_DQ0/NV_IO0

NV_DQS0 NV_DQS1

NV_CE2* NV_CE3*

NV_CE1*

NV_CE0*

AD9

AD3

AD20

AD28 AD29

SERR* PERR*

GNT1*/GPIO51

REQ1*/GPIO50

PIRQC* PIRQD*

REQ0*

AD30

AD21 AD22

PIRQG*/GPIO4 PIRQH*/GPIO5

PCIRST*

AD0 AD1

AD4 AD5 AD6 AD7 AD8

AD10 AD11 AD12 AD13 AD14

AD24 AD25 AD26

CLKOUT_PCI2

C/BE0*

C/BE2* C/BE3*

DEVSEL* FRAME*

GNT0*

GNT2*/GPIO53 GNT3*/GPIO55

IRDY* PAR

PIRQA* PIRQB*

PIRQE*/GPIO2 PIRQF*/GPIO3

PLOCK*

PME*

REQ2*/GPIO52 REQ3*/GPIO54

STOP* TRDY*

AD15 AD16 AD17 AD18 AD19

AD27

AD31

C/BE1*

AD23

OC2*/GPIO41

PLTRST*

CLKOUT_PCI1

CLKOUT_PCI3

CLKOUT_PCI0

CLKOUT_PCI4

(5 OF 10)

USB

PCI

NVRAM

OUT

OUT OUT

IN IN IN

IN

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPD) (IPD)

EHCI2

(DPD)

(IPU)

(DPD)

EHCI1

NOTE: Internal pull-downs on all USB pins

(IPU)

T57

External Hub 1

External Hub 2

36 93

35 93

402

1/16W MF-LF

5%

10K

R2060

1

2

402

1/16W MF-LF

5%

10K

R2062

1

2

MF-LF

10K

402

1/16W

5%

R2061

1

2

5% MF-LF

1/16W 402

10K

R2064

1

2

MF-LF

1/16W

402

22.6

1%

R2070

1

2

27 94

27

27 31 40

19 25

10K

MF-LF1/16W

5% 402

R2024

1 2

10K

5%

1/16W MF-LF

402

R2023

1 2

10K

MF-LF1/16W

4025%

R2022

1 2

10K

5%

MF-LF

402

1/16W

R2020

1 2

10K

5%

MF-LF

402

1/16W

R2021

1 2

10K

4025%

1/16W MF-LF

R2027

1 2

402

1/16W MF-LF

10K

5%

R2026

1 2

10K

402

MF-LF1/16W

5%

R2010

1 2

10K

402

MF-LF1/16W

5%

R2011

1 2

402

10K

1/16W MF-LF

5%

R2012

1 2

10K

MF-LF

5%

1/16W

402

R2013

1 2

10K

402

MF-LF1/16W

5%

R2014

1 2

H18

IBEX_PEAK_M

OMIT

FCBGA

U1800

H40 N34

E40 C40 M48 M45 F53 M40 M43 J36 K48 F40

C44

C42 K46 M51 J52 K51 L34 F42 J40 G46 F44

A38

M47 H36

C36 J34 A40 D45 E36 H48

J50 G42 H47 G34

N52 P53 P46 P51 P48

F46 C46

F48 K45 F36 H53

A42

BD3

AY9 BD1 AP15 BD8

AY6

AP7

BD6 BB7 BC8 BJ8 BJ6 BG6

AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6

AV9 BG8

AV7

AU2

AV11 BF5

AY8 AY5

N16 J16 F16 L16 E14 G16 F12 T15

H44

K6

E50

G38 H51 B37 A44

B41 K53 A36 A48

D49

D5

M7

F51 A46 B45 M53

E44

D41 C48

J18

A22 C22 G24 H24 L24 M24 A24 C24

A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22

D25

B25

27

5% MF-LF

1/16W 402

10K

R2066

1

2

402

1/16W MF-LF

5%

10K

R2065

1

2

5%

10K

MF-LF1/16W

402

R2025

1 2

19 88

10K

MF-LF

402

1/16W

5%

R2030

1 2

10K

MF-LF

402

1/16W

5%

R2031

1 2

10K

MF-LF

402

1/16W

5%

R2032

1 2

402

10K

MF-LF1/16W

5%

R2036

1 2

10K

MF-LF

402

1/16W

5%

R2035

1 2

5%

1/16W

402

MF-LF

10K

R2037

1 2

19 64

19

19 64

10K

MF-LF

402

1/16W

5%

R2038

1 2

5%

1/16W

402

MF-LF

10K

R2081

1 2

10K

MF-LF

402

1/16W

5%

R2080

1 2

19 25

93

103

93

103

SYNC_DATE=10/07/2009

PCH PCI/FlashCache/USB

SYNC_MASTER=K18_MLB

NC_NV_WR_RE_L<0> NC_NV_WR_RE_L<1>

USB_HUB1_UP_N USB_HUB1_UP_P NC_USB_1N

NC_NV_RB_L

NC_NV_WE_CK_L<1>

PCI_INTC_L

PP3V3_S0_PCH

NC_USB_11P

NC_USB_9P

NC_PCI_AD<27>

NC_USB_11N

NC_USB_13P

NC_USB_1P

NC_USB_3P

NC_USB_4P NC_USB_5N NC_USB_5P

NC_USB_13N

PCH_USB_RBIAS

NC_USB_7N

NC_USB_3N

NC_USB_4N

NC_USB_6N

NC_USB_10N

NC_USB_12P

NC_USB_10P

NC_USB_6P

USB_BRCRYPT_P

USB_BRCRYPT_N

PP3V3_S5_PCH

NC_PCI_AD<17>

NC_PCI_AD<20>

NC_PCI_AD<30>

NC_PCI_AD<29>

NC_PCI_C_BE_L<0>

NC_PCI_GNT1_L

AUD_IP_PERIPHERAL_DET

PCI_REQ3_L PCH_GPIO2

JTAG_GMUX_TMS

AUD_I2C_INT_L

NC_PCI_AD<12>

PP3V3_S5_PCH

PCH_GPIO59 PM_LATRIGGER_L

PCI_PLOCK_L

PCH_CLK33M_PCIOUT

LPC_CLK33M_SMC_R

PLT_RESET_L

PCI_IRDY_L

PCI_SERR_L

PCI_INTD_L PCI_REQ0_L

PCI_INTA_L PCI_INTB_L

MIKEY_MIC_LOAD_DET

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

JTAG_GMUX_TMS

PM_LATRIGGER_L

NC_PCI_CLK33M_OUT3

NC_PCI_AD<23>

NC_PCI_C_BE_L<1>

NC_PCI_AD<31>

NC_PCI_AD<19>

NC_PCI_AD<18>

NC_PCI_AD<16>

NC_PCI_AD<15>

PCH_GPIO2

NC_PCI_PAR

NC_PCI_GNT2_L

NC_PCI_GNT0_L

NC_PCI_C_BE_L<3>

NC_PCI_C_BE_L<2>

LPC_CLK33M_GMUX_R

NC_PCI_AD<26>

NC_PCI_AD<25>

NC_PCI_AD<24>

NC_PCI_AD<14>

NC_PCI_AD<13>

NC_PCI_AD<11>

NC_PCI_AD<10>

NC_PCI_AD<8>

NC_PCI_AD<7>

NC_PCI_AD<6>

NC_PCI_AD<5>

NC_PCI_AD<4>

NC_PCI_AD<1>

NC_PCI_AD<0>

NC_PCI_RESET_L

NC_PCI_AD<22>

NC_PCI_AD<21>

NC_PCI_AD<28>

NC_PCI_AD<9>

NC_NV_CE_L<0> NC_NV_CE_L<1>

NC_NV_CE_L<3>

NC_NV_CE_L<2>

NC_NV_DQS<1>

NC_NV_DQS<0>

NC_NV_DQ<0>

NC_NV_DQ<2>

NC_NV_DQ<1>

NC_NV_DQ<4>

NC_NV_DQ<3>

NC_NV_DQ<6>

NC_NV_ALE NC_NV_CLE

NC_NV_WE_CK_L<0>

NC_PCI_AD<2>

PCI_TRDY_L

LPC_CLK33M_LPCPLUS_R

PCI_STOP_L

PCI_PERR_L

MIKEY_MIC_LOAD_DET

PCI_FRAME_L

PCI_DEVSEL_L

NC_PCI_GNT3_L

JTAG_GMUX_TDI PCI_REQ3_L

NC_PCI_PME_L

USB_HUB2_UP_N USB_HUB2_UP_P

NC_NV_DQ<9>

NC_NV_DQ<5>

NC_USB_7P

NC_NV_DQ<15>

NC_NV_DQ<8>

NC_NV_DQ<7>

NC_NV_DQ<14>

NC_NV_DQ<13>

NC_NV_DQ<12>

NC_NV_DQ<11>

NC_NV_DQ<10>

NC_USB_9N

NC_USB_12N

PCH_GPIO59

PCH_GPIO41

USB_HUB_SOFT_RESET_L

PCH_GPIO42 PCH_GPIO43 PCH_GPIO9 PCH_GPIO10

TP_PCH_NV_RCOMP

NC_PCI_AD<3>

JTAG_GMUX_TDI

20 OF 132 19 OF 103

6

17 18 20 21 23 24

101

6

93

6

17 18 19 20 21 23

101

6

19 64

19

19 88

19 64

6

17 18 19 20 21 23

101

19 25

6

19

6

27

6

19

6

19

6

25

25 35

25

6

19 88

www.vinafix.vn

IN

OUT OUT

BI

OUT

IN

OUT

NC_5

NC_3 NC_4

NC_1 NC_2

TP8

TP19

TP18

TP17

TP15

TP16

TP14

TP13

TP12

TP11

TP9

TP10

TP6

TP7

TP4

TP5

TP2

TP1

INIT3_3V*

TP24

VSS_NCTF31

VSS_NCTF30

VSS_NCTF28 VSS_NCTF29

VSS_NCTF25 VSS_NCTF26 VSS_NCTF27

VSS_NCTF24

VSS_NCTF23

VSS_NCTF22

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF13

VSS_NCTF12

VSS_NCTF10 VSS_NCTF11

VSS_NCTF8 VSS_NCTF9

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF2 VSS_NCTF3 VSS_NCTF4

VSS_NCTF1

GPIO57

SATA5GP/GPIO49

SDATAOUT1/GPIO48

PCIECLKRQ7*/GPIO46

SDATAOUT0/GPIO39

PCIECLKRQ6*/GPIO45

SLOAD/GPIO38

SATA3GP/GPIO37

SATA2GP/GPIO36

SATACLKREQ*/GPIO35

STP_PCI*/GPIO34

GPIO27

GPIO28

MEM_LED/GPIO24

TACH0/GPIO17

SCLOCK/GPIO22

SATA4GP/GPIO16

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

TACH3/GPIO7

TACH1/GPIO1

TACH2/GPIO6

BMBUSY*/GPIO0

THRMTRIP*

PROCPWRGD

RCIN*

PECI

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

A20GATE

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

TP3

CLKOUT_PCIE7P

(6 OF 10)

CPU

NCTF

RSVD

GPIO

MISC

IN

BI

OUT

BI

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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Apple Inc.

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A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPU*)

(IPD)

(IPU*)

(DPL_B_MON2_P)

(SATA_OB_ANA)

(DPL_B_MON2_N)

(DPL_B_MON1_P)

(DPL_B_MON1_N)

(XCKPLL_MON1_P)

(XCKPLL_MON1_N)

(IPU)

IPU* = Only on TACH function.

(IPU*)

(IPD)

20 46

10 91

10 25 91

56

5%

MF-LF

1/16W

402

R2161

1 2

10 47 91

56

5%

402

1/16W MF-LF

R2160

1

2

10K

402

5% 1/16W MF-LF

R2155

1

2

20

OMIT

FCBGA

IBEX_PEAK_M

U1800

U2

Y3

AM3 AM1

AH45 AH46

AF48 AF47

T7

AB12

V13

F8

F10

P6

K9

H10

AB45 AB38 AB42 AB41 T39

H3

F1

BG10

BE10

T1

AB7

AB13

AA2

AA4

V6

Y7

P3

AB6

V3

M11

F38

C38

D37

J32

BD10

BA22

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AW22

C10

BB22

AY45

AY46

AV43

AV45

AF13

M18

A4

A49

BE1

BE53

BF1

BF53

BH1

BH2 BH52 BH53

BJ1

BJ2

A5

BJ4 BJ49

BJ5 BJ50 BJ52 BJ53

D1 D2

D53

E1

A50

E53

A52

A53

B2

B4 B52 B53

10K

MF-LF

1/16W

5%

402

R2150

1

2

5%

1/16W

402

MF-LF

10K

R2116

1 2

2.2K

5%

1/16W MF-LF

R2115

402

21

5%

1/16W

402

MF-LF

10K

R2113

1 2

1/16W

402

MF-LF

20K

R2112

1 2

5%

1/16W

5% 402

MF-LF

10K

R2114

1 2

10K

402

1/16W

5%

R2110

1 2

MF-LF

10K

402

R2111

1

1/16W

2

5%

MF-LF

20 25 46 47

8

20 40

20 88

6

20 48

20 25 64

20 42

6

20 48 58

20 25

20 40

20 33 74

20 74

20 25 88

20 88

25 31

5%

1/16W

402

MF-LF

10K

R2121

1 2

5%

1/16W

402

MF-LF

10K

R2120

1 2

10K

MF-LF1/16W

5% 402

R2122

1 2

10K

MF-LF

5%

1/16W

402

R2123

1 2

10K

402

1/16W5%MF-LF

R2124

1 2

20 25

10K

5%

1/16W

402

MF-LF

R2130

1 2

5%

1/16W

402

MF-LF

10K

R2131

1 2

5%

1/16W

402

MF-LF

10K

R2133

1 2

5%

1/16W

402

10K

MF-LF

R2132

1 2

5%

1/16W

402

MF-LF

10K

R2134

1 2

5% 402

MF-LF

10K

1/16W

R2135

1 2

10K

MF-LF

402

1/16W

5%

R2136

1 2

5% 402

MF-LF1/16W

R2137

1 2

10K

5% 402

MF-LF1/16W

1 2

10K

R2138

5% 402

MF-LF

100K

1/16W

R2139

1 2

20 37

PCH MISC

SYNC_MASTER=K18_MLB

SYNC_DATE=11/13/2009

FW_PLUG_DET_L GMUX_INT

SMC_IG_THROTTLE_L

PP3V3_S0_PCH

ENET_LOW_PWR

PP3V3_S3

PP3V3_S5_PCH

AUD_IPHS_SWITCH_EN LPCPLUS_GPIO

PCH_VSS_NCTF<27>

PCH_VSS_NCTF<15>

GMUX_INT SMC_RUNTIME_SCI_L

CPU_PWRGD

PCH_GPIO15

NC_PCH_TP19

NC_PCH_NC1 NC_PCH_NC2

PCH_THRMTRIP_L

NC_PCH_TP2

NC_PCH_TP3

NC_PCH_TP4

NC_PCH_TP1

NC_PCH_TP5

NC_PCH_TP6

NC_PCH_TP7

NC_PCH_TP10

NC_PCH_TP16

NC_PCH_TP15

NC_PCH_TP13

NC_PCH_TP12

NC_PCH_TP17

NC_PCH_NC3

NC_PCH_NC5

NC_PCH_TP18

NC_PCH_NC4

NC_PCH_SST

PCH_VSS_NCTF<1> PCH_VSS_NCTF<2>

PCH_VSS_NCTF<5>

TP_PCH_VSS_NCTF<7>

PCH_VSS_NCTF<9>

PCH_VSS_NCTF<11> PCH_VSS_NCTF<12>

PCH_VSS_NCTF<17>

PCH_VSS_NCTF<29>

PCH_VSS_NCTF<25>

PCH_VSS_NCTF<21>

SPIROM_USE_MLB

PCH_VSS_NCTF<19>

PCH_VSS_NCTF<22>

PCH_VRM_EN

PCH_GPIO24

SPIROM_USE_MLB

PCH_GPIO39

JTAG_GMUX_TDO

SDCARD_RESET

PCH_RCIN_L

PPVTT_S0_PCH

PP3V3_S0_PCH

PCH_A20GATE

NC_PCH_TP8

NC_PCH_TP14

NC_PCH_TP11

NC_PCH_TP9

TP_PCH_INIT3V3_L

PCH_GPIO39

TP_PCH_STP_PCI_L

PCH_VRM_EN

PCH_GPIO15

CPU_PECI

FSB_CLK133M_CPU_P

FSB_CLK133M_CPU_N

NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE7P

PCH_FCIM_EN_L

AUD_IPHS_SWITCH_EN

ODD_PWR_EN_L PCH_GPIO24

ME_TEMP_ALERT_L

AP_PWR_EN

WOL_EN

JTAG_GMUX_TCK JTAG_GMUX_TDO

ISOLATE_CPU_MEM_L

LPCPLUS_GPIO

SDCARD_RESET

FW_PWR_EN

PCH_FCIM_EN_L

SMC_RUNTIME_SCI_L

ODD_PWR_EN_L

JTAG_GMUX_TCK

ME_TEMP_ALERT_L

FW_PWR_EN

AP_PWR_EN

WOL_EN

MXM_GOOD

FW_PLUG_DET_L

SMC_IG_THROTTLE_L

ENET_LOW_PWR

PM_THRMTRIP_L

21 OF 132 20 OF 103

8

20 40

20 88

20 25 46 47

17 18 19 20 21 23 24

101

20 37

6 7

17 31 32 33 34 35 36 49 50 51 54 55

56 72 74 88

102 103

17 18 19 21 23

101

20 25 64

6

20 48

6

94

6

94

20

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

20

6

20 48 58

20

20 88

20 25

21 23

101

17 18 19 20 21 23 24

101

6

20

6

20

20 46

20 42

20 25 88

20 25

20 40

20 33 74

20 74

20

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VCCIO24

VCCIO55

VCCIO54

VCCIO53

VCCIO52

VCCIO51

VCCIO50

VCCIO49

VCCIO48

VCCIO47

VCCIO46

VCCIO45

VCCIO44

VCCIO43

VCCIO42

VCCIO41

VCCIO40

VCCIO39

VCCIO38

VCCIO37

VCCIO36

VCCIO35

VCCIO34

VCCIO33

VCCIO32

VCCIO31

VCCIO29

VCCIO28

VCCIO27

VCCIO26

VCCIO25

VCCVRM2

VCCFDIPLL

VCCAPLLEXP

VCCALVDS

VCCADAC1 VCCADAC2

VSSA_DAC1 VSSA_DAC2

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_2

VCC3_3_4

VCC3_3_3

VCCPNAND1 VCCPNAND2 VCCPNAND3 VCCPNAND4 VCCPNAND5 VCCPNAND6 VCCPNAND7 VCCPNAND8 VCCPNAND9

VCCME3_3_1 VCCME3_3_2 VCCME3_3_3 VCCME3_3_4

VCC3_3_1

VCCVRM1

VSSA_LVDS

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15

VCCDMI1 VCCDMI2

VCCIO30

VCCIO1

CRT

PCI-E*

NAND / SPI

HVCMOS

(7 OF 10)

VCC CORE

LVDS

FDI

DMI

VCCSUS3_3_23

VCCSUS3_3_28

VCCSUS3_3_27

VCCSUS3_3_26

VCCSUS3_3_25

VCCSUS3_3_24

VCCSUS3_3_22

VCCSUS3_3_21

VCCSUS3_3_20

VCCSUS3_3_19

VCCSUS3_3_18

VCCSUS3_3_17

VCCSUS3_3_16

VCCSUS3_3_15

VCCSUS3_3_14

VCCSUS3_3_13

VCCSUS3_3_12

VCCSUS3_3_11

VCCSUS3_3_10

VCCSUS3_3_9

VCCSUS3_3_8

VCCSUS3_3_7

VCCSUS3_3_6

VCCSUS3_3_5

VCCSUS3_3_4

VCCSUS3_3_3

VCCSUS3_3_2

VCCSUS3_3_1

VCCSUS3_3_29

VCCME3

V5REF

V5REF_SUS

VCC3_3_8 VCC3_3_9

VCC3_3_11

VCC3_3_10

VCC3_3_12 VCC3_3_13

VCC3_3_14

VCCSATAPLL1 VCCSATAPLL2

VCCVRM4

VCCME13 VCCME14 VCCME15 VCCME16

VCCSUSHDA

VCCRTC

V_CPU_IO1 V_CPU_IO2

DCPSST

DCPSUS

VCCSUS3_3_30

VCCSUS3_3_32

VCC3_3_6 VCC3_3_7

VCCACLK1 VCCACLK2

VCCLAN1 VCCLAN2

VCCME1

DCPSUSBYP

VCCME2

VCCME6

VCCME5

VCCME4

VCCME7 VCCME8 VCCME9

VCCME11

VCCME10

DCPRTC

VCCME12

VCCVRM3

VCCADPLLA1 VCCADPLLA2

VCCADPLLB2

VCCADPLLB1

VCC3_3_5

VCCSUS3_3_31

VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20

VCCIO9

VCCIO56VCCIO21 VCCIO22 VCCIO23

VCCIO2 VCCIO3 VCCIO4

VCCIO5 VCCIO6 VCCIO7 VCCIO8

PCI/GPIO/LPC

USB

CPU

RTC

HDA

(10 OF 10)

CLOCK AND MISCELLANEOUS

PCI/GPIO/LPC

SATA

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

(VCCIO[1-56] total)

3062 mA

115 mA

GPIO27 HDA_SYNC VccVRM PLLs

31 mA (if GPIO27 is low)

< 1 mA

PCH output, for decoupling only

(VCCSUS3_3[1-32] total)

164 mA (VCCVRM[1-4] total)

68 mA

3062 mA (VCCIO[1-56] total)

164 mA (VCCVRM[1-4] total)

357 mA (VCC3_3[1-14] total)

PCH output, for decoupling only

69 mA

PCH output, for decoupling only

3062 mA (VCCIO[1-56] total)

59 mA

52 mA

Verify S0 okay

(VCCME[1-16] total)

< 1 mA

< 1 mA S0-S5

357 mA

(VCCSUS3_3[1-32] total)

61 mA (1.1V) 58 mA (1.05V)

320 mA S0, 67 mA M-on

1849 mA S0, 700 mA M-on

163 mA S0, 65 mA S3-S5

357 mA

2 mA S0-S5, ~6 uA G3

6 mA S0, < 1 mA S3-S5

1849 mA S0, 700 mA M-on

3062 mA (VCCIO[1-56] total)

40 mA (if GPIO27 is low)

5 mA (if GPIO27 is low)

3062 mA (VCCIO[1-56] total)

69 mA

85 mA S0, 22 mA M-on

< 1 mA

156 mA (1.8V) NOTE: Connect to 3.3V if NAND not used.

357 mA (VCC3_3[1-14] total)

3062 mA (VCCIO[1-56] total)

(VCC3_3[1-14] total)

Note: 1.5V option consumes more current than 1.8V

1 (IPU) 1 1.5V Float

(VCC3_3[1-14] total)

357 mA

1432 mA

3062 mA (VCCIO[1-56] total)

(VCC3_3[1-14] total)

(VCCME[1-16] total)

PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL

0 X 1.05V 1.05V

1 (IPU) 0 (IPD) 1.8V Float

163 mA S0, 65 mA S3-S5

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

IBEX_PEAK_M

FCBGA

OMIT

U1800

AN35

AB34 AB35 AD35

AE50 AE52

AH38

BJ24

AB24

AH26 AH28 AH30 AH31 AJ30 AJ31

AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31

AT16 AU16

BJ18

AM23

AK24

AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27

AN30 AN31

AM8 AM9 AP11 AP9

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AP43 AP45 AT46 AT45

AT22

AT24

AF53 AF51

AH39

IBEX_PEAK_M

FCBGA

OMIT

U1800

V9

V12

Y22

Y20

K49

F24

AT18 AU18

M36 N36 P36 U35

AD13

V15 V16 Y16

J38 L38

AP51 AP53

BB51 BB53

BD51 BD53

AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22

AF34

AD22

AH23 AJ35 AH35

AH34 AF32

V24

V23

V26 Y24 Y26

AH22

AF23 AF24

AD38

Y39 Y41 Y42

AA34 Y34 Y35 AA35

AD39 AD41 AF43 AF41 AF42

V39 V41 V42

A12

AK3 AK1

V28

M26 L28 L26 J28 J26 H28 H26 G28 G26 F28

U28

F26 E28 E26 C28 C26 B27 A28 A26 U23

P18

U26

U19 U20 U22

U24 P28 P26 N28 N26 M28

L30

AU24

AT20

20% CERM

10V

0.1UF

402

PLACE_NEAR=U1800.Y20:2.54MM

C2200

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.V9:2.54MM

C2210

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.V12:2.54MM

C2220

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.Y22:2.54MM

C2230

1

2

20%

4.7UF

X5R

4V

402

C2225

1

2

402-HF

1%

0.2

1/6W

MF

R2225

1 2

SYNC_MASTER=K18_MLB

PCH Power

SYNC_DATE=10/02/2009

PP1V05_S0_PCH

PPVTT_S0_PCH

PP3V3_S0_PCH

PP5V_S5_PCH_V5REFSUS

GND

PP5V_S0_PCH_V5REF

PP1V05_S0_PCH_VCCA_CLK

PP1V8_S0_PCH

PP1V05_S0_PCH

PP3V42_G3H

PP3V3R1V5_S0_PCH

PP1V05_S0_PCH

PP1V8_S0_PCH

PP1V05_S0_PCH_VCCAPLL_SATA

PP3V3_S5_PCH

PP1V05_S0_PCH

PP1V05_S0_PCH_VCCAPLL_FDI

PP1V05_S0_PCH

PP1V05_S0_PCH_VCCAPLL_EXP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=X.XV

PPVOUT_S0_PCH_DCPSST

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV

PP3V3_S0_PCH

PP1V05_S0_PCH

PP1V05_S0_PCH_VCCADPLLA

PP3V3_S5_PCH

PP3V3_S0_PCH

PP1V8_S0_PCH

PPVTT_S0_PCH

PP1V8_S0_PCH_VCCTX_LVDS

PP3V3_S0_PCH_VCCALVDS

PP3V3_S0_PCH_VCCA_DAC

PP3V3R1V8_S0_PCH_VCCPNAND

PP3V3_S0M_PCH

PP1V05_S0_PCH_VCCADPLLB

PP1V8_S0_PCH

PP3V3_S0_PCH

MIN_NECK_WIDTH=0.2 mm

PPVOUT_G3_PCH_DCPRTC

VOLTAGE=X.XV

MIN_LINE_WIDTH=0.2 mm

PP3V3_S0_PCH

PP1V05_S0_PCH

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.1 mm

PP1V05_S0_PCH_VCCIO_SSC_FLT

22 OF 132 21 OF 103

17 18 21 23 24

101

17 18 21 23 24

101

17 18 21 23 24

101

20 21 23

101

17 18 19 20 21 23 24

101

23

21 24

101

17 18 21 23 24

101

6 7

17 23 43 45 46 47 48 49

50 51 54 65 66 74

23

101

17 18 21 23 24

101

21 24

101

23

17 18 19 20 21 23

101

17 18 21 23 24

101

23

17 18 21 23 24

101

17 18 21 23 24

101

23

17 18 19 20 21 23 24

101

17 18 21 23 24

101

24

17 18 19 20 21 23

101

17 18 19 20 21 23 24

101

21 24

101

20 21 23

101

24

101

24

23

101

23

101

24

21 24

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

17 18 21 23 24

101

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VSSVSS

(8 OF 10)

VSSVSS

(9 OF 10)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

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SIZE

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Apple Inc.

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A

B

C

345678

D

B

8 7 5 4 2 1

IBEX_PEAK_M

OMIT

FCBGA

U1800

AB16 AA19

AA32

AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42

AB11

AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52

AB15

AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12

AB23

AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24

AB30

AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18

AB31

AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

AB32 AB39 AB43 AB47

AA20

AB5 AB8

AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31

AA22

AD32 AD34 AU22 AD42 AD46 AD49

AD7

AE2

AE4 AF12

AM19

Y13 AH49

AU4 AF35 AP13 AN34 AF45 AF46 AF49

AF5

AA24

AF8

AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43

AA26

AH47

AH7 AJ19

AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32

AA28

AJ34

AT5

AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28

AA30

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5

AA31

AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26

OMIT

IBEX_PEAK_M

FCBGA

U1800

AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47

B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49

BB5 BC10 BC14 BC18

BC2 BC22 BC32 BC36 BC40 BC44 BC52

BH9 BD48 BD49

BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50

BE6

BE8

BF3 BF49 BF51 BG18 BG24

BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47

BH7

C12

C50

D51

E12

E16

E20

E24

E30

E34

E38

E42

E46

E48

E6 E8

F49

F5 G10 G14 G18

G2 G22 G32 G36 G40 G44 G52

AF39

H16 H20 H30 H34 H38 H42

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

PCH Grounds

SYNC_MASTER=T22_MLB

SYNC_DATE=03/26/2009

23 OF 132 22 OF 103

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

PAGE

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A

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345678

D

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8 7 5 4 2 1

PCH V5REF Filter & Follower

PCH VCC3_3 BYPASS

(PCH Misc PLL PWR)

PCH VCCACLK Filter

(VCCSUS3_3 Total)

PCH USB/VCCSUS3_3 BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

6 uA G3

2 mA S0-S5 /

1 mA S0-S5

PCH VCCIO BYPASS (PCH DMI 1.05V PWR)

(PCH 1.05V LAN Core PWR)

PCH V_CPU_IO BYPASS (PCH 1.1V/1.05V CPU I/O PWR)

(PCH SUSPEND USB 3.3V PWR)

1 mA S0-S5

(PCH Reference for 5V Tolerance on USB)

PCH V5REF_SUS Filter & Follower

(PCH MISC 3.3V PWR)

1 mA

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

(PCH CLK/HVCMOS 3.3V PWR)

(PCH PCI 3.3V PWR)

PCH CORE/VCC3_3 BYPASS

(PCH PCIE 1.05V PWR)

PCH VCCIO BYPASS

(PCH SATA 1.05V PWR)

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

PCH VCCIO BYPASS

PCH VCCCORE BYPASS

(PCH RTC 3.3V PWR)

1 mA

(PCH CLK 1.05V PWR)

PCH VCCSUSHDA BYPASS

PCH VCCPNAND BYPASS (PCH NAND 1.8V/3.3V PWR)

(PCH 1.05V CORE PWR)

PCH VCCSUS3_3 BYPASS (PCH SUSPEND PCI 3.3V PWR)

PCH VCCME3_3 BYPASS (PCH ME 3.3V PWR)

(PCH SATA 3.3V PWR)

PCH VCC3_3 BYPASS

163 mA S0 /

65 mA S3-S5

PCH VCCME BYPASS (PCH 1.05V ME Core PWR)

PCH VCC3_3 BYPASS

(PCH PCIe/DMI 3.3V PWR)

PCH VCCFDIPLL Filter (PCH FDI PLL PWR)

WF: C2413 not in DG or CRB

WF: C2311 not in DG or CRB

PCH VCCAPLLEXP Filter (PCH PCIe PLL PWR)

PCH VCCLAN BYPASS

(PCH Reference for 5V Tolerance on PCI)

PCH VCCSATAPLL Filter (PCH SATA PLL PWR)

PCH VCCRTC BYPASS

402

10V

10% X5R

1UF

PLACE_NEAR=U1800.K49:2.54MM

C2401

1

2

NO STUFF

PLACE_NEAR=U1800.AP51:2.54MM

2

1

C2419

1UF

CERM 402

10%

6.3V

5%

1/16W

402

MF-LF

100

R2401

2

1

2

1

402

10%

1UF

X5R

PLACE_NEAR=U1800.F24:2.54MM

10V

C2400

BAT54DW-X-G

SOT-363

D2400

1

6

5

1/16W

10

5%

402

R2400

2

1

MF-LF

D2400

BAT54DW-X-G

SOT-363

2

3

4

16V

10% 402

X5R

0.1UF

PLACE_NEAR=U1800.A12:2.54MM

C2421

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.P18:2.54MM

C2425

1

2

16V

10% 402

X5R

0.1UF

PLACE_NEAR=U1800.A12:2.54MM

C2422

1

2

C2413

6.3V

10%

402

CERM

1UF

OMIT

PLACE_NEAR=U1800.BJ24:2.54MM

1

2

6.3V

10% 402

1UF

OMIT

CERM

PLACE_NEAR=U1800.BJ18:2.54MM

C2415

1

2

NO STUFF

PLACE_NEAR=U1800.AK1:2.54MM

2

1

C2417

1UF

CERM 402

10%

6.3V

X5R 402

16V

0.1UF

10%

PLACE_NEAR=U1800.U23:2.54MM

C2427

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.A26:2.54MM

C2426

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AM8:2.54MM

C2430

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.V15:2.54MM

C2435

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.J38:2.54MM

C2436

1

2

PLACE_NEAR=U1800.AD13:2.54MM

0.1UF

X5R 402

10% 16V

C2437

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AN35:2.54MM

C2438

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AB34:2.54MM

C2439

1

2

16V

10%

402

X5R

0.1UF

C2440

1

2

PLACE_NEAR=U1800.AK13:2.54MM

1UF

CERM 402

10%

6.3V

PLACE_NEAR=U1800.L30:2.54MM

C2445

1

2

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U1800.AT18:2.54MM

C2452

1

2

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U1800.AT18:2.54MM

C2451

1

2

6.3V

20%

603

X5R

4.7UF

PLACE_NEAR=U1800.AT18:2.54MM

C2450

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.V39:2.54MM

C2469

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.V39:2.54MM

C2467

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.AD38:2.54MM

C2466

1

2

NO STUFF

C2460

1UF

10%

6.3V 402

CERM

PLACE_NEAR=U1800.AF23:2.54MM

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AH35:2.54MM

C2477

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AH23:2.54MM

C2476

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AF32:2.54MM

C2475

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.V24:2.54MM

C2480

1

2

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.AB19:2.54MM

C2485

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2494

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2493

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2492

1

2

402

6.3V

10% CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2491

1

2

10UF

6.3V

20% 603

X5R

PLACE_NEAR=U1800.AN20:2.54MM

C2490

1

2

402

6.3V

10% CERM

1UF

PLACE_NEAR=U1800.AT16:2.54MM

C2455

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AD38:2.54MM

C2468

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.AD38:2.54MM

C2465

1

2

402

2

6.3V CERM

10%

PLACE_NEAR=U1800.AB24:2.54MM

1

1UF

C2471

10UF

C2470

PLACE_NEAR=U1800.AB24:2.54MM

6.3V X5R 603

1

2

20%

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.A12:2.54MM

C2420

1

2

PCH Non-GFX Decoupling

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

PP1V05_S0_PCH_VCCA_CLK

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_SATA

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V

PP5V_S5

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_EXP

PP1V05_S0_PCH_VCCAPLL_FDI

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP5V_S5_PCH_V5REFSUS

PP3V3_S0_PCH

PP1V05_S0_PCH

PP3V3_S5_PCH

PP3V3_S0M_PCH

PP3V3_S0_PCH

PP3V3R1V5_S0_PCH

PP3V3R1V8_S0_PCH_VCCPNAND

GND

PP1V05_S0_PCH

PPVTT_S0_PCH

PP1V05_S0_PCH

PP3V3_S0_PCH

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

PP5V_S0_PCH_V5REF

VOLTAGE=5V

PP5V_S0

PP3V42_G3H

PP3V3_S5_PCH

24 OF 132 23 OF 103

21

7

57 67 73

102

21

17 18 19 20 21 23

24

101

17 18 21 23 24

101

17 18 19 20 21 23

101

21

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

17 18 19 20 21 23 24

101

21

101

21

101

17 18 21 23 24

101

17 18 21 23 24

101

17 18 21 23 24

101

17 18 21 23 24

101

20 21 23

101

20 21 23

101

17 18 21 23 24

101

17 18 19 20 21 23 24

101

21

6 7 8

42

48 53 55 69 70

71 73

87

102

6 7

17 21 43 45 46 47 48 49

50 51 54 65 66 74

17 18 19 20 21 23

101

17 18 19 20 21 23

101

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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345678

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8 7 5 4 2 1

PCH VCCTX_LVDS Filter

69 mA

68 mA

(PCH DPLLB PWR)

(PCH DAC PLL PWR)

Design recommendations from Calpella Design Guide Rev 1.5 (doc #398905) Section 3.25.3 tables 161 and 162.

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

69 mA

59 mA

(PCH LVDS TX PWR)

PCH VCCADAC Filter

69 mA

68 mA

59 mA

69 mA

137 mA

actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

GFX (CPU VCCAXG) DECOUPLING

3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402

PLACEMENT_NOTE (C2510-C2514):

5x 1uF 0402

PLACEMENT_NOTE (C2500-C2506):

PLACEMENT_NOTE (C2524-C2539):

VCAP2 (CPU BSC Package) DECOUPLING

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PCH VCCADPLLB Filter

0805

0.1UH

PLACE_NEAR=U1800.AP43:2.54MM

L2570

1 2

PLACE_NEAR=U1800.AP43:2.54MM

16V 402

0.01UF

20% CERM

C2572

1

2

NO STUFF

PLACE_NEAR=U1800.BB51:2.54MM

402

CERM

1UF

6.3V

10%

C2561

1

2

0

402

5%

MF-LF

1/16W

R2560

1 2

CASE-B2-SM1

220UF

POLY-TANT

2.5V

20%

PLACE_NEAR=U1800.BB51:2.54MM

C2560

1

2

NO STUFF

PLACE_NEAR=U1800.BD51:2.54MM

402

6.3V CERM

1UF

10%

C2566

1

2

PLACE_NEAR=U1800.BD51:2.54MM

220UF

POLY-TANT

CASE-B2-SM1

20%

2.5V

C2565

1

2

MF-LF

402

1/16W

0

5%

R2565

1 2

PLACE_NEAR=U1800.AE50:2.54MM

CERM

20% 16V

402

0.01UF

C2552

1

2

PLACE_NEAR=U1800.AE50:2.54MM

20%

6.3V X5R 603

10UF

C2550

1

2

X5R-CERM

22UF

Place on bottom side of U1000.

20%

603

6.3V

C2500

1

2

PLACE_NEAR=U1800.AE50:2.54MM

0603

180-OHM-1.5A

L2550

1 2

MF-LF

1/16W

5%

402

0

R2550

1 2

16V 402

20% CERM

PLACE_NEAR=U1800.AP43:2.54MM

0.01UF

C2571

1

2

PLACE_NEAR=U1800.AE50:2.54MM

10% 402

0.1UF

16V X5R

C2551

1

2

Place on bottom side of U1000.

10V 402

1UF

10% X5R

C2514

1

2

Place on bottom side of U1000.

1UF

X5R

10% 402

10V

C2513

1

2

402

Place on bottom side of U1000.

X5R

10%

1UF

10V

C2512

1

2

Place on bottom side of U1000.

1UF

X5R

10% 402

10V

C2511

1

2

Place on bottom side of U1000.

10V 402

1UF

10% X5R

C2510

1

2

D2T-SM2

20% POLY-TANT

2.0V

330UF

C2505

1

23

330UF

D2T-SM2

2.0V

20% POLY-TANT

C2506

1

23

603

X5R-CERM

PLACE_NEAR=U1800.AP43:2.54MM

22UF

20%

6.3V

C2570

1

2

10UH-0.12A-0.36OHM

0603

L2560

1 2

Place on bottom side of U1000.

6.3V X5R-CERM 603

22UF

20%

C2501

1

2

10UH-0.12A-0.36OHM

0603

L2565

1 2

402

10% X5R

1UF

10V

C2535

1

2

402

10% X5R

10V

1UF

C2534

1

2

402

10% X5R

1UF

10V

C2533

1

2

402

10% X5R

1UF

10V

C2532

1

2

402

10% X5R

1UF

10V

C2531

1

2

402

10% X5R

10V

1UF

C2530

1

2

402

10% X5R

1UF

10V

C2529

1

2

402

10% X5R

1UF

10V

C2528

1

2

Place on bottom side of U1000.

402

10% X5R

1UF

10V

C2527

1

2

Place on bottom side of U1000.

402

10% X5R

10V

1UF

C2526

1

2

1UF

Place on bottom side of U1000.

402

10V

10% X5R

C2525

1

2

Place on bottom side of U1000.

402

10% X5R

1UF

10V

C2524

1

2

402

10V

10% X5R

1UF

C2539

1

2

402

10V X5R

10%

1UF

C2538

1

2

402

10% X5R

1UF

10V

C2537

1

2

402

10% X5R

1UF

10V

C2536

1

2

20%

22UF

603

X5R-CERM

6.3V

Place on bottom side of U1000.

C2502

1

2

CPU/PCH GFX Decoupling

SYNC_MASTER=K17_WFERRY

SYNC_DATE=06/09/2009

PPVCORE_S0_GFX

PPVCORE_S0_CPU_VCAP2

PP3V3_S0_PCH

PP1V8_S0_PCH

PP3V3_S0_PCH_VCCA_DAC_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=3.3V

PP1V8_S0_PCH_VCCTX_LVDS

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCCA_DAC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCADPLLA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCADPLLA_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCADPLLB_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLB

VOLTAGE=1.05V

25 OF 132 24 OF 103

7

13 50 70

7

13

17 18 19 20 21 23

101

21

101

21

17 18 21 23

101

21

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BI

OUT

NC

BI

OUT

IN

IN IN

IN

OUT

NC

BI

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

IN

IN IN

IN

IN IN IN IN

IN

IN IN

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

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8 7 5 4 2 1

PCH OC6#

PCH OC5#

PCH OC4#

PCH OC3#

OBSFN_A0

HOOK3

SDA

NOTE: This is not the standard XDP pinout.

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT PCH DEBUGGING.

OBSDATA_C2

OBSFN_B0

OBSDATA_D0

Calpella PCH mini XDP

OBSFN_D1

OBSDATA_A1

OBSDATA_A2

PCH OC0#

OBSDATA_A0

PCH GPIO16

PCH GPIO37

PCH GPIO36

ITPCLK/HOOK4 ITPCLK#/HOOK5

998-2515

1K series R on PCH Support Page

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

OBSFN_D0

OBSDATA_C3

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

XDP_PRESENT#

TRSTn

TDO

TDI TMS

OBSDATA_B0 OBSDATA_B1

OBSDATA_D1

OBSDATA_D2

HOOK2

PCH OC2#

PCH OC7#

PCH OC1#

PCH GPIO28

PCH GPIO18

PCH GPIO20

PCH GPIO21 PCH GPIO19

PCH GPIO49

PCH GPIO0

RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TRSTn

TCK1

OBSDATA_A3

OBSDATA_B3

HOOK1

HOOK2

OBSDATA_B2

SCL

OBSFN_A1

OBSFN_B1

OBSDATA_A0 OBSDATA_A1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSFN_A0 OBSFN_A1

OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

OBSDATA_B2

HOOK3

TCK1 TCK0

OBSFN_B1

OBSDATA_B0 OBSDATA_B1

SDA SCL

OBSDATA_C1

OBSDATA_C3

OBSDATA_C2

OBSFN_D1

OBSFN_D0

OBSFN_C1

OBSFN_C0

OBSDATA_D0

ITPCLK/HOOK4 ITPCLK#/HOOK5

OBSDATA_D3

XDP_PRESENT#

VCC_OBS_CD

TDO

TDI TMS

998-1571

OBSDATA_C0

PWRGD/HOOK0

TCK0

VCC_OBS_AB

Calpella Processor mini XDP

6

17 25 26 28 30 32 34 42 48 49 64 94

17

10 91

17

27 46 74 88

19

19 35

19

17

402

MF-LF

1/16W

2

1

R2615

5%

XDP

51

CRITICAL XDP_CONN

F-ST-SM

59

57

51 53 55

47 49

45

41 43

35

39

37

31 33

25 27

21 23

17

15

19

13

11

9

7

5

1 34

2

6

8 10 12 14

20

16 18

22 24 26

30

28

34

32

38 40

36

42 44 46 48 50

56

54

52

58 60

J2600

LTH-030-01-G-D-NOPEGS

29

DF40C-60DS-0.4V

J2650

F-ST-SM

7

41

39

37

35

20

36

CRITICAL XDP_CONN

3

1

5

11

9

13

17

15

23

19 21

25 27 29

33

31

43 45 47 49 51 53

59

57

55

38 40

32 34

30

28

26

24

22

16 18

10

14

12

6 8

2 4

56 58 60

54

52

50

48

46

44

42

2

1

XDP

X5R

10%

402

16V

0.1uF

C2600

2

1

C2601

XDP

X5R

0.1uF

10%

402

16V

6

17 25 26 28 30 32 34 42 48 49 64 94

10 91

10 25 27 91

10 91

21

R2611

PLACE_NEAR=U1000.N70:1.00MM

5%

MF-LF

1/16W

402

XDP

1K

10 20 91

10 91

18 25 46

10 91

XDP_NORMAL&XDP_CPU

21

R2690

MF-LF

1/16W

402

0

5%

XDP

R2610

402

1/16W MF-LF

21

5%

1K

XDP_CPU

R2695

21

5%

0

402

1/16W MF-LF

402

XDP_GMCH

21

R2696

MF-LF

1/16W

0

5%

XDP_NORMAL&XDP_GMCH

21

R2692

MF-LF

1/16W

402

0

5%

R2691

2

1

XDP_NORMAL

MF-LF

1/16W

402

0

5%

10

9

91

9

91

10 91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

8 9

91

9

91

9

91

9

91

9

91

8

1/16W SM-LF

5

6

7

4

3

2

1

RP2600

5%

0

XDP_CPU_BPM

RP2601

5

6

7

8

4

3

2

1

1/16W SM-LF

5%

0

XDP_CPU_CFG

PLACEMENT_NOTE=Place R2601 close to R2600 to minimize stubs.

10 91

9

91

9

91

9

91

9

91

20 46 47

20 31

17 40

17 33

17 42

17

27

20 88

20

20 64

SYNC_DATE=06/22/2009

SYNC_MASTER=K18_MLB

eXtended Debug Port (XDP)

CPU_CFG<15>

CPU_CFG<13>

XDP_BPM_L<3>

PCH_GPIO59

SMBUS_PCH_DATA SMBUS_PCH_CLK

TP_XDP_HOOK3

XDP_CPUPWRGD

PPCPUVTT_S0

PM_PWRBTN_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<4> XDP_BPM_L<5>

CPU_CFG<16>

CPU_CFG<17>

XDP_OBSDATA_A<3>

XDP_OBSDATA_A<2>

XDP_OBSDATA_A<1>

XDP_OBSDATA_A<0>

XDP_PRDY_L

XDP_PREQ_L CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<11>

CPU_CFG<10>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<6>

FSB_CLK133M_ITP_P

CPU_CFG<7>

FSB_CLK133M_ITP_N

XDP_CPURST_L XDP_DBRESET_L

XDP_TDI

XDP_TRST_L

XDP_TDO

XDP_TMS

XDP_BPM_L<0>

XDP_BPM_L<2>

XDP_BPM_L<1>

CPU_CFG<12>

CPU_CFG<14>

CPU_PWRGD

JTAG_GMCH_TDI

JTAG_CPU_TDO

JTAG_GMCH_TDO

JTAG_CPU_TDI

FSB_CPURST_L

XDPPCH_PLTRST_L XDP_DBRESET_L

TP_XDPPCH_TRST_L JTAG_PCH_TDI

ISOLATE_CPU_MEM_L SMC_IG_THROTTLE_L

AP_CLKREQ_L

FW_CLKREQ_L

SATARDRVR_A_EN

JTAG_GMUX_TCK

AUD_IPHS_SWITCH_EN ME_TEMP_ALERT_L

TP_XDPPCH_HOOK4

TP_XDPPCH_HOOK3

TP_XDPPCH_HOOK2

PCH_GPIO9

PCH_GPIO43

PCH_GPIO41

USB_HUB_SOFT_RESET_L

TP_XDPPCH_OBSFN_A<1>

TP_XDPPCH_HOOK5

JTAG_PCH_TDO

JTAG_PCH_TMS

PM_LATRIGGER_L

PCH_GPIO42

XDP_TDI

TP_XDPPCH_OBSFN_D<0>

SDCARD_RESET

TP_XDPPCH_OBSFN_D<1>

SATARDRVR_B_EN

SMBUS_PCH_DATA SMBUS_PCH_CLK

JTAG_PCH_TCK

PM_PWRBTN_L

ALL_SYS_PWRGD

PCH_GPIO10

TP_XDPPCH_OBSFN_B<1>

TP_XDPPCH_OBSFN_B<0>

PP3V3_S0

TP_XDPPCH_OBSFN_A<0>

XDP_TDO

XDP_TCK

XDP_PWRGD

26 OF 132 25 OF 103

6 7

10 12 13 15 26 40 71 74

101

91

25 91

10 25 27 91

25 91

6

17 25 26 28 30 32 34 42 48

49 64 94 6

17 25 26 28 30 32 34 42 48

49 64 94

18 25 46

6 7 8

26 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

25 91

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IN

BI

IN

OUT

CPU0*

CPU0

REF_FS

USB

CPU1

CPU1*

SRC1*

SRC1

SRC0*/SATA*

SRC0/SATA

27M_NSS

27M_SS

DOT96*

XOUT

XIN

SCLK

SDATA

CK_PWRGD/PWRDWN*

VDD_SRC

VDD_CPU

VDD_REF

VDD_DOT

VDD_27

VDD_SRC_IO

VDD_CPU_IOVSS_CPU

VSS_27

VSS_DOT

THRM

VSS_SRC

VSS_REF

DOT96

27MHZ_OE*

PAD

OUT OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: REF/FS pin is input until first CK_PWRGD rising edge. FS=0 => 133MHz BCLKs, FS=1 => 100MHz BCLKs All other output frequencies are fixed.

PCH DMI/PCIe 100MHz

GPU 27MHz Clocks (Single-Ended)

PCH SATA 100MHz

PCH BCLK 133MHz

Unused BCLK 133MHz

PCH REFCLK 14.31818MHz Unused 48MHz

PCH USB Clock 96MHz

(IPD)

Must be strapped appropriately or connected to logic for Muxed Graphics implementations.

No internal pull.

0.1UF

CERM

402

20% 10V

BYPASS=U2790::5 mm

C2790

1

2

69

74HC1G00GWDG

SC70-5

U2790

3

2

1

4

5

18pF

402

CERM

50V

5%

PLACE_NEAR=Y2730.1:2 mm:NO_VIA

C2730

1

2

14.31818

5X3.2-SM

CRITICAL

Y2730

1 2

PLACE_NEAR=Y2730.2:2 mm:NO_VIA

5% 50V CERM 402

18pF

C2731

1

2

0402

FERR-120-OHM-1.5A

L2710

1 2

FERR-120-OHM-1.5A

0402

L2700

1 2

20%

6.3V X5R 603

10UF

PLACE_NEAR=L2700.2:2 mm:NO_VIA

C2700

1

2

10UF

603

X5R

6.3V

20%

PLACE_NEAR=L2710.2:2 mm:NO_VIA

C2710

1

2

6

17 25 28 30 32 34 42 48 49 64 94

6

17 25 28 30 32 34 42 48 49 64 94

17 93

0.1UF

402

X5R

16V

10%

PLACE_NEAR=U2700.15:2 mm

C2715

1

2

0.1UF

402

X5R

16V

10%

PLACE_NEAR=U2700.18:2 mm

C2716

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.1:2 mm

C2705

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.5:2 mm

C2706

1

2

SL28776

QFN

CRITICAL

U2700

6

7

16

25

23

22

20

19

3

4

30

32

31

11 10

13

14

33

8

5

24

18

1

29

17

15

9212

26

12

28 27

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.17:2 mm

C2707

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.24:2 mm

C2708

1

2

10% 16V X5R 402

0.1UF

PLACE_NEAR=U2700.29:2 mm

C2709

1

2

17 93

74

1

2

402

R2790

10K

5% 1/16W MF-LF

Clock (CK505)

SYNC_MASTER=K17_REF

SYNC_DATE=05/19/2009

PP3V3_S0

CPUIMVP_CLK_EN_L

TP_CK505_CPU1P

PCH_CLK100M_SATA_P CK505_CLK27M TP_CK505_CLK27M_SS

CK505_27MHZ_EN_L

SMBUS_PCH_DATA

SMBUS_PCH_CLK

CK505_CLK14P3M_XOUT

CK505_CLK14P3M_XIN

CK505_CKPWRGD

TP_CK505_USB

TP_CK505_CPU1N

FSB_CLK133M_PCH_P

FSB_CLK133M_PCH_N

PPCPUVTT_S0

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_S0_CK505_F

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

PP3V3_S0_CK505_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLK14P3M_REFCLK

27 OF 132 26 OF 103

6 7 8

25 27 28 30 34 37 40 42 47 48 49

52 53 55 59 63 64 69 70 71 72 73 74 81

84 85 86 88 99

101

27

6 7

10 12 13 15 25 40 71 74

101

www.vinafix.vn

IN

OUT

IN

OUT

IN

OUT

NC NC

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

D

GS

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH RTC Crystal

PCH 25MHz Crystal

Ethernet WAKE# Isolation

PCH S0 PWRGD

Platform Reset Connections

Unbuffered

VTT voltage divider on CPU page

Series R is R4283

PCH Reset Button

Buffered

Caesar II (ENET) 25MHz Crystal

10 25 91

5%

402

50V

CERM

12pF

C2810

1 2

CERM

5%

402

50V

12pF

C2811

1 2

32.768K

CRITICAL

SM-2

Y2810

2 4

1 3

402

MF-LF

0

1/16W

5%

R2810

1 2

402

MF-LF

10M

5%

R2811

1

2

1/16W

XDP

MF-LF

5%

0

1/16W

R2896

1 2

402

MF-LF

402

1/16W

33

5%

R2883

1 2

1/16W

33

MF-LF

402

5%

R2881

1 2

6

27 48 88 94

46

33

17

19 27 31 40

22

5%

MF-LF

1/16W

402

R2826

1 2

PLACE_NEAR=U1800.P53:5mm

22

402

1/16W MF-LF

5%

R2825

1 2

PLACE_NEAR=U1800.N52:5mm

19 94

12pF

50V 402

5%

CERM

C2815

1 2

5%

50V

12pF

CERM

402

C2816

1 2

SM-3.2X2.5MM

25.0000M

CRITICAL

Y2815

2 4

1 3

MF-LF

1/16W

5%

0

402

R2815

1 2

DCI

402

1/16W MF-LF

10M

5%

R2816

1

2

17

32

0

MF-LF

5%

402

1/16W

R2871

1 2

C2850

402

20% CERM

0.1UF

10V

1

2

25 46 74 88

69

6

48 94

46 94

18

MC74VHC1G08

SC70-HF

U2850

3

2

1

4

5

19

CERM

50V

5%

402

27pF

C2820

1 2

50V

5%

CERM

402

27pF

C2821

1 2

CRITICAL

25.0000M

SM-3.2X2.5MM

Y2820

2 4

1 3

1/16W

402

5%

MF-LF

200

R2820

1 2

402

NO STUFF

5%

MF-LF

10M

R2821

1

2

1/16W

37 95

88

22

5% 1/16W MF-LF

402

R2827

1 2

PLACE_NEAR=U1800.P46:5mm

25

5%

MF-LF

402

1/16W

XDP

1K

R2889

1 2

5%

0

1/16W MF-LF

402

R2888

1 2

34

0

5%

MF-LF

1/16W

402

R2884

1 2

CERM

20% 10V

402

0.1UF

C2880

1

2

SC70-HF

MC74VHC1G08

U2880

3

2

1

4

5

402

100K

5% MF-LF

1/16W

R2880

1

2

R2850

10K

5%

402

1/16W MF-LF

2

1

37 95

0

5% MF-LF

402

1/16W

R2882

1 2

17 93

22

402

MF-LF

1/16W

5%

R2829

1 2

PLACE_NEAR=U1800.P48:5mm

19

19 27

27 88

MF-LF

1/16W

5%

402

0

R2887

1 2

SILK_PART=SYS RESET

MF-LF

1/16W 402

5%

0

OMIT

R2897

1

2

6

27 48 88 94

0

1/16W

5% MF-LF

402

1 2

R2824

PLACE_NEAR=U2700.6:5mm

26 27

90

402

1/16W MF-LF

5%

0

R2893

1 2

10K

MF-LF

1/16W 402

5%

R2895

1

2

80 81 98

6

18 46

19 27 31 40

SSM3K15FV

SOD-VESM-HF

Q2830

3

1

2

6

18 33 34 27 37

10K

5%

402

1/16W MF-LF

R2830

1

2

10 27

SYNC_DATE=06/17/2009

SYNC_MASTER=K17_REF

Chipset Support

MAKE_BASE=TRUE

ENET_WAKE_L

XDP_DBRESET_L

PM_SYSRST_L

PP3V3_S0

GMUX_RESET_L

MAKE_BASE=TRUE

BKLT_PLT_RST_L

PLT_RESET_L

MAKE_BASE=TRUE

GMUX_RESET_L

PCH_CLK32K_RTCX1

ENET_RESET_L

AP_RESET_L

LPCPLUS_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

EXCARD_RESET_L

PLT_RESET_L

PCA9557D_RESET_L

XDPPCH_PLTRST_L

PLT_RST_BUF_L

MAKE_BASE=TRUE

PM_PCH_PWRGD

ALL_SYS_PWRGD

CPUIMVP_PGOOD

PP3V3_S0

SMC_LRESET_L

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

GPU_CLK27M

MAKE_BASE=TRUEMAKE_BASE=TRUE

CK505_CLK27M

LPC_CLK33M_GMUX_R

CK505_CLK27M

PCH_CLK32K_RTCX2_R

BCM5764_CLK25M_XTALO_R

PCH_CLK32K_RTCX2

PCH_CLK25M_XTALOUT

BCM5764_CLK25M_XTALO

ENET_WAKE_L

BCM5764_CLK25M_XTALI

PP3V3_ENET

PCIE_WAKE_L

LPC_CLK33M_GMUX

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

PCH_CLK25M_XTALIN

PCH_CLK25M_XTALOUT_R

PCH_CLK33M_PCIOUT

MAKE_BASE=TRUE

LPC_CLK33M_GMUX_R

28 OF 132 27 OF 103

27 37

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

27 88

10 27

6 7 8

25 26 27 28 30 34 37 40 42 47

48 49 52 53 55 59 63 64 69 70 71 72

73 74 81 84 85 86 88 99

101

6 7 8

25 26 27 28 30 34 37 40 42 47 48

49 52 53 55 59 63 64 69 70 71 72 73 74

81 84 85 86 88 99

101

26 27

7

37 74

19 27

www.vinafix.vn

A6

A7

A11

A5

DQ33

VDD A10/AP

VDD

VSS

SA1 VTT

VSS

DQS4* DQS4 VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43 VSS

DM5 VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0 VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

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SHEET

PAGE TITLE

C

A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

- =PP1V5_S3_MEM_A

Signal aliases required by this page:

SPD ADDR=0xA0(WR)/0xA1(RD)

BOM options provided by this page:

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S0_MEM_A

- =PP0V75_S0_MEM_VTT_A

(NONE)

"Factory" (top) slot

Power aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

Page Notes

516-0229

J2900

DDR3-SODIMM-DUAL-K6

F-RT-THB

199

185

76

74

78 80 82

88

92 94 96

102

98 100

106

104

112

110

108

116

114

122

120

118

126

130 132

128

136

134

138 140 142

148

146

144

152

150

73 75 77 79 81 83 85

89

87

93 95 97

101

99

111

109

113 115

119 121

117

123 125

129

133

141

147

145

149

158

156

154

162

160

164

168

166

172

170

174 176 178

184

182

180

188

186

194

190 192

198

196

204

202

200

157

155

153

161

159

163 165 167

171

169

173

177

175

181 183

179

187

193

191

189

197

103

151

143

139

137

135

127

203

201

195

124

107

105

131

91

84 86

90

29

C2931

2

1

0.1UF

CERM 402

20% 10V

2

1

C2930

6.3V CERM 402-LF

20%

2.2UF

29

11 92

11 29 92

29

30 31

29

CRITICAL

J2900

DDR3-SODIMM-DUAL-K6

F-RT-THB 15 17

3

1

7

5

9 11 13

19

23

21

25 27 29

33

31

35

43

41

45

49

47

51 53 55

59

57

2

6 8 10 12 14 16 18 20 22 24 26 28 30

34

32

36 38 40

44

42

46 48 50

54

52

56 58 60 62 64 66 68 70 72

4

71

69

67

65

63

61

39

37

11 29 92

29

11 92

29

11 92

11 29 92

29

2

1

C2936

10V

20%

402

CERM

0.1UF

2

1

402-LF

20%

6.3V CERM

2.2UF

C2935

29

30 46 47

6

17 25 26 30 32 34 42 48 49 64

94

6

17 25 26 30 32 34 42 48 49 64

94

11 92

29

2

1

R2941

10K

5%

402

1/16W MF-LF

2

1

R2940

MF-LF

1/16W

5%

10K

402

2

1

2.2UF

20%

CERM 402-LF

6.3V

C2940

2

1

603

X5R

20%

10UF

C2900

6.3V

1

6.3V

20%

2

C2901

10UF

X5R 603

2

1

C2910

CERM 402

10V

20%

0.1UF

2

1

C2911

0.1UF

402

CERM

20% 10V

2

1

C2912

CERM

0.1UF

20% 10V

402

2

1

C2913

402

CERM

10V

20%

0.1UF

2

1

C2914

10V 402

CERM

20%

0.1UF

2

1

C2915

0.1UF

20%

402

CERM

10V

2

1

C2916

10V

0.1UF

20%

402

CERM

2

1

C2917

10V

0.1UF

20%

402

CERM

2

1

C2918

10V

0.1UF

20%

402

CERM

2

1

C2919

10V

0.1UF

20%

402

CERM

2

1

C2920

10V

20%

402

CERM

0.1UF

2

1

C2921

10V

0.1UF

20%

402

CERM

2

1

C2922

10V

0.1UF

20%

402

CERM

2

1

C2923

10V

0.1UF

20%

402

CERM

SYNC_MASTER=K17_REF

SYNC_DATE=05/13/2009

DDR3 SO-DIMM Connector A

PP1V5_S3

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PP3V3_S0

=MEM_A_DQS_N<4>

MEM_A_SA<0>

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PP0V75_S3_MEM_VREFCA_A

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MEM_A_DM<0>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

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=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<24>

=MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

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MEM_A_A<15> MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_ODT<1>

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MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_CS_L<1>

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MEM_EVENT_A_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

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MEM_A_CLK_N<0>

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MEM_A_SA<1>

MEM_A_A<10>

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MEM_A_A<5>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6>

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MEM_A_CKE<1>

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MEM_A_A<12>

MEM_A_BA<2>

MEM_A_CKE<0>

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MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<9>

MEM_A_A<13>

PP0V75_S0_DDRVTT

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PP0V75_S3_MEM_VREFDQ_A

29 OF 132 28 OF 103

7

30 31 68 73

6 7 8

25 26 27

30 34 37 40 42 47 48 49

52 53 55 59 63

64 69 70 71 72 73 74 81

84 85 86 88 99

101

32

7

30 31 68

32

www.vinafix.vn

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

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SYNC_DATE=06/19/2009

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MEM_B_DQ<42>

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MEM_B_DQ<47>MEM_A_DQ<47>

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MEM_A_DQ<35>

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MEM_A_DQ<24>

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DM<3> MEM_A_DQ<31>

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MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQ<18>

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MAKE_BASE=TRUE

MEM_B_DQ<30>

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MAKE_BASE=TRUE

MEM_B_DM<6>

MEM_A_DQ<30>

MAKE_BASE=TRUE

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MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MEM_A_DM<2>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MEM_A_DQS_N<0>

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_A_DQ<62>

MAKE_BASE=TRUE

MEM_A_DM<7>

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MEM_A_DM<5>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<40>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DM<6> MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DM<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQ<37>

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MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MAKE_BASE=TRUE

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

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MEM_A_DQS_N<2>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQ<20>

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MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

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MEM_A_DQ<37>

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MEM_A_DQ<3>

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MEM_A_DQ<0>

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MEM_A_DM<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MEM_A_DQ<13>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<7> MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<11>

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

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MEM_A_DQS_N<0>

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MEM_A_DM<0>

MEM_A_DQS_P<0> MEM_A_DM<0>

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MEM_B_DQS_P<0>

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MEM_B_DQ<11>

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MEM_B_DQ<10>

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MEM_B_DQ<18>

MAKE_BASE=TRUE

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MEM_B_DQ<17>

MAKE_BASE=TRUE

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MEM_B_DQ<31>

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MEM_B_DQ<26>

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MAKE_BASE=TRUE

MEM_B_DQ<27>

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MAKE_BASE=TRUE

MEM_B_DQ<25>

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MAKE_BASE=TRUE

MEM_B_DQS_N<4>

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MAKE_BASE=TRUE

MEM_B_DQ<39>

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MEM_B_DQS_P<4>

MAKE_BASE=TRUE

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MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<35>

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MAKE_BASE=TRUE

MEM_B_DQ<36>

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MEM_B_DQ<33>

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MEM_B_DQ<32>

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MAKE_BASE=TRUE

MEM_B_DQS_P<5>

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MEM_B_DM<5>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MEM_B_DQ<44>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<40>

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MEM_B_DQ<41>

MAKE_BASE=TRUE

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MEM_B_DQS_N<6>

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MEM_B_DQS_P<6>

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MEM_B_DQ<55>

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MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<53>

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MEM_B_DQ<52>

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MAKE_BASE=TRUE

MEM_B_DQ<51>

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MAKE_BASE=TRUE

MEM_B_DQ<50>

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MAKE_BASE=TRUE

MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<48>

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MEM_B_DQS_P<7>

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MEM_B_DQS_N<7>

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MEM_B_DQ<62>

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MEM_B_DQ<63>

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MEM_B_DQ<60>

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MEM_B_DQ<61>

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MEM_B_DQ<57>

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MEM_B_DQ<58>

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MEM_B_DQ<56>

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MEM_A_DQ<4>

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MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<7>

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MEM_B_DM<0>

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MEM_B_DQ<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<1>

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MEM_B_DQ<2>

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MEM_B_DQ<3>

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MEM_B_DQ<4>

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MEM_B_DQS_N<1>

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MEM_B_DQ<1>

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MEM_B_DQ<14>

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MEM_B_DQ<20>

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MEM_B_DQ<21>

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MEM_B_DM<2>

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MEM_B_DQS_P<2>

MEM_B_DM<1>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<15>

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MEM_B_DQS_N<2>

MEM_B_DQ<9>

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MEM_B_DQ<12>

MEM_B_DQ<8>

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MEM_B_DQ<19>

MEM_B_DQS_P<3>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DM<3>

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MEM_B_DQ<22>

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MEM_B_DQ<23>

MEM_B_DM<0>

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MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DM<4>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

=MEM_B_DQ<33> =MEM_B_DQ<39> =MEM_B_DQ<37>

=MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<16>

=MEM_A_DQ<22>

=MEM_A_DQ<20>

30 OF 132 29 OF 103

30

30 11 92

11 92 11 92

30

11 92

28

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30

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30

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28

11 92

11 28 29 92

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28

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30

30 11 92

30

11 92

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30

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30

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30

30 11 92

30

30 11 92

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30

30 11 92

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30

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28

www.vinafix.vn

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516s0806

Power aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Page Notes

- =PP0V75_S0_MEM_VTT_B

(NONE)

BOM options provided by this page:

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

Signal aliases required by this page:

"Expansion" (bottom) slot

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

SPD ADDR=0xA4(WR)/0xA5(RD)

11 92

29

28 46 47

6

17 25 26 28 32 34 42 48 49 64

94

6

17 25 26 28 32 34 42 48 49 64

94

2

1

C3131

0.1UF

CERM 402

20% 10V

11 92

29

11 29 92

29

2

1

C3130

2.2UF

20%

6.3V

402-LF

CERM

1 2

402

5%

MF-LF

1/16W

10K

R3141

10K

5% 1/16W MF-LF 402

R3140

1

2

20%

CERM 402-LF

6.3V

2.2UF

C3140

1

2

1

C3100

10UF

20% X5R

603

6.3V 2

1

C3101

6.3V

10UF

X5R 603

20%

2

1

C3110

CERM 402

10V

20%

0.1UF

2

1

C3111

0.1UF

402

CERM

10V

20%

2

1

C3112

CERM

0.1UF

20% 10V

402

2

1

C3113

CERM 402

0.1UF

10V

20%

29

2

1

C3114

0.1UF

10V 402

CERM

20%

2

1

C3115

10V CERM

0.1UF

20%

402

2

1

C3116

10V

0.1UF

20%

402

CERM

2

1

C3117

10V

0.1UF

20%

402

CERM

2

1

C3118

10V

0.1UF

20%

402

CERM

2

1

C3119

10V

0.1UF

20%

402

CERM

2

1

C3120

10V

20%

402

CERM

0.1UF

2

1

C3121

10V

0.1UF

20%

402

CERM

2

1

C3122

10V

0.1UF

20%

402

CERM

2

1

C3123

10V

0.1UF

20%

402

CERM

29

11 92

DDR3-SODIMM

F-RT-BGA6

205

199

195

193

189 191

197

201 203

183

179

206

212211

210209

207 208

181

185 187

94

115

127

137 139

143

103 105 107

175 177

173

169 171

155

200 202 204

196 198

192

190

194

186 188

180 182 184

178

176

174

170 172

166 168

164

160 162

154 156 158

145 147

141

133

129 131

125

123

117

121

119

113

109 111

101

79

77

75

73

150 152

144 146 148

142

140

138

134 136

128

132

130

124 126

118 120 122

114 116

108 110 112

104 106

100

98

102

96

92

88 90

86

84

82

80

78

74 76

153

135

149 151

167

165

163

159

157

161

83

81

85 87 89 91 93 95 97 99

J3100

OMIT

11 29 92

29

28 31

29

CRITICAL

DDR3-SODIMM

J3100

F-RT-BGA6

37 39

61 63 65 67 69 71

4

72

70

68

66

64

62

60

58

56

52 54

50

48

46

42 44

40

38

36

32 34

30

28

26

24

22

20

18

16

14

12

10

8

6

2

57 59

55

53

51

47 49

45

41 43

35

31 33

29

27

25

21 23

19

13

11

9

5 7

1 3

17

15

OMIT

11 29 92

29

11 92

29

11 92

29

11 92

29

2

1

C3136

20%

0.1UF

10V

402

CERM

2

1

C3135

402-LF

20%

CERM

6.3V

2.2UF

29

DDR3 SO-DIMM Connector B

SYNC_DATE=06/09/2009

SYNC_MASTER=K17_WFERRY

MEM_B_SA<1>

=MEM_B_DQS_P<4>

MEM_B_DQ<37> =MEM_B_DQ<35>

=MEM_B_DM<5>

PP1V5_S3

MEM_B_ODT<0>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DQ<24>

=MEM_B_DQ<18> =MEM_B_DQ<19>

=MEM_B_DM<3>

=MEM_B_DQ<27>

=MEM_B_DQ<36>

=MEM_B_DQ<9>

MEM_B_ODT<1>

=MEM_B_DQS_P<6>

=MEM_B_DQ<50>

=MEM_B_DQ<57>

=MEM_B_DQ<47>

=MEM_B_DQ<48> =MEM_B_DQ<49>

=MEM_B_DQS_N<6>

=MEM_B_DQ<51>

=MEM_B_DQ<54> =MEM_B_DQ<55>

=MEM_B_DQ<60>

=MEM_B_DQS_N<7>

PP0V75_S0_DDRVTT

MEM_RESET_L

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<21>

=MEM_B_DQ<13>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

=MEM_B_DQ<20>

=MEM_B_DQ<25>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<16>

=MEM_B_DQ<37>

=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<53>

=MEM_B_DQ<61>

=MEM_B_DQ<62>

=MEM_B_DQ<45>

SMBUS_PCH_DATA

=MEM_B_DQ<59>

=MEM_B_DQ<56>

=MEM_B_DQ<33>

=MEM_B_DQS_N<4>

=MEM_B_DQ<32>

MEM_B_A<5>

=MEM_B_DQS_P<7>

MEM_B_A<1>

MEM_B_CLK_N<0>

MEM_B_A<3> MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<0>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_A<10>

SMBUS_PCH_CLK

MEM_EVENT_A_L

=MEM_B_DQ<63>

=MEM_B_DM<6>

=MEM_B_DQ<52>

=MEM_B_DQ<40>

MEM_B_WE_L

MEM_B_CLK_P<0>

=MEM_B_DQ<44>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DM<4>

MEM_B_CS_L<0>

MEM_B_CLK_P<1>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=MEM_B_DQ<26>

=MEM_B_DQ<4>

=MEM_B_DM<1>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

=MEM_B_DQ<5>

=MEM_B_DQ<10>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

MEM_B_DM<0>

=MEM_B_DQ<0> =MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_BA<2>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_A<8>

=MEM_B_DQ<41>

MEM_B_CKE<0>

=MEM_B_DQ<12>

=MEM_B_DM<2>

=MEM_B_DQ<17>

MEM_B_CLK_N<1>

MEM_B_A<9>

MEM_B_A<12>

=MEM_B_DQ<2>

=MEM_B_DQ<11>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DM<7>

=MEM_B_DQ<58>

MEM_B_SA<0>

PP3V3_S0

31 OF 132 30 OF 103

7

28 31 68 73

32

7

28 31 68

32

6 7 8

25 26 27 28

34 37 40 42 47 48 49 52 53

55 59 63 64 69 70

71 72 73 74 81 84 85 86 88

99

101

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Apple A1297 K17 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual